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-rw-r--r--CHANGELOG752
-rw-r--r--Makefile2
-rw-r--r--arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S140
-rw-r--r--arch/powerpc/cpu/mpc5xxx/Makefile5
-rw-r--r--arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c71
-rw-r--r--arch/powerpc/lib/Makefile5
-rw-r--r--common/cmd_setexpr.c2
7 files changed, 905 insertions, 72 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 91664a0..5399007 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,736 @@
+commit 460c2ce362e56890c2a029e2c3b1ff2796c7fc54
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Jun 21 22:29:59 2010 +0200
+
+ MPC5200: workaround data corruption for unaligned local bus accesses
+
+ The MPC5200 has a nasty problem that will cause silent data corruption
+ when performing unaligned 16 or 32 byte accesses when reading from the
+ local bus - typically this affects reading from flash. The problem can
+ be easily shown:
+
+ => md fc0c0000 10
+ fc0c0000: 323e4337 01626f6f 74636d64 3d72756e 2>C7.bootcmd=run
+ fc0c0010: 206e6574 5f6e6673 00626f6f 7464656c net_nfs.bootdel
+ fc0c0020: 61793d35 00626175 64726174 653d3131 ay=5.baudrate=11
+ fc0c0030: 35323030 00707265 626f6f74 3d656368 5200.preboot=ech
+ => md fc0c0001 10
+ fc0c0001: 65636801 00000074 0000003d 00000020 ech....t...=...
+ fc0c0011: 0000005f 00000000 00000074 00000061 ..._.......t...a
+ fc0c0021: 00000000 00000064 00000065 00000035 .......d...e...5
+ fc0c0031: 00000000 00000062 0000003d 0000006f .......b...=...o
+ => md.w fc0c0001 10
+ fc0c0001: 0000 3701 0000 6f74 0000 643d 0000 6e20 ..7...ot..d=..n
+ fc0c0011: 0000 745f 0000 7300 0000 6f74 0000 6c61 ..t_..s...ot..la
+
+ This commit implements a workaround at least for the most blatant
+ problem: using memcpy() from NOR flash. We rename the assembler
+ routine into __memcpy() and provide a wrapper, which will use a
+ byte-wise copy loop for unaligned source or target addresses when
+ reading from NOR flash, and branch to the optimized __memcpy()
+ in all other cases, thus minimizing the performance impact.
+
+ Tested on lite5200b and TQM5200S.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: Detlev Zundel <dzu@denx.de>
+
+commit 47ea6edfb3004fb2d2a979e19c3f6e4e32f45e51
+Author: Minkyu Kang <mk7.kang@samsung.com>
+Date: Fri Jun 18 19:31:10 2010 +0900
+
+ ARM: remove unused VIDEOLFB ATAG
+
+ ATAG_VIDEOLFB is not used anywhere.
+ The belowing warning is occurred due to this ATAG.
+
+ [ 0.000000] Ignoring unrecognised tag 0x54410008
+
+ This patch fixed it.
+
+ Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
+ Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+ Acked-by: Martin Krause <Martin.Krause@tqs.de>
+
+commit ceeba0030844b2e84ce4e47f4be7ad347cd1e827
+Author: Peter Horton <zero@colonel-panic.org>
+Date: Sat Jun 12 10:11:56 2010 +0900
+
+ UBI: initialise update marker
+
+ UBI: initialise update marker
+
+ The in kernel copy of a volume's update marker is not initialised from the
+ volume table. This means that volumes where an update was unfinnished will
+ not be treated as "forbidden to use". This is basically that the update
+ functionality was broken.
+
+ Signed-off-by: Peter Horton <zero@colonel-panic.org>
+ Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
+ Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+ Acked-by: Stefan Roese <sr@denx.de>
+
+commit b8c4eea56b5f41f9bdbb89d3d5c79b7d282d513c
+Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+Date: Wed Apr 14 15:32:06 2010 +0200
+
+ remove myself as a maintainer of several ARM boards
+
+ Since I haven't been actively maintaining these boards for a long while,
+ keeping myself as their maintainer makes no sense.
+
+ Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+
+commit d6b937142008463d628ef26a753f9c20c57f3617
+Author: Ilya Yanok <yanok@emcraft.com>
+Date: Mon Jun 21 18:13:21 2010 +0400
+
+ Makefile: always call date with LC_ALL=C set
+
+ Ensure that date is called only with LC_ALL=C locale set to make dates
+ locale neutral thus preventing lurking of non-ASCII characters into
+ U-Boot binary.
+
+ Signed-off-by: Ilya Yanok <yanok@emcraft.com>
+
+ Changed LANG= into LC_ALL= as suggested by Mike Frysinger <vapier@gentoo.org>
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 23fdf0580660edf38cb7118f05b8865f2f73c674
+Author: Albert Aribaud <[albert.aribaud@free.fr]>
+Date: Tue Jun 22 15:50:28 2010 +0530
+
+ Fix wrong orion5x MPP and GIPO writel arguments
+
+ Orion5x MPP and GPIO setting code had writel arguments
+ the wrong way around. Fixed and tested.
+
+ Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
+
+commit 95bc39e848dd3f741a064c826d1c282c48125d41
+Author: Terry Lv <r65388@freescale.com>
+Date: Thu May 6 18:30:55 2010 +0800
+
+ ARM: fix bug in macro __arch_ioremap.
+
+ Signed-off-by: Terry Lv <r65388@freescale.com>
+
+ Fix commit message and code formatting.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit a71da1b6c96205549ca2e7cf991e2340181bbfcf
+Author: Vitaly Kuzmichev <vkuzmichev@mvista.com>
+Date: Tue Jun 15 22:18:11 2010 +0400
+
+ ARM: Align stack to 8 bytes
+
+ The ARM ABI requires that the stack be aligned to 8 bytes as it is noted
+ in Procedure Call Standard for the ARM Architecture:
+ http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042d/index.html
+
+ Unaligned SP also causes the problem with variable-length arrays
+ allocation when VLA address becomes less than stack pointer during
+ aligning of this address, so the next 'push' in the stack overwrites
+ first 4 bytes of VLA.
+
+ Signed-off-by: Vitaly Kuzmichev <vkuzmichev@mvista.com>
+
+ Tested on tx25(mx25), imx27lite(mx27), qong(mx31) and trab(s3c2400)
+ Tested-by: Wolfgang Denk <wd@denx.de>
+
+commit 6de27bdc788e7c4532ee0721ae291aeb5df475dc
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jun 20 12:32:37 2010 +0200
+
+ net/eth.c: eth_mac_skip() is only needed when CONFIG_NET_MULTI is set
+
+ Move it inside the #ifdef CONFIG_NET_MULTI to avoid
+
+ eth.c:64: warning: 'eth_mac_skip' defined but not used
+
+ messages from a number of old, non-CONFIG_NET_MULTI boards.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit e397e59e861aa818cda12a23206dde06f7e9f660
+Author: Fillod Stephane <stephane.fillod@grassvalley.com>
+Date: Fri Jun 11 19:26:43 2010 +0200
+
+ ip/defrag: fix processing of last short fragment
+
+ TFTP'ing a file of size 1747851 bytes with CONFIG_IP_DEFRAG and
+ CONFIG_TFTP_BLOCKSIZE set to 4096 fails with a timeout, because
+ the last fragment is not taken into account. This patch fixes
+ IP fragments having less than 8 bytes of payload.
+
+ Signed-off-by: Stephane Fillod <stephane.fillod@grassvalley.com>
+ Acked-by: Alessandro Rubini <rubini@gnudd.com>
+ Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 9c00b2f0a3fe0f779761607024f99b7690c9776c
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jun 20 12:30:22 2010 +0200
+
+ net/eth.c: eth_mac_skip() is only needed when CONFIG_NET_MULTI is set
+
+ Move it inside the #ifdef CONFIG_NET_MULTI to avoid
+
+ eth.c:64: warning: 'eth_mac_skip' defined but not used
+
+ messages from anumber of old, non-CONFIG_NET_MULTI boards.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: Ben Warren <biggerbadderben@gmail.com>
+
+commit 9312bba01a41191f20821b66b84b3ff1d2902e8a
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jun 20 02:16:44 2010 +0200
+
+ include/compiler.h: remove redundant declaration of errno
+
+ Commit 37566090 "compiler.h: unify system ifdef cruft here" added both
+ a "#include <errno.h>" and a "extern int errno;" to include/compiler.h
+ which is causing build warnings for some systems, for example for the
+ "netstar" board:
+
+ In file included from /home/wd/git/u-boot/work/lib/crc32.c:15:
+ include/compiler.h:28: warning: function declaration isn't a prototype
+
+ The declaration of "errno" should be redundant, as <errno.h> is
+ supposed to provide a correct declaration, so drop it.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: Mike Frysinger <vapier@gentoo.org>
+
+commit cd040a4953e55efe89dc3af4acf0302d5923026f
+Author: Wolfgang Denk <wd@denx.de>
+Date: Fri Jun 18 15:55:15 2010 +0200
+
+ arch/arm/cpu/arm_cortexa8/omap3/cache.S: make build with older tools
+
+ The push / pop instructions used in this file are available only with
+ more recent tool chains:
+
+ cache.S: Assembler messages:
+ cache.S:133: Error: bad instruction `push {r0,r1,r2,lr}'
+ cache.S:160: Error: bad instruction `pop {r1,r2,r3,pc}'
+ cache.S:164: Error: bad instruction `push {r0,r1,r2,lr}'
+ cache.S:191: Error: bad instruction `pop {r1,r2,r3,pc}'
+
+ Change push/pop into stmfd/ldmfd instructions to support older
+ versions of binutils as well.
+
+ I verified that the modified source code generates exactly the same
+ binary code.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+ Cc: Sandeep Paulraj <s-paulraj@ti.com>
+ Cc: Tom Rix <tom@bumblecow.com>
+
+commit ce9c227cc71afc3b4c78dcc0a565c40d4ad943e4
+Author: Albert Aribaud <[albert.aribaud@free.fr]>
+Date: Thu Jun 17 19:38:21 2010 +0530
+
+ Add support for the LaCie ED Mini V2 board
+
+ This patch adds support for the LaCie ED Mini V2 product
+ which is based on the Marvell Orion5x SoC.
+
+ Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
+
+commit 83142c112d30ee3da23b62387909d33db064bdc4
+Author: Albert Aribaud <[albert.aribaud@free.fr]>
+Date: Thu Jun 17 19:37:01 2010 +0530
+
+ Add Orion5x support to 16550 device driver
+
+ This patch provides access to the 16550-compatible
+ serial device of the Orion5x SoC.
+
+ Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
+
+commit 0c61e6f9257ef416959b740ee3cf191bf682007d
+Author: Albert Aribaud <[albert.aribaud@free.fr]>
+Date: Thu Jun 17 19:36:07 2010 +0530
+
+ Initial support for Marvell Orion5x SoC
+
+ This patch adds support for the Marvell Orion5x SoC.
+ It has no use alone, and must be followed by a patch
+ to add Orion5x support for serial, then support for
+ the ED Mini V2, an Orion5x-based product from LaCie.
+
+ Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
+
+commit 376e7fadbad3285231e390c6534feb5af86d594b
+Author: Minkyu Kang <mk7.kang@samsung.com>
+Date: Tue Jun 8 14:40:47 2010 +0900
+
+ SAMSUNG: goni: add the GPL licence
+
+ Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
+ Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+ Acked-by: Tom <Tom@bumblecow.com>
+
+commit c474a8ebb880e564df0c701c6a8cf73b7779b1d2
+Author: Minkyu Kang <mk7.kang@samsung.com>
+Date: Mon May 31 22:02:42 2010 +0900
+
+ s5pc1xx: Add support for Samsung Goni board
+
+ This patch adds support for the Samsung Goni board (S5PC110 SoC)
+
+ Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
+ Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
+
+commit ffb4b02554d9972d66502efbe97b3933620c8a31
+Author: Minkyu Kang <mk7.kang@samsung.com>
+Date: Fri May 28 12:34:29 2010 +0900
+
+ s5pc1xx: gpio: bug fix at gpio_set_pull function
+
+ When set to PULL_NONE, gpio_set_pull function is returned without write the register.
+ This patch fixed it.
+
+ Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
+
+commit a9046b9e1aeeedc66ddf1d00474ad0ce8c6aa6e4
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jun 13 17:48:15 2010 +0200
+
+ Prepare v2010-rc2
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 3a96ad851f4f9267e1199b700cb838a77334e4b2
+Author: Marek Vasut <marek.vasut@gmail.com>
+Date: Sun Apr 11 08:53:55 2010 +0200
+
+ PXA: Align stack to 8 bytes
+
+ Part of this patch is by: Mikhail Kshevetskiy.
+
+ Stack must be aligned to 8 bytes on PXA (possibly all armv5te) for LDRD/STRD
+ instructions. In case LDRD/STRD is issued on an unaligned address, the behaviour
+ is undefined.
+
+ The issue was observed when working with the NAND code, which was rendered
+ disfunctional. Also, the vsprintf() function had serious problems with printing
+ 64bit wide long longs. After aligning the stack, this wrong behaviour is no
+ longer present.
+
+ Tested on:
+ Marvell Littleton PXA310 board
+ Toradex Colibri PXA320 board
+ Aeronix Zipit Z2 PXA270 handheld
+ Voipac PXA270 board
+
+ Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
+
+commit 89b765c7f6ddfde07ba673dd4adbeb5da391a81b
+Author: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
+Date: Thu Jun 10 15:18:15 2010 +0530
+
+ TI: DaVinci: Add board specific code for da850 EVM
+
+ Provides initial support for TI OMAP-L138/DA850 SoC devices on
+ a Logic PD EVM board.
+
+ Provides:
+ Initial boot and configuration.
+ Support for i2c.
+ UART support (console).
+
+ Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
+ Acked-by: Ben Gardiner <bengardiner@nanometrics.ca>
+ Reviewed-by: Wolfgang Denk <wd@denx.de>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 158557001afe167dcb848bb14ba0f2f20aeb25a1
+Author: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
+Date: Tue Jun 8 11:01:58 2010 +0530
+
+ TI: DaVinci: Prepare for da850 support
+
+ DA850/OMAP-L138 is a new SoC from Texas Instruments
+ (http://focus.ti.com/docs/prod/folders/print/omap-l138.html).
+ This SoC is similar to DA830/OMAP-L137 in many aspects. Hence
+ rename the da830 specific files and folders to da8xx to
+ accommodate DA850/OMAP-L138.
+
+ Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
+ Acked-by: Ben Gardiner <bengardiner@nanometrics.ca>
+ Reviewed-by: Wolfgang Denk <wd@denx.de>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 9d79956029ec379e7137948ba3a7debbea61325f
+Author: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
+Date: Mon Jun 7 12:39:59 2010 +0530
+
+ da830: Move common code out of da830evm.c file
+
+ TI's DA850/OMAP-L138 platform is similar to DA830/OMAP-L137
+ in many aspects. So instead of repeating the same code in
+ multiple files, move the common code to a different file
+ and call those functions from the respective da830/da850
+ files.
+
+ Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
+ Acked-by: Nick Thompson <nick.thompson@ge.com>
+ Acked-by: Ben Gardiner <bengardiner@nanometrics.ca>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 5246d01edd8935e04cdf79a5b9a03874509a31b1
+Author: Grazvydas Ignotas <notasas@gmail.com>
+Date: Tue Jun 8 17:19:22 2010 -0400
+
+ OMAP3: pandora: enable battery backup capacitor
+
+ Pandora has a capacitor connected as backup battery, which allows
+ retaining RTC for some time while main battery is removed. Enable backup
+ battery charge function to charge that capacitor.
+
+ Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 9268236529161312c877e638a14c011fd3c883e1
+Author: Delio Brignoli <dbrignoli@audioscience.com>
+Date: Mon Jun 7 17:16:13 2010 -0400
+
+ DaVinci: Improve DaVinci SPI speed.
+
+ I have updated this patch based on the comments [1] by Wolfgang Denk and
+ removed unused variables.
+ [1][http://lists.denx.de/pipermail/u-boot/2010-May/071728.html]
+
+ Reduce the number of reads per byte transferred on the BUF register from 2 to 1 and
+ take advantage of the TX buffer in the SPI module. On LogicPD OMAP-L138 EVM,
+ SPI read throughput goes up from ~0.8Mbyte/s to ~1.3Mbyte/s. Tested with a 2Mbyte image file.
+ Remove unused variables in the spi_xfer() function.
+
+ Signed-off-by: Delio Brignoli <dbrignoli@audioscience.com>
+ Tested-by: Ben Gardiner <bengardiner@nanometrics.ca>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 1a5038ca6831e31875cf67c46226f04743574032
+Author: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Mon Jun 7 15:20:53 2010 -0400
+
+ AM35x: Add support for EMIF4
+
+ This patch adds support for the EMIF4 interface
+ available in the AM35x processors.
+
+ Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+ Signed-off-by: Sanjeev Premi <premi@ti.com>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit ed01e45cfa20d60ee83a4ee0128d843730055294
+Author: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Mon Jun 7 15:20:43 2010 -0400
+
+ AM35x: Add support for AM3517EVM
+
+ This patch adds basic support for the AM3517EVM.
+ It includes:
+ - Board files (.c and .h)
+ - Default configuration file
+ - Updates for Makefile
+
+ Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+ Signed-off-by: Sanjeev Premi <premi@ti.com>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit cae377b59a179e34d27cd6b79dee24d967de839c
+Author: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Mon Jun 7 15:20:34 2010 -0400
+
+ omap3: Consolidate SDRC related operations
+
+ Consolidated SDRC related functions into one file - sdrc.c
+
+ And also replaced sdrc_init with generic memory init
+ function (mem_init), this generalization of omap memory setup
+ is necessary to support the new emif4 interface introduced in AM3517.
+
+ Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit d11212e3772c8fe43a1f487bbf58f3341118a241
+Author: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Mon Jun 7 15:20:29 2010 -0400
+
+ omap3: Calculate CS1 size only when SDRC is
+
+ initialized for CS1
+
+ From: Vaibhav Hiremath <hvaibhav@ti.com>
+
+ The patch makes sure that size for SDRC CS1 gets calculated
+ only when the CS1 SDRC is initialized.
+
+ Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 675e0eaf0f0429aac3c6fb41634fbcea2350fe49
+Author: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Mon Jun 7 15:20:19 2010 -0400
+
+ OMAP3EVM: Added NAND support
+
+ The EVMS have been shipping with NAND (instead of OneNAND) as default.
+ So, this patch sets NAND as default.
+
+ To choose OneNAND, define CMD_ONENAND instead of CMD_NAND in the
+ config file omap3_evm.h.
+
+ Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 5cc48f7e55df0d74a12d338de2117f05951fc536
+Author: Cyril Chemparathy <cyril@ti.com>
+Date: Mon Jun 7 14:13:36 2010 -0400
+
+ TI: TNETV107X EVM initial support
+
+ TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a
+ bunch on on-chip integrated peripherals. This patch adds support for the
+ TNETV107X EVM board.
+
+ Signed-off-by: Cyril Chemparathy <cyril@ti.com>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 3712367c4830e87b4e7af5b480e82d316bab1251
+Author: Cyril Chemparathy <cyril@ti.com>
+Date: Mon Jun 7 14:13:32 2010 -0400
+
+ ARM1176: TI: TNETV107X soc initial support
+
+ TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a
+ bunch on on-chip integrated peripherals. This is an initial commit with
+ basic functionality, more commits with drivers, etc. to follow.
+
+ Signed-off-by: Cyril Chemparathy <cyril@ti.com>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 678e008c3a3a27fe2d30cf423679d2d11d0fa5c2
+Author: Cyril Chemparathy <cyril@ti.com>
+Date: Mon Jun 7 14:13:27 2010 -0400
+
+ ARM1176: Coexist with other ARM1176 platforms
+
+ The current ARM1176 CPU specific code is too specific to the SMDK6400
+ architecture. The following changes were necessary prerequisites for the
+ addition of other SoCs based on ARM1176.
+
+ Existing board's (SMDK6400) configuration has been modified to keep behavior
+ unchanged despite these changes.
+
+ 1. Peripheral port remap configurability
+ The earlier code had hardcoded remap values specific to s3c64xx in start.S.
+ This change makes the peripheral port remap addresses and sizes configurable.
+
+ 2. U-Boot code relocation support
+ Most architectures allow u-boot code to run initially at a different
+ address (possibly in NOR) and then get relocated to its final resting place
+ in RAM. Added support for this capability in ARM1176 architecture.
+
+ 3. Disable TCM if necessary
+ If a ROM based bootloader happened to have initialized TCM, we disable it here
+ to keep things sane.
+
+ 4. Remove unnecessary SoC specific includes
+ ARM1176 code does not really need this SoC specific include. The presence
+ of this include prevents builds on other ARM1176 archs.
+
+ 5. Modified virt-to-phys conversion during MMU disable
+ The original MMU disable code masks out too many bits from the load address
+ when it tries to figure out the physical address of the jump target label.
+ Consequently, it ends up branching to the wrong address after disabling the
+ MMU.
+
+ Signed-off-by: Cyril Chemparathy <cyril@ti.com>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 23911740486c59851df57521c49bfd81ce1865ec
+Author: Delio Brignoli <dbrignoli@audioscience.com>
+Date: Mon Jun 7 17:16:13 2010 -0400
+
+ DaVinci: Improve DaVinci SPI speed.
+
+ I have updated this patch based on the comments [1] by Wolfgang Denk and
+ removed unused variables.
+ [1][http://lists.denx.de/pipermail/u-boot/2010-May/071728.html]
+
+ Reduce the number of reads per byte transferred on the BUF register from 2 to 1 and
+ take advantage of the TX buffer in the SPI module. On LogicPD OMAP-L138 EVM,
+ SPI read throughput goes up from ~0.8Mbyte/s to ~1.3Mbyte/s. Tested with a 2Mbyte image file.
+ Remove unused variables in the spi_xfer() function.
+
+ Signed-off-by: Delio Brignoli <dbrignoli@audioscience.com>
+ Tested-by: Ben Gardiner <bengardiner@nanometrics.ca>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 05ee415e316e3b1617aba06a747649f4d4053d41
+Author: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Mon Jun 7 15:20:53 2010 -0400
+
+ AM35x: Add support for EMIF4
+
+ This patch adds support for the EMIF4 interface
+ available in the AM35x processors.
+
+ Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+ Signed-off-by: Sanjeev Premi <premi@ti.com>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 3d9f0ffddaf1ece95a826785b971860ebdadf424
+Author: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Mon Jun 7 15:20:43 2010 -0400
+
+ AM35x: Add support for AM3517EVM
+
+ This patch adds basic support for the AM3517EVM.
+ It includes:
+ - Board files (.c and .h)
+ - Default configuration file
+ - Updates for Makefile
+
+ Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+ Signed-off-by: Sanjeev Premi <premi@ti.com>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 8aa5c7cdc4e534df9129485ba317a2871c4f9880
+Author: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Mon Jun 7 15:20:34 2010 -0400
+
+ omap3: Consolidate SDRC related operations
+
+ Consolidated SDRC related functions into one file - sdrc.c
+
+ And also replaced sdrc_init with generic memory init
+ function (mem_init), this generalization of omap memory setup
+ is necessary to support the new emif4 interface introduced in AM3517.
+
+ Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 16807ee411d83762804d075a3fe11f0a2b5eaf39
+Author: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Mon Jun 7 15:20:29 2010 -0400
+
+ omap3: Calculate CS1 size only when SDRC is
+
+ initialized for CS1
+
+ From: Vaibhav Hiremath <hvaibhav@ti.com>
+
+ The patch makes sure that size for SDRC CS1 gets calculated
+ only when the CS1 SDRC is initialized.
+
+ Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 7ca4766bd7f74e5f7371fb331b573ec384230c1d
+Author: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Mon Jun 7 15:20:19 2010 -0400
+
+ OMAP3EVM: Added NAND support
+
+ The EVMS have been shipping with NAND (instead of OneNAND) as default.
+ So, this patch sets NAND as default.
+
+ To choose OneNAND, define CMD_ONENAND instead of CMD_NAND in the
+ config file omap3_evm.h.
+
+ Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit 04cbc19fedb55265d08cddea294c3b6d9f8b2d18
+Author: Cyril Chemparathy <cyril@ti.com>
+Date: Mon Jun 7 14:13:36 2010 -0400
+
+ TI: TNETV107X EVM initial support
+
+ TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a
+ bunch on on-chip integrated peripherals. This patch adds support for the
+ TNETV107X EVM board.
+
+ Signed-off-by: Cyril Chemparathy <cyril@ti.com>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit da1ec42aafcc821ce6b5d316a2d4105292960d6b
+Author: Cyril Chemparathy <cyril@ti.com>
+Date: Mon Jun 7 14:13:32 2010 -0400
+
+ ARM1176: TI: TNETV107X soc initial support
+
+ TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a
+ bunch on on-chip integrated peripherals. This is an initial commit with
+ basic functionality, more commits with drivers, etc. to follow.
+
+ Signed-off-by: Cyril Chemparathy <cyril@ti.com>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit b87996d24a41cfc15fea125e5c805163af4acba1
+Author: Cyril Chemparathy <cyril@ti.com>
+Date: Mon Jun 7 14:13:27 2010 -0400
+
+ ARM1176: Coexist with other ARM1176 platforms
+
+ The current ARM1176 CPU specific code is too specific to the SMDK6400
+ architecture. The following changes were necessary prerequisites for the
+ addition of other SoCs based on ARM1176.
+
+ Existing board's (SMDK6400) configuration has been modified to keep behavior
+ unchanged despite these changes.
+
+ 1. Peripheral port remap configurability
+ The earlier code had hardcoded remap values specific to s3c64xx in start.S.
+ This change makes the peripheral port remap addresses and sizes configurable.
+
+ 2. U-Boot code relocation support
+ Most architectures allow u-boot code to run initially at a different
+ address (possibly in NOR) and then get relocated to its final resting place
+ in RAM. Added support for this capability in ARM1176 architecture.
+
+ 3. Disable TCM if necessary
+ If a ROM based bootloader happened to have initialized TCM, we disable it here
+ to keep things sane.
+
+ 4. Remove unnecessary SoC specific includes
+ ARM1176 code does not really need this SoC specific include. The presence
+ of this include prevents builds on other ARM1176 archs.
+
+ 5. Modified virt-to-phys conversion during MMU disable
+ The original MMU disable code masks out too many bits from the load address
+ when it tries to figure out the physical address of the jump target label.
+ Consequently, it ends up branching to the wrong address after disabling the
+ MMU.
+
+ Signed-off-by: Cyril Chemparathy <cyril@ti.com>
+ Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+
+commit b5d289fc29842095d5cd0f82cceab1b0b2e824ba
+Author: Asen Dimov <dimov@ronetix.at>
+Date: Tue Apr 20 22:49:04 2010 +0300
+
+ add new board pm9g45
+
+ Add the new board PM9G45 from Ronetix GmbH.
+ * AT91SAM9G45 MCU at 400Mhz.
+ * 128MB DDR2 SDRAM
+ * 256MB NAND
+ * 10/100 MBits Ethernet DP83848
+ * Serial number chip DS2401
+
+ The board is made as SODIMM200 module.
+ For more info www.ronatix.at or info@ronetix.at.
+
+ Signed-off-by: Asen Dimov <dimov@ronetix.at>
+
commit f986325dd569faeaec4186f678d113505c5c4828
Author: Ron Madrid <ron_madrid@sbcglobal.net>
Date: Tue Jun 1 17:00:49 2010 -0700
@@ -13,6 +746,25 @@ Date: Tue Jun 1 17:00:49 2010 -0700
Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+commit 409a07c9d72b0d833c1cce264bdb4bb2628fe28e
+Author: George G. Davis <gdavis@mvista.com>
+Date: Tue May 11 10:15:36 2010 -0400
+
+ ARM1136: Fix cache_flush() error and correct cpu_init_crit() comments
+
+ The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0"
+ instruction which means "Invalidate Both Caches" when in fact the intent
+ is to clean and invalidate all caches. So add an "mcr p15, 0, %0, c7,
+ c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate
+ Both Caches" instruction to insure that memory is consistent with any
+ dirty cache lines.
+
+ Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so
+ that they correctly describe the actual ARM1136 CP15 C7 Cache Operations
+ used.
+
+ Signed-off-by: George G. Davis <gdavis@mvista.com>
+
commit 3057c6be5efda781a72ca04432e0a4ed6e670030
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Fri Apr 23 12:20:11 2010 -0500
diff --git a/Makefile b/Makefile
index 9a436fe..87d5214 100644
--- a/Makefile
+++ b/Makefile
@@ -24,7 +24,7 @@
VERSION = 2010
PATCHLEVEL = 06
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
diff --git a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S b/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S
index b0e15f6..0523bd4 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S
+++ b/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S
@@ -87,30 +87,30 @@
lowlevel_init:
/* Use 'r4 as the base for internal register accesses */
- ldr r4, =ORION5X_REGS_PHY_BASE
+ ldr r4, =ORION5X_REGS_PHY_BASE
/* move internal registers from the default 0xD0000000
* to their intended location, defined by SoC */
ldr r3, =0xD0000000
add r3, r3, #0x20000
- str r4, [r3, #0x80]
+ str r4, [r3, #0x80]
/* Use R3 as the base for DRAM registers */
- add r3, r4, #0x01000
+ add r3, r4, #0x01000
/*DDR SDRAM Initialization Control */
ldr r6, =0x00000001
str r6, [r3, #0x480]
/* Use R3 as the base for PCI registers */
- add r3, r4, #0x31000
+ add r3, r4, #0x31000
/* Disable arbiter */
ldr r6, =0x00000030
str r6, [r3, #0xd00]
/* Use R3 as the base for DRAM registers */
- add r3, r4, #0x01000
+ add r3, r4, #0x01000
/* set all dram windows to 0 */
mov r6, #0
@@ -127,63 +127,63 @@ lowlevel_init:
ldr r6, =SDRAM_CONTROL
str r6, [r3, #0x404]
- /* 3) Write SDRAM address control register */
+ /* 3) Write SDRAM address control register */
ldr r6, =SDRAM_ADDR_CTRL
str r6, [r3, #0x410]
- /* 4) Write SDRAM bank 0 size register */
+ /* 4) Write SDRAM bank 0 size register */
ldr r6, =SDRAM_BANK0_SIZE
str r6, [r3, #0x504]
/* keep other banks disabled */
- /* 5) Write SDRAM open pages control register */
+ /* 5) Write SDRAM open pages control register */
ldr r6, =SDRAM_OPEN_PAGE_EN
str r6, [r3, #0x414]
- /* 6) Write SDRAM timing Low register */
+ /* 6) Write SDRAM timing Low register */
ldr r6, =SDRAM_TIME_CTRL_LOW
str r6, [r3, #0x408]
- /* 7) Write SDRAM timing High register */
+ /* 7) Write SDRAM timing High register */
ldr r6, =SDRAM_TIME_CTRL_HI
str r6, [r3, #0x40C]
- /* 8) Write SDRAM mode register */
- /* The CPU must not attempt to change the SDRAM Mode register setting */
- /* prior to DRAM controller completion of the DRAM initialization */
- /* sequence. To guarantee this restriction, it is recommended that */
- /* the CPU sets the SDRAM Operation register to NOP command, performs */
- /* read polling until the register is back in Normal operation value, */
- /* and then sets SDRAM Mode register to its new value. */
+ /* 8) Write SDRAM mode register */
+ /* The CPU must not attempt to change the SDRAM Mode register setting */
+ /* prior to DRAM controller completion of the DRAM initialization */
+ /* sequence. To guarantee this restriction, it is recommended that */
+ /* the CPU sets the SDRAM Operation register to NOP command, performs */
+ /* read polling until the register is back in Normal operation value, */
+ /* and then sets SDRAM Mode register to its new value. */
/* 8.1 write 'nop' to SDRAM operation */
- ldr r6, =SDRAM_OP_NOP
+ ldr r6, =SDRAM_OP_NOP
str r6, [r3, #0x418]
- /* 8.2 poll SDRAM operation until back in 'normal' mode. */
+ /* 8.2 poll SDRAM operation until back in 'normal' mode. */
1:
ldr r6, [r3, #0x418]
cmp r6, #0
bne 1b
- /* 8.3 Now its safe to write new value to SDRAM Mode register */
+ /* 8.3 Now its safe to write new value to SDRAM Mode register */
ldr r6, =SDRAM_MODE
str r6, [r3, #0x41C]
- /* 8.4 Set new mode */
- ldr r6, =SDRAM_OP_SETMODE
+ /* 8.4 Set new mode */
+ ldr r6, =SDRAM_OP_SETMODE
str r6, [r3, #0x418]
- /* 8.5 poll SDRAM operation until back in 'normal' mode. */
+ /* 8.5 poll SDRAM operation until back in 'normal' mode. */
2:
ldr r6, [r3, #0x418]
cmp r6, #0
bne 2b
- /* DDR SDRAM Address/Control Pads Calibration */
+ /* DDR SDRAM Address/Control Pads Calibration */
ldr r6, [r3, #0x4C0]
- /* Set Bit [31] to make the register writable */
+ /* Set Bit [31] to make the register writable */
orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
str r6, [r3, #0x4C0]
@@ -192,20 +192,20 @@ lowlevel_init:
bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
- /* Get the final N locked value of driving strength [22:17] */
- mov r1, r6
- mov r1, r1, LSL #9
- mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
- orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
+ /* Get the final N locked value of driving strength [22:17] */
+ mov r1, r6
+ mov r1, r1, LSL #9
+ mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
+ orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
- /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
+ /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
orr r6, r6, r1
str r6, [r3, #0x4C0]
- /* DDR SDRAM Data Pads Calibration */
+ /* DDR SDRAM Data Pads Calibration */
ldr r6, [r3, #0x4C4]
- /* Set Bit [31] to make the register writable */
+ /* Set Bit [31] to make the register writable */
orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
str r6, [r3, #0x4C4]
@@ -214,21 +214,21 @@ lowlevel_init:
bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
- /* Get the final N locked value of driving strength [22:17] */
- mov r1, r6
- mov r1, r1, LSL #9
- mov r1, r1, LSR #26
- orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
+ /* Get the final N locked value of driving strength [22:17] */
+ mov r1, r6
+ mov r1, r1, LSL #9
+ mov r1, r1, LSR #26
+ orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
- /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
+ /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
orr r6, r6, r1
str r6, [r3, #0x4C4]
- /* Implement Guideline (GL# MEM-3) Drive Strength Value */
- /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
+ /* Implement Guideline (GL# MEM-3) Drive Strength Value */
+ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
- ldr r1, =DDR1_PAD_STRENGTH_DEFAULT
+ ldr r1, =DDR1_PAD_STRENGTH_DEFAULT
/* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
ldr r6, [r3, #0x4C0]
@@ -252,42 +252,42 @@ lowlevel_init:
orr r6, r6, r1
str r6, [r3, #0x4C4]
- /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
- /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
+ /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
+ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
- /* Get the "sample on reset" register for the DDR frequancy */
+ /* Get the "sample on reset" register for the DDR frequancy */
ldr r3, =0x10000
- ldr r6, [r3, #0x010]
- ldr r1, =MSAR_ARMDDRCLCK_MASK
- and r1, r6, r1
-
- ldr r6, =FTDLL_DDR1_166MHZ
- cmp r1, #MSAR_ARMDDRCLCK_333_167
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_500_167
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_667_167
- beq 3f
-
- ldr r6, =FTDLL_DDR1_200MHZ
- cmp r1, #MSAR_ARMDDRCLCK_400_200_1
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_400_200
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_600_200
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_800_200
- beq 3f
-
- ldr r6, =0
+ ldr r6, [r3, #0x010]
+ ldr r1, =MSAR_ARMDDRCLCK_MASK
+ and r1, r6, r1
+
+ ldr r6, =FTDLL_DDR1_166MHZ
+ cmp r1, #MSAR_ARMDDRCLCK_333_167
+ beq 3f
+ cmp r1, #MSAR_ARMDDRCLCK_500_167
+ beq 3f
+ cmp r1, #MSAR_ARMDDRCLCK_667_167
+ beq 3f
+
+ ldr r6, =FTDLL_DDR1_200MHZ
+ cmp r1, #MSAR_ARMDDRCLCK_400_200_1
+ beq 3f
+ cmp r1, #MSAR_ARMDDRCLCK_400_200
+ beq 3f
+ cmp r1, #MSAR_ARMDDRCLCK_600_200
+ beq 3f
+ cmp r1, #MSAR_ARMDDRCLCK_800_200
+ beq 3f
+
+ ldr r6, =0
3:
/* Use R3 as the base for DRAM registers */
- add r3, r4, #0x01000
+ add r3, r4, #0x01000
ldr r2, [r3, #0x484]
orr r2, r2, r6
str r2, [r3, #0x484]
/* Return to U-boot via saved link register */
- mov pc, lr
+ mov pc, lr
diff --git a/arch/powerpc/cpu/mpc5xxx/Makefile b/arch/powerpc/cpu/mpc5xxx/Makefile
index 0ee0611..4ab2b7b 100644
--- a/arch/powerpc/cpu/mpc5xxx/Makefile
+++ b/arch/powerpc/cpu/mpc5xxx/Makefile
@@ -30,6 +30,11 @@ SOBJS = io.o firmware_sc_task_bestcomm.impl.o
COBJS = i2c.o traps.o cpu.o cpu_init.o ide.o interrupts.o \
loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o
+# Workaround for local bus unaligned access problem on MPC5200
+#ifdef CONFIG_MPC5200
+COBJS += memcpy_mpc5200.o
+#endif
+
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
START := $(addprefix $(obj),$(START))
diff --git a/arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c b/arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c
new file mode 100644
index 0000000..0950354
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This is a workaround for issues on the MPC5200, where unaligned
+ * 32-bit-accesses to the local bus will deliver corrupted data. This
+ * happens for example when trying to use memcpy() from an odd NOR
+ * flash address; the behaviour can be also seen when using "md" on an
+ * odd NOR flash address (but there it is not a bug in U-Boot, which
+ * only shows the behaviour of this processor).
+ *
+ * For memcpy(), we test if either the source or the target address
+ * are not 32 bit aligned, and - if so - if the source address is in
+ * NOR flash: in this case we perform a byte-wise (slow) then; for
+ * aligned operations of non-flash areas we use the optimized (fast)
+ * real __memcpy(). This way we minimize the performance impact of
+ * this workaround.
+ *
+ */
+
+#include <common.h>
+#include <flash.h>
+#include <linux/types.h>
+
+void *memcpy(void *trg, const void *src, size_t len)
+{
+ extern void* __memcpy(void *, const void *, size_t);
+ char *s = (char *)src;
+ char *t = (char *)trg;
+ void *dest = (void *)src;
+
+ /*
+ * Check is source address is in flash:
+ * If not, we use the fast assembler code
+ */
+ if (((((unsigned long)s & 3) == 0) /* source aligned */
+ && /* AND */
+ (((unsigned long)t & 3) == 0)) /* target aligned, */
+ || /* or */
+ (addr2info((ulong)s) == NULL)) { /* source not in flash */
+ return __memcpy(trg, src, len);
+ }
+
+ /*
+ * Copying from flash, perform byte by byte copy.
+ */
+ while (len-- > 0)
+ *t++ = *s++;
+
+ return dest;
+}
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 5f85502..bf23790 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -43,6 +43,11 @@ COBJS-y += time.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+# Workaround for local bus unaligned access problem on MPC5200
+ifdef CONFIG_MPC5200
+$(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy
+endif
+
$(LIB): $(obj).depend $(OBJS)
@if ! $(CROSS_COMPILE)readelf -S $(OBJS) | grep -q '\.fixup.*PROGBITS';\
then \
diff --git a/common/cmd_setexpr.c b/common/cmd_setexpr.c
index 2d37197..da9e844 100644
--- a/common/cmd_setexpr.c
+++ b/common/cmd_setexpr.c
@@ -32,7 +32,7 @@ static ulong get_arg(char *s, int w)
{
ulong *p;
- /*
+ /*
* if the parameter starts with a '*' then assume
* it is a pointer to the value we want
*/
generated by cgit v1.1 at 2024-12-28 07:47:29 +0000