diff options
57 files changed, 980 insertions, 457 deletions
@@ -408,6 +408,7 @@ ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin +ALL-$(CONFIG_SPL) += $(obj)$(subst ",,$(CONFIG_SPL_TARGET)) ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin # enable combined SPL/u-boot/dtb rules for tegra @@ -475,14 +476,15 @@ $(obj)u-boot.sha1: $(obj)u-boot.bin $(obj)u-boot.dis: $(obj)u-boot $(OBJDUMP) -d $< > $@ -$(obj)u-boot.ubl: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin +$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin - cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-ubl.bin - $(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \ - -e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-ubl.bin $(obj)u-boot.ubl - rm $(obj)u-boot-ubl.bin + cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@ rm $(obj)spl/u-boot-spl-pad.bin +$(obj)u-boot.ubl: $(obj)u-boot-with-spl.bin + $(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \ + -e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl + $(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img $(obj)tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \ -T aisimage \ @@ -642,6 +644,16 @@ checkthumb: echo '*** Your board is configured for THUMB mode.'; \ false; \ fi + +# GCC 3.x is reported to have problems generating the type of relocation +# that U-Boot wants. +# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html +checkgcc4: + @if test $(call cc-version) -lt 0400; then \ + echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \ + false; \ + fi + # # Auto-generate the autoconf.mk file (which is included by all makefiles) # @@ -2664,6 +2664,10 @@ FIT uImage format: CONFIG_SPL_TEXT_BASE TEXT_BASE for linking the SPL binary. + CONFIG_SPL_RELOC_TEXT_BASE + Address to relocate to. If unspecified, this is equal to + CONFIG_SPL_TEXT_BASE (i.e. no relocation is done). + CONFIG_SPL_BSS_START_ADDR Link address for the BSS within the SPL binary. @@ -2673,6 +2677,11 @@ FIT uImage format: CONFIG_SPL_STACK Adress of the start of the stack SPL will use + CONFIG_SPL_RELOC_STACK + Adress of the start of the stack SPL will use after + relocation. If unspecified, this is equal to + CONFIG_SPL_STACK. + CONFIG_SYS_SPL_MALLOC_START Starting address of the malloc pool used in SPL. @@ -2688,6 +2697,9 @@ FIT uImage format: For ARM, enable an optional function to print more information about the running system. + CONFIG_SPL_INIT_MINIMAL + Arch init code should be built for a very small image + CONFIG_SPL_LIBCOMMON_SUPPORT Support for common/libcommon.o in SPL binary @@ -2715,8 +2727,19 @@ FIT uImage format: CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME Filename to read to load U-Boot when reading from FAT + CONFIG_SPL_NAND_BASE + Include nand_base.c in the SPL. Requires + CONFIG_SPL_NAND_DRIVERS. + + CONFIG_SPL_NAND_DRIVERS + SPL uses normal NAND drivers, not minimal drivers. + + CONFIG_SPL_NAND_ECC + Include standard software ECC in the SPL + CONFIG_SPL_NAND_SIMPLE - Support for drivers/mtd/nand/libnand.o in SPL binary + Support for NAND boot using simple NAND drivers that + expose the cmd_ctrl() interface. CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT, CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE, @@ -2724,15 +2747,19 @@ FIT uImage format: CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE, CONFIG_SYS_NAND_ECCBYTES Defines the size and behavior of the NAND that SPL uses - to read U-Boot with CONFIG_SPL_NAND_SIMPLE + to read U-Boot CONFIG_SYS_NAND_U_BOOT_OFFS - Location in NAND for CONFIG_SPL_NAND_SIMPLE to read U-Boot - from. + Location in NAND to read U-Boot from + + CONFIG_SYS_NAND_U_BOOT_DST + Location in memory to load U-Boot to + + CONFIG_SYS_NAND_U_BOOT_SIZE + Size of image to load CONFIG_SYS_NAND_U_BOOT_START - Location in memory for CONFIG_SPL_NAND_SIMPLE to load U-Boot - to. + Entry point in loaded image to jump to CONFIG_SYS_NAND_HW_ECC_OOBFIRST Define this if you need to first read the OOB and then the @@ -2757,6 +2784,11 @@ FIT uImage format: CONFIG_SPL_LIBGENERIC_SUPPORT Support for lib/libgeneric.o in SPL binary + CONFIG_SPL_TARGET + Final target image containing SPL and payload. Some SPLs + use an arch-specific makefile fragment instead, for + example if more than one image needs to be produced. + Modem Support: -------------- @@ -3859,6 +3891,7 @@ saveenv - save environment variables to persistent storage protect - enable or disable FLASH write protection erase - erase FLASH memory flinfo - print FLASH memory information +nand - NAND memory operations (see doc/README.nand) bdinfo - print Board Info structure iminfo - print header information for application image coninfo - print console devices and informations diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index a307154..b706281 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -42,3 +42,8 @@ endif ifeq ($(CROSS_COMPILE),powerpc-openbsd-) PLATFORM_CPPFLAGS+= -D__PPC__ endif + +# Only test once +ifneq ($(CONFIG_SPL_BUILD),y) +ALL-y += checkgcc4 +endif diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 78c412d..4c2b104 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -28,7 +28,22 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).o -START = start.o resetvec.o +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +START = start.o resetvec.o + +ifdef MINIMAL + +COBJS-y += cpu_init_early.o tlb.o spl_minimal.o + +else + SOBJS-$(CONFIG_MP) += release.o SOBJS = $(SOBJS-y) @@ -121,17 +136,20 @@ COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o -COBJS = $(COBJS-y) -COBJS += cpu.o -COBJS += cpu_init.o -COBJS += cpu_init_early.o -COBJS += interrupts.o -COBJS += speed.o -COBJS += tlb.o -COBJS += traps.o +COBJS-y += cpu.o +COBJS-y += cpu_init.o +COBJS-y += cpu_init_early.o +COBJS-y += interrupts.o +COBJS-y += speed.o +COBJS-y += tlb.o +COBJS-y += traps.o # Stub implementations of cache management functions for USB -COBJS += cache.o +COBJS-y += cache.o + +endif # not minimal + +COBJS = $(COBJS-y) SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index db232e6..78486aa 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -332,7 +332,8 @@ void mpc85xx_reginfo(void) /* Common ddr init for non-corenet fsl 85xx platforms */ #ifndef CONFIG_FSL_CORENET -#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR) +#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \ + !defined(CONFIG_SYS_INIT_L2_ADDR) phys_size_t initdram(int board_type) { #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index f01804b..705c16c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -470,7 +470,7 @@ int cpu_init_r(void) && l2srbar >= CONFIG_SYS_FLASH_BASE) { l2srbar = CONFIG_SYS_INIT_L2_ADDR; l2cache->l2srbar0 = l2srbar; - printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); + printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); } #endif /* CONFIG_SYS_INIT_L2_ADDR */ puts("\n"); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index bf7a6f6..c6b9cd0 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -21,12 +21,16 @@ */ #include <common.h> +#include <asm/processor.h> +#include <asm/global_data.h> #include <asm/fsl_ifc.h> #include <asm/io.h> +DECLARE_GLOBAL_DATA_PTR; + void cpu_init_f(void) { -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) +#ifdef CONFIG_SYS_INIT_L2_ADDR ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); @@ -40,3 +44,16 @@ void cpu_init_f(void) (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); #endif } + +#ifndef CONFIG_SYS_FSL_TBCLK_DIV +#define CONFIG_SYS_FSL_TBCLK_DIV 8 +#endif + +void udelay(unsigned long usec) +{ + u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000); + u32 ticks = ticks_per_usec * usec; + u32 s = mfspr(SPRN_TBRL); + + while ((mfspr(SPRN_TBRL) - s) < ticks); +} diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index ac17f9d..bb0dc1a 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -44,6 +44,15 @@ #undef MSR_KERNEL #define MSR_KERNEL ( MSR_ME ) /* Machine Check */ +#if defined(CONFIG_NAND_SPL) || \ + (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) +#define MINIMAL_SPL +#endif + +#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) +#define NOR_BOOT +#endif + /* * Set up GOT: Global Offset Table * @@ -53,7 +62,7 @@ GOT_ENTRY(_GOT2_TABLE_) GOT_ENTRY(_FIXUP_TABLE_) -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL GOT_ENTRY(_start) GOT_ENTRY(_start_of_vectors) GOT_ENTRY(_end_of_vectors) @@ -282,51 +291,8 @@ l2_disabled: isync .endm -#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL) -/* - * TLB entry for debuggging in AS1 - * Create temporary TLB entry in AS0 to handle debug exception - * As on debug exception MSR is cleared i.e. Address space is changed - * to 0. A TLB entry (in AS0) is required to handle debug exception generated - * in AS1. - */ - -#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) -/* - * TLB entry is created for IVPR + IVOR15 to map on valid OP code address - * bacause flash's virtual address maps to 0xff800000 - 0xffffffff. - * and this window is outside of 4K boot window. - */ - create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ - 0, BOOKE_PAGESZ_4M, \ - CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \ - 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ - 0, r6 - -#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) - create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ - 0, BOOKE_PAGESZ_1M, \ - CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \ - CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \ - 0, r6 -#else -/* - * TLB entry is created for IVPR + IVOR15 to map on valid OP code address - * because "nexti" will resize TLB to 4K - */ - create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ - 0, BOOKE_PAGESZ_256K, \ - CONFIG_SYS_MONITOR_BASE, MAS2_I, \ - CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \ - 0, r6 -#endif -#endif - -/* - * Ne need to setup interrupt vector for NAND SPL - * because NAND SPL never compiles it. - */ -#if !defined(CONFIG_NAND_SPL) +/* Interrupt vectors do not fit in minimal SPL. */ +#if !defined(MINIMAL_SPL) /* Setup interrupt vectors */ lis r1,CONFIG_SYS_MONITOR_BASE@h mtspr IVPR,r1 @@ -534,10 +500,6 @@ nexti: mflr r1 /* R1 = our PC */ li r3, 0 mtspr MAS1, r3 1: cmpw r3, r14 -#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL) - cmpwi cr1, r3, CONFIG_SYS_PPC_E500_DEBUG_TLB - cror cr0*4+eq, cr0*4+eq, cr1*4+eq -#endif rlwinm r5, r3, 16, MAS0_ESEL_MSK addi r3, r3, 1 beq 2f /* skip the entry we're executing from */ @@ -553,6 +515,46 @@ nexti: mflr r1 /* R1 = our PC */ 2: cmpw r3, r4 blt 1b +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) +/* + * TLB entry for debuggging in AS1 + * Create temporary TLB entry in AS0 to handle debug exception + * As on debug exception MSR is cleared i.e. Address space is changed + * to 0. A TLB entry (in AS0) is required to handle debug exception generated + * in AS1. + */ + +#ifdef NOR_BOOT +/* + * TLB entry is created for IVPR + IVOR15 to map on valid OP code address + * bacause flash's virtual address maps to 0xff800000 - 0xffffffff. + * and this window is outside of 4K boot window. + */ + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ + 0, BOOKE_PAGESZ_4M, \ + CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \ + 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 + +#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ + 0, BOOKE_PAGESZ_1M, \ + CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \ + CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 +#else +/* + * TLB entry is created for IVPR + IVOR15 to map on valid OP code address + * because "nexti" will resize TLB to 4K + */ + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ + 0, BOOKE_PAGESZ_256K, \ + CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \ + CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 +#endif +#endif + /* * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default * location is not where we want it. This typically happens on a 36-bit @@ -1036,7 +1038,7 @@ create_init_ram_area: lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l -#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) +#ifdef NOR_BOOT /* create a temp mapping in AS=1 to the 4M boot window */ create_tlb1_entry 15, \ 1, BOOKE_PAGESZ_4M, \ @@ -1050,8 +1052,8 @@ create_init_ram_area: */ create_tlb1_entry 15, \ 1, BOOKE_PAGESZ_1M, \ - CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \ - CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \ + CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ + CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 #else /* @@ -1060,8 +1062,8 @@ create_init_ram_area: */ create_tlb1_entry 15, \ 1, BOOKE_PAGESZ_1M, \ - CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \ - CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \ + CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ + CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 #endif @@ -1111,7 +1113,8 @@ switch_as: bdnz 1b /* Jump out the last 4K page and continue to 'normal' start */ -#ifdef CONFIG_SYS_RAMBOOT +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) + /* We assume that we're already running at the address we're linked at */ b _start_cont #else /* Calculate absolute address in FLASH and jump there */ @@ -1157,7 +1160,7 @@ _start_cont: /* NOTREACHED - board_init_f() does not return */ -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL . = EXC_OFF_SYS_RESET .globl _start_of_vectors _start_of_vectors: @@ -1601,7 +1604,7 @@ in32: in32r: lwbrx r3,r0,r3 blr -#endif /* !CONFIG_NAND_SPL */ +#endif /* !MINIMAL_SPL */ /*------------------------------------------------------------------------------*/ @@ -1798,7 +1801,7 @@ clear_bss: mr r4,r10 /* Destination Address */ bl board_init_r -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL /* * Copy exception vector code to low memory * @@ -1971,4 +1974,4 @@ setup_ivors: #include "fixed_ivor.S" blr -#endif /* !CONFIG_NAND_SPL */ +#endif /* !MINIMAL_SPL */ diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index a548dec..f44fadc 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -55,7 +55,7 @@ void init_tlbs(void) return ; } -#ifndef CONFIG_NAND_SPL +#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, phys_addr_t *rpn) { @@ -332,4 +332,4 @@ void clear_ddr_tlbs(unsigned int memsize_in_meg) } -#endif /* !CONFIG_NAND_SPL */ +#endif /* not SPL */ diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds new file mode 100644 index 0000000..1c408e2 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de + * + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "config.h" /* CONFIG_BOARDDIR */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + . = CONFIG_SPL_TEXT_BASE; + .text : { + *(.text*) + } + _etext = .; + + .reloc : { + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + . = ALIGN(8); + .data : { + *(.rodata*) + *(.data*) + *(.sdata*) + } + _edata = .; + + . = ALIGN(8); + __init_begin = .; + __init_end = .; +/* FIXME for non-NAND SPL */ +#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ + .bootpg ADDR(.text) + 0x1000 : + { + start.o (.bootpg) + } +#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */ +#elif defined(CONFIG_FSL_ELBC) +#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */ +#else +#error unknown NAND controller +#endif + .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : { + KEEP(*(.resetvec)) + } = 0xffff + + /* + * Make sure that the bss segment isn't linked at 0x0, otherwise its + * address won't be updated during relocation fixups. + */ + . |= 0x10; + + __bss_start = .; + .bss : { + *(.sbss*) + *(.bss*) + } + __bss_end__ = .; +} diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index 4ae26e4..3dc8e05 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -10,6 +10,20 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib8xxx.o +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifdef MINIMAL + +COBJS-$(CONFIG_FSL_LAW) += law.o + +else + ifneq ($(CPU),mpc83xx) COBJS-y += cpu.o endif @@ -18,6 +32,9 @@ COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o COBJS-$(CONFIG_SYS_SRIO) += srio.o +COBJS-$(CONFIG_FSL_LAW) += law.o + +endif SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/drivers/misc/fsl_law.c b/arch/powerpc/cpu/mpc8xxx/law.c index 223cd5d..ce1d71e 100644 --- a/drivers/misc/fsl_law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -92,7 +92,7 @@ void disable_law(u8 idx) return; } -#ifndef CONFIG_NAND_SPL +#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) static int get_law_entry(u8 i, struct law_entry *e) { u32 lawar; @@ -122,7 +122,7 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) return idx; } -#ifndef CONFIG_NAND_SPL +#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { u32 idx; @@ -233,7 +233,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id) return 0; } -#endif +#endif /* not SPL */ void init_laws(void) { @@ -258,9 +258,10 @@ void init_laws(void) gd->used_laws |= (1 << i); } -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) /* - * in NAND boot we've already parsed the law_table and setup those LAWs + * in SPL boot we've already parsed the law_table and setup those LAWs * so don't do it again. */ return; diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 808021c..20c5c38 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -38,8 +38,21 @@ endif LIB = $(obj)lib$(ARCH).o -SOBJS-y += ppccache.o +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifdef MINIMAL +COBJS-y += cache.o +else + SOBJS-y += ppcstring.o + +SOBJS-y += ppccache.o SOBJS-y += ticks.o SOBJS-y += reloc.o @@ -64,6 +77,8 @@ $(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy COBJS-y += memcpy_mpc5200.o endif +endif # not minimal + COBJS += $(sort $(COBJS-y)) SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \ @@ -75,12 +90,6 @@ TARGETS += $(LIB) all: $(TARGETS) $(LIB): $(obj).depend $(OBJS) - @if ! $(CROSS_COMPILE)readelf -S $(OBJS) | grep -q '\.fixup.*PROGBITS';\ - then \ - echo "ERROR: Your compiler doesn't generate .fixup sections!";\ - echo " Upgrade to a recent toolchain."; \ - exit 1; \ - fi; $(call cmd_link_o_target, $(OBJS)) $(LIBGCC): $(obj).depend $(LGOBJS) diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile index 0dcf7d1..5b45d72 100644 --- a/board/freescale/p1_p2_rdb_pc/Makefile +++ b/board/freescale/p1_p2_rdb_pc/Makefile @@ -24,11 +24,27 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifdef MINIMAL + +COBJS-y += spl_minimal.o tlb.o law.o + +else + COBJS-y += $(BOARD).o COBJS-y += ddr.o COBJS-y += law.o COBJS-y += tlb.o +endif + SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 88ba56f..9355536 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -206,6 +206,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, } #endif /* CONFIG_SYS_DDR_RAW_TIMING */ +#ifdef CONFIG_SYS_DDR_CS0_BNDS /* Fixed sdram init -- doesn't use serial presence detect. */ phys_size_t fixed_sdram(void) { @@ -260,6 +261,7 @@ phys_size_t fixed_sdram(void) return ddr_size; } +#endif void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 0da8300..cb5e7b7 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -32,7 +32,7 @@ struct law_entry law_table[] = { #endif SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), #ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), #endif }; diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index aa39260..5b5b86c 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -177,7 +177,7 @@ void board_gpio_init(void) */ setbits_be32(&pgpio->gpdir, 0x02130000); -#ifndef CONFIG_SYS_RAMBOOT +#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL) /* init DDR3 reset signal */ setbits_be32(&pgpio->gpdir, 0x00200000); setbits_be32(&pgpio->gpodr, 0x00200000); diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index 4c140c1..d48fb01 100644 --- a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -23,16 +23,18 @@ #include <ns16550.h> #include <asm/io.h> #include <nand.h> +#include <linux/compiler.h> #include <asm/fsl_law.h> #include <asm/fsl_ddr_sdram.h> #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_SYS_INIT_L2_ADDR /* * Fixed sdram init -- doesn't use serial presence detect. */ -void sdram_init(void) +static void sdram_init(void) { ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; @@ -71,6 +73,7 @@ void sdram_init(void) set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1); } +#endif void board_init_f(ulong bootflag) { @@ -101,15 +104,16 @@ void board_init_f(ulong bootflag) __raw_writel(0x00000000, &pgpio->gpdir); #endif +#ifndef CONFIG_SYS_INIT_L2_ADDR /* Initialize the DDR3 */ sdram_init(); +#endif /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. */ - relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, - CONFIG_SYS_NAND_U_BOOT_RELOC); + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); } void board_init_r(gd_t *gd, ulong dest_addr) diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 6d22463..3e4dffd 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -53,7 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), -#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD /* W**G* - Flash/promjet, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, @@ -85,7 +85,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), -#endif +#endif /* not SPL */ #ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */ @@ -94,7 +94,17 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 7, BOOKE_PAGESZ_1M, 1), #endif -#ifdef CONFIG_SYS_RAMBOOT +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) +#ifdef CONFIG_SYS_INIT_L2_ADDR + /* L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_256K, 1), +#else /* *I*G - eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, @@ -106,9 +116,9 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_1G, 1), -#endif -#endif - +#endif /* P1020MBG */ +#endif /* not L2 SRAM */ +#endif /* RAMBOOT/SPL */ }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 4b16069..1568594 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -700,6 +700,25 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return ret == 0 ? 0 : 1; } +#ifdef CONFIG_CMD_NAND_TORTURE + if (strcmp(cmd, "torture") == 0) { + if (argc < 3) + goto usage; + + if (!str2off(argv[2], &off)) { + puts("Offset is not a valid number\n"); + return 1; + } + + printf("\nNAND torture: device %d offset 0x%llx size 0x%x\n", + dev, off, nand->erasesize); + ret = nand_torture(nand, off); + printf(" %s\n", ret ? "Failed" : "Passed"); + + return ret == 0 ? 0 : 1; + } +#endif + if (strcmp(cmd, "markbad") == 0) { argc -= 2; argv += 2; @@ -810,6 +829,9 @@ static char nand_help_text[] = "nand erase.chip [clean] - erase entire chip'\n" "nand bad - show bad blocks\n" "nand dump[.oob] off - dump page\n" +#ifdef CONFIG_CMD_NAND_TORTURE + "nand torture off - torture block at offset\n" +#endif "nand scrub [-y] off size | scrub.part partition | scrub.chip\n" " really clean NAND erasing bad blocks (UNSAFE)\n" "nand markbad off [...] - mark bad block(s) at offset (UNSAFE)\n" diff --git a/doc/README.mpc85xx b/doc/README.mpc85xx index 5a4b591..f9b023f 100644 --- a/doc/README.mpc85xx +++ b/doc/README.mpc85xx @@ -26,7 +26,7 @@ Major Config Switches during various boot Modes ---------------------------------------------- NOR boot - !defined(CONFIG_SYS_RAMBOOT) + !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL) NOR boot Secure !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) RAMBOOT(SD, SPI & NAND boot) diff --git a/doc/README.nand b/doc/README.nand index c130189..a1a511c 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -108,6 +108,9 @@ Configuration Options: CONFIG_CMD_NAND Enables NAND support and commmands. + CONFIG_CMD_NAND_TORTURE + Enables the torture command (see description of this command below). + CONFIG_MTD_NAND_ECC_JFFS2 Define this if you want the Error Correction Code information in the out-of-band data to be formatted to match the JFFS2 file system. @@ -213,6 +216,24 @@ Miscellaneous and testing commands: DANGEROUS!!! Factory set bad blocks will be lost. Use only to remove artificial bad blocks created with the "markbad" command. + "torture offset" + Torture block to determine if it is still reliable. + Enabled by the CONFIG_CMD_NAND_TORTURE configuration option. + This command returns 0 if the block is still reliable, else 1. + If the block is detected as unreliable, it is up to the user to decide to + mark this block as bad. + The analyzed block is put through 3 erase / write cycles (or less if the block + is detected as unreliable earlier). + This command can be used in scripts, e.g. together with the markbad command to + automate retries and handling of possibly newly detected bad blocks if the + nand write command fails. + It can also be used manually by users having seen some NAND errors in logs to + search the root cause of these errors. + The underlying nand_torture() function is also useful for code willing to + automate actions following a nand->write() error. This would e.g. be required + in order to program or update safely firmware to NAND, especially for the UBI + part of such firmware. + NAND locking command (for chips with active LOCKPRE pin) diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index cdec88b..1f035e6 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -27,7 +27,6 @@ LIB := $(obj)libmisc.o COBJS-$(CONFIG_ALI152X) += ali512x.o COBJS-$(CONFIG_DS4510) += ds4510.o -COBJS-$(CONFIG_FSL_LAW) += fsl_law.o COBJS-$(CONFIG_GPIO_LED) += gpio_led.o COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o COBJS-$(CONFIG_NS87308) += ns87308.o diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index beb99ca..28e52bd 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -26,21 +26,33 @@ include $(TOPDIR)/config.mk LIB := $(obj)libnand.o ifdef CONFIG_CMD_NAND + ifdef CONFIG_SPL_BUILD -ifdef CONFIG_SPL_NAND_SIMPLE -COBJS-y += nand_spl_simple.o -endif -ifdef CONFIG_SPL_NAND_LOAD -COBJS-y += nand_spl_load.o + +ifdef CONFIG_SPL_NAND_DRIVERS +NORMAL_DRIVERS=y endif -else + +COBJS-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o +COBJS-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o +COBJS-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o +COBJS-$(CONFIG_SPL_NAND_BASE) += nand_base.o + +else # not spl + +NORMAL_DRIVERS=y + COBJS-y += nand.o COBJS-y += nand_bbt.o COBJS-y += nand_ids.o COBJS-y += nand_util.o -endif COBJS-y += nand_ecc.o COBJS-y += nand_base.o + +endif # not spl + +ifdef NORMAL_DRIVERS + COBJS-$(CONFIG_NAND_ECC_BCH) += nand_bch.o COBJS-$(CONFIG_NAND_ATMEL) += atmel_nand.o @@ -65,7 +77,13 @@ COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o COBJS-$(CONFIG_TEGRA_NAND) += tegra_nand.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o -endif + +else # minimal SPL drivers + +COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o + +endif # drivers +endif # nand COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 9076ad4..834a8a6 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -748,7 +748,7 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr) /* set up nand options */ nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR | - NAND_USE_FLASH_BBT; + NAND_USE_FLASH_BBT | NAND_NO_SUBPAGE_WRITE; nand->controller = &elbc_ctrl->controller; nand->priv = priv; diff --git a/drivers/mtd/nand/fsl_elbc_spl.c b/drivers/mtd/nand/fsl_elbc_spl.c new file mode 100644 index 0000000..50ff4fe --- /dev/null +++ b/drivers/mtd/nand/fsl_elbc_spl.c @@ -0,0 +1,168 @@ +/* + * NAND boot for Freescale Enhanced Local Bus Controller, Flash Control Machine + * + * (C) Copyright 2006-2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Copyright (c) 2008 Freescale Semiconductor, Inc. + * Author: Scott Wood <scottwood@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/fsl_lbc.h> +#include <nand.h> + +#define WINDOW_SIZE 8192 + +static void nand_wait(void) +{ + fsl_lbc_t *regs = LBC_BASE_ADDR; + + for (;;) { + uint32_t status = in_be32(®s->ltesr); + + if (status == 1) + return; + + if (status & 1) { + puts("read failed (ltesr)\n"); + for (;;); + } + } +} + +static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) +{ + fsl_lbc_t *regs = LBC_BASE_ADDR; + uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; + const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS; + const int block_shift = large ? 17 : 14; + const int block_size = 1 << block_shift; + const int page_size = large ? 2048 : 512; + const int bad_marker = large ? page_size + 0 : page_size + 5; + int fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT) | 2; + int pos = 0; + char *dst = vdst; + + if (offs & (block_size - 1)) { + puts("bad offset\n"); + for (;;); + } + + if (large) { + fmr |= FMR_ECCM; + out_be32(®s->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | + (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); + out_be32(®s->fir, + (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_CW1 << FIR_OP3_SHIFT) | + (FIR_OP_RBW << FIR_OP4_SHIFT)); + } else { + out_be32(®s->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); + out_be32(®s->fir, + (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_RBW << FIR_OP3_SHIFT)); + } + + out_be32(®s->fbcr, 0); + clrsetbits_be32(®s->bank[0].br, BR_DECC, BR_DECC_CHK_GEN); + + while (pos < uboot_size) { + int i = 0; + out_be32(®s->fbar, offs >> block_shift); + + do { + int j; + unsigned int page_offs = (offs & (block_size - 1)) << 1; + + out_be32(®s->ltesr, ~0); + out_be32(®s->lteatr, 0); + out_be32(®s->fpar, page_offs); + out_be32(®s->fmr, fmr); + out_be32(®s->lsor, 0); + nand_wait(); + + page_offs %= WINDOW_SIZE; + + /* + * If either of the first two pages are marked bad, + * continue to the next block. + */ + if (i++ < 2 && buf[page_offs + bad_marker] != 0xff) { + puts("skipping\n"); + offs = (offs + block_size) & ~(block_size - 1); + pos &= ~(block_size - 1); + break; + } + + for (j = 0; j < page_size; j++) + dst[pos + j] = buf[page_offs + j]; + + pos += page_size; + offs += page_size; + } while ((offs & (block_size - 1)) && (pos < uboot_size)); + } + + return 0; +} + +/* + * The main entry for NAND booting. It's necessary that SDRAM is already + * configured and available since this code loads the main U-Boot image + * from NAND into SDRAM and starts it from there. + */ +void nand_boot(void) +{ + __attribute__((noreturn)) void (*uboot)(void); + /* + * Load U-Boot image from NAND into RAM + */ + nand_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + CONFIG_SYS_NAND_U_BOOT_SIZE, + (void *)CONFIG_SYS_NAND_U_BOOT_DST); + +#ifdef CONFIG_NAND_ENV_DST + nand_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (void *)CONFIG_NAND_ENV_DST); + +#ifdef CONFIG_ENV_OFFSET_REDUND + nand_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, + (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); +#endif +#endif + +#ifdef CONFIG_SPL_FLUSH_IMAGE + /* + * Clean d-cache and invalidate i-cache, to + * make sure that no stale data is executed. + */ + flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE); +#endif + + puts("transfering control\n"); + /* + * Jump to U-Boot image + */ + uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; + (*uboot)(); +} diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index b3b7c70..0878bec 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -30,6 +30,7 @@ #include <asm/errno.h> #include <asm/fsl_ifc.h> +#define FSL_IFC_V1_1_0 0x01010000 #define MAX_BANKS 4 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ @@ -738,11 +739,66 @@ static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip) { } +static void fsl_ifc_sram_init(void) +{ + struct fsl_ifc *ifc = ifc_ctrl->regs; + uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0; + long long end_tick; + + cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT; + + /* Save CSOR and CSOR_ext */ + csor = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor); + csor_ext = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext); + + /* chage PageSize 8K and SpareSize 1K*/ + csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000; + out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k); + out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400); + + /* READID */ + out_be32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); + out_be32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT); + out_be32(&ifc->ifc_nand.row3, 0x0); + + out_be32(&ifc->ifc_nand.nand_fbcr, 0x0); + + /* Program ROW0/COL0 */ + out_be32(&ifc->ifc_nand.row0, 0x0); + out_be32(&ifc->ifc_nand.col0, 0x0); + + /* set the chip select for NAND Transaction */ + out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); + + /* start read seq */ + out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT); + + /* wait for NAND Machine complete flag or timeout */ + end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); + + while (end_tick > get_ticks()) { + ifc_ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat); + + if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC) + break; + } + + out_be32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status); + + /* Restore CSOR and CSOR_ext */ + out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor); + out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext); +} + int board_nand_init(struct nand_chip *nand) { struct fsl_ifc_mtd *priv; struct nand_ecclayout *layout; - uint32_t cspr = 0, csor = 0; + uint32_t cspr = 0, csor = 0, ver = 0; if (!ifc_ctrl) { fsl_ifc_ctrl_init(); @@ -797,7 +853,7 @@ int board_nand_init(struct nand_chip *nand) /* set up nand options */ nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR | - NAND_USE_FLASH_BBT; + NAND_USE_FLASH_BBT | NAND_NO_SUBPAGE_WRITE; if (cspr & CSPR_PORT_SIZE_16) { nand->read_byte = fsl_ifc_read_byte16; @@ -861,5 +917,9 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.mode = NAND_ECC_SOFT; } + ver = in_be32(&ifc_ctrl->regs->ifc_rev); + if (ver == FSL_IFC_V1_1_0) + fsl_ifc_sram_init(); + return 0; } diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index d3b71a5..a2d06be 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -1245,7 +1245,8 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, if (unlikely(ops->mode == MTD_OOB_RAW)) ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, page); - else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob) + else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && + !oob) ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi); else @@ -1256,7 +1257,7 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, /* Transfer not aligned data */ if (!aligned) { - if (!NAND_SUBPAGE_READ(chip) && !oob && + if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && !(mtd->ecc_stats.failed - stats.failed)) chip->pagebuf = realpage; memcpy(buf, chip->buffers->databuf + col, bytes); @@ -3150,6 +3151,10 @@ int nand_scan_tail(struct mtd_info *mtd) /* Invalidate the pagebuffer reference */ chip->pagebuf = -1; + /* Large page NAND with SOFT_ECC should support subpage reads */ + if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9)) + chip->options |= NAND_SUBPAGE_READ; + /* Fill in remaining MTD driver data */ mtd->type = MTD_NANDFLASH; mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index c4752a7..2ba0c5e 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -50,8 +50,8 @@ #include <nand.h> #include <jffs2/jffs2.h> -typedef struct erase_info erase_info_t; -typedef struct mtd_info mtd_info_t; +typedef struct erase_info erase_info_t; +typedef struct mtd_info mtd_info_t; /* support only for native endian JFFS2 */ #define cpu_to_je16(x) (x) @@ -59,7 +59,7 @@ typedef struct mtd_info mtd_info_t; /** * nand_erase_opts: - erase NAND flash with support for various options - * (jffs2 formating) + * (jffs2 formatting) * * @param meminfo NAND device to erase * @param opts options, @see struct nand_erase_options @@ -80,8 +80,8 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) struct mtd_oob_ops oob_opts; struct nand_chip *chip = meminfo->priv; - if ((opts->offset & (meminfo->writesize - 1)) != 0) { - printf("Attempt to erase non page aligned data\n"); + if ((opts->offset & (meminfo->erasesize - 1)) != 0) { + printf("Attempt to erase non block-aligned data\n"); return -1; } @@ -94,8 +94,8 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) erase_length = lldiv(opts->length + meminfo->erasesize - 1, meminfo->erasesize); - cleanmarker.magic = cpu_to_je16 (JFFS2_MAGIC_BITMASK); - cleanmarker.nodetype = cpu_to_je16 (JFFS2_NODETYPE_CLEANMARKER); + cleanmarker.magic = cpu_to_je16(JFFS2_MAGIC_BITMASK); + cleanmarker.nodetype = cpu_to_je16(JFFS2_NODETYPE_CLEANMARKER); cleanmarker.totlen = cpu_to_je32(8); /* scrub option allows to erase badblock. To prevent internal @@ -118,7 +118,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) erased_length < erase_length; erase.addr += meminfo->erasesize) { - WATCHDOG_RESET (); + WATCHDOG_RESET(); if (!opts->scrub && bbtest) { int ret = meminfo->block_isbad(meminfo, erase.addr); @@ -259,7 +259,7 @@ int nand_lock(struct mtd_info *mtd, int tight) * flash * * @param mtd nand mtd instance - * @param offset page address to query (muss be page aligned!) + * @param offset page address to query (must be page-aligned!) * * @return -1 in case of error * >0 lock status: @@ -281,7 +281,7 @@ int nand_get_lock_status(struct mtd_info *mtd, loff_t offset) if ((offset & (mtd->writesize - 1)) != 0) { - printf ("nand_get_lock_status: " + printf("nand_get_lock_status: " "Start address must be beginning of " "nand page!\n"); ret = -1; @@ -332,20 +332,20 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length, /* check the WP bit */ chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); if (!(chip->read_byte(mtd) & NAND_STATUS_WP)) { - printf ("nand_unlock: Device is write protected!\n"); + printf("nand_unlock: Device is write protected!\n"); ret = -1; goto out; } if ((start & (mtd->erasesize - 1)) != 0) { - printf ("nand_unlock: Start address must be beginning of " + printf("nand_unlock: Start address must be beginning of " "nand block!\n"); ret = -1; goto out; } if (length == 0 || (length & (mtd->erasesize - 1)) != 0) { - printf ("nand_unlock: Length must be a multiple of nand block " + printf("nand_unlock: Length must be a multiple of nand block " "size %08x!\n", mtd->erasesize); ret = -1; goto out; @@ -485,7 +485,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, pages = nand->erasesize / nand->writesize; blocksize = (pages * nand->oobsize) + nand->erasesize; if (*length % (nand->writesize + nand->oobsize)) { - printf ("Attempt to write incomplete page" + printf("Attempt to write incomplete page" " in yaffs mode\n"); return -EINVAL; } @@ -507,25 +507,25 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, * partition boundary). So don't try to handle that. */ if ((offset & (nand->writesize - 1)) != 0) { - printf ("Attempt to write non page aligned data\n"); + printf("Attempt to write non page-aligned data\n"); *length = 0; return -EINVAL; } need_skip = check_skip_len(nand, offset, *length); if (need_skip < 0) { - printf ("Attempt to write outside the flash area\n"); + printf("Attempt to write outside the flash area\n"); *length = 0; return -EINVAL; } if (!need_skip && !(flags & WITH_DROP_FFS)) { - rval = nand_write (nand, offset, length, buffer); + rval = nand_write(nand, offset, length, buffer); if (rval == 0) return 0; *length = 0; - printf ("NAND write to offset %llx failed %d\n", + printf("NAND write to offset %llx failed %d\n", offset, rval); return rval; } @@ -534,10 +534,10 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, size_t block_offset = offset & (nand->erasesize - 1); size_t write_size, truncated_write_size; - WATCHDOG_RESET (); + WATCHDOG_RESET(); - if (nand_block_isbad (nand, offset & ~(nand->erasesize - 1))) { - printf ("Skip bad block 0x%08llx\n", + if (nand_block_isbad(nand, offset & ~(nand->erasesize - 1))) { + printf("Skip bad block 0x%08llx\n", offset & ~(nand->erasesize - 1)); offset += nand->erasesize - block_offset; continue; @@ -592,7 +592,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, } if (rval != 0) { - printf ("NAND write to offset %llx failed %d\n", + printf("NAND write to offset %llx failed %d\n", offset, rval); *length -= left_to_write; return rval; @@ -608,13 +608,13 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, * nand_read_skip_bad: * * Read image from NAND flash. - * Blocks that are marked bad are skipped and the next block is readen + * Blocks that are marked bad are skipped and the next block is read * instead as long as the image is short enough to fit even after skipping the * bad blocks. * * @param nand NAND device * @param offset offset in flash - * @param length buffer length, on return holds remaining bytes to read + * @param length buffer length, on return holds number of read bytes * @param buffer buffer to write to * @return 0 in case of success */ @@ -627,25 +627,25 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, int need_skip; if ((offset & (nand->writesize - 1)) != 0) { - printf ("Attempt to read non page aligned data\n"); + printf("Attempt to read non page-aligned data\n"); *length = 0; return -EINVAL; } need_skip = check_skip_len(nand, offset, *length); if (need_skip < 0) { - printf ("Attempt to read outside the flash area\n"); + printf("Attempt to read outside the flash area\n"); *length = 0; return -EINVAL; } if (!need_skip) { - rval = nand_read (nand, offset, length, buffer); + rval = nand_read(nand, offset, length, buffer); if (!rval || rval == -EUCLEAN) return 0; *length = 0; - printf ("NAND read from offset %llx failed %d\n", + printf("NAND read from offset %llx failed %d\n", offset, rval); return rval; } @@ -654,10 +654,10 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, size_t block_offset = offset & (nand->erasesize - 1); size_t read_length; - WATCHDOG_RESET (); + WATCHDOG_RESET(); - if (nand_block_isbad (nand, offset & ~(nand->erasesize - 1))) { - printf ("Skipping bad block 0x%08llx\n", + if (nand_block_isbad(nand, offset & ~(nand->erasesize - 1))) { + printf("Skipping bad block 0x%08llx\n", offset & ~(nand->erasesize - 1)); offset += nand->erasesize - block_offset; continue; @@ -668,9 +668,9 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, else read_length = nand->erasesize - block_offset; - rval = nand_read (nand, offset, &read_length, p_buffer); + rval = nand_read(nand, offset, &read_length, p_buffer); if (rval && rval != -EUCLEAN) { - printf ("NAND read from offset %llx failed %d\n", + printf("NAND read from offset %llx failed %d\n", offset, rval); *length -= left_to_read; return rval; @@ -683,3 +683,125 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, return 0; } + +#ifdef CONFIG_CMD_NAND_TORTURE + +/** + * check_pattern: + * + * Check if buffer contains only a certain byte pattern. + * + * @param buf buffer to check + * @param patt the pattern to check + * @param size buffer size in bytes + * @return 1 if there are only patt bytes in buf + * 0 if something else was found + */ +static int check_pattern(const u_char *buf, u_char patt, int size) +{ + int i; + + for (i = 0; i < size; i++) + if (buf[i] != patt) + return 0; + return 1; +} + +/** + * nand_torture: + * + * Torture a block of NAND flash. + * This is useful to determine if a block that caused a write error is still + * good or should be marked as bad. + * + * @param nand NAND device + * @param offset offset in flash + * @return 0 if the block is still good + */ +int nand_torture(nand_info_t *nand, loff_t offset) +{ + u_char patterns[] = {0xa5, 0x5a, 0x00}; + struct erase_info instr = { + .mtd = nand, + .addr = offset, + .len = nand->erasesize, + }; + size_t retlen; + int err, ret = -1, i, patt_count; + u_char *buf; + + if ((offset & (nand->erasesize - 1)) != 0) { + puts("Attempt to torture a block at a non block-aligned offset\n"); + return -EINVAL; + } + + if (offset + nand->erasesize > nand->size) { + puts("Attempt to torture a block outside the flash area\n"); + return -EINVAL; + } + + patt_count = ARRAY_SIZE(patterns); + + buf = malloc(nand->erasesize); + if (buf == NULL) { + puts("Out of memory for erase block buffer\n"); + return -ENOMEM; + } + + for (i = 0; i < patt_count; i++) { + err = nand->erase(nand, &instr); + if (err) { + printf("%s: erase() failed for block at 0x%llx: %d\n", + nand->name, instr.addr, err); + goto out; + } + + /* Make sure the block contains only 0xff bytes */ + err = nand->read(nand, offset, nand->erasesize, &retlen, buf); + if ((err && err != -EUCLEAN) || retlen != nand->erasesize) { + printf("%s: read() failed for block at 0x%llx: %d\n", + nand->name, instr.addr, err); + goto out; + } + + err = check_pattern(buf, 0xff, nand->erasesize); + if (!err) { + printf("Erased block at 0x%llx, but a non-0xff byte was found\n", + offset); + ret = -EIO; + goto out; + } + + /* Write a pattern and check it */ + memset(buf, patterns[i], nand->erasesize); + err = nand->write(nand, offset, nand->erasesize, &retlen, buf); + if (err || retlen != nand->erasesize) { + printf("%s: write() failed for block at 0x%llx: %d\n", + nand->name, instr.addr, err); + goto out; + } + + err = nand->read(nand, offset, nand->erasesize, &retlen, buf); + if ((err && err != -EUCLEAN) || retlen != nand->erasesize) { + printf("%s: read() failed for block at 0x%llx: %d\n", + nand->name, instr.addr, err); + goto out; + } + + err = check_pattern(buf, patterns[i], nand->erasesize); + if (!err) { + printf("Pattern 0x%.2x checking failed for block at " + "0x%llx\n", patterns[i], offset); + ret = -EIO; + goto out; + } + } + + ret = 0; + +out: + free(buf); + return ret; +} + +#endif diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 9027781..bbd91ca 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -36,6 +36,9 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) { + while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT)) + ; + serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \ defined(CONFIG_AM33XX) diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index c1c0134..fc01a3c 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -31,6 +31,8 @@ #include <serial.h> +#ifndef CONFIG_NS16550_MIN_FUNCTIONS + DECLARE_GLOBAL_DATA_PTR; #if !defined(CONFIG_CONS_INDEX) @@ -304,3 +306,5 @@ void ns16550_serial_initialize(void) serial_register(&eserial6_device); #endif } + +#endif /* !CONFIG_NS16550_MIN_FUNCTIONS */ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 20a3df5..e1ad1e5 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -337,6 +337,9 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 9484e55..ba15325 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -331,6 +331,9 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h index 56dc1cb..a7a698c 100644 --- a/include/configs/cam_enc_4xx.h +++ b/include/configs/cam_enc_4xx.h @@ -219,6 +219,9 @@ #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST #define CONFIG_SPL_SERIAL_SUPPORT diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index ddd6155..99b4de7 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -227,6 +227,9 @@ #define CONFIG_SYS_NAND_ECCBYTES 10 #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_NAND_LOAD #endif diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index da3263f..83a8b5d 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -316,6 +316,9 @@ #define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h index c0e3ed3..8d27590 100644 --- a/include/configs/hawkboard.h +++ b/include/configs/hawkboard.h @@ -63,6 +63,9 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_LIBGENERIC_SUPPORT /* for udelay and __div64_32 for NAND */ #define CONFIG_SPL_SERIAL_SUPPORT diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index c81ab76..be7937d 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -338,6 +338,9 @@ #ifdef CONFIG_BOOT_NAND #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE diff --git a/include/configs/mcx.h b/include/configs/mcx.h index e18d879..e304c99 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -378,6 +378,9 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 31ffb32..12d65f2 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -412,6 +412,9 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_OMAP3_ID_NAND diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index f6e4236..b4d925e 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -113,6 +113,9 @@ /* NAND SPL */ #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h index 362fa1d..8f02584 100644 --- a/include/configs/omap3_evm_quick_nand.h +++ b/include/configs/omap3_evm_quick_nand.h @@ -81,6 +81,9 @@ */ #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 626cf7a..fd31c73 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -319,6 +319,9 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 350150b..964bfcd 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -38,6 +38,7 @@ #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xe4 #define __SW_BOOT_SD 0x54 +#define CONFIG_SYS_L2_SIZE (256 << 10) #endif #if defined(CONFIG_P1020UTM) @@ -46,6 +47,7 @@ #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xe0 #define __SW_BOOT_SD 0x50 +#define CONFIG_SYS_L2_SIZE (256 << 10) #endif #if defined(CONFIG_P1020RDB) @@ -61,6 +63,7 @@ #define __SW_BOOT_SD 0x9c #define __SW_BOOT_NAND 0xec #define __SW_BOOT_PCIE 0x6c +#define CONFIG_SYS_L2_SIZE (256 << 10) #endif #if defined(CONFIG_P1021RDB) @@ -78,6 +81,7 @@ #define __SW_BOOT_SD 0x9c #define __SW_BOOT_NAND 0xec #define __SW_BOOT_PCIE 0x6c +#define CONFIG_SYS_L2_SIZE (256 << 10) #endif #if defined(CONFIG_P1024RDB) @@ -91,6 +95,7 @@ #define __SW_BOOT_SPI 0x08 #define __SW_BOOT_SD 0x04 #define __SW_BOOT_NAND 0x0c +#define CONFIG_SYS_L2_SIZE (256 << 10) #endif #if defined(CONFIG_P1025RDB) @@ -108,6 +113,7 @@ #define __SW_BOOT_SPI 0x08 #define __SW_BOOT_SD 0x04 #define __SW_BOOT_NAND 0x0c +#define CONFIG_SYS_L2_SIZE (256 << 10) #endif #if defined(CONFIG_P2020RDB) @@ -122,6 +128,14 @@ #define __SW_BOOT_SD 0x68 /* or 0x18 */ #define __SW_BOOT_NAND 0xe8 #define __SW_BOOT_PCIE 0xa8 +#define CONFIG_SYS_L2_SIZE (512 << 10) +#endif + +#if CONFIG_SYS_L2_SIZE >= (512 << 10) +/* must be 32-bit */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #endif #ifdef CONFIG_SDCARD @@ -140,16 +154,39 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc #endif -#if defined(CONFIG_NAND) && defined(CONFIG_NAND_FSL_ELBC) -#define CONFIG_NAND_U_BOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_TEXT_BASE_SPL 0xff800000 -#ifdef CONFIG_NAND_SPL -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL +#ifdef CONFIG_NAND +#define CONFIG_SPL +#define CONFIG_SPL_INIT_MINIMAL +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" + +#define CONFIG_SPL_TEXT_BASE 0xfffff000 +#define CONFIG_SPL_MAX_SIZE (4 * 1024) + +#ifdef CONFIG_SYS_INIT_L2_ADDR +/* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */ +#define CONFIG_SYS_TEXT_BASE 0xf8f82000 +#define CONFIG_SPL_RELOC_TEXT_BASE \ + (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2) +#define CONFIG_SPL_RELOC_STACK \ + (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2) +#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) +#define CONFIG_SYS_NAND_U_BOOT_START \ + (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SPL_MAX_SIZE) #else -#define CONFIG_SYS_TEXT_BASE 0x11001000 -#endif /* CONFIG_NAND_SPL */ +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 +#define CONFIG_SPL_RELOC_STACK 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#endif + +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #endif #ifndef CONFIG_SYS_TEXT_BASE @@ -161,8 +198,12 @@ #endif #ifndef CONFIG_SYS_MONITOR_BASE +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif +#endif /* High Level Configuration Options */ #define CONFIG_BOOKE @@ -221,7 +262,7 @@ /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k SPL code*/ -#if defined(CONFIG_NAND_SPL) +#ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif @@ -248,39 +289,7 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Default settings for DDR3 */ -#ifdef CONFIG_P2020RDB -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 -#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 - -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 - -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8645F607 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC7000000 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x02401400 - -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x00330104 -#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4644 -#define CONFIG_SYS_DDR_TIMING_2 0x0FA88CCF -#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000 -#define CONFIG_SYS_DDR_MODE_1 0x00421422 -#define CONFIG_SYS_DDR_MODE_2 0x04000000 -#define CONFIG_SYS_DDR_INTERVAL 0x0C300100 - -#else +#ifndef CONFIG_P2020RDB #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 @@ -318,21 +327,18 @@ /* * Memory map * - * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable + * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) + * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 + * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable + * (early boot only) + * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 + * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 + * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 + * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable - * - * Localbus cacheable (TBD) - * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable - * - * Localbus non-cacheable - * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable - * 0xff80_0000 0xff8f_ffff NAND flash 1M non-cacheable - * 0xff90_0000 0xff97_ffff L2 SDRAM(REV.) 512K cacheable(optional) - * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable - * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable */ @@ -392,15 +398,6 @@ #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) -/* NAND boot: 4K NAND loader config */ -#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) -#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) - #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ @@ -461,7 +458,7 @@ OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ OR_GPCM_EAD) -#ifdef CONFIG_NAND_U_BOOT +#ifdef CONFIG_NAND #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ @@ -511,7 +508,7 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#ifdef CONFIG_NAND_SPL +#ifdef CONFIG_SPL_BUILD #define CONFIG_NS16550_MIN_FUNCTIONS #endif @@ -709,7 +706,6 @@ /* * Environment */ -#ifdef CONFIG_SYS_RAMBOOT #ifdef CONFIG_RAMBOOT_SPIFLASH #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_BUS 0 @@ -724,16 +720,15 @@ #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 -#elif defined(CONFIG_NAND_U_BOOT) +#elif defined(CONFIG_NAND) #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) -#else +#elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #define CONFIG_ENV_SIZE 0x2000 -#endif #else #define CONFIG_ENV_IS_IN_FLASH #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index ac534ac..ee73c27 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -252,6 +252,9 @@ #define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 5859a73..be0d2ec 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -282,6 +282,9 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index f63e04b..e9e9045 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -194,6 +194,9 @@ typedef enum { /* Device behaves just like nand, but is readonly */ #define NAND_ROM 0x00000800 +/* Device supports subpage reads */ +#define NAND_SUBPAGE_READ 0x00001000 + /* Options valid for Samsung large page devices */ #define NAND_SAMSUNG_LP_OPTIONS \ (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) @@ -203,9 +206,7 @@ typedef enum { #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) -/* Large page NAND with SOFT_ECC should support subpage reads */ -#define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \ - && (chip->page_shift > 9)) +#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) /* Non chip related options */ /* diff --git a/include/nand.h b/include/nand.h index bbe28b2..dded4e2 100644 --- a/include/nand.h +++ b/include/nand.h @@ -139,6 +139,7 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, u_char *buffer, int flags); int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts); +int nand_torture(nand_info_t *nand, loff_t offset); #define NAND_LOCK_STATUS_TIGHT 0x01 #define NAND_LOCK_STATUS_UNLOCK 0x04 diff --git a/nand_spl/board/freescale/common.c b/nand_spl/board/freescale/common.c deleted file mode 100644 index 0e099bc..0000000 --- a/nand_spl/board/freescale/common.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * Author: Matthew McClintock <msm@freescale.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_FSL_TBCLK_DIV -#define CONFIG_SYS_FSL_TBCLK_DIV 8 -#endif - -void udelay(unsigned long usec) -{ - u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000); - u32 ticks = ticks_per_usec * usec; - u32 s = mfspr(SPRN_TBRL); - - while ((mfspr(SPRN_TBRL) - s) < ticks); -} diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile index 822ae7c..9c77826 100644 --- a/nand_spl/board/freescale/mpc8536ds/Makefile +++ b/nand_spl/board/freescale/mpc8536ds/Makefile @@ -39,7 +39,7 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) @@ -80,13 +80,13 @@ $(obj)cpu_init_early.c: @rm -f $(obj)cpu_init_early.c ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c -$(obj)cpu_init_nand.c: - @rm -f $(obj)cpu_init_nand.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c +$(obj)spl_minimal.c: + @rm -f $(obj)spl_minimal.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c $(obj)fsl_law.c: @rm -f $(obj)fsl_law.c - ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c $(obj)law.c: @rm -f $(obj)law.c diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile index 822ae7c..9c77826 100644 --- a/nand_spl/board/freescale/mpc8569mds/Makefile +++ b/nand_spl/board/freescale/mpc8569mds/Makefile @@ -39,7 +39,7 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) @@ -80,13 +80,13 @@ $(obj)cpu_init_early.c: @rm -f $(obj)cpu_init_early.c ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c -$(obj)cpu_init_nand.c: - @rm -f $(obj)cpu_init_nand.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c +$(obj)spl_minimal.c: + @rm -f $(obj)spl_minimal.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c $(obj)fsl_law.c: @rm -f $(obj)fsl_law.c - ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c $(obj)law.c: @rm -f $(obj)law.c diff --git a/nand_spl/board/freescale/mpc8572ds/Makefile b/nand_spl/board/freescale/mpc8572ds/Makefile index 822ae7c..9c77826 100644 --- a/nand_spl/board/freescale/mpc8572ds/Makefile +++ b/nand_spl/board/freescale/mpc8572ds/Makefile @@ -39,7 +39,7 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) @@ -80,13 +80,13 @@ $(obj)cpu_init_early.c: @rm -f $(obj)cpu_init_early.c ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c -$(obj)cpu_init_nand.c: - @rm -f $(obj)cpu_init_nand.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c +$(obj)spl_minimal.c: + @rm -f $(obj)spl_minimal.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c $(obj)fsl_law.c: @rm -f $(obj)fsl_law.c - ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c $(obj)law.c: @rm -f $(obj)law.c diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile index 9dff942..c3495ec 100644 --- a/nand_spl/board/freescale/p1010rdb/Makefile +++ b/nand_spl/board/freescale/p1010rdb/Makefile @@ -39,9 +39,8 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o ticks.o -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o \ - ../common.o +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ + nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -81,13 +80,13 @@ $(obj)cpu_init_early.c: @rm -f $(obj)cpu_init_early.c ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c -$(obj)cpu_init_nand.c: - @rm -f $(obj)cpu_init_nand.c - ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c +$(obj)spl_minimal.c: + @rm -f $(obj)spl_minimal.c + ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c $(obj)fsl_law.c: @rm -f $(obj)fsl_law.c - ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c $(obj)law.c: @rm -f $(obj)law.c @@ -130,9 +129,6 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c -$(obj)../common.c: - @rm -f $(obj)../common.c - ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c endif ######################################################################### diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile index 7a87cf6..9b2c0d7 100644 --- a/nand_spl/board/freescale/p1023rds/Makefile +++ b/nand_spl/board/freescale/p1023rds/Makefile @@ -34,9 +34,8 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \ - ../common.o +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -76,13 +75,13 @@ $(obj)cpu_init_early.c: @rm -f $(obj)cpu_init_early.c ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c -$(obj)cpu_init_nand.c: - @rm -f $(obj)cpu_init_nand.c - ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c +$(obj)spl_minimal.c: + @rm -f $(obj)spl_minimal.c + ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c $(obj)fsl_law.c: @rm -f $(obj)fsl_law.c - ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c $(obj)law.c: @rm -f $(obj)law.c @@ -121,9 +120,6 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c -$(obj)../common.c: - @rm -f $(obj)../common.c - ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c endif ######################################################################### diff --git a/nand_spl/board/freescale/p1_p2_rdb/Makefile b/nand_spl/board/freescale/p1_p2_rdb/Makefile index 822ae7c..9c77826 100644 --- a/nand_spl/board/freescale/p1_p2_rdb/Makefile +++ b/nand_spl/board/freescale/p1_p2_rdb/Makefile @@ -39,7 +39,7 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) @@ -80,13 +80,13 @@ $(obj)cpu_init_early.c: @rm -f $(obj)cpu_init_early.c ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c -$(obj)cpu_init_nand.c: - @rm -f $(obj)cpu_init_nand.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c +$(obj)spl_minimal.c: + @rm -f $(obj)spl_minimal.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c $(obj)fsl_law.c: @rm -f $(obj)fsl_law.c - ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c $(obj)law.c: @rm -f $(obj)law.c diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile deleted file mode 100644 index 7146d16..0000000 --- a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile +++ /dev/null @@ -1,146 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# Copyright 2011 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -NAND_SPL := y -CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000 -PAD_TO := 0xff801000 - -include $(TOPDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds -LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst -LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ - $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL - -SOBJS = start.o resetvec.o -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \ - ../common.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl - -# The following line expands into whole rule which generates $(LSTSCRIPT), -# the file containing u-boots LG-array linker section. This is included into -# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. -$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@ - -# create symbolic links for common files - -$(obj)cache.c: - @rm -f $(obj)cache.c - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c - -$(obj)cpu_init_early.c: - @rm -f $(obj)cpu_init_early.c - ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c - -$(obj)cpu_init_nand.c: - @rm -f $(obj)cpu_init_nand.c - ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c - -$(obj)fsl_law.c: - @rm -f $(obj)fsl_law.c - ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c - -$(obj)law.c: - @rm -f $(obj)law.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c - -$(obj)nand_boot_fsl_elbc.c: - @rm -f $(obj)nand_boot_fsl_elbc.c - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ - $(obj)nand_boot_fsl_elbc.c - -$(obj)ns16550.c: - @rm -f $(obj)ns16550.c - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c - -$(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S - -$(obj)fixed_ivor.S: - @rm -f $(obj)fixed_ivor.S - ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S - -$(obj)start.S: $(obj)fixed_ivor.S - @rm -f $(obj)start.S - ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S - -$(obj)tlb.c: - @rm -f $(obj)tlb.c - ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c - -$(obj)tlb_table.c: - @rm -f $(obj)tlb_table.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c -$(obj)../common.c: - @rm -f $(obj)../common.c - ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/spl/Makefile b/spl/Makefile index 3195390..eacf4a2 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -32,9 +32,30 @@ START_PATH := $(CPUDIR) endif START := $(START_PATH)/start.o +ifeq ($(CPU),x86) +START += $(START_PATH)/start16.o +START += $(START_PATH)/resetvec.o +endif +ifeq ($(CPU),ppc4xx) +START += $(START_PATH)/resetvec.o +endif +ifeq ($(CPU),mpc85xx) +START += $(START_PATH)/resetvec.o +endif LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o + LIBS-y += $(CPUDIR)/lib$(CPU).o +ifeq ($(CPU),mpc83xx) +LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o +endif +ifeq ($(CPU),mpc85xx) +LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o +endif +ifeq ($(CPU),mpc86xx) +LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o +endif + ifdef SOC LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o endif |