diff options
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 4 | ||||
| -rw-r--r-- | board/freescale/mx6sllevk/mx6sllevk.c | 226 | ||||
| -rw-r--r-- | configs/mx6sll_lpddr3_arm2_epdc_defconfig | 1 | ||||
| -rw-r--r-- | configs/mx6sllevk_epdc_defconfig | 45 | ||||
| -rw-r--r-- | include/configs/mx6sll_arm2.h | 6 | ||||
| -rw-r--r-- | include/configs/mx6sllevk.h | 15 | ||||
| -rw-r--r-- | include/mxc_epdc_fb.h | 6 |
7 files changed, 294 insertions, 9 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 4bce9f3..772b047 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -1607,7 +1607,8 @@ void enable_eim_clk(unsigned char enable) } #endif -#if defined(CONFIG_MXC_EPDC) && defined(CONFIG_MX6ULL) +#if defined(CONFIG_MXC_EPDC) +#if defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL) void enable_epdc_clock(void) { u32 reg = 0; @@ -1635,6 +1636,7 @@ void enable_epdc_clock(void) setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK); } #endif +#endif /***************************************************/ diff --git a/board/freescale/mx6sllevk/mx6sllevk.c b/board/freescale/mx6sllevk/mx6sllevk.c index 26d5979..d42e0b5 100644 --- a/board/freescale/mx6sllevk/mx6sllevk.c +++ b/board/freescale/mx6sllevk/mx6sllevk.c @@ -21,6 +21,11 @@ #include <power/pmic.h> #include <power/pfuze100_pmic.h> #include "../common/pfuze.h" + +#if defined(CONFIG_MXC_EPDC) +#include <lcd.h> +#include <mxc_epdc_fb.h> +#endif #include <asm/imx-common/video.h> DECLARE_GLOBAL_DATA_PTR; @@ -32,6 +37,9 @@ DECLARE_GLOBAL_DATA_PTR; #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -183,6 +191,219 @@ struct display_info_t const displays[] = {{ size_t display_count = ARRAY_SIZE(displays); #endif +#ifdef CONFIG_MXC_EPDC +static iomux_v3_cfg_t const epdc_enable_pads[] = { + MX6_PAD_EPDC_DATA00__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA01__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA02__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA03__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA04__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA05__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA06__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA07__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA08__EPDC_DATA08 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA09__EPDC_DATA09 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA10__EPDC_DATA10 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA11__EPDC_DATA11 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA12__EPDC_DATA12 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA13__EPDC_DATA13 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA14__EPDC_DATA14 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA15__EPDC_DATA15 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDCLK__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + MX6_PAD_EPDC_DATA01__GPIO1_IO08, + MX6_PAD_EPDC_DATA02__GPIO1_IO09, + MX6_PAD_EPDC_DATA03__GPIO1_IO10, + MX6_PAD_EPDC_DATA04__GPIO1_IO11, + MX6_PAD_EPDC_DATA05__GPIO1_IO12, + MX6_PAD_EPDC_DATA06__GPIO1_IO13, + MX6_PAD_EPDC_DATA07__GPIO1_IO14, + MX6_PAD_EPDC_DATA08__GPIO1_IO15, + MX6_PAD_EPDC_DATA09__GPIO1_IO16, + MX6_PAD_EPDC_DATA10__GPIO1_IO17, + MX6_PAD_EPDC_DATA11__GPIO1_IO18, + MX6_PAD_EPDC_DATA12__GPIO1_IO19, + MX6_PAD_EPDC_DATA13__GPIO1_IO20, + MX6_PAD_EPDC_DATA14__GPIO1_IO21, + MX6_PAD_EPDC_DATA15__GPIO1_IO22, + MX6_PAD_EPDC_SDCLK__GPIO1_IO23, + MX6_PAD_EPDC_SDLE__GPIO1_IO24, + MX6_PAD_EPDC_SDOE__GPIO1_IO25, + MX6_PAD_EPDC_SDSHR__GPIO1_IO26, + MX6_PAD_EPDC_SDCE0__GPIO1_IO27, + MX6_PAD_EPDC_GDCLK__GPIO1_IO31, + MX6_PAD_EPDC_GDOE__GPIO2_IO00, + MX6_PAD_EPDC_GDRL__GPIO2_IO01, + MX6_PAD_EPDC_GDSP__GPIO2_IO02, +}; + +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 1024, + .vl_row = 758, + .vl_pixclock = 40000000, + .vl_left_margin = 12, + .vl_right_margin = 76, + .vl_upper_margin = 4, + .vl_lower_margin = 5, + .vl_hsync = 12, + .vl_vsync = 2, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 524, + .gdsp_offs = 327, + .gdoe_offs = 0, + .gdclk_offs = 19, + .num_ce = 1, +}; + +static void setup_epdc_power(void) +{ + /* Setup epdc voltage */ + + /* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_STAT__GPIO2_IO13 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + gpio_request(IMX_GPIO_NR(2, 13), "epdc_pwrstat"); + gpio_direction_input(IMX_GPIO_NR(2, 13)); + + /* EPDC_VCOM0 - GPIO2[03] for VCOM control */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO2_IO03 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 3), "epdc_vcom0"); + gpio_direction_output(IMX_GPIO_NR(2, 3), 1); + + /* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_WAKE__GPIO2_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 14), "epdc_pwr_wake"); + gpio_direction_output(IMX_GPIO_NR(2, 14), 1); + + /* EPDC_PWRCTRL0 - GPIO2[07] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 7), "epdc_pwr_ctrl0"); + gpio_direction_output(IMX_GPIO_NR(2, 7), 1); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, + ARRAY_SIZE(epdc_enable_pads)); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, + ARRAY_SIZE(epdc_disable_pads)); +} + +static void setup_epdc(void) +{ + /*** epdc Maxim PMIC settings ***/ + + /* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_STAT__GPIO2_IO13 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_VCOM0 - GPIO2[03] for VCOM control */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO2_IO03 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_WAKE__GPIO2_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRCTRL0 - GPIO2[07] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set pixel clock rates for EPDC in clock.c */ + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 7), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 14), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 13))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(2, 3), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 14), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(2, 3), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 7), 0); +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -195,6 +416,11 @@ int board_init(void) /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_MXC_EPDC + enable_epdc_clock(); + setup_epdc(); +#endif + return 0; } diff --git a/configs/mx6sll_lpddr3_arm2_epdc_defconfig b/configs/mx6sll_lpddr3_arm2_epdc_defconfig index ad2c0d2..bf48e48 100644 --- a/configs/mx6sll_lpddr3_arm2_epdc_defconfig +++ b/configs/mx6sll_lpddr3_arm2_epdc_defconfig @@ -4,6 +4,7 @@ CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6SLL_ARM2=y CONFIG_VIDEO=y CONFIG_MXC_EPDC=y +CONFIG_LCD=y CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr3-arm2" CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr3-arm2.dtb" CONFIG_BOOTDELAY=3 diff --git a/configs/mx6sllevk_epdc_defconfig b/configs/mx6sllevk_epdc_defconfig new file mode 100644 index 0000000..16dd7cc --- /dev/null +++ b/configs/mx6sllevk_epdc_defconfig @@ -0,0 +1,45 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLLEVK=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg" +CONFIG_MXC_EPDC=y +CONFIG_LCD=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +# CONFIG_BLK is not set +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/mx6sll_arm2.h b/include/configs/mx6sll_arm2.h index 3aa1f26..b71c0b6 100644 --- a/include/configs/mx6sll_arm2.h +++ b/include/configs/mx6sll_arm2.h @@ -223,14 +223,10 @@ */ #define CONFIG_SPLASH_SCREEN #define CONFIG_CMD_BMP - #define CONFIG_LCD - #define CONFIG_SYS_CONSOLE_IS_IN_ENV -#ifdef CONFIG_MXC_EPDC #undef LCD_TEST_PATTERN #define LCD_BPP LCD_MONOCHROME #define CONFIG_WAVEFORM_BUF_SIZE 0x200000 -#endif -#endif /* CONFIG_SPLASH_SCREEN */ +#endif /* CONFIG_MXC_EPDC */ #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 67a20f7..200c21a 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -173,4 +173,19 @@ #define CONFIG_IMX_VIDEO_SKIP #endif +/* + * EPDC SPLASH SCREEN Configs + */ +#ifdef CONFIG_MXC_EPDC + /* + * Framebuffer and LCD + */ + #define CONFIG_SPLASH_SCREEN + #define CONFIG_CMD_BMP + #undef LCD_TEST_PATTERN + #define LCD_BPP LCD_MONOCHROME + + #define CONFIG_WAVEFORM_BUF_SIZE 0x200000 +#endif /* CONFIG_MXC_EPDC */ + #endif /* __CONFIG_H */ diff --git a/include/mxc_epdc_fb.h b/include/mxc_epdc_fb.h index 7594958..a32ebac 100644 --- a/include/mxc_epdc_fb.h +++ b/include/mxc_epdc_fb.h @@ -193,7 +193,7 @@ #define EPDC_PIGEON_16_0 0xC00 #define EPDC_PIGEON_16_1 0xC10 #define EPDC_PIGEON_16_2 0xC20 -#if defined(CONFIG_MX7) || defined(CONFIG_MX6ULL) +#if defined(CONFIG_MX7) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL) #define EPDC_WB_ADDR_TCE 0x010 #else #define EPDC_WB_ADDR_TCE 0xC10 @@ -306,7 +306,7 @@ enum { /* EPDC_UPD_CTRL field values */ EPDC_UPD_CTRL_USE_FIXED = 0x80000000, -#ifdef CONFIG_MX7 +#if defined(CONFIG_MX7) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL) EPDC_UPD_CTRL_LUT_SEL_MASK = 0x3F0000, #else EPDC_UPD_CTRL_LUT_SEL_MASK = 0xF0000, @@ -331,7 +331,7 @@ enum { /* EPDC_AUTOWV_LUT field values */ EPDC_AUTOWV_LUT_DATA_MASK = 0xFF0000, EPDC_AUTOWV_LUT_DATA_OFFSET = 16, -#ifdef CONFIG_MX7 +#if defined(CONFIG_MX7) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL) EPDC_AUTOWV_LUT_ADDR_MASK = 0x7, #else EPDC_AUTOWV_LUT_ADDR_MASK = 0xFF, |