diff options
72 files changed, 1082 insertions, 1129 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 394be1e..5b3c93a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -161,7 +161,7 @@ M: Masahiro Yamada <yamada.masahiro@socionext.com> S: Maintained T: git git://git.denx.de/u-boot-uniphier.git F: arch/arm/mach-uniphier/ -F: configs/ph1_*_defconfig +F: configs/uniphier_*_defconfig N: uniphier ARM ZYNQ diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 224928f..a202709 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -34,6 +34,10 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + soc { + u-boot,dm-pre-reloc; + }; }; &gmac1 { diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi new file mode 100644 index 0000000..5d4b2cf --- /dev/null +++ b/arch/arm/dts/uniphier-common32.dtsi @@ -0,0 +1,105 @@ +/* + * Device Tree Source commonly used by UniPhier ARM SoCs + * + * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/include/ "skeleton.dtsi" + +/ { + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + + extbus: extbus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart_clk>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&uart_clk>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&uart_clk>; + }; + + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 177 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&uart_clk>; + }; + + system-bus-controller@58c00000 { + compatible = "socionext,uniphier-system-bus-controller"; + reg = <0x58c00000 0x400>, <0x59800000 0x2000>; + }; + + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x104>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x104>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + pinctrl: pinctrl@5f801000 { + /* specify compatible in each SoC DTSI */ + reg = <0x5f801000 0xe00>; + }; + + nand: nand@68000000 { + compatible = "denali,denali-nand-dt"; + reg = <0x68000000 0x20>, <0x68100000 0x1000>; + reg-names = "nand_data", "denali_reg"; + }; + }; +}; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts index 9d697c1..469bd05 100644 --- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts @@ -20,8 +20,7 @@ }; chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &serial0; + stdout-path = "serial0:115200n8"; }; aliases { diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi index 5f12e10..856c207 100644 --- a/arch/arm/dts/uniphier-ph1-ld4.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi @@ -6,7 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ X11 */ -/include/ "skeleton.dtsi" +/include/ "uniphier-common32.dtsi" / { compatible = "socionext,ph1-ld4"; @@ -19,6 +19,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + next-level-cache = <&l2>; }; }; @@ -41,183 +42,117 @@ clock-frequency = <100000000>; }; }; +}; - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - extbus: extbus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - interrupts = <0 33 4>; - clocks = <&uart_clk>; - clock-frequency = <36864000>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - interrupts = <0 35 4>; - clocks = <&uart_clk>; - clock-frequency = <36864000>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - interrupts = <0 37 4>; - clocks = <&uart_clk>; - clock-frequency = <36864000>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - interrupts = <0 29 4>; - clocks = <&uart_clk>; - clock-frequency = <36864000>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - interrupts = <0 41 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - interrupts = <0 42 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(512 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - interrupts = <0 43 1>; - clocks = <&iobus_clk>; - clock-frequency = <400000>; - }; + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - interrupts = <0 44 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; - system-bus-controller-misc@59800000 { - compatible = "socionext,uniphier-system-bus-controller-misc", - "syscon"; - reg = <0x59800000 0x2000>; - }; + /* chip-internal connection for DMD */ + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&iobus_clk>; + clock-frequency = <400000>; + }; - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - interrupts = <0 80 4>; - }; + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - interrupts = <0 81 4>; - }; + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + }; - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - interrupts = <0 82 4>; - }; + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + }; - pinctrl: pinctrl@5f801000 { - compatible = "socionext,ph1-ld4-pinctrl", - "syscon"; - reg = <0x5f801000 0xe00>; - }; + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 82 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + }; +}; - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0x104>; - clocks = <&arm_timer_clk>; - }; +&serial0 { + clock-frequency = <36864000>; +}; - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0x104>; - clocks = <&arm_timer_clk>; - }; +&serial1 { + clock-frequency = <36864000>; +}; - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - }; +&serial2 { + clock-frequency = <36864000>; +}; - nand: nand@68000000 { - compatible = "denali,denali-nand-dt"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - reg-names = "nand_data", "denali_reg"; - }; - }; +&serial3 { + interrupts = <0 29 4>; + clock-frequency = <36864000>; }; -/include/ "uniphier-pinctrl.dtsi" +&pinctrl { + compatible = "socionext,ph1-ld4-pinctrl", "syscon"; +}; diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts index ccadd81..e0a972f 100644 --- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts @@ -20,8 +20,7 @@ }; chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &serial0; + stdout-path = "serial0:115200n8"; }; aliases { diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts index a825069..02e74a7 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts +++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts @@ -20,8 +20,7 @@ }; chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &serial0; + stdout-path = "serial0:115200n8"; }; aliases { diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi index a11b628..244ccf6 100644 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -6,7 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ X11 */ -/include/ "skeleton.dtsi" +/include/ "uniphier-common32.dtsi" / { compatible = "socionext,ph1-pro4"; @@ -20,12 +20,14 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + next-level-cache = <&l2>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + next-level-cache = <&l2>; }; }; @@ -48,216 +50,149 @@ clock-frequency = <50000000>; }; }; +}; - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - extbus: extbus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - interrupts = <0 33 4>; - clocks = <&uart_clk>; - clock-frequency = <73728000>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - interrupts = <0 35 4>; - clocks = <&uart_clk>; - clock-frequency = <73728000>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - interrupts = <0 37 4>; - clocks = <&uart_clk>; - clock-frequency = <73728000>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - interrupts = <0 29 4>; - clocks = <&uart_clk>; - clock-frequency = <73728000>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - interrupts = <0 41 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - interrupts = <0 42 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(768 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - interrupts = <0 43 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - interrupts = <0 44 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - /* i2c4 does not exist */ + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; + /* i2c4 does not exist */ - system-bus-controller-misc@59800000 { - compatible = "socionext,uniphier-system-bus-controller-misc", - "syscon"; - reg = <0x59800000 0x2000>; - }; + /* chip-internal connection for DMD */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; - usb2: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - interrupts = <0 80 4>; - }; + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; - usb3: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - interrupts = <0 81 4>; - }; + usb2: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + }; - usb0: usb@65a00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; - status = "disabled"; - reg = <0x65a00000 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - interrupts = <0 134 4>; - }; + usb3: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + }; - usb1: usb@65c00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; - status = "disabled"; - reg = <0x65c00000 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - interrupts = <0 137 4>; - }; + usb0: usb@65a00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65a00000 0x100>; + interrupts = <0 134 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + }; - pinctrl: pinctrl@5f801000 { - compatible = "socionext,ph1-pro4-pinctrl", - "syscon"; - reg = <0x5f801000 0xe00>; - }; + usb1: usb@65c00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65c00000 0x100>; + interrupts = <0 137 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + }; +}; - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0x304>; - clocks = <&arm_timer_clk>; - }; +&serial0 { + clock-frequency = <73728000>; +}; - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0x304>; - clocks = <&arm_timer_clk>; - }; +&serial1 { + clock-frequency = <73728000>; +}; - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - }; +&serial2 { + clock-frequency = <73728000>; +}; - nand: nand@68000000 { - compatible = "denali,denali-nand-dt"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - reg-names = "nand_data", "denali_reg"; - }; - }; +&serial3 { + clock-frequency = <73728000>; }; -/include/ "uniphier-pinctrl.dtsi" +&pinctrl { + compatible = "socionext,ph1-pro4-pinctrl", "syscon"; +}; diff --git a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts index 52dd1f9..d46e827 100644 --- a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts +++ b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts @@ -19,8 +19,7 @@ }; chosen { - bootargs = "console=ttyS1,115200"; - stdout-path = &serial1; + stdout-path = "serial1:115200n8"; }; aliases { diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi index 6f19bf8..0049106 100644 --- a/arch/arm/dts/uniphier-ph1-pro5.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi @@ -6,7 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ X11 */ -/include/ "skeleton.dtsi" +/include/ "uniphier-common32.dtsi" / { compatible = "socionext,ph1-pro5"; @@ -20,12 +20,14 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + next-level-cache = <&l2>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + next-level-cache = <&l2>; }; }; @@ -48,187 +50,143 @@ clock-frequency = <50000000>; }; }; +}; - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - extbus: extbus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - interrupts = <0 33 4>; - clocks = <&uart_clk>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - interrupts = <0 35 4>; - clocks = <&uart_clk>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - interrupts = <0 37 4>; - clocks = <&uart_clk>; - }; +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; + interrupts = <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <(2 * 1024 * 1024)>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + next-level-cache = <&l3>; + }; - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - interrupts = <0 177 4>; - clocks = <&uart_clk>; - }; + l3: l3-cache@500c8000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(2 * 1024 * 1024)>; + cache-sets = <512>; + cache-line-size = <256>; + cache-level = <3>; + }; - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - interrupts = <0 41 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - interrupts = <0 42 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - interrupts = <0 43 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - interrupts = <0 44 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - /* i2c4 does not exist */ - - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; + /* i2c4 does not exist */ - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; + /* chip-internal connection for DMD */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; - system-bus-controller-misc@59800000 { - compatible = "socionext,uniphier-system-bus-controller-misc", - "syscon"; - reg = <0x59800000 0x2000>; - }; + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; - pinctrl: pinctrl@5f801000 { - compatible = "socionext,ph1-pro5-pinctrl", "syscon"; - reg = <0x5f801000 0xe00>; - }; + usb0: usb@65a00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65a00000 0x100>; + interrupts = <0 134 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + }; - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0x304>; - clocks = <&arm_timer_clk>; - }; + usb1: usb@65c00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65c00000 0x100>; + interrupts = <0 137 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; + }; +}; - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0x304>; - clocks = <&arm_timer_clk>; - }; +&serial0 { + clock-frequency = <73728000>; +}; - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - }; +&serial1 { + clock-frequency = <73728000>; +}; - usb0: usb@65a00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; - status = "disabled"; - reg = <0x65a00000 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - interrupts = <0 134 4>; - }; +&serial2 { + clock-frequency = <73728000>; +}; - usb1: usb@65c00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; - status = "disabled"; - reg = <0x65c00000 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; - interrupts = <0 137 4>; - }; - }; +&serial3 { + clock-frequency = <73728000>; }; -/include/ "uniphier-pinctrl.dtsi" +&pinctrl { + compatible = "socionext,ph1-pro5-pinctrl", "syscon"; +}; diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts index c760b6d..1f3aee9 100644 --- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts +++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts @@ -21,8 +21,7 @@ }; chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &serial0; + stdout-path = "serial0:115200n8"; }; aliases { diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts index 2cfcaff..b58bf07 100644 --- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts +++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts @@ -20,8 +20,7 @@ }; chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &serial0; + stdout-path = "serial0:115200n8"; }; aliases { diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi index 7d06f7e..cb28bc4 100644 --- a/arch/arm/dts/uniphier-ph1-sld8.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi @@ -6,7 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ X11 */ -/include/ "skeleton.dtsi" +/include/ "uniphier-common32.dtsi" / { compatible = "socionext,ph1-sld8"; @@ -19,6 +19,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + next-level-cache = <&l2>; }; }; @@ -41,183 +42,117 @@ clock-frequency = <100000000>; }; }; +}; - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - extbus: extbus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - interrupts = <0 33 4>; - clocks = <&uart_clk>; - clock-frequency = <80000000>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - interrupts = <0 35 4>; - clocks = <&uart_clk>; - clock-frequency = <80000000>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - interrupts = <0 37 4>; - clocks = <&uart_clk>; - clock-frequency = <80000000>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - interrupts = <0 29 4>; - clocks = <&uart_clk>; - clock-frequency = <80000000>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - interrupts = <0 41 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - interrupts = <0 42 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(256 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - interrupts = <0 43 1>; - clocks = <&iobus_clk>; - clock-frequency = <400000>; - }; + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - interrupts = <0 44 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; - system-bus-controller-misc@59800000 { - compatible = "socionext,uniphier-system-bus-controller-misc", - "syscon"; - reg = <0x59800000 0x2000>; - }; + /* chip-internal connection for DMD */ + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&iobus_clk>; + clock-frequency = <400000>; + }; - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - interrupts = <0 80 4>; - }; + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - interrupts = <0 81 4>; - }; + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + }; - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - interrupts = <0 82 4>; - }; + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + }; - pinctrl: pinctrl@5f801000 { - compatible = "socionext,ph1-sld8-pinctrl", - "syscon"; - reg = <0x5f801000 0xe00>; - }; + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 82 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + }; +}; - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0x104>; - clocks = <&arm_timer_clk>; - }; +&serial0 { + clock-frequency = <80000000>; +}; - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0x104>; - clocks = <&arm_timer_clk>; - }; +&serial1 { + clock-frequency = <80000000>; +}; - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - }; +&serial2 { + clock-frequency = <80000000>; +}; - nand: nand@68000000 { - compatible = "denali,denali-nand-dt"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - reg-names = "nand_data", "denali_reg"; - }; - }; +&serial3 { + interrupts = <0 29 4>; + clock-frequency = <80000000>; }; -/include/ "uniphier-pinctrl.dtsi" +&pinctrl { + compatible = "socionext,ph1-sld8-pinctrl", "syscon"; +}; diff --git a/arch/arm/dts/uniphier-pinctrl.dtsi b/arch/arm/dts/uniphier-pinctrl.dtsi index b584213..b1691d0 100644 --- a/arch/arm/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/dts/uniphier-pinctrl.dtsi @@ -7,6 +7,11 @@ */ &pinctrl { + pinctrl_emmc: emmc_grp { + groups = "emmc", "emmc_dat8"; + function = "emmc"; + }; + pinctrl_i2c0: i2c0_grp { groups = "i2c0"; function = "i2c0"; @@ -27,6 +32,16 @@ function = "i2c3"; }; + pinctrl_sd: sd_grp { + groups = "sd"; + function = "sd"; + }; + + pinctrl_sd1: sd1_grp { + groups = "sd1"; + function = "sd1"; + }; + pinctrl_uart0: uart0_grp { groups = "uart0"; function = "uart0"; diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts index d0af8ac..a49215e 100644 --- a/arch/arm/dts/uniphier-proxstream2-gentil.dts +++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts @@ -19,8 +19,7 @@ }; chosen { - bootargs = "console=ttyS2,115200"; - stdout-path = &serial2; + stdout-path = "serial2:115200n8"; }; aliases { diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts index 92d7404..63bd363 100644 --- a/arch/arm/dts/uniphier-proxstream2-vodka.dts +++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts @@ -19,8 +19,7 @@ }; chosen { - bootargs = "console=ttyS2,115200"; - stdout-path = &serial2; + stdout-path = "serial2:115200n8"; }; aliases { diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi index cd0cf4e..3ba6a4a 100644 --- a/arch/arm/dts/uniphier-proxstream2.dtsi +++ b/arch/arm/dts/uniphier-proxstream2.dtsi @@ -6,7 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ X11 */ -/include/ "skeleton.dtsi" +/include/ "uniphier-common32.dtsi" / { compatible = "socionext,proxstream2"; @@ -20,24 +20,28 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + next-level-cache = <&l2>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + next-level-cache = <&l2>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; + next-level-cache = <&l2>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; + next-level-cache = <&l2>; }; }; @@ -60,200 +64,140 @@ clock-frequency = <50000000>; }; }; +}; - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - extbus: extbus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - interrupts = <0 33 4>; - clocks = <&uart_clk>; - clock-frequency = <88900000>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - interrupts = <0 35 4>; - clocks = <&uart_clk>; - clock-frequency = <88900000>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - interrupts = <0 37 4>; - clocks = <&uart_clk>; - clock-frequency = <88900000>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - interrupts = <0 177 4>; - clocks = <&uart_clk>; - clock-frequency = <88900000>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - interrupts = <0 41 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <(1280 * 1024)>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + }; - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - interrupts = <0 42 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - interrupts = <0 43 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - interrupts = <0 44 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + interrupts = <0 43 4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - /* chip-internal connection for DMD */ - i2c4: i2c@58784000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58784000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; - /* chip-internal connection for STM */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; + /* chip-internal connection for DMD */ + i2c4: i2c@58784000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58784000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 45 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; + /* chip-internal connection for STM */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; - system-bus-controller-misc@59800000 { - compatible = "socionext,uniphier-system-bus-controller-misc", - "syscon"; - reg = <0x59800000 0x2000>; - }; + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; - pinctrl: pinctrl@5f801000 { - compatible = "socionext,proxstream2-pinctrl", "syscon"; - reg = <0x5f801000 0xe00>; - }; + usb0: usb@65a00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65a00000 0x100>; + interrupts = <0 134 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; + }; - timer@60000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x60000200 0x20>; - interrupts = <1 11 0xf04>; - clocks = <&arm_timer_clk>; - }; + usb1: usb@65c00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65c00000 0x100>; + interrupts = <0 137 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; + }; +}; - timer@60000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x60000600 0x20>; - interrupts = <1 13 0xf04>; - clocks = <&arm_timer_clk>; - }; +&serial0 { + clock-frequency = <88900000>; +}; - intc: interrupt-controller@60001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x60001000 0x1000>, - <0x60000100 0x100>; - }; +&serial1 { + clock-frequency = <88900000>; +}; - usb0: usb@65a00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; - status = "disabled"; - reg = <0x65a00000 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; - interrupts = <0 134 4>; - }; +&serial2 { + clock-frequency = <88900000>; +}; - usb1: usb@65c00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; - status = "disabled"; - reg = <0x65c00000 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; - interrupts = <0 137 4>; - }; - }; +&serial3 { + clock-frequency = <88900000>; }; -/include/ "uniphier-pinctrl.dtsi" +&pinctrl { + compatible = "socionext,proxstream2-pinctrl", "syscon"; +}; diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index e50fbd8..2f070f2 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -65,12 +65,13 @@ struct socfpga_reset_manager { */ #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_NAND RSTMGR_DEFINE(1, 4) +#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) #define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) -#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) #define RSTMGR_DMA RSTMGR_DEFINE(1, 28) #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index b110f5b..9b43b92 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -54,14 +54,23 @@ void enable_caches(void) void v7_outer_cache_enable(void) { - /* disable the L2 cache */ - writel(0, &pl310->pl310_ctrl); + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); /* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | L310_AUX_CTRL_INST_PREFETCH_MASK | L310_SHARED_ATT_OVERRIDE_ENABLE); + + /* Enable the L2 cache */ + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} + +void v7_outer_cache_disable(void) +{ + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } /* @@ -350,6 +359,10 @@ int arch_early_init_r(void) socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); #endif +#ifdef CONFIG_NAND_DENALI + socfpga_per_reset(SOCFPGA_RESET(NAND), 0); +#endif + return 0; } diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index 775a827..98c16a0 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -40,6 +40,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_RAM; case 0x2: /* NAND Flash (1.8V) */ case 0x3: /* NAND Flash (3.0V) */ + socfpga_per_reset(SOCFPGA_RESET(NAND), 0); return BOOT_DEVICE_NAND; case 0x4: /* SD/MMC External Transceiver (1.8V) */ case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index b597a13..5b19f93 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -6,9 +6,8 @@ ifdef CONFIG_SPL_BUILD obj-y += lowlevel_init.o obj-y += init_page_table.o -obj-y += boards.o -obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ umc/ ddrphy/ +obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ dram/ obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/ obj-$(CONFIG_DEBUG_LL) += debug_ll.o @@ -33,6 +32,7 @@ obj-y += pinctrl/ clk/ endif obj-y += timer.o +obj-y += boards.o obj-y += soc_info.o obj-y += boot-mode/ diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index a7530eb..c2a3261 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -6,6 +6,7 @@ #include <common.h> #include <spl.h> +#include <libfdt.h> #include <nand.h> #include <linux/io.h> #include <../drivers/mtd/nand/denali.h> @@ -25,6 +26,38 @@ static void nand_denali_wp_disable(void) #endif } +struct uniphier_fdt_file { + const char *compatible; + const char *file_name; +}; + +static const struct uniphier_fdt_file uniphier_fdt_files[] = { + { "socionext,ph1-ld4-ref", "uniphier-ph1-ld4-ref.dtb", }, + { "socionext,ph1-ld6b-ref", "uniphier-ph1-ld6b-ref.dtb", }, + { "socionext,ph1-ld10-ref", "uniphier-ph1-ld10-ref.dtb", }, + { "socionext,ph1-pro4-ref", "uniphier-ph1-pro4-ref.dtb", }, + { "socionext,ph1-pro5-4kbox", "uniphier-ph1-pro5-4kbox.dtb", }, + { "socionext,ph1-sld3-ref", "uniphier-ph1-sld3-ref.dtb", }, + { "socionext,ph1-sld8-ref", "uniphier-ph1-sld8-ref.dtb", }, + { "socionext,proxstream2-gentil", "uniphier-proxstream2-gentil.dtb", }, + { "socionext,proxstream2-vodka", "uniphier-proxstream2-vodka.dtb", }, +}; + +static void uniphier_set_fdt_file(void) +{ + DECLARE_GLOBAL_DATA_PTR; + int i; + + /* lookup DTB file name based on the compatible string */ + for (i = 0; i < ARRAY_SIZE(uniphier_fdt_files); i++) { + if (!fdt_node_check_compatible(gd->fdt_blob, 0, + uniphier_fdt_files[i].compatible)) { + setenv("fdt_file", uniphier_fdt_files[i].file_name); + return; + } + } +} + int board_late_init(void) { puts("MODE: "); @@ -48,5 +81,7 @@ int board_late_init(void) return -1; } + uniphier_set_fdt_file(); + return 0; } diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index 812c58f..d075a11 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -4,10 +4,13 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <common.h> #include <libfdt.h> #include <linux/kernel.h> #include <mach/init.h> +DECLARE_GLOBAL_DATA_PTR; + #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) static const struct uniphier_board_data ph1_sld3_data = { .dram_ch0_base = 0x80000000, @@ -71,8 +74,7 @@ static const struct uniphier_board_data ph1_pro5_data = { }; #endif -#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \ - defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B) +#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) static const struct uniphier_board_data proxstream2_data = { .dram_ch0_base = 0x80000000, .dram_ch0_size = 0x40000000, @@ -83,6 +85,21 @@ static const struct uniphier_board_data proxstream2_data = { .dram_ch2_base = 0xe0000000, .dram_ch2_size = 0x20000000, .dram_ch2_width = 16, + .dram_freq = 2133, +}; +#endif + +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B) +static const struct uniphier_board_data ph1_ld6b_data = { + .dram_ch0_base = 0x80000000, + .dram_ch0_size = 0x40000000, + .dram_ch0_width = 32, + .dram_ch1_base = 0xc0000000, + .dram_ch1_size = 0x20000000, + .dram_ch1_width = 32, + .dram_ch2_base = 0xe0000000, + .dram_ch2_size = 0x20000000, + .dram_ch2_width = 16, .dram_freq = 1866, }; #endif @@ -112,16 +129,16 @@ static const struct uniphier_board_id uniphier_boards[] = { { "socionext,proxstream2", &proxstream2_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B) - { "socionext,ph1-ld6b", &proxstream2_data, }, + { "socionext,ph1-ld6b", &ph1_ld6b_data, }, #endif }; -const struct uniphier_board_data *uniphier_get_board_param(const void *fdt) +const struct uniphier_board_data *uniphier_get_board_param(void) { int i; for (i = 0; i < ARRAY_SIZE(uniphier_boards); i++) { - if (!fdt_node_check_compatible(fdt, 0, + if (!fdt_node_check_compatible(gd->fdt_blob, 0, uniphier_boards[i].compatible)) return uniphier_boards[i].param; } diff --git a/arch/arm/mach-uniphier/cmd_ddrphy.c b/arch/arm/mach-uniphier/cmd_ddrphy.c index dbbefd4..f9b79ab 100644 --- a/arch/arm/mach-uniphier/cmd_ddrphy.c +++ b/arch/arm/mach-uniphier/cmd_ddrphy.c @@ -50,7 +50,7 @@ static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx) printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff); } -void wbdl_dump(void) +static void wbdl_dump(void) { printf("\n--- Write Bit Delay Line ---\n"); printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n"); @@ -68,7 +68,7 @@ static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx) printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff); } -void rbdl_dump(void) +static void rbdl_dump(void) { printf("\n--- Read Bit Delay Line ---\n"); printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n"); @@ -91,7 +91,7 @@ static void __wld_dump(struct ddrphy_datx8 __iomem *dx) } } -void wld_dump(void) +static void wld_dump(void) { printf("\n--- Write Leveling Delay ---\n"); printf(" Rank0 Rank1 Rank2 Rank3\n"); @@ -113,7 +113,7 @@ static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx) } } -void dqsgd_dump(void) +static void dqsgd_dump(void) { printf("\n--- DQS Gating Delay ---\n"); printf(" Rank0 Rank1 Rank2 Rank3\n"); @@ -129,7 +129,7 @@ static void __mdl_dump(struct ddrphy_datx8 __iomem *dx) printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff); } -void mdl_dump(void) +static void mdl_dump(void) { printf("\n--- Master Delay Line ---\n"); printf(" IPRD TPRD MDLD\n"); @@ -141,7 +141,7 @@ void mdl_dump(void) { u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \ p - (u32 *)phy, #x, p, readl(p)); } -void reg_dump(void) +static void reg_dump(void) { int ch, p; struct ddrphy __iomem *phy; diff --git a/arch/arm/mach-uniphier/cpu_info.c b/arch/arm/mach-uniphier/cpu_info.c index 5d9ed84..935b209 100644 --- a/arch/arm/mach-uniphier/cpu_info.c +++ b/arch/arm/mach-uniphier/cpu_info.c @@ -43,13 +43,18 @@ int print_cpuinfo(void) case 0x2F: puts("PH1-LD6b (MN2WS0320)"); break; + case 0x31: + puts("PH1-sLD11 ()"); + break; + case 0x32: + puts("PH1-LD10 ()"); + break; default: printf("Unknown Processor ID (0x%x)\n", revision); return -1; } - if (model > 1) - printf(" model %d", model); + printf(" model %d", model); printf(" (rev. %d)\n", rev); diff --git a/arch/arm/mach-uniphier/ddrphy/Makefile b/arch/arm/mach-uniphier/ddrphy/Makefile deleted file mode 100644 index d0f4bd3..0000000 --- a/arch/arm/mach-uniphier/ddrphy/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += ddrphy-training.o ddrphy-ph1-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += ddrphy-training.o ddrphy-ph1-pro4.o -obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += ddrphy-training.o ddrphy-ph1-sld8.o diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile new file mode 100644 index 0000000..d3a767b --- /dev/null +++ b/arch/arm/mach-uniphier/dram/Makefile @@ -0,0 +1,10 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o \ + ddrphy-training.o ddrphy-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o \ + ddrphy-training.o ddrphy-ph1-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o \ + ddrphy-training.o ddrphy-ph1-sld8.o diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c index 991d929..991d929 100644 --- a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c index bc47ba3..bc47ba3 100644 --- a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c index 39024a0..39024a0 100644 --- a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c b/arch/arm/mach-uniphier/dram/ddrphy-training.c index a98b814..4852f2d 100644 --- a/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-training.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <linux/err.h> #include <linux/io.h> #include <mach/ddrphy-regs.h> @@ -32,8 +33,8 @@ void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank) /* Use Multi-Purpose Register for DQS gate training */ tmp |= DTCR_DTMPR; /* Specify the rank enabled for data-training */ - tmp &= ~DTCR_RNKEN_MASK; - tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK; + tmp &= ~DTCR_RANKEN_MASK; + tmp |= (1 << (DTCR_RANKEN_SHIFT + rank)) & DTCR_RANKEN_MASK; writel(tmp, p); } @@ -44,7 +45,7 @@ struct ddrphy_init_sequence { u32 err_flag; }; -static struct ddrphy_init_sequence init_sequence[] = { +static const struct ddrphy_init_sequence init_sequence[] = { { "DRAM Initialization", PIR_DRAMRST | PIR_DRAMINIT, @@ -117,7 +118,7 @@ int ddrphy_training(struct ddrphy __iomem *phy) if (--timeout < 0) { printf("%s: error: timeout during DDR training\n", __func__); - return -1; + return -ETIMEDOUT; } udelay(1); pgsr0 = readl(&phy->pgsr[0]); @@ -127,7 +128,7 @@ int ddrphy_training(struct ddrphy __iomem *phy) if (pgsr0 & init_sequence[i].err_flag) { printf("%s: error: %s failed\n", __func__, init_sequence[i].description); - return -1; + return -EIO; } } diff --git a/arch/arm/mach-uniphier/umc/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c index 8124685..8124685 100644 --- a/arch/arm/mach-uniphier/umc/umc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c diff --git a/arch/arm/mach-uniphier/umc/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index 8c9f057..8c9f057 100644 --- a/arch/arm/mach-uniphier/umc/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c diff --git a/arch/arm/mach-uniphier/umc/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index bc60a34..bc60a34 100644 --- a/arch/arm/mach-uniphier/umc/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h index adcc972..03aedc2 100644 --- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h @@ -9,6 +9,7 @@ #ifndef ARCH_DDRPHY_REGS_H #define ARCH_DDRPHY_REGS_H +#include <linux/bitops.h> #include <linux/compiler.h> #ifndef __ASSEMBLY__ @@ -79,52 +80,52 @@ struct ddrphy { #endif /* __ASSEMBLY__ */ -#define PIR_INIT (1 << 0) /* Initialization Trigger */ -#define PIR_ZCAL (1 << 1) /* Impedance Calibration */ -#define PIR_PLLINIT (1 << 4) /* PLL Initialization */ -#define PIR_DCAL (1 << 5) /* DDL Calibration */ -#define PIR_PHYRST (1 << 6) /* PHY Reset */ -#define PIR_DRAMRST (1 << 7) /* DRAM Reset */ -#define PIR_DRAMINIT (1 << 8) /* DRAM Initialization */ -#define PIR_WL (1 << 9) /* Write Leveling */ -#define PIR_QSGATE (1 << 10) /* Read DQS Gate Training */ -#define PIR_WLADJ (1 << 11) /* Write Leveling Adjust */ -#define PIR_RDDSKW (1 << 12) /* Read Data Bit Deskew */ -#define PIR_WRDSKW (1 << 13) /* Write Data Bit Deskew */ -#define PIR_RDEYE (1 << 14) /* Read Data Eye Training */ -#define PIR_WREYE (1 << 15) /* Write Data Eye Training */ -#define PIR_LOCKBYP (1 << 28) /* PLL Lock Bypass */ -#define PIR_DCALBYP (1 << 29) /* DDL Calibration Bypass */ -#define PIR_ZCALBYP (1 << 30) /* Impedance Calib Bypass */ -#define PIR_INITBYP (1 << 31) /* Initialization Bypass */ - -#define PGSR0_IDONE (1 << 0) /* Initialization Done */ -#define PGSR0_PLDONE (1 << 1) /* PLL Lock Done */ -#define PGSR0_DCDONE (1 << 2) /* DDL Calibration Done */ -#define PGSR0_ZCDONE (1 << 3) /* Impedance Calibration Done */ -#define PGSR0_DIDONE (1 << 4) /* DRAM Initialization Done */ -#define PGSR0_WLDONE (1 << 5) /* Write Leveling Done */ -#define PGSR0_QSGDONE (1 << 6) /* DQS Gate Training Done */ -#define PGSR0_WLADONE (1 << 7) /* Write Leveling Adjust Done */ -#define PGSR0_RDDONE (1 << 8) /* Read Bit Deskew Done */ -#define PGSR0_WDDONE (1 << 9) /* Write Bit Deskew Done */ -#define PGSR0_REDONE (1 << 10) /* Read Eye Training Done */ -#define PGSR0_WEDONE (1 << 11) /* Write Eye Training Done */ -#define PGSR0_IERR (1 << 16) /* Initialization Error */ -#define PGSR0_PLERR (1 << 17) /* PLL Lock Error */ -#define PGSR0_DCERR (1 << 18) /* DDL Calibration Error */ -#define PGSR0_ZCERR (1 << 19) /* Impedance Calib Error */ -#define PGSR0_DIERR (1 << 20) /* DRAM Initialization Error */ -#define PGSR0_WLERR (1 << 21) /* Write Leveling Error */ -#define PGSR0_QSGERR (1 << 22) /* DQS Gate Training Error */ -#define PGSR0_WLAERR (1 << 23) /* Write Leveling Adj Error */ -#define PGSR0_RDERR (1 << 24) /* Read Bit Deskew Error */ -#define PGSR0_WDERR (1 << 25) /* Write Bit Deskew Error */ -#define PGSR0_REERR (1 << 26) /* Read Eye Training Error */ -#define PGSR0_WEERR (1 << 27) /* Write Eye Training Error */ +#define PIR_INIT BIT(0) /* Initialization Trigger */ +#define PIR_ZCAL BIT(1) /* Impedance Calibration */ +#define PIR_PLLINIT BIT(4) /* PLL Initialization */ +#define PIR_DCAL BIT(5) /* DDL Calibration */ +#define PIR_PHYRST BIT(6) /* PHY Reset */ +#define PIR_DRAMRST BIT(7) /* DRAM Reset */ +#define PIR_DRAMINIT BIT(8) /* DRAM Initialization */ +#define PIR_WL BIT(9) /* Write Leveling */ +#define PIR_QSGATE BIT(10) /* Read DQS Gate Training */ +#define PIR_WLADJ BIT(11) /* Write Leveling Adjust */ +#define PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */ +#define PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */ +#define PIR_RDEYE BIT(14) /* Read Data Eye Training */ +#define PIR_WREYE BIT(15) /* Write Data Eye Training */ +#define PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */ +#define PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */ +#define PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */ +#define PIR_INITBYP BIT(31) /* Initialization Bypass */ + +#define PGSR0_IDONE BIT(0) /* Initialization Done */ +#define PGSR0_PLDONE BIT(1) /* PLL Lock Done */ +#define PGSR0_DCDONE BIT(2) /* DDL Calibration Done */ +#define PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */ +#define PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */ +#define PGSR0_WLDONE BIT(5) /* Write Leveling Done */ +#define PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */ +#define PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */ +#define PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */ +#define PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */ +#define PGSR0_REDONE BIT(10) /* Read Eye Training Done */ +#define PGSR0_WEDONE BIT(11) /* Write Eye Training Done */ +#define PGSR0_IERR BIT(16) /* Initialization Error */ +#define PGSR0_PLERR BIT(17) /* PLL Lock Error */ +#define PGSR0_DCERR BIT(18) /* DDL Calibration Error */ +#define PGSR0_ZCERR BIT(19) /* Impedance Calib Error */ +#define PGSR0_DIERR BIT(20) /* DRAM Initialization Error */ +#define PGSR0_WLERR BIT(21) /* Write Leveling Error */ +#define PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */ +#define PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */ +#define PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */ +#define PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */ +#define PGSR0_REERR BIT(26) /* Read Eye Training Error */ +#define PGSR0_WEERR BIT(27) /* Write Eye Training Error */ #define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/ #define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT)) -#define PGSR0_APLOCK (1 << 31) /* AC PLL Lock */ +#define PGSR0_APLOCK BIT(31) /* AC PLL Lock */ #define DXCCR_DQSRES_OPEN (0 << 5) #define DXCCR_DQSRES_688_OHM (1 << 5) @@ -146,9 +147,9 @@ struct ddrphy { #define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */ #define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT)) -#define DTCR_DTMPR (1 << 6) /* Data Training using MPR */ -#define DTCR_RNKEN_SHIFT 24 /* Rank Enable */ -#define DTCR_RNKEN_MASK (0xf << (DTCR_RNKEN_SHIFT)) +#define DTCR_DTMPR BIT(6) /* Data Training using MPR */ +#define DTCR_RANKEN_SHIFT 24 /* Rank Enable */ +#define DTCR_RANKEN_MASK (0xf << (DTCR_RANKEN_SHIFT)) #define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */ #define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT)) diff --git a/arch/arm/mach-uniphier/include/mach/init.h b/arch/arm/mach-uniphier/include/mach/init.h index 5108edd..27ae27d 100644 --- a/arch/arm/mach-uniphier/include/mach/init.h +++ b/arch/arm/mach-uniphier/include/mach/init.h @@ -20,7 +20,7 @@ struct uniphier_board_data { unsigned int dram_freq; }; -const struct uniphier_board_data *uniphier_get_board_param(const void *fdt); +const struct uniphier_board_data *uniphier_get_board_param(void); int ph1_sld3_init(const struct uniphier_board_data *bd); int ph1_ld4_init(const struct uniphier_board_data *bd); diff --git a/arch/arm/mach-uniphier/include/mach/soc_info.h b/arch/arm/mach-uniphier/include/mach/soc_info.h index 623e7ef..3cfd1e9 100644 --- a/arch/arm/mach-uniphier/include/mach/soc_info.h +++ b/arch/arm/mach-uniphier/include/mach/soc_info.h @@ -15,6 +15,8 @@ enum uniphier_soc_id { SOC_UNIPHIER_PH1_PRO5, SOC_UNIPHIER_PROXSTREAM2, SOC_UNIPHIER_PH1_LD6B, + SOC_UNIPHIER_PH1_SLD11, + SOC_UNIPHIER_PH1_LD10, SOC_UNIPHIER_UNKNOWN, }; @@ -25,7 +27,9 @@ enum uniphier_soc_id { IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + \ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO5) + \ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) + \ - IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B) + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B) + \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD11) + \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD10) #define UNIPHIER_MULTI_SOC ((UNIPHIER_NR_ENABLED_SOCS) > 1) @@ -55,9 +59,18 @@ static inline enum uniphier_soc_id uniphier_get_soc_type(void) #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B) return SOC_UNIPHIER_PH1_LD6B; #endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD11) + return SOC_UNIPHIER_PH1_SLD11; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD10) + return SOC_UNIPHIER_PH1_LD10; +#endif return SOC_UNIPHIER_UNKNOWN; } #endif +int uniphier_get_soc_model(void); +int uniphier_get_soc_revision(void); + #endif /* __MACH_SOC_INFO_H__ */ diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c index bbfc8e5..eda169e 100644 --- a/arch/arm/mach-uniphier/init/init.c +++ b/arch/arm/mach-uniphier/init/init.c @@ -9,13 +9,11 @@ #include <mach/init.h> #include <mach/soc_info.h> -DECLARE_GLOBAL_DATA_PTR; - void spl_board_init(void) { const struct uniphier_board_data *param; - param = uniphier_get_board_param(gd->fdt_blob); + param = uniphier_get_board_param(); if (!param) hang(); diff --git a/arch/arm/mach-uniphier/soc_info.c b/arch/arm/mach-uniphier/soc_info.c index 3e8e7f4..6cdeae6 100644 --- a/arch/arm/mach-uniphier/soc_info.c +++ b/arch/arm/mach-uniphier/soc_info.c @@ -51,6 +51,16 @@ enum uniphier_soc_id uniphier_get_soc_type(void) ret = SOC_UNIPHIER_PH1_LD6B; break; #endif +#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD11 + case 0x31: + ret = SOC_UNIPHIER_PH1_SLD11; + break; +#endif +#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD10 + case 0x32: + ret = SOC_UNIPHIER_PH1_LD10; + break; +#endif default: ret = SOC_UNIPHIER_UNKNOWN; break; @@ -59,3 +69,15 @@ enum uniphier_soc_id uniphier_get_soc_type(void) return ret; } #endif + +int uniphier_get_soc_model(void) +{ + return (readl(SG_REVISION) & SG_REVISION_MODEL_MASK) >> + SG_REVISION_MODEL_SHIFT; +} + +int uniphier_get_soc_revision(void) +{ + return (readl(SG_REVISION) & SG_REVISION_REV_MASK) >> + SG_REVISION_REV_SHIFT; +} diff --git a/arch/arm/mach-uniphier/umc/Makefile b/arch/arm/mach-uniphier/umc/Makefile deleted file mode 100644 index 89b2dec..0000000 --- a/arch/arm/mach-uniphier/umc/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o -obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 33cf1fd..f1e6d2b 100644 --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -9,19 +9,19 @@ const u8 sys_mgr_init_table[] = { 3, /* EMACIO0 */ - 3, /* EMACIO1 */ - 3, /* EMACIO2 */ - 3, /* EMACIO3 */ - 3, /* EMACIO4 */ - 3, /* EMACIO5 */ - 3, /* EMACIO6 */ - 3, /* EMACIO7 */ - 3, /* EMACIO8 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ 3, /* EMACIO9 */ - 3, /* EMACIO10 */ - 3, /* EMACIO11 */ - 3, /* EMACIO12 */ - 3, /* EMACIO13 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ 0, /* EMACIO14 */ 0, /* EMACIO15 */ 0, /* EMACIO16 */ @@ -55,8 +55,8 @@ const u8 sys_mgr_init_table[] = { 0, /* GENERALIO12 */ 2, /* GENERALIO13 */ 2, /* GENERALIO14 */ - 0, /* GENERALIO15 */ - 0, /* GENERALIO16 */ + 3, /* GENERALIO15 */ + 3, /* GENERALIO16 */ 2, /* GENERALIO17 */ 2, /* GENERALIO18 */ 0, /* GENERALIO19 */ @@ -72,27 +72,27 @@ const u8 sys_mgr_init_table[] = { 0, /* GENERALIO29 */ 0, /* GENERALIO30 */ 0, /* GENERALIO31 */ - 0, /* MIXED1IO0 */ - 1, /* MIXED1IO1 */ - 1, /* MIXED1IO2 */ - 1, /* MIXED1IO3 */ - 1, /* MIXED1IO4 */ - 0, /* MIXED1IO5 */ - 0, /* MIXED1IO6 */ - 0, /* MIXED1IO7 */ - 1, /* MIXED1IO8 */ - 1, /* MIXED1IO9 */ - 1, /* MIXED1IO10 */ - 1, /* MIXED1IO11 */ - 0, /* MIXED1IO12 */ - 0, /* MIXED1IO13 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ 0, /* MIXED1IO14 */ - 1, /* MIXED1IO15 */ - 1, /* MIXED1IO16 */ - 1, /* MIXED1IO17 */ - 1, /* MIXED1IO18 */ - 0, /* MIXED1IO19 */ - 0, /* MIXED1IO20 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ 0, /* MIXED1IO21 */ 0, /* MIXED2IO0 */ 0, /* MIXED2IO1 */ diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index 3d621ed..4abd2e0 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -14,7 +14,7 @@ #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 @@ -31,7 +31,7 @@ #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79 #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index fc0918f..858a9ca 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -48,9 +48,6 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_ETH_DESIGNWARE) u32 interface = PHY_INTERFACE_MODE_MII; -#if defined(CONFIG_DW_AUTONEG) - interface = PHY_INTERFACE_MODE_GMII; -#endif if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig deleted file mode 100644 index 4474ec3..0000000 --- a/configs/ph1_sld8_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_UNIPHIER=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_ARCH_UNIPHIER_PH1_SLD8=y -CONFIG_MICRO_SUPPORT_CARD=y -CONFIG_SYS_TEXT_BASE=0x84000000 -CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref" -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_ENV_EXISTS is not set -CONFIG_CMD_NAND=y -CONFIG_CMD_I2C=y -CONFIG_CMD_USB=y -# CONFIG_CMD_FPGA is not set -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_PING=y -CONFIG_CMD_TIME=y -# CONFIG_CMD_MISC is not set -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_SIMPLE_BUS=y -CONFIG_NAND_DENALI=y -CONFIG_SYS_NAND_DENALI_64BIT=y -CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 -CONFIG_SPL_NAND_DENALI=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_UNIPHIER_SERIAL=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 10eb91d..68d12df 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_STACK_R=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y +CONFIG_SPL_SIMPLE_BUS=y CONFIG_DWAPB_GPIO=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y @@ -23,3 +24,4 @@ CONFIG_DESIGNWARE_SPI=y CONFIG_DM_MMC=y CONFIG_USB=y CONFIG_DM_USB=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 864358c..accee92 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_STACK_R=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y +CONFIG_SPL_SIMPLE_BUS=y CONFIG_DWAPB_GPIO=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y @@ -23,3 +24,4 @@ CONFIG_DESIGNWARE_SPI=y CONFIG_DM_MMC=y CONFIG_USB=y CONFIG_DM_USB=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 2c75bda..3d98a63 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -17,3 +17,4 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_DM_MMC=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set diff --git a/configs/ph1_ld4_defconfig b/configs/uniphier_ld4_sld8_defconfig index 2ddd1eb..ee3cbad 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ARCH_UNIPHIER_PH1_LD4=y +CONFIG_ARCH_UNIPHIER_PH1_SLD8=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref" diff --git a/configs/ph1_pro4_defconfig b/configs/uniphier_pro4_defconfig index 2361db6..2361db6 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/uniphier_pro4_defconfig diff --git a/configs/ph1_pro5_defconfig b/configs/uniphier_pro5_defconfig index be0d7b5..be0d7b5 100644 --- a/configs/ph1_pro5_defconfig +++ b/configs/uniphier_pro5_defconfig diff --git a/configs/ph1_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig index bbcb344..f8cb794 100644 --- a/configs/ph1_ld6b_defconfig +++ b/configs/uniphier_pxs2_ld6b_defconfig @@ -1,10 +1,11 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ARCH_UNIPHIER_PROXSTREAM2=y CONFIG_ARCH_UNIPHIER_PH1_LD6B=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 -CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld6b-ref" +CONFIG_DEFAULT_DEVICE_TREE="uniphier-proxstream2-vodka" CONFIG_HUSH_PARSER=y # CONFIG_CMD_XIMG is not set # CONFIG_CMD_ENV_EXISTS is not set diff --git a/configs/ph1_sld3_defconfig b/configs/uniphier_sld3_defconfig index 4b871d0..4b871d0 100644 --- a/configs/ph1_sld3_defconfig +++ b/configs/uniphier_sld3_defconfig diff --git a/doc/README.uniphier b/doc/README.uniphier index 57b947b..f0f5346 100644 --- a/doc/README.uniphier +++ b/doc/README.uniphier @@ -28,34 +28,38 @@ Tested toolchains Compile the source ------------------ -PH1-sLD3: - $ make ph1_sld3_defconfig +PH1-sLD3 reference board: + $ make uniphier_sld3_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- -PH1-LD4: - $ make ph1_ld4_defconfig +PH1-LD4 reference board: + $ make uniphier_ld4_sld8_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- -PH1-Pro4: - $ make ph1_pro4_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- +PH1-sLD8 reference board: + $ make uniphier_ld4_sld8_defconfig + $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-sld8-ref -PH1-sLD8: - $ make ph1_sld8_defconfig +PH1-Pro4 reference board: + $ make uniphier_pro4_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- -PH1-Pro5: - $ make ph1_pro5_defconfig +PH1-Pro5 4KBOX Board: + $ make uniphier_pro5_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- -ProXstream2: - $ make pxs2_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- +ProXstream2 Gentil board: + $ make uniphier_pxs2_ld6b_defconfig + $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-proxstream2-gentil -PH1-LD6b: - $ make ph1_ld6b_defconfig +ProXstream2 Vodka board: + $ make uniphier_pxs2_ld6b_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- +PH1-LD6b reference board: + $ make uniphier_pxs2_ld6b_defconfig + $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-ld6b-ref + You may wish to change the "CROSS_COMPILE=arm-linux-gnueabi-" to use your favorite compiler. diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index ae5e78d..de54ca8 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -88,6 +88,7 @@ config ETH_SANDBOX_RAW config ETH_DESIGNWARE bool "Synopsys Designware Ethernet MAC" + select PHYLIB help This MAC is present in SoCs from various vendors. It supports 100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to diff --git a/drivers/net/designware.c b/drivers/net/designware.c index a6c39c3..04114a1 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -22,10 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if !defined(CONFIG_PHYLIB) -# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB" -#endif - static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) { struct eth_mac_regs *mac_p = bus->priv; @@ -107,8 +103,8 @@ static void tx_descs_init(struct dw_eth_dev *priv) #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | - DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \ - DESC_TXSTS_TXCHECKINSCTRL | \ + DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | + DESC_TXSTS_TXCHECKINSCTRL | DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; @@ -155,7 +151,7 @@ static void rx_descs_init(struct dw_eth_dev *priv) desc_p->dmamac_next = &desc_table_p[idx + 1]; desc_p->dmamac_cntl = - (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \ + (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | DESC_RXCTRL_RXCHAIN; desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; @@ -321,14 +317,14 @@ static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; - desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ + desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & DESC_TXCTRL_SIZE1MASK; desc_p->txrx_status &= ~(DESC_TXSTS_MSK); desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; #else - desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \ - DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \ + desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & + DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | DESC_TXCTRL_TXFIRST; desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; @@ -368,7 +364,7 @@ static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) /* Check if the owner is the CPU */ if (!(status & DESC_RXSTS_OWNBYDMA)) { - length = (status & DESC_RXSTS_FRMLENMSK) >> \ + length = (status & DESC_RXSTS_FRMLENMSK) >> DESC_RXSTS_FRMLENSHFT; /* Invalidate received data */ diff --git a/include/configs/axs101.h b/include/configs/axs101.h index c92cca2..98fff63 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -95,16 +95,10 @@ /* * Ethernet PHY configuration */ -#define CONFIG_PHYLIB #define CONFIG_MII #define CONFIG_PHY_GIGE /* - * Ethernet configuration - */ -#define CONFIG_DW_AUTONEG - -/* * USB 1.1 configuration */ #define CONFIG_USB_OHCI_NEW diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index 0e353b9..b5d4847 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -75,7 +75,6 @@ #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_CMD_MII #define CONFIG_MII -#define CONFIG_PHYLIB /* i2c Settings */ #define CONFIG_SYS_I2C diff --git a/include/configs/galileo.h b/include/configs/galileo.h index eb16a5e..14a42b1 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -45,7 +45,6 @@ /* 10/100M Ethernet support */ #define CONFIG_DESIGNWARE_ETH #define CONFIG_DW_ALTDESCRIPTOR -#define CONFIG_PHYLIB /* Environment configuration */ #define CONFIG_ENV_SECT_SIZE 0x1000 diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index 3d5665d..a0161bc 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -52,8 +52,6 @@ #endif #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -72,11 +70,13 @@ "mmcload=mmc rescan;" \ "load mmc 0:1 ${loadaddr} ${bootimage};" \ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ - "qspiroot=/dev/mtdblock0\0" \ - "qspirootfstype=jffs2\0" \ + "qspiload=sf probe && mtdparts default && run ubiload\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" + " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "ubiload=ubi part UBI && ubifsmount ubi0 && " \ + "ubifsload ${loadaddr} /boot/${bootimage} && " \ + "ubifsload ${fdt_addr} /boot/${fdtimage}\0" /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 3a4df63..a09e906 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -109,7 +109,6 @@ #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_MII #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) -#define CONFIG_PHYLIB #define CONFIG_PHY_GIGE #endif @@ -162,6 +161,19 @@ #endif /* + * NAND Support + */ +#ifdef CONFIG_NAND_DENALI +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_DENALI_ECC_SIZE 512 +#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS +#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS +#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) +#endif + +/* * I2C support */ #define CONFIG_SYS_I2C @@ -197,7 +209,7 @@ unsigned int cm_get_l4_sp_clk_hz(void); #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define MTDIDS_DEFAULT "nor0=ff705000.spi" +#define MTDIDS_DEFAULT "nor0=ff705000.spi.0" #endif /* QSPI reference clock */ #ifndef __ASSEMBLY__ @@ -249,7 +261,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_USB_FUNCTION_MASS_STORAGE #define CONFIG_USB_FUNCTION_DFU +#ifdef CONFIG_DM_MMC #define CONFIG_DFU_MMC +#endif #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) #define DFU_DEFAULT_POLL_TIMEOUT 300 @@ -271,6 +285,43 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE #define CONFIG_ENV_SIZE 4096 +/* Environment for SDMMC boot */ +#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ +#endif + +/* + * mtd partitioning for serial NOR flash + * + * device nor0 <ff705000.spi.0>, # parts = 6 + * #: name size offset mask_flags + * 0: u-boot 0x00100000 0x00000000 0 + * 1: env1 0x00040000 0x00100000 0 + * 2: env2 0x00040000 0x00140000 0 + * 3: UBI 0x03e80000 0x00180000 0 + * 4: boot 0x00e80000 0x00180000 0 + * 5: rootfs 0x01000000 0x01000000 0 + * + */ +#if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) +#define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ + "1m(u-boot)," \ + "256k(env1)," \ + "256k(env2)," \ + "14848k(boot)," \ + "16m(rootfs)," \ + "-@1536k(UBI)\0" +#endif + +/* UBI and UBIFS support */ +#if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND) +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO +#endif + /* * SPL * @@ -294,8 +345,15 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_WATCHDOG_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#ifdef CONFIG_DM_MMC #define CONFIG_SPL_MMC_SUPPORT +#endif +#ifdef CONFIG_DM_SPI #define CONFIG_SPL_SPI_SUPPORT +#endif +#ifdef CONFIG_SPL_NAND_DENALI +#define CONFIG_SPL_NAND_SUPPORT +#endif /* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT @@ -318,6 +376,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 #endif +/* SPL NAND boot support */ +#ifdef CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#endif + /* * Stack setup */ diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index d2efdda..c4c4ecb 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -52,8 +52,6 @@ #endif #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -72,11 +70,13 @@ "mmcload=mmc rescan;" \ "load mmc 0:1 ${loadaddr} ${bootimage};" \ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ - "qspiroot=/dev/mtdblock0\0" \ - "qspirootfstype=jffs2\0" \ + "qspiload=sf probe && mtdparts default && run ubiload\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" + " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "ubiload=ubi part UBI && ubifsmount ubi0 && " \ + "ubifsload ${loadaddr} /boot/${bootimage} && " \ + "ubifsload ${fdt_addr} /boot/${fdtimage}\0" /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index 959e3af..cbc7396 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -48,8 +48,6 @@ #endif #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index cd63faf..e7b5675 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -45,8 +45,6 @@ /* Environment is in MMC */ #define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index 6cbe367..95e7ba6 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -48,8 +48,6 @@ #endif #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -68,6 +66,13 @@ "mmcload=mmc rescan;" \ "load mmc 0:1 ${loadaddr} ${bootimage};" \ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiload=sf probe && mtdparts default && run ubiload\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "ubiload=ubi part UBI && ubifsmount ubi0 && " \ + "ubifsload ${loadaddr} /boot/${bootimage} && " \ + "ubifsload ${fdt_addr} /boot/${fdtimage}\0" /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h index 1d88f4f..c32a40a 100644 --- a/include/configs/socfpga_socrates.h +++ b/include/configs/socfpga_socrates.h @@ -48,8 +48,6 @@ #endif #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index 5bd2956..fdf67ca 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -70,11 +70,13 @@ "mmcload=mmc rescan;" \ "load mmc 0:1 ${loadaddr} ${bootimage};" \ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ - "qspiroot=/dev/mtdblock0\0" \ - "qspirootfstype=jffs2\0" \ + "qspiload=sf probe && mtdparts default && run ubiload\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" + " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "ubiload=ubi part UBI && ubifsmount ubi0 && " \ + "ubifsload ${loadaddr} /boot/${bootimage} && " \ + "ubifsload ${fdt_addr} /boot/${fdtimage}\0" /* Environment */ #define CONFIG_ENV_IS_IN_SPI_FLASH diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 1d69477..d2630f4 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -17,7 +17,6 @@ /* Ethernet driver configuration */ #define CONFIG_MII -#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 14c6a9e..f421321 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -53,7 +53,6 @@ /* GMAC related configs */ #define CONFIG_MII -#define CONFIG_PHYLIB #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_PHY_MICREL diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 8042073..790e704 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -309,11 +309,9 @@ extern int soft_i2c_gpio_scl; #endif #ifdef CONFIG_SUNXI_GMAC -#define CONFIG_DW_AUTONEG #define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */ #define CONFIG_PHY_ADDR 1 #define CONFIG_MII /* MII PHY management */ -#define CONFIG_PHYLIB #endif #ifdef CONFIG_USB_EHCI_HCD diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 8660ed4..e06484f 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -42,7 +42,6 @@ /* * Ethernet PHY configuration */ -#define CONFIG_PHYLIB #define CONFIG_PHY_GIGE /* diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 0562598..463c687 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -188,14 +188,14 @@ "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ "bootm $fit_addr_r\0" #else -#define CONFIG_BOOTFILE "uImage" +#define CONFIG_CMD_BOOTZ +#define CONFIG_BOOTFILE "zImage" #define LINUXBOOT_ENV_SETTINGS \ "fdt_addr=0x00100000\0" \ "fdt_addr_r=0x84100000\0" \ "fdt_size=0x00008000\0" \ - "fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "kernel_addr=0x00200000\0" \ - "kernel_addr_r=0x84200000\0" \ + "kernel_addr_r=0x80208000\0" \ "kernel_size=0x00800000\0" \ "ramdisk_addr=0x00a00000\0" \ "ramdisk_addr_r=0x84a00000\0" \ @@ -204,15 +204,15 @@ "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ "setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \ "setexpr fdt_addr $nor_base + $fdt_addr &&" \ - "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \ + "bootz $kernel_addr $ramdisk_addr $fdt_addr\0" \ "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ - "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ + "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ "tftpboot $fdt_addr_r $fdt_file &&" \ - "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" + "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/x600.h b/include/configs/x600.h index 58f1aca..0263c50 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -77,7 +77,6 @@ /* Ethernet config options */ #define CONFIG_MII -#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ |