diff options
60 files changed, 579 insertions, 270 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2d3303b..ada2217 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -656,6 +656,7 @@ config TARGET_VEXPRESS64_JUNO config TARGET_LS2080A_EMU bool "Support ls2080a_emu" + select ARCH_LS2080A select ARM64 select ARMV8_MULTIENTRY help @@ -666,6 +667,7 @@ config TARGET_LS2080A_EMU config TARGET_LS2080A_SIMU bool "Support ls2080a_simu" + select ARCH_LS2080A select ARM64 select ARMV8_MULTIENTRY help @@ -676,6 +678,7 @@ config TARGET_LS2080A_SIMU config TARGET_LS2080AQDS bool "Support ls2080aqds" + select ARCH_LS2080A select ARM64 select ARMV8_MULTIENTRY select SUPPORT_SPL @@ -687,6 +690,7 @@ config TARGET_LS2080AQDS config TARGET_LS2080ARDB bool "Support ls2080ardb" + select ARCH_LS2080A select ARM64 select ARMV8_MULTIENTRY select SUPPORT_SPL @@ -740,6 +744,8 @@ config TARGET_LS1012AFRDM config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUPPORT_SPL select ARCH_LS1021A select ARCH_SUPPORT_PSCI @@ -748,6 +754,8 @@ config TARGET_LS1021AQDS config TARGET_LS1021ATWR bool "Support ls1021atwr" select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUPPORT_SPL select ARCH_LS1021A select ARCH_SUPPORT_PSCI diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 0d4bfbc..c1eeefd 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,7 +12,7 @@ obj-y += cache_v7.o cache_v7_asm.o obj-y += cpu.o cp15.o obj-y += syslib.o -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_LS102XA),) ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 920eb4a..28bf778 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -1,6 +1,89 @@ config ARCH_LS1021A - bool "Freescale Layerscape LS1021A SoC" + bool select SYS_FSL_ERRATUM_A010315 + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES + select SYS_FSL_DDR_BE + select SYS_FSL_DDR_VER_50 + +menu "LS102xA architecture" + depends on ARCH_LS1021A config LS1_DEEP_SLEEP - bool "Freescale Layerscape 1 deep sleep" + bool "Deep sleep" + depends on ARCH_LS1021A + +config MAX_CPUS + int "Maximum number of CPUs permitted for LS102xA" + depends on ARCH_LS1021A + default 2 + help + Set this number to the maximum number of possible CPUs in the SoC. + SoCs may have multiple clusters with each cluster may have multiple + ports. If some ports are reserved but higher ports are used for + cores, count the reserved ports. This will allocate enough memory + in spin table to properly handle all cores. + +config NUM_DDR_CONTROLLERS + int "Maximum DDR controllers" + default 1 + +config SYS_FSL_ERRATUM_A010315 + bool "Workaround for PCIe erratum A010315" + +config SYS_FSL_SRDS_1 + bool + +config SYS_FSL_SRDS_2 + bool + +config SYS_HAS_SERDES + bool + +config SYS_FSL_DDR + bool "Freescale DDR driver" + help + Select Freescale General DDR driver, shared between most Freescale + PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- + based Layerscape SoCs (such as ls2080a). + +config SYS_FSL_DDR_BE + bool + default y + help + Access DDR registers in big-endian. + +config SYS_FSL_DDR_VER + int + default 50 if SYS_FSL_DDR_VER_50 + +config SYS_FSL_DDR_VER_50 + bool + +config SYS_FSL_DDRC_ARM_GEN3 + bool + +config SYS_FSL_DDRC_GEN4 + bool + +config SYS_FSL_DDR3 + bool "Freescale DDR3 controller" + depends on !SYS_FSL_DDR4 + select SYS_FSL_DDR + select SYS_FSL_DDRC_ARM_GEN3 + help + Enable Freescale DDR3 controller on ARM-based SoCs. + +config SYS_FSL_DDR4 + bool "Freescale DDR4 controller" + select SYS_FSL_DDR + select SYS_FSL_DDRC_GEN4 + help + Enable Freescale DDR4 controller. + +config SYS_FSL_IFC_BANK_COUNT + int "Maximum banks of Integrated flash controller" + depends on ARCH_LS1021A + default 8 + +endmenu diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 31f00cb..52fb6f8 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -60,6 +60,10 @@ unsigned int get_soc_major_rev(void) return major; } +void s_init(void) +{ +} + #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 void erratum_a010315(void) { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f8057ba..94ec8d5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,17 +1,138 @@ config ARCH_LS1012A - bool "Freescale Layerscape LS1012A SoC" + bool + select FSL_LSCH2 + select SYS_FSL_DDR_BE select SYS_FSL_MMDC select SYS_FSL_ERRATUM_A010315 config ARCH_LS1043A - bool "Freescale Layerscape LS1043A SoC" + bool + select FSL_LSCH2 + select SYS_FSL_DDR_BE + select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A010315 + select SYS_FSL_ERRATUM_A010539 config ARCH_LS1046A - bool "Freescale Layerscape LS1046A SoC" + bool + select FSL_LSCH2 + select SYS_FSL_DDR_BE + select SYS_FSL_DDR4 + select SYS_FSL_DDR_VER_50 + select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_SRDS_2 + +config ARCH_LS2080A + bool + select FSL_LSCH3 + select SYS_FSL_DDR4 + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_HAS_DP_DDR + select SYS_FSL_SRDS_2 + +config FSL_LSCH2 + bool + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES + +config FSL_LSCH3 + bool + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES + +menu "Layerscape architecture" + depends on FSL_LSCH2 || FSL_LSCH3 config SYS_FSL_MMDC - bool "Freescale Multi Mode DDR Controller" + bool config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" + +config SYS_FSL_ERRATUM_A010539 + bool "Workaround for PIN MUX erratum A010539" + +config MAX_CPUS + int "Maximum number of CPUs permitted for Layerscape" + default 4 if ARCH_LS1043A + default 4 if ARCH_LS1046A + default 16 if ARCH_LS2080A + default 1 + help + Set this number to the maximum number of possible CPUs in the SoC. + SoCs may have multiple clusters with each cluster may have multiple + ports. If some ports are reserved but higher ports are used for + cores, count the reserved ports. This will allocate enough memory + in spin table to properly handle all cores. + +config NUM_DDR_CONTROLLERS + int "Maximum DDR controllers" + default 3 if ARCH_LS2080A + default 1 + +config SYS_FSL_IFC_BANK_COUNT + int "Maximum banks of Integrated flash controller" + depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A + default 4 if ARCH_LS1043A + default 4 if ARCH_LS1046A + default 8 if ARCH_LS2080A + +config SYS_FSL_HAS_DP_DDR + bool + +config SYS_FSL_SRDS_1 + bool + +config SYS_FSL_SRDS_2 + bool + +config SYS_HAS_SERDES + bool + +config SYS_FSL_DDR + bool "Freescale DDR driver" + help + Select Freescale General DDR driver, shared between most Freescale + PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- + based Layerscape SoCs (such as ls2080a). + +config SYS_FSL_DDR_BE + bool + help + Access DDR registers in big-endian. + +config SYS_FSL_DDR_LE + bool + help + Access DDR registers in little-endian. + +config SYS_FSL_DDR_VER + int + default 50 if SYS_FSL_DDR_VER_50 + +config SYS_FSL_DDR_VER_50 + bool + +config SYS_FSL_DDRC_ARM_GEN3 + bool + +config SYS_FSL_DDRC_GEN4 + bool + +config SYS_FSL_DDR3 + bool "Freescale DDR3 controller" + depends on !SYS_FSL_DDR4 + select SYS_FSL_DDR + select SYS_FSL_DDRC_ARM_GEN3 + help + Enable Freescale DDR3 controller on ARM-based SoCs. + +config SYS_FSL_DDR4 + bool "Freescale DDR4 controller" + select SYS_FSL_DDR + select SYS_FSL_DDRC_GEN4 + help + Enable Freescale DDR4 controller. + +endmenu diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index f865373..b7a2e0c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -44,6 +44,9 @@ void cpu_name(char *name) if (IS_E_PROCESSOR(svr)) strcat(name, "E"); + + sprintf(name + strlen(name), " Rev%d.%d", + SVR_MAJ(svr), SVR_MIN(svr)); break; } @@ -200,6 +203,27 @@ static inline u32 initiator_type(u32 cluster, int init_id) return 0; } +u32 cpu_pos_mask(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + int i = 0; + u32 cluster, type, mask = 0; + + do { + int j; + + cluster = gur_in32(&gur->tp_cluster[i].lower); + for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { + type = initiator_type(cluster, j); + if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)) + mask |= 1 << (i * TP_INIT_PER_CLUSTER + j); + } + i++; + } while ((cluster & TP_CLUSTER_EOC) == 0x0); + + return mask; +} + u32 cpu_mask(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 40d6a76..1a8321b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -108,6 +108,24 @@ remove_psci_node: } #endif +void fsl_fdt_disable_usb(void *blob) +{ + int off; + /* + * SYSCLK is used as a reference clock for USB. When the USB + * controller is used, SYSCLK must meet the additional requirement + * of 100 MHz. + */ + if (CONFIG_SYS_CLK_FREQ != 100000000) { + off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3"); + while (off != -FDT_ERR_NOTFOUND) { + fdt_status_disabled(blob, off); + off = fdt_node_offset_by_compatible(blob, off, + "snps,dwc3"); + } + } +} + void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_FSL_LSCH2 @@ -150,4 +168,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_firmware(blob); #endif + fsl_fdt_disable_usb(blob); + } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index df7ffb8..f607c39 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -104,6 +104,11 @@ int is_core_valid(unsigned int core) return !!((1 << core) & cpu_mask()); } +static int is_pos_valid(unsigned int pos) +{ + return !!((1 << pos) & cpu_pos_mask()); +} + int is_core_online(u64 cpu_id) { u64 *table; @@ -126,9 +131,9 @@ int cpu_disable(int nr) return 0; } -int core_to_pos(int nr) +static int core_to_pos(int nr) { - u32 cores = cpu_mask(); + u32 cores = cpu_pos_mask(); int i, count = 0; if (nr == 0) { @@ -139,14 +144,17 @@ int core_to_pos(int nr) } for (i = 1; i < 32; i++) { - if (is_core_valid(i)) { + if (is_pos_valid(i)) { count++; if (count == nr) break; } } - return count; + if (count != nr) + return -1; + + return i; } int cpu_status(int nr) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 463d1e3..d68eeba 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -233,9 +233,8 @@ int sata_init(void) out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000); #endif out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); - out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); - out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); ahci_init((void __iomem *)CONFIG_SYS_SATA); scsi_scan(0); @@ -321,6 +320,19 @@ void erratum_a010315(void) } #endif +static void erratum_a010539(void) +{ +#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT) + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 porsr1; + + porsr1 = in_be32(&gur->porsr1); + porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; + out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), + porsr1); +#endif +} + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -339,7 +351,9 @@ void fsl_lsch2_early_init_f(void) #endif /* Make SEC reads and writes snoopable */ setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | - SCFG_SNPCNFGCR_SECWRSNP); + SCFG_SNPCNFGCR_SECWRSNP | + SCFG_SNPCNFGCR_SATARDSNP | + SCFG_SNPCNFGCR_SATAWRSNP); /* * Enable snoop requests and DVM message requests for @@ -352,6 +366,7 @@ void fsl_lsch2_early_init_f(void) erratum_a008850_early(); /* part 1 of 2 */ erratum_a009929(); erratum_a009660(); + erratum_a010539(); } #endif diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index a8bffba..f038f96 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -215,5 +215,26 @@ big-endian; status = "disabled"; }; + + usb0: usb3@2f00000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x2f00000 0x0 0x10000>; + interrupts = <0 60 0x4>; + dr_mode = "host"; + }; + + usb1: usb3@3000000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3000000 0x0 0x10000>; + interrupts = <0 61 0x4>; + dr_mode = "host"; + }; + + usb2: usb3@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 63 0x4>; + dr_mode = "host"; + }; }; }; diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index b308c8b..f76e981 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -75,4 +75,18 @@ reg-names = "QuadSPI", "QuadSPI-memory"; num-cs = <4>; }; + + usb0: usb3@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; /* Level high type */ + dr_mode = "host"; + }; + + usb1: usb3@3110000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; /* Level high type */ + dr_mode = "host"; + }; }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index a5c6c4c..4201e0f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -12,17 +12,6 @@ #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 -#ifdef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDRC_GEN4 -#else -#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ -#endif - -#ifndef CONFIG_ARCH_LS1012A -#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 -#endif - /* * Reserve secure memory * To be aligned with MMU block size @@ -30,14 +19,8 @@ #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ #ifdef CONFIG_LS2080A -#define CONFIG_MAX_CPUS 16 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_NUM_DDR_CONTROLLERS 3 -#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */ #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 -#define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_PAGE_SIZE 0x10000 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 @@ -48,7 +31,6 @@ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ /* DDR */ -#define CONFIG_SYS_FSL_DDR_LE #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE @@ -152,7 +134,6 @@ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #elif defined(CONFIG_FSL_LSCH2) -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ @@ -167,17 +148,12 @@ #define CONFIG_SYS_FSL_PEX_LUT_BE #define CONFIG_SYS_FSL_SEC_BE -#define CONFIG_SYS_FSL_SRDS_1 - /* SoC related */ #ifdef CONFIG_LS1043A -#define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 7 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 -#define CONFIG_SYS_FSL_DDR_BE #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE @@ -206,23 +182,18 @@ #define CONFIG_SYS_FSL_ERRATUM_A009660 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #elif defined(CONFIG_ARCH_LS1012A) -#define CONFIG_MAX_CPUS 1 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3 #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 #elif defined(CONFIG_ARCH_LS1046A) -#define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 -#define CONFIG_SYS_FSL_DDR_BE #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -#define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_FSL_IFC_BE #define CONFIG_SYS_FSL_SFP_VER_3_2 #define CONFIG_SYS_FSL_SNVS_LE diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index df51871..d88543d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -168,6 +168,8 @@ struct sys_info { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) /* Device Configuration and Pin Control */ +#define DCFG_DCSR_PORCR1 0x0 + struct ccsr_gur { u32 porsr1; /* POR status 1 */ #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 @@ -335,6 +337,8 @@ struct ccsr_gur { #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 +#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 +#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 /* Supplemental Configuration Unit */ struct ccsr_scfg { diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h index e46e076..f7306ff 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -34,5 +34,6 @@ void *get_spin_tbl_addr(void); phys_addr_t determine_mp_bootpg(void); void secondary_boot_func(void); int is_core_online(u64 cpu_id); +u32 cpu_pos_mask(void); #endif #endif /* _FSL_LAYERSCAPE_MP_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 4512732..58e90d8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -60,9 +60,8 @@ struct cpu_type { /* ahci port register default value */ #define AHCI_PORT_PHY_1_CFG 0xa003fffe -#define AHCI_PORT_PHY_2_CFG 0x28184d1f -#define AHCI_PORT_PHY_3_CFG 0x0e081509 #define AHCI_PORT_TRANS_CFG 0x08000029 +#define AHCI_PORT_AXICC_CFG 0x3fffffff /* AHCI (sata) register map */ struct ccsr_ahci { diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index fab8774..ec65cc0 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -94,14 +94,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A008407 #ifdef CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR_BE #define CONFIG_VERY_BIG_RAM -#ifdef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDRC_GEN4 -#else -#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 -#endif -#define CONFIG_SYS_FSL_DDR #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE #endif @@ -120,13 +113,7 @@ #define DCU_LAYER_MAX_NUM 16 -#define CONFIG_SYS_FSL_SRDS_1 - #ifdef CONFIG_LS102XA -#define CONFIG_MAX_CPUS 2 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_ERRATUM_A008378 diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 8c171b1..2b723a4 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -301,27 +301,15 @@ static inline u32 get_key_len(struct fsl_secboot_img_priv *img) */ static void fsl_secboot_header_verification_failure(void) { - struct ccsr_sec_mon_regs *sec_mon_regs = (void *) - (CONFIG_SYS_SEC_MON_ADDR); struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); - u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat); /* 29th bit of OSPR is ITS */ u32 its = sfp_in32(&sfp_regs->ospr) >> 2; - /* - * Read the SEC_MON status register - * Read SSM_ST field - */ - sts = sec_mon_in32(&sec_mon_regs->hp_stat); - if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) { - if (its == 1) - change_sec_mon_state(HPSR_SSM_ST_TRUST, - HPSR_SSM_ST_SOFT_FAIL); - else - change_sec_mon_state(HPSR_SSM_ST_TRUST, - HPSR_SSM_ST_NON_SECURE); - } + if (its == 1) + set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL); + else + set_sec_mon_state(HPSR_SSM_ST_NON_SECURE); printf("Generating reset request\n"); do_reset(NULL, 0, 0, NULL); @@ -338,32 +326,20 @@ static void fsl_secboot_header_verification_failure(void) */ static void fsl_secboot_image_verification_failure(void) { - struct ccsr_sec_mon_regs *sec_mon_regs = (void *) - (CONFIG_SYS_SEC_MON_ADDR); struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); - u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat); u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT; - /* - * Read the SEC_MON status register - * Read SSM_ST field - */ - sts = sec_mon_in32(&sec_mon_regs->hp_stat); - if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) { - if (its == 1) { - change_sec_mon_state(HPSR_SSM_ST_TRUST, - HPSR_SSM_ST_SOFT_FAIL); - - printf("Generating reset request\n"); - do_reset(NULL, 0, 0, NULL); - /* If reset doesn't coocur, halt execution */ - do_esbc_halt(NULL, 0, 0, NULL); - - } else { - change_sec_mon_state(HPSR_SSM_ST_TRUST, - HPSR_SSM_ST_NON_SECURE); - } + if (its == 1) { + set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL); + + printf("Generating reset request\n"); + do_reset(NULL, 0, 0, NULL); + /* If reset doesn't coocur, halt execution */ + do_esbc_halt(NULL, 0, 0, NULL); + + } else { + set_sec_mon_state(HPSR_SSM_ST_NON_SECURE); } } diff --git a/board/freescale/ls1021aqds/README b/board/freescale/ls1021aqds/README index c561776..6cf7146 100644 --- a/board/freescale/ls1021aqds/README +++ b/board/freescale/ls1021aqds/README @@ -110,3 +110,9 @@ Start Address End Address Description Size 0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB 0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB 0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB + +LS1021a rev1.0 Soc specific Options/Settings +-------------------------------------------- +If the LS1021a Soc is rev1.0, you need modify the configure file. +Add the following define in include/configs/ls1021aqds.h: +#define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/board/freescale/ls1021atwr/README b/board/freescale/ls1021atwr/README index d2821cb..896a659 100644 --- a/board/freescale/ls1021atwr/README +++ b/board/freescale/ls1021atwr/README @@ -107,3 +107,9 @@ Start Address End Address Description Size 0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB 0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB 0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB + +LS1021a rev1.0 Soc specific Options/Settings +-------------------------------------------- +If the LS1021a Soc is rev1.0, you need modify the configure file. +Add the following define in include/configs/ls1021atwr.h: +#define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 8761b60..b746ad7 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index 5bb475e..b6df305 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -5,7 +5,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART" +CONFIG_SYS_EXTRA_OPTIONS="LPUART" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 628f2d5..3beda1e 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -13,6 +13,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" +CONFIG_SYS_FSL_DDR3=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SPL=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index b511eb0..03e7bb2 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index a59d339..66fdc5b 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -25,6 +25,7 @@ CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_DM_SERIAL=y +CONFIG_SYS_FSL_DDR3=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index c7db8b7..6db90ff 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="LPUART" +CONFIG_SYS_FSL_DDR3=y CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 49c88a6..be2c05e 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_SYS_FSL_DDR3=y CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index f856ad7..d76606f 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" +CONFIG_SYS_FSL_DDR3=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SPL=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 09df451..4fcc92c 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_SYS_FSL_DDR3=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SPL=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index b209486..9352d82 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -4,7 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -29,4 +29,5 @@ CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index a60ea68..d384985 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -4,7 +4,8 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART" +CONFIG_SYS_EXTRA_OPTIONS="LPUART" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -30,4 +31,5 @@ CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 593f244..75e53f2 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -12,7 +12,8 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" +CONFIG_SYS_FSL_DDR4=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y @@ -40,4 +41,5 @@ CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index a844d9d..1103346 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -23,9 +23,11 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y +CONFIG_SYS_FSL_DDR3=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 92e5e80..94c602c 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -4,7 +4,8 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_SYS_FSL_DDR4=y CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y @@ -31,4 +32,5 @@ CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index e360906..d2cdd8c 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -12,7 +12,8 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" +CONFIG_SYS_FSL_DDR4=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y @@ -40,4 +41,5 @@ CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index b6ece37..463d317 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -12,7 +12,8 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_SYS_FSL_DDR4=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y @@ -41,4 +42,5 @@ CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index f51e020..262769d 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -4,7 +4,8 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y @@ -25,6 +26,7 @@ CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 5c20e44..e1b75ac 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -4,7 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_SYS_FSL_DDR4=y CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y @@ -25,4 +25,5 @@ CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index a203030..3d39e18 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -12,7 +12,8 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" +CONFIG_SYS_FSL_DDR4=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y @@ -36,4 +37,5 @@ CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index 323bb77..f1edf35 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -12,7 +12,8 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4" +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" +CONFIG_SYS_FSL_DDR4=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_SPL=y @@ -36,4 +37,5 @@ CONFIG_DM_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index 6a434c0..31e69b4 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -33,6 +33,7 @@ CONFIG_FSL_DSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index 53d5774..af52818 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -33,5 +33,6 @@ CONFIG_FSL_DSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 8eb4121..f09809d 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -42,5 +42,6 @@ CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 5917f60..2b24a94 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -34,5 +34,6 @@ CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 932a4bd..a62d864 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -33,6 +33,7 @@ CONFIG_FSL_DSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index c477961..bbf2a74 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -33,5 +33,6 @@ CONFIG_FSL_DSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 551f158..98a00e2 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080ARDB=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y @@ -27,13 +28,16 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y +CONFIG_DM=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/drivers/misc/fsl_sec_mon.c b/drivers/misc/fsl_sec_mon.c index d482a7d..415232e 100644 --- a/drivers/misc/fsl_sec_mon.c +++ b/drivers/misc/fsl_sec_mon.c @@ -7,140 +7,158 @@ #include <common.h> #include <fsl_sec_mon.h> -int change_sec_mon_state(u32 initial_state, u32 final_state) +static u32 get_sec_mon_state(void) { struct ccsr_sec_mon_regs *sec_mon_regs = (void *) (CONFIG_SYS_SEC_MON_ADDR); - u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat); + return sec_mon_in32(&sec_mon_regs->hp_stat) & HPSR_SSM_ST_MASK; +} + +static int set_sec_mon_state_non_sec(void) +{ + u32 sts; int timeout = 10; + struct ccsr_sec_mon_regs *sec_mon_regs = (void *) + (CONFIG_SYS_SEC_MON_ADDR); - if ((sts & HPSR_SSM_ST_MASK) != initial_state) - return -1; + sts = get_sec_mon_state(); - if (initial_state == HPSR_SSM_ST_TRUST) { - switch (final_state) { - case HPSR_SSM_ST_NON_SECURE: - printf("SEC_MON state transitioning to Soft Fail.\n"); - sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV); - - /* - * poll till SEC_MON is in - * Soft Fail state - */ - while (((sts & HPSR_SSM_ST_MASK) != - HPSR_SSM_ST_SOFT_FAIL)) { - while (timeout) { - sts = sec_mon_in32 - (&sec_mon_regs->hp_stat); - - if ((sts & HPSR_SSM_ST_MASK) == - HPSR_SSM_ST_SOFT_FAIL) - break; - - udelay(10); - timeout--; - } - } + switch (sts) { + /* + * If initial state is check or Non-Secure, then set the Software + * Security Violation Bit and transition to Non-Secure State. + */ + case HPSR_SSM_ST_CHECK: + printf("SEC_MON state transitioning to Non Secure.\n"); + sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV); - if (timeout == 0) { - printf("SEC_MON state transition timeout.\n"); - return -1; - } + /* polling loop till SEC_MON is in Non Secure state */ + while (timeout) { + sts = get_sec_mon_state(); + + if ((sts & HPSR_SSM_ST_MASK) == + HPSR_SSM_ST_NON_SECURE) + break; + + udelay(10); + timeout--; + } - timeout = 10; + if (timeout == 0) { + printf("SEC_MON state transition timeout.\n"); + return -1; + } + break; + + /* + * If initial state is Trusted, Secure or Soft-Fail, then first set + * the Software Security Violation Bit and transition to Soft-Fail + * State. + */ + case HPSR_SSM_ST_TRUST: + case HPSR_SSM_ST_SECURE: + case HPSR_SSM_ST_SOFT_FAIL: + printf("SEC_MON state transitioning to Soft Fail.\n"); + sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV); + + /* polling loop till SEC_MON is in Soft-Fail state */ + while (timeout) { + sts = get_sec_mon_state(); + + if ((sts & HPSR_SSM_ST_MASK) == + HPSR_SSM_ST_SOFT_FAIL) + break; + + udelay(10); + timeout--; + } + + if (timeout == 0) { + printf("SEC_MON state transition timeout.\n"); + return -1; + } + + timeout = 10; + /* + * If SSM Soft Fail to Non-Secure State Transition + * disable is not set, then set SSM_ST bit and + * transition to Non-Secure State. + */ + if ((sec_mon_in32(&sec_mon_regs->hp_com) & + HPCOMR_SSM_SFNS_DIS) == 0) { printf("SEC_MON state transitioning to Non Secure.\n"); sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SSM_ST); - /* - * poll till SEC_MON is in - * Non Secure state - */ - while (((sts & HPSR_SSM_ST_MASK) != - HPSR_SSM_ST_NON_SECURE)) { - while (timeout) { - sts = sec_mon_in32 - (&sec_mon_regs->hp_stat); - - if ((sts & HPSR_SSM_ST_MASK) == - HPSR_SSM_ST_NON_SECURE) - break; - - udelay(10); - timeout--; - } - } + /* polling loop till SEC_MON is in Non Secure*/ + while (timeout) { + sts = get_sec_mon_state(); - if (timeout == 0) { - printf("SEC_MON state transition timeout.\n"); - return -1; - } - break; - case HPSR_SSM_ST_SOFT_FAIL: - printf("SEC_MON state transitioning to Soft Fail.\n"); - sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV); - - /* - * polling loop till SEC_MON is in - * Soft Fail state - */ - while (((sts & HPSR_SSM_ST_MASK) != - HPSR_SSM_ST_SOFT_FAIL)) { - while (timeout) { - sts = sec_mon_in32 - (&sec_mon_regs->hp_stat); - - if ((sts & HPSR_SSM_ST_MASK) == - HPSR_SSM_ST_SOFT_FAIL) - break; - - udelay(10); - timeout--; - } + if ((sts & HPSR_SSM_ST_MASK) == + HPSR_SSM_ST_NON_SECURE) + break; + + udelay(10); + timeout--; } if (timeout == 0) { printf("SEC_MON state transition timeout.\n"); return -1; } - break; - default: - return -1; } - } else if (initial_state == HPSR_SSM_ST_NON_SECURE) { - switch (final_state) { - case HPSR_SSM_ST_SOFT_FAIL: - printf("SEC_MON state transitioning to Soft Fail.\n"); - sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV); - - /* - * polling loop till SEC_MON is in - * Soft Fail state - */ - while (((sts & HPSR_SSM_ST_MASK) != - HPSR_SSM_ST_SOFT_FAIL)) { - while (timeout) { - sts = sec_mon_in32 - (&sec_mon_regs->hp_stat); - - if ((sts & HPSR_SSM_ST_MASK) == - HPSR_SSM_ST_SOFT_FAIL) - break; - - udelay(10); - timeout--; - } - } + break; + default: + printf("SEC_MON already in Non Secure state.\n"); + return 0; + } + return 0; +} - if (timeout == 0) { - printf("SEC_MON state transition timeout.\n"); - return -1; - } +static int set_sec_mon_state_soft_fail(void) +{ + u32 sts; + int timeout = 10; + struct ccsr_sec_mon_regs *sec_mon_regs = (void *) + (CONFIG_SYS_SEC_MON_ADDR); + + printf("SEC_MON state transitioning to Soft Fail.\n"); + sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV); + + /* polling loop till SEC_MON is in Soft-Fail state */ + while (timeout) { + sts = get_sec_mon_state(); + + if ((sts & HPSR_SSM_ST_MASK) == + HPSR_SSM_ST_SOFT_FAIL) break; - default: - return -1; - } + + udelay(10); + timeout--; } + if (timeout == 0) { + printf("SEC_MON state transition timeout.\n"); + return -1; + } return 0; } + +int set_sec_mon_state(u32 state) +{ + int ret = -1; + + switch (state) { + case HPSR_SSM_ST_NON_SECURE: + ret = set_sec_mon_state_non_sec(); + break; + case HPSR_SSM_ST_SOFT_FAIL: + ret = set_sec_mon_state_soft_fail(); + break; + default: + printf("SEC_MON state transition not supported.\n"); + return 0; + } + + return ret; +} diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 2144fca..729ded9 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -865,6 +865,7 @@ static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave) struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { + u32 mcr_val; struct fsl_qspi *qspi; struct fsl_qspi_regs *regs; u32 total_size; @@ -896,8 +897,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, qspi->slave.max_write_size = TX_BUFFER_SIZE; + mcr_val = qspi_read32(qspi->priv.flags, ®s->mcr); qspi_write32(qspi->priv.flags, ®s->mcr, - QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK); + QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK | + (mcr_val & QSPI_MCR_END_CFD_MASK)); qspi_cfg_smpr(&qspi->priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK | @@ -975,6 +978,7 @@ static int fsl_qspi_child_pre_probe(struct udevice *dev) static int fsl_qspi_probe(struct udevice *bus) { + u32 mcr_val; u32 amba_size_per_chip; struct fsl_qspi_platdata *plat = dev_get_platdata(bus); struct fsl_qspi_priv *priv = dev_get_priv(bus); @@ -999,8 +1003,10 @@ static int fsl_qspi_probe(struct udevice *bus) priv->flash_num = plat->flash_num; priv->num_chipselect = plat->num_chipselect; + mcr_val = qspi_read32(priv->flags, &priv->regs->mcr); qspi_write32(priv->flags, &priv->regs->mcr, - QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK); + QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK | + (mcr_val & QSPI_MCR_END_CFD_MASK)); qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK | QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0); diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index ba27437..80603c9 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -8,11 +8,8 @@ #define __LS1012A_COMMON_H #define CONFIG_FSL_LAYERSCAPE -#define CONFIG_FSL_LSCH2 #define CONFIG_GICV2 -#define CONFIG_SYS_HAS_SERDES - #include <asm/arch/config.h> #define CONFIG_SYS_NO_FLASH @@ -103,19 +100,14 @@ /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "initrd_high=0xffffffff\0" \ "verify=no\0" \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ "kernel_addr=0x100000\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_start=0xa00000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ - "console=ttyAMA0,38400n8\0" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0500" diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 612f243..f6f88e8 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -20,6 +20,17 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=no\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0xa00000\0" \ + "kernel_load=0x96000000\0" \ + "kernel_size=0x2800000\0" + /* * USB */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 5bf6081..eefd93d 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -125,7 +125,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ #ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ #define CONFIG_SYS_DDR_RAW_TIMING #endif #define CONFIG_DIMM_SLOTS_PER_CTLR 1 @@ -140,8 +139,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_SYS_HAS_SERDES - #define CONFIG_FSL_CAAM /* Enable CAAM */ #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ @@ -541,8 +538,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING -#define CONFIG_ARMV7_NONSEC -#define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 0e90f56..da07329 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -167,8 +167,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_HAS_SERDES - #define CONFIG_FSL_CAAM /* Enable CAAM */ #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ @@ -413,8 +411,6 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING -#define CONFIG_ARMV7_NONSEC -#define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index ed0e434..0fd69bf 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -9,16 +9,12 @@ #define CONFIG_REMAKE_ELF #define CONFIG_FSL_LAYERSCAPE -#define CONFIG_FSL_LSCH2 #define CONFIG_LS1043A #define CONFIG_MP #define CONFIG_SYS_FSL_CLK #define CONFIG_GICV2 #include <asm/arch/config.h> -#ifdef CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_HAS_SERDES -#endif /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) @@ -28,10 +24,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F 1 -#ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ -#endif - #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 820adc4..561a05a 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -39,9 +39,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ -#ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ -#endif #define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC @@ -49,8 +46,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_SYS_HAS_SERDES - #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET #define CONFIG_PHYLIB diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 7c5e635..c4bbd56 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -9,15 +9,11 @@ #define CONFIG_REMAKE_ELF #define CONFIG_FSL_LAYERSCAPE -#define CONFIG_FSL_LSCH2 #define CONFIG_MP #define CONFIG_SYS_FSL_CLK #define CONFIG_GICV2 #include <asm/arch/config.h> -#ifdef CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_HAS_SERDES -#endif /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 37518bd..c0f5bd3 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -46,8 +46,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_SYS_HAS_SERDES - /* DSPI */ #ifdef CONFIG_FSL_DSPI #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 5576279..2cae966 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -9,16 +9,12 @@ #define CONFIG_REMAKE_ELF #define CONFIG_FSL_LAYERSCAPE -#define CONFIG_FSL_LSCH3 #define CONFIG_MP #define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147 #include <asm/arch/ls2080a_stream_id.h> #include <asm/arch/config.h> -#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2)) -#define CONFIG_SYS_HAS_SERDES -#endif /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) @@ -50,7 +46,6 @@ #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ #endif #ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ #define CONFIG_SYS_DDR_RAW_TIMING #endif diff --git a/include/fsl_sec_mon.h b/include/fsl_sec_mon.h index b6794ce..1f31f88 100644 --- a/include/fsl_sec_mon.h +++ b/include/fsl_sec_mon.h @@ -34,13 +34,16 @@ struct ccsr_sec_mon_regs { u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */ }; -#define HPCOMR_SW_SV 0x100 /* Security Violation bit */ -#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */ -#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */ +#define HPCOMR_SW_SV 0x100 /* Security Violation bit */ +#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */ +#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */ +#define HPCOMR_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */ +#define HPCOMR_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */ #define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */ #define HPSR_SSM_ST_NON_SECURE 0xb00 /* SEC_MON is in non secure state */ #define HPSR_SSM_ST_TRUST 0xd00 /* SEC_MON is in trusted state */ #define HPSR_SSM_ST_SOFT_FAIL 0x300 /* SEC_MON is in soft fail state */ +#define HPSR_SSM_ST_SECURE 0xf00 /* SEC_MON is in secure state */ #define HPSR_SSM_ST_MASK 0xf00 /* Mask for SSM_ST field */ /* @@ -53,6 +56,7 @@ enum { SEC_MON_SW_SV, }; -int change_sec_mon_state(uint32_t initial_state, uint32_t final_state); +/* Transition SEC_MON state */ +int set_sec_mon_state(u32 state); #endif /* __FSL_SEC_MON_H */ diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h index 2976a2c..d3a2813 100644 --- a/include/fsl_sfp.h +++ b/include/fsl_sfp.h @@ -78,9 +78,16 @@ struct ccsr_sfp_regs { u32 fsl_uid; /* 0xB0 FSL Unique ID */ }; #endif + #define ITS_MASK 0x00000004 #define ITS_BIT 2 -#define OSPR_KEY_REVOC_SHIFT 13 -#define OSPR_KEY_REVOC_MASK 0x0000e000 + +#if defined(CONFIG_SYS_FSL_SFP_VER_3_4) +#define OSPR_KEY_REVOC_SHIFT 9 +#define OSPR_KEY_REVOC_MASK 0x0000fe00 +#else +#define OSPR_KEY_REVOC_SHIFT 13 +#define OSPR_KEY_REVOC_MASK 0x0000e000 +#endif /* CONFIG_SYS_FSL_SFP_VER_3_4 */ #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 3621c91..04e9536 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1294,8 +1294,6 @@ CONFIG_FSL_LAW CONFIG_FSL_LAYERSCAPE CONFIG_FSL_LBC CONFIG_FSL_LINFLEXUART -CONFIG_FSL_LSCH2 -CONFIG_FSL_LSCH3 CONFIG_FSL_LS_PPA CONFIG_FSL_MC9SDZ60 CONFIG_FSL_MC_ENET |