diff options
| -rw-r--r-- | arch/x86/cpu/coreboot/coreboot.c | 11 | ||||
| -rw-r--r-- | board/google/chromebook_link/link.c | 5 | ||||
| -rw-r--r-- | common/board_r.c | 3 | ||||
| -rw-r--r-- | include/configs/chromebook_link.h | 1 |
4 files changed, 0 insertions, 20 deletions
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 2df7288..cfacc05 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -39,17 +39,6 @@ int board_early_init_f(void) return 0; } -int board_early_init_r(void) -{ - /* CPU Speed to 100MHz */ - gd->cpu_clk = 100000000; - - /* Crystal is 33.000MHz */ - gd->bus_clk = 33000000; - - return 0; -} - int print_cpuinfo(void) { return default_print_cpuinfo(); diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index 88cee05..0a1ae61 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -12,11 +12,6 @@ int arch_early_init_r(void) return 0; } -int board_early_init_r(void) -{ - return 0; -} - static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */ .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */ diff --git a/common/board_r.c b/common/board_r.c index 19c6427..bfa74c7 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -838,9 +838,6 @@ init_fnc_t init_sequence_r[] = { #ifdef CONFIG_CMD_KGDB initr_kgdb, #endif -#ifdef CONFIG_X86 - board_early_init_r, -#endif interrupt_init, #if defined(CONFIG_ARM) || defined(CONFIG_x86) initr_enable_interrupts, diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 8caeca6..cd4a8a0 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -21,7 +21,6 @@ #define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 #define CONFIG_SYS_X86_START16 0xfffff800 #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_DISPLAY_CPUINFO #define CONFIG_X86_RESET_VECTOR |