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-rwxr-xr-xMAKEALL3
-rw-r--r--Makefile9
-rw-r--r--board/delta/Makefile48
-rw-r--r--board/delta/config.mk8
-rw-r--r--board/delta/delta.c75
-rw-r--r--board/delta/lowlevel_init.S385
-rw-r--r--board/delta/nand.c590
-rw-r--r--board/delta/u-boot.lds56
-rw-r--r--board/mcc200/mt48lc8m32b2-6-7.h8
-rw-r--r--board/zylonite/Makefile48
-rw-r--r--board/zylonite/config.mk4
-rw-r--r--board/zylonite/flash.c434
-rw-r--r--board/zylonite/lowlevel_init.S371
-rw-r--r--board/zylonite/u-boot.lds56
-rw-r--r--board/zylonite/zylonite.c75
-rw-r--r--config.mk9
-rw-r--r--cpu/pxa/config.mk1
-rw-r--r--cpu/pxa/cpu.c2
-rw-r--r--cpu/pxa/serial.c12
-rw-r--r--cpu/pxa/start.S106
-rw-r--r--drivers/nand/nand_base.c5
-rw-r--r--drivers/smc91111.c2
-rw-r--r--include/asm-arm/arch-pxa/hardware.h4
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h659
-rw-r--r--include/asm-arm/global_data.h7
-rw-r--r--include/configs/delta.h288
-rw-r--r--include/configs/zylonite.h256
-rw-r--r--lib_arm/board.c9
28 files changed, 3475 insertions, 55 deletions
diff --git a/MAKEALL b/MAKEALL
index d4400fe..65b1761 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -204,7 +204,8 @@ LIST_ARM11=" \
LIST_pxa=" \
adsvix cerf250 cradle csb226 \
innokom lubbock pxa255_idp wepep250 \
- xaeniax xm250 xsengine \
+ xaeniax xm250 xsengine zylonite \
+ delta
"
LIST_ixp="ixdp425"
diff --git a/Makefile b/Makefile
index 485c4c3..67eb0dc 100644
--- a/Makefile
+++ b/Makefile
@@ -208,6 +208,9 @@ etags:
net disk rtc dtt drivers drivers/sk98lin common \
\( -name CVS -prune \) -o \( -name '*.[ch]' -print \)`
+ctags:
+ ctags -Re
+
System.map: u-boot
@$(NM) $< | \
grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
@@ -1641,6 +1644,9 @@ cerf250_config : unconfig
cradle_config : unconfig
@./mkconfig $(@:_config=) arm pxa cradle
+delta_config :
+ @./mkconfig $(@:_config=) arm pxa delta
+
csb226_config : unconfig
@./mkconfig $(@:_config=) arm pxa csb226
@@ -1671,6 +1677,9 @@ xm250_config : unconfig
xsengine_config : unconfig
@./mkconfig $(@:_config=) arm pxa xsengine
+zylonite_config :
+ @./mkconfig $(@:_config=) arm pxa zylonite
+
#########################################################################
## ARM1136 Systems
#########################################################################
diff --git a/board/delta/Makefile b/board/delta/Makefile
new file mode 100644
index 0000000..e744eec
--- /dev/null
+++ b/board/delta/Makefile
@@ -0,0 +1,48 @@
+
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := delta.o nand.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/delta/config.mk b/board/delta/config.mk
new file mode 100644
index 0000000..9564625
--- /dev/null
+++ b/board/delta/config.mk
@@ -0,0 +1,8 @@
+#TEXT_BASE = 0x0
+#TEXT_BASE = 0xa1700000
+#TEXT_BASE = 0xa3080000
+#TEXT_BASE = 0x9ffe0000
+TEXT_BASE = 0xa3008000
+
+# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE)
+BOARDLIBS = drivers/nand/libnand.a
diff --git a/board/delta/delta.c b/board/delta/delta.c
new file mode 100644
index 0000000..3ffcc2a
--- /dev/null
+++ b/board/delta/delta.c
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of Lubbock-Board mk@tbd: fix this! */
+ gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setenv("stdout", "serial");
+ setenv("stderr", "serial");
+ return 0;
+}
+
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+ return 0;
+}
diff --git a/board/delta/lowlevel_init.S b/board/delta/lowlevel_init.S
new file mode 100644
index 0000000..498cf7f
--- /dev/null
+++ b/board/delta/lowlevel_init.S
@@ -0,0 +1,385 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE: .long CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+.macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+.endm
+
+
+.macro wait time
+ ldr r2, =OSCR
+ mov r3, #0
+ str r3, [r2]
+0:
+ ldr r3, [r2]
+ cmp r3, \time
+ bls 0b
+.endm
+
+/*
+ * Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+ /* Set up GPIO pins first ----------------------------------------- */
+ mov r10, lr
+
+ /* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */
+ ldr r0, =GPIO97
+ ldr r1, =0x801
+ str r1, [r0]
+
+ ldr r0, =GPIO98
+ ldr r1, =0x801
+ str r1, [r0]
+
+ /* tebrandt - ASCR, clear the RDH bit */
+ ldr r0, =ASCR
+ ldr r1, [r0]
+ bic r1, r1, #0x80000000
+ str r1, [r0]
+
+ /* ---------------------------------------------------------------- */
+ /* Enable memory interface */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 1: Wait for at least 200 microsedonds to allow internal */
+ /* clocks to settle. Only necessary after hard reset... */
+ /* FIXME: can be optimized later */
+ /* ---------------------------------------------------------------- */
+; wait #300
+
+mem_init:
+
+#define NEW_SDRAM_INIT 1
+#ifdef NEW_SDRAM_INIT
+
+ /* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
+ ldr r0, =ACCR
+ ldr r1, [r0]
+ orr r1, r1, #0x3000
+ str r1, [r0]
+ ldr r1, [r0]
+
+ /* 2. Programm MDCNFG, leaving DMCEN de-asserted */
+ ldr r0, =MDCNFG
+ ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
+ /* ldr r1, =0x80000403 */
+ str r1, [r0]
+ ldr r1, [r0] /* delay until written */
+
+ /* 3. wait nop power up waiting period (200ms)
+ * optimization: Steps 4+6 can be done during this
+ */
+ wait #300
+
+ /* 4. Perform an initial Rcomp-calibration cycle */
+ ldr r0, =RCOMP
+ ldr r1, =0x80000000
+ str r1, [r0]
+ ldr r1, [r0] /* delay until written */
+ /* missing: program for automatic rcomp evaluation cycles */
+
+ /* 5. DDR DRAM strobe delay calibration */
+ ldr r0, =DDR_HCAL
+ ldr r1, =0x88000007
+ str r1, [r0]
+ wait #5
+ ldr r1, [r0] /* delay until written */
+
+ /* Set MDMRS */
+ ldr r0, =MDMRS
+ ldr r1, =0x60000033
+ str r1, [r0]
+ wait #300
+
+ /* Configure MDREFR */
+ ldr r0, =MDREFR
+ ldr r1, =0x00000006
+ str r1, [r0]
+ ldr r1, [r0]
+
+ /* Enable the dynamic memory controller */
+ ldr r0, =MDCNFG
+ ldr r1, [r0]
+ orr r1, r1, #MDCNFG_DMCEN
+ str r1, [r0]
+
+
+#else /* NEW_SDRAM_INIT */
+
+ /* configure the MEMCLKCFG register */
+ ldr r1, =MEMCLKCFG
+ ldr r2, =0x00010001
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set CSADRCFG[0] to data flash SRAM mode */
+ ldr r1, =CSADRCFG0
+ ldr r2, =0x00320809
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set CSADRCFG[1] to data flash SRAM mode */
+ ldr r1, =CSADRCFG1
+ ldr r2, =0x00320809
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set MSC 0 register for SRAM memory */
+ ldr r1, =MSC0
+ ldr r2, =0x11191119
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set CSADRCFG[2] to data flash SRAM mode */
+ ldr r1, =CSADRCFG2
+ ldr r2, =0x00320809
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set CSADRCFG[3] to VLIO mode */
+ ldr r1, =CSADRCFG3
+ ldr r2, =0x0032080B
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set MSC 1 register for VLIO memory */
+ ldr r1, =MSC1
+ ldr r2, =0x123C1119
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+#if 0
+ /* This does not work in Zylonite. -SC */
+ ldr r0, =0x15fffff0
+ ldr r1, =0xb10b
+ str r1, [r0]
+ str r1, [r0, #4]
+#endif
+
+ /* Configure ACCR Register */
+ ldr r0, =ACCR @ ACCR
+ ldr r1, =0x0180b108
+ str r1, [r0]
+ ldr r1, [r0]
+
+ /* Configure MDCNFG Register */
+ ldr r0, =MDCNFG @ MDCNFG
+ ldr r1, =0x403
+ str r1, [r0]
+ ldr r1, [r0]
+
+ /* Perform Resistive Compensation by configuring RCOMP register */
+ ldr r1, =RCOMP @ RCOMP
+ ldr r2, =0x000000ff
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure MDMRS Register for SDCS0 */
+ ldr r1, =MDMRS @ MDMRS
+ ldr r2, =0x60000023
+ ldr r3, [r1]
+ orr r2, r2, r3
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure MDMRS Register for SDCS1 */
+ ldr r1, =MDMRS @ MDMRS
+ ldr r2, =0xa0000023
+ ldr r3, [r1]
+ orr r2, r2, r3
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure MDREFR */
+ ldr r1, =MDREFR @ MDREFR
+ ldr r2, =0x00000006
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure EMPI */
+ ldr r1, =EMPI @ EMPI
+ ldr r2, =0x80000000
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Hardware DDR Read-Strobe Delay Calibration */
+ ldr r0, =DDR_HCAL @ DDR_HCAL
+ ldr r1, =0x803ffc07 @ the offset is correct? -SC
+ str r1, [r0]
+ wait #5
+ ldr r1, [r0]
+
+ /* Here we assume the hardware calibration alwasy be successful. -SC */
+ /* Set DMCEN bit in MDCNFG Register */
+ ldr r0, =MDCNFG @ MDCNFG
+ ldr r1, [r0]
+ orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
+ str r1, [r0]
+
+#endif /* NEW_SDRAM_INIT */
+
+#ifndef CFG_SKIP_DRAM_SCRUB
+ /* scrub/init SDRAM if enabled/present */
+ ldr r8, =CFG_DRAM_BASE /* base address of SDRAM (CFG_DRAM_BASE) */
+ ldr r9, =CFG_DRAM_SIZE /* size of memory to scrub (CFG_DRAM_SIZE) */
+ mov r0, #0 /* scrub with 0x0000:0000 */
+ mov r1, #0
+ mov r2, #0
+ mov r3, #0
+ mov r4, #0
+ mov r5, #0
+ mov r6, #0
+ mov r7, #0
+10: /* fastScrubLoop */
+ subs r9, r9, #32 /* 8 words/line */
+ stmia r8!, {r0-r7}
+ beq 15f
+ b 10b
+#endif /* CFG_SKIP_DRAM_SCRUB */
+
+15:
+ /* Mask all interrupts */
+ mov r1, #0
+ mcr p6, 0, r1, c1, c0, 0 @ ICMR
+
+ /* Disable software and data breakpoints */
+ mov r0, #0
+ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
+ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
+ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /* Enable all debug functionality */
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 /* dcsr */
+
+endlowlevel_init:
+
+ mov pc, lr
+
+
+/*
+@********************************************************************************
+@ DDR calibration
+@
+@ This function is used to calibrate DQS delay lines.
+@ Monahans supports three ways to do it. One is software
+@ calibration. Two is hardware calibration. Three is hybrid
+@ calibration.
+@
+@ TBD
+@ -SC
+ddr_calibration:
+
+ @ Case 1: Write the correct delay value once
+ @ Configure DDR_SCAL Register
+ ldr r0, =DDR_SCAL @ DDR_SCAL
+q ldr r1, =0xaf2f2f2f
+ str r1, [r0]
+ ldr r1, [r0]
+*/
+/* @ Case 2: Software Calibration
+ @ Write test pattern to memory
+ ldr r5, =0x0faf0faf @ Data Pattern
+ ldr r4, =0xa0000000 @ DDR ram
+ str r5, [r4]
+
+ mov r1, =0x0 @ delay count
+ mov r6, =0x0
+ mov r7, =0x0
+ddr_loop1:
+ add r1, r1, =0x1
+ cmp r1, =0xf
+ ble end_loop
+ mov r3, r1
+ mov r0, r1, lsl #30
+ orr r3, r3, r0
+ mov r0, r1, lsl #22
+ orr r3, r3, r0
+ mov r0, r1, lsl #14
+ orr r3, r3, r0
+ orr r3, r3, =0x80000000
+ ldr r2, =DDR_SCAL
+ str r3, [r2]
+
+ ldr r2, [r4]
+ cmp r2, r5
+ bne ddr_loop1
+ mov r6, r1
+ddr_loop2:
+ add r1, r1, =0x1
+ cmp r1, =0xf
+ ble end_loop
+ mov r3, r1
+ mov r0, r1, lsl #30
+ orr r3, r3, r0
+ mov r0, r1, lsl #22
+ orr r3, r3, r0
+ mov r0, r1, lsl #14
+ orr r3, r3, r0
+ orr r3, r3, =0x80000000
+ ldr r2, =DDR_SCAL
+ str r3, [r2]
+
+ ldr r2, [r4]
+ cmp r2, r5
+ be ddr_loop2
+ mov r7, r2
+
+ add r3, r6, r7
+ lsr r3, r3, =0x1
+ mov r0, r1, lsl #30
+ orr r3, r3, r0
+ mov r0, r1, lsl #22
+ orr r3, r3, r0
+ mov r0, r1, lsl #14
+ orr r3, r3, r0
+ orr r3, r3, =0x80000000
+ ldr r2, =DDR_SCAL
+
+end_loop:
+
+ @ Case 3: Hardware Calibratoin
+ ldr r0, =DDR_HCAL @ DDR_HCAL
+ ldr r1, =0x803ffc07 @ the offset is correct? -SC
+ str r1, [r0]
+ wait #5
+ ldr r1, [r0]
+ mov pc, lr
+*/
diff --git a/board/delta/nand.c b/board/delta/nand.c
new file mode 100644
index 0000000..50def59
--- /dev/null
+++ b/board/delta/nand.c
@@ -0,0 +1,590 @@
+/*
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#ifdef CONFIG_NEW_NAND_CODE
+
+#include <nand.h>
+#include <asm/arch/pxa-regs.h>
+
+#ifdef CFG_DFC_DEBUG1
+# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG1(fmt, args...)
+#endif
+
+#ifdef CFG_DFC_DEBUG2
+# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG2(fmt, args...)
+#endif
+
+#ifdef CFG_DFC_DEBUG3
+# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG3(fmt, args...)
+#endif
+
+#define MIN(x, y) ((x < y) ? x : y)
+
+/* These really don't belong here, as they are specific to the NAND Model */
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+
+static struct nand_bbt_descr delta_bbt_descr = {
+ .options = 0,
+ .offs = 0,
+ .len = 2,
+ .pattern = scan_ff_pattern
+};
+
+static struct nand_oobinfo delta_oob = {
+ .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
+ .eccbytes = 6,
+ .eccpos = {2, 3, 4, 5, 6, 7},
+ .oobfree = { {8, 2}, {12, 4} }
+};
+
+
+/*
+ * not required for Monahans DFC
+ */
+static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+ return;
+}
+
+#if 0
+/* read device ready pin */
+static int dfc_device_ready(struct mtd_info *mtdinfo)
+{
+ if(NDSR & NDSR_RDY)
+ return 1;
+ else
+ return 0;
+ return 0;
+}
+#endif
+
+/*
+ * Write buf to the DFC Controller Data Buffer
+ */
+static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ unsigned long bytes_multi = len & 0xfffffffc;
+ unsigned long rest = len & 0x3;
+ unsigned long *long_buf;
+ int i;
+
+ DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
+ if(bytes_multi) {
+ for(i=0; i<bytes_multi; i+=4) {
+ long_buf = (unsigned long*) &buf[i];
+ NDDB = *long_buf;
+ }
+ }
+ if(rest) {
+ printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
+ }
+ return;
+}
+
+
+/*
+ * These functions are quite problematic for the DFC. Luckily they are
+ * not used in the current nand code, except for nand_command, which
+ * we've defined our own anyway. The problem is, that we always need
+ * to write 4 bytes to the DFC Data Buffer, but in these functions we
+ * don't know if to buffer the bytes/half words until we've gathered 4
+ * bytes or if to send them straight away.
+ *
+ * Solution: Don't use these with Mona's DFC and complain loudly.
+ */
+static void dfc_write_word(struct mtd_info *mtd, u16 word)
+{
+ printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n");
+}
+static void dfc_write_byte(struct mtd_info *mtd, u_char byte)
+{
+ printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n");
+}
+
+/* The original:
+ * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
+ *
+ * Shouldn't this be "u_char * const buf" ?
+ */
+static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
+{
+ int i=0, j;
+
+ /* we have to be carefull not to overflow the buffer if len is
+ * not a multiple of 4 */
+ unsigned long bytes_multi = len & 0xfffffffc;
+ unsigned long rest = len & 0x3;
+ unsigned long *long_buf;
+
+ DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
+ /* if there are any, first copy multiple of 4 bytes */
+ if(bytes_multi) {
+ for(i=0; i<bytes_multi; i+=4) {
+ long_buf = (unsigned long*) &buf[i];
+ *long_buf = NDDB;
+ }
+ }
+
+ /* ...then the rest */
+ if(rest) {
+ unsigned long rest_data = NDDB;
+ for(j=0;j<rest; j++)
+ buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
+ }
+
+ return;
+}
+
+/*
+ * read a word. Not implemented as not used in NAND code.
+ */
+static u16 dfc_read_word(struct mtd_info *mtd)
+{
+ printf("dfc_write_byte: UNIMPLEMENTED.\n");
+ return 0;
+}
+
+/* global var, too bad: mk@tbd: move to ->priv pointer */
+static unsigned long read_buf = 0;
+static int bytes_read = -1;
+
+/*
+ * read a byte from NDDB Because we can only read 4 bytes from NDDB at
+ * a time, we buffer the remaining bytes. The buffer is reset when a
+ * new command is sent to the chip.
+ *
+ * WARNING:
+ * This function is currently only used to read status and id
+ * bytes. For these commands always 8 bytes need to be read from
+ * NDDB. So we read and discard these bytes right now. In case this
+ * function is used for anything else in the future, we must check
+ * what was the last command issued and read the appropriate amount of
+ * bytes respectively.
+ */
+static u_char dfc_read_byte(struct mtd_info *mtd)
+{
+ unsigned char byte;
+ unsigned long dummy;
+
+ if(bytes_read < 0) {
+ read_buf = NDDB;
+ dummy = NDDB;
+ bytes_read = 0;
+ }
+ byte = (unsigned char) (read_buf>>(8 * bytes_read++));
+ if(bytes_read >= 4)
+ bytes_read = -1;
+
+ DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
+ return byte;
+}
+
+/* calculate delta between OSCR values start and now */
+static unsigned long get_delta(unsigned long start)
+{
+ unsigned long cur = OSCR;
+
+ if(cur < start) /* OSCR overflowed */
+ return (cur + (start^0xffffffff));
+ else
+ return (cur - start);
+}
+
+/* delay function, this doesn't belong here */
+static void wait_us(unsigned long us)
+{
+ unsigned long start = OSCR;
+ us *= OSCR_CLK_FREQ;
+
+ while (get_delta(start) < us) {
+ /* do nothing */
+ }
+}
+
+static void dfc_clear_nddb()
+{
+ NDCR &= ~NDCR_ND_RUN;
+ wait_us(CFG_NAND_OTHER_TO);
+}
+
+/* wait_event with timeout */
+static unsigned long dfc_wait_event(unsigned long event)
+{
+ unsigned long ndsr, timeout, start = OSCR;
+
+ if(!event)
+ return 0xff000000;
+ else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
+ timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
+ else
+ timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ;
+
+ while(1) {
+ ndsr = NDSR;
+ if(ndsr & event) {
+ NDSR |= event;
+ break;
+ }
+ if(get_delta(start) > timeout) {
+ DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event);
+ return 0xff000000;
+ }
+
+ }
+ return ndsr;
+}
+
+/* we don't always wan't to do this */
+static void dfc_new_cmd()
+{
+ int retry = 0;
+ unsigned long status;
+
+ while(retry++ <= CFG_NAND_SENDCMD_RETRY) {
+ /* Clear NDSR */
+ NDSR = 0xFFF;
+
+ /* set NDCR[NDRUN] */
+ if(!(NDCR & NDCR_ND_RUN))
+ NDCR |= NDCR_ND_RUN;
+
+ status = dfc_wait_event(NDSR_WRCMDREQ);
+
+ if(status & NDSR_WRCMDREQ)
+ return;
+
+ DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
+ dfc_clear_nddb();
+ }
+ DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
+}
+
+/* this function is called after Programm and Erase Operations to
+ * check for success or failure */
+static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
+{
+ unsigned long ndsr=0, event=0;
+
+ /* mk@tbd set appropriate timeouts */
+ /* if (state == FL_ERASING) */
+ /* timeo = CFG_HZ * 400; */
+ /* else */
+ /* timeo = CFG_HZ * 20; */
+ if(state == FL_WRITING) {
+ event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
+ } else if(state == FL_ERASING) {
+ event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
+ }
+
+ ndsr = dfc_wait_event(event);
+
+ if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
+ return(0x1); /* Status Read error */
+ return 0;
+}
+
+/* cmdfunc send commands to the DFC */
+static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
+ int column, int page_addr)
+{
+ /* register struct nand_chip *this = mtd->priv; */
+ unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
+
+ /* clear the ugly byte read buffer */
+ bytes_read = -1;
+ read_buf = 0;
+
+ switch (command) {
+ case NAND_CMD_READ0:
+ DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
+ dfc_new_cmd();
+ ndcb0 = (NAND_CMD_READ0 | (4<<16));
+ column >>= 1; /* adjust for 16 bit bus */
+ ndcb1 = (((column>>1) & 0xff) |
+ ((page_addr<<8) & 0xff00) |
+ ((page_addr<<8) & 0xff0000) |
+ ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
+ event = NDSR_RDDREQ;
+ goto write_cmd;
+ case NAND_CMD_READ1:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
+ goto end;
+ case NAND_CMD_READOOB:
+ DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
+ goto end;
+ case NAND_CMD_READID:
+ dfc_new_cmd();
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
+ ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
+ event = NDSR_RDDREQ;
+ goto write_cmd;
+ case NAND_CMD_PAGEPROG:
+ /* sent as a multicommand in NAND_CMD_SEQIN */
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
+ goto end;
+ case NAND_CMD_ERASE1:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
+ dfc_new_cmd();
+ ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
+ ndcb1 = (page_addr & 0x00ffffff);
+ goto write_cmd;
+ case NAND_CMD_ERASE2:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
+ goto end;
+ case NAND_CMD_SEQIN:
+ /* send PAGE_PROG command(0x1080) */
+ dfc_new_cmd();
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
+ ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
+ column >>= 1; /* adjust for 16 bit bus */
+ ndcb1 = (((column>>1) & 0xff) |
+ ((page_addr<<8) & 0xff00) |
+ ((page_addr<<8) & 0xff0000) |
+ ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
+ event = NDSR_WRDREQ;
+ goto write_cmd;
+ case NAND_CMD_STATUS:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
+ dfc_new_cmd();
+ ndcb0 = NAND_CMD_STATUS | (4<<21);
+ event = NDSR_RDDREQ;
+ goto write_cmd;
+ case NAND_CMD_RESET:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
+ ndcb0 = NAND_CMD_RESET | (5<<21);
+ event = NDSR_CS0_CMDD;
+ goto write_cmd;
+ default:
+ printk("dfc_cmdfunc: error, unsupported command.\n");
+ goto end;
+ }
+
+ write_cmd:
+ NDCB0 = ndcb0;
+ NDCB0 = ndcb1;
+ NDCB0 = ndcb2;
+
+ /* wait_event: */
+ dfc_wait_event(event);
+ end:
+ return;
+}
+
+static void dfc_gpio_init()
+{
+ DFC_DEBUG2("Setting up DFC GPIO's.\n");
+
+ /* no idea what is done here, see zylonite.c */
+ GPIO4 = 0x1;
+
+ DF_ALE_WE1 = 0x00000001;
+ DF_ALE_WE2 = 0x00000001;
+ DF_nCS0 = 0x00000001;
+ DF_nCS1 = 0x00000001;
+ DF_nWE = 0x00000001;
+ DF_nRE = 0x00000001;
+ DF_IO0 = 0x00000001;
+ DF_IO8 = 0x00000001;
+ DF_IO1 = 0x00000001;
+ DF_IO9 = 0x00000001;
+ DF_IO2 = 0x00000001;
+ DF_IO10 = 0x00000001;
+ DF_IO3 = 0x00000001;
+ DF_IO11 = 0x00000001;
+ DF_IO4 = 0x00000001;
+ DF_IO12 = 0x00000001;
+ DF_IO5 = 0x00000001;
+ DF_IO13 = 0x00000001;
+ DF_IO6 = 0x00000001;
+ DF_IO14 = 0x00000001;
+ DF_IO7 = 0x00000001;
+ DF_IO15 = 0x00000001;
+
+ DF_nWE = 0x1901;
+ DF_nRE = 0x1901;
+ DF_CLE_NOE = 0x1900;
+ DF_ALE_WE1 = 0x1901;
+ DF_INT_RnB = 0x1900;
+}
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand_new.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for accesing device ready/busy line
+ * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
+ * only be provided if a hardware ECC is available
+ * - eccmode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ * read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ * nand_scan about special functionality. See the defines for further
+ * explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+void board_nand_init(struct nand_chip *nand)
+{
+ unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
+
+ /* set up GPIO Control Registers */
+ dfc_gpio_init();
+
+ /* turn on the NAND Controller Clock (104 MHz @ D0) */
+ CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
+
+#undef CFG_TIMING_TIGHT
+#ifndef CFG_TIMING_TIGHT
+ tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tCH);
+ tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tCS);
+ tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tWH);
+ tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tWP);
+ tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tRH);
+ tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tRP);
+ tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tR);
+ tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tWHR);
+ tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tAR);
+#else /* this is the tight timing */
+
+ tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
+ DFC_MAX_tCH);
+ tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
+ DFC_MAX_tCS);
+ tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
+ DFC_MAX_tWH);
+ tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
+ DFC_MAX_tWP);
+ tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
+ DFC_MAX_tRH);
+ tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
+ DFC_MAX_tRP);
+ tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
+ DFC_MAX_tR);
+ tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
+ DFC_MAX_tWHR);
+ tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
+ DFC_MAX_tAR);
+#endif /* CFG_TIMING_TIGHT */
+
+
+ DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
+
+ /* tRP value is split in the register */
+ if(tRP & (1 << 4)) {
+ tRP_high = 1;
+ tRP &= ~(1 << 4);
+ } else {
+ tRP_high = 0;
+ }
+
+ NDTR0CS0 = (tCH << 19) |
+ (tCS << 16) |
+ (tWH << 11) |
+ (tWP << 8) |
+ (tRP_high << 6) |
+ (tRH << 3) |
+ (tRP << 0);
+
+ NDTR1CS0 = (tR << 16) |
+ (tWHR << 4) |
+ (tAR << 0);
+
+ /* If it doesn't work (unlikely) think about:
+ * - ecc enable
+ * - chip select don't care
+ * - read id byte count
+ *
+ * Intentionally enabled by not setting bits:
+ * - dma (DMA_EN)
+ * - page size = 512
+ * - cs don't care, see if we can enable later!
+ * - row address start position (after second cycle)
+ * - pages per block = 32
+ * - ND_RDY : clears command buffer
+ */
+ /* NDCR_NCSX | /\* Chip select busy don't care *\/ */
+
+ NDCR = (NDCR_SPARE_EN | /* use the spare area */
+ NDCR_DWIDTH_C | /* 16bit DFC data bus width */
+ NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
+ (2 << 16) | /* read id count = 7 ???? mk@tbd */
+ NDCR_ND_ARB_EN | /* enable bus arbiter */
+ NDCR_RDYM | /* flash device ready ir masked */
+ NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
+ NDCR_CS1_PAGEDM |
+ NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
+ NDCR_CS1_CMDDM |
+ NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
+ NDCR_CS1_BBDM |
+ NDCR_DBERRM | /* double bit error ir masked */
+ NDCR_SBERRM | /* single bit error ir masked */
+ NDCR_WRDREQM | /* write data request ir masked */
+ NDCR_RDDREQM | /* read data request ir masked */
+ NDCR_WRCMDREQM); /* write command request ir masked */
+
+
+ /* wait 10 us due to cmd buffer clear reset */
+ /* wait(10); */
+
+
+ nand->hwcontrol = dfc_hwcontrol;
+/* nand->dev_ready = dfc_device_ready; */
+ nand->eccmode = NAND_ECC_SOFT;
+ nand->chip_delay = NAND_DELAY_US;
+ nand->options = NAND_BUSWIDTH_16;
+ nand->waitfunc = dfc_wait;
+ nand->read_byte = dfc_read_byte;
+ nand->write_byte = dfc_write_byte;
+ nand->read_word = dfc_read_word;
+ nand->write_word = dfc_write_word;
+ nand->read_buf = dfc_read_buf;
+ nand->write_buf = dfc_write_buf;
+
+ nand->cmdfunc = dfc_cmdfunc;
+ nand->autooob = &delta_oob;
+ nand->badblock_pattern = &delta_bbt_descr;
+}
+
+#else
+ #error "U-Boot legacy NAND support not available for Monahans DFC."
+#endif
+#endif
diff --git a/board/delta/u-boot.lds b/board/delta/u-boot.lds
new file mode 100644
index 0000000..f010239
--- /dev/null
+++ b/board/delta/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/pxa/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h
index 73dcd5c..13aebbd 100644
--- a/board/mcc200/mt48lc8m32b2-6-7.h
+++ b/board/mcc200/mt48lc8m32b2-6-7.h
@@ -6,7 +6,7 @@
/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x008d0000 // CL-3 BURST-8 -> Mode Register—MBAR + 0x0100
-#define SDRAM_CONTROL 0x504f0000 // Control Register—MBAR + 0x0104
-#define SDRAM_CONFIG1 0xc2222900 // Delays between commands -> Configuration Register 1—MBAR + 0x0108
-#define SDRAM_CONFIG2 0x88c70000 // Delays between commands -> Configuration Register 2—MBAR + 0x010C
+#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */
+#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */
+#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */
+#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */
diff --git a/board/zylonite/Makefile b/board/zylonite/Makefile
new file mode 100644
index 0000000..999647f
--- /dev/null
+++ b/board/zylonite/Makefile
@@ -0,0 +1,48 @@
+
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := zylonite.o flash.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/zylonite/config.mk b/board/zylonite/config.mk
new file mode 100644
index 0000000..09b0f71
--- /dev/null
+++ b/board/zylonite/config.mk
@@ -0,0 +1,4 @@
+#TEXT_BASE = 0x0
+#TEXT_BASE = 0xa1700000
+#TEXT_BASE = 0xa3080000
+TEXT_BASE = 0xa3008000
diff --git a/board/zylonite/flash.c b/board/zylonite/flash.c
new file mode 100644
index 0000000..883c1ba
--- /dev/null
+++ b/board/zylonite/flash.c
@@ -0,0 +1,434 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH ushort
+#define FLASH_PORT_WIDTHV vu_short
+#define SWAP(x) __swab16(x)
+#else
+#define FLASH_PORT_WIDTH ulong
+#define FLASH_PORT_WIDTHV vu_long
+#define SWAP(x) __swab32(x)
+#endif
+
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+#if 0
+ int i;
+ ulong size = 0;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ switch (i) {
+ case 0:
+ flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+ flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+ break;
+ case 1:
+ flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+ flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+ break;
+ default:
+ panic ("configured too many flash banks!\n");
+ break;
+ }
+ size += flash_info[i].size;
+ }
+
+ /* Protect monitor and environment sectors
+ */
+ flash_protect ( FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE + monitor_flash_len - 1,
+ &flash_info[0] );
+
+ flash_protect ( FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+
+ return size;
+#endif
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+ info->protect[i] = 0;
+ }
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL:
+ printf ("INTEL ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F128J3A:
+ printf ("28F128J3A\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+ return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+ volatile FPW value;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr[0x5555] = (FPW) 0x00AA00AA;
+ addr[0x2AAA] = (FPW) 0x00550055;
+ addr[0x5555] = (FPW) 0x00900090;
+
+ mb ();
+ value = addr[0];
+
+ switch (value) {
+
+ case (FPW) INTEL_MANUFACT:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
+ return (0); /* no or unknown flash */
+ }
+
+ mb ();
+ value = addr[1]; /* device ID */
+
+ switch (value) {
+
+ case (FPW) INTEL_ID_28F128J3A:
+ info->flash_id += FLASH_28F128J3A;
+ info->sector_count = 128;
+ info->size = 0x02000000;
+ break; /* => 16 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ break;
+ }
+
+ if (info->sector_count > CFG_MAX_FLASH_SECT) {
+ printf ("** ERROR: sector count %d > max (%d) **\n",
+ info->sector_count, CFG_MAX_FLASH_SECT);
+ info->sector_count = CFG_MAX_FLASH_SECT;
+ }
+
+ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong type, start, last;
+ int rcode = 0;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ type = (info->flash_id & FLASH_VENDMASK);
+ if ((type != FLASH_MAN_INTEL)) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ start = get_timer (0);
+ last = start;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ FPWV *addr = (FPWV *) (info->start[sect]);
+ FPW status;
+
+ printf ("Erasing sector %2d ... ", sect);
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked ();
+
+ *addr = (FPW) 0x00500050; /* clear status register */
+ *addr = (FPW) 0x00200020; /* erase setup */
+ *addr = (FPW) 0x00D000D0; /* erase confirm */
+
+ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = (FPW) 0x00B000B0; /* suspend erase */
+ *addr = (FPW) 0x00FF00FF; /* reset to read mode */
+ rcode = 1;
+ break;
+ }
+ }
+
+ *addr = 0x00500050; /* clear status register cmd. */
+ *addr = 0x00FF00FF; /* resest to read mode */
+
+ printf (" done\n");
+ }
+ }
+ return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp;
+ FPW data;
+ int count, i, l, rc, port_width;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return 4;
+ }
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+ wp = (addr & ~1);
+ port_width = 2;
+#else
+ wp = (addr & ~3);
+ port_width = 4;
+#endif
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < port_width && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ count = 0;
+ while (cnt >= port_width) {
+ data = 0;
+ for (i = 0; i < port_width; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ cnt -= port_width;
+ if (count++ > 0x800) {
+ spin_wheel ();
+ count = 0;
+ }
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+ FPWV *addr = (FPWV *) dest;
+ ulong status;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ *addr = (FPW) 0x00400040; /* write setup */
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked ();
+
+ /* wait while polling the status register */
+ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+ if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+ *addr = (FPW) 0x00FF00FF; /* restore read mode */
+ return (1);
+ }
+ }
+
+ *addr = (FPW) 0x00FF00FF; /* restore read mode */
+
+ return (0);
+}
+
+void inline spin_wheel (void)
+{
+ static int p = 0;
+ static char w[] = "\\/-";
+
+ printf ("\010%c", w[p]);
+ (++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/zylonite/lowlevel_init.S b/board/zylonite/lowlevel_init.S
new file mode 100644
index 0000000..c3bb4eb
--- /dev/null
+++ b/board/zylonite/lowlevel_init.S
@@ -0,0 +1,371 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE: .long CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+.macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+.endm
+
+
+.macro wait time
+ ldr r2, =OSCR
+ mov r3, #0
+ str r3, [r2]
+0:
+ ldr r3, [r2]
+ cmp r3, \time
+ bls 0b
+.endm
+
+/*
+ * Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+ /* Set up GPIO pins first ----------------------------------------- */
+ mov r10, lr
+
+ /* Configure GPIO Pins 41 - 48 as UART1 / altern. Fkt. 2 */
+ ldr r0, =0x40E10438 @ GPIO41 FFRXD
+ ldr r1, =0x802
+ str r1, [r0]
+
+ ldr r0, =0x40E1043C @ GPIO42 FFTXD
+ ldr r1, =0x802
+ str r1, [r0]
+
+ ldr r0, =0x40E10440 @ GPIO43 FFCTS
+ ldr r1, =0x802
+ str r1, [r0]
+
+ ldr r0, =0x40E10444 @ GPIO 44 FFDCD
+ ldr r1, =0x802
+ str r1, [r0]
+
+ ldr r0, =0x40E10448 @ GPIO 45 FFDSR
+ ldr r1, =0x802
+ str r1, [r0]
+
+ ldr r0, =0x40E1044C @ GPIO 46 FFRI
+ ldr r1, =0x802
+ str r1, [r0]
+
+ ldr r0, =0x40E10450 @ GPIO 47 FFDTR
+ ldr r1, =0x802
+ str r1, [r0]
+
+ ldr r0, =0x40E10454 @ GPIO 48
+ ldr r1, =0x802
+ str r1, [r0]
+
+ /* tebrandt - ASCR, clear the RDH bit */
+ ldr r0, =ASCR
+ ldr r1, [r0]
+ bic r1, r1, #0x80000000
+ str r1, [r0]
+
+ /* ---------------------------------------------------------------- */
+ /* Enable memory interface */
+ /* */
+ /* The sequence below is based on the recommended init steps */
+ /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+ /* Chapter 10. */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 1: Wait for at least 200 microsedonds to allow internal */
+ /* clocks to settle. Only necessary after hard reset... */
+ /* FIXME: can be optimized later */
+ /* ---------------------------------------------------------------- */
+
+ /* mk: replaced with wait macro */
+/* ldr r3, =OSCR /\* reset the OS Timer Count to zero *\/ */
+/* mov r2, #0 */
+/* str r2, [r3] */
+/* ldr r4, =0x300 /\* really 0x2E1 is about 200usec, *\/ */
+/* /\* so 0x300 should be plenty *\/ */
+/* 1: */
+/* ldr r2, [r3] */
+/* cmp r4, r2 */
+/* bgt 1b */
+ wait #300
+
+mem_init:
+
+ /* configure the MEMCLKCFG register */
+ ldr r1, =MEMCLKCFG
+ ldr r2, =0x00010001
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set CSADRCFG[0] to data flash SRAM mode */
+ ldr r1, =CSADRCFG0
+ ldr r2, =0x00320809
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set CSADRCFG[1] to data flash SRAM mode */
+ ldr r1, =CSADRCFG1
+ ldr r2, =0x00320809
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set MSC 0 register for SRAM memory */
+ ldr r1, =MSC0
+ ldr r2, =0x11191119
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set CSADRCFG[2] to data flash SRAM mode */
+ ldr r1, =CSADRCFG2
+ ldr r2, =0x00320809
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set CSADRCFG[3] to VLIO mode */
+ ldr r1, =CSADRCFG3
+ ldr r2, =0x0032080B
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set MSC 1 register for VLIO memory */
+ ldr r1, =MSC1
+ ldr r2, =0x123C1119
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+#if 0
+ /* This does not work in Zylonite. -SC */
+ ldr r0, =0x15fffff0
+ ldr r1, =0xb10b
+ str r1, [r0]
+ str r1, [r0, #4]
+#endif
+
+ /* Configure ACCR Register */
+ ldr r0, =ACCR @ ACCR
+ ldr r1, =0x0180b108
+ str r1, [r0]
+ ldr r1, [r0]
+
+ /* Configure MDCNFG Register */
+ ldr r0, =MDCNFG @ MDCNFG
+ ldr r1, =0x403
+ str r1, [r0]
+ ldr r1, [r0]
+
+ /* Perform Resistive Compensation by configuring RCOMP register */
+ ldr r1, =RCOMP @ RCOMP
+ ldr r2, =0x000000ff
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure MDMRS Register for SDCS0 */
+ ldr r1, =MDMRS @ MDMRS
+ ldr r2, =0x60000023
+ ldr r3, [r1]
+ orr r2, r2, r3
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure MDMRS Register for SDCS1 */
+ ldr r1, =MDMRS @ MDMRS
+ ldr r2, =0xa0000023
+ ldr r3, [r1]
+ orr r2, r2, r3
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure MDREFR */
+ ldr r1, =MDREFR @ MDREFR
+ ldr r2, =0x00000006
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure EMPI */
+ ldr r1, =EMPI @ EMPI
+ ldr r2, =0x80000000
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Hardware DDR Read-Strobe Delay Calibration */
+ ldr r0, =DDR_HCAL @ DDR_HCAL
+ ldr r1, =0x803ffc07 @ the offset is correct? -SC
+ str r1, [r0]
+ wait #5
+ ldr r1, [r0]
+
+ /* Here we assume the hardware calibration alwasy be successful. -SC */
+ /* Set DMCEN bit in MDCNFG Register */
+ ldr r0, =MDCNFG @ MDCNFG
+ ldr r1, [r0]
+ orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
+ str r1, [r0]
+
+ /* scrub/init SDRAM if enabled/present */
+/* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */
+/* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */
+/* mov r8,r12 /\* save DRAM size (mk: why???) *\/ */
+ ldr r8, =0xa0000000 /* base address of SDRAM (CFG_DRAM_BASE) */
+ ldr r9, =0x04000000 /* size of memory to scrub (CFG_DRAM_SIZE) */
+ mov r0, #0 /* scrub with 0x0000:0000 */
+ mov r1, #0
+ mov r2, #0
+ mov r3, #0
+ mov r4, #0
+ mov r5, #0
+ mov r6, #0
+ mov r7, #0
+10: /* fastScrubLoop */
+ subs r9, r9, #32 /* 32 bytes/line */
+ stmia r8!, {r0-r7}
+ beq 15f
+ b 10b
+
+15:
+ /* Mask all interrupts */
+ mov r1, #0
+ mcr p6, 0, r1, c1, c0, 0 @ ICMR
+
+ /* Disable software and data breakpoints */
+ mov r0, #0
+ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
+ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
+ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /* Enable all debug functionality */
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 /* dcsr */
+
+ /* We are finished with Intel's memory controller initialisation */
+
+ /* ---------------------------------------------------------------- */
+ /* End lowlevel_init */
+ /* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+ mov pc, lr
+
+/*
+@********************************************************************************
+@ DDR calibration
+@
+@ This function is used to calibrate DQS delay lines.
+@ Monahans supports three ways to do it. One is software
+@ calibration. Two is hardware calibration. Three is hybrid
+@ calibration.
+@
+@ TBD
+@ -SC
+ddr_calibration:
+
+ @ Case 1: Write the correct delay value once
+ @ Configure DDR_SCAL Register
+ ldr r0, =DDR_SCAL @ DDR_SCAL
+q ldr r1, =0xaf2f2f2f
+ str r1, [r0]
+ ldr r1, [r0]
+*/
+/* @ Case 2: Software Calibration
+ @ Write test pattern to memory
+ ldr r5, =0x0faf0faf @ Data Pattern
+ ldr r4, =0xa0000000 @ DDR ram
+ str r5, [r4]
+
+ mov r1, =0x0 @ delay count
+ mov r6, =0x0
+ mov r7, =0x0
+ddr_loop1:
+ add r1, r1, =0x1
+ cmp r1, =0xf
+ ble end_loop
+ mov r3, r1
+ mov r0, r1, lsl #30
+ orr r3, r3, r0
+ mov r0, r1, lsl #22
+ orr r3, r3, r0
+ mov r0, r1, lsl #14
+ orr r3, r3, r0
+ orr r3, r3, =0x80000000
+ ldr r2, =DDR_SCAL
+ str r3, [r2]
+
+ ldr r2, [r4]
+ cmp r2, r5
+ bne ddr_loop1
+ mov r6, r1
+ddr_loop2:
+ add r1, r1, =0x1
+ cmp r1, =0xf
+ ble end_loop
+ mov r3, r1
+ mov r0, r1, lsl #30
+ orr r3, r3, r0
+ mov r0, r1, lsl #22
+ orr r3, r3, r0
+ mov r0, r1, lsl #14
+ orr r3, r3, r0
+ orr r3, r3, =0x80000000
+ ldr r2, =DDR_SCAL
+ str r3, [r2]
+
+ ldr r2, [r4]
+ cmp r2, r5
+ be ddr_loop2
+ mov r7, r2
+
+ add r3, r6, r7
+ lsr r3, r3, =0x1
+ mov r0, r1, lsl #30
+ orr r3, r3, r0
+ mov r0, r1, lsl #22
+ orr r3, r3, r0
+ mov r0, r1, lsl #14
+ orr r3, r3, r0
+ orr r3, r3, =0x80000000
+ ldr r2, =DDR_SCAL
+
+end_loop:
+
+ @ Case 3: Hardware Calibratoin
+ ldr r0, =DDR_HCAL @ DDR_HCAL
+ ldr r1, =0x803ffc07 @ the offset is correct? -SC
+ str r1, [r0]
+ wait #5
+ ldr r1, [r0]
+ mov pc, lr
+*/
diff --git a/board/zylonite/u-boot.lds b/board/zylonite/u-boot.lds
new file mode 100644
index 0000000..f010239
--- /dev/null
+++ b/board/zylonite/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/pxa/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/board/zylonite/zylonite.c b/board/zylonite/zylonite.c
new file mode 100644
index 0000000..e618ab9
--- /dev/null
+++ b/board/zylonite/zylonite.c
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of Lubbock-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setenv("stdout", "serial");
+ setenv("stderr", "serial");
+ return 0;
+}
+
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+ return 0;
+}
diff --git a/config.mk b/config.mk
index d85ac36..aef099e 100644
--- a/config.mk
+++ b/config.mk
@@ -131,6 +131,15 @@ else
CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes
endif
+ifdef WILD_WILD_WEST
+CFLAGS := $(CPPFLAGS) -Werror
+endif
+
+ifdef NO_JUMP
+CFLAGS := $(CPPFLAGS) -fno-schedule-insns -fno-schedule-insns2
+endif
+
+
# avoid trigraph warnings while parsing pci.h (produced by NIOS gcc-2.9)
# this option have to be placed behind -Wall -- that's why it is here
ifeq ($(ARCH),nios)
diff --git a/cpu/pxa/config.mk b/cpu/pxa/config.mk
index fb810ca..f30a1fe 100644
--- a/cpu/pxa/config.mk
+++ b/cpu/pxa/config.mk
@@ -33,4 +33,5 @@ PLATFORM_CPPFLAGS += -march=armv5 -mtune=xscale
#
# ========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+# for gcc-3x: PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c
index d1551dd..b33d674 100644
--- a/cpu/pxa/cpu.c
+++ b/cpu/pxa/cpu.c
@@ -143,6 +143,7 @@ int dcache_status (void)
return 0; /* always off */
}
+#ifndef CONFIG_CPU_MONAHANS
void set_GPIO_mode(int gpio_mode)
{
int gpio = gpio_mode & GPIO_MD_MASK_NR;
@@ -160,3 +161,4 @@ void set_GPIO_mode(int gpio_mode)
gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
}
+#endif /* CONFIG_CPU_MONAHANS */
diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c
index cedebfe..9bf2a7c 100644
--- a/cpu/pxa/serial.c
+++ b/cpu/pxa/serial.c
@@ -54,7 +54,11 @@ void serial_setbrg (void)
hang ();
#ifdef CONFIG_FFUART
+#ifdef CONFIG_CPU_MONAHANS
+ CKENA |= CKENA_22_FFUART;
+#else
CKEN |= CKEN6_FFUART;
+#endif /* CONFIG_CPU_MONAHANS */
FFIER = 0; /* Disable for now */
FFFCR = 0; /* No fifos enabled */
@@ -68,7 +72,11 @@ void serial_setbrg (void)
FFIER = IER_UUE; /* Enable FFUART */
#elif defined(CONFIG_BTUART)
+#ifdef CONFIG_CPU_MONAHANS
+ CKENA |= CKENA_21_BTUART;
+#else
CKEN |= CKEN7_BTUART;
+#endif /* CONFIG_CPU_MONAHANS */
BTIER = 0;
BTFCR = 0;
@@ -82,7 +90,11 @@ void serial_setbrg (void)
BTIER = IER_UUE; /* Enable BFUART */
#elif defined(CONFIG_STUART)
+#ifdef CONFIG_CPU_MONAHANS
+ CKENA |= CKENA_23_STUART;
+#else
CKEN |= CKEN5_STUART;
+#endif /* CONFIG_CPU_MONAHANS */
STIER = 0;
STFCR = 0;
diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S
index a8cc080..9541c9b 100644
--- a/cpu/pxa/start.S
+++ b/cpu/pxa/start.S
@@ -6,8 +6,8 @@
* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
* Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
- * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
- * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
+ * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -30,6 +30,7 @@
#include <config.h>
#include <version.h>
+#include <asm/arch/pxa-regs.h>
.globl _start
_start: b reset
@@ -116,13 +117,13 @@ reset:
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
+ cmp r0, r1 /* don't reloc during debug */
+ beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
+ sub r2, r3, r2 /* r2 <- size of armboot */
+ add r2, r0, r2 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
@@ -134,19 +135,19 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
+ ldr r0, _bss_start /* find start of bss segment */
+ ldr r1, _bss_end /* stop here */
+ mov r2, #0x00000000 /* clear */
-clbss_l:str r2, [r0] /* clear loop... */
+clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
ble clbss_l
@@ -164,8 +165,16 @@ _start_armboot: .word start_armboot
/* - setup memory timing */
/* */
/****************************************************************************/
+/* mk@tbd: Fix this! */
+#ifdef CONFIG_CPU_MONAHANS
+#undef ICMR
+#undef OSMR3
+#undef OSCR
+#undef OWER
+#undef OIER
+#endif
-/* Interrupt-Controller base address */
+/* Interrupt-Controller base address */
IC_BASE: .word 0x40d00000
#define ICMR 0x04
@@ -180,7 +189,7 @@ OSTIMER_BASE: .word 0x40a00000
#define OWER 0x18
#define OIER 0x1C
-/* Clock Manager Registers */
+/* Clock Manager Registers */
#ifdef CFG_CPUSPEED
CC_BASE: .word 0x41300000
#define CCCR 0x00
@@ -189,25 +198,44 @@ cpuspeed: .word CFG_CPUSPEED
#error "You have to define CFG_CPUSPEED!!"
#endif
-
- /* RS: ??? */
- .macro CPWAIT
- mrc p15,0,r0,c2,c0,0
- mov r0,r0
+ /* takes care the CP15 update has taken place */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
sub pc,pc,#4
.endm
-
cpu_init_crit:
/* mask all IRQs */
+#ifndef CONFIG_CPU_MONAHANS
ldr r0, IC_BASE
mov r1, #0x00
str r1, [r0, #ICMR]
+#else
+ /* Step 1 - Enable CP6 permission */
+ mrc p15, 0, r1, c15, c1, 0 @ read CPAR
+ orr r1, r1, #0x40
+ mcr p15, 0, r1, c15, c1, 0
+ CPWAIT r1
+
+ /* Step 2 - Mask ICMR & ICMR2 */
+ mov r1, #0
+ mcr p6, 0, r1, c1, c0, 0 @ ICMR
+ mcr p6, 0, r1, c7, c0, 0 @ ICMR2
+
+ /* turn off all clocks but the ones we will definitly require */
+ ldr r1, =CKENA
+ ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
+ str r2, [r1]
+ ldr r1, =CKENB
+ ldr r2, =(CKENB_6_IRQ)
+ str r2, [r1]
+#endif
-#if defined(CFG_CPUSPEED)
-
- /* set clock speed */
+#ifndef CONFIG_CPU_MONAHANS
+#ifdef CFG_CPUSPEED
+ /* set clock speed tbd@mk: required for monahans? */
ldr r0, CC_BASE
ldr r1, cpuspeed
str r1, [r0, #CCCR]
@@ -215,7 +243,9 @@ cpu_init_crit:
mcr p14, 0, r0, c6, c0, 0
setspeed_done:
-#endif
+
+#endif /* CFG_CPUSPEED */
+#endif /* CONFIG_CPU_MONAHANS */
/*
* before relocating, we have to setup RAM timing
@@ -227,19 +257,21 @@ setspeed_done:
mov lr, ip
/* Memory interfaces are working. Disable MMU and enable I-cache. */
+ /* mk: hmm, this is not in the monahans docs, leave it now but
+ * check here if it doesn't work :-) */
ldr r0, =0x2001 /* enable access to all coproc. */
mcr p15, 0, r0, c15, c1, 0
- CPWAIT
+ CPWAIT r0
mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
- CPWAIT
+ CPWAIT r0
mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
- CPWAIT
+ CPWAIT r0
mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
- CPWAIT
+ CPWAIT r0
/* Enable the Icache */
/*
@@ -292,7 +324,7 @@ setspeed_done:
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
@@ -419,17 +451,17 @@ fiq:
#endif
/****************************************************************************/
-/* */
+/* */
/* Reset function: the PXA250 doesn't have a reset function, so we have to */
-/* perform a watchdog timeout for a soft reset. */
-/* */
+/* perform a watchdog timeout for a soft reset. */
+/* */
/****************************************************************************/
.align 5
.globl reset_cpu
- /* FIXME: this code is PXA250 specific. How is this handled on */
- /* other XScale processors? */
+ /* FIXME: this code is PXA250 specific. How is this handled on */
+ /* other XScale processors? */
reset_cpu:
@@ -437,13 +469,13 @@ reset_cpu:
ldr r0, OSTIMER_BASE
ldr r1, [r0, #OWER]
- orr r1, r1, #0x0001 /* bit0: WME */
+ orr r1, r1, #0x0001 /* bit0: WME */
str r1, [r0, #OWER]
/* OS timer does only wrap every 1165 seconds, so we have to set */
- /* the match register as well. */
+ /* the match register as well. */
- ldr r1, [r0, #OSCR] /* read OS timer */
+ ldr r1, [r0, #OSCR] /* read OS timer */
add r1, r1, #0x800 /* let OSMR3 match after */
add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
str r1, [r0, #OSMR3]
diff --git a/drivers/nand/nand_base.c b/drivers/nand/nand_base.c
index b2cd62e..d91d90b 100644
--- a/drivers/nand/nand_base.c
+++ b/drivers/nand/nand_base.c
@@ -1724,6 +1724,8 @@ static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len,
numpages = min (totalpages, ppblock);
page &= this->pagemask;
startpage = page;
+ oob = 0;
+ this->oobdirty = 1;
oobbuf = nand_prepare_oobbuf (mtd, eccbuf, oobsel,
autoplace, numpages);
/* Check, if we cross a chip boundary */
@@ -2148,13 +2150,14 @@ int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbb
instr->state = MTD_ERASING;
while (len) {
+#ifndef NAND_ALLOW_ERASE_ALL
/* Check if we have a bad block, we do not erase bad blocks ! */
if (nand_block_checkbad(mtd, ((loff_t) page) << this->page_shift, 0, allowbbt)) {
printk (KERN_WARNING "nand_erase: attempt to erase a bad block at page 0x%08x\n", page);
instr->state = MTD_ERASE_FAILED;
goto erase_exit;
}
-
+#endif
/* Invalidate the page cache, if we erase the block which contains
the current cached page */
if (page <= this->pagebuf && this->pagebuf < (page + pages_per_block))
diff --git a/drivers/smc91111.c b/drivers/smc91111.c
index 060da8f..7941244 100644
--- a/drivers/smc91111.c
+++ b/drivers/smc91111.c
@@ -72,7 +72,7 @@
#define NO_AUTOPROBE
-#define SMC_DEBUG 0
+#define SMC_DEBUG 3
#if SMC_DEBUG > 1
static const char version[] =
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index 3ff1d26..c8c479a 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -92,6 +92,10 @@ typedef struct { volatile u32 offset[4096]; } __regbase;
# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
# else
# define __REG(x) (x)
+# ifdef CONFIG_CPU_MONAHANS /* Hack to make this work with mona's pxa-regs.h */
+# define __REG_2(x) (x)
+# define __REG_3(x) (x)
+# endif
# endif
#endif /* UBOOT_REG_FIX */
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 41d37d7..83ae5e3 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -33,12 +33,21 @@ typedef void (*ExcpHndlr) (void) ;
/*
* PXA Chip selects
*/
+#ifdef CONFIG_CPU_MONAHANS
+#define PXA_CS0_PHYS 0x00000000 /* for both small and large same start */
+#define PXA_CS1_PHYS 0x04000000 /* Small partition start address (64MB) */
+#define PXA_CS1_LPHYS 0x30000000 /* Large partition start address (256MB) */
+#define PXA_CS2_PHYS 0x10000000 /* (64MB) */
+#define PXA_CS3_PHYS 0x14000000 /* (64MB) */
+#define PXA_PCMCIA_PHYS 0x20000000 /* (256MB) */
+#else
#define PXA_CS0_PHYS 0x00000000
#define PXA_CS1_PHYS 0x04000000
#define PXA_CS2_PHYS 0x08000000
#define PXA_CS3_PHYS 0x0C000000
#define PXA_CS4_PHYS 0x10000000
#define PXA_CS5_PHYS 0x14000000
+#endif /* CONFIG_CPU_MONAHANS */
/*
* Personal Computer Memory Card International Association (PCMCIA) sockets
@@ -49,10 +58,12 @@ typedef void (*ExcpHndlr) (void) ;
#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
+#ifndef CONFIG_CPU_MONAHANS /* Monahans supports only one slot */
#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
+#endif
#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
@@ -72,10 +83,12 @@ typedef void (*ExcpHndlr) (void) ;
#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
+#ifndef CONFIG_CPU_MONAHANS /* Monahans supports only one slot */
#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
+#endif
/*
* DMA Controller
@@ -96,6 +109,24 @@ typedef void (*ExcpHndlr) (void) ;
#define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
#define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
#define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
+#ifdef CONFIG_CPU_MONAHANS
+#define DCSR16 __REG(0x40000040) /* DMA Control / Status Register for Channel 16 */
+#define DCSR17 __REG(0x40000044) /* DMA Control / Status Register for Channel 17 */
+#define DCSR18 __REG(0x40000048) /* DMA Control / Status Register for Channel 18 */
+#define DCSR19 __REG(0x4000004c) /* DMA Control / Status Register for Channel 19 */
+#define DCSR20 __REG(0x40000050) /* DMA Control / Status Register for Channel 20 */
+#define DCSR21 __REG(0x40000054) /* DMA Control / Status Register for Channel 21 */
+#define DCSR22 __REG(0x40000058) /* DMA Control / Status Register for Channel 22 */
+#define DCSR23 __REG(0x4000005c) /* DMA Control / Status Register for Channel 23 */
+#define DCSR24 __REG(0x40000060) /* DMA Control / Status Register for Channel 24 */
+#define DCSR25 __REG(0x40000064) /* DMA Control / Status Register for Channel 25 */
+#define DCSR26 __REG(0x40000068) /* DMA Control / Status Register for Channel 26 */
+#define DCSR27 __REG(0x4000006c) /* DMA Control / Status Register for Channel 27 */
+#define DCSR28 __REG(0x40000070) /* DMA Control / Status Register for Channel 28 */
+#define DCSR29 __REG(0x40000074) /* DMA Control / Status Register for Channel 29 */
+#define DCSR30 __REG(0x40000078) /* DMA Control / Status Register for Channel 30 */
+#define DCSR31 __REG(0x4000007c) /* DMA Control / Status Register for Channel 31 */
+#endif /* CONFIG_CPU_MONAHANS */
#define DCSR(x) __REG2(0x40000000, (x) << 2)
@@ -103,7 +134,7 @@ typedef void (*ExcpHndlr) (void) ;
#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_PXA27X) || defined (CONFIG_CPU_MONAHANS)
#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
@@ -813,15 +844,47 @@ typedef void (*ExcpHndlr) (void) ;
/*
* OS Timer & Match Registers
*/
-#define OSMR0 __REG(0x40A00000) /* */
-#define OSMR1 __REG(0x40A00004) /* */
-#define OSMR2 __REG(0x40A00008) /* */
-#define OSMR3 __REG(0x40A0000C) /* */
+#define OSMR0 __REG(0x40A00000) /* OS Timer Match Register 0 */
+#define OSMR1 __REG(0x40A00004) /* OS Timer Match Register 1 */
+#define OSMR2 __REG(0x40A00008) /* OS Timer Match Register 2 */
+#define OSMR3 __REG(0x40A0000C) /* OS Timer Match Register 3 */
#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
#define OSSR __REG(0x40A00014) /* OS Timer Status Register */
#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
+#ifdef CONFIG_CPU_MONAHANS
+#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register 4 */
+#define OSCR5 __REG(0x40A00044) /* OS Timer Counter Register 5 */
+#define OSCR6 __REG(0x40A00048) /* OS Timer Counter Register 6 */
+#define OSCR7 __REG(0x40A0004C) /* OS Timer Counter Register 7 */
+#define OSCR8 __REG(0x40A00050) /* OS Timer Counter Register 8 */
+#define OSCR9 __REG(0x40A00054) /* OS Timer Counter Register 9 */
+#define OSCR10 __REG(0x40A00058) /* OS Timer Counter Register 10 */
+#define OSCR11 __REG(0x40A0005C) /* OS Timer Counter Register 11 */
+
+#define OSMR4 __REG(0x40A00080) /* OS Timer Match Register 4 */
+#define OSMR5 __REG(0x40A00084) /* OS Timer Match Register 5 */
+#define OSMR6 __REG(0x40A00088) /* OS Timer Match Register 6 */
+#define OSMR7 __REG(0x40A0008C) /* OS Timer Match Register 7 */
+#define OSMR8 __REG(0x40A00090) /* OS Timer Match Register 8 */
+#define OSMR9 __REG(0x40A00094) /* OS Timer Match Register 9 */
+#define OSMR10 __REG(0x40A00098) /* OS Timer Match Register 10 */
+#define OSMR11 __REG(0x40A0009C) /* OS Timer Match Register 11 */
+
+#define OMCR4 __REG(0x40A000C0) /* OS Match Control Register 4 */
+#define OMCR5 __REG(0x40A000C4) /* OS Match Control Register 5 */
+#define OMCR6 __REG(0x40A000C8) /* OS Match Control Register 6 */
+#define OMCR7 __REG(0x40A000CC) /* OS Match Control Register 7 */
+#define OMCR8 __REG(0x40A000D0) /* OS Match Control Register 8 */
+#define OMCR9 __REG(0x40A000D4) /* OS Match Control Register 9 */
+#define OMCR10 __REG(0x40A000D8) /* OS Match Control Register 10 */
+#define OMCR11 __REG(0x40A000DC) /* OS Match Control Register 11 */
+
+#define OSCR_CLK_FREQ 3.250 /* MHz */
+#endif /* CONFIG_CPU_MONAHANS */
+
+#define OSSR_M4 (1 << 4) /* Match status channel 4 */
#define OSSR_M3 (1 << 3) /* Match status channel 3 */
#define OSSR_M2 (1 << 2) /* Match status channel 2 */
#define OSSR_M1 (1 << 1) /* Match status channel 1 */
@@ -829,6 +892,7 @@ typedef void (*ExcpHndlr) (void) ;
#define OWER_WME (1 << 0) /* Watchdog Match Enable */
+#define OIER_E4 (1 << 4) /* Interrupt enable channel 4 */
#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
@@ -855,6 +919,19 @@ typedef void (*ExcpHndlr) (void) ;
#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
+#ifdef CONFIG_CPU_MONAHANS
+#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */
+/* Missing: 32 Interrupt priority registers */
+/* mk@tbd: These are the same as beneath for PXA27x: maybe can be
+ * merged if GPIO Stuff is same too. */
+#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
+#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
+#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
+#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
+#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
+/* Missing: 2 Interrupt priority registers */
+#endif /* CONFIG_CPU_MONAHANS */
+
/*
* General Purpose I/O
*/
@@ -886,12 +963,287 @@ typedef void (*ExcpHndlr) (void) ;
#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
+#ifdef CONFIG_CPU_MONAHANS
+#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
+#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
+#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
+#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
+#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
+#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
+#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
+
+#define GSDR0 __REG(0x40E00400) /* Bit-wise Set of GPDR[31:0] */
+#define GSDR1 __REG(0x40E00404) /* Bit-wise Set of GPDR[63:32] */
+#define GSDR2 __REG(0x40E00408) /* Bit-wise Set of GPDR[95:64] */
+#define GSDR3 __REG(0x40E0040C) /* Bit-wise Set of GPDR[127:96] */
+
+#define GCDR0 __REG(0x40E00420) /* Bit-wise Clear of GPDR[31:0] */
+#define GCDR1 __REG(0x40E00424) /* Bit-wise Clear of GPDR[63:32] */
+#define GCDR2 __REG(0x40E00428) /* Bit-wise Clear of GPDR[95:64] */
+#define GCDR3 __REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */
+
+#define GSRER0 __REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */
+#define GSRER1 __REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */
+#define GSRER2 __REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */
+#define GSRER3 __REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */
+
+#define GCRER0 __REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */
+#define GCRER1 __REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */
+#define GCRER2 __REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */
+#define GCRER3 __REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */
+
+#define GSFER0 __REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */
+#define GSFER1 __REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */
+#define GSFER2 __REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */
+#define GSFER3 __REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */
+
+#define GCFER0 __REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */
+#define GCFER1 __REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */
+#define GCFER2 __REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */
+#define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
+
+#define GSDR(x) __REG2(0x40E00400, ((x) & 0x60) >> 3)
+#define GCDR(x) __REG2(0x40300420, ((x) & 0x60) >> 3)
+
+/* Multi-funktion Pin Registers, uncomplete, only:
+ * - GPIO
+ * - Data Flash DF_* pins defined.
+ */
+#define GPIO0 __REG(0x40e10124)
+#define GPIO1 __REG(0x40e10128)
+#define GPIO2 __REG(0x40e1012c)
+#define GPIO3 __REG(0x40e10130)
+#define GPIO4 __REG(0x40e10134)
+#define nXCVREN __REG(0x40e10138)
+
+#define DF_CLE_NOE __REG(0x40e10204)
+#define DF_ALE_WE1 __REG(0x40e10208)
+
+#define DF_SCLK_E __REG(0x40e10210)
+#define nBE0 __REG(0x40e10214)
+#define nBE1 __REG(0x40e10218)
+#define DF_ALE_WE2 __REG(0x40e1021c)
+#define DF_INT_RnB __REG(0x40e10220)
+#define DF_nCS0 __REG(0x40e10224)
+#define DF_nCS1 __REG(0x40e10228)
+#define DF_nWE __REG(0x40e1022c)
+#define DF_nRE __REG(0x40e10230)
+#define nLUA __REG(0x40e10234)
+#define nLLA __REG(0x40e10238)
+#define DF_ADDR0 __REG(0x40e1023c)
+#define DF_ADDR1 __REG(0x40e10240)
+#define DF_ADDR2 __REG(0x40e10244)
+#define DF_ADDR3 __REG(0x40e10248)
+#define DF_IO0 __REG(0x40e1024c)
+#define DF_IO8 __REG(0x40e10250)
+#define DF_IO1 __REG(0x40e10254)
+#define DF_IO9 __REG(0x40e10258)
+#define DF_IO2 __REG(0x40e1025c)
+#define DF_IO10 __REG(0x40e10260)
+#define DF_IO3 __REG(0x40e10264)
+#define DF_IO11 __REG(0x40e10268)
+#define DF_IO4 __REG(0x40e1026c)
+#define DF_IO12 __REG(0x40e10270)
+#define DF_IO5 __REG(0x40e10274)
+#define DF_IO13 __REG(0x40e10278)
+#define DF_IO6 __REG(0x40e1027c)
+#define DF_IO14 __REG(0x40e10280)
+#define DF_IO7 __REG(0x40e10284)
+#define DF_IO15 __REG(0x40e10288)
+
+#define GPIO5 __REG(0x40e1028c)
+#define GPIO6 __REG(0x40e10290)
+#define GPIO7 __REG(0x40e10294)
+#define GPIO8 __REG(0x40e10298)
+#define GPIO9 __REG(0x40e1029c)
+
+#define GPIO11 __REG(0x40e102a0)
+#define GPIO12 __REG(0x40e102a4)
+#define GPIO13 __REG(0x40e102a8)
+#define GPIO14 __REG(0x40e102ac)
+#define GPIO15 __REG(0x40e102b0)
+#define GPIO16 __REG(0x40e102b4)
+#define GPIO17 __REG(0x40e102b8)
+#define GPIO18 __REG(0x40e102bc)
+#define GPIO19 __REG(0x40e102c0)
+#define GPIO20 __REG(0x40e102c4)
+#define GPIO21 __REG(0x40e102c8)
+#define GPIO22 __REG(0x40e102cc)
+#define GPIO23 __REG(0x40e102d0)
+#define GPIO24 __REG(0x40e102d4)
+#define GPIO25 __REG(0x40e102d8)
+#define GPIO26 __REG(0x40e102dc)
+
+#define GPIO27 __REG(0x40e10400)
+#define GPIO28 __REG(0x40e10404)
+#define GPIO29 __REG(0x40e10408)
+#define GPIO30 __REG(0x40e1040c)
+#define GPIO31 __REG(0x40e10410)
+#define GPIO32 __REG(0x40e10414)
+#define GPIO33 __REG(0x40e10418)
+#define GPIO34 __REG(0x40e1041c)
+#define GPIO35 __REG(0x40e10420)
+#define GPIO36 __REG(0x40e10424)
+#define GPIO37 __REG(0x40e10428)
+#define GPIO38 __REG(0x40e1042c)
+#define GPIO39 __REG(0x40e10430)
+#define GPIO40 __REG(0x40e10434)
+#define GPIO41 __REG(0x40e10438)
+#define GPIO42 __REG(0x40e1043c)
+#define GPIO43 __REG(0x40e10440)
+#define GPIO44 __REG(0x40e10444)
+#define GPIO45 __REG(0x40e10448)
+#define GPIO46 __REG(0x40e1044c)
+#define GPIO47 __REG(0x40e10450)
+#define GPIO48 __REG(0x40e10454)
+
+#define GPIO10 __REG(0x40e10458)
+
+#define GPIO49 __REG(0x40e1045c)
+#define GPIO50 __REG(0x40e10460)
+#define GPIO51 __REG(0x40e10464)
+#define GPIO52 __REG(0x40e10468)
+#define GPIO53 __REG(0x40e1046c)
+#define GPIO54 __REG(0x40e10470)
+#define GPIO55 __REG(0x40e10474)
+#define GPIO56 __REG(0x40e10478)
+#define GPIO57 __REG(0x40e1047c)
+#define GPIO58 __REG(0x40e10480)
+#define GPIO59 __REG(0x40e10484)
+#define GPIO60 __REG(0x40e10488)
+#define GPIO61 __REG(0x40e1048c)
+#define GPIO62 __REG(0x40e10490)
+
+#define GPIO6_2 __REG(0x40e10494)
+#define GPIO7_2 __REG(0x40e10498)
+#define GPIO8_2 __REG(0x40e1049c)
+#define GPIO9_2 __REG(0x40e104a0)
+#define GPIO10_2 __REG(0x40e104a4)
+#define GPIO11_2 __REG(0x40e104a8)
+#define GPIO12_2 __REG(0x40e104ac)
+#define GPIO13_2 __REG(0x40e104b0)
+
+#define GPIO63 __REG(0x40e104b4)
+#define GPIO64 __REG(0x40e104b8)
+#define GPIO65 __REG(0x40e104bc)
+#define GPIO66 __REG(0x40e104c0)
+#define GPIO67 __REG(0x40e104c4)
+#define GPIO68 __REG(0x40e104c8)
+#define GPIO69 __REG(0x40e104cc)
+#define GPIO70 __REG(0x40e104d0)
+#define GPIO71 __REG(0x40e104d4)
+#define GPIO72 __REG(0x40e104d8)
+#define GPIO73 __REG(0x40e104dc)
+
+#define GPIO14_2 __REG(0x40e104e0)
+#define GPIO15_2 __REG(0x40e104e4)
+#define GPIO16_2 __REG(0x40e104e8)
+#define GPIO17_2 __REG(0x40e104ec)
+
+#define GPIO74 __REG(0x40e104f0)
+#define GPIO75 __REG(0x40e104f4)
+#define GPIO76 __REG(0x40e104f8)
+#define GPIO77 __REG(0x40e104fc)
+#define GPIO78 __REG(0x40e10500)
+#define GPIO79 __REG(0x40e10504)
+#define GPIO80 __REG(0x40e10508)
+#define GPIO81 __REG(0x40e1050c)
+#define GPIO82 __REG(0x40e10510)
+#define GPIO83 __REG(0x40e10514)
+#define GPIO84 __REG(0x40e10518)
+#define GPIO85 __REG(0x40e1051c)
+#define GPIO86 __REG(0x40e10520)
+#define GPIO87 __REG(0x40e10524)
+#define GPIO88 __REG(0x40e10528)
+#define GPIO89 __REG(0x40e1052c)
+#define GPIO90 __REG(0x40e10530)
+#define GPIO91 __REG(0x40e10534)
+#define GPIO92 __REG(0x40e10538)
+#define GPIO93 __REG(0x40e1053c)
+#define GPIO94 __REG(0x40e10540)
+#define GPIO95 __REG(0x40e10544)
+#define GPIO96 __REG(0x40e10548)
+#define GPIO97 __REG(0x40e1054c)
+#define GPIO98 __REG(0x40e10550)
+
+#define GPIO99 __REG(0x40e10600)
+#define GPIO100 __REG(0x40e10604)
+#define GPIO101 __REG(0x40e10608)
+#define GPIO102 __REG(0x40e1060c)
+#define GPIO103 __REG(0x40e10610)
+#define GPIO104 __REG(0x40e10614)
+#define GPIO105 __REG(0x40e10618)
+#define GPIO106 __REG(0x40e1061c)
+#define GPIO107 __REG(0x40e10620)
+#define GPIO108 __REG(0x40e10624)
+#define GPIO109 __REG(0x40e10628)
+#define GPIO110 __REG(0x40e1062c)
+#define GPIO111 __REG(0x40e10630)
+#define GPIO112 __REG(0x40e10634)
+
+#define GPIO113 __REG(0x40e10638)
+#define GPIO114 __REG(0x40e1063c)
+#define GPIO115 __REG(0x40e10640)
+#define GPIO116 __REG(0x40e10644)
+#define GPIO117 __REG(0x40e10648)
+#define GPIO118 __REG(0x40e1064c)
+#define GPIO119 __REG(0x40e10650)
+#define GPIO120 __REG(0x40e10654)
+#define GPIO121 __REG(0x40e10658)
+#define GPIO122 __REG(0x40e1065c)
+#define GPIO123 __REG(0x40e10660)
+#define GPIO124 __REG(0x40e10664)
+#define GPIO125 __REG(0x40e10668)
+#define GPIO126 __REG(0x40e1066c)
+#define GPIO127 __REG(0x40e10670)
+
+#define GPIO0_2 __REG(0x40e10674)
+#define GPIO1_2 __REG(0x40e10678)
+#define GPIO2_2 __REG(0x40e1067c)
+#define GPIO3_2 __REG(0x40e10680)
+#define GPIO4_2 __REG(0x40e10684)
+#define GPIO5_2 __REG(0x40e10688)
+
+/* MFPR Bit Definitions, see 4-10, Vol. 1 */
+#define PULL_SEL 0x8000
+#define PULLUP_EN 0x4000
+#define PULLDOWN_EN 0x2000
+
+#define DRIVE_FAST_1mA 0x0
+#define DRIVE_FAST_2mA 0x400
+#define DRIVE_FAST_3mA 0x800
+#define DRIVE_FAST_4mA 0xC00
+#define DRIVE_SLOW_6mA 0x1000
+#define DRIVE_FAST_6mA 0x1400
+#define DRIVE_SLOW_10mA 0x1800
+#define DRIVE_FAST_10mA 0x1C00
+
+#define SLEEP_SEL 0x200
+#define SLEEP_DATA 0x100
+#define SLEEP_OE_N 0x80
+#define EDGE_CLEAR 0x40
+#define EDGE_FALL_EN 0x20
+#define EDGE_RISE_EN 0x10
+
+#define AF_SEL_0 0x0 /* Alternate function 0 (reset state) */
+#define AF_SEL_1 0x1 /* Alternate function 1 */
+#define AF_SEL_2 0x2 /* Alternate function 2 */
+#define AF_SEL_3 0x3 /* Alternate function 3 */
+#define AF_SEL_4 0x4 /* Alternate function 4 */
+#define AF_SEL_5 0x5 /* Alternate function 5 */
+#define AF_SEL_6 0x6 /* Alternate function 6 */
+#define AF_SEL_7 0x7 /* Alternate function 7 */
+
+
+#else /* CONFIG_CPU_MONAHANS */
+
#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO 80 */
+#endif /* CONFIG_CPU_MONAHANS */
/* More handy macros. The argument is a literal GPIO number. */
@@ -1142,6 +1494,79 @@ typedef void (*ExcpHndlr) (void) ;
/*
* Power Manager
*/
+#ifdef CONFIG_CPU_MONAHANS
+
+#define ASCR __REG(0x40F40000) /* Application Subsystem Power Status/Control Register */
+#define ARSR __REG(0x40F40004) /* Application Subsystem Reset Status Register */
+#define AD3ER __REG(0x40F40008) /* Application Subsystem D3 state Wakeup Enable Register */
+#define AD3SR __REG(0x40F4000C) /* Application Subsystem D3 state Wakeup Status Register */
+#define AD2D0ER __REG(0x40F40010) /* Application Subsystem D2 to D0 state Wakeup Enable Register */
+#define AD2D0SR __REG(0x40F40014) /* Application Subsystem D2 to D0 state Wakeup Status Register */
+#define AD2D1ER __REG(0x40F40018) /* Application Subsystem D2 to D1 state Wakeup Enable Register */
+#define AD2D1SR __REG(0x40F4001C) /* Application Subsystem D2 to D1 state Wakeup Status Register */
+#define AD1D0ER __REG(0x40F40020) /* Application Subsystem D1 to D0 state Wakeup Enable Register */
+#define AD1D0SR __REG(0x40F40024) /* Application Subsystem D1 to D0 state Wakeup Status Register */
+#define ASDCNT __REG(0x40F40028) /* Application Subsystem SRAM Drowsy Count Register */
+#define AD3R __REG(0x40F40030) /* Application Subsystem D3 State Configuration Register */
+#define AD2R __REG(0x40F40034) /* Application Subsystem D2 State Configuration Register */
+#define AD1R __REG(0x40F40038) /* Application Subsystem D1 State Configuration Register */
+
+#define PMCR __REG(0x40F50000) /* Power Manager Control Register */
+#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */
+#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */
+#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */
+#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
+#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
+#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */
+#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
+#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */
+#define PCMD(x) __REG(0x40F50110 + x*4)
+#define PCMD0 __REG(0x40F50110 + 0 * 4)
+#define PCMD1 __REG(0x40F50110 + 1 * 4)
+#define PCMD2 __REG(0x40F50110 + 2 * 4)
+#define PCMD3 __REG(0x40F50110 + 3 * 4)
+#define PCMD4 __REG(0x40F50110 + 4 * 4)
+#define PCMD5 __REG(0x40F50110 + 5 * 4)
+#define PCMD6 __REG(0x40F50110 + 6 * 4)
+#define PCMD7 __REG(0x40F50110 + 7 * 4)
+#define PCMD8 __REG(0x40F50110 + 8 * 4)
+#define PCMD9 __REG(0x40F50110 + 9 * 4)
+#define PCMD10 __REG(0x40F50110 + 10 * 4)
+#define PCMD11 __REG(0x40F50110 + 11 * 4)
+#define PCMD12 __REG(0x40F50110 + 12 * 4)
+#define PCMD13 __REG(0x40F50110 + 13 * 4)
+#define PCMD14 __REG(0x40F50110 + 14 * 4)
+#define PCMD15 __REG(0x40F50110 + 15 * 4)
+#define PCMD16 __REG(0x40F50110 + 16 * 4)
+#define PCMD17 __REG(0x40F50110 + 17 * 4)
+#define PCMD18 __REG(0x40F50110 + 18 * 4)
+#define PCMD19 __REG(0x40F50110 + 19 * 4)
+#define PCMD20 __REG(0x40F50110 + 20 * 4)
+#define PCMD21 __REG(0x40F50110 + 21 * 4)
+#define PCMD22 __REG(0x40F50110 + 22 * 4)
+#define PCMD23 __REG(0x40F50110 + 23 * 4)
+#define PCMD24 __REG(0x40F50110 + 24 * 4)
+#define PCMD25 __REG(0x40F50110 + 25 * 4)
+#define PCMD26 __REG(0x40F50110 + 26 * 4)
+#define PCMD27 __REG(0x40F50110 + 27 * 4)
+#define PCMD28 __REG(0x40F50110 + 28 * 4)
+#define PCMD29 __REG(0x40F50110 + 29 * 4)
+#define PCMD30 __REG(0x40F50110 + 30 * 4)
+#define PCMD31 __REG(0x40F50110 + 31 * 4)
+
+#define PCMD_MBC (1<<12)
+#define PCMD_DCE (1<<11)
+#define PCMD_LC (1<<10)
+#define PCMD_SQC (3<<8) /* only 00 and 01 are valid */
+
+#define PVCR_FVC (0x1 << 28)
+#define PVCR_VCSA (0x1<<14)
+#define PVCR_CommandDelay (0xf80)
+#define PVCR_ReadPointer (0x01f00000)
+#define PVCR_SlaveAddress (0x7f)
+
+#else /* ifdef CONFIG_CPU_MONAHANS */
+
#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
@@ -1225,6 +1650,8 @@ typedef void (*ExcpHndlr) (void) ;
#define RCSR_WDR (1 << 1) /* Watchdog Reset */
#define RCSR_HWR (1 << 0) /* Hardware Reset */
+#endif /* CONFIG_CPU_MONAHANS */
+
/*
* SSP Serial Port Registers
*/
@@ -1259,6 +1686,67 @@ typedef void (*ExcpHndlr) (void) ;
/*
* Core Clock
*/
+
+#if defined(CONFIG_CPU_MONAHANS)
+#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
+#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */
+#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */
+#define CKENA __REG(0x4134000C) /* A Clock Enable Register */
+#define CKENB __REG(0x41340010) /* B Clock Enable Register */
+#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */
+
+#define ACCR_SMC_MASK 0x03800000 /* Static Memory Controller Frequency Select */
+#define ACCR_SRAM_MASK 0x000c0000 /* SRAM Controller Frequency Select */
+#define ACCR_FC_MASK 0x00030000 /* Frequency Change Frequency Select */
+#define ACCR_HSIO_MASK 0x0000c000 /* High Speed IO Frequency Select */
+#define ACCR_DDR_MASK 0x00003000 /* DDR Memory Controller Frequency Select */
+#define ACCR_XN_MASK 0x00000700 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#define ACCR_XL_MASK 0x0000001f /* Crystal Frequency to Memory Frequency Multiplier */
+#define ACCR_XPDIS (1 << 31)
+#define ACCR_SPDIS (1 << 30)
+#define ACCR_13MEND1 (1 << 27)
+#define ACCR_D0CS (1 << 26)
+#define ACCR_13MEND2 (1 << 21)
+#define ACCR_PCCE (1 << 11)
+
+#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */
+#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */
+#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */
+#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */
+#define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */
+#define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */
+#define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */
+#define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */
+#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */
+#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */
+#define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */
+#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */
+#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */
+#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */
+#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */
+#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */
+#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */
+#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */
+#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */
+#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */
+#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */
+#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */
+#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */
+#define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */
+#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */
+#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */
+#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */
+#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */
+
+#define CKENB_8_1WIRE ((1 << 8) + 32) /* One Wire Interface Unit Clock Enable */
+#define CKENB_7_GPIO ((1 << 7) + 32) /* GPIO Clock Enable */
+#define CKENB_6_IRQ ((1 << 6) + 32) /* Interrupt Controller Clock Enable */
+#define CKENB_4_I2C ((1 << 4) + 32) /* I2C Unit Clock Enable */
+#define CKENB_1_PWM1 ((1 << 1) + 32) /* PWM2 & PWM3 Clock Enable */
+#define CKENB_0_PWM0 ((1 << 0) + 32) /* PWM0 & PWM1 Clock Enable */
+
+#else /* if defined CONFIG_CPU_MONAHANS */
+
#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
#define CKEN __REG(0x41300004) /* Clock Enable Register */
#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
@@ -1318,6 +1806,8 @@ typedef void (*ExcpHndlr) (void) ;
#define CCCR_N30 (0x6 << 7)
#endif
+#endif /* CONFIG_CPU_MONAHANS */
+
/*
* LCD
*/
@@ -1502,6 +1992,163 @@ typedef void (*ExcpHndlr) (void) ;
/*
* Memory controller
*/
+
+#ifdef CONFIG_CPU_MONAHANS
+/* Static Memory Controller Registers */
+#define MSC0 __REG_2(0x4A000008) /* Static Memory Control Register 0 */
+#define MSC1 __REG_2(0x4A00000C) /* Static Memory Control Register 1 */
+#define MECR __REG_2(0x4A000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define SXCNFG __REG_2(0x4A00001C) /* Synchronous Static Memory Control Register */
+#define MCMEM0 __REG_2(0x4A000028) /* Card interface Common Memory Space Socket 0 Timing */
+#define MCATT0 __REG_2(0x4A000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define MCIO0 __REG_2(0x4A000038) /* Card interface I/O Space Socket 0 Timing Configuration */
+#define MEMCLKCFG __REG_2(0x4A000068) /* SCLK speed configuration */
+#define CSADRCFG0 __REG_2(0x4A000080) /* Address Configuration for chip select 0 */
+#define CSADRCFG1 __REG_2(0x4A000084) /* Address Configuration for chip select 1 */
+#define CSADRCFG2 __REG_2(0x4A000088) /* Address Configuration for chip select 2 */
+#define CSADRCFG3 __REG_2(0x4A00008C) /* Address Configuration for chip select 3 */
+#define CSADRCFG_P __REG_2(0x4A000090) /* Address Configuration for pcmcia card interface */
+#define CSMSADRCFG __REG_2(0x4A0000A0) /* Master Address Configuration Register */
+#define CLK_RET_DEL __REG_2(0x4A0000B0) /* Delay line and mux selects for return data latching for sync. flash */
+#define ADV_RET_DEL __REG_2(0x4A0000B4) /* Delay line and mux selects for return data latching for sync. flash */
+
+/* Dynamic Memory Controller Registers */
+#define MDCNFG __REG_2(0x48100000) /* SDRAM Configuration Register 0 */
+#define MDREFR __REG_2(0x48100004) /* SDRAM Refresh Control Register */
+#define FLYCNFG __REG_2(0x48100020) /* Fly-by DMA DVAL[1:0] polarities */
+#define MDMRS __REG_2(0x48100040) /* MRS value to be written to SDRAM */
+#define DDR_SCAL __REG_2(0x48100050) /* Software Delay Line Calibration/Configuration for external DDR memory. */
+#define DDR_HCAL __REG_2(0x48100060) /* Hardware Delay Line Calibration/Configuration for external DDR memory. */
+#define DDR_WCAL __REG_2(0x48100068) /* DDR Write Strobe Calibration Register */
+#define DMCIER __REG_2(0x48100070) /* Dynamic MC Interrupt Enable Register. */
+#define DMCISR __REG_2(0x48100078) /* Dynamic MC Interrupt Status Register. */
+#define DDR_DLS __REG_2(0x48100080) /* DDR Delay Line Value Status register for external DDR memory. */
+#define EMPI __REG_2(0x48100090) /* EMPI Control Register */
+#define RCOMP __REG_2(0x48100100)
+#define PAD_MA __REG_2(0x48100110)
+#define PAD_MDMSB __REG_2(0x48100114)
+#define PAD_MDLSB __REG_2(0x48100118)
+#define PAD_DMEM __REG_2(0x4810011c)
+#define PAD_SDCLK __REG_2(0x48100120)
+#define PAD_SDCS __REG_2(0x48100124)
+#define PAD_SMEM __REG_2(0x48100128)
+#define PAD_SCLK __REG_2(0x4810012C)
+#define TAI __REG_2(0x48100F00) /* TAI Tavor Address Isolation Register */
+
+/* Some frequently used bits */
+#define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */
+#define MDCNFG_DMCEN 0x40000000 /* Enable Dynamic Memory Controller */
+#define MDCNFG_HWFREQ 0x20000000 /* Hardware Frequency Change Calibration */
+#define MDCNFG_DTYPE 0x400 /* SDRAM Type: 1=DDR SDRAM */
+
+#define MDCNFG_DTC_0 0x0 /* Timing Category of SDRAM */
+#define MDCNFG_DTC_1 0x100
+#define MDCNFG_DTC_2 0x200
+#define MDCNFG_DTC_3 0x300
+
+#define MDCNFG_DRAC_12 0x0 /* Number of Row Access Bits */
+#define MDCNFG_DRAC_13 0x20
+#define MDCNFG_DRAC_14 0x40
+
+#define MDCNFG_DCAC_9 0x0 /* Number of Column Acess Bits */
+#define MDCNFG_DCAC_10 0x08
+#define MDCNFG_DCAC_11 0x10
+
+#define MDCNFG_DBW_16 0x4 /* SDRAM Data Bus width 16bit */
+#define MDCNFG_DCSE1 0x2 /* SDRAM CS 1 Enable */
+#define MDCNFG_DCSE0 0x1 /* SDRAM CS 0 Enable */
+
+
+/* Data Flash Controller Registers */
+
+#define NDCR __REG(0x43100000) /* Data Flash Control register */
+#define NDTR0CS0 __REG(0x43100004) /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
+/* #define NDTR0CS1 __REG(0x43100008) /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */
+#define NDTR1CS0 __REG(0x4310000C) /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
+/* #define NDTR1CS1 __REG(0x43100010) /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */
+#define NDSR __REG(0x43100014) /* Data Controller Status Register */
+#define NDPCR __REG(0x43100018) /* Data Controller Page Count Register */
+#define NDBDR0 __REG(0x4310001C) /* Data Controller Bad Block Register 0 */
+#define NDBDR1 __REG(0x43100020) /* Data Controller Bad Block Register 1 */
+#define NDDB __REG(0x43100040) /* Data Controller Data Buffer */
+#define NDCB0 __REG(0x43100048) /* Data Controller Command Buffer0 */
+#define NDCB1 __REG(0x4310004C) /* Data Controller Command Buffer1 */
+#define NDCB2 __REG(0x43100050) /* Data Controller Command Buffer2 */
+
+#define NDCR_SPARE_EN (0x1<<31)
+#define NDCR_ECC_EN (0x1<<30)
+#define NDCR_DMA_EN (0x1<<29)
+#define NDCR_ND_RUN (0x1<<28)
+#define NDCR_DWIDTH_C (0x1<<27)
+#define NDCR_DWIDTH_M (0x1<<26)
+#define NDCR_PAGE_SZ (0x3<<24)
+#define NDCR_NCSX (0x1<<23)
+#define NDCR_ND_STOP (0x1<<22)
+/* reserved:
+ * #define NDCR_ND_MODE (0x3<<21)
+ * #define NDCR_NAND_MODE 0x0 */
+#define NDCR_CLR_PG_CNT (0x1<<20)
+#define NDCR_CLR_ECC (0x1<<19)
+#define NDCR_RD_ID_CNT (0x7<<16)
+#define NDCR_RA_START (0x1<<15)
+#define NDCR_PG_PER_BLK (0x1<<14)
+#define NDCR_ND_ARB_EN (0x1<<12)
+#define NDCR_RDYM (0x1<<11)
+#define NDCR_CS0_PAGEDM (0x1<<10)
+#define NDCR_CS1_PAGEDM (0x1<<9)
+#define NDCR_CS0_CMDDM (0x1<<8)
+#define NDCR_CS1_CMDDM (0x1<<7)
+#define NDCR_CS0_BBDM (0x1<<6)
+#define NDCR_CS1_BBDM (0x1<<5)
+#define NDCR_DBERRM (0x1<<4)
+#define NDCR_SBERRM (0x1<<3)
+#define NDCR_WRDREQM (0x1<<2)
+#define NDCR_RDDREQM (0x1<<1)
+#define NDCR_WRCMDREQM (0x1)
+
+#define NDSR_RDY (0x1<<11)
+#define NDSR_CS0_PAGED (0x1<<10)
+#define NDSR_CS1_PAGED (0x1<<9)
+#define NDSR_CS0_CMDD (0x1<<8)
+#define NDSR_CS1_CMDD (0x1<<7)
+#define NDSR_CS0_BBD (0x1<<6)
+#define NDSR_CS1_BBD (0x1<<5)
+#define NDSR_DBERR (0x1<<4)
+#define NDSR_SBERR (0x1<<3)
+#define NDSR_WRDREQ (0x1<<2)
+#define NDSR_RDDREQ (0x1<<1)
+#define NDSR_WRCMDREQ (0x1)
+
+#define NDCB0_AUTO_RS (0x1<<25)
+#define NDCB0_CSEL (0x1<<24)
+#define NDCB0_CMD_TYPE (0x7<<21)
+#define NDCB0_NC (0x1<<20)
+#define NDCB0_DBC (0x1<<19)
+#define NDCB0_ADDR_CYC (0x7<<16)
+#define NDCB0_CMD2 (0xff<<8)
+#define NDCB0_CMD1 (0xff)
+#define MCMEM(s) MCMEM0
+#define MCATT(s) MCATT0
+#define MCIO(s) MCIO0
+#define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */
+
+/* Maximum values for NAND Interface Timing Registers in DFC clock
+ * periods */
+#define DFC_MAX_tCH 7
+#define DFC_MAX_tCS 7
+#define DFC_MAX_tWH 7
+#define DFC_MAX_tWP 7
+#define DFC_MAX_tRH 7
+#define DFC_MAX_tRP 15
+#define DFC_MAX_tR 65535
+#define DFC_MAX_tWHR 15
+#define DFC_MAX_tAR 15
+
+#define DFC_CLOCK 104 /* DFC Clock is 104 MHz */
+#define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */
+
+#else /* CONFIG_CPU_MONAHANS */
+
#define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */
#define MDCNFG_OFFSET 0x0
#define MDREFR_OFFSET 0x4
@@ -1573,6 +2220,8 @@ typedef void (*ExcpHndlr) (void) ;
#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
+#endif /* CONFIG_CPU_MONAHANS */
+
/* Interrupt Controller */
#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
diff --git a/include/asm-arm/global_data.h b/include/asm-arm/global_data.h
index c2d5291..0b6c817 100644
--- a/include/asm-arm/global_data.h
+++ b/include/asm-arm/global_data.h
@@ -61,6 +61,11 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
-#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8")
+#undef GCC_4_SCREW_GDP
+#ifdef GCC_4_SCREW_GDP
+# define DECLARE_GLOBAL_DATA_PTR register gd_t* volatile gd asm ("r8");
+#else
+# define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8")
+#endif
#endif /* __ASM_GBL_DATA_H */
diff --git a/include/configs/delta.h b/include/configs/delta.h
new file mode 100644
index 0000000..8e5e612
--- /dev/null
+++ b/include/configs/delta.h
@@ -0,0 +1,288 @@
+/*
+ * Configuation settings for the Delta board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
+#define CONFIG_DELTA 1 /* Delta board */
+
+/* #define CONFIG_LCD 1 */
+#ifdef CONFIG_LCD
+#define CONFIG_SHARP_LM8V31
+#endif
+/* #define CONFIG_MMC 1 */
+#define BOARD_LATE_INIT 1
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#undef TURN_ON_ETHERNET
+#ifdef TURN_ON_ETHERNET
+# define CONFIG_DRIVER_SMC91111 1
+# define CONFIG_SMC91111_BASE 0x14000300
+# define CONFIG_SMC91111_EXT_PHY
+# define CONFIG_SMC_USE_32_BIT
+# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
+#endif
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+/* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */
+#ifdef TURN_ON_ETHERNET
+# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
+#else
+# define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_NAND) \
+ & ~(CFG_CMD_NET | CFG_CMD_FLASH | \
+ CFG_CMD_ENV | CFG_CMD_IMLS))
+#endif
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY -1
+#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
+#define CONFIG_NETMASK 255.255.0.0
+#define CONFIG_IPADDR 192.168.0.21
+#define CONFIG_SERVERIP 192.168.0.250
+#define CONFIG_BOOTCOMMAND "bootm 80000"
+#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_TIMESTAMP
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER 1
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#define CFG_LONGHELP /* undef to save memory */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT "$ " /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_DEVICE_NULLDEV 1
+
+#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */
+
+#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
+
+ /* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* #define CFG_MMC_BASE 0xF0000000 */
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */
+#define PHYS_SDRAM_2 0xa1000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */
+#define PHYS_SDRAM_3 0xa2000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */
+#define PHYS_SDRAM_4 0xa3000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */
+
+#define CFG_DRAM_BASE 0xa0000000 /* at CS0 */
+#define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */
+
+#undef CFG_SKIP_DRAM_SCRUB
+
+/*
+ * NAND Flash
+ */
+/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
+#define CONFIG_NEW_NAND_CODE
+#define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
+#undef CFG_NAND1_BASE
+
+#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define SECTORSIZE 512
+#define NAND_DELAY_US 25 /* mk@tbd: could be 0, I guess */
+
+/* nand timeout values */
+#define CFG_NAND_PROG_ERASE_TO 3000
+#define CFG_NAND_OTHER_TO 100
+#define CFG_NAND_SENDCMD_RETRY 3
+#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
+
+/* NAND Timing Parameters (in ns) */
+#define NAND_TIMING_tCH 10
+#define NAND_TIMING_tCS 0
+#define NAND_TIMING_tWH 20
+#define NAND_TIMING_tWP 40
+
+#define NAND_TIMING_tRH 20
+#define NAND_TIMING_tRP 40
+
+#define NAND_TIMING_tR 11123
+/* #define NAND_TIMING_tWHR 110 */
+#define NAND_TIMING_tWHR 100
+#define NAND_TIMING_tAR 10
+
+/* NAND debugging */
+#define CFG_DFC_DEBUG1 /* usefull */
+#undef CFG_DFC_DEBUG2 /* noisy */
+#undef CFG_DFC_DEBUG3 /* extremly noisy */
+
+#define CONFIG_MTD_DEBUG
+#define CONFIG_MTD_DEBUG_VERBOSE 1
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NO_FLASH 1
+#ifndef CGF_NO_FLASH
+/* these are required by the environment code */
+#define PHYS_FLASH_1 CFG_NAND0_BASE /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x04000000 /* 64 MB */
+#define PHYS_FLASH_BANK_SIZE 0x04000000 /* 64 MB Banks */
+#define PHYS_FLASH_SECT_SIZE (SECTORSIZE*1024) /* KB sectors (x2) */
+#endif
+
+/*
+ * GPIO settings
+ */
+#define CFG_GPSR0_VAL 0x00008000
+#define CFG_GPSR1_VAL 0x00FC0382
+#define CFG_GPSR2_VAL 0x0001FFFF
+#define CFG_GPCR0_VAL 0x00000000
+#define CFG_GPCR1_VAL 0x00000000
+#define CFG_GPCR2_VAL 0x00000000
+#define CFG_GPDR0_VAL 0x0060A800
+#define CFG_GPDR1_VAL 0x00FF0382
+#define CFG_GPDR2_VAL 0x0001C000
+#define CFG_GAFR0_L_VAL 0x98400000
+#define CFG_GAFR0_U_VAL 0x00002950
+#define CFG_GAFR1_L_VAL 0x000A9558
+#define CFG_GAFR1_U_VAL 0x0005AAAA
+#define CFG_GAFR2_L_VAL 0xA0000000
+#define CFG_GAFR2_U_VAL 0x00000002
+
+#define CFG_PSSR_VAL 0x20
+
+/*
+ * Memory settings
+ */
+#define CFG_MSC0_VAL 0x23F223F2
+#define CFG_MSC1_VAL 0x3FF1A441
+#define CFG_MSC2_VAL 0x7FF97FF1
+#define CFG_MDCNFG_VAL 0x00001AC9
+#define CFG_MDREFR_VAL 0x00018018
+#define CFG_MDMRS_VAL 0x00000000
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL 0x00000000
+#define CFG_MCMEM0_VAL 0x00010504
+#define CFG_MCMEM1_VAL 0x00010504
+#define CFG_MCATT0_VAL 0x00010504
+#define CFG_MCATT1_VAL 0x00010504
+#define CFG_MCIO0_VAL 0x00004715
+#define CFG_MCIO1_VAL 0x00004715
+
+#define _LED 0x08000010
+#define LED_BLANK 0x08000040
+
+/*
+ * FLASH and environment organization
+ */
+#ifndef CFG_NO_FLASH
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
+
+
+/* NOTE: many default partitioning schemes assume the kernel starts at the
+ * second sector, not an environment. You have been warned!
+ */
+#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE
+#endif /* #ifndef CFG_NO_FLASH */
+
+#define CFG_ENV_IS_NOWHERE
+/* #define CFG_ENV_IS_IN_NAND 1 */
+#define CFG_ENV_OFFSET 0x40000
+#define CFG_ENV_SIZE 0x4000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h
new file mode 100644
index 0000000..4232d50
--- /dev/null
+++ b/include/configs/zylonite.h
@@ -0,0 +1,256 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the Zylonite board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
+#define CONFIG_ZYLONITE 1 /* Zylonite board */
+
+/* #define CONFIG_LCD 1 */
+#ifdef CONFIG_LCD
+#define CONFIG_SHARP_LM8V31
+#endif
+/* #define CONFIG_MMC 1 */
+#define BOARD_LATE_INIT 1
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#undef TURN_ON_ETHERNET
+#ifdef TURN_ON_ETHERNET
+# define CONFIG_DRIVER_SMC91111 1
+# define CONFIG_SMC91111_BASE 0x14000300
+# define CONFIG_SMC91111_EXT_PHY
+# define CONFIG_SMC_USE_32_BIT
+# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
+#endif
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+/* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */
+#ifdef TURN_ON_ETHERNET
+# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
+#else
+# define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET)
+#endif
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY -1
+#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
+#define CONFIG_NETMASK 255.255.0.0
+#define CONFIG_IPADDR 192.168.0.21
+#define CONFIG_SERVERIP 192.168.0.250
+#define CONFIG_BOOTCOMMAND "bootm 80000"
+#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_TIMESTAMP
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER 1
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#define CFG_LONGHELP /* undef to save memory */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT "$ " /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_DEVICE_NULLDEV 1
+
+#define CFG_MEMTEST_START 0x9c000000 /* memtest works on */
+#define CFG_MEMTEST_END 0x9c400000 /* 4 ... 8 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */
+
+#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
+
+ /* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* #define CFG_MMC_BASE 0xF0000000 */
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
+#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
+#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
+#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
+
+#define CFG_DRAM_BASE 0xa0000000
+#define CFG_DRAM_SIZE 0x04000000
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+#define FPGA_REGS_BASE_PHYSICAL 0x08000000
+
+/*
+ * GPIO settings
+ */
+#define CFG_GPSR0_VAL 0x00008000
+#define CFG_GPSR1_VAL 0x00FC0382
+#define CFG_GPSR2_VAL 0x0001FFFF
+#define CFG_GPCR0_VAL 0x00000000
+#define CFG_GPCR1_VAL 0x00000000
+#define CFG_GPCR2_VAL 0x00000000
+#define CFG_GPDR0_VAL 0x0060A800
+#define CFG_GPDR1_VAL 0x00FF0382
+#define CFG_GPDR2_VAL 0x0001C000
+#define CFG_GAFR0_L_VAL 0x98400000
+#define CFG_GAFR0_U_VAL 0x00002950
+#define CFG_GAFR1_L_VAL 0x000A9558
+#define CFG_GAFR1_U_VAL 0x0005AAAA
+#define CFG_GAFR2_L_VAL 0xA0000000
+#define CFG_GAFR2_U_VAL 0x00000002
+
+#define CFG_PSSR_VAL 0x20
+
+/*
+ * Memory settings
+ */
+#define CFG_MSC0_VAL 0x23F223F2
+#define CFG_MSC1_VAL 0x3FF1A441
+#define CFG_MSC2_VAL 0x7FF97FF1
+#define CFG_MDCNFG_VAL 0x00001AC9
+#define CFG_MDREFR_VAL 0x00018018
+#define CFG_MDMRS_VAL 0x00000000
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL 0x00000000
+#define CFG_MCMEM0_VAL 0x00010504
+#define CFG_MCMEM1_VAL 0x00010504
+#define CFG_MCATT0_VAL 0x00010504
+#define CFG_MCATT1_VAL 0x00010504
+#define CFG_MCIO0_VAL 0x00004715
+#define CFG_MCIO1_VAL 0x00004715
+
+#define _LED 0x08000010
+#define LED_BLANK 0x08000040
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
+
+/* NOTE: many default partitioning schemes assume the kernel starts at the
+ * second sector, not an environment. You have been warned!
+ */
+#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
+#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
+#define CFG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16)
+
+
+/*
+ * FPGA Offsets
+ */
+#define WHOAMI_OFFSET 0x00
+#define HEXLED_OFFSET 0x10
+#define BLANKLED_OFFSET 0x40
+#define DISCRETELED_OFFSET 0x40
+#define CNFG_SWITCHES_OFFSET 0x50
+#define USER_SWITCHES_OFFSET 0x60
+#define MISC_WR_OFFSET 0x80
+#define MISC_RD_OFFSET 0x90
+#define INT_MASK_OFFSET 0xC0
+#define INT_CLEAR_OFFSET 0xD0
+#define GP_OFFSET 0x100
+
+#endif /* __CONFIG_H */
diff --git a/lib_arm/board.c b/lib_arm/board.c
index f7ee9ee..0f3a999 100644
--- a/lib_arm/board.c
+++ b/lib_arm/board.c
@@ -38,6 +38,8 @@
* FIQ Stack: 00ebef7c
*/
+#define DEBUG 1
+
#include <common.h>
#include <command.h>
#include <malloc.h>
@@ -52,6 +54,8 @@
#include "../drivers/lan91c96.h"
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
void nand_init (void);
#endif
@@ -119,8 +123,6 @@ void *sbrk (ptrdiff_t increment)
static int init_baudrate (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
uchar tmp[64]; /* long enough for environment variables */
int i = getenv_r ("baudrate", tmp, sizeof (tmp));
gd->bd->bi_baudrate = gd->baudrate = (i > 0)
@@ -155,7 +157,6 @@ static int display_banner (void)
*/
static int display_dram_config (void)
{
- DECLARE_GLOBAL_DATA_PTR;
int i;
#ifdef DEBUG
@@ -236,8 +237,6 @@ init_fnc_t *init_sequence[] = {
void start_armboot (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
ulong size;
init_fnc_t **init_fnc_ptr;
char *s;
generated by cgit v1.1 at 2024-11-24 01:19:20 +0000