diff options
51 files changed, 1252 insertions, 128 deletions
@@ -356,6 +356,13 @@ The following options need to be configured: Define this option if you want to enable the ICache only when Code runs from RAM. +- 85xx CPU Options: + CONFIG_SYS_FSL_TBCLK_DIV + + Defines the core time base clock divider ratio compared to the + system clock. On most PQ3 devices this is 8, on newer QorIQ + devices it can be 16 or 32. The ratio varies from SoC to Soc. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index e94975a..7b9f773 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -44,6 +44,12 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) puts("Work-around for Erratum SERDES8 enabled\n"); #endif +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) + puts("Work-around for Erratum SERDES9 enabled\n"); +#endif +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005) + puts("Work-around for Erratum SERDES-A005 enabled\n"); +#endif #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) puts("Work-around for Erratum CPU22 enabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index f5b39c0..f863f4a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -234,13 +234,14 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* * Get timebase clock frequency */ +#ifndef CONFIG_SYS_FSL_TBCLK_DIV +#define CONFIG_SYS_FSL_TBCLK_DIV 8 +#endif unsigned long get_tbclk (void) { -#ifdef CONFIG_FSL_CORENET - return (gd->bus_clk + 8) / 16; -#else - return (gd->bus_clk + 4UL)/8UL; -#endif + unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; + + return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 6f256cf..b3da970 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -436,6 +436,23 @@ int cpu_init_r(void) isync(); #endif +#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE + { + ccsr_usb_phy_t *usb_phy1 = + (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; + out_be32(&usb_phy1->usb_enable_override, + CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); + } +#endif +#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE + { + ccsr_usb_phy_t *usb_phy2 = + (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; + out_be32(&usb_phy2->usb_enable_override, + CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); + } +#endif + return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 642f6c5..6e909b5 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -473,6 +473,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_portal(blob, "fsl,bman-portal", "bman-portals", (u64)CONFIG_SYS_BMAN_MEM_PHYS, CONFIG_SYS_BMAN_MEM_SIZE); + fdt_fixup_bportals(blob); #endif #if defined(CONFIG_SYS_QMAN_MEM_PHYS) diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index f58d6d6..741a0f8 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -29,6 +29,7 @@ #include <asm/io.h> #include <asm/processor.h> #include <asm/fsl_law.h> +#include <asm/errno.h> #include "fsl_corenet_serdes.h" static u32 serdes_prtcl_map; @@ -91,7 +92,7 @@ int serdes_get_lane_idx(int lane) return lanes[lane].idx; } -int serdes_get_bank(int lane) +int serdes_get_bank_by_lane(int lane) { return lanes[lane].bank; } @@ -132,6 +133,125 @@ int is_serdes_configured(enum srds_prtcl device) return (1 << device) & serdes_prtcl_map; } +static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device) +{ + int i; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_get_prtcl(prtcl, i) == device) + return i; + } + + return -ENODEV; +} + +/* + * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given + * device. This depends on the current SERDES protocol, as defined in the RCW. + * + * Returns a negative error code if SERDES is disabled or the given device is + * not supported in the current SERDES protocol. + */ +int serdes_get_first_lane(enum srds_prtcl device) +{ + u32 prtcl; + const ccsr_gur_t *gur; + + gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Is serdes enabled at all? */ + if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) + return -ENODEV; + + prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + return __serdes_get_first_lane(prtcl, device); +} + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 +/* + * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given + * SERDES protocol. + * + * Returns a negative error code if the given device is not supported for the + * given SERDES protocol. + */ +static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device) +{ + int lane; + + lane = __serdes_get_first_lane(prtcl, device); + if (unlikely(lane < 0)) + return lane; + + return serdes_get_bank_by_lane(lane); +} + +static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device, + int first) +{ + int lane; + + for (lane = first; lane < SRDS_MAX_LANES; lane++) { + if (serdes_get_prtcl(prtcl, lane) != device) + break; + } + + return lane - first; +} + +static void __serdes_reset_rx(serdes_corenet_t *regs, + uint32_t prtcl, + enum srds_prtcl device) +{ + int lane, idx, first, last; + + lane = __serdes_get_first_lane(prtcl, device); + if (unlikely(lane < 0)) + return; + first = serdes_get_lane_idx(lane); + last = first + __serdes_get_lane_count(prtcl, device, lane); + + /* + * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is + * selected as XAUI to place the lane into reset. + */ + for (idx = first; idx < last; idx++) + clrbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST); + + /* Wait at least 250 ns */ + udelay(1); + + /* + * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is + * selected as XAUI to bring the lane out of reset. + */ + for (idx = first; idx < last; idx++) + setbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST); +} + +void serdes_reset_rx(enum srds_prtcl device) +{ + u32 prtcl; + const ccsr_gur_t *gur; + serdes_corenet_t *regs; + + if (unlikely(device == NONE)) + return; + + gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Is serdes enabled at all? */ + if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) + return; + + regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + __serdes_reset_rx(regs, prtcl, device); +} +#endif + #ifndef CONFIG_SYS_DCSRBAR_PHYS #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ #define CONFIG_SYS_DCSRBAR 0x80000000 @@ -266,6 +386,74 @@ static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur, } #endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005 +/* + * If PCIe is not selected as a protocol for any lanes driven by a given PLL, + * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0. + */ +static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg) +{ + enum srds_prtcl device; + + switch (cfg) { + case 0x13: + case 0x16: + /* + * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL] + * to 0. + */ + clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + break; + case 0x19: + /* + * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and + * SRDSB3PLLCR1[PLLBW_SEL] to 1. + */ + clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + break; + } + + /* + * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI + * before XAUI is initialized. + */ + for (device = XAUI_FM1; device <= XAUI_FM2; device++) { + if (is_serdes_configured(device)) { + int bank = serdes_get_bank_by_device(cfg, device); + + clrbits_be32(®s->bank[bank].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + } + } +} +#endif + +/* + * Wait for the RSTDONE bit to get set, or a one-second timeout. + */ +static void wait_for_rstdone(unsigned int bank) +{ + serdes_corenet_t *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + unsigned long long end_tick; + u32 rstctl; + + /* wait for reset complete or 1-second timeout */ + end_tick = usec2ticks(1000000) + get_ticks(); + do { + rstctl = in_be32(&srds_regs->bank[bank].rstctl); + if (rstctl & SRDS_RSTCTL_RSTDONE) + break; + } while (end_tick > get_ticks()); + + if (!(rstctl & SRDS_RSTCTL_RSTDONE)) + printf("SERDES: timeout resetting bank %u\n", bank); +} + void fsl_serdes_init(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -273,7 +461,6 @@ void fsl_serdes_init(void) serdes_corenet_t *srds_regs; int lane, bank, idx; enum srds_prtcl lane_prtcl; - long long end_tick; int have_bank[SRDS_MAX_BANK] = {}; #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 u32 serdes8_devdisr = 0; @@ -282,6 +469,12 @@ void fsl_serdes_init(void) const char *srds_lpd_arg; size_t arglen; #endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 + enum srds_prtcl device; +#endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */ +#endif char buffer[HWCONFIG_BUFFER_SIZE]; char *buf = NULL; @@ -307,6 +500,17 @@ void fsl_serdes_init(void) #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 /* + * Display a warning if banks two and three are not disabled in the RCW, + * since our work-around for SERDES8 depends on these banks being + * disabled at power-on. + */ +#define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3) + if ((in_be32(&gur->rcwsr[5]) & B2_B3) != B2_B3) { + printf("Warning: SERDES8 requires banks two and " + "three to be disabled in the RCW\n"); + } + + /* * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3 * hwconfig options into the srds_lpd_b[] array. See README.p4080ds * for a description of these options. @@ -325,7 +529,7 @@ void fsl_serdes_init(void) for (lane = 0; lane < SRDS_MAX_LANES; lane++) { enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane); if (serdes_lane_enabled(lane)) { - have_bank[serdes_get_bank(lane)] = 1; + have_bank[serdes_get_bank_by_lane(lane)] = 1; serdes_prtcl_map |= (1 << lane_prtcl); } } @@ -339,11 +543,32 @@ void fsl_serdes_init(void) have_bank[FSL_SRDS_BANK_3] = 1; #endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + /* + * The work-aroud for erratum SERDES-A001 is needed only if bank two + * is disabled and bank three is enabled. + */ + need_serdes_a001 = + !have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3]; +#endif + + /* Power down the banks we're not interested in */ for (bank = 0; bank < SRDS_MAX_BANK; bank++) { if (!have_bank[bank]) { printf("SERDES: bank %d disabled\n", bank + 1); +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + /* + * Erratum SERDES-A001 says bank two needs to be powered + * down after bank three is powered up, so don't power + * down bank two here. + */ + if (!need_serdes_a001 || (bank != FSL_SRDS_BANK_2)) + setbits_be32(&srds_regs->bank[bank].rstctl, + SRDS_RSTCTL_SDPD); +#else setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_SDPD); +#endif } } @@ -369,6 +594,35 @@ void fsl_serdes_init(void) printf("%s ", serdes_prtcl_str[lane_prtcl]); #endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 + /* + * Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for + * each of the SerDes lanes selected as SGMII, XAUI, SRIO, or + * AURORA before the device is initialized. + */ + switch (lane_prtcl) { + case SGMII_FM1_DTSEC1: + case SGMII_FM1_DTSEC2: + case SGMII_FM1_DTSEC3: + case SGMII_FM1_DTSEC4: + case SGMII_FM2_DTSEC1: + case SGMII_FM2_DTSEC2: + case SGMII_FM2_DTSEC3: + case SGMII_FM2_DTSEC4: + case XAUI_FM1: + case XAUI_FM2: + case SRIO1: + case SRIO2: + case AURORA: + clrsetbits_be32(&srds_regs->lane[idx].ttlcr0, + SRDS_TTLCR0_FLT_SEL_MASK, + SRDS_TTLCR0_FLT_SEL_750PPM | + SRDS_TTLCR0_PM_DIS); + default: + break; + } +#endif + #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 switch (lane_prtcl) { case PCIE1: @@ -415,13 +669,12 @@ void fsl_serdes_init(void) FSL_CORENET_DEVDISR2_DTSEC2_4; break; case XAUI_FM1: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | + FSL_CORENET_DEVDISR2_10GEC1; + break; case XAUI_FM2: - if (lane_prtcl == XAUI_FM1) - serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | - FSL_CORENET_DEVDISR2_10GEC1; - else - serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | - FSL_CORENET_DEVDISR2_10GEC2; + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_10GEC2; break; case AURORA: break; @@ -436,9 +689,11 @@ void fsl_serdes_init(void) puts("\n"); #endif - for (idx = 0; idx < SRDS_MAX_BANK; idx++) { - u32 rstctl; +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005 + p4080_erratum_serdes_a005(srds_regs, cfg); +#endif + for (idx = 0; idx < SRDS_MAX_BANK; idx++) { bank = idx; #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 @@ -477,18 +732,30 @@ void fsl_serdes_init(void) /* reset banks for errata */ setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_RST); - /* wait for reset complete or 1-second timeout */ - end_tick = usec2ticks(1000000) + get_ticks(); - do { - rstctl = in_be32(&srds_regs->bank[bank].rstctl); - if (rstctl & SRDS_RSTCTL_RSTDONE) - break; - } while (end_tick > get_ticks()); - - if (!(rstctl & SRDS_RSTCTL_RSTDONE)) { - printf("SERDES: timeout resetting bank %d\n", - bank + 1); - continue; - } + wait_for_rstdone(bank); } + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + if (need_serdes_a001) { + /* + * Bank three has been enabled, so enable bank two and then + * disable it. + */ + srds_lpd_b[FSL_SRDS_BANK_2] = 0; + enable_bank(gur, FSL_SRDS_BANK_2); + + wait_for_rstdone(FSL_SRDS_BANK_2); + + /* Disable bank 2 */ + setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl, + SRDS_RSTCTL_SDPD); + } +#endif + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 + for (device = XAUI_FM1; device <= XAUI_FM2; device++) { + if (is_serdes_configured(device)) + __serdes_reset_rx(srds_regs, cfg, device); + } +#endif } diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h index 42d771e..f261351 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h @@ -33,7 +33,7 @@ enum srds_bank { int is_serdes_prtcl_valid(u32 prtcl); int serdes_get_lane_idx(int lane); -int serdes_get_bank(int lane); +int serdes_get_bank_by_lane(int lane); int serdes_lane_enabled(int lane); enum srds_prtcl serdes_get_prtcl(int cfg, int lane); diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c index e8d53bb..c014163 100644 --- a/arch/powerpc/cpu/mpc85xx/portals.c +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -31,6 +31,7 @@ #include <asm/fsl_liodn.h> static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR; +static ccsr_bman_t *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR; void setup_portals(void) { @@ -250,3 +251,32 @@ err: off = fdt_node_offset_by_compatible(blob, off, "fsl,qman-portal"); } } + +void fdt_fixup_bportals(void *blob) +{ + int off, err; + unsigned int maj, min; + u32 rev_1 = in_be32(&bman->ip_rev_1); + char compat[64]; + int compat_len; + + maj = (rev_1 >> 8) & 0xff; + min = rev_1 & 0xff; + + compat_len = sprintf(compat, "fsl,bman-portal-%u.%u", maj, min) + 1; + compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1; + + off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal"); + while (off != -FDT_ERR_NOTFOUND) { + err = fdt_setprop(blob, off, "compatible", compat, compat_len); + if (err < 0) { + printf("ERROR: unable to create props for %s: %s\n", + fdt_get_name(blob, off, NULL), + fdt_strerror(err)); + return; + } + + off = fdt_node_offset_by_compatible(blob, off, "fsl,bman-portal"); + } + +} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c index 02908b4..104d360 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c @@ -13,11 +13,11 @@ #include "ddr.h" /* To avoid 64-bit full-divides, we factor this here */ -#define ULL_2e12 2000000000000ULL -#define UL_5pow12 244140625UL -#define UL_2pow13 (1UL << 13) +#define ULL_2E12 2000000000000ULL +#define UL_5POW12 244140625UL +#define UL_2POW13 (1UL << 13) -#define ULL_8Fs 0xFFFFFFFFULL +#define ULL_8FS 0xFFFFFFFFULL /* * Round mclk_ps to nearest 10 ps in memory controller code. @@ -32,7 +32,7 @@ unsigned int get_memory_clk_period_ps(void) unsigned int result; /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ - unsigned long long mclk_ps = ULL_2e12; + unsigned long long mclk_ps = ULL_2E12; /* Add 5*data_rate, for rounding */ mclk_ps += 5*(unsigned long long)data_rate; @@ -61,9 +61,9 @@ unsigned int picos_to_mclk(unsigned int picos) * Now divide by 5^12 and track the 32-bit remainder, then divide * by 2*(2^12) using shifts (and updating the remainder). */ - clks_rem = do_div(clks, UL_5pow12); + clks_rem = do_div(clks, UL_5POW12); clks_rem <<= 13; - clks_rem |= clks & (UL_2pow13-1); + clks_rem |= clks & (UL_2POW13-1); clks >>= 13; /* If we had a remainder, then round up */ @@ -71,8 +71,8 @@ unsigned int picos_to_mclk(unsigned int picos) clks++; /* Clamp to the maximum representable value */ - if (clks > ULL_8Fs) - clks = ULL_8Fs; + if (clks > ULL_8FS) + clks = ULL_8FS; return (unsigned int) clks; } diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c index 39a4556..e794821 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c @@ -38,47 +38,46 @@ void print_ifc_regs(void) void init_early_memctl_regs(void) { #if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) - set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); - set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); - set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); - set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0); set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1); set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2); set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3); + + set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); + set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); + set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); #endif #if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) - set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1); - set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1); - set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1); - set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2); set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3); + + set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1); + set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1); + set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1); #endif #if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) - set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2); - set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); - set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2); - set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2); set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3); + set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2); + set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); + set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2); #endif #if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) - set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3); - set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); - set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3); - set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2); set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3); + + set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3); + set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); + set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3); #endif } diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 624d8c2..9aad9be 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -29,6 +29,13 @@ #include <asm/config_mpc86xx.h> #endif +/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ +#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI) +# ifndef CONFIG_HARD_SPI +# define CONFIG_HARD_SPI +# endif +#endif + #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH #define CONFIG_SYS_BOOT_GET_CMDLINE diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 41fd86c..41c2d20 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -264,6 +264,10 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -275,6 +279,10 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 @@ -282,6 +290,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -295,6 +304,7 @@ #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 @@ -304,6 +314,9 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 +#define CONFIG_SYS_P4080_ERRATUM_SERDES9 +#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 +#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 /* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) @@ -316,6 +329,10 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 @@ -327,6 +344,10 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #else #error Processor type not defined for this platform diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 0ec5c0a..801571f 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -115,10 +115,18 @@ extern void fdt_fixup_liodn(void *blob); FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \ +/* + * handle both old and new versioned SEC properties: + * "fsl,secX.Y" became "fsl,sec-vX.Y" during development + */ #define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \ SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\ offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \ + SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\ + offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum) /* This is a bit evil since we treat rtic param as both a string & hex value */ @@ -127,6 +135,11 @@ extern void fdt_fixup_liodn(void *blob); liodnA, \ offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \ + SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \ + liodnA, \ + offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)) #define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \ diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 82d75be..fc47a9f 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -230,7 +230,9 @@ int fsl_pcie_init_board(int busno); #define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3) #define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4) -#if defined(CONFIG_FSL_CORENET) +#if !defined(CONFIG_PCI) +#define FT_FSL_PCI_SETUP +#elif defined(CONFIG_FSL_CORENET) #define FSL_PCIE_COMPAT "fsl,p4080-pcie" #define FT_FSL_PCI_SETUP \ FT_FSL_PCIE1_SETUP; \ diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h index cb32927..e1c1212 100644 --- a/arch/powerpc/include/asm/fsl_portals.h +++ b/arch/powerpc/include/asm/fsl_portals.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -51,6 +51,7 @@ extern int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev, u32 *liodns, int liodn_offset); extern void setup_portals(void); extern void fdt_fixup_qportals(void *blob); +extern void fdt_fixup_bportals(void *blob); extern struct qportal_info qp_info[]; extern void fdt_portal(void *blob, const char *compat, const char *container, diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 85518eb..0f31af1 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -53,4 +53,11 @@ enum srds_prtcl { int is_serdes_configured(enum srds_prtcl device); void fsl_serdes_init(void); +#ifdef CONFIG_FSL_CORENET +int serdes_get_first_lane(enum srds_prtcl device); +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 +void serdes_reset_rx(enum srds_prtcl device); +#endif +#endif + #endif /* __FSL_SERDES_H */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index b51017b..f85cee2 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1920,9 +1920,56 @@ typedef struct ccsr_gur { u32 gpindr; /* General-purpose input data */ u8 res5[12]; u32 pmuxcr; /* Alt. function signal multiplex control */ +#if defined(CONFIG_P1010) || defined(CONFIG_P1014) +#define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000 +#define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000 +#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000 +#define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000 +#define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000 +#define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000 +#define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000 +#define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000 +#define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000 +#define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000 +#define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000 +#define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000 +#define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000 +#define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000 +#define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000 +#define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000 +#define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000 +#define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000 +#define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000 +#define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000 +#define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000 +#define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000 +#define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000 +#define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000 +#define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000 +#define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000 +#define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000 +#define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000 +#define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400 +#define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800 +#define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00 +#define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300 +#define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200 +#define MPC85xx_PMUXCR_LCLK_RES 0x00000040 +#define MPC85xx_PMUXCR_LCLK_USB 0x00000080 +#define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0 +#define MPC85xx_PMUXCR_SPI_RES 0x00000030 +#define MPC85xx_PMUXCR_SPI_GPIO 0x00000020 +#define MPC85xx_PMUXCR_CAN1_UART 0x00000004 +#define MPC85xx_PMUXCR_CAN1_TDM 0x00000008 +#define MPC85xx_PMUXCR_CAN1_RES 0x0000000C +#define MPC85xx_PMUXCR_CAN2_UART 0x00000001 +#define MPC85xx_PMUXCR_CAN2_TDM 0x00000002 +#define MPC85xx_PMUXCR_CAN2_RES 0x00000003 +#endif #define MPC85xx_PMUXCR_SD_DATA 0x80000000 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000 +#define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000 #define MPC85xx_PMUXCR_TDM_ENA 0x00800000 #define MPC85xx_PMUXCR_QE0 0x00008000 #define MPC85xx_PMUXCR_QE1 0x00004000 @@ -1944,6 +1991,31 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_SPI 0x00000000 #endif u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ +#if defined(CONFIG_P1010) || defined(CONFIG_P1014) +#define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 +#define MPC85xx_PMUXCR2_UART_TDM 0x80000000 +#define MPC85xx_PMUXCR2_UART_RES 0xC0000000 +#define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000 +#define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000 +#define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000 +#define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000 +#define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000 +#define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000 +#define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000 +#define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000 +#define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000 +#define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000 +#define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000 +#define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000 +#define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000 +#define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000 +#define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000 +#define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000 +#define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000 +#define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000 +#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000 +#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000 +#endif #if defined(CONFIG_P1013) || defined(CONFIG_P1022) #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f1000 #define MPC85xx_PMUXCR2_USB 0x00150000 @@ -2029,6 +2101,7 @@ typedef struct serdes_corenet { #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 +#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000 @@ -2065,6 +2138,9 @@ typedef struct serdes_corenet { #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000 u32 res3; u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */ +#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000 +#define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000 +#define SRDS_TTLCR0_PM_DIS 0x00004000 u32 res4[7]; } lane[24]; u32 res6[384]; @@ -2213,6 +2289,13 @@ typedef struct ccsr_pme { u8 res4[0x400]; } ccsr_pme_t; +typedef struct ccsr_usb_phy { + u8 res0[0x18]; + u32 usb_enable_override; + u8 res[0xe4]; +} ccsr_usb_phy_t; +#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 + #ifdef CONFIG_FSL_CORENET #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 @@ -2235,6 +2318,8 @@ typedef struct ccsr_pme { #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000 #define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET +#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000 +#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 @@ -2357,6 +2442,10 @@ typedef struct ccsr_pme { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) #define CONFIG_SYS_MPC85xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) +#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET) +#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET) #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) #define CONFIG_SYS_FSL_FM1_ADDR \ diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 8ea5acb..dbf1da8 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -46,7 +46,9 @@ COBJS-$(CONFIG_MPC8536DS) += ics307_clk.o COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o COBJS-$(CONFIG_P1022DS) += ics307_clk.o COBJS-$(CONFIG_P2020DS) += ics307_clk.o +COBJS-$(CONFIG_P3041DS) += ics307_clk.o COBJS-$(CONFIG_P4080DS) += ics307_clk.o +COBJS-$(CONFIG_P5020DS) += ics307_clk.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c index 4e01e5a..765f035 100644 --- a/board/freescale/common/ngpixis.c +++ b/board/freescale/common/ngpixis.c @@ -119,11 +119,50 @@ void __set_altbank(void) } void set_altbank(void) __attribute__((weak, alias("__set_altbank"))); +#ifdef DEBUG +static void pixis_dump_regs(void) +{ + unsigned int i; + + printf("id=%02x\n", PIXIS_READ(id)); + printf("arch=%02x\n", PIXIS_READ(arch)); + printf("scver=%02x\n", PIXIS_READ(scver)); + printf("csr=%02x\n", PIXIS_READ(csr)); + printf("rst=%02x\n", PIXIS_READ(rst)); + printf("aux=%02x\n", PIXIS_READ(aux)); + printf("spd=%02x\n", PIXIS_READ(spd)); + printf("brdcfg0=%02x\n", PIXIS_READ(brdcfg0)); + printf("brdcfg1=%02x\n", PIXIS_READ(brdcfg1)); + printf("addr=%02x\n", PIXIS_READ(addr)); + printf("data=%02x\n", PIXIS_READ(data)); + printf("led=%02x\n", PIXIS_READ(led)); + printf("vctl=%02x\n", PIXIS_READ(vctl)); + printf("vstat=%02x\n", PIXIS_READ(vstat)); + printf("vcfgen0=%02x\n", PIXIS_READ(vcfgen0)); + printf("ocmcsr=%02x\n", PIXIS_READ(ocmcsr)); + printf("ocmmsg=%02x\n", PIXIS_READ(ocmmsg)); + printf("gmdbg=%02x\n", PIXIS_READ(gmdbg)); + printf("sclk=%02x%02x%02x\n", + PIXIS_READ(sclk[0]), PIXIS_READ(sclk[1]), PIXIS_READ(sclk[2])); + printf("dclk=%02x%02x%02x\n", + PIXIS_READ(dclk[0]), PIXIS_READ(dclk[1]), PIXIS_READ(dclk[2])); + printf("watch=%02x\n", PIXIS_READ(watch)); + + for (i = 0; i < 8; i++) { + printf("SW%u=%02x/%02x ", i + 1, + PIXIS_READ(s[i].sw), PIXIS_READ(s[i].en)); + } + putc('\n'); +} +#endif int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned int i; char *p_altbank = NULL; +#ifdef DEBUG + char *p_dump = NULL; +#endif char *unknown_param = NULL; /* No args is a simple reset request. @@ -137,6 +176,13 @@ int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) continue; } +#ifdef DEBUG + if (strcmp(argv[i], "dump") == 0) { + p_dump = argv[i]; + continue; + } +#endif + unknown_param = argv[i]; } @@ -145,6 +191,15 @@ int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; } +#ifdef DEBUG + if (p_dump) { + pixis_dump_regs(); + + /* 'dump' ignores other commands */ + return 0; + } +#endif + if (p_altbank) set_altbank(); else @@ -161,4 +216,7 @@ U_BOOT_CMD( "Reset the board using the FPGA sequencer", "- hard reset to default bank\n" "pixis_reset altbank - reset to alternate bank\n" +#ifdef DEBUG + "pixis_reset dump - display the PIXIS registers\n" +#endif ); diff --git a/board/freescale/common/ngpixis.h b/board/freescale/common/ngpixis.h index 681b0d0..1d4483d 100644 --- a/board/freescale/common/ngpixis.h +++ b/board/freescale/common/ngpixis.h @@ -20,16 +20,17 @@ typedef struct ngpixis { u8 scver; u8 csr; u8 rst; - u8 res1; + u8 serclk; u8 aux; u8 spd; u8 brdcfg0; u8 brdcfg1; /* On some boards, this register is called 'dma' */ u8 addr; - u8 res2[2]; + u8 brdcfg2; + u8 gpiodir; u8 data; u8 led; - u8 res3; + u8 tag; u8 vctl; u8 vstat; u8 vcfgen0; diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile index 1047d78..69e81a4 100644 --- a/board/freescale/corenet_ds/Makefile +++ b/board/freescale/corenet_ds/Makefile @@ -28,7 +28,9 @@ LIB = $(obj)lib$(BOARD).o COBJS-y += $(BOARD).o COBJS-y += ddr.o +COBJS-$(CONFIG_P3041DS) += p3041ds_ddr.o COBJS-$(CONFIG_P4080DS) += p4080ds_ddr.o +COBJS-$(CONFIG_P5020DS) += p5020ds_ddr.o COBJS-$(CONFIG_PCI) += pci.o COBJS-y += law.o COBJS-y += tlb.o diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 3db93c3..9324125 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -87,10 +87,21 @@ int checkboard (void) * don't match. */ puts("SERDES Reference Clocks: "); +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) + sw = in_8(&PIXIS_SW(5)); + for (i = 0; i < 3; i++) { + static const char *freq[] = {"100", "125", "156.25", "212.5" }; + unsigned int clock = (sw >> (6 - (2 * i))) & 3; + + printf("Bank%u=%sMhz ", i+1, freq[clock]); + } + puts("\n"); +#else sw = in_8(&PIXIS_SW(3)); printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100); printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125"); printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125"); +#endif return 0; } @@ -146,7 +157,7 @@ static const char *serdes_clock_to_string(u32 clock) case SRDS_PLLCR0_RFCK_SEL_156_25: return "156.25"; default: - return "???"; + return "150"; } } @@ -157,19 +168,41 @@ int misc_init_r(void) serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; u32 actual[NUM_SRDS_BANKS]; unsigned int i; - u8 sw3; + u8 sw; +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) + sw = in_8(&PIXIS_SW(5)); + for (i = 0; i < 3; i++) { + unsigned int clock = (sw >> (6 - (2 * i))) & 3; + switch (clock) { + case 0: + actual[i] = SRDS_PLLCR0_RFCK_SEL_100; + break; + case 1: + actual[i] = SRDS_PLLCR0_RFCK_SEL_125; + break; + case 2: + actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; + break; + default: + printf("Warning: SDREFCLK%u switch setting of '11' is " + "unsupported\n", i + 1); + break; + } + } +#else /* Warn if the expected SERDES reference clocks don't match the * actual reference clocks. This needs to be done after calling * p4080_erratum_serdes8(), since that function may modify the clocks. */ - sw3 = in_8(&PIXIS_SW(3)); - actual[0] = (sw3 & 0x40) ? + sw = in_8(&PIXIS_SW(3)); + actual[0] = (sw & 0x40) ? SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; - actual[1] = (sw3 & 0x20) ? + actual[1] = (sw & 0x20) ? SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; - actual[2] = (sw3 & 0x10) ? + actual[2] = (sw & 0x10) ? SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; +#endif for (i = 0; i < NUM_SRDS_BANKS; i++) { u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; diff --git a/board/freescale/corenet_ds/law.c b/board/freescale/corenet_ds/law.c index 43b4b97..d2ba556 100644 --- a/board/freescale/corenet_ds/law.c +++ b/board/freescale/corenet_ds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -35,6 +35,9 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), #endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c new file mode 100644 index 0000000..5a8ed94 --- /dev/null +++ b/board/freescale/corenet_ds/p3041ds_ddr.c @@ -0,0 +1,14 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <asm/fsl_ddr_sdram.h> + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {0, 0, NULL} +}; diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c new file mode 100644 index 0000000..e65de36 --- /dev/null +++ b/board/freescale/corenet_ds/p5020ds_ddr.c @@ -0,0 +1,18 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <asm/fsl_ddr_sdram.h> + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {0, 0, NULL} +}; + +fixed_ddr_parm_t fixed_ddr_parm_1[] = { + {0, 0, NULL} +}; diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c index fe77e79..38736b4 100644 --- a/board/freescale/corenet_ds/tlb.c +++ b/board/freescale/corenet_ds/tlb.c @@ -117,6 +117,16 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_4M, 1), #endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_1M, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index cd2ce4b..e3916fc 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -34,11 +34,6 @@ phys_size_t fixed_sdram(void); -int board_early_init_f(void) -{ - return 0; -} - int checkboard(void) { u8 vboot; diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 73a1021..8ef627f 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -46,6 +46,9 @@ int board_early_init_f(void) /* Set the pin muxing to enable ETSEC2. */ clrbits_be32(&gur->pmuxcr2, 0x001F8000); + /* Enable the SPI */ + clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI); + return 0; } diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 0b4ae9d..d66b130 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -47,6 +47,7 @@ DECLARE_GLOBAL_DATA_PTR; #define RGMII_PHY_RST_SET 0x02000000 #define USB_RST_CLR 0x04000000 +#define USB2_PORT_OUT_EN 0x01000000 #define GPIO_DIR 0x060f0000 @@ -128,6 +129,19 @@ int checkboard (void) return 0; } +int misc_init_r(void) +{ +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gpio_t *gpio = (void *)CONFIG_SYS_MPC85xx_GPIO_ADDR; + + setbits_be32(&gpio->gpdir, USB2_PORT_OUT_EN); + setbits_be32(&gpio->gpdat, USB2_PORT_OUT_EN); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_ELBC_OFF_USB2_ON); +#endif + return 0; +} + int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; @@ -558,6 +558,7 @@ P2020DS powerpc mpc85xx p2020ds freesca P2020DS_36BIT powerpc mpc85xx p2020ds freescale - P2020DS:36BIT P2020DS_DDR2 powerpc mpc85xx p2020ds freescale - P2020DS:DDR2 P2020DS_SDCARD powerpc mpc85xx p2020ds freescale - P2020DS:SDCARD +P2020DS_SPIFLASH powerpc mpc85xx p2020ds freescale - P2020DS:SPIFLASH P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB P2020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT P2020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT,SDCARD @@ -565,8 +566,10 @@ P2020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freesca P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,NAND P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH +P3041DS powerpc mpc85xx corenet_ds freescale P4080DS powerpc mpc85xx corenet_ds freescale P4080DS_RAMBOOT_PBL powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF80000 +P5020DS powerpc mpc85xx corenet_ds freescale mpq101 powerpc mpc85xx mpq101 mercury - mpq101 stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index a9fcfe7..a9b1ca4 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -39,6 +39,7 @@ COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o +COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c new file mode 100644 index 0000000..f872cd8 --- /dev/null +++ b/drivers/spi/fsl_espi.c @@ -0,0 +1,334 @@ +/* + * eSPI controller driver. + * + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Mingkai Hu (Mingkai.hu@freescale.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#include <malloc.h> +#include <spi.h> +#include <asm/immap_85xx.h> + +struct fsl_spi_slave { + struct spi_slave slave; + unsigned int div16; + unsigned int pm; + unsigned int mode; + size_t cmd_len; + u8 cmd_buf[16]; + size_t data_len; + unsigned int max_transfer_length; +}; + +#define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave) + +#define ESPI_MAX_CS_NUM 4 + +#define ESPI_EV_RNE (1 << 9) +#define ESPI_EV_TNF (1 << 8) + +#define ESPI_MODE_EN (1 << 31) /* Enable interface */ +#define ESPI_MODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold */ +#define ESPI_MODE_RXTHR(x) ((x) << 0) /* Rx FIFO threshold */ + +#define ESPI_COM_CS(x) ((x) << 30) +#define ESPI_COM_TRANLEN(x) ((x) << 0) + +#define ESPI_CSMODE_CI_INACTIVEHIGH (1 << 31) +#define ESPI_CSMODE_CP_BEGIN_EDGCLK (1 << 30) +#define ESPI_CSMODE_REV_MSB_FIRST (1 << 29) +#define ESPI_CSMODE_DIV16 (1 << 28) +#define ESPI_CSMODE_PM(x) ((x) << 24) +#define ESPI_CSMODE_POL_ASSERTED_LOW (1 << 20) +#define ESPI_CSMODE_LEN(x) ((x) << 16) +#define ESPI_CSMODE_CSBEF(x) ((x) << 12) +#define ESPI_CSMODE_CSAFT(x) ((x) << 8) +#define ESPI_CSMODE_CSCG(x) ((x) << 3) + +#define ESPI_CSMODE_INIT_VAL (ESPI_CSMODE_POL_ASSERTED_LOW | \ + ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | \ + ESPI_CSMODE_CSCG(1)) + +#define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0 + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct fsl_spi_slave *fsl; + sys_info_t sysinfo; + unsigned long spibrg = 0; + unsigned char pm = 0; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + fsl = malloc(sizeof(struct fsl_spi_slave)); + if (!fsl) + return NULL; + + fsl->slave.bus = bus; + fsl->slave.cs = cs; + fsl->mode = mode; + fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; + + /* Set eSPI BRG clock source */ + get_sys_info(&sysinfo); + spibrg = sysinfo.freqSystemBus / 2; + fsl->div16 = 0; + if ((spibrg / max_hz) > 32) { + fsl->div16 = ESPI_CSMODE_DIV16; + pm = spibrg / (max_hz * 16 * 2); + if (pm > 16) { + pm = 16; + debug("Requested speed is too low: %d Hz, " + "%d Hz is used.\n", max_hz, spibrg / (32 * 16)); + } + } else + pm = spibrg / (max_hz * 2); + if (pm) + pm--; + fsl->pm = pm; + + return &fsl->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + free(fsl); +} + +void spi_init(void) +{ + +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + unsigned char pm = fsl->pm; + unsigned int cs = slave->cs; + unsigned int mode = fsl->mode; + unsigned int div16 = fsl->div16; + int i; + + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs); + + /* Enable eSPI interface */ + out_be32(&espi->mode, ESPI_MODE_RXTHR(3) + | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN); + + out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */ + out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */ + + /* Init CS mode interface */ + for (i = 0; i < ESPI_MAX_CS_NUM; i++) + out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL); + + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & + ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 + | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK + | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF))); + + /* Set eSPI BRG clock source */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_PM(pm) | div16); + + /* Set eSPI mode */ + if (mode & SPI_CPHA) + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_CP_BEGIN_EDGCLK); + if (mode & SPI_CPOL) + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_CI_INACTIVEHIGH); + + /* Character bit order: msb first */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_REV_MSB_FIRST); + + /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_LEN(7)); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, + void *data_in, unsigned long flags) +{ + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + unsigned int tmpdout, tmpdin, event; + const void *dout = NULL; + void *din = NULL; + int len = 0; + int num_blks, num_chunks, max_tran_len, tran_len; + int num_bytes; + unsigned char *ch; + unsigned char *buffer = NULL; + size_t buf_len; + u8 *cmd_buf = fsl->cmd_buf; + size_t cmd_len = fsl->cmd_len; + size_t data_len = bitlen / 8; + size_t rx_offset = 0; + + max_tran_len = fsl->max_transfer_length; + switch (flags) { + case SPI_XFER_BEGIN: + cmd_len = fsl->cmd_len = data_len; + memcpy(cmd_buf, data_out, cmd_len); + return 0; + case 0: + case SPI_XFER_END: + if (bitlen == 0) { + spi_cs_deactivate(slave); + return 0; + } + buf_len = 2 * cmd_len + min(data_len, max_tran_len); + len = cmd_len + data_len; + rx_offset = cmd_len; + buffer = (unsigned char *)malloc(buf_len); + if (!buffer) { + debug("SF: Failed to malloc memory.\n"); + return 1; + } + memcpy(buffer, cmd_buf, cmd_len); + if (cmd_len != 1) { + if (data_in == NULL) + memcpy(buffer + cmd_len, data_out, data_len); + } + break; + case SPI_XFER_BEGIN | SPI_XFER_END: + len = data_len; + buffer = (unsigned char *)malloc(len * 2); + if (!buffer) { + debug("SF: Failed to malloc memory.\n"); + return 1; + } + memcpy(buffer, data_out, len); + rx_offset = len; + cmd_len = 0; + break; + } + + debug("spi_xfer: slave %u:%u dout %08X(%08x) din %08X(%08x) len %u\n", + slave->bus, slave->cs, *(uint *) dout, + dout, *(uint *) din, din, len); + + num_chunks = data_len / max_tran_len + + (data_len % max_tran_len ? 1 : 0); + while (num_chunks--) { + if (data_in) + din = buffer + rx_offset; + dout = buffer; + tran_len = min(data_len , max_tran_len); + num_blks = (tran_len + cmd_len) / 4 + + ((tran_len + cmd_len) % 4 ? 1 : 0); + num_bytes = (tran_len + cmd_len) % 4; + fsl->data_len = tran_len + cmd_len; + spi_cs_activate(slave); + + /* Clear all eSPI events */ + out_be32(&espi->event , 0xffffffff); + /* handle data in 32-bit chunks */ + while (num_blks--) { + + event = in_be32(&espi->event); + if (event & ESPI_EV_TNF) { + tmpdout = *(u32 *)dout; + + /* Set up the next iteration */ + if (len > 4) { + len -= 4; + dout += 4; + } + + out_be32(&espi->tx, tmpdout); + out_be32(&espi->event, ESPI_EV_TNF); + debug("***spi_xfer:...%08x written\n", tmpdout); + } + + /* Wait for eSPI transmit to get out */ + udelay(80); + + event = in_be32(&espi->event); + if (event & ESPI_EV_RNE) { + tmpdin = in_be32(&espi->rx); + if (num_blks == 0 && num_bytes != 0) { + ch = (unsigned char *)&tmpdin; + while (num_bytes--) + *(unsigned char *)din++ = *ch++; + } else { + *(u32 *) din = tmpdin; + din += 4; + } + + out_be32(&espi->event, in_be32(&espi->event) + | ESPI_EV_RNE); + debug("***spi_xfer:...%08x readed\n", tmpdin); + } + } + if (data_in) { + memcpy(data_in, buffer + 2 * cmd_len, tran_len); + if (*buffer == 0x0b) { + data_in += tran_len; + data_len -= tran_len; + *(int *)buffer += tran_len; + } + } + spi_cs_deactivate(slave); + } + + free(buffer); + return 0; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs < ESPI_MAX_CS_NUM; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + unsigned int com = 0; + size_t data_len = fsl->data_len; + + com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF)); + com |= ESPI_COM_CS(slave->cs); + com |= ESPI_COM_TRANLEN(data_len - 1); + out_be32(&espi->com, com); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + + /* clear the RXCNT and TXCNT */ + out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN)); + out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN); +} diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 9b3e032..7f7ff9f 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -721,11 +721,11 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 8b3aff8..e1d933e 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -420,11 +420,11 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 7101230..5918e64 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -432,11 +432,11 @@ extern unsigned long get_clock_freq(void); /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 62bac6d..b25fb55 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -452,11 +452,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 43e2c2e..0c0ae02 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -491,11 +491,11 @@ extern unsigned long get_clock_freq(void); /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 106034d..4c580a3 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -430,11 +430,11 @@ extern unsigned long get_clock_freq(void); /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 15ebb6f..f55ef9d 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -461,11 +461,11 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 6237b23..f7df7f0 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -451,11 +451,11 @@ extern unsigned long get_clock_freq(void); /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 8835ef5..fa626bb 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -590,11 +590,11 @@ extern unsigned long get_clock_freq(void); /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index d93185c..bb8fb66 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -708,11 +708,11 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 0cca603..0ddb76f 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -90,8 +90,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) #endif -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00400000 diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index e9622e7..a118975 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -170,6 +170,8 @@ #define PIXIS_LBMAP_SWITCH 7 #define PIXIS_LBMAP_MASK 0xF0 #define PIXIS_LBMAP_ALTBANK 0x20 +#define PIXIS_ELBC_SPI_MASK 0xc0 +#define PIXIS_SPI 0x80 #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ @@ -269,6 +271,19 @@ #define CONFIG_SYS_EEPROM_BUS_NUM 1 /* + * eSPI - Enhanced SPI + */ +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION + +#define CONFIG_HARD_SPI +#define CONFIG_FSL_ESPI + +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +/* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ @@ -462,11 +477,11 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index cccf84d..59f9755 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -244,6 +244,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_R #define CONFIG_HWCONFIG #define CONFIG_SYS_INIT_RAM_LOCK 1 @@ -410,6 +411,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_RTC_DS1337 #define CONFIG_SYS_RTC_DS1337_NOOSC #define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* eSPI - Enhanced SPI */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. @@ -521,9 +531,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#elif defined(CONFIG_RAMBOOT_SDCARD) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_RAMBOOT_SPIFLASH) + #define CONFIG_ENV_IS_IN_SPI_FLASH + #define CONFIG_ENV_SPI_BUS 0 + #define CONFIG_ENV_SPI_CS 0 + #define CONFIG_ENV_SPI_MAX_HZ 10000000 + #define CONFIG_ENV_SPI_MODE 0 + #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ + #define CONFIG_ENV_SECT_SIZE 0x10000 #define CONFIG_ENV_SIZE 0x2000 #endif #else @@ -611,11 +630,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20)/* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20)/* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 47f1f18..b5db0b3 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -40,6 +40,13 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc #endif +#ifdef CONFIG_SPIFLASH +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -418,6 +425,18 @@ #define CONFIG_SYS_EEPROM_BUS_NUM 0 /* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION + +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +/* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ @@ -594,6 +613,15 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_SPIFLASH) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH 1 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 @@ -681,11 +709,11 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h new file mode 100644 index 0000000..46f91cc --- /dev/null +++ b/include/configs/P3041DS.h @@ -0,0 +1,37 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * P3041 DS board configuration file + * + */ +#define CONFIG_P3041DS +#define CONFIG_PHYS_64BIT +#define CONFIG_PPC_P3041 + +#define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE4 + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + +#include "corenet_ds.h" + diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h new file mode 100644 index 0000000..6d279b3 --- /dev/null +++ b/include/configs/P5020DS.h @@ -0,0 +1,37 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * P5020 DS board configuration file + * + */ +#define CONFIG_P5020DS +#define CONFIG_PHYS_64BIT +#define CONFIG_PPC_P5020 + +#define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE4 + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + +#include "corenet_ds.h" + diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index bec8cd1..d1cda15 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -162,6 +162,7 @@ #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /* @@ -218,6 +219,43 @@ #define CONFIG_SYS_RAMBOOT #endif +/* Nand Flash */ +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) +#define CONFIG_NAND_FSL_ELBC +#ifdef CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif + +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* NAND flash config */ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ + | OR_FCM_PGS /* Large Page*/ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) + +#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ +#endif /* CONFIG_NAND_FSL_ELBC */ +#endif + #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} @@ -356,7 +394,7 @@ #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull @@ -534,11 +572,11 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/spi.h b/include/spi.h index 7887d0f..60e85db 100644 --- a/include/spi.h +++ b/include/spi.h @@ -26,13 +26,6 @@ /* Controller-specific definitions: */ -/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ -#ifdef CONFIG_MPC8XXX_SPI -# ifndef CONFIG_HARD_SPI -# define CONFIG_HARD_SPI -# endif -#endif - /* SPI mode flags */ #define SPI_CPHA 0x01 /* clock phase */ #define SPI_CPOL 0x02 /* clock polarity */ diff --git a/include/tsec.h b/include/tsec.h index 8ed30ac..f0f3d4d 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -25,7 +25,7 @@ #define TSEC_SIZE 0x01000 #define TSEC_MDIO_OFFSET 0x01000 -#define CONFIG_SYS_MDIO_BASE_ADDR (TSEC_BASE_ADDR + 0x520) +#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520) #define DEFAULT_MII_NAME "FSL_MDIO" |