diff options
| -rw-r--r-- | MAINTAINERS | 5 | ||||
| -rwxr-xr-x | MAKEALL | 1 | ||||
| -rw-r--r-- | Makefile | 5 | ||||
| -rw-r--r-- | board/sh7785lcr/Makefile | 45 | ||||
| -rw-r--r-- | board/sh7785lcr/config.mk | 26 | ||||
| -rw-r--r-- | board/sh7785lcr/lowlevel_init.S | 318 | ||||
| -rw-r--r-- | board/sh7785lcr/rtl8169.h | 58 | ||||
| -rw-r--r-- | board/sh7785lcr/rtl8169_mac.c | 349 | ||||
| -rw-r--r-- | board/sh7785lcr/selfcheck.c | 173 | ||||
| -rw-r--r-- | board/sh7785lcr/sh7785lcr.c | 51 | ||||
| -rw-r--r-- | board/sh7785lcr/u-boot.lds | 97 | ||||
| -rw-r--r-- | doc/README.sh7785lcr | 83 | ||||
| -rw-r--r-- | include/configs/sh7785lcr.h | 167 |
13 files changed, 1378 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 57a79b4..368a0c9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -767,6 +767,11 @@ Mark Jonas <mark.jonas@de.bosch.com> Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> MS7720SE SH7720 + R0P77850011RL SH7785 + +Yusuke Goda <goda.yusuke@renesas.com> + + MIGO-R SH7722 ######################################################################### # Blackfin Systems: # @@ -752,6 +752,7 @@ LIST_sh4=" \ r7780mp \ r2dplus \ sh7763rdp \ + sh7785lcr \ " LIST_sh=" \ @@ -3053,6 +3053,11 @@ sh7763rdp_config : unconfig @echo "#define CONFIG_SH7763RDP 1" > $(obj)include/config.h @./mkconfig -a $(@:_config=) sh sh4 sh7763rdp +sh7785lcr_config : unconfig + @ >include/config.h + @echo "#define CONFIG_SH7785LCR 1" >> include/config.h + @$(MKCONFIG) -a $(@:_config=) sh sh4 sh7785lcr + #======================================================================== # SPARC #======================================================================== diff --git a/board/sh7785lcr/Makefile b/board/sh7785lcr/Makefile new file mode 100644 index 0000000..43688d5 --- /dev/null +++ b/board/sh7785lcr/Makefile @@ -0,0 +1,45 @@ +# +# Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +COBJS := sh7785lcr.o selfcheck.o rtl8169_mac.o +SOBJS := lowlevel_init.o + +$(LIB): $(obj).depend $(COBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(COBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/sh7785lcr/config.mk b/board/sh7785lcr/config.mk new file mode 100644 index 0000000..93761ee --- /dev/null +++ b/board/sh7785lcr/config.mk @@ -0,0 +1,26 @@ +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +# +# TEXT_BASE refers to image _after_ relocation. +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# +TEXT_BASE = 0x0ff80000 + diff --git a/board/sh7785lcr/lowlevel_init.S b/board/sh7785lcr/lowlevel_init.S new file mode 100644 index 0000000..8126296 --- /dev/null +++ b/board/sh7785lcr/lowlevel_init.S @@ -0,0 +1,318 @@ +/* + * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <config.h> +#include <version.h> +#include <asm/processor.h> + +.macro write32, addr, data + mov.l \addr ,r1 + mov.l \data ,r0 + mov.l r0, @r1 +.endm + +.macro write16, addr, data + mov.l \addr ,r1 + mov.l \data ,r0 + mov.w r0, @r1 +.endm + +.macro write8, addr, data + mov.l \addr ,r1 + mov.l \data ,r0 + mov.b r0, @r1 +.endm + +.macro wait_timer, time + mov.l \time ,r3 +1: + nop + tst r3, r3 + bf/s 1b + dt r3 +.endm + +#include <asm/processor.h> + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + wait_timer WAIT_200US + wait_timer WAIT_200US + + /*------- LBSC -------*/ + write32 MMSELR_A, MMSELR_D + + /*------- DBSC2 -------*/ + write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D + write32 DBSC2_DBTR0_A, DBSC2_DBTR0_D + write32 DBSC2_DBTR1_A, DBSC2_DBTR1_D + write32 DBSC2_DBTR2_A, DBSC2_DBTR2_D + write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1 + write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2 + wait_timer WAIT_200US + + write32 DBSC2_DBDICODTOCD_A, DBSC2_DBDICODTOCD_D + write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_CKE_H + wait_timer WAIT_200US + write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS2 + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS3 + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1 + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_1 + write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL + write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF + write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_2 + wait_timer WAIT_200US + + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_2 + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1 + + write32 DBSC2_DBEN_A, DBSC2_DBEN_D + write32 DBSC2_DBRFCNT1_A, DBSC2_DBRFCNT1_D + write32 DBSC2_DBRFCNT2_A, DBSC2_DBRFCNT2_D + write32 DBSC2_DBRFCNT0_A, DBSC2_DBRFCNT0_D + wait_timer WAIT_200US + + /*------- GPIO -------*/ + write16 PACR_A, PACR_D + write16 PBCR_A, PBCR_D + write16 PCCR_A, PCCR_D + write16 PDCR_A, PDCR_D + write16 PECR_A, PECR_D + write16 PFCR_A, PFCR_D + write16 PGCR_A, PGCR_D + write16 PHCR_A, PHCR_D + write16 PJCR_A, PJCR_D + write16 PKCR_A, PKCR_D + write16 PLCR_A, PLCR_D + write16 PMCR_A, PMCR_D + write16 PNCR_A, PNCR_D + write16 PPCR_A, PPCR_D + write16 PQCR_A, PQCR_D + write16 PRCR_A, PRCR_D + + write8 PEPUPR_A, PEPUPR_D + write8 PHPUPR_A, PHPUPR_D + write8 PJPUPR_A, PJPUPR_D + write8 PKPUPR_A, PKPUPR_D + write8 PLPUPR_A, PLPUPR_D + write8 PMPUPR_A, PMPUPR_D + write8 PNPUPR_A, PNPUPR_D + write16 PPUPR1_A, PPUPR1_D + write16 PPUPR2_A, PPUPR2_D + write16 P1MSELR_A, P1MSELR_D + write16 P2MSELR_A, P2MSELR_D + + /*------- LBSC -------*/ + write32 BCR_A, BCR_D + write32 CS0BCR_A, CS0BCR_D + write32 CS0WCR_A, CS0WCR_D + write32 CS1BCR_A, CS1BCR_D + write32 CS1WCR_A, CS1WCR_D + write32 CS4BCR_A, CS4BCR_D + write32 CS4WCR_A, CS4WCR_D + + mov.l PASCR_A, r0 + mov.l @r0, r2 + mov.l PASCR_32BIT_MODE, r1 + tst r1, r2 + bt lbsc_29bit + + write32 CS2BCR_A, CS_USB_BCR_D + write32 CS2WCR_A, CS_USB_WCR_D + write32 CS3BCR_A, CS_SD_BCR_D + write32 CS3WCR_A, CS_SD_WCR_D + write32 CS5BCR_A, CS_I2C_BCR_D + write32 CS5WCR_A, CS_I2C_WCR_D + write32 CS6BCR_A, CS0BCR_D + write32 CS6WCR_A, CS0WCR_D + bra lbsc_end + nop + +lbsc_29bit: + write32 CS5BCR_A, CS_USB_BCR_D + write32 CS5WCR_A, CS_USB_WCR_D + write32 CS6BCR_A, CS_SD_BCR_D + write32 CS6WCR_A, CS_SD_WCR_D + +lbsc_end: + + write32 CCR_A, CCR_D + + rts + nop + + .align 4 + +/*------- LBSC -------*/ +MMSELR_A: .long 0xfc400020 +MMSELR_D: .long 0xa5a50002 + +/*------- DBSC2 -------*/ +#define DBSC2_BASE 0xfe800000 +DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c +DBSC2_DBEN_A: .long DBSC2_BASE + 0x10 +DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14 +DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20 +DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30 +DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34 +DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38 +DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40 +DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44 +DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48 +DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c +DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50 +DBSC2_DBDICODTOCD_A: .long DBSC2_BASE + 0x54 +DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60 +DDR_DUMMY_ACCESS_A: .long 0x40000000 + +DBSC2_DBCONF_D: .long 0x00630002 +DBSC2_DBTR0_D: .long 0x050b1f04 +DBSC2_DBTR1_D: .long 0x00040204 +DBSC2_DBTR2_D: .long 0x02100308 +DBSC2_DBFREQ_D1: .long 0x00000000 +DBSC2_DBFREQ_D2: .long 0x00000100 +DBSC2_DBDICODTOCD_D: .long 0x000f0907 + +DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003 +DBSC2_DBCMDCNT_D_PALL: .long 0x00000002 +DBSC2_DBCMDCNT_D_REF: .long 0x00000004 + +DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000 +DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000 +DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006 +DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386 +DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952 +DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852 + +DBSC2_DBEN_D: .long 0x00000001 + +DBSC2_DBPDCNT0_D3: .long 0x00000080 +DBSC2_DBRFCNT1_D: .long 0x00000926 +DBSC2_DBRFCNT2_D: .long 0x00fe00fe +DBSC2_DBRFCNT0_D: .long 0x00010000 + +WAIT_200US: .long 33333 + +/*------- GPIO -------*/ +#define GPIO_BASE 0xffe70000 +PACR_A: .long GPIO_BASE + 0x00 +PBCR_A: .long GPIO_BASE + 0x02 +PCCR_A: .long GPIO_BASE + 0x04 +PDCR_A: .long GPIO_BASE + 0x06 +PECR_A: .long GPIO_BASE + 0x08 +PFCR_A: .long GPIO_BASE + 0x0a +PGCR_A: .long GPIO_BASE + 0x0c +PHCR_A: .long GPIO_BASE + 0x0e +PJCR_A: .long GPIO_BASE + 0x10 +PKCR_A: .long GPIO_BASE + 0x12 +PLCR_A: .long GPIO_BASE + 0x14 +PMCR_A: .long GPIO_BASE + 0x16 +PNCR_A: .long GPIO_BASE + 0x18 +PPCR_A: .long GPIO_BASE + 0x1a +PQCR_A: .long GPIO_BASE + 0x1c +PRCR_A: .long GPIO_BASE + 0x1e +PEPUPR_A: .long GPIO_BASE + 0x48 +PHPUPR_A: .long GPIO_BASE + 0x4e +PJPUPR_A: .long GPIO_BASE + 0x50 +PKPUPR_A: .long GPIO_BASE + 0x52 +PLPUPR_A: .long GPIO_BASE + 0x54 +PMPUPR_A: .long GPIO_BASE + 0x56 +PNPUPR_A: .long GPIO_BASE + 0x58 +PPUPR1_A: .long GPIO_BASE + 0x60 +PPUPR2_A: .long GPIO_BASE + 0x62 +P1MSELR_A: .long GPIO_BASE + 0x80 +P2MSELR_A: .long GPIO_BASE + 0x82 + +PACR_D: .long 0x0000 +PBCR_D: .long 0x0000 +PCCR_D: .long 0x0000 +PDCR_D: .long 0x0000 +PECR_D: .long 0x0000 +PFCR_D: .long 0x0000 +PGCR_D: .long 0x0000 +PHCR_D: .long 0x00c0 +PJCR_D: .long 0xc3fc +PKCR_D: .long 0x03ff +PLCR_D: .long 0x0000 +PMCR_D: .long 0xffff +PNCR_D: .long 0xf0c3 +PPCR_D: .long 0x0000 +PQCR_D: .long 0x0000 +PRCR_D: .long 0x0000 + +PEPUPR_D: .long 0xff +PHPUPR_D: .long 0x00 +PJPUPR_D: .long 0x00 +PKPUPR_D: .long 0x00 +PLPUPR_D: .long 0x00 +PMPUPR_D: .long 0xfc +PNPUPR_D: .long 0x00 +PPUPR1_D: .long 0xffbf +PPUPR2_D: .long 0xff00 +P1MSELR_D: .long 0x3780 +P2MSELR_D: .long 0x0000 + +/*------- LBSC -------*/ +PASCR_A: .long 0xff000070 +PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */ + +BCR_A: .long BCR +CS0BCR_A: .long CS0BCR +CS0WCR_A: .long CS0WCR +CS1BCR_A: .long CS1BCR +CS1WCR_A: .long CS1WCR +CS2BCR_A: .long CS2BCR +CS2WCR_A: .long CS2WCR +CS3BCR_A: .long CS3BCR +CS3WCR_A: .long CS3WCR +CS4BCR_A: .long CS4BCR +CS4WCR_A: .long CS4WCR +CS5BCR_A: .long CS5BCR +CS5WCR_A: .long CS5WCR +CS6BCR_A: .long CS6BCR +CS6WCR_A: .long CS6WCR + +BCR_D: .long 0x80000003 +CS0BCR_D: .long 0x22222340 +CS0WCR_D: .long 0x00111118 +CS1BCR_D: .long 0x11111100 +CS1WCR_D: .long 0x33333303 +CS4BCR_D: .long 0x11111300 +CS4WCR_D: .long 0x00101012 + +/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */ +CS_USB_BCR_D: .long 0x11111200 +CS_USB_WCR_D: .long 0x00020004 + +/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */ +CS_SD_BCR_D: .long 0x00000300 +CS_SD_WCR_D: .long 0x00030108 + +/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */ +CS_I2C_BCR_D: .long 0x11111100 +CS_I2C_WCR_D: .long 0x00000003 + +CCR_A: .long 0xff00001c +CCR_D: .long 0x0000090b + diff --git a/board/sh7785lcr/rtl8169.h b/board/sh7785lcr/rtl8169.h new file mode 100644 index 0000000..d1c0d64 --- /dev/null +++ b/board/sh7785lcr/rtl8169.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define PCIREG_8(_adr) (*(volatile unsigned char *)(_adr)) +#define PCIREG_32(_adr) (*(volatile unsigned long *)(_adr)) +#define PCI_PAR PCIREG_32(0xfe0401c0) +#define PCI_PDR PCIREG_32(0xfe040220) +#define PCI_CR PCIREG_32(0xfe040100) +#define PCI_CONF1 PCIREG_32(0xfe040004) + +#define HIGH 1 +#define LOW 0 + +#define PCI_PROG 0x80 +#define PCI_EEP_ADDRESS (unsigned short)0x0007 +#define PCI_MAC_ADDRESS_SIZE 3 + +#define TIME1 100 +#define TIME2 20000 + +#define BIT_DUMMY 0 +#define MAC_EEP_READ 1 +#define MAC_EEP_WRITE 2 +#define MAC_EEP_ERACE 3 +#define MAC_EEP_EWEN 4 +#define MAC_EEP_EWDS 5 + +/* RTL8169 */ +const unsigned short EEPROM_W_Data_8169_A[] = { + 0x8129, 0x10ec, 0x8169, 0x1154, 0x032b, + 0x4020, 0xa101 +}; +const unsigned short EEPROM_W_Data_8169_B[] = { + 0x4d15, 0xf7c2, 0x8000, 0x0000, 0x0000, 0x1300, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 +}; + diff --git a/board/sh7785lcr/rtl8169_mac.c b/board/sh7785lcr/rtl8169_mac.c new file mode 100644 index 0000000..2bc873b --- /dev/null +++ b/board/sh7785lcr/rtl8169_mac.c @@ -0,0 +1,349 @@ +/* + * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include "rtl8169.h" + +static unsigned char *PCI_MEMR; + +static void mac_delay(unsigned int cnt) +{ + udelay(cnt); +} + +static void mac_pci_setup(void) +{ + unsigned long pci_data; + + PCI_PAR = 0x00000010; + PCI_PDR = 0x00001000; + PCI_PAR = 0x00000004; + pci_data = PCI_PDR; + PCI_PDR = pci_data | 0x00000007; + PCI_PAR = 0x00000010; + + PCI_MEMR = (unsigned char *)((PCI_PDR | 0xFE240050) & 0xFFFFFFF0); +} + +static void EECS(int level) +{ + unsigned char data = *PCI_MEMR; + + if (level) + *PCI_MEMR = data | 0x08; + else + *PCI_MEMR = data & 0xf7; +} + +static void EECLK(int level) +{ + unsigned char data = *PCI_MEMR; + + if (level) + *PCI_MEMR = data | 0x04; + else + *PCI_MEMR = data & 0xfb; +} + +static void EEDI(int level) +{ + unsigned char data = *PCI_MEMR; + + if (level) + *PCI_MEMR = data | 0x02; + else + *PCI_MEMR = data & 0xfd; +} + +static inline void sh7785lcr_bitset(unsigned short bit) +{ + if (bit) + EEDI(HIGH); + else + EEDI(LOW); + + EECLK(LOW); + mac_delay(TIME1); + EECLK(HIGH); + mac_delay(TIME1); + EEDI(LOW); +} + +static inline unsigned char sh7785lcr_bitget(void) +{ + unsigned char bit; + + EECLK(LOW); + mac_delay(TIME1); + bit = *PCI_MEMR & 0x01; + EECLK(HIGH); + mac_delay(TIME1); + + return bit; +} + +static inline void sh7785lcr_setcmd(unsigned char command) +{ + sh7785lcr_bitset(BIT_DUMMY); + switch (command) { + case MAC_EEP_READ: + sh7785lcr_bitset(1); + sh7785lcr_bitset(1); + sh7785lcr_bitset(0); + break; + case MAC_EEP_WRITE: + sh7785lcr_bitset(1); + sh7785lcr_bitset(0); + sh7785lcr_bitset(1); + break; + case MAC_EEP_ERACE: + sh7785lcr_bitset(1); + sh7785lcr_bitset(1); + sh7785lcr_bitset(1); + break; + case MAC_EEP_EWEN: + sh7785lcr_bitset(1); + sh7785lcr_bitset(0); + sh7785lcr_bitset(0); + break; + case MAC_EEP_EWDS: + sh7785lcr_bitset(1); + sh7785lcr_bitset(0); + sh7785lcr_bitset(0); + break; + default: + break; + } +} + +static inline unsigned short sh7785lcr_getdt(void) +{ + unsigned short data = 0; + int i; + + sh7785lcr_bitget(); /* DUMMY */ + for (i = 0 ; i < 16 ; i++) { + data <<= 1; + data |= sh7785lcr_bitget(); + } + return data; +} + +static inline void sh7785lcr_setadd(unsigned short address) +{ + sh7785lcr_bitset(address & 0x0020); /* A5 */ + sh7785lcr_bitset(address & 0x0010); /* A4 */ + sh7785lcr_bitset(address & 0x0008); /* A3 */ + sh7785lcr_bitset(address & 0x0004); /* A2 */ + sh7785lcr_bitset(address & 0x0002); /* A1 */ + sh7785lcr_bitset(address & 0x0001); /* A0 */ +} + +static inline void sh7785lcr_setdata(unsigned short data) +{ + sh7785lcr_bitset(data & 0x8000); + sh7785lcr_bitset(data & 0x4000); + sh7785lcr_bitset(data & 0x2000); + sh7785lcr_bitset(data & 0x1000); + sh7785lcr_bitset(data & 0x0800); + sh7785lcr_bitset(data & 0x0400); + sh7785lcr_bitset(data & 0x0200); + sh7785lcr_bitset(data & 0x0100); + sh7785lcr_bitset(data & 0x0080); + sh7785lcr_bitset(data & 0x0040); + sh7785lcr_bitset(data & 0x0020); + sh7785lcr_bitset(data & 0x0010); + sh7785lcr_bitset(data & 0x0008); + sh7785lcr_bitset(data & 0x0004); + sh7785lcr_bitset(data & 0x0002); + sh7785lcr_bitset(data & 0x0001); +} + +static void sh7785lcr_datawrite(const unsigned short *data, unsigned short address, + unsigned int count) +{ + unsigned int i; + + for (i = 0; i < count; i++) { + EECS(HIGH); + EEDI(LOW); + mac_delay(TIME1); + + sh7785lcr_setcmd(MAC_EEP_WRITE); + sh7785lcr_setadd(address++); + sh7785lcr_setdata(*(data + i)); + + EECLK(LOW); + EEDI(LOW); + EECS(LOW); + mac_delay(TIME2); + } +} + +static void sh7785lcr_macerase(void) +{ + unsigned int i; + unsigned short pci_address = 7; + + for (i = 0; i < 3; i++) { + EECS(HIGH); + EEDI(LOW); + mac_delay(TIME1); + sh7785lcr_setcmd(MAC_EEP_ERACE); + sh7785lcr_setadd(pci_address++); + mac_delay(TIME1); + EECLK(LOW); + EEDI(LOW); + EECS(LOW); + } + + mac_delay(TIME2); + + printf("\n\nErace End\n"); + for (i = 0; i < 10; i++) + mac_delay(TIME2); +} + +static void sh7785lcr_macwrite(unsigned short *data) +{ + sh7785lcr_macerase(); + + sh7785lcr_datawrite(EEPROM_W_Data_8169_A, 0x0000, 7); + sh7785lcr_datawrite(data, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE); + sh7785lcr_datawrite(EEPROM_W_Data_8169_B, 0x000a, 54); +} + +void sh7785lcr_macdtrd(unsigned char *buf, unsigned short address, unsigned int count) +{ + unsigned int i; + unsigned short wk; + + for (i = 0 ; i < count; i++) { + EECS(HIGH); + EEDI(LOW); + mac_delay(TIME1); + sh7785lcr_setcmd(MAC_EEP_READ); + sh7785lcr_setadd(address++); + wk = sh7785lcr_getdt(); + + *buf++ = (unsigned char)(wk & 0xff); + *buf++ = (unsigned char)((wk >> 8) & 0xff); + EECLK(LOW); + EEDI(LOW); + EECS(LOW); + } +} + +static void sh7785lcr_macadrd(unsigned char *buf) +{ + *PCI_MEMR = PCI_PROG; + + sh7785lcr_macdtrd(buf, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE); +} + +static void sh7785lcr_eepewen(void) +{ + *PCI_MEMR = PCI_PROG; + mac_delay(TIME1); + EECS(LOW); + EECLK(LOW); + EEDI(LOW); + EECS(HIGH); + mac_delay(TIME1); + + sh7785lcr_setcmd(MAC_EEP_EWEN); + sh7785lcr_bitset(1); + sh7785lcr_bitset(1); + sh7785lcr_bitset(BIT_DUMMY); + sh7785lcr_bitset(BIT_DUMMY); + sh7785lcr_bitset(BIT_DUMMY); + sh7785lcr_bitset(BIT_DUMMY); + + EECLK(LOW); + EEDI(LOW); + EECS(LOW); + mac_delay(TIME1); +} + +void mac_write(unsigned short *data) +{ + mac_pci_setup(); + sh7785lcr_eepewen(); + sh7785lcr_macwrite(data); +} + +void mac_read(void) +{ + unsigned char data[6]; + + mac_pci_setup(); + sh7785lcr_macadrd(data); + printf("Mac = %02x:%02x:%02x:%02x:%02x:%02x\n", + data[0], data[1], data[2], data[3], data[4], data[5]); +} + +int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + unsigned char mac[6]; + char *s, *e; + + if (argc != 2) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + s = argv[1]; + + for (i = 0; i < 6; i++) { + mac[i] = s ? simple_strtoul(s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + mac_write((unsigned short *)mac); + + return 0; +} + +U_BOOT_CMD( + setmac, 2, 1, do_set_mac, + "setmac - write MAC address for RTL8110SCL\n", + "\n" + "setmac <mac address> - write MAC address for RTL8110SCL\n" +); + +int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (argc != 1) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + mac_read(); + + return 0; +} + +U_BOOT_CMD( + printmac, 1, 1, do_print_mac, + "printmac - print MAC address for RTL8110\n", + "\n" + " - print MAC address for RTL8110\n" +); + diff --git a/board/sh7785lcr/selfcheck.c b/board/sh7785lcr/selfcheck.c new file mode 100644 index 0000000..9c228e5 --- /dev/null +++ b/board/sh7785lcr/selfcheck.c @@ -0,0 +1,173 @@ +/* + * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/pci.h> + +#if defined(CONFIG_CPU_32BIT) +#define NOCACHE_OFFSET 0x00000000 +#else +#define NOCACHE_OFFSET 0xa0000000 +#endif +#define PLD_LEDCR (0x04000008 + NOCACHE_OFFSET) +#define PLD_SWSR (0x0400000a + NOCACHE_OFFSET) +#define PLD_VERSR (0x0400000c + NOCACHE_OFFSET) + +#define SM107_DEVICEID (0x13e00060 + NOCACHE_OFFSET) + +static void wait_ms(unsigned long time) +{ + while (time--) + udelay(1000); +} + +static void test_pld(void) +{ + printf("PLD version = %04x\n", readb(PLD_VERSR)); +} + +static void test_sm107(void) +{ + printf("SM107 device ID = %04x\n", readl(SM107_DEVICEID)); +} + +static void test_led(void) +{ + printf("turn on LEDs 3, 5, 7, 9\n"); + writeb(0x55, PLD_LEDCR); + wait_ms(2000); + printf("turn on LEDs 4, 6, 8, 10\n"); + writeb(0xaa, PLD_LEDCR); + wait_ms(2000); + writeb(0x00, PLD_LEDCR); +} + +static void test_dipsw(void) +{ + printf("Please DIPSW set = B'0101\n"); + while (readb(PLD_SWSR) != 0x05) { + if (ctrlc()) + return; + } + printf("Please DIPSW set = B'1010\n"); + while (readb(PLD_SWSR) != 0x0A) { + if (ctrlc()) + return; + } + printf("DIPSW OK\n"); +} + +static void test_net(void) +{ + unsigned long data; + + writel(0x80000000, 0xfe0401c0); + data = readl(0xfe040220); + if (data == 0x816910ec) + printf("Ethernet OK\n"); + else + printf("Ethernet NG, data = %08x\n", data); +} + +static void test_sata(void) +{ + unsigned long data; + + writel(0x80000800, 0xfe0401c0); + data = readl(0xfe040220); + if (data == 0x35121095) + printf("SATA OK\n"); + else + printf("SATA NG, data = %08x\n", data); +} + +static void test_pci(void) +{ + writel(0x80001800, 0xfe0401c0); + printf("PCI CN1 ID = %08x\n", readl(0xfe040220)); + + writel(0x80001000, 0xfe0401c0); + printf("PCI CN2 ID = %08x\n", readl(0xfe040220)); +} + +int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *cmd; + + if (argc != 2) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + cmd = argv[1]; + switch (cmd[0]) { + case 'a': /* all */ + test_pld(); + test_led(); + test_dipsw(); + test_sm107(); + test_net(); + test_sata(); + test_pci(); + break; + case 'p': /* pld or pci */ + if (cmd[1] == 'l') + test_pld(); + else + test_pci(); + break; + case 'l': /* led */ + test_led(); + break; + case 'd': /* dipsw */ + test_dipsw(); + break; + case 's': /* sm107 or sata */ + if (cmd[1] == 'm') + test_sm107(); + else + test_sata(); + break; + case 'n': /* net */ + test_net(); + break; + default: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + return 0; +} + +U_BOOT_CMD( + hwtest, 2, 1, do_hw_test, + "hwtest - hardware test for R0P7785LC0011RL board\n", + "\n" + "hwtest all - test all hardware\n" + "hwtest pld - output PLD version\n" + "hwtest led - turn on LEDs\n" + "hwtest dipsw - test DIP switch\n" + "hwtest sm107 - output SM107 version\n" + "hwtest net - check RTL8110 ID\n" + "hwtest sata - check SiI3512 ID\n" + "hwtest pci - output PCI slot device ID\n" +); + diff --git a/board/sh7785lcr/sh7785lcr.c b/board/sh7785lcr/sh7785lcr.c new file mode 100644 index 0000000..5b9c403 --- /dev/null +++ b/board/sh7785lcr/sh7785lcr.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/pci.h> + +int checkboard(void) +{ + puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n"); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_SDRAM_SIZE; + printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +static struct pci_controller hose; +void pci_init_board(void) +{ + pci_sh7780_init(&hose); +} + diff --git a/board/sh7785lcr/u-boot.lds b/board/sh7785lcr/u-boot.lds new file mode 100644 index 0000000..f0109eb --- /dev/null +++ b/board/sh7785lcr/u-boot.lds @@ -0,0 +1,97 @@ +/* + * Copyrigth (c) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * Copyrigth (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + . = 0x08000000 + (128 * 1024 * 1024) - (512 * 1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh4/start.o (.text) + . = ALIGN(8192); + common/environment.o (.ppcenv) + . = ALIGN(8192); + common/environment.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} + diff --git a/doc/README.sh7785lcr b/doc/README.sh7785lcr new file mode 100644 index 0000000..0770276 --- /dev/null +++ b/doc/README.sh7785lcr @@ -0,0 +1,83 @@ +======================================== +Renesas Technology R0P7785LC0011RL board +======================================== + +This board specification: +========================= + +The R0P7785LC0011RL(board config name:sh7785lcr) has the following device: + + - SH7785 (SH-4A) + - DDR2-SDRAM 512MB + - NOR Flash 64MB + - 2D Graphic controller + - SATA controller + - Ethernet controller + - USB host/peripheral controller + - SD controller + - I2C controller + - RTC + +This board has 2 physical memory maps. It can be changed with DIP switch(S2-5). + + phys address | S2-5 = OFF | S2-5 = ON + -------------------------------+---------------+--------------- + 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash + 0x04000000 - 0x05ffffff(CS1) | PLD | PLD + 0x06000000 - 0x07ffffff(CS1) | reserved | I2C + 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM + 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM + 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107 + 0x14000000 - 0x17ffffff(CS5) | I2C | USB + 0x18000000 - 0x1bffffff(CS6) | reserved | SD + 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use) + + +This board specific command: +============================ + +This board has the following its specific command: + + - hwtest + - printmac + - setmac + + +1. hwtest + +This is self-check command. This command has the following options: + + - all : test all hardware + - pld : output PLD version + - led : turn on LEDs + - dipsw : test DIP switch + - sm107 : output SM107 version + - net : check RTL8110 ID + - sata : check SiI3512 ID + - net : output PCI slot device ID + +i.e) +=> hwtest led +turn on LEDs 3, 5, 7, 9 +turn on LEDs 4, 6, 8, 10 + +=> hwtest net +Ethernet OK + + +2. printmac + +This command outputs MAC address of this board. + +i.e) +=> printmac +MAC = 00:00:87:**:**:** + + +3. setmac + +This command writes MAC address of this board. + +i.e) +=> setmac 00:00:87:**:**:** + diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h new file mode 100644 index 0000000..63f22e9 --- /dev/null +++ b/include/configs/sh7785lcr.h @@ -0,0 +1,167 @@ +/* + * Configuation settings for the Renesas Technology R0P7785LC0011RL board + * + * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SH7785LCR_H +#define __SH7785LCR_H + +#undef DEBUG +#define CONFIG_SH 1 +#define CONFIG_SH4A 1 +#define CONFIG_CPU_SH7785 1 +#define CONFIG_SH7785LCR 1 + +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_NFS +#define CONFIG_CMD_DFL +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_RUN +#define CONFIG_CMD_ENV + +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootdevice=0:1\0" \ + "usbload=usb reset;usbboot;usb stop;bootm\0" + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +/* MEMORY */ +#define SH7785LCR_SDRAM_BASE (0x08000000) +#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024) +#define SH7785LCR_FLASH_BASE_1 (0xa0000000) +#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) +#define SH7785LCR_USB_BASE (0xb4000000) + +#define CFG_LONGHELP +#define CFG_PROMPT "=> " +#define CFG_CBSIZE 256 +#define CFG_PBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_BARGSIZE 512 +#define CFG_BAUDRATE_TABLE { 115200 } + +/* SCIF */ +#define CFG_SCIF_CONSOLE 1 +#define CONFIG_CONS_SCIF1 1 +#define CONFIG_SCIF_EXT_CLOCK 1 +#undef CFG_CONSOLE_INFO_QUIET +#undef CFG_CONSOLE_OVERWRITE_ROUTINE +#undef CFG_CONSOLE_ENV_OVERWRITE + + +#define CFG_MEMTEST_START (SH7785LCR_SDRAM_BASE) +#define CFG_MEMTEST_END (CFG_MEMTEST_START + \ + (SH7785LCR_SDRAM_SIZE) - \ + 4 * 1024 * 1024) +#undef CFG_ALT_MEMTEST +#undef CFG_MEMTEST_SCRATCH +#undef CFG_LOADS_BAUD_CHANGE + +#define CFG_SDRAM_BASE (SH7785LCR_SDRAM_BASE) +#define CFG_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE) +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 16 * 1024 * 1024) + +#define CFG_MONITOR_BASE (SH7785LCR_FLASH_BASE_1) +#define CFG_MONITOR_LEN (512 * 1024) +#define CFG_MALLOC_LEN (512 * 1024) +#define CFG_GBL_DATA_SIZE (256) +#define CFG_BOOTMAPSZ (8 * 1024 * 1024) + +/* FLASH */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#undef CFG_FLASH_QUIET_TEST +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_BASE (SH7785LCR_FLASH_BASE_1) +#define CFG_MAX_FLASH_SECT 512 + +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE + \ + (0 * SH7785LCR_FLASH_BANK_SIZE) } + +#define CFG_FLASH_ERASE_TOUT (3 * 1000) +#define CFG_FLASH_WRITE_TOUT (3 * 1000) +#define CFG_FLASH_LOCK_TOUT (3 * 1000) +#define CFG_FLASH_UNLOCK_TOUT (3 * 1000) + +#undef CFG_FLASH_PROTECTION +#undef CFG_DIRECT_FLASH_TFTP + +/* R8A66597 */ +#define LITTLEENDIAN /* for include/usb.h */ +#define CONFIG_USB_R8A66597_HCD +#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE +#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ +#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ +#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ + +/* PCI Controller */ +#define CONFIG_PCI +#define CONFIG_SH4_PCI +#define CONFIG_SH7780_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW 1 + +#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ + +#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ + +/* Network device (RTL8169) support */ +#define CONFIG_NET_MULTI +#define CONFIG_RTL8169 + +/* ENV setting */ +#define CFG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE 1 +#define CFG_ENV_SECT_SIZE (256 * 1024) +#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE) + +/* Board Clock */ +/* The SCIF used external clock. system clock only used timer. */ +#define CONFIG_SYS_CLK_FREQ 50000000 +#define TMU_CLK_DIVIDER 4 +#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) + +#endif /* __SH7785LCR_H */ |