diff options
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/4xx_pcie.c | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c index a87e93b..43b972f 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c @@ -227,7 +227,6 @@ static void pcie_dmer_enable(void) static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, int offset, int len, u32 *val) { - u8 *address; *val = 0; if (validate_endpoint(hose)) @@ -255,7 +254,7 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) return 0; - address = pcie_get_base(hose, devfn); + pcie_get_base(hose, devfn); offset += devfn << 4; /* @@ -287,8 +286,6 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, int offset, int len, u32 val) { - u8 *address; - if (validate_endpoint(hose)) return 0; /* No upstream config access */ @@ -307,7 +304,7 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) return 0; - address = pcie_get_base(hose, devfn); + pcie_get_base(hose, devfn); offset += devfn << 4; /* @@ -1063,7 +1060,6 @@ int ppc4xx_init_pcie_endport(int port) void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) { volatile void *mbase = NULL; - volatile void *rmbase = NULL; pci_set_ops(hose, pcie_read_config_byte, @@ -1076,18 +1072,15 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) switch (port) { case 0: mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE; - rmbase = (u32 *)CONFIG_SYS_PCIE0_CFGBASE; hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE; break; case 1: mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE; - rmbase = (u32 *)CONFIG_SYS_PCIE1_CFGBASE; hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE; break; #if CONFIG_SYS_PCIE_NR_PORTS > 2 case 2: mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE; - rmbase = (u32 *)CONFIG_SYS_PCIE2_CFGBASE; hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE; break; #endif |