diff options
| -rw-r--r-- | arch/powerpc/cpu/mpc8260/Kconfig | 4 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc8260/pci.c | 2 | ||||
| -rw-r--r-- | board/tqc/tqm8272/Kconfig | 12 | ||||
| -rw-r--r-- | board/tqc/tqm8272/MAINTAINERS | 6 | ||||
| -rw-r--r-- | board/tqc/tqm8272/Makefile | 8 | ||||
| -rw-r--r-- | board/tqc/tqm8272/nand.c | 264 | ||||
| -rw-r--r-- | board/tqc/tqm8272/tqm8272.c | 944 | ||||
| -rw-r--r-- | board/tqc/tqm8272/tqm8272.h | 37 | ||||
| -rw-r--r-- | configs/TQM8272_defconfig | 3 | ||||
| -rw-r--r-- | doc/README.scrapyard | 1 | ||||
| -rw-r--r-- | include/configs/TQM8272.h | 735 |
11 files changed, 1 insertions, 2015 deletions
diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig index e28628f..2541400 100644 --- a/arch/powerpc/cpu/mpc8260/Kconfig +++ b/arch/powerpc/cpu/mpc8260/Kconfig @@ -55,9 +55,6 @@ config TARGET_VOVPN_GW config TARGET_KM82XX bool "Support km82xx" -config TARGET_TQM8272 - bool "Support TQM8272" - endchoice source "board/atc/Kconfig" @@ -76,6 +73,5 @@ source "board/pm826/Kconfig" source "board/pm828/Kconfig" source "board/ppmc8260/Kconfig" source "board/sacsng/Kconfig" -source "board/tqc/tqm8272/Kconfig" endmenu diff --git a/arch/powerpc/cpu/mpc8260/pci.c b/arch/powerpc/cpu/mpc8260/pci.c index 0a47fdc..f7bb05d 100644 --- a/arch/powerpc/cpu/mpc8260/pci.c +++ b/arch/powerpc/cpu/mpc8260/pci.c @@ -262,8 +262,6 @@ void pci_mpc8250_init (struct pci_controller *hose) | SIUMCR_CS10PC00 | SIUMCR_BCTLC00 | SIUMCR_MMR11; -#elif defined(CONFIG_TQM8272) -/* nothing to do for this Board here */ #else /* * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), diff --git a/board/tqc/tqm8272/Kconfig b/board/tqc/tqm8272/Kconfig deleted file mode 100644 index 7b5cd8b..0000000 --- a/board/tqc/tqm8272/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_TQM8272 - -config SYS_BOARD - default "tqm8272" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM8272" - -endif diff --git a/board/tqc/tqm8272/MAINTAINERS b/board/tqc/tqm8272/MAINTAINERS deleted file mode 100644 index 988d2b1..0000000 --- a/board/tqc/tqm8272/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TQM8272 BOARD -#M: - -S: Maintained -F: board/tqc/tqm8272/ -F: include/configs/TQM8272.h -F: configs/TQM8272_defconfig diff --git a/board/tqc/tqm8272/Makefile b/board/tqc/tqm8272/Makefile deleted file mode 100644 index 8bf0241..0000000 --- a/board/tqc/tqm8272/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = tqm8272.o ../tqm8xx/load_sernum_ethaddr.o nand.o diff --git a/board/tqc/tqm8272/nand.c b/board/tqc/tqm8272/nand.c deleted file mode 100644 index 7fb2dfa..0000000 --- a/board/tqc/tqm8272/nand.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> - -#include "tqm8272.h" - -/* UPM pattern for bus clock = 66.7 MHz */ -static const uint upmTable67[] = -{ - /* Offset UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000, - /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ - /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, - /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 100 MHz */ -static const uint upmTable100[] = -{ - /* Offset UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000, - /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ - /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00, - /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 133.3 MHz */ -static const uint upmTable133[] = -{ - /* Offset UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000, - /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ - /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00, - /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -static int chipsel = 0; - -#if defined(CONFIG_CMD_NAND) - -#include <nand.h> -#include <linux/mtd/mtd.h> - -static u8 hwctl = 0; - -static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - - if (hwctl & 0x1) { - WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS); - } else if (hwctl & 0x2) { - WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS); - } else { - WRITE_NAND(byte, base); - } -} - -static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - hwctl |= 0x1; - else - hwctl &= ~0x1; - if ( ctrl & NAND_ALE ) - hwctl |= 0x2; - else - hwctl &= ~0x2; - } - if (cmd != NAND_CMD_NONE) - upmnand_write_byte (mtd, cmd); -} - -static u_char upmnand_read_byte(struct mtd_info *mtdinfo) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - - return READ_NAND(base); -} - -static int tqm8272_dev_ready(struct mtd_info *mtdinfo) -{ - /* constant delay (see also tR in the datasheet) */ - udelay(12); \ - return 1; -} - -#ifndef CONFIG_NAND_SPL -static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - int i; - - for (i = 0; i< len; i++) - buf[i] = *base; -} - -static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - int i; - - for (i = 0; i< len; i++) - *base = buf[i]; -} - -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - int i; - - for (i = 0; i < len; i++) - if (buf[i] != *base) - return -1; - return 0; -} -#endif -#endif /* #ifndef CONFIG_NAND_SPL */ - -void board_nand_select_device(struct nand_chip *nand, int chip) -{ - chipsel = chip; -} - -int board_nand_init(struct nand_chip *nand) -{ - static int UpmInit = 0; - volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immr->im_memctl; - - if (hwinf.nand == 0) return -1; - - /* Setup the UPM */ - if (UpmInit == 0) { - switch (hwinf.busclk_real) { - case 100000000: - upmconfig (UPMB, (uint *) upmTable100, - sizeof (upmTable100) / sizeof (uint)); - break; - case 133333333: - upmconfig (UPMB, (uint *) upmTable133, - sizeof (upmTable133) / sizeof (uint)); - break; - default: - upmconfig (UPMB, (uint *) upmTable67, - sizeof (upmTable67) / sizeof (uint)); - break; - } - UpmInit = 1; - } - - /* Setup the memctrl */ - memctl->memc_or3 = CONFIG_SYS_NAND_OR; - memctl->memc_br3 = CONFIG_SYS_NAND_BR; - memctl->memc_mbmr = (MxMR_OP_NORM); - - nand->ecc.mode = NAND_ECC_SOFT; - - nand->cmd_ctrl = upmnand_hwcontrol; - nand->read_byte = upmnand_read_byte; - nand->dev_ready = tqm8272_dev_ready; - -#ifndef CONFIG_NAND_SPL - nand->write_buf = tqm8272_write_buf; - nand->read_buf = tqm8272_read_buf; -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - nand->verify_buf = tqm8272_verify_buf; -#endif -#endif - - /* - * Select required NAND chip - */ - board_nand_select_device(nand, 0); - return 0; -} - -#endif diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c deleted file mode 100644 index d650868..0000000 --- a/board/tqc/tqm8272/tqm8272.c +++ /dev/null @@ -1,944 +0,0 @@ -/* - * (C) Copyright 2006 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> - -#include <command.h> -#include <netdev.h> -#ifdef CONFIG_PCI -#include <pci.h> -#include <asm/m8260_pci.h> -#endif -#include "tqm8272.h" - -#if 0 -#define deb_printf(fmt,arg...) \ - printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg) -#else -#define deb_printf(fmt,arg...) \ - do { } while (0) -#endif - -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -unsigned long board_get_cpu_clk_f (void); -#endif - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ - /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ - /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ - /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ - /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ - /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 MDC */ - /* PC16 */ { 1, 0, 0, 0, 0, 0 }, /* PC16 MDIO*/ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* PC10 */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* PC9 */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* PC5 SMC1 TXD */ - /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* PC4 SMC1 RXD */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ -#if defined(CONFIG_SYS_I2C_SOFT) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* UPM pattern for slow init */ -static const uint upmTableSlow[] = -{ - /* Offset UPM Read Single RAM array entry */ - /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00, - /* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry */ - /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80, - /* 0x1C */ 0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for fast init */ -static const uint upmTableFast[] = -{ - /* Offset UPM Read Single RAM array entry */ - /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00, - /* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry */ - /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00, - /* 0x1C */ 0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - char *p = (char *) HWIB_INFO_START_ADDR; - - puts ("Board: "); - if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - puts (p); - } else { - puts ("No HWIB assuming TQM8272"); - } - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -static int get_cas_latency (void) -{ - /* get it from the option -ts in CIB */ - /* default is 3 */ - int ret = 3; - int pos = 0; - char *p = (char *) CIB_INFO_START_ADDR; - - while ((*p != '\0') && (pos < CIB_INFO_LEN)) { - if (*p < ' ' || *p > '~') { /* ASCII strings! */ - return ret; - } - if (*p == '-') { - if ((p[1] == 't') && (p[2] == 's')) { - return (p[4] - '0'); - } - } - p++; - pos++; - } - return ret; -} -#endif - -static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col) -{ -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) - int clk = board_get_cpu_clk_f (); - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - int busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0); - int cas; - - sdmr = sdmr & ~(PSDMR_RFRC_MSK | PSDMR_PRETOACT_MSK | PSDMR_WRC_MSK | \ - PSDMR_BUFCMD); - if (busmode) { - switch (clk) { - case 66666666: - sdmr |= (PSDMR_RFRC_66MHZ_60X | \ - PSDMR_PRETOACT_66MHZ_60X | \ - PSDMR_WRC_66MHZ_60X | \ - PSDMR_BUFCMD_66MHZ_60X); - break; - case 100000000: - sdmr |= (PSDMR_RFRC_100MHZ_60X | \ - PSDMR_PRETOACT_100MHZ_60X | \ - PSDMR_WRC_100MHZ_60X | \ - PSDMR_BUFCMD_100MHZ_60X); - break; - - } - } else { - switch (clk) { - case 66666666: - sdmr |= (PSDMR_RFRC_66MHZ_SINGLE | \ - PSDMR_PRETOACT_66MHZ_SINGLE | \ - PSDMR_WRC_66MHZ_SINGLE | \ - PSDMR_BUFCMD_66MHZ_SINGLE); - break; - case 100000000: - sdmr |= (PSDMR_RFRC_100MHZ_SINGLE | \ - PSDMR_PRETOACT_100MHZ_SINGLE | \ - PSDMR_WRC_100MHZ_SINGLE | \ - PSDMR_BUFCMD_100MHZ_SINGLE); - break; - case 133333333: - sdmr |= (PSDMR_RFRC_133MHZ_SINGLE | \ - PSDMR_PRETOACT_133MHZ_SINGLE | \ - PSDMR_WRC_133MHZ_SINGLE | \ - PSDMR_BUFCMD_133MHZ_SINGLE); - break; - } - } - cas = get_cas_latency(); - sdmr &=~ (PSDMR_CL_MSK | PSDMR_LDOTOPRE_MSK); - sdmr |= cas; - sdmr |= ((cas - 1) << 6); - return sdmr; -#else - return sdmr; -#endif -} - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base, int col) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that - * we are configuring CS1 if base != 0 - */ - sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; - orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; - - *orx_ptr = orx; - sdmr = set_sdram_timing (sdmr_ptr, sdmr, col); - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CONFIG_SYS_RAMBOOT - long size8, size9; -#endif - long psize; - - psize = 16 * 1024 * 1024; - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#ifndef CONFIG_SYS_RAMBOOT - /* 60x SDRAM setup: - */ - size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE, 8); - size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL, - (uchar *) CONFIG_SYS_SDRAM_BASE, 9); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL - %ld MB, ", psize >> 20); - } else { - psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE, 8); - printf ("(60x:8COL - %ld MB, ", psize >> 20); - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - icache_enable (); - - return (psize); -} - - -static inline int scanChar (char *p, int len, unsigned long *number) -{ - int akt = 0; - - *number = 0; - while (akt < len) { - if ((*p >= '0') && (*p <= '9')) { - *number *= 10; - *number += *p - '0'; - p += 1; - } else { - if (*p == '-') return akt; - return -1; - } - akt ++; - } - return akt; -} - -static int dump_hwib(void) -{ - HWIB_INFO *hw = &hwinf; - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - if (i < 0) - buf[0] = '\0'; - - if (hw->OK) { - printf ("HWIB on %x\n", HWIB_INFO_START_ADDR); - printf ("serial : %s\n", buf); - printf ("ethaddr: %s\n", hw->ethaddr); - printf ("FLASH : %x nr:%d\n", hw->flash, hw->flash_nr); - printf ("RAM : %x cs:%d\n", hw->ram, hw->ram_cs); - printf ("CPU : %lu\n", hw->cpunr); - printf ("CAN : %d\n", hw->can); - if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom); - else printf ("No EEprom\n"); - if (hw->nand) { - printf ("NAND : %x\n", hw->nand); - printf ("NAND CS: %d\n", hw->nand_cs); - } else { printf ("No NAND\n");} - printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII")); - printf (" real : %s\n", (immr->im_siu_conf.sc_bcr & BCR_EBM ? \ - "60x" : "Single PQII")); - printf ("Option : %lx\n", hw->option); - printf ("%s Security Engine\n", (hw->SecEng ? "with" : "no")); - printf ("CPM Clk: %d\n", hw->cpmcl); - printf ("CPU Clk: %d\n", hw->cpucl); - printf ("Bus Clk: %d\n", hw->buscl); - if (hw->busclk_real_ok) { - printf (" real Clk: %d\n", hw->busclk_real); - } - printf ("CAS : %d\n", get_cas_latency()); - } else { - printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR); - } - return 0; -} - -static inline int search_real_busclk (int *clk) -{ - int part = 0, pos = 0; - char *p = (char *) CIB_INFO_START_ADDR; - int ok = 0; - - while ((*p != '\0') && (pos < CIB_INFO_LEN)) { - if (*p < ' ' || *p > '~') { /* ASCII strings! */ - return 0; - } - switch (part) { - default: - if (*p == '-') { - ++part; - } - break; - case 3: - if (*p == '-') { - ++part; - break; - } - if (*p == 'b') { - ok = 1; - p++; - break; - } - if (ok) { - switch (*p) { - case '6': - *clk = 66666666; - return 1; - break; - case '1': - if (p[1] == '3') { - *clk = 133333333; - } else { - *clk = 100000000; - } - return 1; - break; - } - } - break; - } - p++; - } - return 0; -} - -int analyse_hwib (void) -{ - char *p = (char *) HWIB_INFO_START_ADDR; - int anz; - int part = 1, i = 0, pos = 0; - HWIB_INFO *hw = &hwinf; - - deb_printf(" %s pointer: %p\n", __FUNCTION__, p); - /* Head = TQM */ - if (*((unsigned long *)p) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - deb_printf("No HWIB\n"); - return -1; - } - p += 3; - if (scanChar (p, 4, &hw->cpunr) < 0) { - deb_printf("No CPU\n"); - return -2; - } - p +=4; - - hw->flash = 0x200000 << (*p - 'A'); - p++; - hw->flash_nr = *p - '0'; - p++; - - hw->ram = 0x2000000 << (*p - 'A'); - p++; - if (*p == '2') { - hw->ram_cs = 2; - p++; - } - - if (*p == 'A') hw->can = 1; - if (*p == 'B') hw->can = 2; - p +=1; - p +=1; /* connector */ - if (*p != '0') { - hw->eeprom = 0x1000 << (*p - 'A'); - } - p++; - - if ((*p < '0') || (*p > '9')) { - /* NAND before z-option */ - hw->nand = 0x8000000 << (*p - 'A'); - p++; - hw->nand_cs = *p - '0'; - p += 2; - } - /* z-option */ - anz = scanChar (p, 4, &hw->option); - if (anz < 0) { - deb_printf("No option\n"); - return -3; - } - if (hw->option & 0x8) hw->Bus = 1; - p += anz; - if (*p != '-') { - deb_printf("No -\n"); - return -4; - } - p++; - /* C option */ - if (*p == 'E') { - hw->SecEng = 1; - p++; - } - switch (*p) { - case 'M': hw->cpucl = 266666666; - break; - case 'P': hw->cpucl = 300000000; - break; - case 'T': hw->cpucl = 400000000; - break; - default: - deb_printf("No CPU Clk: %c\n", *p); - return -5; - break; - } - p++; - switch (*p) { - case 'I': hw->cpmcl = 200000000; - break; - case 'M': hw->cpmcl = 300000000; - break; - default: - deb_printf("No CPM Clk\n"); - return -6; - break; - } - p++; - switch (*p) { - case 'B': hw->buscl = 66666666; - break; - case 'E': hw->buscl = 100000000; - break; - case 'F': hw->buscl = 133333333; - break; - default: - deb_printf("No BUS Clk\n"); - return -7; - break; - } - p++; - - hw->OK = 1; - /* search MAC Address */ - while ((*p != '\0') && (pos < CONFIG_SYS_HWINFO_SIZE)) { - if (*p < ' ' || *p > '~') { /* ASCII strings! */ - return 0; - } - switch (part) { - default: - if (*p == ' ') { - ++part; - i = 0; - } - break; - case 3: /* Copy MAC address */ - if (*p == ' ') { - ++part; - i = 0; - break; - } - hw->ethaddr[i++] = *p; - if ((i % 3) == 2) - hw->ethaddr[i++] = ':'; - break; - - } - p++; - } - - hw->busclk_real_ok = search_real_busclk (&hw->busclk_real); - return 0; -} - -#if defined(CONFIG_GET_CPU_STR_F) -/* !! This routine runs from Flash */ -char get_cpu_str_f (char *buf) -{ - char *p = (char *) HWIB_INFO_START_ADDR; - int i = 0; - - buf[i++] = 'M'; - buf[i++] = 'P'; - buf[i++] = 'C'; - if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - buf[i++] = *&p[3]; - buf[i++] = *&p[4]; - buf[i++] = *&p[5]; - buf[i++] = *&p[6]; - } else { - buf[i++] = '8'; - buf[i++] = '2'; - buf[i++] = '7'; - buf[i++] = 'x'; - } - buf[i++] = 0; - return 0; -} -#endif - -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -/* !! This routine runs from Flash */ -unsigned long board_get_cpu_clk_f (void) -{ - char *p = (char *) HWIB_INFO_START_ADDR; - int i = 0; - - if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - if (search_real_busclk (&i)) - return i; - } - return CONFIG_8260_CLKIN; -} -#endif - -#if CONFIG_BOARD_EARLY_INIT_R - -static int can_test (unsigned long off) -{ - volatile unsigned char *base = (unsigned char *) (CONFIG_SYS_CAN_BASE + off); - - *(base + 0x17) = 'T'; - *(base + 0x18) = 'Q'; - *(base + 0x19) = 'M'; - if ((*(base + 0x17) != 'T') || - (*(base + 0x18) != 'Q') || - (*(base + 0x19) != 'M')) { - return 0; - } - return 1; -} - -static int can_config_one (unsigned long off) -{ - volatile unsigned char *ctrl = (unsigned char *) (CONFIG_SYS_CAN_BASE + off); - volatile unsigned char *cpu_if = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x02); - volatile unsigned char *clkout = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x1f); - unsigned char temp; - - *cpu_if = 0x45; - temp = *ctrl; - temp |= 0x40; - *ctrl = temp; - *clkout = 0x20; - temp = *ctrl; - temp &= ~0x40; - *ctrl = temp; - return 0; -} - -static int can_config (void) -{ - int ret = 0; - can_config_one (0); - if (hwinf.can == 2) { - can_config_one (0x100); - } - /* make Test if they really there */ - ret += can_test (0); - ret += can_test (0x100); - return ret; -} - -static int init_can (void) -{ - volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immr->im_memctl; - int count = 0; - - if ((hwinf.OK) && (hwinf.can)) { - memctl->memc_or4 = CONFIG_SYS_CAN_OR; - memctl->memc_br4 = CONFIG_SYS_CAN_BR; - /* upm Init */ - upmconfig (UPMC, (uint *) upmTableFast, - sizeof (upmTableFast) / sizeof (uint)); - memctl->memc_mcmr = (MxMR_DSx_3_CYCL | - MxMR_GPL_x4DIS | - MxMR_RLFx_2X | - MxMR_WLFx_2X | - MxMR_OP_NORM); - /* can configure */ - count = can_config (); - printf ("CAN: %d @ %x\n", count, CONFIG_SYS_CAN_BASE); - if (hwinf.can != count) printf("!!! difference to HWIB\n"); - } else { - printf ("CAN: No\n"); - } - return 0; -} - -int board_early_init_r(void) -{ - analyse_hwib (); - init_can (); - return 0; -} -#endif - -int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - dump_hwib (); - return 0; -} - -U_BOOT_CMD( - hwib, 1, 1, do_hwib_dump, - "dump HWIB'", - "" -); - -#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE -static int get_flash_timing (void) -{ - /* get it from the option -tf in CIB */ - /* default is 0x00000c84 */ - int ret = 0x00000c84; - int pos = 0; - int nr = 0; - char *p = (char *) CIB_INFO_START_ADDR; - - while ((*p != '\0') && (pos < CIB_INFO_LEN)) { - if (*p < ' ' || *p > '~') { /* ASCII strings! */ - return ret; - } - if (*p == '-') { - if ((p[1] == 't') && (p[2] == 'f')) { - p += 6; - ret = 0; - while (nr < 8) { - if ((*p >= '0') && (*p <= '9')) { - ret *= 0x10; - ret += *p - '0'; - p += 1; - nr ++; - } else if ((*p >= 'A') && (*p <= 'F')) { - ret *= 10; - ret += *p - '7'; - p += 1; - nr ++; - } else { - if (nr < 8) return 0x00000c84; - return ret; - } - } - } - } - p++; - pos++; - } - return ret; -} - -/* Update the Flash_Size and the Flash Timing */ -int update_flash_size (int flash_size) -{ - volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immr->im_memctl; - unsigned long reg; - unsigned long tim; - - /* I must use reg, otherwise the board hang */ - reg = memctl->memc_or0; - reg &= ~ORxU_AM_MSK; - reg |= MEG_TO_AM(flash_size >> 20); - tim = get_flash_timing (); - reg &= ~0xfff; - reg |= (tim & 0xfff); - memctl->memc_or0 = reg; - return 0; -} -#endif - -#ifdef CONFIG_PCI -struct pci_controller hose; - -int board_early_init_f (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; - return 0; -} - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/tqc/tqm8272/tqm8272.h b/board/tqc/tqm8272/tqm8272.h deleted file mode 100644 index 1eeaf0e..0000000 --- a/board/tqc/tqm8272/tqm8272.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TQM8272_HEADER_H -#define _TQM8272_HEADER_H - -#define _NOT_USED_ 0xFFFFFFFF - -typedef struct{ - int Bus; - int flash; - int flash_nr; - int ram; - int ram_cs; - int nand; - int nand_cs; - int eeprom; - int can; - unsigned long cpunr; - unsigned long option; - int SecEng; - int cpucl; - int cpmcl; - int buscl; - int busclk_real_ok; - int busclk_real; - unsigned char OK; - unsigned char ethaddr[20]; -} HWIB_INFO; - -static HWIB_INFO hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0, - 0, 0, 0, 0, 0, 0}; -#endif /* __CONFIG_H */ diff --git a/configs/TQM8272_defconfig b/configs/TQM8272_defconfig deleted file mode 100644 index 0070baf..0000000 --- a/configs/TQM8272_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8272=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 566162e..775c3a7 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +TQM8272 powerpc mpc8260 - - - TQM8260 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de> IDS8247 powerpc mpc8260 - - Heiko Schocher <hs@denx.de> HWW1U1A powerpc mpc85xx - - Kyle Moffett <Kyle.D.Moffett@boeing.com> diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h deleted file mode 100644 index 9c7e163..0000000 --- a/include/configs/TQM8272.h +++ /dev/null @@ -1,735 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8272_FAMILY 1 -#define CONFIG_TQM8272 1 - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */ -#define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */ - -#define STK82xx_150 1 /* on a STK82xx.150 */ - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_EARLY_INIT_R 1 - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 115200 -#endif - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consdev=ttyCPM0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "hostname=tqm8272\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=$(consdev),$(baudrate)\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 300000 ${bootfile};" \ - "run nfsargs addip addcons;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/tqm8272/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40100000\0" \ - "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \ - "update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \ - "cp.b 300000 40000000 40000;" \ - "setenv filesize;saveenv\0" \ - "cphwib=cp.b 4003fc00 33fc00 400\0" \ - "upd=run load cphwib update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_I2C 1 - -#if CONFIG_I2C -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_I2C_X - -/* EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ - -/* I2C RTC */ -#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - -#else -#undef CONFIG_SYS_I2C -#undef CONFIG_HARD_I2C -#undef CONFIG_SYS_I2C_SOFT -#endif - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#ifdef CONFIG_82xx_CONS_SMC1 -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#endif -#ifdef CONFIG_82xx_CONS_SMC2 -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ -#endif - -#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - * - * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the - * X.29 connector, and FCC2 is hardwired to the X.1 connector) - */ -#define CONFIG_SYS_FCC_ETHERNET - -#if defined(CONFIG_SYS_FCC_ETHERNET) -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ -#else -#define CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#endif - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#if STK82xx_150 -#define CONFIG_SYS_MDIO_PIN 0x00008000 /* PC16 */ -#define CONFIG_SYS_MDC_PIN 0x00004000 /* PC17 */ -#endif - -#if STK82xx_100 -#define CONFIG_SYS_MDIO_PIN 0x00000002 /* PC30 */ -#define CONFIG_SYS_MDC_PIN 0x00000001 /* PC31 */ -#endif - -#if 1 -#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) -#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) -#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ - else iop->pdat &= ~CONFIG_SYS_MDIO_PIN - -#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ - else iop->pdat &= ~CONFIG_SYS_MDC_PIN -#else -#define MDIO_ACTIVE ({unsigned long tmp; tmp = iop->pdir; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;}) -#define MDIO_TRISTATE ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;}) -#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) - -#define MDIO(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\ - else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;} - -#define MDC(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\ - else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;} -#endif - -#define MIIDELAY udelay(1) - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP - -#if CONFIG_I2C - #define CONFIG_CMD_I2C - #define CONFIG_CMD_DATE - #define CONFIG_CMD_DTT - #define CONFIG_CMD_EEPROM -#endif - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#if 0 -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */ - -#define CONFIG_SYS_RESET_ADDRESS 0x40000104 /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * CAN stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_CAN_BASE 0x51000000 -#define CONFIG_SYS_CAN_SIZE 1 -#define CONFIG_SYS_CAN_BR ((CONFIG_SYS_CAN_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMC |\ - BRx_V) - -#define CONFIG_SYS_CAN_OR (MEG_TO_AM(CONFIG_SYS_CAN_SIZE) |\ - ORxU_BI) - - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8272/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH0_SIZE 32 /* 32 MB */ - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_SYS_UPDATE_FLASH_SIZE - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND 0x20000 - -/* Where is the Hardwareinformation Block (from Monitor Sources) */ -#define MON_RES_LENGTH (0x0003FC00) -#define HWIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH) -#define HWIB_INFO_LEN 512 -#define CIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN) -#define CIB_INFO_LEN 512 - -#define CONFIG_SYS_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000060 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_CMD_NAND) - -#define CONFIG_SYS_NAND_CS_DIST 0x80 -#define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS 0x20 -#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS 0x40 - -#define CONFIG_SYS_NAND_BR ((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMB |\ - BRx_V) - -#define CONFIG_SYS_NAND_OR (MEG_TO_AM(CONFIG_SYS_NAND_SIZE) |\ - ORxU_BI |\ - ORxU_EHTR_8IDLE) - -#define CONFIG_SYS_NAND_SIZE 1 -#define CONFIG_SYS_NAND0_BASE 0x50000000 -#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST) -#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST) -#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST) - -#define CONFIG_SYS_MAX_NAND_DEVICE 4 /* Max number of NAND devices */ - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \ - CONFIG_SYS_NAND1_BASE, \ - CONFIG_SYS_NAND2_BASE, \ - CONFIG_SYS_NAND3_BASE, \ - } - -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr))) -#define WRITE_NAND_UPM(d, adr, off) do \ -{ \ - volatile unsigned char *addr = (unsigned char *) (adr + off); \ - WRITE_NAND(d, addr); \ -} while(0) - -#endif /* CONFIG_CMD_NAND */ - -#define CONFIG_PCI -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_PCI_PNP -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_PCI_SCAN_SHOW -#endif - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#if 0 -#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) - -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) -#else -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111) -#endif - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */ -#define BCR_APD01 0x10000000 -#define CONFIG_SYS_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -#define CONFIG_SYS_SIUMCR_LOW (SIUMCR_DPPC00) -#define CONFIG_SYS_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE) -#else -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00) -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR SCCR_DFBRG01 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * 2 60x UPMB 8 bit NAND - * 3 60x UPMC 8 bit CAN - * - */ - -/* Initialize SDRAM - */ -#undef CONFIG_SYS_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */ - -#define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ - -#define CONFIG_SYS_MPTPR 0x4000 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - * In fact, the address is rather configuration data presented to the SDRAM on - * its address lines. Because the address lines may be mux'ed externally either - * for 8 column or 9 column devices, some bits appear twice in the 8260's - * address: - * - * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | - * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | - * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | - * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | - * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 - -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV4 |\ - ORxG_SCY_8_CLK |\ - ORxG_TRLX) - -/* SDRAM on TQM8272 can have either 8 or 9 columns. - * The number affects configuration values. - */ - -/* Bank 1 - 60x bus SDRAM - */ -#define CONFIG_SYS_PSRT 0x20 /* Low Value */ -/* #define CONFIG_SYS_PSRT 0x10 Fast Value */ -#define CONFIG_SYS_LSRT 0x20 /* Local Bus */ -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL - -/* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD |\ - PSDMR_CL_2) - - -/* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A5 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD |\ - PSDMR_CL_2) - -#define CONFIG_SYS_OR1_10COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A4 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_10COL (PSDMR_PBI |\ - PSDMR_SDAM_A17_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A4 |\ - PSDMR_RFRC_6_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD |\ - PSDMR_CL_2) - -#define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */ -#define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */ -#define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */ -#define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */ -#define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */ -#define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */ - -#define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */ -#define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */ -#define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */ -#define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */ -#define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */ -#define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */ - -#define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */ -#define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */ -#define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */ -#define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */ -#define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */ -#define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */ - -#define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */ -#define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */ -#define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */ -#define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */ -#define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */ -#define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */ - -#endif /* CONFIG_SYS_RAMBOOT */ - -#endif /* __CONFIG_H */ |