diff options
| -rw-r--r-- | arch/powerpc/cpu/mpc8260/Kconfig | 4 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc8260/pci.c | 57 | ||||
| -rw-r--r-- | board/freescale/mpc8266ads/Kconfig | 12 | ||||
| -rw-r--r-- | board/freescale/mpc8266ads/MAINTAINERS | 6 | ||||
| -rw-r--r-- | board/freescale/mpc8266ads/Makefile | 8 | ||||
| -rw-r--r-- | board/freescale/mpc8266ads/flash.c | 493 | ||||
| -rw-r--r-- | board/freescale/mpc8266ads/mpc8266ads.c | 582 | ||||
| -rw-r--r-- | configs/MPC8266ADS_defconfig | 3 | ||||
| -rw-r--r-- | doc/README.scrapyard | 1 | ||||
| -rw-r--r-- | include/configs/MPC8266ADS.h | 563 |
10 files changed, 3 insertions, 1726 deletions
diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig index 15742d9..d9dba83 100644 --- a/arch/powerpc/cpu/mpc8260/Kconfig +++ b/arch/powerpc/cpu/mpc8260/Kconfig @@ -34,9 +34,6 @@ config TARGET_PM826 config TARGET_PM828 bool "Support PM828" -config TARGET_MPC8266ADS - bool "Support MPC8266ADS" - config TARGET_KM82XX bool "Support km82xx" @@ -46,7 +43,6 @@ source "board/atc/Kconfig" source "board/cpu86/Kconfig" source "board/cpu87/Kconfig" source "board/ep82xxm/Kconfig" -source "board/freescale/mpc8266ads/Kconfig" source "board/gw8260/Kconfig" source "board/iphase4539/Kconfig" source "board/keymile/km82xx/Kconfig" diff --git a/arch/powerpc/cpu/mpc8260/pci.c b/arch/powerpc/cpu/mpc8260/pci.c index f7bb05d..079b6e6 100644 --- a/arch/powerpc/cpu/mpc8260/pci.c +++ b/arch/powerpc/cpu/mpc8260/pci.c @@ -22,7 +22,7 @@ #include <fdt_support.h> #endif -#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826 +#if defined CONFIG_PM826 DECLARE_GLOBAL_DATA_PTR; #endif @@ -236,34 +236,6 @@ void pci_mpc8250_init (struct pci_controller *hose) CONFIG_SYS_IMMR + PCI_CFG_DATA_REG); /* - * Setting required to enable local bus for PCI (SIUMCR [LBPC]). - */ -#ifdef CONFIG_MPC8266ADS - immap->im_siu_conf.sc_siumcr = - (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) - | SIUMCR_LBPC01; -#elif defined CONFIG_MPC8272 - immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & - ~SIUMCR_BBD & - ~SIUMCR_ESE & - ~SIUMCR_PBSE & - ~SIUMCR_CDIS & - ~SIUMCR_DPPC11 & - ~SIUMCR_L2CPC11 & - ~SIUMCR_LBPC11 & - ~SIUMCR_APPC11 & - ~SIUMCR_CS10PC11 & - ~SIUMCR_BCTLC11 & - ~SIUMCR_MMR11) - | SIUMCR_DPPC11 - | SIUMCR_L2CPC01 - | SIUMCR_LBPC00 - | SIUMCR_APPC10 - | SIUMCR_CS10PC00 - | SIUMCR_BCTLC00 - | SIUMCR_MMR11; -#else - /* * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), * and local bus for PCI (SIUMCR [LBPC]). */ @@ -274,7 +246,6 @@ void pci_mpc8250_init (struct pci_controller *hose) SIUMCR_LBPC01 | SIUMCR_CS10PC01 | SIUMCR_APPC10; -#endif /* Make PCI lowest priority */ /* Each 4 bits is a device bus request and the MS 4bits @@ -304,24 +275,11 @@ void pci_mpc8250_init (struct pci_controller *hose) immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK; immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE; -#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 - immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK; - immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE; -#endif - /* Release PCI RST (by default the PCI RST signal is held low) */ immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN); /* give it some time */ { -#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 - /* Give the PCI cards more time to initialize before query - This might be good for other boards also - */ - int i; - - for (i = 0; i < 1000; ++i) -#endif udelay (1000); } @@ -358,11 +316,7 @@ void pci_mpc8250_init (struct pci_controller *hose) immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */ /* See above for description - puts PCI request as highest priority */ -#ifdef CONFIG_MPC8272 - immap->im_siu_conf.sc_ppc_alrh = 0x01236745; -#else immap->im_siu_conf.sc_ppc_alrh = 0x03124567; -#endif /* Park the bus on the PCI */ immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI; @@ -388,7 +342,7 @@ void pci_mpc8250_init (struct pci_controller *hose) hose->last_busno = 0xff; /* System memory space */ -#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826 +#if defined CONFIG_PM826 pci_set_region (hose->regions + 0, PCI_SLV_MEM_BUS, PCI_SLV_MEM_LOCAL, @@ -401,17 +355,10 @@ void pci_mpc8250_init (struct pci_controller *hose) #endif /* PCI memory space */ -#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 - pci_set_region (hose->regions + 1, - PCI_MSTR_MEMIO_BUS, - PCI_MSTR_MEMIO_LOCAL, - PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM); -#else pci_set_region (hose->regions + 1, PCI_MSTR_MEM_BUS, PCI_MSTR_MEM_LOCAL, PCI_MSTR_MEM_SIZE, PCI_REGION_MEM); -#endif /* PCI I/O space */ pci_set_region (hose->regions + 2, diff --git a/board/freescale/mpc8266ads/Kconfig b/board/freescale/mpc8266ads/Kconfig deleted file mode 100644 index 78963b9..0000000 --- a/board/freescale/mpc8266ads/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8266ADS - -config SYS_BOARD - default "mpc8266ads" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8266ADS" - -endif diff --git a/board/freescale/mpc8266ads/MAINTAINERS b/board/freescale/mpc8266ads/MAINTAINERS deleted file mode 100644 index bdea02d..0000000 --- a/board/freescale/mpc8266ads/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MPC8266ADS BOARD -M: Rune Torgersen <runet@innovsys.com> -S: Maintained -F: board/freescale/mpc8266ads/ -F: include/configs/MPC8266ADS.h -F: configs/MPC8266ADS_defconfig diff --git a/board/freescale/mpc8266ads/Makefile b/board/freescale/mpc8266ads/Makefile deleted file mode 100644 index ee63dc0..0000000 --- a/board/freescale/mpc8266ads/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mpc8266ads.o flash.o diff --git a/board/freescale/mpc8266ads/flash.c b/board/freescale/mpc8266ads/flash.c deleted file mode 100644 index ef28194..0000000 --- a/board/freescale/mpc8266ads/flash.c +++ /dev/null @@ -1,493 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Add support the Sharp chips on the mpc8260ads. - * I started with board/ip860/flash.c and made changes I found in - * the MTD project by David Schleef. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static int clear_block_lock_bit(vu_long * addr); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ -#ifndef CONFIG_MPC8266ADS - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; -#endif - unsigned long size; - int i; - - /* Init: enable write, - * or we cannot even write flash commands - */ -#ifndef CONFIG_MPC8266ADS - bcsr->bd_ctrl |= BD_CTRL_FLWE; -#endif - - - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* set the default sector offset */ - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size, size<<20); - } - -#ifndef CONFIG_MPC8266ADS - /* Remap FLASH according to real size */ - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br1 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | - (memctl->memc_br1 & ~(BR_BA_MSK)); -#endif - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_SHARP: printf ("Sharp "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); - break; - case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); - break; - case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); - break; - case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - ulong sector_offset; - - /* Write "Intelligent Identifier" command: read Manufacturer ID */ - *addr = 0x90909090; - - value = addr[0] & 0x00FF00FF; - switch (value) { - case MT_MANUFACT: /* SHARP, MT or => Intel */ - case INTEL_ALT_MANU: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - printf("unknown manufacturer: %x\n", (unsigned int)value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case (INTEL_ID_28F016S): - info->flash_id += FLASH_28F016SV; - info->sector_count = 32; - info->size = 0x00400000; - sector_offset = 0x20000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F160S3): - info->flash_id += FLASH_28F160S3; - info->sector_count = 32; - info->size = 0x00400000; - sector_offset = 0x20000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F320S3): - info->flash_id += FLASH_28F320S3; - info->sector_count = 64; - info->size = 0x00800000; - sector_offset = 0x20000; - break; /* => 2x4 MB */ - - case SHARP_ID_28F016SCL: - case SHARP_ID_28F016SCZ: - info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; - info->sector_count = 32; - info->size = 0x00800000; - sector_offset = 0x40000; - break; /* => 4x2 MB */ - - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += sector_offset; - /* don't know how to check sector protection */ - info->protect[i] = 0; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - - *addr = 0xFFFFFF; /* reset bank to read array mode */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Make Sure Block Lock Bit is not set. */ - if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ - return 1; - } - - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - - last = start = get_timer (0); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Reset Array */ - *addr = 0xffffffff; - /* Clear Status Register */ - *addr = 0x50505050; - /* Single Block Erase Command */ - *addr = 0x20202020; - /* Confirm */ - *addr = 0xD0D0D0D0; - - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { - /* Resume Command, as per errata update */ - *addr = 0xD0D0D0D0; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - while ((*addr & 0x80808080) != 0x80808080) { - if(*addr & 0x20202020){ - printf("Error in Block Erase - Lock Bit may be set!\n"); - printf("Status Register = 0x%X\n", (uint)*addr); - *addr = 0xFFFFFFFF; /* reset bank */ - return 1; - } - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - /* reset to read mode */ - *addr = 0xFFFFFFFF; - } - } - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - ulong start, csr; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Write Command */ - *addr = 0x10101010; - - /* Write Data */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - while (((csr = *addr) & 0x80808080) != 0x80808080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x40404040) { - printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); - flag = 1; - } - - /* Clear Status Registers Command */ - *addr = 0x50505050; - /* Reset to read array mode */ - *addr = 0xFFFFFFFF; - - return (flag); -} - -/*----------------------------------------------------------------------- - * Clear Block Lock Bit, returns: - * 0 - OK - * 1 - Timeout - */ - -static int clear_block_lock_bit(vu_long * addr) -{ - ulong start, now; - - /* Reset Array */ - *addr = 0xffffffff; - /* Clear Status Register */ - *addr = 0x50505050; - - *addr = 0x60606060; - *addr = 0xd0d0d0d0; - - start = get_timer (0); - while(*addr != 0x80808080){ - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout on clearing Block Lock Bit\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - return 1; - } - } - return 0; -} diff --git a/board/freescale/mpc8266ads/mpc8266ads.c b/board/freescale/mpc8266ads/mpc8266ads.c deleted file mode 100644 index 1eeec3f..0000000 --- a/board/freescale/mpc8266ads/mpc8266ads.c +++ /dev/null @@ -1,582 +0,0 @@ -/* - * (C) Copyright 2001-2011 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified during 2001 by - * Advanced Communications Technologies (Australia) Pty. Ltd. - * Howard Walker, Tuong Vu-Dinh - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Added support for the 16M dram simm on the 8260ads boards - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <i2c.h> -#include <mpc8260.h> -#include <pci.h> - -/* - * PBI Page Based Interleaving - * PSDMR_PBI page based interleaving - * 0 bank based interleaving - * External Address Multiplexing (EAMUX) adds a clock to address cycles - * (this can help with marginal board layouts) - * PSDMR_EAMUX adds a clock - * 0 no extra clock - * Buffer Command (BUFCMD) adds a clock to command cycles. - * PSDMR_BUFCMD adds a clock - * 0 no extra clock - */ -#define CONFIG_PBI 0 -#define PESSIMISTIC_SDRAM 0 -#define EAMUX 0 /* EST requires EAMUX */ -#define BUFCMD 0 - - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -typedef struct bscr_ { - unsigned long bcsr0; - unsigned long bcsr1; - unsigned long bcsr2; - unsigned long bcsr3; - unsigned long bcsr4; - unsigned long bcsr5; - unsigned long bcsr6; - unsigned long bcsr7; -} bcsr_t; - -typedef struct pci_ic_s { - unsigned long pci_int_stat; - unsigned long pci_int_mask; -} pci_ic_t; - -void reset_phy(void) -{ - volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR; - - /* reset the FEC port */ - bcsr->bcsr1 &= ~FETH_RST; - bcsr->bcsr1 |= FETH_RST; -} - - -int board_early_init_f(void) -{ - volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR; - volatile pci_ic_t *pci_ic = (pci_ic_t *)CONFIG_SYS_PCI_INT; - - bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2; - - /* mask all PCI interrupts */ - pci_ic->pci_int_mask |= 0xfff00000; - - return 0; -} - -int checkboard(void) -{ - puts("Board: Motorola MPC8266ADS\n"); - return 0; -} - -phys_size_t initdram(int board_type) -{ - /* Autoinit part stolen from board/sacsng/sacsng.c */ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0xff; - volatile uchar *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8); - uint psdmr = CONFIG_SYS_PSDMR; - int i; - - uint psrt = 0x21; /* for no SPD */ - uint chipselects = 1; /* for no SPD */ - uint sdram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; /* for no SPD */ - uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */ - uint data_width; - uint rows; - uint banks; - uint cols; - uint caslatency; - uint width; - uint rowst; - uint sdam; - uint bsma; - uint sda10; - u_char data; - u_char cksum; - int j; - - /* - * Keep the compiler from complaining about - * potentially uninitialized vars - */ - data_width = rows = banks = cols = caslatency = 0; - - /* - * Read the SDRAM SPD EEPROM via I2C. - */ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); - cksum = data; - for (j = 1; j < 64; j++) { /* read only the checksummed bytes */ - /* note: the I2C address autoincrements when alen == 0 */ - i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1); - /*printf("addr %d = 0x%02x\n", j, data); */ - if (j == 5) - chipselects = data & 0x0F; - else if (j == 6) - data_width = data; - else if (j == 7) - data_width |= data << 8; - else if (j == 3) - rows = data & 0x0F; - else if (j == 4) - cols = data & 0x0F; - else if (j == 12) { - /* - * Refresh rate: this assumes the prescaler is set to - * approximately 0.39uSec per tick and the target - * refresh period is about 85% of maximum. - */ - switch (data & 0x7F) { - default: - case 0: - psrt = 0x21; /* 15.625uS */ - break; - case 1: - psrt = 0x07; /* 3.9uS */ - break; - case 2: - psrt = 0x0F; /* 7.8uS */ - break; - case 3: - psrt = 0x43; /* 31.3uS */ - break; - case 4: - psrt = 0x87; /* 62.5uS */ - break; - case 5: - psrt = 0xFF; /* 125uS */ - break; - } - } else if (j == 17) - banks = data; - else if (j == 18) { - caslatency = 3; /* default CL */ -#if (PESSIMISTIC_SDRAM) - if ((data & 0x04) != 0) - caslatency = 3; - else if ((data & 0x02) != 0) - caslatency = 2; - else if ((data & 0x01) != 0) - caslatency = 1; -#else - if ((data & 0x01) != 0) - caslatency = 1; - else if ((data & 0x02) != 0) - caslatency = 2; - else if ((data & 0x04) != 0) - caslatency = 3; -#endif - else { - printf("WARNING: Unknown CAS latency 0x%02X, using 3\n", - data); - } - } else if (j == 63) { - if (data != cksum) { - printf("WARNING: Configuration data checksum failure:" - " is 0x%02x, calculated 0x%02x\n", - data, cksum); - } - } - cksum += data; - } - - /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ - if (caslatency < 2) { - printf("CL was %d, forcing to 2\n", caslatency); - caslatency = 2; - } - if (rows > 14) { - printf("This doesn't look good, rows = %d, should be <= 14\n", - rows); - rows = 14; - } - if (cols > 11) { - printf("This doesn't look good, columns = %d, should be <= 11\n", - cols); - cols = 11; - } - - if ((data_width != 64) && (data_width != 72)) { - printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n", - data_width); - } - width = 3; /* 2^3 = 8 bytes = 64 bits wide */ - /* - * Convert banks into log2(banks) - */ - if (banks == 2) - banks = 1; - else if (banks == 4) - banks = 2; - else if (banks == 8) - banks = 3; - - - sdram_size = 1 << (rows + cols + banks + width); - /* hack for high density memory (512MB per CS) */ - /* !!!!! Will ONLY work with Page Based Interleave !!!!! - ( PSDMR[PBI] = 1 ) - */ - /* - * memory actually has 11 column addresses, but the memory - * controller doesn't really care. - * - * the calculations that follow will however move the rows so - * that they are muxed one bit off if you use 11 bit columns. - * - * The solution is to tell the memory controller the correct - * size of the memory but change the number of columns to 10 - * afterwards. - * - * The 11th column addre will still be mucxed correctly onto - * the bus. - * - * Also be aware that the MPC8266ADS board Rev B has not - * connected Row address 13 to anything. - * - * The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126) - */ - if (cols > 10) - cols = 10; - -#if (CONFIG_PBI == 0) /* bank-based interleaving */ - rowst = ((32 - 6) - (rows + cols + width)) * 2; -#else - rowst = 32 - (rows + banks + cols + width); -#endif - - or = ~(sdram_size - 1) | /* SDAM address mask */ - ((banks - 1) << 13) | /* banks per device */ - (rowst << 9) | /* rowst */ - ((rows - 9) << 6); /* numr */ - - - /*printf("memctl->memc_or2 = 0x%08x\n", or); */ - - /* - * SDAM specifies the number of columns that are multiplexed - * (reference AN2165/D), defined to be (columns - 6) for page - * interleave, (columns - 8) for bank interleave. - * - * BSMA is 14 - max(rows, cols). The bank select lines come - * into play above the highest "address" line going into the - * the SDRAM. - */ -#if (CONFIG_PBI == 0) /* bank-based interleaving */ - sdam = cols - 8; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam + 2; -#else - sdam = cols + banks - 8; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam; -#endif -#if (PESSIMISTIC_SDRAM) - psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_16_CLK | - PSDMR_PRETOACT_8W | PSDMR_ACTTORW_8W | PSDMR_WRC_4C | - PSDMR_EAMUX | PSDMR_BUFCMD) | caslatency | - ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ - (sdam << 24) | (bsma << 21) | (sda10 << 18); -#else - psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_7_CLK | - PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ - PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ - PSDMR_WRC_1C | /* 1 clock + 7nSec */ - EAMUX | BUFCMD) | caslatency | - ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ - (sdam << 24) | (bsma << 21) | (sda10 << 18); -#endif - /*printf("psdmr = 0x%08x\n", psdmr); */ - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * Quote from Micron MT48LC8M16A2 data sheet: - * - * "...the SDRAM requires a 100uS delay prior to issuing any - * command other than a COMMAND INHIBIT or NOP. Starting at some - * point during this 100uS period and continuing at least through - * the end of this period, COMMAND INHIBIT or NOP commands should - * be applied." - * - * "Once the 100uS delay has been satisfied with at least one COMMAND - * INHIBIT or NOP command having been applied, a /PRECHARGE command/ - * should be applied. All banks must then be precharged, thereby - * placing the device in the all banks idle state." - * - * "Once in the idle state, /two/ AUTO REFRESH cycles must be - * performed. After the AUTO REFRESH cycles are complete, the - * SDRAM is ready for mode register programming." - * - * (/emphasis/ mine, gvb) - * - * The way I interpret this, Micron start up sequence is: - * 1. Issue a PRECHARGE-BANK command (initial precharge) - * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged") - * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands - * 4. Issue a MODE-SET command to initialize the mode register - * - * -------- - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set - * when we get here. The SDRAM can be accessed at the address - * CONFIG_SYS_SDRAM_BASE. - */ - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - memctl->memc_psrt = psrt; - - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - memctl->memc_or2 = or; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - /* - * Do it a second time for the second set of chips if the DIMM has - * two chip selects (double sided). - */ - if (chipselects > 1) { - ramaddr += sdram_size; - - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size; - memctl->memc_or3 = or; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - } - - /* print info */ - printf("SDRAM configuration read from SPD\n"); - printf("\tSize per side = %dMB\n", sdram_size >> 20); - printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", - chipselects, 1 << (banks), cols, rows, data_width); - printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency); -#if (CONFIG_PBI == 0) /* bank-based interleaving */ - printf(", Using Bank Based Interleave\n"); -#else - printf(", Using Page Based Interleave\n"); -#endif - printf("\tTotal size: "); - - /* this delay only needed for original 16MB DIMM... - * Not needed for any other memory configuration */ - if ((sdram_size * chipselects) == (16 * 1024 * 1024)) - udelay(250000); - - return sdram_size * chipselects; -} - -#ifdef CONFIG_PCI -struct pci_controller hose; - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif diff --git a/configs/MPC8266ADS_defconfig b/configs/MPC8266ADS_defconfig deleted file mode 100644 index 485c842..0000000 --- a/configs/MPC8266ADS_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_MPC8266ADS=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 7e4eaef..d358d62 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +MPC8266ADS powerpc mpc8260 - - Rune Torgersen <runet@innovsys.com> VoVPN-GW powerpc mpc8260 - - ep8260 powerpc mpc8260 - - Frank Panno <fpanno@delphintech.com> ppmc8260 powerpc mpc8260 - - Brad Kemp <Brad.Kemp@seranoa.com> diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h deleted file mode 100644 index 8d9c8fb..0000000 --- a/include/configs/MPC8266ADS.h +++ /dev/null @@ -1,563 +0,0 @@ -/* - * (C) Copyright 2001 - * Stuart Hughes <stuarth@lineo.com> - * This file is based on similar values for other boards found in other - * U-Boot config files, and some that I found in the mpc8260ads manual. - * - * Note: my board is a PILOT rev. - * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Config header file for a MPC8266ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm - */ - -/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! - !! !! - !! This configuration requires JP3 to be in position 1-2 to work !! - !! To make it work for the default, the CONFIG_SYS_TEXT_BASE define in !! - !! board/mpc8266ads/config.mk must be changed from 0xfe000000 to !! - !! 0xfff00000 !! - !! The CONFIG_SYS_HRCW_MASTER define below must also be changed to match !! - !! !! - !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8266ADS 1 /* ...on motorola ADS board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_SYS_TEXT_BASE 0xfe000000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -/* allow serial and ethaddr to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * Port pins used for bit-banged MII communictions (if applicable). - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) - -#if (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Half duplex - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_INDEX */ - -/* other options */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* PCI */ -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_PNP -#define CONFIG_PCI_BOOTDELAY 0 -#undef CONFIG_PCI_SCAN_SHOW - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x50 - -#define CONFIG_8260_CLKIN 66000000 /* in Hz */ -#define CONFIG_BAUDRATE 115200 - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -/* Commands we want, that are not part of default set */ -#define CONFIG_CMD_ASKENV /* ask for env variable */ -#define CONFIG_CMD_CACHE /* icache, dcache */ -#define CONFIG_CMD_DHCP /* DHCP Support */ -#define CONFIG_CMD_DIAG /* Diagnostics */ -#define CONFIG_CMD_IMMAP /* IMMR dump support */ -#define CONFIG_CMD_IRQ /* irqinfo */ -#define CONFIG_CMD_MII /* MII support */ -#define CONFIG_CMD_PCI /* pciinfo */ -#define CONFIG_CMD_PING /* ping support */ -#define CONFIG_CMD_PORTIO /* Port I/O */ -#define CONFIG_CMD_REGINFO /* Register dump */ -#define CONFIG_CMD_SAVES /* save S record dump */ -#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */ - -/* Commands from default set we don't need */ -#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ -#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ - -/* Define a command string that is automatically executed when no character - * is read on the console interface withing "Boot Delay" after reset. - */ -#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ -#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ - -#ifdef CONFIG_BOOT_ROOT_INITRD -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/ram0 rw " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_INITRD */ - -#ifdef CONFIG_BOOT_ROOT_NFS -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_NFS */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#if defined(CONFIG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#endif - -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ - /* for versions < 2.4.5-pre5 */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define FLASH_BASE 0xFE000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_SIZE 8 -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */ - -#undef CONFIG_SYS_FLASH_CHECKSUM - -/* this is stuff came out of the Motorola docs */ -/* Only change this if you also change the Hardware configuration Word */ -#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000 - -/* Set IMMR to 0xF0000000 or above to boot Linux */ -#define CONFIG_SYS_IMMR 0xF0000000 -#define CONFIG_SYS_BCSR 0xF8000000 -#define CONFIG_SYS_PCI_INT 0xF8200000 /* PCI interrupt controller */ - -/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes - */ -/*#define CONFIG_VERY_BIG_RAM 1*/ - -/* What should be the base address of SDRAM DIMM and how big is - * it (in Mbytes)? This will normally auto-configure via the SPD. -*/ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 - -#define SDRAM_SPD_ADDR 0x50 - -/*----------------------------------------------------------------------- - * BR2,BR3 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR2,OR3 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* Bank 2,3 - SDRAM DIMM - */ - -/* The BR2 is configured as follows: - * - * - Base address of 0x00000000 - * - 64 bit port size (60x bus only) - * - Data errors checking is disabled - * - Read and write access - * - SDRAM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -/* With a 64 MB DIMM, the OR2 is configured as follows: - * - * - 64 MB - * - 4 internal banks per device - * - Row start address bit is A8 with PSDMR[PBI] = 0 - * - 12 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ -#if (CONFIG_SYS_SDRAM_SIZE == 64) -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A8 |\ - ORxS_NUMR_12) -#elif (CONFIG_SYS_SDRAM_SIZE == 16) -#define CONFIG_SYS_OR2_PRELIM (0xFF000C80) -#else -#error "INVALID SDRAM CONFIGURATION" -#endif - -/*----------------------------------------------------------------------- - * PSDMR - 60x Bus SDRAM Mode Register - * Ref: Section 10.3.3 on page 10-21 - *----------------------------------------------------------------------- - */ - -#if (CONFIG_SYS_SDRAM_SIZE == 64) -/* With a 64 MB DIMM, the PSDMR is configured as follows: - * - * - Bank Based Interleaving, - * - Refresh Enable, - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A14-A16 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - CAS Latency is 2. - */ -#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) -#elif (CONFIG_SYS_SDRAM_SIZE == 16) -/* With a 16 MB DIMM, the PSDMR is configured as follows: - * - * configuration parameters found in Motorola documentation - */ -#define CONFIG_SYS_PSDMR (0x016EB452) -#else -#error "INVALID SDRAM CONFIGURATION" -#endif - -#define RS232EN_1 0x02000002 -#define RS232EN_2 0x01000001 -#define FETHIEN 0x08000008 -#define FETH_RST 0x04000004 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */ -/* 0x0EB2B645 */ -#define CONFIG_SYS_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\ - ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 ) |\ - ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\ - ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \ - ) - -/* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3) */ -/* #define CONFIG_SYS_HRCW_MASTER 0x0cb23645 */ - -/* This value should actually be situated in the first 256 bytes of the FLASH - which on the standard MPC8266ADS board is at address 0xFF800000 - The linker script places it at 0xFFF00000 instead. - - It still works, however, as long as the ADS board jumper JP3 is set to - position 2-3 so the board is using the BCSR as Hardware Configuration Word - - If you want to use the one defined here instead, ust copy the first 256 bytes from - 0xfff00000 to 0xff800000 (for 8MB flash) - - - Rune - -*/ - -/* no slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#ifndef CONFIG_SYS_RAMBOOT -# define CONFIG_ENV_IS_IN_FLASH 1 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -# define CONFIG_ENV_SECT_SIZE 0x40000 -#else -# define CONFIG_ENV_IS_IN_NVRAM 1 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -# define CONFIG_ENV_SIZE 0x200 -#endif /* CONFIG_SYS_RAMBOOT */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -/*#define CONFIG_SYS_HID0_INIT 0 */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE |\ - HID0_DCE |\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) - -#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) - -#define CONFIG_SYS_HID2 0 - -#define CONFIG_SYS_SYPCR 0xFFFFFFC3 -#define CONFIG_SYS_BCR 0x004C0000 -#define CONFIG_SYS_SIUMCR 0x4E64C000 -#define CONFIG_SYS_SCCR 0x00000000 - -/* local bus memory map - * - * 0x00000000-0x03FFFFFF 64MB SDRAM - * 0x80000000-0x9FFFFFFF 512MB outbound prefetchable PCI memory window - * 0xA0000000-0xBFFFFFFF 512MB outbound non-prefetchable PCI memory window - * 0xF0000000-0xF001FFFF 128KB MPC8266 internal memory - * 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window - * 0xF8000000-0xF8007FFF 32KB BCSR - * 0xF8100000-0xF8107FFF 32KB ATM UNI - * 0xF8200000-0xF8207FFF 32KB PCI interrupt controller - * 0xF8300000-0xF8307FFF 32KB EEPROM - * 0xFE000000-0xFFFFFFFF 32MB flash - */ -#define CONFIG_SYS_BR0_PRELIM 0xFE001801 /* flash */ -#define CONFIG_SYS_OR0_PRELIM 0xFE000836 -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x1801) /* BCSR */ -#define CONFIG_SYS_OR1_PRELIM 0xFFFF8010 -#define CONFIG_SYS_BR4_PRELIM 0xF8300801 /* EEPROM */ -#define CONFIG_SYS_OR4_PRELIM 0xFFFF8846 -#define CONFIG_SYS_BR5_PRELIM 0xF8100801 /* PM5350 ATM UNI */ -#define CONFIG_SYS_OR5_PRELIM 0xFFFF8E36 -#define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */ -#define CONFIG_SYS_OR8_PRELIM 0xFFFF8010 - -#define CONFIG_SYS_RMR 0x0001 -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) -#define CONFIG_SYS_RCCR 0 -#define CONFIG_SYS_MPTPR 0x00001900 -#define CONFIG_SYS_PSRT 0x00000021 - -/* This address must not exist */ -#define CONFIG_SYS_RESET_ADDRESS 0xFCFFFF00 - -/* PCI Memory map (if different from default map */ -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */ -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ -#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ - PICMR_PREFETCH_EN) - -/* - * These are the windows that allow the CPU to access PCI address space. - * All three PCI master windows, which allow the CPU to access PCI - * prefetch, non prefetch, and IO space (see below), must all fit within - * these windows. - */ - -/* PCIBR0 */ -#define CONFIG_SYS_PCI_MSTR0_LOCAL 0x80000000 /* Local base */ -#define CONFIG_SYS_PCIMSK0_MASK PCIMSK_1GB /* Size of window */ -/* PCIBR1 */ -#define CONFIG_SYS_PCI_MSTR1_LOCAL 0xF4000000 /* Local base */ -#define CONFIG_SYS_PCIMSK1_MASK PCIMSK_64MB /* Size of window */ - -/* - * Master window that allows the CPU to access PCI Memory (prefetch). - * This window will be setup with the first set of Outbound ATU registers - * in the bridge. - */ - -#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ -#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ -#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL -#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ -#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) - -/* - * Master window that allows the CPU to access PCI Memory (non-prefetch). - * This window will be setup with the second set of Outbound ATU registers - * in the bridge. - */ - -#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ -#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ -#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL -#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ -#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) - -/* - * Master window that allows the CPU to access PCI IO space. - * This window will be setup with the third set of Outbound ATU registers - * in the bridge. - */ - -#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */ -#define CONFIG_SYS_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */ -#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL -#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */ -#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO) - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ |