diff options
233 files changed, 27175 insertions, 6108 deletions
@@ -2,17 +2,255 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Add support for WTK FO300 board (TQM5200 based). + +* Fix TQM834x hang. + +* Update for SC520 board. + Patch by David Updegraff, 02 Dec 2005 + +* Fixed common.h spelling error. + Patch by Cory Tusar, 30 Nov 2005 + +* Fix typo. + Patch by Andreas Engel, 28 Nov 2005 + +* Fix fatload command on FAT32 formatted partitions. + Patch by Joachim Jaeger, 18 Nov 2005 + +* Fix drivers/dm9000.c when configured in 32 bit mode. + Patch by Eric Benard, 17 Nov 2005 + +* Cleanup debug code for yucca board. + +* MCC200: restrict addressable flash space to 32 MB + +* Add debug console on COM12 for MCC200 board + +* Fix control-c handing in CONFIG_CMDLINE_EDITING + Properly pass break code back from readline. + Patch by Roger Blofeld, 31 Jul 2006 + +* Add commandline history support to all AMCC eval boards + Patch by Stefan Roese, 07 Aug 2006 + +* Add Macronix MXLV320T flash support for AMCC Bamboo + Patch by Stefan Roese, 07 Aug 2006 + +* Change "mii info" to not print an error upon missing PHY at address + Patch by Stefan Roese, 07 Aug 2006 + +* Fix PCI-Express on PPC440SPe rev. A. + +* Fix preboot message on TQM85xx after switching to hush parser. + +* Adapt TQM85xx ramdisk address to Linux kernel memory map + +* Add initial support for PCI-Express on PPC440SPe (Yucca board). + +* Fix compiler warning for TRAB board. + Patch by Martin Krause, 07 Aug 2006 + +* Prevent USB commands from working when USB is stopped. + +* Add rudimentary handling of alternate settings of USB interfaces. + This is in order to fix issues with some USB sticks timing out + during initialization. Some code readability improvements. + +* PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance + AMCC suggested to set the PMU bit to 0 for best performace on + the PPC440 DDR controller. + Please see doc/README.440-DDR-performance for details. + Patch by Stefan Roese, 28 Jul 2006 + +* AMCC bamboo (440EP) U-Boot image reduced to 384kbyte + Please see doc/README.bamboo for details. + Patch by Stefan Roese, 27 Jul 2006 + +* Fix CONFIG_CMDLINE_EDITING implementation + Patch by Stefan Roese, 27 Jul 2006 + +* Fix preboot message on TQM5200 after switching to hush parser. + +* MCC200: set default configuration to low_boot DDR, + and support for configurable options high_boot and/or SDRAM. + +* Add support for 256 MB SDRAM on CPU87 + Patch by Josef Wagner, 25 Nov 2005 + +* Add configuration for cam5200 board (based on TQM5200S). + +* More code cleanup + +* Disabled kvme080 board in MAKEALL because of build problems. + +* Code cleanup + +* Update NetStar board + Patch by Ladislav Michl, 03 Nov 2005 + +* Make code better readable. + Patch by Ladislav Michl, 14 Sep 2005 + +* Enable initrd ATAG for xm250 board. + Patch by Josef Wagner, 05 Sep 2005 + +* Add readline cmdline-editing extension + Patch by JinHua Luo, 01 Sep 2005 + +* Add support for friendly-arm SBC-2410X board + Patch by JinHua Luo, 01 Sep 2005 + +* Fix multi-part image support on i386 platform. + Patch by David Updegraff, 19 Aug 2005 + +* Add support for KVME080 board + Patch by Sangmoon Kim, 18 Aug 2005 + +* Fix MIPS LE build problem + Patch by Matej Kupljen, 10 Aug 2005 + +* Check argument count in "mii" command. + Problem pointed out by Andrew Dyer, 13 Jun 2005 + +* Cleanup TQM5200 board configurations: + - make highboot configurations use environment at high end, too, + to avoid flash fragmentation + - always use redundand environment + - don't enable video code for modules without graphics controller + - provide useful (though different) mtdparts settings + - get rid of CONFIG_CS_AUTOCONF which was always set anyway + +* Extend mkconfig tool to print more useful target name + +* Add support for high-boot on TQM5200 and TQM5200S boards. + Hint: the CPLD on the TQM5200 must be programmed with a software + version supporting the high boot option! The new TQM5200S is + already supporting this option. On the TQM5200 this option will be + supported in configurations with MPC5200 rev B processors. + To actually "high boot", set jumper X30 on the STK52xx. + Patch by Martin Krause, 12 Jul 2006 + +* Add support for new TQM5200 revisions + - Support for TQM5200S (short version without graphic controller) + - Support for modules with 'N' type S29GL128N Spansion flashes + (requires changes to flash layout) + - Support for MPC5200B cpu (mostly support for second SDRAM bank) + Patch by Martin Krause, 07 Jul 2006 + +* Fix support for PS/2 keyboard on TQM85xx boards + The PS/2 keyobard driver for the TQM85xx modules only supports the + internal DUART of the MPC85xx CPU. Since the MPC8560 doesn't + include a DUART, the TQM8560 modules can't be used with the PS/2 + keyboard controller on the STK85xx board. + The PS/2 keyboard driver should work with the modules TQM8540, + TQM8541 and TQM8555, but it only has been tested on a TQM8540, yet. + Make sure the PS/2 controller on the STK85xx is programmed. Jumper + settings: X66 1-2, 9-10; X61 2-3 + Patch by Martin Krause, 21 Jun 2006 + +* Adjust RTC century handling on STK52xx board to match Linux driver. + Patch by Martin Krause, 12 Jun 2006 + +* Adjust filenames for USB update images on TRAB board. + During an automatic update via USB stick, U-Boot searches for + images with the name "firmware.img" and "kernel.img". This names + are now changed to "firmw_01.img" and "kernl_01.img". This is done, + to prevent updates of new boards (with the new macronics "c" step + flashes) with old, incompatible firmware or kernel versions. + Patch by Martin Krause, 21 Jun 2006 + +* Bugfix in VFD routine on TRAB board. + Make sure upper lext pixel can be set to blue, too + (so far only red was possible). + Patch by Martin Krause, 15 Feb 2006 + +* Enable buffered flash writes for TB5200 board. + +* Fix some bugs in TRAB board flash driver. + - increase CFG_FLASH_ERASE_TOUT from 2 to 15 seconds + - use CFG_FLASH_WRITE_TOUT for programming instead of CFG_FLASH_ERASE_TOUT + - remove "Unlock Bypass" mode, because macronix flashes do not support + this mode officially + - fix flash reset command from 0x00FF to 0x00F0. 0x00FF is only specified + for Intel compatible flashes, not for AMD compatible. + Patch by Martin Krause, 15 Feb 2006 + +* Add additional error messages to flash driver on TRAB board + (for erase errors and timeout errors) + Patch by Martin Krause, 14 Feb 2006 + +* Add support for TB5200 board + The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module + integrated in a little aluminium case. + Patch by Martin Krause, 8 Jun 2006 + +* Enable buffered flash writes for TQM5200 board. + +* Fix problems with SanDisk Corporation Cruzer Micro USB memory stick. + +* Add support for TQM885D board. + Patch by Martin Krause, 20 Mar 2006 + +* Fix FEC initialisation: All MII configuration is done via FEC1 + registers, but MII_SPEED was configured according to FEC used. So + if only FEC2 was used, this caused the real MII_SPEED register in + FEC1 to stay uninitalised, leqading to "mii_send STUCK!" messages. + Fix: always configure MII_SPEED on FEC1 only. + Patch by Markus Klotzbuecher, 12 Jul 2006 + +* Add support for SPC1920 board. + Patch by Markus Klotzbuecher, 12 Jul 2006 + +* MCC200 board: support console on any one of the Quad UART ports. + +* Fix error in flash protection calculation on MCC200 board. + +* Major PCMCIA Cleanup to make code better readable and maintainable. + Notes: + - Board-dependend code for RPXLITE and RPXCLASSIC-based boards + placed to the drivers/rpx_pmcia.c file to avoid duplication. + Same for TQM8xx-based boards (drivers/tqm8xx_pmcia.c). + - drivers/i82365.c has been split into two parts located at + board/atc/ti113x.c and board/cpc45/pd67290.c (ATC and CPC45 are + the only boards using CONFIG_82365). + - Changes were tested for clean build and *very* *few* boards. + +* Fix timer problems on AMCC yucca board. + Set Timer Clock Select to use CPU clock as a timer input source. + +* Bring yucca config more in line with other AMCC boards. + +* Add AMCC bamboo board to MAKEALL build script. + +* Fix AMCC bamboo eval board compilation errors. + +* Add system memory to the PCI region list for AMCC PPC44x CPUs. + Enabled it for Yucca board. + +* Cleanup config file and bootup output for Yucca board. + +* Fix CONFIG_440_GX define usage. + +* Remove autogenerated bmp_logo.h file. + +* Add support for AMCC 440SPe CPU based eval board (Yucca). + +* Call serial_initialize() before first debug() is used. + +* Cleanup trab board for GCC-4.x + * VoiceBlue update: use new MTD flash partitioning methods, use more reasonable TEXT_BASE, update default environment and enable keyed autoboot. - Patch by Ladislav Michl, 16. Aug 2005 + Patch by Ladislav Michl, 16. Aug 2005 * Add forgotten changes for the PLEB 2 Board. Patch by David Snowdon, 13. Aug 2005 * Add support for wrPPMC7xx/74xx boards Patch by Richard Danter, 12 Aug 2005 - + * Add support for gth2 board Patch by Thomas Lange, Aug 11 2005 @@ -34,7 +272,7 @@ Changes since U-Boot 1.1.4: With this fix pin I2CSCL (PG6) is really configured as GPIO so the clock pulses are really generated. Patch by Martin Krause, 04 Apr 2006 - + * Fix DDR6 errata on TQM834x boards Patch by Thomas Waehner, 07 Mar 2006 @@ -51,7 +289,7 @@ Changes since U-Boot 1.1.4: has been programmed. Jumper Settings: X66 1-2, 9-10; X61 2-3 * Fix TRAB channel switching delay for trab_fkt.bin standalone applikation - In tsc2000_read_channel() the delay after setting the multiplexer + In tsc2000_read_channel() the delay after setting the multiplexer to a temperature channel is increased from 1,5 ms to 10 ms. This is to allow the multiplexer inputs to stabilize after huge steps of the input signal level. @@ -233,6 +233,7 @@ D: Port to Windriver ppmc8260 board N: Sangmoon Kim E: dogoil@etinsys.com D: Support for debris board +D: Support for KVME080 board N: Frederick W. Klatt E: fred.klatt@windriver.com diff --git a/MAINTAINERS b/MAINTAINERS index aaf91cd..e1baa42 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -197,6 +197,7 @@ Brad Kemp <Brad.Kemp@seranoa.com> Sangmoon Kim <dogoil@etinsys.com> debris MPC8245 + KVME080 MPC8245 Thomas Lange <thomas@corelatus.se> @@ -25,16 +25,16 @@ LIST_5xx=" \ ######################################################################### LIST_5xxx=" \ - BC3450 cpci5200 EVAL5200 icecube_5100 \ - icecube_5200 lite5200b mcc200 o2dnt \ - pf5200 PM520 Total5100 Total5200 \ - Total5200_Rev2 TQM5200 \ + BC3450 cpci5200 EVAL5200 fo300 \ + icecube_5100 icecube_5200 lite5200b mcc200 \ + o2dnt pf5200 PM520 TB5200 \ + Total5100 Total5200 Total5200_Rev2 TQM5200 \ + TQM5200_B TQM5200S \ " ######################################################################### ## MPC8xx Systems ######################################################################### - LIST_8xx=" \ Adder87x GENIETV MBX860T R360MPI \ AdderII GTH MHPC RBC823 \ @@ -44,16 +44,18 @@ LIST_8xx=" \ CCM IP860 NETPHONE RPXlite_DW \ cogent_mpc8xx IVML24 NETTA RRvision \ ELPT860 IVML24_128 NETTA2 SM850 \ - EP88x IVML24_256 NETTA_ISDN SPD823TS \ - ESTEEM192E IVMS8 NETVIA svm_sc8xx \ - ETX094 IVMS8_128 NETVIA_V2 SXNI855T \ - FADS823 IVMS8_256 NX823 TOP860 \ - FADS850SAR KUP4K pcu_e TQM823L \ - FADS860T KUP4X QS823 TQM823L_LCD \ - FLAGADM LANTEC QS850 TQM850L \ - FPS850L lwmon QS860T TQM855L \ - GEN860T MBX quantum TQM860L \ - GEN860T_SC uc100 \ + EP88x IVML24_256 NETTA_ISDN spc1920 \ + ESTEEM192E IVMS8 NETVIA SPD823TS \ + ETX094 IVMS8_128 NETVIA_V2 svm_sc8xx \ + FADS823 IVMS8_256 NX823 SXNI855T \ + FADS850SAR KUP4K pcu_e TOP860 \ + FADS860T KUP4X QS823 TQM823L \ + FLAGADM LANTEC QS850 TQM823L_LCD \ + FPS850L lwmon QS860T TQM850L \ + GEN860T MBX quantum TQM855L \ + GEN860T_SC TQM860L \ + TQM885D \ + uc100 \ v37 \ " @@ -72,10 +74,10 @@ LIST_4xx=" \ luan METROBOX MIP405 MIP405T \ ML2 ml300 ocotea OCRTC \ ORSG p3p440 PCI405 pcs440ep \ - PIP405 PLU405 PMC405 PPChameleonEVB \ - sbc405 VOH405 VOM405 W7OLMC \ + PIP405 PLU405 PMC405 PPChameleonEVB \ + sbc405 VOH405 VOM405 W7OLMC \ W7OLMG walnut WUH405 XPEDITE1K \ - yellowstone yosemite \ + yellowstone yosemite yucca bamboo \ " ######################################################################### @@ -93,9 +95,9 @@ LIST_8220=" \ LIST_824x=" \ A3000 barco BMW CPC45 \ CU824 debris eXalion HIDDEN_DRAGON \ - MOUSSE MUSENKI MVBLUE OXC \ - PN62 Sandpoint8240 Sandpoint8245 sbc8240 \ - SL8245 utx8245 \ + MOUSSE MUSENKI MVBLUE \ + OXC PN62 Sandpoint8240 Sandpoint8245 \ + sbc8240 SL8245 utx8245 \ " ######################################################################### @@ -179,9 +181,10 @@ LIST_ARM9=" \ ap966 cp920t cp922_XA10 cp926ejs \ cp946es cp966 lpd7a400 mp2usb \ mx1ads mx1fs2 netstar omap1510inn \ - omap1610h2 omap1610inn omap730p2 scb9328 \ - smdk2400 smdk2410 trab VCMA9 \ - versatile versatileab versatilepb voiceblue + omap1610h2 omap1610inn omap730p2 sbc2410x \ + scb9328 smdk2400 smdk2410 trab \ + VCMA9 versatile versatileab versatilepb \ + voiceblue \ " ######################################################################### @@ -301,7 +304,7 @@ build_target() { ${MAKE} distclean >/dev/null ${MAKE} ${target}_config ${MAKE} ${JOBS} all 2>&1 >LOG/$target.MAKELOG | tee LOG/$target.ERR -# ${CROSS_COMPILE:-ppc_8xx-}size u-boot | tee -a LOG/$target.MAKELOG + ${CROSS_COMPILE:-ppc_8xx-}size u-boot | tee -a LOG/$target.MAKELOG } #----------------------------------------------------------------------- @@ -7,7 +7,7 @@ # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of +# published by the Free Software Foundatio; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, @@ -114,6 +114,9 @@ endif ifeq ($(CPU),mpc85xx) OBJS += cpu/$(CPU)/resetvec.o endif +ifeq ($(CPU),mpc86xx) +OBJS += cpu/$(CPU)/resetvec.o +endif ifeq ($(CPU),bf533) OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o OBJS += cpu/$(CPU)/cplbhdlr.o cpu/$(CPU)/cplbmgr.o cpu/$(CPU)/flush.o @@ -323,13 +326,30 @@ lite5200b_LOWBOOT_config: unconfig @./mkconfig -a IceCube ppc mpc5xxx icecube mcc200_config \ -mcc200_lowboot_config: unconfig +mcc200_SDRAM \ +mcc200_highboot \ +mcc200_COM12 \ +mcc200_highboot_SDRAM: unconfig @ >include/config.h - @[ -z "$(findstring lowboot_,$@)" ] || \ - { echo "TEXT_BASE = 0xFC000000" >board/mcc200/config.tmp ; \ - echo "... with lowboot configuration" ; \ + @[ -n "$(findstring highboot,$@)" ] || \ + { echo "... with lowboot configuration" ; \ + } + @[ -z "$(findstring highboot,$@)" ] || \ + { echo "TEXT_BASE = 0xFFF00000" >board/mcc200/config.tmp ; \ + echo "... with highboot configuration" ; \ + } + @[ -n "$(findstring _SDRAM,$@)" ] || \ + { echo "... with DDR" ; \ + } + @[ -z "$(findstring _SDRAM,$@)" ] || \ + { echo "#define CONFIG_MCC200_SDRAM" >>include/config.h ; \ + echo "... with SDRAM" ; \ } - @./mkconfig mcc200 ppc mpc5xxx mcc200 + @[ -z "$(findstring COM12,$@)" ] || \ + { echo "#define CONFIG_CONSOLE_COM12" >>include/config.h ; \ + echo "... with console on COM12" ; \ + } + @./mkconfig -a mcc200 ppc mpc5xxx mcc200 o2dnt_config: @./mkconfig o2dnt ppc mpc5xxx o2dnt @@ -356,15 +376,21 @@ smmaco4_config: unconfig @./mkconfig -a smmaco4 ppc mpc5xxx tqm5200 spieval_config: unconfig - @echo "#define CONFIG_CS_AUTOCONF">>include/config.h - @echo "... with automatic CS configuration" @./mkconfig -a spieval ppc mpc5xxx tqm5200 +TB5200_B_config \ +TB5200_config: unconfig + @[ -z "$(findstring _B,$@)" ] || \ + { echo "#define CONFIG_TQM5200_B" >>include/config.h ; \ + echo "... with MPC5200B processor" ; \ + } + @./mkconfig -n $@ -a TB5200 ppc mpc5xxx tqm5200 + MINI5200_config \ EVAL5200_config \ TOP5200_config: unconfig @ echo "#define CONFIG_$(@:_config=) 1" >include/config.h - @./mkconfig -a TOP5200 ppc mpc5xxx top5200 emk + @./mkconfig -n $@ -a TOP5200 ppc mpc5xxx top5200 emk Total5100_config \ Total5200_config \ @@ -394,10 +420,26 @@ Total5200_Rev2_lowboot_config: unconfig } @./mkconfig -a Total5200 ppc mpc5xxx total5200 +cam5200_config \ +fo300_config \ +MiniFAP_config \ +TQM5200S_config \ +TQM5200S_HIGHBOOT_config \ +TQM5200_B_config \ +TQM5200_B_HIGHBOOT_config \ TQM5200_config \ -TQM5200_STK100_config \ -MiniFAP_config: unconfig +TQM5200_STK100_config: unconfig @ >include/config.h + @[ -z "$(findstring cam5200,$@)" ] || \ + { echo "#define CONFIG_CAM5200" >>include/config.h ; \ + echo "#define CONFIG_TQM5200S" >>include/config.h ; \ + echo "#define CONFIG_TQM5200_B" >>include/config.h ; \ + echo "... TQM5200S on Cam5200" ; \ + } + @[ -z "$(findstring fo300,$@)" ] || \ + { echo "#define CONFIG_FO300" >>include/config.h ; \ + echo "... TQM5200 on FO300" ; \ + } @[ -z "$(findstring MiniFAP,$@)" ] || \ { echo "#define CONFIG_MINIFAP" >>include/config.h ; \ echo "... TQM5200_AC on MiniFAP" ; \ @@ -406,9 +448,17 @@ MiniFAP_config: unconfig { echo "#define CONFIG_STK52XX_REV100" >>include/config.h ; \ echo "... on a STK52XX.100 base board" ; \ } - @echo "#define CONFIG_CS_AUTOCONF">>include/config.h ; - @echo "... with automatic CS configuration" ; - @./mkconfig -a TQM5200 ppc mpc5xxx tqm5200 + @[ -z "$(findstring TQM5200_B,$@)" ] || \ + { echo "#define CONFIG_TQM5200_B" >>include/config.h ; \ + } + @[ -z "$(findstring TQM5200S,$@)" ] || \ + { echo "#define CONFIG_TQM5200S" >>include/config.h ; \ + echo "#define CONFIG_TQM5200_B" >>include/config.h ; \ + } + @[ -z "$(findstring HIGHBOOT,$@)" ] || \ + { echo "TEXT_BASE = 0xFFF00000" >board/tqm5200/config.tmp ; \ + } + @./mkconfig -n $@ -a TQM5200 ppc mpc5xxx tqm5200 ######################################################################### ## MPC8xx Systems @@ -705,6 +755,9 @@ RRvision_LCD_config: unconfig SM850_config : unconfig @./mkconfig $(@:_config=) ppc mpc8xx tqm8xx +spc1920_config: + @./mkconfig $(@:_config=) ppc mpc8xx spc1920 + SPD823TS_config: unconfig @./mkconfig $(@:_config=) ppc mpc8xx spd8xx @@ -742,6 +795,7 @@ TQM855M_config \ TQM860M_config \ TQM862M_config \ TQM866M_config \ +TQM885D_config \ virtlab2_config: unconfig @ >include/config.h @[ -z "$(findstring _LCD,$@)" ] || \ @@ -981,6 +1035,9 @@ yosemite_config: unconfig yellowstone_config: unconfig @./mkconfig $(@:_config=) ppc ppc4xx yellowstone amcc +yucca_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx yucca amcc + ######################################################################### ## MPC8220 Systems ######################################################################### @@ -1031,6 +1088,9 @@ eXalion_config: unconfig HIDDEN_DRAGON_config: unconfig @./mkconfig $(@:_config=) ppc mpc824x hidden_dragon +kvme080_config: unconfig + @./mkconfig $(@:_config=) ppc mpc824x kvme080 etin + MOUSSE_config: unconfig @./mkconfig $(@:_config=) ppc mpc824x mousse @@ -1417,6 +1477,14 @@ TQM8560_config: unconfig @./mkconfig -a TQM85xx ppc mpc85xx tqm85xx ######################################################################### +## MPC86xx Systems +######################################################################### + +MPC8641HPCN_config: unconfig + @./mkconfig $(@:_config=) ppc mpc86xx mpc8641hpcn + + +######################################################################### ## 74xx/7xx Systems ######################################################################### @@ -1454,7 +1522,7 @@ ZUMA_config: unconfig ppmc7xx_config: unconfig @./mkconfig $(@:_config=) ppc 74xx_7xx ppmc7xx - + #======================================================================== # ARM #======================================================================== @@ -1588,6 +1656,9 @@ omap730p2_cs3boot_config : unconfig fi; @./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 NULL omap +sbc2410x_config: unconfig + @./mkconfig $(@:_config=) arm arm920t sbc2410x NULL s3c24x0 + scb9328_config : unconfig @./mkconfig $(@:_config=) arm arm920t scb9328 NULL imx @@ -1968,6 +2039,7 @@ clean: rm -f board/netstar/*.srec board/netstar/*.bin rm -f board/trab/trab_fkt board/voiceblue/eeprom rm -f board/integratorap/u-boot.lds board/integratorcp/u-boot.lds + rm -f include/bmp_logo.h clobber: clean find . -type f \( -name .depend \ @@ -306,7 +306,7 @@ The following options need to be configured: CONFIG_ARMADILLO, CONFIG_AT91RM9200DK, CONFIG_CERF250, CONFIG_CSB637, CONFIG_DELTA, CONFIG_DNP1110, - CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE, + CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE, CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610, CONFIG_KB9202, CONFIG_LART, CONFIG_LPD7A400, CONFIG_LUBBOCK, CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4, @@ -1495,6 +1495,12 @@ The following options need to be configured: of the backslashes before semicolons and special symbols. +- Commandline Editing and History: + CONFIG_CMDLINE_EDITING + + Enable editiong and History functions for interactive + commandline input operations + - Default Environment: CONFIG_EXTRA_ENV_SETTINGS diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/event.c b/board/MAI/bios_emulator/scitech/src/pm/win32/event.c index 86448e3..6388052 100644 --- a/board/MAI/bios_emulator/scitech/src/pm/win32/event.c +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/event.c @@ -147,14 +147,14 @@ void _EVT_pumpMessages(void) if (EVT.oldMove != -1) { EVT.evtq[EVT.oldMove].where_x = evt.where_x;/* Modify existing one */ EVT.evtq[EVT.oldMove].where_y = evt.where_y; -/* EVT.evtq[EVT.oldMove].relative_x += mickeyX; // TODO! */ -/* EVT.evtq[EVT.oldMove].relative_y += mickeyY; // TODO! */ +/* EVT.evtq[EVT.oldMove].relative_x += mickeyX; / / TODO! */ +/* EVT.evtq[EVT.oldMove].relative_y += mickeyY; / / TODO! */ evt.what = 0; } else { EVT.oldMove = EVT.freeHead; /* Save id of this move event */ -/* evt.relative_x = mickeyX; // TODO! */ -/* evt.relative_y = mickeyY; // TODO! */ +/* evt.relative_x = mickeyX; / / TODO! */ +/* evt.relative_y = mickeyY; / / TODO! */ } } else diff --git a/board/Marvell/include/core.h b/board/Marvell/include/core.h index 081d5fd..c413439 100644 --- a/board/Marvell/include/core.h +++ b/board/Marvell/include/core.h @@ -91,7 +91,10 @@ extern unsigned int INTERNAL_REG_BASE_ADDR; #define _1G 0x40000000 #define _2G 0x80000000 +#ifndef BOOL_WAS_DEFINED +#define BOOL_WAS_DEFINED typedef enum _bool{false,true} bool; +#endif /* Little to Big endian conversion macros */ diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 7c98920..c93ba6e 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -435,7 +435,7 @@ long int initdram (int board_type) */ init_spd_array(); - dram_size = spd_sdram (0); + dram_size = spd_sdram(); return dram_size; } diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h index 5f5fcde..1ce6366 100644 --- a/board/amcc/bamboo/bamboo.h +++ b/board/amcc/bamboo/bamboo.h @@ -283,10 +283,8 @@ /*----------------------------------------------------------------------------+ | PPC440EP GPIOs addresses. +----------------------------------------------------------------------------*/ -#define GPIO0_BASE 0xEF600B00 #define GPIO0_REAL 0xEF600B00 -#define GPIO1_BASE 0xEF600C00 #define GPIO1_REAL 0xEF600C00 /* Offsets */ @@ -332,17 +330,6 @@ /*----------------------------------------------------------------------------+ - | Declare Configuration values - +----------------------------------------------------------------------------*/ -typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t; -typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t; - -typedef struct { unsigned long add; /* gpio core base address */ - gpio_driver_t in_out; /* Driver Setting */ - gpio_select_t alt_nb; /* Selected Alternate */ -} gpio_param_s; - -/*----------------------------------------------------------------------------+ | XX XX | | XXXXXX XXX XX XXX XXX diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk index 35cb655..9d7f4c3 100644 --- a/board/amcc/bamboo/config.mk +++ b/board/amcc/bamboo/config.mk @@ -1,5 +1,5 @@ # -# (C) Copyright 2002 +# (C) Copyright 2002-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -TEXT_BASE = 0xFFF80000 +TEXT_BASE = 0xFFFA0000 PLATFORM_CPPFLAGS += -DCONFIG_440=1 diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c index 3a50b09..a0acbba 100644 --- a/board/amcc/common/flash.c +++ b/board/amcc/common/flash.c @@ -76,6 +76,9 @@ void flash_print_info(flash_info_t * info) case FLASH_MAN_SST: printf("SST "); break; + case FLASH_MAN_MX: + printf ("MACRONIX "); + break; default: printf("Unknown Vendor "); break; @@ -124,6 +127,9 @@ void flash_print_info(flash_info_t * info) case FLASH_STMW320DT: printf ("M29W320DT (32 M, top sector)\n"); break; + case FLASH_MXLV320T: + printf ("MXLV320T (32 Mbit, top sector)\n"); + break; default: printf("Unknown Chip Type\n"); break; @@ -375,6 +381,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) { if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) || ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { return flash_erase_2(info, s_first, s_last); } else { @@ -555,6 +562,7 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) { if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) || ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { return write_word_2(info, dest, data); } else { @@ -648,6 +656,9 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: info->flash_id = FLASH_MAN_STM; break; + case (CFG_FLASH_WORD_SIZE) MX_MANUFACT: + info->flash_id = FLASH_MAN_MX; + break; default: info->flash_id = FLASH_UNKNOWN; info->sector_count = 0; @@ -676,6 +687,12 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) info->sector_count = 67; info->size = 0x00400000; break; /* => 4 MB */ + case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T: + info->flash_id += FLASH_MXLV320T; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 4 MB */ + default: info->flash_id = FLASH_UNKNOWN; return (0); /* => no or unknown flash */ @@ -711,6 +728,19 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) --i; info->start[i] = base; } + } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) { + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00002000; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000a000; + info->start[i--] = base + info->size - 0x0000c000; + info->start[i--] = base + info->size - 0x0000e000; + info->start[i--] = base + info->size - 0x00010000; + + for (; i >= 0; i--) + info->start[i] = base + i * 0x00010000; } else { if (info->flash_id & FLASH_BTYPE) { /* set sector offsets for bottom boot block type */ diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c index 86d0db7..92dc9d4 100644 --- a/board/amcc/yellowstone/yellowstone.c +++ b/board/amcc/yellowstone/yellowstone.c @@ -313,13 +313,13 @@ void sdram_init(void) mtsdram(mem_tr0, 0x410a4012); /* ?? */ mtsdram(mem_rtr, 0x04080000); /* ?? */ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ - mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */ + mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */ udelay(400); /* Delay 200 usecs (min) */ /*-------------------------------------------------------------------- * Enable the controller, then wait for DCEN to complete *------------------------------------------------------------------*/ - mtsdram(mem_cfg0, 0x84000000); /* Enable */ + mtsdram(mem_cfg0, 0x80000000); /* Enable */ for (;;) { mfsdram(mem_mcsts, reg); diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 6742441..7f2e718 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -309,13 +309,13 @@ void sdram_init(void) mtsdram(mem_tr0, 0x410a4012); /* ?? */ mtsdram(mem_rtr, 0x04080000); /* ?? */ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ - mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */ + mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */ udelay(400); /* Delay 200 usecs (min) */ /*-------------------------------------------------------------------- * Enable the controller, then wait for DCEN to complete *------------------------------------------------------------------*/ - mtsdram(mem_cfg0, 0x84000000); /* Enable */ + mtsdram(mem_cfg0, 0x80000000); /* Enable */ for (;;) { mfsdram(mem_mcsts, reg); diff --git a/board/amcc/yucca/Makefile b/board/amcc/yucca/Makefile new file mode 100644 index 0000000..c85fa31 --- /dev/null +++ b/board/amcc/yucca/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o cmd_yucca.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c new file mode 100644 index 0000000..e698b20 --- /dev/null +++ b/board/amcc/yucca/cmd_yucca.c @@ -0,0 +1,288 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * hacked for evb440spe + */ + +#include <common.h> +#include <command.h> +#include "yucca.h" +#include <i2c.h> +#include <asm/byteorder.h> + +extern void print_evb440spe_info(void); +static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, + int flag, int argc, char *argv[]); + +extern int cmd_get_data_size(char* arg, int default_size); + +/* ------------------------------------------------------------------------- */ +int do_evb440spe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + return setBootStrapClock (cmdtp, 1, flag, argc, argv); +} + +/* ------------------------------------------------------------------------- */ +/* Modify memory. + * + * Syntax: + * evb440spe wrclk prom0,prom1 + */ +static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, + int argc, char *argv[]) +{ + uchar chip; + ulong data; + int nbytes; + extern char console_buffer[]; + + char sysClock[4]; + char cpuClock[4]; + char plbClock[4]; + char pcixClock[4]; + + if (argc < 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[2], "prom0") == 0) + chip = IIC0_BOOTPROM_ADDR; + else + chip = IIC0_ALT_BOOTPROM_ADDR; + + do { + printf("enter sys clock frequency 33 or 66 Mhz or quit to abort\n"); + nbytes = readline (" ? "); + + if (strcmp(console_buffer, "quit") == 0) + return 0; + + if ((strcmp(console_buffer, "33") != 0) & + (strcmp(console_buffer, "66") != 0)) + nbytes=0; + + strcpy(sysClock, console_buffer); + + } while (nbytes == 0); + + do { + if (strcmp(sysClock, "66") == 0) { + printf("enter cpu clock frequency 400, 533 Mhz or quit to abort\n"); + } else { +#ifdef CONFIG_STRESS + printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n"); +#else + printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n"); +#endif + } + nbytes = readline (" ? "); + + if (strcmp(console_buffer, "quit") == 0) + return 0; + + if (strcmp(sysClock, "66") == 0) { + if ((strcmp(console_buffer, "400") != 0) & + (strcmp(console_buffer, "533") != 0) +#ifdef CONFIG_STRESS + & (strcmp(console_buffer, "667") != 0) +#endif + ) { + nbytes = 0; + } + } else { + if ((strcmp(console_buffer, "400") != 0) & + (strcmp(console_buffer, "500") != 0) & + (strcmp(console_buffer, "533") != 0) +#ifdef CONFIG_STRESS + & (strcmp(console_buffer, "667") != 0) +#endif + ) { + nbytes = 0; + } + } + + strcpy(cpuClock, console_buffer); + + } while (nbytes == 0); + + if (strcmp(cpuClock, "500") == 0){ + strcpy(plbClock, "166"); + } else if (strcmp(cpuClock, "533") == 0){ + strcpy(plbClock, "133"); + } else { + do { + if (strcmp(cpuClock, "400") == 0) + printf("enter plb clock frequency 100, 133 Mhz or quit to abort\n"); + +#ifdef CONFIG_STRESS + if (strcmp(cpuClock, "667") == 0) + printf("enter plb clock frequency 133, 166 Mhz or quit to abort\n"); + +#endif + nbytes = readline (" ? "); + + if (strcmp(console_buffer, "quit") == 0) + return 0; + + if (strcmp(cpuClock, "400") == 0) { + if ((strcmp(console_buffer, "100") != 0) & + (strcmp(console_buffer, "133") != 0)) + nbytes = 0; + } +#ifdef CONFIG_STRESS + if (strcmp(cpuClock, "667") == 0) { + if ((strcmp(console_buffer, "133") != 0) & + (strcmp(console_buffer, "166") != 0)) + nbytes = 0; + } +#endif + strcpy(plbClock, console_buffer); + + } while (nbytes == 0); + } + + do { + printf("enter Pci-X clock frequency 33, 66, 100 or 133 Mhz or quit to abort\n"); + nbytes = readline (" ? "); + + if (strcmp(console_buffer, "quit") == 0) + return 0; + + if ((strcmp(console_buffer, "33") != 0) & + (strcmp(console_buffer, "66") != 0) & + (strcmp(console_buffer, "100") != 0) & + (strcmp(console_buffer, "133") != 0)) { + nbytes = 0; + } + strcpy(pcixClock, console_buffer); + + } while (nbytes == 0); + + printf("\nsys clk = %sMhz\n", sysClock); + printf("cpu clk = %sMhz\n", cpuClock); + printf("plb clk = %sMhz\n", plbClock); + printf("Pci-X clk = %sMhz\n", pcixClock); + + do { + printf("\npress [y] to write I2C bootstrap \n"); + printf("or [n] to abort. \n"); + printf("Don't forget to set board switches \n"); + printf("according to your choice before re-starting \n"); + printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n"); + + nbytes = readline (" ? "); + if (strcmp(console_buffer, "n") == 0) + return 0; + + } while (nbytes == 0); + + if (strcmp(sysClock, "33") == 0) { + if ((strcmp(cpuClock, "400") == 0) & + (strcmp(plbClock, "100") == 0)) + data = 0x8678c206; + + if ((strcmp(cpuClock, "400") == 0) & + (strcmp(plbClock, "133") == 0)) + data = 0x8678c2c6; + + if ((strcmp(cpuClock, "500") == 0)) + data = 0x8778f2c6; + + if ((strcmp(cpuClock, "533") == 0)) + data = 0x87790252; + +#ifdef CONFIG_STRESS + if ((strcmp(cpuClock, "667") == 0) & + (strcmp(plbClock, "133") == 0)) + data = 0x87794256; + + if ((strcmp(cpuClock, "667") == 0) & + (strcmp(plbClock, "166") == 0)) + data = 0x87794206; + +#endif + } + if (strcmp(sysClock, "66") == 0) { + if ((strcmp(cpuClock, "400") == 0) & + (strcmp(plbClock, "100") == 0)) + data = 0x84706206; + + if ((strcmp(cpuClock, "400") == 0) & + (strcmp(plbClock, "133") == 0)) + data = 0x847062c6; + + if ((strcmp(cpuClock, "533") == 0)) + data = 0x85708206; + +#ifdef CONFIG_STRESS + if ((strcmp(cpuClock, "667") == 0) & + (strcmp(plbClock, "133") == 0)) + data = 0x8570a256; + + if ((strcmp(cpuClock, "667") == 0) & + (strcmp(plbClock, "166") == 0)) + data = 0x8570a206; + +#endif + } + +#ifdef DEBUG + printf(" pin strap0 to write in i2c = %x\n", data); +#endif /* DEBUG */ + + if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0) + printf("Error writing strap0 in %s\n", argv[2]); + + if (strcmp(pcixClock, "33") == 0) + data = 0x00000701; + + if (strcmp(pcixClock, "66") == 0) + data = 0x00000601; + + if (strcmp(pcixClock, "100") == 0) + data = 0x00000501; + + if (strcmp(pcixClock, "133") == 0) + data = 0x00000401; + + if (strcmp(plbClock, "166") == 0) + data = data | 0x05950000; + else + data = data | 0x05A50000; + +#ifdef DEBUG + printf(" pin strap1 to write in i2c = %x\n", data); +#endif /* DEBUG */ + + udelay(1000); + if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0) + printf("Error writing strap1 in %s\n", argv[2]); + + return 0; +} + +U_BOOT_CMD( + evb440spe, 3, 1, do_evb440spe, + "evb440spe - program the serial device strap\n", + "wrclk [prom0|prom1] - program the serial device strap\n" +); diff --git a/board/amcc/yucca/config.mk b/board/amcc/yucca/config.mk new file mode 100644 index 0000000..ff454eb --- /dev/null +++ b/board/amcc/yucca/config.mk @@ -0,0 +1,42 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# AMCC 440SPe Reference Platform (yucca) board +# + +ifeq ($(ramsym),1) +TEXT_BASE = 0x07FD0000 +else +TEXT_BASE = 0xfffb0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c new file mode 100644 index 0000000..15b8a46 --- /dev/null +++ b/board/amcc/yucca/flash.c @@ -0,0 +1,1054 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> + * Add support for Am29F016D and dynamic switch setting. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> +#include <ppc440.h> +#include "yucca.h" + +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* + * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0 + */ +static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = { + {0xfff00000, 0xfff80000, 0xe7c00001}, /* 0:boot from small flash */ + {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */ + {0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash */ + {0xe7F00000, 0xe7F80000, 0xFFC00001}, /* 3:boot from big flash 33*/ + {0xe7F00000, 0xe7F80000, 0xFFC00001}, /* 4:boot from big flash 66*/ + {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */ + {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */ + {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */ + {0xfff00000, 0xfff80000, 0xe7c00001}, /* 8:boot from small flash */ +}; + +/* + * include common flash code (for amcc boards) + */ +/*----------------------------------------------------------------------- + * Functions + */ +static int write_word(flash_info_t * info, ulong dest, ulong data); +#ifdef CFG_FLASH_2ND_16BIT_DEV +static int write_word_1(flash_info_t * info, ulong dest, ulong data); +static int write_word_2(flash_info_t * info, ulong dest, ulong data); +static int flash_erase_1(flash_info_t * info, int s_first, int s_last); +static int flash_erase_2(flash_info_t * info, int s_first, int s_last); +static ulong flash_get_size_1(vu_long * addr, flash_info_t * info); +static ulong flash_get_size_2(vu_long * addr, flash_info_t * info); +#endif + +void flash_print_info(flash_info_t * info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_STM: + printf("STM "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_SST: + printf("SST "); + break; + case FLASH_MAN_MX: + printf("MIXC "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf("AM29F040 (512 Kbit, uniform sector size)\n"); + break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AMD016: + printf("AM29F016D (16 Mbit, uniform sector size)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_AM033C: + printf("AM29LV033C (32 Mbit, top boot sector)\n"); + break; + case FLASH_SST800A: + printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); + break; + case FLASH_SST160A: + printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); + break; + case FLASH_STMW320DT: + printf ("M29W320DT (32 M, top sector)\n"); + break; + case FLASH_MXLV320T: + printf ("MXLV320T (32 Mbit, top sector)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k = 0; k < size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s%s", + info->start[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " "); + } + printf("\n"); + return; +} + + +/* + * The following code cannot be run from FLASH! + */ +#ifdef CFG_FLASH_2ND_16BIT_DEV +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +{ + /* bit 0 used for big flash marking */ + if ((ulong)addr & 0x1) + return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info); + else + return flash_get_size_1(addr, info); +} + +static ulong flash_get_size_1(vu_long * addr, flash_info_t * info) +#else +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +#endif +{ + short i; + CFG_FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + + DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); + + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + udelay(1000); + + value = addr2[0]; + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D: + info->flash_id += FLASH_AMD016; + info->sector_count = 32; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C: + info->flash_id += FLASH_AMDLV033C; + info->sector_count = 64; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + + /* For AMD29033C flash we need to resend the command of * + * reading flash protection for upper 8 Mb of flash */ + if (i == 32) { + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + + return (info->size); +} + +static int wait_for_DQ7_1(flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile CFG_FLASH_WORD_SIZE *addr = + (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer(0); + last = start; + while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (CFG_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + return 0; +} + +#ifdef CFG_FLASH_2ND_16BIT_DEV +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) { + return flash_erase_2(info, s_first, s_last); + } else { + return flash_erase_1(info, s_first, s_last); + } +} + +static int flash_erase_1(flash_info_t * info, int s_first, int s_last) +#else +int flash_erase(flash_info_t * info, int s_first, int s_last) +#endif +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + + if (prot) + printf("- Warning: %d protected sectors will not be erased!", prot); + + printf("\n"); + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ + for (i = 0; i < 50; i++) + udelay(1000); /* wait 1 ms */ + } else { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7_1(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + + for (; cnt == 0 && i < 4; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + if ((rc = write_word(info, wp, data)) != 0) + return (rc); + + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) + data = (data << 8) | *src++; + + if ((rc = write_word(info, wp, data)) != 0) + return (rc); + + wp += 4; + cnt -= 4; + } + + if (cnt == 0) + return (0); + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +#ifdef CFG_FLASH_2ND_16BIT_DEV +static int write_word(flash_info_t * info, ulong dest, ulong data) +{ + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) { + return write_word_2(info, dest, data); + } else { + return write_word_1(info, dest, data); + } +} + +static int write_word_1(flash_info_t * info, ulong dest, ulong data) +#else +static int write_word(flash_info_t * info, ulong dest, ulong data) +#endif +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + ulong start; + int i, flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) + return (2); + + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + return (1); + } + } + + return (0); +} + +#ifdef CFG_FLASH_2ND_16BIT_DEV + +#undef CFG_FLASH_WORD_SIZE +#define CFG_FLASH_WORD_SIZE unsigned short + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) +{ + short i; + int n; + CFG_FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + + DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + udelay(1000); + + value = addr2[0]; + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + case (CFG_FLASH_WORD_SIZE) MX_MANUFACT: + info->flash_id = FLASH_MAN_MX; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 4 MB */ + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 4 MB */ + case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT: + info->flash_id += FLASH_STMW320DT; + info->sector_count = 67; + info->size = 0x00400000; + break; /* => 4 MB */ + case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T: + info->flash_id += FLASH_MXLV320T; + info->sector_count = 71; + info->size = 0x00400000; + break; /* => 4 MB */ + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) { + /* set sector offsets for top boot block type */ + base += info->size; + i = info->sector_count; + /* 1 x 16k boot sector */ + base -= 16 << 10; + --i; + info->start[i] = base; + /* 2 x 8k boot sectors */ + for (n = 0; n < 2; ++n) { + base -= 8 << 10; + --i; + info->start[i] = base; + } + /* 1 x 32k boot sector */ + base -= 32 << 10; + --i; + info->start[i] = base; + + while (i > 0) { /* 64k regular sectors */ + base -= 64 << 10; + --i; + info->start[i] = base; + } + } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) { + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00002000; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000a000; + info->start[i--] = base + info->size - 0x0000c000; + info->start[i--] = base + info->size - 0x0000e000; + info->start[i--] = base + info->size - 0x00010000; + + for (; i >= 0; i--) + info->start[i] = base + i * 0x00010000; + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + + for (i = 4; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + + for (; i >= 0; i--) + info->start[i] = base + i * 0x00010000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + + /* For AMD29033C flash we need to resend the command of * + * reading flash protection for upper 8 Mb of flash */ + if (i == 32) { + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + + return (info->size); +} + +static int wait_for_DQ7_2(flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile CFG_FLASH_WORD_SIZE *addr = + (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer(0); + last = start; + while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (CFG_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + return 0; +} + +static int flash_erase_2(flash_info_t * info, int s_first, int s_last) +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + + if (prot) + printf("- Warning: %d protected sectors will not be erased!", prot); + + printf("\n"); + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ + for (i = 0; i < 50; i++) + udelay(1000); /* wait 1 ms */ + } else { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7_2(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +static int write_word_2(flash_info_t * info, ulong dest, ulong data) +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) + return (2); + + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + return (1); + } + } + + return (0); +} +#endif /* CFG_FLASH_2ND_16BIT_DEV */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static int write_word(flash_info_t * info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init(void) +{ + unsigned long total_b = 0; + unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned short index = 0; + int i; + unsigned long val; + unsigned long ebc_boot_size; + unsigned long boot_selection; + + mfsdr(sdr_pstrp0, val); + index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 28; + + if ((index == 0xc) || (index == 8)) { + /* + * Boot Settings in IIC EEprom address 0xA8 or 0xA0 + * Read Serial Device Strap Register1 in PPC440SPe + */ + mfsdr(sdr_sdstp1, val); + boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK; + ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK; + + switch(boot_selection) { + case SDR0_SDSTP1_BOOT_SEL_EBC: + switch(ebc_boot_size) { + case SDR0_SDSTP1_EBC_ROM_BS_16BIT: + index = 3; + break; + case SDR0_SDSTP1_EBC_ROM_BS_8BIT: + index = 0; + break; + } + break; + + case SDR0_SDSTP1_BOOT_SEL_PCI: + index = 1; + break; + + } + } /*else if (index == 0) {*/ +/* if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE)*/ +/* index = 8;*/ /* sram below op code flash -> new index 8*/ +/* }*/ + + DEBUGF("\n"); + DEBUGF("FLASH: Index: %d\n", index); + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + + /* check whether the address is 0 */ + if (flash_addr_table[index][i] == 0) + continue; + + /* call flash_get_size() to initialize sector address */ + size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], + &flash_info[i]); + + flash_info[i].size = size_b[i]; + + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, size_b[i], size_b[i] << 20); + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + } + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[i]); +#if defined(CFG_ENV_IS_IN_FLASH) + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[i]); +#if defined(CFG_ENV_ADDR_REDUND) + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[i]); +#endif +#endif + total_b += flash_info[i].size; + } + + return total_b; +} diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S new file mode 100644 index 0000000..c9eca68 --- /dev/null +++ b/board/amcc/yucca/init.S @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* port to AMCC 440SPE evaluatioon board - SG April 12,2005 */ + +#include <ppc_asm.tmpl> +#include <config.h> + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID )) +#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn)) +#define TLB2(a) ((a) & 0x00000fbf) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ;\ +0: mflr r0 ;\ + mtlr r1 ;\ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + +/************************************************************************** + * TLB table for revA + *************************************************************************/ + .globl tlbtabA +tlbtabA: + tlbtab_start + tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G) + + tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + + tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) + tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I) + + tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbtab_end + +/************************************************************************** + * TLB table for revB + * + * Notice: revB of the 440SPe chip is very strict about PLB real addresses + * and ranges to be mapped for config space: it seems to only work with + * d_nnnn_nnnn range (hangs the core upon config transaction attempts when + * set otherwise) while revA uses c_nnnn_nnnn. + *************************************************************************/ + .globl tlbtabB +tlbtabB: + tlbtab_start + tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G) + + tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + + tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) + tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I) + + tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbtab_end diff --git a/board/amcc/yucca/u-boot.lds b/board/amcc/yucca/u-boot.lds new file mode 100644 index 0000000..9df4f92 --- /dev/null +++ b/board/amcc/yucca/u-boot.lds @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/yucca/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/yucca/u-boot.lds.debug b/board/amcc/yucca/u-boot.lds.debug new file mode 100644 index 0000000..474f922 --- /dev/null +++ b/board/amcc/yucca/u-boot.lds.debug @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2002-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/yucca/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c new file mode 100644 index 0000000..af12839 --- /dev/null +++ b/board/amcc/yucca/yucca.c @@ -0,0 +1,1224 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Port to AMCC-440SPE Evaluation Board SOP - April 2005 + * + * PCIe supporting routines derived from Linux 440SPe PCIe driver. + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> +#include <i2c.h> +#include <asm-ppc/io.h> + +#include "yucca.h" + +void fpga_init (void); + +void get_sys_info(PPC440_SYS_INFO *board_cfg ); +int compare_to_true(char *str ); +char *remove_l_w_space(char *in_str ); +char *remove_t_w_space(char *in_str ); +int get_console_port(void); +unsigned long ppcMfcpr(unsigned long cpr_reg); +unsigned long ppcMfsdr(unsigned long sdr_reg); + +int ppc440spe_init_pcie_rootport(int port); +void ppc440spe_setup_pcie(struct pci_controller *hose, int port); + +#define DEBUG_ENV +#ifdef DEBUG_ENV +#define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif + +#define FALSE 0 +#define TRUE 1 + +int board_early_init_f (void) +{ +/*----------------------------------------------------------------------------+ +| Define Boot devices ++----------------------------------------------------------------------------*/ +#define BOOT_FROM_SMALL_FLASH 0x00 +#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01 +#define BOOT_FROM_PCI 0x02 +#define BOOT_DEVICE_UNKNOWN 0x03 + +/*----------------------------------------------------------------------------+ +| EBC Devices Characteristics +| Peripheral Bank Access Parameters - EBC_BxAP +| Peripheral Bank Configuration Register - EBC_BxCR ++----------------------------------------------------------------------------*/ + +/* + * Small Flash and FRAM + * BU Value + * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 + * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000 + * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000 + */ +#define EBC_BXAP_SMALL_FLASH EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(7) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(0) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED + +#define EBC_BXCR_SMALL_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \ + EBC_BXCR_BS_16MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_8BIT + +#define EBC_BXCR_SMALL_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xe7000000) | \ + EBC_BXCR_BS_16MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_8BIT + +/* + * Large Flash and SRAM + * BU Value + * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 + * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000 + * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000 +*/ +#define EBC_BXAP_LARGE_FLASH EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(7) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(0) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED + +#define EBC_BXCR_LARGE_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \ + EBC_BXCR_BS_16MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT + +#define EBC_BXCR_LARGE_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xE7000000) | \ + EBC_BXCR_BS_16MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT + +/* + * FPGA + * BU value : + * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000 + * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000 + */ +#define EBC_BXAP_FPGA EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(11) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(10) | \ + EBC_BXAP_OEN_ENCODE(1) | \ + EBC_BXAP_WBN_ENCODE(1) | \ + EBC_BXAP_WBF_ENCODE(1) | \ + EBC_BXAP_TH_ENCODE(1) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_RW | \ + EBC_BXAP_PEN_DISABLED + +#define EBC_BXCR_FPGA_CS1 EBC_BXCR_BAS_ENCODE(0xe2000000) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT + + unsigned long mfr; + /* + * Define Variables for EBC initialization depending on BOOTSTRAP option + */ + unsigned long sdr0_pinstp, sdr0_sdstp1 ; + unsigned long bootstrap_settings, ebc_data_width, boot_selection; + int computed_boot_device = BOOT_DEVICE_UNKNOWN; + + /*-------------------------------------------------------------------+ + | Initialize EBC CONFIG - + | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC + | default value : + | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 + | + +-------------------------------------------------------------------*/ + mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + EBC_CFG_PTD_ENABLE | + EBC_CFG_RTC_16PERCLK | + EBC_CFG_ATC_PREVIOUS | + EBC_CFG_DTC_PREVIOUS | + EBC_CFG_CTC_PREVIOUS | + EBC_CFG_OEO_PREVIOUS | + EBC_CFG_EMC_DEFAULT | + EBC_CFG_PME_DISABLE | + EBC_CFG_PR_16); + + /*-------------------------------------------------------------------+ + | + | PART 1 : Initialize EBC Bank 1 + | ============================== + | Bank1 is always associated to the EPLD. + | It has to be initialized prior to other banks settings computation + | since some board registers values may be needed to determine the + | boot type + | + +-------------------------------------------------------------------*/ + mtebc(pb1ap, EBC_BXAP_FPGA); + mtebc(pb1cr, EBC_BXCR_FPGA_CS1); + + /*-------------------------------------------------------------------+ + | + | PART 2 : Determine which boot device was selected + | ================================================= + | + | Read Pin Strap Register in PPC440SPe + | Result can either be : + | - Boot strap = boot from EBC 8bits => Small Flash + | - Boot strap = boot from PCI + | - Boot strap = IIC + | In case of boot from IIC, read Serial Device Strap Register1 + | + | Result can either be : + | - Boot from EBC - EBC Bus Width = 8bits => Small Flash + | - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM + | - Boot from PCI + | + +-------------------------------------------------------------------*/ + /* Read Pin Strap Register in PPC440SP */ + sdr0_pinstp = ppcMfsdr(SDR0_PINSTP); + bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK; + + switch (bootstrap_settings) { + case SDR0_PINSTP_BOOTSTRAP_SETTINGS0: + /* + * Strapping Option A + * Boot from EBC - 8 bits , Small Flash + */ + computed_boot_device = BOOT_FROM_SMALL_FLASH; + break; + case SDR0_PINSTP_BOOTSTRAP_SETTINGS1: + /* + * Strappping Option B + * Boot from PCI + */ + computed_boot_device = BOOT_FROM_PCI; + break; + case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN: + case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN: + /* + * Strapping Option C or D + * Boot Settings in IIC EEprom address 0x50 or 0x54 + * Read Serial Device Strap Register1 in PPC440SPe + */ + sdr0_sdstp1 = ppcMfsdr(SDR0_SDSTP1); + boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK; + ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK; + + switch (boot_selection) { + case SDR0_SDSTP1_ERPN_EBC: + switch (ebc_data_width) { + case SDR0_SDSTP1_EBCW_16_BITS: + computed_boot_device = + BOOT_FROM_LARGE_FLASH_OR_SRAM; + break; + case SDR0_SDSTP1_EBCW_8_BITS : + computed_boot_device = BOOT_FROM_SMALL_FLASH; + break; + } + break; + + case SDR0_SDSTP1_ERPN_PCI: + computed_boot_device = BOOT_FROM_PCI; + break; + default: + /* should not occure */ + computed_boot_device = BOOT_DEVICE_UNKNOWN; + } + break; + default: + /* should not be */ + computed_boot_device = BOOT_DEVICE_UNKNOWN; + break; + } + + /*-------------------------------------------------------------------+ + | + | PART 3 : Compute EBC settings depending on selected boot device + | ====== ====================================================== + | + | Resulting EBC init will be among following configurations : + | + | - Boot from EBC 8bits => boot from Small Flash selected + | EBC-CS0 = Small Flash + | EBC-CS2 = Large Flash and SRAM + | + | - Boot from EBC 16bits => boot from Large Flash or SRAM + | EBC-CS0 = Large Flash or SRAM + | EBC-CS2 = Small Flash + | + | - Boot from PCI + | EBC-CS0 = not initialized to avoid address contention + | EBC-CS2 = same as boot from Small Flash selected + | + +-------------------------------------------------------------------*/ + unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0; + unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0; + + switch (computed_boot_device) { + /*-------------------------------------------------------------------*/ + case BOOT_FROM_PCI: + /*-------------------------------------------------------------------*/ + /* + * By Default CS2 is affected to LARGE Flash + * do not initialize SMALL FLASH to avoid address contention + * Large Flash + */ + ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; + ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2; + break; + + /*-------------------------------------------------------------------*/ + case BOOT_FROM_SMALL_FLASH: + /*-------------------------------------------------------------------*/ + ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH; + ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0; + + /* + * Large Flash or SRAM + */ + /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */ + ebc0_cs2_bxap_value = 0x048ff240; + ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2; + break; + + /*-------------------------------------------------------------------*/ + case BOOT_FROM_LARGE_FLASH_OR_SRAM: + /*-------------------------------------------------------------------*/ + ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH; + ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0; + + /* Small flash */ + ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH; + ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2; + break; + + /*-------------------------------------------------------------------*/ + default: + /*-------------------------------------------------------------------*/ + /* BOOT_DEVICE_UNKNOWN */ + break; + } + + mtebc(pb0ap, ebc0_cs0_bxap_value); + mtebc(pb0cr, ebc0_cs0_bxcr_value); + mtebc(pb2ap, ebc0_cs2_bxap_value); + mtebc(pb2cr, ebc0_cs2_bxcr_value); + + /*--------------------------------------------------------------------+ + | Interrupt controller setup for the AMCC 440SPe Evaluation board. + +--------------------------------------------------------------------+ + +---------------------------------------------------------------------+ + |Interrupt| Source | Pol. | Sensi.| Crit. | + +---------+-----------------------------------+-------+-------+-------+ + | IRQ 00 | UART0 | High | Level | Non | + | IRQ 01 | UART1 | High | Level | Non | + | IRQ 02 | IIC0 | High | Level | Non | + | IRQ 03 | IIC1 | High | Level | Non | + | IRQ 04 | PCI0X0 MSG IN | High | Level | Non | + | IRQ 05 | PCI0X0 CMD Write | High | Level | Non | + | IRQ 06 | PCI0X0 Power Mgt | High | Level | Non | + | IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non | + | IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non | + | IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non | + | IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non | + | IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit | + | IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non | + | IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non | + | IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non | + | IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non | + | IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non | + | IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit | + | IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non | + | IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non | + | IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non | + | IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non | + | IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non | + | IRQ 23 | I2O Inbound Doorbell | High | Level | Non | + | IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non | + | IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non | + | IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non | + | IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non | + | IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non | + | IRQ 29 | GPT Down Count Timer | Rising| Edge | Non | + | IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non | + | IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. | + |---------------------------------------------------------------------- + | IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non | + | IRQ 33 | MAL Serr | High | Level | Non | + | IRQ 34 | MAL Txde | High | Level | Non | + | IRQ 35 | MAL Rxde | High | Level | Non | + | IRQ 36 | DMC CE or DMC UE | High | Level | Non | + | IRQ 37 | EBC or UART2 | High |Lvl Edg| Non | + | IRQ 38 | MAL TX EOB | High | Level | Non | + | IRQ 39 | MAL RX EOB | High | Level | Non | + | IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non | + | IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non | + | IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non | + | IRQ 43 | L2 Cache | Risin | Edge | Non | + | IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non | + | IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non | + | IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non | + | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | + | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | + | IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non | + | IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non | + | IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non | + | IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | + | IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non | + | IRQ 54 | DMA Error | High | Level | Non | + | IRQ 55 | DMA I2O Error | High | Level | Non | + | IRQ 56 | Serial ROM | High | Level | Non | + | IRQ 57 | PCIX0 Error | High | Edge | Non | + | IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non | + | IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non | + | IRQ 60 | EMAC0 Interrupt | High | Level | Non | + | IRQ 61 | EMAC0 Wake-up | High | Level | Non | + | IRQ 62 | Reserved | High | Level | Non | + | IRQ 63 | XOR | High | Level | Non | + |---------------------------------------------------------------------- + | IRQ 64 | PE0 AL | High | Level | Non | + | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | + | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | + | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | + | IRQ 68 | PE0 TCR | High | Level | Non | + | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | + | IRQ 70 | PE0 DCR Error | High | Level | Non | + | IRQ 71 | Reserved | N/A | N/A | Non | + | IRQ 72 | PE1 AL | High | Level | Non | + | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | + | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | + | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | + | IRQ 76 | PE1 TCR | High | Level | Non | + | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | + | IRQ 78 | PE1 DCR Error | High | Level | Non | + | IRQ 79 | Reserved | N/A | N/A | Non | + | IRQ 80 | PE2 AL | High | Level | Non | + | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | + | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | + | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | + | IRQ 84 | PE2 TCR | High | Level | Non | + | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | + | IRQ 86 | PE2 DCR Error | High | Level | Non | + | IRQ 87 | Reserved | N/A | N/A | Non | + | IRQ 88 | External IRQ(5) | Progr | Progr | Non | + | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | + | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | + | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | + | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | + | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | + | IRQ 94 | Reserved | N/A | N/A | Non | + | IRQ 95 | Reserved | N/A | N/A | Non | + |--------------------------------------------------------------------- + | IRQ 96 | PE0 INTA | High | Level | Non | + | IRQ 97 | PE0 INTB | High | Level | Non | + | IRQ 98 | PE0 INTC | High | Level | Non | + | IRQ 99 | PE0 INTD | High | Level | Non | + | IRQ 100 | PE1 INTA | High | Level | Non | + | IRQ 101 | PE1 INTB | High | Level | Non | + | IRQ 102 | PE1 INTC | High | Level | Non | + | IRQ 103 | PE1 INTD | High | Level | Non | + | IRQ 104 | PE2 INTA | High | Level | Non | + | IRQ 105 | PE2 INTB | High | Level | Non | + | IRQ 106 | PE2 INTC | High | Level | Non | + | IRQ 107 | PE2 INTD | Risin | Edge | Non | + | IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non | + | IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non | + | IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non | + | IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non | + | IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non | + | IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non | + | IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non | + | IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non | + | IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non | + | IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non | + | IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non | + | IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non | + | IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non | + | IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non | + | IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non | + | IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non | + | IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non | + | IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non | + | IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non | + | IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non | + +---------+-----------------------------------+-------+-------+------*/ + /*--------------------------------------------------------------------+ + | Put UICs in PowerPC440SPemode. + | Initialise UIC registers. Clear all interrupts. Disable all + | interrupts. + | Set critical interrupt values. Set interrupt polarities. Set + | interrupt trigger levels. Make bit 0 High priority. Clear all + | interrupts again. + +-------------------------------------------------------------------*/ + mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic3er, 0x00000000); /* disable all interrupts */ + mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical + * interrupts */ + mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */ + mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest + * priority */ + mtdcr (uic3sr, 0x00000000); /* clear all interrupts */ + mtdcr (uic3sr, 0xffffffff); /* clear all interrupts */ + + mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic2er, 0x00000000); /* disable all interrupts */ + mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical + * interrupts */ + mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities */ + mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */ + mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest + * priority */ + mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ + mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ + + mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic1er, 0x00000000); /* disable all interrupts */ + mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical + * interrupts */ + mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels */ + mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest + * priority */ + mtdcr (uic1sr, 0x00000000); /* clear all interrupts */ + mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */ + + mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted + * cascade to be checked */ + mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical + * interrupts */ + mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities */ + mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */ + mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest + * priority */ + mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ + mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ + + /* SDR0_MFR should be part of Ethernet init */ + mfsdr (sdr_mfr, mfr); + mfr &= ~SDR0_MFR_ECS_MASK; + /*mtsdr(sdr_mfr, mfr);*/ + fpga_init(); + + return 0; +} + +int checkboard (void) +{ + char *s = getenv("serial#"); + + printf("Board: Yucca - AMCC 440SPe Evaluation Board"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +static long int yucca_probe_for_dimms(void) +{ + long int dimm_installed[MAXDIMMS]; + long int dimm_num, probe_result; + long int dimms_found = 0; + uchar dimm_addr = IIC0_DIMM0_ADDR; + + for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) { + /* check if there is a chip at the dimm address */ + switch (dimm_num) { + case 0: + dimm_addr = IIC0_DIMM0_ADDR; + break; + case 1: + dimm_addr = IIC0_DIMM1_ADDR; + break; + } + probe_result = i2c_probe(dimm_addr); + + if (probe_result == 0) { + dimm_installed[dimm_num] = TRUE; + dimms_found++; + debug("DIMM slot %d: DDR2 SDRAM detected\n",dimm_num); + } else { + dimm_installed[dimm_num] = FALSE; + debug("DIMM slot %d: Not populated or cannot sucessfully probe the DIMM\n", dimm_num); + } + } + + if (dimms_found == 0) { + printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); + hang(); + } + + if (dimm_installed[0] != TRUE) { + printf("\nERROR - DIMM slot 0 must be populated before DIMM slot 1.\n"); + printf(" Unsupported configuration. Move DIMM module from DIMM slot 1 to slot 0.\n\n"); + hang(); + } + + return dimms_found; +} + +/************************************************************************* + * init SDRAM controller with fixed value + * the initialization values are for 2x MICRON DDR2 + * PN: MT18HTF6472DY-53EB2 + * 512MB, DDR2, 533, CL4, ECC, REG + ************************************************************************/ +static long int fixed_sdram(void) +{ + long int yucca_dimms = 0; + + yucca_dimms = yucca_probe_for_dimms(); + + /* SDRAM0_MCOPT2 (0X21) Clear DCEN BIT */ + mtdcr( 0x10, 0x00000021 ); + mtdcr( 0x11, 0x84000000 ); + + /* SDRAM0_MCOPT1 (0X20) ECC OFF / 64 bits / 4 banks / DDR2 */ + mtdcr( 0x10, 0x00000020 ); + mtdcr( 0x11, 0x2D122000 ); + + /* SET MCIF0_CODT Die Termination On */ + mtdcr( 0x10, 0x00000026 ); + if (yucca_dimms == 2) + mtdcr( 0x11, 0x2A800021 ); + else if (yucca_dimms == 1) + mtdcr( 0x11, 0x02800021 ); + + /* On-Die Termination for Bank 0 */ + mtdcr( 0x10, 0x00000022 ); + if (yucca_dimms == 2) + mtdcr( 0x11, 0x18000000 ); + else if (yucca_dimms == 1) + mtdcr( 0x11, 0x06000000 ); + + /* On-Die Termination for Bank 1 */ + mtdcr( 0x10, 0x00000023 ); + if (yucca_dimms == 2) + mtdcr( 0x11, 0x18000000 ); + else if (yucca_dimms == 1) + mtdcr( 0x11, 0x01800000 ); + + /* On-Die Termination for Bank 2 */ + mtdcr( 0x10, 0x00000024 ); + if (yucca_dimms == 2) + mtdcr( 0x11, 0x01800000 ); + else if (yucca_dimms == 1) + mtdcr( 0x11, 0x00000000 ); + + /* On-Die Termination for Bank 3 */ + mtdcr( 0x10, 0x00000025 ); + if (yucca_dimms == 2) + mtdcr( 0x11, 0x01800000 ); + else if (yucca_dimms == 1) + mtdcr( 0x11, 0x00000000 ); + + /* Refresh Time register (0x30) Refresh every 7.8125uS */ + mtdcr( 0x10, 0x00000030 ); + mtdcr( 0x11, 0x08200000 ); + + /* SET MCIF0_MMODE CL 4 */ + mtdcr( 0x10, 0x00000088 ); + mtdcr( 0x11, 0x00000642 ); + + /* MCIF0_MEMODE */ + mtdcr( 0x10, 0x00000089 ); + mtdcr( 0x11, 0x00000004 ); + + /*SET MCIF0_MB0CF */ + mtdcr( 0x10, 0x00000040 ); + mtdcr( 0x11, 0x00000201 ); + + /* SET MCIF0_MB1CF */ + mtdcr( 0x10, 0x00000044 ); + mtdcr( 0x11, 0x00000201 ); + + /* SET MCIF0_MB2CF */ + mtdcr( 0x10, 0x00000048 ); + if (yucca_dimms == 2) + mtdcr( 0x11, 0x00000201 ); + else if (yucca_dimms == 1) + mtdcr( 0x11, 0x00000000 ); + + /* SET MCIF0_MB3CF */ + mtdcr( 0x10, 0x0000004c ); + if (yucca_dimms == 2) + mtdcr( 0x11, 0x00000201 ); + else if (yucca_dimms == 1) + mtdcr( 0x11, 0x00000000 ); + + /* SET MCIF0_INITPLR0 # NOP */ + mtdcr( 0x10, 0x00000050 ); + mtdcr( 0x11, 0xB5380000 ); + + /* SET MCIF0_INITPLR1 # PRE */ + mtdcr( 0x10, 0x00000051 ); + mtdcr( 0x11, 0x82100400 ); + + /* SET MCIF0_INITPLR2 # EMR2 */ + mtdcr( 0x10, 0x00000052 ); + mtdcr( 0x11, 0x80820000 ); + + /* SET MCIF0_INITPLR3 # EMR3 */ + mtdcr( 0x10, 0x00000053 ); + mtdcr( 0x11, 0x80830000 ); + + /* SET MCIF0_INITPLR4 # EMR DLL ENABLE */ + mtdcr( 0x10, 0x00000054 ); + mtdcr( 0x11, 0x80810000 ); + + /* SET MCIF0_INITPLR5 # MR DLL RESET */ + mtdcr( 0x10, 0x00000055 ); + mtdcr( 0x11, 0x80800542 ); + + /* SET MCIF0_INITPLR6 # PRE */ + mtdcr( 0x10, 0x00000056 ); + mtdcr( 0x11, 0x82100400 ); + + /* SET MCIF0_INITPLR7 # Refresh */ + mtdcr( 0x10, 0x00000057 ); + mtdcr( 0x11, 0x8A080000 ); + + /* SET MCIF0_INITPLR8 # Refresh */ + mtdcr( 0x10, 0x00000058 ); + mtdcr( 0x11, 0x8A080000 ); + + /* SET MCIF0_INITPLR9 # Refresh */ + mtdcr( 0x10, 0x00000059 ); + mtdcr( 0x11, 0x8A080000 ); + + /* SET MCIF0_INITPLR10 # Refresh */ + mtdcr( 0x10, 0x0000005A ); + mtdcr( 0x11, 0x8A080000 ); + + /* SET MCIF0_INITPLR11 # MR */ + mtdcr( 0x10, 0x0000005B ); + mtdcr( 0x11, 0x80800442 ); + + /* SET MCIF0_INITPLR12 # EMR OCD Default*/ + mtdcr( 0x10, 0x0000005C ); + mtdcr( 0x11, 0x80810380 ); + + /* SET MCIF0_INITPLR13 # EMR OCD Exit */ + mtdcr( 0x10, 0x0000005D ); + mtdcr( 0x11, 0x80810000 ); + + /* 0x80: Adv Addr clock by 180 deg */ + mtdcr( 0x10, 0x00000080 ); + mtdcr( 0x11, 0x80000000 ); + + /* 0x21: Exit self refresh, set DC_EN */ + mtdcr( 0x10, 0x00000021 ); + mtdcr( 0x11, 0x28000000 ); + + /* 0x81: Write DQS Adv 90 + Fractional DQS Delay */ + mtdcr( 0x10, 0x00000081 ); + mtdcr( 0x11, 0x80000800 ); + + /* MCIF0_SDTR1 */ + mtdcr( 0x10, 0x00000085 ); + mtdcr( 0x11, 0x80201000 ); + + /* MCIF0_SDTR2 */ + mtdcr( 0x10, 0x00000086 ); + mtdcr( 0x11, 0x42103242 ); + + /* MCIF0_SDTR3 */ + mtdcr( 0x10, 0x00000087 ); + mtdcr( 0x11, 0x0C100D14 ); + + /* SET MQ0_B0BAS base addr 00000000 / 256MB */ + mtdcr( 0x40, 0x0000F800 ); + + /* SET MQ0_B1BAS base addr 10000000 / 256MB */ + mtdcr( 0x41, 0x0400F800 ); + + /* SET MQ0_B2BAS base addr 20000000 / 256MB */ + if (yucca_dimms == 2) + mtdcr( 0x42, 0x0800F800 ); + else if (yucca_dimms == 1) + mtdcr( 0x42, 0x00000000 ); + + /* SET MQ0_B3BAS base addr 30000000 / 256MB */ + if (yucca_dimms == 2) + mtdcr( 0x43, 0x0C00F800 ); + else if (yucca_dimms == 1) + mtdcr( 0x43, 0x00000000 ); + + /* SDRAM_RQDC */ + mtdcr( 0x10, 0x00000070 ); + mtdcr( 0x11, 0x8000003F ); + + /* SDRAM_RDCC */ + mtdcr( 0x10, 0x00000078 ); + mtdcr( 0x11, 0x80000000 ); + + /* SDRAM_RFDC */ + mtdcr( 0x10, 0x00000074 ); + mtdcr( 0x11, 0x00000220 ); + + return (yucca_dimms * 512) << 20; +} + +long int initdram (int board_type) +{ + long dram_size = 0; + + dram_size = fixed_sdram(); + + return dram_size; +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) 0x00000000; + uint *pend = (uint *) 0x08000000; + uint *p; + + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + return 0; +} +#endif + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller * hose ) +{ + unsigned long strap; + + /*-------------------------------------------------------------------+ + * The yucca board is always configured as the host & requires the + * PCI arbiter to be enabled. + *-------------------------------------------------------------------*/ + mfsdr(sdr_sdstp1, strap); + if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { + printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); + return 0; + } + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller * hose ) +{ + DECLARE_GLOBAL_DATA_PTR; + + /*-------------------------------------------------------------------+ + * Disable everything + *-------------------------------------------------------------------*/ + out32r( PCIX0_PIM0SA, 0 ); /* disable */ + out32r( PCIX0_PIM1SA, 0 ); /* disable */ + out32r( PCIX0_PIM2SA, 0 ); /* disable */ + out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + + /*-------------------------------------------------------------------+ + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 + * strapping options to not support sizes such as 128/256 MB. + *-------------------------------------------------------------------*/ + out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAH, 0 ); + out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + out32r( PCIX0_BAR0, 0 ); + + /*-------------------------------------------------------------------+ + * Program the board's subsystem id/vendor id + *-------------------------------------------------------------------*/ + out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + + out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +#if defined(CONFIG_PCI) +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +int is_pci_host(struct pci_controller *hose) +{ + /* The yucca board is always configured as host. */ + return 1; +} + + +int yucca_pcie_card_present(int port) +{ + u16 reg; + + reg = in_be16((u16 *)FPGA_REG1C); + switch(port) { + case 0: + return !(reg & FPGA_REG1C_PE0_PRSNT); + case 1: + return !(reg & FPGA_REG1C_PE1_PRSNT); + case 2: + return !(reg & FPGA_REG1C_PE2_PRSNT); + default: + return 0; + } +} + +/* + * For the given slot, set rootpoint mode, send power to the slot, + * turn on the green LED and turn off the yellow LED, enable the clock + * and turn off reset. + */ +void yucca_setup_pcie_fpga_rootpoint(int port) +{ + u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint; + + switch(port) { + case 0: + rootpoint = FPGA_REG1C_PE0_ROOTPOINT; + endpoint = 0; + power = FPGA_REG1A_PE0_PWRON; + green_led = FPGA_REG1A_PE0_GLED; + clock = FPGA_REG1A_PE0_REFCLK_ENABLE; + yellow_led = FPGA_REG1A_PE0_YLED; + reset_off = FPGA_REG1C_PE0_PERST; + break; + case 1: + rootpoint = 0; + endpoint = FPGA_REG1C_PE1_ENDPOINT; + power = FPGA_REG1A_PE1_PWRON; + green_led = FPGA_REG1A_PE1_GLED; + clock = FPGA_REG1A_PE1_REFCLK_ENABLE; + yellow_led = FPGA_REG1A_PE1_YLED; + reset_off = FPGA_REG1C_PE1_PERST; + break; + case 2: + rootpoint = 0; + endpoint = FPGA_REG1C_PE2_ENDPOINT; + power = FPGA_REG1A_PE2_PWRON; + green_led = FPGA_REG1A_PE2_GLED; + clock = FPGA_REG1A_PE2_REFCLK_ENABLE; + yellow_led = FPGA_REG1A_PE2_YLED; + reset_off = FPGA_REG1C_PE2_PERST; + break; + + default: + return; + } + + out_be16((u16 *)FPGA_REG1A, + ~(power | clock | green_led) & + (yellow_led | in_be16((u16 *)FPGA_REG1A))); + + out_be16((u16 *)FPGA_REG1C, + ~(endpoint | reset_off) & + (rootpoint | in_be16((u16 *)FPGA_REG1C))); + /* + * Leave device in reset for a while after powering on the + * slot to give it a chance to initialize. + */ + udelay(250 * 1000); + + out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C)); +} + + +static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; + +void pcie_setup_hoses(void) +{ + struct pci_controller *hose; + int i, bus; + + /* + * assume we're called after the PCIX hose is initialized, which takes + * bus ID 0 and therefore start numbering PCIe's from 1. + */ + bus = 1; + for (i = 0; i <= 2; i++) { + /* Check for yucca card presence */ + if (!yucca_pcie_card_present(i)) + continue; + + yucca_setup_pcie_fpga_rootpoint(i); + + if (ppc440spe_init_pcie_rootport(i)) { + printf("PCIE%d: initialization failed\n", i); + continue; + } + + hose = &pcie_hose[i]; + hose->first_busno = bus; + hose->last_busno = bus; + bus++; + + /* setup mem resource */ + pci_set_region(hose->regions + 0, + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, + CFG_PCIE_MEMSIZE, + PCI_REGION_MEM + ); + hose->region_count = 1; + pci_register_hose(hose); + + ppc440spe_setup_pcie(hose, i); + hose->last_busno = pci_hose_scan(hose); + } +} +#endif /* defined(CONFIG_PCI) */ + +int misc_init_f (void) +{ + uint reg; +#if defined(CONFIG_STRESS) + uint i ; + uint disp; +#endif + + out16(FPGA_REG10, (in16(FPGA_REG10) & + ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) | + FPGA_REG10_10MHZ_ENABLE | + FPGA_REG10_100MHZ_ENABLE | + FPGA_REG10_GIGABIT_ENABLE | + FPGA_REG10_FULL_DUPLEX ); + + udelay(10000); /* wait 10ms */ + + out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH)); + + /* minimal init for PCIe */ + /* pci express 0 Endpoint Mode */ + mfsdr(SDR0_PE0DLPSET, reg); + reg &= (~0x00400000); + mtsdr(SDR0_PE0DLPSET, reg); + /* pci express 1 Rootpoint Mode */ + mfsdr(SDR0_PE1DLPSET, reg); + reg |= 0x00400000; + mtsdr(SDR0_PE1DLPSET, reg); + /* pci express 2 Rootpoint Mode */ + mfsdr(SDR0_PE2DLPSET, reg); + reg |= 0x00400000; + mtsdr(SDR0_PE2DLPSET, reg); + + out16(FPGA_REG1C,(in16 (FPGA_REG1C) & + ~FPGA_REG1C_PE0_ROOTPOINT & + ~FPGA_REG1C_PE1_ENDPOINT & + ~FPGA_REG1C_PE2_ENDPOINT)); + +#if defined(CONFIG_STRESS) + /* + * all this setting done by linux only needed by stress an charac. test + * procedure + * PCIe 1 Rootpoint PCIe2 Endpoint + * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver + * Power Level + */ + for (i = 0, disp = 0; i < 8; i++, disp += 3) { + mfsdr(SDR0_PE0HSSSET1L0 + disp, reg); + reg |= 0x33000000; + mtsdr(SDR0_PE0HSSSET1L0 + disp, reg); + } + + /* + * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver + * Power Level + */ + for (i = 0, disp = 0; i < 4; i++, disp += 3) { + mfsdr(SDR0_PE1HSSSET1L0 + disp, reg); + reg |= 0x33000000; + mtsdr(SDR0_PE1HSSSET1L0 + disp, reg); + } + + /* + * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver + * Power Level + */ + for (i = 0, disp = 0; i < 4; i++, disp += 3) { + mfsdr(SDR0_PE2HSSSET1L0 + disp, reg); + reg |= 0x33000000; + mtsdr(SDR0_PE2HSSSET1L0 + disp, reg); + } + + reg = 0x21242222; + mtsdr(SDR0_PE2UTLSET1, reg); + reg = 0x11000000; + mtsdr(SDR0_PE2UTLSET2, reg); + /* pci express 1 Endpoint Mode */ + reg = 0x00004000; + mtsdr(SDR0_PE2DLPSET, reg); + + mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */ +#endif + return 0; +} + +void fpga_init(void) +{ + /* + * by default sdram access is disabled by fpga + */ + out16(FPGA_REG10, (in16 (FPGA_REG10) | + FPGA_REG10_SDRAM_ENABLE | + FPGA_REG10_ENABLE_DISPLAY )); + + return; +} + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return (ctrlc()); +} +#endif + +/*---------------------------------------------------------------------------+ + | onboard_pci_arbiter_selected => from EPLD + +---------------------------------------------------------------------------*/ +int onboard_pci_arbiter_selected(int core_pci) +{ +#if 0 + unsigned long onboard_pci_arbiter_sel; + + onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK; + + if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL) + return (BOARD_OPTION_SELECTED); + else +#endif + return (BOARD_OPTION_NOT_SELECTED); +} + +/*---------------------------------------------------------------------------+ + | ppcMfcpr. + +---------------------------------------------------------------------------*/ +unsigned long ppcMfcpr(unsigned long cpr_reg) +{ + unsigned long msr; + unsigned long cpr_cfgaddr_temp; + unsigned long cpr_value; + + msr = (mfmsr () & ~(MSR_EE)); + cpr_cfgaddr_temp = mfdcr(CPR0_CFGADDR); + mtdcr(CPR0_CFGADDR, cpr_reg); + cpr_value = mfdcr(CPR0_CFGDATA); + mtdcr(CPR0_CFGADDR, cpr_cfgaddr_temp); + mtmsr(msr); + + return (cpr_value); +} + +/*----------------------------------------------------------------------------+ +| Indirect Access of the System DCR's (SDR) +| ppcMfsdr ++----------------------------------------------------------------------------*/ +unsigned long ppcMfsdr(unsigned long sdr_reg) +{ + unsigned long msr; + unsigned long sdr_cfgaddr_temp; + unsigned long sdr_value; + + msr = (mfmsr () & ~(MSR_EE)); + sdr_cfgaddr_temp = mfdcr(SDR0_CFGADDR); + mtdcr(SDR0_CFGADDR, sdr_reg); + sdr_value = mfdcr(SDR0_CFGDATA); + mtdcr(SDR0_CFGADDR, sdr_cfgaddr_temp); + mtmsr(msr); + + return (sdr_value); +} diff --git a/board/amcc/yucca/yucca.h b/board/amcc/yucca/yucca.h new file mode 100644 index 0000000..66f7584 --- /dev/null +++ b/board/amcc/yucca/yucca.h @@ -0,0 +1,363 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __YUCCA_H_ +#define __YUCCA_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------------------------+ +| Defines ++----------------------------------------------------------------------------*/ + +#define TMR_FREQ_EXT 25000000 +#define BOARD_UART_CLOCK 11059200 + +#define BOARD_OPTION_SELECTED 1 +#define BOARD_OPTION_NOT_SELECTED 0 + +#define ENGINEERING_CLOCK_CHECKING "clk_chk" +#define ENGINEERING_EXTERNAL_CLOCK "ext_clk" + +#define ENGINEERING_CLOCK_CHECKING_DATA 1 +#define ENGINEERING_EXTERNAL_CLOCK_DATA 2 + +/* ethernet definition */ +#define MAX_ENETMODE_PARM 3 +#define ENETMODE_NEG 0 +#define ENETMODE_SPEED 1 +#define ENETMODE_DUPLEX 2 + +#define ENETMODE_AUTONEG 0 +#define ENETMODE_NO_AUTONEG 1 +#define ENETMODE_10 2 +#define ENETMODE_100 3 +#define ENETMODE_1000 4 +#define ENETMODE_HALF 5 +#define ENETMODE_FULL 6 + +#define NUM_TLB_ENTRIES 64 + +/*----------------------------------------------------------------------------+ +| TLB specific defines. ++----------------------------------------------------------------------------*/ +#define TLB_256MB_ALIGN_MASK 0xF0000000 +#define TLB_16MB_ALIGN_MASK 0xFF000000 +#define TLB_1MB_ALIGN_MASK 0xFFF00000 +#define TLB_256KB_ALIGN_MASK 0xFFFC0000 +#define TLB_64KB_ALIGN_MASK 0xFFFF0000 +#define TLB_16KB_ALIGN_MASK 0xFFFFC000 +#define TLB_4KB_ALIGN_MASK 0xFFFFF000 +#define TLB_1KB_ALIGN_MASK 0xFFFFFC00 +#define TLB_256MB_SIZE 0x10000000 +#define TLB_16MB_SIZE 0x01000000 +#define TLB_1MB_SIZE 0x00100000 +#define TLB_256KB_SIZE 0x00040000 +#define TLB_64KB_SIZE 0x00010000 +#define TLB_16KB_SIZE 0x00004000 +#define TLB_4KB_SIZE 0x00001000 +#define TLB_1KB_SIZE 0x00000400 + +#define TLB_WORD0_EPN_MASK 0xFFFFFC00 +#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00) +#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00) +#define TLB_WORD0_V_MASK 0x00000200 +#define TLB_WORD0_V_ENABLE 0x00000200 +#define TLB_WORD0_V_DISABLE 0x00000000 +#define TLB_WORD0_TS_MASK 0x00000100 +#define TLB_WORD0_TS_1 0x00000100 +#define TLB_WORD0_TS_0 0x00000000 +#define TLB_WORD0_SIZE_MASK 0x000000F0 +#define TLB_WORD0_SIZE_1KB 0x00000000 +#define TLB_WORD0_SIZE_4KB 0x00000010 +#define TLB_WORD0_SIZE_16KB 0x00000020 +#define TLB_WORD0_SIZE_64KB 0x00000030 +#define TLB_WORD0_SIZE_256KB 0x00000040 +#define TLB_WORD0_SIZE_1MB 0x00000050 +#define TLB_WORD0_SIZE_16MB 0x00000070 +#define TLB_WORD0_SIZE_256MB 0x00000090 +#define TLB_WORD0_TPAR_MASK 0x0000000F +#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0) +#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F) + +#define TLB_WORD1_RPN_MASK 0xFFFFFC00 +#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00) +#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00) +#define TLB_WORD1_PAR1_MASK 0x00000300 +#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) +#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03) +#define TLB_WORD1_PAR1_0 0x00000000 +#define TLB_WORD1_PAR1_1 0x00000100 +#define TLB_WORD1_PAR1_2 0x00000200 +#define TLB_WORD1_PAR1_3 0x00000300 +#define TLB_WORD1_ERPN_MASK 0x0000000F +#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0) +#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F) + +#define TLB_WORD2_PAR2_MASK 0xC0000000 +#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30) +#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03) +#define TLB_WORD2_PAR2_0 0x00000000 +#define TLB_WORD2_PAR2_1 0x40000000 +#define TLB_WORD2_PAR2_2 0x80000000 +#define TLB_WORD2_PAR2_3 0xC0000000 +#define TLB_WORD2_U0_MASK 0x00008000 +#define TLB_WORD2_U0_ENABLE 0x00008000 +#define TLB_WORD2_U0_DISABLE 0x00000000 +#define TLB_WORD2_U1_MASK 0x00004000 +#define TLB_WORD2_U1_ENABLE 0x00004000 +#define TLB_WORD2_U1_DISABLE 0x00000000 +#define TLB_WORD2_U2_MASK 0x00002000 +#define TLB_WORD2_U2_ENABLE 0x00002000 +#define TLB_WORD2_U2_DISABLE 0x00000000 +#define TLB_WORD2_U3_MASK 0x00001000 +#define TLB_WORD2_U3_ENABLE 0x00001000 +#define TLB_WORD2_U3_DISABLE 0x00000000 +#define TLB_WORD2_W_MASK 0x00000800 +#define TLB_WORD2_W_ENABLE 0x00000800 +#define TLB_WORD2_W_DISABLE 0x00000000 +#define TLB_WORD2_I_MASK 0x00000400 +#define TLB_WORD2_I_ENABLE 0x00000400 +#define TLB_WORD2_I_DISABLE 0x00000000 +#define TLB_WORD2_M_MASK 0x00000200 +#define TLB_WORD2_M_ENABLE 0x00000200 +#define TLB_WORD2_M_DISABLE 0x00000000 +#define TLB_WORD2_G_MASK 0x00000100 +#define TLB_WORD2_G_ENABLE 0x00000100 +#define TLB_WORD2_G_DISABLE 0x00000000 +#define TLB_WORD2_E_MASK 0x00000080 +#define TLB_WORD2_E_ENABLE 0x00000080 +#define TLB_WORD2_E_DISABLE 0x00000000 +#define TLB_WORD2_UX_MASK 0x00000020 +#define TLB_WORD2_UX_ENABLE 0x00000020 +#define TLB_WORD2_UX_DISABLE 0x00000000 +#define TLB_WORD2_UW_MASK 0x00000010 +#define TLB_WORD2_UW_ENABLE 0x00000010 +#define TLB_WORD2_UW_DISABLE 0x00000000 +#define TLB_WORD2_UR_MASK 0x00000008 +#define TLB_WORD2_UR_ENABLE 0x00000008 +#define TLB_WORD2_UR_DISABLE 0x00000000 +#define TLB_WORD2_SX_MASK 0x00000004 +#define TLB_WORD2_SX_ENABLE 0x00000004 +#define TLB_WORD2_SX_DISABLE 0x00000000 +#define TLB_WORD2_SW_MASK 0x00000002 +#define TLB_WORD2_SW_ENABLE 0x00000002 +#define TLB_WORD2_SW_DISABLE 0x00000000 +#define TLB_WORD2_SR_MASK 0x00000001 +#define TLB_WORD2_SR_ENABLE 0x00000001 +#define TLB_WORD2_SR_DISABLE 0x00000000 + +/*----------------------------------------------------------------------------+ +| Board specific defines. ++----------------------------------------------------------------------------*/ +#define NONCACHE_MEMORY_SIZE (64*1024) +#define NONCACHE_AREA0_ENDOFFSET (64*1024) +#define NONCACHE_AREA1_ENDOFFSET (32*1024) + +#define FLASH_SECTORSIZE 0x00010000 + +/* SDRAM MICRON */ +#define SDRAM_MICRON 0x2C + +#define SDRAM_TRUE 1 +#define SDRAM_FALSE 0 +#define SDRAM_DDR1 1 +#define SDRAM_DDR2 2 +#define SDRAM_NONE 0 +#define MAXDIMMS 2 /* Changes le 12/01/05 pour 1.6 */ +#define MAXRANKS 4 /* Changes le 12/01/05 pour 1.6 */ +#define MAXBANKSPERDIMM 2 +#define MAXRANKSPERDIMM 2 +#define MAXBXCF 4 /* Changes le 12/01/05 pour 1.6 */ +#define MAXSDRAMMEMORY 0xFFFFFFFF /* 4GB */ +#define ERROR_STR_LENGTH 256 +#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */ + +/*----------------------------------------------------------------------------+ +| SDR Configuration registers ++----------------------------------------------------------------------------*/ +/* Serial Device Strap Reg 0 */ +#define sdr_pstrp0 0x0040 + +#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00000080 /* EBC Boot bus width Mask */ +#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00000080 /* EBC 16 Bits */ +#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */ + +#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00080000 /* Boot device Selection Mask */ +#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */ +#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00080000 /* PCI */ + +#define SDR0_SDSTP1_EBC_SIZE_MASK 0x00000060 /* Boot rom size Mask */ +#define SDR0_SDSTP1_BOOT_SIZE_16MB 0x00000060 /* 16 MB */ +#define SDR0_SDSTP1_BOOT_SIZE_8MB 0x00000040 /* 8 MB */ +#define SDR0_SDSTP1_BOOT_SIZE_4MB 0x00000020 /* 4 MB */ +#define SDR0_SDSTP1_BOOT_SIZE_2MB 0x00000000 /* 2 MB */ + +/* Serial Device Enabled - Addr = 0xA8 */ +#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 +/* Serial Device Enabled - Addr = 0xA4 */ +#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 + +/* Pin Straps Reg */ +#define SDR0_PSTRP0 0x0040 +#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */ + +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */ + +/* fpgareg - defines are in include/config/YUCCA.h */ + +#define SDR0_CUST0_ENET3_MASK 0x00000080 +#define SDR0_CUST0_ENET3_COPPER 0x00000000 +#define SDR0_CUST0_ENET3_FIBER 0x00000080 +#define SDR0_CUST0_RGMII3_MASK 0x00000070 +#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4) +#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07) +#define SDR0_CUST0_RGMII3_DISAB 0x00000000 +#define SDR0_CUST0_RGMII3_RTBI 0x00000040 +#define SDR0_CUST0_RGMII3_RGMII 0x00000050 +#define SDR0_CUST0_RGMII3_TBI 0x00000060 +#define SDR0_CUST0_RGMII3_GMII 0x00000070 +#define SDR0_CUST0_ENET2_MASK 0x00000008 +#define SDR0_CUST0_ENET2_COPPER 0x00000000 +#define SDR0_CUST0_ENET2_FIBER 0x00000008 +#define SDR0_CUST0_RGMII2_MASK 0x00000007 +#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) +#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07) +#define SDR0_CUST0_RGMII2_DISAB 0x00000000 +#define SDR0_CUST0_RGMII2_RTBI 0x00000004 +#define SDR0_CUST0_RGMII2_RGMII 0x00000005 +#define SDR0_CUST0_RGMII2_TBI 0x00000006 +#define SDR0_CUST0_RGMII2_GMII 0x00000007 + +#define ONE_MILLION 1000000 +#define ONE_BILLION 1000000000 + +/*----------------------------------------------------------------------------+ +| X +| XX +| XX XXX XXXXX XX XXX XXXXX +| XX XX X XXX XX XX +| XX XX XXXXXX XX XX +| XX XX X XX XX XX XX +| XXX XX XXXXX X XXXX XXX ++----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------+ +| Declare Configuration values ++----------------------------------------------------------------------------*/ + +typedef enum config_selection { + CONFIG_NOT_SELECTED, + CONFIG_SELECTED +} config_selection_t; + +typedef enum config_list { + UART2_IN_SERVICE_MODE, + CPU_TRACE_MODE, + UART1_CTS_RTS, + CONFIG_NB +} config_list_t; + +#define MAX_CONFIG_SELECT_NB 3 + +#define BOARD_INFO_UART2_IN_SERVICE_MODE 1 +#define BOARD_INFO_CPU_TRACE_MODE 2 +#define BOARD_INFO_UART1_CTS_RTS_MODE 4 + +void force_bup_config_selection(config_selection_t *confgi_select_P); +void update_config_selection_table(config_selection_t *config_select_P); +void display_config_selection(config_selection_t *config_select_P); + +/*----------------------------------------------------------------------------+ +| XX +| +| XXXX XX XXX XXX XXXX +| XX XX XX XX XX XX +| XX XXX XX XX XX XX XX +| XX XX XXXXX XX XX XX +| XXXX XX XXXX XXXX +| XXXX +| +| +| +| +------------------------------------------------------------------+ +| | GPIO/Secondary func | Primary Function | I/O | Alternate1 | I/O | +| +----------------------+------------------+-----+------------+-----+ +| | | | | | | +| | GPIO0_0 | PCIX0REQ2_N | I/O | TRCCLK | | +| | GPIO0_1 | PCIX0REQ3_N | I/O | TRCBS0 | | +| | GPIO0_2 | PCIX0GNT2_N | I/O | TRCBS1 | | +| | GPIO0_3 | PCIX0GNT3_N | I/O | TRCBS2 | | +| | GPIO0_4 | PCIX1REQ2_N | I/O | TRCES0 | | +| | GPIO0_5 | PCIX1REQ3_N | I/O | TRCES1 | | +| | GPIO0_6 | PCIX1GNT2_N | I/O | TRCES2 | NA | +| | GPIO0_7 | PCIX1GNT3_N | I/O | TRCES3 | NA | +| | GPIO0_8 | PERREADY | I | TRCES4 | NA | +| | GPIO0_9 | PERCS1_N | O | TRCTS0 | NA | +| | GPIO0_10 | PERCS2_N | O | TRCTS1 | NA | +| | GPIO0_11 | IRQ0 | I | TRCTS2 | NA | +| | GPIO0_12 | IRQ1 | I | TRCTS3 | NA | +| | GPIO0_13 | IRQ2 | I | TRCTS4 | NA | +| | GPIO0_14 | IRQ3 | I | TRCTS5 | NA | +| | GPIO0_15 | IRQ4 | I | TRCTS6 | NA | +| | GPIO0_16 | IRQ5 | I | UART2RX | I | +| | GPIO0_17 | PERBE0_N | O | UART2TX | O | +| | GPIO0_18 | PCI0GNT0_N | I/O | NA | NA | +| | GPIO0_19 | PCI0GNT1_N | I/O | NA | NA | +| | GPIO0_20 | PCI0REQ0_N | I/O | NA | NA | +| | GPIO0_21 | PCI0REQ1_N | I/O | NA | NA | +| | GPIO0_22 | PCI1GNT0_N | I/O | NA | NA | +| | GPIO0_23 | PCI1GNT1_N | I/O | NA | NA | +| | GPIO0_24 | PCI1REQ0_N | I/O | NA | NA | +| | GPIO0_25 | PCI1REQ1_N | I/O | NA | NA | +| | GPIO0_26 | PCI2GNT0_N | I/O | NA | NA | +| | GPIO0_27 | PCI2GNT1_N | I/O | NA | NA | +| | GPIO0_28 | PCI2REQ0_N | I/O | NA | NA | +| | GPIO0_29 | PCI2REQ1_N | I/O | NA | NA | +| | GPIO0_30 | UART1RX | I | NA | NA | +| | GPIO0_31 | UART1TX | O | NA | NA | +| | | | | | | +| +----------------------+------------------+-----+------------+-----+ +| ++----------------------------------------------------------------------------*/ + +unsigned long auto_calc_speed(void); +/*----------------------------------------------------------------------------+ +| Prototypes ++----------------------------------------------------------------------------*/ +void print_evb440spe_info(void); + +int onboard_pci_arbiter_selected(int core_pci); + +#ifdef __cplusplus +} +#endif +#endif /* __YUCCA_H_ */ diff --git a/board/atc/Makefile b/board/atc/Makefile index 7a2014d..7573a0c 100644 --- a/board/atc/Makefile +++ b/board/atc/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o ti113x.o $(LIB): .depend $(OBJS) $(AR) crv $@ $(OBJS) diff --git a/board/atc/ti113x.c b/board/atc/ti113x.c new file mode 100644 index 0000000..d5e935c --- /dev/null +++ b/board/atc/ti113x.c @@ -0,0 +1,637 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * + * Lots of code copied from: + * + * i82365.c 1.352 - Linux driver for Intel 82365 and compatible + * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers. + * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net> + */ + +#include <common.h> + +#ifdef CONFIG_I82365 + +#include <command.h> +#include <pci.h> +#include <pcmcia.h> +#include <asm/io.h> + +#include <pcmcia/ss.h> +#include <pcmcia/i82365.h> +#include <pcmcia/yenta.h> +#include <pcmcia/ti113x.h> + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510}, + {0, 0} +}; + +#define CYCLE_TIME 120 + +#ifdef DEBUG +static void i82365_dump_regions (pci_dev_t dev); +#endif + +typedef struct socket_info_t { + pci_dev_t dev; + u_short bcr; + u_char pci_lat, cb_lat, sub_bus, cache; + u_int cb_phys; + + socket_cap_t cap; + u_short type; + u_int flags; + ti113x_state_t state; +} socket_info_t; + +static socket_info_t socket; +static socket_state_t state; +static struct pccard_mem_map mem; +static struct pccard_io_map io; + +/*====================================================================*/ + +/* Some PCI shortcuts */ + +static int pci_readb (socket_info_t * s, int r, u_char * v) +{ + return pci_read_config_byte (s->dev, r, v); +} +static int pci_writeb (socket_info_t * s, int r, u_char v) +{ + return pci_write_config_byte (s->dev, r, v); +} +static int pci_readw (socket_info_t * s, int r, u_short * v) +{ + return pci_read_config_word (s->dev, r, v); +} +static int pci_writew (socket_info_t * s, int r, u_short v) +{ + return pci_write_config_word (s->dev, r, v); +} +static int pci_readl (socket_info_t * s, int r, u_int * v) +{ + return pci_read_config_dword (s->dev, r, v); +} +static int pci_writel (socket_info_t * s, int r, u_int v) +{ + return pci_write_config_dword (s->dev, r, v); +} + +/*====================================================================*/ + +#define cb_readb(s, r) readb((s)->cb_phys + (r)) +#define cb_readl(s, r) readl((s)->cb_phys + (r)) +#define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r)) +#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r)) + +static u_char i365_get (socket_info_t * s, u_short reg) +{ + return cb_readb (s, 0x0800 + reg); +} + +static void i365_set (socket_info_t * s, u_short reg, u_char data) +{ + cb_writeb (s, 0x0800 + reg, data); +} + +static void i365_bset (socket_info_t * s, u_short reg, u_char mask) +{ + i365_set (s, reg, i365_get (s, reg) | mask); +} + +static void i365_bclr (socket_info_t * s, u_short reg, u_char mask) +{ + i365_set (s, reg, i365_get (s, reg) & ~mask); +} + +#if 0 /* not used */ +static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b) +{ + u_char d = i365_get (s, reg); + + i365_set (s, reg, (b) ? (d | mask) : (d & ~mask)); +} + +static u_short i365_get_pair (socket_info_t * s, u_short reg) +{ + return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8)); +} +#endif /* not used */ + +static void i365_set_pair (socket_info_t * s, u_short reg, u_short data) +{ + i365_set (s, reg, data & 0xff); + i365_set (s, reg + 1, data >> 8); +} + +/*====================================================================== + + Code to save and restore global state information for TI 1130 and + TI 1131 controllers, and to set and report global configuration + options. + +======================================================================*/ + +static void ti113x_get_state (socket_info_t * s) +{ + ti113x_state_t *p = &s->state; + + pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl); + pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl); + pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl); + pci_readb (s, TI1250_DIAGNOSTIC, &p->diag); + pci_readl (s, TI12XX_IRQMUX, &p->irqmux); +} + +static void ti113x_set_state (socket_info_t * s) +{ + ti113x_state_t *p = &s->state; + + pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl); + pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl); + pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl); + pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0); + pci_writeb (s, TI1250_DIAGNOSTIC, p->diag); + pci_writel (s, TI12XX_IRQMUX, p->irqmux); + i365_set_pair (s, TI113X_IO_OFFSET (0), 0); + i365_set_pair (s, TI113X_IO_OFFSET (1), 0); +} + +static u_int ti113x_set_opts (socket_info_t * s) +{ + ti113x_state_t *p = &s->state; + u_int mask = 0xffff; + + p->cardctl &= ~TI113X_CCR_ZVENABLE; + p->cardctl |= TI113X_CCR_SPKROUTEN; + + return mask; +} + +/*====================================================================== + + Routines to handle common CardBus options + +======================================================================*/ + +/* Default settings for PCI command configuration register */ +#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \ + PCI_COMMAND_MASTER|PCI_COMMAND_WAIT) + +static void cb_get_state (socket_info_t * s) +{ + pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache); + pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat); + pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat); + pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus); + pci_readb (s, CB_SUBORD_BUS, &s->sub_bus); + pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr); +} + +static void cb_set_state (socket_info_t * s) +{ + pci_writel (s, CB_LEGACY_MODE_BASE, 0); + pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys); + pci_writew (s, PCI_COMMAND, CMD_DFLT); + pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache); + pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat); + pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat); + pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus); + pci_writeb (s, CB_SUBORD_BUS, s->sub_bus); + pci_writew (s, CB_BRIDGE_CONTROL, s->bcr); +} + +static void cb_set_opts (socket_info_t * s) +{ + if (s->cache == 0) + s->cache = 8; + if (s->pci_lat == 0) + s->pci_lat = 0xa8; + if (s->cb_lat == 0) + s->cb_lat = 0xb0; +} + +/*====================================================================== + + Power control for Cardbus controllers: used both for 16-bit and + Cardbus cards. + +======================================================================*/ + +static int cb_set_power (socket_info_t * s, socket_state_t * state) +{ + u_int reg = 0; + + /* restart card voltage detection if it seems appropriate */ + if ((state->Vcc == 0) && (state->Vpp == 0) && + !(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE)) + cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST); + switch (state->Vcc) { + case 0: + reg = 0; + break; + case 33: + reg = CB_SC_VCC_3V; + break; + case 50: + reg = CB_SC_VCC_5V; + break; + default: + return -1; + } + switch (state->Vpp) { + case 0: + break; + case 33: + reg |= CB_SC_VPP_3V; + break; + case 50: + reg |= CB_SC_VPP_5V; + break; + case 120: + reg |= CB_SC_VPP_12V; + break; + default: + return -1; + } + if (reg != cb_readl (s, CB_SOCKET_CONTROL)) + cb_writel (s, CB_SOCKET_CONTROL, reg); + + return 0; +} + +/*====================================================================== + + Generic routines to get and set controller options + +======================================================================*/ + +static void get_bridge_state (socket_info_t * s) +{ + ti113x_get_state (s); + cb_get_state (s); +} + +static void set_bridge_state (socket_info_t * s) +{ + cb_set_state (s); + i365_set (s, I365_GBLCTL, 0x00); + i365_set (s, I365_GENCTL, 0x00); + ti113x_set_state (s); +} + +static void set_bridge_opts (socket_info_t * s) +{ + ti113x_set_opts (s); + cb_set_opts (s); +} + +/*====================================================================*/ +#define PD67_EXT_INDEX 0x2e /* Extension index */ +#define PD67_EXT_DATA 0x2f /* Extension data */ +#define PD67_EXD_VS1(s) (0x01 << ((s)<<1)) + +#define pd67_ext_get(s, r) \ + (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA)) + +static int i365_get_status (socket_info_t * s, u_int * value) +{ + u_int status; + + status = i365_get (s, I365_IDENT); + status = i365_get (s, I365_STATUS); + *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0; + if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) { + *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG; + } else { + *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD; + *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN; + } + *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0; + *value |= (status & I365_CS_READY) ? SS_READY : 0; + *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0; + + status = cb_readl (s, CB_SOCKET_STATE); + *value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0; + *value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0; + *value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0; + *value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING; + /* For now, ignore cards with unsupported voltage keys */ + if (*value & SS_XVCARD) + *value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD); + + return 0; +} /* i365_get_status */ + +static int i365_set_socket (socket_info_t * s, socket_state_t * state) +{ + u_char reg; + + set_bridge_state (s); + + /* IO card, RESET flag */ + reg = 0; + reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET; + reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0; + i365_set (s, I365_INTCTL, reg); + + reg = I365_PWR_NORESET; + if (state->flags & SS_PWR_AUTO) + reg |= I365_PWR_AUTO; + if (state->flags & SS_OUTPUT_ENA) + reg |= I365_PWR_OUT; + + cb_set_power (s, state); + reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK); + + if (reg != i365_get (s, I365_POWER)) + i365_set (s, I365_POWER, reg); + + return 0; +} /* i365_set_socket */ + +/*====================================================================*/ + +static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem) +{ + u_short base, i; + u_char map; + + debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n", + mem->map, mem->flags, mem->speed, + mem->sys_start, mem->sys_stop, mem->card_start); + + map = mem->map; + if ((map > 4) || + (mem->card_start > 0x3ffffff) || + (mem->sys_start > mem->sys_stop) || + (mem->speed > 1000)) { + return -1; + } + + /* Turn off the window before changing anything */ + if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map)) + i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map)); + + /* Take care of high byte, for PCI controllers */ + i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24); + + base = I365_MEM (map); + i = (mem->sys_start >> 12) & 0x0fff; + if (mem->flags & MAP_16BIT) + i |= I365_MEM_16BIT; + if (mem->flags & MAP_0WS) + i |= I365_MEM_0WS; + i365_set_pair (s, base + I365_W_START, i); + + i = (mem->sys_stop >> 12) & 0x0fff; + switch (mem->speed / CYCLE_TIME) { + case 0: + break; + case 1: + i |= I365_MEM_WS0; + break; + case 2: + i |= I365_MEM_WS1; + break; + default: + i |= I365_MEM_WS1 | I365_MEM_WS0; + break; + } + i365_set_pair (s, base + I365_W_STOP, i); + + i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff; + if (mem->flags & MAP_WRPROT) + i |= I365_MEM_WRPROT; + if (mem->flags & MAP_ATTRIB) + i |= I365_MEM_REG; + i365_set_pair (s, base + I365_W_OFF, i); + + /* Turn on the window if necessary */ + if (mem->flags & MAP_ACTIVE) + i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map)); + return 0; +} /* i365_set_mem_map */ + +static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io) +{ + u_char map, ioctl; + + map = io->map; + /* comment out: comparison is always false due to limited range of data type */ + if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */ + (io->stop < io->start)) + return -1; + /* Turn off the window before changing anything */ + if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map)) + i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map)); + i365_set_pair (s, I365_IO (map) + I365_W_START, io->start); + i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop); + ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map); + if (io->speed) + ioctl |= I365_IOCTL_WAIT (map); + if (io->flags & MAP_0WS) + ioctl |= I365_IOCTL_0WS (map); + if (io->flags & MAP_16BIT) + ioctl |= I365_IOCTL_16BIT (map); + if (io->flags & MAP_AUTOSZ) + ioctl |= I365_IOCTL_IOCS16 (map); + i365_set (s, I365_IOCTL, ioctl); + /* Turn on the window if necessary */ + if (io->flags & MAP_ACTIVE) + i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map)); + return 0; +} /* i365_set_io_map */ + +/*====================================================================*/ + +int i82365_init (void) +{ + u_int val; + int i; + + if ((socket.dev = pci_find_devices (supported, 0)) < 0) { + /* Controller not found */ + return 1; + } + debug ("i82365 Device Found!\n"); + + pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys); + socket.cb_phys &= ~0xf; + + get_bridge_state (&socket); + set_bridge_opts (&socket); + + i = i365_get_status (&socket, &val); + + if (val & SS_DETECT) { + if (val & SS_3VCARD) { + state.Vcc = state.Vpp = 33; + puts (" 3.3V card found: "); + } else if (!(val & SS_XVCARD)) { + state.Vcc = state.Vpp = 50; + puts (" 5.0V card found: "); + } else { + puts ("i82365: unsupported voltage key\n"); + state.Vcc = state.Vpp = 0; + } + } else { + /* No card inserted */ + puts ("No card\n"); + return 1; + } + + state.flags = SS_IOCARD | SS_OUTPUT_ENA; + state.csc_mask = 0; + state.io_irq = 0; + + i365_set_socket (&socket, &state); + + for (i = 500; i; i--) { + if ((i365_get (&socket, I365_STATUS) & I365_CS_READY)) + break; + udelay (1000); + } + + if (i == 0) { + /* PC Card not ready for data transfer */ + puts ("i82365 PC Card not ready for data transfer\n"); + return 1; + } + debug (" PC Card ready for data transfer: "); + + mem.map = 0; + mem.flags = MAP_ATTRIB | MAP_ACTIVE; + mem.speed = 300; + mem.sys_start = CFG_PCMCIA_MEM_ADDR; + mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1; + mem.card_start = 0; + i365_set_mem_map (&socket, &mem); + + io.map = 0; + io.flags = MAP_AUTOSZ | MAP_ACTIVE; + io.speed = 0; + io.start = 0x0100; + io.stop = 0x010F; + i365_set_io_map (&socket, &io); + +#ifdef DEBUG + i82365_dump_regions (socket.dev); +#endif + + return 0; +} + +void i82365_exit (void) +{ + io.map = 0; + io.flags = 0; + io.speed = 0; + io.start = 0; + io.stop = 0x1; + + i365_set_io_map (&socket, &io); + + mem.map = 0; + mem.flags = 0; + mem.speed = 0; + mem.sys_start = 0; + mem.sys_stop = 0x1000; + mem.card_start = 0; + + i365_set_mem_map (&socket, &mem); + + socket.state.sysctl &= 0xFFFF00FF; + + state.Vcc = state.Vpp = 0; + + i365_set_socket (&socket, &state); +} + +int pcmcia_on (void) +{ + u_int rc; + + debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); + + rc = i82365_init(); + if (rc) + goto exit; + + rc = check_ide_device(0); + if (rc == 0) + goto exit; + + i82365_exit(); + +exit: + return rc; +} + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +int pcmcia_off (void) +{ + printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n"); + + i82365_exit(); + + return 0; +} +#endif + +/*====================================================================== + + Debug stuff + +======================================================================*/ + +#ifdef DEBUG +static void i82365_dump_regions (pci_dev_t dev) +{ + u_int tmp[2]; + u_int *mem = (void *) socket.cb_phys; + u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR; + u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET); + + pci_read_config_dword (dev, 0x00, tmp + 0); + pci_read_config_dword (dev, 0x80, tmp + 1); + + printf ("PCI CONF: %08X ... %08X\n", + tmp[0], tmp[1]); + printf ("PCI MEM: ... %08X ... %08X\n", + mem[0x8 / 4], mem[0x800 / 4]); + printf ("CIS: ...%c%c%c%c%c%c%c%c...\n", + cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e], + cis[0x40], cis[0x42], cis[0x44], cis[0x48]); + printf ("CIS CONF: %02X %02X %02X ...\n", + cis[0x200], cis[0x202], cis[0x204]); + printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n", + ide[0], ide[1], ide[2], ide[3], + ide[4], ide[5], ide[6], ide[7]); +} +#endif /* DEBUG */ + +#endif /* CONFIG_I82365 */ diff --git a/board/c2mon/Makefile b/board/c2mon/Makefile index 7a2014d..7b2b545 100644 --- a/board/c2mon/Makefile +++ b/board/c2mon/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o pcmcia.o $(LIB): .depend $(OBJS) $(AR) crv $@ $(OBJS) diff --git a/board/c2mon/pcmcia.c b/board/c2mon/pcmcia.c new file mode 100644 index 0000000..5e50c4d --- /dev/null +++ b/board/c2mon/pcmcia.c @@ -0,0 +1,284 @@ +#include <common.h> +#include <mpc8xx.h> +#include <pcmcia.h> + +#undef CONFIG_PCMCIA + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#define CONFIG_PCMCIA +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#define CONFIG_PCMCIA +#endif + +#ifdef CONFIG_PCMCIA + +#define PCMCIA_BOARD_MSG "C2MON" + +static void cfg_ports (void) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + ushort sreg; + + immap = (immap_t *)CFG_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* + * Configure Port C for TPS2211 PC-Card Power-Interface Switch + * + * Switch off all voltages, assert shutdown + */ + sreg = immap->im_ioport.iop_pcdat; + sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1); /* VAVPP => Hi-Z */ + sreg &= ~(TPS2211_VCCD0 | TPS2211_VCCD1); /* 3V and 5V off */ + immap->im_ioport.iop_pcdat = sreg; + + immap->im_ioport.iop_pcpar &= ~(TPS2211_OUTPUTS); + immap->im_ioport.iop_pcdir |= TPS2211_OUTPUTS; + + debug ("Set Port C: PAR: %04x DIR: %04x DAT: %04x\n", + immap->im_ioport.iop_pcpar, + immap->im_ioport.iop_pcdir, + immap->im_ioport.iop_pcdat); + + /* + * Configure Port B for TPS2211 PC-Card Power-Interface Switch + * + * Over-Current Input only + */ + cp->cp_pbpar &= ~(TPS2211_INPUTS); + cp->cp_pbdir &= ~(TPS2211_INPUTS); + + debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n", + cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat); +} + +int pcmcia_hardware_enable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, pipr, mask; + ushort sreg; + int i; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + udelay(10000); + + immap = (immap_t *)CFG_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ + cfg_ports (); + + /* + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ + sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); + pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { + printf (" No Card found\n"); + return (1); + } + + /* + * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z + */ + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + pipr = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + pipr, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); + + sreg = immap->im_ioport.iop_pcdat; + if ((pipr & mask) == mask) { + sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1 | /* VAVPP => Hi-Z */ + TPS2211_VCCD1); /* 5V on */ + sreg &= ~(TPS2211_VCCD0); /* 3V off */ + puts (" 5.0V card found: "); + } else { + sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1 | /* VAVPP => Hi-Z */ + TPS2211_VCCD0); /* 3V on */ + sreg &= ~(TPS2211_VCCD1); /* 5V off */ + puts (" 3.3V card found: "); + } + + debug ("\nPC DAT: %04x -> 3.3V %s 5.0V %s\n", + sreg, + ( (sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) ? "on" : "off", + (!(sreg & TPS2211_VCCD0) && (sreg & TPS2211_VCCD1)) ? "on" : "off" + ); + + immap->im_ioport.iop_pcdat = sreg; + + /* Wait 500 ms; use this to check for over-current */ + for (i=0; i<5000; ++i) { + if ((cp->cp_pbdat & TPS2211_OC) == 0) { + printf (" *** Overcurrent - Safety shutdown ***\n"); + immap->im_ioport.iop_pcdat &= ~(TPS2211_VCCD0|TPS2211_VCCD1); + return (1); + } + udelay (100); + } + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +int pcmcia_hardware_disable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + + /* Configure PCMCIA General Control Register */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + /* ALl voltages off / Hi-Z */ + immap->im_ioport.iop_pcdat |= (TPS2211_VPPD0 | TPS2211_VPPD1 | + TPS2211_VCCD0 | TPS2211_VCCD1 ); + + udelay(10000); + + return (0); +} +#endif /* CFG_CMD_PCMCIA */ + + +int pcmcia_voltage_set(int slot, int vcc, int vpp) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + ushort sreg; + + debug ("voltage_set: " + PCMCIA_BOARD_MSG + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + immap = (immap_t *)CFG_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Configure Port C pins for + * 5 Volts Enable and 3 Volts enable, + * Turn all power pins to Hi-Z + */ + debug ("PCMCIA power OFF\n"); + cfg_ports (); /* Enables switch, but all in Hi-Z */ + + sreg = immap->im_ioport.iop_pcdat; + sreg |= TPS2211_VPPD0 | TPS2211_VPPD1; /* VAVPP always Hi-Z */ + + switch(vcc) { + case 0: break; /* Switch off */ + case 33: sreg |= TPS2211_VCCD0; /* Switch on 3.3V */ + sreg &= ~TPS2211_VCCD1; + break; + case 50: sreg &= ~TPS2211_VCCD0; /* Switch on 5.0V */ + sreg |= TPS2211_VCCD1; + break; + default: goto done; + } + + /* Checking supported voltages */ + + debug ("PIPR: 0x%x --> %s\n", + pcmp->pcmc_pipr, + (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); + + immap->im_ioport.iop_pcdat = sreg; + +#ifdef DEBUG +{ + char *s; + + if ((sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) { + s = "at 3.3V"; + } else if (!(sreg & TPS2211_VCCD0) && (sreg & TPS2211_VCCD1)) { + s = "at 5.0V"; + } else { + s = "down"; + } + printf ("PCMCIA powered %s\n", s); +} +#endif + +done: + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", + slot+'A'); + return (0); +} + +#endif /* CONFIG_PCMCIA */ diff --git a/board/cpc45/pd67290.c b/board/cpc45/pd67290.c index c84fbae..6ca3e7b 100644 --- a/board/cpc45/pd67290.c +++ b/board/cpc45/pd67290.c @@ -1,4 +1,6 @@ -/* pd67290.c - system configuration module for SPD67290 +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this * project. @@ -18,51 +20,799 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA * - * (C) 2004 DENX Software Engineering, Heiko Schocher <hs@denx.de> + ******************************************************************** + * + * Lots of code copied from: + * + * i82365.c 1.352 - Linux driver for Intel 82365 and compatible + * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers. + * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net> */ #include <common.h> -#include <malloc.h> -#include <net.h> -#include <asm/io.h> + +#ifdef CONFIG_I82365 + +#include <command.h> #include <pci.h> +#include <pcmcia.h> +#include <asm/io.h> -/* imports */ -#include <mpc824x.h> +#include <pcmcia/ss.h> +#include <pcmcia/i82365.h> +#include <pcmcia/yenta.h> +#include <pcmcia/cirrus.h> static struct pci_device_id supported[] = { {PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729}, - {} + {0, 0} +}; + +#define CYCLE_TIME 120 + +#ifdef DEBUG +static void i82365_dump_regions (pci_dev_t dev); +#endif + +typedef struct socket_info_t { + pci_dev_t dev; + u_short bcr; + u_char pci_lat, cb_lat, sub_bus, cache; + u_int cb_phys; + + socket_cap_t cap; + u_short type; + u_int flags; + cirrus_state_t c_state; +} socket_info_t; + +/* These definitions must match the pcic table! */ +typedef enum pcic_id { + IS_PD6710, IS_PD672X, IS_VT83C469 +} pcic_id; + +typedef struct pcic_t { + char *name; +} pcic_t; + +static pcic_t pcic[] = { + {" Cirrus PD6710: "}, + {" Cirrus PD672x: "}, + {" VIA VT83C469: "}, }; -/*************************************************************************** -* -* SPD67290Init - -* -* RETURNS: -1 on error, 0 if OK -*/ +static socket_info_t socket; +static socket_state_t state; +static struct pccard_mem_map mem; +static struct pccard_io_map io; -int SPD67290Init (void) +/*====================================================================*/ + +/* Some PCI shortcuts */ + +static int pci_readb (socket_info_t * s, int r, u_char * v) +{ + return pci_read_config_byte (s->dev, r, v); +} +static int pci_writeb (socket_info_t * s, int r, u_char v) +{ + return pci_write_config_byte (s->dev, r, v); +} +static int pci_readw (socket_info_t * s, int r, u_short * v) +{ + return pci_read_config_word (s->dev, r, v); +} +static int pci_writew (socket_info_t * s, int r, u_short v) { - pci_dev_t devno; - int idx = 0; /* general index */ - ulong membaseCsr; /* base address of device memory space */ + return pci_write_config_word (s->dev, r, v); +} - /* find PD67290 device */ - if ((devno = pci_find_devices (supported, idx++)) < 0) { - printf ("No PD67290 device found !!\n"); +/*====================================================================*/ + +#define cb_readb(s) readb((s)->cb_phys + 1) +#define cb_writeb(s, v) writeb(v, (s)->cb_phys) +#define cb_writeb2(s, v) writeb(v, (s)->cb_phys + 1) +#define cb_readl(s, r) readl((s)->cb_phys + (r)) +#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r)) + + +static u_char i365_get (socket_info_t * s, u_short reg) +{ + u_char val; +#ifdef CONFIG_PCMCIA_SLOT_A + int slot = 0; +#else + int slot = 1; +#endif + + val = I365_REG (slot, reg); + + cb_writeb (s, val); + val = cb_readb (s); + + debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val); + return val; +} + +static void i365_set (socket_info_t * s, u_short reg, u_char data) +{ +#ifdef CONFIG_PCMCIA_SLOT_A + int slot = 0; +#else + int slot = 1; +#endif + u_char val; + + val = I365_REG (slot, reg); + + cb_writeb (s, val); + cb_writeb2 (s, data); + + debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data); +} + +static void i365_bset (socket_info_t * s, u_short reg, u_char mask) +{ + i365_set (s, reg, i365_get (s, reg) | mask); +} + +static void i365_bclr (socket_info_t * s, u_short reg, u_char mask) +{ + i365_set (s, reg, i365_get (s, reg) & ~mask); +} + +#if 0 /* not used */ +static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b) +{ + u_char d = i365_get (s, reg); + + i365_set (s, reg, (b) ? (d | mask) : (d & ~mask)); +} + +static u_short i365_get_pair (socket_info_t * s, u_short reg) +{ + return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8)); +} +#endif /* not used */ + +static void i365_set_pair (socket_info_t * s, u_short reg, u_short data) +{ + i365_set (s, reg, data & 0xff); + i365_set (s, reg + 1, data >> 8); +} + +/*====================================================================== + + Code to save and restore global state information for Cirrus + PD67xx controllers, and to set and report global configuration + options. + +======================================================================*/ + +#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b)))) + +static void cirrus_get_state (socket_info_t * s) +{ + int i; + cirrus_state_t *p = &s->c_state; + + p->misc1 = i365_get (s, PD67_MISC_CTL_1); + p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA); + p->misc2 = i365_get (s, PD67_MISC_CTL_2); + for (i = 0; i < 6; i++) + p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i); + +} + +static void cirrus_set_state (socket_info_t * s) +{ + int i; + u_char misc; + cirrus_state_t *p = &s->c_state; + + misc = i365_get (s, PD67_MISC_CTL_2); + i365_set (s, PD67_MISC_CTL_2, p->misc2); + if (misc & PD67_MC2_SUSPEND) + udelay (50000); + misc = i365_get (s, PD67_MISC_CTL_1); + misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA); + i365_set (s, PD67_MISC_CTL_1, misc | p->misc1); + for (i = 0; i < 6; i++) + i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]); +} + +static u_int cirrus_set_opts (socket_info_t * s) +{ + cirrus_state_t *p = &s->c_state; + u_int mask = 0xffff; +#if DEBUG + char buf[200]; + + memset (buf, 0, 200); +#endif + + if (has_ring == -1) + has_ring = 1; + flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring); + flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode); +#if DEBUG + if (p->misc2 & PD67_MC2_IRQ15_RI) + strcat (buf, " [ring]"); + if (p->misc2 & PD67_MC2_DYNAMIC_MODE) + strcat (buf, " [dyn mode]"); + if (p->misc1 & PD67_MC1_INPACK_ENA) + strcat (buf, " [inpack]"); +#endif + + if (p->misc2 & PD67_MC2_IRQ15_RI) + mask &= ~0x8000; + if (has_led > 0) { +#if DEBUG + strcat (buf, " [led]"); +#endif + mask &= ~0x1000; + } + if (has_dma > 0) { +#if DEBUG + strcat (buf, " [dma]"); +#endif + mask &= ~0x0600; + flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass); +#if DEBUG + if (p->misc2 & PD67_MC2_FREQ_BYPASS) + strcat (buf, " [freq bypass]"); +#endif + } + + if (setup_time >= 0) + p->timer[0] = p->timer[3] = setup_time; + if (cmd_time > 0) { + p->timer[1] = cmd_time; + p->timer[4] = cmd_time * 2 + 4; + } + if (p->timer[1] == 0) { + p->timer[1] = 6; + p->timer[4] = 16; + if (p->timer[0] == 0) + p->timer[0] = p->timer[3] = 1; + } + if (recov_time >= 0) + p->timer[2] = p->timer[5] = recov_time; + + debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n", + buf, + p->timer[0], p->timer[1], p->timer[2], + p->timer[3], p->timer[4], p->timer[5]); + + return mask; +} + +/*====================================================================== + + Routines to handle common CardBus options + +======================================================================*/ + +/* Default settings for PCI command configuration register */ +#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \ + PCI_COMMAND_MASTER|PCI_COMMAND_WAIT) + +static void cb_get_state (socket_info_t * s) +{ + pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache); + pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat); + pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat); + pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus); + pci_readb (s, CB_SUBORD_BUS, &s->sub_bus); + pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr); +} + +static void cb_set_state (socket_info_t * s) +{ + pci_writew (s, PCI_COMMAND, CMD_DFLT); + pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache); + pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat); + pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat); + pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus); + pci_writeb (s, CB_SUBORD_BUS, s->sub_bus); + pci_writew (s, CB_BRIDGE_CONTROL, s->bcr); +} + +static void cb_set_opts (socket_info_t * s) +{ +} + +/*====================================================================== + + Power control for Cardbus controllers: used both for 16-bit and + Cardbus cards. + +======================================================================*/ + +static int cb_set_power (socket_info_t * s, socket_state_t * state) +{ + u_int reg = 0; + + reg = I365_PWR_NORESET; + if (state->flags & SS_PWR_AUTO) + reg |= I365_PWR_AUTO; + if (state->flags & SS_OUTPUT_ENA) + reg |= I365_PWR_OUT; + if (state->Vpp != 0) { + if (state->Vpp == 120) { + reg |= I365_VPP1_12V; + puts (" 12V card found: "); + } else if (state->Vpp == state->Vcc) { + reg |= I365_VPP1_5V; + } else { + puts (" power not found: "); + return -1; + } + } + if (state->Vcc != 0) { + reg |= I365_VCC_5V; + if (state->Vcc == 33) { + puts (" 3.3V card found: "); + i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); + } else if (state->Vcc == 50) { + puts (" 5V card found: "); + i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); + } else { + puts (" power not found: "); + return -1; + } + } + + if (reg != i365_get (s, I365_POWER)) { + reg = (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V); + i365_set (s, I365_POWER, reg); + } + + return 0; +} + +/*====================================================================== + + Generic routines to get and set controller options + +======================================================================*/ + +static void get_bridge_state (socket_info_t * s) +{ + cirrus_get_state (s); + cb_get_state (s); +} + +static void set_bridge_state (socket_info_t * s) +{ + cb_set_state (s); + i365_set (s, I365_GBLCTL, 0x00); + i365_set (s, I365_GENCTL, 0x00); + cirrus_set_state (s); +} + +static void set_bridge_opts (socket_info_t * s) +{ + cirrus_set_opts (s); + cb_set_opts (s); +} + +/*====================================================================*/ +#define PD67_EXT_INDEX 0x2e /* Extension index */ +#define PD67_EXT_DATA 0x2f /* Extension data */ +#define PD67_EXD_VS1(s) (0x01 << ((s)<<1)) + +#define pd67_ext_get(s, r) \ + (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA)) + +static int i365_get_status (socket_info_t * s, u_int * value) +{ + u_int status; + u_char val; + u_char power, vcc, vpp; + u_int powerstate; + + status = i365_get (s, I365_IDENT); + status = i365_get (s, I365_STATUS); + *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0; + if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) { + *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG; + } else { + *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD; + *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN; + } + *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0; + *value |= (status & I365_CS_READY) ? SS_READY : 0; + *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0; + + /* Check for Cirrus CL-PD67xx chips */ + i365_set (s, PD67_CHIP_INFO, 0); + val = i365_get (s, PD67_CHIP_INFO); + s->type = -1; + if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) { + val = i365_get (s, PD67_CHIP_INFO); + if ((val & PD67_INFO_CHIP_ID) == 0) { + s->type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710; + i365_set (s, PD67_EXT_INDEX, 0xe5); + if (i365_get (s, PD67_EXT_INDEX) != 0xe5) + s->type = IS_VT83C469; + } + } else { + printf ("no Cirrus Chip found\n"); + *value = 0; return -1; } - /* - 0xfe000000 see MPC 8245 Users Manual Adress Map B */ - membaseCsr = PCMCIA_IO_BASE - 0xfe000000; + + power = i365_get (s, I365_POWER); + state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0; + state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0; + vcc = power & I365_VCC_MASK; + vpp = power & I365_VPP1_MASK; + state.Vcc = state.Vpp = 0; + if((vcc== 0) || (vpp == 0)) { + /* + * On the Cirrus we get the info which card voltage + * we have in EXTERN DATA and write it to MISC_CTL1 + */ + powerstate = pd67_ext_get(s, PD67_EXTERN_DATA); + if (powerstate & PD67_EXD_VS1(0)) { + /* 5V Card */ + i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); + } else { + /* 3.3V Card */ + i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); + } + i365_set (s, I365_POWER, (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V)); + power = i365_get (s, I365_POWER); + } + if (power & I365_VCC_5V) { + state.Vcc = (i365_get(s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) ? 33 : 50; + } + + if (power == I365_VPP1_12V) + state.Vpp = 120; + + /* IO card, RESET flags, IO interrupt */ + power = i365_get (s, I365_INTCTL); + state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET; + if (power & I365_PC_IOCARD) + state.flags |= SS_IOCARD; + state.io_irq = power & I365_IRQ_MASK; + + /* Card status change mask */ + power = i365_get (s, I365_CSCINT); + state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0; + if (state.flags & SS_IOCARD) + state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0; + else { + state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0; + state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0; + state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0; + } + debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, " + "io_irq %d, csc_mask %#2.2x\n", state.flags, + state.Vcc, state.Vpp, state.io_irq, state.csc_mask); + + return 0; +} /* i365_get_status */ + +static int i365_set_socket (socket_info_t * s, socket_state_t * state) +{ + u_char reg; + + set_bridge_state (s); + + /* IO card, RESET flag */ + reg = 0; + reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET; + reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0; + i365_set (s, I365_INTCTL, reg); + + cb_set_power (s, state); + +#if 0 + /* Card status change interrupt mask */ + reg = s->cs_irq << 4; + if (state->csc_mask & SS_DETECT) + reg |= I365_CSC_DETECT; + if (state->flags & SS_IOCARD) { + if (state->csc_mask & SS_STSCHG) + reg |= I365_CSC_STSCHG; + } else { + if (state->csc_mask & SS_BATDEAD) + reg |= I365_CSC_BVD1; + if (state->csc_mask & SS_BATWARN) + reg |= I365_CSC_BVD2; + if (state->csc_mask & SS_READY) + reg |= I365_CSC_READY; + } + i365_set (s, I365_CSCINT, reg); + i365_get (s, I365_CSC); +#endif /* 0 */ + + return 0; +} /* i365_set_socket */ + +/*====================================================================*/ + +static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem) +{ + u_short base, i; + u_char map; + + debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n", + mem->map, mem->flags, mem->speed, + mem->sys_start, mem->sys_stop, mem->card_start); + + map = mem->map; + if ((map > 4) || + (mem->card_start > 0x3ffffff) || + (mem->sys_start > mem->sys_stop) || + (mem->speed > 1000)) { + return -1; + } + + /* Turn off the window before changing anything */ + if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map)) + i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map)); + + /* Take care of high byte, for PCI controllers */ + i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24); + + base = I365_MEM (map); + i = (mem->sys_start >> 12) & 0x0fff; + if (mem->flags & MAP_16BIT) + i |= I365_MEM_16BIT; + if (mem->flags & MAP_0WS) + i |= I365_MEM_0WS; + i365_set_pair (s, base + I365_W_START, i); + + i = (mem->sys_stop >> 12) & 0x0fff; + switch (mem->speed / CYCLE_TIME) { + case 0: + break; + case 1: + i |= I365_MEM_WS0; + break; + case 2: + i |= I365_MEM_WS1; + break; + default: + i |= I365_MEM_WS1 | I365_MEM_WS0; + break; + } + i365_set_pair (s, base + I365_W_STOP, i); + + i = 0; + if (mem->flags & MAP_WRPROT) + i |= I365_MEM_WRPROT; + if (mem->flags & MAP_ATTRIB) + i |= I365_MEM_REG; + i365_set_pair (s, base + I365_W_OFF, i); + + /* set System Memory map Upper Adress */ + i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map)); + i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff)); + + /* Turn on the window if necessary */ + if (mem->flags & MAP_ACTIVE) + i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map)); + return 0; +} /* i365_set_mem_map */ + +static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io) +{ + u_char map, ioctl; + + map = io->map; + /* comment out: comparison is always false due to limited range of data type */ + if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */ + (io->stop < io->start)) + return -1; + /* Turn off the window before changing anything */ + if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map)) + i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map)); + i365_set_pair (s, I365_IO (map) + I365_W_START, io->start); + i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop); + ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map); + if (io->speed) + ioctl |= I365_IOCTL_WAIT (map); + if (io->flags & MAP_0WS) + ioctl |= I365_IOCTL_0WS (map); + if (io->flags & MAP_16BIT) + ioctl |= I365_IOCTL_16BIT (map); + if (io->flags & MAP_AUTOSZ) + ioctl |= I365_IOCTL_IOCS16 (map); + i365_set (s, I365_IOCTL, ioctl); + /* Turn on the window if necessary */ + if (io->flags & MAP_ACTIVE) + i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map)); + return 0; +} /* i365_set_io_map */ + +/*====================================================================*/ + +/* + * PCI_ADDR = (HOST_ADDR - 0xfe000000) + * see MPC 8245 Users Manual Adress Map B + */ +#define HOST_TO_PCI(addr) ((addr) - 0xfe000000) +#define PCI_TO_HOST(addr) ((addr) + 0xfe000000) + +int i82365_init (void) +{ + u_int val; + int i; + + if ((socket.dev = pci_find_devices (supported, 0)) < 0) { + /* Controller not found */ + printf ("No PD67290 device found !!\n"); + return 1; + } + debug ("i82365 Device Found!\n"); + + socket.cb_phys = PCMCIA_IO_BASE; /* set base address */ - pci_write_config_dword (devno, PCI_BASE_ADDRESS_0, membaseCsr); + pci_write_config_dword (socket.dev, PCI_BASE_ADDRESS_0, + HOST_TO_PCI(socket.cb_phys)); /* enable mapped memory and IO addresses */ - pci_write_config_dword (devno, + pci_write_config_dword (socket.dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_WAIT); + + get_bridge_state (&socket); + set_bridge_opts (&socket); + + i = i365_get_status (&socket, &val); + + if (i > -1) { + puts (pcic[socket.type].name); + } else { + printf ("i82365: Controller not found.\n"); + return 1; + } + if((val & SS_DETECT) != SS_DETECT){ + puts ("No card\n"); + return 1; + } + + state.flags |= SS_OUTPUT_ENA; + + i365_set_socket (&socket, &state); + + for (i = 500; i; i--) { + if ((i365_get (&socket, I365_STATUS) & I365_CS_READY)) + break; + udelay (1000); + } + + if (i == 0) { + /* PC Card not ready for data transfer */ + puts ("i82365 PC Card not ready for data transfer\n"); + return 1; + } + debug (" PC Card ready for data transfer: "); + + mem.map = 0; + mem.flags = MAP_ATTRIB | MAP_ACTIVE; + mem.speed = 300; + mem.sys_start = CFG_PCMCIA_MEM_ADDR; + mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1; + mem.card_start = 0; + i365_set_mem_map (&socket, &mem); + + mem.map = 1; + mem.flags = MAP_ACTIVE; + mem.speed = 300; + mem.sys_start = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE; + mem.sys_stop = CFG_PCMCIA_MEM_ADDR + (2 * CFG_PCMCIA_MEM_SIZE) - 1; + mem.card_start = 0; + i365_set_mem_map (&socket, &mem); + +#ifdef DEBUG + i82365_dump_regions (socket.dev); +#endif + return 0; } + +void i82365_exit (void) +{ + io.map = 0; + io.flags = 0; + io.speed = 0; + io.start = 0; + io.stop = 0x1; + + i365_set_io_map (&socket, &io); + + mem.map = 0; + mem.flags = 0; + mem.speed = 0; + mem.sys_start = 0; + mem.sys_stop = 0x1000; + mem.card_start = 0; + + i365_set_mem_map (&socket, &mem); + + mem.map = 1; + mem.flags = 0; + mem.speed = 0; + mem.sys_start = 0; + mem.sys_stop = 0x1000; + mem.card_start = 0; + + i365_set_mem_map (&socket, &mem); + + state.Vcc = state.Vpp = 0; + + i365_set_socket (&socket, &state); +} + +int pcmcia_on (void) +{ + u_int rc; + + debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); + + rc = i82365_init(); + if (rc) + goto exit; + + rc = check_ide_device(0); + if (rc == 0) + goto exit; + + i82365_exit(); + +exit: + return rc; +} + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +int pcmcia_off (void) +{ + printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n"); + + i82365_exit(); + + return 0; +} +#endif + +/*====================================================================== + + Debug stuff + +======================================================================*/ + +#ifdef DEBUG +static void i82365_dump_regions (pci_dev_t dev) +{ + u_int tmp[2]; + u_int *mem = (void *) socket.cb_phys; + u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR; + u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET); + + pci_read_config_dword (dev, 0x00, tmp + 0); + pci_read_config_dword (dev, 0x80, tmp + 1); + + printf ("PCI CONF: %08X ... %08X\n", + tmp[0], tmp[1]); + printf ("PCI MEM: ... %08X ... %08X\n", + mem[0x8 / 4], mem[0x800 / 4]); + printf ("CIS: ...%c%c%c%c%c%c%c%c...\n", + cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e], + cis[0x40], cis[0x42], cis[0x44], cis[0x48]); + printf ("CIS CONF: %02X %02X %02X ...\n", + cis[0x200], cis[0x202], cis[0x204]); + printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n", + ide[0], ide[1], ide[2], ide[3], + ide[4], ide[5], ide[6], ide[7]); +} +#endif /* DEBUG */ + +#endif /* CONFIG_I82365 */ diff --git a/board/cpu87/cpu87.c b/board/cpu87/cpu87.c index 8363d86..e8c2614 100644 --- a/board/cpu87/cpu87.c +++ b/board/cpu87/cpu87.c @@ -197,7 +197,7 @@ const iop_conf_t iop_conf_tab[4][32] = { */ int checkboard (void) { - printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV); + printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV & 0x7f); return 0; } @@ -280,7 +280,7 @@ long int initdram (int board_type) volatile memctl8260_t *memctl = &immap->im_memctl; #ifndef CFG_RAMBOOT - ulong size8, size9; + ulong size8, size9, size10; #endif long psize; @@ -294,17 +294,25 @@ long int initdram (int board_type) */ size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, (uchar *) CFG_SDRAM_BASE); + size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, (uchar *) CFG_SDRAM_BASE); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL) "); - } else { + + size10 = try_init (memctl, CFG_PSDMR_10COL, CFG_OR2_10COL, + (uchar *) CFG_SDRAM_BASE); + + psize = max(size8,max(size9,size10)); + + if (psize == size8) { psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, (uchar *) CFG_SDRAM_BASE); printf ("(60x:8COL) "); - } + } else if (psize == size9){ + psize = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, + (uchar *) CFG_SDRAM_BASE); + printf ("(60x:9COL) "); + } else + printf ("(60x:10COL) "); #endif /* CFG_RAMBOOT */ diff --git a/board/etin/kvme080/Makefile b/board/etin/kvme080/Makefile new file mode 100644 index 0000000..303ccfa --- /dev/null +++ b/board/etin/kvme080/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o multiverse.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/etin/kvme080/config.mk b/board/etin/kvme080/config.mk new file mode 100644 index 0000000..45abdc0 --- /dev/null +++ b/board/etin/kvme080/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2005 +# Sangmoon, Etin Systems, dogoil@etinsys.com. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# KVME080 board +# + +TEXT_BASE = 0xFFF00000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/etin/kvme080/kvme080.c b/board/etin/kvme080/kvme080.c new file mode 100644 index 0000000..de62fa0 --- /dev/null +++ b/board/etin/kvme080/kvme080.c @@ -0,0 +1,193 @@ +/* + * (C) Copyright 2005 + * Sangmoon Kim, Etin Systems. dogoil@etinsys.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc824x.h> +#include <pci.h> +#include <i2c.h> +#include <asm/processor.h> + +int checkboard(void) +{ + puts ("Board: KVME080\n"); + return 0; +} + +unsigned long setdram(int m, int row, int col, int bank) +{ + int i; + unsigned long start, end; + uint32_t mccr1; + uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0; + uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0; + uint8_t mber = 0; + + CONFIG_READ_WORD(MCCR1, mccr1); + mccr1 &= 0xffff0000; + + start = CFG_SDRAM_BASE; + end = start + (1 << (col + row + 3) ) * bank - 1; + + for (i = 0; i < m; i++) { + mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2; + if (i < 4) { + msar1 |= ((start >> 20) & 0xff) << i * 8; + emsar1 |= ((start >> 28) & 0xff) << i * 8; + mear1 |= ((end >> 20) & 0xff) << i * 8; + emear1 |= ((end >> 28) & 0xff) << i * 8; + } else { + msar2 |= ((start >> 20) & 0xff) << (i-4) * 8; + emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8; + mear2 |= ((end >> 20) & 0xff) << (i-4) * 8; + emear2 |= ((end >> 28) & 0xff) << (i-4) * 8; + } + mber |= 1 << i; + start += (1 << (col + row + 3) ) * bank; + end += (1 << (col + row + 3) ) * bank; + } + for (; i < 8; i++) { + if (i < 4) { + msar1 |= 0xff << i * 8; + emsar1 |= 0x30 << i * 8; + mear1 |= 0xff << i * 8; + emear1 |= 0x30 << i * 8; + } else { + msar2 |= 0xff << (i-4) * 8; + emsar2 |= 0x30 << (i-4) * 8; + mear2 |= 0xff << (i-4) * 8; + emear2 |= 0x30 << (i-4) * 8; + } + } + + CONFIG_WRITE_WORD(MCCR1, mccr1); + CONFIG_WRITE_WORD(MSAR1, msar1); + CONFIG_WRITE_WORD(EMSAR1, emsar1); + CONFIG_WRITE_WORD(MEAR1, mear1); + CONFIG_WRITE_WORD(EMEAR1, emear1); + CONFIG_WRITE_WORD(MSAR2, msar2); + CONFIG_WRITE_WORD(EMSAR2, emsar2); + CONFIG_WRITE_WORD(MEAR2, mear2); + CONFIG_WRITE_WORD(EMEAR2, emear2); + CONFIG_WRITE_BYTE(MBER, mber); + + return (1 << (col + row + 3) ) * bank * m; +} + +long int initdram(int board_type) +{ + unsigned int msr; + long int size = 0; + + msr = mfmsr(); + mtmsr(msr & ~(MSR_IR | MSR_DR)); + mtspr(IBAT2L, CFG_IBAT0L + 0x10000000); + mtspr(IBAT2U, CFG_IBAT0U + 0x10000000); + mtspr(DBAT2L, CFG_DBAT0L + 0x10000000); + mtspr(DBAT2U, CFG_DBAT0U + 0x10000000); + mtmsr(msr); + + if (setdram(2,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x20000000)) + size = 0x20000000; /* 512MB */ + else if (setdram(1,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000)) + size = 0x10000000; /* 256MB */ + else if (setdram(2,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000)) + size = 0x10000000; /* 256MB */ + else if (setdram(1,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000)) + size = 0x08000000; /* 128MB */ + else if (setdram(2,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000)) + size = 0x08000000; /* 128MB */ + else if (setdram(1,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x04000000)) + size = 0x04000000; /* 64MB */ + + msr = mfmsr(); + mtmsr(msr & ~(MSR_IR | MSR_DR)); + mtspr(IBAT2L, CFG_IBAT2L); + mtspr(IBAT2U, CFG_IBAT2U); + mtspr(DBAT2L, CFG_DBAT2L); + mtspr(DBAT2U, CFG_DBAT2U); + mtmsr(msr); + + return size; +} + +struct pci_controller hose; + +void pci_init_board(void) +{ + pci_mpc824x_init(&hose); +} + +int board_early_init_f(void) +{ + *(volatile unsigned char *)(0xff080120) = 0xfb; + + return 0; +} + +int board_early_init_r(void) +{ + unsigned int msr; + + CONFIG_WRITE_WORD(ERCR1, 0x95ff8000); + CONFIG_WRITE_WORD(ERCR3, 0x0c00000e); + CONFIG_WRITE_WORD(ERCR4, 0x0800000e); + + msr = mfmsr(); + mtmsr(msr & ~(MSR_IR | MSR_DR)); + mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT); + mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP); + mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT); + mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP); + mtmsr(msr); + + return 0; +} + +extern int multiverse_init(void); + +int misc_init_r(void) +{ + multiverse_init(); + return 0; +} + +void *nvram_read(void *dest, const long src, size_t count) +{ + volatile uchar *d = (volatile uchar*) dest; + volatile uchar *s = (volatile uchar*) src; + while(count--) { + *d++ = *s++; + asm volatile("sync"); + } + return dest; +} + +void nvram_write(long dest, const void *src, size_t count) +{ + volatile uchar *d = (volatile uchar*)dest; + volatile uchar *s = (volatile uchar*)src; + while(count--) { + *d++ = *s++; + asm volatile("sync"); + } +} diff --git a/board/etin/kvme080/multiverse.c b/board/etin/kvme080/multiverse.c new file mode 100644 index 0000000..eb89581 --- /dev/null +++ b/board/etin/kvme080/multiverse.c @@ -0,0 +1,186 @@ +/* + * multiverse.c + * + * VME driver for Multiverse + * + * Author : Sangmoon Kim + * dogoil@etinsys.com + * + * Copyright 2005 ETIN SYSTEMS Co.,Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <common.h> +#include <asm/io.h> +#include <pci.h> + +#include "multiverse.h" + +static unsigned long vme_asi_addr; +static unsigned long vme_iack_addr; +static unsigned long pci_reg_addr; +static unsigned long vme_reg_addr; + +int multiv_reset(unsigned long base) +{ + writeb(0x09, base + VME_SLAVE32_AM); + writeb(0x39, base + VME_SLAVE24_AM); + writeb(0x29, base + VME_SLAVE16_AM); + writeb(0x2f, base + VME_SLAVE_REG_AM); + writeb((VME_A32_SLV_BUS >> 24) & 0xff, base + VME_SLAVE32_A); + writeb((VME_A24_SLV_BUS >> 16) & 0xff, base + VME_SLAVE24_A); + writeb((VME_A16_SLV_BUS >> 8 ) & 0xff, base + VME_SLAVE16_A); +#ifdef A32_SLV_WINDOW + if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) { + writeb(((~(VME_A32_SLV_SIZE-1)) >> 24) & 0xff, + base + VME_SLAVE32_MASK); + writeb(0x01, base + VME_SLAVE32_EN); + } else { + writeb(0xff, base + VME_SLAVE32_MASK); + writeb(0x00, base + VME_SLAVE32_EN); + } +#else + writeb(0xff, base + VME_SLAVE32_MASK); + writeb(0x00, base + VME_SLAVE32_EN); +#endif +#ifdef A24_SLV_WINDOW + if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) { + writeb(((~(VME_A24_SLV_SIZE-1)) >> 16) & 0xff, + base + VME_SLAVE24_MASK); + writeb(0x01, base + VME_SLAVE24_EN); + } else { + writeb(0xff, base + VME_SLAVE24_MASK); + writeb(0x00, base + VME_SLAVE24_EN); + } +#else + writeb(0xff, base + VME_SLAVE24_MASK); + writeb(0x00, base + VME_SLAVE24_EN); +#endif +#ifdef A16_SLV_WINDOW + if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) { + writeb(((~(VME_A16_SLV_SIZE-1)) >> 8) & 0xff, + base + VME_SLAVE16_MASK); + writeb(0x01, base + VME_SLAVE16_EN); + } else { + writeb(0xff, base + VME_SLAVE16_MASK); + writeb(0x00, base + VME_SLAVE16_EN); + } +#else + writeb(0xff, base + VME_SLAVE16_MASK); + writeb(0x00, base + VME_SLAVE16_EN); +#endif +#ifdef REG_SLV_WINDOW + if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) { + writeb(((~(VME_REG_SLV_SIZE-1)) >> 16) & 0xff, + base + VME_SLAVE_REG_MASK); + writeb(0x01, base + VME_SLAVE_REG_EN); + } else { + writeb(0xf8, base + VME_SLAVE_REG_MASK); + } +#else + writeb(0xf8, base + VME_SLAVE_REG_MASK); +#endif + writeb(0x09, base + VME_MASTER32_AM); + writeb(0x39, base + VME_MASTER24_AM); + writeb(0x29, base + VME_MASTER16_AM); + writeb(0x2f, base + VME_MASTER_REG_AM); + writel(0x00000000, base + VME_RMW_ADRS); + writeb(0x00, base + VME_IRQ); + writeb(0x00, base + VME_INT_EN); + writel(0x00000000, base + VME_IRQ1_REG); + writel(0x00000000, base + VME_IRQ2_REG); + writel(0x00000000, base + VME_IRQ3_REG); + writel(0x00000000, base + VME_IRQ4_REG); + writel(0x00000000, base + VME_IRQ5_REG); + writel(0x00000000, base + VME_IRQ6_REG); + writel(0x00000000, base + VME_IRQ7_REG); + return 0; +} + +void multiv_auto_slot_id(unsigned long base) +{ + unsigned int vector; + int slot_id = 1; + if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) { + *(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe; + writeb(readb(base + VME_IRQ) | 0x04, base + VME_IRQ); + writeb(readb(base + VME_CTRL) & ~VME_CTRL_SYSFAIL, + base + VME_CTRL); + while (readb(base + VME_STATUS) & VME_STATUS_SYSFAIL); + if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) { + while (readb(base + VME_INT) & 0x04) { + vector = *(volatile unsigned int*) + (vme_iack_addr + VME_IACK2); + *(unsigned char*)(vme_asi_addr + 0x7ffff) + = (slot_id << 3) & 0xff; + slot_id ++; + if (slot_id > 31) + break; + } + } + } +} + +int multiverse_init(void) +{ + int i; + pci_dev_t pdev; + unsigned int bar[6]; + + pdev = pci_find_device(0x1895, 0x0001, 0); + + if (pdev == 0) + return -1; + + for (i = 0; i < 6; i++) + pci_read_config_dword (pdev, + PCI_BASE_ADDRESS_0 + i * 4, &bar[i]); + + pci_reg_addr = bar[0]; + vme_reg_addr = bar[1] + 0x00F00000; + vme_iack_addr = bar[1] + 0x00200000; + vme_asi_addr = bar[3]; + + pci_write_config_dword (pdev, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + writel(0xFF000000, pci_reg_addr + P_TA1); + writel(0x04, pci_reg_addr + P_IMG_CTRL1); + writel(0xf0000000, pci_reg_addr + P_TA2); + writel(0x04, pci_reg_addr + P_IMG_CTRL2); + writel(0xF1000000, pci_reg_addr + P_TA3); + writel(0x04, pci_reg_addr + P_IMG_CTRL3); + writel(VME_A32_MSTR_BUS, pci_reg_addr + P_TA5); + writel(~(VME_A32_MSTR_SIZE-1), pci_reg_addr + P_AM5); + writel(0x04, pci_reg_addr + P_IMG_CTRL5); + + writel(VME_A32_SLV_BUS, pci_reg_addr + W_BA1); + writel(~(VME_A32_SLV_SIZE-1), pci_reg_addr + W_AM1); + writel(VME_A32_SLV_LOCAL, pci_reg_addr + W_TA1); + writel(0x04, pci_reg_addr + W_IMG_CTRL1); + + writel(0xF0000000, pci_reg_addr + W_BA2); + writel(0xFF000000, pci_reg_addr + W_AM2); + writel(VME_A24_SLV_LOCAL, pci_reg_addr + W_TA2); + writel(0x04, pci_reg_addr + W_IMG_CTRL2); + + writel(0xFF000000, pci_reg_addr + W_BA3); + writel(0xFF000000, pci_reg_addr + W_AM3); + writel(VME_A16_SLV_LOCAL, pci_reg_addr + W_TA3); + writel(0x04, pci_reg_addr + W_IMG_CTRL3); + + writel(0x00000001, pci_reg_addr + W_ERR_CS); + writel(0x00000001, pci_reg_addr + P_ERR_CS); + + multiv_reset(vme_reg_addr); + writeb(readb(vme_reg_addr + VME_CTRL) | VME_CTRL_SHORT_D, + vme_reg_addr + VME_CTRL); + + multiv_auto_slot_id(vme_reg_addr); + + return 0; +} diff --git a/board/etin/kvme080/multiverse.h b/board/etin/kvme080/multiverse.h new file mode 100644 index 0000000..776162d --- /dev/null +++ b/board/etin/kvme080/multiverse.h @@ -0,0 +1,176 @@ +/* + * multiverse.h + * + * VME driver for Multiverse + * + * Author : Sangmoon Kim + * dogoil@etinsys.com + * + * Copyright 2005 ETIN SYSTEMS Co.,Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MULTIVERSE_H__ +#define __MULTIVERSE_H__ + +#define VME_A32_MSTR_BUS 0x90000000 +#define VME_A32_MSTR_SIZE 0x01000000 + +#define VME_A32_SLV_SIZE 0x01000000 + +#define VME_A32_SLV_BUS 0x90000000 +#define VME_A24_SLV_BUS 0x00000000 +#define VME_A16_SLV_BUS 0x00000000 + +#define VME_A32_SLV_LOCAL 0x00000000 +#define VME_A24_SLV_LOCAL 0x00000000 +#define VME_A16_SLV_LOCAL 0x00000000 + +#define A32_SLV_WINDOW +#undef A24_SLV_WINDOW +#undef A16_SLV_WINDOW +#undef REG_SLV_WINDOW + +/* PCI Registers */ + +#define P_IMG_CTRL0 0x100 +#define P_BA0 0x104 +#define P_AM0 0x108 +#define P_TA0 0x10C +#define P_IMG_CTRL1 0x110 +#define P_BA1 0x114 +#define P_AM1 0x118 +#define P_TA1 0x11C +#define P_IMG_CTRL2 0x120 +#define P_BA2 0x124 +#define P_AM2 0x128 +#define P_TA2 0x12C +#define P_IMG_CTRL3 0x130 +#define P_BA3 0x134 +#define P_AM3 0x138 +#define P_TA3 0x13C +#define P_IMG_CTRL4 0x140 +#define P_BA4 0x144 +#define P_AM4 0x148 +#define P_TA4 0x14C +#define P_IMG_CTRL5 0x150 +#define P_BA5 0x154 +#define P_AM5 0x158 +#define P_TA5 0x15C +#define P_ERR_CS 0x160 +#define P_ERR_ADDR 0x164 +#define P_ERR_DATA 0x168 + +#define WB_CONF_SPC_BAR 0x180 +#define W_IMG_CTRL1 0x184 +#define W_BA1 0x188 +#define W_AM1 0x18C +#define W_TA1 0x190 +#define W_IMG_CTRL2 0x194 +#define W_BA2 0x198 +#define W_AM2 0x19C +#define W_TA2 0x1A0 +#define W_IMG_CTRL3 0x1A4 +#define W_BA3 0x1A8 +#define W_AM3 0x1AC +#define W_TA3 0x1B0 +#define W_IMG_CTRL4 0x1B4 +#define W_BA4 0x1B8 +#define W_AM4 0x1BC +#define W_TA4 0x1C0 +#define W_IMG_CTRL5 0x1C4 +#define W_BA5 0x1C8 +#define W_AM5 0x1CC +#define W_TA5 0x1D0 +#define W_ERR_CS 0x1D4 +#define W_ERR_ADDR 0x1D8 +#define W_ERR_DATA 0x1DC +#define CNF_ADDR 0x1E0 +#define CNF_DATA 0x1E4 +#define INT_ACK 0x1E8 +#define ICR 0x1EC +#define ISR 0x1F0 + +/* VME registers */ + +#define VME_SLAVE32_AM 0x03 +#define VME_SLAVE24_AM 0x02 +#define VME_SLAVE16_AM 0x01 +#define VME_SLAVE_REG_AM 0x00 +#define VME_SLAVE32_A 0x07 +#define VME_SLAVE24_A 0x06 +#define VME_SLAVE16_A 0x05 +#define VME_SLAVE_REG_A 0x04 +#define VME_SLAVE32_MASK 0x0B +#define VME_SLAVE24_MASK 0x0A +#define VME_SLAVE16_MASK 0x09 +#define VME_SLAVE_REG_MASK 0x08 +#define VME_SLAVE32_EN 0x0F +#define VME_SLAVE24_EN 0x0E +#define VME_SLAVE16_EN 0x0D +#define VME_SLAVE_REG_EN 0x0C +#define VME_MASTER32_AM 0x13 +#define VME_MASTER24_AM 0x12 +#define VME_MASTER16_AM 0x11 +#define VME_MASTER_REG_AM 0x10 +#define VME_RMW_ADRS 0x14 +#define VME_MBOX 0x18 +#define VME_STATUS 0x1E +#define VME_CTRL 0x1C +#define VME_IRQ 0x20 +#define VME_INT_EN 0x21 +#define VME_INT 0x22 +#define VME_IRQ1_REG 0x24 +#define VME_IRQ2_REG 0x28 +#define VME_IRQ3_REG 0x2C +#define VME_IRQ4_REG 0x30 +#define VME_IRQ5_REG 0x34 +#define VME_IRQ6_REG 0x38 +#define VME_IRQ7_REG 0x3C + +/* VME control register */ + +#define VME_CTRL_BRDRST 0x01 +#define VME_CTRL_SYSRST 0x02 +#define VME_CTRL_RMW 0x04 +#define VME_CTRL_SHORT_D 0x08 +#define VME_CTRL_SYSFAIL 0x10 +#define VME_CTRL_VOWN 0x20 +#define VME_CTRL_A16_REG_MODE 0x40 + +/* VME status register */ + +#define VME_STATUS_SYSCON 0x01 +#define VME_STATUS_SYSFAIL 0x02 +#define VME_STATUS_ACFAIL 0x04 +#define VME_STATUS_SYSRST 0x08 +#define VME_STATUS_VOWN 0x10 + +/* Interrupt types */ + +#define LVL1 0x0002 +#define LVL2 0x0004 +#define LVL3 0x0008 +#define LVL4 0x0010 +#define LVL5 0x0020 +#define LVL6 0x0040 +#define LVL7 0x0080 +#define MULTIVERSE_INTI_INT 0x0100 +#define MULTIVERSE_WB_INT 0x0200 +#define MULTIVERSE_PCI_INT 0x0400 + +/* interrupt acknowledge */ + +#define VME_IACK1 0x04 +#define VME_IACK2 0x08 +#define VME_IACK3 0x0c +#define VME_IACK4 0x10 +#define VME_IACK5 0x14 +#define VME_IACK6 0x18 +#define VME_IACK7 0x1c + +#endif /* __MULTIVERSE_H__ */ diff --git a/board/etin/kvme080/u-boot.lds b/board/etin/kvme080/u-boot.lds new file mode 100644 index 0000000..dda3687 --- /dev/null +++ b/board/etin/kvme080/u-boot.lds @@ -0,0 +1,128 @@ +/* + * (C) Copyright 2001-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/fads/Makefile b/board/fads/Makefile index baa6c2e..7fc88ee 100644 --- a/board/fads/Makefile +++ b/board/fads/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o lamp.o +OBJS = $(BOARD).o flash.o lamp.o pcmcia.o $(LIB): .depend $(OBJS) $(AR) crv $@ $(OBJS) diff --git a/board/fads/fads.h b/board/fads/fads.h index e981be0..41f18b5 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -467,7 +467,9 @@ #define CONFIG_ISO_PARTITION 1 #undef CONFIG_ATAPI +#if 0 /* does not make sense when CFG_CMD_IDE is not enabled, too */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ +#endif #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ #undef CONFIG_IDE_LED /* LED for ide not supported */ #undef CONFIG_IDE_RESET /* reset for ide not supported */ diff --git a/board/fads/pcmcia.c b/board/fads/pcmcia.c new file mode 100644 index 0000000..978c16b --- /dev/null +++ b/board/fads/pcmcia.c @@ -0,0 +1,84 @@ +#include <common.h> +#include <mpc8xx.h> +#include <pcmcia.h> + +#undef CONFIG_PCMCIA + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#define CONFIG_PCMCIA +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#define CONFIG_PCMCIA +#endif + +#ifdef CONFIG_PCMCIA + +#ifdef CONFIG_ADS +#define PCMCIA_BOARD_MSG "ADS" +#else +#define PCMCIA_BOARD_MSG "FADS" +#endif + +int pcmcia_voltage_set(int slot, int vcc, int vpp) +{ + u_long reg = 0; + + switch(vpp) { + case 0: reg = 0; break; + case 50: reg = 1; break; + case 120: reg = 2; break; + default: return 1; + } + + switch(vcc) { + case 0: reg = 0; break; +#ifdef CONFIG_ADS + case 50: reg = BCSR1_PCCVCCON; break; +#endif +#ifdef CONFIG_FADS + case 33: reg = BCSR1_PCCVCC0 | BCSR1_PCCVCC1; break; + case 50: reg = BCSR1_PCCVCC1; break; +#endif + default: return 1; + } + + /* first, turn off all power */ + +#ifdef CONFIG_ADS + *((uint *)BCSR1) |= BCSR1_PCCVCCON; +#endif +#ifdef CONFIG_FADS + *((uint *)BCSR1) &= ~(BCSR1_PCCVCC0 | BCSR1_PCCVCC1); +#endif + *((uint *)BCSR1) &= ~BCSR1_PCCVPP_MASK; + + /* enable new powersettings */ + +#ifdef CONFIG_ADS + *((uint *)BCSR1) &= ~reg; +#endif +#ifdef CONFIG_FADS + *((uint *)BCSR1) |= reg; +#endif + + *((uint *)BCSR1) |= reg << 20; + + return 0; +} + +int pcmcia_hardware_enable(int slot) +{ + *((uint *)BCSR1) &= ~BCSR1_PCCEN; + return 0; +} + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +int pcmcia_hardware_disable(int slot) +{ + *((uint *)BCSR1) &= ~BCSR1_PCCEN; + return 0; +} +#endif /* CFG_CMD_PCMCIA */ + +#endif /* CONFIG_PCMCIA */ diff --git a/board/gth/Makefile b/board/gth/Makefile index e14c12e..48f74cd 100644 --- a/board/gth/Makefile +++ b/board/gth/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o ee_access.o +OBJS = $(BOARD).o flash.o ee_access.o pcmcia.o $(LIB): .depend $(OBJS) $(AR) crv $@ $(OBJS) diff --git a/board/gth/pcmcia.c b/board/gth/pcmcia.c new file mode 100644 index 0000000..fce5492 --- /dev/null +++ b/board/gth/pcmcia.c @@ -0,0 +1,93 @@ +#include <common.h> +#include <mpc8xx.h> +#include <pcmcia.h> + +#undef CONFIG_PCMCIA + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#define CONFIG_PCMCIA +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#define CONFIG_PCMCIA +#endif + +#ifdef CONFIG_PCMCIA + +#define PCMCIA_BOARD_MSG "GTH COMPACT FLASH" + +int pcmcia_voltage_set (int slot, int vcc, int vpp) +{ /* Do nothing */ + return 0; +} + +int pcmcia_hardware_enable (int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, mask; + + debug ("hardware_enable: GTH Slot %c\n", 'A' + slot); + + immap = (immap_t *) CFG_IMMR; + sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm)); + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK (_slot_); + pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX (_slot_) = reg; + udelay (500); + + /* + * Make sure there is a card in the slot, + * then configure the interface. + */ + udelay (10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__, __FUNCTION__, + &(pcmp->pcmc_pipr), pcmp->pcmc_pipr); + if (pcmp->pcmc_pipr & 0x98000000) { + printf (" No Card found\n"); + return (1); + } + + mask = PCMCIA_VS1 (slot) | PCMCIA_VS2 (slot); + reg = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + reg, + (reg & PCMCIA_VS1 (slot)) ? "n" : "ff", + (reg & PCMCIA_VS2 (slot)) ? "n" : "ff"); + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX (_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX (_slot_) = reg; + + udelay (250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return 0; +} +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +int pcmcia_hardware_disable(int slot) +{ + return 0; /* No hardware to disable */ +} +#endif + +#endif /* CONFIG_PCMCIA */ diff --git a/board/gth2/config.mk b/board/gth2/config.mk index 6d21ba1..2bc1338 100644 --- a/board/gth2/config.mk +++ b/board/gth2/config.mk @@ -39,4 +39,3 @@ TEXT_BASE = 0x90000000 endif endif endif - diff --git a/board/gth2/ee_access.c b/board/gth2/ee_access.c index e293139..d4798c4 100644 --- a/board/gth2/ee_access.c +++ b/board/gth2/ee_access.c @@ -8,7 +8,7 @@ For documentaion, see data sheet for DS2438, 2438.pdf By Thomas.Lange@corelatus.com 001025 - + Copyright (C) 2000-2005 Corelatus AB */ /* This program is free software; you can redistribute it and/or @@ -105,7 +105,7 @@ static u8 make_new_crc( u8 Old_crc, u8 New_value ){ /* Compute a new checksum with new byte, using previous checksum as input See DS app note 17, understanding and using cyclic redundancy checks... Also see DS2438, page 11 */ - return( crc_lookup[Old_crc ^ New_value ]); + return( crc_lookup[Old_crc ^ New_value ]); } int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){ @@ -119,16 +119,16 @@ int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){ Curr_byte++; } E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc); - + if(Curr_crc == Crc){ - /* Good */ + /* Good */ return(TRUE); } printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc); return(FALSE); } -static void +static void set_idle(void){ /* Send idle and keep start time Continous 1 is idle */ @@ -136,7 +136,7 @@ set_idle(void){ } -static int +static int do_cpu_reset(void){ /* Release reset and verify that chip responds with presence pulse */ int Retries=0; @@ -146,10 +146,10 @@ do_cpu_reset(void){ /* Send reset */ WRITE_PORT(0); udelay(RESET_LOW_TIME); - + /* Release reset */ WRITE_PORT(1); - + /* Wait for EEPROM to drive output */ udelay(PRESENCE_TIMEOUT); if(!READ_PORT){ @@ -166,17 +166,17 @@ do_cpu_reset(void){ } printk(KERN_ERR"eeprom did not respond when releasing reset\n"); - + /* Make sure chip releases pin */ udelay(PRESENCE_LOW_TIME); /* Set to idle again */ set_idle(); - + return(-EIO); } -static u8 +static u8 read_cpu_byte(void){ /* Read a single byte from EEPROM Read LSb first */ @@ -186,36 +186,36 @@ read_cpu_byte(void){ u32 Flags; E_DEBUG("Reading byte\n"); - + for(i=0;i<8;i++){ /* Small delay between pulses */ udelay(1); -#ifdef __KERNEL__ - /* Disable irq */ +#ifdef __KERNEL__ + /* Disable irq */ save_flags(Flags); cli(); -#endif +#endif /* Pull down pin short time to start read See page 26 in data sheet */ - + WRITE_PORT(0); udelay(READ_LOW); WRITE_PORT(1); - + /* Wait for chip to drive pin */ udelay(READ_TIMEOUT); - + Value = READ_PORT; if(Value) Value=1; #ifdef __KERNEL__ - /* Enable irq */ + /* Enable irq */ restore_flags(Flags); #endif - + /* Wait for chip to release pin */ udelay(TOTAL_READ_LOW-READ_TIMEOUT); @@ -230,30 +230,30 @@ read_cpu_byte(void){ return(Result); } -static void +static void write_cpu_byte(u8 Byte){ /* Write a single byte to EEPROM Write LSb first */ int i; int Value; u32 Flags; - + E_DEBUG("Writing byte 0x%x\n",Byte); - + for(i=0;i<8;i++){ /* Small delay between pulses */ udelay(1); Value = Byte&1; - + #ifdef __KERNEL__ - /* Disable irq */ + /* Disable irq */ save_flags(Flags); cli(); -#endif +#endif /* Pull down pin short time for a 1, long time for a 0 See page 26 in data sheet */ - + WRITE_PORT(0); if(Value){ /* Write a 1 */ @@ -267,54 +267,54 @@ write_cpu_byte(u8 Byte){ WRITE_PORT(1); #ifdef __KERNEL__ - /* Enable irq */ + /* Enable irq */ restore_flags(Flags); #endif if(Value) /* Wait for chip to read the 1 */ udelay(TOTAL_WRITE_LOW-WRITE_1_LOW); - + /* E_DEBUG("Wrote %d\n",Value); */ Byte>>=1; } } int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){ - /* Execute this command string, including + /* Execute this command string, including giving reset and setting to idle after command - if Rx_len is set, we read out data from EEPROM */ + if Rx_len is set, we read out data from EEPROM */ int i; E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len ); - + if(do_cpu_reset()){ /* Failed! */ return(-EIO); } if(Send_skip) - /* Always send SKIP_ROM first to tell chip we are sending a command, + /* Always send SKIP_ROM first to tell chip we are sending a command, except when we read out rom data for chip */ write_cpu_byte(SKIP_ROM); - + /* Always have Tx data */ for(i=0;i<Tx_len;i++){ write_cpu_byte(Tx[i]); } - + if(Rx_len){ for(i=0;i<Rx_len;i++){ Rx[i]=read_cpu_byte(); } } - + set_idle(); E_DEBUG("Command done\n"); return(0); -} +} int ee_init_cpu_data(void){ int i; @@ -323,7 +323,7 @@ int ee_init_cpu_data(void){ /* Leave it floting since altera is driving the same pin */ set_idle(); - /* Copy all User EEPROM data to scratchpad */ + /* Copy all User EEPROM data to scratchpad */ for(i=0;i<USER_PAGES;i++){ Tx[0]=RECALL_MEMORY; Tx[1]=EE_USER_PAGE_0+i; @@ -332,16 +332,16 @@ int ee_init_cpu_data(void){ /* Make sure chip doesnt store measurements in NVRAM */ Tx[0]=WRITE_SCRATCHPAD; - Tx[1]=0; /* Page */ + Tx[1]=0; /* Page */ Tx[2]=9; if(ee_do_cpu_command(Tx,3,NULL,0,TRUE)) return(-EIO); Tx[0]=COPY_SCRATCHPAD; if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO); - + for(i=0;i<10;i++){ udelay(1000); } - + return(0); } diff --git a/board/gth2/ee_access.h b/board/gth2/ee_access.h index c21730e..926199d 100644 --- a/board/gth2/ee_access.h +++ b/board/gth2/ee_access.h @@ -21,7 +21,7 @@ int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ); #define EE_BUSY 0x40000000 #define EE_ERROR 0x20000000 -/* Commands */ +/* Commands */ #define EE_CMD_NOP 0 #define EE_CMD_INIT_RES 1 #define EE_CMD_WR_BYTE 2 diff --git a/board/gth2/ee_dev.h b/board/gth2/ee_dev.h index acc3418..89ef2f8 100644 --- a/board/gth2/ee_dev.h +++ b/board/gth2/ee_dev.h @@ -21,7 +21,7 @@ #ifndef INCeedevh #define INCeedevh -#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args) +#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args) /* MIPS */ #define WRITE_PORT(Value) write_gpio_data(Value) diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c index 77fc5b4..ffeaf58 100644 --- a/board/gth2/gth2.c +++ b/board/gth2/gth2.c @@ -61,13 +61,13 @@ void init_log_serial(void){ u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER; /* Copy buffer from last run */ - memcpy(serial_log_buffer + 4096, - serial_log_buffer, + memcpy(serial_log_buffer + 4096, + serial_log_buffer, 4096); memset(serial_log_buffer, 0, 4096); - *serial_log_offsetp = 4; + *serial_log_offsetp = 4; } @@ -118,7 +118,7 @@ void set_ledcard(u32 value){ udelay(1); *sys_outputclr = GPIO_LEDCLK; udelay(1); - + value<<=1; } /* Data is enable output */ @@ -228,7 +228,7 @@ static void write_bootdata (volatile u16 * addr, u8 System, u8 Count) printf ("Invalid boot count %u, setting 1\n", Count); Count = 1; } - + printf ("Boot attempt %d\n", Count); data = (System << 8) | Count; @@ -241,9 +241,9 @@ static void write_bootdata (volatile u16 * addr, u8 System, u8 Count) } static int random_system(void){ - /* EEPROM read failed. Just try to choose one + /* EEPROM read failed. Just try to choose one system release and hope it works */ - + /* FIXME */ return(SYSTEM_BOOT); } @@ -320,8 +320,8 @@ static void check_boot_tries (void) data = *addr; system = data >> 8; count = data & 0xFF; - if ((system != SYSTEM_BOOT) & - (system != SYSTEM2_BOOT) & + if ((system != SYSTEM_BOOT) & + (system != SYSTEM2_BOOT) & (system != FAILSAFE_BOOT)) { printf ("*** Wrong system %d\n", system); system = FAILSAFE_BOOT; diff --git a/board/gth2/lowlevel_init.S b/board/gth2/lowlevel_init.S index 62e3657..983ff70 100644 --- a/board/gth2/lowlevel_init.S +++ b/board/gth2/lowlevel_init.S @@ -197,11 +197,11 @@ noCacheJump: /* RCE2 CP Altera */ li t0, MEM_STCFG2 - li t1, 0x00000280 /* BE, EW */ + li t1, 0x00000280 /* BE, EW */ sw t1, 0(t0) li t0, MEM_STTIME2 - li t1, 0x0303000c + li t1, 0x0303000c sw t1, 0(t0) li t0, MEM_STADDR2 @@ -210,11 +210,11 @@ noCacheJump: /* RCE3 DP Altera */ li t0, MEM_STCFG3 - li t1, 0x00000280 /* BE, EW */ + li t1, 0x00000280 /* BE, EW */ sw t1, 0(t0) li t0, MEM_STTIME3 - li t1, 0x0303000c + li t1, 0x0303000c sw t1, 0(t0) li t0, MEM_STADDR3 @@ -428,14 +428,14 @@ mt0: sw t0, 0(t0) li t0, 0x80000000 li t1, 0xFFF000 /* 64 MB */ mt1: lw t2, 0(t0) - bne t0, t2, memhang + bne t0, t2, memhang add t1, -1 add t0, 4 bne t1, zero, mt1 nop nop .globl clearmem -clearmem: +clearmem: /* Clear memory */ li t0, 0x80000000 li t1, 0xFFF000 /* 64 MB */ @@ -445,10 +445,10 @@ mtc: sw zero, 0(t0) bne t1, zero, mtc nop nop -memtestend: +memtestend: j ra nop - -memhang: + +memhang: b memhang nop diff --git a/board/icu862/Makefile b/board/icu862/Makefile index 7a2014d..7b2b545 100644 --- a/board/icu862/Makefile +++ b/board/icu862/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o pcmcia.o $(LIB): .depend $(OBJS) $(AR) crv $@ $(OBJS) diff --git a/board/icu862/pcmcia.c b/board/icu862/pcmcia.c new file mode 100644 index 0000000..20f653b --- /dev/null +++ b/board/icu862/pcmcia.c @@ -0,0 +1,268 @@ +#include <common.h> +#include <mpc8xx.h> +#include <pcmcia.h> + +#undef CONFIG_PCMCIA + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#define CONFIG_PCMCIA +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#define CONFIG_PCMCIA +#endif + +#ifdef CONFIG_PCMCIA + +#define PCMCIA_BOARD_MSG "ICU862" + +static void cfg_port_B (void) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + uint reg; + + immap = (immap_t *)CFG_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* + * Configure Port B for TPS2205 PC-Card Power-Interface Switch + * + * Switch off all voltages, assert shutdown + */ + reg = cp->cp_pbdat; + reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ + TPS2205_VCC3 | TPS2205_VCC5 | /* VAVCC => Hi-Z */ + TPS2205_SHDN); /* enable switch */ + cp->cp_pbdat = reg; + + cp->cp_pbpar &= ~(TPS2205_INPUTS | TPS2205_OUTPUTS); + + reg = cp->cp_pbdir & ~(TPS2205_INPUTS); + cp->cp_pbdir = reg | TPS2205_OUTPUTS; + + debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n", + cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat); +} + +int pcmcia_hardware_enable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, pipr, mask; + int i; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + udelay(10000); + + immap = (immap_t *)CFG_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* Configure Port B for TPS2205 PC-Card Power-Interface Switch */ + cfg_port_B (); + + /* + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ + sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); + pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { + printf (" No Card found\n"); + return (1); + } + + /* + * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z + */ + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + pipr = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + pipr, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); + + reg = cp->cp_pbdat; + if ((pipr & mask) == mask) { + reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ + TPS2205_VCC3); /* 3V off */ + reg &= ~(TPS2205_VCC5); /* 5V on */ + puts (" 5.0V card found: "); + } else { + reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ + TPS2205_VCC5); /* 5V off */ + reg &= ~(TPS2205_VCC3); /* 3V on */ + puts (" 3.3V card found: "); + } + + debug ("\nPB DAT: %08x -> 3.3V %s 5.0V %s VPP_PGM %s VPP_VCC %s\n", + reg, + (reg & TPS2205_VCC3) ? "off" : "on", + (reg & TPS2205_VCC5) ? "off" : "on", + (reg & TPS2205_VPP_PGM) ? "off" : "on", + (reg & TPS2205_VPP_VCC) ? "off" : "on" ); + + cp->cp_pbdat = reg; + + /* Wait 500 ms; use this to check for over-current */ + for (i=0; i<5000; ++i) { + if ((cp->cp_pbdat & TPS2205_OC) == 0) { + printf (" *** Overcurrent - Safety shutdown ***\n"); + cp->cp_pbdat &= ~(TPS2205_SHDN); + return (1); + } + udelay (100); + } + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +int pcmcia_hardware_disable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + immap = (immap_t *)CFG_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + + /* Shut down */ + cp->cp_pbdat &= ~(TPS2205_SHDN); + + /* Configure PCMCIA General Control Register */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(10000); + + return (0); +} +#endif /* CFG_CMD_PCMCIA */ + + +int pcmcia_voltage_set(int slot, int vcc, int vpp) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("voltage_set: " + PCMCIA_BOARD_MSG + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + immap = (immap_t *)CFG_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Configure Port C pins for + * 5 Volts Enable and 3 Volts enable, + * Turn all power pins to Hi-Z + */ + debug ("PCMCIA power OFF\n"); + cfg_port_B (); /* Enables switch, but all in Hi-Z */ + + reg = cp->cp_pbdat; + + switch(vcc) { + case 0: break; /* Switch off */ + case 33: reg &= ~TPS2205_VCC3; break; /* Switch on 3.3V */ + case 50: reg &= ~TPS2205_VCC5; break; /* Switch on 5.0V */ + default: goto done; + } + + /* Checking supported voltages */ + + debug ("PIPR: 0x%x --> %s\n", + pcmp->pcmc_pipr, + (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); + + cp->cp_pbdat = reg; + +#ifdef DEBUG +{ + char *s; + + if ((reg & TPS2205_VCC3) == 0) { + s = "at 3.3V"; + } else if ((reg & TPS2205_VCC5) == 0) { + s = "at 5.0V"; + } else { + s = "down"; + } + printf ("PCMCIA powered %s\n", s); +} +#endif + +done: + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", + slot+'A'); + return (0); +} + +#endif /* CONFIG_PCMCIA */ diff --git a/board/kup/common/pcmcia.c b/board/kup/common/pcmcia.c new file mode 100644 index 0000000..1f61a0e --- /dev/null +++ b/board/kup/common/pcmcia.c @@ -0,0 +1,225 @@ +#include <common.h> +#include <mpc8xx.h> +#include <pcmcia.h> + +#undef CONFIG_PCMCIA + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#define CONFIG_PCMCIA +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#define CONFIG_PCMCIA +#endif + +#ifdef CONFIG_PCMCIA + +#define PCMCIA_BOARD_MSG "KUP" + +#define KUP4K_PCMCIA_B_3V3 (0x00020000) + +int pcmcia_hardware_enable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, mask; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + udelay(10000); + + immap = (immap_t *)CFG_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ + sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(slot); + pcmp->pcmc_per &= ~PCMCIA_MASK(slot); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(slot) = reg; + udelay(2500); + + /* + * Configure Port B pins for + * 3 Volts enable + */ + if (slot) { /* Slot A is built-in */ + cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3; + cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3; + /* remove all power */ + cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */ + } + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { + printf (" No Card found\n"); + return (1); + } + + /* + * Power On. + */ + printf("%s Slot %c:", slot ? "" : "\n", 'A' + slot); + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + reg = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + reg, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); + if ((reg & mask) == mask) { + puts (" 5.0V card found: NOT SUPPORTED !!!\n"); + } else { + if(slot) + cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3; + puts (" 3.3V card found: "); + } +#if 0 + /* VCC switch error flag, PCMCIA slot INPACK_ pin */ + cp->cp_pbdir &= ~(0x0020 | 0x0010); + cp->cp_pbpar &= ~(0x0020 | 0x0010); + udelay(500000); +#endif + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(slot); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(slot) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +int pcmcia_hardware_disable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* remove all power */ + if (slot) + cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; + + /* Configure PCMCIA General Control Register */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(slot) = reg; + + udelay(10000); + + return (0); +} +#endif /* CFG_CMD_PCMCIA */ + + +int pcmcia_voltage_set(int slot, int vcc, int vpp) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("voltage_set: " \ + PCMCIA_BOARD_MSG \ + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + if (!slot) /* Slot A is not configurable */ + return 0; + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(slot); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(slot) = reg; + udelay(500); + + debug ("PCMCIA power OFF\n"); + /* + * Configure Port B pins for + * 3 Volts enable + */ + cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3; + cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3; + /* remove all power */ + cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */ + + switch(vcc) { + case 0: break; + case 33: + cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3; + debug ("PCMCIA powered at 3.3V\n"); + break; + case 50: + debug ("PCMCIA: 5Volt vcc not supported\n"); + break; + default: + puts("PCMCIA: vcc not supported"); + break; + } + udelay(10000); + /* Checking supported voltages */ + + debug ("PIPR: 0x%x --> %s\n", + pcmp->pcmc_pipr, + (pcmp->pcmc_pipr & (0x80000000 >> (slot << 4))) + ? "only 5 V --> NOT SUPPORTED" + : "can do 3.3V"); + + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(slot); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(slot) = reg; + udelay(500); + + debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", + slot+'A'); + return (0); +} + +#endif /* CONFIG_PCMCIA */ diff --git a/board/kup/kup4k/Makefile b/board/kup/kup4k/Makefile index 62d289b..4a3954c 100644 --- a/board/kup/kup4k/Makefile +++ b/board/kup/kup4k/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o +OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o $(LIB): .depend $(OBJS) $(AR) crv $@ $(OBJS) diff --git a/board/kup/kup4x/Makefile b/board/kup/kup4x/Makefile index 62d289b..4a3954c 100644 --- a/board/kup/kup4x/Makefile +++ b/board/kup/kup4x/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o +OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o $(LIB): .depend $(OBJS) $(AR) crv $@ $(OBJS) diff --git a/board/lwmon/Makefile b/board/lwmon/Makefile index 7a2014d..7b2b545 100644 --- a/board/lwmon/Makefile +++ b/board/lwmon/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o pcmcia.o $(LIB): .depend $(OBJS) $(AR) crv $@ $(OBJS) diff --git a/board/lwmon/pcmcia.c b/board/lwmon/pcmcia.c new file mode 100644 index 0000000..2349286 --- /dev/null +++ b/board/lwmon/pcmcia.c @@ -0,0 +1,240 @@ +#include <common.h> +#include <mpc8xx.h> +#include <pcmcia.h> +#include <i2c.h> + +#undef CONFIG_PCMCIA + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#define CONFIG_PCMCIA +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#define CONFIG_PCMCIA +#endif + +#ifdef CONFIG_PCMCIA + +#define PCMCIA_BOARD_MSG "LWMON" + +/* #define's for MAX1604 Power Switch */ +#define MAX1604_OP_SUS 0x80 +#define MAX1604_VCCBON 0x40 +#define MAX1604_VCC_35 0x20 +#define MAX1604_VCCBHIZ 0x10 +#define MAX1604_VPPBON 0x08 +#define MAX1604_VPPBPBPGM 0x04 +#define MAX1604_VPPBHIZ 0x02 +/* reserved 0x01 */ + +int pcmcia_hardware_enable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, mask; + uchar val; + + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + /* Switch on PCMCIA port in PIC register 0x60 */ + reg = pic_read (0x60); + debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); + reg &= ~0x10; + /* reg |= 0x08; Vpp not needed */ + pic_write (0x60, reg); +#ifdef DEBUG + reg = pic_read (0x60); + printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); +#endif + udelay(10000); + + immap = (immap_t *)CFG_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ + sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); + pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { + printf (" No Card found\n"); + return (1); + } + + /* + * Power On. + */ + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + reg = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + reg, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); + if ((reg & mask) == mask) { + val = 0; /* VCCB3/5 = 0 ==> use Vx = 5.0 V */ + puts (" 5.0V card found: "); + } else { + val = MAX1604_VCC_35; /* VCCB3/5 = 1 ==> use Vy = 3.3 V */ + puts (" 3.3V card found: "); + } + + /* switch VCC on */ + val |= MAX1604_OP_SUS | MAX1604_VCCBON; + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1); + + udelay(500000); + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +int pcmcia_hardware_disable(int slot) +{ + volatile immap_t *immap; + volatile pcmconf8xx_t *pcmp; + u_long reg; + uchar val; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + + /* remove all power, put output in high impedance state */ + val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ; + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1); + + /* Configure PCMCIA General Control Register */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + /* Switch off PCMCIA port in PIC register 0x60 */ + reg = pic_read (0x60); + debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); + reg |= 0x10; + reg &= ~0x08; + pic_write (0x60, reg); +#ifdef DEBUG + reg = pic_read (0x60); + printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); +#endif + udelay(10000); + + return (0); +} +#endif /* CFG_CMD_PCMCIA */ + + +int pcmcia_voltage_set(int slot, int vcc, int vpp) +{ + volatile immap_t *immap; + volatile pcmconf8xx_t *pcmp; + u_long reg; + uchar val; + + debug ("voltage_set: " + PCMCIA_BOARD_MSG + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Turn off all power (switch to high impedance) + */ + debug ("PCMCIA power OFF\n"); + val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ; + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1); + + val = 0; + switch(vcc) { + case 0: break; + case 33: val = MAX1604_VCC_35; break; + case 50: break; + default: goto done; + } + + /* Checking supported voltages */ + + debug ("PIPR: 0x%x --> %s\n", + pcmp->pcmc_pipr, + (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); + + i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1); + if (val) { + debug ("PCMCIA powered at %sV\n", + (val & MAX1604_VCC_35) ? "3.3" : "5.0"); + } else { + debug ("PCMCIA powered down\n"); + } + +done: + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", + slot+'A'); + return (0); +} + +#endif /* CONFIG_PCMCIA */ diff --git a/board/mbx8xx/Makefile b/board/mbx8xx/Makefile index 3e8376c..e4d1099 100644 --- a/board/mbx8xx/Makefile +++ b/board/mbx8xx/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o vpd.o +OBJS = $(BOARD).o flash.o vpd.o pcmcia.o $(LIB): .depend $(OBJS) $(AR) crv $@ $(OBJS) diff --git a/board/mbx8xx/pcmcia.c b/board/mbx8xx/pcmcia.c new file mode 100644 index 0000000..132a688 --- /dev/null +++ b/board/mbx8xx/pcmcia.c @@ -0,0 +1,166 @@ +#include <common.h> +#include <mpc8xx.h> +#include <pcmcia.h> + +#include "csr.h" + +#undef CONFIG_PCMCIA + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#define CONFIG_PCMCIA +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#define CONFIG_PCMCIA +#endif + +#ifdef CONFIG_PCMCIA + +/* A lot of this has been taken from the RPX code in this file it works from me. + I have added the voltage selection for the MBX board. */ + +/* MBX voltage bit in control register #2 */ +#define CR2_VPP12 ((uchar)0x10) +#define CR2_VPPVDD ((uchar)0x20) +#define CR2_VDD5 ((uchar)0x40) +#define CR2_VDD3 ((uchar)0x80) + +#define PCMCIA_BOARD_MSG "MBX860" + +int pcmcia_voltage_set (int slot, int vcc, int vpp) +{ + uchar reg = 0; + + debug ("voltage_set: PCMCIA_BOARD_MSG Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A' + slot, vcc / 10, vcc % 10, vpp / 10, vcc % 10); + + switch (vcc) { + case 0: + break; + case 33: + reg |= CR2_VDD3; + break; + case 50: + reg |= CR2_VDD5; + break; + default: + return 1; + } + + switch (vpp) { + case 0: + break; + case 33: + case 50: + if (vcc == vpp) { + reg |= CR2_VPPVDD; + } else { + return 1; + } + break; + case 120: + reg |= CR2_VPP12; + break; + default: + return 1; + } + + /* first, turn off all power */ + MBX_CSR2 &= ~(CR2_VDDSEL | CR2_VPPSEL); + + /* enable new powersettings */ + MBX_CSR2 |= reg; + debug ("MBX_CSR2 read = 0x%02x\n", MBX_CSR2); + + return (0); +} + +int pcmcia_hardware_enable (int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, mask; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", + 'A' + slot); + + udelay (10000); + + immap = (immap_t *) CFG_IMMR; + sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm)); + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK (_slot_); + pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX (_slot_) = reg; + udelay (500); + + /* remove all power */ + pcmcia_voltage_set (slot, 0, 0); + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); +#ifndef CONFIG_HMI10 + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { +#else + if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) { +#endif /* CONFIG_HMI10 */ + printf (" No Card found\n"); + return (1); + } + + /* + * Power On. + */ + mask = PCMCIA_VS1 (_slot_) | PCMCIA_VS2 (_slot_); + reg = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg, + (reg & PCMCIA_VS1 (slot)) ? "n" : "ff", + (reg & PCMCIA_VS2 (slot)) ? "n" : "ff"); + + if ((reg & mask) == mask) { + pcmcia_voltage_set (_slot_, 50, 0); + printf (" 5.0V card found: "); + } else { + pcmcia_voltage_set (_slot_, 33, 0); + printf (" 3.3V card found: "); + } + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX (_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX (_slot_) = reg; + + udelay (250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); + } + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +int pcmcia_hardware_disable (int slot) +{ + return 0; /* No hardware to disable */ +} +#endif /* CFG_CMD_PCMCIA */ + +#endif /* CONFIG_PCMCIA */ diff --git a/board/mcc200/config.mk b/board/mcc200/config.mk index fa55673..a822559 100644 --- a/board/mcc200/config.mk +++ b/board/mcc200/config.mk @@ -26,16 +26,18 @@ # # Valid values for TEXT_BASE are: # -# 0xFFF00000 boot high (standard configuration) -# 0xFE000000 boot low +# 0xFC000000 boot low (standard configuration) +# 0xFFF00000 boot high # 0x00100000 boot from RAM (for testing only) # sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp ifndef TEXT_BASE -## Standard: boot high -TEXT_BASE = 0xFFF00000 +## Standard: boot low +TEXT_BASE = 0xFC000000 +## Boot high +# TEXT_BASE = 0xFFF00000 ## For testing: boot from RAM # TEXT_BASE = 0x00100000 endif diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c index b9b9a71..775030c 100644 --- a/board/mcc200/mcc200.c +++ b/board/mcc200/mcc200.c @@ -32,7 +32,12 @@ /* #include "mt48lc8m32b2-6-7.h" */ /* One MT48LC16M32S2 for 64 MB */ -#include "mt48lc16m32s2-75.h" +/* #include "mt48lc16m32s2-75.h" */ +#if defined (CONFIG_MCC200_SDRAM) +#include "mt48lc16m16a2-75.h" +#else +#include "mt46v16m16-75.h" +#endif DECLARE_GLOBAL_DATA_PTR; @@ -198,6 +203,8 @@ int checkboard (void) int misc_init_r (void) { + ulong flash_sup_end, snum; + /* * Adjust flash start and offset to detected values */ @@ -249,9 +256,15 @@ int misc_init_r (void) *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6); flash_protect (FLAG_PROTECT_CLEAR, flash_info[0].start[0] + flash_info[0].size / 2, - (flash_info[0].start[0] + flash_info[0].size) / 2 - 1, + (flash_info[0].start[0] - 1) + flash_info[0].size, &flash_info[0]); *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6); + printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n"); + flash_info[0].size = 32 << 20; + for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20); + flash_info[0].start[snum] < flash_sup_end; + snum++); + flash_info[0].sector_count = snum; } return (0); diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile new file mode 100644 index 0000000..f70f44b --- /dev/null +++ b/board/mpc8641hpcn/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o pixis.o sys_eeprom.o +SOBJS := init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +.PHONY: distclean +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ +ifeq ($(filter distclean, $(MAKECMDGOALS)),) +-include .depend +endif + +######################################################################### diff --git a/board/mpc8641hpcn/config.mk b/board/mpc8641hpcn/config.mk new file mode 100644 index 0000000..989a40b --- /dev/null +++ b/board/mpc8641hpcn/config.mk @@ -0,0 +1,31 @@ +# Copyright 2004 Freescale Semiconductor. +# Modified by Jeff Brown +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8641hpcn board +# default CCSRBAR is at 0xff700000 +# assume U-Boot is less than 0.5MB +# +TEXT_BASE = 0xfff01000 + +PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S new file mode 100644 index 0000000..c6ea55e --- /dev/null +++ b/board/mpc8641hpcn/init.S @@ -0,0 +1,180 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Jeff Brown + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <asm/cache.h> +#include <asm/mmu.h> +#include <config.h> +#include <mpc86xx.h> + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xf800_0000 0xf80f_ffff CCSRBAR 1M + * 0xf810_0000 0xf81f_ffff PIXIS 1M + * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M + * + * Notes: + * CCSRBAR don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#else +#define LAWBAR1 0 +#define LAWAR1 ((LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) +#endif + +#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff) +#define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))) + +/* + * This is not so much the SDRAM map as it is the whole localbus map. + */ +#define LAWBAR4 ((0xf8100000>>12) & 0xffffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M)) + +#define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +#define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff) +#define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))) + +#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) +#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR8 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) +#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#else +#define LAWBAR8 0 +#define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) +#endif + +#define LAWBAR9 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + .section .bootpg, "ax" + .globl law_entry +law_entry: + lis r7,CFG_CCSRBAR@h + ori r7,r7,CFG_CCSRBAR@l + + addi r4,r7,0 + addi r5,r7,0 + + /* Skip LAWAR0, start at LAWAR1 */ + lis r6,LAWBAR1@h + ori r6,r6,LAWBAR1@l + stwu r6, 0xc28(r4) + + lis r6,LAWAR1@h + ori r6,r6,LAWAR1@l + stwu r6, 0xc30(r5) + + /* LAWBAR2, LAWAR2 */ + lis r6,LAWBAR2@h + ori r6,r6,LAWBAR2@l + stwu r6, 0x20(r4) + + lis r6,LAWAR2@h + ori r6,r6,LAWAR2@l + stwu r6, 0x20(r5) + + /* LAWBAR3, LAWAR3 */ + lis r6,LAWBAR3@h + ori r6,r6,LAWBAR3@l + stwu r6, 0x20(r4) + + lis r6,LAWAR3@h + ori r6,r6,LAWAR3@l + stwu r6, 0x20(r5) + + /* LAWBAR4, LAWAR4 */ + lis r6,LAWBAR4@h + ori r6,r6,LAWBAR4@l + stwu r6, 0x20(r4) + + lis r6,LAWAR4@h + ori r6,r6,LAWAR4@l + stwu r6, 0x20(r5) + /* LAWBAR5, LAWAR5 */ + lis r6,LAWBAR5@h + ori r6,r6,LAWBAR5@l + stwu r6, 0x20(r4) + + lis r6,LAWAR5@h + ori r6,r6,LAWAR5@l + stwu r6, 0x20(r5) + + /* LAWBAR6, LAWAR6 */ + lis r6,LAWBAR6@h + ori r6,r6,LAWBAR6@l + stwu r6, 0x20(r4) + + lis r6,LAWAR6@h + ori r6,r6,LAWAR6@l + stwu r6, 0x20(r5) + + /* LAWBAR7, LAWAR7 */ + lis r6,LAWBAR7@h + ori r6,r6,LAWBAR7@l + stwu r6, 0x20(r4) + + lis r6,LAWAR7@h + ori r6,r6,LAWAR7@l + stwu r6, 0x20(r5) + + /* LAWBAR8, LAWAR8 */ + lis r6,LAWBAR8@h + ori r6,r6,LAWBAR8@l + stwu r6, 0x20(r4) + + lis r6,LAWAR8@h + ori r6,r6,LAWAR8@l + stwu r6, 0x20(r5) + + /* LAWBAR9, LAWAR9 */ + lis r6,LAWBAR9@h + ori r6,r6,LAWBAR9@l + stwu r6, 0x20(r4) + + lis r6,LAWAR9@h + ori r6,r6,LAWAR9@l + stwu r6, 0x20(r5) + + blr + diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c new file mode 100644 index 0000000..b2cf4a9 --- /dev/null +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -0,0 +1,426 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Jeff Brown + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/immap_86xx.h> +#include <spd.h> + +#if defined(CONFIG_OF_FLAT_TREE) +#include <ft_build.h> +extern void ft_cpu_setup(void *blob, bd_t *bd); +#endif + +#include "pixis.h" + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +#if defined(CONFIG_SPD_EEPROM) +#include "spd_sdram.h" +#endif + +void sdram_init(void); +long int fixed_sdram(void); + + +int board_early_init_f(void) +{ + return 0; +} + +int checkboard(void) +{ + puts("Board: MPC8641HPCN\n"); + +#ifdef CONFIG_PCI + + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_pex_t *pex1 = &immap->im_pex1; + + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); + + if ((io_sel == 2 || io_sel == 3 || io_sel == 5 + || io_sel == 6 || io_sel == 7 || io_sel == 0xF) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); + debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det); + if (pex1->pme_msg_det) { + pex1->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pex1->pme_msg_det); + } + debug("\n"); + } else { + puts("PCI-EXPRESS 1: Disabled\n"); + } + +#else + puts("PCI-EXPRESS1: Disabled\n"); +#endif + + return 0; +} + + +long int +initdram(int board_type) +{ + long dram_size = 0; + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram(); +#else + dram_size = fixed_sdram(); +#endif + +#if defined(CFG_RAMBOOT) + puts(" DDR: "); + return dram_size; +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + puts(" DDR: "); + return dram_size; +} + + +#if defined(CFG_DRAM_TEST) +int +testdram(void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + puts("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + puts("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + puts("SDRAM test passed.\n"); + return 0; +} +#endif + + +#if !defined(CONFIG_SPD_EEPROM) +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +long int +fixed_sdram(void) +{ +#if !defined(CFG_RAMBOOT) + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_ddr_t *ddr = &immap->im_ddr1; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->ext_refrec = CFG_DDR_EXT_REFRESH; + ddr->timing_cfg_0 = CFG_DDR_TIMING_0; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_mode_1 = CFG_DDR_MODE_1; + ddr->sdram_mode_2 = CFG_DDR_MODE_2; + ddr->sdram_interval = CFG_DDR_INTERVAL; + ddr->sdram_data_init = CFG_DDR_DATA_INIT; + ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; + ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; + ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS; + +#if defined (CONFIG_DDR_ECC) + ddr->err_disable = 0x0000008D; + ddr->err_sbe = 0x00ff0000; +#endif + asm("sync;isync"); + + udelay(500); + +#if defined (CONFIG_DDR_ECC) + /* Enable ECC checking */ + ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000); +#else + ddr->sdram_cfg_1 = CFG_DDR_CONTROL; + ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; +#endif + asm("sync; isync"); + + udelay(500); +#endif + return CFG_SDRAM_SIZE * 1024 * 1024; +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_fsl86xxads_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, + {} +}; +#endif + + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc86xxcts_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + +void pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc86xx_init(struct pci_controller *hose); + + pci_mpc86xx_init(&hose); +#endif /* CONFIG_PCI */ +} + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +} +#endif + + +void +mpc8641_reset_board(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + char cmd; + ulong val; + ulong corepll; + + /* + * No args is a simple reset request. + */ + if (argc <= 1) { + out8(PIXIS_BASE + PIXIS_RST, 0); + /* not reached */ + } + + cmd = argv[1][1]; + switch (cmd) { + case 'f': /* reset with frequency changed */ + if (argc < 5) + goto my_usage; + read_from_px_regs(0); + + val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10)); + + corepll = strfractoint(argv[3]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10)); + if (val == 3) { + puts("Setting registers VCFGEN0 and VCTL\n"); + read_from_px_regs(1); + puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); + set_px_go(); + } else + goto my_usage; + + while (1) ; /* Not reached */ + + case 'l': + if (argv[2][1] == 'f') { + read_from_px_regs(0); + read_from_px_regs_altbank(0); + /* reset with frequency changed */ + val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10)); + + corepll = strfractoint(argv[4]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[5], + NULL, 10)); + if (val == 3) { + puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs(1); + read_from_px_regs_altbank(1); + puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); + set_px_go_with_watchdog(); + } else + goto my_usage; + + while (1) ; /* Not reached */ + + } else if (argv[2][1] == 'd') { + /* + * Reset from alternate bank without changing + * frequencies but with watchdog timer enabled. + */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + puts("Setting registers VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); + set_px_go_with_watchdog(); + while (1) ; /* Not reached */ + + } else { + /* + * Reset from next bank without changing + * frequency and without watchdog timer enabled. + */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + if (argc > 2) + goto my_usage; + puts("Setting registers VCFGNE1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + puts("Resetting board to boot from the other bank....\n"); + set_px_go(); + } + + default: + goto my_usage; + } + +my_usage: + puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"); + puts(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n"); + puts(" reset altbank [wd]\n"); + puts("For example: reset cf 40 2.5 10\n"); + puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); +} + + +/* + * get_board_sys_clk + * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ + */ + +unsigned long +get_board_sys_clk(ulong dummy) +{ + u8 i, go_bit, rd_clks; + ulong val = 0; + + go_bit = in8(PIXIS_BASE + PIXIS_VCTL); + go_bit &= 0x01; + + rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); + rd_clks &= 0x1C; + + /* + * Only if both go bit and the SCLK bit in VCFGEN0 are set + * should we be using the AUX register. Remember, we also set the + * GO bit to boot from the alternate bank on the on-board flash + */ + + if (go_bit) { + if (rd_clks == 0x1c) + i = in8(PIXIS_BASE + PIXIS_AUX); + else + i = in8(PIXIS_BASE + PIXIS_SPD); + } else { + i = in8(PIXIS_BASE + PIXIS_SPD); + } + + i &= 0x07; + + switch (i) { + case 0: + val = 33000000; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66000000; + break; + case 4: + val = 83000000; + break; + case 5: + val = 100000000; + break; + case 6: + val = 134000000; + break; + case 7: + val = 166000000; + break; + } + + return val; +} diff --git a/board/mpc8641hpcn/pixis.c b/board/mpc8641hpcn/pixis.c new file mode 100644 index 0000000..964a17c --- /dev/null +++ b/board/mpc8641hpcn/pixis.c @@ -0,0 +1,321 @@ +/* + * Copyright 2006 Freescale Semiconductor + * Jeff Brown + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <command.h> +#include <asm/cache.h> +#include <mpc86xx.h> + +#include "pixis.h" + + +/* + * Per table 27, page 58 of MPC8641HPCN spec. + */ +int set_px_sysclk(ulong sysclk) +{ + u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux; + + switch (sysclk) { + case 33: + sysclk_s = 0x04; + sysclk_r = 0x04; + sysclk_v = 0x07; + sysclk_aux = 0x00; + break; + case 40: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x20; + sysclk_aux = 0x01; + break; + case 50: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x2A; + sysclk_aux = 0x02; + break; + case 66: + sysclk_s = 0x01; + sysclk_r = 0x04; + sysclk_v = 0x04; + sysclk_aux = 0x03; + break; + case 83: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x4B; + sysclk_aux = 0x04; + break; + case 100: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x5C; + sysclk_aux = 0x05; + break; + case 134: + sysclk_s = 0x06; + sysclk_r = 0x1F; + sysclk_v = 0x3B; + sysclk_aux = 0x06; + break; + case 166: + sysclk_s = 0x06; + sysclk_r = 0x1F; + sysclk_v = 0x4B; + sysclk_aux = 0x07; + break; + default: + printf("Unsupported SYSCLK frequency.\n"); + return 0; + } + + vclkh = (sysclk_s << 5) | sysclk_r; + vclkl = sysclk_v; + + out8(PIXIS_BASE + PIXIS_VCLKH, vclkh); + out8(PIXIS_BASE + PIXIS_VCLKL, vclkl); + + out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux); + + return 1; +} + + +int set_px_mpxpll(ulong mpxpll) +{ + u8 tmp; + u8 val; + + switch (mpxpll) { + case 2: + case 4: + case 6: + case 8: + case 10: + case 12: + case 14: + case 16: + val = (u8) mpxpll; + break; + default: + printf("Unsupported MPXPLL ratio.\n"); + return 0; + } + + tmp = in8(PIXIS_BASE + PIXIS_VSPEED1); + tmp = (tmp & 0xF0) | (val & 0x0F); + out8(PIXIS_BASE + PIXIS_VSPEED1, tmp); + + return 1; +} + + +int set_px_corepll(ulong corepll) +{ + u8 tmp; + u8 val; + + switch ((int)corepll) { + case 20: + val = 0x08; + break; + case 25: + val = 0x0C; + break; + case 30: + val = 0x10; + break; + case 35: + val = 0x1C; + break; + case 40: + val = 0x14; + break; + case 45: + val = 0x0E; + break; + default: + printf("Unsupported COREPLL ratio.\n"); + return 0; + } + + tmp = in8(PIXIS_BASE + PIXIS_VSPEED0); + tmp = (tmp & 0xE0) | (val & 0x1F); + out8(PIXIS_BASE + PIXIS_VSPEED0, tmp); + + return 1; +} + + +void read_from_px_regs(int set) +{ + u8 mask = 0x1C; + u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0); + + if (set) + tmp = tmp | mask; + else + tmp = tmp & ~mask; + out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp); +} + + +void read_from_px_regs_altbank(int set) +{ + u8 mask = 0x04; + u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1); + + if (set) + tmp = tmp | mask; + else + tmp = tmp & ~mask; + out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp); +} + + +void set_altbank(void) +{ + u8 tmp; + + tmp = in8(PIXIS_BASE + PIXIS_VBOOT); + tmp ^= 0x40; + + out8(PIXIS_BASE + PIXIS_VBOOT, tmp); +} + + +void set_px_go(void) +{ + u8 tmp; + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp & 0x1E; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp | 0x01; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); +} + + +void set_px_go_with_watchdog(void) +{ + u8 tmp; + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp & 0x1E; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp | 0x09; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); +} + + +int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u8 tmp; + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp & 0x1E; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); + + /* setting VCTL[WDEN] to 0 to disable watch dog */ + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp &= ~0x08; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); + + return 0; +} + +U_BOOT_CMD( + diswd, 1, 0, disable_watchdog, + "diswd - Disable watchdog timer \n", + NULL); + +/* + * This function takes the non-integral cpu:mpx pll ratio + * and converts it to an integer that can be used to assign + * FPGA register values. + * input: strptr i.e. argv[2] + */ + +ulong strfractoint(uchar *strptr) +{ + int i, j, retval; + int mulconst; + int intarr_len = 0, decarr_len = 0, no_dec = 0; + ulong intval = 0, decval = 0; + uchar intarr[3], decarr[3]; + + /* Assign the integer part to intarr[] + * If there is no decimal point i.e. + * if the ratio is an integral value + * simply create the intarr. + */ + i = 0; + while (strptr[i] != 46) { + if (strptr[i] == 0) { + no_dec = 1; + break; + } + intarr[i] = strptr[i]; + i++; + } + + /* Assign length of integer part to intarr_len. */ + intarr_len = i; + intarr[i] = '\0'; + + if (no_dec) { + /* Currently needed only for single digit corepll ratios */ + mulconst = 10; + decval = 0; + } else { + j = 0; + i++; /* Skipping the decimal point */ + while ((strptr[i] > 47) && (strptr[i] < 58)) { + decarr[j] = strptr[i]; + i++; + j++; + } + + decarr_len = j; + decarr[j] = '\0'; + + mulconst = 1; + for (i = 0; i < decarr_len; i++) + mulconst *= 10; + decval = simple_strtoul(decarr, NULL, 10); + } + + intval = simple_strtoul(intarr, NULL, 10); + intval = intval * mulconst; + + retval = intval + decval; + + return retval; +} diff --git a/board/mpc8641hpcn/pixis.h b/board/mpc8641hpcn/pixis.h new file mode 100644 index 0000000..cd9a45d --- /dev/null +++ b/board/mpc8641hpcn/pixis.h @@ -0,0 +1,33 @@ +/* + * Copyright 2006 Freescale Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +extern int set_px_sysclk(ulong sysclk); +extern int set_px_mpxpll(ulong mpxpll); +extern int set_px_corepll(ulong corepll); +extern void read_from_px_regs(int set); +extern void read_from_px_regs_altbank(int set); +extern void set_altbank(void); +extern void set_px_go(void); +extern void set_px_go_with_watchdog(void); +extern int disable_watchdog(cmd_tbl_t *cmdtp, + int flag, int argc, char *argv[]); +extern ulong strfractoint(uchar *strptr); diff --git a/board/mpc8641hpcn/sys_eeprom.c b/board/mpc8641hpcn/sys_eeprom.c new file mode 100644 index 0000000..74e2a3d --- /dev/null +++ b/board/mpc8641hpcn/sys_eeprom.c @@ -0,0 +1,256 @@ +/* + * Copyright 2006 Freescale Semiconductor + * York Sun (yorksun@freescale.com) + * Haiying Wang (haiying.wang@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> +#include <linux/ctype.h> + +#ifdef CFG_ID_EEPROM +typedef struct { + unsigned char id[4]; /* 0x0000 - 0x0003 */ + unsigned char sn[12]; /* 0x0004 - 0x000F */ + unsigned char errata[5]; /* 0x0010 - 0x0014 */ + unsigned char date[7]; /* 0x0015 - 0x001a */ + unsigned char res_1[37]; /* 0x001b - 0x003f */ + unsigned char tab_size; /* 0x0040 */ + unsigned char tab_flag; /* 0x0041 */ + unsigned char mac[8][6]; /* 0x0042 - 0x0071 */ + unsigned char res_2[126]; /* 0x0072 - 0x00ef */ + unsigned int crc; /* 0x00f0 - 0x00f3 crc32 checksum */ +} EEPROM_data; + +static EEPROM_data mac_data; + +int mac_show(void) +{ + int i; + unsigned char ethaddr[8][18]; + + printf("ID %c%c%c%c\n", + mac_data.id[0], + mac_data.id[1], + mac_data.id[2], + mac_data.id[3]); + printf("Errata %c%c%c%c%c\n", + mac_data.errata[0], + mac_data.errata[1], + mac_data.errata[2], + mac_data.errata[3], + mac_data.errata[4]); + printf("Date %c%c%c%c%c%c%c\n", + mac_data.date[0], + mac_data.date[1], + mac_data.date[2], + mac_data.date[3], + mac_data.date[4], + mac_data.date[5], + mac_data.date[6]); + for (i = 0; i < 8; i++) { + sprintf(ethaddr[i], + "%02x:%02x:%02x:%02x:%02x:%02x", + mac_data.mac[i][0], + mac_data.mac[i][1], + mac_data.mac[i][2], + mac_data.mac[i][3], + mac_data.mac[i][4], + mac_data.mac[i][5]); + printf("MAC %d %s\n", i, ethaddr[i]); + } + + setenv("ethaddr", ethaddr[0]); + setenv("eth1addr", ethaddr[1]); + setenv("eth2addr", ethaddr[2]); + setenv("eth3addr", ethaddr[3]); + + return 0; +} + +int mac_read(void) +{ + int ret, length; + unsigned int crc = 0; + unsigned char dev = ID_EEPROM_ADDR, *data; + + length = sizeof(EEPROM_data); + ret = i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length); + if (ret) { + printf("Read failed.\n"); + return -1; + } + + data = (unsigned char *)(&mac_data); + printf("Check CRC on reading ..."); + crc = crc32(crc, data, length - 4); + if (crc != mac_data.crc) { + printf("CRC checksum is invalid, in EEPROM CRC is %x, calculated CRC is %x\n", + mac_data.crc, crc); + return -1; + } else { + printf("CRC OK\n"); + mac_show(); + } + return 0; +} + +int mac_prog(void) +{ + int ret, i, length; + unsigned int crc = 0; + unsigned char dev = ID_EEPROM_ADDR, *ptr; + unsigned char *eeprom_data = (unsigned char *)(&mac_data); + + for (i = 0; i < sizeof(mac_data.res_1); i++) + mac_data.res_1[i] = 0; + for (i = 0; i < sizeof(mac_data.res_2); i++) + mac_data.res_2[i] = 0; + length = sizeof(EEPROM_data); + crc = crc32(crc, eeprom_data, length - 4); + mac_data.crc = crc; + for (i = 0, ptr = eeprom_data; i < length; i += 8, ptr += 8) { + ret = + i2c_write(dev, i, 1, ptr, + (length - i) < 8 ? (length - i) : 8); + udelay(5000); /* 5ms write cycle timing */ + if (ret) + break; + } + if (ret) { + printf("Programming failed.\n"); + return -1; + } else { + printf("Programming %d bytes. Reading back ...\n", length); + mac_read(); + } + return 0; +} + +int do_mac(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int i; + char cmd = 's'; + unsigned long long mac_val; + + if (i2c_probe(ID_EEPROM_ADDR) != 0) + return -1; + + if (argc > 1) { + cmd = argv[1][0]; + switch (cmd) { + case 'r': /* display */ + mac_read(); + break; + case 's': /* save */ + mac_prog(); + break; + case 'i': /* id */ + for (i = 0; i < 4; i++) { + mac_data.id[i] = argv[2][i]; + } + break; + case 'n': /* serial number */ + for (i = 0; i < 12; i++) { + mac_data.sn[i] = argv[2][i]; + } + break; + case 'e': /* errata */ + for (i = 0; i < 5; i++) { + mac_data.errata[i] = argv[2][i]; + } + break; + case 'd': /* date */ + for (i = 0; i < 7; i++) { + mac_data.date[i] = argv[2][i]; + } + break; + case 'p': /* number of ports */ + mac_data.tab_size = + (unsigned char)simple_strtoul(argv[2], NULL, 16); + break; + case '0': /* mac 0 */ + case '1': /* mac 1 */ + case '2': /* mac 2 */ + case '3': /* mac 3 */ + case '4': /* mac 4 */ + case '5': /* mac 5 */ + case '6': /* mac 6 */ + case '7': /* mac 7 */ + mac_val = simple_strtoull(argv[2], NULL, 16); + for (i = 0; i < 6; i++) { + mac_data.mac[cmd - '0'][i] = + *((unsigned char *) + (((unsigned int)(&mac_val)) + i + 2)); + } + break; + case 'h': /* help */ + default: + printf("Usage:\n%s\n", cmdtp->usage); + break; + } + } else { + mac_show(); + } + return 0; +} + +int mac_read_from_eeprom(void) +{ + int length, i; + unsigned char dev = ID_EEPROM_ADDR; + unsigned char *data; + unsigned char ethaddr[4][18]; + unsigned char enetvar[32]; + unsigned int crc = 0; + + length = sizeof(EEPROM_data); + if (i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length)) { + printf("Read failed.\n"); + return -1; + } + + data = (unsigned char *)(&mac_data); + crc = crc32(crc, data, length - 4); + if (crc != mac_data.crc) { + return -1; + } else { + for (i = 0; i < 4; i++) { + if (memcmp(&mac_data.mac[i], "\0\0\0\0\0\0", 6)) { + sprintf(ethaddr[i], + "%02x:%02x:%02x:%02x:%02x:%02x", + mac_data.mac[i][0], + mac_data.mac[i][1], + mac_data.mac[i][2], + mac_data.mac[i][3], + mac_data.mac[i][4], + mac_data.mac[i][5]); + sprintf(enetvar, + i ? "eth%daddr" : "ethaddr", + i); + setenv(enetvar, ethaddr[i]); + } + } + } + return 0; +} +#endif /* CFG_ID_EEPROM */ diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds new file mode 100644 index 0000000..b34de8e --- /dev/null +++ b/board/mpc8641hpcn/u-boot.lds @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2004, Freescale, Inc. + * (C) Copyright 2002,2003, Motorola,Inc. + * Jeff Brown + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFF00100 : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFF70000 : + { + cpu/mpc86xx/start.o (.bootpg) + board/mpc8641hpcn/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + 1024; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc86xx/start.o (.text) + board/mpc8641hpcn/init.o (.text) + cpu/mpc86xx/traps.o (.text) + cpu/mpc86xx/interrupts.o (.text) + cpu/mpc86xx/cpu_init.o (.text) + cpu/mpc86xx/cpu.o (.text) + cpu/mpc86xx/speed.o (.text) + cpu/mpc86xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/netstar/crcek.S b/board/netstar/crcek.S index 6ca4d11..a74abf9 100644 --- a/board/netstar/crcek.S +++ b/board/netstar/crcek.S @@ -13,6 +13,7 @@ * u32 - crc32 */ +#include <config.h> #include "crcek.h" /** @@ -39,7 +40,7 @@ .macro crcuj, offset, size mov r0, #0 ldr r1, \offset - ldr r2, [r1] + ldr r2, [r1], #4 cmp r2, r0 @ no data, no problem beq 2f tst r2, #3 @ unaligned size @@ -47,7 +48,6 @@ ldr r3, \size cmp r2, r3 @ bogus size bhi 2f - add r1, r1, #4 do_crc32 ldr r1, [r1] 2: @@ -55,16 +55,71 @@ .endm .macro wait, reg - mov \reg, #0x1000 + mov \reg, #0x100000 3: subs \reg, \reg, #0x1 bne 3b - .endm + .text .globl crcek crcek: - b crc2_bad + /* Enable I-cache */ + mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register + mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register + mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register + orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000 + mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register + mov r1, #0x00 + mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache + nop + nop + nop + nop + + /* Setup clocking mode */ + ldr r0, MPU_CLKM_BASE @ base of CLOCK unit + ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status + bic r1, r1, #(7 << 11) @ clear clock select + orr r1, r1, #(2 << 11) @ set synchronous scalable + mov r2, #0 +loop: + cmp r2, #1 @ this loop will wait for at least 100 cycles + streqh r1, [r0, #0x18] @ before issuing next request from MPU + add r2, r2, #1 @ on the 1st run code is loaded into I-cache + cmp r2, #16 @ and second run will set clocking mode + bne loop + nop + + /* Setup clock dividers */ + ldr r1, CKCTL_VAL + orr r1, r1, #0x2000 @ enable DSP clock + strh r1, [r0] @ setup clock divisors + + /* Setup DPLL to generate requested freq */ + ldr r0, DPLL1_BASE @ base of DPLL1 register + mov r1, #0x0010 @ set PLL_ENABLE + orr r1, r1, #0x2000 @ set IOB to new locking + orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF + orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF + strh r1, [r0] @ write + +locking: + ldrh r1, [r0] @ get DPLL value + tst r1, #0x01 + beq locking @ while LOCK not set + + /* Enable clock */ + ldr r0, MPU_CLKM_BASE @ base of CLOCK unit + mov r1, #(1 << 10) @ disable idle mode do not check + @ nWAKEUP pin, other remain active + strh r1, [r0, #0x04] + ldr r1, EN_CLK_VAL + strh r1, [r0, #0x08] + mov r1, #0x003f @ FLASH.RP not enabled in idle and + strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN ) + + mov r6, #0 crcuj _LOADER1_OFFSET, _LOADER_SIZE bne crc1_bad @@ -76,9 +131,8 @@ crc1_bad: crc2_bad: ldr r3, _LOADER1_OFFSET ldr r4, _LOADER2_OFFSET - b boot_2nd - tst r6, #3 - beq one_is_bad @ one of them (or both) has bad crc + teq r6, #3 + bne one_is_bad @ one of them (or both) has bad crc ldr r1, [r3, #4] ldr r2, [r4, #4] cmp r1, r2 @ boot 2nd loader if versions differ @@ -90,6 +144,7 @@ one_is_bad: tst r6, #2 bne boot_2nd @ We are doomed, so let user know. +hell: ldr r0, GPIO_BASE @ configure GPIO pins ldr r1, GPIO_DIRECTION strh r1, [r0, #0x08] @@ -171,6 +226,15 @@ CRC32_TABLE: GPIO_BASE: .word 0xfffce000 +MPU_CLKM_BASE: + .word 0xfffece00 +DPLL1_BASE: + .word 0xfffecf00 + +CKCTL_VAL: + .word OMAP5910_ARM_CKCTL +EN_CLK_VAL: + .word OMAP5910_ARM_EN_CLK GPIO_DIRECTION: .word 0x0000ffe7 diff --git a/board/netstar/crcit b/board/netstar/crcit Binary files differindex 98ae42e..203645d 100755 --- a/board/netstar/crcit +++ b/board/netstar/crcit diff --git a/board/netstar/crcit.c b/board/netstar/crcit.c index f6d3066..ce98e20 100644 --- a/board/netstar/crcit.c +++ b/board/netstar/crcit.c @@ -77,7 +77,7 @@ int main(int argc, char **argv) } else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) { char *endptr, *nptr = argv[2]; unsigned ver = strtoul(nptr, &endptr, 0); - if (nptr != '\0' && endptr == '\0') + if (*nptr != '\0' && *endptr == '\0') return doit(argv[3], ver); } fprintf(stderr, "Usage: crcit [-v version] <image>\n"); diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c index 4b7eba1..d6b620c 100644 --- a/board/netstar/netstar.c +++ b/board/netstar/netstar.c @@ -27,7 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { /* arch number of NetStar board */ - /* TODO: use define from asm/mach-types.h */ gd->bd->bi_arch_number = 692; /* adress of boot parameters */ @@ -51,15 +50,11 @@ int dram_init(void) return 0; } -extern void partition_flash(void); - int misc_init_r(void) { return 0; } -extern void nand_init(void); - int board_late_init(void) { return 0; diff --git a/board/netstar/setup.S b/board/netstar/setup.S index f67786d..5dacc9c 100644 --- a/board/netstar/setup.S +++ b/board/netstar/setup.S @@ -145,25 +145,23 @@ lowlevel_init: nop /* Setup clocking mode */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit - ldrh r1, [r0, #0x18] @ get reset status + ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit + ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status bic r1, r1, #(7 << 11) @ clear clock select orr r1, r1, #(2 << 11) @ set synchronous scalable - mov r2, #0 @ set wait counter to 100 clock cycles - -icache_loop: - cmp r2, #0x01 - streqh r1, [r0, #0x18] - add r2, r2, #0x01 - cmp r2, #0x10 - bne icache_loop + mov r2, #0 +loop: + cmp r2, #1 @ this loop will wait for at least 100 cycles + streqh r1, [r0, #0x18] @ before issuing next request from MPU + add r2, r2, #1 @ on the 1st run code is loaded into I-cache + cmp r2, #16 @ and second run will set clocking mode + bne loop nop - /* Setup clock divisors */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit + /* Setup clock dividers */ ldr r1, _OMAP5910_ARM_CKCTL orr r1, r1, #0x2000 @ enable DSP clock - strh r1, [r0, #0x00] @ setup clock divisors + strh r1, [r0] @ setup clock divisors /* Setup DPLL to generate requested freq */ ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register @@ -186,8 +184,7 @@ locking: ldr r1, _OMAP5910_ARM_EN_CLK strh r1, [r0, #0x08] mov r1, #0x003f @ FLASH.RP not enabled in idle and - @ max delayed ( 32 x CLKIN ) - strh r1, [r0, #0x0c] + strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN ) /* Configure 5910 pins functions to match our board. */ ldr r0, MUX_CONFIG_BASE diff --git a/board/netta/Makefile b/board/netta/Makefile index 68e2402..ee200c2 100644 --- a/board/netta/Makefile +++ b/board/netta/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o dsp.o codec.o +OBJS = $(BOARD).o flash.o dsp.o codec.o pcmcia.o $(LIB): .depend $(OBJS) $(AR) crv $@ $(OBJS) diff --git a/board/netta/pcmcia.c b/board/netta/pcmcia.c new file mode 100644 index 0000000..a3709f7 --- /dev/null +++ b/board/netta/pcmcia.c @@ -0,0 +1,370 @@ +#include <common.h> +#include <mpc8xx.h> +#include <pcmcia.h> + +#undef CONFIG_PCMCIA + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#define CONFIG_PCMCIA +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#define CONFIG_PCMCIA +#endif + +#ifdef CONFIG_PCMCIA + +/* some sane bit macros */ +#define _BD(_b) (1U << (31-(_b))) +#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) + +#define _BW(_b) (1U << (15-(_b))) +#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) + +#define _BB(_b) (1U << (7-(_b))) +#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) + +#define _B(_b) _BD(_b) +#define _BR(_l, _h) _BDR(_l, _h) + +#define PCMCIA_BOARD_MSG "NETTA" + +static const unsigned short vppd_masks[2] = { _BW(14), _BW(15) }; + +static void cfg_vppd(int no) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask; + + if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0])) + return; + + mask = vppd_masks[no]; + + immap->im_ioport.iop_papar &= ~mask; + immap->im_ioport.iop_paodr &= ~mask; + immap->im_ioport.iop_padir |= mask; +} + +static void set_vppd(int no, int what) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask; + + if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0])) + return; + + mask = vppd_masks[no]; + + if (what) + immap->im_ioport.iop_padat |= mask; + else + immap->im_ioport.iop_padat &= ~mask; +} + +static const unsigned short vccd_masks[2] = { _BW(10), _BW(6) }; + +static void cfg_vccd(int no) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask; + + if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0])) + return; + + mask = vccd_masks[no]; + + immap->im_ioport.iop_papar &= ~mask; + immap->im_ioport.iop_paodr &= ~mask; + immap->im_ioport.iop_padir |= mask; +} + +static void set_vccd(int no, int what) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask; + + if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0])) + return; + + mask = vccd_masks[no]; + + if (what) + immap->im_ioport.iop_padat |= mask; + else + immap->im_ioport.iop_padat &= ~mask; +} + +static const unsigned short oc_mask = _BW(8); + +static void cfg_oc(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask = oc_mask; + + immap->im_ioport.iop_pcdir &= ~mask; + immap->im_ioport.iop_pcso &= ~mask; + immap->im_ioport.iop_pcint &= ~mask; + immap->im_ioport.iop_pcpar &= ~mask; +} + +static int get_oc(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask = oc_mask; + int what; + + what = !!(immap->im_ioport.iop_pcdat & mask);; + return what; +} + +static const unsigned short shdn_mask = _BW(12); + +static void cfg_shdn(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask; + + mask = shdn_mask; + + immap->im_ioport.iop_papar &= ~mask; + immap->im_ioport.iop_paodr &= ~mask; + immap->im_ioport.iop_padir |= mask; +} + +static void set_shdn(int what) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + unsigned short mask; + + mask = shdn_mask; + + if (what) + immap->im_ioport.iop_padat |= mask; + else + immap->im_ioport.iop_padat &= ~mask; +} + +static void cfg_ports (void) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + + immap = (immap_t *)CFG_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + + cfg_vppd(0); cfg_vppd(1); /* VPPD0,VPPD1 VAVPP => Hi-Z */ + cfg_vccd(0); cfg_vccd(1); /* 3V and 5V off */ + cfg_shdn(); + cfg_oc(); + + /* + * Configure Port A for TPS2211 PC-Card Power-Interface Switch + * + * Switch off all voltages, assert shutdown + */ + set_vppd(0, 1); set_vppd(1, 1); + set_vccd(0, 0); set_vccd(1, 0); + set_shdn(1); + + udelay(100000); +} + +int pcmcia_hardware_enable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, pipr, mask; + int i; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + udelay(10000); + + immap = (immap_t *)CFG_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ + cfg_ports (); + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); + pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(500); + + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { + printf (" No Card found\n"); + return (1); + } + + /* + * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z + */ + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + pipr = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + pipr, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); + + if ((pipr & mask) == mask) { + set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */ + set_vccd(0, 0); set_vccd(1, 1); /* 5V on, 3V off */ + puts (" 5.0V card found: "); + } else { + set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */ + set_vccd(0, 1); set_vccd(1, 0); /* 5V off, 3V on */ + puts (" 3.3V card found: "); + } + + /* Wait 500 ms; use this to check for over-current */ + for (i=0; i<5000; ++i) { + if (!get_oc()) { + printf (" *** Overcurrent - Safety shutdown ***\n"); + set_vccd(0, 0); set_vccd(1, 0); /* VAVPP => Hi-Z */ + return (1); + } + udelay (100); + } + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +int pcmcia_hardware_disable(int slot) +{ + volatile immap_t *immap; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + + /* Configure PCMCIA General Control Register */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + /* All voltages off / Hi-Z */ + set_vppd(0, 1); set_vppd(1, 1); + set_vccd(0, 1); set_vccd(1, 1); + + udelay(10000); + + return (0); +} +#endif /* CFG_CMD_PCMCIA */ + + +int pcmcia_voltage_set(int slot, int vcc, int vpp) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + ushort sreg; + + debug ("voltage_set: " + PCMCIA_BOARD_MSG + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + immap = (immap_t *)CFG_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Configure Port C pins for + * 5 Volts Enable and 3 Volts enable, + * Turn all power pins to Hi-Z + */ + debug ("PCMCIA power OFF\n"); + cfg_ports (); /* Enables switch, but all in Hi-Z */ + + sreg = immap->im_ioport.iop_pcdat; + set_vppd(0, 1); set_vppd(1, 1); + + switch(vcc) { + case 0: + break; /* Switch off */ + + case 33: + set_vccd(0, 1); set_vccd(1, 0); + break; + + case 50: + set_vccd(0, 0); set_vccd(1, 1); + break; + + default: + goto done; + } + + /* Checking supported voltages */ + + debug ("PIPR: 0x%x --> %s\n", + pcmp->pcmc_pipr, + (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); + +done: + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", + slot+'A'); + return (0); +} + +#endif /* CONFIG_PCMCIA */ diff --git a/board/ppmc7xx/config.mk b/board/ppmc7xx/config.mk index bcb6c81..b5b46dc 100644 --- a/board/ppmc7xx/config.mk +++ b/board/ppmc7xx/config.mk @@ -1,6 +1,6 @@ # # (C) Copyright 2005 -# Richard Danter, Wind River Systems +# Richard Danter, Wind River Systems # # (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -22,11 +22,6 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA -# - -# -# -# TEXT_BASE = 0xFFF00000 TEXT_END = 0xFFF40000 diff --git a/board/ppmc7xx/flash.c b/board/ppmc7xx/flash.c index 1cbcadc..4be6f13 100644 --- a/board/ppmc7xx/flash.c +++ b/board/ppmc7xx/flash.c @@ -1,10 +1,10 @@ /* * flash.c * ------- - * + * * Flash programming routines for the Wind River PPMC 74xx/7xx * based on flash.c from the TQM8260 board. - * + * * By Richard Danter (richard.danter@windriver.com) * Copyright (C) 2005 Wind River Systems */ @@ -27,13 +27,13 @@ void flash_reset (void) { unsigned long msr; DWORD cmd_reset = 0x00F000F000F000F0LL; - + if (flash_info[0].flash_id != FLASH_UNKNOWN) { msr = get_msr (); set_msr (msr | MSR_FP); write_via_fpu ((DWORD*)flash_info[0].start[0], &cmd_reset ); - + set_msr (msr); } } @@ -50,16 +50,16 @@ ulong flash_get_size (ulong baseaddr, flash_info_t * info) /* Enable FPU */ msr = get_msr (); - set_msr (msr | MSR_FP); - + set_msr (msr | MSR_FP); + /* Write auto-select command sequence */ write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[0] ); write_via_fpu ((DWORD*)(baseaddr + (0x02AA << 3)), &cmd_select[1] ); write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[2] ); - + /* Restore FPU */ set_msr (msr); - + /* Read manufacturer ID */ flashtest = *(volatile DWORD*)baseaddr; switch ((int)flashtest) { @@ -70,7 +70,7 @@ ulong flash_get_size (ulong baseaddr, flash_info_t * info) info->flash_id = FLASH_MAN_FUJ; break; default: - /* No, faulty or unknown flash */ + /* No, faulty or unknown flash */ info->flash_id = FLASH_UNKNOWN; info->sector_count = 0; info->size = 0; @@ -291,7 +291,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) DWORD cmd_erase[6] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL, 0x0080008000800080LL, 0x00AA00AA00AA00AALL, 0x0055005500550055LL, 0x0030003000300030LL }; - + if ((s_first < 0) || (s_first > s_last)) { if (info->flash_id == FLASH_UNKNOWN) { printf ("- missing\n"); @@ -319,7 +319,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* Enable FPU */ msr = get_msr(); set_msr ( msr | MSR_FP ); - + /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -344,7 +344,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* Restore FPU */ set_msr (msr); - + /* wait at least 80us - let's wait 1 ms */ udelay (1000); @@ -373,7 +373,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) DONE: /* reset to read mode */ flash_reset (); - + printf (" done\n"); return 0; } @@ -446,7 +446,7 @@ static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata) DWORD data; DWORD cmd_write[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL, 0x00A000A000A000A0LL }; - + for (data = 0, i = 0; i < 8; i++) data = (data << 8) + *pdata++; @@ -454,11 +454,11 @@ static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata) if ((*(DWORD*)dest & data) != data) { return (2); } - + /* Enable FPU */ msr = get_msr(); set_msr( msr | MSR_FP ); - + /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -473,7 +473,7 @@ static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata) /* Restore FPU */ set_msr(msr); - + /* data polling for D7 */ start = get_timer (0); while (*(volatile DWORD*)dest != data ) { diff --git a/board/ppmc7xx/init.S b/board/ppmc7xx/init.S index e4ed7a6..99a818a 100644 --- a/board/ppmc7xx/init.S +++ b/board/ppmc7xx/init.S @@ -21,314 +21,314 @@ board_asm_init: ori r4,r4,0x0000 lis r5,0xFEE0 ori r5,r5,0x0000 - lis r3,0x8000 # ADDR_00 + lis r3,0x8000 # ADDR_00 ori r3,r3,0x0000 stwbrx r3,0,r4 - li r3,0x1057 # VENDOR + li r3,0x1057 # VENDOR li r8, 0x0 sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_02 + lis r3,0x8000 # ADDR_02 ori r3,r3,0x0002 stwbrx r3,0,r4 - li r3,0x0004 # ID + li r3,0x0004 # ID li r8, 0x2 sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_04 + lis r3,0x8000 # ADDR_04 ori r3,r3,0x0004 stwbrx r3,0,r4 - li r3,0x0006 # PCICMD + li r3,0x0006 # PCICMD li r8, 0x0 sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_06 + lis r3,0x8000 # ADDR_06 ori r3,r3,0x0006 stwbrx r3,0,r4 - li r3,0x00A0 # PCISTAT + li r3,0x00A0 # PCISTAT li r8, 0x2 sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_08 + lis r3,0x8000 # ADDR_08 ori r3,r3,0x0008 stwbrx r3,0,r4 - li r3,0x10 # REVID + li r3,0x10 # REVID stb r3,0x0(r5) - lis r3,0x8000 # ADDR_09 + lis r3,0x8000 # ADDR_09 ori r3,r3,0x0009 stwbrx r3,0,r4 - li r3,0x00 # PROGIR + li r3,0x00 # PROGIR stb r3,0x1(r5) - lis r3,0x8000 # ADDR_0A + lis r3,0x8000 # ADDR_0A ori r3,r3,0x000A stwbrx r3,0,r4 - li r3,0x00 # SUBCCODE + li r3,0x00 # SUBCCODE stb r3,0x2(r5) - lis r3,0x8000 # ADDR_0B + lis r3,0x8000 # ADDR_0B ori r3,r3,0x000B stwbrx r3,0,r4 - li r3,0x06 # PBCCR + li r3,0x06 # PBCCR stb r3,0x3(r5) - lis r3,0x8000 # ADDR_0C + lis r3,0x8000 # ADDR_0C ori r3,r3,0x000C stwbrx r3,0,r4 - li r3,0x08 # PCLSR + li r3,0x08 # PCLSR stb r3,0x0(r5) - lis r3,0x8000 # ADDR_0D + lis r3,0x8000 # ADDR_0D ori r3,r3,0x000D stwbrx r3,0,r4 - li r3,0x00 # PLTR + li r3,0x00 # PLTR stb r3,0x1(r5) - lis r3,0x8000 # ADDR_0E + lis r3,0x8000 # ADDR_0E ori r3,r3,0x000E stwbrx r3,0,r4 - li r3,0x00 # HEADTYPE + li r3,0x00 # HEADTYPE stb r3,0x2(r5) - lis r3,0x8000 # ADDR_0F + lis r3,0x8000 # ADDR_0F ori r3,r3,0x000F stwbrx r3,0,r4 - li r3,0x00 # BISTCTRL + li r3,0x00 # BISTCTRL stb r3,0x3(r5) - lis r3,0x8000 # ADDR_10 + lis r3,0x8000 # ADDR_10 ori r3,r3,0x0010 stwbrx r3,0,r4 - lis r3,0x0000 # LMBAR + lis r3,0x0000 # LMBAR ori r3,r3,0x0008 li r8, 0x0 stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_14 + lis r3,0x8000 # ADDR_14 ori r3,r3,0x0014 stwbrx r3,0,r4 - lis r3,0xF000 # PCSRBAR + lis r3,0xF000 # PCSRBAR ori r3,r3,0x0000 li r8, 0x0 stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_3C + lis r3,0x8000 # ADDR_3C ori r3,r3,0x003C stwbrx r3,0,r4 - li r3,0x00 # ILR + li r3,0x00 # ILR stb r3,0x0(r5) - lis r3,0x8000 # ADDR_3D + lis r3,0x8000 # ADDR_3D ori r3,r3,0x003D stwbrx r3,0,r4 - li r3,0x01 # INTPIN + li r3,0x01 # INTPIN stb r3,0x1(r5) - lis r3,0x8000 # ADDR_3E + lis r3,0x8000 # ADDR_3E ori r3,r3,0x003E stwbrx r3,0,r4 - li r3,0x00 # MIN_GNT + li r3,0x00 # MIN_GNT stb r3,0x2(r5) - lis r3,0x8000 # ADDR_3F + lis r3,0x8000 # ADDR_3F ori r3,r3,0x003F stwbrx r3,0,r4 - li r3,0x00 # MAX_LAT + li r3,0x00 # MAX_LAT stb r3,0x3(r5) - lis r3,0x8000 # ADDR_40 + lis r3,0x8000 # ADDR_40 ori r3,r3,0x0040 stwbrx r3,0,r4 - li r3,0x00 # BUSNB + li r3,0x00 # BUSNB stb r3,0x0(r5) - lis r3,0x8000 # ADDR_41 + lis r3,0x8000 # ADDR_41 ori r3,r3,0x0041 stwbrx r3,0,r4 - li r3,0x00 # SBUSNB + li r3,0x00 # SBUSNB stb r3,0x1(r5) - lis r3,0x8000 # ADDR_46 + lis r3,0x8000 # ADDR_46 ori r3,r3,0x0046 stwbrx r3,0,r4 -# li r3,0xE080 # PCIARB - li r3,-0x1F80 # PCIARB +# li r3,0xE080 # PCIARB + li r3,-0x1F80 # PCIARB li r8, 0x2 sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_70 + lis r3,0x8000 # ADDR_70 ori r3,r3,0x0070 stwbrx r3,0,r4 - li r3,0x0000 # PMCR1 + li r3,0x0000 # PMCR1 li r8, 0x0 sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_72 + lis r3,0x8000 # ADDR_72 ori r3,r3,0x0072 stwbrx r3,0,r4 - li r3,0xC0 # PMCR2 + li r3,0xC0 # PMCR2 stb r3,0x2(r5) - lis r3,0x8000 # ADDR_73 + lis r3,0x8000 # ADDR_73 ori r3,r3,0x0073 stwbrx r3,0,r4 - li r3,0xEF # ODCR + li r3,0xEF # ODCR stb r3,0x3(r5) - lis r3,0x8000 # ADDR_74 + lis r3,0x8000 # ADDR_74 ori r3,r3,0x0074 stwbrx r3,0,r4 - li r3,0x7D00 # CLKDCR + li r3,0x7D00 # CLKDCR li r8, 0x0 sthbrx r3,r8,r5 - lis r3,0x8000 # ADDR_76 + lis r3,0x8000 # ADDR_76 ori r3,r3,0x0076 stwbrx r3,0,r4 - li r3,0x00 # MDCR + li r3,0x00 # MDCR stb r3,0x2(r5) lis r6,0xFCE0 ori r6,r6,0x0000 # r6 is the EUMBAR Base Address - lis r3,0x8000 # ADDR_78 + lis r3,0x8000 # ADDR_78 ori r3,r3,0x0078 stwbrx r3,0,r4 - lis r3,0xFCE0 # EUMBBAR + lis r3,0xFCE0 # EUMBBAR ori r3,r3,0x0000 li r8, 0x0 stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_80 + lis r3,0x8000 # ADDR_80 ori r3,r3,0x0080 stwbrx r3,0,r4 - lis r3,0xFFFF # MSADDR1 + lis r3,0xFFFF # MSADDR1 ori r3,r3,0x4000 li r8, 0x0 stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_84 + lis r3,0x8000 # ADDR_84 ori r3,r3,0x0084 stwbrx r3,0,r4 - lis r3,0xFFFF # MSADDR2 + lis r3,0xFFFF # MSADDR2 ori r3,r3,0xFFFF li r8, 0x0 stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_88 + lis r3,0x8000 # ADDR_88 ori r3,r3,0x0088 stwbrx r3,0,r4 - lis r3,0x0303 # EMSADDR1 + lis r3,0x0303 # EMSADDR1 ori r3,r3,0x0000 li r8, 0x0 stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_8C + lis r3,0x8000 # ADDR_8C ori r3,r3,0x008C stwbrx r3,0,r4 - lis r3,0x0303 # EMSADDR2 + lis r3,0x0303 # EMSADDR2 ori r3,r3,0x0303 li r8, 0x0 stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_90 + lis r3,0x8000 # ADDR_90 ori r3,r3,0x0090 stwbrx r3,0,r4 - lis r3,0xFFFF # EMEADDR1 + lis r3,0xFFFF # EMEADDR1 ori r3,r3,0x7F3F li r8, 0x0 stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_94 + lis r3,0x8000 # ADDR_94 ori r3,r3,0x0094 stwbrx r3,0,r4 - lis r3,0xFFFF # EMEADDR2 + lis r3,0xFFFF # EMEADDR2 ori r3,r3,0xFFFF li r8, 0x0 stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_98 + lis r3,0x8000 # ADDR_98 ori r3,r3,0x0098 stwbrx r3,0,r4 - lis r3,0x0303 # EXTEMEM1 + lis r3,0x0303 # EXTEMEM1 ori r3,r3,0x0000 li r8, 0x0 stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_9C + lis r3,0x8000 # ADDR_9C ori r3,r3,0x009C stwbrx r3,0,r4 - lis r3,0x0303 # EXTEMEM2 + lis r3,0x0303 # EXTEMEM2 ori r3,r3,0x0303 li r8, 0x0 stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_A0 + lis r3,0x8000 # ADDR_A0 ori r3,r3,0x00A0 stwbrx r3,0,r4 - li r3,0x03 # MEMBNKEN + li r3,0x03 # MEMBNKEN stb r3,0x0(r5) - lis r3,0x8000 # ADDR_A3 + lis r3,0x8000 # ADDR_A3 ori r3,r3,0x00A3 stwbrx r3,0,r4 - li r3,0x00 # MEMPMODE + li r3,0x00 # MEMPMODE stb r3,0x3(r5) - lis r3,0x8000 # ADDR_B8 + lis r3,0x8000 # ADDR_B8 ori r3,r3,0x00B8 stwbrx r3,0,r4 - li r3,0x00 # ECCCNT + li r3,0x00 # ECCCNT stb r3,0x0(r5) - lis r3,0x8000 # ADDR_B9 + lis r3,0x8000 # ADDR_B9 ori r3,r3,0x00B9 stwbrx r3,0,r4 - li r3,0x00 # ECCTRG + li r3,0x00 # ECCTRG stb r3,0x1(r5) - lis r3,0x8000 # ADDR_C0 + lis r3,0x8000 # ADDR_C0 ori r3,r3,0x00C0 stwbrx r3,0,r4 - li r3,0xFF # ERRENR1 + li r3,0xFF # ERRENR1 stb r3,0x0(r5) - lis r3,0x8000 # ADDR_C1 + lis r3,0x8000 # ADDR_C1 ori r3,r3,0x00C1 stwbrx r3,0,r4 - li r3,0x00 # ERRDR1 + li r3,0x00 # ERRDR1 stb r3,0x1(r5) - lis r3,0x8000 # ADDR_C3 + lis r3,0x8000 # ADDR_C3 ori r3,r3,0x00C3 stwbrx r3,0,r4 - li r3,0x50 # IPBESR + li r3,0x50 # IPBESR stb r3,0x3(r5) - lis r3,0x8000 # ADDR_C4 + lis r3,0x8000 # ADDR_C4 ori r3,r3,0x00C4 stwbrx r3,0,r4 - li r3,0xBF # ERRENR2 + li r3,0xBF # ERRENR2 stb r3,0x0(r5) - lis r3,0x8000 # ADDR_C5 + lis r3,0x8000 # ADDR_C5 ori r3,r3,0x00C5 stwbrx r3,0,r4 - li r3,0x00 # ERRDR2 + li r3,0x00 # ERRDR2 stb r3,0x1(r5) - lis r3,0x8000 # ADDR_C7 + lis r3,0x8000 # ADDR_C7 ori r3,r3,0x00C7 stwbrx r3,0,r4 - li r3,0x00 # PCIBESR + li r3,0x00 # PCIBESR stb r3,0x3(r5) - lis r3,0x8000 # ADDR_C8 + lis r3,0x8000 # ADDR_C8 ori r3,r3,0x00C8 stwbrx r3,0,r4 - lis r3,0x0000 # BERRADDR + lis r3,0x0000 # BERRADDR ori r3,r3,0xE0FE li r8, 0x0 stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_E0 + lis r3,0x8000 # ADDR_E0 ori r3,r3,0x00E0 stwbrx r3,0,r4 - li r3,0xC0 # AMBOR + li r3,0xC0 # AMBOR stb r3,0x0(r5) - lis r3,0x8000 # ADDR_F4 + lis r3,0x8000 # ADDR_F4 ori r3,r3,0x00F4 stwbrx r3,0,r4 - lis r3,0x0000 # MCCR2 + lis r3,0x0000 # MCCR2 ori r3,r3,0x020C li r8, 0x0 stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_F8 + lis r3,0x8000 # ADDR_F8 ori r3,r3,0x00F8 stwbrx r3,0,r4 - lis r3,0x0230 # MCCR3 + lis r3,0x0230 # MCCR3 ori r3,r3,0x0000 li r8, 0x0 stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_FC + lis r3,0x8000 # ADDR_FC ori r3,r3,0x00FC stwbrx r3,0,r4 - lis r3,0x2532 # MCCR4 + lis r3,0x2532 # MCCR4 ori r3,r3,0x2220 li r8, 0x0 stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_F0 + lis r3,0x8000 # ADDR_F0 ori r3,r3,0x00F0 stwbrx r3,0,r4 - lis r3,0xFFC8 # MCCR1 + lis r3,0xFFC8 # MCCR1 ori r3,r3,0x0000 li r8, 0x0 stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_A8 + lis r3,0x8000 # ADDR_A8 ori r3,r3,0x00A8 stwbrx r3,0,r4 - lis r3,0xFF14 # PICR1 + lis r3,0xFF14 # PICR1 ori r3,r3,0x1CC8 li r8, 0x0 stwbrx r3,r8,r5 - lis r3,0x8000 # ADDR_AC + lis r3,0x8000 # ADDR_AC ori r3,r3,0x00AC stwbrx r3,0,r4 - lis r3,0x0000 # PICR2 + lis r3,0x0000 # PICR2 ori r3,r3,0x0000 li r8, 0x0 stwbrx r3,r8,r5 diff --git a/board/ppmc7xx/ppmc7xx.c b/board/ppmc7xx/ppmc7xx.c index 0597c72..402ac5e 100644 --- a/board/ppmc7xx/ppmc7xx.c +++ b/board/ppmc7xx/ppmc7xx.c @@ -1,9 +1,9 @@ /* * ppmc7xx.c * --------- - * + * * Main board-specific routines for Wind River PPMC 7xx/74xx board. - * + * * By Richard Danter (richard.danter@windriver.com) * Copyright (C) 2005 Wind River Systems */ @@ -24,7 +24,7 @@ extern void _start_warm(void); /* * initdram() - * + * * This function normally initialises the (S)DRAM of the system. For this board * the SDRAM was already initialised by board_asm_init (see init.S) so we just * return the size of RAM. @@ -37,12 +37,12 @@ long initdram( int board_type ) /* * after_reloc() - * + * * This is called after U-Boot has been copied from Flash/ROM to RAM. It gives * us an opportunity to do some additional setup before the rest of the system * is initialised. We don't need to do anything, so we just call board_init_r() * which should never return. - */ + */ void after_reloc( ulong dest_addr, gd_t* gd ) { /* Jump to the main U-Boot board init code */ @@ -52,7 +52,7 @@ void after_reloc( ulong dest_addr, gd_t* gd ) /* * checkboard() - * + * * We could do some board level checks here, such as working out what version * it is, but for this board we simply display it's name (on the console). */ @@ -65,7 +65,7 @@ int checkboard( void ) /* * misc_init_r - * + * * Used for other setup which needs to be done late in the bring-up phase. */ int misc_init_r( void ) @@ -78,27 +78,27 @@ int misc_init_r( void ) /* Enable the I-Cache */ icache_enable(); - + return 0; } /* * do_reset() - * + * * Shell command to reset the board. */ void do_reset( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) { printf( "Resetting...\n" ); - + /* Disabe and invalidate cache */ icache_disable(); dcache_disable(); /* Jump to warm start (in RAM) */ _start_warm(); - + /* Should never get here */ while(1); } diff --git a/board/r360mpi/Makefile b/board/r360mpi/Makefile index 13ce9fc..1a7e7a6 100644 --- a/board/r360mpi/Makefile +++ b/board/r360mpi/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o pcmcia.o $(LIB): .depend $(OBJS) $(AR) crv $@ $(OBJS) diff --git a/board/r360mpi/pcmcia.c b/board/r360mpi/pcmcia.c new file mode 100644 index 0000000..7d34ac8 --- /dev/null +++ b/board/r360mpi/pcmcia.c @@ -0,0 +1,236 @@ +#include <common.h> +#include <mpc8xx.h> +#include <pcmcia.h> + +#undef CONFIG_PCMCIA + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#define CONFIG_PCMCIA +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#define CONFIG_PCMCIA +#endif + +#ifdef CONFIG_PCMCIA + +#define PCMCIA_BOARD_MSG "R360MPI" + +int pcmcia_hardware_enable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, mask; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + udelay(10000); + + immap = (immap_t *)CFG_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ + sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); + pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Configure Ports A, B & C pins for + * 5 Volts Enable and 3 Volts enable + */ + immap->im_ioport.iop_pcpar &= ~(0x0400); + immap->im_ioport.iop_pcso &= ~(0x0400);/* + immap->im_ioport.iop_pcdir |= 0x0400;*/ + + immap->im_ioport.iop_papar &= ~(0x0200);/* + immap->im_ioport.iop_padir |= 0x0200;*/ +#if 0 + immap->im_ioport.iop_pbpar &= ~(0xC000); + immap->im_ioport.iop_pbdir &= ~(0xC000); +#endif + /* remove all power */ + + immap->im_ioport.iop_pcdat |= 0x0400; + immap->im_ioport.iop_padat |= 0x0200; + + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { + printf (" No Card found\n"); + return (1); + } + + /* + * Power On. + */ + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + reg = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + reg, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); + if ((reg & mask) == mask) { + immap->im_ioport.iop_pcdat &= ~(0x4000); + puts (" 5.0V card found: "); + } else { + immap->im_ioport.iop_padat &= ~(0x0002); + puts (" 3.3V card found: "); + } + immap->im_ioport.iop_pcdir |= 0x0400; + immap->im_ioport.iop_padir |= 0x0200; +#if 0 + /* VCC switch error flag, PCMCIA slot INPACK_ pin */ + cp->cp_pbdir &= ~(0x0020 | 0x0010); + cp->cp_pbpar &= ~(0x0020 | 0x0010); + udelay(500000); +#endif + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +int pcmcia_hardware_disable(int slot) +{ + volatile immap_t *immap; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + + /* remove all power */ + immap->im_ioport.iop_pcdat |= 0x0400; + immap->im_ioport.iop_padat |= 0x0200; + + /* Configure PCMCIA General Control Register */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(10000); + + return (0); +} +#endif /* CFG_CMD_PCMCIA */ + + +int pcmcia_voltage_set(int slot, int vcc, int vpp) +{ + volatile immap_t *immap; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("voltage_set: " + PCMCIA_BOARD_MSG + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Configure Ports A & C pins for + * 5 Volts Enable and 3 Volts enable, + * Turn off all power + */ + debug ("PCMCIA power OFF\n"); + immap->im_ioport.iop_pcpar &= ~(0x0400); + immap->im_ioport.iop_pcso &= ~(0x0400);/* + immap->im_ioport.iop_pcdir |= 0x0400;*/ + + immap->im_ioport.iop_papar &= ~(0x0200);/* + immap->im_ioport.iop_padir |= 0x0200;*/ + + immap->im_ioport.iop_pcdat |= 0x0400; + immap->im_ioport.iop_padat |= 0x0200; + + reg = 0; + switch(vcc) { + case 0: break; + case 33: reg |= 0x0200; break; + case 50: reg |= 0x0400; break; + default: goto done; + } + + /* Checking supported voltages */ + + debug ("PIPR: 0x%x --> %s\n", + pcmp->pcmc_pipr, + (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); + + if (reg & 0x0200) + immap->im_ioport.iop_pcdat &= !reg; + if (reg & 0x0400) + immap->im_ioport.iop_padat &= !reg; + immap->im_ioport.iop_pcdir |= 0x0200; + immap->im_ioport.iop_padir |= 0x0400; + if (reg) { + debug ("PCMCIA powered at %sV\n", + (reg&0x0400) ? "5.0" : "3.3"); + } else { + debug ("PCMCIA powered down\n"); + } + +done: + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", + slot+'A'); + return (0); +} + +#endif /* CCONFIG_PCMCIA */ diff --git a/board/sbc2410x/Makefile b/board/sbc2410x/Makefile new file mode 100644 index 0000000..ae8665e --- /dev/null +++ b/board/sbc2410x/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := sbc2410x.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/sbc2410x/config.mk b/board/sbc2410x/config.mk new file mode 100644 index 0000000..f244e64 --- /dev/null +++ b/board/sbc2410x/config.mk @@ -0,0 +1,23 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj@denx.de> +# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> +# +# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu +# +# see http://www.samsung.com/ for more information on SAMSUNG +# + +# +# SMDK2410 has 1 bank of 64 MB DRAM +# +# 3000'0000 to 3400'0000 +# +# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 +# optionally with a ramdisk at 3080'0000 +# +# we load ourself to 33F8'0000 +# +# download area is 3300'0000 + +TEXT_BASE = 0x33F80000 diff --git a/board/sbc2410x/flash.c b/board/sbc2410x/flash.c new file mode 100644 index 0000000..f2718f2 --- /dev/null +++ b/board/sbc2410x/flash.c @@ -0,0 +1,431 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +ulong myflush (void); + +#define FLASH_BANK_SIZE PHYS_FLASH_SIZE +#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +#define CMD_READ_ARRAY 0x000000F0 +#define CMD_UNLOCK1 0x000000AA +#define CMD_UNLOCK2 0x00000055 +#define CMD_ERASE_SETUP 0x00000080 +#define CMD_ERASE_CONFIRM 0x00000030 +#define CMD_PROGRAM 0x000000A0 +#define CMD_UNLOCK_BYPASS 0x00000020 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1))) + +#define BIT_ERASE_DONE 0x00000080 +#define BIT_RDY_MASK 0x00000080 +#define BIT_PROGRAM_ERROR 0x00000020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + +/*----------------------------------------------------------------------- + */ + +ulong flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_info[i].flash_id = +#if defined(CONFIG_AMD_LV400) + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV400B & FLASH_TYPEMASK); +#elif defined(CONFIG_AMD_LV800) + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV800B & FLASH_TYPEMASK); +#else +#error "Unknown flash configured" +#endif + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic ("configured too many flash banks!\n"); + for (j = 0; j < flash_info[i].sector_count; j++) { + if (j <= 3) { + /* 1st one is 16 KB */ + if (j == 0) { + flash_info[i].start[j] = + flashbase + 0; + } + + /* 2nd and 3rd are both 8 KB */ + if ((j == 1) || (j == 2)) { + flash_info[i].start[j] = + flashbase + 0x4000 + (j - + 1) * + 0x2000; + } + + /* 4th 32 KB */ + if (j == 3) { + flash_info[i].start[j] = + flashbase + 0x8000; + } + } else { + flash_info[i].start[j] = + flashbase + (j - 3) * MAIN_SECT_SIZE; + } + } + size += flash_info[i].size; + } + + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (AMD_MANUFACT & FLASH_VENDMASK): + printf ("AMD: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_LV400B & FLASH_TYPEMASK): + printf ("1x Amd29LV400BB (4Mbit)\n"); + break; + case (AMD_ID_LV800B & FLASH_TYPEMASK): + printf ("1x Amd29LV800BB (8Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + + Done:; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + ushort result; + int iflag, cflag, prot, sect; + int rc = ERR_OK; + int chip; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (AMD_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + if (info->protect[sect] == 0) { /* not protected */ + vu_short *addr = (vu_short *) (info->start[sect]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + chip = 0; + + do { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > + CFG_FLASH_ERASE_TOUT) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + chip = TMO; + break; + } + + if (!chip + && (result & 0xFFFF) & BIT_ERASE_DONE) + chip = READY; + + if (!chip + && (result & 0xFFFF) & BIT_PROGRAM_ERROR) + chip = ERR; + + } while (!chip); + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (chip == ERR) { + rc = ERR_PROG_ERROR; + goto outahere; + } + if (chip == TMO) { + rc = ERR_TIMOUT; + goto outahere; + } + + printf ("ok.\n"); + } else { /* it was protected */ + + printf ("protected!\n"); + } + } + + if (ctrlc ()) + printf ("User Interrupt!\n"); + + outahere: + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +volatile static int write_hword (flash_info_t * info, ulong dest, ushort data) +{ + vu_short *addr = (vu_short *) dest; + ushort result; + int rc = ERR_OK; + int cflag, iflag; + int chip; + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS; + *addr = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait until flash is ready */ + chip = 0; + do { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + chip = ERR | TMO; + break; + } + if (!chip && ((result & 0x80) == (data & 0x80))) + chip = READY; + + if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { + result = *addr; + + if ((result & 0x80) == (data & 0x80)) + chip = READY; + else + chip = ERR; + } + + } while (!chip); + + *addr = CMD_READ_ARRAY; + + if (chip == ERR || *addr != data) + rc = ERR_PROG_ERROR; + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + int l; + int i, rc; + ushort data; + + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + for (; i < 2 && cnt > 0; ++i) { + data = (data >> 8) | (*src++ << 8); + --cnt; + ++cp; + } + for (; cnt == 0 && i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + if ((rc = write_hword (info, wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* + * handle word aligned part + */ + while (cnt >= 2) { + data = *((vu_short *) src); + if ((rc = write_hword (info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 0) { + return ERR_OK; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + return write_hword (info, wp, data); +} diff --git a/board/sbc2410x/lowlevel_init.S b/board/sbc2410x/lowlevel_init.S new file mode 100644 index 0000000..3df63cd --- /dev/null +++ b/board/sbc2410x/lowlevel_init.S @@ -0,0 +1,163 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * Modified for the Samsung SMDK2410 by + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> + * + * Modified for the friendly-arm SBC-2410X by + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +/* + * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S + * + * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com> + */ + +#define BWSCON 0x48000000 + +/* BWSCON */ +#define DW8 (0x0) +#define DW16 (0x1) +#define DW32 (0x2) +#define WAIT (0x1<<2) +#define UBLB (0x1<<3) + +#define B1_BWSCON (DW16) +#define B2_BWSCON (DW16) +#define B3_BWSCON (DW16 + WAIT + UBLB) +#define B4_BWSCON (DW16) +#define B5_BWSCON (DW16) +#define B6_BWSCON (DW32) +#define B7_BWSCON (DW32) + +#define B0_Tacs 0x0 +#define B0_Tcos 0x0 +#define B0_Tacc 0x7 +#define B0_Tcoh 0x0 +#define B0_Tah 0x0 +#define B0_Tacp 0x0 +#define B0_PMC 0x0 + +#define B1_Tacs 0x0 +#define B1_Tcos 0x0 +#define B1_Tacc 0x7 +#define B1_Tcoh 0x0 +#define B1_Tah 0x0 +#define B1_Tacp 0x0 +#define B1_PMC 0x0 + +#define B2_Tacs 0x0 +#define B2_Tcos 0x0 +#define B2_Tacc 0x7 +#define B2_Tcoh 0x0 +#define B2_Tah 0x0 +#define B2_Tacp 0x0 +#define B2_PMC 0x0 + +#define B3_Tacs 0xc +#define B3_Tcos 0x7 +#define B3_Tacc 0xf +#define B3_Tcoh 0x1 +#define B3_Tah 0x0 +#define B3_Tacp 0x0 +#define B3_PMC 0x0 + +#define B4_Tacs 0x0 +#define B4_Tcos 0x0 +#define B4_Tacc 0x7 +#define B4_Tcoh 0x0 +#define B4_Tah 0x0 +#define B4_Tacp 0x0 +#define B4_PMC 0x0 + +#define B5_Tacs 0xc +#define B5_Tcos 0x7 +#define B5_Tacc 0xf +#define B5_Tcoh 0x1 +#define B5_Tah 0x0 +#define B5_Tacp 0x0 +#define B5_PMC 0x0 + +#define B6_MT 0x3 /* SDRAM */ +#define B6_Trcd 0x1 +#define B6_SCAN 0x1 /* 9bit */ + +#define B7_MT 0x3 /* SDRAM */ +#define B7_Trcd 0x1 /* 3clk */ +#define B7_SCAN 0x1 /* 9bit */ + +/* REFRESH parameter */ +#define REFEN 0x1 /* Refresh enable */ +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ +#define Trp 0x0 /* 2clk */ +#define Trc 0x3 /* 7clk */ +#define Tchr 0x2 /* 3clk */ +#define REFCNT 0x0459 +/**************************************/ + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + /* memory control configuration */ + /* make r0 relative the current location so that it */ + /* reads SMRDATA out of FLASH rather than memory ! */ + ldr r0, =SMRDATA + ldr r1, _TEXT_BASE + sub r0, r0, r1 + ldr r1, =BWSCON /* Bus Width Status Controller */ + add r2, r0, #13*4 +0: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r2, r0 + bne 0b + + /* everything is fine now */ + mov pc, lr + + .ltorg +/* the literal pools origin */ + +SMRDATA: + .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) + .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) + .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) + .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) + .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) + .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) + .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) + .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) + .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) + .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) + .word 0xb2 + .word 0x30 + .word 0x30 diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c new file mode 100644 index 0000000..7030985 --- /dev/null +++ b/board/sbc2410x/sbc2410x.c @@ -0,0 +1,183 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> + * + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <s3c2410.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include <linux/mtd/nand.h> +#endif + +/* ------------------------------------------------------------------------- */ + +#define FCLK_SPEED 1 + +#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ +#define M_MDIV 0xC3 +#define M_PDIV 0x4 +#define M_SDIV 0x1 +#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ +#define M_MDIV 0x5c +#define M_PDIV 0x4 +#define M_SDIV 0x0 +#endif + +#define USB_CLOCK 1 + +#if USB_CLOCK==0 +#define U_M_MDIV 0xA1 +#define U_M_PDIV 0x3 +#define U_M_SDIV 0x1 +#elif USB_CLOCK==1 +#define U_M_MDIV 0x48 +#define U_M_PDIV 0x3 +#define U_M_SDIV 0x2 +#endif + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + /* to reduce PLL lock time, adjust the LOCKTIME register */ + clk_power->LOCKTIME = 0xFFFFFF; + + /* configure MPLL */ + clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + + /* some delay between MPLL and UPLL */ + delay (4000); + + /* configure UPLL */ + clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + + /* some delay between MPLL and UPLL */ + delay (8000); + + /* set up the I/O ports */ + gpio->GPACON = 0x007FFFFF; + gpio->GPBCON = 0x00044556; + gpio->GPBUP = 0x000007FF; + gpio->GPCCON = 0xAAAAAAAA; + gpio->GPCUP = 0x0000FFFF; + gpio->GPDCON = 0xAAAAAAAA; + gpio->GPDUP = 0x0000FFFF; + gpio->GPECON = 0xAAAAAAAA; + gpio->GPEUP = 0x0000FFFF; + gpio->GPFCON = 0x000055AA; + gpio->GPFUP = 0x000000FF; + gpio->GPGCON = 0xFF95FF3A; + gpio->GPGUP = 0x0000FFFF; + gpio->GPHCON = 0x0016FAAA; + gpio->GPHUP = 0x000007FF; + + gpio->EXTINT0=0x22222222; + gpio->EXTINT1=0x22222222; + gpio->EXTINT2=0x22222222; + + /* arch number of SMDK2410-Board */ + gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x30000100; + + icache_enable(); + dcache_enable(); + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +extern ulong nand_probe(ulong physadr); + +static inline void NF_Reset(void) +{ + int i; + + NF_SetCE(NFCE_LOW); + NF_Cmd(0xFF); /* reset command */ + for(i = 0; i < 10; i++); /* tWB = 100ns. */ + NF_WaitRB(); /* wait 200~500us; */ + NF_SetCE(NFCE_HIGH); +} + +static inline void NF_Init(void) +{ +#if 1 +#define TACLS 0 +#define TWRPH0 3 +#define TWRPH1 0 +#else +#define TACLS 0 +#define TWRPH0 4 +#define TWRPH1 2 +#endif + + NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0)); + /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */ + /* 1 1 1 1, 1 xxx, r xxx, r xxx */ + /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */ + + NF_Reset(); +} + +void nand_init(void) +{ + S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); + + NF_Init(); +#ifdef DEBUG + printf("NAND flash probing at 0x%.8lX\n", (ulong)nand); +#endif + printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20); +} +#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */ diff --git a/board/sbc2410x/u-boot.lds b/board/sbc2410x/u-boot.lds new file mode 100644 index 0000000..76df6b2 --- /dev/null +++ b/board/sbc2410x/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/spc1920/Makefile b/board/spc1920/Makefile new file mode 100644 index 0000000..47afef7 --- /dev/null +++ b/board/spc1920/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/spc1920/config.mk b/board/spc1920/config.mk new file mode 100644 index 0000000..e361694 --- /dev/null +++ b/board/spc1920/config.mk @@ -0,0 +1,35 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and +# MPC885ADS boards +# + +#TEXT_BASE = 0xFE000000 +TEXT_BASE = 0xFFF00000 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/spc1920 +HOST_CFLAGS += -I$(TOPDIR)/board/spc1920 +HOST_ENVIRO_CFLAGS += -I$(TOPDIR)/board/spc1920 diff --git a/board/spc1920/pld.h b/board/spc1920/pld.h new file mode 100644 index 0000000..3254f82 --- /dev/null +++ b/board/spc1920/pld.h @@ -0,0 +1,14 @@ +#ifndef __PLD_H__ +#define __PLD_H__ + +typedef struct spc1920_pld { + uchar com1_en; + uchar dsp_reset; + uchar dsp_hpi_on; + uchar codec_dsp_power_en; + uchar clk2_en; + uchar clk3_select; + uchar clk4_select; +} spc1920_pld_t; + +#endif /* __PLD_H__ */ diff --git a/board/spc1920/spc1920.c b/board/spc1920/spc1920.c new file mode 100644 index 0000000..028f4c6 --- /dev/null +++ b/board/spc1920/spc1920.c @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <mpc8xx.h> +#include "pld.h" + +#define _NOT_USED_ 0xFFFFFFFF +/* #define debug(fmt,args...) printf (fmt ,##args) */ + +static long int dram_size (long int, long int *, long int); + +const uint sdram_table[] = { + /* + * Single Read. (Offset 0 in UPMB RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, + 0x1FF77C47, /* last */ + /* + * SDRAM Initialization (offset 5 in UPMB RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ + /* + * Burst Read. (Offset 8 in UPMB RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPMB RAM) + */ + 0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPMB RAM) + */ + 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPMB RAM) + */ + 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPMB RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +long int initdram (int board_type) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + /* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE; */ + + long int size_b0; + long int size8, size9; + int i; + + /* + * Configure UPMB for SDRAM + */ + upmconfig (UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); + + udelay(100); + + memctl->memc_mptpr = CFG_MPTPR; + + /* burst length=4, burst type=sequential, CAS latency=2 */ + memctl->memc_mar = CFG_MAR; + + /* + * Map controller bank 1 to the SDRAM bank at preliminary address. + */ + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; + + /* initialize memory address register */ + memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */ + + /* mode initialization (offset 5) */ + udelay (200); /* 0x80006105 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x05); + + /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ + udelay (1); /* 0x80006130 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30); + udelay (1); /* 0x80006130 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30); + udelay (1); /* 0x80006106 */ + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x06); + + memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */ + + udelay (200); + + /* Need at least 10 DRAM accesses to stabilize */ + for (i = 0; i < 10; ++i) { + volatile unsigned long *addr = + (volatile unsigned long *) CFG_SDRAM_BASE; + unsigned long val; + + val = *(addr + i); + *(addr + i) = val; + } + + /* + * Check Bank 0 Memory Size for re-configuration + * + * try 8 column mode + */ + size8 = dram_size (CFG_MBMR_8COL, (long *)CFG_SDRAM_BASE, SDRAM_MAX_SIZE); + + udelay (1000); + + /* + * try 9 column mode + */ + size9 = dram_size (CFG_MBMR_9COL, (long *)CFG_SDRAM_BASE, SDRAM_MAX_SIZE); + + if (size8 < size9) { /* leave configuration at 9 columns */ + size_b0 = size9; + memctl->memc_mbmr = CFG_MBMR_9COL | MBMR_PTBE; + udelay (500); + } else { /* back to 8 columns */ + size_b0 = size8; + memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE; + udelay (500); + } + + /* + * Final mapping: + */ + + memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | + OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING; + memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V; + udelay (1000); + + + /* PLD Setup */ + memctl->memc_or5 = CFG_OR5_PRELIM; + memctl->memc_br5 = CFG_BR5_PRELIM; + udelay(1000); + + return (size_b0); +} + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ +static long int dram_size (long int mbmr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mbmr = mbmr_value; + + return (get_ram_size (base, maxsize)); +} + + +/************* other stuff ******************/ + + +int board_early_init_f(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + + /* Turn on LED PD9 */ + immap->im_ioport.iop_pdpar &= ~(0x0040); + immap->im_ioport.iop_pddir |= 0x0040; + immap->im_ioport.iop_pddat |= 0x0040; + + /* Enable PD10 (COM2_EN) */ + immap->im_ioport.iop_pdpar &= ~0x0020; + immap->im_ioport.iop_pddir &= ~0x4000; + immap->im_ioport.iop_pddir |= 0x0020; + immap->im_ioport.iop_pddat |= 0x0020; + + +#ifdef CFG_SMC1_PLD_CLK4 /* SMC1 uses CLK4 from PLD */ + immap->im_cpm.cp_simode |= 0x7000; + immap->im_cpm.cp_simode &= ~(0x8000); +#endif + + return 0; +} + + +int checkboard (void) +{ + puts("Board: SPC1920\n"); + return 0; +} diff --git a/board/spc1920/u-boot.lds b/board/spc1920/u-boot.lds new file mode 100644 index 0000000..d526d1d --- /dev/null +++ b/board/spc1920/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.ppcenv) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/tqm5200/Makefile b/board/tqm5200/Makefile index ab0ff1a..9a1ea48 100644 --- a/board/tqm5200/Makefile +++ b/board/tqm5200/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS := $(BOARD).o cmd_stk52xx.o +OBJS := $(BOARD).o cmd_stk52xx.o cmd_tb5200.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) diff --git a/board/tqm5200/cmd_stk52xx.c b/board/tqm5200/cmd_stk52xx.c index 8b9057f..7af69f2 100755 --- a/board/tqm5200/cmd_stk52xx.c +++ b/board/tqm5200/cmd_stk52xx.c @@ -22,7 +22,7 @@ */ /* - * SKT52XX specific functions + * STK52XX specific functions */ /*#define DEBUG*/ @@ -31,6 +31,7 @@ #if (CONFIG_COMMANDS & CFG_CMD_BSP) +#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) #define DEFAULT_VOL 45 #define DEFAULT_FREQ 500 #define DEFAULT_DURATION 200 @@ -60,7 +61,6 @@ static int spi_transmit(unsigned char data); static void pcm1772_write_reg(unsigned char addr, unsigned char data); static void set_attenuation(unsigned char attenuation); -#ifdef CONFIG_STK52XX static void spi_init(void) { struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; @@ -537,7 +537,9 @@ static int cmd_beep(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return rcode; } +#endif +#if defined(CONFIG_STK52XX) void led_init(void) { struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; @@ -736,7 +738,9 @@ int do_led(char *argv[]) return 0; } +#endif +#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) /* * return 1 on CAN initialization failure * return 0 if no failure @@ -1106,6 +1110,7 @@ int do_rs232(char *argv[]) return error_status; } +#ifndef CONFIG_FO300 static void sm501_backlight (unsigned int state) { if (state == BL_ON) { @@ -1115,6 +1120,7 @@ static void sm501_backlight (unsigned int state) *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &= ~((1 << 26) | (1 << 27)); } +#endif int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { @@ -1124,7 +1130,9 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf ("Revision 100 of STK52XX not supported!\n"); return 1; #endif +#if defined(CONFIG_STK52XX) led_init(); +#endif can_init(); switch (argc) { @@ -1152,6 +1160,7 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) else printf ("Error\n"); return rcode; +#ifndef CONFIG_FO300 } else if (strncmp (argv[1], "backlight", 4) == 0) { if (strncmp (argv[2], "on", 2) == 0) { sm501_backlight (BL_ON); @@ -1161,14 +1170,17 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) sm501_backlight (BL_OFF); return 0; } +#endif } break; +#if defined(CONFIG_STK52XX) case 4: if (strcmp (argv[1], "led") == 0) { return (do_led (argv)); } break; +#endif default: break; @@ -1204,12 +1216,14 @@ U_BOOT_CMD( "[channel]\n" " - play short beep on \"l\"eft or \"r\"ight channel\n" ); +#endif /* CONFIG_STK52XX || CONFIG_FO300 */ +#if defined(CONFIG_STK52XX) U_BOOT_CMD( fkt , 4, 1, cmd_fkt, "fkt - Function test routines\n", "led number on/off\n" - " - 'number's like printed on SKT52XX board\n" + " - 'number's like printed on STK52XX board\n" "fkt can\n" " - loopback plug for X83 required\n" "fkt rs232 number\n" @@ -1217,5 +1231,14 @@ U_BOOT_CMD( "fkt backlight on/off\n" " - switch backlight on or off\n" ); -#endif /* CONFIG_STK52XX */ +#elif defined(CONFIG_FO300) +U_BOOT_CMD( + fkt , 3, 1, cmd_fkt, + "fkt - Function test routines\n", + "fkt can\n" + " - loopback plug for X16/X29 required\n" + "fkt rs232 number\n" + " - loopback plug(s) for X21/X22 required\n" +); +#endif #endif /* CFG_CMD_BSP */ diff --git a/board/tqm5200/cmd_tb5200.c b/board/tqm5200/cmd_tb5200.c new file mode 100644 index 0000000..8784b1f --- /dev/null +++ b/board/tqm5200/cmd_tb5200.c @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2005 - 2006 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * TB5200 specific functions + */ +/*#define DEBUG*/ + +#include <common.h> +#include <command.h> + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) +#if defined (CONFIG_TB5200) + +#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL + +static void led_init(void) +{ + struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + + /* configure timer 4 for simple GPIO output */ + gpt->gpt4.emsr |= 0x00000024; +} + +int cmd_led(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + + led_init(); + + if (strcmp (argv[1], "on") == 0) { + debug ("switch status LED on\n"); + gpt->gpt4.emsr |= (1 << 4); + } else if (strcmp (argv[1], "off") == 0) { + debug ("switch status LED off\n"); + gpt->gpt4.emsr &= ~(1 << 4); + } else { + printf ("Usage:\nled on/off\n"); + return 1; + } + + return 0; +} + +static void sm501_backlight (unsigned int state) +{ + if (state == 1) { + *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |= + (1 << 26) | (1 << 27); + } else if (state == 0) + *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &= + ~((1 << 26) | (1 << 27)); +} + +int cmd_backlight(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (strcmp (argv[1], "on") == 0) { + debug ("switch backlight on\n"); + sm501_backlight (1); + } else if (strcmp (argv[1], "off") == 0) { + debug ("switch backlight off\n"); + sm501_backlight (0); + } else { + printf ("Usage:\nbacklight on/off\n"); + return 1; + } + + return 0; +} + +U_BOOT_CMD( + led , 2, 1, cmd_led, + "led - switch status LED on or off\n", + "on/off\n" +); + +U_BOOT_CMD( + backlight , 2, 1, cmd_backlight, + "backlight - switch backlight on or off\n", + "on/off\n" + ); + +#endif /* CONFIG_STK52XX */ +#endif /* CFG_CMD_BSP */ diff --git a/board/tqm5200/config.mk b/board/tqm5200/config.mk index 585a99a..84ddee8 100644 --- a/board/tqm5200/config.mk +++ b/board/tqm5200/config.mk @@ -28,12 +28,17 @@ # # 0xFC000000 boot low (standard configuration with room for max 64 MByte # Flash ROM) +# 0xFFF00000 boot high (for a backup copy of U-Boot) # 0x00100000 boot from RAM (for testing only) # +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + ifndef TEXT_BASE ## Standard: boot low TEXT_BASE = 0xFC000000 +## For a backup copy of U-Boot at the end of flash: boot high +# TEXT_BASE = 0xFFF00000 ## For testing: boot from RAM # TEXT_BASE = 0x00100000 endif diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index 310abd2..c8350ab 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -1,11 +1,11 @@ /* - * (C) Copyright 2003-2004 + * (C) Copyright 2003-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2004 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. * - * (C) Copyright 2004-2005 + * (C) Copyright 2004-2006 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de * * See file CREDITS for list of people who contributed to this @@ -30,6 +30,7 @@ #include <common.h> #include <mpc5xxx.h> #include <pci.h> +#include <asm/processor.h> #ifdef CONFIG_VIDEO_SM501 #include <sm501.h> @@ -101,6 +102,8 @@ long int initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; + uint svr, pvr; + #ifndef CFG_RAMBOOT ulong test1, test2; @@ -190,11 +193,31 @@ long int initdram (int board_type) } else { dramsize2 = 0; } - #endif /* CFG_RAMBOOT */ -/* return dramsize + dramsize2; */ + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + +#if defined(CONFIG_TQM5200_B) + return dramsize + dramsize2; +#else return dramsize; +#endif /* CONFIG_TQM5200_B */ } #elif defined(CONFIG_MGT5100) @@ -250,20 +273,38 @@ long int initdram (int board_type) int checkboard (void) { -#if defined (CONFIG_AEVFIFO) +#if defined(CONFIG_AEVFIFO) puts ("Board: AEVFIFO\n"); return 0; #endif -#if defined (CONFIG_TQM5200) - puts ("Board: TQM5200 (TQ-Components GmbH)\n"); + +#if defined(CONFIG_TQM5200S) +# define MODULE_NAME "TQM5200S" +#else +# define MODULE_NAME "TQM5200" #endif -#if defined (CONFIG_STK52XX) - puts (" on a STK52XX baseboard\n"); + +#if defined(CONFIG_STK52XX) +# define CARRIER_NAME "STK52xx" +#elif defined(CONFIG_TB5200) +# define CARRIER_NAME "TB5200" +#elif defined(CONFIG_CAM5200) +# define CARRIER_NAME "Cam5200" +#elif defined(CONFIG_FO300) +# define CARRIER_NAME "FO300" +#else +# error "UNKNOWN" #endif + puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n" + " on a " CARRIER_NAME " carrier board\n"); + return 0; } +#undef MODULE_NAME +#undef CARRIER_NAME + void flash_preinit(void) { /* @@ -405,7 +446,6 @@ int board_early_init_r (void) #endif #endif /* CONFIG_PS2MULT */ -#if defined(CONFIG_CS_AUTOCONF) int last_stage_init (void) { /* @@ -500,11 +540,14 @@ int last_stage_init (void) return 0; } -#endif /* CONFIG_CS_AUTOCONF */ #ifdef CONFIG_VIDEO_SM501 +#ifdef CONFIG_FO300 +#define DISPLAY_WIDTH 800 +#else #define DISPLAY_WIDTH 640 +#endif #define DISPLAY_HEIGHT 480 #ifdef CONFIG_VIDEO_SM501_8BPP @@ -534,6 +577,28 @@ static const SMI_REGS init_regs [] = {0x80218, 0x000201e9}, {0x80200, 0x00013306}, #else /* panel + CRT */ +#ifdef CONFIG_FO300 + {0x00004, 0x0}, + {0x00048, 0x00021807}, + {0x0004C, 0x301a0a01}, + {0x00054, 0x1}, + {0x00040, 0x00021807}, + {0x00044, 0x091a0a01}, + {0x00054, 0x0}, + {0x80000, 0x0f013106}, + {0x80004, 0xc428bb17}, + {0x8000C, 0x00000000}, + {0x80010, 0x0C800C80}, + {0x80014, 0x03200000}, + {0x80018, 0x01e00000}, + {0x8001C, 0x00000000}, + {0x80020, 0x01e00320}, + {0x80024, 0x042a031f}, + {0x80028, 0x0086034a}, + {0x8002C, 0x020c01df}, + {0x80030, 0x000201ea}, + {0x80200, 0x00010000}, +#else {0x00004, 0x0}, {0x00048, 0x00021807}, {0x0004C, 0x091a0a01}, @@ -554,6 +619,7 @@ static const SMI_REGS init_regs [] = {0x8002C, 0x020c01df}, {0x80030, 0x000201e9}, {0x80200, 0x00010000}, +#endif /* #ifdef CONFIG_FO300 */ #endif {0, 0} }; @@ -567,9 +633,17 @@ void video_get_info_str (int line_number, char *info) { if (line_number == 1) { strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); -#if defined (CONFIG_STK52XX) +#if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) || defined(CONFIG_FO300) } else if (line_number == 2) { - strcpy (info, " on a STK52XX baseboard"); +#if defined (CONFIG_STK52XX) + strcpy (info, " on a STK52xx carrier board"); +#endif +#if defined (CONFIG_TB5200) + strcpy (info, " on a TB5200 carrier board"); +#endif +#if defined (CONFIG_FO300) + strcpy (info, " on a FO300 carrier board"); +#endif #endif } else { @@ -655,3 +729,33 @@ int board_get_height (void) } #endif /* CONFIG_VIDEO_SM501 */ + + +#ifdef CONFIG_BOARD_EARLY_INIT_F +#ifdef CONFIG_FO300 +int board_early_init_f (void) +{ + vu_long timer3_status; + DECLARE_GLOBAL_DATA_PTR; + + /* Configure GPT3 as GPIO input */ + *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004; + + /* Read in TIMER_3 pin status */ + timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS; + +#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED + /* Force silent console mode if S1 switch + * is in closed position (TIMER_3 pin status is LOW). */ + if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0) +#else + /* Force silent console mode if S1 switch + * is in open position (TIMER_3 pin status is HIGH). */ + if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1) +#endif + gd->flags |= GD_FLG_SILENT; + + return 0; +} +#endif +#endif diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c index d992aec..41b34cc 100644 --- a/board/tqm834x/tqm834x.c +++ b/board/tqm834x/tqm834x.c @@ -424,10 +424,12 @@ static void set_ddr_config(void) { * which has to be written with a certain value defined by * errata sheet. */ + u32 *reserved_p = (u32 *)((u8 *)im + 0x2f00); + #if defined(DDR_CASLAT_20) - *((u8 *)im + 0x2f00) = 0x201c0000; + *reserved_p = 0x201c0000; #else - *((u8 *)im + 0x2f00) = 0x202c0000; + *reserved_p = 0x202c0000; #endif } } diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c index befe8b7..b4ef5af 100644 --- a/board/tqm85xx/tqm85xx.c +++ b/board/tqm85xx/tqm85xx.c @@ -27,10 +27,6 @@ * MA 02111-1307 USA */ -#ifdef CONFIG_PS2MULT -void ps2mult_early_init(void); -#endif - #include <common.h> #include <pci.h> #include <asm/processor.h> @@ -47,6 +43,10 @@ void local_bus_init (void); long int fixed_sdram (void); ulong flash_get_size (ulong base, int banknum); +#ifdef CONFIG_PS2MULT +void ps2mult_early_init(void); +#endif + #ifdef CONFIG_CPM2 /* * I/O Port configuration table @@ -423,4 +423,3 @@ int board_early_init_r (void) return (0); } #endif /* CONFIG_BOARD_EARLY_INIT_R */ - diff --git a/board/tqm8xx/flash.c b/board/tqm8xx/flash.c index ab57ee5..db0a7e5 100644 --- a/board/tqm8xx/flash.c +++ b/board/tqm8xx/flash.c @@ -33,12 +33,13 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) +#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ + && !defined(CONFIG_TQM885D) # ifndef CFG_OR_TIMING_FLASH_AT_50MHZ # define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ OR_SCY_2_CLK | OR_EHTR | OR_BI) # endif -#endif /* CONFIG_TQM8xxL/M, !TQM866M */ +#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */ #ifndef CFG_ENV_ADDR #define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c index b292231..6b206f8 100644 --- a/board/tqm8xx/tqm8xx.c +++ b/board/tqm8xx/tqm8xx.c @@ -119,6 +119,10 @@ int checkboard (void) gd->board_type = 'M'; } + if ((*(s + 6) == 'D')) { /* a TQM885D type */ + gd->board_type = 'D'; + } + for (; *s; ++s) { if (*s == ' ') break; @@ -178,7 +182,8 @@ long int initdram (int board_type) #ifndef CONFIG_CAN_DRIVER if ((board_type != 'L') && - (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */ + (board_type != 'M') && + (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */ memctl->memc_or3 = CFG_OR3_PRELIM; memctl->memc_br3 = CFG_BR3_PRELIM; } @@ -197,7 +202,8 @@ long int initdram (int board_type) #ifndef CONFIG_CAN_DRIVER if ((board_type != 'L') && - (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */ + (board_type != 'M') && + (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */ memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */ udelay (1); memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */ @@ -214,8 +220,7 @@ long int initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); + size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20); udelay (1000); @@ -223,8 +228,7 @@ long int initdram (int board_type) /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); + size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20); udelay(1000); @@ -233,8 +237,7 @@ long int initdram (int board_type) /* * try 10 column mode */ - size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); + size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20); #else size10 = 0; @@ -255,7 +258,8 @@ long int initdram (int board_type) #ifndef CONFIG_CAN_DRIVER if ((board_type != 'L') && - (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */ + (board_type != 'M') && + (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */ /* * Check Bank 1 Memory Size * use current column settings diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c index 056e562..d2c8d44 100644 --- a/board/trab/auto_update.c +++ b/board/trab/auto_update.c @@ -57,9 +57,9 @@ * valid then run it. * 2) if preinst.img is found load it into memory. If it is * valid then run it. Update the EEPROM. - * 3) if firmware.img is found load it into memory. If it is valid, + * 3) if firmw_01.img is found load it into memory. If it is valid, * burn it into FLASH and update the EEPROM. - * 4) if kernel.img is found load it into memory. If it is valid, + * 4) if kernl_01.img is found load it into memory. If it is valid, * burn it into FLASH and update the EEPROM. * 5) if app.img is found load it into memory. If it is valid, * burn it into FLASH and update the EEPROM. @@ -81,8 +81,8 @@ /* possible names of files on the USB stick. */ #define AU_PREPARE "prepare.img" #define AU_PREINST "preinst.img" -#define AU_FIRMWARE "firmware.img" -#define AU_KERNEL "kernel.img" +#define AU_FIRMWARE "firmw_01.img" +#define AU_KERNEL "kernl_01.img" #define AU_APP "app.img" #define AU_DISK "disk.img" #define AU_POSTINST "postinst.img" @@ -222,7 +222,7 @@ au_check_cksum_valid(int idx, long nbytes) /* check the data CRC */ checksum = ntohl(hdr->ih_dcrc); - if (crc32 (0, (char *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size)) + if (crc32 (0, (uchar *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size)) != checksum) { printf ("Image %s bad data checksum\n", aufile[idx]); @@ -261,7 +261,7 @@ au_check_header_valid(int idx, long nbytes) checksum = ntohl(hdr->ih_hcrc); hdr->ih_hcrc = 0; - if (crc32 (0, (char *)hdr, sizeof(*hdr)) != checksum) { + if (crc32 (0, (uchar *)hdr, sizeof(*hdr)) != checksum) { printf ("Image %s bad header checksum\n", aufile[idx]); return -1; } @@ -397,7 +397,7 @@ au_do_update(int idx, long sz) } /* check the dcrc of the copy */ - if (crc32 (0, (char *)(start + off), ntohl(hdr->ih_size)) != ntohl(hdr->ih_dcrc)) { + if (crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size)) != ntohl(hdr->ih_dcrc)) { printf ("Image %s Bad Data Checksum After COPY\n", aufile[idx]); return -1; } @@ -613,7 +613,8 @@ do_auto_update(void) #define VFD_LOGO_WIDTH 112 #define VFD_LOGO_HEIGHT 72 /* must call transfer_pic directly */ - transfer_pic(3, env, VFD_LOGO_HEIGHT, VFD_LOGO_WIDTH); + transfer_pic(3, (unsigned char *)env, + VFD_LOGO_HEIGHT, VFD_LOGO_WIDTH); } bitmap_first = 1; } diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c index edea8f0..b82c8ed 100644 --- a/board/trab/cmd_trab.c +++ b/board/trab/cmd_trab.c @@ -147,11 +147,11 @@ u8 status; u16 pass_cycles; u16 first_error_cycle; u8 first_error_num; -unsigned char first_error_name[16]; +char first_error_name[16]; u16 act_cycle; typedef struct test_function_s { - unsigned char *name; + char *name; int (*pf)(void); } test_function_t; @@ -376,7 +376,7 @@ int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (1); } if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME, - 1, first_error_name, + 1, (unsigned char*)first_error_name, sizeof (first_error_name))) { return (1); } @@ -537,7 +537,7 @@ static int test_eeprom (void) /* write test string 1, read back and verify */ if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1, - EEPROM_TEST_STRING_1, + (unsigned char*)EEPROM_TEST_STRING_1, sizeof (EEPROM_TEST_STRING_1))) { return (1); } @@ -547,7 +547,7 @@ static int test_eeprom (void) return (1); } - if (strcmp (temp, EEPROM_TEST_STRING_1) != 0) { + if (strcmp ((char *)temp, EEPROM_TEST_STRING_1) != 0) { result = 1; printf ("%s: error; read_str = \"%s\"\n", __FUNCTION__, temp); } @@ -555,7 +555,7 @@ static int test_eeprom (void) /* write test string 2, read back and verify */ if (result == 0) { if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1, - EEPROM_TEST_STRING_2, + (unsigned char*)EEPROM_TEST_STRING_2, sizeof (EEPROM_TEST_STRING_2))) { return (1); } @@ -565,7 +565,7 @@ static int test_eeprom (void) return (1); } - if (strcmp (temp, EEPROM_TEST_STRING_2) != 0) { + if (strcmp ((char *)temp, EEPROM_TEST_STRING_2) != 0) { result = 1; printf ("%s: error; read str = \"%s\"\n", __FUNCTION__, temp); @@ -777,7 +777,7 @@ static int global_vars_write_to_eeprom (void) return (1); } if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME, - 1, first_error_name, + 1, (unsigned char*) first_error_name, sizeof(first_error_name))) { return (1); } diff --git a/board/trab/flash.c b/board/trab/flash.c index 8cdd824..3e8f105 100644 --- a/board/trab/flash.c +++ b/board/trab/flash.c @@ -281,10 +281,12 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) if (chip1 == ERR || chip2 == ERR) { rc = ERR_PROG_ERROR; + printf ("Flash erase error\n"); goto outahere; } if (chip1 == TMO) { rc = ERR_TIMOUT; + printf ("Flash erase timeout error\n"); goto outahere; } } @@ -340,7 +342,9 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) #endif iflag = disable_interrupts (); - *addr = CMD_PROGRAM; + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_PROGRAM; *addr = data; /* arm simple, non interrupt dependent timer */ @@ -352,7 +356,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) result = *addr; /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { chip1 = ERR | TMO; break; } @@ -384,8 +388,13 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) *addr = CMD_READ_ARRAY; - if (chip1 == ERR || chip2 == ERR || *addr != data) + if (chip1 == ERR || chip2 == ERR || *addr != data) { rc = ERR_PROG_ERROR; + printf ("Flash program error\n"); + debug ("chip1: %#x, chip2: %#x, addr: %#lx *addr: %#lx, " + "data: %#lx\n", + chip1, chip2, addr, *addr, data); + } if (iflag) enable_interrupts (); @@ -408,10 +417,6 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) int l; int i, rc; - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS; - wp = (addr & ~3); /* get lower word aligned address */ /* @@ -479,9 +484,6 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) Done: - MEM_FLASH_ADDR = CMD_UNLOCK_BYPASS_RES1; - MEM_FLASH_ADDR = CMD_UNLOCK_BYPASS_RES2; - return (rc); } @@ -515,7 +517,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) info->flash_id = FLASH_UNKNOWN; info->sector_count = 0; info->size = 0; - addr[0] = 0x00FF00FF; /* restore read mode */ + addr[0] = CMD_READ_ARRAY; /* restore read mode */ debug ("## flash_init: unknown manufacturer\n"); return (0); /* no or unknown flash */ } @@ -530,7 +532,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) info->sector_count = 71; info->size = 0x00800000; - addr[0] = 0x00FF00FF; /* restore read mode */ + addr[0] = CMD_READ_ARRAY; /* restore read mode */ break; /* => 8 MB */ case AMD_ID_LV640U: @@ -538,7 +540,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) info->sector_count = 128; info->size = 0x01000000; - addr[0] = 0x00F000F0; /* restore read mode */ + addr[0] = CMD_READ_ARRAY; /* restore read mode */ break; /* => 16 MB */ case MX_ID_LV320B: @@ -546,13 +548,13 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) info->sector_count = 71; info->size = 0x00800000; - addr[0] = 0x00FF00FF; /* restore read mode */ + addr[0] = CMD_READ_ARRAY; /* restore read mode */ break; /* => 8 MB */ default: debug ("## flash_init: unknown flash chip\n"); info->flash_id = FLASH_UNKNOWN; - addr[0] = 0x00FF00FF; /* restore read mode */ + addr[0] = CMD_READ_ARRAY; /* restore read mode */ return (0); /* => no or unknown flash */ } diff --git a/board/trab/memory.c b/board/trab/memory.c index 4097892..58bd995 100644 --- a/board/trab/memory.c +++ b/board/trab/memory.c @@ -419,14 +419,14 @@ int memory_post_tests (unsigned long start, unsigned long size) int ret = 0; if (ret == 0) - ret = memory_post_dataline ((long long *)start); + ret = memory_post_dataline ((unsigned long long *)start); WATCHDOG_RESET (); if (ret == 0) - ret = memory_post_addrline ((long *)start, (long *)start, size); + ret = memory_post_addrline ((ulong *)start, (ulong *)start, size); WATCHDOG_RESET (); if (ret == 0) - ret = memory_post_addrline ((long *)(start + size - 8), - (long *)start, size); + ret = memory_post_addrline ((ulong *)(start + size - 8), + (ulong *)start, size); WATCHDOG_RESET (); if (ret == 0) ret = memory_post_test1 (start, size, 0x00000000); diff --git a/board/trab/trab.c b/board/trab/trab.c index 346406e..d8a726b 100644 --- a/board/trab/trab.c +++ b/board/trab/trab.c @@ -152,13 +152,13 @@ int dram_init (void) #define KBD_DATA (((*(volatile ulong *)0x04020000) >> 16) & 0xF) -static uchar *key_match (ulong); +static char *key_match (ulong); int misc_init_r (void) { ulong kbd_data = KBD_DATA; - uchar keybd_env[KEYBD_KEY_NUM + 1]; - uchar *str; + char *str; + char keybd_env[KEYBD_KEY_NUM + 1]; int i; #ifdef CONFIG_VERSION_VARIABLE @@ -175,9 +175,11 @@ int misc_init_r (void) #endif /* CONFIG_VERSION_VARIABLE */ #ifdef CONFIG_AUTO_UPDATE - extern int do_auto_update(void); - /* this has priority over all else */ - do_auto_update(); + { + extern int do_auto_update(void); + /* this has priority over all else */ + do_auto_update(); + } #endif for (i = 0; i < KEYBD_KEY_NUM; ++i) { @@ -208,7 +210,7 @@ int misc_init_r (void) static uchar kbd_magic_prefix[] = "key_magic"; static uchar kbd_command_prefix[] = "key_cmd"; -static int compare_magic (ulong kbd_data, uchar *str) +static int compare_magic (ulong kbd_data, char *str) { uchar key_mask; @@ -254,12 +256,12 @@ static int compare_magic (ulong kbd_data, uchar *str) * Note: the string points to static environment data and must be * saved before you call any function that modifies the environment. */ -static uchar *key_match (ulong kbd_data) +static char *key_match (ulong kbd_data) { - uchar magic[sizeof (kbd_magic_prefix) + 1]; - uchar cmd_name[sizeof (kbd_command_prefix) + 1]; - uchar *suffix; - uchar *kbd_magic_keys; + char magic[sizeof (kbd_magic_prefix) + 1]; + char cmd_name[sizeof (kbd_command_prefix) + 1]; + char *suffix; + char *kbd_magic_keys; /* * The following string defines the characters that can pe appended @@ -304,7 +306,7 @@ static uchar *key_match (ulong kbd_data) int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { ulong kbd_data = KBD_DATA; - uchar keybd_env[KEYBD_KEY_NUM + 1]; + char keybd_env[KEYBD_KEY_NUM + 1]; int i; puts ("Keys:"); @@ -404,7 +406,7 @@ static void tsc2000_write(unsigned int page, unsigned int reg, static void tsc2000_set_brightness(void) { - uchar tmp[10]; + char tmp[10]; int i, br; spi_init(); diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c index abb3b29..71be6e0 100644 --- a/board/trab/trab_fkt.c +++ b/board/trab/trab_fkt.c @@ -967,21 +967,21 @@ static int touch_write_clibration_values (int calib_point, int x, int y) if (calib_point == CALIB_TL) { if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X0, 1, - (char *)&x, 2)) { + (unsigned char *)&x, 2)) { return 1; } if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y0, 1, - (char *)&y, 2)) { + (unsigned char *)&y, 2)) { return 1; } /* verify written values */ if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X0, 1, - (char *)&x_verify, 2)) { + (unsigned char *)&x_verify, 2)) { return 1; } if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y0, 1, - (char *)&y_verify, 2)) { + (unsigned char *)&y_verify, 2)) { return 1; } if ((y != y_verify) || (x != x_verify)) { @@ -993,21 +993,21 @@ static int touch_write_clibration_values (int calib_point, int x, int y) } else if (calib_point == CALIB_DR) { if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X1, 1, - (char *)&x, 2)) { + (unsigned char *)&x, 2)) { return 1; } if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y1, 1, - (char *)&y, 2)) { + (unsigned char *)&y, 2)) { return 1; } /* verify written values */ if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X1, 1, - (char *)&x_verify, 2)) { + (unsigned char *)&x_verify, 2)) { return 1; } if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y1, 1, - (char *)&y_verify, 2)) { + (unsigned char *)&y_verify, 2)) { return 1; } if ((y != y_verify) || (x != x_verify)) { @@ -1110,7 +1110,7 @@ int do_serial_number (char **argv) if (strcmp (argv[2], "read") == 0) { if (i2c_read (I2C_EEPROM_DEV_ADDR, SERIAL_NUMBER, 1, - (char *)&serial_number, 4)) { + (unsigned char *)&serial_number, 4)) { printf ("could not read from eeprom\n"); return (1); } @@ -1121,7 +1121,7 @@ int do_serial_number (char **argv) else if (strcmp (argv[2], "write") == 0) { serial_number = simple_strtoul(argv[3], NULL, 10); if (i2c_write (I2C_EEPROM_DEV_ADDR, SERIAL_NUMBER, 1, - (char *)&serial_number, 4)) { + (unsigned char *)&serial_number, 4)) { printf ("could not write to eeprom\n"); return (1); } @@ -1141,7 +1141,7 @@ int do_crc16 (void) { #if (CONFIG_COMMANDS & CFG_CMD_I2C) int crc; - char buf[EEPROM_MAX_CRC_BUF]; + unsigned char buf[EEPROM_MAX_CRC_BUF]; if (i2c_read (I2C_EEPROM_DEV_ADDR, 0, 1, buf, 60)) { printf ("could not read from eeprom\n"); @@ -1153,7 +1153,7 @@ int do_crc16 (void) print_identifier (); printf ("crc16=%#04x\n", crc); - if (i2c_write (I2C_EEPROM_DEV_ADDR, CRC16, 1, (char *)&crc, + if (i2c_write (I2C_EEPROM_DEV_ADDR, CRC16, 1, (unsigned char *)&crc, sizeof (crc))) { printf ("could not read from eeprom\n"); return (1); diff --git a/board/trab/vfd.c b/board/trab/vfd.c index 2f1e7d7..b6798fd 100644 --- a/board/trab/vfd.c +++ b/board/trab/vfd.c @@ -251,19 +251,17 @@ void create_vfd_table(void) unsigned long adr = gd->fb_base; unsigned int bit_nr = 0; - if (vfd_table[x][y][color][display][entry]) { - - pixel = vfd_table[x][y][color][display][entry] + frame_buf_offs; - /* - * wrap arround if offset - * (see manual S3C2400) - */ - if (pixel>=FRAME_BUF_SIZE*8) - pixel = pixel-(FRAME_BUF_SIZE*8); - adr = gd->fb_base+(pixel/32)*4+(3-(pixel%32)/8); - bit_nr = pixel%8; - bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4; - } + pixel = vfd_table[x][y][color][display][entry] + frame_buf_offs; + /* + * wrap arround if offset + * (see manual S3C2400) + */ + if (pixel>=FRAME_BUF_SIZE*8) + pixel = pixel-(FRAME_BUF_SIZE*8); + adr = gd->fb_base+(pixel/32)*4+(3-(pixel%32)/8); + bit_nr = pixel%8; + bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4; + adr_vfd_table[x][y][color][display][entry] = adr; bit_vfd_table[x][y][color][display][entry] = bit_nr; } diff --git a/board/uc100/Makefile b/board/uc100/Makefile index eb81625..2d2cc23 100644 --- a/board/uc100/Makefile +++ b/board/uc100/Makefile @@ -25,8 +25,8 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -#OBJS = $(BOARD).o flash.o -OBJS = $(BOARD).o +#OBJS = $(BOARD).o flash.o pcmcia.o +OBJS = $(BOARD).o pcmcia.o $(LIB): .depend $(OBJS) $(AR) crv $@ $(OBJS) diff --git a/board/uc100/pcmcia.c b/board/uc100/pcmcia.c new file mode 100644 index 0000000..6e4b6d6 --- /dev/null +++ b/board/uc100/pcmcia.c @@ -0,0 +1,198 @@ +#include <common.h> +#include <mpc8xx.h> +#include <pcmcia.h> + +#undef CONFIG_PCMCIA + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#define CONFIG_PCMCIA +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#define CONFIG_PCMCIA +#endif + +#ifdef CONFIG_PCMCIA + +#define PCMCIA_BOARD_MSG "UC100" + +/* + * Remark: don't turn off OE "__MY_PCMCIA_GCRX_CXOE" on UC100 board. + * This leads to board-hangup! (sr, 8 Dez. 2004) + */ +static void cfg_ports (void) +{ + volatile immap_t *immap; + + immap = (immap_t *)CFG_IMMR; + + /* + * Configure Port A for MAX1602 PC-Card Power-Interface Switch + */ + immap->im_ioport.iop_padat &= ~0x8000; /* set port x output to low */ + immap->im_ioport.iop_padir |= 0x8000; /* enable port x as output */ + + debug ("Set Port A: PAR: %08x DIR: %08x DAT: %08x\n", + immap->im_ioport.iop_papar, immap->im_ioport.iop_padir, + immap->im_ioport.iop_padat); +} + +int pcmcia_hardware_enable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, mask; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + udelay(10000); + + immap = (immap_t *)CFG_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + + /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ + cfg_ports (); + + /* + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ + sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); + pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { + printf (" No Card found\n"); + return (1); + } + + /* + * Power On. + */ + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + reg = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + reg, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); + if ((reg & mask) == mask) { + puts (" 5.0V card found: "); + } else { + puts (" 3.3V card found: "); + } + + /* switch VCC on */ + immap->im_ioport.iop_padat |= 0x8000; /* power enable 3.3V */ + + udelay(10000); + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +int pcmcia_hardware_disable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + + /* switch VCC off */ + immap->im_ioport.iop_padat &= ~0x8000; /* power disable 3.3V */ + + /* Configure PCMCIA General Control Register */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + PCMCIA_PGCRX(_slot_) = reg; + + udelay(10000); + + return (0); +} +#endif /* CFG_CMD_PCMCIA */ + + +int pcmcia_voltage_set(int slot, int vcc, int vpp) +{ + volatile immap_t *immap; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("voltage_set: " + PCMCIA_BOARD_MSG + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + immap = (immap_t *)CFG_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + /* + * Configure Port C pins for + * 5 Volts Enable and 3 Volts enable, + * Turn all power pins to Hi-Z + */ + debug ("PCMCIA power OFF\n"); + cfg_ports (); /* Enables switch, but all in Hi-Z */ + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(_slot_); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(_slot_) = reg; + udelay(500); + + debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", + slot+'A'); + return (0); +} + +#endif /* CONFIG_PCMCIA */ diff --git a/common/Makefile b/common/Makefile index eb0b5da..a62bc16 100644 --- a/common/Makefile +++ b/common/Makefile @@ -51,7 +51,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o \ memsize.o miiphybb.o miiphyutil.o \ s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \ usb.o usb_kbd.o usb_storage.o \ - virtex2.o xilinx.o crc16.o xyzModem.o + virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o OBJS = $(AOBJS) $(COBJS) diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 04fa4fa..256e4bc 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -61,11 +61,12 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) print_num ("bootflags", bd->bi_bootflags ); #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) + defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440SP) print_str ("procfreq", strmhz(buf, bd->bi_procfreq)); print_str ("plb_busfreq", strmhz(buf, bd->bi_plb_busfreq)); #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) + defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE) print_str ("pci_busfreq", strmhz(buf, bd->bi_pci_busfreq)); #endif #else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */ diff --git a/common/cmd_boot.c b/common/cmd_boot.c index e68f16f..182e2ab 100644 --- a/common/cmd_boot.c +++ b/common/cmd_boot.c @@ -83,7 +83,7 @@ U_BOOT_CMD( extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); U_BOOT_CMD( - reset, 1, 0, do_reset, + reset, CFG_MAXARGS, 1, do_reset, "reset - Perform RESET of the CPU\n", NULL ); diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index f1c0eb4..652d843 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -528,7 +528,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, void (*kernel)(bd_t *, ulong, ulong, ulong, ulong); image_header_t *hdr = &header; #ifdef CONFIG_OF_FLAT_TREE - char *of_flat_tree; + char *of_flat_tree = NULL; #endif if ((s = getenv ("initrd_high")) != NULL) { @@ -737,14 +737,76 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, } #ifdef CONFIG_OF_FLAT_TREE - if (argc >= 3) - { + if(argc > 3) { of_flat_tree = (char *) simple_strtoul(argv[3], NULL, 16); - printf ("Booting using flat device tree at 0x%x\n", + hdr = (image_header_t *)of_flat_tree; + + if (*(ulong *)of_flat_tree == OF_DT_HEADER) { +#ifndef CFG_NO_FLASH + if (addr2info((ulong)of_flat_tree) != NULL) { + printf ("Cannot modify flat device tree stored in flash\n" \ + "Copy to memory before using the bootm command\n"); + return; + } +#endif + } else if (ntohl(hdr->ih_magic) == IH_MAGIC) { + printf("## Flat Device Tree Image at %08lX\n", hdr); + print_image_hdr(hdr); + + if ((ntohl(hdr->ih_load) < ((unsigned long)hdr + ntohl(hdr->ih_size) + sizeof(hdr))) && + ((ntohl(hdr->ih_load) + ntohl(hdr->ih_size)) > (unsigned long)hdr)) { + printf ("ERROR: Load address overwrites Flat Device Tree uImage\n"); + return; + } + + printf(" Verifying Checksum ... "); + memmove (&header, (char *)hdr, sizeof(image_header_t)); + checksum = ntohl(header.ih_hcrc); + header.ih_hcrc = 0; + + if(checksum != crc32(0, (uchar *)&header, sizeof(image_header_t))) { + printf("ERROR: Flat Device Tree header checksum is invalid\n"); + return; + } + + checksum = ntohl(hdr->ih_dcrc); + addr = (ulong)((uchar *)(hdr) + sizeof(image_header_t)); + len = ntohl(hdr->ih_size); + + if(checksum != crc32(0, (uchar *)addr, len)) { + printf("ERROR: Flat Device Tree checksum is invalid\n"); + return; + } + printf("OK\n"); + + if (ntohl(hdr->ih_type) != IH_TYPE_FLATDT) { + printf ("ERROR: uImage not Flat Device Tree type\n"); + return; + } + if (ntohl(hdr->ih_comp) != IH_COMP_NONE) { + printf("ERROR: uImage is not uncompressed\n"); + return; + } + if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) { + printf ("ERROR: uImage data is not a flat device tree\n"); + return; + } + + memmove((void *)ntohl(hdr->ih_load), + (void *)(of_flat_tree + sizeof(image_header_t)), + ntohl(hdr->ih_size)); + of_flat_tree = (char *)ntohl(hdr->ih_load); + } else { + printf ("Did not find a flat flat device tree at address %08lX\n", of_flat_tree); + return; + } + printf (" Booting using flat device tree at 0x%x\n", of_flat_tree); + } else if(getenv("disable_of") == NULL) { + printf ("ERROR: bootm needs flat device tree as third argument\n"); + return; } #endif - if (!data) { debug ("No initrd\n"); } @@ -1272,6 +1334,7 @@ print_type (image_header_t *hdr) case IH_TYPE_MULTI: type = "Multi-File Image"; break; case IH_TYPE_FIRMWARE: type = "Firmware"; break; case IH_TYPE_SCRIPT: type = "Script"; break; + case IH_TYPE_FLATDT: type = "Flat Device Tree"; break; default: type = "Unknown Image"; break; } diff --git a/common/cmd_mac.c b/common/cmd_mac.c new file mode 100644 index 0000000..0add432 --- /dev/null +++ b/common/cmd_mac.c @@ -0,0 +1,66 @@ +/* + * Copyright 2006 Freescale Semiconductor + * York Sun (yorksun@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> + +#ifdef CFG_ID_EEPROM + +extern int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +U_BOOT_CMD( + mac, 3, 1, do_mac, + "mac - display and program the system ID and MAC addresses in EEPROM\n", + "[read|save|id|num|errata|date|ports|0|1|2|3|4|5|6|7]\n" + "read\n" + " - show content of mac\n" + "mac save\n" + " - save to the EEPROM\n" + "mac id\n" + " - program system id\n" + "mac num\n" + " - program system serial number\n" + "mac errata\n" + " - program errata data\n" + "mac date\n" + " - program data date\n" + "mac ports\n" + " - program the number of ports\n" + "mac 0\n" + " - program the MAC address for port 0\n" + "mac 1\n" + " - program the MAC address for port 1\n" + "mac 2\n" + " - program the MAC address for port 2\n" + "mac 3\n" + " - program the MAC address for port 3\n" + "mac 4\n" + " - program the MAC address for port 4\n" + "mac 5\n" + " - program the MAC address for port 5\n" + "mac 6\n" + " - program the MAC address for port 6\n" + "mac 7\n" + " - program the MAC address for port 7\n" +); +#endif /* CFG_ID_EEPROM */ diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 0f4f9b7..d0fae6b 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -707,7 +707,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CFG_MEMTEST_SCRATCH) vu_long *dummy = (vu_long*)CFG_MEMTEST_SCRATCH; #else - vu_long *dummy = NULL; + vu_long *dummy = 0; /* yes, this is address 0x0, not NULL */ #endif int j; int iterations = 1; diff --git a/common/cmd_mii.c b/common/cmd_mii.c index 48a4e77..e659536 100644 --- a/common/cmd_mii.c +++ b/common/cmd_mii.c @@ -57,6 +57,11 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) int rcode = 0; char *devname; + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + #if defined(CONFIG_8xx) || defined(CONFIG_MCF52x2) mii_init (); #endif @@ -112,8 +117,6 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) miiphy_speed (devname, j), (miiphy_duplex (devname, j) == FULL) ? "FDX" : "HDX"); - } else { - puts ("Error reading info from the PHY\n"); } } } else if (op == 'r') { @@ -498,8 +501,6 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) miiphy_speed (devname, j), (miiphy_duplex (devname, j) == FULL) ? "FDX" : "HDX"); - } else { - puts ("Error reading info from the PHY\n"); } } } else if (op[0] == 'r') { diff --git a/common/cmd_pcmcia.c b/common/cmd_pcmcia.c index 8e3e84b..2eb5b26 100644 --- a/common/cmd_pcmcia.c +++ b/common/cmd_pcmcia.c @@ -57,75 +57,14 @@ #include <command.h> #include <config.h> #include <pcmcia.h> -#if defined(CONFIG_8xx) -#include <mpc8xx.h> -#endif -#if defined(CONFIG_LWMON) -#include <i2c.h> -#endif -#ifdef CONFIG_PXA_PCMCIA -#include <asm/arch/pxa-regs.h> -#endif - #include <asm/io.h> -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || \ - ((CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)) - -int pcmcia_on (void); - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -static int pcmcia_off (void); -#endif - -#ifdef CONFIG_I82365 - -extern int i82365_init (void); -extern void i82365_exit (void); - -#else /* ! CONFIG_I82365 */ - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -static int hardware_disable(int slot); -#endif -static int hardware_enable (int slot); -static int voltage_set(int slot, int vcc, int vpp); - -#if (! defined(CONFIG_I82365)) && (! defined(CONFIG_PXA_PCMCIA)) -static u_int m8xx_get_graycode(u_int size); -#endif /* !CONFIG_I82365, !CONFIG_PXA_PCMCIA */ -#if 0 -static u_int m8xx_get_speed(u_int ns, u_int is_io); -#endif - /* -------------------------------------------------------------------- */ -#ifndef CONFIG_PXA_PCMCIA - -/* look up table for pgcrx registers */ - -static u_int *pcmcia_pgcrx[2] = { - &((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcra, - &((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb, -}; -#define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot]) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -#endif /* CONFIG_PXA_PCMCIA */ - -#endif /* CONFIG_I82365 */ - -#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA) -static void print_funcid (int func); -static void print_fixed (volatile uchar *p); -static int identify (volatile uchar *p); -static int check_ide_device (int slot); -#endif /* CONFIG_IDE_8xx_PCCARD, CONFIG_PXA_PCMCIA */ - -const char *indent = "\t "; - -/* -------------------------------------------------------------------- */ - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +extern int pcmcia_on (void); +extern int pcmcia_off (void); int do_pinit (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { @@ -136,7 +75,7 @@ int do_pinit (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } if (strcmp(argv[1],"on") == 0) { - rcode = pcmcia_on (); + rcode = pcmcia_on (); } else if (strcmp(argv[1],"off") == 0) { rcode = pcmcia_off (); } else { @@ -146,2656 +85,82 @@ int do_pinit (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return rcode; } -#endif /* CFG_CMD_PCMCIA */ - -/* -------------------------------------------------------------------- */ - -#ifdef CONFIG_I82365 -int pcmcia_on (void) -{ - u_int rc; - - debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); - rc = i82365_init(); +U_BOOT_CMD( + pinit, 2, 1, do_pinit, + "pinit - PCMCIA sub-system\n", + "on - power on PCMCIA socket\n" + "pinit off - power off PCMCIA socket\n" + ); - if (rc == 0) { - rc = check_ide_device(0); - } +#endif /* CONFIG_COMMANDS & CFG_CMD_PCMCIA */ - return (rc); -} -#else +/* -------------------------------------------------------------------- */ -#ifndef CONFIG_PXA_PCMCIA +#undef CHECK_IDE_DEVICE -#ifdef CONFIG_HMI10 -# define HMI10_FRAM_TIMING (PCMCIA_SHT(2) | PCMCIA_SST(2) | PCMCIA_SL(4)) +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#define CHECK_IDE_DEVICE #endif -#if defined(CONFIG_LWMON) || defined(CONFIG_NSCU) -# define CFG_PCMCIA_TIMING (PCMCIA_SHT(9) | PCMCIA_SST(3) | PCMCIA_SL(12)) -#else -# define CFG_PCMCIA_TIMING (PCMCIA_SHT(2) | PCMCIA_SST(4) | PCMCIA_SL(9)) + +#if defined(CONFIG_PXA_PCMCIA) +#define CHECK_IDE_DEVICE #endif -int pcmcia_on (void) -{ - int i; - u_long reg, base; - pcmcia_win_t *win; - u_int slotbit; - u_int rc, slot; +#ifdef CHECK_IDE_DEVICE - debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); +int ide_devices_found; +static uchar *known_cards[] = { + (uchar *)"ARGOSY PnPIDE D5", + NULL +}; - /* intialize the fixed memory windows */ - win = (pcmcia_win_t *)(&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pbr0); - base = CFG_PCMCIA_MEM_ADDR; +#define MAX_TUPEL_SZ 512 +#define MAX_FEATURES 4 - if((reg = m8xx_get_graycode(CFG_PCMCIA_MEM_SIZE)) == -1) { - printf ("Cannot set window size to 0x%08x\n", - CFG_PCMCIA_MEM_SIZE); - return (1); - } +#define MAX_IDENT_CHARS 64 +#define MAX_IDENT_FIELDS 4 - slotbit = PCMCIA_SLOT_x; - for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) { - win->br = base; +#define indent "\t " -#if (PCMCIA_SOCKETS_NO == 2) - if (i == 4) /* Another slot starting from win 4 */ - slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B); -#endif - switch (i) { -#ifdef CONFIG_IDE_8xx_PCCARD - case 4: -#ifdef CONFIG_HMI10 - { /* map FRAM area */ - win->or = ( PCMCIA_BSIZE_256K - | PCMCIA_PPS_8 - | PCMCIA_PRS_ATTR - | slotbit - | PCMCIA_PV - | HMI10_FRAM_TIMING ); - break; - } -#endif - case 0: { /* map attribute memory */ - win->or = ( PCMCIA_BSIZE_64M - | PCMCIA_PPS_8 - | PCMCIA_PRS_ATTR - | slotbit - | PCMCIA_PV - | CFG_PCMCIA_TIMING ); +static void print_funcid (int func) +{ + puts (indent); + switch (func) { + case CISTPL_FUNCID_MULTI: + puts (" Multi-Function"); break; - } - case 5: - case 1: { /* map I/O window for data reg */ - win->or = ( PCMCIA_BSIZE_1K - | PCMCIA_PPS_16 - | PCMCIA_PRS_IO - | slotbit - | PCMCIA_PV - | CFG_PCMCIA_TIMING ); + case CISTPL_FUNCID_MEMORY: + puts (" Memory"); break; - } - case 6: - case 2: { /* map I/O window for cmd/ctrl reg block */ - win->or = ( PCMCIA_BSIZE_1K - | PCMCIA_PPS_8 - | PCMCIA_PRS_IO - | slotbit - | PCMCIA_PV - | CFG_PCMCIA_TIMING ); + case CISTPL_FUNCID_SERIAL: + puts (" Serial Port"); break; - } -#endif /* CONFIG_IDE_8xx_PCCARD */ -#ifdef CONFIG_HMI10 - case 3: { /* map I/O window for 4xUART data/ctrl */ - win->br += 0x40000; - win->or = ( PCMCIA_BSIZE_256K - | PCMCIA_PPS_8 - | PCMCIA_PRS_IO - | slotbit - | PCMCIA_PV - | CFG_PCMCIA_TIMING ); + case CISTPL_FUNCID_PARALLEL: + puts (" Parallel Port"); break; - } -#endif /* CONFIG_HMI10 */ - default: /* set to not valid */ - win->or = 0; + case CISTPL_FUNCID_FIXED: + puts (" Fixed Disk"); break; - } - - debug ("MemWin %d: PBR 0x%08lX POR %08lX\n", - i, win->br, win->or); - base += CFG_PCMCIA_MEM_SIZE; - ++win; - } - - for (i=0, rc=0, slot=_slot_; i<PCMCIA_SOCKETS_NO; i++, slot = !slot) { - /* turn off voltage */ - if ((rc = voltage_set(slot, 0, 0))) - continue; - - /* Enable external hardware */ - if ((rc = hardware_enable(slot))) - continue; - -#ifdef CONFIG_IDE_8xx_PCCARD - if ((rc = check_ide_device(i))) - continue; -#endif - } - return (rc); -} - -#endif /* CONFIG_PXA_PCMCIA */ - -#endif /* CONFIG_I82365 */ - -#ifdef CONFIG_PXA_PCMCIA - -static int hardware_enable (int slot) -{ - return 0; /* No hardware to enable */ -} - -static int hardware_disable(int slot) -{ - return 0; /* No hardware to disable */ -} - -static int voltage_set(int slot, int vcc, int vpp) -{ - return 0; -} - -void msWait(unsigned msVal) -{ - udelay(msVal*1000); -} - -int pcmcia_on (void) -{ - unsigned int reg_arr[] = { - 0x48000028, CFG_MCMEM0_VAL, - 0x4800002c, CFG_MCMEM1_VAL, - 0x48000030, CFG_MCATT0_VAL, - 0x48000034, CFG_MCATT1_VAL, - 0x48000038, CFG_MCIO0_VAL, - 0x4800003c, CFG_MCIO1_VAL, - - 0, 0 - }; - int i, rc; - -#ifdef CONFIG_EXADRON1 - int cardDetect; - volatile unsigned int *v_pBCRReg = - (volatile unsigned int *) 0x08000000; -#endif - - debug ("%s\n", __FUNCTION__); - - i = 0; - while (reg_arr[i]) - *((volatile unsigned int *) reg_arr[i++]) |= reg_arr[i++]; - udelay (1000); - - debug ("%s: programmed mem controller \n", __FUNCTION__); - -#ifdef CONFIG_EXADRON1 - -/*define useful BCR masks */ -#define BCR_CF_INIT_VAL 0x00007230 -#define BCR_CF_PWRON_BUSOFF_RESETOFF_VAL 0x00007231 -#define BCR_CF_PWRON_BUSOFF_RESETON_VAL 0x00007233 -#define BCR_CF_PWRON_BUSON_RESETON_VAL 0x00007213 -#define BCR_CF_PWRON_BUSON_RESETOFF_VAL 0x00007211 - - /* we see from the GPIO bit if the card is present */ - cardDetect = !(GPLR0 & GPIO_bit (14)); - - if (cardDetect) { - printf ("No PCMCIA card found!\n"); - } - - /* reset the card via the BCR line */ - *v_pBCRReg = (unsigned) BCR_CF_INIT_VAL; - msWait (500); - - *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETOFF_VAL; - msWait (500); - - *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETON_VAL; - msWait (500); - - *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETON_VAL; - msWait (500); - - *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETOFF_VAL; - msWait (1500); - - /* enable address bus */ - GPCR1 = 0x01; - /* and the first CF slot */ - MECR = 0x00000002; - -#endif /* EXADRON 1 */ - - rc = check_ide_device (0); /* use just slot 0 */ - - return rc; -} - -#endif /* CONFIG_PXA_PCMCIA */ - -/* -------------------------------------------------------------------- */ - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) - -#ifdef CONFIG_I82365 -static int pcmcia_off (void) -{ - printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n"); - - i82365_exit(); - - return 0; -} -#else - -#ifndef CONFIG_PXA_PCMCIA - -static int pcmcia_off (void) -{ - int i; - pcmcia_win_t *win; - - printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n"); - - /* clear interrupt state, and disable interrupts */ - ((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pscr = PCMCIA_MASK(_slot_); - ((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_per &= ~PCMCIA_MASK(_slot_); - - /* turn off interrupt and disable CxOE */ - PCMCIA_PGCRX(_slot_) = __MY_PCMCIA_GCRX_CXOE; - - /* turn off memory windows */ - win = (pcmcia_win_t *)(&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pbr0); - - for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) { - /* disable memory window */ - win->or = 0; - ++win; - } - - /* turn off voltage */ - voltage_set(_slot_, 0, 0); - - /* disable external hardware */ - printf ("Shutdown and Poweroff " PCMCIA_SLOT_MSG "\n"); - hardware_disable(_slot_); - return 0; -} - -#endif /* CONFIG_PXA_PCMCIA */ - -#endif /* CONFIG_I82365 */ - -#ifdef CONFIG_PXA_PCMCIA -static int pcmcia_off (void) -{ - return 0; -} -#endif - -#endif /* CFG_CMD_PCMCIA */ - -/* -------------------------------------------------------------------- */ - -#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA) - -#define MAX_TUPEL_SZ 512 -#define MAX_FEATURES 4 - -int ide_devices_found; -static int check_ide_device (int slot) -{ - volatile uchar *ident = NULL; - volatile uchar *feature_p[MAX_FEATURES]; - volatile uchar *p, *start, *addr; - int n_features = 0; - uchar func_id = ~0; - uchar code, len; - ushort config_base = 0; - int found = 0; - int i; - - addr = (volatile uchar *)(CFG_PCMCIA_MEM_ADDR + - CFG_PCMCIA_MEM_SIZE * (slot * 4)); - debug ("PCMCIA MEM: %08lX\n", (ulong)addr); - - start = p = (volatile uchar *) addr; - - while ((p - start) < MAX_TUPEL_SZ) { - - code = *p; p += 2; - - if (code == 0xFF) { /* End of chain */ + case CISTPL_FUNCID_VIDEO: + puts (" Video Adapter"); break; - } - - len = *p; p += 2; -#if defined(DEBUG) && (DEBUG > 1) - { volatile uchar *q = p; - printf ("\nTuple code %02x length %d\n\tData:", - code, len); - - for (i = 0; i < len; ++i) { - printf (" %02x", *q); - q+= 2; - } - } -#endif /* DEBUG */ - switch (code) { - case CISTPL_VERS_1: - ident = p + 4; + case CISTPL_FUNCID_NETWORK: + puts (" Network Adapter"); break; - case CISTPL_FUNCID: - /* Fix for broken SanDisk which may have 0x80 bit set */ - func_id = *p & 0x7F; + case CISTPL_FUNCID_AIMS: + puts (" AIMS Card"); break; - case CISTPL_FUNCE: - if (n_features < MAX_FEATURES) - feature_p[n_features++] = p; + case CISTPL_FUNCID_SCSI: + puts (" SCSI Adapter"); break; - case CISTPL_CONFIG: - config_base = (*(p+6) << 8) + (*(p+4)); - debug ("\n## Config_base = %04x ###\n", config_base); default: + puts (" Unknown"); break; - } - p += 2 * len; - } - - found = identify (ident); - - if (func_id != ((uchar)~0)) { - print_funcid (func_id); - - if (func_id == CISTPL_FUNCID_FIXED) - found = 1; - else - return (1); /* no disk drive */ - } - - for (i=0; i<n_features; ++i) { - print_fixed (feature_p[i]); - } - - if (!found) { - printf ("unknown card type\n"); - return (1); - } - - ide_devices_found |= (1 << slot); - -#if CONFIG_CPC45 -#else - /* set I/O area in config reg -> only valid for ARGOSY D5!!! */ - *((uchar *)(addr + config_base)) = 1; -#endif -#if 0 - printf("\n## Config_base = %04x ###\n", config_base); - printf("Configuration Option Register: %02x @ %x\n", readb(addr + config_base), addr + config_base); - printf("Card Configuration and Status Register: %02x\n", readb(addr + config_base + 2)); - printf("Pin Replacement Register Register: %02x\n", readb(addr + config_base + 4)); - printf("Socket and Copy Register: %02x\n", readb(addr + config_base + 6)); -#endif - return (0); -} -#endif /* CONFIG_IDE_8xx_PCCARD */ - -/* -------------------------------------------------------------------- */ - - -/* -------------------------------------------------------------------- */ -/* board specific stuff: */ -/* voltage_set(), hardware_enable() and hardware_disable() */ -/* -------------------------------------------------------------------- */ - -/* -------------------------------------------------------------------- */ -/* RPX Boards from Embedded Planet */ -/* -------------------------------------------------------------------- */ - -#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) - -/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks. - * SYPCR is write once only, therefore must the slowest memory be faster - * than the bus monitor or we will get a machine check due to the bus timeout. - */ - -#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE" - -#undef PCMCIA_BMT_LIMIT -#define PCMCIA_BMT_LIMIT (6*8) - -static int voltage_set(int slot, int vcc, int vpp) -{ - u_long reg = 0; - - switch(vcc) { - case 0: break; - case 33: reg |= BCSR1_PCVCTL4; break; - case 50: reg |= BCSR1_PCVCTL5; break; - default: return 1; - } - - switch(vpp) { - case 0: break; - case 33: - case 50: - if(vcc == vpp) - reg |= BCSR1_PCVCTL6; - else - return 1; - break; - case 120: - reg |= BCSR1_PCVCTL7; - default: return 1; - } - - if(vcc == 120) - return 1; - - /* first, turn off all power */ - - *((uint *)RPX_CSR_ADDR) &= ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5 - | BCSR1_PCVCTL6 | BCSR1_PCVCTL7); - - /* enable new powersettings */ - - *((uint *)RPX_CSR_ADDR) |= reg; - - return 0; -} - -#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V -static int hardware_enable (int slot) -{ - return 0; /* No hardware to enable */ -} -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -static int hardware_disable(int slot) -{ - return 0; /* No hardware to disable */ -} -#endif /* CFG_CMD_PCMCIA */ -#endif /* CONFIG_RPXCLASSIC */ - -/* -------------------------------------------------------------------- */ -/* (F)ADS Boards from Motorola */ -/* -------------------------------------------------------------------- */ - -#if defined(CONFIG_ADS) || defined(CONFIG_FADS) - -#ifdef CONFIG_ADS -#define PCMCIA_BOARD_MSG "ADS" -#define PCMCIA_GLITCHY_CD /* My ADS board needs this */ -#else -#define PCMCIA_BOARD_MSG "FADS" -#endif - -static int voltage_set(int slot, int vcc, int vpp) -{ - u_long reg = 0; - - switch(vpp) { - case 0: reg = 0; break; - case 50: reg = 1; break; - case 120: reg = 2; break; - default: return 1; - } - - switch(vcc) { - case 0: reg = 0; break; -#ifdef CONFIG_ADS - case 50: reg = BCSR1_PCCVCCON; break; -#endif -#ifdef CONFIG_FADS - case 33: reg = BCSR1_PCCVCC0 | BCSR1_PCCVCC1; break; - case 50: reg = BCSR1_PCCVCC1; break; -#endif - default: return 1; - } - - /* first, turn off all power */ - -#ifdef CONFIG_ADS - *((uint *)BCSR1) |= BCSR1_PCCVCCON; -#endif -#ifdef CONFIG_FADS - *((uint *)BCSR1) &= ~(BCSR1_PCCVCC0 | BCSR1_PCCVCC1); -#endif - *((uint *)BCSR1) &= ~BCSR1_PCCVPP_MASK; - - /* enable new powersettings */ - -#ifdef CONFIG_ADS - *((uint *)BCSR1) &= ~reg; -#endif -#ifdef CONFIG_FADS - *((uint *)BCSR1) |= reg; -#endif - - *((uint *)BCSR1) |= reg << 20; - - return 0; -} - -#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V - -static int hardware_enable(int slot) -{ - *((uint *)BCSR1) &= ~BCSR1_PCCEN; - return 0; -} - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -static int hardware_disable(int slot) -{ - *((uint *)BCSR1) &= ~BCSR1_PCCEN; - return 0; -} -#endif /* CFG_CMD_PCMCIA */ - -#endif /* (F)ADS */ - -/* -------------------------------------------------------------------- */ -/* TQM8xxL Boards by TQ Components */ -/* SC8xx Boards by SinoVee Microsystems */ -/* -------------------------------------------------------------------- */ - -#if (defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)) \ - && !defined(CONFIG_VIRTLAB2) - -#if defined(CONFIG_TQM8xxL) -#define PCMCIA_BOARD_MSG "TQM8xxL" -#endif -#if defined(CONFIG_SVM_SC8xx) -#define PCMCIA_BOARD_MSG "SC8xx" -#endif - -static int hardware_enable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; - uint reg, mask; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - immap = (immap_t *)CFG_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - - /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ - sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(slot); - pcmp->pcmc_per &= ~PCMCIA_MASK(slot); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ -#ifndef NSCU_OE_INV - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ -#endif - PCMCIA_PGCRX(slot) = reg; - udelay(500); - -#ifndef CONFIG_HMI10 -#ifndef CONFIG_NSCU - /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable - */ - immap->im_ioport.iop_pcpar &= ~(0x0002 | 0x0004); - immap->im_ioport.iop_pcso &= ~(0x0002 | 0x0004); - /* remove all power */ - - immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004); -#endif -#else /* CONFIG_HMI10 */ - /* - * Configure Port B pins for - * 5 Volts Enable and 3 Volts enable - */ - immap->im_cpm.cp_pbpar &= ~(0x00000300); - - /* remove all power */ - immap->im_cpm.cp_pbdat |= 0x00000300; -#endif /* CONFIG_HMI10 */ - - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); -#ifndef CONFIG_HMI10 - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { -#else - if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) { -#endif /* CONFIG_HMI10 */ - printf (" No Card found\n"); - return (1); - } - - /* - * Power On. - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - reg = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - reg, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); -#ifndef CONFIG_NSCU - if ((reg & mask) == mask) { -#ifndef CONFIG_HMI10 - immap->im_ioport.iop_pcdat |= 0x0004; -#else - immap->im_cpm.cp_pbdat &= ~(0x0000100); -#endif /* CONFIG_HMI10 */ - puts (" 5.0V card found: "); - } else { -#ifndef CONFIG_HMI10 - immap->im_ioport.iop_pcdat |= 0x0002; -#else - immap->im_cpm.cp_pbdat &= ~(0x0000200); -#endif /* CONFIG_HMI10 */ - puts (" 3.3V card found: "); - } -#ifndef CONFIG_HMI10 - immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004); -#else - immap->im_cpm.cp_pbdir |= 0x00000300; -#endif /* CONFIG_HMI10 */ -#else - if ((reg & mask) == mask) { - puts (" 5.0V card found: "); - } else { - puts (" 3.3V card found: "); - } -#endif -#if 0 - /* VCC switch error flag, PCMCIA slot INPACK_ pin */ - cp->cp_pbdir &= ~(0x0020 | 0x0010); - cp->cp_pbpar &= ~(0x0020 | 0x0010); - udelay(500000); -#endif - udelay(1000); - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(slot); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ -#ifndef NSCU_OE_INV - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ -#else - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ -#endif - PCMCIA_PGCRX(slot) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -static int hardware_disable(int slot) -{ - volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - -#ifndef CONFIG_HMI10 -#ifndef CONFIG_NSCU - /* remove all power */ - immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004); -#endif -#else /* CONFIG_HMI10 */ - immap->im_cpm.cp_pbdat |= 0x00000300; -#endif /* CONFIG_HMI10 */ - - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ -#ifndef NSCU_OE_INV - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ -#endif - PCMCIA_PGCRX(slot) = reg; - - udelay(10000); - - return (0); -} -#endif /* CFG_CMD_PCMCIA */ - -#ifdef CONFIG_NSCU -static int voltage_set(int slot, int vcc, int vpp) -{ - return 0; -} -#else -static int voltage_set(int slot, int vcc, int vpp) -{ - volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("voltage_set: " - PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(slot); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ -#ifndef NSCU_OE_INV - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ -#else - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ -#endif - PCMCIA_PGCRX(slot) = reg; - udelay(500); - -#ifndef CONFIG_HMI10 - /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable, - * Turn off all power - */ - debug ("PCMCIA power OFF\n"); - immap->im_ioport.iop_pcpar &= ~(0x0002 | 0x0004); - immap->im_ioport.iop_pcso &= ~(0x0002 | 0x0004); - immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004); - - reg = 0; - switch(vcc) { - case 0: break; - case 33: reg |= 0x0002; break; - case 50: reg |= 0x0004; break; - default: goto done; - } -#else /* CONFIG_HMI10 */ - /* - * Configure Port B pins for - * 5 Volts Enable and 3 Volts enable, - * Turn off all power - */ - debug ("PCMCIA power OFF\n"); - immap->im_cpm.cp_pbpar &= ~(0x00000300); - /* remove all power */ - - immap->im_cpm.cp_pbdat |= 0x00000300; - - reg = 0; - switch(vcc) { - case 0: break; - case 33: reg |= 0x00000200; break; - case 50: reg |= 0x00000100; break; - default: goto done; -} -#endif /* CONFIG_HMI10 */ - - /* Checking supported voltages */ - - debug ("PIPR: 0x%x --> %s\n", - pcmp->pcmc_pipr, - (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); - -#ifndef CONFIG_HMI10 - immap->im_ioport.iop_pcdat |= reg; - immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004); -#else - immap->im_cpm.cp_pbdat &= !reg; - immap->im_cpm.cp_pbdir |= 0x00000300; -#endif /* CONFIG_HMI10 */ - if (reg) { -#ifndef CONFIG_HMI10 - debug ("PCMCIA powered at %sV\n", - (reg&0x0004) ? "5.0" : "3.3"); -#else - debug ("PCMCIA powered at %sV\n", - (reg&0x00000200) ? "5.0" : "3.3"); -#endif /* CONFIG_HMI10 */ - } else { - debug ("PCMCIA powered down\n"); - } - -done: - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(slot); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ -#ifndef NSCU_OE_INV - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ -#else - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ -#endif - PCMCIA_PGCRX(slot) = reg; - udelay(500); - - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", - slot+'A'); - return (0); -} -#endif - -#endif /* TQM8xxL */ - -/* -------------------------------------------------------------------- */ -/* Virtlab2 Board by TQ Components */ -/* -------------------------------------------------------------------- */ - -#if defined(CONFIG_VIRTLAB2) -#define PCMCIA_BOARD_MSG "Virtlab2" - -static int hardware_enable(int slot) -{ - volatile pcmconf8xx_t *pcmp = - (pcmconf8xx_t *)&(((immap_t *)CFG_IMMR)->im_pcmcia); - volatile unsigned char *powerctl = - (volatile unsigned char *)PCMCIA_CTRL; - volatile sysconf8xx_t *sysp = - (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); - unsigned int reg, mask; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - /* - * Configure SIUMCR to enable PCMCIA port B - */ - sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(slot); - pcmp->pcmc_per &= ~PCMCIA_MASK(slot); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - - PCMCIA_PGCRX(slot) = reg; - udelay(500); - - /* remove all power */ - *powerctl = 0; - - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On. - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - reg = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); - - if ((reg & mask) == mask) { - *powerctl = 2; /* Enable 5V Vccout */ - puts (" 5.0V card found: "); - } else { - *powerctl = 1; /* Enable 3.3 V Vccout */ - puts (" 3.3V card found: "); - } - - udelay(1000); - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(slot); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - - PCMCIA_PGCRX(slot) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -static int hardware_disable(int slot) -{ - volatile unsigned char *powerctl = - (volatile unsigned char *)PCMCIA_CTRL; - unsigned long reg; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - /* remove all power */ - *powerctl = 0; - - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - - PCMCIA_PGCRX(slot) = reg; - - udelay(10000); - - return (0); -} -#endif - -static int voltage_set(int slot, int vcc, int vpp) -{ -#ifdef DEBUG - volatile pcmconf8xx_t *pcmp = - (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); -#endif - volatile unsigned char *powerctl = - (volatile unsigned char *)PCMCIA_CTRL; - unsigned long reg; - - debug ("voltage_set: " PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(slot); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - - PCMCIA_PGCRX(slot) = reg; - udelay(500); - - /* - * Configure pins for 5 Volts Enable and 3 Volts enable, - * Turn off all power. - */ - debug ("PCMCIA power OFF\n"); - reg = 0; - switch(vcc) { - case 0: break; - case 33: reg = 0x0001; break; - case 50: reg = 0x0002; break; - default: goto done; - } - - /* Checking supported voltages */ - - debug ("PIPR: 0x%x --> %s\n", pcmp->pcmc_pipr, - (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); - - *powerctl = reg; - - if (reg) { - debug ("PCMCIA powered at %sV\n", (reg&0x0004) ? "5.0" : "3.3"); - } else { - debug ("PCMCIA powered down\n"); - } - -done: - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(slot); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - - PCMCIA_PGCRX(slot) = reg; - udelay(500); - - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", slot+'A'); - return (0); -} -#endif /* CONFIG_VIRTLAB2 */ - -/* -------------------------------------------------------------------- */ -/* LWMON Board */ -/* -------------------------------------------------------------------- */ - -#if defined(CONFIG_LWMON) - -#define PCMCIA_BOARD_MSG "LWMON" - -/* #define's for MAX1604 Power Switch */ -#define MAX1604_OP_SUS 0x80 -#define MAX1604_VCCBON 0x40 -#define MAX1604_VCC_35 0x20 -#define MAX1604_VCCBHIZ 0x10 -#define MAX1604_VPPBON 0x08 -#define MAX1604_VPPBPBPGM 0x04 -#define MAX1604_VPPBHIZ 0x02 -/* reserved 0x01 */ - -static int hardware_enable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; - uint reg, mask; - uchar val; - - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - /* Switch on PCMCIA port in PIC register 0x60 */ - reg = pic_read (0x60); - debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); - reg &= ~0x10; - /* reg |= 0x08; Vpp not needed */ - pic_write (0x60, reg); -#ifdef DEBUG - reg = pic_read (0x60); - printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); -#endif - udelay(10000); - - immap = (immap_t *)CFG_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - - /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ - sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On. - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - reg = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - reg, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); - if ((reg & mask) == mask) { - val = 0; /* VCCB3/5 = 0 ==> use Vx = 5.0 V */ - puts (" 5.0V card found: "); - } else { - val = MAX1604_VCC_35; /* VCCB3/5 = 1 ==> use Vy = 3.3 V */ - puts (" 3.3V card found: "); - } - - /* switch VCC on */ - val |= MAX1604_OP_SUS | MAX1604_VCCBON; - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1); - - udelay(500000); - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -static int hardware_disable(int slot) -{ - volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; - u_long reg; - uchar val; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - - /* remove all power, put output in high impedance state */ - val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ; - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1); - - /* Configure PCMCIA General Control Register */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - /* Switch off PCMCIA port in PIC register 0x60 */ - reg = pic_read (0x60); - debug ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); - reg |= 0x10; - reg &= ~0x08; - pic_write (0x60, reg); -#ifdef DEBUG - reg = pic_read (0x60); - printf ("[%d] PIC read: reg_60 = 0x%02x\n", __LINE__, reg); -#endif - udelay(10000); - - return (0); -} -#endif /* CFG_CMD_PCMCIA */ - - -static int voltage_set(int slot, int vcc, int vpp) -{ - volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; - u_long reg; - uchar val; - - debug ("voltage_set: " - PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Turn off all power (switch to high impedance) - */ - debug ("PCMCIA power OFF\n"); - val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ; - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1); - - val = 0; - switch(vcc) { - case 0: break; - case 33: val = MAX1604_VCC_35; break; - case 50: break; - default: goto done; - } - - /* Checking supported voltages */ - - debug ("PIPR: 0x%x --> %s\n", - pcmp->pcmc_pipr, - (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); - - i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1); - if (val) { - debug ("PCMCIA powered at %sV\n", - (val & MAX1604_VCC_35) ? "3.3" : "5.0"); - } else { - debug ("PCMCIA powered down\n"); - } - -done: - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", - slot+'A'); - return (0); -} - -#endif /* LWMON */ - -/* -------------------------------------------------------------------- */ -/* GTH board by Corelatus AB */ -/* -------------------------------------------------------------------- */ -#if defined(CONFIG_GTH) - -#define PCMCIA_BOARD_MSG "GTH COMPACT FLASH" - -static int voltage_set (int slot, int vcc, int vpp) -{ /* Do nothing */ - return 0; -} - -static int hardware_enable (int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; - uint reg, mask; - - debug ("hardware_enable: GTH Slot %c\n", 'A' + slot); - - immap = (immap_t *) CFG_IMMR; - sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm)); - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK (_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX (_slot_) = reg; - udelay (500); - - /* - * Make sure there is a card in the slot, - * then configure the interface. - */ - udelay (10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__, __FUNCTION__, - &(pcmp->pcmc_pipr), pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & 0x98000000) { - printf (" No Card found\n"); - return (1); - } - - mask = PCMCIA_VS1 (slot) | PCMCIA_VS2 (slot); - reg = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - reg, - (reg & PCMCIA_VS1 (slot)) ? "n" : "ff", - (reg & PCMCIA_VS2 (slot)) ? "n" : "ff"); - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX (_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX (_slot_) = reg; - - udelay (250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return 0; -} -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -static int hardware_disable(int slot) -{ - return 0; /* No hardware to disable */ -} -#endif /* CFG_CMD_PCMCIA */ -#endif /* CONFIG_GTH */ - -/* -------------------------------------------------------------------- */ -/* ICU862 Boards by Cambridge Broadband Ltd. */ -/* -------------------------------------------------------------------- */ - -#if defined(CONFIG_ICU862) - -#define PCMCIA_BOARD_MSG "ICU862" - -static void cfg_port_B (void); - -static int hardware_enable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; - uint reg, pipr, mask; - int i; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - immap = (immap_t *)CFG_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - - /* Configure Port B for TPS2205 PC-Card Power-Interface Switch */ - cfg_port_B (); - - /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ - sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - pipr = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - pipr, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); - - reg = cp->cp_pbdat; - if ((pipr & mask) == mask) { - reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ - TPS2205_VCC3); /* 3V off */ - reg &= ~(TPS2205_VCC5); /* 5V on */ - puts (" 5.0V card found: "); - } else { - reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ - TPS2205_VCC5); /* 5V off */ - reg &= ~(TPS2205_VCC3); /* 3V on */ - puts (" 3.3V card found: "); - } - - debug ("\nPB DAT: %08x -> 3.3V %s 5.0V %s VPP_PGM %s VPP_VCC %s\n", - reg, - (reg & TPS2205_VCC3) ? "off" : "on", - (reg & TPS2205_VCC5) ? "off" : "on", - (reg & TPS2205_VPP_PGM) ? "off" : "on", - (reg & TPS2205_VPP_VCC) ? "off" : "on" ); - - cp->cp_pbdat = reg; - - /* Wait 500 ms; use this to check for over-current */ - for (i=0; i<5000; ++i) { - if ((cp->cp_pbdat & TPS2205_OC) == 0) { - printf (" *** Overcurrent - Safety shutdown ***\n"); - cp->cp_pbdat &= ~(TPS2205_SHDN); - return (1); - } - udelay (100); - } - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -static int hardware_disable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - immap = (immap_t *)CFG_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - - /* Shut down */ - cp->cp_pbdat &= ~(TPS2205_SHDN); - - /* Configure PCMCIA General Control Register */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(10000); - - return (0); -} -#endif /* CFG_CMD_PCMCIA */ - - -static int voltage_set(int slot, int vcc, int vpp) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("voltage_set: " - PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - immap = (immap_t *)CFG_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable, - * Turn all power pins to Hi-Z - */ - debug ("PCMCIA power OFF\n"); - cfg_port_B (); /* Enables switch, but all in Hi-Z */ - - reg = cp->cp_pbdat; - - switch(vcc) { - case 0: break; /* Switch off */ - case 33: reg &= ~TPS2205_VCC3; break; /* Switch on 3.3V */ - case 50: reg &= ~TPS2205_VCC5; break; /* Switch on 5.0V */ - default: goto done; - } - - /* Checking supported voltages */ - - debug ("PIPR: 0x%x --> %s\n", - pcmp->pcmc_pipr, - (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); - - cp->cp_pbdat = reg; - -#ifdef DEBUG - { - char *s; - - if ((reg & TPS2205_VCC3) == 0) { - s = "at 3.3V"; - } else if ((reg & TPS2205_VCC5) == 0) { - s = "at 5.0V"; - } else { - s = "down"; - } - printf ("PCMCIA powered %s\n", s); - } -#endif - -done: - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", - slot+'A'); - return (0); -} - -static void cfg_port_B (void) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - uint reg; - - immap = (immap_t *)CFG_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - - /* - * Configure Port B for TPS2205 PC-Card Power-Interface Switch - * - * Switch off all voltages, assert shutdown - */ - reg = cp->cp_pbdat; - reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ - TPS2205_VCC3 | TPS2205_VCC5 | /* VAVCC => Hi-Z */ - TPS2205_SHDN); /* enable switch */ - cp->cp_pbdat = reg; - - cp->cp_pbpar &= ~(TPS2205_INPUTS | TPS2205_OUTPUTS); - - reg = cp->cp_pbdir & ~(TPS2205_INPUTS); - cp->cp_pbdir = reg | TPS2205_OUTPUTS; - - debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n", - cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat); -} - -#endif /* ICU862 */ - - -/* -------------------------------------------------------------------- */ -/* C2MON Boards by TTTech Computertechnik AG */ -/* -------------------------------------------------------------------- */ - -#if defined(CONFIG_C2MON) - -#define PCMCIA_BOARD_MSG "C2MON" - -static void cfg_ports (void); - -static int hardware_enable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; - uint reg, pipr, mask; - ushort sreg; - int i; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - immap = (immap_t *)CFG_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - - /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ - cfg_ports (); - - /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ - sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - pipr = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - pipr, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); - - sreg = immap->im_ioport.iop_pcdat; - if ((pipr & mask) == mask) { - sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1 | /* VAVPP => Hi-Z */ - TPS2211_VCCD1); /* 5V on */ - sreg &= ~(TPS2211_VCCD0); /* 3V off */ - puts (" 5.0V card found: "); - } else { - sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1 | /* VAVPP => Hi-Z */ - TPS2211_VCCD0); /* 3V on */ - sreg &= ~(TPS2211_VCCD1); /* 5V off */ - puts (" 3.3V card found: "); - } - - debug ("\nPC DAT: %04x -> 3.3V %s 5.0V %s\n", - sreg, - ( (sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) ? "on" : "off", - (!(sreg & TPS2211_VCCD0) && (sreg & TPS2211_VCCD1)) ? "on" : "off" - ); - - immap->im_ioport.iop_pcdat = sreg; - - /* Wait 500 ms; use this to check for over-current */ - for (i=0; i<5000; ++i) { - if ((cp->cp_pbdat & TPS2211_OC) == 0) { - printf (" *** Overcurrent - Safety shutdown ***\n"); - immap->im_ioport.iop_pcdat &= ~(TPS2211_VCCD0|TPS2211_VCCD1); - return (1); - } - udelay (100); - } - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -static int hardware_disable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - - /* Configure PCMCIA General Control Register */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - /* ALl voltages off / Hi-Z */ - immap->im_ioport.iop_pcdat |= (TPS2211_VPPD0 | TPS2211_VPPD1 | - TPS2211_VCCD0 | TPS2211_VCCD1 ); - - udelay(10000); - - return (0); -} -#endif /* CFG_CMD_PCMCIA */ - - -static int voltage_set(int slot, int vcc, int vpp) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - u_long reg; - ushort sreg; - - debug ("voltage_set: " - PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - immap = (immap_t *)CFG_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable, - * Turn all power pins to Hi-Z - */ - debug ("PCMCIA power OFF\n"); - cfg_ports (); /* Enables switch, but all in Hi-Z */ - - sreg = immap->im_ioport.iop_pcdat; - sreg |= TPS2211_VPPD0 | TPS2211_VPPD1; /* VAVPP always Hi-Z */ - - switch(vcc) { - case 0: break; /* Switch off */ - case 33: sreg |= TPS2211_VCCD0; /* Switch on 3.3V */ - sreg &= ~TPS2211_VCCD1; - break; - case 50: sreg &= ~TPS2211_VCCD0; /* Switch on 5.0V */ - sreg |= TPS2211_VCCD1; - break; - default: goto done; - } - - /* Checking supported voltages */ - - debug ("PIPR: 0x%x --> %s\n", - pcmp->pcmc_pipr, - (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); - - immap->im_ioport.iop_pcdat = sreg; - -#ifdef DEBUG - { - char *s; - - if ((sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) { - s = "at 3.3V"; - } else if (!(sreg & TPS2211_VCCD0) && (sreg & TPS2211_VCCD1)) { - s = "at 5.0V"; - } else { - s = "down"; - } - printf ("PCMCIA powered %s\n", s); - } -#endif - -done: - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", - slot+'A'); - return (0); -} - -static void cfg_ports (void) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - ushort sreg; - - immap = (immap_t *)CFG_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - - /* - * Configure Port C for TPS2211 PC-Card Power-Interface Switch - * - * Switch off all voltages, assert shutdown - */ - sreg = immap->im_ioport.iop_pcdat; - sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1); /* VAVPP => Hi-Z */ - sreg &= ~(TPS2211_VCCD0 | TPS2211_VCCD1); /* 3V and 5V off */ - immap->im_ioport.iop_pcdat = sreg; - - immap->im_ioport.iop_pcpar &= ~(TPS2211_OUTPUTS); - immap->im_ioport.iop_pcdir |= TPS2211_OUTPUTS; - - debug ("Set Port C: PAR: %04x DIR: %04x DAT: %04x\n", - immap->im_ioport.iop_pcpar, - immap->im_ioport.iop_pcdir, - immap->im_ioport.iop_pcdat); - - /* - * Configure Port B for TPS2211 PC-Card Power-Interface Switch - * - * Over-Current Input only - */ - cp->cp_pbpar &= ~(TPS2211_INPUTS); - cp->cp_pbdir &= ~(TPS2211_INPUTS); - - debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n", - cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat); -} - -#endif /* C2MON */ - -/* -------------------------------------------------------------------- */ -/* MBX board from Morotola */ -/* -------------------------------------------------------------------- */ - -#if defined( CONFIG_MBX ) -#include <../board/mbx8xx/csr.h> - -/* A lot of this has been taken from the RPX code in this file it works from me. - I have added the voltage selection for the MBX board. */ - -/* MBX voltage bit in control register #2 */ -#define CR2_VPP12 ((uchar)0x10) -#define CR2_VPPVDD ((uchar)0x20) -#define CR2_VDD5 ((uchar)0x40) -#define CR2_VDD3 ((uchar)0x80) - -#define PCMCIA_BOARD_MSG "MBX860" - -static int voltage_set (int slot, int vcc, int vpp) -{ - uchar reg = 0; - - debug ("voltage_set: PCMCIA_BOARD_MSG Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A' + slot, vcc / 10, vcc % 10, vpp / 10, vcc % 10); - - switch (vcc) { - case 0: - break; - case 33: - reg |= CR2_VDD3; - break; - case 50: - reg |= CR2_VDD5; - break; - default: - return 1; - } - - switch (vpp) { - case 0: - break; - case 33: - case 50: - if (vcc == vpp) { - reg |= CR2_VPPVDD; - } else { - return 1; - } - break; - case 120: - reg |= CR2_VPP12; - break; - default: - return 1; - } - - /* first, turn off all power */ - MBX_CSR2 &= ~(CR2_VDDSEL | CR2_VPPSEL); - - /* enable new powersettings */ - MBX_CSR2 |= reg; - debug ("MBX_CSR2 read = 0x%02x\n", MBX_CSR2); - - return (0); -} - -static int hardware_enable (int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; - uint reg, mask; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", - 'A' + slot); - - udelay (10000); - - immap = (immap_t *) CFG_IMMR; - sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm)); - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK (_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX (_slot_) = reg; - udelay (500); - - /* remove all power */ - voltage_set (slot, 0, 0); - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); -#ifndef CONFIG_HMI10 - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { -#else - if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) { -#endif /* CONFIG_HMI10 */ - printf (" No Card found\n"); - return (1); - } - - /* - * Power On. - */ - mask = PCMCIA_VS1 (_slot_) | PCMCIA_VS2 (_slot_); - reg = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg, - (reg & PCMCIA_VS1 (slot)) ? "n" : "ff", - (reg & PCMCIA_VS2 (slot)) ? "n" : "ff"); - - if ((reg & mask) == mask) { - voltage_set (_slot_, 50, 0); - printf (" 5.0V card found: "); - } else { - voltage_set (_slot_, 33, 0); - printf (" 3.3V card found: "); - } - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX (_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX (_slot_) = reg; - - udelay (250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -static int hardware_disable (int slot) -{ - return 0; /* No hardware to disable */ -} -#endif /* CFG_CMD_PCMCIA */ -#endif /* CONFIG_MBX */ -/* -------------------------------------------------------------------- */ -/* R360MPI Board */ -/* -------------------------------------------------------------------- */ - -#if defined(CONFIG_R360MPI) - -#define PCMCIA_BOARD_MSG "R360MPI" - - -static int hardware_enable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; - uint reg, mask; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - immap = (immap_t *)CFG_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - - /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ - sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Configure Ports A, B & C pins for - * 5 Volts Enable and 3 Volts enable - */ - immap->im_ioport.iop_pcpar &= ~(0x0400); - immap->im_ioport.iop_pcso &= ~(0x0400);/* - immap->im_ioport.iop_pcdir |= 0x0400;*/ - - immap->im_ioport.iop_papar &= ~(0x0200);/* - immap->im_ioport.iop_padir |= 0x0200;*/ -#if 0 - immap->im_ioport.iop_pbpar &= ~(0xC000); - immap->im_ioport.iop_pbdir &= ~(0xC000); -#endif - /* remove all power */ - - immap->im_ioport.iop_pcdat |= 0x0400; - immap->im_ioport.iop_padat |= 0x0200; - - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On. - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - reg = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - reg, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); - if ((reg & mask) == mask) { - immap->im_ioport.iop_pcdat &= ~(0x4000); - puts (" 5.0V card found: "); - } else { - immap->im_ioport.iop_padat &= ~(0x0002); - puts (" 3.3V card found: "); - } - immap->im_ioport.iop_pcdir |= 0x0400; - immap->im_ioport.iop_padir |= 0x0200; -#if 0 - /* VCC switch error flag, PCMCIA slot INPACK_ pin */ - cp->cp_pbdir &= ~(0x0020 | 0x0010); - cp->cp_pbpar &= ~(0x0020 | 0x0010); - udelay(500000); -#endif - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -static int hardware_disable(int slot) -{ - volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - - /* remove all power */ - immap->im_ioport.iop_pcdat |= 0x0400; - immap->im_ioport.iop_padat |= 0x0200; - - /* Configure PCMCIA General Control Register */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(10000); - - return (0); -} -#endif /* CFG_CMD_PCMCIA */ - - -static int voltage_set(int slot, int vcc, int vpp) -{ - volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("voltage_set: " - PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Configure Ports A & C pins for - * 5 Volts Enable and 3 Volts enable, - * Turn off all power - */ - debug ("PCMCIA power OFF\n"); - immap->im_ioport.iop_pcpar &= ~(0x0400); - immap->im_ioport.iop_pcso &= ~(0x0400);/* - immap->im_ioport.iop_pcdir |= 0x0400;*/ - - immap->im_ioport.iop_papar &= ~(0x0200);/* - immap->im_ioport.iop_padir |= 0x0200;*/ - - immap->im_ioport.iop_pcdat |= 0x0400; - immap->im_ioport.iop_padat |= 0x0200; - - reg = 0; - switch(vcc) { - case 0: break; - case 33: reg |= 0x0200; break; - case 50: reg |= 0x0400; break; - default: goto done; - } - - /* Checking supported voltages */ - - debug ("PIPR: 0x%x --> %s\n", - pcmp->pcmc_pipr, - (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); - - if (reg & 0x0200) - immap->im_ioport.iop_pcdat &= !reg; - if (reg & 0x0400) - immap->im_ioport.iop_padat &= !reg; - immap->im_ioport.iop_pcdir |= 0x0200; - immap->im_ioport.iop_padir |= 0x0400; - if (reg) { - debug ("PCMCIA powered at %sV\n", - (reg&0x0400) ? "5.0" : "3.3"); - } else { - debug ("PCMCIA powered down\n"); - } - -done: - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", - slot+'A'); - return (0); -} - -#endif /* R360MPI */ - -/* -------------------------------------------------------------------- */ -/* KUP4K and KUP4X Boards */ -/* -------------------------------------------------------------------- */ -#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) - -#define PCMCIA_BOARD_MSG "KUP" - -#define KUP4K_PCMCIA_B_3V3 (0x00020000) - -static int hardware_enable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; - uint reg, mask; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - immap = (immap_t *)CFG_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - - /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ - sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(slot); - pcmp->pcmc_per &= ~PCMCIA_MASK(slot); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(slot) = reg; - udelay(2500); - - /* - * Configure Port B pins for - * 3 Volts enable - */ - if (slot) { /* Slot A is built-in */ - cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3; - cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3; - /* remove all power */ - cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */ - } - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On. - */ - printf("%s Slot %c:", slot ? "" : "\n", 'A' + slot); - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - reg = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - reg, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); - if ((reg & mask) == mask) { - puts (" 5.0V card found: NOT SUPPORTED !!!\n"); - } else { - if(slot) - cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3; - puts (" 3.3V card found: "); - } -#if 0 - /* VCC switch error flag, PCMCIA slot INPACK_ pin */ - cp->cp_pbdir &= ~(0x0020 | 0x0010); - cp->cp_pbpar &= ~(0x0020 | 0x0010); - udelay(500000); -#endif - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(slot); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(slot) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -static int hardware_disable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - - /* remove all power */ - if (slot) - cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; - - /* Configure PCMCIA General Control Register */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(slot) = reg; - - udelay(10000); - - return (0); -} -#endif /* CFG_CMD_PCMCIA */ - - -static int voltage_set(int slot, int vcc, int vpp) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("voltage_set: " \ - PCMCIA_BOARD_MSG \ - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - if (!slot) /* Slot A is not configurable */ - return 0; - - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(slot); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(slot) = reg; - udelay(500); - - debug ("PCMCIA power OFF\n"); - /* - * Configure Port B pins for - * 3 Volts enable - */ - cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3; - cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3; - /* remove all power */ - cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */ - - switch(vcc) { - case 0: break; - case 33: - cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3; - debug ("PCMCIA powered at 3.3V\n"); - break; - case 50: - debug ("PCMCIA: 5Volt vcc not supported\n"); - break; - default: - puts("PCMCIA: vcc not supported"); - break; - } - udelay(10000); - /* Checking supported voltages */ - - debug ("PIPR: 0x%x --> %s\n", - pcmp->pcmc_pipr, - (pcmp->pcmc_pipr & (0x80000000 >> (slot << 4))) - ? "only 5 V --> NOT SUPPORTED" - : "can do 3.3V"); - - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(slot); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(slot) = reg; - udelay(500); - - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", - slot+'A'); - return (0); -} - -#endif /* KUP4K || KUP4X */ - - -/* -------------------------------------------------------------------- */ -/* End of Board Specific Stuff */ -/* -------------------------------------------------------------------- */ - - -/* -------------------------------------------------------------------- */ -/* MPC8xx Specific Stuff - should go to MPC8xx directory */ -/* -------------------------------------------------------------------- */ - -/* - * Search this table to see if the windowsize is - * supported... - */ - -#define M8XX_SIZES_NO 32 - -static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] = -{ 0x00000001, 0x00000002, 0x00000008, 0x00000004, - 0x00000080, 0x00000040, 0x00000010, 0x00000020, - 0x00008000, 0x00004000, 0x00001000, 0x00002000, - 0x00000100, 0x00000200, 0x00000800, 0x00000400, - - 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0x01000000, 0x02000000, 0xffffffff, 0x04000000, - 0x00010000, 0x00020000, 0x00080000, 0x00040000, - 0x00800000, 0x00400000, 0x00100000, 0x00200000 }; - - -/* -------------------------------------------------------------------- */ - -#if ( ! defined(CONFIG_I82365) && ! defined(CONFIG_PXA_PCMCIA) ) - -static u_int m8xx_get_graycode(u_int size) -{ - u_int k; - - for (k = 0; k < M8XX_SIZES_NO; k++) { - if(m8xx_size_to_gray[k] == size) - break; - } - - if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1)) - k = -1; - - return k; -} - -#endif /* CONFIG_I82365 */ - -/* -------------------------------------------------------------------- */ - -#if 0 -static u_int m8xx_get_speed(u_int ns, u_int is_io) -{ - u_int reg, clocks, psst, psl, psht; - - if(!ns) { - - /* - * We get called with IO maps setup to 0ns - * if not specified by the user. - * They should be 255ns. - */ - - if(is_io) - ns = 255; - else - ns = 100; /* fast memory if 0 */ - } - - /* - * In PSST, PSL, PSHT fields we tell the controller - * timing parameters in CLKOUT clock cycles. - * CLKOUT is the same as GCLK2_50. - */ - -/* how we want to adjust the timing - in percent */ - -#define ADJ 180 /* 80 % longer accesstime - to be sure */ - - clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000; - clocks = (clocks * ADJ) / (100*1000); - - if(clocks >= PCMCIA_BMT_LIMIT) { - DEBUG(0, "Max access time limit reached\n"); - clocks = PCMCIA_BMT_LIMIT-1; - } - - psst = clocks / 7; /* setup time */ - psht = clocks / 7; /* hold time */ - psl = (clocks * 5) / 7; /* strobe length */ - - psst += clocks - (psst + psht + psl); - - reg = psst << 12; - reg |= psl << 7; - reg |= psht << 16; - - return reg; -} -#endif - -/* -------------------------------------------------------------------- */ - -#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA) -static void print_funcid (int func) -{ - puts (indent); - switch (func) { - case CISTPL_FUNCID_MULTI: - puts (" Multi-Function"); - break; - case CISTPL_FUNCID_MEMORY: - puts (" Memory"); - break; - case CISTPL_FUNCID_SERIAL: - puts (" Serial Port"); - break; - case CISTPL_FUNCID_PARALLEL: - puts (" Parallel Port"); - break; - case CISTPL_FUNCID_FIXED: - puts (" Fixed Disk"); - break; - case CISTPL_FUNCID_VIDEO: - puts (" Video Adapter"); - break; - case CISTPL_FUNCID_NETWORK: - puts (" Network Adapter"); - break; - case CISTPL_FUNCID_AIMS: - puts (" AIMS Card"); - break; - case CISTPL_FUNCID_SCSI: - puts (" SCSI Adapter"); - break; - default: - puts (" Unknown"); - break; } puts (" Card\n"); } -#endif /* CONFIG_IDE_8xx_PCCARD */ - -/* -------------------------------------------------------------------- */ -#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA) static void print_fixed (volatile uchar *p) { if (p == NULL) @@ -2804,16 +169,16 @@ static void print_fixed (volatile uchar *p) puts(indent); switch (*p) { - case CISTPL_FUNCE_IDE_IFACE: - { uchar iface = *(p+2); + case CISTPL_FUNCE_IDE_IFACE: + { uchar iface = *(p+2); puts ((iface == CISTPL_IDE_INTERFACE) ? " IDE" : " unknown"); puts (" interface "); break; - } - case CISTPL_FUNCE_IDE_MASTER: - case CISTPL_FUNCE_IDE_SLAVE: - { uchar f1 = *(p+2); + } + case CISTPL_FUNCE_IDE_MASTER: + case CISTPL_FUNCE_IDE_SLAVE: + { uchar f1 = *(p+2); uchar f2 = *(p+4); puts ((f1 & CISTPL_IDE_SILICON) ? " [silicon]" : " [rotating]"); @@ -2845,23 +210,10 @@ static void print_fixed (volatile uchar *p) puts (" [IOis16]"); break; - } + } } putc ('\n'); } -#endif /* CONFIG_IDE_8xx_PCCARD */ - -/* -------------------------------------------------------------------- */ - -#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_PXA_PCMCIA) - -#define MAX_IDENT_CHARS 64 -#define MAX_IDENT_FIELDS 4 - -static uchar *known_cards[] = { - (uchar *)"ARGOSY PnPIDE D5", - NULL -}; static int identify (volatile uchar *p) { @@ -2913,576 +265,101 @@ static int identify (volatile uchar *p) return (0); /* don't know */ } -#endif /* CONFIG_IDE_8xx_PCCARD */ - -/* -------------------------------------------------------------------- */ -/* NETTA board by Intracom S.A. */ -/* -------------------------------------------------------------------- */ - -#if defined(CONFIG_NETTA) - -/* some sane bit macros */ -#define _BD(_b) (1U << (31-(_b))) -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) - -#define _BW(_b) (1U << (15-(_b))) -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) - -#define _BB(_b) (1U << (7-(_b))) -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) - -#define _B(_b) _BD(_b) -#define _BR(_l, _h) _BDR(_l, _h) -#define PCMCIA_BOARD_MSG "NETTA" - -static const unsigned short vppd_masks[2] = { _BW(14), _BW(15) }; - -static void cfg_vppd(int no) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - unsigned short mask; - - if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0])) - return; - - mask = vppd_masks[no]; - - immap->im_ioport.iop_papar &= ~mask; - immap->im_ioport.iop_paodr &= ~mask; - immap->im_ioport.iop_padir |= mask; -} - -static void set_vppd(int no, int what) +int check_ide_device (int slot) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - unsigned short mask; - - if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0])) - return; - - mask = vppd_masks[no]; - - if (what) - immap->im_ioport.iop_padat |= mask; - else - immap->im_ioport.iop_padat &= ~mask; -} - -static const unsigned short vccd_masks[2] = { _BW(10), _BW(6) }; - -static void cfg_vccd(int no) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - unsigned short mask; - - if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0])) - return; - - mask = vccd_masks[no]; - - immap->im_ioport.iop_papar &= ~mask; - immap->im_ioport.iop_paodr &= ~mask; - immap->im_ioport.iop_padir |= mask; -} - -static void set_vccd(int no, int what) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - unsigned short mask; - - if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0])) - return; - - mask = vccd_masks[no]; - - if (what) - immap->im_ioport.iop_padat |= mask; - else - immap->im_ioport.iop_padat &= ~mask; -} - -static const unsigned short oc_mask = _BW(8); - -static void cfg_oc(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - unsigned short mask = oc_mask; - - immap->im_ioport.iop_pcdir &= ~mask; - immap->im_ioport.iop_pcso &= ~mask; - immap->im_ioport.iop_pcint &= ~mask; - immap->im_ioport.iop_pcpar &= ~mask; -} - -static int get_oc(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - unsigned short mask = oc_mask; - int what; - - what = !!(immap->im_ioport.iop_pcdat & mask);; - return what; -} - -static const unsigned short shdn_mask = _BW(12); - -static void cfg_shdn(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - unsigned short mask; - - mask = shdn_mask; - - immap->im_ioport.iop_papar &= ~mask; - immap->im_ioport.iop_paodr &= ~mask; - immap->im_ioport.iop_padir |= mask; -} - -static void set_shdn(int what) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - unsigned short mask; - - mask = shdn_mask; - - if (what) - immap->im_ioport.iop_padat |= mask; - else - immap->im_ioport.iop_padat &= ~mask; -} - -static void cfg_ports (void); - -static int hardware_enable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; - uint reg, pipr, mask; + volatile uchar *ident = NULL; + volatile uchar *feature_p[MAX_FEATURES]; + volatile uchar *p, *start, *addr; + int n_features = 0; + uchar func_id = ~0; + uchar code, len; + ushort config_base = 0; + int found = 0; int i; - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - immap = (immap_t *)CFG_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - - /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ - cfg_ports (); - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); + addr = (volatile uchar *)(CFG_PCMCIA_MEM_ADDR + + CFG_PCMCIA_MEM_SIZE * (slot * 4)); + debug ("PCMCIA MEM: %08lX\n", (ulong)addr); - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; + start = p = (volatile uchar *) addr; - udelay(500); + while ((p - start) < MAX_TUPEL_SZ) { - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } + code = *p; p += 2; - /* - * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - pipr = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - pipr, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); + if (code == 0xFF) { /* End of chain */ + break; + } - if ((pipr & mask) == mask) { - set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */ - set_vccd(0, 0); set_vccd(1, 1); /* 5V on, 3V off */ - puts (" 5.0V card found: "); - } else { - set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */ - set_vccd(0, 1); set_vccd(1, 0); /* 5V off, 3V on */ - puts (" 3.3V card found: "); - } + len = *p; p += 2; +#if defined(DEBUG) && (DEBUG > 1) + { volatile uchar *q = p; + printf ("\nTuple code %02x length %d\n\tData:", + code, len); - /* Wait 500 ms; use this to check for over-current */ - for (i=0; i<5000; ++i) { - if (!get_oc()) { - printf (" *** Overcurrent - Safety shutdown ***\n"); - set_vccd(0, 0); set_vccd(1, 0); /* VAVPP => Hi-Z */ - return (1); + for (i = 0; i < len; ++i) { + printf (" %02x", *q); + q+= 2; + } } - udelay (100); +#endif /* DEBUG */ + switch (code) { + case CISTPL_VERS_1: + ident = p + 4; + break; + case CISTPL_FUNCID: + /* Fix for broken SanDisk which may have 0x80 bit set */ + func_id = *p & 0x7F; + break; + case CISTPL_FUNCE: + if (n_features < MAX_FEATURES) + feature_p[n_features++] = p; + break; + case CISTPL_CONFIG: + config_base = (*(p+6) << 8) + (*(p+4)); + debug ("\n## Config_base = %04x ###\n", config_base); + default: + break; + } + p += 2 * len; } - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -static int hardware_disable(int slot) -{ - volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - - /* Configure PCMCIA General Control Register */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - /* All voltages off / Hi-Z */ - set_vppd(0, 1); set_vppd(1, 1); - set_vccd(0, 1); set_vccd(1, 1); - - udelay(10000); - - return (0); -} -#endif /* CFG_CMD_PCMCIA */ - - -static int voltage_set(int slot, int vcc, int vpp) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - u_long reg; - ushort sreg; - - debug ("voltage_set: " - PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - immap = (immap_t *)CFG_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable, - * Turn all power pins to Hi-Z - */ - debug ("PCMCIA power OFF\n"); - cfg_ports (); /* Enables switch, but all in Hi-Z */ - - sreg = immap->im_ioport.iop_pcdat; - set_vppd(0, 1); set_vppd(1, 1); - - switch(vcc) { - case 0: - break; /* Switch off */ - - case 33: - set_vccd(0, 1); set_vccd(1, 0); - break; + found = identify (ident); - case 50: - set_vccd(0, 0); set_vccd(1, 1); - break; + if (func_id != ((uchar)~0)) { + print_funcid (func_id); - default: - goto done; + if (func_id == CISTPL_FUNCID_FIXED) + found = 1; + else + return (1); /* no disk drive */ } - /* Checking supported voltages */ - - debug ("PIPR: 0x%x --> %s\n", - pcmp->pcmc_pipr, - (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); - -done: - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", - slot+'A'); - return (0); -} - -static void cfg_ports (void) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - - immap = (immap_t *)CFG_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - - - cfg_vppd(0); cfg_vppd(1); /* VPPD0,VPPD1 VAVPP => Hi-Z */ - cfg_vccd(0); cfg_vccd(1); /* 3V and 5V off */ - cfg_shdn(); - cfg_oc(); - - /* - * Configure Port A for TPS2211 PC-Card Power-Interface Switch - * - * Switch off all voltages, assert shutdown - */ - set_vppd(0, 1); set_vppd(1, 1); - set_vccd(0, 0); set_vccd(1, 0); - set_shdn(1); - - udelay(100000); -} - -#endif /* NETTA */ - - -/* -------------------------------------------------------------------- */ -/* UC100 Boards */ -/* -------------------------------------------------------------------- */ - -#if defined(CONFIG_UC100) - -#define PCMCIA_BOARD_MSG "UC100" - -/* - * Remark: don't turn off OE "__MY_PCMCIA_GCRX_CXOE" on UC100 board. - * This leads to board-hangup! (sr, 8 Dez. 2004) - */ - -static void cfg_ports (void); - -static int hardware_enable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; - uint reg, mask; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - immap = (immap_t *)CFG_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - - /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ - cfg_ports (); - - /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ - sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); + for (i=0; i<n_features; ++i) { + print_fixed (feature_p[i]); } - /* - * Power On. - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - reg = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - reg, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); - if ((reg & mask) == mask) { - puts (" 5.0V card found: "); - } else { - puts (" 3.3V card found: "); + if (!found) { + printf ("unknown card type\n"); + return (1); } - /* switch VCC on */ - immap->im_ioport.iop_padat |= 0x8000; /* power enable 3.3V */ - - udelay(10000); - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -static int hardware_disable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - - /* switch VCC off */ - immap->im_ioport.iop_padat &= ~0x8000; /* power disable 3.3V */ - - /* Configure PCMCIA General Control Register */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(10000); - - return (0); -} -#endif /* CFG_CMD_PCMCIA */ - - -static int voltage_set(int slot, int vcc, int vpp) -{ - volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("voltage_set: " - PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable, - * Turn all power pins to Hi-Z - */ - debug ("PCMCIA power OFF\n"); - cfg_ports (); /* Enables switch, but all in Hi-Z */ - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); + ide_devices_found |= (1 << slot); - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", - slot+'A'); +#if CONFIG_CPC45 +#else + /* set I/O area in config reg -> only valid for ARGOSY D5!!! */ + *((uchar *)(addr + config_base)) = 1; +#endif +#if 0 + printf("\n## Config_base = %04x ###\n", config_base); + printf("Configuration Option Register: %02x @ %x\n", readb(addr + config_base), addr + config_base); + printf("Card Configuration and Status Register: %02x\n", readb(addr + config_base + 2)); + printf("Pin Replacement Register Register: %02x\n", readb(addr + config_base + 4)); + printf("Socket and Copy Register: %02x\n", readb(addr + config_base + 6)); +#endif return (0); } -static void cfg_ports (void) -{ - volatile immap_t *immap; - - immap = (immap_t *)CFG_IMMR; - - /* - * Configure Port A for MAX1602 PC-Card Power-Interface Switch - */ - immap->im_ioport.iop_padat &= ~0x8000; /* set port x output to low */ - immap->im_ioport.iop_padir |= 0x8000; /* enable port x as output */ - - debug ("Set Port A: PAR: %08x DIR: %08x DAT: %08x\n", - immap->im_ioport.iop_papar, immap->im_ioport.iop_padir, - immap->im_ioport.iop_padat); -} - -#endif /* UC100 */ - - -/* -------------------------------------------------------------------- */ - -#endif /* CFG_CMD_PCMCIA || (CFG_CMD_IDE && CONFIG_IDE_8xx_PCCARD) */ - -/**************************************************/ - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -U_BOOT_CMD( - pinit, 2, 1, do_pinit, - "pinit - PCMCIA sub-system\n", - "on - power on PCMCIA socket\n" - "pinit off - power off PCMCIA socket\n" -); -#endif +#endif /* CHECK_IDE_DEVICE */ diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c index 15ac16a..f428f7e 100644 --- a/common/cmd_reginfo.c +++ b/common/cmd_reginfo.c @@ -328,7 +328,7 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) (*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0); printf ("\tSDRAMCS0: %08X\n", *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG); - printf ("\tSDRAMCS0: %08X\n", + printf ("\tSDRAMCS1: %08X\n", *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG); #endif /* CONFIG_MPC5200 */ return 0; diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index e804861..cc08743 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -43,8 +43,13 @@ #else #define SCSI_DEV_ID CONFIG_SCSI_DEV_ID #endif +#elif defined CONFIG_SATA_ULI5288 + +#define SCSI_VEND_ID 0x10b9 +#define SCSI_DEV_ID 0x5288 + #else -#error CONFIG_SCSI_SYM53C8XX must be defined +#error no scsi device defined #endif diff --git a/common/cmd_usb.c b/common/cmd_usb.c index fdfd042..28c05aa 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -186,7 +186,7 @@ void usb_display_conf_desc(struct usb_config_descriptor *config,struct usb_devic void usb_display_if_desc(struct usb_interface_descriptor *ifdesc,struct usb_device *dev) { printf(" Interface: %d\n",ifdesc->bInterfaceNumber); - printf(" - Alternate Settings %d, Endpoints: %d\n",ifdesc->bAlternateSetting,ifdesc->bNumEndpoints); + printf(" - Alternate Setting %d, Endpoints: %d\n",ifdesc->bAlternateSetting,ifdesc->bNumEndpoints); printf(" - Class "); usb_display_class_sub(ifdesc->bInterfaceClass,ifdesc->bInterfaceSubClass,ifdesc->bInterfaceProtocol); printf("\n"); @@ -444,6 +444,7 @@ int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int i; struct usb_device *dev = NULL; + extern char usb_started; #ifdef CONFIG_USB_STORAGE block_dev_desc_t *stor_dev; #endif @@ -477,6 +478,10 @@ int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) usb_stop(); return 0; } + if (!usb_started) { + printf("USB is stopped. Please issue 'usb start' first.\n"); + return 1; + } if (strncmp(argv[1],"tree",4) == 0) { printf("\nDevice Tree:\n"); usb_show_tree(usb_get_dev_index(0)); diff --git a/common/crc16.c b/common/crc16.c index 3cef106..6904365 100644 --- a/common/crc16.c +++ b/common/crc16.c @@ -101,7 +101,7 @@ cyg_crc16(unsigned char *buf, int len) cksum = 0; for (i = 0; i < len; i++) { - cksum = crc16_tab[((cksum>>8) ^ *buf++) & 0xFF] ^ (cksum << 8); + cksum = crc16_tab[((cksum>>8) ^ *buf++) & 0xFF] ^ (cksum << 8); } return cksum; } diff --git a/common/main.c b/common/main.c index 758ef8d..13d12a4 100644 --- a/common/main.c +++ b/common/main.c @@ -2,6 +2,10 @@ * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * + * Add to readline cmdline-editing by + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com> + * * See file CREDITS for list of people who contributed to this * project. * @@ -49,7 +53,6 @@ extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); #define MAX_DELAY_STOP_STR 32 -static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen); static int parse_line (char *, char *[]); #if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) static int abortboot(int); @@ -59,8 +62,11 @@ static int abortboot(int); char console_buffer[CFG_CBSIZE]; /* console I/O buffer */ +#ifndef CONFIG_CMDLINE_EDITING +static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen); static char erase_seq[] = "\b \b"; /* erase sequence */ static char tab_seq[] = " "; /* used to expand TABs */ +#endif /* CONFIG_CMDLINE_EDITING */ #ifdef CONFIG_BOOT_RETRY_TIME static uint64_t endtime = 0; /* must be set, default is instant timeout */ @@ -516,6 +522,406 @@ void reset_cmd_timeout(void) } #endif +#ifdef CONFIG_CMDLINE_EDITING + +/* + * cmdline-editing related codes from vivi. + * Author: Janghoon Lyu <nandy@mizi.com> + */ + +#if 1 /* avoid redundand code -- wd */ +#define putnstr(str,n) do { \ + printf ("%.*s", n, str); \ + } while (0) +#else +void putnstr(const char *str, size_t n) +{ + if (str == NULL) + return; + + while (n && *str != '\0') { + putc(*str); + str++; + n--; + } +} +#endif + +#define CTL_CH(c) ((c) - 'a' + 1) + +#define MAX_CMDBUF_SIZE 256 + +#define CTL_BACKSPACE ('\b') +#define DEL ((char)255) +#define DEL7 ((char)127) +#define CREAD_HIST_CHAR ('!') + +#define getcmd_putch(ch) putc(ch) +#define getcmd_getch() getc() +#define getcmd_cbeep() getcmd_putch('\a') + +#define HIST_MAX 20 +#define HIST_SIZE MAX_CMDBUF_SIZE + +static int hist_max = 0; +static int hist_add_idx = 0; +static int hist_cur = -1; +unsigned hist_num = 0; + +char* hist_list[HIST_MAX]; +char hist_lines[HIST_MAX][HIST_SIZE]; + +#define add_idx_minus_one() ((hist_add_idx == 0) ? hist_max : hist_add_idx-1) + +static void hist_init(void) +{ + int i; + + hist_max = 0; + hist_add_idx = 0; + hist_cur = -1; + hist_num = 0; + + for (i = 0; i < HIST_MAX; i++) { + hist_list[i] = hist_lines[i]; + hist_list[i][0] = '\0'; + } +} + +static void cread_add_to_hist(char *line) +{ + strcpy(hist_list[hist_add_idx], line); + + if (++hist_add_idx >= HIST_MAX) + hist_add_idx = 0; + + if (hist_add_idx > hist_max) + hist_max = hist_add_idx; + + hist_num++; +} + +static char* hist_prev(void) +{ + char *ret; + int old_cur; + + if (hist_cur < 0) + return NULL; + + old_cur = hist_cur; + if (--hist_cur < 0) + hist_cur = hist_max; + + if (hist_cur == hist_add_idx) { + hist_cur = old_cur; + ret = NULL; + } else + ret = hist_list[hist_cur]; + + return (ret); +} + +static char* hist_next(void) +{ + char *ret; + + if (hist_cur < 0) + return NULL; + + if (hist_cur == hist_add_idx) + return NULL; + + if (++hist_cur > hist_max) + hist_cur = 0; + + if (hist_cur == hist_add_idx) { + ret = ""; + } else + ret = hist_list[hist_cur]; + + return (ret); +} + +#ifndef CONFIG_CMDLINE_EDITING +static void cread_print_hist_list(void) +{ + int i; + unsigned long n; + + n = hist_num - hist_max; + + i = hist_add_idx + 1; + while (1) { + if (i > hist_max) + i = 0; + if (i == hist_add_idx) + break; + printf("%s\n", hist_list[i]); + n++; + i++; + } +} +#endif /* CONFIG_CMDLINE_EDITING */ + +#define BEGINNING_OF_LINE() { \ + while (num) { \ + getcmd_putch(CTL_BACKSPACE); \ + num--; \ + } \ +} + +#define ERASE_TO_EOL() { \ + if (num < eol_num) { \ + int tmp; \ + for (tmp = num; tmp < eol_num; tmp++) \ + getcmd_putch(' '); \ + while (tmp-- > num) \ + getcmd_putch(CTL_BACKSPACE); \ + eol_num = num; \ + } \ +} + +#define REFRESH_TO_EOL() { \ + if (num < eol_num) { \ + wlen = eol_num - num; \ + putnstr(buf + num, wlen); \ + num = eol_num; \ + } \ +} + +static void cread_add_char(char ichar, int insert, unsigned long *num, + unsigned long *eol_num, char *buf, unsigned long len) +{ + unsigned long wlen; + + /* room ??? */ + if (insert || *num == *eol_num) { + if (*eol_num > len - 1) { + getcmd_cbeep(); + return; + } + (*eol_num)++; + } + + if (insert) { + wlen = *eol_num - *num; + if (wlen > 1) { + memmove(&buf[*num+1], &buf[*num], wlen-1); + } + + buf[*num] = ichar; + putnstr(buf + *num, wlen); + (*num)++; + while (--wlen) { + getcmd_putch(CTL_BACKSPACE); + } + } else { + /* echo the character */ + wlen = 1; + buf[*num] = ichar; + putnstr(buf + *num, wlen); + (*num)++; + } +} + +static void cread_add_str(char *str, int strsize, int insert, unsigned long *num, + unsigned long *eol_num, char *buf, unsigned long len) +{ + while (strsize--) { + cread_add_char(*str, insert, num, eol_num, buf, len); + str++; + } +} + +static int cread_line(char *buf, unsigned int *len) +{ + unsigned long num = 0; + unsigned long eol_num = 0; + unsigned long rlen; + unsigned long wlen; + char ichar; + int insert = 1; + int esc_len = 0; + int rc = 0; + char esc_save[8]; + + while (1) { + rlen = 1; + ichar = getcmd_getch(); + + if ((ichar == '\n') || (ichar == '\r')) { + putc('\n'); + break; + } + + /* + * handle standard linux xterm esc sequences for arrow key, etc. + */ + if (esc_len != 0) { + if (esc_len == 1) { + if (ichar == '[') { + esc_save[esc_len] = ichar; + esc_len = 2; + } else { + cread_add_str(esc_save, esc_len, insert, + &num, &eol_num, buf, *len); + esc_len = 0; + } + continue; + } + + switch (ichar) { + + case 'D': /* <- key */ + ichar = CTL_CH('b'); + esc_len = 0; + break; + case 'C': /* -> key */ + ichar = CTL_CH('f'); + esc_len = 0; + break; /* pass off to ^F handler */ + case 'H': /* Home key */ + ichar = CTL_CH('a'); + esc_len = 0; + break; /* pass off to ^A handler */ + case 'A': /* up arrow */ + ichar = CTL_CH('p'); + esc_len = 0; + break; /* pass off to ^P handler */ + case 'B': /* down arrow */ + ichar = CTL_CH('n'); + esc_len = 0; + break; /* pass off to ^N handler */ + default: + esc_save[esc_len++] = ichar; + cread_add_str(esc_save, esc_len, insert, + &num, &eol_num, buf, *len); + esc_len = 0; + continue; + } + } + + switch (ichar) { + case 0x1b: + if (esc_len == 0) { + esc_save[esc_len] = ichar; + esc_len = 1; + } else { + puts("impossible condition #876\n"); + esc_len = 0; + } + break; + + case CTL_CH('a'): + BEGINNING_OF_LINE(); + break; + case CTL_CH('c'): /* ^C - break */ + *buf = '\0'; /* discard input */ + return (-1); + case CTL_CH('f'): + if (num < eol_num) { + getcmd_putch(buf[num]); + num++; + } + break; + case CTL_CH('b'): + if (num) { + getcmd_putch(CTL_BACKSPACE); + num--; + } + break; + case CTL_CH('d'): + if (num < eol_num) { + wlen = eol_num - num - 1; + if (wlen) { + memmove(&buf[num], &buf[num+1], wlen); + putnstr(buf + num, wlen); + } + + getcmd_putch(' '); + do { + getcmd_putch(CTL_BACKSPACE); + } while (wlen--); + eol_num--; + } + break; + case CTL_CH('k'): + ERASE_TO_EOL(); + break; + case CTL_CH('e'): + REFRESH_TO_EOL(); + break; + case CTL_CH('o'): + insert = !insert; + break; + case CTL_CH('x'): + BEGINNING_OF_LINE(); + ERASE_TO_EOL(); + break; + case DEL: + case DEL7: + case 8: + if (num) { + wlen = eol_num - num; + num--; + memmove(&buf[num], &buf[num+1], wlen); + getcmd_putch(CTL_BACKSPACE); + putnstr(buf + num, wlen); + getcmd_putch(' '); + do { + getcmd_putch(CTL_BACKSPACE); + } while (wlen--); + eol_num--; + } + break; + case CTL_CH('p'): + case CTL_CH('n'): + { + char * hline; + + esc_len = 0; + + if (ichar == CTL_CH('p')) + hline = hist_prev(); + else + hline = hist_next(); + + if (!hline) { + getcmd_cbeep(); + continue; + } + + /* nuke the current line */ + /* first, go home */ + BEGINNING_OF_LINE(); + + /* erase to end of line */ + ERASE_TO_EOL(); + + /* copy new line into place and display */ + strcpy(buf, hline); + eol_num = strlen(buf); + REFRESH_TO_EOL(); + continue; + } + default: + cread_add_char(ichar, insert, &num, &eol_num, buf, *len); + break; + } + } + *len = eol_num; + buf[eol_num] = '\0'; /* lose the newline */ + + if (buf[0] && buf[0] != CREAD_HIST_CHAR) + cread_add_to_hist(buf); + hist_cur = hist_add_idx; + + return (rc); +} + +#endif /* CONFIG_CMDLINE_EDITING */ + /****************************************************************************/ /* @@ -528,6 +934,22 @@ void reset_cmd_timeout(void) */ int readline (const char *const prompt) { +#ifdef CONFIG_CMDLINE_EDITING + char *p = console_buffer; + unsigned int len=MAX_CMDBUF_SIZE; + int rc; + static int initted = 0; + + if (!initted) { + hist_init(); + initted = 1; + } + + puts (prompt); + + rc = cread_line(p, &len); + return rc < 0 ? rc : len; +#else char *p = console_buffer; int n = 0; /* buffer index */ int plen = 0; /* prompt length */ @@ -623,10 +1045,12 @@ int readline (const char *const prompt) } } } +#endif /* CONFIG_CMDLINE_EDITING */ } /****************************************************************************/ +#ifndef CONFIG_CMDLINE_EDITING static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen) { char *s; @@ -656,6 +1080,7 @@ static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen) (*np)--; return (p); } +#endif /* CONFIG_CMDLINE_EDITING */ /****************************************************************************/ diff --git a/common/serial.c b/common/serial.c index 7b29951..38057d2 100644 --- a/common/serial.c +++ b/common/serial.c @@ -42,7 +42,11 @@ struct serial_device *default_serial_console (void) return &serial_scc_device; #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ || defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx) - return &serial0_device; +#if defined(CONFIG_UART1_CONSOLE) + return &serial1_device; +#else + return &serial0_device; +#endif #else #error No default console #endif diff --git a/common/usb.c b/common/usb.c index d9515e6..0857494 100644 --- a/common/usb.c +++ b/common/usb.c @@ -72,6 +72,8 @@ static int running; static int asynch_allowed; static struct devrequest setup_packet; +char usb_started; /* flag for the started/stopped USB status */ + /********************************************************************** * some forward declerations... */ @@ -110,10 +112,12 @@ int usb_init(void) printf("scanning bus for devices... "); running=1; usb_scan_devices(); + usb_started = 1; return 0; } else { printf("Error, couldn't init Lowlevel part\n"); + usb_started = 0; return -1; } } @@ -124,6 +128,7 @@ int usb_init(void) int usb_stop(void) { asynch_allowed=1; + usb_started = 0; usb_hub_reset(); return usb_lowlevel_stop(); } @@ -280,56 +285,68 @@ int usb_set_maxpacket(struct usb_device *dev) int usb_parse_config(struct usb_device *dev, unsigned char *buffer, int cfgno) { struct usb_descriptor_header *head; - int index,ifno,epno; - ifno=-1; - epno=-1; - - dev->configno=cfgno; - head =(struct usb_descriptor_header *)&buffer[0]; - if(head->bDescriptorType!=USB_DT_CONFIG) { - printf(" ERROR: NOT USB_CONFIG_DESC %x\n",head->bDescriptorType); + int index, ifno, epno, curr_if_num; + int i; + unsigned char *ch; + + ifno = -1; + epno = -1; + curr_if_num = -1; + + dev->configno = cfgno; + head = (struct usb_descriptor_header *) &buffer[0]; + if(head->bDescriptorType != USB_DT_CONFIG) { + printf(" ERROR: NOT USB_CONFIG_DESC %x\n", head->bDescriptorType); return -1; } - memcpy(&dev->config,buffer,buffer[0]); - dev->config.wTotalLength=swap_16(dev->config.wTotalLength); - dev->config.no_of_if=0; + memcpy(&dev->config, buffer, buffer[0]); + dev->config.wTotalLength = swap_16(dev->config.wTotalLength); + dev->config.no_of_if = 0; - index=dev->config.bLength; + index = dev->config.bLength; /* Ok the first entry must be a configuration entry, now process the others */ - head=(struct usb_descriptor_header *)&buffer[index]; - while(index+1 < dev->config.wTotalLength) { + head = (struct usb_descriptor_header *) &buffer[index]; + while(index + 1 < dev->config.wTotalLength) { switch(head->bDescriptorType) { case USB_DT_INTERFACE: - ifno=dev->config.no_of_if; - dev->config.no_of_if++; /* found an interface desc, increase numbers */ - memcpy(&dev->config.if_desc[ifno],&buffer[index],buffer[index]); /* copy new desc */ - dev->config.if_desc[ifno].no_of_ep=0; - + if(((struct usb_interface_descriptor *) &buffer[index])-> + bInterfaceNumber != curr_if_num) { + /* this is a new interface, copy new desc */ + ifno = dev->config.no_of_if; + dev->config.no_of_if++; + memcpy(&dev->config.if_desc[ifno], + &buffer[index], buffer[index]); + dev->config.if_desc[ifno].no_of_ep = 0; + dev->config.if_desc[ifno].num_altsetting = 1; + curr_if_num = dev->config.if_desc[ifno].bInterfaceNumber; + } else { + /* found alternate setting for the interface */ + dev->config.if_desc[ifno].num_altsetting++; + } break; case USB_DT_ENDPOINT: - epno=dev->config.if_desc[ifno].no_of_ep; + epno = dev->config.if_desc[ifno].no_of_ep; dev->config.if_desc[ifno].no_of_ep++; /* found an endpoint */ - memcpy(&dev->config.if_desc[ifno].ep_desc[epno],&buffer[index],buffer[index]); - dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize - =swap_16(dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize); - USB_PRINTF("if %d, ep %d\n",ifno,epno); + memcpy(&dev->config.if_desc[ifno].ep_desc[epno], + &buffer[index], buffer[index]); + dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize = + swap_16(dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize); + USB_PRINTF("if %d, ep %d\n", ifno, epno); break; default: - if(head->bLength==0) + if(head->bLength == 0) return 1; - USB_PRINTF("unknown Description Type : %x\n",head->bDescriptorType); + USB_PRINTF("unknown Description Type : %x\n", head->bDescriptorType); { - int i; - unsigned char *ch; - ch=(unsigned char *)head; - for(i=0;i<head->bLength; i++) - USB_PRINTF("%02X ",*ch++); + ch = (unsigned char *)head; + for(i = 0; i < head->bLength; i++) + USB_PRINTF("%02X ", *ch++); USB_PRINTF("\n\n\n"); } break; } - index+=head->bLength; - head=(struct usb_descriptor_header *)&buffer[index]; + index += head->bLength; + head = (struct usb_descriptor_header *)&buffer[index]; } return 1; } @@ -443,6 +460,14 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate) printf("selecting invalid interface %d", interface); return -1; } + /* + * We should return now for devices with only one alternate setting. + * According to 9.4.10 of the Universal Serial Bus Specification Revision 2.0 + * such devices can return with a STALL. This results in some USB sticks + * timeouting during initialization and then being unusable in U-Boot. + */ + if (if_face->num_altsetting == 1) + return 0; if ((ret = usb_control_msg(dev, usb_sndctrlpipe(dev, 0), USB_REQ_SET_INTERFACE, USB_RECIP_INTERFACE, alternate, diff --git a/common/usb_storage.c b/common/usb_storage.c index 99e4ab0..e64470c 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -1139,6 +1139,10 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t /* USB007 Mini-USB2 Flash Drive */ (dev->descriptor.idVendor == 0x066f && dev->descriptor.idProduct == 0x2010) + || + /* SanDisk Corporation Cruzer Micro 20044318410546613953 */ + (dev->descriptor.idVendor == 0x0781 && + dev->descriptor.idProduct == 0x5151) ) USB_STOR_PRINTF("usb_stor_get_info: skipping RESET..\n"); else diff --git a/common/xyzModem.c b/common/xyzModem.c index 9b455a3..d1d66e8 100644 --- a/common/xyzModem.c +++ b/common/xyzModem.c @@ -261,8 +261,8 @@ zm_dprintf(char *fmt, ...) static void zm_flush(void) { - char *p = zm_out_start; #ifdef REDBOOT + char *p = zm_out_start; while (*p) mon_write_char(*p++); #endif zm_out = zm_out_start; diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c index 3ec9b54..1b36412 100644 --- a/cpu/arm920t/s3c24x0/interrupts.c +++ b/cpu/arm920t/s3c24x0/interrupts.c @@ -176,7 +176,9 @@ ulong get_tbclk (void) #if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB) tbclk = timer_load_val * 100; -#elif defined(CONFIG_SMDK2410) || defined(CONFIG_VCMA9) +#elif defined(CONFIG_SBC2410X) || \ + defined(CONFIG_SMDK2410) || \ + defined(CONFIG_VCMA9) tbclk = CFG_HZ; #else # error "tbclk not configured" diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c index c83f0bb..1c4370b 100644 --- a/cpu/i386/sc520.c +++ b/cpu/i386/sc520.c @@ -31,7 +31,9 @@ #include <common.h> #include <config.h> #include <pci.h> +#ifdef CONFIG_SC520_SSI #include <ssi.h> +#endif #include <asm/io.h> #include <asm/pci.h> #include <asm/ic/sc520.h> @@ -143,7 +145,15 @@ unsigned long init_sc520_dram(void) u32 dram_present=0; u32 dram_ctrl; - +#ifdef CFG_SDRAM_DRCTMCTL + /* these memory control registers are set up in the assember part, + * in sc520_asm.S, during 'mem_init'. If we muck with them here, + * after we are running a stack in RAM, we have troubles. Besides, + * these refresh and delay values are better ? simply specified + * outright in the include/configs/{cfg} file since the HW designer + * simply dictates it. + */ +#else int val; int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY; @@ -162,6 +172,7 @@ unsigned long init_sc520_dram(void) } else { val = 3; /* 62.4us */ } + write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4)); val = read_mmcr_byte(SC520_DRCTMCTL); @@ -181,13 +192,12 @@ unsigned long init_sc520_dram(void) val |= 1; } write_mmcr_byte(SC520_DRCTMCTL, val); - +#endif /* We read-back the configuration of the dram * controller that the assembly code wrote */ dram_ctrl = read_mmcr_long(SC520_DRCBENDADR); - bd->bi_dram[0].start = 0; if (dram_ctrl & 0x80) { /* bank 0 enabled */ @@ -274,7 +284,7 @@ int pci_sc520_set_irq(int pci_pin, int irq) { int i; -# if 0 +# if 1 printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq); #endif if (irq < 0 || irq > 15) { diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S index 80464fa..e1fa37a 100644 --- a/cpu/i386/sc520_asm.S +++ b/cpu/i386/sc520_asm.S @@ -113,6 +113,7 @@ .equ DRCCFG, 0x0fffef014 /* DRAM bank configuration register */ .equ DRCBENDADR, 0x0fffef018 /* DRAM bank ending address register */ .equ ECCCTL, 0x0fffef020 /* DRAM ECC control register */ +.equ ECCINT, 0x0fffefd18 /* DRAM ECC nmi-INT mapping */ .equ DBCTL, 0x0fffef040 /* DRAM buffer control register */ .equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */ @@ -459,6 +460,12 @@ emptybank: incl %edi loop cleanuplp +#if defined CFG_SDRAM_DRCTMCTL + /* just have your hardware desinger _GIVE_ you what you need here! */ + movl $DRCTMCTL, %edi + movb $CFG_SDRAM_DRCTMCTL,%al + movb (%edi), %al +#else #if defined(CFG_SDRAM_CAS_LATENCY_2T) || defined(CFG_SDRAM_CAS_LATENCY_3T) /* set the CAS latency now since it is hard to do * when we run from the RAM */ @@ -470,7 +477,8 @@ emptybank: #ifdef CFG_SDRAM_CAS_LATENCY_3T orb $0x10, %al #endif - movb %al, (%edi) + movb %al, (%edi) +#endif #endif movl $DRCCTL, %edi /* DRAM Control register */ movb $0x3,%al /* Load mode register cmd */ @@ -528,9 +536,49 @@ bank0: movl (%edi), %eax shll $22, %eax movl %eax, %ebx -done: movl %ebx, %eax +done: + movl %ebx, %eax + +#if CFG_SDRAM_ECC_ENABLE + /* A nominal memory test: just a byte at each address line */ + movl %eax, %ecx + shrl $0x1, %ecx + movl $0x1, %edi +memtest0: + movb $0xa5, (%edi) + cmpb $0xa5, (%edi) + jne out + shrl $1, %ecx + andl %ecx,%ecx + jz set_ecc + shll $1, %edi + jmp memtest0 + +set_ecc: + /* clear all ram with a memset */ + movl %eax, %ecx + xorl %esi, %esi + xorl %edi, %edi + xorl %eax, %eax + shrl $2, %ecx + cld + rep stosl + /* enable read, write buffers */ + movb $0x11, %al + movl $DBCTL, %edi + movb %al, (%edi) + /* enable NMI mapping for ECC */ + movl $ECCINT, %edi + mov $0x10, %al + movb %al, (%edi) + /* Turn on ECC */ + movl $ECCCTL, %edi + mov $0x05, %al + movb %al, (%edi) +#endif +out: + movl %ebx, %eax jmp *%ebp - #endif /* CONFIG_SC520 */ diff --git a/cpu/mips/config.mk b/cpu/mips/config.mk index c357615..b29986e 100644 --- a/cpu/mips/config.mk +++ b/cpu/mips/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # v=$(shell \ -mips-linux-as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}') +$(CROSS_COMPILE)as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}') MIPSFLAGS=$(shell \ if [ "$v" -lt "14" ]; then \ echo "-mcpu=4kc"; \ diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile new file mode 100644 index 0000000..7995945 --- /dev/null +++ b/cpu/mpc86xx/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2002,2003 Motorola Inc. +# Xianghua Xiao,X.Xiao@motorola.com +# +# (C) Copyright 2004 Freescale Semiconductor. (MC86xx Port) +# Jeff Brown +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o #resetvec.o +ASOBJS = cache.o +COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ + pci.o pcie_indirect.o i2c.o spd_sdram.o +OBJS = $(COBJS) + +all: .depend $(START) $(ASOBJS) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(ASOBJS) $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(ASOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S new file mode 100644 index 0000000..f316b3e --- /dev/null +++ b/cpu/mpc86xx/cache.S @@ -0,0 +1,374 @@ +#include <config.h> +#include <mpc86xx.h> +#include <version.h> + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#include <asm/cache.h> +#include <asm/mmu.h> + +#ifndef CACHE_LINE_SIZE +# define CACHE_LINE_SIZE L1_CACHE_BYTES +#endif + +#if CACHE_LINE_SIZE == 128 +#define LG_CACHE_LINE_SIZE 7 +#elif CACHE_LINE_SIZE == 32 +#define LG_CACHE_LINE_SIZE 5 +#elif CACHE_LINE_SIZE == 16 +#define LG_CACHE_LINE_SIZE 4 +#elif CACHE_LINE_SIZE == 8 +#define LG_CACHE_LINE_SIZE 3 +#else +# error "Invalid cache line size!" +#endif + +/* + * Most of this code is taken from 74xx_7xx/cache.S + * and then cleaned up a bit + */ + +/* + * Invalidate L1 instruction cache. + */ +_GLOBAL(invalidate_l1_instruction_cache) + /* use invalidate-all bit in HID0 */ + mfspr r3,HID0 + ori r3,r3,HID0_ICFI + mtspr HID0,r3 + isync + blr + +/* + * Invalidate L1 data cache. + */ +_GLOBAL(invalidate_l1_data_cache) + mfspr r3,HID0 + ori r3,r3,HID0_DCFI + mtspr HID0,r3 + isync + blr + +/* + * Flush data cache. + */ +_GLOBAL(flush_data_cache) + lis r3,0 + lis r5,CACHE_LINE_SIZE +flush: + cmp 0,1,r3,r5 + bge done + lwz r5,0(r3) + lis r5,CACHE_LINE_SIZE + addi r3,r3,0x4 + b flush +done: + blr +/* + * Write any modified data cache blocks out to memory + * and invalidate the corresponding instruction cache blocks. + * This is a no-op on the 601. + * + * flush_icache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(flush_icache_range) + li r5,CACHE_LINE_SIZE-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,LG_CACHE_LINE_SIZE + beqlr + mtctr r4 + mr r6,r3 +1: dcbst 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync /* wait for dcbst's to get to ram */ + mtctr r4 +2: icbi 0,r6 + addi r6,r6,CACHE_LINE_SIZE + bdnz 2b + sync /* additional sync needed on g4 */ + isync + blr +/* + * Write any modified data cache blocks out to memory. + * Does not invalidate the corresponding cache lines (especially for + * any corresponding instruction cache). + * + * clean_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(clean_dcache_range) + li r5,CACHE_LINE_SIZE-1 + andc r3,r3,r5 /* align r3 down to cache line */ + subf r4,r3,r4 /* r4 = offset of stop from start of cache line */ + add r4,r4,r5 /* r4 += cache_line_size-1 */ + srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */ + beqlr /* if r4 == 0 return */ + mtctr r4 /* ctr = r4 */ + + sync +1: dcbst 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync /* wait for dcbst's to get to ram */ + blr + +/* + * Write any modified data cache blocks out to memory + * and invalidate the corresponding instruction cache blocks. + * + * flush_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(flush_dcache_range) + li r5,CACHE_LINE_SIZE-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,LG_CACHE_LINE_SIZE + beqlr + mtctr r4 + + sync +1: dcbf 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync /* wait for dcbf's to get to ram */ + blr + +/* + * Like above, but invalidate the D-cache. This is used by the 8xx + * to invalidate the cache so the PPC core doesn't get stale data + * from the CPM (no cache snooping here :-). + * + * invalidate_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(invalidate_dcache_range) + li r5,CACHE_LINE_SIZE-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,LG_CACHE_LINE_SIZE + beqlr + mtctr r4 + + sync +1: dcbi 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync /* wait for dcbi's to get to ram */ + blr + +/* + * Flush a particular page from the data cache to RAM. + * Note: this is necessary because the instruction cache does *not* + * snoop from the data cache. + * + * void __flush_page_to_ram(void *page) + */ +_GLOBAL(__flush_page_to_ram) + rlwinm r3,r3,0,0,19 /* Get page base address */ + li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ + mtctr r4 + mr r6,r3 +0: dcbst 0,r3 /* Write line to ram */ + addi r3,r3,CACHE_LINE_SIZE + bdnz 0b + sync + mtctr r4 +1: icbi 0,r6 + addi r6,r6,CACHE_LINE_SIZE + bdnz 1b + sync + isync + blr + +/* + * Flush a particular page from the instruction cache. + * Note: this is necessary because the instruction cache does *not* + * snoop from the data cache. + * + * void __flush_icache_page(void *page) + */ +_GLOBAL(__flush_icache_page) + li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ + mtctr r4 +1: icbi 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync + isync + blr + +/* + * Clear a page using the dcbz instruction, which doesn't cause any + * memory traffic (except to write out any cache lines which get + * displaced). This only works on cacheable memory. + */ +_GLOBAL(clear_page) + li r0,4096/CACHE_LINE_SIZE + mtctr r0 +1: dcbz 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + blr + +/* + * Enable L1 Instruction cache + */ +_GLOBAL(icache_enable) + mfspr r3, HID0 + li r5, HID0_ICFI|HID0_ILOCK + andc r3, r3, r5 + ori r3, r3, HID0_ICE + ori r5, r3, HID0_ICFI + mtspr HID0, r5 + mtspr HID0, r3 + isync + blr + +/* + * Disable L1 Instruction cache + */ +_GLOBAL(icache_disable) + mfspr r3, HID0 + li r5, 0 + ori r5, r5, HID0_ICE + andc r3, r3, r5 + mtspr HID0, r3 + isync + blr + +/* + * Is instruction cache enabled? + */ +_GLOBAL(icache_status) + mfspr r3, HID0 + andi. r3, r3, HID0_ICE + blr + + +_GLOBAL(l1dcache_enable) + mfspr r3, HID0 + li r5, HID0_DCFI|HID0_DLOCK + andc r3, r3, r5 + mtspr HID0, r3 /* no invalidate, unlock */ + ori r3, r3, HID0_DCE + ori r5, r3, HID0_DCFI + mtspr HID0, r5 /* enable + invalidate */ + mtspr HID0, r3 /* enable */ + sync + blr + +/* + * Enable data cache(s) - L1 and optionally L2 + * Calls l2cache_enable. LR saved in r5 + */ +_GLOBAL(dcache_enable) + mfspr r3, HID0 + li r5, HID0_DCFI|HID0_DLOCK + andc r3, r3, r5 + mtspr HID0, r3 /* no invalidate, unlock */ + ori r3, r3, HID0_DCE + ori r5, r3, HID0_DCFI + mtspr HID0, r5 /* enable + invalidate */ + mtspr HID0, r3 /* enable */ + sync +#ifdef CFG_L2 + mflr r5 + bl l2cache_enable /* uses r3 and r4 */ + sync + mtlr r5 +#endif + blr + + +/* + * Disable data cache(s) - L1 and optionally L2 + * Calls flush_data_cache and l2cache_disable_no_flush. + * LR saved in r4 + */ +_GLOBAL(dcache_disable) + mflr r4 /* save link register */ + bl flush_data_cache /* uses r3 and r5 */ + sync + mfspr r3, HID0 + li r5, HID0_DCFI|HID0_DLOCK + andc r3, r3, r5 + mtspr HID0, r3 /* no invalidate, unlock */ + li r5, HID0_DCE|HID0_DCFI + andc r3, r3, r5 /* no enable, no invalidate */ + mtspr HID0, r3 + sync +#ifdef CFG_L2 + bl l2cache_disable_no_flush /* uses r3 */ +#endif + mtlr r4 /* restore link register */ + blr + +/* + * Is data cache enabled? + */ +_GLOBAL(dcache_status) + mfspr r3, HID0 + andi. r3, r3, HID0_DCE + blr + +/* + * Invalidate L2 cache using L2I, assume L2 is enabled + */ +_GLOBAL(l2cache_invalidate) + mfspr r3, l2cr + rlwinm. r3, r3, 0, 0, 0 + beq 1f + + mfspr r3, l2cr + rlwinm r3, r3, 0, 1, 31 + +#ifdef CONFIG_ALTIVEC + dssall +#endif + sync + mtspr l2cr, r3 + sync +1: mfspr r3, l2cr + oris r3, r3, L2CR_L2I@h + mtspr l2cr, r3 + +invl2: + mfspr r3, l2cr + andi. r3, r3, L2CR_L2I@h + bne invl2 + blr + +/* + * Enable L2 cache + * Calls l2cache_invalidate. LR is saved in r4 + */ +_GLOBAL(l2cache_enable) + mflr r4 /* save link register */ + bl l2cache_invalidate /* uses r3 */ + sync + lis r3, L2_ENABLE@h + ori r3, r3, L2_ENABLE@l + mtspr l2cr, r3 + isync + mtlr r4 /* restore link register */ + blr + +/* + * Disable L2 cache + * Calls flush_data_cache. LR is saved in r4 + */ +_GLOBAL(l2cache_disable) + mflr r4 /* save link register */ + bl flush_data_cache /* uses r3 and r5 */ + sync + mtlr r4 /* restore link register */ +l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */ + lis r3, L2_INIT@h + ori r3, r3, L2_INIT@l + mtspr l2cr, r3 + isync + blr diff --git a/cpu/mpc86xx/config.mk b/cpu/mpc86xx/config.mk new file mode 100644 index 0000000..3c54f4a --- /dev/null +++ b/cpu/mpc86xx/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2004 Freescale Semiconductor. +# Jeff Brown +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi + +PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -ffixed-r2 -ffixed-r29 -mstring diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c new file mode 100644 index 0000000..ddd0ad3 --- /dev/null +++ b/cpu/mpc86xx/cpu.c @@ -0,0 +1,307 @@ +/* + * Copyright 2006 Freescale Semiconductor + * Jeff Brown + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <command.h> +#include <asm/cache.h> +#include <mpc86xx.h> + +#if defined(CONFIG_OF_FLAT_TREE) +#include <ft_build.h> +#endif + +#ifdef CONFIG_MPC8641HPCN +extern void mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, + int argc, char *argv[]); +#endif + + +int +checkcpu(void) +{ + sys_info_t sysinfo; + uint pvr, svr; + uint ver; + uint major, minor; + uint lcrr; /* local bus clock ratio register */ + uint clkdiv; /* clock divider portion of lcrr */ + + puts("Freescale PowerPC\n"); + + pvr = get_pvr(); + ver = PVR_VER(pvr); + major = PVR_MAJ(pvr); + minor = PVR_MIN(pvr); + + puts("CPU:\n"); + puts(" Core: "); + + switch (ver) { + case PVR_VER(PVR_86xx): + puts("E600"); + break; + default: + puts("Unknown"); + break; + } + printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); + + svr = get_svr(); + ver = SVR_VER(svr); + major = SVR_MAJ(svr); + minor = SVR_MIN(svr); + + puts(" System: "); + switch (ver) { + case SVR_8641: + puts("8641"); + break; + case SVR_8641D: + puts("8641D"); + break; + default: + puts("Unknown"); + break; + } + printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); + + get_sys_info(&sysinfo); + + puts(" Clocks: "); + printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); + printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000); + printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); + +#if defined(CFG_LBC_LCRR) + lcrr = CFG_LBC_LCRR; +#else + { + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + lcrr = lbc->lcrr; + } +#endif + clkdiv = lcrr & 0x0f; + if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { + printf("LBC:%4lu MHz\n", + sysinfo.freqSystemBus / 1000000 / clkdiv); + } else { + printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr); + } + + puts(" L2: "); + if (get_l2cr() & 0x80000000) + puts("Enabled\n"); + else + puts("Disabled\n"); + + return 0; +} + + +static inline void +soft_restart(unsigned long addr) +{ +#ifndef CONFIG_MPC8641HPCN + + /* + * SRR0 has system reset vector, SRR1 has default MSR value + * rfi restores MSR from SRR1 and sets the PC to the SRR0 value + */ + + __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); + __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); + __asm__ __volatile__ ("mtspr 27, 4"); + __asm__ __volatile__ ("rfi"); + +#else /* CONFIG_MPC8641HPCN */ + + out8(PIXIS_BASE + PIXIS_RST, 0); + +#endif /* !CONFIG_MPC8641HPCN */ + + while (1) ; /* not reached */ +} + + +/* + * No generic way to do board reset. Simply call soft_reset. + */ +void +do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#ifndef CONFIG_MPC8641HPCN + +#ifdef CFG_RESET_ADDRESS + ulong addr = CFG_RESET_ADDRESS; +#else + /* + * note: when CFG_MONITOR_BASE points to a RAM address, + * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid + * address. Better pick an address known to be invalid on your + * system and assign it to CFG_RESET_ADDRESS. + */ + ulong addr = CFG_MONITOR_BASE - sizeof(ulong); +#endif + + /* flush and disable I/D cache */ + __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); + __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); + __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); + __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("mtspr 1008, 4"); + __asm__ __volatile__ ("isync"); + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("mtspr 1008, 5"); + __asm__ __volatile__ ("isync"); + __asm__ __volatile__ ("sync"); + + soft_restart(addr); + +#else /* CONFIG_MPC8641HPCN */ + + mpc8641_reset_board(cmdtp, flag, argc, argv); + +#endif /* !CONFIG_MPC8641HPCN */ + + while (1) ; /* not reached */ +} + + +/* + * Get timebase clock frequency + */ +unsigned long +get_tbclk(void) +{ + sys_info_t sys_info; + + get_sys_info(&sys_info); + return (sys_info.freqSystemBus + 3L) / 4L; +} + + +#if defined(CONFIG_WATCHDOG) +void +watchdog_reset(void) +{ +} +#endif /* CONFIG_WATCHDOG */ + + +#if defined(CONFIG_DDR_ECC) +void +dma_init(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_dma_t *dma = &immap->im_dma; + + dma->satr0 = 0x00040000; + dma->datr0 = 0x00040000; + asm("sync; isync"); +} + +uint +dma_check(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_dma_t *dma = &immap->im_dma; + volatile uint status = dma->sr0; + + /* While the channel is busy, spin */ + while ((status & 4) == 4) { + status = dma->sr0; + } + + if (status != 0) { + printf("DMA Error: status = %x\n", status); + } + return status; +} + +int +dma_xfer(void *dest, uint count, void *src) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_dma_t *dma = &immap->im_dma; + + dma->dar0 = (uint) dest; + dma->sar0 = (uint) src; + dma->bcr0 = count; + dma->mr0 = 0xf000004; + asm("sync;isync"); + dma->mr0 = 0xf000005; + asm("sync;isync"); + return dma_check(); +} + +#endif /* CONFIG_DDR_ECC */ + + +#ifdef CONFIG_OF_FLAT_TREE +void +ft_cpu_setup(void *blob, bd_t *bd) +{ + u32 *p; + ulong clock; + int len; + + clock = bd->bi_busfreq; + p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + + p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + + p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + +#if defined(CONFIG_MPC86XX_TSEC1) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); + memcpy(p, bd->bi_enetaddr, 6); +#endif + +#if defined(CONFIG_MPC86XX_TSEC2) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); + memcpy(p, bd->bi_enet1addr, 6); +#endif + +#if defined(CONFIG_MPC86XX_TSEC3) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len); + memcpy(p, bd->bi_enet2addr, 6); +#endif + +#if defined(CONFIG_MPC86XX_TSEC4) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len); + memcpy(p, bd->bi_enet3addr, 6); +#endif + +} +#endif diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c new file mode 100644 index 0000000..6ed7c37 --- /dev/null +++ b/cpu/mpc86xx/cpu_init.c @@ -0,0 +1,122 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Jeff Brown + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * cpu_init.c - low level cpu init + */ + +#include <common.h> +#include <mpc86xx.h> + +/* + * Breathe some life into the CPU... + * + * Set up the memory map + * initialize a bunch of registers + */ + +void cpu_init_f(void) +{ + DECLARE_GLOBAL_DATA_PTR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *memctl = &immap->im_lbc; + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + + /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary + * addresses - these have to be modified later when FLASH size + * has been determined + */ + +#if defined(CFG_OR0_REMAP) + memctl->or0 = CFG_OR0_REMAP; +#endif +#if defined(CFG_OR1_REMAP) + memctl->or1 = CFG_OR1_REMAP; +#endif + + /* now restrict to preliminary range */ +#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM) + memctl->br0 = CFG_BR0_PRELIM; + memctl->or0 = CFG_OR0_PRELIM; +#endif + +#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) + memctl->or1 = CFG_OR1_PRELIM; + memctl->br1 = CFG_BR1_PRELIM; +#endif + +#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) + memctl->or2 = CFG_OR2_PRELIM; + memctl->br2 = CFG_BR2_PRELIM; +#endif + +#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) + memctl->or3 = CFG_OR3_PRELIM; + memctl->br3 = CFG_BR3_PRELIM; +#endif + +#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) + memctl->or4 = CFG_OR4_PRELIM; + memctl->br4 = CFG_BR4_PRELIM; +#endif + +#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) + memctl->or5 = CFG_OR5_PRELIM; + memctl->br5 = CFG_BR5_PRELIM; +#endif + +#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM) + memctl->or6 = CFG_OR6_PRELIM; + memctl->br6 = CFG_BR6_PRELIM; +#endif + +#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM) + memctl->or7 = CFG_OR7_PRELIM; + memctl->br7 = CFG_BR7_PRELIM; +#endif + + /* enable the timebase bit in HID0 */ + set_hid0(get_hid0() | 0x4000000); + + /* enable SYNCBE | ABE bits in HID1 */ + set_hid1(get_hid1() | 0x00000C00); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ + return 0; +} + + + + + diff --git a/cpu/mpc86xx/i2c.c b/cpu/mpc86xx/i2c.c new file mode 100644 index 0000000..d99ecb9 --- /dev/null +++ b/cpu/mpc86xx/i2c.c @@ -0,0 +1,269 @@ +/* + * (C) Copyright 2003,Motorola Inc. + * Xianghua Xiao <x.xiao@motorola.com> + * Adapted for Motorola 85xx chip. + * + * (C) Copyright 2003 + * Gleb Natapov <gnatapov@mrv.com> + * Some bits are taken from linux driver writen by adrian@humboldt.co.uk + * + * Modified for MPC86xx by Jeff Brown + * + * Hardware I2C driver for MPC107 PCI bridge. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#ifdef CONFIG_HARD_I2C +#include <i2c.h> + +#define TIMEOUT (CFG_HZ/4) + +#define I2C_Addr ((u8 *)(CFG_CCSRBAR + 0x3100)) + +#define I2CADR &I2C_Addr[0] +#define I2CFDR &I2C_Addr[4] +#define I2CCCR &I2C_Addr[8] +#define I2CCSR &I2C_Addr[12] +#define I2CCDR &I2C_Addr[16] +#define I2CDFSRR &I2C_Addr[20] + +#define I2C_READ 1 +#define I2C_WRITE 0 + +void +i2c_init(int speed, int slaveadd) +{ + /* stop I2C controller */ + writeb(0x0, I2CCCR); + + /* set clock */ + writeb(0x3f, I2CFDR); + + /* set default filter */ + writeb(0x10, I2CDFSRR); + + /* write slave address */ + writeb(slaveadd, I2CADR); + + /* clear status register */ + writeb(0x0, I2CCSR); + + /* start I2C controller */ + writeb(MPC86xx_I2CCR_MEN, I2CCCR); +} + +static __inline__ int +i2c_wait4bus(void) +{ + ulong timeval = get_timer(0); + + while (readb(I2CCSR) & MPC86xx_I2CSR_MBB) { + if (get_timer(timeval) > TIMEOUT) { + return -1; + } + } + + return 0; +} + +static __inline__ int +i2c_wait(int write) +{ + u32 csr; + ulong timeval = get_timer(0); + + do { + csr = readb(I2CCSR); + if (!(csr & MPC86xx_I2CSR_MIF)) + continue; + + writeb(0x0, I2CCSR); + + if (csr & MPC86xx_I2CSR_MAL) { + debug("i2c_wait: MAL\n"); + return -1; + } + + if (!(csr & MPC86xx_I2CSR_MCF)) { + debug("i2c_wait: unfinished\n"); + return -1; + } + + if (write == I2C_WRITE && (csr & MPC86xx_I2CSR_RXAK)) { + debug("i2c_wait: No RXACK\n"); + return -1; + } + + return 0; + } while (get_timer(timeval) < TIMEOUT); + + debug("i2c_wait: timed out\n"); + return -1; +} + +static __inline__ int +i2c_write_addr(u8 dev, u8 dir, int rsta) +{ + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX + | (rsta ? MPC86xx_I2CCR_RSTA : 0), + I2CCCR); + + writeb((dev << 1) | dir, I2CCDR); + + if (i2c_wait(I2C_WRITE) < 0) + return 0; + + return 1; +} + +static __inline__ int +__i2c_write(u8 *data, int length) +{ + int i; + + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX, + I2CCCR); + + for (i = 0; i < length; i++) { + writeb(data[i], I2CCDR); + + if (i2c_wait(I2C_WRITE) < 0) + break; + } + + return i; +} + +static __inline__ int +__i2c_read(u8 *data, int length) +{ + int i; + + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA + | ((length == 1) ? MPC86xx_I2CCR_TXAK : 0), + I2CCCR); + + /* dummy read */ + readb(I2CCDR); + + for (i = 0; i < length; i++) { + if (i2c_wait(I2C_READ) < 0) + break; + + /* Generate ack on last next to last byte */ + if (i == length - 2) + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA + | MPC86xx_I2CCR_TXAK, I2CCCR); + + /* Generate stop on last byte */ + if (i == length - 1) + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_TXAK, I2CCCR); + + data[i] = readb(I2CCDR); + } + + return i; +} + +int +i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) +{ + int i = 0; + u8 *a = (u8 *) &addr; + + if (i2c_wait4bus() < 0) + goto exit; + + if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) + goto exit; + + if (__i2c_write(&a[4 - alen], alen) != alen) + goto exit; + + if (i2c_write_addr(dev, I2C_READ, 1) == 0) + goto exit; + + i = __i2c_read(data, length); + +exit: + writeb(MPC86xx_I2CCR_MEN, I2CCCR); + + return !(i == length); +} + +int +i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) +{ + int i = 0; + u8 *a = (u8 *) &addr; + + if (i2c_wait4bus() < 0) + goto exit; + + if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) + goto exit; + + if (__i2c_write(&a[4 - alen], alen) != alen) + goto exit; + + i = __i2c_write(data, length); + +exit: + writeb(MPC86xx_I2CCR_MEN, I2CCCR); + + return !(i == length); +} + +int +i2c_probe(uchar chip) +{ + int tmp; + + /* + * Try to read the first location of the chip. The underlying + * driver doesn't appear to support sending just the chip address + * and looking for an <ACK> back. + */ + udelay(10000); + + return i2c_read(chip, 0, 1, (char *)&tmp, 1); +} + +uchar +i2c_reg_read(uchar i2c_addr, uchar reg) +{ + char buf[1]; + + i2c_read(i2c_addr, reg, 1, buf, 1); + + return buf[0]; +} + +void +i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) +{ + i2c_write(i2c_addr, reg, 1, &val, 1); +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c new file mode 100644 index 0000000..1df6cdc --- /dev/null +++ b/cpu/mpc86xx/interrupts.c @@ -0,0 +1,204 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 (440 port) + * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com + * + * (C) Copyright 2003 Motorola Inc. (MPC85xx port) + * Xianghua Xiao (X.Xiao@motorola.com) + * + * (C) Copyright 2004 Freescale Semiconductor. (MPC86xx Port) + * Jeff Brown + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc86xx.h> +#include <command.h> +#include <asm/processor.h> +#include <ppc_asm.tmpl> + +unsigned long decrementer_count; /* count value for 1e6/HZ microseconds */ +unsigned long timestamp; + + +static __inline__ unsigned long get_msr(void) +{ + unsigned long msr; + + asm volatile ("mfmsr %0":"=r" (msr):); + + return msr; +} + +static __inline__ void set_msr(unsigned long msr) +{ + asm volatile ("mtmsr %0"::"r" (msr)); +} + +static __inline__ unsigned long get_dec(void) +{ + unsigned long val; + + asm volatile ("mfdec %0":"=r" (val):); + + return val; +} + +static __inline__ void set_dec(unsigned long val) +{ + if (val) + asm volatile ("mtdec %0"::"r" (val)); +} + +/* interrupt is not supported yet */ +int interrupt_init_cpu(unsigned *decrementer_count) +{ + return 0; +} + +int interrupt_init(void) +{ + int ret; + + /* call cpu specific function from $(CPU)/interrupts.c */ + ret = interrupt_init_cpu(&decrementer_count); + + if (ret) + return ret; + + decrementer_count = get_tbclk() / CFG_HZ; + debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", + (get_tbclk() / 1000000), + decrementer_count); + + set_dec(decrementer_count); + + set_msr(get_msr() | MSR_EE); + + debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", + get_msr(), + get_dec()); + + return 0; +} + +void enable_interrupts(void) +{ + set_msr(get_msr() | MSR_EE); +} + +/* returns flag if MSR_EE was set before */ +int disable_interrupts(void) +{ + ulong msr = get_msr(); + + set_msr(msr & ~MSR_EE); + return (msr & MSR_EE) != 0; +} + +void increment_timestamp(void) +{ + timestamp++; +} + +/* + * timer_interrupt - gets called when the decrementer overflows, + * with interrupts disabled. + * Trivial implementation - no need to be really accurate. + */ +void timer_interrupt_cpu(struct pt_regs *regs) +{ + /* nothing to do here */ +} + +void timer_interrupt(struct pt_regs *regs) +{ + /* call cpu specific function from $(CPU)/interrupts.c */ + timer_interrupt_cpu(regs); + + timestamp++; + + ppcDcbf(×tamp); + + /* Restore Decrementer Count */ + set_dec(decrementer_count); + +#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) + if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0) + WATCHDOG_RESET(); +#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */ + +#ifdef CONFIG_STATUS_LED + status_led_tick(timestamp); +#endif /* CONFIG_STATUS_LED */ + +#ifdef CONFIG_SHOW_ACTIVITY + board_show_activity(timestamp); +#endif /* CONFIG_SHOW_ACTIVITY */ + +} + +void reset_timer(void) +{ + timestamp = 0; +} + +ulong get_timer(ulong base) +{ + return timestamp - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +/* + * Install and free a interrupt handler. Not implemented yet. + */ + +void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) +{ +} + +void irq_free_handler(int vec) +{ +} + +/* + * irqinfo - print information about PCI devices,not implemented. + */ +int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf("\nInterrupt-unsupported:\n"); + + return 0; +} + +/* + * Handle external interrupts + */ +void external_interrupt(struct pt_regs *regs) +{ + puts("external_interrupt (oops!)\n"); +} diff --git a/cpu/mpc86xx/pci.c b/cpu/mpc86xx/pci.c new file mode 100644 index 0000000..b86548d --- /dev/null +++ b/cpu/mpc86xx/pci.c @@ -0,0 +1,146 @@ +/* + * Copyright (C) Freescale Semiconductor,Inc. + * 2005, 2006. All rights reserved. + * + * Ed Swarthout (ed.swarthout@freescale.com) + * Jason Jin (Jason.jin@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCIE Configuration space access support for PCIE Bridge + */ +#include <common.h> +#include <pci.h> + +#if defined(CONFIG_PCI) +void +pci_mpc86xx_init(struct pci_controller *hose) +{ + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_pex_t *pcie1 = &immap->im_pex1; + u16 temp16; + u32 temp32; + + volatile ccsr_gur_t *gur = &immap->im_gur; + uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; + uint pcie1_host = (host1_agent == 2) || (host1_agent == 3); + uint pcie1_agent = (host1_agent == 0) || (host1_agent == 1); + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + + if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || + io_sel == 7 || io_sel == 0xf) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + printf("PCI-EXPRESS 1: Configured as %s \n", + pcie1_agent ? "Agent" : "Host"); + if (pcie1_agent) + return; /*Don't scan bus when configured as agent */ + printf(" Scanning PCIE bus"); + debug("0x%08x=0x%08x ", + &pcie1->pme_msg_det, + pcie1->pme_msg_det); + if (pcie1->pme_msg_det) { + pcie1->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pcie1->pme_msg_det); + } + debug("\n"); + } else { + printf("PCI-EXPRESS 1 disabled!\n"); + return; + } + + /* + * Set first_bus=0 only skipped B0:D0:F0 which is + * a reserved device in M1575, but make it easy for + * most of the scan process. + */ + hose->first_busno = 0x00; + hose->last_busno = 0xfe; + + pcie_setup_indirect(hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004)); + + pci_hose_read_config_word(hose, + PCI_BDF(0, 0, 0), PCI_COMMAND, &temp16); + temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_hose_write_config_word(hose, + PCI_BDF(0, 0, 0), PCI_COMMAND, temp16); + + pci_hose_write_config_word(hose, PCI_BDF(0, 0, 0), PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, + PCI_BDF(0, 0, 0), PCI_LATENCY_TIMER, 0x80); + + pci_hose_read_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS, + &temp32); + temp32 = (temp32 & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16); + pci_hose_write_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS, + temp32); + + pcie1->powar1 = 0; + pcie1->powar2 = 0; + pcie1->piwar1 = 0; + pcie1->piwar1 = 0; + + pcie1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcie1->powar1 = 0x8004401c; /* 512M MEM space */ + pcie1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcie1->potear1 = 0x00000000; + + pcie1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; + pcie1->powar2 = 0x80088017; /* 16M IO space */ + pcie1->potar2 = 0x00000000; + pcie1->potear2 = 0x00000000; + + pcie1->pitar1 = 0x00000000; + pcie1->piwbar1 = 0x00000000; + /* Enable, Prefetch, Local Mem, * Snoop R/W, 2G */ + pcie1->piwar1 = 0xa0f5501e; + + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + pci_set_region(hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + pci_register_hose(hose); + + hose->last_busno = pci_hose_scan(hose); + debug("pcie_mpc86xx_init: last_busno %x\n", hose->last_busno); + debug("pcie_mpc86xx init: current_busno %x\n ", hose->current_busno); + + printf("....PCIE1 scan & enumeration done\n"); +} +#endif /* CONFIG_PCI */ diff --git a/cpu/mpc86xx/pcie_indirect.c b/cpu/mpc86xx/pcie_indirect.c new file mode 100644 index 0000000..b00ad76 --- /dev/null +++ b/cpu/mpc86xx/pcie_indirect.c @@ -0,0 +1,199 @@ +/* + * Support for indirect PCI bridges. + * + * Copyright (c) Freescale Semiconductor, Inc. + * 2006. All rights reserved. + * + * Jason Jin <Jason.jin@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * partly derived from + * arch/powerpc/platforms/86xx/mpc86xx_pcie.c + */ + +#include <common.h> + +#ifdef CONFIG_PCI + +#include <asm/processor.h> +#include <asm/io.h> +#include <pci.h> + +#define PCI_CFG_OUT out_be32 +#define PEX_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff) + +static int +indirect_read_config_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + int len, + u32 *val) +{ + int bus = PCI_BUS(dev); + + volatile unsigned char *cfg_data; + u32 temp; + + PEX_FIX; + if (bus == 0xff) { + PCI_CFG_OUT(hose->cfg_addr, + dev | (offset & 0xfc) | 0x80000001); + } else { + PCI_CFG_OUT(hose->cfg_addr, + dev | (offset & 0xfc) | 0x80000000); + } + /* + * Note: the caller has already checked that offset is + * suitably aligned and that len is 1, 2 or 4. + */ + /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ + cfg_data = hose->cfg_data; + PEX_FIX; + temp = in_le32((u32 *) cfg_data); + switch (len) { + case 1: + *val = (temp >> (((offset & 3)) * 8)) & 0xff; + break; + case 2: + *val = (temp >> (((offset & 3)) * 8)) & 0xffff; + break; + default: + *val = temp; + break; + } + + return 0; +} + +static int +indirect_write_config_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + int len, + u32 val) +{ + int bus = PCI_BUS(dev); + volatile unsigned char *cfg_data; + u32 temp; + + PEX_FIX; + if (bus == 0xff) { + PCI_CFG_OUT(hose->cfg_addr, + dev | (offset & 0xfc) | 0x80000001); + } else { + PCI_CFG_OUT(hose->cfg_addr, + dev | (offset & 0xfc) | 0x80000000); + } + + /* + * Note: the caller has already checked that offset is + * suitably aligned and that len is 1, 2 or 4. + */ + /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ + cfg_data = hose->cfg_data; + switch (len) { + case 1: + PEX_FIX; + temp = in_le32((u32 *) cfg_data); + temp = (temp & ~(0xff << ((offset & 3) * 8))) | + (val << ((offset & 3) * 8)); + PEX_FIX; + out_le32((u32 *) cfg_data, temp); + break; + case 2: + PEX_FIX; + temp = in_le32((u32 *) cfg_data); + temp = (temp & ~(0xffff << ((offset & 3) * 8))); + temp |= (val << ((offset & 3) * 8)); + PEX_FIX; + out_le32((u32 *) cfg_data, temp); + break; + default: + PEX_FIX; + out_le32((u32 *) cfg_data, val); + break; + } + PEX_FIX; + return 0; +} + +static int +indirect_read_config_byte_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + u8 *val) +{ + u32 val32; + indirect_read_config_pcie(hose, dev, offset, 1, &val32); + *val = (u8) val32; + return 0; +} + +static int +indirect_read_config_word_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + u16 *val) +{ + u32 val32; + indirect_read_config_pcie(hose, dev, offset, 2, &val32); + *val = (u16) val32; + return 0; +} + +static int +indirect_read_config_dword_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + u32 *val) +{ + return indirect_read_config_pcie(hose, dev, offset, 4, val); +} + +static int +indirect_write_config_byte_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + u8 val) +{ + return indirect_write_config_pcie(hose, dev, offset, 1, (u32) val); +} + +static int +indirect_write_config_word_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + unsigned short val) +{ + return indirect_write_config_pcie(hose, dev, offset, 2, (u32) val); +} + +static int +indirect_write_config_dword_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + u32 val) +{ + return indirect_write_config_pcie(hose, dev, offset, 4, val); +} + +void +pcie_setup_indirect(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) +{ + pci_set_ops(hose, + indirect_read_config_byte_pcie, + indirect_read_config_word_pcie, + indirect_read_config_dword_pcie, + indirect_write_config_byte_pcie, + indirect_write_config_word_pcie, + indirect_write_config_dword_pcie); + + hose->cfg_addr = (unsigned int *)cfg_addr; + hose->cfg_data = (unsigned char *)cfg_data; +} + +#endif /* CONFIG_PCI */ diff --git a/cpu/mpc86xx/resetvec.S b/cpu/mpc86xx/resetvec.S new file mode 100644 index 0000000..9a552f6 --- /dev/null +++ b/cpu/mpc86xx/resetvec.S @@ -0,0 +1,2 @@ + .section .resetvec,"ax" + b _start diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c new file mode 100644 index 0000000..a4b9d54 --- /dev/null +++ b/cpu/mpc86xx/spd_sdram.c @@ -0,0 +1,1332 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2003 Motorola Inc. + * Xianghua Xiao (X.Xiao@motorola.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <i2c.h> +#include <spd.h> +#include <asm/mmu.h> + + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void dma_init(void); +extern uint dma_check(void); +extern int dma_xfer(void *dest, uint count, void *src); +#endif + +#ifdef CONFIG_SPD_EEPROM + +#ifndef CFG_READ_SPD +#define CFG_READ_SPD i2c_read +#endif + +/* + * Only one of the following three should be 1; others should be 0 + * By default the cache line interleaving is selected if + * the CONFIG_DDR_INTERLEAVE flag is defined + */ +#define CFG_PAGE_INTERLEAVING 0 +#define CFG_BANK_INTERLEAVING 0 +#define CFG_SUPER_BANK_INTERLEAVING 0 + +/* + * Convert picoseconds into clock cycles (rounding up if needed). + */ + +int +picos_to_clk(int picos) +{ + int clks; + + clks = picos / (2000000000 / (get_bus_freq(0) / 1000)); + if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) { + clks++; + } + + return clks; +} + + +/* + * Calculate the Density of each Physical Rank. + * Returned size is in bytes. + * + * Study these table from Byte 31 of JEDEC SPD Spec. + * + * DDR I DDR II + * Bit Size Size + * --- ----- ------ + * 7 high 512MB 512MB + * 6 256MB 256MB + * 5 128MB 128MB + * 4 64MB 16GB + * 3 32MB 8GB + * 2 16MB 4GB + * 1 2GB 2GB + * 0 low 1GB 1GB + * + * Reorder Table to be linear by stripping the bottom + * 2 or 5 bits off and shifting them up to the top. + */ + +unsigned int +compute_banksize(unsigned int mem_type, unsigned char row_dens) +{ + unsigned int bsize; + + if (mem_type == SPD_MEMTYPE_DDR) { + /* Bottom 2 bits up to the top. */ + bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24; + debug("DDR: DDR I rank density = 0x%08x\n", bsize); + } else { + /* Bottom 5 bits up to the top. */ + bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27; + debug("DDR: DDR II rank density = 0x%08x\n", bsize); + } + return bsize; +} + + +/* + * Convert a two-nibble BCD value into a cycle time. + * While the spec calls for nano-seconds, picos are returned. + * + * This implements the tables for bytes 9, 23 and 25 for both + * DDR I and II. No allowance for distinguishing the invalid + * fields absent for DDR I yet present in DDR II is made. + * (That is, cycle times of .25, .33, .66 and .75 ns are + * allowed for both DDR II and I.) + */ + +unsigned int +convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) +{ + /* + * Table look up the lower nibble, allow DDR I & II. + */ + unsigned int tenths_ps[16] = { + 0, + 100, + 200, + 300, + 400, + 500, + 600, + 700, + 800, + 900, + 250, + 330, + 660, + 750, + 0, /* undefined */ + 0 /* undefined */ + }; + + unsigned int whole_ns = (spd_val & 0xF0) >> 4; + unsigned int tenth_ns = spd_val & 0x0F; + unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns]; + + return ps; +} + + +long int +spd_init(unsigned char i2c_address, unsigned int ddr_num, + unsigned int dimm_num, unsigned int start_addr) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr; + volatile ccsr_gur_t *gur = &immap->im_gur; + spd_eeprom_t spd; + unsigned int n_ranks; + unsigned int rank_density; + unsigned int odt_rd_cfg, odt_wr_cfg; + unsigned int odt_cfg, mode_odt_enable; + unsigned int dqs_cfg; + unsigned char twr_clk, twtr_clk, twr_auto_clk; + unsigned int tCKmin_ps, tCKmax_ps; + unsigned int max_data_rate; + unsigned int busfreq; + unsigned sdram_cfg_1; + unsigned int memsize; + unsigned char caslat, caslat_ctrl; + unsigned int trfc, trfc_clk, trfc_low, trfc_high; + unsigned int trcd_clk; + unsigned int trtp_clk; + unsigned char cke_min_clk; + unsigned char add_lat; + unsigned char wr_lat; + unsigned char wr_data_delay; + unsigned char four_act; + unsigned char cpo; + unsigned char burst_len; + unsigned int mode_caslat; + unsigned char sdram_type; + unsigned char d_init; + unsigned int law_size; + volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; + unsigned int tCycle_ps, modfreq; + + if (ddr_num == 1) + ddr = &immap->im_ddr1; + else + ddr = &immap->im_ddr2; + + /* + * Read SPD information. + */ + + debug("Performing SPD read at I2C address 0x%02lx\n",i2c_address); + memset((void *)&spd, 0, sizeof(spd)); + CFG_READ_SPD(i2c_address, 0, 1, (uchar *) &spd, sizeof(spd)); + + /* + * Check for supported memory module types. + */ + if (spd.mem_type != SPD_MEMTYPE_DDR && + spd.mem_type != SPD_MEMTYPE_DDR2) { + debug("Warning: Unable to locate DDR I or DDR II module for DIMM %d of DDR controller %d.\n" + " Fundamental memory type is 0x%0x\n", + dimm_num, + ddr_num, + spd.mem_type); + return 0; + } + + debug("\nFound memory of type 0x%02lx ", spd.mem_type); + if (spd.mem_type == SPD_MEMTYPE_DDR) + debug("DDR I\n"); + else + debug("DDR II\n"); + + /* + * These test gloss over DDR I and II differences in interpretation + * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks + * are not supported on DDR I; and not encoded on DDR II. + * + * Also note that the 8548 controller can support: + * 12 <= nrow <= 16 + * and + * 8 <= ncol <= 11 (still, for DDR) + * 6 <= ncol <= 9 (for FCRAM) + */ + if (spd.nrow_addr < 12 || spd.nrow_addr > 14) { + printf("DDR: Unsupported number of Row Addr lines: %d.\n", + spd.nrow_addr); + return 0; + } + if (spd.ncol_addr < 8 || spd.ncol_addr > 11) { + printf("DDR: Unsupported number of Column Addr lines: %d.\n", + spd.ncol_addr); + return 0; + } + + /* + * Determine the number of physical banks controlled by + * different Chip Select signals. This is not quite the + * same as the number of DIMM modules on the board. Feh. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + n_ranks = spd.nrows; + } else { + n_ranks = (spd.nrows & 0x7) + 1; + } + + debug("DDR: number of ranks = %d\n", n_ranks); + + if (n_ranks > 2) { + printf("DDR: Only 2 chip selects are supported: %d\n", + n_ranks); + return 0; + } + + /* + * Adjust DDR II IO voltage biasing. It just makes it work. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + gur->ddrioovcr = (0 + | 0x80000000 /* Enable */ + | 0x10000000 /* VSEL to 1.8V */ + ); + } + + /* + * Determine the size of each Rank in bytes. + */ + rank_density = compute_banksize(spd.mem_type, spd.row_dens); + + debug("Start address for this controller is 0x%08lx\n", start_addr); + + /* + * ODT configuration recommendation from DDR Controller Chapter. + */ + odt_rd_cfg = 0; /* Never assert ODT */ + odt_wr_cfg = 0; /* Never assert ODT */ + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */ + } + +#ifdef CONFIG_DDR_INTERLEAVE + + if (dimm_num != 1) { + printf("For interleaving memory on HPCN, need to use DIMM 1 for DDR Controller %d !\n", ddr_num); + return 0; + } else { + /* + * Since interleaved memory only uses CS0, the + * memory sticks have to be identical in size and quantity + * of ranks. That essentially gives double the size on + * one rank, i.e on CS0 for both controllers put together. + * Confirm this??? + */ + rank_density *= 2; + + /* + * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg + */ + start_addr = 0; + ddr->cs0_bnds = (start_addr >> 8) + | (((start_addr + rank_density - 1) >> 24)); + /* + * Default interleaving mode to cache-line interleaving. + */ + ddr->cs0_config = ( 1 << 31 +#if (CFG_PAGE_INTERLEAVING == 1) + | (PAGE_INTERLEAVING) +#elif (CFG_BANK_INTERLEAVING == 1) + | (BANK_INTERLEAVING) +#elif (CFG_SUPER_BANK_INTERLEAVING == 1) + | (SUPER_BANK_INTERLEAVING) +#else + | (CACHE_LINE_INTERLEAVING) +#endif + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + + debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds); + debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config); + + /* + * Adjustment for dual rank memory to get correct memory + * size (return value of this function). + */ + if (n_ranks == 2) { + n_ranks = 1; + rank_density /= 2; + } else { + rank_density /= 2; + } + } +#else /* CONFIG_DDR_INTERLEAVE */ + + if (dimm_num == 1) { + /* + * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg + */ + ddr->cs0_bnds = (start_addr >> 8) + | (((start_addr + rank_density - 1) >> 24)); + + ddr->cs0_config = ( 1 << 31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + + debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds); + debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config); + + if (n_ranks == 2) { + /* + * Eg: Bounds: 0x1000_0000 to 0x1f00_0000, + * second 256 Meg + */ + ddr->cs1_bnds = (((start_addr + rank_density) >> 8) + | (( start_addr + 2*rank_density - 1) + >> 24)); + ddr->cs1_config = ( 1<<31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds); + debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config); + } + + } else { + /* + * This is the 2nd DIMM slot for this controller + */ + /* + * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg + */ + ddr->cs2_bnds = (start_addr >> 8) + | (((start_addr + rank_density - 1) >> 24)); + + ddr->cs2_config = ( 1 << 31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + + debug("DDR: cs2_bnds = 0x%08x\n", ddr->cs2_bnds); + debug("DDR: cs2_config = 0x%08x\n", ddr->cs2_config); + + if (n_ranks == 2) { + /* + * Eg: Bounds: 0x1000_0000 to 0x1f00_0000, + * second 256 Meg + */ + ddr->cs3_bnds = (((start_addr + rank_density) >> 8) + | (( start_addr + 2*rank_density - 1) + >> 24)); + ddr->cs3_config = ( 1<<31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + debug("DDR: cs3_bnds = 0x%08x\n", ddr->cs3_bnds); + debug("DDR: cs3_config = 0x%08x\n", ddr->cs3_config); + } + } +#endif /* CONFIG_DDR_INTERLEAVE */ + + /* + * Find the largest CAS by locating the highest 1 bit + * in the spd.cas_lat field. Translate it to a DDR + * controller field value: + * + * CAS Lat DDR I DDR II Ctrl + * Clocks SPD Bit SPD Bit Value + * ------- ------- ------- ----- + * 1.0 0 0001 + * 1.5 1 0010 + * 2.0 2 2 0011 + * 2.5 3 0100 + * 3.0 4 3 0101 + * 3.5 5 0110 + * 4.0 4 0111 + * 4.5 1000 + * 5.0 5 1001 + */ + caslat = __ilog2(spd.cas_lat); + if ((spd.mem_type == SPD_MEMTYPE_DDR) + && (caslat > 5)) { + printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat); + return 0; + + } else if (spd.mem_type == SPD_MEMTYPE_DDR2 + && (caslat < 2 || caslat > 5)) { + printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n", + spd.cas_lat); + return 0; + } + debug("DDR: caslat SPD bit is %d\n", caslat); + + /* + * Calculate the Maximum Data Rate based on the Minimum Cycle time. + * The SPD clk_cycle field (tCKmin) is measured in tenths of + * nanoseconds and represented as BCD. + */ + tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle); + debug("DDR: tCKmin = %d ps\n", tCKmin_ps); + + /* + * Double-data rate, scaled 1000 to picoseconds, and back down to MHz. + */ + max_data_rate = 2 * 1000 * 1000 / tCKmin_ps; + debug("DDR: Module max data rate = %d Mhz\n", max_data_rate); + + + /* + * Adjust the CAS Latency to allow for bus speeds that + * are slower than the DDR module. + */ + busfreq = get_bus_freq(0) / 1000000; /* MHz */ + + if ((spd.mem_type == SPD_MEMTYPE_DDR2) && (busfreq < 266)) { + printf("DDR: platform frequency too low for correct DDR2 controller operation\n"); + return 0; + } else if (busfreq < 90) { + printf("DDR: platform frequency too low for correct DDR1 operation\n"); + return 0; + } + + if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 2)))) { + caslat -= 2; + } else { + tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle2); + modfreq = 2 * 1000 * 1000 / tCycle_ps; + if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 1)))) + caslat -= 1; + else if (busfreq > max_data_rate) { + printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n", + busfreq, max_data_rate); + return 0; + } + } + + /* + * Empirically set ~MCAS-to-preamble override for DDR 2. + * Your milage will vary. + */ + cpo = 0; + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + if (busfreq <= 333) { + cpo = 0x7; + } else if (busfreq <= 400) { + cpo = 0x9; + } else { + cpo = 0xa; + } + } + + /* + * Convert caslat clocks to DDR controller value. + * Force caslat_ctrl to be DDR Controller field-sized. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + caslat_ctrl = (caslat + 1) & 0x07; + } else { + caslat_ctrl = (2 * caslat - 1) & 0x0f; + } + + debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n", + caslat, caslat_ctrl); + + /* + * Timing Config 0. + * Avoid writing for DDR I. The new PQ38 DDR controller + * dreams up non-zero default values to be backwards compatible. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + unsigned char taxpd_clk = 8; /* By the book. */ + unsigned char tmrd_clk = 2; /* By the book. */ + unsigned char act_pd_exit = 2; /* Empirical? */ + unsigned char pre_pd_exit = 6; /* Empirical? */ + + ddr->timing_cfg_0 = (0 + | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */ + | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */ + | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */ + | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */ + ); + debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); + + } + + + /* + * Some Timing Config 1 values now. + * Sneak Extended Refresh Recovery in here too. + */ + + /* + * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD, + * use conservative value. + * For DDR II, they are bytes 36 and 37, in quarter nanos. + */ + + if (spd.mem_type == SPD_MEMTYPE_DDR) { + twr_clk = 3; /* Clocks */ + twtr_clk = 1; /* Clocks */ + } else { + twr_clk = picos_to_clk(spd.twr * 250); + twtr_clk = picos_to_clk(spd.twtr * 250); + } + + /* + * Calculate Trfc, in picos. + * DDR I: Byte 42 straight up in ns. + * DDR II: Byte 40 and 42 swizzled some, in ns. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + trfc = spd.trfc * 1000; /* up to ps */ + } else { + unsigned int byte40_table_ps[8] = { + 0, + 250, + 330, + 500, + 660, + 750, + 0, + 0 + }; + + trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000 + + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7]; + } + trfc_clk = picos_to_clk(trfc); + + /* + * Trcd, Byte 29, from quarter nanos to ps and clocks. + */ + trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7; + + /* + * Convert trfc_clk to DDR controller fields. DDR I should + * fit in the REFREC field (16-19) of TIMING_CFG_1, but the + * 8548 controller has an extended REFREC field of three bits. + * The controller automatically adds 8 clocks to this value, + * so preadjust it down 8 first before splitting it up. + */ + trfc_low = (trfc_clk - 8) & 0xf; + trfc_high = ((trfc_clk - 8) >> 4) & 0x3; + + /* + * Sneak in some Extended Refresh Recovery. + */ + ddr->ext_refrec = (trfc_high << 16); + debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec); + + ddr->timing_cfg_1 = + (0 + | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */ + | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */ + | (trcd_clk << 20) /* ACTTORW */ + | (caslat_ctrl << 16) /* CASLAT */ + | (trfc_low << 12) /* REFEC */ + | ((twr_clk & 0x07) << 8) /* WRRREC */ + | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */ + | ((twtr_clk & 0x07) << 0) /* WRTORD */ + ); + + debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); + + + /* + * Timing_Config_2 + * Was: 0x00000800; + */ + + /* + * Additive Latency + * For DDR I, 0. + * For DDR II, with ODT enabled, use "a value" less than ACTTORW, + * which comes from Trcd, and also note that: + * add_lat + caslat must be >= 4 + */ + add_lat = 0; + if (spd.mem_type == SPD_MEMTYPE_DDR2 + && (odt_wr_cfg || odt_rd_cfg) + && (caslat < 4)) { + add_lat = 4 - caslat; + if (add_lat >= trcd_clk) { + add_lat = trcd_clk - 1; + } + } + + /* + * Write Data Delay + * Historically 0x2 == 4/8 clock delay. + * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266. + */ + wr_data_delay = 3; + + /* + * Write Latency + * Read to Precharge + * Minimum CKE Pulse Width. + * Four Activate Window + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + /* + * This is a lie. It should really be 1, but if it is + * set to 1, bits overlap into the old controller's + * otherwise unused ACSM field. If we leave it 0, then + * the HW will magically treat it as 1 for DDR 1. Oh Yea. + */ + wr_lat = 0; + + trtp_clk = 2; /* By the book. */ + cke_min_clk = 1; /* By the book. */ + four_act = 1; /* By the book. */ + + } else { + wr_lat = caslat - 1; + + /* Convert SPD value from quarter nanos to picos. */ + trtp_clk = picos_to_clk(spd.trtp * 250); + + cke_min_clk = 3; /* By the book. */ + four_act = picos_to_clk(37500); /* By the book. 1k pages? */ + } + + ddr->timing_cfg_2 = (0 + | ((add_lat & 0x7) << 28) /* ADD_LAT */ + | ((cpo & 0x1f) << 23) /* CPO */ + | ((wr_lat & 0x7) << 19) /* WR_LAT */ + | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */ + | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */ + | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */ + | ((four_act & 0x1f) << 0) /* FOUR_ACT */ + ); + + debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); + + + /* + * Determine the Mode Register Set. + * + * This is nominally part specific, but it appears to be + * consistent for all DDR I devices, and for all DDR II devices. + * + * caslat must be programmed + * burst length is always 4 + * burst type is sequential + * + * For DDR I: + * operating mode is "normal" + * + * For DDR II: + * other stuff + */ + + mode_caslat = 0; + + /* + * Table lookup from DDR I or II Device Operation Specs. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + if (1 <= caslat && caslat <= 4) { + unsigned char mode_caslat_table[4] = { + 0x5, /* 1.5 clocks */ + 0x2, /* 2.0 clocks */ + 0x6, /* 2.5 clocks */ + 0x3 /* 3.0 clocks */ + }; + mode_caslat = mode_caslat_table[caslat - 1]; + } else { + puts("DDR I: Only CAS Latencies of 1.5, 2.0, " + "2.5 and 3.0 clocks are supported.\n"); + return 0; + } + + } else { + if (2 <= caslat && caslat <= 5) { + mode_caslat = caslat; + } else { + puts("DDR II: Only CAS Latencies of 2.0, 3.0, " + "4.0 and 5.0 clocks are supported.\n"); + return 0; + } + } + + /* + * Encoded Burst Length of 4. + */ + burst_len = 2; /* Fiat. */ + + if (spd.mem_type == SPD_MEMTYPE_DDR) { + twr_auto_clk = 0; /* Historical */ + } else { + /* + * Determine tCK max in picos. Grab tWR and convert to picos. + * Auto-precharge write recovery is: + * WR = roundup(tWR_ns/tCKmax_ns). + * + * Ponder: Is twr_auto_clk different than twr_clk? + */ + tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax); + twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps; + } + + + /* + * Mode Reg in bits 16 ~ 31, + * Extended Mode Reg 1 in bits 0 ~ 15. + */ + mode_odt_enable = 0x0; /* Default disabled */ + if (odt_wr_cfg || odt_rd_cfg) { + /* + * Bits 6 and 2 in Extended MRS(1) + * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules. + * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module. + */ + mode_odt_enable = 0x40; /* 150 Ohm */ + } + + ddr->sdram_mode_1 = + (0 + | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ + | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */ + | (twr_auto_clk << 9) /* Write Recovery Autopre */ + | (mode_caslat << 4) /* caslat */ + | (burst_len << 0) /* Burst length */ + ); + + debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode_1); + + + /* + * Clear EMRS2 and EMRS3. + */ + ddr->sdram_mode_2 = 0; + debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2); + + + /* + * Determine Refresh Rate. Ignore self refresh bit on DDR I. + * Table from SPD Spec, Byte 12, converted to picoseconds and + * filled in with "default" normal values. + */ + { + unsigned int refresh_clk; + unsigned int refresh_time_ns[8] = { + 15625000, /* 0 Normal 1.00x */ + 3900000, /* 1 Reduced .25x */ + 7800000, /* 2 Extended .50x */ + 31300000, /* 3 Extended 2.00x */ + 62500000, /* 4 Extended 4.00x */ + 125000000, /* 5 Extended 8.00x */ + 15625000, /* 6 Normal 1.00x filler */ + 15625000, /* 7 Normal 1.00x filler */ + }; + + refresh_clk = picos_to_clk(refresh_time_ns[spd.refresh & 0x7]); + + /* + * Set BSTOPRE to 0x100 for page mode + * If auto-charge is used, set BSTOPRE = 0 + */ + ddr->sdram_interval = + (0 + | (refresh_clk & 0x3fff) << 16 + | 0x100 + ); + debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval); + } + + /* + * Is this an ECC DDR chip? + * But don't mess with it if the DDR controller will init mem. + */ +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + if (spd.config == 0x02) { + ddr->err_disable = 0x0000000d; + ddr->err_sbe = 0x00ff0000; + } + debug("DDR: err_disable = 0x%08x\n", ddr->err_disable); + debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe); +#endif + + asm("sync;isync"); + udelay(500); + + /* + * SDRAM Cfg 2 + */ + + /* + * When ODT is enabled, Chap 9 suggests asserting ODT to + * internal IOs only during reads. + */ + odt_cfg = 0; + if (odt_rd_cfg | odt_wr_cfg) { + odt_cfg = 0x2; /* ODT to IOs during reads */ + } + + /* + * Try to use differential DQS with DDR II. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + dqs_cfg = 0; /* No Differential DQS for DDR I */ + } else { + dqs_cfg = 0x1; /* Differential DQS for DDR II */ + } + +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Use the DDR controller to auto initialize memory. + */ + d_init = 1; + ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE; + debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init); +#else + /* + * Memory will be initialized via DMA, or not at all. + */ + d_init = 0; +#endif + + ddr->sdram_cfg_2 = (0 + | (dqs_cfg << 26) /* Differential DQS */ + | (odt_cfg << 21) /* ODT */ + | (d_init << 4) /* D_INIT auto init DDR */ + ); + + debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2); + + +#ifdef MPC86xx_DDR_SDRAM_CLK_CNTL + { + unsigned char clk_adjust; + + /* + * Setup the clock control. + * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1 + * SDRAM_CLK_CNTL[5-7] = Clock Adjust + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + clk_adjust = 0x6; + } else { + clk_adjust = 0x7; + } + + ddr->sdram_clk_cntl = (0 + | 0x80000000 + | (clk_adjust << 23) + ); + debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl); + } +#endif + + + /* + * Figure out memory size in Megabytes. + */ + debug("# ranks = %d, rank_density = 0x%08lx\n", n_ranks, rank_density); + memsize = n_ranks * rank_density / 0x100000; + return memsize; +} + + +unsigned int enable_ddr(unsigned int ddr_num) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + spd_eeprom_t spd1,spd2; + volatile ccsr_ddr_t *ddr; + unsigned sdram_cfg_1; + unsigned char sdram_type, mem_type, config, mod_attr; + unsigned char d_init; + unsigned int no_dimm1=0, no_dimm2=0; + + /* Set up pointer to enable the current ddr controller */ + if (ddr_num == 1) + ddr = &immap->im_ddr1; + else + ddr = &immap->im_ddr2; + + /* + * Read both dimm slots and decide whether + * or not to enable this controller. + */ + memset((void *)&spd1,0,sizeof(spd1)); + memset((void *)&spd2,0,sizeof(spd2)); + + if (ddr_num == 1) { + CFG_READ_SPD(SPD_EEPROM_ADDRESS1, + 0, 1, (uchar *) &spd1, sizeof(spd1)); + CFG_READ_SPD(SPD_EEPROM_ADDRESS2, + 0, 1, (uchar *) &spd2, sizeof(spd2)); + } else { + CFG_READ_SPD(SPD_EEPROM_ADDRESS3, + 0, 1, (uchar *) &spd1, sizeof(spd1)); + CFG_READ_SPD(SPD_EEPROM_ADDRESS4, + 0, 1, (uchar *) &spd2, sizeof(spd2)); + } + + /* + * Check for supported memory module types. + */ + if (spd1.mem_type != SPD_MEMTYPE_DDR + && spd1.mem_type != SPD_MEMTYPE_DDR2) { + no_dimm1 = 1; + } else { + debug("\nFound memory of type 0x%02lx ",spd1.mem_type ); + if (spd1.mem_type == SPD_MEMTYPE_DDR) + debug("DDR I\n"); + else + debug("DDR II\n"); + } + + if (spd2.mem_type != SPD_MEMTYPE_DDR && + spd2.mem_type != SPD_MEMTYPE_DDR2) { + no_dimm2 = 1; + } else { + debug("\nFound memory of type 0x%02lx ",spd2.mem_type ); + if (spd2.mem_type == SPD_MEMTYPE_DDR) + debug("DDR I\n"); + else + debug("DDR II\n"); + } + +#ifdef CONFIG_DDR_INTERLEAVE + if (no_dimm1) { + printf("For interleaved operation memory modules need to be present in CS0 DIMM slots of both DDR controllers!\n"); + return 0; + } +#endif + + /* + * Memory is not present in DIMM1 and DIMM2 - so do not enable DDRn + */ + if (no_dimm1 && no_dimm2) { + printf("No memory modules found for DDR controller %d!!\n", ddr_num); + return 0; + } else { + mem_type = no_dimm2 ? spd1.mem_type : spd2.mem_type; + + /* + * Figure out the settings for the sdram_cfg register. + * Build up the entire register in 'sdram_cfg' before + * writing since the write into the register will + * actually enable the memory controller; all settings + * must be done before enabling. + * + * sdram_cfg[0] = 1 (ddr sdram logic enable) + * sdram_cfg[1] = 1 (self-refresh-enable) + * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM) + * 010 DDR 1 SDRAM + * 011 DDR 2 SDRAM + */ + sdram_type = (mem_type == SPD_MEMTYPE_DDR) ? 2 : 3; + sdram_cfg_1 = (0 + | (1 << 31) /* Enable */ + | (1 << 30) /* Self refresh */ + | (sdram_type << 24) /* SDRAM type */ + ); + + /* + * sdram_cfg[3] = RD_EN - registered DIMM enable + * A value of 0x26 indicates micron registered + * DIMMS (micron.com) + */ + mod_attr = no_dimm2 ? spd1.mod_attr : spd2.mod_attr; + if (mem_type == SPD_MEMTYPE_DDR && mod_attr == 0x26) { + sdram_cfg_1 |= 0x10000000; /* RD_EN */ + } + +#if defined(CONFIG_DDR_ECC) + + config = no_dimm2 ? spd1.config : spd2.config; + + /* + * If the user wanted ECC (enabled via sdram_cfg[2]) + */ + if (config == 0x02) { + ddr->err_disable = 0x00000000; + asm("sync;isync;"); + ddr->err_sbe = 0x00ff0000; + ddr->err_int_en = 0x0000000d; + sdram_cfg_1 |= 0x20000000; /* ECC_EN */ + } +#endif + + /* + * Set 1T or 2T timing based on 1 or 2 modules + */ + { + if (!(no_dimm1 || no_dimm2)) { + /* + * 2T timing,because both DIMMS are present. + * Enable 2T timing by setting sdram_cfg[16]. + */ + sdram_cfg_1 |= 0x8000; /* 2T_EN */ + } + } + + /* + * 200 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + */ + udelay(200); + + /* + * Go! + */ + ddr->sdram_cfg_1 = sdram_cfg_1; + + asm volatile("sync;isync"); + udelay(500); + + debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg_1); + + +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + d_init = 1; + debug("DDR: memory initializing\n"); + + /* + * Poll until memory is initialized. + * 512 Meg at 400 might hit this 200 times or so. + */ + while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { + udelay(1000); + } + debug("DDR: memory initialized\n\n"); +#endif + + debug("Enabled DDR Controller %d\n", ddr_num); + return 1; + } +} + + +long int +spd_sdram(void) +{ + int memsize_ddr1_dimm1 = 0; + int memsize_ddr1_dimm2 = 0; + int memsize_ddr2_dimm1 = 0; + int memsize_ddr2_dimm2 = 0; + int memsize_total = 0; + int memsize_ddr1 = 0; + int memsize_ddr2 = 0; + unsigned int ddr1_enabled = 0; + unsigned int ddr2_enabled = 0; + unsigned int law_size_ddr1; + unsigned int law_size_ddr2; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; + volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2; + volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; + +#ifdef CONFIG_DDR_INTERLEAVE + unsigned int law_size_interleaved; + + memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1, + 1, 1, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr1_dimm1; + + memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3, + 2, 1, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr2_dimm1; + + if (memsize_ddr1_dimm1 != memsize_ddr2_dimm1) { + if (memsize_ddr1_dimm1 < memsize_ddr2_dimm1) + memsize_total -= memsize_ddr1_dimm1; + else + memsize_total -= memsize_ddr2_dimm1; + debug("Total memory available for interleaving 0x%08lx\n", + memsize_total * 1024 * 1024); + debug("Adjusting CS0_BNDS to account for unequal DIMM sizes in interleaved memory\n"); + ddr1->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24; + ddr2->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24; + debug("DDR1: cs0_bnds = 0x%08x\n", ddr1->cs0_bnds); + debug("DDR2: cs0_bnds = 0x%08x\n", ddr2->cs0_bnds); + } + + ddr1_enabled = enable_ddr(1); + ddr2_enabled = enable_ddr(2); + + /* + * Both controllers need to be enabled for interleaving. + */ + if (ddr1_enabled && ddr2_enabled) { + law_size_interleaved = 19 + __ilog2(memsize_total); + + /* + * Set up LAWBAR for DDR 1 space. + */ + mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); + mcm->lawar1 = (LAWAR_EN + | LAWAR_TRGT_IF_DDR_INTERLEAVED + | (LAWAR_SIZE & law_size_interleaved)); + debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); + debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1); + debug("Interleaved memory size is 0x%08lx\n", memsize_total); + +#ifdef CONFIG_DDR_INTERLEAVE +#if (CFG_PAGE_INTERLEAVING == 1) + printf("Page "); +#elif (CFG_BANK_INTERLEAVING == 1) + printf("Bank "); +#elif (CFG_SUPER_BANK_INTERLEAVING == 1) + printf("Super-bank "); +#else + printf("Cache-line "); +#endif +#endif + printf("Interleaved"); + return memsize_total * 1024 * 1024; + } else { + printf("Interleaved memory not enabled - check CS0 DIMM slots for both controllers.\n"); + return 0; + } + +#else + /* + * Call spd_sdram() routine to init ddr1 - pass I2c address, + * controller number, dimm number, and starting address. + */ + memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1, + 1, 1, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr1_dimm1; + + memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2, + 1, 2, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr1_dimm2; + + /* + * Enable the DDR controller - pass ddr controller number. + */ + ddr1_enabled = enable_ddr(1); + + /* Keep track of memory to be addressed by DDR1 */ + memsize_ddr1 = memsize_ddr1_dimm1 + memsize_ddr1_dimm2; + + /* + * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord. + */ + if (ddr1_enabled) { + law_size_ddr1 = 19 + __ilog2(memsize_ddr1); + + /* + * Set up LAWBAR for DDR 1 space. + */ + mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); + mcm->lawar1 = (LAWAR_EN + | LAWAR_TRGT_IF_DDR1 + | (LAWAR_SIZE & law_size_ddr1)); + debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); + debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1); + } + +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) + memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3, + 2, 1, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr2_dimm1; + + memsize_ddr2_dimm2 = spd_init(SPD_EEPROM_ADDRESS4, + 2, 2, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr2_dimm2; + + ddr2_enabled = enable_ddr(2); + + /* Keep track of memory to be addressed by DDR2 */ + memsize_ddr2 = memsize_ddr2_dimm1 + memsize_ddr2_dimm2; + + if (ddr2_enabled) { + law_size_ddr2 = 19 + __ilog2(memsize_ddr2); + + /* + * Set up LAWBAR for DDR 2 space. + */ + if (ddr1_enabled) + mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12) + & 0xfffff); + else + mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); + + mcm->lawar8 = (LAWAR_EN + | LAWAR_TRGT_IF_DDR2 + | (LAWAR_SIZE & law_size_ddr2)); + debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8); + debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8); + } +#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */ + + debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n", + memsize_ddr1, memsize_ddr2); + + /* + * If neither DDR controller is enabled return 0. + */ + if (!ddr1_enabled && !ddr2_enabled) + return 0; + else { + printf("Non-interleaved"); + return memsize_total * 1024 * 1024; + } + +#endif /* CONFIG_DDR_INTERLEAVE */ +} + + +#endif /* CONFIG_SPD_EEPROM */ + + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + +/* + * Initialize all of memory for ECC, then enable errors. + */ + +void +ddr_enable_ecc(unsigned int dram_size) +{ + uint *p = 0; + uint i = 0; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr1= &immap->im_ddr1; + + dma_init(); + + for (*p = 0; p < (uint *)(8 * 1024); p++) { + if (((unsigned int)p & 0x1f) == 0) { + ppcDcbz((unsigned long) p); + } + *p = (unsigned int)CONFIG_MEM_INIT_VALUE; + if (((unsigned int)p & 0x1c) == 0x1c) { + ppcDcbf((unsigned long) p); + } + } + + /* 8K */ + dma_xfer((uint *)0x2000, 0x2000, (uint *)0); + /* 16K */ + dma_xfer((uint *)0x4000, 0x4000, (uint *)0); + /* 32K */ + dma_xfer((uint *)0x8000, 0x8000, (uint *)0); + /* 64K */ + dma_xfer((uint *)0x10000, 0x10000, (uint *)0); + /* 128k */ + dma_xfer((uint *)0x20000, 0x20000, (uint *)0); + /* 256k */ + dma_xfer((uint *)0x40000, 0x40000, (uint *)0); + /* 512k */ + dma_xfer((uint *)0x80000, 0x80000, (uint *)0); + /* 1M */ + dma_xfer((uint *)0x100000, 0x100000, (uint *)0); + /* 2M */ + dma_xfer((uint *)0x200000, 0x200000, (uint *)0); + /* 4M */ + dma_xfer((uint *)0x400000, 0x400000, (uint *)0); + + for (i = 1; i < dram_size / 0x800000; i++) { + dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0); + } + + /* + * Enable errors for ECC. + */ + debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable); + ddr1->err_disable = 0x00000000; + asm("sync;isync;msync"); + debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable); +} + +#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */ diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c new file mode 100644 index 0000000..312ca12 --- /dev/null +++ b/cpu/mpc86xx/speed.c @@ -0,0 +1,127 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Jeff Brown + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc86xx.h> +#include <asm/processor.h> + + +void get_sys_info(sys_info_t *sysInfo) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint plat_ratio, e600_ratio; + + plat_ratio = (gur->porpllsr) & 0x0000003e; + plat_ratio >>= 1; + + switch (plat_ratio) { + case 0x0: + sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ; + break; + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x08: + case 0x09: + case 0x0a: + case 0x0c: + case 0x10: + sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; + break; + default: + sysInfo->freqSystemBus = 0; + break; + } + + e600_ratio = (gur->porpllsr) & 0x003f0000; + e600_ratio >>= 16; + + switch (e600_ratio) { + case 0x10: + sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus; + break; + case 0x19: + sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus / 2; + break; + case 0x20: + sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; + break; + case 0x39: + sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus / 2; + break; + case 0x28: + sysInfo->freqProcessor = 4 * sysInfo->freqSystemBus; + break; + case 0x1d: + sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus / 2; + break; + default: + sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus; + break; + } +} + + +/* + * Measure CPU clock speed (core clock GCLK1, GCLK2) + * (Approx. GCLK frequency in Hz) + */ + +int get_clocks(void) +{ + DECLARE_GLOBAL_DATA_PTR; + sys_info_t sys_info; + + get_sys_info(&sys_info); + gd->cpu_clk = sys_info.freqProcessor; + gd->bus_clk = sys_info.freqSystemBus; + + if (gd->cpu_clk != 0) + return 0; + else + return 1; +} + + +/* + * get_bus_freq + * Return system bus freq in Hz + */ + +ulong get_bus_freq(ulong dummy) +{ + ulong val; + sys_info_t sys_info; + + get_sys_info(&sys_info); + val = sys_info.freqSystemBus; + + return val; +} diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S new file mode 100644 index 0000000..e537dcb --- /dev/null +++ b/cpu/mpc86xx/start.S @@ -0,0 +1,1227 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Srikanth Srinivasan <srikanth.srinivaan@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards + * + * + * The processor starts at 0xfff00100 and the code is executed + * from flash. The code is organized to be at an other address + * in memory, but as long we don't jump around before relocating. + * board_init lies at a quite high address and when the cpu has + * jumped there, everything is ok. + */ +#include <config.h> +#include <mpc86xx.h> +#include <version.h> + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#include <asm/cache.h> +#include <asm/mmu.h> + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +/* We don't want the MMU yet. +*/ +#undef MSR_KERNEL +/* Machine Check and Recoverable Interr. */ +#define MSR_KERNEL ( MSR_ME | MSR_RI ) + +/* + * Set up GOT: Global Offset Table + * + * Use r14 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) + + GOT_ENTRY(__init_end) + GOT_ENTRY(_end) + GOT_ENTRY(__bss_start) + END_GOT + +/* + * r3 - 1st arg to board_init(): IMMP pointer + * r4 - 2nd arg to board_init(): boot flag + */ + .text + .long 0x27051956 /* U-Boot Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" + + . = EXC_OFF_SYS_RESET + .globl _start +_start: + li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */ + b boot_cold + sync + + . = EXC_OFF_SYS_RESET + 0x10 + + .globl _start_warm +_start_warm: + li r21, BOOTFLAG_WARM /* Software reboot */ + b boot_warm + sync + + /* the boot code is located below the exception table */ + + .globl _start_of_vectors +_start_of_vectors: + +/* Machine check */ + STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) + +/* Data Storage exception. */ + STD_EXCEPTION(0x300, DataStorage, UnknownException) + +/* Instruction Storage exception. */ + STD_EXCEPTION(0x400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) + +/* Alignment exception. */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_Alignment: + .long AlignmentException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Program check exception */ + . = 0x700 +ProgramCheck: + EXCEPTION_PROLOG + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_ProgramCheck: + .long ProgramCheckException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + + STD_EXCEPTION(0x800, FPUnavailable, UnknownException) + + /* I guess we could implement decrementer, and may have + * to someday for timekeeping. + */ + STD_EXCEPTION(0x900, Decrementer, timer_interrupt) + STD_EXCEPTION(0xa00, Trap_0a, UnknownException) + STD_EXCEPTION(0xb00, Trap_0b, UnknownException) + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + STD_EXCEPTION(0xd00, SingleStep, UnknownException) + STD_EXCEPTION(0xe00, Trap_0e, UnknownException) + STD_EXCEPTION(0xf00, Trap_0f, UnknownException) + STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) + STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) + STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) + STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) + STD_EXCEPTION(0x1400, DataTLBError, UnknownException) + STD_EXCEPTION(0x1500, Reserved5, UnknownException) + STD_EXCEPTION(0x1600, Reserved6, UnknownException) + STD_EXCEPTION(0x1700, Reserved7, UnknownException) + STD_EXCEPTION(0x1800, Reserved8, UnknownException) + STD_EXCEPTION(0x1900, Reserved9, UnknownException) + STD_EXCEPTION(0x1a00, ReservedA, UnknownException) + STD_EXCEPTION(0x1b00, ReservedB, UnknownException) + STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) + STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException) + STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) + STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) + + .globl _end_of_vectors +_end_of_vectors: + + . = 0x2000 + +boot_cold: +boot_warm: + + /* if this is a multi-core system we need to check which cpu + * this is, if it is not cpu 0 send the cpu to the linux reset + * vector */ +#if (CONFIG_NUM_CPUS > 1) + mfspr r0, MSSCR0 + andi. r0, r0, 0x0020 + rlwinm r0,r0,27,31,31 + mtspr PIR, r0 + beq 1f + + bl secondary_cpu_setup +#endif + + /* disable everything */ +1: li r0, 0 + mtspr HID0, r0 + sync + mtmsr 0 + bl invalidate_bats + sync + +#ifdef CFG_L2 + /* init the L2 cache */ + addis r3, r0, L2_INIT@h + ori r3, r3, L2_INIT@l + mtspr l2cr, r3 + /* invalidate the L2 cache */ + bl l2cache_invalidate + sync +#endif + + /* + * Calculate absolute address in FLASH and jump there + *------------------------------------------------------*/ + lis r3, CFG_MONITOR_BASE@h + ori r3, r3, CFG_MONITOR_BASE@l + addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET + mtlr r3 + blr + +in_flash: + /* let the C-code set up the rest */ + /* */ + /* Be careful to keep code relocatable ! */ + /*------------------------------------------------------*/ + /* perform low-level init */ + + /* enable extended addressing */ + bl enable_ext_addr + + /* setup the bats */ + bl setup_bats + sync + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* setup ccsrbar */ + bl setup_ccsrbar +#endif + + /* Fix for SMP linux - Changing arbitration to round-robin */ + lis r3, CFG_CCSRBAR@h + ori r3, r3, 0x1000 + xor r4, r4, r4 + li r4, 0x1000 + stw r4, 0(r3) + + /* setup the law entries */ + bl law_entry + sync + + /* Don't use this feature due to bug in 8641D PD4 */ + /* Disable ERD_DIS */ + lis r3, CFG_CCSRBAR@h + ori r3, r3, 0x1008 + lwz r4, 0(r3) + oris r4, r4, 0x4000 + stw r4, 0(r3) + sync + +#if (EMULATOR_RUN == 1) + /* On the emulator we want to adjust these ASAP */ + /* otherwise things are sloooow */ + /* Setup OR0 (LALE FIX)*/ + lis r3, CFG_CCSRBAR@h + ori r3, r3, 0x5004 + li r4, 0x0FF3 + stw r4, 0(r3) + sync + + /* Setup LCRR */ + lis r3, CFG_CCSRBAR@h + ori r3, r3, 0x50D4 + lis r4, 0x8000 + ori r4, r4, 0x0002 + stw r4, 0(r3) + sync +#endif +#if 1 + /* make sure timer enabled in guts register too */ + lis r3, CFG_CCSRBAR@h + oris r3,r3, 0xE + ori r3,r3,0x0070 + lwz r4, 0(r3) + lis r5,0xFFFC + ori r5,r5,0x5FFF + and r4,r4,r5 + stw r4,0(r3) +#endif + /* + * Cache must be enabled here for stack-in-cache trick. + * This means we need to enable the BATS. + * Cache should be turned on after BATs, since by default + * everything is write-through. + */ + + /* enable address translation */ + bl enable_addr_trans + sync + + /* enable and invalidate the data cache */ +/* bl l1dcache_enable */ + bl dcache_enable + sync + +#if 1 + bl icache_enable +#endif + +#ifdef CFG_INIT_RAM_LOCK + bl lock_ram_in_cache + sync +#endif + + /* set up the stack pointer in our newly created + * cache-ram (r1) */ + lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h + ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l + + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + + GET_GOT /* initialize GOT access */ + + /* run low-level CPU init code (from Flash) */ + bl cpu_init_f + sync + +#ifdef RUN_DIAG + + /* Sri: Code to run the diagnostic automatically */ + + /* Load PX_AUX register address in r4 */ + lis r4, 0xf810 + ori r4, r4, 0x6 + /* Load contents of PX_AUX in r3 bits 24 to 31*/ + lbz r3, 0(r4) + + /* Mask and obtain the bit in r3 */ + rlwinm. r3, r3, 0, 24, 24 + /* If not zero, jump and continue with u-boot */ + bne diag_done + + /* Load back contents of PX_AUX in r3 bits 24 to 31 */ + lbz r3, 0(r4) + /* Set the MSB of the register value */ + ori r3, r3, 0x80 + /* Write value in r3 back to PX_AUX */ + stb r3, 0(r4) + + /* Get the address to jump to in r3*/ + lis r3, CFG_DIAG_ADDR@h + ori r3, r3, CFG_DIAG_ADDR@l + + /* Load the LR with the branch address */ + mtlr r3 + + /* Branch to diagnostic */ + blr + +diag_done: +#endif + + /* bl l2cache_enable*/ + mr r3, r21 + + /* r3: BOOTFLAG */ + /* run 1st part of board init code (from Flash) */ + bl board_init_f + sync + + /* NOTREACHED */ + + .globl invalidate_bats +invalidate_bats: + + /* invalidate BATs */ + mtspr IBAT0U, r0 + mtspr IBAT1U, r0 + mtspr IBAT2U, r0 + mtspr IBAT3U, r0 + mtspr IBAT4U, r0 + mtspr IBAT5U, r0 + mtspr IBAT6U, r0 + mtspr IBAT7U, r0 + + isync + mtspr DBAT0U, r0 + mtspr DBAT1U, r0 + mtspr DBAT2U, r0 + mtspr DBAT3U, r0 + mtspr DBAT4U, r0 + mtspr DBAT5U, r0 + mtspr DBAT6U, r0 + mtspr DBAT7U, r0 + + isync + sync + blr + + + /* setup_bats - set them up to some initial state */ + .globl setup_bats +setup_bats: + + addis r0, r0, 0x0000 + + /* IBAT 0 */ + addis r4, r0, CFG_IBAT0L@h + ori r4, r4, CFG_IBAT0L@l + addis r3, r0, CFG_IBAT0U@h + ori r3, r3, CFG_IBAT0U@l + mtspr IBAT0L, r4 + mtspr IBAT0U, r3 + isync + + /* DBAT 0 */ + addis r4, r0, CFG_DBAT0L@h + ori r4, r4, CFG_DBAT0L@l + addis r3, r0, CFG_DBAT0U@h + ori r3, r3, CFG_DBAT0U@l + mtspr DBAT0L, r4 + mtspr DBAT0U, r3 + isync + + /* IBAT 1 */ + addis r4, r0, CFG_IBAT1L@h + ori r4, r4, CFG_IBAT1L@l + addis r3, r0, CFG_IBAT1U@h + ori r3, r3, CFG_IBAT1U@l + mtspr IBAT1L, r4 + mtspr IBAT1U, r3 + isync + + /* DBAT 1 */ + addis r4, r0, CFG_DBAT1L@h + ori r4, r4, CFG_DBAT1L@l + addis r3, r0, CFG_DBAT1U@h + ori r3, r3, CFG_DBAT1U@l + mtspr DBAT1L, r4 + mtspr DBAT1U, r3 + isync + + /* IBAT 2 */ + addis r4, r0, CFG_IBAT2L@h + ori r4, r4, CFG_IBAT2L@l + addis r3, r0, CFG_IBAT2U@h + ori r3, r3, CFG_IBAT2U@l + mtspr IBAT2L, r4 + mtspr IBAT2U, r3 + isync + + /* DBAT 2 */ + addis r4, r0, CFG_DBAT2L@h + ori r4, r4, CFG_DBAT2L@l + addis r3, r0, CFG_DBAT2U@h + ori r3, r3, CFG_DBAT2U@l + mtspr DBAT2L, r4 + mtspr DBAT2U, r3 + isync + + /* IBAT 3 */ + addis r4, r0, CFG_IBAT3L@h + ori r4, r4, CFG_IBAT3L@l + addis r3, r0, CFG_IBAT3U@h + ori r3, r3, CFG_IBAT3U@l + mtspr IBAT3L, r4 + mtspr IBAT3U, r3 + isync + + /* DBAT 3 */ + addis r4, r0, CFG_DBAT3L@h + ori r4, r4, CFG_DBAT3L@l + addis r3, r0, CFG_DBAT3U@h + ori r3, r3, CFG_DBAT3U@l + mtspr DBAT3L, r4 + mtspr DBAT3U, r3 + isync + + /* IBAT 4 */ + addis r4, r0, CFG_IBAT4L@h + ori r4, r4, CFG_IBAT4L@l + addis r3, r0, CFG_IBAT4U@h + ori r3, r3, CFG_IBAT4U@l + mtspr IBAT4L, r4 + mtspr IBAT4U, r3 + isync + + /* DBAT 4 */ + addis r4, r0, CFG_DBAT4L@h + ori r4, r4, CFG_DBAT4L@l + addis r3, r0, CFG_DBAT4U@h + ori r3, r3, CFG_DBAT4U@l + mtspr DBAT4L, r4 + mtspr DBAT4U, r3 + isync + + /* IBAT 5 */ + addis r4, r0, CFG_IBAT5L@h + ori r4, r4, CFG_IBAT5L@l + addis r3, r0, CFG_IBAT5U@h + ori r3, r3, CFG_IBAT5U@l + mtspr IBAT5L, r4 + mtspr IBAT5U, r3 + isync + + /* DBAT 5 */ + addis r4, r0, CFG_DBAT5L@h + ori r4, r4, CFG_DBAT5L@l + addis r3, r0, CFG_DBAT5U@h + ori r3, r3, CFG_DBAT5U@l + mtspr DBAT5L, r4 + mtspr DBAT5U, r3 + isync + + /* IBAT 6 */ + addis r4, r0, CFG_IBAT6L@h + ori r4, r4, CFG_IBAT6L@l + addis r3, r0, CFG_IBAT6U@h + ori r3, r3, CFG_IBAT6U@l + mtspr IBAT6L, r4 + mtspr IBAT6U, r3 + isync + + /* DBAT 6 */ + addis r4, r0, CFG_DBAT6L@h + ori r4, r4, CFG_DBAT6L@l + addis r3, r0, CFG_DBAT6U@h + ori r3, r3, CFG_DBAT6U@l + mtspr DBAT6L, r4 + mtspr DBAT6U, r3 + isync + + /* IBAT 7 */ + addis r4, r0, CFG_IBAT7L@h + ori r4, r4, CFG_IBAT7L@l + addis r3, r0, CFG_IBAT7U@h + ori r3, r3, CFG_IBAT7U@l + mtspr IBAT7L, r4 + mtspr IBAT7U, r3 + isync + + /* DBAT 7 */ + addis r4, r0, CFG_DBAT7L@h + ori r4, r4, CFG_DBAT7L@l + addis r3, r0, CFG_DBAT7U@h + ori r3, r3, CFG_DBAT7U@l + mtspr DBAT7L, r4 + mtspr DBAT7U, r3 + isync + +1: + addis r3, 0, 0x0000 + addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */ + isync + +tlblp: + tlbie r3 + sync + addi r3, r3, 0x1000 + cmp 0, 0, r3, r5 + blt tlblp + + blr + + .globl enable_addr_trans +enable_addr_trans: + /* enable address translation */ + mfmsr r5 + ori r5, r5, (MSR_IR | MSR_DR) + mtmsr r5 + isync + blr + + .globl disable_addr_trans +disable_addr_trans: + /* disable address translation */ + mflr r4 + mfmsr r3 + andi. r0, r3, (MSR_IR | MSR_DR) + beqlr + andc r3, r3, r0 + mtspr SRR0, r4 + mtspr SRR1, r3 + rfi + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + mtspr SPRG2,r22 /* r1 is now kernel sp */ + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + + .globl dc_read +dc_read: + blr + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + + .globl get_svr +get_svr: + mfspr r3, SVR + blr + + +/* + * Function: in8 + * Description: Input 8 bits + */ + .globl in8 +in8: + lbz r3,0x0000(r3) + blr + +/* + * Function: out8 + * Description: Output 8 bits + */ + .globl out8 +out8: + stb r4,0x0000(r3) + blr + +/* + * Function: out16 + * Description: Output 16 bits + */ + .globl out16 +out16: + sth r4,0x0000(r3) + blr + +/* + * Function: out16r + * Description: Byte reverse and output 16 bits + */ + .globl out16r +out16r: + sthbrx r4,r0,r3 + blr + +/* + * Function: out32 + * Description: Output 32 bits + */ + .globl out32 +out32: + stw r4,0x0000(r3) + blr + +/* + * Function: out32r + * Description: Byte reverse and output 32 bits + */ + .globl out32r +out32r: + stwbrx r4,r0,r3 + blr + +/* + * Function: in16 + * Description: Input 16 bits + */ + .globl in16 +in16: + lhz r3,0x0000(r3) + blr + +/* + * Function: in16r + * Description: Input 16 bits and byte reverse + */ + .globl in16r +in16r: + lhbrx r3,r0,r3 + blr + +/* + * Function: in32 + * Description: Input 32 bits + */ + .globl in32 +in32: + lwz 3,0x0000(3) + blr + +/* + * Function: in32r + * Description: Input 32 bits and byte reverse + */ + .globl in32r +in32r: + lwbrx r3,r0,r3 + blr + +/* + * Function: ppcDcbf + * Description: Data Cache block flush + * Input: r3 = effective address + * Output: none. + */ + .globl ppcDcbf +ppcDcbf: + dcbf r0,r3 + blr + +/* + * Function: ppcDcbi + * Description: Data Cache block Invalidate + * Input: r3 = effective address + * Output: none. + */ + .globl ppcDcbi +ppcDcbi: + dcbi r0,r3 + blr + +/* + * Function: ppcDcbz + * Description: Data Cache block zero. + * Input: r3 = effective address + * Output: none. + */ + .globl ppcDcbz +ppcDcbz: + dcbz r0,r3 + blr + +/* + * Function: ppcSync + * Description: Processor Synchronize + * Input: none. + * Output: none. + */ + .globl ppcSync +ppcSync: + sync + blr + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + + mr r1, r3 /* Set new stack pointer */ + mr r9, r4 /* Save copy of Global Data pointer */ + mr r29, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */ + mr r10, r5 /* Save copy of Destination Address */ + + mr r3, r5 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * + * Offset: + */ + sub r15, r10, r4 + + /* First our own GOT */ + add r14, r14, r15 + /* then the one used by the C code */ + add r30, r30, r15 + + /* + * Now relocate code + */ +#ifdef CONFIG_ECC + bl board_relocate_rom + sync + mr r3, r10 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ +#else + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + + la r8,-4(r4) + la r7,-4(r3) +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + b 4f + +2: slwi r0,r0,2 + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b +#endif +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + mtlr r0 + blr + +in_ram: +#ifdef CONFIG_ECC + bl board_init_ecc +#endif + /* + * Relocation Function, r14 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + add r0,r0,r11 + stw r0,0(r3) + bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ +2: li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + add r0,r0,r11 + stw r10,0(r3) + stw r0,0(r4) + bdnz 3b +4: +/* clear_bss: */ + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(_end) + + cmplw 0, r3, r4 + beq 6f + + li r0, 0 +5: + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 + bne 5b +6: + mr r3, r9 /* Init Date pointer */ + mr r4, r10 /* Destination Address */ + bl board_init_r + + /* not reached - end relocate_code */ +/*-----------------------------------------------------------------------*/ + + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) + + li r9, 0x100 /* reset vector always at 0x100 */ + + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ + + mflr r4 /* save link register */ +1: + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r8, Alignment - _start + EXC_OFF_SYS_RESET +2: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r8, SystemCall - _start + EXC_OFF_SYS_RESET +3: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 3b + + li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET +4: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 4b + + /* enable execptions from RAM vectors */ + mfmsr r7 + li r8,MSR_IP + andc r7,r7,r8 + mtmsr r7 + + mtlr r4 /* restore link register */ + blr + + /* + * Function: relocate entries for one exception vector + */ +trap_reloc: + lwz r0, 0(r7) /* hdlr ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 0(r7) + + lwz r0, 4(r7) /* int_return ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 4(r7) + + sync + isync + + blr + +.globl enable_ext_addr +enable_ext_addr: + mfspr r0, HID0 + lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h + ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l + mtspr HID0, r0 + sync + isync + blr + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) +.globl setup_ccsrbar +setup_ccsrbar: + /* Special sequence needed to update CCSRBAR itself */ + lis r4, CFG_CCSRBAR_DEFAULT@h + ori r4, r4, CFG_CCSRBAR_DEFAULT@l + + lis r5, CFG_CCSRBAR@h + ori r5, r5, CFG_CCSRBAR@l + srwi r6,r5,12 + stw r6, 0(r4) + isync + + lis r5, 0xffff + ori r5,r5,0xf000 + lwz r5, 0(r5) + isync + + lis r3, CFG_CCSRBAR@h + lwz r5, CFG_CCSRBAR@l(r3) + isync + + blr +#endif + +#ifdef CFG_INIT_RAM_LOCK +lock_ram_in_cache: + /* Allocate Initial RAM in data cache. + */ + lis r3, (CFG_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l + li r2, ((CFG_INIT_RAM_END & ~31) + \ + (CFG_INIT_RAM_ADDR & 31) + 31) / 32 + mtctr r2 +1: + dcbz r0, r3 + addi r3, r3, 32 + bdnz 1b +#if 1 +/* Lock the data cache */ + mfspr r0, HID0 + ori r0, r0, 0x1000 + sync + mtspr HID0, r0 + sync + blr +#endif +#if 0 + /* Lock the first way of the data cache */ + mfspr r0, LDSTCR + ori r0, r0, 0x0080 +#if defined(CONFIG_ALTIVEC) + dssall +#endif + sync + mtspr LDSTCR, r0 + sync + isync + blr +#endif + +.globl unlock_ram_in_cache +unlock_ram_in_cache: + /* invalidate the INIT_RAM section */ + lis r3, (CFG_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l + li r2, ((CFG_INIT_RAM_END & ~31) + \ + (CFG_INIT_RAM_ADDR & 31) + 31) / 32 + mtctr r2 +1: icbi r0, r3 + addi r3, r3, 32 + bdnz 1b + sync /* Wait for all icbi to complete on bus */ + isync +#if 1 +/* Unlock the data cache and invalidate it */ + mfspr r0, HID0 + li r3,0x1000 + andc r0,r0,r3 + li r3,0x0400 + or r0,r0,r3 + sync + mtspr HID0, r0 + sync + blr +#endif +#if 0 + /* Unlock the first way of the data cache */ + mfspr r0, LDSTCR + li r3,0x0080 + andc r0,r0,r3 +#ifdef CONFIG_ALTIVEC + dssall +#endif + sync + mtspr LDSTCR, r0 + sync + isync + li r3,0x0400 + or r0,r0,r3 + sync + mtspr HID0, r0 + sync + blr +#endif +#endif + +/* If this is a multi-cpu system then we need to handle the + * 2nd cpu. The assumption is that the 2nd cpu is being + * held in boot holdoff mode until the 1st cpu unlocks it + * from Linux. We'll do some basic cpu init and then pass + * it to the Linux Reset Vector. + * Sri: Much of this initialization is not required. Linux + * rewrites the bats, and the sprs and also enables the L1 cache. + */ +#if (CONFIG_NUM_CPUS > 1) +.globl secondary_cpu_setup +secondary_cpu_setup: + /* Do only core setup on all cores except cpu0 */ + bl invalidate_bats + sync + bl enable_ext_addr + +#ifdef CFG_L2 + /* init the L2 cache */ + addis r3, r0, L2_INIT@h + ori r3, r3, L2_INIT@l + sync + mtspr l2cr, r3 +#ifdef CONFIG_ALTIVEC + dssall +#endif + /* invalidate the L2 cache */ + bl l2cache_invalidate + sync +#endif + + /* enable and invalidate the data cache */ + bl dcache_enable + sync + + /* enable and invalidate the instruction cache*/ + bl icache_enable + sync + + /* TBEN in HID0 */ + mfspr r4, HID0 + oris r4, r4, 0x0400 + mtspr HID0, r4 + sync + isync + + /*SYNCBE|ABE in HID1*/ + mfspr r4, HID1 + ori r4, r4, 0x0C00 + mtspr HID1, r4 + sync + isync + + lis r3, CONFIG_LINUX_RESET_VEC@h + ori r3, r3, CONFIG_LINUX_RESET_VEC@l + mtlr r3 + blr + + /* Never Returns, Running in Linux Now */ +#endif + diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c new file mode 100644 index 0000000..8ea14e5 --- /dev/null +++ b/cpu/mpc86xx/traps.c @@ -0,0 +1,226 @@ +/* + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modified by Cort Dougan (cort@cs.nmt.edu) + * and Paul Mackerras (paulus@cs.anu.edu.au) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file handles the architecture-dependent parts of hardware exceptions + */ + +#include <common.h> +#include <command.h> +#include <asm/processor.h> + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +int (*debugger_exception_handler)(struct pt_regs *) = 0; +#endif + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) + +/* + * Trap & Exception support + */ + +void +print_backtrace(unsigned long *sp) +{ + DECLARE_GLOBAL_DATA_PTR; + + int cnt = 0; + unsigned long i; + + printf("Call backtrace: "); + while (sp) { + if ((uint) sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + printf("\n"); + printf("%08lX ", i); + if (cnt > 32) + break; + sp = (unsigned long *)*sp; + } + printf("\n"); +} + +void +show_regs(struct pt_regs *regs) +{ + int i; + + printf("NIP: %08lX XER: %08lX LR: %08lX REGS:" + " %p TRAP: %04lx DAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + printf("MSR: %08lx EE: %01x PR: %01x FP:" + " %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr & MSR_EE ? 1 : 0, + regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0, + regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0, + regs->msr & MSR_DR ? 1 : 0); + + printf("\n"); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) { + printf("GPR%02d: ", i); + } + + printf("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) { + printf("\n"); + } + } +} + + +void +_exception(int signr, struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Exception in kernel pc %lx signal %d", regs->nip, signr); +} + +void +MachineCheckException(struct pt_regs *regs) +{ + unsigned long fixup; + + /* Probing PCI using config cycles cause this exception + * when a device is not present. Catch it and return to + * the PCI exception handler. + */ + if ((fixup = search_exception_table(regs->nip)) != 0) { + regs->nip = fixup; + return; + } + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler) (regs)) + return; +#endif + + printf("Machine check in kernel mode.\n"); + printf("Caused by (from msr): "); + printf("regs %p ", regs); + switch (regs->msr & 0x000F0000) { + case (0x80000000 >> 12): + printf("Machine check signal - probably due to mm fault\n" + "with mmu off\n"); + break; + case (0x80000000 >> 13): + printf("Transfer error ack signal\n"); + break; + case (0x80000000 >> 14): + printf("Data parity signal\n"); + break; + case (0x80000000 >> 15): + printf("Address parity signal\n"); + break; + default: + printf("Unknown values in msr\n"); + } + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("machine check"); +} + +void +AlignmentException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler) (regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Alignment Exception"); +} + +void +ProgramCheckException(struct pt_regs *regs) +{ + unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL; + int i, j; + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler) (regs)) + return; +#endif + show_regs(regs); + + p = (unsigned char *)((unsigned long)p & 0xFFFFFFE0); + p -= 32; + for (i = 0; i < 256; i += 16) { + printf("%08x: ", (unsigned int)p + i); + for (j = 0; j < 16; j++) { + printf("%02x ", p[i + j]); + } + printf("\n"); + } + + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Program Check Exception"); +} + +void +SoftEmuException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler) (regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Software Emulation Exception"); +} + +void +UnknownException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler) (regs)) + return; +#endif + printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception(0, regs); +} + +/* + * Probe an address by reading. + * If not present, return -1, + * otherwise return 0. + */ +int +addr_probe(uint *addr) +{ + return 0; +} diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c index 1a7111f..c79e578 100644 --- a/cpu/mpc8xx/cpu_init.c +++ b/cpu/mpc8xx/cpu_init.c @@ -161,6 +161,7 @@ void cpu_init_f (volatile immap_t * immr) defined(CONFIG_RMU) || \ defined(CONFIG_RPXCLASSIC) || \ defined(CONFIG_RPXLITE) || \ + defined(CONFIG_SPC1920) || \ defined(CONFIG_SPD823TS) memctl->memc_br0 = CFG_BR0_PRELIM; diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c index 6006478..6d2755e 100644 --- a/cpu/mpc8xx/fec.c +++ b/cpu/mpc8xx/fec.c @@ -396,8 +396,10 @@ static void fec_pin_init(int fecidx) * * to 2.5 MHz. * * This MDC frequency is equal to system clock / (2 * MII_SPEED). * * Then MII_SPEED = system_clock / 2 * 2,5 Mhz. + * + * All MII configuration is done via FEC1 registers: */ - fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; + immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; #if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2) /* our PHYs are the limit at 2.5 MHz */ @@ -508,8 +510,6 @@ static void fec_pin_init(int fecidx) #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ #if !defined(CONFIG_RMII) - -#warning this configuration is not tested; please report if it works immr->im_cpm.cp_pepar |= 0x0003fffc; immr->im_cpm.cp_pedir |= 0x0003fffc; immr->im_cpm.cp_peso &= ~0x000087fc; @@ -822,6 +822,7 @@ static void fec_halt(struct eth_device* dev) #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ #define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */ +#define PHY_ID_KSM8995M 0x00221450 /* MICREL KS8995MA */ /* send command to phy using mii, wait for result */ static uint @@ -907,6 +908,9 @@ static int mii_discover_phy(struct eth_device *dev) case PHY_ID_DM9161: printf("Davicom DM9161\n"); break; + case PHY_ID_KSM8995M: + printf("MICREL KS8995M\n"); + break; default: printf("0x%08x\n", phytype); break; diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c index 26a82cc..8ae584f 100644 --- a/cpu/mpc8xx/serial.c +++ b/cpu/mpc8xx/serial.c @@ -227,9 +227,12 @@ static int smc_init (void) sp->smc_smcm = 0; sp->smc_smce = 0xff; - /* Set up the baud rate generator. - */ +#ifdef CFG_SPC1920_SMC1_CLK4 /* clock source is PLD */ + *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0xff; +#else + /* Set up the baud rate generator */ smc_setbrg (); +#endif /* Make the first buffer the only buffer. */ diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c index 57f91c0..101d5f9 100644 --- a/cpu/mpc8xx/speed.c +++ b/cpu/mpc8xx/speed.c @@ -259,7 +259,11 @@ int get_clocks_866 (void) */ sccr_reg = immr->im_clkrst.car_sccr; sccr_reg &= ~SCCR_EBDF11; +#if defined(CONFIG_TQM885D) + if (gd->cpu_clk <= 80000000) { +#else if (gd->cpu_clk <= 66000000) { +#endif sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */ gd->bus_clk = gd->cpu_clk; } else { @@ -360,7 +364,8 @@ static long init_pll_866 (long clk) #endif /* CONFIG_8xx_CPUCLK_DEFAULT */ -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) +#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ + && !defined(CONFIG_TQM885D) /* * Adjust sdram refresh rate to actual CPU clock * and set timebase source according to actual CPU clock @@ -384,6 +389,6 @@ int adjust_sdram_tbs_8xx (void) return (0); } -#endif /* CONFIG_TQM8xxL/M, !TQM866M */ +#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */ /* ------------------------------------------------------------------------- */ diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index fad895b..0b0686b 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -315,7 +315,6 @@ void pci_405gp_init(struct pci_controller *hose) #ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif - hose->last_busno = pci_hose_scan(hose); } #endif /* CONFIG_PCI_PNP */ @@ -438,7 +437,7 @@ void pci_440_init (struct pci_controller *hose) * The PCI initialization sequence enable bit must be set ... if not abort * pci setup since updating the bit requires chip reset. *--------------------------------------------------------------------------*/ -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long strap; mfsdr(sdr_sdstp1,strap); @@ -465,17 +464,30 @@ void pci_440_init (struct pci_controller *hose) hose->first_busno = 0; hose->last_busno = 0xff; + /* PCI I/O space */ pci_set_region(hose->regions + reg_num++, 0x00000000, PCIX0_IOBASE, 0x10000, PCI_REGION_IO); + /* PCI memory space */ pci_set_region(hose->regions + reg_num++, CFG_PCI_TARGBASE, CFG_PCI_MEMBASE, 0x10000000, PCI_REGION_MEM ); + +#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \ + defined(CONFIG_PCI_SYS_MEM_SIZE) + /* System memory space */ + pci_set_region(hose->regions + reg_num++, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + CONFIG_PCI_SYS_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY ); +#endif + hose->region_count = reg_num; pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA); @@ -502,7 +514,7 @@ void pci_440_init (struct pci_controller *hose) out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ #endif -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ #elif defined(PCIX0_BRDGOPT1) @@ -520,8 +532,13 @@ void pci_440_init (struct pci_controller *hose) out32r( PCIX0_POM0SA, 0 ); /* disable */ out32r( PCIX0_POM1SA, 0 ); /* disable */ out32r( PCIX0_POM2SA, 0 ); /* disable */ +#if defined(CONFIG_440SPE) + out32r( PCIX0_POM0LAL, 0x10000000 ); + out32r( PCIX0_POM0LAH, 0x0000000c ); +#else out32r( PCIX0_POM0LAL, 0x00000000 ); out32r( PCIX0_POM0LAH, 0x00000003 ); +#endif out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE ); out32r( PCIX0_POM0PCIAH, 0x00000000 ); out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */ @@ -545,10 +562,12 @@ void pci_440_init (struct pci_controller *hose) } } - void pci_init_board(void) { pci_440_init (&ppc440_hose); +#if defined(CONFIG_440SPE) + pcie_setup_hoses(); +#endif } #endif /* CONFIG_440 & CONFIG_PCI */ diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c new file mode 100644 index 0000000..2e920aa --- /dev/null +++ b/cpu/ppc4xx/440spe_pcie.c @@ -0,0 +1,592 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * Roland Dreier <rolandd@cisco.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm/processor.h> +#include <asm-ppc/io.h> +#include <ppc4xx.h> +#include <common.h> +#include <pci.h> + +#include "440spe_pcie.h" + +#if defined(CONFIG_440SPE) +#if defined(CONFIG_PCI) + +enum { + PTYPE_ENDPOINT = 0x0, + PTYPE_LEGACY_ENDPOINT = 0x1, + PTYPE_ROOT_PORT = 0x4, + + LNKW_X1 = 0x1, + LNKW_X4 = 0x4, + LNKW_X8 = 0x8 +}; + +static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, + int offset, int len, u32 *val) { + + *val = 0; + /* + * 440SPE implements only one function per port + */ + if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1))) + return 0; + + devfn = PCI_BDF(0,0,0); + offset += devfn << 4; + + switch (len) { + case 1: + *val = in_8(hose->cfg_data + offset); + break; + case 2: + *val = in_le16((u16 *)(hose->cfg_data + offset)); + break; + default: + *val = in_le32((u32 *)(hose->cfg_data + offset)); + break; + } + return 0; +} + +static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, + int offset, int len, u32 val) { + + /* + * 440SPE implements only one function per port + */ + if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1))) + return 0; + + devfn = PCI_BDF(0,0,0); + offset += devfn << 4; + + switch (len) { + case 1: + out_8(hose->cfg_data + offset, val); + break; + case 2: + out_le16((u16 *)(hose->cfg_data + offset), val); + break; + default: + out_le32((u32 *)(hose->cfg_data + offset), val); + break; + } + return 0; +} + +int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val) +{ + u32 v; + int rv; + + rv = pcie_read_config(hose, dev, offset, 1, &v); + *val = (u8)v; + return rv; +} + +int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val) +{ + u32 v; + int rv; + + rv = pcie_read_config(hose, dev, offset, 2, &v); + *val = (u16)v; + return rv; +} + +int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val) +{ + u32 v; + int rv; + + rv = pcie_read_config(hose, dev, offset, 3, &v); + *val = (u32)v; + return rv; +} + +int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val) +{ + return pcie_write_config(hose,(u32)dev,offset,1,val); +} + +int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val) +{ + return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val); +} + +int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val) +{ + return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val); +} + +static void ppc440spe_setup_utl(u32 port) { + + volatile void *utl_base = NULL; + + /* + * Map UTL registers + */ + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c); + mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); + mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800); + break; + + case 1: + mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c); + mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); + mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800); + break; + + case 2: + mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c); + mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001); + mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800); + break; + } + utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port); + + /* + * Set buffer allocations and then assert VRB and TXE. + */ + out_be32(utl_base + PEUTL_OUTTR, 0x08000000); + out_be32(utl_base + PEUTL_INTR, 0x02000000); + out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000); + out_be32(utl_base + PEUTL_PBBSZ, 0x53000000); + out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000); + out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000); + out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); + out_be32(utl_base + PEUTL_PCTL, 0x80800066); +} + +static int check_error(void) +{ + u32 valPE0, valPE1, valPE2; + int err = 0; + + /* SDR0_PEGPLLLCT1 reset */ + if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) { + printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0); + } + + valPE0 = SDR_READ(PESDR0_RCSSET); + valPE1 = SDR_READ(PESDR1_RCSSET); + valPE2 = SDR_READ(PESDR2_RCSSET); + + /* SDR0_PExRCSSET rstgu */ + if (!(valPE0 & 0x01000000) || + !(valPE1 & 0x01000000) || + !(valPE2 & 0x01000000)) { + printf("PCIE: SDR0_PExRCSSET rstgu error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rstdl */ + if (!(valPE0 & 0x00010000) || + !(valPE1 & 0x00010000) || + !(valPE2 & 0x00010000)) { + printf("PCIE: SDR0_PExRCSSET rstdl error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rstpyn */ + if ((valPE0 & 0x00001000) || + (valPE1 & 0x00001000) || + (valPE2 & 0x00001000)) { + printf("PCIE: SDR0_PExRCSSET rstpyn error\n"); + err = -1; + } + + /* SDR0_PExRCSSET hldplb */ + if ((valPE0 & 0x10000000) || + (valPE1 & 0x10000000) || + (valPE2 & 0x10000000)) { + printf("PCIE: SDR0_PExRCSSET hldplb error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rdy */ + if ((valPE0 & 0x00100000) || + (valPE1 & 0x00100000) || + (valPE2 & 0x00100000)) { + printf("PCIE: SDR0_PExRCSSET rdy error\n"); + err = -1; + } + + /* SDR0_PExRCSSET shutdown */ + if ((valPE0 & 0x00000100) || + (valPE1 & 0x00000100) || + (valPE2 & 0x00000100)) { + printf("PCIE: SDR0_PExRCSSET shutdown error\n"); + err = -1; + } + return err; +} + +/* + * Initialize PCI Express core + */ +int ppc440spe_init_pcie(void) +{ + int time_out = 20; + + /* Set PLL clock receiver to LVPECL */ + SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28); + + if (check_error()) + return -1; + + if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) + { + printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n", + SDR_READ(PESDR0_PLLLCT2)); + return -1; + } + /* De-assert reset of PCIe PLL, wait for lock */ + SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); + udelay(3); + + while(time_out) { + if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) { + time_out--; + udelay(1); + } else + break; + } + if (!time_out) { + printf("PCIE: VCO output not locked\n"); + return -1; + } + return 0; +} + +int ppc440spe_init_pcie_rootport(int port) +{ + static int core_init; + volatile u32 val = 0; + int attempts; + + if (!core_init) { + ++core_init; + if (ppc440spe_init_pcie()) + return -1; + } + + /* + * Initialize various parts of the PCI Express core for our port: + * + * - Set as a root port and enable max width + * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). + * - Set up UTL configuration. + * - Increase SERDES drive strength to levels suggested by AMCC. + * - De-assert RSTPYN, RSTDL and RSTGU. + * + * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with + * default setting 0x11310000. The register has new fields, + * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core + * hang. + */ + switch (port) { + case 0: + SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12); + + SDR_WRITE(PESDR0_UTLSET1, 0x21222222); + if (!ppc440spe_revB()) + SDR_WRITE(PESDR0_UTLSET2, 0x11000000); + SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); + SDR_WRITE(PESDR0_RCSSET, + (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + break; + + case 1: + SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); + SDR_WRITE(PESDR1_UTLSET1, 0x21222222); + if (!ppc440spe_revB()) + SDR_WRITE(PESDR1_UTLSET2, 0x11000000); + SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000); + SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000); + SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000); + SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000); + SDR_WRITE(PESDR1_RCSSET, + (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + break; + + case 2: + SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); + SDR_WRITE(PESDR2_UTLSET1, 0x21222222); + if (!ppc440spe_revB()) + SDR_WRITE(PESDR2_UTLSET2, 0x11000000); + SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000); + SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000); + SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000); + SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000); + SDR_WRITE(PESDR2_RCSSET, + (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + break; + } + /* + * Notice: the following delay has critical impact on device + * initialization - if too short (<50ms) the link doesn't get up. + */ + mdelay(100); + + switch (port) { + case 0: val = SDR_READ(PESDR0_RCSSTS); break; + case 1: val = SDR_READ(PESDR1_RCSSTS); break; + case 2: val = SDR_READ(PESDR2_RCSSTS); break; + } + + if (val & (1 << 20)) { + printf("PCIE%d: PGRST failed %08x\n", port, val); + return -1; + } + + /* + * Verify link is up + */ + val = 0; + switch (port) + { + case 0: + val = SDR_READ(PESDR0_LOOP); + break; + case 1: + val = SDR_READ(PESDR1_LOOP); + break; + case 2: + val = SDR_READ(PESDR2_LOOP); + break; + } + if (!(val & 0x00001000)) { + printf("PCIE%d: link is not up.\n", port); + return -1; + } + + /* + * Setup UTL registers - but only on revA! + * We use default settings for revB chip. + */ + if (!ppc440spe_revB()) + ppc440spe_setup_utl(port); + + /* + * We map PCI Express configuration access into the 512MB regions + * + * NOTICE: revB is very strict about PLB real addressess and ranges to + * be mapped for config space; it seems to only work with d_nnnn_nnnn + * range (hangs the core upon config transaction attempts when set + * otherwise) while revA uses c_nnnn_nnnn. + * + * For revA: + * PCIE0: 0xc_4000_0000 + * PCIE1: 0xc_8000_0000 + * PCIE2: 0xc_c000_0000 + * + * For revB: + * PCIE0: 0xd_0000_0000 + * PCIE1: 0xd_2000_0000 + * PCIE2: 0xd_4000_0000 + */ + + switch (port) { + case 0: + if (ppc440spe_revB()) { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000); + } else { + /* revA */ + mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000); + } + mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ + break; + + case 1: + if (ppc440spe_revB()) { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000); + } else { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000); + } + mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ + break; + + case 2: + if (ppc440spe_revB()) { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000); + } else { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000); + } + mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ + break; + } + + /* + * Check for VC0 active and assert RDY. + */ + attempts = 10; + switch (port) { + case 0: + while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE0: VC0 not active\n"); + return -1; + } + mdelay(1000); + } + SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20); + break; + case 1: + while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE1: VC0 not active\n"); + return -1; + } + mdelay(1000); + } + + SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20); + break; + case 2: + while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE2: VC0 not active\n"); + return -1; + } + mdelay(1000); + } + + SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20); + break; + } + mdelay(100); + + return 0; +} + +void ppc440spe_setup_pcie(struct pci_controller *hose, int port) +{ + volatile void *mbase = NULL; + + pci_set_ops(hose, + pcie_read_config_byte, + pcie_read_config_word, + pcie_read_config_dword, + pcie_write_config_byte, + pcie_write_config_word, + pcie_write_config_dword); + + switch(port) { + case 0: + mbase = (u32 *)CFG_PCIE0_XCFGBASE; + hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE; + break; + case 1: + mbase = (u32 *)CFG_PCIE1_XCFGBASE; + hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; + break; + case 2: + mbase = (u32 *)CFG_PCIE2_XCFGBASE; + hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; + break; + } + + /* + * Set bus numbers on our root port + */ + if (ppc440spe_revB()) { + out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); + out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); + out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); + } else { + out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); + out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0); + } + + /* + * Set up outbound translation to hose->mem_space from PLB + * addresses at an offset of 0xd_0000_0000. We set the low + * bits of the mask to 11 to turn off splitting into 8 + * subregions and to enable the outbound translation. + */ + out_le32(mbase + PECFG_POM0LAH, 0x00000000); + out_le32(mbase + PECFG_POM0LAL, (CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE)); + + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), + ~(CFG_PCIE_MEMSIZE - 1) | 3); + break; + case 1: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE)); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), + ~(CFG_PCIE_MEMSIZE - 1) | 3); + break; + case 2: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE)); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), + ~(CFG_PCIE_MEMSIZE - 1) | 3); + break; + } + + /* Set up 16GB inbound memory window at 0 */ + out_le32(mbase + PCI_BASE_ADDRESS_0, 0); + out_le32(mbase + PCI_BASE_ADDRESS_1, 0); + out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); + out_le32(mbase + PECFG_BAR0LMPA, 0); + out_le32(mbase + PECFG_PIM0LAL, 0); + out_le32(mbase + PECFG_PIM0LAH, 0); + out_le32(mbase + PECFG_PIMEN, 0x1); + + /* Enable I/O, Mem, and Busmaster cycles */ + out_le16((u16 *)(mbase + PCI_COMMAND), + in_le16((u16 *)(mbase + PCI_COMMAND)) | + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); +} +#endif /* CONFIG_PCI */ +#endif /* CONFIG_440SPE */ diff --git a/cpu/ppc4xx/440spe_pcie.h b/cpu/ppc4xx/440spe_pcie.h new file mode 100644 index 0000000..47df762 --- /dev/null +++ b/cpu/ppc4xx/440spe_pcie.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * Roland Dreier <rolandd@cisco.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <ppc4xx.h> +#ifndef __440SPE_PCIE_H +#define __440SPE_PCIE_H + +#define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);}) + +#define DCRN_SDR0_CFGADDR 0x00e +#define DCRN_SDR0_CFGDATA 0x00f + +#define DCRN_PCIE0_BASE 0x100 +#define DCRN_PCIE1_BASE 0x120 +#define DCRN_PCIE2_BASE 0x140 +#define PCIE0 DCRN_PCIE0_BASE +#define PCIE1 DCRN_PCIE1_BASE +#define PCIE2 DCRN_PCIE2_BASE + +#define DCRN_PEGPL_CFGBAH(base) (base + 0x00) +#define DCRN_PEGPL_CFGBAL(base) (base + 0x01) +#define DCRN_PEGPL_CFGMSK(base) (base + 0x02) +#define DCRN_PEGPL_MSGBAH(base) (base + 0x03) +#define DCRN_PEGPL_MSGBAL(base) (base + 0x04) +#define DCRN_PEGPL_MSGMSK(base) (base + 0x05) +#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06) +#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07) +#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08) +#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09) +#define DCRN_PEGPL_REGBAH(base) (base + 0x12) +#define DCRN_PEGPL_REGBAL(base) (base + 0x13) +#define DCRN_PEGPL_REGMSK(base) (base + 0x14) +#define DCRN_PEGPL_SPECIAL(base) (base + 0x15) + +/* + * System DCRs (SDRs) + */ +#define PESDR0_PLLLCT1 0x03a0 +#define PESDR0_PLLLCT2 0x03a1 +#define PESDR0_PLLLCT3 0x03a2 + +#define PESDR0_UTLSET1 0x0300 +#define PESDR0_UTLSET2 0x0301 +#define PESDR0_DLPSET 0x0302 +#define PESDR0_LOOP 0x0303 +#define PESDR0_RCSSET 0x0304 +#define PESDR0_RCSSTS 0x0305 +#define PESDR0_HSSL0SET1 0x0306 +#define PESDR0_HSSL0SET2 0x0307 +#define PESDR0_HSSL0STS 0x0308 +#define PESDR0_HSSL1SET1 0x0309 +#define PESDR0_HSSL1SET2 0x030a +#define PESDR0_HSSL1STS 0x030b +#define PESDR0_HSSL2SET1 0x030c +#define PESDR0_HSSL2SET2 0x030d +#define PESDR0_HSSL2STS 0x030e +#define PESDR0_HSSL3SET1 0x030f +#define PESDR0_HSSL3SET2 0x0310 +#define PESDR0_HSSL3STS 0x0311 +#define PESDR0_HSSL4SET1 0x0312 +#define PESDR0_HSSL4SET2 0x0313 +#define PESDR0_HSSL4STS 0x0314 +#define PESDR0_HSSL5SET1 0x0315 +#define PESDR0_HSSL5SET2 0x0316 +#define PESDR0_HSSL5STS 0x0317 +#define PESDR0_HSSL6SET1 0x0318 +#define PESDR0_HSSL6SET2 0x0319 +#define PESDR0_HSSL6STS 0x031a +#define PESDR0_HSSL7SET1 0x031b +#define PESDR0_HSSL7SET2 0x031c +#define PESDR0_HSSL7STS 0x031d +#define PESDR0_HSSCTLSET 0x031e +#define PESDR0_LANE_ABCD 0x031f +#define PESDR0_LANE_EFGH 0x0320 + +#define PESDR1_UTLSET1 0x0340 +#define PESDR1_UTLSET2 0x0341 +#define PESDR1_DLPSET 0x0342 +#define PESDR1_LOOP 0x0343 +#define PESDR1_RCSSET 0x0344 +#define PESDR1_RCSSTS 0x0345 +#define PESDR1_HSSL0SET1 0x0346 +#define PESDR1_HSSL0SET2 0x0347 +#define PESDR1_HSSL0STS 0x0348 +#define PESDR1_HSSL1SET1 0x0349 +#define PESDR1_HSSL1SET2 0x034a +#define PESDR1_HSSL1STS 0x034b +#define PESDR1_HSSL2SET1 0x034c +#define PESDR1_HSSL2SET2 0x034d +#define PESDR1_HSSL2STS 0x034e +#define PESDR1_HSSL3SET1 0x034f +#define PESDR1_HSSL3SET2 0x0350 +#define PESDR1_HSSL3STS 0x0351 +#define PESDR1_HSSCTLSET 0x0352 +#define PESDR1_LANE_ABCD 0x0353 + +#define PESDR2_UTLSET1 0x0370 +#define PESDR2_UTLSET2 0x0371 +#define PESDR2_DLPSET 0x0372 +#define PESDR2_LOOP 0x0373 +#define PESDR2_RCSSET 0x0374 +#define PESDR2_RCSSTS 0x0375 +#define PESDR2_HSSL0SET1 0x0376 +#define PESDR2_HSSL0SET2 0x0377 +#define PESDR2_HSSL0STS 0x0378 +#define PESDR2_HSSL1SET1 0x0379 +#define PESDR2_HSSL1SET2 0x037a +#define PESDR2_HSSL1STS 0x037b +#define PESDR2_HSSL2SET1 0x037c +#define PESDR2_HSSL2SET2 0x037d +#define PESDR2_HSSL2STS 0x037e +#define PESDR2_HSSL3SET1 0x037f +#define PESDR2_HSSL3SET2 0x0380 +#define PESDR2_HSSL3STS 0x0381 +#define PESDR2_HSSCTLSET 0x0382 +#define PESDR2_LANE_ABCD 0x0383 + +/* + * UTL register offsets + */ +#define PEUTL_PBBSZ 0x20 +#define PEUTL_OPDBSZ 0x68 +#define PEUTL_IPHBSZ 0x70 +#define PEUTL_IPDBSZ 0x78 +#define PEUTL_OUTTR 0x90 +#define PEUTL_INTR 0x98 +#define PEUTL_PCTL 0xa0 +#define PEUTL_RCIRQEN 0xb8 + +/* + * Config space register offsets + */ +#define PECFG_BAR0LMPA 0x210 +#define PECFG_BAR0HMPA 0x214 +#define PECFG_PIMEN 0x33c +#define PECFG_PIM0LAL 0x340 +#define PECFG_PIM0LAH 0x344 +#define PECFG_POM0LAL 0x380 +#define PECFG_POM0LAH 0x384 + +#define SDR_READ(offset) ({\ + mtdcr(DCRN_SDR0_CFGADDR, offset); \ + mfdcr(DCRN_SDR0_CFGDATA);}) + +#define SDR_WRITE(offset, data) ({\ + mtdcr(DCRN_SDR0_CFGADDR, offset); \ + mtdcr(DCRN_SDR0_CFGDATA,data);}) + +int ppc440spe_init_pcie(void); +int ppc440spe_init_pcie_rootport(int port); +void yucca_setup_pcie_fpga_rootpoint(int port); +void ppc440spe_setup_pcie(struct pci_controller *hose, int port); +int yucca_pcie_card_present(int port); +int pcie_hose_scan(struct pci_controller *hose, int bus); +#endif /* __440SPE_PCIE_H */ diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 86dc2d0..fab65af 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -181,6 +181,9 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) { EMAC_4XX_HW_PST hw_p = dev->priv; uint32_t failsafe = 10000; +#if defined(CONFIG_440SPE) + unsigned long mfr; +#endif out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ @@ -202,8 +205,23 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) } /* EMAC RESET */ +#if defined(CONFIG_440SPE) + /* provide clocks for EMAC internal loopback */ + mfsdr (sdr_mfr, mfr); + mfr |= 0x08000000; + mtsdr(sdr_mfr, mfr); +#endif + out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); +#if defined(CONFIG_440SPE) + /* remove clocks for EMAC internal loopback */ + mfsdr (sdr_mfr, mfr); + mfr &= ~0x08000000; + mtsdr(sdr_mfr, mfr); +#endif + + #ifndef CONFIG_NETCONSOLE hw_p->print_speed = 1; /* print speed message again next time */ #endif @@ -301,7 +319,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) return ((int)pfc1); } -#endif +#endif /* CONFIG_440_GX */ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) { @@ -314,12 +332,16 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) unsigned mode_reg; unsigned short devnum; unsigned short reg_short; -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) sys_info_t sysinfo; -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) int ethgroup = -1; #endif #endif +#if defined(CONFIG_440SPE) + unsigned long mfr; +#endif + EMAC_4XX_HW_PST hw_p = dev->priv; @@ -330,7 +352,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) return -1; } -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* Need to get the OPB frequency so we can access the PHY */ get_sys_info (&sysinfo); #endif @@ -360,6 +382,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) hw_p->stats.pkts_tx = 0; hw_p->stats.pkts_rx = 0; hw_p->stats.pkts_handled = 0; + hw_p->print_speed = 1; /* print speed message again next time */ #endif hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */ @@ -373,7 +396,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */ hw_p->tx_u_index = 0; /* Transmit User Queue Index */ -#if defined(CONFIG_440) && !defined(CONFIG_440SP) +#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) /* set RMII mode */ /* NOTE: 440GX spec states that mode is mutually exclusive */ /* NOTE: Therefore, disable all other EMACS, since we handle */ @@ -406,6 +429,12 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) __asm__ volatile ("eieio"); /* reset emac so we have access to the phy */ +#if defined(CONFIG_440SPE) + /* provide clocks for EMAC internal loopback */ + mfsdr (sdr_mfr, mfr); + mfr |= 0x08000000; + mtsdr(sdr_mfr, mfr); +#endif out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); __asm__ volatile ("eieio"); @@ -416,7 +445,14 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) failsafe--; } -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_440SPE) + /* remove clocks for EMAC internal loopback */ + mfsdr (sdr_mfr, mfr); + mfr &= ~0x08000000; + mtsdr(sdr_mfr, mfr); +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* Whack the M1 register */ mode_reg = 0x0; mode_reg &= ~0x00000038; @@ -468,7 +504,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) if (hw_p->first_init == 0) { miiphy_reset (dev->name, reg); -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) #if defined(CONFIG_CIS8201_PHY) /* * Cicada 8201 PHY needs to have an extended register whacked @@ -544,7 +580,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) (int) speed, (duplex == HALF) ? "HALF" : "FULL"); } -#if defined(CONFIG_440) && !defined(CONFIG_440SP) +#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) mfsdr(sdr_mfr, reg); if (speed == 100) { @@ -575,7 +611,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ /* set the Mal configuration reg */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); #else @@ -759,8 +795,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* set speed */ if (speed == _1000BASET) { -#if defined(CONFIG_440SP) -#define SDR0_PFC1_EM_1000 0x00200000 +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long pfc1; mfsdr (sdr_pfc1, pfc1); pfc1 |= SDR0_PFC1_EM_1000; @@ -787,7 +822,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* set receive low/high water mark register */ #if defined(CONFIG_440) - /* 440GP has a 64 byte burst length */ + /* 440s has a 64 byte burst length */ out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); #else /* 405s have a 16 byte burst length */ @@ -895,7 +930,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, #if defined (CONFIG_440) -#if defined(CONFIG_440SP) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* * Hack: On 440SP all enet irq sources are located on UIC1 * Needs some cleanup. --sr @@ -1367,21 +1402,20 @@ int ppc_4xx_eth_initialize (bd_t * bis) #endif /* set phy num and mode */ bis->bi_phynum[0] = CONFIG_PHY_ADDR; + bis->bi_phymode[0] = 0; + #if defined(CONFIG_PHY1_ADDR) bis->bi_phynum[1] = CONFIG_PHY1_ADDR; + bis->bi_phymode[1] = 0; #endif #if defined(CONFIG_440GX) bis->bi_phynum[2] = CONFIG_PHY2_ADDR; bis->bi_phynum[3] = CONFIG_PHY3_ADDR; - bis->bi_phymode[0] = 0; - bis->bi_phymode[1] = 0; bis->bi_phymode[2] = 2; bis->bi_phymode[3] = 2; -#if defined (CONFIG_440GX) ppc_4xx_eth_setup_bridge(0, bis); #endif -#endif for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { @@ -1478,9 +1512,15 @@ int ppc_4xx_eth_initialize (bd_t * bis) if (0 == virgin) { /* set the MAL IER ??? names may change with new spec ??? */ +#if defined(CONFIG_440SPE) + mal_ier = + MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE | + MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ; +#else mal_ier = MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | MAL_IER_OPBE | MAL_IER_PLBE; +#endif mtdcr (malesr, 0xffffffff); /* clear pending interrupts */ mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */ mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */ @@ -1510,11 +1550,13 @@ int ppc_4xx_eth_initialize (bd_t * bis) #else emac0_dev = dev; #endif + +#if defined(CONFIG_NET_MULTI) #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) miiphy_register (dev->name, emac4xx_miiphy_read, emac4xx_miiphy_write); #endif - +#endif } /* end for each supported device */ return (1); } diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index c563457..7d6990f 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -31,7 +31,8 @@ COBJS = 405gp_pci.o 4xx_enet.o \ bedbug_405.o commproc.o \ cpu.o cpu_init.o i2c.o interrupts.o \ miiphy.o sdram.o serial.o \ - spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o + spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o \ + 440spe_pcie.o OBJS = $(AOBJS) $(COBJS) diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index d9b5d32..bc51fbf 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -82,7 +82,9 @@ int pci_arbiter_enabled(void) return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK); #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) unsigned long val; mfsdr(sdr_sdstp1, val); @@ -91,8 +93,8 @@ int pci_arbiter_enabled(void) } #endif -#if defined(CONFIG_405EP)|| defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define I2C_BOOTROM @@ -102,7 +104,9 @@ int i2c_bootrom_enabled(void) return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP); #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) unsigned long val; mfsdr(sdr_sdcs, val); @@ -248,6 +252,14 @@ int checkcpu (void) puts("SP Rev. B"); break; + case PVR_440SPe_RA: + puts("SPe Rev. A"); + break; + + case PVR_440SPe_RB: + puts("SPe Rev. B"); + break; + default: printf (" UNKNOWN (PVR=%08x)", pvr); break; @@ -303,6 +315,17 @@ int checkcpu (void) return 0; } +#if defined (CONFIG_440SPE) +int ppc440spe_revB() { + unsigned int pvr; + + pvr = get_pvr(); + if (pvr == PVR_440SPe_RB) + return 1; + else + return 0; +} +#endif /* ------------------------------------------------------------------------- */ diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index 3aae4ce..886f405 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -50,18 +50,22 @@ struct irq_action { }; static struct irq_action irq_vecs[32]; +void uic0_interrupt( void * parms); /* UIC0 handler */ #if defined(CONFIG_440) static struct irq_action irq_vecs1[32]; /* For UIC1 */ void uic1_interrupt( void * parms); /* UIC1 handler */ -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) static struct irq_action irq_vecs2[32]; /* For UIC2 */ - -void uic0_interrupt( void * parms); /* UIC0 handler */ void uic2_interrupt( void * parms); /* UIC2 handler */ -#endif /* CONFIG_440GX */ +#endif /* CONFIG_440GX CONFIG_440SPE */ + +#if defined(CONFIG_440SPE) +static struct irq_action irq_vecs3[32]; /* For UIC3 */ +void uic3_interrupt( void * parms); /* UIC3 handler */ +#endif /* CONFIG_440SPE */ #endif /* CONFIG_440 */ @@ -115,11 +119,16 @@ int interrupt_init_cpu (unsigned *decrementer_count) irq_vecs1[vec].handler = NULL; irq_vecs1[vec].arg = NULL; irq_vecs1[vec].count = 0; -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) irq_vecs2[vec].handler = NULL; irq_vecs2[vec].arg = NULL; irq_vecs2[vec].count = 0; #endif /* CONFIG_440GX */ +#if defined(CONFIG_440SPE) + irq_vecs3[vec].handler = NULL; + irq_vecs3[vec].arg = NULL; + irq_vecs3[vec].count = 0; +#endif /* CONFIG_440SPE */ #endif } @@ -221,6 +230,34 @@ void external_interrupt(struct pt_regs *regs) } /* external_interrupt CONFIG_440GX */ +#elif defined(CONFIG_440SPE) +void external_interrupt(struct pt_regs *regs) +{ + ulong uic_msr; + + /* + * Read masked interrupt status register to determine interrupt source + */ + /* 440 SPe uses base uic register */ + uic_msr = mfdcr(uic0msr); + + if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) ) + uic1_interrupt(0); + + if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) ) + uic2_interrupt(0); + + if ( (UICB0_UIC3CI & uic_msr) || (UICB0_UIC3NCI & uic_msr) ) + uic3_interrupt(0); + + if (uic_msr & ~(UICB0_ALL)) + uic0_interrupt(0); + + mtdcr(uic0sr, uic_msr); + + return; +} /* external_interrupt CONFIG_440SPE */ + #else void external_interrupt(struct pt_regs *regs) @@ -266,7 +303,7 @@ void external_interrupt(struct pt_regs *regs) } #endif -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) /* Handler for UIC0 interrupt */ void uic0_interrupt( void * parms) { @@ -357,8 +394,8 @@ void uic1_interrupt( void * parms) } #endif /* defined(CONFIG_440) */ -#if defined(CONFIG_440GX) -/* Handler for UIC1 interrupt */ +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +/* Handler for UIC2 interrupt */ void uic2_interrupt( void * parms) { ulong uic2_msr; @@ -384,7 +421,7 @@ void uic2_interrupt( void * parms) (*irq_vecs2[vec].handler)(irq_vecs2[vec].arg); } else { mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> vec)); - printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec); + printf ("Masking bogus interrupt vector (uic2) 0x%x\n", vec); } /* @@ -402,6 +439,51 @@ void uic2_interrupt( void * parms) } #endif /* defined(CONFIG_440GX) */ +#if defined(CONFIG_440SPE) +/* Handler for UIC3 interrupt */ +void uic3_interrupt( void * parms) +{ + ulong uic3_msr; + ulong msr_shift; + int vec; + + /* + * Read masked interrupt status register to determine interrupt source + */ + uic3_msr = mfdcr(uic3msr); + msr_shift = uic3_msr; + vec = 0; + + while (msr_shift != 0) { + if (msr_shift & 0x80000000) { + /* + * Increment irq counter (for debug purpose only) + */ + irq_vecs3[vec].count++; + + if (irq_vecs3[vec].handler != NULL) { + /* call isr */ + (*irq_vecs3[vec].handler)(irq_vecs3[vec].arg); + } else { + mtdcr(uic3er, mfdcr(uic3er) & ~(0x80000000 >> vec)); + printf ("Masking bogus interrupt vector (uic3) 0x%x\n", vec); + } + + /* + * After servicing the interrupt, we have to remove the status indicator. + */ + mtdcr(uic3sr, (0x80000000 >> vec)); + } + + /* + * Shift msr to next position and increment vector + */ + msr_shift <<= 1; + vec++; + } +} +#endif /* defined(CONFIG_440SPE) */ + /****************************************************************************/ /* @@ -414,7 +496,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) int i = vec; #if defined(CONFIG_440) -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) if ((vec > 31) && (vec < 64)) { i = vec - 32; irqa = irq_vecs1; @@ -441,7 +523,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) irqa[i].arg = arg; #if defined(CONFIG_440) -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) if ((vec > 31) && (vec < 64)) mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i)); else if (vec > 63) @@ -464,7 +546,7 @@ void irq_free_handler (int vec) int i = vec; #if defined(CONFIG_440) -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) if ((vec > 31) && (vec < 64)) { irqa = irq_vecs1; i = vec - 32; @@ -485,7 +567,7 @@ void irq_free_handler (int vec) #endif #if defined(CONFIG_440) -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) if ((vec > 31) && (vec < 64)) mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i)); else if (vec > 63) @@ -553,7 +635,7 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf("\n"); #endif -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) printf ("\nUIC 2\n"); printf ("Nr Routine Arg Count\n"); @@ -566,6 +648,19 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf("\n"); #endif +#if defined(CONFIG_440SPE) + printf ("\nUIC 3\n"); + printf ("Nr Routine Arg Count\n"); + + for (vec=0; vec<32; vec++) { + if (irq_vecs3[vec].handler != NULL) + printf ("%02d %08lx %08lx %d\n", + vec+63, (ulong)irq_vecs3[vec].handler, + (ulong)irq_vecs3[vec].arg, irq_vecs3[vec].count); + } + printf("\n"); +#endif + return 0; } #endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index f26f2a2..aa580ed 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -50,7 +50,7 @@ #include <405_mal.h> #include <miiphy.h> - +#undef ET_DEBUG /***********************************************************/ /* Dump out to the screen PHY regs */ /***********************************************************/ @@ -90,6 +90,10 @@ int phy_setup_aneg (char *devname, unsigned char addr) PHY_ANLPAR_10); miiphy_write (devname, addr, PHY_ANAR, adv); + miiphy_read (devname, addr, PHY_1000BTCR, &adv); + adv |= (0x0300); + miiphy_write (devname, addr, PHY_1000BTCR, adv); + /* Start/Restart aneg */ miiphy_read (devname, addr, PHY_BMCR, &ctl); ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); @@ -104,7 +108,7 @@ int phy_setup_aneg (char *devname, unsigned char addr) /***********************************************************/ unsigned int miiphy_getemac_offset (void) { -#if (defined(CONFIG_440) && !defined(CONFIG_440SP)) && defined(CONFIG_NET_MULTI) +#if (defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)) && defined(CONFIG_NET_MULTI) unsigned long zmii; unsigned long eoffset; @@ -155,10 +159,12 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, i = 0; /* see if it is ready for sec */ - while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) { + while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { udelay (7); if (i > 5) { -#if 0 +#ifdef ET_DEBUG + sta_reg = in32 (EMAC_STACR + emac_reg); + printf ("read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ printf ("read err 1\n"); #endif return -1; @@ -167,31 +173,41 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, } sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ -#if defined(CONFIG_440GX) - sta_reg |= EMAC_STACR_READ; +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ + sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ; +#else + sta_reg |= EMAC_STACR_READ; +#endif #else sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ; #endif -#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) +#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE) sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; #endif sta_reg = sta_reg | (addr << 5); /* Phy address */ - + sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ out32 (EMAC_STACR + emac_reg, sta_reg); -#if 0 /* test-only */ +#ifdef ET_DEBUG printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif sta_reg = in32 (EMAC_STACR + emac_reg); +#ifdef ET_DEBUG + printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ +#endif i = 0; - while ((sta_reg & EMAC_STACR_OC) == 0) { + while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { udelay (7); if (i > 5) { return -1; } i++; sta_reg = in32 (EMAC_STACR + emac_reg); +#ifdef ET_DEBUG + printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ +#endif } if ((sta_reg & EMAC_STACR_PHYE) != 0) { return -1; @@ -219,7 +235,7 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, /* see if it is ready for 1000 nsec */ i = 0; - while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) { + while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { if (i > 5) return -1; udelay (7); @@ -228,16 +244,21 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, sta_reg = 0; sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ -#if defined(CONFIG_440GX) - sta_reg |= EMAC_STACR_WRITE; +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ + sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE; +#else + sta_reg |= EMAC_STACR_WRITE; +#endif #else sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ; #endif -#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) +#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE) sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */ #endif - sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */ + sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */ + sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ memcpy (&sta_reg, &value, 2); /* put in data */ out32 (EMAC_STACR + emac_reg, sta_reg); @@ -245,12 +266,18 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, /* wait for completion */ i = 0; sta_reg = in32 (EMAC_STACR + emac_reg); - while ((sta_reg & EMAC_STACR_OC) == 0) { +#ifdef ET_DEBUG + printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ +#endif + while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { udelay (7); if (i > 5) return -1; i++; sta_reg = in32 (EMAC_STACR + emac_reg); +#ifdef ET_DEBUG + printf ("a32: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ +#endif } if ((sta_reg & EMAC_STACR_PHYE) != 0) diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index e31d59d..faeea5c 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -379,7 +379,7 @@ long int initdram(int board_type) /* * Enable the controller, then wait for DCEN to complete */ - mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + mtsdram(mem_cfg0, 0x82000000); /* DCEN=1, PMUD=0, 64-bit */ udelay(10000); if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) { diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index 83c9479..ad3ca6e 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -275,11 +275,11 @@ int serial_tstc () #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300 #endif -#if defined(CONFIG_440SP) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600 #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define CR0_MASK 0xdfffffff #define CR0_EXTCLK_ENA 0x00800000 #define CR0_UDIV_POS 0 @@ -309,14 +309,18 @@ int serial_tstc () #if defined(CONFIG_UART1_CONSOLE) #define ACTING_UART0_BASE UART1_BASE #define ACTING_UART1_BASE UART0_BASE -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) #define UART0_SDR sdr_uart1 #define UART1_SDR sdr_uart0 #endif /* CONFIG_440GX */ #else #define ACTING_UART0_BASE UART0_BASE #define ACTING_UART1_BASE UART1_BASE -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) #define UART0_SDR sdr_uart0 #define UART1_SDR sdr_uart1 #endif /* CONFIG_440GX */ @@ -437,7 +441,8 @@ int serial_init(void) unsigned long tmp; #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) #if defined(CONFIG_SERIAL_MULTI) if (UART0_BASE == dev_base) { mfsdr(UART0_SDR,reg); @@ -466,7 +471,9 @@ int serial_init(void) serial_divs (gd->baudrate, &udiv, &bdiv); #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */ #if defined(CONFIG_SERIAL_MULTI) if (UART0_BASE == dev_base) { @@ -607,8 +614,28 @@ void serial_setbrg (void) #else udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1; #endif /* CONFIG_405EP */ + +#if !defined(CFG_EXT_SERIAL_CLOCK) && \ + ( defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) ) + serial_divs (gd->baudrate, &udiv, &bdiv); + tmp = udiv << CR0_UDIV_POS; /* set the UART divisor */ +#if defined(CONFIG_SERIAL_MULTI) + if (UART0_BASE == dev_base) { + mtsdr (UART0_SDR, tmp); + } else { + mtsdr (UART1_SDR, tmp); + } +#else + mtsdr (UART0_SDR, tmp); +#endif + +#else + tmp = gd->baudrate * udiv * 16; bdiv = (clk + tmp / 2) / tmp; +#endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */ #if defined(CONFIG_SERIAL_MULTI) out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */ diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c index c0a6933..c24456b 100644 --- a/cpu/ppc4xx/spd_sdram.c +++ b/cpu/ppc4xx/spd_sdram.c @@ -1007,9 +1007,9 @@ void program_cfg0(unsigned long* dimm_populated, } /* - * program Page Management Unit + * program Page Management Unit (0 == enabled) */ - cfg0 |= SDRAM_CFG0_PMUD; + cfg0 &= ~SDRAM_CFG0_PMUD; /* * program Memory Controller Options 0 diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 02b4383..e552c03 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -29,7 +29,11 @@ DECLARE_GLOBAL_DATA_PTR; #define ONE_BILLION 1000000000 - +#ifdef DEBUG +#define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif #if defined(CONFIG_405GP) || defined(CONFIG_405CR) @@ -283,7 +287,7 @@ ulong get_PCI_freq (void) return sys_info.freqPCI; } -#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) +#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) void get_sys_info (sys_info_t * sysInfo) { unsigned long strp0; @@ -326,6 +330,26 @@ void get_sys_info (sys_info_t * sysInfo) unsigned long m; unsigned long prbdv0; +#if defined(CONFIG_440SPE) + unsigned long sys_freq; + unsigned long sys_per=0; + unsigned long msr; + unsigned long pci_clock_per; + unsigned long sdr_ddrpll; + + /*-------------------------------------------------------------------------+ + | Get the system clock period. + +-------------------------------------------------------------------------*/ + sys_per = determine_sysper(); + + msr = (mfmsr () & ~(MSR_EE)); /* disable interrupts */ + + /*-------------------------------------------------------------------------+ + | Calculate the system clock speed from the period. + +-------------------------------------------------------------------------*/ + sys_freq=(ONE_BILLION/sys_per)*1000; +#endif + /* Extract configured divisors */ mfsdr( sdr_sdstp0,strp0 ); mfsdr( sdr_sdstp1,strp1 ); @@ -360,12 +384,238 @@ void get_sys_info (sys_info_t * sysInfo) m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB; /* Now calculate the individual clocks */ +#if defined(CONFIG_440SPE) + sysInfo->freqVCOMhz = (m * sys_freq) ; +#else sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1); +#endif sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA; sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0; sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv; +#if defined(CONFIG_440SPE) + /* Determine PCI Clock Period */ + pci_clock_per = determine_pci_clock_per(); + sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000; + mfsdr(sdr_ddr0, sdr_ddrpll); + sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll)); +#endif + + +} + +#endif + +#if defined(CONFIG_440SPE) +unsigned long determine_sysper(void) +{ + unsigned int fpga_clocking_reg; + unsigned int master_clock_selection; + unsigned long master_clock_per = 0; + unsigned long fb_div_selection; + unsigned int vco_div_reg_value; + unsigned long vco_div_selection; + unsigned long sys_per = 0; + int extClkVal; + + /*-------------------------------------------------------------------------+ + | Read FPGA reg 0 and reg 1 to get FPGA reg information + +-------------------------------------------------------------------------*/ + fpga_clocking_reg = in16(FPGA_REG16); + + + /* Determine Master Clock Source Selection */ + master_clock_selection = fpga_clocking_reg & FPGA_REG16_MASTER_CLK_MASK; + + switch(master_clock_selection) { + case FPGA_REG16_MASTER_CLK_66_66: + master_clock_per = PERIOD_66_66MHZ; + break; + case FPGA_REG16_MASTER_CLK_50: + master_clock_per = PERIOD_50_00MHZ; + break; + case FPGA_REG16_MASTER_CLK_33_33: + master_clock_per = PERIOD_33_33MHZ; + break; + case FPGA_REG16_MASTER_CLK_25: + master_clock_per = PERIOD_25_00MHZ; + break; + case FPGA_REG16_MASTER_CLK_EXT: + if ((extClkVal==EXTCLK_33_33) + && (extClkVal==EXTCLK_50) + && (extClkVal==EXTCLK_66_66) + && (extClkVal==EXTCLK_83)) { + /* calculate master clock period from external clock value */ + master_clock_per=(ONE_BILLION/extClkVal) * 1000; + } else { + /* Unsupported */ + DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__); + hang(); + } + break; + default: + /* Unsupported */ + DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__); + hang(); + break; + } + + /* Determine FB divisors values */ + if ((fpga_clocking_reg & FPGA_REG16_FB1_DIV_MASK) == FPGA_REG16_FB1_DIV_LOW) { + if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW) + fb_div_selection = FPGA_FB_DIV_6; + else + fb_div_selection = FPGA_FB_DIV_12; + } else { + if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW) + fb_div_selection = FPGA_FB_DIV_10; + else + fb_div_selection = FPGA_FB_DIV_20; + } + + /* Determine VCO divisors values */ + vco_div_reg_value = fpga_clocking_reg & FPGA_REG16_VCO_DIV_MASK; + + switch(vco_div_reg_value) { + case FPGA_REG16_VCO_DIV_4: + vco_div_selection = FPGA_VCO_DIV_4; + break; + case FPGA_REG16_VCO_DIV_6: + vco_div_selection = FPGA_VCO_DIV_6; + break; + case FPGA_REG16_VCO_DIV_8: + vco_div_selection = FPGA_VCO_DIV_8; + break; + case FPGA_REG16_VCO_DIV_10: + default: + vco_div_selection = FPGA_VCO_DIV_10; + break; + } + + if (master_clock_selection == FPGA_REG16_MASTER_CLK_EXT) { + switch(master_clock_per) { + case PERIOD_25_00MHZ: + if (fb_div_selection == FPGA_FB_DIV_12) { + if (vco_div_selection == FPGA_VCO_DIV_4) + sys_per = PERIOD_75_00MHZ; + if (vco_div_selection == FPGA_VCO_DIV_6) + sys_per = PERIOD_50_00MHZ; + } + break; + case PERIOD_33_33MHZ: + if (fb_div_selection == FPGA_FB_DIV_6) { + if (vco_div_selection == FPGA_VCO_DIV_4) + sys_per = PERIOD_50_00MHZ; + if (vco_div_selection == FPGA_VCO_DIV_6) + sys_per = PERIOD_33_33MHZ; + } + if (fb_div_selection == FPGA_FB_DIV_10) { + if (vco_div_selection == FPGA_VCO_DIV_4) + sys_per = PERIOD_83_33MHZ; + if (vco_div_selection == FPGA_VCO_DIV_10) + sys_per = PERIOD_33_33MHZ; + } + if (fb_div_selection == FPGA_FB_DIV_12) { + if (vco_div_selection == FPGA_VCO_DIV_4) + sys_per = PERIOD_100_00MHZ; + if (vco_div_selection == FPGA_VCO_DIV_6) + sys_per = PERIOD_66_66MHZ; + if (vco_div_selection == FPGA_VCO_DIV_8) + sys_per = PERIOD_50_00MHZ; + } + break; + case PERIOD_50_00MHZ: + if (fb_div_selection == FPGA_FB_DIV_6) { + if (vco_div_selection == FPGA_VCO_DIV_4) + sys_per = PERIOD_75_00MHZ; + if (vco_div_selection == FPGA_VCO_DIV_6) + sys_per = PERIOD_50_00MHZ; + } + if (fb_div_selection == FPGA_FB_DIV_10) { + if (vco_div_selection == FPGA_VCO_DIV_6) + sys_per = PERIOD_83_33MHZ; + if (vco_div_selection == FPGA_VCO_DIV_10) + sys_per = PERIOD_50_00MHZ; + } + if (fb_div_selection == FPGA_FB_DIV_12) { + if (vco_div_selection == FPGA_VCO_DIV_6) + sys_per = PERIOD_100_00MHZ; + if (vco_div_selection == FPGA_VCO_DIV_8) + sys_per = PERIOD_75_00MHZ; + } + break; + case PERIOD_66_66MHZ: + if (fb_div_selection == FPGA_FB_DIV_6) { + if (vco_div_selection == FPGA_VCO_DIV_4) + sys_per = PERIOD_100_00MHZ; + if (vco_div_selection == FPGA_VCO_DIV_6) + sys_per = PERIOD_66_66MHZ; + if (vco_div_selection == FPGA_VCO_DIV_8) + sys_per = PERIOD_50_00MHZ; + } + if (fb_div_selection == FPGA_FB_DIV_10) { + if (vco_div_selection == FPGA_VCO_DIV_8) + sys_per = PERIOD_83_33MHZ; + if (vco_div_selection == FPGA_VCO_DIV_10) + sys_per = PERIOD_66_66MHZ; + } + if (fb_div_selection == FPGA_FB_DIV_12) { + if (vco_div_selection == FPGA_VCO_DIV_8) + sys_per = PERIOD_100_00MHZ; + } + break; + default: + break; + } + + if (sys_per == 0) { + /* Other combinations are not supported */ + DEBUGF ("%s[%d] *** sys period compute failed ***\n", __FUNCTION__,__LINE__); + hang(); + } + } else { + /* calcul system clock without cheking */ + /* if engineering option clock no check is selected */ + /* sys_per = master_clock_per * vco_div_selection / fb_div_selection */ + sys_per = (master_clock_per/fb_div_selection) * vco_div_selection; + } + + return(sys_per); + +} + +/*-------------------------------------------------------------------------+ +| determine_pci_clock_per. ++-------------------------------------------------------------------------*/ +unsigned long determine_pci_clock_per(void) +{ + unsigned long pci_clock_selection, pci_period; + + /*-------------------------------------------------------------------------+ + | Read FPGA reg 6 to get PCI 0 FPGA reg information + +-------------------------------------------------------------------------*/ + pci_clock_selection = in16(FPGA_REG16); /* was reg6 averifier */ + + + pci_clock_selection = pci_clock_selection & FPGA_REG16_PCI0_CLK_MASK; + + switch (pci_clock_selection) { + case FPGA_REG16_PCI0_CLK_133_33: + pci_period = PERIOD_133_33MHZ; + break; + case FPGA_REG16_PCI0_CLK_100: + pci_period = PERIOD_100_00MHZ; + break; + case FPGA_REG16_PCI0_CLK_66_66: + pci_period = PERIOD_66_66MHZ; + break; + default: + pci_period = PERIOD_33_33MHZ;; + break; + } + + return(pci_period); } #endif diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 647088f..60ed2d5 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -155,6 +155,11 @@ /**************************************************************************/ _start_440: + /*----------------------------------------------------------------+ + | Core bug fix. Clear the esr + +-----------------------------------------------------------------*/ + li r0,0 + mtspr esr,r0 /*----------------------------------------------------------------*/ /* Clear and set up some registers. */ /*----------------------------------------------------------------*/ @@ -166,7 +171,7 @@ _start_440: mtspr srr1,r0 mtspr csrr0,r0 mtspr csrr1,r0 -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) /* NOTE: 440GX adds machine check status regs */ +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* NOTE: 440GX adds machine check status regs */ mtspr mcsrr0,r0 mtspr mcsrr1,r0 mfspr r1, mcsr @@ -200,6 +205,31 @@ _start_440: ori r1,r1,0x6000 /* cache touch */ mtspr ccr0,r1 +#if defined (CONFIG_440SPE) + /*----------------------------------------------------------------+ + | Initialize Core Configuration Reg1. + | a. ICDPEI: Record even parity. Normal operation. + | b. ICTPEI: Record even parity. Normal operation. + | c. DCTPEI: Record even parity. Normal operation. + | d. DCDPEI: Record even parity. Normal operation. + | e. DCUPEI: Record even parity. Normal operation. + | f. DCMPEI: Record even parity. Normal operation. + | g. FCOM: Normal operation + | h. MMUPEI: Record even parity. Normal operation. + | i. FFF: Flush only as much data as necessary. + | j. TCS: Timebase increments from CPU clock. + +-----------------------------------------------------------------*/ + li r0,0 + mtspr ccr1, r0 + + /*----------------------------------------------------------------+ + | Reset the timebase. + | The previous write to CCR1 sets the timebase source. + +-----------------------------------------------------------------*/ + mtspr tbl, r0 + mtspr tbu, r0 +#endif + /*----------------------------------------------------------------*/ /* Setup interrupt vectors */ /*----------------------------------------------------------------*/ @@ -261,20 +291,47 @@ _start_440: mtspr ivlim,r1 mtspr dvlim,r1 + /*----------------------------------------------------------------+ + |Initialize MMUCR[STID] = 0. + +-----------------------------------------------------------------*/ + mfspr r0,mmucr + addis r1,0,0xFFFF + ori r1,r1,0xFF00 + and r0,r0,r1 + mtspr mmucr,r0 + /*----------------------------------------------------------------*/ /* Clear all TLB entries -- TID = 0, TS = 0 */ /*----------------------------------------------------------------*/ - mtspr mmucr,r0 + addis r0,0,0x0000 li r1,0x003f /* 64 TLB entries */ mtctr r1 -0: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ +rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ + tlbwe r0,r1,0x0001 + tlbwe r0,r1,0x0002 subi r1,r1,0x0001 - bdnz 0b + bdnz rsttlb /*----------------------------------------------------------------*/ /* TLB entry setup -- step thru tlbtab */ /*----------------------------------------------------------------*/ +#if defined(CONFIG_440SPE) + /*----------------------------------------------------------------*/ + /* We have different TLB tables for revA and rev B of 440SPe */ + /*----------------------------------------------------------------*/ + mfspr r1, PVR + lis r0,0x5342 + ori r0,r0,0x1891 + cmpw r7,r1,r0 + bne r7,..revA + bl tlbtabB + b ..goon +..revA: + bl tlbtabA +..goon: +#else bl tlbtab /* Get tlbtab pointer */ +#endif mr r5,r0 li r1,0x003f /* 64 TLB entries max */ mtctr r1 @@ -377,7 +434,7 @@ _start: addi r3,r3,32 bdnz ..d_ag #else -#if defined (CONFIG_440GX) || defined(CONFIG_440SP) +#if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */ #endif mtdcr isram0_sb1cr,r0 /* Disable bank 1 */ @@ -404,6 +461,19 @@ _start: lis r1, 0x8003 ori r1,r1, 0x0980 /* fourth 64k */ mtdcr isram0_sb3cr,r1 +#elif defined(CONFIG_440SPE) + lis r1,0x0000 /* BAS = 0000_0000 */ + ori r1,r1,0x0984 /* first 64k */ + mtdcr isram0_sb0cr,r1 + lis r1,0x0001 + ori r1,r1,0x0984 /* second 64k */ + mtdcr isram0_sb1cr,r1 + lis r1, 0x0002 + ori r1,r1, 0x0984 /* third 64k */ + mtdcr isram0_sb2cr,r1 + lis r1, 0x0003 + ori r1,r1, 0x0984 /* fourth 64k */ + mtdcr isram0_sb3cr,r1 #else ori r1,r1,0x0380 /* 8k rw */ mtdcr isram0_sb0cr,r1 @@ -1197,7 +1267,7 @@ ppcSync: */ .globl relocate_code relocate_code: -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE) /* * On some 440er platforms the cache is enabled in the first TLB (Boot-CS) * to speed up the boot process. Now this cache needs to be disabled. @@ -1412,7 +1482,7 @@ trap_init: cmplw 0, r7, r8 blt 4b -#if !defined(CONFIG_440_GX) +#if !defined(CONFIG_440GX) && !defined(CONFIG_440SPE) addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ mtmsr r7 /* change MSR */ diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h index cbfe41d..93cef02 100644 --- a/cpu/ppc4xx/vecnum.h +++ b/cpu/ppc4xx/vecnum.h @@ -31,7 +31,48 @@ #ifndef _VECNUMS_H_ #define _VECNUMS_H_ -#if defined(CONFIG_440SP) +#if defined(CONFIG_440SPE) +/* UIC 0 */ +#define VECNUM_U0 0 /* UART0 */ +#define VECNUM_U1 1 /* UART1 */ +#define VECNUM_IIC0 2 /* IIC0 */ +#define VECNUM_IIC1 3 /* IIC1 */ +#define VECNUM_PIM 4 /* PCI inbound message */ +#define VECNUM_PCRW 5 /* PCI command reg write */ +#define VECNUM_PPM 6 /* PCI power management */ +#define VECNUM_MSI0 7 /* PCI MSI level 0 */ +#define VECNUM_MSI1 8 /* PCI MSI level 0 */ +#define VECNUM_MSI2 9 /* PCI MSI level 0 */ +#define VECNUM_D0 12 /* DMA channel 0 */ +#define VECNUM_D1 13 /* DMA channel 1 */ +#define VECNUM_D2 14 /* DMA channel 2 */ +#define VECNUM_D3 15 /* DMA channel 3 */ +#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ +#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ + +/* UIC 1 */ +#define VECNUM_MS (32 + 1 ) /* MAL SERR */ +#define VECNUM_TXDE (32 + 2 ) /* MAL TXDE */ +#define VECNUM_RXDE (32 + 3 ) /* MAL RXDE */ +#define VECNUM_MTE (32 + 6 ) /* MAL Tx EOB */ +#define VECNUM_MRE (32 + 7 ) /* MAL Rx EOB */ +#define VECNUM_CT0 (32 + 12 ) /* GPT compare timer 0 */ +#define VECNUM_CT1 (32 + 13 ) /* GPT compare timer 1 */ +#define VECNUM_CT2 (32 + 14 ) /* GPT compare timer 2 */ +#define VECNUM_CT3 (32 + 15 ) /* GPT compare timer 3 */ +#define VECNUM_CT4 (32 + 16 ) /* GPT compare timer 4 */ +#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ +#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ + +/* UIC 2 */ +#define VECNUM_EIR5 (62 + 24) /* External interrupt 5 */ +#define VECNUM_EIR4 (62 + 25) /* External interrupt 4 */ +#define VECNUM_EIR3 (62 + 26) /* External interrupt 3 */ +#define VECNUM_EIR2 (62 + 27) /* External interrupt 2 */ +#define VECNUM_EIR1 (62 + 28) /* External interrupt 1 */ +#define VECNUM_EIR0 (62 + 29) /* External interrupt 0 */ + +#elif defined(CONFIG_440SP) /* UIC 0 */ #define VECNUM_U0 0 /* UART0 */ diff --git a/doc/README.440-DDR-performance b/doc/README.440-DDR-performance new file mode 100644 index 0000000..17bc747 --- /dev/null +++ b/doc/README.440-DDR-performance @@ -0,0 +1,90 @@ +AMCC suggested to set the PMU bit to 0 for best performace on the +PPC440 DDR controller. The 440er common DDR setup files (sdram.c & +spd_sdram.c) are changed accordingly. So all 440er boards using +these setup routines will automatically receive this performance +increase. + +Please see below some benchmarks done by AMCC to demonstrate this +performance changes: + + +---------------------------------------- +SDRAM0_CFG0[PMU] = 1 (U-boot default for Bamboo, Yosemite and Yellowstone) +---------------------------------------- +Stream benchmark results +------------------------------------------------------------- +This system uses 8 bytes per DOUBLE PRECISION word. +------------------------------------------------------------- +Array size = 2000000, Offset = 0 +Total memory required = 45.8 MB. +Each test is run 10 times, but only +the *best* time for each is used. +------------------------------------------------------------- +Your clock granularity/precision appears to be 1 microseconds. +Each test below will take on the order of 112345 microseconds. + (= 112345 clock ticks) +Increase the size of the arrays if this shows that you are not getting +at least 20 clock ticks per test. +------------------------------------------------------------- +WARNING -- The above is only a rough guideline. +For best results, please be sure you know the precision of your system +timer. +------------------------------------------------------------- +Function Rate (MB/s) RMS time Min time Max time +Copy: 256.7683 0.1248 0.1246 0.1250 +Scale: 246.0157 0.1302 0.1301 0.1302 +Add: 255.0316 0.1883 0.1882 0.1885 +Triad: 253.1245 0.1897 0.1896 0.1899 + + +TTCP Benchmark Results +ttcp-t: socket +ttcp-t: connect +ttcp-t: buflen=8192, nbuf=2048, align=16384/0, port=5000 tcp -> +localhost +ttcp-t: 16777216 bytes in 0.28 real seconds = 454.29 Mbit/sec +++ +ttcp-t: 2048 I/O calls, msec/call = 0.14, calls/sec = 7268.57 +ttcp-t: 0.0user 0.1sys 0:00real 60% 0i+0d 0maxrss 0+2pf 3+1506csw + +---------------------------------------- +SDRAM0_CFG0[PMU] = 0 (Suggested modification) +Setting PMU = 0 provides a noticeable performance improvement *2% to +5% improvement in memory performance. +*Improves the Mbit/sec for TTCP benchmark by almost 76%. +---------------------------------------- +Stream benchmark results +------------------------------------------------------------- +This system uses 8 bytes per DOUBLE PRECISION word. +------------------------------------------------------------- +Array size = 2000000, Offset = 0 +Total memory required = 45.8 MB. +Each test is run 10 times, but only +the *best* time for each is used. +------------------------------------------------------------- +Your clock granularity/precision appears to be 1 microseconds. +Each test below will take on the order of 120066 microseconds. + (= 120066 clock ticks) +Increase the size of the arrays if this shows that you are not getting +at least 20 clock ticks per test. +------------------------------------------------------------- +WARNING -- The above is only a rough guideline. +For best results, please be sure you know the precision of your system +timer. +------------------------------------------------------------- +Function Rate (MB/s) RMS time Min time Max time +Copy: 262.5167 0.1221 0.1219 0.1223 +Scale: 258.4856 0.1238 0.1238 0.1240 +Add: 262.5404 0.1829 0.1828 0.1831 +Triad: 266.8594 0.1800 0.1799 0.1802 + +TTCP Benchmark Results +ttcp-t: socket +ttcp-t: connect +ttcp-t: buflen=8192, nbuf=2048, align=16384/0, port=5000 tcp -> +localhost +ttcp-t: 16777216 bytes in 0.16 real seconds = 804.06 Mbit/sec +++ +ttcp-t: 2048 I/O calls, msec/call = 0.08, calls/sec = 12864.89 +ttcp-t: 0.0user 0.0sys 0:00real 46% 0i+0d 0maxrss 0+2pf 120+1csw + + +2006-07-28, Stefan Roese <sr@denx.de> diff --git a/doc/README.bamboo b/doc/README.bamboo new file mode 100644 index 0000000..b50be01 --- /dev/null +++ b/doc/README.bamboo @@ -0,0 +1,15 @@ +The configuration for the AMCC 440EP eval board "Bamboo" was changed +to only use 384 kbytes of FLASH for the U-Boot image. This way the +redundant environment can be saved in the remaining 2 sectors of the +same flash chip. + +Caution: With an upgrade from an earlier U-Boot version the current +environment will be erased since the environment is now saved in +different sectors. By using the following command the environment can +be saved after upgrading the U-Boot image and *before* resetting the +board: + +setenv recover_env 'prot off FFF80000 FFF9FFFF;era FFF80000 FFF9FFFF;' \ + 'cp.b FFF60000 FFF80000 20000' + +2006-07-27, Stefan Roese <sr@denx.de> diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn new file mode 100644 index 0000000..8ea0b1e --- /dev/null +++ b/doc/README.mpc8641hpcn @@ -0,0 +1,123 @@ +Freescale MPC8641HPCN board +=========================== + +Created 05/24/2006 Haiying Wang +------------------------------- + +1. Building U-Boot +------------------ +The 86xx HPCN code base is known to compile using: + Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3 + + $ make MPC8641HPCN_config + Configuring for MPC8641HPCN board... + + $ make + + +2. Switch and Jumper Setting +---------------------------- +Jumpers: + J14 Pins 1-2 (near plcc32 socket) + +Switches: + SW1(1-5) = 01100 CFG_COREPLL = 01000 :: CORE = 2:1 + 01100 :: CORE = 2.5:1 + 10000 :: CORE = 3:1 + 11100 :: CORE = 3.5:1 + 10100 :: CORE = 4:1 + 01110 :: CORE = 4.5:1 + SW1(6-8) = 001 CFG_SYSCLK = 000 :: SYSCLK = 33MHz + 001 :: SYSCLK = 40MHz + + SW2(1-4) = 1100 CFG_CCBPLL = 0010 :: 2X + 0100 :: 4X + 0110 :: 6X + 1000 :: 8X + 1010 :: 10X + 1100 :: 12X + 1110 :: 14X + 0000 :: 16X + SW2(5-8) = 1110 CFG_BOOTLOC = 1110 :: boot 16-bit localbus + + SW3(1-7) = 0011000 CFG_VID = 0011000 :: VCORE = 1.2V + 0100000 :: VCORE = 1.11V + SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V + 1 :: VCC_PLAT = 1.0V + + SW4(1-2) = 11 CFG_HOSTMODE = 11 :: both prots host/root + SW4(3-4) = 11 CFG_BOOTSEQ = 11 :: no boot seq + SW4(5-8) = 0011 CFG_IOPORT = 0011 :: both PEX + + SW5(1) = 1 CFG_FLASHMAP = 1 :: boot from flash + 0 :: boot from PromJet + SW5(2) = 1 CFG_FLASHBANK = 1 :: swap upper/lower + halves (virtual banks) + 0 :: normal + SW5(3) = 0 CFG_FLASHWP = 0 :: not protected + SW5(4) = 0 CFG_PORTDIV = 1 :: 2:1 for PD4 + 1:1 for PD6 + SW5(5-6) = 11 CFG_PIXISOPT = 11 :: s/w determined + SW5(7-8) = 11 CFG_LADOPT = 11 :: s/w determined + + SW6(1) = 1 CFG_CPUBOOT = 1 :: no boot holdoff + SW6(2) = 1 CFG_BOOTADDR = 1 :: no traslation + SW6(3-5) = 000 CFG_REFCLKSEL = 000 :: 100MHZ + SW6(6) = 1 CFG_SERROM_ADDR= 1 :: + SW6(7) = 1 CFG_MEMDEBUG = 1 :: + SW6(8) = 1 CFG_DDRDEBUG = 1 :: + + SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49 + SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled + SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode + SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz + SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode + SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled + SW8(7) = 1 ACPWR = 1 :: non-battery + SW8(8) = 0 CFG_IDWP = 0 :: write enable + + +3. Flash U-Boot +--------------- +The flash range 0xFF800000 to 0xFFFFFFFF can be divided into 2 halves. +It is possible to use either half to boot using u-boot. Switch 5 bit 2 +is used for this purpose. + +0xFF800000 to 0xFFBFFFFF - 4MB +0xFFC00000 to 0xFFFFFFFF - 4MB +When this bit is 0, U-Boot is at 0xFFF00000. +When this bit is 1, U-Boot is at 0xFFB00000. + +Use the above mentioned flash commands to program the other half, and +use switch 5, bit 2 to alternate between the halves. Note: The booting +version of U-Boot will always be at 0xFFF00000. + +To Flash U-Boot into the booting bank (0xFFC00000 - 0xFFFFFFFF): + + tftp 1000000 u-boot.bin + protect off all + erase fff00000 ffffffff + cp.b 1000000 fff00100 80000 + +To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF): + + tftp 1000000 u-boot.bin + erase ffb00000 ffbfffff + cp.b 1000000 ffb00100 80000 + + +4. Memory Map +------------- + + Memory Range Device Size + ------------ ------ ---- + 0x0000_0000 0x7fff_ffff DDR 2G + 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M + 0xa000_0000 0xafff_ffff PCI2/PEX2 MEM 512M + 0xf800_0000 0xf80f_ffff CCSR 1M + 0xf810_0000 0xf81f_ffff PIXIS 1M + 0xf840_0000 0xf840_3fff Stack space 32K + 0xe200_0000 0xe2ff_ffff PCI1/PEX1 IO 16M + 0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 16M + 0xfe00_0000 0xfeff_ffff Flash(alternate)16M + 0xff00_0000 0xffff_ffff Flash(boot bank)16M diff --git a/drivers/Makefile b/drivers/Makefile index e6176ed..25e1622 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -31,7 +31,7 @@ OBJS = 3c589.o 5701rls.o ali512x.o \ bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \ cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \ e1000.o eepro100.o \ - i8042.o i82365.o inca-ip_sw.o keyboard.o \ + i8042.o inca-ip_sw.o keyboard.o \ lan91c96.o \ natsemi.o ne2000.o netarm_eth.o netconsole.o \ ns16550.o ns8382x.o ns87308.o ns7520_eth.o omap1510_i2c.o \ @@ -44,11 +44,13 @@ OBJS = 3c589.o 5701rls.o ali512x.o \ serial.o serial_max3100.o \ serial_pl010.o serial_pl011.o serial_xuartlite.o \ sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ - status_led.o sym53c8xx.o \ + status_led.o sym53c8xx.o ahci.o \ ti_pci1410a.o tigon3.o tsec.o \ usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \ videomodes.o w83c553f.o \ - ks8695eth.o + ks8695eth.o \ + pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \ + rpx_pcmcia.o all: $(LIB) diff --git a/drivers/ahci.c b/drivers/ahci.c new file mode 100644 index 0000000..8ceff00 --- /dev/null +++ b/drivers/ahci.c @@ -0,0 +1,702 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * Author: Jason Jin<Jason.jin@freescale.com> + * Zhang Wei<wei.zhang@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * with the reference on libata and ahci drvier in kernel + * + */ +#include <common.h> + +#ifdef CONFIG_SCSI_AHCI + +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <malloc.h> +#include <scsi.h> +#include <ata.h> +#include <linux/ctype.h> +#include <ahci.h> + +struct ahci_probe_ent *probe_ent = NULL; +hd_driveid_t *ataid[AHCI_MAX_PORTS]; + +#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) + + +static inline u32 ahci_port_base(u32 base, u32 port) +{ + return base + 0x100 + (port * 0x80); +} + + +static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, + unsigned int port_idx) +{ + base = ahci_port_base(base, port_idx); + + port->cmd_addr = base; + port->scr_addr = base + PORT_SCR; +} + + +#define msleep(a) udelay(a * 1000) +#define ssleep(a) msleep(a * 1000) + +static int waiting_for_cmd_completed(volatile u8 *offset, + int timeout_msec, + u32 sign) +{ + int i; + u32 status; + + for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) + msleep(1); + + return (i < timeout_msec) ? 0 : -1; +} + + +static int ahci_host_init(struct ahci_probe_ent *probe_ent) +{ + pci_dev_t pdev = probe_ent->dev; + volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; + u32 tmp, cap_save; + u16 tmp16; + int i, j; + volatile u8 *port_mmio; + unsigned short vendor; + + cap_save = readl(mmio + HOST_CAP); + cap_save &= ((1 << 28) | (1 << 17)); + cap_save |= (1 << 27); + + /* global controller reset */ + tmp = readl(mmio + HOST_CTL); + if ((tmp & HOST_RESET) == 0) + writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); + + /* reset must complete within 1 second, or + * the hardware should be considered fried. + */ + ssleep(1); + + tmp = readl(mmio + HOST_CTL); + if (tmp & HOST_RESET) { + debug("controller reset failed (0x%x)\n", tmp); + return -1; + } + + writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); + writel(cap_save, mmio + HOST_CAP); + writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); + + pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); + + if (vendor == PCI_VENDOR_ID_INTEL) { + u16 tmp16; + pci_read_config_word(pdev, 0x92, &tmp16); + tmp16 |= 0xf; + pci_write_config_word(pdev, 0x92, tmp16); + } + + probe_ent->cap = readl(mmio + HOST_CAP); + probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); + probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; + + debug("cap 0x%x port_map 0x%x n_ports %d\n", + probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); + + for (i = 0; i < probe_ent->n_ports; i++) { + probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); + port_mmio = (u8 *) probe_ent->port[i].port_mmio; + ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); + + /* make sure port is not active */ + tmp = readl(port_mmio + PORT_CMD); + if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | + PORT_CMD_FIS_RX | PORT_CMD_START)) { + tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | + PORT_CMD_FIS_RX | PORT_CMD_START); + writel_with_flush(tmp, port_mmio + PORT_CMD); + + /* spec says 500 msecs for each bit, so + * this is slightly incorrect. + */ + msleep(500); + } + + writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); + + j = 0; + while (j < 100) { + msleep(10); + tmp = readl(port_mmio + PORT_SCR_STAT); + if ((tmp & 0xf) == 0x3) + break; + j++; + } + + tmp = readl(port_mmio + PORT_SCR_ERR); + debug("PORT_SCR_ERR 0x%x\n", tmp); + writel(tmp, port_mmio + PORT_SCR_ERR); + + /* ack any pending irq events for this port */ + tmp = readl(port_mmio + PORT_IRQ_STAT); + debug("PORT_IRQ_STAT 0x%x\n", tmp); + if (tmp) + writel(tmp, port_mmio + PORT_IRQ_STAT); + + writel(1 << i, mmio + HOST_IRQ_STAT); + + /* set irq mask (enables interrupts) */ + writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); + + /*register linkup ports */ + tmp = readl(port_mmio + PORT_SCR_STAT); + debug("Port %d status: 0x%x\n", i, tmp); + if ((tmp & 0xf) == 0x03) + probe_ent->link_port_map |= (0x01 << i); + } + + tmp = readl(mmio + HOST_CTL); + debug("HOST_CTL 0x%x\n", tmp); + writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); + tmp = readl(mmio + HOST_CTL); + debug("HOST_CTL 0x%x\n", tmp); + + pci_read_config_word(pdev, PCI_COMMAND, &tmp16); + tmp |= PCI_COMMAND_MASTER; + pci_write_config_word(pdev, PCI_COMMAND, tmp16); + + return 0; +} + + +static void ahci_print_info(struct ahci_probe_ent *probe_ent) +{ + pci_dev_t pdev = probe_ent->dev; + volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; + u32 vers, cap, impl, speed; + const char *speed_s; + u16 cc; + const char *scc_s; + + vers = readl(mmio + HOST_VERSION); + cap = probe_ent->cap; + impl = probe_ent->port_map; + + speed = (cap >> 20) & 0xf; + if (speed == 1) + speed_s = "1.5"; + else if (speed == 2) + speed_s = "3"; + else + speed_s = "?"; + + pci_read_config_word(pdev, 0x0a, &cc); + if (cc == 0x0101) + scc_s = "IDE"; + else if (cc == 0x0106) + scc_s = "SATA"; + else if (cc == 0x0104) + scc_s = "RAID"; + else + scc_s = "unknown"; + + printf("AHCI %02x%02x.%02x%02x " + "%u slots %u ports %s Gbps 0x%x impl %s mode\n", + (vers >> 24) & 0xff, + (vers >> 16) & 0xff, + (vers >> 8) & 0xff, + vers & 0xff, + ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); + + printf("flags: " + "%s%s%s%s%s%s" + "%s%s%s%s%s%s%s\n", + cap & (1 << 31) ? "64bit " : "", + cap & (1 << 30) ? "ncq " : "", + cap & (1 << 28) ? "ilck " : "", + cap & (1 << 27) ? "stag " : "", + cap & (1 << 26) ? "pm " : "", + cap & (1 << 25) ? "led " : "", + cap & (1 << 24) ? "clo " : "", + cap & (1 << 19) ? "nz " : "", + cap & (1 << 18) ? "only " : "", + cap & (1 << 17) ? "pmp " : "", + cap & (1 << 15) ? "pio " : "", + cap & (1 << 14) ? "slum " : "", + cap & (1 << 13) ? "part " : ""); +} + +static int ahci_init_one(pci_dev_t pdev) +{ + u32 iobase, vendor; + int rc; + + memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); + + probe_ent = malloc(sizeof(probe_ent)); + memset(probe_ent, 0, sizeof(probe_ent)); + probe_ent->dev = pdev; + + pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase); + iobase &= ~0xf; + + probe_ent->host_flags = ATA_FLAG_SATA + | ATA_FLAG_NO_LEGACY + | ATA_FLAG_MMIO + | ATA_FLAG_PIO_DMA + | ATA_FLAG_NO_ATAPI; + probe_ent->pio_mask = 0x1f; + probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ + + probe_ent->mmio_base = iobase; + + /* Take from kernel: + * JMicron-specific fixup: + * make sure we're in AHCI mode + */ + pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); + if (vendor == 0x197b) + pci_write_config_byte(pdev, 0x41, 0xa1); + + /* initialize adapter */ + rc = ahci_host_init(probe_ent); + if (rc) + goto err_out; + + ahci_print_info(probe_ent); + + return 0; + + err_out: + return rc; +} + + +#define MAX_DATA_BYTE_COUNT (4*1024*1024) + +static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) +{ + struct ahci_ioports *pp = &(probe_ent->port[port]); + struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; + u32 sg_count; + int i; + + sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; + if (sg_count > AHCI_MAX_SG) { + printf("Error:Too much sg!\n"); + return -1; + } + + for (i = 0; i < sg_count; i++) { + ahci_sg->addr = + cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); + ahci_sg->addr_hi = 0; + ahci_sg->flags_size = cpu_to_le32(0x3fffff & + (buf_len < MAX_DATA_BYTE_COUNT + ? (buf_len - 1) + : (MAX_DATA_BYTE_COUNT - 1))); + ahci_sg++; + buf_len -= MAX_DATA_BYTE_COUNT; + } + + return sg_count; +} + + +static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) +{ + pp->cmd_slot->opts = cpu_to_le32(opts); + pp->cmd_slot->status = 0; + pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); + pp->cmd_slot->tbl_addr_hi = 0; +} + + +static void ahci_set_feature(u8 port) +{ + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + u32 cmd_fis_len = 5; /* five dwords */ + u8 fis[20]; + + /*set feature */ + memset(fis, 0, 20); + fis[0] = 0x27; + fis[1] = 1 << 7; + fis[2] = ATA_CMD_SETF; + fis[3] = SETFEATURES_XFER; + fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; + + memcpy((unsigned char *)pp->cmd_tbl, fis, 20); + ahci_fill_cmd_slot(pp, cmd_fis_len); + writel(1, port_mmio + PORT_CMD_ISSUE); + readl(port_mmio + PORT_CMD_ISSUE); + + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { + printf("set feature error!\n"); + } +} + + +static int ahci_port_start(u8 port) +{ + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + u32 port_status; + u32 mem; + + debug("Enter start port: %d\n", port); + port_status = readl(port_mmio + PORT_SCR_STAT); + debug("Port %d status: %x\n", port, port_status); + if ((port_status & 0xf) != 0x03) { + printf("No Link on this port!\n"); + return -1; + } + + mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); + if (!mem) { + free(pp); + printf("No mem for table!\n"); + return -ENOMEM; + } + + mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ + memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); + + /* + * First item in chunk of DMA memory: 32-slot command table, + * 32 bytes each in size + */ + pp->cmd_slot = (struct ahci_cmd_hdr *)mem; + debug("cmd_slot = 0x%x\n", pp->cmd_slot); + mem += (AHCI_CMD_SLOT_SZ + 224); + + /* + * Second item: Received-FIS area + */ + pp->rx_fis = mem; + mem += AHCI_RX_FIS_SZ; + + /* + * Third item: data area for storing a single command + * and its scatter-gather table + */ + pp->cmd_tbl = mem; + debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); + + mem += AHCI_CMD_TBL_HDR; + pp->cmd_tbl_sg = (struct ahci_sg *)mem; + + writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); + + writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); + + writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | + PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | + PORT_CMD_START, port_mmio + PORT_CMD); + + debug("Exit start port %d\n", port); + + return 0; +} + + +static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, + int buf_len) +{ + + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + u32 opts; + u32 port_status; + int sg_count; + + debug("Enter get_ahci_device_data: for port %d\n", port); + + if (port > probe_ent->n_ports) { + printf("Invaild port number %d\n", port); + return -1; + } + + port_status = readl(port_mmio + PORT_SCR_STAT); + if ((port_status & 0xf) != 0x03) { + debug("No Link on port %d!\n", port); + return -1; + } + + memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); + + sg_count = ahci_fill_sg(port, buf, buf_len); + opts = (fis_len >> 2) | (sg_count << 16); + ahci_fill_cmd_slot(pp, opts); + + writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); + + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { + printf("timeout exit!\n"); + return -1; + } + debug("get_ahci_device_data: %d byte transferred.\n", + pp->cmd_slot->status); + + return 0; +} + + +static char *ata_id_strcpy(u16 *target, u16 *src, int len) +{ + int i; + for (i = 0; i < len / 2; i++) + target[i] = le16_to_cpu(src[i]); + return (char *)target; +} + + +static void dump_ataid(hd_driveid_t *ataid) +{ + debug("(49)ataid->capability = 0x%x\n", ataid->capability); + debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid); + debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword); + debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes); + debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth); + debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num); + debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num); + debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1); + debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2); + debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse); + debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1); + debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2); + debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default); + debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra); + debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); +} + + +/* + * SCSI INQUIRY command operation. + */ +static int ata_scsiop_inquiry(ccb *pccb) +{ + u8 hdr[] = { + 0, + 0, + 0x5, /* claim SPC-3 version compatibility */ + 2, + 95 - 4, + }; + u8 fis[20]; + u8 *tmpid; + u8 port; + + /* Clean ccb data buffer */ + memset(pccb->pdata, 0, pccb->datalen); + + memcpy(pccb->pdata, hdr, sizeof(hdr)); + + if (pccb->datalen <= 35) + return 0; + + memset(fis, 0, 20); + /* Construct the FIS */ + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ + fis[2] = ATA_CMD_IDENT; /* Command byte. */ + + /* Read id from sata */ + port = pccb->target; + if (!(tmpid = malloc(sizeof(hd_driveid_t)))) + return -ENOMEM; + + if (get_ahci_device_data(port, (u8 *) & fis, 20, + tmpid, sizeof(hd_driveid_t))) { + debug("scsi_ahci: SCSI inquiry command failure.\n"); + return -EIO; + } + + if (ataid[port]) + free(ataid[port]); + ataid[port] = (hd_driveid_t *) tmpid; + + memcpy(&pccb->pdata[8], "ATA ", 8); + ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16); + ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); + + dump_ataid(ataid[port]); + return 0; +} + + +/* + * SCSI READ10 command operation. + */ +static int ata_scsiop_read10(ccb * pccb) +{ + u64 lba = 0; + u32 len = 0; + u8 fis[20]; + + lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16) + | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]); + len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]); + + /* For 10-byte and 16-byte SCSI R/W commands, transfer + * length 0 means transfer 0 block of data. + * However, for ATA R/W commands, sector count 0 means + * 256 or 65536 sectors, not 0 sectors as in SCSI. + * + * WARNING: one or two older ATA drives treat 0 as 0... + */ + if (!len) + return 0; + memset(fis, 0, 20); + + /* Construct the FIS */ + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ + fis[2] = ATA_CMD_RD_DMA; /* Command byte. */ + + /* LBA address, only support LBA28 in this driver */ + fis[4] = pccb->cmd[5]; + fis[5] = pccb->cmd[4]; + fis[6] = pccb->cmd[3]; + fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0; + + /* Sector Count */ + fis[12] = pccb->cmd[8]; + fis[13] = pccb->cmd[7]; + + /* Read from ahci */ + if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20, + pccb->pdata, pccb->datalen)) { + debug("scsi_ahci: SCSI READ10 command failure.\n"); + return -EIO; + } + + return 0; +} + + +/* + * SCSI READ CAPACITY10 command operation. + */ +static int ata_scsiop_read_capacity10(ccb *pccb) +{ + u8 buf[8]; + + if (!ataid[pccb->target]) { + printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " + "\tNo ATA info!\n" + "\tPlease run SCSI commmand INQUIRY firstly!\n"); + return -EPERM; + } + + memset(buf, 0, 8); + + *(u32 *) buf = le32_to_cpu(ataid[pccb->target]->lba_capacity); + + buf[6] = 512 >> 8; + buf[7] = 512 & 0xff; + + memcpy(pccb->pdata, buf, 8); + + return 0; +} + + +/* + * SCSI TEST UNIT READY command operation. + */ +static int ata_scsiop_test_unit_ready(ccb *pccb) +{ + return (ataid[pccb->target]) ? 0 : -EPERM; +} + + +int scsi_exec(ccb *pccb) +{ + int ret; + + switch (pccb->cmd[0]) { + case SCSI_READ10: + ret = ata_scsiop_read10(pccb); + break; + case SCSI_RD_CAPAC: + ret = ata_scsiop_read_capacity10(pccb); + break; + case SCSI_TST_U_RDY: + ret = ata_scsiop_test_unit_ready(pccb); + break; + case SCSI_INQUIRY: + ret = ata_scsiop_inquiry(pccb); + break; + default: + printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); + return FALSE; + } + + if (ret) { + debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); + return FALSE; + } + return TRUE; + +} + + +void scsi_low_level_init(int busdevfunc) +{ + int i; + u32 linkmap; + + ahci_init_one(busdevfunc); + + linkmap = probe_ent->link_port_map; + + for (i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++) { + if (((linkmap >> i) & 0x01)) { + if (ahci_port_start((u8) i)) { + printf("Can not start port %d\n", i); + continue; + } + ahci_set_feature((u8) i); + } + } +} + + +void scsi_bus_reset(void) +{ + /*Not implement*/ +} + + +void scsi_print_error(ccb * pccb) +{ + /*The ahci error info can be read in the ahci driver*/ +} +#endif diff --git a/drivers/dm9000x.c b/drivers/dm9000x.c index 0e475d4..6877076 100644 --- a/drivers/dm9000x.c +++ b/drivers/dm9000x.c @@ -436,6 +436,9 @@ eth_rx(void) u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0]; u16 RxStatus, RxLen = 0; u32 tmplen, i; +#ifdef CONFIG_DM9000_USE_32BIT + u32 tmpdata; +#endif /* Check packet ready or not */ DM9000_ior(DM9000_MRCMDX); /* Dummy read */ diff --git a/drivers/keyboard.c b/drivers/keyboard.c index 41eccf2..9975202 100644 --- a/drivers/keyboard.c +++ b/drivers/keyboard.c @@ -33,7 +33,7 @@ #define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */ -#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC85xx) +#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) int ps2ser_check(void); #endif @@ -75,7 +75,7 @@ static void kbd_put_queue(char data) /* test if a character is in the queue */ static int kbd_testc(void) { -#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC85xx) +#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) /* no ISR is used, so received chars must be polled */ ps2ser_check(); #endif @@ -90,7 +90,7 @@ static int kbd_getc(void) { char c; while(in_pointer==out_pointer) { -#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC85xx) +#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) /* no ISR is used, so received chars must be polled */ ps2ser_check(); #endif diff --git a/drivers/mpc8xx_pcmcia.c b/drivers/mpc8xx_pcmcia.c new file mode 100644 index 0000000..399a719 --- /dev/null +++ b/drivers/mpc8xx_pcmcia.c @@ -0,0 +1,304 @@ +#include <common.h> +#if defined(CONFIG_8xx) +#include <mpc8xx.h> +#endif +#include <pcmcia.h> + +#undef CONFIG_PCMCIA + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#define CONFIG_PCMCIA +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#define CONFIG_PCMCIA +#endif + +#if defined(CONFIG_8xx) && defined(CONFIG_PCMCIA) + +#if defined(CONFIG_IDE_8xx_PCCARD) +extern int check_ide_device (int slot); +#endif + +extern int pcmcia_hardware_enable (int slot); +extern int pcmcia_voltage_set(int slot, int vcc, int vpp); + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +extern int pcmcia_hardware_disable(int slot); +#endif + +static u_int m8xx_get_graycode(u_int size); +#if 0 /* Disabled */ +static u_int m8xx_get_speed(u_int ns, u_int is_io); +#endif + +/* look up table for pgcrx registers */ +u_int *pcmcia_pgcrx[2] = { + &((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcra, + &((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb, +}; + +/* + * Search this table to see if the windowsize is + * supported... + */ + +#define M8XX_SIZES_NO 32 + +static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] = +{ 0x00000001, 0x00000002, 0x00000008, 0x00000004, + 0x00000080, 0x00000040, 0x00000010, 0x00000020, + 0x00008000, 0x00004000, 0x00001000, 0x00002000, + 0x00000100, 0x00000200, 0x00000800, 0x00000400, + + 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x01000000, 0x02000000, 0xffffffff, 0x04000000, + 0x00010000, 0x00020000, 0x00080000, 0x00040000, + 0x00800000, 0x00400000, 0x00100000, 0x00200000 }; + + +/* -------------------------------------------------------------------- */ + +#ifdef CONFIG_HMI10 +#define HMI10_FRAM_TIMING ( PCMCIA_SHT(2) \ + | PCMCIA_SST(2) \ + | PCMCIA_SL(4)) +#endif + +#if defined(CONFIG_LWMON) || defined(CONFIG_NSCU) +#define CFG_PCMCIA_TIMING ( PCMCIA_SHT(9) \ + | PCMCIA_SST(3) \ + | PCMCIA_SL(12)) +#else +#define CFG_PCMCIA_TIMING ( PCMCIA_SHT(2) \ + | PCMCIA_SST(4) \ + | PCMCIA_SL(9)) +#endif + +/* -------------------------------------------------------------------- */ + +int pcmcia_on (void) +{ + u_long reg, base; + pcmcia_win_t *win; + u_int slotbit; + u_int rc, slot; + int i; + + debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); + + /* intialize the fixed memory windows */ + win = (pcmcia_win_t *)(&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pbr0); + base = CFG_PCMCIA_MEM_ADDR; + + if((reg = m8xx_get_graycode(CFG_PCMCIA_MEM_SIZE)) == -1) { + printf ("Cannot set window size to 0x%08x\n", + CFG_PCMCIA_MEM_SIZE); + return (1); + } + + slotbit = PCMCIA_SLOT_x; + for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) { + win->br = base; + +#if (PCMCIA_SOCKETS_NO == 2) + if (i == 4) /* Another slot starting from win 4 */ + slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B); +#endif + switch (i) { +#ifdef CONFIG_IDE_8xx_PCCARD + case 4: +#ifdef CONFIG_HMI10 + { /* map FRAM area */ + win->or = ( PCMCIA_BSIZE_256K + | PCMCIA_PPS_8 + | PCMCIA_PRS_ATTR + | slotbit + | PCMCIA_PV + | HMI10_FRAM_TIMING ); + break; + } +#endif + case 0: { /* map attribute memory */ + win->or = ( PCMCIA_BSIZE_64M + | PCMCIA_PPS_8 + | PCMCIA_PRS_ATTR + | slotbit + | PCMCIA_PV + | CFG_PCMCIA_TIMING ); + break; + } + case 5: + case 1: { /* map I/O window for data reg */ + win->or = ( PCMCIA_BSIZE_1K + | PCMCIA_PPS_16 + | PCMCIA_PRS_IO + | slotbit + | PCMCIA_PV + | CFG_PCMCIA_TIMING ); + break; + } + case 6: + case 2: { /* map I/O window for cmd/ctrl reg block */ + win->or = ( PCMCIA_BSIZE_1K + | PCMCIA_PPS_8 + | PCMCIA_PRS_IO + | slotbit + | PCMCIA_PV + | CFG_PCMCIA_TIMING ); + break; + } +#endif /* CONFIG_IDE_8xx_PCCARD */ +#ifdef CONFIG_HMI10 + case 3: { /* map I/O window for 4xUART data/ctrl */ + win->br += 0x40000; + win->or = ( PCMCIA_BSIZE_256K + | PCMCIA_PPS_8 + | PCMCIA_PRS_IO + | slotbit + | PCMCIA_PV + | CFG_PCMCIA_TIMING ); + break; + } +#endif /* CONFIG_HMI10 */ + default: /* set to not valid */ + win->or = 0; + break; + } + + debug ("MemWin %d: PBR 0x%08lX POR %08lX\n", + i, win->br, win->or); + base += CFG_PCMCIA_MEM_SIZE; + ++win; + } + + for (i=0, rc=0, slot=_slot_; i<PCMCIA_SOCKETS_NO; i++, slot = !slot) { + /* turn off voltage */ + if ((rc = pcmcia_voltage_set(slot, 0, 0))) + continue; + + /* Enable external hardware */ + if ((rc = pcmcia_hardware_enable(slot))) + continue; + +#ifdef CONFIG_IDE_8xx_PCCARD + if ((rc = check_ide_device(i))) + continue; +#endif + } + return rc; +} + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +int pcmcia_off (void) +{ + int i; + pcmcia_win_t *win; + + printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n"); + + /* clear interrupt state, and disable interrupts */ + ((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pscr = PCMCIA_MASK(_slot_); + ((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_per &= ~PCMCIA_MASK(_slot_); + + /* turn off interrupt and disable CxOE */ + PCMCIA_PGCRX(_slot_) = __MY_PCMCIA_GCRX_CXOE; + + /* turn off memory windows */ + win = (pcmcia_win_t *)(&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pbr0); + + for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) { + /* disable memory window */ + win->or = 0; + ++win; + } + + /* turn off voltage */ + pcmcia_voltage_set(_slot_, 0, 0); + + /* disable external hardware */ + printf ("Shutdown and Poweroff " PCMCIA_SLOT_MSG "\n"); + pcmcia_hardware_disable(_slot_); + return 0; +} +#endif /* CFG_CMD_PCMCIA */ + + +static u_int m8xx_get_graycode(u_int size) +{ + u_int k; + + for (k = 0; k < M8XX_SIZES_NO; k++) { + if(m8xx_size_to_gray[k] == size) + break; + } + + if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1)) + k = -1; + + return k; +} + +#if 0 + +#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) + +/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks. + * SYPCR is write once only, therefore must the slowest memory be faster + * than the bus monitor or we will get a machine check due to the bus timeout. + */ +#undef PCMCIA_BMT_LIMIT +#define PCMCIA_BMT_LIMIT (6*8) +#endif + +static u_int m8xx_get_speed(u_int ns, u_int is_io) +{ + u_int reg, clocks, psst, psl, psht; + + if(!ns) { + + /* + * We get called with IO maps setup to 0ns + * if not specified by the user. + * They should be 255ns. + */ + + if(is_io) + ns = 255; + else + ns = 100; /* fast memory if 0 */ + } + + /* + * In PSST, PSL, PSHT fields we tell the controller + * timing parameters in CLKOUT clock cycles. + * CLKOUT is the same as GCLK2_50. + */ + + /* how we want to adjust the timing - in percent */ + +#define ADJ 180 /* 80 % longer accesstime - to be sure */ + + clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000; + clocks = (clocks * ADJ) / (100*1000); + + if(clocks >= PCMCIA_BMT_LIMIT) { + DEBUG(0, "Max access time limit reached\n"); + clocks = PCMCIA_BMT_LIMIT-1; + } + + psst = clocks / 7; /* setup time */ + psht = clocks / 7; /* hold time */ + psl = (clocks * 5) / 7; /* strobe length */ + + psst += clocks - (psst + psht + psl); + + reg = psst << 12; + reg |= psl << 7; + reg |= psht << 16; + + return reg; +} +#endif /* 0 */ + +#endif /* CONFIG_8xx && CONFIG_PCMCIA */ diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 8fde330..9691675 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -102,7 +102,8 @@ void pciauto_setup_device(struct pci_controller *hose, /* Check the BAR type and set our address mask */ if (bar_response & PCI_BASE_ADDRESS_SPACE) { - bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; + bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK)) + & 0xffff) + 1; bar_res = io; DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size); diff --git a/drivers/pci_indirect.c b/drivers/pci_indirect.c index f0c4a1c..d7be081 100644 --- a/drivers/pci_indirect.c +++ b/drivers/pci_indirect.c @@ -60,7 +60,7 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \ cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ return 0; \ } -#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) +#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE) #define INDIRECT_PCI_OP(rw, size, type, op, mask) \ static int \ indirect_##rw##_config_##size(struct pci_controller *hose, \ diff --git a/drivers/ps2ser.c b/drivers/ps2ser.c index 8aea8fd..4e304f7 100644 --- a/drivers/ps2ser.c +++ b/drivers/ps2ser.c @@ -20,7 +20,7 @@ #include <asm/io.h> #include <asm/atomic.h> #include <ps2mult.h> -#ifdef CFG_NS16550 +#if defined(CFG_NS16550) || defined(CONFIG_MPC85xx) #include <ns16550.h> #endif @@ -49,7 +49,7 @@ DECLARE_GLOBAL_DATA_PTR; #error CONFIG_PS2SERIAL must be in 1 ... 6 #endif -#elif defined(CONFIG_MPC85xx) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) #if CONFIG_PS2SERIAL == 1 #define COM_BASE (CFG_CCSRBAR+0x4500) @@ -59,13 +59,13 @@ DECLARE_GLOBAL_DATA_PTR; #error CONFIG_PS2SERIAL must be in 1 ... 2 #endif -#endif /* CONFIG_MPC5xxx / CONFIG_MPC85xx */ +#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */ static int ps2ser_getc_hw(void); static void ps2ser_interrupt(void *dev_id); extern struct serial_state rs_table[]; /* in serial.c */ -#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC85xx) +#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8555) static struct serial_state *state; #endif @@ -120,7 +120,7 @@ int ps2ser_init(void) return (0); } -#elif defined(CONFIG_MPC85xx) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) int ps2ser_init(void) { NS16550_t com_port = (NS16550_t)COM_BASE; @@ -136,7 +136,7 @@ int ps2ser_init(void) return (0); } -#else /* !CONFIG_MPC5xxx && !CONFIG_MPC85xx */ +#else /* !CONFIG_MPC5xxx && !CONFIG_MPC8540 / other */ static inline unsigned int ps2ser_in(int offset) { @@ -180,13 +180,13 @@ int ps2ser_init(void) return 0; } -#endif /* CONFIG_MPC5xxx / CONFIG_MPC85xx / other */ +#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */ void ps2ser_putc(int chr) { #ifdef CONFIG_MPC5xxx volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#elif defined(CONFIG_MPC85xx) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) NS16550_t com_port = (NS16550_t)COM_BASE; #endif #ifdef DEBUG @@ -197,7 +197,7 @@ void ps2ser_putc(int chr) while (!(psc->psc_status & PSC_SR_TXRDY)); psc->psc_buffer_8 = chr; -#elif defined(CONFIG_MPC85xx) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) while ((com_port->lsr & LSR_THRE) == 0); com_port->thr = chr; #else @@ -211,7 +211,7 @@ static int ps2ser_getc_hw(void) { #ifdef CONFIG_MPC5xxx volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#elif defined(CONFIG_MPC85xx) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) NS16550_t com_port = (NS16550_t)COM_BASE; #endif int res = -1; @@ -220,7 +220,7 @@ static int ps2ser_getc_hw(void) if (psc->psc_status & PSC_SR_RXRDY) { res = (psc->psc_buffer_8); } -#elif defined(CONFIG_MPC85xx) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) if (com_port->lsr & LSR_DR) { res = com_port->rbr; } @@ -279,7 +279,7 @@ static void ps2ser_interrupt(void *dev_id) { #ifdef CONFIG_MPC5xxx volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#elif defined(CONFIG_MPC85xx) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) NS16550_t com_port = (NS16550_t)COM_BASE; #endif int chr; @@ -289,7 +289,7 @@ static void ps2ser_interrupt(void *dev_id) chr = ps2ser_getc_hw(); #ifdef CONFIG_MPC5xxx status = psc->psc_status; -#elif defined(CONFIG_MPC85xx) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) status = com_port->lsr; #else status = ps2ser_in(UART_IIR); @@ -305,7 +305,7 @@ static void ps2ser_interrupt(void *dev_id) } #ifdef CONFIG_MPC5xxx } while (status & PSC_SR_RXRDY); -#elif defined(CONFIG_MPC85xx) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) } while (status & LSR_DR); #else } while (status & UART_IIR_RDI); diff --git a/drivers/pxa_pcmcia.c b/drivers/pxa_pcmcia.c new file mode 100644 index 0000000..d9d38bb --- /dev/null +++ b/drivers/pxa_pcmcia.c @@ -0,0 +1,95 @@ +#include <common.h> +#include <config.h> + +#ifdef CONFIG_PXA_PCMCIA + +#include <pcmcia.h> +#include <asm/arch/pxa-regs.h> +#include <asm/io.h> + +static inline void msWait(unsigned msVal) +{ + udelay(msVal*1000); +} + +int pcmcia_on (void) +{ + unsigned int reg_arr[] = { + 0x48000028, CFG_MCMEM0_VAL, + 0x4800002c, CFG_MCMEM1_VAL, + 0x48000030, CFG_MCATT0_VAL, + 0x48000034, CFG_MCATT1_VAL, + 0x48000038, CFG_MCIO0_VAL, + 0x4800003c, CFG_MCIO1_VAL, + + 0, 0 + }; + int i, rc; + +#ifdef CONFIG_EXADRON1 + int cardDetect; + volatile unsigned int *v_pBCRReg = + (volatile unsigned int *) 0x08000000; +#endif + + debug ("%s\n", __FUNCTION__); + + i = 0; + while (reg_arr[i]) + *((volatile unsigned int *) reg_arr[i++]) |= reg_arr[i++]; + udelay (1000); + + debug ("%s: programmed mem controller \n", __FUNCTION__); + +#ifdef CONFIG_EXADRON1 + +/*define useful BCR masks */ +#define BCR_CF_INIT_VAL 0x00007230 +#define BCR_CF_PWRON_BUSOFF_RESETOFF_VAL 0x00007231 +#define BCR_CF_PWRON_BUSOFF_RESETON_VAL 0x00007233 +#define BCR_CF_PWRON_BUSON_RESETON_VAL 0x00007213 +#define BCR_CF_PWRON_BUSON_RESETOFF_VAL 0x00007211 + + /* we see from the GPIO bit if the card is present */ + cardDetect = !(GPLR0 & GPIO_bit (14)); + + if (cardDetect) { + printf ("No PCMCIA card found!\n"); + } + + /* reset the card via the BCR line */ + *v_pBCRReg = (unsigned) BCR_CF_INIT_VAL; + msWait (500); + + *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETOFF_VAL; + msWait (500); + + *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETON_VAL; + msWait (500); + + *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETON_VAL; + msWait (500); + + *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETOFF_VAL; + msWait (1500); + + /* enable address bus */ + GPCR1 = 0x01; + /* and the first CF slot */ + MECR = 0x00000002; + +#endif /* EXADRON 1 */ + + rc = check_ide_device (0); /* use just slot 0 */ + + return rc; +} + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +int pcmcia_off (void) +{ + return 0; +} +#endif + +#endif /* CONFIG_PXA_PCMCIA */ diff --git a/drivers/rpx_pcmcia.c b/drivers/rpx_pcmcia.c new file mode 100644 index 0000000..2a0a9e0 --- /dev/null +++ b/drivers/rpx_pcmcia.c @@ -0,0 +1,73 @@ +/* -------------------------------------------------------------------- */ +/* RPX Boards from Embedded Planet */ +/* -------------------------------------------------------------------- */ +#include <common.h> +#ifdef CONFIG_8xx +#include <mpc8xx.h> +#endif +#include <pcmcia.h> + +#undef CONFIG_PCMCIA + +#if CONFIG_COMMANDS & CFG_CMD_PCMCIA +#define CONFIG_PCMCIA +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#define CONFIG_PCMCIA +#endif + +#if defined(CONFIG_PCMCIA) \ + && (defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)) + +#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE" + +int pcmcia_voltage_set(int slot, int vcc, int vpp) +{ + u_long reg = 0; + + switch(vcc) { + case 0: break; + case 33: reg |= BCSR1_PCVCTL4; break; + case 50: reg |= BCSR1_PCVCTL5; break; + default: return 1; + } + + switch(vpp) { + case 0: break; + case 33: + case 50: + if(vcc == vpp) + reg |= BCSR1_PCVCTL6; + else + return 1; + break; + case 120: + reg |= BCSR1_PCVCTL7; + default: return 1; + } + + /* first, turn off all power */ + *((uint *)RPX_CSR_ADDR) &= ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5 + | BCSR1_PCVCTL6 | BCSR1_PCVCTL7); + + /* enable new powersettings */ + *((uint *)RPX_CSR_ADDR) |= reg; + + return 0; +} + +int pcmcia_hardware_enable (int slot) +{ + return 0; /* No hardware to enable */ +} + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +static int pcmcia_hardware_disable(int slot) +{ + return 0; /* No hardware to disable */ +} +#endif /* CONFIG_COMMANDS & CFG_CMD_PCMCIA */ + + +#endif /* CONFIG_PCMCIA && (CONFIG_RPXCLASSIC || CONFIG_RPXLITE) */ diff --git a/drivers/rtl8139.c b/drivers/rtl8139.c index a95f84e..afe1a4f 100644 --- a/drivers/rtl8139.c +++ b/drivers/rtl8139.c @@ -196,6 +196,7 @@ static void rtl_disable(struct eth_device *dev); static struct pci_device_id supported[] = { {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139}, + {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139}, {} }; diff --git a/drivers/s3c4510b_eth.c b/drivers/s3c4510b_eth.c index 0274dd2..48901aa 100644 --- a/drivers/s3c4510b_eth.c +++ b/drivers/s3c4510b_eth.c @@ -175,7 +175,7 @@ s32 eth_send(volatile void *packet, s32 length) } /* copy user data into frame data pointer */ - memcpy((void *)eth->m_curTX_FD->m_frameDataPtr.bf.dataPtr, + memcpy((void *)(eth->m_curTX_FD->m_frameDataPtr.bf.dataPtr), (void *)packet, length); diff --git a/drivers/tqm8xx_pcmcia.c b/drivers/tqm8xx_pcmcia.c new file mode 100644 index 0000000..a0f53cd --- /dev/null +++ b/drivers/tqm8xx_pcmcia.c @@ -0,0 +1,330 @@ +/* -------------------------------------------------------------------- */ +/* TQM8xxL Boards by TQ Components */ +/* SC8xx Boards by SinoVee Microsystems */ +/* -------------------------------------------------------------------- */ +#include <common.h> +#ifdef CONFIG_8xx +#include <mpc8xx.h> +#endif +#include <pcmcia.h> + +#undef CONFIG_PCMCIA + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#define CONFIG_PCMCIA +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#define CONFIG_PCMCIA +#endif + +#if defined(CONFIG_PCMCIA) \ + && (defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)) + +#if defined(CONFIG_VIRTLAB2) +#define PCMCIA_BOARD_MSG "Virtlab2" +#elif defined(CONFIG_TQM8xxL) +#define PCMCIA_BOARD_MSG "TQM8xxL" +#elif defined(CONFIG_SVM_SC8xx) +#define PCMCIA_BOARD_MSG "SC8xx" +#endif + +#if defined(CONFIG_NSCU) + +#define power_config(slot) do {} while (0) +#define power_off(slot) do {} while (0) +#define power_on_5_0(slot) do {} while (0) +#define power_on_3_3(slot) do {} while (0) + +#elif defined(CONFIG_HMI10) + +static inline void power_config(int slot) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + /* + * Configure Port B pins for + * 5 Volts Enable and 3 Volts enable + */ + immap->im_cpm.cp_pbpar &= ~(0x00000300); +} + +static inline void power_off(int slot) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + /* remove all power */ + immap->im_cpm.cp_pbdat |= 0x00000300; +} + +static inline void power_on_5_0(int slot) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + immap->im_cpm.cp_pbdat &= ~(0x0000100); + immap->im_cpm.cp_pbdir |= 0x00000300; +} + +static inline void power_on_3_3(int slot) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + immap->im_cpm.cp_pbdat &= ~(0x0000200); + immap->im_cpm.cp_pbdir |= 0x00000300; +} + +#elif defined(CONFIG_VIRTLAB2) + +#define power_config(slot) do {} while (0) +static inline void power_off(int slot) +{ + volatile unsigned char *powerctl = + (volatile unsigned char *)PCMCIA_CTRL; + *powerctl = 0; +} + +static inline void power_on_5_0(int slot) +{ + volatile unsigned char *powerctl = + (volatile unsigned char *)PCMCIA_CTRL; + *powerctl = 2; /* Enable 5V Vccout */ +} + +static inline void power_on_3_3(int slot) +{ + volatile unsigned char *powerctl = + (volatile unsigned char *)PCMCIA_CTRL; + *powerctl = 1; /* Enable 3.3V Vccout */ +} + +#else + +static inline void power_config(int slot) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + /* + * Configure Port C pins for + * 5 Volts Enable and 3 Volts enable + */ + immap->im_ioport.iop_pcpar &= ~(0x0002 | 0x0004); + immap->im_ioport.iop_pcso &= ~(0x0002 | 0x0004); +} + +static inline void power_off(int slot) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004); +} + +static inline void power_on_5_0(int slot) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + immap->im_ioport.iop_pcdat |= 0x0004; + immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004); +} + +static inline void power_on_3_3(int slot) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + immap->im_ioport.iop_pcdat |= 0x0002; + immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004); +} + +#endif + +#ifdef CONFIG_HMI10 +static inline int check_card_is_absent(int slot) +{ + volatile pcmconf8xx_t *pcmp = + (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + return pcmp->pcmc_pipr & (0x10000000 >> (slot << 4)); +} +#else +static inline int check_card_is_absent(int slot) +{ + volatile pcmconf8xx_t *pcmp = + (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + return pcmp->pcmc_pipr & (0x18000000 >> (slot << 4)); +} +#endif + +#ifdef NSCU_OE_INV +#define NSCU_GCRX_CXOE 0 +#else +#define NSCU_GCRX_CXOE __MY_PCMCIA_GCRX_CXOE +#endif + +int pcmcia_hardware_enable(int slot) +{ + volatile pcmconf8xx_t *pcmp = + (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + volatile sysconf8xx_t *sysp = + (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + uint reg, mask; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + udelay(10000); + + /* + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ + sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(slot); + pcmp->pcmc_per &= ~PCMCIA_MASK(slot); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= NSCU_GCRX_CXOE; + + PCMCIA_PGCRX(slot) = reg; + udelay(500); + + power_config(slot); + power_off(slot); + + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); + + if (check_card_is_absent(slot)) { + printf (" No Card found\n"); + return (1); + } + + /* + * Power On. + */ + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + reg = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + reg, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); + + if ((reg & mask) == mask) { + power_on_5_0(slot); + puts (" 5.0V card found: "); + } else { + power_on_3_3(slot); + puts (" 3.3V card found: "); + } + +#if 0 + /* VCC switch error flag, PCMCIA slot INPACK_ pin */ + cp->cp_pbdir &= ~(0x0020 | 0x0010); + cp->cp_pbpar &= ~(0x0020 | 0x0010); + udelay(500000); +#endif + + udelay(1000); + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(slot); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + reg &= ~NSCU_GCRX_CXOE; + + PCMCIA_PGCRX(slot) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +int pcmcia_hardware_disable(int slot) +{ + u_long reg; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + + /* remove all power */ + power_off(slot); + + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= NSCU_GCRX_CXOE; /* active low */ + + PCMCIA_PGCRX(slot) = reg; + + udelay(10000); + + return (0); +} +#endif /* CFG_CMD_PCMCIA */ + +int pcmcia_voltage_set(int slot, int vcc, int vpp) +{ +#ifndef CONFIG_NSCU + u_long reg; +# ifdef DEBUG + volatile pcmconf8xx_t *pcmp = + (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); +# endif + + debug ("voltage_set: " PCMCIA_BOARD_MSG + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(slot); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + reg |= NSCU_GCRX_CXOE; /* active low */ + + PCMCIA_PGCRX(slot) = reg; + udelay(500); + + debug ("PCMCIA power OFF\n"); + power_config(slot); + power_off(slot); + + switch(vcc) { + case 0: break; + case 33: power_on_3_3(slot); break; + case 50: power_on_5_0(slot); break; + default: goto done; + } + + /* Checking supported voltages */ + + debug("PIPR: 0x%x --> %s\n", pcmp->pcmc_pipr, + (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); + + if (vcc) + debug("PCMCIA powered at %sV\n", (vcc == 50) ? "5.0" : "3.3"); + else + debug("PCMCIA powered down\n"); + +done: + debug("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(slot); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + reg &= ~NSCU_GCRX_CXOE; /* active low */ + + PCMCIA_PGCRX(slot) = reg; + udelay(500); + + debug("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", slot+'A'); +#endif /* CONFIG_NSCU */ + return (0); +} + +#endif /* CONFIG_PCMCIA && (CONFIG_TQM8xxL || CONFIG_SVM_SC8xx) */ diff --git a/drivers/tsec.c b/drivers/tsec.c index 7ec565c..a8a2ba2 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -14,6 +14,7 @@ #include <config.h> #include <mpc85xx.h> +#include <mpc86xx.h> #include <common.h> #include <malloc.h> #include <net.h> @@ -74,27 +75,33 @@ struct tsec_info_struct { static struct tsec_info_struct tsec_info[] = { #if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1) {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX}, +#elif defined(CONFIG_MPC86XX_TSEC1) + {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX}, #else { 0, 0, 0}, #endif #if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2) {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX}, +#elif defined(CONFIG_MPC86XX_TSEC2) + {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX}, #else { 0, 0, 0}, #endif #ifdef CONFIG_MPC85XX_FEC {FEC_PHY_ADDR, 0, FEC_PHYIDX}, #else -# if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) +#if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3) {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX}, -# else +#else { 0, 0, 0}, -# endif -# if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) +#endif +#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) {TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX}, -# else +#elif defined(CONFIG_MPC86XX_TSEC4) + {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX}, +#else { 0, 0, 0}, -# endif +#endif #endif }; @@ -365,7 +372,7 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private *priv) if (i > PHY_AUTONEGOTIATE_TIMEOUT) { puts (" TIMEOUT !\n"); priv->link = 0; - break; + return 0; } if ((i++ % 1000) == 0) { @@ -467,6 +474,32 @@ uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv) return 0; } +/* Parse the vsc8244's status register for speed and duplex + * information */ +uint mii_parse_vsc8244(uint mii_reg, struct tsec_private *priv) +{ + uint speed; + + if(mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) + priv->duplexity = 1; + else + priv->duplexity = 0; + + speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; + switch(speed) { + case MIIM_VSC8244_AUXCONSTAT_GBIT: + priv->speed = 1000; + break; + case MIIM_VSC8244_AUXCONSTAT_100: + priv->speed = 100; + break; + default: + priv->speed = 10; + break; + } + + return 0; +} /* Parse the DM9161's status register for speed and duplex @@ -859,6 +892,29 @@ struct phy_info phy_info_cis8201 = { {miim_end,} }, }; +struct phy_info phy_info_VSC8244 = { + 0x3f1b, + "Vitesse VSC8244", + 6, + (struct phy_cmd[]) { /* config */ + /* Override PHY config settings */ + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; struct phy_info phy_info_dm9161 = { @@ -1001,6 +1057,7 @@ struct phy_info *phy_info[] = { &phy_info_M88E1111S, &phy_info_dm9161, &phy_info_lxt971, + &phy_info_VSC8244, &phy_info_dp83865, NULL }; diff --git a/drivers/tsec.h b/drivers/tsec.h index b55b299..31f1867 100644 --- a/drivers/tsec.h +++ b/drivers/tsec.h @@ -27,7 +27,7 @@ #define TSEC_SIZE 0x01000 /* FIXME: Should these be pushed back to 83xx and 85xx config files? */ -#if defined(CONFIG_MPC85xx) +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET) #elif defined(CONFIG_MPC83XX) #define TSEC_BASE_ADDR (CFG_IMMRBAR + CFG_TSEC1_OFFSET) @@ -133,6 +133,24 @@ #define MIIM_GBIT_CON 0x09 #define MIIM_GBIT_CON_ADVERT 0x0e00 +/* Entry for Vitesse VSC8244 regs starts here */ +/* Vitesse VSC8244 Auxiliary Control/Status Register */ +#define MIIM_VSC8244_AUX_CONSTAT 0x1c +#define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000 +#define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020 +#define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018 +#define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010 +#define MIIM_VSC8244_AUXCONSTAT_100 0x0008 +#define MIIM_CONTROL_INIT_LOOPBACK 0x4000 + +/* Vitesse VSC8244 Extended PHY Control Register 1 */ +#define MIIM_VSC8244_EPHY_CON 0x17 +#define MIIM_VSC8244_EPHYCON_INIT 0x0006 + +/* Vitesse VSC8244 Serial LED Control Register */ +#define MIIM_VSC8244_LED_CON 0x1b +#define MIIM_VSC8244_LEDCON_INIT 0xF011 + /* 88E1011 PHY Status Register */ #define MIIM_88E1011_PHY_STATUS 0x11 #define MIIM_88E1011_PHYSTAT_SPEED 0xc000 diff --git a/include/405_mal.h b/include/405_mal.h index 69d20c9..0598586 100644 --- a/include/405_mal.h +++ b/include/405_mal.h @@ -92,11 +92,21 @@ #define MAL_ESR_PBEI 0x00000001 /* ^^ ^^ */ /* Mal IER */ +#ifdef CONFIG_440SPE +#define MAL_IER_PT 0x00000080 +#define MAL_IER_PRE 0x00000040 +#define MAL_IER_PWE 0x00000020 +#define MAL_IER_DE 0x00000010 +#define MAL_IER_OTE 0x00000004 +#define MAL_IER_OE 0x00000002 +#define MAL_IER_PE 0x00000001 +#else #define MAL_IER_DE 0x00000010 #define MAL_IER_NE 0x00000008 #define MAL_IER_TE 0x00000004 #define MAL_IER_OPBE 0x00000002 #define MAL_IER_PLBE 0x00000001 +#endif /* MAL Channel Active Set and Reset Registers */ #define MAL_TXRX_CASR (0x80000000) diff --git a/include/ahci.h b/include/ahci.h new file mode 100644 index 0000000..80701e2 --- /dev/null +++ b/include/ahci.h @@ -0,0 +1,190 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * Author: Jason Jin<Jason.jin@freescale.com> + * Zhang Wei<wei.zhang@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#ifndef _AHCI_H_ +#define _AHCI_H_ + +#define AHCI_PCI_BAR 0x24 +#define AHCI_MAX_SG 56 /* hardware max is 64K */ +#define AHCI_CMD_SLOT_SZ 32 +#define AHCI_RX_FIS_SZ 256 +#define AHCI_CMD_TBL_HDR 0x80 +#define AHCI_CMD_TBL_CDB 0x40 +#define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16) +#define AHCI_PORT_PRIV_DMA_SZ AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ \ + + AHCI_RX_FIS_SZ +#define AHCI_CMD_ATAPI (1 << 5) +#define AHCI_CMD_WRITE (1 << 6) +#define AHCI_CMD_PREFETCH (1 << 7) +#define AHCI_CMD_RESET (1 << 8) +#define AHCI_CMD_CLR_BUSY (1 << 10) + +#define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */ + +/* Global controller registers */ +#define HOST_CAP 0x00 /* host capabilities */ +#define HOST_CTL 0x04 /* global host control */ +#define HOST_IRQ_STAT 0x08 /* interrupt status */ +#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ +#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */ + +/* HOST_CTL bits */ +#define HOST_RESET (1 << 0) /* reset controller; self-clear */ +#define HOST_IRQ_EN (1 << 1) /* global IRQ enable */ +#define HOST_AHCI_EN (1 << 31) /* AHCI enabled */ + +/* Registers for each SATA port */ +#define PORT_LST_ADDR 0x00 /* command list DMA addr */ +#define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */ +#define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */ +#define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */ +#define PORT_IRQ_STAT 0x10 /* interrupt status */ +#define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */ +#define PORT_CMD 0x18 /* port command */ +#define PORT_TFDATA 0x20 /* taskfile data */ +#define PORT_SIG 0x24 /* device TF signature */ +#define PORT_CMD_ISSUE 0x38 /* command issue */ +#define PORT_SCR 0x28 /* SATA phy register block */ +#define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */ +#define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */ +#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */ +#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */ + +/* PORT_IRQ_{STAT,MASK} bits */ +#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */ +#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ +#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */ +#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ +#define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */ +#define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */ +#define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */ +#define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */ + +#define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */ +#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ +#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */ +#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ +#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ +#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ +#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ +#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ +#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ + +#define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \ + | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR + +#define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \ + | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \ + | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \ + | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \ + | PORT_IRQ_D2H_REG_FIS + +/* PORT_CMD bits */ +#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */ +#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */ +#define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */ +#define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */ +#define PORT_CMD_CLO (1 << 3) /* Command list override */ +#define PORT_CMD_POWER_ON (1 << 2) /* Power up device */ +#define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */ +#define PORT_CMD_START (1 << 0) /* Enable port DMA engine */ + +#define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */ +#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */ +#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */ + +#define AHCI_MAX_PORTS 32 + +/* SETFEATURES stuff */ +#define SETFEATURES_XFER 0x03 +#define XFER_UDMA_7 0x47 +#define XFER_UDMA_6 0x46 +#define XFER_UDMA_5 0x45 +#define XFER_UDMA_4 0x44 +#define XFER_UDMA_3 0x43 +#define XFER_UDMA_2 0x42 +#define XFER_UDMA_1 0x41 +#define XFER_UDMA_0 0x40 +#define XFER_MW_DMA_2 0x22 +#define XFER_MW_DMA_1 0x21 +#define XFER_MW_DMA_0 0x20 +#define XFER_SW_DMA_2 0x12 +#define XFER_SW_DMA_1 0x11 +#define XFER_SW_DMA_0 0x10 +#define XFER_PIO_4 0x0C +#define XFER_PIO_3 0x0B +#define XFER_PIO_2 0x0A +#define XFER_PIO_1 0x09 +#define XFER_PIO_0 0x08 +#define XFER_PIO_SLOW 0x00 + +#define ATA_FLAG_SATA (1 << 3) +#define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */ +#define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */ +#define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */ +#define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */ +#define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */ + +struct ahci_cmd_hdr { + u32 opts; + u32 status; + u32 tbl_addr; + u32 tbl_addr_hi; + u32 reserved[4]; +}; + +struct ahci_sg { + u32 addr; + u32 addr_hi; + u32 reserved; + u32 flags_size; +}; + +struct ahci_ioports { + u32 cmd_addr; + u32 scr_addr; + u32 port_mmio; + struct ahci_cmd_hdr *cmd_slot; + struct ahci_sg *cmd_tbl_sg; + u32 cmd_tbl; + u32 rx_fis; +}; + +struct ahci_probe_ent { + pci_dev_t dev; + struct ahci_ioports port[AHCI_MAX_PORTS]; + u32 n_ports; + u32 hard_port_no; + u32 host_flags; + u32 host_set_flags; + u32 mmio_base; + u32 pio_mask; + u32 udma_mask; + u32 flags; + u32 cap; /* cache of HOST_CAP register */ + u32 port_map; /* cache of HOST_PORTS_IMPL reg */ + u32 link_port_map; /*linkup port map*/ +}; + +#endif diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h new file mode 100644 index 0000000..5b1f0f4 --- /dev/null +++ b/include/asm-ppc/immap_86xx.h @@ -0,0 +1,1364 @@ +/* + * MPC86xx Internal Memory Map + * + * Copyright(c) 2004 Freescale Semiconductor + * Jeff Brown (Jeffrey@freescale.com) + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + */ + +#ifndef __IMMAP_86xx__ +#define __IMMAP_86xx__ + + +/* Local-Access Registers and MCM Registers(0x0000-0x2000) */ +typedef struct ccsr_local_mcm { + uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */ + char res1[4]; + uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */ + char res2[4]; + uint altcar; /* 0x10 - Alternate Configuration Attribute Register */ + char res3[12]; + uint bptr; /* 0x20 - Boot Page Translation Register */ + char res4[3044]; + uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */ + char res5[4]; + uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */ + char res6[20]; + uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */ + char res7[4]; + uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */ + char res8[20]; + uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */ + char res9[4]; + uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */ + char res10[20]; + uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */ + char res11[4]; + uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */ + char res12[20]; + uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */ + char res13[4]; + uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */ + char res14[20]; + uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */ + char res15[4]; + uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */ + char res16[20]; + uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */ + char res17[4]; + uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */ + char res18[20]; + uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ + char res19[4]; + uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ + char res20[20]; + uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */ + char res21[4]; + uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */ + char res22[20]; + uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ + char res23[4]; + uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ + char res24[716]; + uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */ + char res25[4]; + uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */ + char res26[4]; + uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */ + char res27[44]; + uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */ + uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */ + uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */ + uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */ + char res28[16]; + uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */ + uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */ + uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */ + char res29[3476]; + uint edr; /* 0x1e00 - MCM Error Detect Register */ + char res30[4]; + uint eer; /* 0x1e08 - MCM Error Enable Register */ + uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */ + uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */ + uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */ + char res31[488]; +} ccsr_local_mcm_t; + +/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */ + +typedef struct ccsr_ddr { + uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */ + char res1[4]; + uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */ + char res2[4]; + uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */ + char res3[4]; + uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */ + char res4[4]; + uint cs4_bnds; /* 0x2020 - DDR Chip Select 4 Memory Bounds */ + char res5[4]; + uint cs5_bnds; /* 0x2028 - DDR Chip Select 5 Memory Bounds */ + char res6[84]; + uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */ + uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */ + uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */ + uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ + uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */ + uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */ + char res7[104]; + uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */ + uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ + uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ + uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ + uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */ + uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ + uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */ + uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */ + uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */ + uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ + uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */ + char res8[4]; + uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ + char res9[12]; + uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ + uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ + uint init_addr; /* 0x2148 - DDR training initialzation address */ + uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */ + char res10[2728]; + uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ + uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ + char res11[512]; + uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */ + uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */ + uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */ + char res12[20]; + uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */ + uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */ + uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */ + char res13[20]; + uint err_detect; /* 0x2e40 - DDR Memory Error Detect */ + uint err_disable; /* 0x2e44 - DDR Memory Error Disable */ + uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */ + uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */ + uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */ + uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ + uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */ + char res14[164]; + uint debug_1; /* 0x2f00 */ + uint debug_2; + uint debug_3; + uint debug_4; + uint debug_5; + char res15[236]; +} ccsr_ddr_t; + + +/* Daul I2C Registers(0x3000-0x4000) */ + +typedef struct ccsr_i2c { + u_char i2cadr1; /* 0x3000 - I2C 1 Address Register */ +#define MPC86xx_I2CADR_MASK 0xFE + char res1[3]; + u_char i2cfdr1; /* 0x3004 - I2C 1 Frequency Divider Register */ +#define MPC86xx_I2CFDR_MASK 0x3F + char res2[3]; + u_char i2ccr1; /* 0x3008 - I2C 1 Control Register */ +#define MPC86xx_I2CCR_MEN 0x80 +#define MPC86xx_I2CCR_MIEN 0x40 +#define MPC86xx_I2CCR_MSTA 0x20 +#define MPC86xx_I2CCR_MTX 0x10 +#define MPC86xx_I2CCR_TXAK 0x08 +#define MPC86xx_I2CCR_RSTA 0x04 +#define MPC86xx_I2CCR_BCST 0x01 + char res3[3]; + u_char i2csr1; /* 0x300c - I2C 1 Status Register */ +#define MPC86xx_I2CSR_MCF 0x80 +#define MPC86xx_I2CSR_MAAS 0x40 +#define MPC86xx_I2CSR_MBB 0x20 +#define MPC86xx_I2CSR_MAL 0x10 +#define MPC86xx_I2CSR_BCSTM 0x08 +#define MPC86xx_I2CSR_SRW 0x04 +#define MPC86xx_I2CSR_MIF 0x02 +#define MPC86xx_I2CSR_RXAK 0x01 + char res4[3]; + u_char i2cdr1; /* 0x3010 - I2C 1 Data Register */ +#define MPC86xx_I2CDR_DATA 0xFF + char res5[3]; + u_char i2cdfsrr1; /* 0x3014 - I2C 1 Digital Filtering Sampling Rate Register */ +#define MPC86xx_I2CDFSRR 0x3F + char res6[235]; + + u_char i2cadr2; /* 0x3100 - I2C 2 Address Register */ + char res7[3]; + u_char i2cfdr2; /* 0x3104 - I2C 2 Frequency Divider Register */ + char res8[3]; + u_char i2ccr2; /* 0x3108 - I2C 2 Control Register */ + char res9[3]; + u_char i2csr2; /* 0x310c - I2C 2 Status Register */ + char res10[3]; + u_char i2cdr2; /* 0x3110 - I2C 2 Data Register */ + char res11[3]; + u_char i2cdfsrr2; /* 0x3114 - I2C 2 Digital Filtering Sampling Rate Register */ + char res12[3819]; +} ccsr_i2c_t; + +/* DUART Registers(0x4000-0x5000) */ +typedef struct ccsr_duart { + char res1[1280]; + u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */ + u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */ + u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */ + u_char ulcr1; /* 0x4503 - UART1 Line Control Register */ + u_char umcr1; /* 0x4504 - UART1 Modem Control Register */ + u_char ulsr1; /* 0x4505 - UART1 Line Status Register */ + u_char umsr1; /* 0x4506 - UART1 Modem Status Register */ + u_char uscr1; /* 0x4507 - UART1 Scratch Register */ + char res2[8]; + u_char udsr1; /* 0x4510 - UART1 DMA Status Register */ + char res3[239]; + u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */ + u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */ + u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */ + u_char ulcr2; /* 0x4603 - UART2 Line Control Register */ + u_char umcr2; /* 0x4604 - UART2 Modem Control Register */ + u_char ulsr2; /* 0x4605 - UART2 Line Status Register */ + u_char umsr2; /* 0x4606 - UART2 Modem Status Register */ + u_char uscr2; /* 0x4607 - UART2 Scratch Register */ + char res4[8]; + u_char udsr2; /* 0x4610 - UART2 DMA Status Register */ + char res5[2543]; +} ccsr_duart_t; + + +/* Local Bus Controller Registers(0x5000-0x6000) */ +typedef struct ccsr_lbc { + uint br0; /* 0x5000 - LBC Base Register 0 */ + uint or0; /* 0x5004 - LBC Options Register 0 */ + uint br1; /* 0x5008 - LBC Base Register 1 */ + uint or1; /* 0x500c - LBC Options Register 1 */ + uint br2; /* 0x5010 - LBC Base Register 2 */ + uint or2; /* 0x5014 - LBC Options Register 2 */ + uint br3; /* 0x5018 - LBC Base Register 3 */ + uint or3; /* 0x501c - LBC Options Register 3 */ + uint br4; /* 0x5020 - LBC Base Register 4 */ + uint or4; /* 0x5024 - LBC Options Register 4 */ + uint br5; /* 0x5028 - LBC Base Register 5 */ + uint or5; /* 0x502c - LBC Options Register 5 */ + uint br6; /* 0x5030 - LBC Base Register 6 */ + uint or6; /* 0x5034 - LBC Options Register 6 */ + uint br7; /* 0x5038 - LBC Base Register 7 */ + uint or7; /* 0x503c - LBC Options Register 7 */ + char res1[40]; + uint mar; /* 0x5068 - LBC UPM Address Register */ + char res2[4]; + uint mamr; /* 0x5070 - LBC UPMA Mode Register */ + uint mbmr; /* 0x5074 - LBC UPMB Mode Register */ + uint mcmr; /* 0x5078 - LBC UPMC Mode Register */ + char res3[8]; + uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */ + uint mdr; /* 0x5088 - LBC UPM Data Register */ + char res4[8]; + uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */ + char res5[8]; + uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */ + uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */ + char res6[8]; + uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */ + uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */ + uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */ + uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */ + uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */ + char res7[12]; + uint lbcr; /* 0x50d0 - LBC Configuration Register */ + uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */ + char res8[3880]; +} ccsr_lbc_t; + +/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */ +typedef struct ccsr_pex { + uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */ + uint cfg_data; /* 0x8004 - PEX Configuration Data Register */ + char res1[4]; + uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */ + char res2[16]; + uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */ + uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */ + uint pme_msg_dis; /* 0x8028 - PEX PME & message disable register */ + uint pm_command; /* 0x802c - PEX PM Command register */ + char res3[3016]; + uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */ + uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */ + uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */ + uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */ + char res4[8]; + uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */ + char res5[12]; + uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */ + uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */ + uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */ + char res6[4]; + uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */ + char res7[12]; + uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */ + uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */ + uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */ + char res8[4]; + uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */ + char res9[12]; + uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */ + uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */ + uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */ + char res10[4]; + uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */ + char res11[12]; + uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */ + uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */ + uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */ + char res12[4]; + uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */ + char res13[12]; + char res14[256]; + uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */ + char res15[4]; + uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */ + uint piwbear3; /* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */ + uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */ + char res16[12]; + uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */ + char res17[4]; + uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */ + uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */ + uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */ + char res18[12]; + uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */ + char res19[4]; + uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */ + uint piwbear1; + uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */ + char res20[12]; + uint pedr; /* 0x8e00 - PEX Error Detect Register */ + char res21[4]; + uint peer; /* 0x8e08 - PEX Error Interrupt Enable Register */ + char res22[4]; + uint pecdr; /* 0x8e10 - PEX Error Disable Register */ + char res23[12]; + uint peer_stat; /* 0x8e20 - PEX Error Capture Status Register */ + char res24[4]; + uint perr_cap0; /* 0x8e28 - PEX Error Capture Register 0 */ + uint perr_cap1; /* 0x8e2c - PEX Error Capture Register 1 */ + uint perr_cap2; /* 0x8e30 - PEX Error Capture Register 2 */ + uint perr_cap3; /* 0x8e34 - PEX Error Capture Register 3 */ + char res25[452]; + char res26[4]; +} ccsr_pex_t; + +/* Hyper Transport Register Block (0xA000-0xB000) */ +typedef struct ccsr_ht { + uint hcfg_addr; /* 0xa000 - HT Configuration Address register */ + uint hcfg_data; /* 0xa004 - HT Configuration Data register */ + char res1[3064]; + uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */ + char res2[12]; + uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */ + char res3[12]; + uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */ + char res4[4]; + uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */ + char res5[4]; + uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */ + char res6[12]; + uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */ + char res7[4]; + uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */ + char res8[4]; + uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */ + char res9[12]; + uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */ + char res10[4]; + uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */ + char res11[4]; + uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */ + char res12[12]; + uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */ + char res13[4]; + uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */ + char res14[4]; + uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */ + char res15[236]; + uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */ + char res16[4]; + uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */ + char res17[4]; + uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */ + char res18[12]; + uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */ + char res19[4]; + uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */ + char res20[4]; + uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */ + char res21[12]; + uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */ + char res22[4]; + uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */ + char res23[4]; + uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */ + char res24[12]; + uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */ + char res25[4]; + uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */ + char res26[4]; + uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */ + char res27[12]; + uint hedr; /* 0xae00 - HT Error Detect register */ + char res28[4]; + uint heier; /* 0xae08 - HT Error Interrupt Enable register */ + char res29[4]; + uint hecdr; /* 0xae10 - HT Error Capture Disbale register */ + char res30[12]; + uint hecsr; /* 0xae20 - HT Error Capture Status register */ + char res31[4]; + uint hec0; /* 0xae28 - HT Error Capture 0 register */ + uint hec1; /* 0xae2c - HT Error Capture 1 register */ + uint hec2; /* 0xae30 - HT Error Capture 2 register */ + char res32[460]; +} ccsr_ht_t; + +/* DMA Registers(0x2_1000-0x2_2000) */ +typedef struct ccsr_dma { + char res1[256]; + uint mr0; /* 0x21100 - DMA 0 Mode Register */ + uint sr0; /* 0x21104 - DMA 0 Status Register */ + char res2[4]; + uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */ + uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */ + uint sar0; /* 0x21114 - DMA 0 Source Address Register */ + uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */ + uint dar0; /* 0x2111c - DMA 0 Destination Address Register */ + uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */ + char res3[4]; + uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */ + char res4[8]; + uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */ + char res5[4]; + uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */ + uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */ + uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */ + char res6[56]; + uint mr1; /* 0x21180 - DMA 1 Mode Register */ + uint sr1; /* 0x21184 - DMA 1 Status Register */ + char res7[4]; + uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */ + uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */ + uint sar1; /* 0x21194 - DMA 1 Source Address Register */ + uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */ + uint dar1; /* 0x2119c - DMA 1 Destination Address Register */ + uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */ + char res8[4]; + uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */ + char res9[8]; + uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */ + char res10[4]; + uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */ + uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */ + uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */ + char res11[56]; + uint mr2; /* 0x21200 - DMA 2 Mode Register */ + uint sr2; /* 0x21204 - DMA 2 Status Register */ + char res12[4]; + uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */ + uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */ + uint sar2; /* 0x21214 - DMA 2 Source Address Register */ + uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */ + uint dar2; /* 0x2121c - DMA 2 Destination Address Register */ + uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */ + char res13[4]; + uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */ + char res14[8]; + uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */ + char res15[4]; + uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */ + uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */ + uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */ + char res16[56]; + uint mr3; /* 0x21280 - DMA 3 Mode Register */ + uint sr3; /* 0x21284 - DMA 3 Status Register */ + char res17[4]; + uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */ + uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */ + uint sar3; /* 0x21294 - DMA 3 Source Address Register */ + uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */ + uint dar3; /* 0x2129c - DMA 3 Destination Address Register */ + uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */ + char res18[4]; + uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */ + char res19[8]; + uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */ + char res20[4]; + uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */ + uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */ + uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */ + char res21[56]; + uint dgsr; /* 0x21300 - DMA General Status Register */ + char res22[3324]; +} ccsr_dma_t; + +/* tsec1-4: 24000-28000 */ +typedef struct ccsr_tsec { + uint id; /* 0x24000 - Controller ID Register */ + char res1[12]; + uint ievent; /* 0x24010 - Interrupt Event Register */ + uint imask; /* 0x24014 - Interrupt Mask Register */ + uint edis; /* 0x24018 - Error Disabled Register */ + char res2[4]; + uint ecntrl; /* 0x24020 - Ethernet Control Register */ + char res2_1[4]; + uint ptv; /* 0x24028 - Pause Time Value Register */ + uint dmactrl; /* 0x2402c - DMA Control Register */ + uint tbipa; /* 0x24030 - TBI PHY Address Register */ + char res3[88]; + uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */ + char res4[8]; + uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */ + uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */ + char res4_1[4]; + uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */ + uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */ + char res5[84]; + uint tctrl; /* 0x24100 - Transmit Control Register */ + uint tstat; /* 0x24104 - Transmit Status Register */ + uint dfvlan; /* 0x24108 - Default VLAN control word */ + char res6[4]; + uint txic; /* 0x24110 - Transmit interrupt coalescing Register */ + uint tqueue; /* 0x24114 - Transmit Queue Control Register */ + char res7[40]; + uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */ + uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */ + char res8[52]; + uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */ + char res9[4]; + uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */ + char res10[4]; + uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */ + char res11[4]; + uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */ + char res12[4]; + uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */ + char res13[4]; + uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */ + char res14[4]; + uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */ + char res15[4]; + uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */ + char res16[4]; + uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */ + char res17[64]; + uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */ + uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */ + char res18[4]; + uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */ + char res19[4]; + uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */ + char res20[4]; + uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */ + char res21[4]; + uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */ + char res22[4]; + uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */ + char res23[4]; + uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */ + char res24[4]; + uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */ + char res25[192]; + uint rctrl; /* 0x24300 - Receive Control Register */ + uint rstat; /* 0x24304 - Receive Status Register */ + char res26[8]; + uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */ + uint rqueue; /* 0x24314 - Receive queue control register */ + char res27[24]; + uint rbifx; /* 0x24330 - Receive bit field extract control Register */ + uint rqfar; /* 0x24334 - Receive queue filing table address Register */ + uint rqfcr; /* 0x24338 - Receive queue filing table control Register */ + uint rqfpr; /* 0x2433c - Receive queue filing table property Register */ + uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */ + char res28[56]; + uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */ + char res29[4]; + uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */ + char res30[4]; + uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */ + char res31[4]; + uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */ + char res32[4]; + uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */ + char res33[4]; + uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */ + char res34[4]; + uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */ + char res35[4]; + uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */ + char res36[4]; + uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */ + char res37[64]; + uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */ + uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */ + char res38[4]; + uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */ + char res39[4]; + uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */ + char res40[4]; + uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */ + char res41[4]; + uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */ + char res42[4]; + uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */ + char res43[4]; + uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */ + char res44[4]; + uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */ + char res45[192]; + uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */ + uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */ + uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */ + uint hafdup; /* 0x2450c - Half Duplex Register */ + uint maxfrm; /* 0x24510 - Maximum Frame Length Register */ + char res46[12]; + uint miimcfg; /* 0x24520 - MII Management Configuration Register */ + uint miimcom; /* 0x24524 - MII Management Command Register */ + uint miimadd; /* 0x24528 - MII Management Address Register */ + uint miimcon; /* 0x2452c - MII Management Control Register */ + uint miimstat; /* 0x24530 - MII Management Status Register */ + uint miimind; /* 0x24534 - MII Management Indicator Register */ + uint ifctrl; /* 0x24538 - Interface Contrl Register */ + uint ifstat; /* 0x2453c - Interface Status Register */ + uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */ + uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */ + uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */ + uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */ + uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */ + uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */ + uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */ + uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */ + uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */ + uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */ + uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */ + uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */ + uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */ + uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */ + uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */ + uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */ + uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */ + uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */ + uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */ + uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */ + uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */ + uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */ + uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */ + uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */ + uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */ + uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */ + uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */ + uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */ + uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */ + uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */ + uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */ + uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */ + char res48[192]; + uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */ + uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */ + uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */ + uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */ + uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */ + uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */ + uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ + uint rbyt; /* 0x2469c - Receive Byte Counter */ + uint rpkt; /* 0x246a0 - Receive Packet Counter */ + uint rfcs; /* 0x246a4 - Receive FCS Error Counter */ + uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */ + uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */ + uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */ + uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */ + uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */ + uint raln; /* 0x246bc - Receive Alignment Error Counter */ + uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */ + uint rcde; /* 0x246c4 - Receive Code Error Counter */ + uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */ + uint rund; /* 0x246cc - Receive Undersize Packet Counter */ + uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */ + uint rfrg; /* 0x246d4 - Receive Fragments Counter */ + uint rjbr; /* 0x246d8 - Receive Jabber Counter */ + uint rdrp; /* 0x246dc - Receive Drop Counter */ + uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */ + uint tpkt; /* 0x246e4 - Transmit Packet Counter */ + uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */ + uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */ + uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */ + uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */ + uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */ + uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */ + uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */ + uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */ + uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */ + uint tncl; /* 0x2470c - Transmit Total Collision Counter */ + char res49[4]; + uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */ + uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */ + uint tfcs; /* 0x2471c - Transmit FCS Error Counter */ + uint txcf; /* 0x24720 - Transmit Control Frame Counter */ + uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */ + uint tund; /* 0x24728 - Transmit Undersize Frame Counter */ + uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */ + uint car1; /* 0x24730 - Carry Register One */ + uint car2; /* 0x24734 - Carry Register Two */ + uint cam1; /* 0x24738 - Carry Mask Register One */ + uint cam2; /* 0x2473c - Carry Mask Register Two */ + uint rrej; /* 0x24740 - Receive filer rejected packet counter */ + char res50[188]; + uint iaddr0; /* 0x24800 - Indivdual address register 0 */ + uint iaddr1; /* 0x24804 - Indivdual address register 1 */ + uint iaddr2; /* 0x24808 - Indivdual address register 2 */ + uint iaddr3; /* 0x2480c - Indivdual address register 3 */ + uint iaddr4; /* 0x24810 - Indivdual address register 4 */ + uint iaddr5; /* 0x24814 - Indivdual address register 5 */ + uint iaddr6; /* 0x24818 - Indivdual address register 6 */ + uint iaddr7; /* 0x2481c - Indivdual address register 7 */ + char res51[96]; + uint gaddr0; /* 0x24880 - Global address register 0 */ + uint gaddr1; /* 0x24884 - Global address register 1 */ + uint gaddr2; /* 0x24888 - Global address register 2 */ + uint gaddr3; /* 0x2488c - Global address register 3 */ + uint gaddr4; /* 0x24890 - Global address register 4 */ + uint gaddr5; /* 0x24894 - Global address register 5 */ + uint gaddr6; /* 0x24898 - Global address register 6 */ + uint gaddr7; /* 0x2489c - Global address register 7 */ + char res52[352]; + uint fifocfg; /* 0x24A00 - FIFO interface configuration register */ + char res53[500]; + uint attr; /* 0x24BF8 - DMA Attribute register */ + uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */ + char res54[1024]; +} ccsr_tsec_t; + +/* PIC Registers(0x4_0000-0x6_1000) */ + +typedef struct ccsr_pic { + char res1[64]; + uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */ + char res2[12]; + uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */ + char res3[12]; + uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */ + char res4[12]; + uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */ + char res5[12]; + uint ctpr; /* 0x40080 - Current Task Priority Register */ + char res6[12]; + uint whoami; /* 0x40090 - Who Am I Register */ + char res7[12]; + uint iack; /* 0x400a0 - Interrupt Acknowledge Register */ + char res8[12]; + uint eoi; /* 0x400b0 - End Of Interrupt Register */ + char res9[3916]; + uint frr; /* 0x41000 - Feature Reporting Register */ + char res10[28]; + uint gcr; /* 0x41020 - Global Configuration Register */ + char res11[92]; + uint vir; /* 0x41080 - Vendor Identification Register */ + char res12[12]; + uint pir; /* 0x41090 - Processor Initialization Register */ + char res13[12]; + uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */ + char res14[12]; + uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */ + char res15[12]; + uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */ + char res16[12]; + uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */ + char res17[12]; + uint svr; /* 0x410e0 - Spurious Vector Register */ + char res18[12]; + uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */ + char res19[12]; + uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */ + char res20[12]; + uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */ + char res21[12]; + uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */ + char res22[12]; + uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */ + char res23[12]; + uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */ + char res24[12]; + uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */ + char res25[12]; + uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */ + char res26[12]; + uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */ + char res27[12]; + uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */ + char res28[12]; + uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */ + char res29[12]; + uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */ + char res30[12]; + uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */ + char res31[12]; + uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */ + char res32[12]; + uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */ + char res33[12]; + uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */ + char res34[12]; + uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */ + char res35[268]; + uint tcr; /* 0x41300 - Timer Control Register */ + char res36[12]; + uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */ + char res37[12]; + uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */ + char res38[12]; + uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */ + char res39[12]; + uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */ + char res40[12]; + uint pm0mr0; /* 0x41350 - Performance monitor 0 mask register 0 */ + char res41[12]; + uint pm0mr1; /* 0x41360 - Performance monitor 0 mask register 1 */ + char res42[12]; + uint pm1mr0; /* 0x41370 - Performance monitor 1 mask register 0 */ + char res43[12]; + uint pm1mr1; /* 0x41380 - Performance monitor 1 mask register 1 */ + char res44[12]; + uint pm2mr0; /* 0x41390 - Performance monitor 2 mask register 0 */ + char res45[12]; + uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */ + char res46[12]; + uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */ + char res47[12]; + uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */ + char res48[60]; + uint msgr0; /* 0x41400 - Message Register 0 */ + char res49[12]; + uint msgr1; /* 0x41410 - Message Register 1 */ + char res50[12]; + uint msgr2; /* 0x41420 - Message Register 2 */ + char res51[12]; + uint msgr3; /* 0x41430 - Message Register 3 */ + char res52[204]; + uint mer; /* 0x41500 - Message Enable Register */ + char res53[12]; + uint msr; /* 0x41510 - Message Status Register */ + char res54[60140]; + uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */ + char res55[12]; + uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */ + char res56[12]; + uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */ + char res57[12]; + uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */ + char res58[12]; + uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */ + char res59[12]; + uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */ + char res60[12]; + uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */ + char res61[12]; + uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */ + char res62[12]; + uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */ + char res63[12]; + uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */ + char res64[12]; + uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */ + char res65[12]; + uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */ + char res66[12]; + uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */ + char res67[12]; + uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */ + char res68[12]; + uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */ + char res69[12]; + uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */ + char res70[12]; + uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */ + char res71[12]; + uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */ + char res72[12]; + uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */ + char res73[12]; + uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */ + char res74[12]; + uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */ + char res75[12]; + uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */ + char res76[12]; + uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */ + char res77[12]; + uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */ + char res78[140]; + uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */ + char res79[12]; + uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */ + char res80[12]; + uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */ + char res81[12]; + uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */ + char res82[12]; + uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */ + char res83[12]; + uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */ + char res84[12]; + uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */ + char res85[12]; + uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */ + char res86[12]; + uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */ + char res87[12]; + uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */ + char res88[12]; + uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */ + char res89[12]; + uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */ + char res90[12]; + uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */ + char res91[12]; + uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */ + char res92[12]; + uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */ + char res93[12]; + uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */ + char res94[12]; + uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */ + char res95[12]; + uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */ + char res96[12]; + uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */ + char res97[12]; + uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */ + char res98[12]; + uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */ + char res99[12]; + uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */ + char res100[12]; + uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */ + char res101[12]; + uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */ + char res102[12]; + uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */ + char res103[12]; + uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */ + char res104[12]; + uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */ + char res105[12]; + uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */ + char res106[12]; + uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */ + char res107[12]; + uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */ + char res108[12]; + uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */ + char res109[12]; + uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */ + char res110[12]; + uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */ + char res111[12]; + uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */ + char res112[12]; + uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */ + char res113[12]; + uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */ + char res114[12]; + uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */ + char res115[12]; + uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */ + char res116[12]; + uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */ + char res117[12]; + uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */ + char res118[12]; + uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */ + char res119[12]; + uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */ + char res120[12]; + uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */ + char res121[12]; + uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */ + char res122[12]; + uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */ + char res123[12]; + uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */ + char res124[12]; + uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */ + char res125[12]; + uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */ + char res126[12]; + uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */ + char res127[12]; + uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */ + char res128[12]; + uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */ + char res129[12]; + uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */ + char res130[12]; + uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */ + char res131[12]; + uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */ + char res132[12]; + uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */ + char res133[12]; + uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */ + char res134[12]; + uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */ + char res135[12]; + uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */ + char res136[12]; + uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */ + char res137[12]; + uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */ + char res138[12]; + uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */ + char res139[12]; + uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */ + char res140[12]; + uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */ + char res141[12]; + uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */ + char res142[4108]; + uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */ + char res143[12]; + uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */ + char res144[12]; + uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */ + char res145[12]; + uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */ + char res146[12]; + uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */ + char res147[12]; + uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */ + char res148[12]; + uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */ + char res149[12]; + uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */ + char res150[59852]; + uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */ + char res151[12]; + uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */ + char res152[12]; + uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */ + char res153[12]; + uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */ + char res154[12]; + uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */ + char res155[12]; + uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */ + char res156[12]; + uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */ + char res157[12]; + uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */ + char res158[3916]; +} ccsr_pic_t; + +/* RapidIO Registers(0xc_0000-0xe_0000) */ + +typedef struct ccsr_rio { + uint didcar; /* 0xc0000 - Device Identity Capability Register */ + uint dicar; /* 0xc0004 - Device Information Capability Register */ + uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */ + uint aicar; /* 0xc000c - Assembly Information Capability Register */ + uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */ + uint spicar; /* 0xc0014 - Switch Port Information Capability Register */ + uint socar; /* 0xc0018 - Source Operations Capability Register */ + uint docar; /* 0xc001c - Destination Operations Capability Register */ + char res1[32]; + uint msr; /* 0xc0040 - Mailbox Command And Status Register */ + uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */ + char res2[4]; + uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */ + char res3[12]; + uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */ + uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */ + char res4[4]; + uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */ + uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */ + char res5[144]; + uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */ + char res6[28]; + uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */ + uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */ + char res7[20]; + uint pgccsr; /* 0xc013c - Port General Command and Status Register */ + uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */ + uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */ + uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */ + char res8[12]; + uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */ + uint pccsr; /* 0xc015c - Port Control Command and Status Register */ + char res9[1184]; + uint erbh; /* 0xc0600 - Error Reporting Block Header Register */ + char res10[4]; + uint ltledcsr; /* 0xc0608 - Logical/Transport layer error detect status register */ + uint ltleecsr; /* 0xc060c - Logical/Transport layer error enable register */ + char res11[4]; + uint ltlaccsr; /* 0xc0614 - Logical/Transport layer addresss capture register */ + uint ltldidccsr; /* 0xc0618 - Logical/Transport layer device ID capture register */ + uint ltlcccsr; /* 0xc061c - Logical/Transport layer control capture register */ + char res12[32]; + uint edcsr; /* 0xc0640 - Port 0 error detect status register */ + uint erecsr; /* 0xc0644 - Port 0 error rate enable status register */ + uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */ + uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */ + uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */ + uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */ + uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */ + char res13[12]; + uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */ + uint ertcsr; /* 0xc066C - Port 0 error rate threshold status register*/ + char res14[63892]; + uint llcr; /* 0xd0004 - Logical Layer Configuration Register */ + char res15[12]; + uint epwisr; /* 0xd0010 - Error / Port-Write Interrupt Status Register */ + char res16[12]; + uint lretcr; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */ + char res17[92]; + uint pretcr; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */ + char res18[124]; + uint adidcsr; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */ + char res19[28]; + uint ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */ + char res20[12]; + uint iecsr; /* 0xd0130 - Port 0 Implementation Error Status Register */ + char res21[12]; + uint pcr; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */ + char res22[20]; + uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */ + char res23[4]; + uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */ + char res24[2716]; + uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */ + uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */ + char res25[8]; + uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */ + char res26[12]; + uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */ + uint rowtear1; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */ + uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */ + char res27[4]; + uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */ + uint rows1r1; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */ + uint rows2r1; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */ + uint rows3r1; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */ + uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */ + uint rowtear2; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */ + uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */ + char res28[4]; + uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */ + uint rows1r2; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */ + uint rows2r2; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */ + uint rows3r2; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */ + uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */ + uint rowtear3; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */ + uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */ + char res29[4]; + uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */ + uint rows1r3; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */ + uint rows2r3; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */ + uint rows3r3; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */ + uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */ + uint rowtear4; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */ + uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */ + char res30[4]; + uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */ + uint rows1r4; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */ + uint rows2r4; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */ + uint rows3r4; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */ + uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */ + uint rowtear5; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */ + uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */ + char res31[4]; + uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */ + uint rows1r5; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */ + uint rows2r5; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */ + uint rows3r5; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */ + uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */ + uint rowtear6; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */ + uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */ + char res32[4]; + uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */ + uint rows1r6; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */ + uint rows2r6; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */ + uint rows3r6; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */ + uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */ + uint rowtear7; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */ + uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */ + char res33[4]; + uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */ + uint rows1r7; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */ + uint rows2r7; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */ + uint rows3r7; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */ + uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */ + uint rowtear8; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */ + uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */ + char res34[4]; + uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */ + uint rows1r8; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */ + uint rows2r8; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */ + uint rows3r8; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */ + char res35[64]; + uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */ + uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */ + char res36[4]; + uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */ + char res37[12]; + uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */ + char res38[4]; + uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */ + char res39[4]; + uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */ + char res40[12]; + uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */ + char res41[4]; + uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */ + char res42[4]; + uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */ + char res43[12]; + uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */ + char res44[4]; + uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */ + char res45[4]; + uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */ + char res46[12]; + uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */ + char res47[12]; + uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */ + char res48[12]; + uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */ + uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */ + uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */ + uint pecr; /* 0xd0e0c - Port Error Control Register */ + uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */ + uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */ + uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */ + char res49[4]; + uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */ + char res50[4]; + uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */ + uint prtr; /* 0xd0e2c - Port Retry Threshold Register */ + char res51[8656]; + uint omr; /* 0xd3000 - Outbound Mode Register */ + uint osr; /* 0xd3004 - Outbound Status Register */ + uint eodqtpar; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */ + uint odqtpar; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */ + uint eosar; /* 0xd3010 - Extended Outbound Unit Source Address Register */ + uint osar; /* 0xd3014 - Outbound Unit Source Address Register */ + uint odpr; /* 0xd3018 - Outbound Destination Port Register */ + uint odatr; /* 0xd301c - Outbound Destination Attributes Register */ + uint odcr; /* 0xd3020 - Outbound Doubleword Count Register */ + uint eodqhpar; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */ + uint odqhpar; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */ + uint oretr; /* 0xd302C - Outbound Retry Error Threshold Register */ + uint omgr; /* 0xd3030 - Outbound Multicast Group Register */ + uint omlr; /* 0xd3034 - Outbound Multicast List Register */ + char res52[40]; + uint imr; /* 0xd3060 - Outbound Mode Register */ + uint isr; /* 0xd3064 - Inbound Status Register */ + uint eidqtpar; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */ + uint idqtpar; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */ + uint eifqhpar; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */ + uint ifqhpar; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */ + uint imirir; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */ + char res53[900]; + uint oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */ + uint oddsr; /* 0xd3404 - Outbound Doorbell Status Register */ + char res54[16]; + uint oddpr; /* 0xd3418 - Outbound Doorbell Destination Port Register */ + uint oddatr; /* 0xd341C - Outbound Doorbell Destination Attributes Register */ + char res55[12]; + uint oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */ + char res56[48]; + uint idmr; /* 0xd3460 - Inbound Doorbell Mode Register */ + uint idsr; /* 0xd3464 - Inbound Doorbell Status Register */ + uint iedqtpar; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */ + uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */ + uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */ + uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */ + uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */ + char res57[100]; + uint pwmr; /* 0xd34e0 - Port-Write Mode Register */ + uint pwsr; /* 0xd34e4 - Port-Write Status Register */ + uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */ + uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */ + char res58[51984]; +} ccsr_rio_t; + +/* Global Utilities Register Block(0xe_0000-0xf_ffff) */ +typedef struct ccsr_gur { + uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ + uint porbmsr; /* 0xe0004 - POR boot mode status register */ +#define MPC86xx_PORBMSR_HA 0x00060000 + uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ + uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ +#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000 + uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ + char res1[12]; + uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ + char res2[12]; + uint gpiocr; /* 0xe0030 - GPIO control register */ + char res3[12]; + uint gpoutdr; /* 0xe0040 - General-purpose output data register */ + char res4[12]; + uint gpindr; /* 0xe0050 - General-purpose input data register */ + char res5[12]; + uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ + char res6[12]; + uint devdisr; /* 0xe0070 - Device disable control */ +#define MPC86xx_DEVDISR_PCIEX1 0x80000000 +#define MPC86xx_DEVDISR_PCIEX2 0x40000000 + char res7[12]; + uint powmgtcsr; /* 0xe0080 - Power management status and control register */ + char res8[12]; + uint mcpsumr; /* 0xe0090 - Machine check summary register */ + char res9[12]; + uint pvr; /* 0xe00a0 - Processor version register */ + uint svr; /* 0xe00a4 - System version register */ + char res10[3416]; + uint clkocr; /* 0xe0e00 - Clock out select register */ + char res11[12]; + uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ + char res12[12]; + uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */ + int res13[57]; + uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/ + int res14[6]; + uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ + char res15[61656]; +} ccsr_gur_t; + +typedef struct immap { + ccsr_local_mcm_t im_local_mcm; + ccsr_ddr_t im_ddr1; + ccsr_i2c_t im_i2c; + ccsr_duart_t im_duart; + ccsr_lbc_t im_lbc; + ccsr_ddr_t im_ddr2; + char res1[4096]; + ccsr_pex_t im_pex1; + ccsr_pex_t im_pex2; + ccsr_ht_t im_ht; + char res2[90112]; + ccsr_dma_t im_dma; + char res3[8192]; + ccsr_tsec_t im_tsec1; + ccsr_tsec_t im_tsec2; + ccsr_tsec_t im_tsec3; + ccsr_tsec_t im_tsec4; + char res4[98304]; + ccsr_pic_t im_pic; + char res5[389120]; + ccsr_rio_t im_rio; + ccsr_gur_t im_gur; +} immap_t; + +extern immap_t *immr; + +#endif /*__IMMAP_86xx__*/ diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 2606b79..5c38ce1 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -434,19 +434,28 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define BOOKE_PAGESZ_1GB 10 #define BOOKE_PAGESZ_4GB 11 +#if defined(CONFIG_MPC86xx) +#define LAWBAR_BASE_ADDR 0x00FFFFFF +#define LAWAR_TRGT_IF 0x01F00000 +#else #define LAWBAR_BASE_ADDR 0x000FFFFF -#define LAWAR_EN 0x80000000 #define LAWAR_TRGT_IF 0x00F00000 +#endif +#define LAWAR_EN 0x80000000 #define LAWAR_SIZE 0x0000003F #define LAWAR_TRGT_IF_PCI 0x00000000 #define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCI2 0x00100000 +#define LAWAR_TRGT_IF_HT 0x00200000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 +#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 #define LAWAR_TRGT_IF_RIO 0x00c00000 #define LAWAR_TRGT_IF_DDR 0x00f00000 +#define LAWAR_TRGT_IF_DDR1 0x00f00000 +#define LAWAR_TRGT_IF_DDR2 0x01600000 #define LAWAR_SIZE_BASE 0xa #define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1) @@ -469,5 +478,50 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18) #define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19) #define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20) +#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) +#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) +#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) +#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) + +#ifdef CONFIG_440SPE +/*----------------------------------------------------------------------------+ +| Following instructions are not available in Book E mode of the GNU assembler. ++----------------------------------------------------------------------------*/ +#define DCCCI(ra,rb) .long 0x7c000000|\ + (ra<<16)|(rb<<11)|(454<<1) + +#define ICCCI(ra,rb) .long 0x7c000000|\ + (ra<<16)|(rb<<11)|(966<<1) + +#define DCREAD(rt,ra,rb) .long 0x7c000000|\ + (rt<<21)|(ra<<16)|(rb<<11)|(486<<1) + +#define ICREAD(ra,rb) .long 0x7c000000|\ + (ra<<16)|(rb<<11)|(998<<1) + +#define TLBSX(rt,ra,rb) .long 0x7c000000|\ + (rt<<21)|(ra<<16)|(rb<<11)|(914<<1) + +#define TLBWE(rs,ra,ws) .long 0x7c000000|\ + (rs<<21)|(ra<<16)|(ws<<11)|(978<<1) + +#define TLBRE(rt,ra,ws) .long 0x7c000000|\ + (rt<<21)|(ra<<16)|(ws<<11)|(946<<1) + +#define TLBSXDOT(rt,ra,rb) .long 0x7c000001|\ + (rt<<21)|(ra<<16)|(rb<<11)|(914<<1) + +#define MSYNC .long 0x7c000000|\ + (598<<1) + +#define MBAR_INST .long 0x7c000000|\ + (854<<1) + +/*----------------------------------------------------------------------------+ +| Following instruction is not available in PPC405 mode of the GNU assembler. ++----------------------------------------------------------------------------*/ +#define TLBRE(rt,ra,ws) .long 0x7c000000|\ + (rt<<21)|(ra<<16)|(ws<<11)|(946<<1) +#endif #endif /* _PPC_MMU_H_ */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 9ff03af..6e1d610 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -264,6 +264,7 @@ #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ +#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ #define SPRN_LR 0x008 /* Link Register */ #define SPRN_MBAR 0x137 /* System memory base address */ @@ -443,6 +444,11 @@ #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ #define ESR_ST 0x00800000 /* Store Operation */ +#if defined(CONFIG_MPC86xx) +#define SPRN_MSSCRO 0x3f6 +#endif + + /* Short-hand versions for a number of the above SPRNs */ #define CTR SPRN_CTR /* Counter Register */ @@ -501,10 +507,14 @@ #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ +#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ #define L2CR SPRN_L2CR /* PPC 750 L2 control register */ #define LR SPRN_LR #define MBAR SPRN_MBAR /* System memory base address */ -#if defined(CONFIG_E500) +#if defined(CONFIG_MPC86xx) +#define MSSCR0 SPRN_MSSCRO +#endif +#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define PIR SPRN_PIR #endif #define SVR SPRN_SVR /* System-On-Chip Version Register */ @@ -538,7 +548,7 @@ #define CSRR0 SPRN_CSRR0 #define CSRR1 SPRN_CSRR1 #define IVPR SPRN_IVPR -#define USPRG0 SPRN_USPRG0 +#define USPRG0 SPRN_USPRG #define SPRG4R SPRN_SPRG4R #define SPRG5R SPRN_SPRG5R #define SPRG6R SPRN_SPRG6R @@ -735,6 +745,8 @@ #define PVR_405EP_RB 0x51210950 #define PVR_440SP_RA 0x53221850 #define PVR_440SP_RB 0x53221891 +#define PVR_440SPe_RA 0x53421890 +#define PVR_440SPe_RB 0x53421891 #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 @@ -757,6 +769,8 @@ #define PVR_85xx_REV1 (PVR_85xx | 0x0010) #define PVR_85xx_REV2 (PVR_85xx | 0x0020) +#define PVR_86xx 0x80040000 +#define PVR_86xx_REV1 (PVR_86xx | 0x0010) /* * For the 8xx processors, all of them report the same PVR family for @@ -810,6 +824,8 @@ #define SVR_8548 0x8031 #define SVR_8548_E 0x8039 +#define SVR_8641 0x8090 +#define SVR_8641D 0x8091 /* I am just adding a single entry for 8260 boards. I think we may be * able to combine mbx, fads, rpxlite, bseip, and classic into a single diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index f7aa55f..f335cd8 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -45,7 +45,7 @@ typedef struct bd_info { unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ #if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ - || defined(CONFIG_E500) + || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) unsigned long bi_immr_base; /* base of IMMR register */ #endif #if defined(CONFIG_MPC5xxx) diff --git a/include/bmp_logo.h b/include/bmp_logo.h deleted file mode 100644 index 9c924b8..0000000 --- a/include/bmp_logo.h +++ /dev/null @@ -1,1948 +0,0 @@ -/* - * Automatically generated by "tools/bmp_logo" - * - * DO NOT EDIT - * - */ - - -#ifndef __BMP_LOGO_H__ -#define __BMP_LOGO_H__ - -#define BMP_LOGO_WIDTH 160 -#define BMP_LOGO_HEIGHT 96 -#define BMP_LOGO_COLORS 31 -#define BMP_LOGO_OFFSET 16 - -unsigned short bmp_logo_palette[] = { - 0x0343, 0x0454, 0x0565, 0x0565, 0x0676, 0x0787, 0x0898, 0x0999, - 0x0AAA, 0x0ABA, 0x0BCB, 0x0CCC, 0x0DDD, 0x0EEE, 0x0FFF, 0x0FB3, - 0x0FB4, 0x0FC4, 0x0FC5, 0x0FC6, 0x0FD7, 0x0FD8, 0x0FD9, 0x0FDA, - 0x0FEA, 0x0FEB, 0x0FEC, 0x0FFD, 0x0FFE, 0x0FFF, 0x0FFF, -}; - -unsigned char bmp_logo_bitmap[] = { - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B, - 0x1B, 0x1B, 0x1B, 0x1B, 0x1B, 0x1B, 0x1B, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 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0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, - 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x10, 0x10, - 0x10, 0x14, 0x13, 0x10, 0x10, 0x10, 0x2E, 0x2E, - -}; - -#endif /* __BMP_LOGO_H__ */ diff --git a/include/common.h b/include/common.h index 5d8b156..8000dd0 100644 --- a/include/common.h +++ b/include/common.h @@ -79,6 +79,10 @@ typedef volatile unsigned char vu_char; #endif #include <asm/immap_8260.h> #endif +#ifdef CONFIG_MPC86xx +#include <mpc86xx.h> +#include <asm/immap_86xx.h> +#endif #ifdef CONFIG_MPC85xx #include <mpc85xx.h> #include <asm/immap_85xx.h> @@ -116,12 +120,13 @@ typedef void (interrupt_handler_t)(void *); /* * enable common handling for all TQM8xxL/M boards: - * - CONFIG_TQM8xxM will be defined for all TQM8xxM boards + * - CONFIG_TQM8xxM will be defined for all TQM8xxM and TQM885D boards * - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards */ #if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \ defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \ - defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) + defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) || \ + defined(CONFIG_TQM885D) # ifndef CONFIG_TQM8xxM # define CONFIG_TQM8xxM # endif @@ -193,6 +198,9 @@ int checkdram (void); char * strmhz(char *buf, long hz); int last_stage_init(void); extern ulong monitor_flash_len; +#ifdef CFG_ID_EEPROM +int mac_read_from_eeprom(void); +#endif /* common/flash.c */ void flash_perror (int); @@ -244,6 +252,9 @@ void pciinfo (int, int); void pci_master_init (struct pci_controller *); # endif int is_pci_host (struct pci_controller *); +#if defined(CONFIG_440SPE) + void pcie_setup_hoses(void); +#endif #endif int misc_init_f (void); @@ -366,6 +377,7 @@ void trap_init (ulong); defined (CONFIG_74xx) || \ defined (CONFIG_MPC8220) || \ defined (CONFIG_MPC85xx) || \ + defined (CONFIG_MPC86xx) || \ defined (CONFIG_MPC83XX) unsigned char in8(unsigned int); void out8(unsigned int, unsigned char); @@ -454,10 +466,19 @@ ulong get_bus_freq (ulong); typedef MPC85xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); #endif +#if defined(CONFIG_MPC86xx) +typedef MPC86xx_SYS_INFO sys_info_t; +void get_sys_info ( sys_info_t * ); +#endif #if defined(CONFIG_4xx) || defined(CONFIG_IOP480) # if defined(CONFIG_440) typedef PPC440_SYS_INFO sys_info_t; +# if defined(CONFIG_440SPE) + unsigned long determine_sysper(void); + unsigned long determine_pci_clock_per(void); + int ppc440spe_revB(void); +# endif # else typedef PPC405_SYS_INFO sys_info_t; # endif @@ -468,7 +489,7 @@ void get_sys_info ( sys_info_t * ); #if defined(CONFIG_8xx) || defined(CONFIG_8260) void cpu_init_f (volatile immap_t *immr); #endif -#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) +#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx) void cpu_init_f (void); #endif @@ -594,7 +615,7 @@ void show_boot_progress (int status); #endif #ifdef CONFIG_INIT_CRITICAL -#error CONFIG_INIT_CRITICAL is depracted! +#error CONFIG_INIT_CRITICAL is deprecated! #error Read section CONFIG_SKIP_LOWLEVEL_INIT in README. #endif diff --git a/include/commproc.h b/include/commproc.h index 061468e..12400e3 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -1405,15 +1405,16 @@ typedef struct scc_enet { #endif /* CONFIG_SXNI855T */ -/*** MVS1, TQM823L/M, TQM850L/M, ETX094, R360MPI *******************/ +/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI **********/ #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \ defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \ defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \ - defined(CONFIG_ETX094) || defined(CONFIG_RRVISION)|| \ - defined(CONFIG_VIRTLAB2)|| \ + defined(CONFIG_TQM885D) || defined(CONFIG_ETX094) || \ + defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \ (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2) + /* Bits in parallel I/O port registers that have to be set/cleared * to configure the pins for SCC2 use. */ @@ -1438,6 +1439,11 @@ typedef struct scc_enet { */ #define SICR_ENET_MASK ((uint)0x0000ff00) #define SICR_ENET_CLKRT ((uint)0x00002600) + +# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ +#define FEC_ENET +# endif /* CONFIG_FEC_ENET */ + #endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */ /*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/ diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h index 9a98e5c..7a1dada 100644 --- a/include/configs/CPU87.h +++ b/include/configs/CPU87.h @@ -455,7 +455,7 @@ #define CFG_MIN_AM_MASK 0xC0000000 /* - * we use the same values for 32 MB and 128 MB SDRAM + * we use the same values for 32 MB, 128 MB and 256 MB SDRAM * refresh rate = 7.68 uS (100 MHz Bus Clock) */ @@ -510,6 +510,24 @@ PSDMR_WRC_1C |\ PSDMR_CL_2) + /* SDRAM initialization values for 10-column chips + */ +#define CFG_OR2_10COL (CFG_MIN_AM_MASK |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A4 |\ + ORxS_NUMR_13) + +#define CFG_PSDMR_10COL (PSDMR_PBI |\ + PSDMR_SDAM_A17_IS_A5 |\ + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI1_A6 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + /* * Init Memory Controller: * @@ -588,9 +606,9 @@ BRx_MS_SDRAM_P |\ BRx_V) -#define CFG_OR2_PRELIM CFG_OR2_9COL +#define CFG_OR2_PRELIM CFG_OR2_8COL -#define CFG_PSDMR CFG_PSDMR_9COL +#define CFG_PSDMR CFG_PSDMR_8COL #endif /* CFG_RAMBOOT */ /* Bank 3 - Dual Ported SRAM diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h new file mode 100644 index 0000000..c704d46 --- /dev/null +++ b/include/configs/MPC8641HPCN.h @@ -0,0 +1,641 @@ +/* + * Copyright 2006 Freescale Semiconductor. + * + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * MPC8641HPCN board configuration file + * + * Make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_MPC86xx 1 /* MPC86xx */ +#define CONFIG_MPC8641 1 /* MPC8641 specific */ +#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ +#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ +#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ +#undef DEBUG + +#ifdef RUN_DIAG +#define CFG_DIAG_ADDR 0xff800000 +#endif + +#define CFG_RESET_ADDRESS 0xfff00100 + +/*#undef CONFIG_PCI*/ +#define CONFIG_PCI + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#undef CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_NUM_DDR_CONTROLLERS 2 +/* #define CONFIG_DDR_INTERLEAVE 1 */ +#define CACHE_LINE_INTERLEAVING 0x20000000 +#define PAGE_INTERLEAVING 0x21000000 +#define BANK_INTERLEAVING 0x22000000 +#define SUPER_BANK_INTERLEAVING 0x23000000 + + +#define CONFIG_ALTIVEC 1 + +/* + * L2CR setup -- make sure this is right for your board! + */ +#define CFG_L2 +#define L2_INIT 0 +#define L2_ENABLE (L2CR_L2E) + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) +#endif + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM + +#define MPC86xx_DDR_SDRAM_CLK_CNTL + +#if defined(CONFIG_SPD_EEPROM) + /* + * Determine DDR configuration from I2C interface. + */ + #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ + +#else + /* + * Manually set up DDR1 parameters + */ + + #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ + + #define CFG_DDR_CS0_BNDS 0x0000000F + #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ + #define CFG_DDR_EXT_REFRESH 0x00000000 + #define CFG_DDR_TIMING_0 0x00260802 + #define CFG_DDR_TIMING_1 0x39357322 + #define CFG_DDR_TIMING_2 0x14904cc8 + #define CFG_DDR_MODE_1 0x00480432 + #define CFG_DDR_MODE_2 0x00000000 + #define CFG_DDR_INTERVAL 0x06090100 + #define CFG_DDR_DATA_INIT 0xdeadbeef + #define CFG_DDR_CLK_CTRL 0x03800000 + #define CFG_DDR_OCD_CTRL 0x00000000 + #define CFG_DDR_OCD_STATUS 0x00000000 + #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ + #define CFG_DDR_CONTROL2 0x04400000 + + /* Not used in fixed_sdram function */ + + #define CFG_DDR_MODE 0x00000022 + #define CFG_DDR_CS1_BNDS 0x00000000 + #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ + #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ + #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ + #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ +#endif + +#define CFG_ID_EEPROM 1 +#define ID_EEPROM_ADDR 0x57 + +/* + * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000. + * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff + * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. + * However, when u-boot comes up, the flash_init needs hard start addresses + * to build its info table. For user convenience, the flash addresses is + * fe800000 and ff800000. That way, u-boot knows where the flash is + * and the user can download u-boot code from promjet to fef00000, a + * more intuitive location than fe700000. + * + * Note that, on switching the boot location, fef00000 becomes fff00000. + */ +#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ +#define CFG_FLASH_BASE2 0xff800000 + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} + +#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ +#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ + +#define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */ +#define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/ + +#define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ +#define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ + +#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ +#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ + + +#define PIXIS_BASE 0xf8100000 /* PIXIS registers */ +#define PIXIS_ID 0x0 /* Board ID at offset 0 */ +#define PIXIS_VER 0x1 /* Board version at offset 1 */ +#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ +#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ +#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ +#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ +#define PIXIS_VCTL 0x10 /* VELA Control Register */ +#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ +#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ +#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ +#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ +#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ +#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ +#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ + +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#if defined(CFG_RAMBOOT) +#undef CFG_FLASH_CFI_DRIVER +#undef CONFIG_SPD_EEPROM +#define CFG_SDRAM_SIZE 256 +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#ifndef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ +#else +#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ +#endif +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree to kernel + */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8641@0" +#define OF_SOC "soc8641@f8000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" + +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + +/* + * I2C + */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/* + * RapidIO MMU + */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +/* For RTL8139 */ +#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) +#define _IO_BASE 0x00000000 + +#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_IO_BASE 0xe3000000 +#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ + + +#if defined(CONFIG_PCI) + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#undef CFG_SCSI_SCAN_BUS_REVERSE + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_RTL8139 + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#define CONFIG_DOS_PARTITION +#define CONFIG_SCSI_AHCI + +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_SATA_ULI5288 +#define CFG_SCSI_MAX_SCSI_ID 4 +#define CFG_SCSI_MAX_LUN 1 +#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) +#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE +#endif + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ + +#define CONFIG_MPC86XX_TSEC1 1 +#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1" +#define CONFIG_MPC86XX_TSEC2 1 +#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2" +#define CONFIG_MPC86XX_TSEC3 1 +#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3" +#define CONFIG_MPC86XX_TSEC4 1 +#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC3_PHY_ADDR 2 +#define TSEC4_PHY_ADDR 3 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#endif /* CONFIG_TSEC_ENET */ + + +/* + * BAT0 2G Cacheable, non-guarded + * 0x0000_0000 2G DDR + */ +#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) +#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) +#define CFG_IBAT0U CFG_DBAT0U + +/* + * BAT1 1G Cache-inhibited, guarded + * 0x8000_0000 512M PCI-Express 1 Memory + * 0xa000_0000 512M PCI-Express 2 Memory + * Changed it for operating from 0xd0000000 + */ +#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT1U CFG_DBAT1U + +/* + * BAT2 512M Cache-inhibited, guarded + * 0xc000_0000 512M RapidIO Memory + */ +#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT2U CFG_DBAT2U + +/* + * BAT3 4M Cache-inhibited, guarded + * 0xf800_0000 4M CCSR + */ +#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT3U CFG_DBAT3U + +/* + * BAT4 32M Cache-inhibited, guarded + * 0xe200_0000 16M PCI-Express 1 I/O + * 0xe300_0000 16M PCI-Express 2 I/0 + * Note that this is at 0xe0000000 + */ +#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT4U CFG_DBAT4U + +/* + * BAT5 128K Cacheable, non-guarded + * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) + */ +#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_IBAT5L CFG_DBAT5L +#define CFG_IBAT5U CFG_DBAT5U + +/* + * BAT6 32M Cache-inhibited, guarded + * 0xfe00_0000 32M FLASH + */ +#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT6U CFG_DBAT6U + +#define CFG_DBAT7L 0x00000000 +#define CFG_DBAT7U 0x00000000 +#define CFG_IBAT7L 0x00000000 +#define CFG_IBAT7U 0x00000000 + + + + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C \ + | CFG_CMD_SCSI \ + | CFG_CMD_EXT2) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_IMLS \ + | CFG_CMD_FLASH \ + | CFG_CMD_LOADS)) + #else + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_SCSI \ + | CGF_CMD_EXT2) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_IMLS \ + | CFG_CMD_FLASH \ + | CFG_CMD_LOADS)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_SCSI \ + | CFG_CMD_EXT2) + #else + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #endif +#endif + +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:E0:0C:00:00:01 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD +#endif + +#define CONFIG_HAS_ETH1 1 +#define CONFIG_HAS_ETH2 1 +#define CONFIG_HAS_ETH3 1 + +#define CONFIG_IPADDR 192.168.1.100 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "dtbaddr=400000\0" \ + "dtbfile=mpc8641_hpcn.dtb\0" \ + "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ + "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ + "maxcpus=2" + + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr - $dtbaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr $ramdiskaddr $dtbaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h new file mode 100644 index 0000000..8a6e5a6 --- /dev/null +++ b/include/configs/TB5200.h @@ -0,0 +1,507 @@ +/* + * (C) Copyright 2003-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004-2006 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ +#define CONFIG_TB5200 1 /* ... on a TB5200 base board */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* default console is on PSC1 */ +#define CONFIG_SERIAL_MULTI 1 /* support multiple consoles */ +#define CONFIG_PSC_CONSOLE2 6 /* second console is on PSC6 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * Video console + */ +#if 1 +#define CONFIG_VIDEO +#define CONFIG_VIDEO_SM501 +#define CONFIG_VIDEO_SM501_32BPP +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_CONSOLE_EXTRA_INFO +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_SPLASH_SCREEN +#define CFG_CONSOLE_IS_IN_ENV +#endif + +#ifdef CONFIG_VIDEO +#define ADD_BMP_CMD CFG_CMD_BMP +#else +#define ADD_BMP_CMD 0 +#endif + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +/* USB */ +#define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +#define CONFIG_USB_STORAGE + +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_I2C) + +#ifdef CONFIG_POST +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG +/* preserve space for the post_word at end of on-chip SRAM */ +#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 +#else +#define CFG_CMD_POST_DIAG 0 +#endif + +/* IDE */ +#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2) + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + ADD_BMP_CMD | \ + ADD_IDE_CMD | \ + ADD_PCI_CMD | \ + ADD_USB_CMD | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SNTP | \ + CFG_CMD_BSP) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_TIMESTAMP /* display image timestamps */ + +#if (TEXT_BASE == 0xFC000000) /* Boot low */ +# define CFG_LOWBOOT 1 +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#if defined(CONFIG_TQM5200_B) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "bootfile=/tftpboot/tqm5200/uImage\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ + "update=protect off FC000000 FC07FFFF;" \ + "erase FC000000 FC07FFFF;" \ + "cp.b 200000 FC000000 ${filesize};" \ + "protect on FC000000 FC07FFFF\0" \ + "" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "bootfile=/tftpboot/tqm5200/uImage\0" \ + "load=tftp 200000 $(u-boot)\0" \ + "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ + "update=protect off FC000000 FC05FFFF;" \ + "erase FC000000 FC05FFFF;" \ + "cp.b 200000 FC000000 ${filesize};" \ + "protect on FC000000 FC05FFFF\0" \ + "" +#endif /* CONFIG_TQM5200_B */ + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +/* + * IPB Bus clocking configuration. + */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ + +#if defined(CFG_IPBSPEED_133) +/* + * PCI Bus clocking configuration + * + * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if + * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't + * been tested with a IPB Bus Clock of 66 MHz. + */ +#define CFG_PCISPEED_66 /* define for 66MHz speed */ +#endif + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #2 */ + +/* + * I2C clock frequency + * + * Please notice, that the resulting clock frequency could differ from the + * configured value. This is because the I2C clock is derived from system + * clock over a frequency divider with only a few divider values. U-boot + * calculates the best approximation for CFG_I2C_SPEED. However the calculated + * approximation allways lies below the configured value, never above. + */ +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work + * also). For other EEPROMs configuration should be verified. On Mini-FAP the + * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the + * same configuration could be used. + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 + +/* List of I2C addresses to be verified by POST */ +#undef I2C_ADDR_LIST +#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ + CFG_I2C_RTC_ADDR, \ + CFG_I2C_SLAVE } + +/* + * Flash configuration + */ +#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ + +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 + +#if !defined(CFG_LOWBOOT) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) +#else /* CFG_LOWBOOT */ +#if defined(CONFIG_TQM5200_B) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00080000) +#else +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) +#endif /* CONFIG_TQM5200_B */ +#endif /* CFG_LOWBOOT */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ + +/* Dynamic MTD partition support */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM5200-0" +#if defined(CONFIG_TQM5200_B) +#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \ + "1280k(kernel)," \ + "2m(initrd)," \ + "4m(small-fs)," \ + "16m(big-fs)," \ + "8m(misc)" +#else +#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ + "1408k(kernel)," \ + "2m(initrd)," \ + "4m(small-fs)," \ + "16m(big-fs)," \ + "8m(misc)" +#endif /* CONFIG_TQM5200_B */ + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x10000 +#if defined(CONFIG_TQM5200_B) +#define CFG_ENV_SECT_SIZE 0x40000 +#else +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CONFIG_TQM5200_B */ + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use ON-Chip SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#ifdef CONFIG_POST +/* preserve space for the post_word at end of on-chip SRAM */ +#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE +#else +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE +#endif + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#if defined(CONFIG_TQM5200_B) +#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ +#else +#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ +#endif /* CONFIG_TQM5200_B */ +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 0x00 + +/* + * GPIO configuration + * + * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): + * Bit 0 (mask: 0x80000000): 1 + * use ALT CAN position: Bits 2-3 (mask: 0x30000000): + * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. + * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. + * Use for REV200 STK52XX boards. Do not use with REV100 modules + * (because, there I2C1 is used as I2C bus) + * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 + * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) + * 000 -> All PSC2 pins are GIOPs + * 001 -> CAN1/2 on PSC2 pins + * Use for REV100 STK52xx boards + * use PSC3: Bits 20:23 (mask: 0x00000300): + * 0001 -> USB2 + * 0000 -> GPIO + * use PSC6: + * on STK52xx: + * use as UART. Pins PSC6_0 to PSC6_3 are used. + * Bits 9:11 (mask: 0x00700000): + * 101 -> PSC6 : Extended POST test is not available + * on MINI-FAP and TQM5200_IB: + * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): + * 000 -> PSC6 could not be used as UART, CODEC or IrDA + * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST + * tests. + */ +#define CFG_GPS_PORT_CONFIG 0x81500114 + +/* + * RTC configuration + */ +#define CONFIG_RTC_M41T11 1 +#define CFG_I2C_RTC_ADDR 0x68 +#define CFG_M41T11_BASE_YEAR 1900 /* because Linux uses the same base + year */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* Enable an alternate, more extensive memory test */ +#define CFG_ALT_MEMTEST + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, + * which is normally part of the default commands (CFV_CMD_DFL) + */ +#define CONFIG_LOOPW + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#ifdef CFG_PCISPEED_66 +#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ +#else +#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ +#endif +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CONFIG_LAST_STAGE_INIT + +/* + * SRAM - Do not map below 2 GB in address space, because this area is used + * for SDRAM autosizing. + */ +#define CFG_CS2_START 0xE5000000 +#define CFG_CS2_SIZE 0x100000 /* 1 MByte */ +#define CFG_CS2_CFG 0x0004D930 + +/* + * Grafic controller - Do not map below 2 GB in address space, because this + * area is used for SDRAM autosizing. + */ +#define SM501_FB_BASE 0xE0000000 +#define CFG_CS1_START (SM501_FB_BASE) +#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ +#define CFG_CS1_CFG 0x8F48FF70 +#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ + +#define CFG_RESET_ADDRESS 0xff000000 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 6b8759f..31e3eed 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -2,7 +2,7 @@ * (C) Copyright 2003-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2004-2005 + * (C) Copyright 2004-2006 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de * * See file CREDITS for list of people who contributed to this @@ -32,29 +32,47 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ -#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ -#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ +#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ +/* On a Cameron or on a FO300 board or ... */ +#if !defined(CONFIG_CAM5200) && !defined(CONFIG_FO300) +#define CONFIG_STK52XX 1 /* ... on a STK52XX board */ +#endif + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif /* * Serial console configuration */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#ifdef CONFIG_FO300 +#define CFG_DEVICE_NULLDEV 1 /* enable null device */ +#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */ + +#if 0 +#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */ + /* switch is closed */ +#endif + +#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */ + /* switch is open */ +#endif /* CONFIG_FO300 */ + #ifdef CONFIG_STK52XX #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ @@ -96,18 +114,24 @@ /* * Video console */ -#if 1 +#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */ #define CONFIG_VIDEO #define CONFIG_VIDEO_SM501 #define CONFIG_VIDEO_SM501_32BPP #define CONFIG_CFB_CONSOLE #define CONFIG_VIDEO_LOGO -#define CONFIG_VGA_AS_SINGLE_DEVICE + +#ifndef CONFIG_FO300 #define CONFIG_CONSOLE_EXTRA_INFO +#else +#define CONFIG_VIDEO_BMP_LOGO +#endif + +#define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_SW_CURSOR #define CONFIG_SPLASH_SCREEN #define CFG_CONSOLE_IS_IN_ENV -#endif +#endif /* #ifndef CONFIG_TQM5200S */ #ifdef CONFIG_VIDEO #define ADD_BMP_CMD CFG_CMD_BMP @@ -121,7 +145,7 @@ #define CONFIG_ISO_PARTITION /* USB */ -#ifdef CONFIG_STK52XX +#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) #define CONFIG_USB_OHCI #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE @@ -129,10 +153,12 @@ #define ADD_USB_CMD 0 #endif +#ifndef CONFIG_CAM5200 /* POST support */ #define CONFIG_POST (CFG_POST_MEMORY | \ CFG_POST_CPU | \ CFG_POST_I2C) +#endif #ifdef CONFIG_POST #define CFG_CMD_POST_DIAG CFG_CMD_DIAG @@ -143,7 +169,7 @@ #endif /* IDE */ -#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) +#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) || defined(CONFIG_FO300) #define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2) #else #define ADD_IDE_CMD 0 @@ -176,8 +202,8 @@ #define CONFIG_TIMESTAMP /* display image timestamps */ -#if (TEXT_BASE == 0xFC000000) /* Boot low */ -# define CFG_LOWBOOT 1 +#if (TEXT_BASE != 0xFFF00000) +# define CFG_LOWBOOT 1 /* Boot low */ #endif /* @@ -186,11 +212,49 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS +#ifdef CONFIG_STK52XX +# if defined(CONFIG_TQM5200_B) +# if defined(CFG_LOWBOOT) +# define ENV_UPDT \ + "update=protect off FC000000 FC07FFFF;" \ + "erase FC000000 FC07FFFF;" \ + "cp.b 200000 FC000000 ${filesize};" \ + "protect on FC000000 FC07FFFF\0" +# else /* highboot */ +# define ENV_UPDT \ + "update=protect off FFF00000 FFF7FFFF;" \ + "erase FFF00000 FFF7FFFF;" \ + "cp.b 200000 FFF00000 ${filesize};" \ + "protect on FFF00000 FFF7FFFF\0" +# endif /* CFG_LOWBOOT */ +# else /* !CONFIG_TQM5200_B */ +# define ENV_UPDT \ + "update=protect off FC000000 FC05FFFF;" \ + "erase FC000000 FC05FFFF;" \ + "cp.b 200000 FC000000 ${filesize};" \ + "protect on FC000000 FC05FFFF\0" +# endif /* CONFIG_TQM5200_B */ +#elif defined (CONFIG_CAM5200) +# define ENV_UPDT \ + "update=protect off FC000000 FC03FFFF;" \ + "erase FC000000 FC03FFFF;" \ + "cp.b 200000 FC000000 ${filesize};" \ + "protect on FC000000 FC03FFFF\0" +#elif defined (CONFIG_FO300) +# define ENV_UPDT \ + "update=protect off FC000000 FC05FFFF;" \ + "erase FC000000 FC05FFFF;" \ + "cp.b 200000 FC000000 ${filesize};" \ + "protect on FC000000 FC05FFFF\0" +#else +# error "Unknown Carrier Board" +#endif /* CONFIG_STK52XX */ + #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ @@ -200,18 +264,18 @@ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ - "flash_self=run ramargs addip;" \ + "addcons=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate}\0" \ + "flash_self=run ramargs addip addcons;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip;" \ + "flash_nfs=run nfsargs addip addcons;" \ "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \ + "bootm\0" \ "bootfile=/tftpboot/tqm5200/uImage\0" \ - "load=tftp 200000 ${u-boot}\0" \ "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" \ + "load=tftp 200000 ${u-boot}\0" \ + ENV_UPDT \ "" #define CONFIG_BOOTCOMMAND "run net_nfs" @@ -283,45 +347,87 @@ /* * Flash configuration */ -#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ +#define CFG_FLASH_BASE 0xFC000000 -/* use CFI flash driver if no module variant is spezified */ +/* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 + +#if defined (CONFIG_CAM5200) +# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) +#elif defined(CONFIG_TQM5200_B) +# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00080000) +#else +# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) +#endif -#if !defined(CFG_LOWBOOT) -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) -#else /* CFG_LOWBOOT */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) -#endif /* CFG_LOWBOOT */ #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks (= chip selects) */ -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ /* Dynamic MTD partition support */ #define CONFIG_JFFS2_CMDLINE #define MTDIDS_DEFAULT "nor0=TQM5200-0" -#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ + +#ifdef CONFIG_STK52XX +# if defined(CONFIG_TQM5200_B) +# if defined(CFG_LOWBOOT) +# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:1m(firmware)," \ + "1536k(kernel)," \ + "3584k(small-fs)," \ + "2m(initrd)," \ + "8m(misc)," \ + "16m(big-fs)" +# else /* highboot */ +# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:2560k(kernel)," \ + "3584k(small-fs)," \ + "2m(initrd)," \ + "8m(misc)," \ + "15m(big-fs)," \ + "1m(firmware)" +# endif /* CFG_LOWBOOT */ +# else /* !CONFIG_TQM5200_B */ +# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ "1408k(kernel)," \ "2m(initrd)," \ "4m(small-fs)," \ - "16m(big-fs)," \ - "8m(misc)" + "8m(misc)," \ + "16m(big-fs)" +# endif /* CONFIG_TQM5200_B */ +#elif defined (CONFIG_CAM5200) +# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \ + "1792k(kernel)," \ + "3584k(small-fs)," \ + "2m(initrd)," \ + "8m(misc)," \ + "16m(big-fs)" +#elif defined (CONFIG_FO300) +# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ + "1408k(kernel)," \ + "2m(initrd)," \ + "4m(small-fs)," \ + "8m(misc)," \ + "16m(big-fs)" +#else +# error "Unknown Carrier Board" +#endif /* CONFIG_STK52XX */ /* * Environment settings */ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */ +#if defined(CONFIG_TQM5200_B) +#define CFG_ENV_SECT_SIZE 0x40000 +#else #define CFG_ENV_SECT_SIZE 0x20000 +#endif /* CONFIG_TQM5200_B */ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) /* * Memory map @@ -349,8 +455,15 @@ # define CFG_RAMBOOT 1 #endif -#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ +#if defined (CONFIG_CAM5200) +# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#elif defined(CONFIG_TQM5200_B) +# define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ +#else +# define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ +#endif + +#define CFG_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* @@ -371,15 +484,18 @@ * use ALT CAN position: Bits 2-3 (mask: 0x30000000): * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards. Do not use with REV100 modules - * (because, there I2C1 is used as I2C bus) + * Use for REV200 STK52XX boards and FO300 boards. Do not use + * with REV100 modules (because, there I2C1 is used as I2C bus) * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) * 000 -> All PSC2 pins are GIOPs * 001 -> CAN1/2 on PSC2 pins * Use for REV100 STK52xx boards + * 01x -> Use AC97 + * use PSC3: Bits 20-23 (mask: 0x00000f00) + * 1100 -> UART/SPI (on FO300 board) * use PSC6: - * on STK52xx: + * on STK52xx and FO300: * use as UART. Pins PSC6_0 to PSC6_3 are used. * Bits 9:11 (mask: 0x00700000): * 101 -> PSC6 : Extended POST test is not available @@ -401,6 +517,8 @@ # define CFG_GPS_PORT_CONFIG 0x91500004 # endif # endif +#elif defined (CONFIG_FO300) +# define CFG_GPS_PORT_CONFIG 0x91502c24 #else /* TMQ5200 Inbetriebnahme-Board */ # define CFG_GPS_PORT_CONFIG 0x81000004 #endif @@ -411,6 +529,8 @@ #if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100) # define CONFIG_RTC_M41T11 1 # define CFG_I2C_RTC_ADDR 0x68 +# define CFG_M41T11_BASE_YEAR 1900 /* because Linux uses the same base + year */ #else # define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ #endif @@ -420,6 +540,10 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#define CFG_PROMPT_HUSH_PS2 "> " + #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -466,32 +590,25 @@ #define CFG_CS0_START CFG_FLASH_BASE #define CFG_CS0_SIZE CFG_FLASH_SIZE -/* automatic configuration of chip selects */ -#ifdef CONFIG_CS_AUTOCONF #define CONFIG_LAST_STAGE_INIT -#endif /* * SRAM - Do not map below 2 GB in address space, because this area is used * for SDRAM autosizing. */ -#if defined (CONFIG_CS_AUTOCONF) #define CFG_CS2_START 0xE5000000 #define CFG_CS2_SIZE 0x100000 /* 1 MByte */ #define CFG_CS2_CFG 0x0004D930 -#endif /* * Grafic controller - Do not map below 2 GB in address space, because this * area is used for SDRAM autosizing. */ -#if defined (CONFIG_CS_AUTOCONF) #define SM501_FB_BASE 0xE0000000 #define CFG_CS1_START (SM501_FB_BASE) #define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ #define CFG_CS1_CFG 0x8F48FF70 #define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 -#endif #define CFG_CS_BURST 0x00000000 #define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index cec7e3e..92c7016 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -422,9 +422,9 @@ extern int tqm834x_num_flash_banks; #define CFG_SICRL SICRL_LDP_A /* i-cache and d-cache disabled */ -#define CFG_HID0_INIT 0x000000000 -#define CFG_HID0_FINAL CFG_HID0_INIT -#define CFG_HID2 0x000000000 +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL CFG_HID0_INIT +#define CFG_HID2 HID2_HBE /* DDR 0 - 512M */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) @@ -437,12 +437,21 @@ extern int tqm834x_num_flash_banks; #define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) /* PCI */ -#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#ifdef CONFIG_PCI +#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) #define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT3L (0) +#define CFG_IBAT3U (0) +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) +#define CFG_IBAT5L (0) +#define CFG_IBAT5U (0) +#endif /* IMMRBAR */ #define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index da6946b..bc3b9aa 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -158,7 +158,7 @@ #undef CONFIG_CONS_NONE /* define if console on something else */ #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#else +#else /* ! TQM8560 */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO @@ -170,19 +170,21 @@ #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) -#endif /* CONFIG_TQM8560 */ - -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - /* PS/2 Keyboard */ +#if !defined(CONFIG_TQM8560) #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ #define CONFIG_PS2SERIAL 2 /* .. on DUART2 */ #define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ #define CONFIG_BOARD_EARLY_INIT_R 1 +#endif /* !CONFIG_TQM8560 */ + +#endif /* CONFIG_TQM8560 */ + +#define CONFIG_BAUDRATE 115200 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} /* Use the HUSH parser */ #define CFG_HUSH_PARSER @@ -422,7 +424,7 @@ #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ @@ -447,7 +449,7 @@ "run nfsargs addip addcons;bootm\0" \ "rootpath=/opt/eldk/ppc_85xx\0" \ "kernel_addr=FE000000\0" \ - "ramdisk_addr=FE100000\0" \ + "ramdisk_addr=FE180000\0" \ "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h new file mode 100644 index 0000000..ede4e3b --- /dev/null +++ b/include/configs/TQM885D.h @@ -0,0 +1,492 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2006 + * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ +#define CONFIG_TQM885D 1 /* ...on a TQM88D module */ + +#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ +#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ +#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ +#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 50 MHz - CPU default clock */ + /* (it will be used if there is no */ + /* 'cpuclk' variable with valid value) */ + +#define CFG_MEASURE_CPUCLK /* Measure real cpu clock */ + /* (function measure_gclk() */ + /* will be called) */ +#ifdef CFG_MEASURE_CPUCLK +#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */ +#endif + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/TQM866M/uImage\0" \ + "kernel_addr=40080000\0" \ + "ramdisk_addr=40180000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ + +#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CFG_I2C_SLAVE 0xFE + +#ifdef CONFIG_SOFT_I2C +/* + * Software (bit-bang) I2C driver configuration + */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +# define CONFIG_RTC_DS1337 1 +# define CFG_I2C_RTC_ADDR 0x68 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ + +#define CONFIG_TIMESTAMP /* but print image timestmps */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_MII | \ + CFG_CMD_NFS | \ + CFG_CMD_PING ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ +#define CFG_ALT_MEMTEST /* alternate, more extensive + memory test.*/ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Enable loopw commando. This has only effect, if CFG_CMD_MEM is defined, + * which is normally part of the default commands (CFV_CMD_DFL) + */ +#define CONFIG_LOOPW + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: Default value of OR0 after reset + */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ + OR_SCY_6_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#ifndef CONFIG_CAN_DRIVER +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ + +/* + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + */ +#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) + +/* + * Memory Periodic Timer Prescaler + * Periodic timer for refresh, start with refresh rate for 40 MHz clock + * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK) + */ +#define CFG_MAMR_PTA 39 + +/* + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank + */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 10 column SDRAM */ +#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Network configuration + */ +#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */ +#define CONFIG_FEC_ENET /* enable ethernet on FEC */ +#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ +#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ + +#if (CONFIG_COMMANDS & CFG_CMD_MII) +#define CFG_DISCOVER_PHY +#endif + +#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before + switching to another netwok (if the + tried network is unreachable) */ + +#define CONFIG_ETHPRIME "SCC ETHERNET" + +#endif /* __CONFIG_H */ diff --git a/include/configs/aev.h b/include/configs/aev.h index aa6bc91..8d9f0a1 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2003-2005 + * (C) Copyright 2003-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2004-2005 @@ -370,10 +370,7 @@ #define CFG_CS0_START CFG_FLASH_BASE #define CFG_CS0_SIZE CFG_FLASH_SIZE -/* automatic configuration of chip selects */ -#ifdef CONFIG_CS_AUTOCONF #define CONFIG_LAST_STAGE_INIT -#endif /* * SRAM - Do not map below 2 GB in address space, because this area is used diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 6d32821..cd4339b 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005 + * (C) Copyright 2005-2006 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this @@ -49,7 +49,7 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ #define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ @@ -257,8 +257,8 @@ "kernel_addr=fff00000\0" \ "ramdisk_addr=fff10000\0" \ "load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0" \ - "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ - "cp.b 100000 fff80000 80000;" \ + "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ + "cp.b 100000 fffa0000 60000;" \ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ "" @@ -310,11 +310,11 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ - CFG_CMD_EEPROM | \ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -358,6 +358,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 4a79835..a66cdc3 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -200,8 +200,9 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ diff --git a/include/configs/ebony.h b/include/configs/ebony.h index a26af69..d8882ea 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -143,7 +143,13 @@ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ @@ -205,6 +211,7 @@ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -243,8 +250,9 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ diff --git a/include/configs/gth2.h b/include/configs/gth2.h index 77d2d56..a49ed3b 100644 --- a/include/configs/gth2.h +++ b/include/configs/gth2.h @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -34,7 +34,7 @@ #define CONFIG_AU1000 1 -#define CONFIG_MISC_INIT_R 1 +#define CONFIG_MISC_INIT_R 1 #define CONFIG_ETHADDR DE:AD:BE:EF:01:02 /* Ethernet address */ @@ -59,21 +59,21 @@ #define CONFIG_AUTOBOOT_DELAY_STR "d" #define CONFIG_AUTOBOOT_STOP_STR " " -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#define CONFIG_BOOTARGS "panic=1" +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#define CONFIG_BOOTARGS "panic=1" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CONFIG_EXTRA_ENV_SETTINGS \ "addmisc=setenv bootargs $(bootargs) " \ - "ethaddr=$(ethaddr) \0" \ - "netboot=bootp;run addmisc;bootm\0" \ - "" + "ethaddr=$(ethaddr) \0" \ + "netboot=bootp;run addmisc;bootm\0" \ + "" /* Boot from Compact flash partition 2 as default */ #define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;run addmisc;bootm" -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \ +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \ ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \ - CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_LOADB | CFG_CMD_ELF | \ + CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_LOADB | CFG_CMD_ELF | \ CFG_CMD_BDI | CFG_CMD_BEDBUG | CFG_CMD_NFS | CFG_CMD_AUTOSCRIPT )) #include <cmd_confdefs.h> @@ -81,11 +81,11 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "GTH2 # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "GTH2 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args*/ #define CFG_MALLOC_LEN 128*1024 @@ -93,16 +93,16 @@ #define CFG_MHZ 500 -#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */ +#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */ #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ -#define CFG_LOAD_ADDR 0x81000000 /* default load address */ +#define CFG_LOAD_ADDR 0x81000000 /* default load address */ #define CFG_MEMTEST_START 0x80100000 #define CFG_MEMTEST_END 0x83000000 -#define CONFIG_HW_WATCHDOG 1 +#define CONFIG_HW_WATCHDOG 1 /*----------------------------------------------------------------------- * FLASH and environment organization @@ -113,8 +113,8 @@ #define PHYS_FLASH 0xbfc00000 /* Flash Bank #1 */ /* The following #defines are needed to get flash environment right */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 << 10) +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) #define CFG_INIT_SP_OFFSET 0x400000 @@ -125,7 +125,7 @@ #define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ -#define CFG_ENV_IS_NOWHERE 1 +#define CFG_ENV_IS_NOWHERE 1 /* Address and size of Primary Environment Sector */ #define CFG_ENV_ADDR 0xB0030000 @@ -158,21 +158,21 @@ #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ #undef CONFIG_IDE_RESET /* reset for ide not supported */ #define CFG_ATA_IDE0_OFFSET 0 -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_IO_BASE +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_IO_BASE /* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET 0 +#define CFG_ATA_DATA_OFFSET 0 -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET 0 +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET 0 -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0200 +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0200 /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h new file mode 100644 index 0000000..61cf705 --- /dev/null +++ b/include/configs/kvme080.h @@ -0,0 +1,262 @@ +/* + * (C) Copyright 2005 + * Sangmoon Kim, dogoil@etinsys.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8245 1 +#define CONFIG_KVME080 1 + +#define CONFIG_CONS_INDEX 1 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_IPADDR 192.168.0.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.0.1 + +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 " \ + "root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \ + "ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \ + "kvme080:eth0:none " \ + "mtdparts=phys_mapped_flash:12m(root),-(kernel)" + +#define CONFIG_BOOTCOMMAND \ + "tftp 800000 kvme080/uImage; " \ + "bootm 800000" + +#define CONFIG_LOADADDR 800000 + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R + +#define CONFIG_LOADS_ECHO 1 +#undef CFG_LOADS_BAUD_CHANGE + +#undef CONFIG_WATCHDOG + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#define CONFIG_RTC_DS164x + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_CACHE | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP) + +#define CONFIG_NETCONSOLE + +#include <cmd_confdefs.h> + +#define CFG_LONGHELP +#define CFG_PROMPT "=> " +#define CFG_CBSIZE 256 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 +#define CFG_BARGSIZE CFG_CBSIZE + +#define CFG_MEMTEST_START 0x00400000 +#define CFG_MEMTEST_END 0x07C00000 + +#define CFG_LOAD_ADDR 0x00100000 +#define CFG_HZ 1000 + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_SIZE 128 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x7C000000 +#define CFG_EUMB_ADDR 0xFC000000 +#define CFG_NVRAM_BASE_ADDR 0xFF000000 +#define CFG_NS16550_COM1 0xFF080000 +#define CFG_NS16550_COM2 0xFF080010 +#define CFG_NS16550_COM3 0xFF080020 +#define CFG_NS16550_COM4 0xFF080030 +#define CFG_RESET_ADDRESS 0xFFF00100 + +#define CFG_MAX_RAM_SIZE 0x20000000 +#define CFG_FLASH_SIZE (16 * 1024 * 1024) +#define CFG_NVRAM_SIZE 0x7FFF8 + +#define CONFIG_VERY_BIG_RAM + +#define CFG_MONITOR_LEN 0x00040000 +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_LEN (512 << 10) + +#define CFG_BOOTMAPSZ (8 << 20) + +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_USE_BUFFER_WRITE +#define CFG_FLASH_PROTECTION +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_PROTECT_CLEAR + +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 256 + +#define CFG_FLASH_ERASE_TOUT 120000 +#define CFG_FLASH_WRITE_TOUT 500 + +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 + +#define CFG_ENV_IS_IN_NVRAM 1 +#define CONFIG_ENV_OVERWRITE 1 +#define CFG_NVRAM_ACCESS_ROUTINE +#define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR +#define CFG_ENV_SIZE 0x400 +#define CFG_ENV_OFFSET 0 + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK 14745600 + +#define CONFIG_PCI +#define CONFIG_PCI_PNP + +#define CONFIG_NET_MULTI +#define CONFIG_EEPRO100 +#define CONFIG_EEPRO100_SROM_WRITE + +#define CFG_RX_ETH_BUFFER 8 + +#define CONFIG_HARD_I2C 1 +#define CFG_I2C_SPEED 400000 +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#define CONFIG_SYS_CLK_FREQ 33333333 + +#define CFG_CACHELINE_SIZE 32 +#if CONFIG_COMMANDS & CFG_CMD_KGDB +# define CFG_CACHELINE_SHIFT 5 +#endif + +#define CFG_DLL_EXTEND 0x00 +#define CFG_PCI_HOLD_DEL 0x20 + +#define CFG_ROMNAL 15 +#define CFG_ROMFAL 31 + +#define CFG_REFINT 430 + +#define CFG_DBUS_SIZE2 1 + +#define CFG_BSTOPRE 121 +#define CFG_REFREC 8 +#define CFG_RDLAT 4 +#define CFG_PRETOACT 3 +#define CFG_ACTTOPRE 5 +#define CFG_ACTORW 3 +#define CFG_SDMODE_CAS_LAT 3 +#define CFG_SDMODE_WRAP 0 + +#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 1 +#define CFG_REGDIMM 0 + +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (0x4000000 - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x04000000 +#define CFG_BANK1_END (0x8000000 - 1) +#define CFG_BANK1_ENABLE 1 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x00000000 +#define CFG_BANK4_END 0x00000000 +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x00000000 +#define CFG_BANK5_END 0x00000000 +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x00000000 +#define CFG_BANK6_END 0x00000000 +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x00000000 +#define CFG_BANK7_END 0x00000000 +#define CFG_BANK7_ENABLE 0 + +#define CFG_BANK_ENABLE 0x03 + +#define CFG_ODCR 0x75 +#define CFG_PGMAX 0x32 + +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +#define BOOTFLAG_COLD 0x01 +#define BOOTFLAG_WARM 0x02 + +#endif /* __CONFIG_H */ diff --git a/include/configs/luan.h b/include/configs/luan.h index 0335a00..0350e91 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -145,6 +145,13 @@ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" @@ -215,6 +222,7 @@ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -253,6 +261,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index d8d63a1..563f797 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -47,8 +47,27 @@ /* * Serial console configuration + * + * To select console on the one of 8 external UARTs, + * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART, + * or as 5, 6, 7, or 8 for the second Quad UART. + * COM11, COM12, COM13, COM14 are located on the second Quad UART. + * + * CONFIG_PSC_CONSOLE must be undefined in this case. + */ +#ifdef CONFIG_CONSOLE_COM12 +#define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */ +#else +#define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */ +#endif +/* + * To select console on PSC1, define CONFIG_PSC_CONSOLE as 1 + * and undefine CONFIG_QUART_CONSOLE. */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +/*#define CONFIG_PSC_CONSOLE 1 */ /* console is on PSC1 */ +#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) +#error "Select only one console device!" +#endif #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } @@ -256,11 +275,59 @@ #define CFG_CS2_SIZE 0x00001000 #define CFG_CS2_CFG 0x1d300 +/* Second Quad UART @0x80010000 */ +#define CFG_CS1_START 0x80010000 +#define CFG_CS1_SIZE 0x00001000 +#define CFG_CS1_CFG 0x1d300 + +/* + * Select one of quarts as a default + * console. If undefined - PSC console + * wil be default + */ #define CFG_CS_BURST 0x00000000 #define CFG_CS_DEADCYCLE 0x33333333 #define CFG_RESET_ADDRESS 0xff000000 +/* + * QUART Expanders support + */ +#if defined(CONFIG_QUART_CONSOLE) +/* + * We'll use NS16550 chip routines, + */ +#define CFG_NS16550 1 +#define CFG_NS16550_SERIAL 1 +#define CONFIG_CONS_INDEX 1 +/* + * To achieve necessary offset on SC16C554 + * A0-A2 (register select) pins with NS16550 + * functions (in struct NS16550), REG_SIZE + * should be 4, because A0-A2 pins are connected + * to DA2-DA4 address bus lines. + */ +#define CFG_NS16550_REG_SIZE 4 +/* + * LocalPlus Bus already inited in cpu_init_f(), + * so can work with QUART's chip selects. + * One of four SC16C554 UARTs is selected with + * A3-A4 (DA5-DA6) lines. + */ +#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) +#define CFG_NS16550_COM1 (CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5) +#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9) +#define CFG_NS16550_COM1 (CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5) +#elif +#error "Wrong QUART expander number." +#endif + +/* + * SC16C554 chip's external crystal oscillator frequency + * is 7.3728 MHz + */ +#define CFG_NS16550_CLK 7372800 +#endif /* CONFIG_QUART_CONSOLE */ /*----------------------------------------------------------------------- * USB stuff *----------------------------------------------------------------------- diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index a13d6a8..89e9164 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -158,7 +158,13 @@ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ @@ -219,6 +225,9 @@ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_PHY_RESET_DELAY 1000 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ @@ -226,6 +235,7 @@ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -264,15 +274,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h index ea15524..072b9dd 100644 --- a/include/configs/ppmc7xx.h +++ b/include/configs/ppmc7xx.h @@ -1,9 +1,9 @@ /* * ppmc7xx.h * --------- - * + * * Wind River PPMC 7xx/74xx board configuration file. - * + * * By Richard Danter (richard.danter@windriver.com) * Copyright (C) 2005 Wind River Systems */ @@ -16,15 +16,15 @@ /*=================================================================== - * + * * User configurable settings - Modify to your preference - * + * *=================================================================== */ /* * Debug - * + * * DEBUG - Define this is you want extra debug info * GTREGREAD - Required to build with debug * do_bdinfo - Required to build with debug @@ -37,7 +37,7 @@ /* * CPU type - * + * * CONFIG_7xx - We have a 750 or 755 CPU * CONFIG_74xx - We have a 7400 CPU * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400) @@ -52,11 +52,11 @@ /* * Monitor configuration - * + * * CONFIG_COMMANDS - List of command sets to include in shell - * + * * The following command sets have been tested and known to work: - * + * * CFG_CMD_CACHE - Cache control commands * CFG_CMD_MEMORY - Memory display, change and test commands * CFG_CMD_FLASH - Erase and program flash @@ -91,7 +91,7 @@ /* * PCI config - * + * * CONFIG_PCI - Enable PCI bus * CONFIG_PCI_PNP - Enable Plug & Play support * CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup @@ -104,7 +104,7 @@ /* * Network config - * + * * CONFIG_NET_MULTI - Support for multiple network interfaces * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM @@ -117,18 +117,18 @@ /* * Enable extra init functions - * + * * CONFIG_MISC_INIT_F - Call pre-relocation init functions * CONFIG_MISC_INIT_R - Call post relocation init functions */ #undef CONFIG_MISC_INIT_F -#define CONFIG_MISC_INIT_R +#define CONFIG_MISC_INIT_R /* * Boot config - * + * * CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec) */ @@ -142,9 +142,9 @@ /*=================================================================== - * + * * Board configuration settings - You should not need to modify these - * + * *=================================================================== */ @@ -154,9 +154,9 @@ /* * Memory map - * + * * This board runs in a standard CHRP (Map-B) configuration. - * + * * Type Start End Size Width Chip Sel * ----------- ----------- ----------- ------- ------- -------- * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0 @@ -164,9 +164,9 @@ * UART 0x7C000000 RCS2 * Mailbox 0xFF000000 RCS1 * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0 - * + * * Flash sectors are laid out as follows. - * + * * Sector Start End Size Comments * ------- ----------- ----------- ------- ----------- * 0 0xFFC00000 0xFFC3FFFF 256KB @@ -193,7 +193,7 @@ /* * SDRAM config - see memory map details above. - * + * * CFG_SDRAM_BASE - Start address of SDRAM, this _must_ be zero! * CFG_SDRAM_SIZE - Total size of contiguous SDRAM bank(s) */ @@ -202,9 +202,9 @@ #define CFG_SDRAM_SIZE 0x04000000 -/* +/* * Flash config - see memory map details above. - * + * * CFG_FLASH_BASE - Start address of flash memory * CFG_FLASH_SIZE - Total size of contiguous flash mem * CFG_FLASH_ERASE_TOUT - Erase timeout in ms @@ -223,7 +223,7 @@ /* * Monitor config - see memory map details above - * + * * CFG_MONITOR_BASE - Base address of monitor code * CFG_MALLOC_LEN - Size of malloc pool (128KB) */ @@ -234,7 +234,7 @@ /* * Command shell settings - * + * * CFG_BARGSIZE - Boot Argument buffer size * CFG_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB) * CFG_CBSIZE - Console Buffer (input) size @@ -261,10 +261,10 @@ /* * Environment config - see memory map details above - * + * * CFG_ENV_IS_IN_FLASH - The env variables are stored in flash * CFG_ENV_ADDR - Address of the sector containing env vars - * CFG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB) + * CFG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB) * CFG_ENV_SECT_SIZE - Size of sector containing env vars (32KB) */ @@ -282,7 +282,7 @@ * Since the main system RAM is initialised very early, we place the INIT_RAM * in the main system RAM just above the exception vectors. The contents are * copied to top of RAM by the init code. - * + * * CFG_INIT_RAM_ADDR - Address of Init RAM, above exception vect * CFG_INIT_RAM_END - Size of Init RAM * CFG_GBL_DATA_SIZE - Ammount of RAM to reserve for global data @@ -297,7 +297,7 @@ /* * Initial BAT config - * + * * BAT0 - System SDRAM * BAT1 - LED's and Serial Port * BAT2 - PCI Memory @@ -327,7 +327,7 @@ /* * Cache config - * + * * CFG_CACHELINE_SIZE - Size of a cache line (CPU specific) * CFG_L2 - L2 cache enabled if defined * L2_INIT - L2 cache init flags @@ -342,7 +342,7 @@ /* * Clocks config - * + * * CFG_BUS_HZ - Bus clock frequency in Hz * CFG_BUS_CLK - As above (?) * CFG_HZ - Decrementer freq in Hz @@ -355,7 +355,7 @@ /* * Serial port config - * + * * CFG_BAUDRATE_TABLE - List of valid baud rates * CFG_NS16550 - Include the NS16550 driver * CFG_NS16550_SERIAL - Include the serial (wrapper) driver @@ -398,7 +398,7 @@ /* * Extra init functions - * + * * CFG_BOARD_ASM_INIT - Call assembly init code */ @@ -407,11 +407,11 @@ /* * Boot flags - * + * * BOOTFLAG_COLD - Indicates a power-on boot * BOOTFLAG_WARM - Indicates a software reset */ - + #define BOOTFLAG_COLD 0x01 #define BOOTFLAG_WARM 0x02 diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h new file mode 100644 index 0000000..866f7b0 --- /dev/null +++ b/include/configs/sbc2410x.h @@ -0,0 +1,239 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * Gary Jennejohn <gj@denx.de> + * David Mueller <d.mueller@elsoft.ch> + * + * Modified for the friendly-arm SBC-2410X by + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com> + * + * Configuation settings for the friendly-arm SBC-2410X board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#undef CONFIG_SKIP_LOWLEVEL_INIT /* undef for developing */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ +#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */ + +/* input clock of PLL */ +#define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */ + + +#define USE_920T_MMU 1 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x19000300 +#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SBC2410X */ + +/************************************************************ + * RTC + ************************************************************/ +#define CONFIG_RTC_S3C24X0 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +/*********************************************************** + * Command definition + ***********************************************************/ +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL | \ + CFG_CMD_CACHE | \ + /*CFG_CMD_NAND |*/ \ + /*CFG_CMD_EEPROM |*/ \ + /*CFG_CMD_I2C |*/ \ + /*CFG_CMD_USB |*/ \ + CFG_CMD_REGINFO | \ + CFG_CMD_DATE | \ + CFG_CMD_PING | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off" +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.0.69 +#define CONFIG_SERVERIP 192.168.0.1 +/*#define CONFIG_BOOTFILE "elinos-lart" */ +#define CONFIG_BOOTCOMMAND "dhcp; bootm" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* what's this ? it's not used anywhere */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "[ ~ljh@GDLC ]# " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x30000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x33000000 /* default load address */ + +/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ +/* it to wrap 100 times (total 1562500) to get 1 sec. */ +#define CFG_HZ 1562500 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +/* #define CONFIG_AMD_LV400 1 /\* uncomment this if you have a LV400 flash *\/ */ + +#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ + +#ifdef CONFIG_AMD_LV800 +#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ +#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */ +#endif + +#ifdef CONFIG_AMD_LV400 +#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ +#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */ +#endif + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ + +/*----------------------------------------------------------------------- + * NAND flash settings + */ +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define NAND_WAIT_READY(nand) NF_WaitRB() +#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH) +#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW) +#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d) +#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d) +#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d) +#define WRITE_NAND(d, adr) NF_Write(d) +#define READ_NAND(adr) NF_Read() +/* the following functions are NOP's because S3C24X0 handles this in hardware */ +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) +/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */ +#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */ + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG + +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CONFIG_CMDLINE_EDITING + +#ifdef CONFIG_CMDLINE_EDITING +#undef CONFIG_AUTO_COMPLETE +#else +#define CONFIG_AUTO_COMPLETE +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h new file mode 100644 index 0000000..9d3609a --- /dev/null +++ b/include/configs/spc1920.h @@ -0,0 +1,362 @@ +/* + * (C) Copyright 2006 + * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de + * + * Configuation settings for the SPC1920 board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __H +#define __CONFIG_H + +#define CONFIG_SPC1920 1 /* SPC1920 board */ +#define CONFIG_MPC885 1 /* MPC885 CPU */ + +#define CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_MII +/* #define MII_DEBUG */ +/* #define CONFIG_FEC_ENET */ +#undef CONFIG_ETHER_ON_FEC1 +#define CONFIG_ETHER_ON_FEC2 +#define FEC_ENET +/* #define CONFIG_FEC2_PHY_NORXERR */ +/* #define CFG_DISCOVER_PHY */ +/* #define CONFIG_PHY_ADDR 0x1 */ +#define CONFIG_FEC2_PHY 1 + +#define CONFIG_BAUDRATE 19200 + +/* use PLD CLK4 instead of brg */ +#undef CFG_SPC1920_SMC1_CLK4 + +#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ +#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 +#define CFG_8xx_CPUCLK_MIN 40000000 +#define CFG_8xx_CPUCLK_MAX 133000000 + +#define CFG_RESET_ADDRESS 0xf8000000 + +#define CONFIG_BOARD_EARLY_INIT_F + + +#if 1 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_NFSBOOTCOMMAND \ + "dhcp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ + "bootm" + +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ + "bootm fe080000" + +#undef CONFIG_BOOTARGS + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ + +#ifndef CONFIG_COMMANDS +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ + | CFG_CMD_ECHO \ + | CFG_CMD_IMMAP \ + | CFG_CMD_JFFS2 \ + | CFG_CMD_PING \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII) + /* & ~( CFG_CMD_NET)) */ + + +#endif /* !CONFIG_COMMANDS */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=>" /* Monitor Command Prompt */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR 0x00100000 + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 2400, 4800, 9600, 19200 } + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xF0000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */ + +#ifdef CONFIG_BZIP2 +#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ +#else +#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ +#endif /* CONFIG_BZIP2 */ + +#define CFG_ALLOC_DPRAM 1 /* use allocation routines */ + +/* + * Flash + */ +/*----------------------------------------------------------------------- + * Flash organisation + */ +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */ + +/* Environment is in flash */ +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + +#define CONFIG_ENV_OVERWRITE + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ + +/*----------------------------------------------------------------------- + * I2C configuration + */ +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */ +#define CFG_I2C_SLAVE 0x7F +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +/* #define CFG_SCCR SCCR_TBS */ +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * DER - Debug Enable Register + *----------------------------------------------------------------------- + * Set to zero to prevent the processor from entering debug mode + */ +#define CFG_DER 0 + + +/* Because of the way the 860 starts up and assigns CS0 the entire + * address space, we have to set the memory controller differently. + * Normally, you write the option register first, and then enable the + * chip select by writing the base register. For CS0, you must write + * the base register first, followed by the option register. + */ + + +/* + * Init Memory Controller: + */ + +/* BR0 and OR0 (FLASH) */ +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ + + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: + */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_3_CLK | OR_EHTR | OR_BI) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + + +/* + * SDRAM CS1 UPMB + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE_PRELIM CFG_SDRAM_BASE +#define SDRAM_MAX_SIZE 0x4000000 /* max 64 MB */ + +#define CFG_PRELIM_OR1_AM 0xF0000000 +/* #define CFG_OR1_TIMING OR_CSNT_SAM/\* | OR_G5LS /\\* *\\/ *\/ */ +#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ + +#define CFG_OR1_PRELIM (CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING) +#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V) + +/* #define CFG_OR1_FINAL ((CFG_OR1_AM & OR_AM_MSK) | CFG_OR1_TIMING) */ +/* #define CFG_BR1_FINAL ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */ + +#define CFG_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64)) +#define CFG_PTA_PER_CLK 195 +#define CFG_MBMR_PTB 195 +#define CFG_MPTPR MPTPR_PTP_DIV16 +#define CFG_MAR 0x88 + +#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ + MBMR_AMB_TYPE_0 | \ + MBMR_G0CLB_A10 | \ + MBMR_DSB_1_CYCL | \ + MBMR_RLFB_1X | \ + MBMR_WLFB_1X | \ + MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */ + +#define CFG_MBMR_9COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ + MBMR_AMB_TYPE_1 | \ + MBMR_G0CLB_A10 | \ + MBMR_DSB_1_CYCL | \ + MBMR_RLFB_1X | \ + MBMR_WLFB_1X | \ + MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */ + + +/* PLD CS5 */ +#define CFG_SPC1920_PLD_BASE 0x80000000 +#define CFG_PRELIM_OR5_AM 0xffff8000 + +#define CFG_OR5_PRELIM (CFG_PRELIM_OR5_AM | \ + OR_CSNT_SAM | \ + OR_ACS_DIV1 | \ + OR_BI | \ + OR_SCY_0_CLK | \ + OR_TRLX) + +#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); + +/* #define CFG_PLD_BASE 0x30000000 */ +/* #define CFG_OR5_PRELIM 0xffff1110 */ +/* #define CFG_BR5_PRELIM 0x30000401 */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* Machine type +*/ +#define _MACH_8xx (_MACH_fads) + +#endif /* __CONFIG_H */ diff --git a/include/configs/spieval.h b/include/configs/spieval.h index 9ebb51e..f40dde2 100644 --- a/include/configs/spieval.h +++ b/include/configs/spieval.h @@ -452,32 +452,25 @@ #define CFG_CS0_START CFG_FLASH_BASE #define CFG_CS0_SIZE CFG_FLASH_SIZE -/* automatic configuration of chip selects */ -#ifdef CONFIG_CS_AUTOCONF #define CONFIG_LAST_STAGE_INIT -#endif /* * SRAM - Do not map below 2 GB in address space, because this area is used * for SDRAM autosizing. */ -#if defined (CONFIG_CS_AUTOCONF) #define CFG_CS2_START 0xE5000000 #define CFG_CS2_SIZE 0x100000 /* 1 MByte */ #define CFG_CS2_CFG 0x0004D930 -#endif /* * Grafic controller - Do not map below 2 GB in address space, because this * area is used for SDRAM autosizing. */ -#if defined (CONFIG_CS_AUTOCONF) #define SM501_FB_BASE 0xE0000000 #define CFG_CS1_START (SM501_FB_BASE) #define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ #define CFG_CS1_CFG 0x8F48FF70 #define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 -#endif #define CFG_CS_BURST 0x00000000 #define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ diff --git a/include/configs/trab.h b/include/configs/trab.h index 8f71acf..a2dc8e7 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -402,7 +402,7 @@ #endif /* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_ERASE_TOUT (15*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ #define CFG_ENV_IS_IN_FLASH 1 diff --git a/include/configs/walnut.h b/include/configs/walnut.h index 1171ee5..28abd6e 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -90,6 +90,11 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* needed for NetConsole */ + #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ @@ -97,6 +102,7 @@ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ @@ -156,16 +162,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* needed for NetConsole */ - /*----------------------------------------------------------------------- * I2C stuff *----------------------------------------------------------------------- @@ -175,6 +177,13 @@ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/xm250.h b/include/configs/xm250.h index 952f73b..825bfd1 100644 --- a/include/configs/xm250.h +++ b/include/configs/xm250.h @@ -119,9 +119,9 @@ /* * Definitions related to passing arguments to kernel. */ -#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ -#undef CONFIG_INITRD_TAG /* do not send initrd params */ +#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ +#define CONFIG_INITRD_TAG 1 /* do not send initrd params */ #undef CONFIG_VFD /* do not send framebuffer setup */ /* diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h index 7d55566..cf42b66 100644 --- a/include/configs/yellowstone.h +++ b/include/configs/yellowstone.h @@ -229,6 +229,7 @@ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -265,6 +266,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index a81cf34..86a85b8 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -231,6 +231,7 @@ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -272,6 +273,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/yucca.h b/include/configs/yucca.h new file mode 100644 index 0000000..a6532b5 --- /dev/null +++ b/include/configs/yucca.h @@ -0,0 +1,536 @@ +/* + * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * 1 january 2005 Alain Saurel <asaurel@amcc.com> + * Adapted to current Das U-Boot source + ***********************************************************************/ +/************************************************************************ + * yucca.h - configuration for AMCC 440SPe Ref (yucca) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_440SPE 1 /* Specifc SPe support */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#undef CFG_DRAM_TEST /* Disable-takes long time */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +#define EXTCLK_33_33 33333333 +#define EXTCLK_66_66 66666666 +#define EXTCLK_50 50000000 +#define EXTCLK_83 83333333 + +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#undef CONFIG_SHOW_BOOT_PROGRESS +#undef CONFIG_STRESS +#undef ENABLE_ECC +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */ +#define CFG_MONITOR_BASE 0xfffb0000 /* start of monitor */ +#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ + +#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE + +#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ +#define CFG_PCIE_MEMSIZE 0x01000000 +#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ + +#define CFG_PCIE0_CFGBASE 0xc0000000 +#define CFG_PCIE0_XCFGBASE 0xc0000400 +#define CFG_PCIE1_CFGBASE 0xc0001000 +#define CFG_PCIE1_XCFGBASE 0xc0001400 +#define CFG_PCIE2_CFGBASE 0xc0002000 +#define CFG_PCIE2_XCFGBASE 0xc0002400 + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) + +#define CFG_FPGA_BASE 0xe2000000 /* epld */ +#define CFG_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */ + +/* #define CFG_NVRAM_BASE_ADDR 0x08000000 */ +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Mon */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CONFIG_SERIAL_MULTI 1 +#undef CONFIG_UART1_CONSOLE + +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#undef CFG_EXT_SERIAL_CLOCK +/* #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */ + +#define CONFIG_BAUDRATE 115200 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses */ +#define IIC0_DIMM0_ADDR 0x53 +#define IIC0_DIMM1_ADDR 0x52 + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define IIC0_BOOTPROM_ADDR 0x50 +#define IIC0_ALT_BOOTPROM_ADDR 0x54 + +/* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54} + +/* #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) */ +/* #define CFG_I2C_EEPROM_ADDR 0x50 */ /* I2C boot EEPROM */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +/* #endif */ + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +/* #define CFG_NVRAM_SIZE (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */ + +#undef CFG_ENV_IS_IN_NVRAM /* ... not in NVRAM */ +#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ +#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ +#define CONFIG_ENV_OVERWRITE 1 + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=yucca\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=yucca/uImage\0" \ + "kernel_addr=E7F10000\0" \ + "ramdisk_addr=E7F20000\0" \ + "load=tftp 100000 yuca/u-boot.bin\0" \ + "update=protect off 2:4-7;era 2:4-7;" \ + "cp.b ${fileaddr} FFFB0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_MII 1 /* MII PHY management */ +#undef CONFIG_NET_MULTI +#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ +#define CONFIG_HAS_ETH0 +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 1000 +#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* needed for NetConsole */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_ADDR0 0x5555 +#define CFG_FLASH_ADDR1 0x2aaa +#define CFG_FLASH_WORD_SIZE unsigned char + +#define CFG_FLASH_2ND_16BIT_DEV 1 /* evb440SPe has 8 and 16bit device */ +#define CFG_FLASH_2ND_ADDR 0xe7c00000 /* evb440SPe has 8 and 16bit device*/ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR 0xfffa0000 +/* #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) */ +#define CFG_ENV_SIZE 0x10000 /* Size of Environment vars */ +#endif /* CFG_ENV_IS_IN_FLASH */ +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#undef CONFIG_PCI_CONFIG_HOST_BRIDGE + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT /* let board init pci target */ +#undef CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ +/* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */ + +/* + * NETWORK Support (PCI): + */ +/* Support for Intel 82557/82559/82559ER chips. */ +#define CONFIG_EEPRO100 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* FB Divisor selection */ +#define FPGA_FB_DIV_6 6 +#define FPGA_FB_DIV_10 10 +#define FPGA_FB_DIV_12 12 +#define FPGA_FB_DIV_20 20 + +/* VCO Divisor selection */ +#define FPGA_VCO_DIV_4 4 +#define FPGA_VCO_DIV_6 6 +#define FPGA_VCO_DIV_8 8 +#define FPGA_VCO_DIV_10 10 + +/*----------------------------------------------------------------------------+ +| FPGA registers and bit definitions ++----------------------------------------------------------------------------*/ +/* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */ +/* TLB initialization makes it correspond to logical address 0xE2000000. */ +/* => Done init_chip.s in bootlib */ +#define FPGA_REG_BASE_ADDR 0xE2000000 +#define FPGA_GPIO_BASE_ADDR 0xE2010000 +#define FPGA_INT_BASE_ADDR 0xE2020000 + +/*----------------------------------------------------------------------------+ +| Display ++----------------------------------------------------------------------------*/ +#define PPC440SPE_DISPLAY FPGA_REG_BASE_ADDR + +#define PPC440SPE_DISPLAY_D8 (FPGA_REG_BASE_ADDR+0x06) +#define PPC440SPE_DISPLAY_D4 (FPGA_REG_BASE_ADDR+0x04) +#define PPC440SPE_DISPLAY_D2 (FPGA_REG_BASE_ADDR+0x02) +#define PPC440SPE_DISPLAY_D1 (FPGA_REG_BASE_ADDR+0x00) +/*define WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/ +/*#define IOREG8(addr) *((volatile unsigned char *)(addr))*/ + +/*----------------------------------------------------------------------------+ +| ethernet/reset/boot Register 1 ++----------------------------------------------------------------------------*/ +#define FPGA_REG10 (FPGA_REG_BASE_ADDR+0x10) + +#define FPGA_REG10_10MHZ_ENABLE 0x8000 +#define FPGA_REG10_100MHZ_ENABLE 0x4000 +#define FPGA_REG10_GIGABIT_ENABLE 0x2000 +#define FPGA_REG10_FULL_DUPLEX 0x1000 /* force Full Duplex*/ +#define FPGA_REG10_RESET_ETH 0x0800 +#define FPGA_REG10_AUTO_NEG_DIS 0x0400 +#define FPGA_REG10_INTP_ETH 0x0200 + +#define FPGA_REG10_RESET_HISR 0x0080 +#define FPGA_REG10_ENABLE_DISPLAY 0x0040 +#define FPGA_REG10_RESET_SDRAM 0x0020 +#define FPGA_REG10_OPER_BOOT 0x0010 +#define FPGA_REG10_SRAM_BOOT 0x0008 +#define FPGA_REG10_SMALL_BOOT 0x0004 +#define FPGA_REG10_FORCE_COLA 0x0002 +#define FPGA_REG10_COLA_MANUAL 0x0001 + +#define FPGA_REG10_SDRAM_ENABLE 0x0020 + +#define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/ +#define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/ + +/*----------------------------------------------------------------------------+ +| MUX control ++----------------------------------------------------------------------------*/ +#define FPGA_REG12 (FPGA_REG_BASE_ADDR+0x12) + +#define FPGA_REG12_EBC_CTL 0x8000 +#define FPGA_REG12_UART1_CTS_RTS 0x4000 +#define FPGA_REG12_UART0_RX_ENABLE 0x2000 +#define FPGA_REG12_UART1_RX_ENABLE 0x1000 +#define FPGA_REG12_UART2_RX_ENABLE 0x0800 +#define FPGA_REG12_EBC_OUT_ENABLE 0x0400 +#define FPGA_REG12_GPIO0_OUT_ENABLE 0x0200 +#define FPGA_REG12_GPIO1_OUT_ENABLE 0x0100 +#define FPGA_REG12_GPIO_SELECT 0x0010 +#define FPGA_REG12_GPIO_CHREG 0x0008 +#define FPGA_REG12_GPIO_CLK_CHREG 0x0004 +#define FPGA_REG12_GPIO_OETRI 0x0002 +#define FPGA_REG12_EBC_ERROR 0x0001 + +/*----------------------------------------------------------------------------+ +| PCI Clock control ++----------------------------------------------------------------------------*/ +#define FPGA_REG16 (FPGA_REG_BASE_ADDR+0x16) + +#define FPGA_REG16_PCI_CLK_CTL0 0x8000 +#define FPGA_REG16_PCI_CLK_CTL1 0x4000 +#define FPGA_REG16_PCI_CLK_CTL2 0x2000 +#define FPGA_REG16_PCI_CLK_CTL3 0x1000 +#define FPGA_REG16_PCI_CLK_CTL4 0x0800 +#define FPGA_REG16_PCI_CLK_CTL5 0x0400 +#define FPGA_REG16_PCI_CLK_CTL6 0x0200 +#define FPGA_REG16_PCI_CLK_CTL7 0x0100 +#define FPGA_REG16_PCI_CLK_CTL8 0x0080 +#define FPGA_REG16_PCI_CLK_CTL9 0x0040 +#define FPGA_REG16_PCI_EXT_ARB0 0x0020 +#define FPGA_REG16_PCI_MODE_1 0x0010 +#define FPGA_REG16_PCI_TARGET_MODE 0x0008 +#define FPGA_REG16_PCI_INTP_MODE 0x0004 + +/* FB1 Divisor selection */ +#define FPGA_REG16_FB2_DIV_MASK 0x1000 +#define FPGA_REG16_FB2_DIV_LOW 0x0000 +#define FPGA_REG16_FB2_DIV_HIGH 0x1000 +/* FB2 Divisor selection */ +/* S3 switch on Board */ +#define FPGA_REG16_FB1_DIV_MASK 0x2000 +#define FPGA_REG16_FB1_DIV_LOW 0x0000 +#define FPGA_REG16_FB1_DIV_HIGH 0x2000 +/* PCI0 Clock Selection */ +/* S3 switch on Board */ +#define FPGA_REG16_PCI0_CLK_MASK 0x0c00 +#define FPGA_REG16_PCI0_CLK_33_33 0x0000 +#define FPGA_REG16_PCI0_CLK_66_66 0x0800 +#define FPGA_REG16_PCI0_CLK_100 0x0400 +#define FPGA_REG16_PCI0_CLK_133_33 0x0c00 +/* VCO Divisor selection */ +/* S3 switch on Board */ +#define FPGA_REG16_VCO_DIV_MASK 0xc000 +#define FPGA_REG16_VCO_DIV_4 0x0000 +#define FPGA_REG16_VCO_DIV_8 0x4000 +#define FPGA_REG16_VCO_DIV_6 0x8000 +#define FPGA_REG16_VCO_DIV_10 0xc000 +/* Master Clock Selection */ +/* S3, S4 switches on Board */ +#define FPGA_REG16_MASTER_CLK_MASK 0x01c0 +#define FPGA_REG16_MASTER_CLK_EXT 0x0000 +#define FPGA_REG16_MASTER_CLK_66_66 0x0040 +#define FPGA_REG16_MASTER_CLK_50 0x0080 +#define FPGA_REG16_MASTER_CLK_33_33 0x00c0 +#define FPGA_REG16_MASTER_CLK_25 0x0100 + +/*----------------------------------------------------------------------------+ +| PCI Miscellaneous ++----------------------------------------------------------------------------*/ +#define FPGA_REG18 (FPGA_REG_BASE_ADDR+0x18) + +#define FPGA_REG18_PCI_PRSNT1 0x8000 +#define FPGA_REG18_PCI_PRSNT2 0x4000 +#define FPGA_REG18_PCI_INTA 0x2000 +#define FPGA_REG18_PCI_SLOT0_INTP 0x1000 +#define FPGA_REG18_PCI_SLOT1_INTP 0x0800 +#define FPGA_REG18_PCI_SLOT2_INTP 0x0400 +#define FPGA_REG18_PCI_SLOT3_INTP 0x0200 +#define FPGA_REG18_PCI_PCI0_VC 0x0100 +#define FPGA_REG18_PCI_PCI0_VTH1 0x0080 +#define FPGA_REG18_PCI_PCI0_VTH2 0x0040 +#define FPGA_REG18_PCI_PCI0_VTH3 0x0020 + +/*----------------------------------------------------------------------------+ +| PCIe Miscellaneous ++----------------------------------------------------------------------------*/ +#define FPGA_REG1A (FPGA_REG_BASE_ADDR+0x1A) + +#define FPGA_REG1A_PE0_GLED 0x8000 +#define FPGA_REG1A_PE1_GLED 0x4000 +#define FPGA_REG1A_PE2_GLED 0x2000 +#define FPGA_REG1A_PE0_YLED 0x1000 +#define FPGA_REG1A_PE1_YLED 0x0800 +#define FPGA_REG1A_PE2_YLED 0x0400 +#define FPGA_REG1A_PE0_PWRON 0x0200 +#define FPGA_REG1A_PE1_PWRON 0x0100 +#define FPGA_REG1A_PE2_PWRON 0x0080 +#define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040 +#define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020 +#define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010 +#define FPGA_REG1A_PE_SPREAD0 0x0008 +#define FPGA_REG1A_PE_SPREAD1 0x0004 +#define FPGA_REG1A_PE_SELSOURCE_0 0x0002 +#define FPGA_REG1A_PE_SELSOURCE_1 0x0001 + +/*----------------------------------------------------------------------------+ +| PCIe Miscellaneous ++----------------------------------------------------------------------------*/ +#define FPGA_REG1C (FPGA_REG_BASE_ADDR+0x1C) + +#define FPGA_REG1C_PE0_ROOTPOINT 0x8000 +#define FPGA_REG1C_PE1_ENDPOINT 0x4000 +#define FPGA_REG1C_PE2_ENDPOINT 0x2000 +#define FPGA_REG1C_PE0_PRSNT 0x1000 +#define FPGA_REG1C_PE1_PRSNT 0x0800 +#define FPGA_REG1C_PE2_PRSNT 0x0400 +#define FPGA_REG1C_PE0_WAKE 0x0080 +#define FPGA_REG1C_PE1_WAKE 0x0040 +#define FPGA_REG1C_PE2_WAKE 0x0020 +#define FPGA_REG1C_PE0_PERST 0x0010 +#define FPGA_REG1C_PE1_PERST 0x0008 +#define FPGA_REG1C_PE2_PERST 0x0004 + +/*----------------------------------------------------------------------------+ +| Defines ++----------------------------------------------------------------------------*/ +#define PERIOD_133_33MHZ 7500 /* 7,5ns */ +#define PERIOD_100_00MHZ 10000 /* 10ns */ +#define PERIOD_83_33MHZ 12000 /* 12ns */ +#define PERIOD_75_00MHZ 13333 /* 13,333ns */ +#define PERIOD_66_66MHZ 15000 /* 15ns */ +#define PERIOD_50_00MHZ 20000 /* 20ns */ +#define PERIOD_33_33MHZ 30000 /* 30ns */ +#define PERIOD_25_00MHZ 40000 /* 40ns */ + +/*---------------------------------------------------------------------------*/ + +#endif /* __CONFIG_H */ diff --git a/include/fat.h b/include/fat.h index 0645458..92638d5 100644 --- a/include/fat.h +++ b/include/fat.h @@ -175,15 +175,19 @@ typedef struct dir_slot { __u8 name11_12[4]; /* Last 2 characters in name */ } dir_slot; -/* Private filesystem parameters */ +/* Private filesystem parameters + * + * Note: FAT buffer has to be 32 bit aligned + * (see FAT32 accesses) + */ typedef struct { + __u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */ int fatsize; /* Size of FAT in bits */ __u16 fatlength; /* Length of FAT in sectors */ __u16 fat_sect; /* Starting sector of the FAT */ __u16 rootdir_sect; /* Start sector of root directory */ __u16 clust_size; /* Size of clusters in sectors */ short data_begin; /* The sector of the first cluster, can be negative */ - __u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */ int fatbufnum; /* Used by get_fatent, init to -1 */ } fsdata; diff --git a/include/galileo/core.h b/include/galileo/core.h index 0735d07..49f4dd2 100644 --- a/include/galileo/core.h +++ b/include/galileo/core.h @@ -110,7 +110,10 @@ extern unsigned int INTERNAL_REG_BASE_ADDR; #define _1G 0x40000000 #define _2G 0x80000000 +#ifndef BOOL_WAS_DEFINED +#define BOOL_WAS_DEFINED typedef enum _bool{false,true} bool; +#endif /* Little to Big endian conversion macros */ diff --git a/include/image.h b/include/image.h index 139df0b..ea7e953 100644 --- a/include/image.h +++ b/include/image.h @@ -124,6 +124,7 @@ #define IH_TYPE_FIRMWARE 5 /* Firmware Image */ #define IH_TYPE_SCRIPT 6 /* Script file */ #define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ +#define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ /* * Compression Types diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index a522718..4b48564 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -2,7 +2,7 @@ * linux/include/linux/mtd/nand.h * * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com> - * Steven J. Hill <sjhill@realitydiluted.com> + * Steven J. Hill <sjhill@realitydiluted.com> * Thomas Gleixner <tglx@linutronix.de> * * $Id: nand.h,v 1.68 2004/11/12 10:40:37 gleixner Exp $ @@ -15,15 +15,15 @@ * Contains standard defines and IDs for NAND flash devices * * Changelog: - * 01-31-2000 DMW Created - * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers + * 01-31-2000 DMW Created + * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers * so it can be used by other NAND flash device * drivers. I also changed the copyright since none * of the original contents of this file are specific * to DoC devices. David can whack me with a baseball * bat later if I did something naughty. - * 10-11-2000 SJH Added private NAND flash structure for driver - * 10-24-2000 SJH Added prototype for 'nand_scan' function + * 10-11-2000 SJH Added private NAND flash structure for driver + * 10-24-2000 SJH Added prototype for 'nand_scan' function * 10-29-2001 TG changed nand_chip structure to support * hardwarespecific function for accessing control lines * 02-21-2002 TG added support for different read/write adress and @@ -36,7 +36,7 @@ * CONFIG_MTD_NAND_ECC_JFFS2 is not set * 08-10-2002 TG extensions to nand_chip structure to support HW-ECC * - * 08-29-2002 tglx nand_chip structure: data_poi for selecting + * 08-29-2002 tglx nand_chip structure: data_poi for selecting * internal / fs-driver buffer * support for 6byte/512byte hardware ECC * read_ecc, write_ecc extended for different oob-layout @@ -45,8 +45,8 @@ * 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL * Split manufacturer and device ID structures * - * 02-08-2004 tglx added option field to nand structure for chip anomalities - * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id + * 02-08-2004 tglx added option field to nand structure for chip anomalities + * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id * update of nand_chip structure description */ #ifndef __LINUX_MTD_NAND_H @@ -75,7 +75,7 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_ * Constants for hardware specific CLE/ALE/NCE function */ /* Select the chip by setting nCE to low */ -#define NAND_CTL_SETNCE 1 +#define NAND_CTL_SETNCE 1 /* Deselect the chip by setting nCE to high */ #define NAND_CTL_CLRNCE 2 /* Select the command latch by setting CLE to high */ @@ -215,7 +215,7 @@ struct nand_chip; #if 0 /** * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices - * @lock: protection lock + * @lock: protection lock * @active: the mtd device which holds the controller currently */ struct nand_hw_control { @@ -244,20 +244,20 @@ struct nand_hw_control { * is read from the chip status register * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready - * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware + * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware * @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw) * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only * be provided if a hardware ECC is available * @erase_cmd: [INTERN] erase command write function, selectable due to AND support * @scan_bbt: [REPLACEABLE] function to scan bad block table * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines - * @eccsize: [INTERN] databytes used per ecc-calculation - * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step + * @eccsize: [INTERN] databytes used per ecc-calculation + * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step * @eccsteps: [INTERN] number of ecc calculation steps per page * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) * @chip_lock: [INTERN] spinlock used to protect access to this structure and the chip * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress - * @state: [INTERN] the current state of the NAND device + * @state: [INTERN] the current state of the NAND device * @page_shift: [INTERN] number of address bits in a page (column address bits) * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry @@ -284,7 +284,7 @@ struct nand_hw_control { struct nand_chip { void __iomem *IO_ADDR_R; - void __iomem *IO_ADDR_W; + void __iomem *IO_ADDR_W; u_char (*read_byte)(struct mtd_info *mtd); void (*write_byte)(struct mtd_info *mtd, u_char byte); @@ -297,12 +297,12 @@ struct nand_chip { void (*select_chip)(struct mtd_info *mtd, int chip); int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); - void (*hwcontrol)(struct mtd_info *mtd, int cmd); - int (*dev_ready)(struct mtd_info *mtd); - void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); - int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state); + void (*hwcontrol)(struct mtd_info *mtd, int cmd); + int (*dev_ready)(struct mtd_info *mtd); + void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); + int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state); int (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code); - int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc); + int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc); void (*enable_hwecc)(struct mtd_info *mtd, int mode); void (*erase_cmd)(struct mtd_info *mtd, int page); int (*scan_bbt)(struct mtd_info *mtd); @@ -310,17 +310,17 @@ struct nand_chip { int eccsize; int eccbytes; int eccsteps; - int chip_delay; + int chip_delay; #if 0 spinlock_t chip_lock; wait_queue_head_t wq; - nand_state_t state; + nand_state_t state; #endif - int page_shift; + int page_shift; int phys_erase_shift; int bbt_erase_shift; int chip_shift; - u_char *data_buf; + u_char *data_buf; u_char *oob_buf; int oobdirty; u_char *data_poi; @@ -335,7 +335,7 @@ struct nand_chip { struct nand_bbt_descr *bbt_td; struct nand_bbt_descr *bbt_md; struct nand_bbt_descr *badblock_pattern; - struct nand_hw_control *controller; + struct nand_hw_control *controller; void *priv; }; @@ -352,14 +352,14 @@ struct nand_chip { /** * struct nand_flash_dev - NAND Flash Device ID Structure * - * @name: Identify the device type - * @id: device ID code - * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 + * @name: Identify the device type + * @id: device ID code + * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 * If the pagesize is 0, then the real pagesize * and the eraseize are determined from the * extended id bytes in the chip - * @erasesize: Size of an erase block in the flash device. - * @chipsize: Total chipsize in Mega Bytes + * @erasesize: Size of an erase block in the flash device. + * @chipsize: Total chipsize in Mega Bytes * @options: Bitfield to store chip relevant options */ struct nand_flash_dev { @@ -374,7 +374,7 @@ struct nand_flash_dev { /** * struct nand_manufacturers - NAND Flash Manufacturer ID Structure * @name: Manufacturer name - * @id: manufacturer ID code of device. + * @id: manufacturer ID code of device. */ struct nand_manufacturers { int id; @@ -398,7 +398,7 @@ extern struct nand_manufacturers nand_manuf_ids[]; * blocks is reserved at the end of the device where the tables are * written. * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than - * bad) block in the stored bbt + * bad) block in the stored bbt * @pattern: pattern to identify bad block table or factory marked good / * bad blocks, can be NULL, if len = 0 * @@ -412,11 +412,11 @@ struct nand_bbt_descr { int pages[NAND_MAX_CHIPS]; int offs; int veroffs; - uint8_t version[NAND_MAX_CHIPS]; + uint8_t version[NAND_MAX_CHIPS]; int len; - int maxblocks; + int maxblocks; int reserved_block_code; - uint8_t *pattern; + uint8_t *pattern; }; /* Options for the bad block table descriptors */ @@ -428,7 +428,7 @@ struct nand_bbt_descr { #define NAND_BBT_4BIT 0x00000004 #define NAND_BBT_8BIT 0x00000008 /* The bad block table is in the last good block of the device */ -#define NAND_BBT_LASTBLOCK 0x00000010 +#define NAND_BBT_LASTBLOCK 0x00000010 /* The bbt is at the given page, else we must scan for the bbt */ #define NAND_BBT_ABSPAGE 0x00000020 /* The bbt is at the given page, else we must scan for the bbt */ @@ -451,7 +451,7 @@ struct nand_bbt_descr { #define NAND_BBT_SCAN2NDPAGE 0x00004000 /* The maximum number of blocks to scan for a bbt */ -#define NAND_BBT_SCAN_MAXBLOCKS 4 +#define NAND_BBT_SCAN_MAXBLOCKS 4 extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd); extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs); diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index 50a6ac1..daa4d5f 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -235,20 +235,30 @@ /* General Purpose Timers registers */ #define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0) #define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4) +#define MPC5XXX_GPT0_STATUS (MPC5XXX_GPT + 0x0C) #define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10) #define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14) +#define MPC5XXX_GPT1_STATUS (MPC5XXX_GPT + 0x1C) #define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20) #define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24) +#define MPC5XXX_GPT2_STATUS (MPC5XXX_GPT + 0x2C) #define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30) #define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34) +#define MPC5XXX_GPT3_STATUS (MPC5XXX_GPT + 0x3C) #define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40) #define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44) +#define MPC5XXX_GPT4_STATUS (MPC5XXX_GPT + 0x4C) #define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50) +#define MPC5XXX_GPT5_STATUS (MPC5XXX_GPT + 0x5C) #define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54) #define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60) #define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64) +#define MPC5XXX_GPT6_STATUS (MPC5XXX_GPT + 0x6C) #define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70) #define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74) +#define MPC5XXX_GPT7_STATUS (MPC5XXX_GPT + 0x7C) + +#define MPC5XXX_GPT_GPIO_PIN(status) ((0x00000100 & (status)) >> 8) #define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78) diff --git a/include/mpc86xx.h b/include/mpc86xx.h new file mode 100644 index 0000000..bc8ba3f --- /dev/null +++ b/include/mpc86xx.h @@ -0,0 +1,116 @@ +/* + * Copyright 2006 Freescale Semiconductor. + * Jeffrey Brown + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + */ + +#ifndef __MPC86xx_H__ +#define __MPC86xx_H__ + +#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ + +/* + * l2cr values. Look in config_<BOARD>.h for the actual setup + */ +#define l2cr 1017 + +#define L2CR_L2E 0x80000000 /* bit 0 - enable */ +#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */ +#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */ +#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */ +#define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */ +#define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */ +#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ +#define L2CR_L2IP 0x00000001 /* global invalidate in progress */ + +/* + * BAT settings. Look in config_<BOARD>.h for the actual setup + */ + +#define BATU_BL_128K 0x00000000 +#define BATU_BL_256K 0x00000004 +#define BATU_BL_512K 0x0000000c +#define BATU_BL_1M 0x0000001c +#define BATU_BL_2M 0x0000003c +#define BATU_BL_4M 0x0000007c +#define BATU_BL_8M 0x000000fc +#define BATU_BL_16M 0x000001fc +#define BATU_BL_32M 0x000003fc +#define BATU_BL_64M 0x000007fc +#define BATU_BL_128M 0x00000ffc +#define BATU_BL_256M 0x00001ffc +#define BATU_BL_512M 0x00003ffc +#define BATU_BL_1G 0x00007ffc +#define BATU_BL_2G 0x0000fffc +#define BATU_BL_4G 0x0001fffc + +#define BATU_VS 0x00000002 +#define BATU_VP 0x00000001 +#define BATU_INVALID 0x00000000 + +#define BATL_WRITETHROUGH 0x00000040 +#define BATL_CACHEINHIBIT 0x00000020 +#define BATL_MEMCOHERENCE 0x00000010 +#define BATL_GUARDEDSTORAGE 0x00000008 +#define BATL_NO_ACCESS 0x00000000 + +#define BATL_PP_MSK 0x00000003 +#define BATL_PP_00 0x00000000 /* No access */ +#define BATL_PP_01 0x00000001 /* Read-only */ +#define BATL_PP_10 0x00000002 /* Read-write */ +#define BATL_PP_11 0x00000003 + +#define BATL_PP_NO_ACCESS BATL_PP_00 +#define BATL_PP_RO BATL_PP_01 +#define BATL_PP_RW BATL_PP_10 + +#define HID0_XBSEN 0x00000100 +#define HID0_HIGH_BAT_EN 0x00800000 +#define HID0_XAEN 0x00020000 + +#ifndef __ASSEMBLY__ + +typedef struct { + unsigned long freqProcessor; + unsigned long freqSystemBus; +} MPC86xx_SYS_INFO; + +#define l1icache_enable icache_enable + +void l2cache_enable(void); +void l1dcache_enable(void); + +static __inline__ unsigned long get_hid0 (void) +{ + unsigned long hid0; + asm volatile("mfspr %0, 1008" : "=r" (hid0) :); + return hid0; +} + +static __inline__ unsigned long get_hid1 (void) +{ + unsigned long hid1; + asm volatile("mfspr %0, 1009" : "=r" (hid1) :); + return hid1; +} + +static __inline__ void set_hid0 (unsigned long hid0) +{ + asm volatile("mtspr 1008, %0" : : "r" (hid0)); +} + +static __inline__ void set_hid1 (unsigned long hid1) +{ + asm volatile("mtspr 1009, %0" : : "r" (hid1)); +} + + +static __inline__ unsigned long get_l2cr (void) +{ + unsigned long l2cr_val; + asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :); + return l2cr_val; +} + +#endif /* _ASMLANGUAGE */ +#endif /* __MPC86xx_H__ */ diff --git a/include/ns16550.h b/include/ns16550.h index 996d915..34888a1 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -7,7 +7,7 @@ * added prototypes for ns16550.c * reduced no of com ports to 2 * modifications (c) Rob Taylor, Flying Pig Systems. 2000. - * + * * added support for port on 64-bit bus * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems */ diff --git a/include/pci_ids.h b/include/pci_ids.h index 8cc3ec0..3b10452 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1045,6 +1045,9 @@ #define PCI_DEVICE_ID_REALTEK_8139 0x8139 #define PCI_DEVICE_ID_REALTEK_8169 0x8169 +#define PCI_VENDOR_ID_DLINK 0x1186 +#define PCI_DEVICE_ID_DLINK_8139 0x1300 + #define PCI_VENDOR_ID_XILINX 0x10ee #define PCI_DEVICE_ID_TURBOPAM 0x4020 diff --git a/include/pcmcia.h b/include/pcmcia.h index 43d4510..8f564da 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -308,4 +308,14 @@ typedef struct { #endif /* CFG_CMD_PCMCIA || CFG_CMD_IDE && (CONFIG_IDE_8xx_PCCARD || CONFIG_IDE_8xx_DIRECT) */ +#ifdef CONFIG_8xx +extern u_int *pcmcia_pgcrx[]; +#define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot]) +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) \ + || defined(CONFIG_PXA_PCMCIA) +extern int check_ide_device(int slot); +#endif + #endif /* _PCMCIA_H */ diff --git a/include/ppc440.h b/include/ppc440.h index 53f14b5..d5a9f66 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -25,6 +25,8 @@ /*--------------------------------------------------------------------- */ /* Special Purpose Registers */ /*--------------------------------------------------------------------- */ +#define xer_reg 0x001 +#define lr_reg 0x008 #define dec 0x016 /* decrementer */ #define srr0 0x01a /* save/restore register 0 */ #define srr1 0x01b /* save/restore register 1 */ @@ -37,6 +39,8 @@ #define ivpr 0x03f /* interrupt prefix register */ #define usprg0 0x100 /* user special purpose register general 0 */ #define usprg1 0x110 /* user special purpose register general 1 */ +#define tblr 0x10c /* time base lower, read only */ +#define tbur 0x10d /* time base upper, read only */ #define sprg1 0x111 /* special purpose register general 1 */ #define sprg2 0x112 /* special purpose register general 2 */ #define sprg3 0x113 /* special purpose register general 3 */ @@ -78,7 +82,7 @@ #define ivor13 0x19d /* interrupt vector offset register 13 */ #define ivor14 0x19e /* interrupt vector offset register 14 */ #define ivor15 0x19f /* interrupt vector offset register 15 */ -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define mcsrr0 0x23a /* machine check save/restore register 0 */ #define mcsrr1 0x23b /* mahcine check save/restore register 1 */ #define mcsr 0x23c /* machine check status register */ @@ -167,12 +171,10 @@ #define sdr_malrbl 0x02a0 #define sdr_maltbs 0x02c0 #define sdr_malrbs 0x02e0 -#define sdr_pci0 0x0300 -#define sdr_usb0 0x0320 +#define sdr_pci0 0x0300 +#define sdr_usb0 0x0320 #define sdr_cust0 0x4000 -#define sdr_sdstp2 0x4001 #define sdr_cust1 0x4002 -#define sdr_sdstp3 0x4003 #define sdr_pfc0 0x4100 /* Pin Function 0 */ #define sdr_pfc1 0x4101 /* Pin Function 1 */ #define sdr_plbtr 0x4200 @@ -212,6 +214,551 @@ #define mem_dlycal 0x0084 /* delay line calibration register */ #define mem_eccesr 0x0098 /* ECC error status */ +#ifdef CONFIG_440GX +#define sdr_amp 0x0240 +#define sdr_xpllc 0x01c1 +#define sdr_xplld 0x01c2 +#define sdr_xcr 0x01c0 +#define sdr_sdstp2 0x4001 +#define sdr_sdstp3 0x4003 +#endif /* CONFIG_440GX */ + +#ifdef CONFIG_440SPE +#undef sdr_sdstp2 +#define sdr_sdstp2 0x0022 +#undef sdr_sdstp3 +#define sdr_sdstp3 0x0023 +#define sdr_ddr0 0x00E1 +#define sdr_uart2 0x0122 +#define sdr_xcr0 0x01c0 +/* #define sdr_xcr1 0x01c3 only one PCIX - SG */ +/* #define sdr_xcr2 0x01c6 only one PCIX - SG */ +#define sdr_xpllc0 0x01c1 +#define sdr_xplld0 0x01c2 +#define sdr_xpllc1 0x01c4 /*notRCW - SG */ +#define sdr_xplld1 0x01c5 /*notRCW - SG */ +#define sdr_xpllc2 0x01c7 /*notRCW - SG */ +#define sdr_xplld2 0x01c8 /*notRCW - SG */ +#define sdr_amp0 0x0240 +#define sdr_amp1 0x0241 +#define sdr_cust2 0x4004 +#define sdr_cust3 0x4006 +#define sdr_sdstp4 0x4001 +#define sdr_sdstp5 0x4003 +#define sdr_sdstp6 0x4005 +#define sdr_sdstp7 0x4007 + +/*----------------------------------------------------------------------------+ +| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only). ++----------------------------------------------------------------------------*/ +#define CCR0_PRE 0x40000000 +#define CCR0_CRPE 0x08000000 +#define CCR0_DSTG 0x00200000 +#define CCR0_DAPUIB 0x00100000 +#define CCR0_DTB 0x00008000 +#define CCR0_GICBT 0x00004000 +#define CCR0_GDCBT 0x00002000 +#define CCR0_FLSTA 0x00000100 +#define CCR0_ICSLC_MASK 0x0000000C +#define CCR0_ICSLT_MASK 0x00000003 +#define CCR1_TCS_MASK 0x00000080 +#define CCR1_TCS_INTCLK 0x00000000 +#define CCR1_TCS_EXTCLK 0x00000080 +#define MMUCR_SEOA 0x01000000 +#define MMUCR_U1TE 0x00400000 +#define MMUCR_U2SWOAE 0x00200000 +#define MMUCR_DULXE 0x00800000 +#define MMUCR_IULXE 0x00400000 +#define MMUCR_STS 0x00100000 +#define MMUCR_STID_MASK 0x000000FF + +#define SDR0_CFGADDR 0x00E +#define SDR0_CFGDATA 0x00F + +/****************************************************************************** + * PCI express defines + ******************************************************************************/ +#define SDR0_PE0UTLSET1 0x00000300 /* PE0 Upper transaction layer conf setting */ +#define SDR0_PE0UTLSET2 0x00000301 /* PE0 Upper transaction layer conf setting 2 */ +#define SDR0_PE0DLPSET 0x00000302 /* PE0 Data link & logical physical configuration */ +#define SDR0_PE0LOOP 0x00000303 /* PE0 Loopback interface status */ +#define SDR0_PE0RCSSET 0x00000304 /* PE0 Reset, clock & shutdown setting */ +#define SDR0_PE0RCSSTS 0x00000305 /* PE0 Reset, clock & shutdown status */ +#define SDR0_PE0HSSSET1L0 0x00000306 /* PE0 HSS Control Setting 1: Lane 0 */ +#define SDR0_PE0HSSSET2L0 0x00000307 /* PE0 HSS Control Setting 2: Lane 0 */ +#define SDR0_PE0HSSSTSL0 0x00000308 /* PE0 HSS Control Status : Lane 0 */ +#define SDR0_PE0HSSSET1L1 0x00000309 /* PE0 HSS Control Setting 1: Lane 1 */ +#define SDR0_PE0HSSSET2L1 0x0000030A /* PE0 HSS Control Setting 2: Lane 1 */ +#define SDR0_PE0HSSSTSL1 0x0000030B /* PE0 HSS Control Status : Lane 1 */ +#define SDR0_PE0HSSSET1L2 0x0000030C /* PE0 HSS Control Setting 1: Lane 2 */ +#define SDR0_PE0HSSSET2L2 0x0000030D /* PE0 HSS Control Setting 2: Lane 2 */ +#define SDR0_PE0HSSSTSL2 0x0000030E /* PE0 HSS Control Status : Lane 2 */ +#define SDR0_PE0HSSSET1L3 0x0000030F /* PE0 HSS Control Setting 1: Lane 3 */ +#define SDR0_PE0HSSSET2L3 0x00000310 /* PE0 HSS Control Setting 2: Lane 3 */ +#define SDR0_PE0HSSSTSL3 0x00000311 /* PE0 HSS Control Status : Lane 3 */ +#define SDR0_PE0HSSSET1L4 0x00000312 /* PE0 HSS Control Setting 1: Lane 4 */ +#define SDR0_PE0HSSSET2L4 0x00000313 /* PE0 HSS Control Setting 2: Lane 4 */ +#define SDR0_PE0HSSSTSL4 0x00000314 /* PE0 HSS Control Status : Lane 4 */ +#define SDR0_PE0HSSSET1L5 0x00000315 /* PE0 HSS Control Setting 1: Lane 5 */ +#define SDR0_PE0HSSSET2L5 0x00000316 /* PE0 HSS Control Setting 2: Lane 5 */ +#define SDR0_PE0HSSSTSL5 0x00000317 /* PE0 HSS Control Status : Lane 5 */ +#define SDR0_PE0HSSSET1L6 0x00000318 /* PE0 HSS Control Setting 1: Lane 6 */ +#define SDR0_PE0HSSSET2L6 0x00000319 /* PE0 HSS Control Setting 2: Lane 6 */ +#define SDR0_PE0HSSSTSL6 0x0000031A /* PE0 HSS Control Status : Lane 6 */ +#define SDR0_PE0HSSSET1L7 0x0000031B /* PE0 HSS Control Setting 1: Lane 7 */ +#define SDR0_PE0HSSSET2L7 0x0000031C /* PE0 HSS Control Setting 2: Lane 7 */ +#define SDR0_PE0HSSSTSL7 0x0000031D /* PE0 HSS Control Status : Lane 7 */ +#define SDR0_PE0HSSSEREN 0x0000031E /* PE0 Serdes Transmitter Enable */ +#define SDR0_PE0LANEABCD 0x0000031F /* PE0 Lanes ABCD affectation */ +#define SDR0_PE0LANEEFGH 0x00000320 /* PE0 Lanes EFGH affectation */ + +#define SDR0_PE1UTLSET1 0x00000340 /* PE1 Upper transaction layer conf setting */ +#define SDR0_PE1UTLSET2 0x00000341 /* PE1 Upper transaction layer conf setting 2 */ +#define SDR0_PE1DLPSET 0x00000342 /* PE1 Data link & logical physical configuration */ +#define SDR0_PE1LOOP 0x00000343 /* PE1 Loopback interface status */ +#define SDR0_PE1RCSSET 0x00000344 /* PE1 Reset, clock & shutdown setting */ +#define SDR0_PE1RCSSTS 0x00000345 /* PE1 Reset, clock & shutdown status */ +#define SDR0_PE1HSSSET1L0 0x00000346 /* PE1 HSS Control Setting 1: Lane 0 */ +#define SDR0_PE1HSSSET2L0 0x00000347 /* PE1 HSS Control Setting 2: Lane 0 */ +#define SDR0_PE1HSSSTSL0 0x00000348 /* PE1 HSS Control Status : Lane 0 */ +#define SDR0_PE1HSSSET1L1 0x00000349 /* PE1 HSS Control Setting 1: Lane 1 */ +#define SDR0_PE1HSSSET2L1 0x0000034A /* PE1 HSS Control Setting 2: Lane 1 */ +#define SDR0_PE1HSSSTSL1 0x0000034B /* PE1 HSS Control Status : Lane 1 */ +#define SDR0_PE1HSSSET1L2 0x0000034C /* PE1 HSS Control Setting 1: Lane 2 */ +#define SDR0_PE1HSSSET2L2 0x0000034D /* PE1 HSS Control Setting 2: Lane 2 */ +#define SDR0_PE1HSSSTSL2 0x0000034E /* PE1 HSS Control Status : Lane 2 */ +#define SDR0_PE1HSSSET1L3 0x0000034F /* PE1 HSS Control Setting 1: Lane 3 */ +#define SDR0_PE1HSSSET2L3 0x00000350 /* PE1 HSS Control Setting 2: Lane 3 */ +#define SDR0_PE1HSSSTSL3 0x00000351 /* PE1 HSS Control Status : Lane 3 */ +#define SDR0_PE1HSSSEREN 0x00000352 /* PE1 Serdes Transmitter Enable */ +#define SDR0_PE1LANEABCD 0x00000353 /* PE1 Lanes ABCD affectation */ +#define SDR0_PE2UTLSET1 0x00000370 /* PE2 Upper transaction layer conf setting */ +#define SDR0_PE2UTLSET2 0x00000371 /* PE2 Upper transaction layer conf setting 2 */ +#define SDR0_PE2DLPSET 0x00000372 /* PE2 Data link & logical physical configuration */ +#define SDR0_PE2LOOP 0x00000373 /* PE2 Loopback interface status */ +#define SDR0_PE2RCSSET 0x00000374 /* PE2 Reset, clock & shutdown setting */ +#define SDR0_PE2RCSSTS 0x00000375 /* PE2 Reset, clock & shutdown status */ +#define SDR0_PE2HSSSET1L0 0x00000376 /* PE2 HSS Control Setting 1: Lane 0 */ +#define SDR0_PE2HSSSET2L0 0x00000377 /* PE2 HSS Control Setting 2: Lane 0 */ +#define SDR0_PE2HSSSTSL0 0x00000378 /* PE2 HSS Control Status : Lane 0 */ +#define SDR0_PE2HSSSET1L1 0x00000379 /* PE2 HSS Control Setting 1: Lane 1 */ +#define SDR0_PE2HSSSET2L1 0x0000037A /* PE2 HSS Control Setting 2: Lane 1 */ +#define SDR0_PE2HSSSTSL1 0x0000037B /* PE2 HSS Control Status : Lane 1 */ +#define SDR0_PE2HSSSET1L2 0x0000037C /* PE2 HSS Control Setting 1: Lane 2 */ +#define SDR0_PE2HSSSET2L2 0x0000037D /* PE2 HSS Control Setting 2: Lane 2 */ +#define SDR0_PE2HSSSTSL2 0x0000037E /* PE2 HSS Control Status : Lane 2 */ +#define SDR0_PE2HSSSET1L3 0x0000037F /* PE2 HSS Control Setting 1: Lane 3 */ +#define SDR0_PE2HSSSET2L3 0x00000380 /* PE2 HSS Control Setting 2: Lane 3 */ +#define SDR0_PE2HSSSTSL3 0x00000381 /* PE2 HSS Control Status : Lane 3 */ +#define SDR0_PE2HSSSEREN 0x00000382 /* PE2 Serdes Transmitter Enable */ +#define SDR0_PE2LANEABCD 0x00000383 /* PE2 Lanes ABCD affectation */ +#define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */ +#define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */ +#define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */ + +/*----------------------------------------------------------------------------+ +| SDRAM Controller ++----------------------------------------------------------------------------*/ +/*-----------------------------------------------------------------------------+ +| SDRAM DLYCAL Options ++-----------------------------------------------------------------------------*/ +#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC +#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) +#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) + +/*----------------------------------------------------------------------------+ +| Memory queue defines ++----------------------------------------------------------------------------*/ +/* A REVOIR versus RWC - SG*/ +#define SDRAMQ_DCR_BASE 0x040 + +#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */ +#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */ +#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */ +#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */ +#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */ +#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */ +#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */ +#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */ +#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */ +#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */ +#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */ +#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */ +#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */ +#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */ +#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */ + +/*-----------------------------------------------------------------------------+ +| Memory Bank 0-7 configuration ++-----------------------------------------------------------------------------*/ +#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */ +#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2) +#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2) +#define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */ +#define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<6) +#define SDRAM_RXBAS_SDSZ_DECODE(n) ((((unsigned long)(n))>>6)&0x3FF) +#define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */ +#define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */ +#define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */ +#define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */ +#define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */ +#define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */ +#define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */ +#define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */ +#define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */ +#define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */ +#define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */ + +/*----------------------------------------------------------------------------+ +| Memory controller defines ++----------------------------------------------------------------------------*/ +#define SDRAMC_DCR_BASE 0x010 +#define SDRAMC_CFGADDR (SDRAMC_DCR_BASE+0x0) /* Memory configuration add */ +#define SDRAMC_CFGDATA (SDRAMC_DCR_BASE+0x1) /* Memory configuration data */ + +/* A REVOIR versus specs 4 bank - SG*/ +#define SDRAM_MCSTAT 0x14 /* memory controller status */ +#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ +#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ +#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ +#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */ +#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */ +#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */ +#define SDRAM_CODT 0x26 /* on die termination for controller */ +#define SDRAM_VVPR 0x27 /* variable VRef programmming */ +#define SDRAM_OPARS 0x28 /* on chip driver control setup */ +#define SDRAM_OPART 0x29 /* on chip driver control trigger */ +#define SDRAM_RTR 0x30 /* refresh timer */ +#define SDRAM_PMIT 0x34 /* power management idle timer */ +#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */ +#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */ +#define SDRAM_MB2CF 0x48 +#define SDRAM_MB3CF 0x4C +#define SDRAM_INITPLR0 0x50 /* manual initialization control */ +#define SDRAM_INITPLR1 0x51 /* manual initialization control */ +#define SDRAM_INITPLR2 0x52 /* manual initialization control */ +#define SDRAM_INITPLR3 0x53 /* manual initialization control */ +#define SDRAM_INITPLR4 0x54 /* manual initialization control */ +#define SDRAM_INITPLR5 0x55 /* manual initialization control */ +#define SDRAM_INITPLR6 0x56 /* manual initialization control */ +#define SDRAM_INITPLR7 0x57 /* manual initialization control */ +#define SDRAM_INITPLR8 0x58 /* manual initialization control */ +#define SDRAM_INITPLR9 0x59 /* manual initialization control */ +#define SDRAM_INITPLR10 0x5a /* manual initialization control */ +#define SDRAM_INITPLR11 0x5b /* manual initialization control */ +#define SDRAM_INITPLR12 0x5c /* manual initialization control */ +#define SDRAM_INITPLR13 0x5d /* manual initialization control */ +#define SDRAM_INITPLR14 0x5e /* manual initialization control */ +#define SDRAM_INITPLR15 0x5f /* manual initialization control */ +#define SDRAM_RQDC 0x70 /* read DQS delay control */ +#define SDRAM_RFDC 0x74 /* read feedback delay control */ +#define SDRAM_RDCC 0x78 /* read data capture control */ +#define SDRAM_DLCR 0x7A /* delay line calibration */ +#define SDRAM_CLKTR 0x80 /* DDR clock timing */ +#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */ +#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */ +#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */ +#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */ +#define SDRAM_MMODE 0x88 /* memory mode */ +#define SDRAM_MEMODE 0x89 /* memory extended mode */ +#define SDRAM_ECCCR 0x98 /* ECC error status */ +#define SDRAM_CID 0xA4 /* core ID */ +#define SDRAM_RID 0xA8 /* revision ID */ + +/*-----------------------------------------------------------------------------+ +| Memory Controller Status ++-----------------------------------------------------------------------------*/ +#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */ +#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */ +#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */ +#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */ +#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */ +#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */ + +/*-----------------------------------------------------------------------------+ +| Memory Controller Options 1 ++-----------------------------------------------------------------------------*/ +#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/ +#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */ +#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */ +#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */ +#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/ +#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3) +#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */ +#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */ +#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */ +#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */ +#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */ +#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */ +#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */ +#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */ +#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */ +#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */ +#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */ +#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */ +#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */ +#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */ +#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */ +#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */ +#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */ +#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */ +#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */ +#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */ +#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */ +#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */ +#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */ +#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */ +#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */ +#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */ +#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */ +#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */ +#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */ + +/*-----------------------------------------------------------------------------+ +| Memory Controller Options 2 ++-----------------------------------------------------------------------------*/ +#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */ +#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */ +#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */ +#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */ +#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */ +#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */ +#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */ +#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */ +#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */ +#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */ +#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */ +#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */ +#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */ +#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */ +#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */ +#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/ +#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */ +#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */ + +/*-----------------------------------------------------------------------------+ +| SDRAM Refresh Timer Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RTR_RINT_MASK 0xFFF80000 +#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16) +#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8) + +/*-----------------------------------------------------------------------------+ +| SDRAM Read DQS Delay Control Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RQDC_RQDE_MASK 0x80000000 +#define SDRAM_RQDC_RQDE_DISABLE 0x00000000 +#define SDRAM_RQDC_RQDE_ENABLE 0x80000000 +#define SDRAM_RQDC_RQFD_MASK 0x000001FF +#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) + +#define SDRAM_RQDC_RQFD_MAX 0x1FF + +/*-----------------------------------------------------------------------------+ +| SDRAM Read Data Capture Control Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RDCC_RDSS_MASK 0xC0000000 +#define SDRAM_RDCC_RDSS_T1 0x00000000 +#define SDRAM_RDCC_RDSS_T2 0x40000000 +#define SDRAM_RDCC_RDSS_T3 0x80000000 +#define SDRAM_RDCC_RDSS_T4 0xC0000000 +#define SDRAM_RDCC_RSAE_MASK 0x00000001 +#define SDRAM_RDCC_RSAE_DISABLE 0x00000001 +#define SDRAM_RDCC_RSAE_ENABLE 0x00000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM Read Feedback Delay Control Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RFDC_ARSE_MASK 0x80000000 +#define SDRAM_RFDC_ARSE_DISABLE 0x80000000 +#define SDRAM_RFDC_ARSE_ENABLE 0x00000000 +#define SDRAM_RFDC_RFOS_MASK 0x007F0000 +#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define SDRAM_RFDC_RFFD_MASK 0x000003FF +#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) + +#define SDRAM_RFDC_RFFD_MAX 0x7FF + +/*-----------------------------------------------------------------------------+ +| SDRAM Delay Line Calibration Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_DLCR_DCLM_MASK 0x80000000 +#define SDRAM_DLCR_DCLM_MANUEL 0x80000000 +#define SDRAM_DLCR_DCLM_AUTO 0x00000000 +#define SDRAM_DLCR_DLCR_MASK 0x08000000 +#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000 +#define SDRAM_DLCR_DLCR_IDLE 0x00000000 +#define SDRAM_DLCR_DLCS_MASK 0x07000000 +#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000 +#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000 +#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000 +#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000 +#define SDRAM_DLCR_DLCS_ERROR 0x04000000 +#define SDRAM_DLCR_DLCV_MASK 0x000001FF +#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) +#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF) + +/*-----------------------------------------------------------------------------+ +| SDRAM Controller On Die Termination Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_CODT_ODT_ON 0x80000000 +#define SDRAM_CODT_ODT_OFF 0x00000000 +#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020 +#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000 +#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020 +#define SDRAM_CODT_DQS_MASK 0x00000010 +#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000 +#define SDRAM_CODT_DQS_SINGLE_END 0x00000010 +#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000 +#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 +#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 +#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 +#define SDRAM_CODT_IO_HIZ 0x00000000 +#define SDRAM_CODT_IO_NMODE 0x00000001 + +/*-----------------------------------------------------------------------------+ +| SDRAM Mode Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_MMODE_WR_MASK 0x00000E00 +#define SDRAM_MMODE_WR_DDR1 0x00000000 +#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400 +#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600 +#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800 +#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00 +#define SDRAM_MMODE_DCL_MASK 0x00000070 +#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020 +#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060 +#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030 +#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020 +#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030 +#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040 +#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050 +#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060 +#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070 + +/*-----------------------------------------------------------------------------+ +| SDRAM Extended Mode Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_MEMODE_DIC_MASK 0x00000002 +#define SDRAM_MEMODE_DIC_NORMAL 0x00000000 +#define SDRAM_MEMODE_DIC_WEAK 0x00000002 +#define SDRAM_MEMODE_DLL_MASK 0x00000001 +#define SDRAM_MEMODE_DLL_DISABLE 0x00000001 +#define SDRAM_MEMODE_DLL_ENABLE 0x00000000 +#define SDRAM_MEMODE_RTT_MASK 0x00000044 +#define SDRAM_MEMODE_RTT_DISABLED 0x00000000 +#define SDRAM_MEMODE_RTT_75OHM 0x00000004 +#define SDRAM_MEMODE_RTT_150OHM 0x00000040 +#define SDRAM_MEMODE_DQS_MASK 0x00000400 +#define SDRAM_MEMODE_DQS_DISABLE 0x00000400 +#define SDRAM_MEMODE_DQS_ENABLE 0x00000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM Clock Timing Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 +#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000 +#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM Write Timing Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_WRDTR_LLWP_MASK 0x10000000 +#define SDRAM_WRDTR_LLWP_DIS 0x10000000 +#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000 +#define SDRAM_WRDTR_WTR_MASK 0x0E000000 +#define SDRAM_WRDTR_WTR_0_DEG 0x06000000 +#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000 +#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM SDTR1 Options ++-----------------------------------------------------------------------------*/ +#define SDRAM_SDTR1_LDOF_MASK 0x80000000 +#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000 +#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000 +#define SDRAM_SDTR1_RTW_MASK 0x00F00000 +#define SDRAM_SDTR1_RTW_2_CLK 0x00200000 +#define SDRAM_SDTR1_RTW_3_CLK 0x00300000 +#define SDRAM_SDTR1_WTWO_MASK 0x000F0000 +#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000 +#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000 +#define SDRAM_SDTR1_RTRO_MASK 0x0000F000 +#define SDRAM_SDTR1_RTRO_1_CLK 0x00001000 +#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000 + +/*-----------------------------------------------------------------------------+ +| SDRAM SDTR2 Options ++-----------------------------------------------------------------------------*/ +#define SDRAM_SDTR2_RCD_MASK 0xF0000000 +#define SDRAM_SDTR2_RCD_1_CLK 0x10000000 +#define SDRAM_SDTR2_RCD_2_CLK 0x20000000 +#define SDRAM_SDTR2_RCD_3_CLK 0x30000000 +#define SDRAM_SDTR2_RCD_4_CLK 0x40000000 +#define SDRAM_SDTR2_RCD_5_CLK 0x50000000 +#define SDRAM_SDTR2_WTR_MASK 0x0F000000 +#define SDRAM_SDTR2_WTR_1_CLK 0x01000000 +#define SDRAM_SDTR2_WTR_2_CLK 0x02000000 +#define SDRAM_SDTR2_WTR_3_CLK 0x03000000 +#define SDRAM_SDTR2_WTR_4_CLK 0x04000000 +#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) +#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000 +#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000 +#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000 +#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000 +#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000 +#define SDRAM_SDTR2_WPC_MASK 0x0000F000 +#define SDRAM_SDTR2_WPC_2_CLK 0x00002000 +#define SDRAM_SDTR2_WPC_3_CLK 0x00003000 +#define SDRAM_SDTR2_WPC_4_CLK 0x00004000 +#define SDRAM_SDTR2_WPC_5_CLK 0x00005000 +#define SDRAM_SDTR2_WPC_6_CLK 0x00006000 +#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12) +#define SDRAM_SDTR2_RPC_MASK 0x00000F00 +#define SDRAM_SDTR2_RPC_2_CLK 0x00000200 +#define SDRAM_SDTR2_RPC_3_CLK 0x00000300 +#define SDRAM_SDTR2_RPC_4_CLK 0x00000400 +#define SDRAM_SDTR2_RP_MASK 0x000000F0 +#define SDRAM_SDTR2_RP_3_CLK 0x00000030 +#define SDRAM_SDTR2_RP_4_CLK 0x00000040 +#define SDRAM_SDTR2_RP_5_CLK 0x00000050 +#define SDRAM_SDTR2_RP_6_CLK 0x00000060 +#define SDRAM_SDTR2_RP_7_CLK 0x00000070 +#define SDRAM_SDTR2_RRD_MASK 0x0000000F +#define SDRAM_SDTR2_RRD_2_CLK 0x00000002 +#define SDRAM_SDTR2_RRD_3_CLK 0x00000003 + +/*-----------------------------------------------------------------------------+ +| SDRAM SDTR3 Options ++-----------------------------------------------------------------------------*/ +#define SDRAM_SDTR3_RAS_MASK 0x1F000000 +#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define SDRAM_SDTR3_RC_MASK 0x001F0000 +#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) +#define SDRAM_SDTR3_XCS_MASK 0x00001F00 +#define SDRAM_SDTR3_XCS 0x00000D00 +#define SDRAM_SDTR3_RFC_MASK 0x0000003F +#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) + +/*-----------------------------------------------------------------------------+ +| Memory Bank 0-1 configuration ++-----------------------------------------------------------------------------*/ +#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */ +#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */ +#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */ +#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */ +#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */ +#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */ +#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */ +#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */ +#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */ +#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */ +#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */ +#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */ +#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */ +#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */ +#endif /* CONFIG_440SPE */ + /*----------------------------------------------------------------------------- | External Bus Controller +----------------------------------------------------------------------------*/ @@ -503,7 +1050,7 @@ /*----------------------------------------------------------------------------- | L2 Cache +----------------------------------------------------------------------------*/ -#if defined (CONFIG_440GX) || defined(CONFIG_440SP) +#if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define L2_CACHE_BASE 0x030 #define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */ #define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */ @@ -526,7 +1073,7 @@ | Clocking, Power Management and Chip Control +----------------------------------------------------------------------------*/ #define CNTRL_DCR_BASE 0x0b0 -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */ #define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */ #define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */ @@ -574,6 +1121,30 @@ #define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */ #define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ +#if defined(CONFIG_440SPE) +#define UIC2_DCR_BASE 0xe0 +#define uic2sr (UIC0_DCR_BASE+0x0) /* UIC2 status-Read Clear */ +#define uic2srs (UIC0_DCR_BASE+0x1) /* UIC2 status-Read Set */ +#define uic2er (UIC0_DCR_BASE+0x2) /* UIC2 enable */ +#define uic2cr (UIC0_DCR_BASE+0x3) /* UIC2 critical */ +#define uic2pr (UIC0_DCR_BASE+0x4) /* UIC2 polarity */ +#define uic2tr (UIC0_DCR_BASE+0x5) /* UIC2 triggering */ +#define uic2msr (UIC0_DCR_BASE+0x6) /* UIC2 masked status */ +#define uic2vr (UIC0_DCR_BASE+0x7) /* UIC2 vector */ +#define uic2vcr (UIC0_DCR_BASE+0x8) /* UIC2 vector configuration */ + +#define UIC3_DCR_BASE 0xf0 +#define uic3sr (UIC1_DCR_BASE+0x0) /* UIC3 status-Read Clear */ +#define uic3srs (UIC0_DCR_BASE+0x1) /* UIC3 status-Read Set */ +#define uic3er (UIC1_DCR_BASE+0x2) /* UIC3 enable */ +#define uic3cr (UIC1_DCR_BASE+0x3) /* UIC3 critical */ +#define uic3pr (UIC1_DCR_BASE+0x4) /* UIC3 polarity */ +#define uic3tr (UIC1_DCR_BASE+0x5) /* UIC3 triggering */ +#define uic3msr (UIC1_DCR_BASE+0x6) /* UIC3 masked status */ +#define uic3vr (UIC1_DCR_BASE+0x7) /* UIC3 vector */ +#define uic3vcr (UIC1_DCR_BASE+0x8) /* UIC3 vector configuration */ +#endif /* CONFIG_440SPE */ + #if defined(CONFIG_440GX) #define UIC2_DCR_BASE 0x210 #define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */ @@ -607,6 +1178,103 @@ #define uicvr uic0vr #define uicvcr uic0vcr +#if defined(CONFIG_440SPE) +/*----------------------------------------------------------------------------+ +| Clock / Power-on-reset DCR's. ++----------------------------------------------------------------------------*/ +#define CPR0_CFGADDR 0x00C +#define CPR0_CFGDATA 0x00D + +#define CPR0_CLKUPD 0x20 +#define CPR0_CLKUPD_BSY_MASK 0x80000000 +#define CPR0_CLKUPD_BSY_COMPLETED 0x00000000 +#define CPR0_CLKUPD_BSY_BUSY 0x80000000 +#define CPR0_CLKUPD_CUI_MASK 0x80000000 +#define CPR0_CLKUPD_CUI_DISABLE 0x00000000 +#define CPR0_CLKUPD_CUI_ENABLE 0x80000000 +#define CPR0_CLKUPD_CUD_MASK 0x40000000 +#define CPR0_CLKUPD_CUD_DISABLE 0x00000000 +#define CPR0_CLKUPD_CUD_ENABLE 0x40000000 + +#define CPR0_PLLC 0x40 +#define CPR0_PLLC_RST_MASK 0x80000000 +#define CPR0_PLLC_RST_PLLLOCKED 0x00000000 +#define CPR0_PLLC_RST_PLLRESET 0x80000000 +#define CPR0_PLLC_ENG_MASK 0x40000000 +#define CPR0_PLLC_ENG_DISABLE 0x00000000 +#define CPR0_PLLC_ENG_ENABLE 0x40000000 +#define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) +#define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01) +#define CPR0_PLLC_SRC_MASK 0x20000000 +#define CPR0_PLLC_SRC_PLLOUTA 0x00000000 +#define CPR0_PLLC_SRC_PLLOUTB 0x20000000 +#define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) +#define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01) +#define CPR0_PLLC_SEL_MASK 0x07000000 +#define CPR0_PLLC_SEL_PLLOUT 0x00000000 +#define CPR0_PLLC_SEL_CPU 0x01000000 +#define CPR0_PLLC_SEL_EBC 0x05000000 +#define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) +#define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07) +#define CPR0_PLLC_TUNE_MASK 0x000003FF +#define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) +#define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) + +#define CPR0_PLLD 0x60 +#define CPR0_PLLD_FBDV_MASK 0x1F000000 +#define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1) +#define CPR0_PLLD_FWDVA_MASK 0x000F0000 +#define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16) +#define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1) +#define CPR0_PLLD_FWDVB_MASK 0x00000700 +#define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8) +#define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1) +#define CPR0_PLLD_LFBDV_MASK 0x0000003F +#define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) +#define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1) + +#define CPR0_PRIMAD 0x80 +#define CPR0_PRIMAD_PRADV0_MASK 0x07000000 +#define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) +#define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) + +#define CPR0_PRIMBD 0xA0 +#define CPR0_PRIMBD_PRBDV0_MASK 0x07000000 +#define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) +#define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) + +#define CPR0_OPBD 0xC0 +#define CPR0_OPBD_OPBDV0_MASK 0x03000000 +#define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) +#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) + +#define CPR0_PERD 0xE0 +#define CPR0_PERD_PERDV0_MASK 0x03000000 +#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) +#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) + +#define CPR0_MALD 0x100 +#define CPR0_MALD_MALDV0_MASK 0x03000000 +#define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) +#define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) + +#define CPR0_ICFG 0x140 +#define CPR0_ICFG_RLI_MASK 0x80000000 +#define CPR0_ICFG_RLI_RESETCPR 0x00000000 +#define CPR0_ICFG_RLI_PRESERVECPR 0x80000000 +#define CPR0_ICFG_ICS_MASK 0x00000007 +#define CPR0_ICFG_ICS_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) +#define CPR0_ICFG_ICS_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1) + +/************************/ +/* IIC defines */ +/************************/ +#define IIC0_MMIO_BASE 0xA0000400 +#define IIC1_MMIO_BASE 0xA0000500 + +#endif /* CONFIG_440SP */ + /*----------------------------------------------------------------------------- | DMA +----------------------------------------------------------------------------*/ @@ -722,7 +1390,7 @@ #define UIC_GPTCT 0x00000004 /* GPT count timer */ #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ -#else /* CONFIG_440SP */ +#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) #define UIC_U0 0x80000000 /* UART 0 */ #define UIC_U1 0x40000000 /* UART 1 */ #define UIC_IIC0 0x20000000 /* IIC */ @@ -755,7 +1423,40 @@ #define UIC_EIR6 0x00000004 /* External interrupt 6 */ #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ -#endif /* CONFIG_440SP */ +#elif !defined(CONFIG_440SPE) +#define UIC_U0 0x80000000 /* UART 0 */ +#define UIC_U1 0x40000000 /* UART 1 */ +#define UIC_IIC0 0x20000000 /* IIC */ +#define UIC_IIC1 0x10000000 /* IIC */ +#define UIC_PIM 0x08000000 /* PCI inbound message */ +#define UIC_PCRW 0x04000000 /* PCI command register write */ +#define UIC_PPM 0x02000000 /* PCI power management */ +#define UIC_MSI0 0x01000000 /* PCI MSI level 0 */ +#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ +#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ +#define UIC_MTE 0x00200000 /* MAL TXEOB */ +#define UIC_MRE 0x00100000 /* MAL RXEOB */ +#define UIC_D0 0x00080000 /* DMA channel 0 */ +#define UIC_D1 0x00040000 /* DMA channel 1 */ +#define UIC_D2 0x00020000 /* DMA channel 2 */ +#define UIC_D3 0x00010000 /* DMA channel 3 */ +#define UIC_RSVD0 0x00008000 /* Reserved */ +#define UIC_RSVD1 0x00004000 /* Reserved */ +#define UIC_CT0 0x00002000 /* GPT compare timer 0 */ +#define UIC_CT1 0x00001000 /* GPT compare timer 1 */ +#define UIC_CT2 0x00000800 /* GPT compare timer 2 */ +#define UIC_CT3 0x00000400 /* GPT compare timer 3 */ +#define UIC_CT4 0x00000200 /* GPT compare timer 4 */ +#define UIC_EIR0 0x00000100 /* External interrupt 0 */ +#define UIC_EIR1 0x00000080 /* External interrupt 1 */ +#define UIC_EIR2 0x00000040 /* External interrupt 2 */ +#define UIC_EIR3 0x00000020 /* External interrupt 3 */ +#define UIC_EIR4 0x00000010 /* External interrupt 4 */ +#define UIC_EIR5 0x00000008 /* External interrupt 5 */ +#define UIC_EIR6 0x00000004 /* External interrupt 6 */ +#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ +#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ +#endif /* CONFIG_440GX */ /* For compatibility with 405 code */ #define UIC_MAL_TXEOB UIC_MTE @@ -797,7 +1498,40 @@ #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ #define UIC_ETH1 0x00000002 /* Reserved */ #define UIC_XOR 0x00000001 /* XOR */ -#else /* CONFIG_440SP */ +#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) +#define UIC_MS 0x80000000 /* MAL SERR */ +#define UIC_MTDE 0x40000000 /* MAL TXDE */ +#define UIC_MRDE 0x20000000 /* MAL RXDE */ +#define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/ +#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ +#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ +#define UIC_EBMI 0x02000000 /* EBMI interrupt status */ +#define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */ +#define UIC_MSI3 0x00800000 /* PCI MSI level 3 */ +#define UIC_MSI4 0x00400000 /* PCI MSI level 4 */ +#define UIC_MSI5 0x00200000 /* PCI MSI level 5 */ +#define UIC_MSI6 0x00100000 /* PCI MSI level 6 */ +#define UIC_MSI7 0x00080000 /* PCI MSI level 7 */ +#define UIC_MSI8 0x00040000 /* PCI MSI level 8 */ +#define UIC_MSI9 0x00020000 /* PCI MSI level 9 */ +#define UIC_MSI10 0x00010000 /* PCI MSI level 10 */ +#define UIC_MSI11 0x00008000 /* PCI MSI level 11 */ +#define UIC_PPMI 0x00004000 /* PPM interrupt status */ +#define UIC_EIR7 0x00002000 /* External interrupt 7 */ +#define UIC_EIR8 0x00001000 /* External interrupt 8 */ +#define UIC_EIR9 0x00000800 /* External interrupt 9 */ +#define UIC_EIR10 0x00000400 /* External interrupt 10 */ +#define UIC_EIR11 0x00000200 /* External interrupt 11 */ +#define UIC_EIR12 0x00000100 /* External interrupt 12 */ +#define UIC_SRE 0x00000080 /* Serial ROM error */ +#define UIC_RSVD2 0x00000040 /* Reserved */ +#define UIC_RSVD3 0x00000020 /* Reserved */ +#define UIC_PAE 0x00000010 /* PCI asynchronous error */ +#define UIC_ETH0 0x00000008 /* Ethernet 0 */ +#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ +#define UIC_ETH1 0x00000002 /* Ethernet 1 */ +#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ +#elif !defined(CONFIG_440SPE) #define UIC_MS 0x80000000 /* MAL SERR */ #define UIC_MTDE 0x40000000 /* MAL TXDE */ #define UIC_MRDE 0x20000000 /* MAL RXDE */ @@ -890,6 +1624,117 @@ #define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \ UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI) #endif /* CONFIG_440GX */ +/*---------------------------------------------------------------------------+ +| Universal interrupt controller interrupts ++---------------------------------------------------------------------------*/ +#if defined(CONFIG_440SPE) +/*#define UICB0_UIC0CI 0x80000000*/ /* UIC0 Critical Interrupt */ +/*#define UICB0_UIC0NCI 0x40000000*/ /* UIC0 Noncritical Interrupt */ +#define UICB0_UIC1CI 0x00000002 /* UIC1 Critical Interrupt */ +#define UICB0_UIC1NCI 0x00000001 /* UIC1 Noncritical Interrupt */ +#define UICB0_UIC2CI 0x00200000 /* UIC2 Critical Interrupt */ +#define UICB0_UIC2NCI 0x00100000 /* UIC2 Noncritical Interrupt */ +#define UICB0_UIC3CI 0x00008000 /* UIC3 Critical Interrupt */ +#define UICB0_UIC3NCI 0x00004000 /* UIC3 Noncritical Interrupt */ + +#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \ + UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI) +/*---------------------------------------------------------------------------+ +| Universal interrupt controller 0 interrupts (UIC0) ++---------------------------------------------------------------------------*/ +#define UIC_U0 0x80000000 /* UART 0 */ +#define UIC_U1 0x40000000 /* UART 1 */ +#define UIC_IIC0 0x20000000 /* IIC */ +#define UIC_IIC1 0x10000000 /* IIC */ +#define UIC_PIM 0x08000000 /* PCI inbound message */ +#define UIC_PCRW 0x04000000 /* PCI command register write */ +#define UIC_PPM 0x02000000 /* PCI power management */ +#define UIC_PVPDA 0x01000000 /* PCIx 0 vpd access */ +#define UIC_MSI0 0x00800000 /* PCIx MSI level 0 */ +#define UIC_EIR15 0x00400000 /* External intp 15 */ +#define UIC_PEMSI0 0x00080000 /* PCIe MSI level 0 */ +#define UIC_PEMSI1 0x00040000 /* PCIe MSI level 1 */ +#define UIC_PEMSI2 0x00020000 /* PCIe MSI level 2 */ +#define UIC_PEMSI3 0x00010000 /* PCIe MSI level 3 */ +#define UIC_EIR14 0x00002000 /* External interrupt 14 */ +#define UIC_D0CPFF 0x00001000 /* DMA0 cp fifo full */ +#define UIC_D0CSNS 0x00000800 /* DMA0 cs fifo needs service */ +#define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */ +#define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */ +#define UIC_I2OID 0x00000100 /* I2O inbound door bell */ +#define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */ +#define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */ +#define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */ +#define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */ +#define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */ +#define UIC_CPTCNT 0x00000004 /* GPT Count Timer */ +/*---------------------------------------------------------------------------+ +| Universal interrupt controller 1 interrupts (UIC1) ++---------------------------------------------------------------------------*/ +#define UIC_EIR13 0x80000000 /* externei intp 13 */ +#define UIC_MS 0x40000000 /* MAL SERR */ +#define UIC_MTDE 0x20000000 /* MAL TXDE */ +#define UIC_MRDE 0x10000000 /* MAL RXDE */ +#define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */ +#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ +#define UIC_MTE 0x02000000 /* MAL TXEOB */ +#define UIC_MRE 0x01000000 /* MAL RXEOB */ +#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ +#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ +#define UIC_MSI3 0x00200000 /* PCI MSI level 3 */ +#define UIC_L2C 0x00100000 /* L2 cache */ +#define UIC_CT0 0x00080000 /* GPT compare timer 0 */ +#define UIC_CT1 0x00040000 /* GPT compare timer 1 */ +#define UIC_CT2 0x00020000 /* GPT compare timer 2 */ +#define UIC_CT3 0x00010000 /* GPT compare timer 3 */ +#define UIC_CT4 0x00008000 /* GPT compare timer 4 */ +#define UIC_EIR12 0x00004000 /* External interrupt 12 */ +#define UIC_EIR11 0x00002000 /* External interrupt 11 */ +#define UIC_EIR10 0x00001000 /* External interrupt 10 */ +#define UIC_EIR9 0x00000800 /* External interrupt 9 */ +#define UIC_EIR8 0x00000400 /* External interrupt 8 */ +#define UIC_DMAE 0x00000200 /* dma error */ +#define UIC_I2OE 0x00000100 /* i2o error */ +#define UIC_SRE 0x00000080 /* Serial ROM error */ +#define UIC_PCIXAE 0x00000040 /* Pcix0 async error */ +#define UIC_EIR7 0x00000020 /* External interrupt 7 */ +#define UIC_EIR6 0x00000010 /* External interrupt 6 */ +#define UIC_ETH0 0x00000008 /* Ethernet 0 */ +#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ +#define UIC_ETH1 0x00000002 /* reserved */ +#define UIC_XOR 0x00000001 /* xor */ + +/*---------------------------------------------------------------------------+ +| Universal interrupt controller 2 interrupts (UIC2) ++---------------------------------------------------------------------------*/ +#define UIC_PEOAL 0x80000000 /* PE0 AL */ +#define UIC_PEOVA 0x40000000 /* PE0 VPD access */ +#define UIC_PEOHRR 0x20000000 /* PE0 Host reset request rising */ +#define UIC_PE0HRF 0x10000000 /* PE0 Host reset request falling */ +#define UIC_PE0TCR 0x08000000 /* PE0 TCR */ +#define UIC_PE0BVCO 0x04000000 /* PE0 Busmaster VCO */ +#define UIC_PE0DCRE 0x02000000 /* PE0 DCR error */ +#define UIC_PE1AL 0x00800000 /* PE1 AL */ +#define UIC_PE1VA 0x00400000 /* PE1 VPD access */ +#define UIC_PE1HRR 0x00200000 /* PE1 Host reset request rising */ +#define UIC_PE1HRF 0x00100000 /* PE1 Host reset request falling */ +#define UIC_PE1TCR 0x00080000 /* PE1 TCR */ +#define UIC_PE1BVCO 0x00040000 /* PE1 Busmaster VCO */ +#define UIC_PE1DCRE 0x00020000 /* PE1 DCR error */ +#define UIC_PE2AL 0x00008000 /* PE2 AL */ +#define UIC_PE2VA 0x00004000 /* PE2 VPD access */ +#define UIC_PE2HRR 0x00002000 /* PE2 Host reset request rising */ +#define UIC_PE2HRF 0x00001000 /* PE2 Host reset request falling */ +#define UIC_PE2TCR 0x00000800 /* PE2 TCR */ +#define UIC_PE2BVCO 0x00000400 /* PE2 Busmaster VCO */ +#define UIC_PE2DCRE 0x00000200 /* PE2 DCR error */ +#define UIC_EIR5 0x00000080 /* External interrupt 5 */ +#define UIC_EIR4 0x00000040 /* External interrupt 4 */ +#define UIC_EIR3 0x00000020 /* External interrupt 3 */ +#define UIC_EIR2 0x00000010 /* External interrupt 2 */ +#define UIC_EIR1 0x00000008 /* External interrupt 1 */ +#define UIC_EIR0 0x00000004 /* External interrupt 0 */ +#endif /* CONFIG_440SPE */ /*-----------------------------------------------------------------------------+ | External Bus Controller Bit Settings @@ -981,6 +1826,432 @@ /*-----------------------------------------------------------------------------+ | SDR0 Bit Settings +-----------------------------------------------------------------------------*/ +#if defined(CONFIG_440SPE) +#define SDR0_CP440 0x0180 +#define SDR0_CP440_ERPN_MASK 0x30000000 +#define SDR0_CP440_ERPN_MASK_HI 0x3000 +#define SDR0_CP440_ERPN_MASK_LO 0x0000 +#define SDR0_CP440_ERPN_EBC 0x10000000 +#define SDR0_CP440_ERPN_EBC_HI 0x1000 +#define SDR0_CP440_ERPN_EBC_LO 0x0000 +#define SDR0_CP440_ERPN_PCI 0x20000000 +#define SDR0_CP440_ERPN_PCI_HI 0x2000 +#define SDR0_CP440_ERPN_PCI_LO 0x0000 +#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) +#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03) +#define SDR0_CP440_NTO1_MASK 0x00000002 +#define SDR0_CP440_NTO1_NTOP 0x00000000 +#define SDR0_CP440_NTO1_NTO1 0x00000002 +#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) +#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) +#define SDR0_CFGADDR 0x00E /*already defined line 277 */ +#define SDR0_CFGDATA 0x00F + + +#define SDR0_SDSTP0 0x0020 +#define SDR0_SDSTP0_ENG_MASK 0x80000000 +#define SDR0_SDSTP0_ENG_PLLDIS 0x00000000 +#define SDR0_SDSTP0_ENG_PLLENAB 0x80000000 +#define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) +#define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01) +#define SDR0_SDSTP0_SRC_MASK 0x40000000 +#define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000 +#define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000 +#define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) +#define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01) +#define SDR0_SDSTP0_SEL_MASK 0x38000000 +#define SDR0_SDSTP0_SEL_PLLOUT 0x00000000 +#define SDR0_SDSTP0_SEL_CPU 0x08000000 +#define SDR0_SDSTP0_SEL_EBC 0x28000000 +#define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27) +#define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07) +#define SDR0_SDSTP0_TUNE_MASK 0x07FE0000 +#define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17) +#define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF) +#define SDR0_SDSTP0_FBDV_MASK 0x0001F000 +#define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) +#define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1) +#define SDR0_SDSTP0_FWDVA_MASK 0x00000F00 +#define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8) +#define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1) +#define SDR0_SDSTP0_FWDVB_MASK 0x000000E0 +#define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5) +#define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1) +#define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C +#define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2) +#define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1) +#define SDR0_SDSTP0_OPBDV0_MASK 0x00000003 +#define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0) +#define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1) + + +#define SDR0_SDSTP1 0x0021 +#define SDR0_SDSTP1_LFBDV_MASK 0xFC000000 +#define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26) +#define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F) +#define SDR0_SDSTP1_PERDV0_MASK 0x03000000 +#define SDR0_SDSTP1_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) +#define SDR0_SDSTP1_PERDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03) +#define SDR0_SDSTP1_MALDV0_MASK 0x00C00000 +#define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22) +#define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03) +#define SDR0_SDSTP1_DDR_MODE_MASK 0x00300000 +#define SDR0_SDSTP1_DDR1_MODE 0x00100000 +#define SDR0_SDSTP1_DDR2_MODE 0x00200000 +#define SDR0_SDSTP1_DDR_ENCODE(n) ((((unsigned long)(n))&0x03)<<20) +#define SDR0_SDSTP1_DDR_DECODE(n) ((((unsigned long)(n))>>20)&0x03) +#define SDR0_SDSTP1_ERPN_MASK 0x00080000 +#define SDR0_SDSTP1_ERPN_EBC 0x00000000 +#define SDR0_SDSTP1_ERPN_PCI 0x00080000 +#define SDR0_SDSTP1_PAE_MASK 0x00040000 +#define SDR0_SDSTP1_PAE_DISABLE 0x00000000 +#define SDR0_SDSTP1_PAE_ENABLE 0x00040000 +#define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18) +#define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01) +#define SDR0_SDSTP1_PHCE_MASK 0x00020000 +#define SDR0_SDSTP1_PHCE_DISABLE 0x00000000 +#define SDR0_SDSTP1_PHCE_ENABLE 0x00020000 +#define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17) +#define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01) +#define SDR0_SDSTP1_PISE_MASK 0x00010000 +#define SDR0_SDSTP1_PISE_DISABLE 0x00000000 +#define SDR0_SDSTP1_PISE_ENABLE 0x00001000 +#define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16) +#define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01) +#define SDR0_SDSTP1_PCWE_MASK 0x00008000 +#define SDR0_SDSTP1_PCWE_DISABLE 0x00000000 +#define SDR0_SDSTP1_PCWE_ENABLE 0x00008000 +#define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15) +#define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01) +#define SDR0_SDSTP1_PPIM_MASK 0x00007800 +#define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11) +#define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F) +#define SDR0_SDSTP1_PR64E_MASK 0x00000400 +#define SDR0_SDSTP1_PR64E_DISABLE 0x00000000 +#define SDR0_SDSTP1_PR64E_ENABLE 0x00000400 +#define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10) +#define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01) +#define SDR0_SDSTP1_PXFS_MASK 0x00000300 +#define SDR0_SDSTP1_PXFS_100_133 0x00000000 +#define SDR0_SDSTP1_PXFS_66_100 0x00000100 +#define SDR0_SDSTP1_PXFS_50_66 0x00000200 +#define SDR0_SDSTP1_PXFS_0_50 0x00000300 +#define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) +#define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03) +#define SDR0_SDSTP1_EBCW_MASK 0x00000080 /* SOP */ +#define SDR0_SDSTP1_EBCW_8_BITS 0x00000000 /* SOP */ +#define SDR0_SDSTP1_EBCW_16_BITS 0x00000080 /* SOP */ +#define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */ +#define SDR0_SDSTP1_DBGEN_FUNC 0x00000000 +#define SDR0_SDSTP1_DBGEN_TRACE 0x00000010 +#define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */ +#define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */ +#define SDR0_SDSTP1_ETH_MASK 0x00000004 +#define SDR0_SDSTP1_ETH_10_100 0x00000000 +#define SDR0_SDSTP1_ETH_GIGA 0x00000004 +#define SDR0_SDSTP1_ETH_ENCODE(n) ((((unsigned long)(n))&0x01)<<2) +#define SDR0_SDSTP1_ETH_DECODE(n) ((((unsigned long)(n))>>2)&0x01) +#define SDR0_SDSTP1_NTO1_MASK 0x00000001 +#define SDR0_SDSTP1_NTO1_DISABLE 0x00000000 +#define SDR0_SDSTP1_NTO1_ENABLE 0x00000001 +#define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0) +#define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01) + +#define SDR0_SDSTP2 0x0022 +#define SDR0_SDSTP2_P1AE_MASK 0x80000000 +#define SDR0_SDSTP2_P1AE_DISABLE 0x00000000 +#define SDR0_SDSTP2_P1AE_ENABLE 0x80000000 +#define SDR0_SDSTP2_P1AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) +#define SDR0_SDSTP2_P1AE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) +#define SDR0_SDSTP2_P1HCE_MASK 0x40000000 +#define SDR0_SDSTP2_P1HCE_DISABLE 0x00000000 +#define SDR0_SDSTP2_P1HCE_ENABLE 0x40000000 +#define SDR0_SDSTP2_P1HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) +#define SDR0_SDSTP2_P1HCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) +#define SDR0_SDSTP2_P1ISE_MASK 0x20000000 +#define SDR0_SDSTP2_P1ISE_DISABLE 0x00000000 +#define SDR0_SDSTP2_P1ISE_ENABLE 0x20000000 +#define SDR0_SDSTP2_P1ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) +#define SDR0_SDSTP2_P1ISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) +#define SDR0_SDSTP2_P1CWE_MASK 0x10000000 +#define SDR0_SDSTP2_P1CWE_DISABLE 0x00000000 +#define SDR0_SDSTP2_P1CWE_ENABLE 0x10000000 +#define SDR0_SDSTP2_P1CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) +#define SDR0_SDSTP2_P1CWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) +#define SDR0_SDSTP2_P1PIM_MASK 0x0F000000 +#define SDR0_SDSTP2_P1PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) +#define SDR0_SDSTP2_P1PIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) +#define SDR0_SDSTP2_P1R64E_MASK 0x00800000 +#define SDR0_SDSTP2_P1R64E_DISABLE 0x00000000 +#define SDR0_SDSTP2_P1R64E_ENABLE 0x00800000 +#define SDR0_SDSTP2_P1R64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) +#define SDR0_SDSTP2_P1R64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) +#define SDR0_SDSTP2_P1XFS_MASK 0x00600000 +#define SDR0_SDSTP2_P1XFS_100_133 0x00000000 +#define SDR0_SDSTP2_P1XFS_66_100 0x00200000 +#define SDR0_SDSTP2_P1XFS_50_66 0x00400000 +#define SDR0_SDSTP2_P1XFS_0_50 0x00600000 +#define SDR0_SDSTP2_P1XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) +#define SDR0_SDSTP2_P1XFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) +#define SDR0_SDSTP2_P2AE_MASK 0x00040000 +#define SDR0_SDSTP2_P2AE_DISABLE 0x00000000 +#define SDR0_SDSTP2_P2AE_ENABLE 0x00040000 +#define SDR0_SDSTP2_P2AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18) +#define SDR0_SDSTP2_P2AE_DECODE(n) ((((unsigned long)(n))>>18)&0x01) +#define SDR0_SDSTP2_P2HCE_MASK 0x00020000 +#define SDR0_SDSTP2_P2HCE_DISABLE 0x00000000 +#define SDR0_SDSTP2_P2HCE_ENABLE 0x00020000 +#define SDR0_SDSTP2_P2HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17) +#define SDR0_SDSTP2_P2HCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01) +#define SDR0_SDSTP2_P2ISE_MASK 0x00010000 +#define SDR0_SDSTP2_P2ISE_DISABLE 0x00000000 +#define SDR0_SDSTP2_P2ISE_ENABLE 0x00010000 +#define SDR0_SDSTP2_P2ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16) +#define SDR0_SDSTP2_P2ISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01) +#define SDR0_SDSTP2_P2CWE_MASK 0x00008000 +#define SDR0_SDSTP2_P2CWE_DISABLE 0x00000000 +#define SDR0_SDSTP2_P2CWE_ENABLE 0x00008000 +#define SDR0_SDSTP2_P2CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15) +#define SDR0_SDSTP2_P2CWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01) +#define SDR0_SDSTP2_P2PIM_MASK 0x00007800 +#define SDR0_SDSTP2_P2PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11) +#define SDR0_SDSTP2_P2PIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F) +#define SDR0_SDSTP2_P2XFS_MASK 0x00000300 +#define SDR0_SDSTP2_P2XFS_100_133 0x00000000 +#define SDR0_SDSTP2_P2XFS_66_100 0x00000100 +#define SDR0_SDSTP2_P2XFS_50_66 0x00000200 +#define SDR0_SDSTP2_P2XFS_0_50 0x00000100 +#define SDR0_SDSTP2_P2XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) +#define SDR0_SDSTP2_P2XFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03) + +#define SDR0_SDSTP3 0x0023 + +#define SDR0_PINSTP 0x0040 +#define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */ +#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */ +#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */ +#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */ +#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */ +#define SDR0_SDCS 0x0060 +#define SDR0_ECID0 0x0080 +#define SDR0_ECID1 0x0081 +#define SDR0_ECID2 0x0082 +#define SDR0_JTAG 0x00C0 + +#define SDR0_DDR0 0x00E1 +#define SDR0_DDR0_DPLLRST 0x80000000 +#define SDR0_DDR0_DDRM_MASK 0x60000000 +#define SDR0_DDR0_DDRM_DDR1 0x20000000 +#define SDR0_DDR0_DDRM_DDR2 0x40000000 +#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29) +#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03) +#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0) +#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF) + +#define SDR0_UART0 0x0120 +#define SDR0_UART1 0x0121 +#define SDR0_UART2 0x0122 +#define SDR0_UARTX_UXICS_MASK 0xF0000000 +#define SDR0_UARTX_UXICS_PLB 0x20000000 +#define SDR0_UARTX_UXEC_MASK 0x00800000 +#define SDR0_UARTX_UXEC_INT 0x00000000 +#define SDR0_UARTX_UXEC_EXT 0x00800000 +#define SDR0_UARTX_UXDIV_MASK 0x000000FF +#define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1) + +#define SDR0_CP440 0x0180 +#define SDR0_CP440_ERPN_MASK 0x30000000 +#define SDR0_CP440_ERPN_MASK_HI 0x3000 +#define SDR0_CP440_ERPN_MASK_LO 0x0000 +#define SDR0_CP440_ERPN_EBC 0x10000000 +#define SDR0_CP440_ERPN_EBC_HI 0x1000 +#define SDR0_CP440_ERPN_EBC_LO 0x0000 +#define SDR0_CP440_ERPN_PCI 0x20000000 +#define SDR0_CP440_ERPN_PCI_HI 0x2000 +#define SDR0_CP440_ERPN_PCI_LO 0x0000 +#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) +#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03) +#define SDR0_CP440_NTO1_MASK 0x00000002 +#define SDR0_CP440_NTO1_NTOP 0x00000000 +#define SDR0_CP440_NTO1_NTO1 0x00000002 +#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) +#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) + +#define SDR0_XCR0 0x01C0 +#define SDR0_XCR1 0x01C3 +#define SDR0_XCR2 0x01C6 +#define SDR0_XCRn_PAE_MASK 0x80000000 +#define SDR0_XCRn_PAE_DISABLE 0x00000000 +#define SDR0_XCRn_PAE_ENABLE 0x80000000 +#define SDR0_XCRn_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) +#define SDR0_XCRn_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) +#define SDR0_XCRn_PHCE_MASK 0x40000000 +#define SDR0_XCRn_PHCE_DISABLE 0x00000000 +#define SDR0_XCRn_PHCE_ENABLE 0x40000000 +#define SDR0_XCRn_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) +#define SDR0_XCRn_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) +#define SDR0_XCRn_PISE_MASK 0x20000000 +#define SDR0_XCRn_PISE_DISABLE 0x00000000 +#define SDR0_XCRn_PISE_ENABLE 0x20000000 +#define SDR0_XCRn_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) +#define SDR0_XCRn_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) +#define SDR0_XCRn_PCWE_MASK 0x10000000 +#define SDR0_XCRn_PCWE_DISABLE 0x00000000 +#define SDR0_XCRn_PCWE_ENABLE 0x10000000 +#define SDR0_XCRn_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) +#define SDR0_XCRn_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) +#define SDR0_XCRn_PPIM_MASK 0x0F000000 +#define SDR0_XCRn_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) +#define SDR0_XCRn_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) +#define SDR0_XCRn_PR64E_MASK 0x00800000 +#define SDR0_XCRn_PR64E_DISABLE 0x00000000 +#define SDR0_XCRn_PR64E_ENABLE 0x00800000 +#define SDR0_XCRn_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) +#define SDR0_XCRn_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) +#define SDR0_XCRn_PXFS_MASK 0x00600000 +#define SDR0_XCRn_PXFS_100_133 0x00000000 +#define SDR0_XCRn_PXFS_66_100 0x00200000 +#define SDR0_XCRn_PXFS_50_66 0x00400000 +#define SDR0_XCRn_PXFS_0_33 0x00600000 +#define SDR0_XCRn_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) +#define SDR0_XCRn_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) + +#define SDR0_XPLLC0 0x01C1 +#define SDR0_XPLLD0 0x01C2 +#define SDR0_XPLLC1 0x01C4 +#define SDR0_XPLLD1 0x01C5 +#define SDR0_XPLLC2 0x01C7 +#define SDR0_XPLLD2 0x01C8 +#define SDR0_SRST 0x0200 +#define SDR0_SLPIPE 0x0220 + +#define SDR0_AMP0 0x0240 +#define SDR0_AMP0_PRIORITY 0xFFFF0000 +#define SDR0_AMP0_ALTERNATE_PRIORITY 0x0000FF00 +#define SDR0_AMP0_RESERVED_BITS_MASK 0x000000FF + +#define SDR0_AMP1 0x0241 +#define SDR0_AMP1_PRIORITY 0xFC000000 +#define SDR0_AMP1_ALTERNATE_PRIORITY 0x0000E000 +#define SDR0_AMP1_RESERVED_BITS_MASK 0x03FF1FFF + +#define SDR0_MIRQ0 0x0260 +#define SDR0_MIRQ1 0x0261 +#define SDR0_MALTBL 0x0280 +#define SDR0_MALRBL 0x02A0 +#define SDR0_MALTBS 0x02C0 +#define SDR0_MALRBS 0x02E0 + +/* Reserved for Customer Use */ +#define SDR0_CUST0 0x4000 +#define SDR0_CUST0_AUTONEG_MASK 0x8000000 +#define SDR0_CUST0_NO_AUTONEG 0x0000000 +#define SDR0_CUST0_AUTONEG 0x8000000 +#define SDR0_CUST0_ETH_FORCE_MASK 0x6000000 +#define SDR0_CUST0_ETH_FORCE_10MHZ 0x0000000 +#define SDR0_CUST0_ETH_FORCE_100MHZ 0x2000000 +#define SDR0_CUST0_ETH_FORCE_1000MHZ 0x4000000 +#define SDR0_CUST0_ETH_DUPLEX_MASK 0x1000000 +#define SDR0_CUST0_ETH_HALF_DUPLEX 0x0000000 +#define SDR0_CUST0_ETH_FULL_DUPLEX 0x1000000 + +#define SDR0_SDSTP4 0x4001 +#define SDR0_CUST1 0x4002 +#define SDR0_SDSTP5 0x4003 +#define SDR0_CUST2 0x4004 +#define SDR0_SDSTP6 0x4005 +#define SDR0_CUST3 0x4006 +#define SDR0_SDSTP7 0x4007 + +#define SDR0_PFC0 0x4100 +#define SDR0_PFC0_GPIO_0 0x80000000 +#define SDR0_PFC0_PCIX0REQ2_N 0x00000000 +#define SDR0_PFC0_GPIO_1 0x40000000 +#define SDR0_PFC0_PCIX0REQ3_N 0x00000000 +#define SDR0_PFC0_GPIO_2 0x20000000 +#define SDR0_PFC0_PCIX0GNT2_N 0x00000000 +#define SDR0_PFC0_GPIO_3 0x10000000 +#define SDR0_PFC0_PCIX0GNT3_N 0x00000000 +#define SDR0_PFC0_GPIO_4 0x08000000 +#define SDR0_PFC0_PCIX1REQ2_N 0x00000000 +#define SDR0_PFC0_GPIO_5 0x04000000 +#define SDR0_PFC0_PCIX1REQ3_N 0x00000000 +#define SDR0_PFC0_GPIO_6 0x02000000 +#define SDR0_PFC0_PCIX1GNT2_N 0x00000000 +#define SDR0_PFC0_GPIO_7 0x01000000 +#define SDR0_PFC0_PCIX1GNT3_N 0x00000000 +#define SDR0_PFC0_GPIO_8 0x00800000 +#define SDR0_PFC0_PERREADY 0x00000000 +#define SDR0_PFC0_GPIO_9 0x00400000 +#define SDR0_PFC0_PERCS1_N 0x00000000 +#define SDR0_PFC0_GPIO_10 0x00200000 +#define SDR0_PFC0_PERCS2_N 0x00000000 +#define SDR0_PFC0_GPIO_11 0x00100000 +#define SDR0_PFC0_IRQ0 0x00000000 +#define SDR0_PFC0_GPIO_12 0x00080000 +#define SDR0_PFC0_IRQ1 0x00000000 +#define SDR0_PFC0_GPIO_13 0x00040000 +#define SDR0_PFC0_IRQ2 0x00000000 +#define SDR0_PFC0_GPIO_14 0x00020000 +#define SDR0_PFC0_IRQ3 0x00000000 +#define SDR0_PFC0_GPIO_15 0x00010000 +#define SDR0_PFC0_IRQ4 0x00000000 +#define SDR0_PFC0_GPIO_16 0x00008000 +#define SDR0_PFC0_IRQ5 0x00000000 +#define SDR0_PFC0_GPIO_17 0x00004000 +#define SDR0_PFC0_PERBE0_N 0x00000000 +#define SDR0_PFC0_GPIO_18 0x00002000 +#define SDR0_PFC0_PCI0GNT0_N 0x00000000 +#define SDR0_PFC0_GPIO_19 0x00001000 +#define SDR0_PFC0_PCI0GNT1_N 0x00000000 +#define SDR0_PFC0_GPIO_20 0x00000800 +#define SDR0_PFC0_PCI0REQ0_N 0x00000000 +#define SDR0_PFC0_GPIO_21 0x00000400 +#define SDR0_PFC0_PCI0REQ1_N 0x00000000 +#define SDR0_PFC0_GPIO_22 0x00000200 +#define SDR0_PFC0_PCI1GNT0_N 0x00000000 +#define SDR0_PFC0_GPIO_23 0x00000100 +#define SDR0_PFC0_PCI1GNT1_N 0x00000000 +#define SDR0_PFC0_GPIO_24 0x00000080 +#define SDR0_PFC0_PCI1REQ0_N 0x00000000 +#define SDR0_PFC0_GPIO_25 0x00000040 +#define SDR0_PFC0_PCI1REQ1_N 0x00000000 +#define SDR0_PFC0_GPIO_26 0x00000020 +#define SDR0_PFC0_PCI2GNT0_N 0x00000000 +#define SDR0_PFC0_GPIO_27 0x00000010 +#define SDR0_PFC0_PCI2GNT1_N 0x00000000 +#define SDR0_PFC0_GPIO_28 0x00000008 +#define SDR0_PFC0_PCI2REQ0_N 0x00000000 +#define SDR0_PFC0_GPIO_29 0x00000004 +#define SDR0_PFC0_PCI2REQ1_N 0x00000000 +#define SDR0_PFC0_GPIO_30 0x00000002 +#define SDR0_PFC0_UART1RX 0x00000000 +#define SDR0_PFC0_GPIO_31 0x00000001 +#define SDR0_PFC0_UART1TX 0x00000000 + +#define SDR0_PFC1 0x4101 +#define SDR0_PFC1_UART1_CTS_RTS_MASK 0x02000000 +#define SDR0_PFC1_UART1_DSR_DTR 0x00000000 +#define SDR0_PFC1_UART1_CTS_RTS 0x02000000 +#define SDR0_PFC1_UART2_IN_SERVICE_MASK 0x01000000 +#define SDR0_PFC1_UART2_NOT_IN_SERVICE 0x00000000 +#define SDR0_PFC1_UART2_IN_SERVICE 0x01000000 +#define SDR0_PFC1_ETH_GIGA_MASK 0x00200000 +#define SDR0_PFC1_ETH_10_100 0x00000000 +#define SDR0_PFC1_ETH_GIGA 0x00200000 +#define SDR0_PFC1_ETH_GIGA_ENCODE(n) ((((unsigned long)(n))&0x1)<<21) +#define SDR0_PFC1_ETH_GIGA_DECODE(n) ((((unsigned long)(n))>>21)&0x01) +#define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */ +#define SDR0_PFC1_CPU_NO_TRACE 0x00000000 +#define SDR0_PFC1_CPU_TRACE 0x00080000 +#define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) /* $218C */ +#define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) /* $218C */ + +#define SDR0_MFR 0x4300 +#endif /* CONFIG_440SPE */ + + #define SDR0_SDCS_SDD (0x80000000 >> 31) #if defined(CONFIG_440GP) @@ -1159,7 +2430,7 @@ /*-----------------------------------------------------------------------------+ | Clocking +-----------------------------------------------------------------------------*/ -#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP) +#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) #define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */ #define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */ #define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */ @@ -1498,6 +2769,9 @@ typedef struct { unsigned long freqOPB; unsigned long freqEPB; unsigned long freqPCI; +#ifdef CONFIG_440SPE + unsigned long freqDDR; +#endif unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ unsigned long pciClkSync; /* PCI clock is synchronous */ } PPC440_SYS_INFO; diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index d6d33b6..ec2e362 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -133,12 +133,21 @@ typedef struct emac_4xx_hw_st { #define EMAC_NUM_DEV 4 #elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \ defined(CONFIG_NET_MULTI) && \ - !defined(CONFIG_440SP) + !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) #define EMAC_NUM_DEV 2 #else #define EMAC_NUM_DEV 1 #endif +#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */ +#define EMAC_STACR_OC_MASK (0x00008000) +#else +#define EMAC_STACR_OC_MASK (0x00000000) +#endif + +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#define SDR0_PFC1_EM_1000 (0x00200000) +#endif /*ZMII Bridge Register addresses */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) @@ -323,7 +332,7 @@ typedef struct emac_4xx_hw_st { #define EMAC_M0_WKE (0x04000000) /* on 440GX EMAC_MR1 has a different layout! */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* MODE Reg 1 */ #define EMAC_M1_FDE (0x80000000) #define EMAC_M1_ILE (0x40000000) @@ -424,8 +433,21 @@ typedef struct emac_4xx_hw_st { /* STA CONTROL REG */ #define EMAC_STACR_OC (0x00008000) #define EMAC_STACR_PHYE (0x00004000) + +#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */ +#define EMAC_STACR_INDIRECT_MODE (0x00002000) +#define EMAC_STACR_WRITE (0x00000800) /* $BUC */ +#define EMAC_STACR_READ (0x00001000) /* $BUC */ +#define EMAC_STACR_OP_MASK (0x00001800) +#define EMAC_STACR_MDIO_ADDR (0x00000000) +#define EMAC_STACR_MDIO_WRITE (0x00000800) +#define EMAC_STACR_MDIO_READ (0x00001800) +#define EMAC_STACR_MDIO_READ_INC (0x00001000) +#else #define EMAC_STACR_WRITE (0x00002000) #define EMAC_STACR_READ (0x00001000) +#endif + #define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */ #define EMAC_STACR_CLK_66MHZ (0x00000400) #define EMAC_STACR_CLK_100MHZ (0x00000C00) diff --git a/include/s3c2400.h b/include/s3c2400.h index bc1f1e9..4fdc62e 100644 --- a/include/s3c2400.h +++ b/include/s3c2400.h @@ -63,71 +63,71 @@ typedef enum { #include <s3c24x0.h> -static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void) +static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void) { return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE; } -static inline S3C24X0_USB_HOST * const S3C24X0_GetBase_USB_HOST(void) +static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void) { return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE; } -static inline S3C24X0_INTERRUPT * const S3C24X0_GetBase_INTERRUPT(void) +static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void) { return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE; } -static inline S3C24X0_DMAS * const S3C24X0_GetBase_DMAS(void) +static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void) { return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE; } -static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void) +static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void) { return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE; } -static inline S3C24X0_LCD * const S3C24X0_GetBase_LCD(void) +static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void) { return (S3C24X0_LCD * const)S3C24X0_LCD_BASE; } -static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr) +static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr) { return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000)); } -static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void) +static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void) { return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE; } -static inline S3C24X0_USB_DEVICE * const S3C24X0_GetBase_USB_DEVICE(void) +static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void) { return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE; } -static inline S3C24X0_WATCHDOG * const S3C24X0_GetBase_WATCHDOG(void) +static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void) { return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE; } -static inline S3C24X0_I2C * const S3C24X0_GetBase_I2C(void) +static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void) { return (S3C24X0_I2C * const)S3C24X0_I2C_BASE; } -static inline S3C24X0_I2S * const S3C24X0_GetBase_I2S(void) +static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void) { return (S3C24X0_I2S * const)S3C24X0_I2S_BASE; } -static inline S3C24X0_GPIO * const S3C24X0_GetBase_GPIO(void) +static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void) { return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE; } -static inline S3C24X0_RTC * const S3C24X0_GetBase_RTC(void) +static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void) { return (S3C24X0_RTC * const)S3C24X0_RTC_BASE; } -static inline S3C2400_ADC * const S3C2400_GetBase_ADC(void) +static inline S3C2400_ADC * S3C2400_GetBase_ADC(void) { return (S3C2400_ADC * const)S3C24X0_ADC_BASE; } -static inline S3C24X0_SPI * const S3C24X0_GetBase_SPI(void) +static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void) { return (S3C24X0_SPI * const)S3C24X0_SPI_BASE; } -static inline S3C2400_MMC * const S3C2400_GetBase_MMC(void) +static inline S3C2400_MMC * S3C2400_GetBase_MMC(void) { return (S3C2400_MMC * const)S3C2400_MMC_BASE; } diff --git a/include/usb.h b/include/usb.h index 39d7f23..bf71554 100644 --- a/include/usb.h +++ b/include/usb.h @@ -108,6 +108,7 @@ struct usb_interface_descriptor { unsigned char iInterface; unsigned char no_of_ep; + unsigned char num_altsetting; unsigned char act_altsetting; struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS]; } __attribute__ ((packed)); diff --git a/include/xyzModem.h b/include/xyzModem.h index 4ec10b5..f437bbd 100644 --- a/include/xyzModem.h +++ b/include/xyzModem.h @@ -97,7 +97,10 @@ typedef struct { #endif } connection_info_t; +#ifndef BOOL_WAS_DEFINED +#define BOOL_WAS_DEFINED typedef unsigned int bool; +#endif #define false 0 #define true 1 diff --git a/lib_i386/i386_linux.c b/lib_i386/i386_linux.c index e5d8eea..b4a6f5a 100644 --- a/lib_i386/i386_linux.c +++ b/lib_i386/i386_linux.c @@ -151,6 +151,12 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], initrd_end = 0; } + /* if multi-part image, we need to advance base ptr */ + if ((hdr->ih_type==IH_TYPE_MULTI) && (len_ptr[1])) { + int i; + for (i=0, addr+=sizeof(int); len_ptr[i++]; addr+=sizeof(int)); + } + base_ptr = load_zimage((void*)addr + sizeof(image_header_t), ntohl(hdr->ih_size), initrd_start, initrd_end-initrd_start, 0); diff --git a/lib_ppc/board.c b/lib_ppc/board.c index e68cf1f..71dae07 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -270,7 +270,8 @@ init_fnc_t *init_sequence[] = { #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) get_clocks, /* get CPU and bus clocks (etc.) */ -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) +#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ + && !defined(CONFIG_TQM885D) adjust_sdram_tbs_8xx, #endif init_timebase, @@ -503,7 +504,7 @@ void board_init_f (ulong bootflag) #endif #if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \ - defined(CONFIG_E500) + defined(CONFIG_E500) || defined(CONFIG_MPC86xx) bd->bi_immr_base = CFG_IMMR; /* base of IMMR register */ #endif #if defined(CONFIG_MPC5xxx) @@ -610,6 +611,11 @@ void board_init_r (gd_t *id, ulong dest_addr) bd = gd->bd; gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ + gd->reloc_off = dest_addr - CFG_MONITOR_BASE; + +#ifdef CONFIG_SERIAL_MULTI + serial_initialize(); +#endif debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); @@ -619,14 +625,8 @@ void board_init_r (gd_t *id, ulong dest_addr) board_early_init_r (); #endif - gd->reloc_off = dest_addr - CFG_MONITOR_BASE; - monitor_flash_len = (ulong)&__init_end - dest_addr; -#ifdef CONFIG_SERIAL_MULTI - serial_initialize(); -#endif - /* * We have to relocate the command table manually */ @@ -862,6 +862,10 @@ void board_init_r (gd_t *id, ulong dest_addr) } #endif +#ifdef CFG_ID_EEPROM + mac_read_from_eeprom(); +#endif + #if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \ defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) load_sernum_ethaddr (); @@ -9,19 +9,23 @@ # APPEND=no # Default: Create new config file +BOARD_NAME="" # Name to print in make output while [ $# -gt 0 ] ; do case "$1" in --) shift ; break ;; -a) shift ; APPEND=yes ;; + -n) shift ; BOARD_NAME="${1%%_config}" ; shift ;; *) break ;; esac done +[ "${BOARD_NAME}" ] || BOARD_NAME="$1" + [ $# -lt 4 ] && exit 1 [ $# -gt 6 ] && exit 1 -echo "Configuring for $1 board..." +echo "Configuring for ${BOARD_NAME} board..." cd ./include @@ -196,6 +196,22 @@ int eth_initialize(bd_t *bis) tsec_initialize(bis, 3, CONFIG_MPC83XX_TSEC4_NAME); # endif #endif +#if defined(CONFIG_MPC86XX_TSEC1) + tsec_initialize(bis, 0, CONFIG_MPC86XX_TSEC1_NAME); +#endif + +#if defined(CONFIG_MPC86XX_TSEC2) + tsec_initialize(bis, 1, CONFIG_MPC86XX_TSEC2_NAME); +#endif + +#if defined(CONFIG_MPC86XX_TSEC3) + tsec_initialize(bis, 2, CONFIG_MPC86XX_TSEC3_NAME); +#endif + +#if defined(CONFIG_MPC86XX_TSEC4) + tsec_initialize(bis, 3, CONFIG_MPC86XX_TSEC4_NAME); +#endif + #if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC) fec_initialize(bis); #endif @@ -225,7 +225,7 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) if (TftpBlock == 0) { TftpBlockWrap++; TftpBlockWrapOffset += TFTP_BLOCK_SIZE * TFTP_SEQUENCE_SIZE; - printf ("\n\t %lu MB reveived\n\t ", TftpBlockWrapOffset>>20); + printf ("\n\t %lu MB received\n\t ", TftpBlockWrapOffset>>20); } else { if (((TftpBlock - 1) % 10) == 0) { putc ('#'); diff --git a/tools/mkimage.c b/tools/mkimage.c index fea3e5b..d6000e0 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -130,6 +130,7 @@ table_entry_t type_name[] = { { IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", }, { IH_TYPE_SCRIPT, "script", "Script", }, { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, + { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", }, { -1, "", "", }, }; |