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-rw-r--r--board/siemens/common/factoryset.c24
-rw-r--r--board/siemens/common/factoryset.h2
-rw-r--r--board/siemens/dxr2/board.c11
-rw-r--r--board/siemens/dxr2/board.h9
-rw-r--r--board/siemens/dxr2/mux.c158
-rw-r--r--board/siemens/pxm2/board.c3
-rw-r--r--board/siemens/rut/board.c51
-rw-r--r--include/configs/dxr2.h13
-rw-r--r--include/configs/pxm2.h7
-rw-r--r--include/configs/rut.h10
-rw-r--r--include/configs/siemens-am33x-common.h69
11 files changed, 305 insertions, 52 deletions
diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c
index fbe7997..266dbbb 100644
--- a/board/siemens/common/factoryset.c
+++ b/board/siemens/common/factoryset.c
@@ -15,7 +15,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/unaligned.h>
#include <net.h>
-#include <usbdescriptors.h>
+#include <errno.h>
+#include <g_dnl.h>
#include "factoryset.h"
#define EEPR_PG_SZ 0x80
@@ -224,8 +225,20 @@ int factoryset_read_eeprom(int i2c_addr)
MAX_STRING_LENGTH)) {
debug("display name: %s\n", factory_dat.disp_name);
}
-
#endif
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
+ (uchar *)"num", factory_dat.serial,
+ MAX_STRING_LENGTH)) {
+ debug("serial number: %s\n", factory_dat.serial);
+ }
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
+ (uchar *)"ver", buf,
+ MAX_STRING_LENGTH)) {
+ factory_dat.version = simple_strtoul((char *)buf,
+ NULL, 16);
+ debug("version number: %d\n", factory_dat.version);
+ }
+
return 0;
err:
@@ -279,6 +292,13 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
{
put_unaligned(factory_dat.usb_vendor_id, &dev->idVendor);
put_unaligned(factory_dat.usb_product_id, &dev->idProduct);
+ g_dnl_set_serialnumber((char *)factory_dat.serial);
+
return 0;
}
+
+int g_dnl_get_board_bcd_device_number(int gcnum)
+{
+ return factory_dat.version;
+}
#endif /* defined(CONFIG_SPL_BUILD) */
diff --git a/board/siemens/common/factoryset.h b/board/siemens/common/factoryset.h
index 445f384..4d6de10 100644
--- a/board/siemens/common/factoryset.h
+++ b/board/siemens/common/factoryset.h
@@ -18,6 +18,8 @@ struct factorysetcontainer {
#if defined(CONFIG_VIDEO)
unsigned char disp_name[MAX_STRING_LENGTH];
#endif
+ unsigned char serial[MAX_STRING_LENGTH];
+ int version;
};
int factoryset_read_eeprom(int i2c_addr);
diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c
index af9d84f..1773ab7 100644
--- a/board/siemens/dxr2/board.c
+++ b/board/siemens/dxr2/board.c
@@ -38,11 +38,11 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD
static struct dxr2_baseboard_id __attribute__((section(".data"))) settings;
-
+/* @303MHz-i0 */
const struct ddr3_data ddr3_default = {
- 0x33524444, 0x56312e33, 0x0100, 0x0001, 0x003A, 0x008A, 0x010B,
- 0x00C4, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x0006, 0x61C04AB2,
- 0x00000618,
+ 0x33524444, 0x56312e34, 0x0080, 0x0000, 0x0038, 0x003E, 0x00A4,
+ 0x0075, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
+ 0x00000618, 0x0000014A,
};
static void set_default_ddr3_timings(void)
@@ -73,6 +73,7 @@ static void print_ddr3_timings(void)
PRINTARGS(sdram_config);
PRINTARGS(ref_ctrl);
+ PRINTARGS(ioctr_val);
}
static void print_chip_data(void)
@@ -168,7 +169,7 @@ struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
- config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &dxr2_ddr3_data,
+ config_ddr(DDR_PLL_FREQ, settings.ddr3.ioctr_val, &dxr2_ddr3_data,
&dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
}
diff --git a/board/siemens/dxr2/board.h b/board/siemens/dxr2/board.h
index 2be78fb..abf5432 100644
--- a/board/siemens/dxr2/board.h
+++ b/board/siemens/dxr2/board.h
@@ -22,11 +22,11 @@
#define MAGIC_CHIP 0x50494843
/* Automatic generated definition */
-/* Wed, 19 Jun 2013 10:57:48 +0200 */
-/* From file: draco/ddr3-data-micron.txt */
+/* Wed, 18 Sep 2013 18:58:27 +0200 */
+/* From file: draco/ddr3-data-micron-v2.txt */
struct ddr3_data {
unsigned int magic; /* 0x33524444 */
- unsigned int version; /* 0x56312e33 */
+ unsigned int version; /* 0x56312e34 */
unsigned short int ddr3_sratio; /* 0x0100 */
unsigned short int iclkout; /* 0x0001 */
unsigned short int dt0rdsratio0; /* 0x003A */
@@ -36,9 +36,10 @@ struct ddr3_data {
unsigned int sdram_tim1; /* 0x0888A39B */
unsigned int sdram_tim2; /* 0x26247FDA */
unsigned int sdram_tim3; /* 0x501F821F */
- unsigned short int emif_ddr_phy_ctlr_1; /* 0x0006 */
+ unsigned int emif_ddr_phy_ctlr_1; /* 0x00100206 */
unsigned int sdram_config; /* 0x61C04AB2 */
unsigned int ref_ctrl; /* 0x00000618 */
+ unsigned int ioctr_val; /* 0x0000018B */
};
struct chip_data {
diff --git a/board/siemens/dxr2/mux.c b/board/siemens/dxr2/mux.c
index bc80b79..5c22999 100644
--- a/board/siemens/dxr2/mux.c
+++ b/board/siemens/dxr2/mux.c
@@ -63,6 +63,164 @@ static struct module_pin_mux gpios_pin_mux[] = {
{OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)},
{OFFSET(gpmc_csn3), MODE(7) }, /* LED0 GPIO2_0 */
{OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */
+ /* Triacs in HW Rev 2 */
+ {OFFSET(uart1_ctsn), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y5 GPIO0_12*/
+ {OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y3 GPIO2_28*/
+ {OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y7 GPIO2_27*/
+ /* Triacs initial HW Rev */
+ {OFFSET(gpmc_csn1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_30 Y0 */
+ {OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_28 Y1 */
+ {OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_31 Y2 */
+ {OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_11 Y3 */
+ {OFFSET(lcd_data14), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_10 Y4 */
+ {OFFSET(gpmc_clk), MODE(7) | RXACTIVE | PULLUDDIS}, /* 2_1 Y5 */
+ {OFFSET(emu1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 3_8 Y6 */
+ {OFFSET(gpmc_ad15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_15 Y7 */
+ /* Remaining pins that were not used in this file */
+ {OFFSET(gpmc_ad8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_ad9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a10), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_vsync), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_hsync), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_pclk), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_ac_bias_en), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mmc0_dat3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mmc0_dat0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mmc0_clk), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mmc0_cmd), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(spi0_sclk), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(spi0_d0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(spi0_d1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(spi0_cs0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart1_rtsn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart1_rxd), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart1_txd), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_aclkx), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_fsx), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_axr0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_ahclkr), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_aclkr), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_fsr), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_axr1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_ahclkx), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(xdma_event_intr0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(xdma_event_intr1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(nresetin_out), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(porz), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(nnmi), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(osc0_in), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(osc0_out), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(rsvd1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(tms), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(tdi), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(tdo), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(tck), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ntrst), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(osc1_in), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(osc1_out), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(pmic_power_en), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(rtc_porz), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(rsvd2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ext_wakeup), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(enz_kaldo_1p8v), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_dm), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_dp), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_ce), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_id), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_vbus), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_dm), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_dp), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_ce), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_id), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_vbus), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_resetn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_csn0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_cke), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_ck), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_nck), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_casn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_rasn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_wen), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_ba0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_ba1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_ba2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a10), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a11), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a12), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a13), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a14), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a15), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_odt), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d10), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d11), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d12), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d13), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d14), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d15), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqm0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqm1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqs0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqsn0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqs1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqsn1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_vref), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_vtp), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_strben0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_strben1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS},
{-1},
};
diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c
index 2c1841f..094b4d6 100644
--- a/board/siemens/pxm2/board.c
+++ b/board/siemens/pxm2/board.c
@@ -413,8 +413,7 @@ static int conf_disp_pll(int m, int n)
static int board_video_init(void)
{
- /* set 300 MHz */
- conf_disp_pll(25, 2);
+ conf_disp_pll(24, 1);
if (factory_dat.pxm50)
da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
else
diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c
index 5de8fc6..0cf17ef 100644
--- a/board/siemens/rut/board.c
+++ b/board/siemens/rut/board.c
@@ -83,9 +83,48 @@ struct cmd_control rut_ddr3_cmd_ctrl_data = {
&rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
}
+static int request_and_pulse_reset(int gpio, const char *name)
+{
+ int ret;
+ const int delay_us = 2000; /* 2ms */
+
+ ret = gpio_request(gpio, name);
+ if (ret < 0) {
+ printf("%s: Unable to request %s\n", __func__, name);
+ goto err;
+ }
+
+ ret = gpio_direction_output(gpio, 0);
+ if (ret < 0) {
+ printf("%s: Unable to set %s as output\n", __func__, name);
+ goto err_free_gpio;
+ }
+
+ udelay(delay_us);
+
+ gpio_set_value(gpio, 1);
+
+ return 0;
+
+err_free_gpio:
+ gpio_free(gpio);
+err:
+ return ret;
+}
+
+#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
+#define ETH_PHY_RESET_GPIO GPIO_TO_PIN(2, 18)
+#define MAXTOUCH_RESET_GPIO GPIO_TO_PIN(3, 18)
+#define DISPLAY_RESET_GPIO GPIO_TO_PIN(3, 19)
+
+#define REQUEST_AND_PULSE_RESET(N) \
+ request_and_pulse_reset(N, #N);
+
static void spl_siemens_board_init(void)
{
- return;
+ REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO);
+ REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
+ REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
}
#endif /* if def CONFIG_SPL_BUILD */
@@ -336,7 +375,6 @@ int clk_get(int clk)
static int conf_disp_pll(int m, int n)
{
struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
- struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
#if defined(DISPL_PLL_SPREAD_SPECTRUM)
struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
@@ -353,8 +391,6 @@ static int conf_disp_pll(int m, int n)
0
};
do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
- /* 0x44e0_0500 write lcdc pixel clock mux Linux hat hier 0 */
- writel(0x0, &cmdpll->clklcdcpixelclk);
do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
@@ -380,10 +416,13 @@ static int enable_lcd(void)
{
unsigned char buf[1];
+ set_gpio(BOARD_LCD_RESET, 0);
+ mdelay(1);
set_gpio(BOARD_LCD_RESET, 1);
+ mdelay(1);
/* spi lcd init */
- kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_3);
+ kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0);
/* backlight on */
buf[0] = 0xf;
@@ -418,7 +457,7 @@ static int board_video_init(void)
printf("%s: %s not found, using default %s\n", __func__,
factory_dat.disp_name, lcd_panels[i].name);
}
- conf_disp_pll(25, 2);
+ conf_disp_pll(24, 1);
da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
lcd_cfgs[display].bpp);
diff --git a/include/configs/dxr2.h b/include/configs/dxr2.h
index cd553ec..1e42f5c 100644
--- a/include/configs/dxr2.h
+++ b/include/configs/dxr2.h
@@ -21,8 +21,8 @@
#define CONFIG_SYS_MPUCLK 275
#define DXR2_IOCTRL_VAL 0x18b
-#define DDR_PLL_FREQ 266
-#define CONFIG_SPL_AM33XX_DO_NOT_ENABLE_RTC32K
+#define DDR_PLL_FREQ 303
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
#define BOARD_DFU_BUTTON_GPIO 27
#define BOARD_DFU_BUTTON_LED 64
@@ -62,7 +62,7 @@
/* Default env settings */
#define CONFIG_EXTRA_ENV_SETTINGS \
"hostname=dxr2\0" \
- "nand_img_size=0x300000\0" \
+ "nand_img_size=0x400000\0" \
"optargs=\0" \
CONFIG_COMMON_ENV_SETTINGS
@@ -75,10 +75,9 @@
"run dfu_start; " \
"reset; " \
"fi;" \
-"if ping ${serverip}; then " \
- "run net_nfs; " \
-"fi;" \
-"run nand_boot;"
+"run nand_boot;" \
+"reset;"
+
#else
#define CONFIG_BOOTDELAY 0
diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h
index 20b0f9a..7722f7b 100644
--- a/include/configs/pxm2.h
+++ b/include/configs/pxm2.h
@@ -70,6 +70,7 @@
"hostname=pxm2\0" \
"nand_img_size=0x500000\0" \
"optargs=\0" \
+ "splashpos=m,m\0" \
CONFIG_COMMON_ENV_SETTINGS \
"mmc_dev=0\0" \
"mmc_root=/dev/mmcblk0p2 rw\0" \
@@ -118,9 +119,7 @@
"fi;" \
"fi;" \
"run nand_boot;" \
- "if ping ${serverip}; then " \
- "run net_nfs; " \
- "fi; "
+ "reset;"
#else
#define CONFIG_BOOTDELAY 0
@@ -148,6 +147,8 @@
#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE
#define PWM_TICKS 0x1388
#define PWM_DUTY 0x200
+#define CONFIG_SYS_CONSOLE_BG_COL 0xff
+#define CONFIG_SYS_CONSOLE_FG_COL 0x00
#endif
#endif /* ! __CONFIG_PXM2_H */
diff --git a/include/configs/rut.h b/include/configs/rut.h
index 7c94644..d4519f9 100644
--- a/include/configs/rut.h
+++ b/include/configs/rut.h
@@ -65,7 +65,8 @@
/* Default env settings */
#define CONFIG_EXTRA_ENV_SETTINGS \
"hostname=rut\0" \
- "splashpos=488,352\0" \
+ "nand_img_size=0x500000\0" \
+ "splashpos=m,m\0" \
"optargs=fixrtc --no-log consoleblank=0 \0" \
CONFIG_COMMON_ENV_SETTINGS \
"mmc_dev=0\0" \
@@ -111,9 +112,7 @@
"fi;" \
"fi;" \
"run nand_boot;" \
- "if ping ${serverip}; then " \
- "run net_nfs; " \
- "fi; "
+ "reset;"
#else
#define CONFIG_BOOTDELAY 0
@@ -151,6 +150,9 @@
#define BOARD_LCD_RESET 115 /* Bank 3 pin 19 */
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_FORMIKE
+#define DISPL_PLL_SPREAD_SPECTRUM
+#define CONFIG_SYS_CONSOLE_BG_COL 0xff
+#define CONFIG_SYS_CONSOLE_FG_COL 0x00
#endif
#endif /* ! __CONFIG_RUT_H */
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 9eb0a04..9296de0 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -254,11 +254,11 @@
#define CONFIG_USB_GADGET
#define CONFIG_USBDOWNLOAD_GADGET
-/* USB TI's IDs */
+/* USB DRACO ID as default */
#define CONFIG_USBD_HS
-#define CONFIG_G_DNL_VENDOR_NUM 0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM 0x4a47
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
+#define CONFIG_G_DNL_VENDOR_NUM 0x0908
+#define CONFIG_G_DNL_PRODUCT_NUM 0x02d2
+#define CONFIG_G_DNL_MANUFACTURER "Siemens AG"
/* USB Device Firmware Update support */
#define CONFIG_DFU_FUNCTION
@@ -358,31 +358,38 @@
#define CONFIG_COMMON_ENV_SETTINGS \
"verify=no \0" \
"project_dir=systemone\0" \
+ "upgrade_available=0\0" \
+ "altbootcmd=run bootcmd\0" \
+ "bootlimit=3\0" \
+ "partitionset_active=A\0" \
"loadaddr=0x82000000\0" \
"kloadaddr=0x81000000\0" \
"script_addr=0x81900000\0" \
- "console=console=ttyMTD,mtdoops console=ttyO0,115200n8\0" \
- "active_set=a\0" \
+ "console=console=ttyMTD,mtdoops console=ttyO0,115200n8 panic=5\0" \
"nand_active_ubi_vol=rootfs_a\0" \
+ "nand_active_ubi_vol_A=rootfs_a\0" \
+ "nand_active_ubi_vol_B=rootfs_b\0" \
"nand_root_fs_type=ubifs rootwait=1\0" \
"nand_src_addr=0x280000\0" \
- "nand_src_addr_a=0x280000\0" \
- "nand_src_addr_b=0x780000\0" \
+ "nand_src_addr_A=0x280000\0" \
+ "nand_src_addr_B=0x780000\0" \
"nfsopts=nolock rw mem=128M\0" \
"ip_method=none\0" \
"bootenv=uEnv.txt\0" \
"bootargs_defaults=setenv bootargs " \
"console=${console} " \
+ "${testargs} " \
"${optargs}\0" \
"nand_args=run bootargs_defaults;" \
"mtdparts default;" \
- "setenv nand_active_ubi_vol rootfs_${active_set};" \
- "setenv ${active_set} true;" \
- "if test -n ${a}; then " \
- "setenv nand_src_addr ${nand_src_addr_a};" \
+ "setenv ${partitionset_active} true;" \
+ "if test -n ${A}; then " \
+ "setenv nand_active_ubi_vol ${nand_active_ubi_vol_A};" \
+ "setenv nand_src_addr ${nand_src_addr_A};" \
"fi;" \
- "if test -n ${b}; then " \
- "setenv nand_src_addr ${nand_src_addr_b};" \
+ "if test -n ${B}; then " \
+ "setenv nand_active_ubi_vol ${nand_active_ubi_vol_B};" \
+ "setenv nand_src_addr ${nand_src_addr_B};" \
"fi;" \
"setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
"ubi.mtd=9,2048;" \
@@ -403,9 +410,26 @@
"setenv bootargs ${bootargs} " \
"root=/dev/nfs ${mtdparts} " \
"nfsroot=${serverip}:${rootpath},${nfsopts} " \
- "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \
+ "ip=${ipaddr}:${serverip}:" \
"${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
- "nand_boot=echo Booting from nand, active set ${active_set} ...; " \
+ "nand_boot=echo Booting from nand; " \
+ "if test ${upgrade_available} -eq 1; then " \
+ "if test ${bootcount} -gt ${bootlimit}; " \
+ "then " \
+ "setenv upgrade_available 0;" \
+ "setenv ${partitionset_active} true;" \
+ "if test -n ${A}; then " \
+ "setenv partitionset_active B; " \
+ "env delete A; " \
+ "fi;" \
+ "if test -n ${B}; then " \
+ "setenv partitionset_active A; " \
+ "env delete B; " \
+ "fi;" \
+ "saveenv; " \
+ "fi;" \
+ "fi;" \
+ "echo set ${partitionset_active}...;" \
"run nand_args; " \
"nand read.i ${kloadaddr} ${nand_src_addr} " \
"${nand_img_size}; bootm ${kloadaddr}\0" \
@@ -414,7 +438,7 @@
"tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \
"bootm ${kloadaddr}\0" \
"flash_self=run nand_boot\0" \
- "flash_self_test=setenv bootargs_defaults ${bootargs_defaults} test; " \
+ "flash_self_test=setenv testargs test; " \
"run nand_boot\0" \
"dfu_start=echo Preparing for dfu mode ...; " \
"run dfu_args; \0" \
@@ -425,8 +449,9 @@
"mode; echo Not ready yet: 'run flash_nfs' to use kernel " \
"from memory and root filesystem over NFS; echo Type " \
"'run net_nfs' to get Kernel over TFTP and mount root " \
- "filesystem over NFS; echo Set active_set variable to 'a' " \
- "or 'b' to select kernel and rootfs partition; " \
+ "filesystem over NFS; " \
+ "echo Set partitionset_active variable to 'A' " \
+ "or 'B' to select kernel and rootfs partition; " \
"echo" \
"\0"
@@ -456,4 +481,10 @@
#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
"press \"<Esc><Esc>\" to stop\n", bootdelay
+/* Reboot after 60 sec if bootcmd fails */
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_BOOT_RETRY_TIME 60
+
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_ENV
#endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */
generated by cgit v1.1 at 2024-12-16 22:08:44 +0000