summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/cpu/arm920t/a320/timer.c6
-rw-r--r--arch/arm/cpu/arm920t/s3c24x0/timer.c14
-rw-r--r--arch/arm/cpu/arm926ejs/armada100/timer.c12
-rw-r--r--arch/arm/cpu/arm926ejs/at91/timer.c6
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/timer.c4
-rw-r--r--arch/arm/cpu/arm926ejs/pantheon/timer.c12
-rw-r--r--arch/arm/cpu/armv7/u8500/timer.c2
-rw-r--r--arch/arm/include/asm/global_data.h2
8 files changed, 29 insertions, 29 deletions
diff --git a/arch/arm/cpu/arm920t/a320/timer.c b/arch/arm/cpu/arm920t/a320/timer.c
index 2873643..781533b 100644
--- a/arch/arm/cpu/arm920t/a320/timer.c
+++ b/arch/arm/cpu/arm920t/a320/timer.c
@@ -75,7 +75,7 @@ int timer_init(void)
writel(cr, &tmr->cr);
gd->arch.timer_rate_hz = TIMER_CLOCK;
- gd->tbu = gd->tbl = 0;
+ gd->arch.tbu = gd->tbl = 0;
return 0;
}
@@ -90,9 +90,9 @@ unsigned long long get_ticks(void)
/* increment tbu if tbl has rolled over */
if (now < gd->tbl)
- gd->tbu++;
+ gd->arch.tbu++;
gd->tbl = now;
- return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+ return (((unsigned long long)gd->arch.tbu) << 32) | gd->tbl;
}
void __udelay(unsigned long usec)
diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c b/arch/arm/cpu/arm920t/s3c24x0/timer.c
index 7694fea..e59e614 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/timer.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c
@@ -45,17 +45,17 @@ int timer_init(void)
/* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */
writel(0x0f00, &timers->tcfg0);
- if (gd->tbu == 0) {
+ if (gd->arch.tbu == 0) {
/*
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
* (default) and prescaler = 16. Should be 10390
* @33.25MHz and 15625 @ 50 MHz
*/
- gd->tbu = get_PCLK() / (2 * 16 * 100);
+ gd->arch.tbu = get_PCLK() / (2 * 16 * 100);
gd->arch.timer_rate_hz = get_PCLK() / (2 * 16);
}
/* load value for 10 ms timeout */
- writel(gd->tbu, &timers->tcntb4);
+ writel(gd->arch.tbu, &timers->tcntb4);
/* auto load, manual update of timer 4 */
tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
writel(tmr, &timers->tcon);
@@ -82,7 +82,7 @@ void __udelay (unsigned long usec)
ulong start = get_ticks();
tmo = usec / 1000;
- tmo *= (gd->tbu * 100);
+ tmo *= (gd->arch.tbu * 100);
tmo /= 1000;
while ((ulong) (get_ticks() - start) < tmo)
@@ -104,10 +104,10 @@ void udelay_masked(unsigned long usec)
if (usec >= 1000) {
tmo = usec / 1000;
- tmo *= (gd->tbu * 100);
+ tmo *= (gd->arch.tbu * 100);
tmo /= 1000;
} else {
- tmo = usec * (gd->tbu * 100);
+ tmo = usec * (gd->arch.tbu * 100);
tmo /= (1000 * 1000);
}
@@ -133,7 +133,7 @@ unsigned long long get_ticks(void)
gd->tbl += gd->lastinc - now;
} else {
/* we have an overflow ... */
- gd->tbl += gd->lastinc + gd->tbu - now;
+ gd->tbl += gd->lastinc + gd->arch.tbu - now;
}
gd->lastinc = now;
diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c
index 355cd6d..18ffd0c 100644
--- a/arch/arm/cpu/arm926ejs/armada100/timer.c
+++ b/arch/arm/cpu/arm926ejs/armada100/timer.c
@@ -61,7 +61,7 @@ struct armd1tmr_registers {
#define COUNT_RD_REQ 0x1
DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+/* Using gd->arch.tbu from timestamp and gd->tbl for lastdec */
/* For preventing risk of instability in reading counter value,
* first set read request to register cvwr and then read same
@@ -84,14 +84,14 @@ ulong get_timer_masked(void)
if (now >= gd->tbl) {
/* normal mode */
- gd->tbu += now - gd->tbl;
+ gd->arch.tbu += now - gd->tbl;
} else {
/* we have an overflow ... */
- gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+ gd->arch.tbu += now + TIMER_LOAD_VAL - gd->tbl;
}
gd->tbl = now;
- return gd->tbu;
+ return gd->arch.tbu;
}
ulong get_timer(ulong base)
@@ -135,9 +135,9 @@ int timer_init(void)
/* Enable timer 0 */
writel(0x1, &armd1timers->cer);
- /* init the gd->tbu and gd->tbl value */
+ /* init the gd->arch.tbu and gd->tbl value */
gd->tbl = read_timer();
- gd->tbu = 0;
+ gd->arch.tbu = 0;
return 0;
}
diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c
index 061ccaf..f691518 100644
--- a/arch/arm/cpu/arm926ejs/at91/timer.c
+++ b/arch/arm/cpu/arm926ejs/at91/timer.c
@@ -80,7 +80,7 @@ int timer_init(void)
writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
- gd->tbu = gd->tbl = 0;
+ gd->arch.tbu = gd->tbl = 0;
return 0;
}
@@ -96,9 +96,9 @@ unsigned long long get_ticks(void)
/* increment tbu if tbl has rolled over */
if (now < gd->tbl)
- gd->tbu++;
+ gd->arch.tbu++;
gd->tbl = now;
- return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+ return (((unsigned long long)gd->arch.tbu) << 32) | gd->tbl;
}
void __udelay(unsigned long usec)
diff --git a/arch/arm/cpu/arm926ejs/davinci/timer.c b/arch/arm/cpu/arm926ejs/davinci/timer.c
index 7e852b5..e28e6e3 100644
--- a/arch/arm/cpu/arm926ejs/davinci/timer.c
+++ b/arch/arm/cpu/arm926ejs/davinci/timer.c
@@ -75,10 +75,10 @@ unsigned long long get_ticks(void)
/* increment tbu if tbl has rolled over */
if (now < gd->tbl)
- gd->tbu++;
+ gd->arch.tbu++;
gd->tbl = now;
- return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+ return (((unsigned long long)gd->arch.tbu) << 32) | gd->tbl;
}
ulong get_timer(ulong base)
diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c
index 28aadad..701d439 100644
--- a/arch/arm/cpu/arm926ejs/pantheon/timer.c
+++ b/arch/arm/cpu/arm926ejs/pantheon/timer.c
@@ -60,7 +60,7 @@ struct panthtmr_registers {
#define COUNT_RD_REQ 0x1
DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+/* Using gd->arch.tbu from timestamp and gd->tbl for lastdec */
/*
* For preventing risk of instability in reading counter value,
@@ -92,14 +92,14 @@ ulong get_timer_masked(void)
if (now >= gd->tbl) {
/* normal mode */
- gd->tbu += now - gd->tbl;
+ gd->arch.tbu += now - gd->tbl;
} else {
/* we have an overflow ... */
- gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+ gd->arch.tbu += now + TIMER_LOAD_VAL - gd->tbl;
}
gd->tbl = now;
- return gd->tbu;
+ return gd->arch.tbu;
}
ulong get_timer(ulong base)
@@ -144,9 +144,9 @@ int timer_init(void)
/* Enable timer 0 */
writel(0x1, &panthtimers->cer);
- /* init the gd->tbu and gd->tbl value */
+ /* init the gd->arch.tbu and gd->tbl value */
gd->tbl = read_timer();
- gd->tbu = 0;
+ gd->arch.tbu = 0;
return 0;
}
diff --git a/arch/arm/cpu/armv7/u8500/timer.c b/arch/arm/cpu/armv7/u8500/timer.c
index 79aad99..bb9165b 100644
--- a/arch/arm/cpu/armv7/u8500/timer.c
+++ b/arch/arm/cpu/armv7/u8500/timer.c
@@ -132,7 +132,7 @@ ulong get_timer(ulong base)
/*
* Emulation of Power architecture long long timebase.
*
- * TODO: Support gd->tbu for real long long timebase.
+ * TODO: Support gd->arch.tbu for real long long timebase.
*/
unsigned long long get_ticks(void)
{
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index eb8c69a..47fa4c0 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -37,6 +37,7 @@ struct arch_global_data {
#endif
/* "static data" needed by most of timer.c on ARM platforms */
unsigned long timer_rate_hz;
+ unsigned long tbu;
};
/*
@@ -64,7 +65,6 @@ typedef struct global_data {
#ifdef CONFIG_ARM
/* "static data" needed by most of timer.c on ARM platforms */
unsigned long tbl;
- unsigned long tbu;
unsigned long long timer_reset_value;
unsigned long lastinc;
#endif
generated by cgit v1.1 at 2024-12-21 13:43:23 +0000