diff options
118 files changed, 3184 insertions, 415 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 143f31b..6e6affa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -697,9 +697,6 @@ Matthias Kaehlcke <matthias@kaehlcke.net> edb9315 ARM920T (EP9315) edb9315a ARM920T (EP9315) -Konstantin Kletschke <kletschke@synertronixx.de> - scb9328 ARM920T - Nishant Kamat <nskamat@ti.com> omap1610h2 ARM926EJS @@ -714,6 +711,9 @@ Chander Kashyap <k.chander@samsung.com> SMDKV310 ARM ARMV7 (S5PC210 SoC) +Torsten Koschorrek <koschorrek@synertronixx.de> + scb9328 ARM920T (i.MXL) + Frederik Kriewitz <frederik@kriewitz.eu> devkit8000 ARM ARMV7 (OMAP3530 SoC) @@ -904,6 +904,7 @@ Lei Wen <leiwen@marvell.com> Matthias Weisser <weisserm@arcor.de> jadecpu ARM926EJS (MB86R01 SoC) + zmx25 ARM926EJS (imx25 SoC) Richard Woodruff <r-woodruff2@ti.com> @@ -442,6 +442,16 @@ The following options need to be configured: crash. This is needed for buggy hardware (uc101) where no pull down resistor is connected to the signal IDE5V_DD7. + CONFIG_MACH_TYPE [relevant for ARM only][mandatory] + + This setting is mandatory for all boards that have only one + machine type and must be used to specify the machine type + number as it appears in the ARM machine registry + (see http://www.arm.linux.org.uk/developer/machines/). + Only boards that have multiple machine types supported + in a single configuration file and the machine type is + runtime discoverable, do not have to use this setting. + - vxWorks boot parameters: bootvx constructs a valid bootline using the following @@ -3314,6 +3324,15 @@ List of environment variables (most likely not complete): This can be used to load and uncompress arbitrary data. + fdt_high - if set this restricts the maximum address that the + flattened device tree will be copied into upon boot. + If this is set to the special value 0xFFFFFFFF then + the fdt will not be copied at all on boot. For this + to work it must reside in writable memory, have + sufficient padding on the end of it for u-boot to + add the information it needs into it, and the memory + must be accessible by the kernel. + i2cfast - (PPC405GP|PPC405EP only) if set to 'y' configures Linux I2C driver for fast mode (400kHZ). This environment variable is used in diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 4ebf38d..248431b 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -23,6 +23,7 @@ #include <common.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> #include <asm/io.h> static u32 mx31_decode_pll(u32 reg, u32 infreq) @@ -60,7 +61,7 @@ static u32 mx31_get_mcu_main_clk(void) return mx31_get_mpl_dpdgck_clk(); } -u32 mx31_get_ipg_clk(void) +static u32 mx31_get_ipg_clk(void) { u32 freq = mx31_get_mcu_main_clk(); u32 pdr0 = __REG(CCM_PDR0); @@ -78,6 +79,24 @@ void mx31_dump_clocks(void) printf("ipg clock : %dHz\n", mx31_get_ipg_clk()); } +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return mx31_get_mcu_main_clk(); + case MXC_IPG_CLK: + case MXC_CSPI_CLK: + case MXC_UART_CLK: + return mx31_get_ipg_clk(); + } + return -1; +} + +u32 imx_get_uartclk(void) +{ + return mxc_get_clock(MXC_UART_CLK); +} + void mx31_gpio_mux(unsigned long mode) { unsigned long reg, shift, tmp; diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile index 20f36e3..284cdc5 100644 --- a/arch/arm/cpu/arm1136/mx35/Makefile +++ b/arch/arm/cpu/arm1136/mx35/Makefile @@ -50,14 +50,3 @@ include $(SRCTREE)/rules.mk sinclude $(obj).depend ######################################################################### - -$(TOPDIR)/include/asm/arch/asm-offsets.h: $(TOPDIR)/include/autoconf.mk.dep \ - ./asm-offsets.s - @echo Generating $@ - $(TOPDIR)/tools/scripts/make-asm-offsets ./asm-offsets.s $@ - -asm-offsets.s: $(TOPDIR)/include/autoconf.mk.dep \ - ./asm-offsets.c - $(CC) -DDO_DEPS_ONLY \ - $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \ - -o $@ ./asm-offsets.c -c -S diff --git a/arch/arm/cpu/arm926ejs/mx25/Makefile b/arch/arm/cpu/arm926ejs/mx25/Makefile index 38d7f03..9219c06 100644 --- a/arch/arm/cpu/arm926ejs/mx25/Makefile +++ b/arch/arm/cpu/arm926ejs/mx25/Makefile @@ -24,18 +24,18 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS = generic.o timer.o -MX27OBJS = reset.o +COBJS = generic.o timer.o reset.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -SRCS += $(addprefix $(SRCTREE)/arch/arm/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(MX27OBJS)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) all: $(obj).depend $(LIB) $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) +$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h + ######################################################################### # defines $(obj).depend target diff --git a/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c new file mode 100644 index 0000000..ba8dfd4 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c @@ -0,0 +1,60 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <common.h> +#include <asm/arch/imx-regs.h> + +#include <linux/kbuild.h> + +int main(void) +{ + /* Clock Control Module */ + DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); + DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0)); + DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1)); + DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2)); + DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2])); + DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr)); + + /* Enhanced SDRAM Controller */ + DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0)); + DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0)); + DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc)); + + /* Multi-Layer AHB Crossbar Switch */ + DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); + DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); + DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); + DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); + DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); + DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); + DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); + DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); + DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); + DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); + DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); + DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); + DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); + DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); + DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); + + /* AHB <-> IP-Bus Interface */ + DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); + DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); + + return 0; +} diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c index 14f0c2d..7c8a71b 100644 --- a/arch/arm/cpu/arm926ejs/mx25/timer.c +++ b/arch/arm/cpu/arm926ejs/mx25/timer.c @@ -187,3 +187,15 @@ void __udelay (unsigned long usec) while (get_ticks() < tmp) /* loop till event */ /*NOP*/; } + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + + tbclk = CONFIG_MX25_CLK32; + return tbclk; +} diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile index 0e112b3..7ac1a21 100644 --- a/arch/arm/cpu/arm926ejs/mx27/Makefile +++ b/arch/arm/cpu/arm926ejs/mx27/Makefile @@ -34,6 +34,8 @@ all: $(obj).depend $(LIB) $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) +$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h + ######################################################################### # defines $(obj).depend target diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c new file mode 100644 index 0000000..f3a8d7b --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c @@ -0,0 +1,45 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <common.h> +#include <asm/arch/imx-regs.h> + +#include <linux/kbuild.h> + +int main(void) +{ + DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0)); + DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1)); + DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0)); + DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1)); + + DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); + DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); + DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); + DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); + DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); + DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); + DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); + + DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0)); + DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0)); + DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1)); + DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1)); + DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc)); + + return 0; +} diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c index 27642bf..222a8e9 100644 --- a/arch/arm/cpu/arm926ejs/mx27/generic.c +++ b/arch/arm/cpu/arm926ejs/mx27/generic.c @@ -271,7 +271,7 @@ void imx_gpio_mode(int gpio_mode) } #ifdef CONFIG_MXC_UART -void mx27_uart_init_pins(void) +void mx27_uart1_init_pins(void) { int i; unsigned int mode[] = { diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c b/arch/arm/cpu/arm926ejs/orion5x/dram.c index 3e1ff7d..5cc31a9 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/dram.c +++ b/arch/arm/cpu/arm926ejs/orion5x/dram.c @@ -53,7 +53,7 @@ int dram_init (void) { /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (volatile long *) orion5x_sdram_bar(0), + (long *) orion5x_sdram_bar(0), CONFIG_MAX_RAM_BANK_SIZE); return 0; } @@ -65,7 +65,7 @@ void dram_init_banksize (void) for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { gd->bd->bi_dram[i].start = orion5x_sdram_bar(i); gd->bd->bi_dram[i].size = get_ram_size( - (volatile long *) (gd->bd->bi_dram[i].start), + (long *) (gd->bd->bi_dram[i].start), CONFIG_MAX_RAM_BANK_SIZE); } } diff --git a/arch/arm/cpu/armv7/mx5/Makefile b/arch/arm/cpu/armv7/mx5/Makefile index e8be9c9..6e13cc3 100644 --- a/arch/arm/cpu/armv7/mx5/Makefile +++ b/arch/arm/cpu/armv7/mx5/Makefile @@ -45,4 +45,6 @@ include $(SRCTREE)/rules.mk sinclude $(obj).depend +lowlevel_init.o : $(TOPDIR)/include/asm/arch/asm-offsets.h + ######################################################################### diff --git a/arch/arm/cpu/armv7/mx5/asm-offsets.c b/arch/arm/cpu/armv7/mx5/asm-offsets.c new file mode 100644 index 0000000..f972498 --- /dev/null +++ b/arch/arm/cpu/armv7/mx5/asm-offsets.c @@ -0,0 +1,76 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <common.h> +#include <asm/arch/imx-regs.h> + +#include <linux/kbuild.h> + +int main(void) +{ + + /* Round up to make sure size gives nice stack alignment */ + DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr)); + DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr)); + DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr)); + DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr)); + DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr)); + DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr)); + DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr)); + DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1)); + DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2)); + DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1)); + DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr)); + DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr)); + DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr)); + DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr)); + DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2)); + DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3)); + DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4)); + DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr)); + DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr)); + DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr)); + DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor)); + DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr)); + DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr)); + DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr)); + DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr)); + DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr)); + DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0)); + DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1)); + DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2)); + DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3)); + DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4)); + DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5)); + DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6)); + DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor)); +#if defined(CONFIG_MX53) + DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7)); +#endif + + /* DPLL */ + DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl)); + DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config)); + DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op)); + DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd)); + DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn)); + DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op)); + DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd)); + DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn)); + + return 0; +} diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 96ebfe2..94de9f1 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -39,10 +39,14 @@ orr r0, r0, #(1 << 23) /* disable write allocate combine */ orr r0, r0, #(1 << 22) /* disable write allocate */ - cmp r3, #0x10 /* r3 contains the silicon rev */ +#if defined(CONFIG_MX51) + ldr r1, =0x0 + ldr r3, [r1, #ROM_SI_REV] + cmp r3, #0x10 /* disable write combine for TO 2 and lower revs */ orrls r0, r0, #(1 << 25) +#endif mcr 15, 1, r0, c9, c0, 2 .endm /* init_l2cc */ diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 0e698b6..eee648b 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -283,6 +283,7 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start +#ifndef CONFIG_SKIP_LOWLEVEL_INIT /************************************************************************* * * CPU_init_critical registers @@ -327,6 +328,7 @@ cpu_init_crit: bl lowlevel_init @ go setup pll,mux,memory mov lr, ip @ restore link mov pc, lr @ back to my caller +#endif /* ************************************************************************* * diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index 55ad115..2ccb445 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -86,8 +86,8 @@ struct esdramc_regs { /* GPIO registers */ struct gpio_regs { - u32 dr; /* data */ - u32 dir; /* direction */ + u32 gpio_dr; /* data */ + u32 gpio_dir; /* direction */ u32 psr; /* pad satus */ u32 icr1; /* interrupt config 1 */ u32 icr2; /* interrupt config 2 */ @@ -141,6 +141,45 @@ struct fuse_bank0_regs { u32 mac_addr[6]; }; +/* Multi-Layer AHB Crossbar Switch (MAX) registers */ +struct max_regs { + u32 mpr0; + u32 pad00[3]; + u32 sgpcr0; + u32 pad01[59]; + u32 mpr1; + u32 pad02[3]; + u32 sgpcr1; + u32 pad03[59]; + u32 mpr2; + u32 pad04[3]; + u32 sgpcr2; + u32 pad05[59]; + u32 mpr3; + u32 pad06[3]; + u32 sgpcr3; + u32 pad07[59]; + u32 mpr4; + u32 pad08[3]; + u32 sgpcr4; + u32 pad09[251]; + u32 mgpcr0; + u32 pad10[63]; + u32 mgpcr1; + u32 pad11[63]; + u32 mgpcr2; + u32 pad12[63]; + u32 mgpcr3; + u32 pad13[63]; + u32 mgpcr4; +}; + +/* AHB <-> IP-Bus Interface (AIPS) */ +struct aips_regs { + u32 mpr_0_7; + u32 mpr_8_15; +}; + #endif /* AIPS 1 */ @@ -318,4 +357,10 @@ struct fuse_bank0_regs { #define WSR_UNLOCK1 0x5555 #define WSR_UNLOCK2 0xAAAA +/* Names used in GPIO driver */ +#define GPIO1_BASE_ADDR IMX_GPIO1_BASE +#define GPIO2_BASE_ADDR IMX_GPIO2_BASE +#define GPIO3_BASE_ADDR IMX_GPIO3_BASE +#define GPIO4_BASE_ADDR IMX_GPIO4_BASE + #endif /* _IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-mx25/macro.h b/arch/arm/include/asm/arch-mx25/macro.h new file mode 100644 index 0000000..276c71c --- /dev/null +++ b/arch/arm/include/asm/arch-mx25/macro.h @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2011 + * Matthias Weisser <weisserm@arcor.de> + * + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby <jrigby@gmail.com> + * + * Common asm macros for imx25 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_MACRO_H__ +#define __ASM_ARM_ARCH_MACRO_H__ +#ifdef __ASSEMBLY__ + +#include <asm/arch/imx-regs.h> +#include <asm/arch/asm-offsets.h> + +.macro init_aips + write32 IMX_AIPS1_BASE + AIPS_MPR_0_7, 0x77777777 + write32 IMX_AIPS1_BASE + AIPS_MPR_8_15, 0x77777777 + write32 IMX_AIPS2_BASE + AIPS_MPR_0_7, 0x77777777 + write32 IMX_AIPS2_BASE + AIPS_MPR_8_15, 0x77777777 +.endm + +.macro init_max + write32 IMX_MAX_BASE + MAX_MPR0, 0x43210 + write32 IMX_MAX_BASE + MAX_MPR1, 0x43210 + write32 IMX_MAX_BASE + MAX_MPR2, 0x43210 + write32 IMX_MAX_BASE + MAX_MPR3, 0x43210 + write32 IMX_MAX_BASE + MAX_MPR4, 0x43210 + + write32 IMX_MAX_BASE + MAX_SGPCR0, 0x10 + write32 IMX_MAX_BASE + MAX_SGPCR1, 0x10 + write32 IMX_MAX_BASE + MAX_SGPCR2, 0x10 + write32 IMX_MAX_BASE + MAX_SGPCR3, 0x10 + write32 IMX_MAX_BASE + MAX_SGPCR4, 0x10 + + write32 IMX_MAX_BASE + MAX_MGPCR0, 0x0 + write32 IMX_MAX_BASE + MAX_MGPCR1, 0x0 + write32 IMX_MAX_BASE + MAX_MGPCR2, 0x0 + write32 IMX_MAX_BASE + MAX_MGPCR3, 0x0 + write32 IMX_MAX_BASE + MAX_MGPCR4, 0x0 +.endm + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARM_ARCH_MACRO_H__ */ diff --git a/arch/arm/include/asm/arch-mx27/asm-offsets.h b/arch/arm/include/asm/arch-mx27/asm-offsets.h deleted file mode 100644 index 497afe5..0000000 --- a/arch/arm/include/asm/arch-mx27/asm-offsets.h +++ /dev/null @@ -1,16 +0,0 @@ -#define AIPI1_PSR0 0x10000000 -#define AIPI1_PSR1 0x10000004 -#define AIPI2_PSR0 0x10020000 -#define AIPI2_PSR1 0x10020004 -#define CSCR 0x10027000 -#define MPCTL0 0x10027004 -#define SPCTL0 0x1002700c -#define PCDR0 0x10027018 -#define PCDR1 0x1002701c -#define PCCR0 0x10027020 -#define PCCR1 0x10027024 -#define ESDCTL0_ROF 0x00 -#define ESDCFG0_ROF 0x04 -#define ESDCTL1_ROF 0x08 -#define ESDCFG1_ROF 0x0C -#define ESDMISC_ROF 0x10 diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index 8f40aa7..b4b2fe6 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -29,7 +29,7 @@ extern void imx_gpio_mode (int gpio_mode); #ifdef CONFIG_MXC_UART -extern void mx27_uart_init_pins(void); +extern void mx27_uart1_init_pins(void); #endif /* CONFIG_MXC_UART */ #ifdef CONFIG_FEC_MXC diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h index 9f7ae80..fb035c4 100644 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ b/arch/arm/include/asm/arch-mx31/clock.h @@ -24,8 +24,15 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H -extern u32 mx31_get_ipg_clk(void); -#define imx_get_uartclk mx31_get_ipg_clk +enum mxc_clock { + MXC_ARM_CLK, + MXC_IPG_CLK, + MXC_CSPI_CLK, + MXC_UART_CLK, +}; + +unsigned int mxc_get_clock(enum mxc_clock clk); +extern u32 imx_get_uartclk(); extern void mx31_gpio_mux(unsigned long mode); extern void mx31_set_pad(enum iomux_pins pin, u32 config); diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 306f966..3c8d607 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -746,7 +746,7 @@ enum iomux_pins { #define IRAM_SIZE (16 * 1024) #define MX31_AIPS1_BASE_ADDR 0x43f00000 -#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) +#define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000) /* USB portsc */ /* values for portsc field */ diff --git a/arch/arm/include/asm/arch-mx5/asm-offsets.h b/arch/arm/include/asm/arch-mx5/asm-offsets.h deleted file mode 100644 index 793f69c..0000000 --- a/arch/arm/include/asm/arch-mx5/asm-offsets.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * needed for arch/arm/cpu/armv7/mx51/lowlevel_init.S - * - * These should be auto-generated - */ -/* CCM */ -#define CLKCTL_CCR 0x00 -#define CLKCTL_CCDR 0x04 -#define CLKCTL_CSR 0x08 -#define CLKCTL_CCSR 0x0C -#define CLKCTL_CACRR 0x10 -#define CLKCTL_CBCDR 0x14 -#define CLKCTL_CBCMR 0x18 -#define CLKCTL_CSCMR1 0x1C -#define CLKCTL_CSCMR2 0x20 -#define CLKCTL_CSCDR1 0x24 -#define CLKCTL_CS1CDR 0x28 -#define CLKCTL_CS2CDR 0x2C -#define CLKCTL_CDCDR 0x30 -#define CLKCTL_CHSCCDR 0x34 -#define CLKCTL_CSCDR2 0x38 -#define CLKCTL_CSCDR3 0x3C -#define CLKCTL_CSCDR4 0x40 -#define CLKCTL_CWDR 0x44 -#define CLKCTL_CDHIPR 0x48 -#define CLKCTL_CDCR 0x4C -#define CLKCTL_CTOR 0x50 -#define CLKCTL_CLPCR 0x54 -#define CLKCTL_CISR 0x58 -#define CLKCTL_CIMR 0x5C -#define CLKCTL_CCOSR 0x60 -#define CLKCTL_CGPR 0x64 -#define CLKCTL_CCGR0 0x68 -#define CLKCTL_CCGR1 0x6C -#define CLKCTL_CCGR2 0x70 -#define CLKCTL_CCGR3 0x74 -#define CLKCTL_CCGR4 0x78 -#define CLKCTL_CCGR5 0x7C -#define CLKCTL_CCGR6 0x80 -#if defined(CONFIG_MX53) -#define CLKCTL_CCGR7 0x84 -#define CLKCTL_CMEOR 0x88 -#elif defined(CONFIG_MX51) -#define CLKCTL_CMEOR 0x84 -#endif - -/* DPLL */ -#define PLL_DP_CTL 0x00 -#define PLL_DP_CONFIG 0x04 -#define PLL_DP_OP 0x08 -#define PLL_DP_MFD 0x0C -#define PLL_DP_MFN 0x10 -#define PLL_DP_HFS_OP 0x1C -#define PLL_DP_HFS_MFD 0x20 -#define PLL_DP_HFS_MFN 0x24 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 9589a62..e83ca29 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -317,9 +317,27 @@ struct clkctl { u32 ccgr4; u32 ccgr5; u32 ccgr6; +#if defined(CONFIG_MX53) + u32 ccgr7; +#endif u32 cmeor; }; +/* DPLL registers */ +struct dpll { + u32 dp_ctl; + u32 dp_config; + u32 dp_op; + u32 dp_mfd; + u32 dp_mfn; + u32 dp_mfn_minus; + u32 dp_mfn_plus; + u32 dp_hfs_op; + u32 dp_hfs_mfd; + u32 dp_hfs_mfn; + u32 dp_mfn_togc; + u32 dp_destat; +}; /* WEIM registers */ struct weim { u32 cs0gcr1; diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index 270f163..879e20e 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -106,6 +106,11 @@ static inline int test_bit(int nr, const void * addr) return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7)); } +static inline int __ilog2(unsigned int x) +{ + return generic_fls(x) - 1; +} + /* * ffz = Find First Zero in word. Undefined if no zero exists, * so code should check against ~0UL first.. diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index fc52a26..6bbedf4 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -281,6 +281,10 @@ void board_init_f (ulong bootflag) gd->mon_len = _bss_end_ofs; +#ifdef CONFIG_MACH_TYPE + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ +#endif + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { if ((*init_fnc_ptr)() != 0) { hang (); diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 85ebcc9..767bc52 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -79,7 +79,7 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P1016, P1016_E, 1), CPU_TYPE_ENTRY(P1016, P1016, 1), CPU_TYPE_ENTRY(P1017, P1017, 1), - CPU_TYPE_ENTRY(P1017, P1017, 1), + CPU_TYPE_ENTRY(P1017, P1017_E, 1), CPU_TYPE_ENTRY(P1020, P1020, 2), CPU_TYPE_ENTRY(P1020, P1020_E, 2), CPU_TYPE_ENTRY(P1021, P1021, 2), diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c index a918b04..856d798 100644 --- a/board/BuS/eb_cpux9k2/cpux9k2.c +++ b/board/BuS/eb_cpux9k2/cpux9k2.c @@ -141,7 +141,7 @@ void reset_phy(void) int dram_init(void) { - gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/armadillo/flash.c b/board/armadillo/flash.c index cdbbfd0..cf7d7f6 100644 --- a/board/armadillo/flash.c +++ b/board/armadillo/flash.c @@ -162,6 +162,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) int rc = ERR_OK; unsigned long base; unsigned long addr; + ulong start; if ((info->flash_id & FLASH_VENDMASK) != (FUJ_MANUFACT & FLASH_VENDMASK)) { @@ -192,7 +193,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { /* ARM simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ @@ -232,6 +233,7 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) { int flag; unsigned long base; + ulong start; /* Check if Flash is (sufficiently) erased */ @@ -250,7 +252,7 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) flag = disable_interrupts (); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); base = dest & 0xF0000000; FL_WORD (base + (0x555 << 1)) = 0xAA; diff --git a/board/atmel/at91rm9200dk/flash.c b/board/atmel/at91rm9200dk/flash.c index 902c3c4..be22743 100644 --- a/board/atmel/at91rm9200dk/flash.c +++ b/board/atmel/at91rm9200dk/flash.c @@ -285,6 +285,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) int iflag, cflag, prot, sect; int rc = ERR_OK; int chip1; + ulong start; /* first look for protection bits */ @@ -325,7 +326,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ volatile u16 *addr = (volatile u16 *) (info->start[sect]); @@ -345,7 +346,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) result = *addr; /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; chip1 = TMO; break; @@ -400,6 +401,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) int rc = ERR_OK; int cflag, iflag; int chip1; + ulong start; /* * Check if Flash is (sufficiently) erased @@ -425,7 +427,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait until flash is ready */ chip1 = 0; @@ -433,7 +435,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) result = *addr; /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { chip1 = ERR | TMO; break; } diff --git a/board/atmel/at91rm9200ek/at91rm9200ek.c b/board/atmel/at91rm9200ek/at91rm9200ek.c index ec0daba..2b4d845 100644 --- a/board/atmel/at91rm9200ek/at91rm9200ek.c +++ b/board/atmel/at91rm9200ek/at91rm9200ek.c @@ -64,7 +64,7 @@ int board_early_init_f(void) int dram_init (void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/cerf250/flash.c b/board/cerf250/flash.c index a4b201e..e1e7807 100644 --- a/board/cerf250/flash.c +++ b/board/cerf250/flash.c @@ -221,7 +221,7 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) int flash_erase (flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -254,9 +254,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - start = get_timer (0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -269,14 +266,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); *addr = (FPW) 0x00500050; /* clear status register */ *addr = (FPW) 0x00200020; /* erase setup */ *addr = (FPW) 0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -393,6 +390,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) FPWV *addr = (FPWV *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -406,11 +404,11 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c index 2e66872..d6fd519 100644 --- a/board/cm4008/flash.c +++ b/board/cm4008/flash.c @@ -209,6 +209,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) int flag, prot, sect; ulong type; int rcode = 0; + ulong start; if ((s_first < 0) || (s_first > s_last)) { if (info->flash_id == FLASH_UNKNOWN) { @@ -250,7 +251,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); addr = (volatile unsigned char *) (info->start[sect]); *addr = 0x50; /* clear status register */ @@ -258,7 +259,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr = 0xD0; /* erase confirm */ while (((status = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = 0xB0; /* suspend erase */ @@ -370,6 +371,7 @@ static int write_data (flash_info_t * info, ulong dest, unsigned char data) volatile unsigned char *addr = (volatile unsigned char *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -384,11 +386,11 @@ static int write_data (flash_info_t * info, ulong dest, unsigned char data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = 0xFF; /* restore read mode */ return (1); } diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c index 2e66872..d6fd519 100644 --- a/board/cm41xx/flash.c +++ b/board/cm41xx/flash.c @@ -209,6 +209,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) int flag, prot, sect; ulong type; int rcode = 0; + ulong start; if ((s_first < 0) || (s_first > s_last)) { if (info->flash_id == FLASH_UNKNOWN) { @@ -250,7 +251,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); addr = (volatile unsigned char *) (info->start[sect]); *addr = 0x50; /* clear status register */ @@ -258,7 +259,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr = 0xD0; /* erase confirm */ while (((status = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = 0xB0; /* suspend erase */ @@ -370,6 +371,7 @@ static int write_data (flash_info_t * info, ulong dest, unsigned char data) volatile unsigned char *addr = (volatile unsigned char *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -384,11 +386,11 @@ static int write_data (flash_info_t * info, ulong dest, unsigned char data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = 0xFF; /* restore read mode */ return (1); } diff --git a/board/cmc_pu2/flash.c b/board/cmc_pu2/flash.c index d832e62..d10faab 100644 --- a/board/cmc_pu2/flash.c +++ b/board/cmc_pu2/flash.c @@ -264,7 +264,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) { vu_short *addr = (vu_short *)(info->start[0]); int flag, prot, sect, ssect, l_sect; - ulong now, last; + ulong now, last, start; debug ("flash_erase: first: %d last: %d\n", s_first, s_last); @@ -335,11 +335,11 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) if (l_sect < 0) goto DONE; - reset_timer_masked (); + start = get_timer(0); last = 0; addr = (vu_short *)(info->start[l_sect]); while ((addr[0] & 0x0080) != 0x0080) { - if ((now = get_timer_masked ()) > CONFIG_SYS_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -434,6 +434,7 @@ static int write_word_amd (flash_info_t *info, vu_short *dest, ushort data) { int flag; vu_short *base; /* first address in flash bank */ + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*dest & data) != data) { @@ -455,11 +456,11 @@ static int write_word_amd (flash_info_t *info, vu_short *dest, ushort data) if (flag) enable_interrupts(); - reset_timer_masked (); + start = get_timer(0); /* data polling for D7 */ while ((*dest & 0x0080) != (data & 0x0080)) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = 0x00F0; /* reset bank */ return (1); } diff --git a/board/cradle/flash.c b/board/cradle/flash.c index b5635fb..1601782 100644 --- a/board/cradle/flash.c +++ b/board/cradle/flash.c @@ -136,6 +136,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) { int flag, prot, sect; int rc = ERR_OK; + ulong start; if (info->flash_id == FLASH_UNKNOWN) return ERR_UNKNOWN_FLASH_TYPE; @@ -173,7 +174,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ vu_short *addr = (vu_short *) (info->start[sect]); @@ -182,7 +183,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr = 0xD0; /* erase confirm */ while ((*addr & 0x80) != 0x80) { - if (get_timer_masked () > + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = 0xB0; /* suspend erase */ *addr = 0xFF; /* reset to read mode */ @@ -221,6 +222,7 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) vu_short *addr = (vu_short *) dest, val; int rc = ERR_OK; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ @@ -246,11 +248,11 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((val = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { rc = ERR_TIMOUT; /* suspend program command */ *addr = 0xB0; diff --git a/board/csb226/flash.c b/board/csb226/flash.c index 02ded1c..e103470 100644 --- a/board/csb226/flash.c +++ b/board/csb226/flash.c @@ -141,6 +141,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; int rc = ERR_OK; + ulong start; if (info->flash_id == FLASH_UNKNOWN) return ERR_UNKNOWN_FLASH_TYPE; @@ -175,7 +176,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) printf("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ u32 * volatile addr = (u32 * volatile)(info->start[sect]); @@ -189,7 +190,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) *addr = 0x00D000D0; /* erase confirm */ while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = 0x00B000B0; /* suspend erase*/ *addr = 0x00FF00FF; /* read mode */ rc = ERR_TIMOUT; @@ -221,6 +222,7 @@ static int write_long (flash_info_t *info, ulong dest, ulong data) u32 * volatile addr = (u32 * volatile)dest, val; int rc = ERR_OK; int flag; + ulong start; /* read array command - just for the case... */ *addr = 0x00FF00FF; @@ -247,11 +249,11 @@ static int write_long (flash_info_t *info, ulong dest, ulong data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); /* wait while polling the status register */ while(((val = *addr) & 0x00800080) != 0x00800080) { - if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { rc = ERR_TIMOUT; /* suspend program command */ *addr = 0x00B000B0; diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index b1238d5..ec22627 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -44,7 +44,7 @@ void hw_watchdog_reset(void) int dram_init (void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c index 2bfdf23..6103339 100644 --- a/board/davinci/common/misc.c +++ b/board/davinci/common/misc.c @@ -38,7 +38,7 @@ int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (volatile void *)CONFIG_SYS_SDRAM_BASE, + (void *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); return 0; } diff --git a/board/dnp1110/flash.c b/board/dnp1110/flash.c index c81abc5..53f89ee 100644 --- a/board/dnp1110/flash.c +++ b/board/dnp1110/flash.c @@ -212,7 +212,7 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) int flash_erase (flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -245,9 +245,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - start = get_timer (0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -260,14 +257,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); *addr = (FPW)0x00500050; /* clear status register */ *addr = (FPW)0x00200020; /* erase setup */ *addr = (FPW)0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW)0x00B000B0; /* suspend erase */ *addr = (FPW)0x00FF00FF; /* reset to read mode */ @@ -385,6 +382,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) FPWV *addr = (FPWV *)dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -398,11 +396,11 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (start = get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW)0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c index 16be532..4b36918 100644 --- a/board/efikamx/efikamx.c +++ b/board/efikamx/efikamx.c @@ -113,7 +113,7 @@ u32 get_board_rev(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/ep7312/flash.c b/board/ep7312/flash.c index 0c2b3ae..2ed9c9a 100644 --- a/board/ep7312/flash.c +++ b/board/ep7312/flash.c @@ -119,6 +119,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) { int flag, prot, sect; int rc = ERR_OK; + ulong start; if (info->flash_id == FLASH_UNKNOWN) return ERR_UNKNOWN_FLASH_TYPE; @@ -156,7 +157,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ vu_short *addr = (vu_short *) (info->start[sect]); @@ -165,7 +166,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr = 0xD0; /* erase confirm */ while ((*addr & 0x80) != 0x80) { - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = 0xB0; /* suspend erase */ *addr = 0xFF; /* reset to read mode */ rc = ERR_TIMOUT; @@ -203,6 +204,7 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) vu_short *addr = (vu_short *) dest, val; int rc = ERR_OK; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ @@ -228,11 +230,11 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((val = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { rc = ERR_TIMOUT; /* suspend program command */ *addr = 0xB0; diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c index 0959c5c..402f19f 100644 --- a/board/eukrea/cpu9260/cpu9260.c +++ b/board/eukrea/cpu9260/cpu9260.c @@ -174,7 +174,7 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/eukrea/cpuat91/cpuat91.c b/board/eukrea/cpuat91/cpuat91.c index 5d05414..f654f87 100644 --- a/board/eukrea/cpuat91/cpuat91.c +++ b/board/eukrea/cpuat91/cpuat91.c @@ -63,7 +63,7 @@ int board_early_init_f(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c index 9bf9c18..7637c92 100644 --- a/board/freescale/mx31ads/mx31ads.c +++ b/board/freescale/mx31ads/mx31ads.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1, + gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index 08addd2..f6e190a 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -42,7 +42,7 @@ void hw_watchdog_reset(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index e2d3d74..fd7342f 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -53,7 +53,7 @@ u32 get_board_rev(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index b51d209..134603a 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -46,8 +46,8 @@ int dram_init(void) { u32 size1, size2; - size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); gd->ram_size = size1 + size2; diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index a89aa25..88095dc 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -46,7 +46,7 @@ u32 get_board_rev(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index d032428..18b388e 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -47,8 +47,8 @@ int dram_init(void) { u32 size1, size2; - size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); gd->ram_size = size1 + size2; diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c index f3c433f..21b5d14 100644 --- a/board/freescale/mx53smd/mx53smd.c +++ b/board/freescale/mx53smd/mx53smd.c @@ -44,8 +44,8 @@ int dram_init(void) { u32 size1, size2; - size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); gd->ram_size = size1 + size2; diff --git a/board/freescale/p2041rdb/Makefile b/board/freescale/p2041rdb/Makefile new file mode 100644 index 0000000..65f348f --- /dev/null +++ b/board/freescale/p2041rdb/Makefile @@ -0,0 +1,56 @@ +# +# Copyright 2011 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += cpld.o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o +COBJS-$(CONFIG_PCI) += pci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c new file mode 100644 index 0000000..8e1f46e --- /dev/null +++ b/board/freescale/p2041rdb/cpld.c @@ -0,0 +1,171 @@ +/** + * Copyright 2011 Freescale Semiconductor + * Author: Mingkai Hu <Mingkai.hu@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CPLD_BASE - The virtual address of the base of the CPLD register map + * + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#include "cpld.h" + +static u8 __cpld_read(unsigned int reg) +{ + void *p = (void *)CPLD_BASE; + + return in_8(p + reg); +} +u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read"))); + +static void __cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CPLD_BASE; + + out_8(p + reg, value); +} +void cpld_write(unsigned int reg, u8 value) + __attribute__((weak, alias("__cpld_write"))); + +/* + * Reset the board. This honors the por_cfg registers. + */ +void __cpld_reset(void) +{ + CPLD_WRITE(system_rst, 1); +} +void cpld_reset(void) __attribute__((weak, alias("__cpld_reset"))); + +/** + * Set the boot bank to the alternate bank + */ +void __cpld_set_altbank(void) +{ + CPLD_WRITE(fbank_sel, 1); +} +void cpld_set_altbank(void) + __attribute__((weak, alias("__cpld_set_altbank"))); + +/** + * Set the boot bank to the default bank + */ +void __cpld_clear_altbank(void) +{ + CPLD_WRITE(fbank_sel, 0); +} +void cpld_clear_altbank(void) + __attribute__((weak, alias("__cpld_clear_altbank"))); + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); + printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver)); + printf("system_rst = 0x%02x\n", CPLD_READ(system_rst)); + printf("wd_cfg = 0x%02x\n", CPLD_READ(wd_cfg)); + printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on)); + printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg)); + printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe)); + printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel)); + printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk)); + printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk)); + printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel)); + printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux)); + printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2))); + putc('\n'); +} +#endif + +int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + unsigned int i; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_clear_altbank(); + + cpld_reset(); + } else if (strcmp(argv[1], "watchdog") == 0) { + static char *period[8] = {"1ms", "10ms", "30ms", "disable", + "100ms", "1s", "10s", "60s"}; + for (i = 0; i < ARRAY_SIZE(period); i++) { + if (strcmp(argv[2], period[i]) == 0) + CPLD_WRITE(wd_cfg, i); + } + } else if (strcmp(argv[1], "lane_mux") == 0) { + u32 lane = simple_strtoul(argv[2], NULL, 16); + u8 val = (u8)simple_strtoul(argv[3], NULL, 16); + u8 reg = CPLD_READ(serdes_mux); + + switch (lane) { + case 0x6: + reg &= ~SERDES_MUX_LANE_6_MASK; + reg |= val << SERDES_MUX_LANE_6_SHIFT; + break; + case 0xa: + reg &= ~SERDES_MUX_LANE_A_MASK; + reg |= val << SERDES_MUX_LANE_A_SHIFT; + break; + case 0xc: + reg &= ~SERDES_MUX_LANE_C_MASK; + reg |= val << SERDES_MUX_LANE_C_SHIFT; + break; + case 0xd: + reg &= ~SERDES_MUX_LANE_D_MASK; + reg |= val << SERDES_MUX_LANE_D_SHIFT; + break; + default: + printf("Invalid value\n"); + break; + } + + CPLD_WRITE(serdes_mux, reg); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd, + "Reset the board or pin mulexing selection using the CPLD sequencer", + "reset - hard reset to default bank\n" + "cpld_cmd reset altbank - reset to alternate bank\n" + "cpld_cmd watchdog <watchdog_period> - set the watchdog period\n" + " period: 1ms 10ms 30ms 100ms 1s 10s 60s disable\n" + "cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n" + " lane 6: 0 -> slot1 (Default)\n" + " 1 -> SGMII\n" + " lane a: 0 -> slot2 (Default)\n" + " 1 -> AURORA\n" + " lane c: 0 -> slot2 (Default)\n" + " 1 -> SATA0\n" + " lane d: 0 -> slot2 (Default)\n" + " 1 -> SATA1\n" +#ifdef DEBUG + "cpld_cmd dump - display the CPLD registers\n" +#endif + ); diff --git a/board/freescale/p2041rdb/cpld.h b/board/freescale/p2041rdb/cpld.h new file mode 100644 index 0000000..3b24cb0 --- /dev/null +++ b/board/freescale/p2041rdb/cpld.h @@ -0,0 +1,53 @@ +/** + * Copyright 2011 Freescale Semiconductor + * Author: Mingkai Hu <Mingkai.hu@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +typedef struct cpld_data { + u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ + u8 pcba_ver; /* 0x2 - PCBA Revision Register */ + u8 system_rst; /* 0x3 - system reset register */ + u8 wd_cfg; /* 0x4 - Watchdog Period Setting Register */ + u8 sw_ctl_on; /* 0x5 - Switch Control Enable Register */ + u8 por_cfg; /* 0x6 - POR Control Register */ + u8 switch_strobe; /* 0x7 - Multiplexed pin Select Register */ + u8 jtag_sel; /* 0x8 - JTAG or AURORA Selection */ + u8 sdbank1_clk; /* 0x9 - SerDes Bank1 Reference clock */ + u8 sdbank2_clk; /* 0xa - SerDes Bank2 Reference clock */ + u8 fbank_sel; /* 0xb - Flash bank selection */ + u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */ + u8 sw[1]; /* 0xd - SW2 Status */ +} __attribute__ ((packed)) cpld_data_t; + +#define SERDES_MUX_LANE_6_MASK 0x2 +#define SERDES_MUX_LANE_6_SHIFT 1 +#define SERDES_MUX_LANE_A_MASK 0x1 +#define SERDES_MUX_LANE_A_SHIFT 0 +#define SERDES_MUX_LANE_C_MASK 0x4 +#define SERDES_MUX_LANE_C_SHIFT 2 +#define SERDES_MUX_LANE_D_MASK 0x8 +#define SERDES_MUX_LANE_D_SHIFT 3 + +/* Pointer to the CPLD register set */ +#define cpld ((cpld_data_t *)CPLD_BASE) + +/* The CPLD SW register that corresponds to board switch X, where x >= 1 */ +#define CPLD_SW(x) (cpld->sw[(x) - 2]) + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg)) +#define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value) diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c new file mode 100644 index 0000000..46de910 --- /dev/null +++ b/board/freescale/p2041rdb/ddr.c @@ -0,0 +1,115 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <i2c.h> +#include <hwconfig.h> +#include <asm/mmu.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> +#include <asm/fsl_law.h> + +typedef struct { + u32 datarate_mhz_low; + u32 datarate_mhz_high; + u32 n_ranks; + u32 clk_adjust; + u32 wrlvl_start; + u32 cpo; + u32 write_data_delay; + u32 force_2T; +} board_specific_parameters_t; + +/* + * ranges for parameters: + * wr_data_delay = 0-6 + * clk adjust = 0-8 + * cpo 2-0x1E (30) + */ +const board_specific_parameters_t board_specific_parameters[] = { + /* + * memory controller 0 + * lo| hi| num| clk| wrlvl | cpo |wrdata|2T + * mhz| mhz|ranks|adjst| start | delay| + */ + { 1017, 1116, 2, 4, 6, 0xff, 2, 0}, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const board_specific_parameters_t *pbsp = + &board_specific_parameters[0]; + u32 num_params = ARRAY_SIZE(board_specific_parameters); + u32 i; + ulong ddr_freq; + + /* + * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + for (i = 0; i < num_params; i++) { + if (ddr_freq >= pbsp->datarate_mhz_low && + ddr_freq <= pbsp->datarate_mhz_high && + pdimm[0].n_ranks == pbsp->n_ranks) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->twoT_en = pbsp->force_2T; + break; + } + pbsp++; + } + + if (i == num_params) { + printf("Warning: board specific timing not found " + "for data rate %lu MT/s!\n", ddr_freq); + } + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* Write leveling override */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* Rtt and Rtt_WR override */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 60 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = 0; + + puts("Initializing...."); + + if (fsl_use_spd()) { + puts("using SPD\n"); + dram_size = fsl_ddr_sdram(); + } else { + puts("no SPD and fixed parameters\n"); + return dram_size; + } + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} diff --git a/board/freescale/p2041rdb/law.c b/board/freescale/p2041rdb/law.c new file mode 100644 index 0000000..127a478 --- /dev/null +++ b/board/freescale/p2041rdb/law.c @@ -0,0 +1,37 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), + SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c new file mode 100644 index 0000000..52269d3 --- /dev/null +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -0,0 +1,203 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <linux/compiler.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +extern void pci_of_setup(void *blob, bd_t *bd); + +#include "cpld.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + u8 sw; + struct cpu_type *cpu = gd->cpu; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + unsigned int i; + + printf("Board: %sRDB, ", cpu->name); + printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver), + CPLD_READ(cpld_ver_sub)); + + sw = CPLD_READ(fbank_sel); + printf("vBank: %d\n", sw & 0x1); + +#ifdef CONFIG_PHYS_64BIT + puts("36-bit Addressing\n"); +#endif + + /* + * Display the RCW, so that no one gets confused as to what RCW + * we're actually using for this boot. + */ + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + u32 rcw = in_be32(&gur->rcwsr[i]); + + if ((i % 4) == 0) + printf("\n %08x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); + + /* + * Display the actual SERDES reference clocks as configured by the + * dip switches on the board. Note that the SWx registers could + * technically be set to force the reference clocks to match the + * values that the SERDES expects (or vice versa). For now, however, + * we just display both values and hope the user notices when they + * don't match. + */ + puts("SERDES Reference Clocks: "); + sw = in_8(&CPLD_SW(2)) >> 2; + for (i = 0; i < 2; i++) { + static const char * const freq[] = {"0", "100", "125"}; + unsigned int clock = (sw >> (2 * i)) & 3; + + printf("Bank%u=%sMhz ", i+1, freq[clock]); + } + puts("\n"); + + return 0; +} + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */ + setbits_be32(&gur->ddrclkdr, 0x000f000f); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); + setup_portals(); + + return 0; +} + +static const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + default: + return "150"; + } +} + +#define NUM_SRDS_BANKS 2 + +int misc_init_r(void) +{ + serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + u32 actual[NUM_SRDS_BANKS]; + unsigned int i; + u8 sw; + + sw = in_8(&CPLD_SW(2)) >> 2; + for (i = 0; i < NUM_SRDS_BANKS; i++) { + unsigned int clock = (sw >> (2 * i)) & 3; + switch (clock) { + case 1: + actual[i] = SRDS_PLLCR0_RFCK_SEL_100; + break; + case 2: + actual[i] = SRDS_PLLCR0_RFCK_SEL_125; + break; + default: + printf("Warning: SDREFCLK%u switch setting of '11' is " + "unsupported\n", i + 1); + break; + } + } + + for (i = 0; i < NUM_SRDS_BANKS; i++) { + u32 expected = in_be32(®s->bank[i].pllcr0); + expected &= SRDS_PLLCR0_RFCK_SEL_MASK; + if (expected != actual[i]) { + printf("Warning: SERDES bank %u expects reference clock" + " %sMHz, but actual is %sMHz\n", i + 1, + serdes_clock_to_string(expected), + serdes_clock_to_string(actual[i])); + } + } + + return 0; +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); +} diff --git a/board/freescale/p2041rdb/pci.c b/board/freescale/p2041rdb/pci.c new file mode 100644 index 0000000..1ab4cdf --- /dev/null +++ b/board/freescale/p2041rdb/pci.c @@ -0,0 +1,39 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/fsl_pci.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/fsl_serdes.h> + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/p2041rdb/tlb.c b/board/freescale/p2041rdb/tlb.c new file mode 100644 index 0000000..43f28ed --- /dev/null +++ b/board/freescale/p2041rdb/tlb.c @@ -0,0 +1,119 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_1M, 1), +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_4M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/gcplus/flash.c b/board/gcplus/flash.c index 8511582..ab567e8 100644 --- a/board/gcplus/flash.c +++ b/board/gcplus/flash.c @@ -225,7 +225,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -258,9 +258,6 @@ flash_erase(flash_info_t * info, int s_first, int s_last) printf("\n"); } - start = get_timer(0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -273,7 +270,7 @@ flash_erase(flash_info_t * info, int s_first, int s_last) printf("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); *addr = (FPW) 0x00500050; /* clear status register */ *addr = (FPW) 0x00200020; /* erase setup */ @@ -282,7 +279,7 @@ flash_erase(flash_info_t * info, int s_first, int s_last) while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -401,6 +398,7 @@ write_data(flash_info_t * info, ulong dest, FPW data) FPWV *addr = (FPWV *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -414,11 +412,11 @@ write_data(flash_info_t * info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/impa7/flash.c b/board/impa7/flash.c index d0c5880..6eae428 100644 --- a/board/impa7/flash.c +++ b/board/impa7/flash.c @@ -128,6 +128,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) { int flag, prot, sect; int rc = ERR_OK; + ulong start; if (info->flash_id == FLASH_UNKNOWN) return ERR_UNKNOWN_FLASH_TYPE; @@ -165,7 +166,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ vu_long *addr = (vu_long *) (info->start[sect]); @@ -174,7 +175,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr = 0x00D000D0; /* erase confirm */ while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer_masked () > + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = 0x00B000B0; /* suspend erase */ *addr = 0x00FF00FF; /* reset to read mode */ @@ -211,6 +212,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) ulong barf; int rc = ERR_OK; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ @@ -236,14 +238,14 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* read status register command */ *addr = 0x00700070; /* wait while polling the status register */ while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { rc = ERR_TIMOUT; /* suspend program command */ *addr = 0x00B000B0; diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c index ca7d6e2..773900e 100644 --- a/board/imx31_phycore/imx31_phycore.c +++ b/board/imx31_phycore/imx31_phycore.c @@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1, + gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/innokom/flash.c b/board/innokom/flash.c index 8c95341..ed4b987 100644 --- a/board/innokom/flash.c +++ b/board/innokom/flash.c @@ -182,6 +182,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; int rc = ERR_OK; + ulong start; if (info->flash_id == FLASH_UNKNOWN) return ERR_UNKNOWN_FLASH_TYPE; @@ -218,7 +219,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) PRINTK("\n"); /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ u16 * volatile addr = (u16 * volatile)(info->start[sect]); @@ -235,7 +236,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) while ((*addr & 0x0080) != 0x0080) { PRINTK("."); - if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = 0x00B0; /* suspend erase*/ *addr = 0x00FF; /* read mode */ rc = ERR_TIMOUT; @@ -279,6 +280,7 @@ static int write_word (flash_info_t *info, ulong dest, ushort data) volatile u16 *addr = (u16 *)dest, val; int rc = ERR_OK; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) return ERR_NOT_ERASED; @@ -302,11 +304,11 @@ static int write_word (flash_info_t *info, ulong dest, ushort data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); /* wait while polling the status register */ while(((val = *addr) & 0x80) != 0x80) { - if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { rc = ERR_TIMOUT; *addr = 0xB0; /* suspend program command */ goto outahere; diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c index 269858c..25b99e8 100644 --- a/board/karo/tx25/tx25.c +++ b/board/karo/tx25/tx25.c @@ -70,18 +70,18 @@ void tx25_fec_init(void) writel(0x0, &padctl->pad_d11); /* drop PHY power and assert reset (low) */ - val = readl(&gpio4->dr) & ~((1 << 7) | (1 << 9)); - writel(val, &gpio4->dr); - val = readl(&gpio4->dir) | (1 << 7) | (1 << 9); - writel(val, &gpio4->dir); + val = readl(&gpio4->gpio_dr) & ~((1 << 7) | (1 << 9)); + writel(val, &gpio4->gpio_dr); + val = readl(&gpio4->gpio_dir) | (1 << 7) | (1 << 9); + writel(val, &gpio4->gpio_dir); mdelay(5); debug("resetting phy\n"); /* turn on PHY power leaving reset asserted */ - val = readl(&gpio4->dr) | 1 << 9; - writel(val, &gpio4->dr); + val = readl(&gpio4->gpio_dr) | 1 << 9; + writel(val, &gpio4->gpio_dr); mdelay(10); @@ -111,19 +111,19 @@ void tx25_fec_init(void) /* * set each to 1 and make each an output */ - val = readl(&gpio3->dr) | (1 << 10) | (1 << 11) | (1 << 12); - writel(val, &gpio3->dr); - val = readl(&gpio3->dir) | (1 << 10) | (1 << 11) | (1 << 12); - writel(val, &gpio3->dir); + val = readl(&gpio3->gpio_dr) | (1 << 10) | (1 << 11) | (1 << 12); + writel(val, &gpio3->gpio_dr); + val = readl(&gpio3->gpio_dir) | (1 << 10) | (1 << 11) | (1 << 12); + writel(val, &gpio3->gpio_dir); mdelay(22); /* this value came from RedBoot */ /* * deassert PHY reset */ - val = readl(&gpio4->dr) | 1 << 7; - writel(val, &gpio4->dr); - writel(val, &gpio4->dr); + val = readl(&gpio4->gpio_dr) | 1 << 7; + writel(val, &gpio4->gpio_dr); + writel(val, &gpio4->gpio_dr); mdelay(5); @@ -160,7 +160,7 @@ int board_late_init(void) int dram_init (void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1, + gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); return 0; } @@ -168,11 +168,11 @@ int dram_init (void) void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1, + gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); #if CONFIG_NR_DRAM_BANKS > 1 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2, + gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); #else diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 5da856f..a8f2b23 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -321,7 +321,7 @@ int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ /* Fix this */ - gd->ram_size = get_ram_size((volatile void *)kw_sdram_bar(0), + gd->ram_size = get_ram_size((void *)kw_sdram_bar(0), kw_sdram_bs(0)); return 0; } diff --git a/board/lart/flash.c b/board/lart/flash.c index 29a331e..408c884 100644 --- a/board/lart/flash.c +++ b/board/lart/flash.c @@ -250,6 +250,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) ulong result; int iflag, cflag, prot, sect; int rc = ERR_OK; + ulong start; /* first look for protection bits */ @@ -291,7 +292,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ @@ -305,7 +306,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) do { /* check timeout */ - if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = PUZZLE_TO_FLASH(CMD_SUSPEND); result = BIT_TIMEOUT; @@ -354,6 +355,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) ulong result; int rc = ERR_OK; int cflag, iflag; + ulong start; /* Check if Flash is (sufficiently) erased */ @@ -377,13 +379,13 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); /* wait until flash is ready */ do { /* check timeout */ - if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = PUZZLE_TO_FLASH(CMD_SUSPEND); result = BIT_TIMEOUT; diff --git a/board/logicpd/imx27lite/imx27lite.c b/board/logicpd/imx27lite/imx27lite.c index 6eb5cc2..2b273ac 100644 --- a/board/logicpd/imx27lite/imx27lite.c +++ b/board/logicpd/imx27lite/imx27lite.c @@ -38,7 +38,7 @@ int board_init (void) gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; #ifdef CONFIG_MXC_UART - mx27_uart_init_pins(); + mx27_uart1_init_pins(); #endif #ifdef CONFIG_FEC_MXC mx27_fec_init_pins(); @@ -67,7 +67,7 @@ int board_init (void) int dram_init (void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } @@ -75,11 +75,11 @@ int dram_init (void) void dram_init_banksize(void) { gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + gd->bd->bi_dram[0].size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); #if CONFIG_NR_DRAM_BANKS > 1 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2, + gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); #endif } diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c index bf635c3..09cc9c5 100644 --- a/board/logicpd/imx31_litekit/imx31_litekit.c +++ b/board/logicpd/imx31_litekit/imx31_litekit.c @@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1, + gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/lpd7a40x/flash.c b/board/lpd7a40x/flash.c index a3ba75b..f5c0713 100644 --- a/board/lpd7a40x/flash.c +++ b/board/lpd7a40x/flash.c @@ -229,6 +229,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) ulong result, result1; int iflag, prot, sect; int rc = ERR_OK; + ulong start; #ifdef USE_920T_MMU int cflag; @@ -284,7 +285,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) sect, info->start[sect]); /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ vu_long *addr = (vu_long *) (info->start[sect]); @@ -297,7 +298,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* wait until flash is ready */ do { /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = CMD_STATUS_RESET; result = BIT_TIMEOUT; break; @@ -357,6 +358,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) ulong result; int rc = ERR_OK; int iflag; + ulong start; #ifdef USE_920T_MMU int cflag; @@ -387,12 +389,12 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait until flash is ready */ do { /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = CMD_SUSPEND; result = BIT_TIMEOUT; break; diff --git a/board/lubbock/flash.c b/board/lubbock/flash.c index a4b201e..1ea2893 100644 --- a/board/lubbock/flash.c +++ b/board/lubbock/flash.c @@ -221,7 +221,7 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) int flash_erase (flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -254,9 +254,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - start = get_timer (0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -269,14 +266,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); *addr = (FPW) 0x00500050; /* clear status register */ *addr = (FPW) 0x00200020; /* erase setup */ *addr = (FPW) 0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -393,6 +390,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) FPWV *addr = (FPWV *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -406,11 +404,11 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/modnet50/flash.c b/board/modnet50/flash.c index 4c31143..4834e21 100644 --- a/board/modnet50/flash.c +++ b/board/modnet50/flash.c @@ -291,6 +291,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) { int flag, sect, setup_offset = 0; int rc = ERR_OK; + ulong start; if (info->flash_id == FLASH_UNKNOWN) { printf ("- missing\n"); @@ -338,14 +339,14 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) (__u16) SECERASE_CMD; /* wait some time */ - reset_timer_masked (); - while (get_timer_masked () < 1000) { + start = get_timer(0); + while (get_timer(start) < 1000) { } /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); while (flash_check_erase_amd (info->start[sect])) { - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("timeout!\n"); /* OOPS: reach timeout, * try to reset chip @@ -411,6 +412,7 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) { int rc = ERR_OK; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*(__u16 *) (dest) & data) != data) @@ -446,10 +448,10 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) } /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); while (flash_check_write_amd (dest)) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { printf ("timeout! @ %08lX\n", dest); /* OOPS: reach timeout, * try to reset chip */ diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c index c11c0fe..86b49fb 100644 --- a/board/mx1ads/mx1ads.c +++ b/board/mx1ads/mx1ads.c @@ -169,7 +169,7 @@ int board_late_init (void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1, + gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c index 47f613c..7331efa 100644 --- a/board/mx1ads/syncflash.c +++ b/board/mx1ads/syncflash.c @@ -276,7 +276,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) { /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + get_timer(0); SF_NvmodeErase(); SF_NvmodeWrite(); diff --git a/board/ns9750dev/flash.c b/board/ns9750dev/flash.c index 5b56b98..185bc2d 100644 --- a/board/ns9750dev/flash.c +++ b/board/ns9750dev/flash.c @@ -261,7 +261,7 @@ void flash_unprotect_sectors (FPWV * addr) int flash_erase (flash_info_t * info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -294,10 +294,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("\n"); } - - start = get_timer (0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -312,7 +308,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) flash_unprotect_sectors (addr); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); *addr = (FPW) 0x00500050;/* clear status register */ *addr = (FPW) 0x00200020;/* erase setup */ @@ -321,7 +317,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); /* suspend erase */ @@ -441,6 +437,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) FPWV *addr = (FPWV *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -454,11 +451,11 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/pleb2/flash.c b/board/pleb2/flash.c index a8897dc..2406c5f 100644 --- a/board/pleb2/flash.c +++ b/board/pleb2/flash.c @@ -472,7 +472,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) FPWV *addr; int flag, prot, sect; int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong now, last; + ulong start, now, last; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -516,8 +516,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("\n"); } - reset_timer_masked (); - /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last && rcode == 0; sect++) { @@ -527,7 +525,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); - reset_timer_masked (); + start = get_timer(0); last = 0; addr = (FPWV *) (info->start[sect]); @@ -559,7 +557,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { if ((now = - get_timer_masked ()) > CONFIG_SYS_FLASH_ERASE_TOUT) { + get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); if (intel) { @@ -661,6 +659,7 @@ static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) int flag; int res = 0; /* result, assume success */ FPWV *base; /* first address in flash bank */ + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*dest & data) != data) { @@ -683,12 +682,12 @@ static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) if (flag) enable_interrupts (); - reset_timer_masked (); + start = get_timer(0); /* data polling for D7 */ while (res == 0 && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW) 0x00F000F0; /* reset bank */ res = 1; } @@ -711,6 +710,7 @@ static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data) { int flag; int res = 0; /* result, assume success */ + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*dest & data) != data) { @@ -730,10 +730,10 @@ static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data) if (flag) enable_interrupts (); - reset_timer_masked (); + start = get_timer(0); while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW) 0x00B000B0; /* Suspend program */ res = 1; } diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index e0f44dd..2c50fe8 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -282,7 +282,7 @@ int board_eth_init(bd_t *bis) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM, + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; } diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index ec9f865..8071600 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -379,7 +379,7 @@ int board_init(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM, + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; } diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 79b7c9d..fa69599 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -160,7 +160,7 @@ int board_init(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM, + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; } diff --git a/board/samsung/smdk2400/flash.c b/board/samsung/smdk2400/flash.c index fb69c21..47382fe 100644 --- a/board/samsung/smdk2400/flash.c +++ b/board/samsung/smdk2400/flash.c @@ -231,6 +231,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) ulong result, result1; int iflag, prot, sect; int rc = ERR_OK; + ulong start; #ifdef USE_920T_MMU int cflag; @@ -286,7 +287,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) sect, info->start[sect]); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ vu_long *addr = (vu_long *) (info->start[sect]); @@ -299,7 +300,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* wait until flash is ready */ do { /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = CMD_STATUS_RESET; result = BIT_TIMEOUT; break; @@ -359,6 +360,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) ulong result; int rc = ERR_OK; int iflag; + ulong start; #ifdef USE_920T_MMU int cflag; @@ -389,12 +391,12 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait until flash is ready */ do { /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = CMD_SUSPEND; result = BIT_TIMEOUT; break; diff --git a/board/sbc2410x/flash.c b/board/sbc2410x/flash.c index abb0935..d209a6f 100644 --- a/board/sbc2410x/flash.c +++ b/board/sbc2410x/flash.c @@ -173,6 +173,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) int iflag, cflag, prot, sect; int rc = ERR_OK; int chip; + ulong start; /* first look for protection bits */ @@ -213,7 +214,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ vu_short *addr = (vu_short *) (info->start[sect]); @@ -233,7 +234,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) result = *addr; /* check timeout */ - if (get_timer_masked () > + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; chip = TMO; @@ -295,6 +296,7 @@ static int write_hword (flash_info_t * info, ulong dest, ushort data) int rc = ERR_OK; int cflag, iflag; int chip; + ulong start; /* * Check if Flash is (sufficiently) erased @@ -322,7 +324,7 @@ static int write_hword (flash_info_t * info, ulong dest, ushort data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + get_timer(start); /* wait until flash is ready */ chip = 0; @@ -330,7 +332,7 @@ static int write_hword (flash_info_t * info, ulong dest, ushort data) result = *addr; /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { chip = ERR | TMO; break; } diff --git a/board/scb9328/config.mk b/board/scb9328/config.mk deleted file mode 100644 index 7c5e067..0000000 --- a/board/scb9328/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# This config file is used for compilation of scb93328 sources -# -# You might change location of U-Boot in memory by setting right CONFIG_SYS_TEXT_BASE. -# This allows for example having one copy located at the end of ram and stored -# in flash device and later on while developing use other location to test -# the code in RAM device only. -# - -CONFIG_SYS_TEXT_BASE = 0x08f00000 diff --git a/board/scb9328/flash.c b/board/scb9328/flash.c index c6f94ae..00c660a 100644 --- a/board/scb9328/flash.c +++ b/board/scb9328/flash.c @@ -97,11 +97,12 @@ static FLASH_BUS_RET flash_status_reg (void) static int flash_ready (ulong timeout) { int ok = 1; + ulong start; - reset_timer_masked (); + start = get_timer(0); while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) != FLASH_CMD (CFI_INTEL_SR_READY)) { - if (get_timer_masked () > timeout && timeout != 0) { + if (get_timer(start) > timeout && timeout != 0) { ok = 0; break; } diff --git a/board/scb9328/scb9328.c b/board/scb9328/scb9328.c index 428e8c9..2e31e8c 100644 --- a/board/scb9328/scb9328.c +++ b/board/scb9328/scb9328.c @@ -39,23 +39,17 @@ int board_init (void) int dram_init (void) { -#if ( CONFIG_NR_DRAM_BANKS > 0 ) + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((volatile void *)SCB9328_SDRAM_1, + SCB9328_SDRAM_1_SIZE); + + return 0; +} + +void dram_init_banksize(void) +{ gd->bd->bi_dram[0].start = SCB9328_SDRAM_1; gd->bd->bi_dram[0].size = SCB9328_SDRAM_1_SIZE; -#endif -#if ( CONFIG_NR_DRAM_BANKS > 1 ) - gd->bd->bi_dram[1].start = SCB9328_SDRAM_2; - gd->bd->bi_dram[1].size = SCB9328_SDRAM_2_SIZE; -#endif -#if ( CONFIG_NR_DRAM_BANKS > 2 ) - gd->bd->bi_dram[2].start = SCB9328_SDRAM_3; - gd->bd->bi_dram[2].size = SCB9328_SDRAM_3_SIZE; -#endif -#if ( CONFIG_NR_DRAM_BANKS > 3 ) - gd->bd->bi_dram[3].start = SCB9328_SDRAM_4; - gd->bd->bi_dram[3].size = SCB9328_SDRAM_4_SIZE; -#endif - return 0; } /** diff --git a/board/shannon/flash.c b/board/shannon/flash.c index 0455afa..179ec5f 100644 --- a/board/shannon/flash.c +++ b/board/shannon/flash.c @@ -190,6 +190,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) int iflag, cflag, prot, sect; int rc = ERR_OK; int chip1, chip2; + ulong start; /* first look for protection bits */ @@ -231,7 +232,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ @@ -253,7 +254,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) result = *addr; /* check timeout */ - if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; chip1 = TMO; @@ -322,6 +323,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) int rc = ERR_OK; int cflag, iflag; int chip1, chip2; + ulong start; /* * Check if Flash is (sufficiently) erased @@ -349,7 +351,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); /* wait until flash is ready */ chip1 = chip2 = 0; @@ -358,7 +360,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) result = *addr; /* check timeout */ - if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { chip1 = ERR | TMO; break; diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c index a7b6e70..63a0d33 100644 --- a/board/syteco/jadecpu/jadecpu.c +++ b/board/syteco/jadecpu/jadecpu.c @@ -152,7 +152,7 @@ int misc_init_r(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM, + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; diff --git a/board/syteco/zmx25/Makefile b/board/syteco/zmx25/Makefile new file mode 100644 index 0000000..5a0e5b3 --- /dev/null +++ b/board/syteco/zmx25/Makefile @@ -0,0 +1,51 @@ +# +# (c) 2010 Graf-Syteco, Matthias Weisser +# <weisserm@arcor.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += zmx25.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/syteco/zmx25/lowlevel_init.S b/board/syteco/zmx25/lowlevel_init.S new file mode 100644 index 0000000..8e63de0 --- /dev/null +++ b/board/syteco/zmx25/lowlevel_init.S @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2011 + * Matthias Weisser <weisserm@arcor.de> + * + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby <jrigby@gmail.com> + * + * Based on U-Boot and RedBoot sources for several different i.mx + * platforms. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/macro.h> +#include <asm/arch/macro.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/asm-offsets.h> + +/* + * clocks + */ +.macro init_clocks + + /* disable clock output */ + write32 IMX_CCM_BASE + CCM_MCR, 0x00000000 + write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000 + + /* + * enable all implemented clocks in all three + * clock control registers + */ + write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff + write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff + write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff + + /* Devide NAND clock by 32 */ + write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F +.endm + +/* + * sdram controller init + */ +.macro init_lpddr + ldr r0, =IMX_ESDRAMC_BASE + ldr r2, =IMX_SDRAM_BANK0_BASE + + /* + * reset SDRAM controller + * then wait for initialization to complete + */ + ldr r1, =(1 << 1) | (1 << 2) + str r1, [r0, #ESDRAMC_ESDMISC] +1: ldr r3, [r0, #ESDRAMC_ESDMISC] + tst r3, #(1 << 31) + beq 1b + ldr r1, =(1 << 2) + str r1, [r0, #ESDRAMC_ESDMISC] + + ldr r1, =0x002a7420 + str r1, [r0, #ESDRAMC_ESDCFG0] + + /* control | precharge */ + ldr r1, =0x92216008 + str r1, [r0, #ESDRAMC_ESDCTL0] + /* dram command encoded in address */ + str r1, [r2, #0x400] + + /* auto refresh */ + ldr r1, =0xa2216008 + str r1, [r0, #ESDRAMC_ESDCTL0] + /* read dram twice to auto refresh */ + ldr r3, [r2] + ldr r3, [r2] + + /* control | load mode */ + ldr r1, =0xb2216008 + str r1, [r0, #ESDRAMC_ESDCTL0] + + /* mode register of lpddram */ + strb r1, [r2, #0x33] + + /* extended mode register of lpddrram */ + ldr r2, =0x81000000 + strb r1, [r2] + + /* control | normal */ + ldr r1, =0x82216008 + str r1, [r0, #ESDRAMC_ESDCTL0] +.endm + +.globl lowlevel_init +lowlevel_init: + init_aips + init_max + init_clocks + init_lpddr + mov pc, lr diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c new file mode 100644 index 0000000..f055038 --- /dev/null +++ b/board/syteco/zmx25/zmx25.c @@ -0,0 +1,203 @@ +/* + * (c) 2011 Graf-Syteco, Matthias Weisser + * <weisserm@arcor.de> + * + * Based on tx25.c: + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby <jrigby@gmail.com> + * + * Based on imx27lite.c: + * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net> + * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com> + * And: + * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> +#include <mxc_gpio.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/imx25-pinmux.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init() +{ + struct iomuxc_mux_ctl *muxctl; + struct iomuxc_pad_ctl *padctl; + struct iomuxc_pad_input_select *inputselect; + u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION; + u32 gpio_mux_mode1 = MX25_PIN_MUX_MODE(1); + u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5); + u32 gpio_mux_mode6 = MX25_PIN_MUX_MODE(6); + u32 input_select1 = MX25_PAD_INPUT_SELECT_DAISY(1); + u32 input_select2 = MX25_PAD_INPUT_SELECT_DAISY(2); + + icache_enable(); + + muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; + padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; + inputselect = (struct iomuxc_pad_input_select *)IMX_IOPADINPUTSEL_BASE; + + /* Setup of core volatage selection pin to run at 1.4V */ + writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */ + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 15), MXC_GPIO_DIRECTION_OUT); + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 15), 1); + + /* Setup of input daisy chains for SD card pins*/ + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_clk); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data0); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data1); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data2); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data3); + + /* Setup of digital output for USB power and OC */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */ + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 28), MXC_GPIO_DIRECTION_OUT); + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 28), 1); + + writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */ + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 18), MXC_GPIO_DIRECTION_IN); + + /* Setup of digital output control pins */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d7); /* Ouput 2 Ctrl GPIO1[6] */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d6); /* Ouput 1 Stat GPIO1[31]*/ + writel(gpio_mux_mode5, &muxctl->pad_csi_d5); /* Ouput 2 Stat GPIO1[30]*/ + + writel(0, &padctl->pad_csi_d6); /* Ouput 1 Stat pull up off */ + writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */ + + /* Switch both output drivers off */ + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 7), 0); + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 7), MXC_GPIO_DIRECTION_OUT); + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 6), 0); + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 6), MXC_GPIO_DIRECTION_OUT); + + /* Setup of key input pin GPIO2[29]*/ + writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0); + writel(0, &padctl->pad_kpp_row0); /* Key pull up off */ + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(2, 29), MXC_GPIO_DIRECTION_IN); + + /* Setup of status LED outputs */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */ + + /* Switch both LEDs off */ + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0); + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(4, 21), MXC_GPIO_DIRECTION_OUT); + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0); + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 29), MXC_GPIO_DIRECTION_OUT); + + /* Setup of CAN1 and CAN2 signals */ + writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */ + writel(gpio_mux_mode6, &muxctl->pad_gpio_b); /* CAN1 RX */ + writel(gpio_mux_mode6, &muxctl->pad_gpio_c); /* CAN2 TX */ + writel(gpio_mux_mode6, &muxctl->pad_gpio_d); /* CAN2 RX */ + + /* Setup of input daisy chains for CAN signals*/ + writel(input_select1, &inputselect->can1_ipp_ind_canrx); /* CAN1 RX */ + writel(input_select1, &inputselect->can2_ipp_ind_canrx); /* CAN2 RX */ + + /* Setup of I2C3 signals */ + writel(gpio_mux_mode1, &muxctl->pad_cspi1_ss1); /* I2C3 SDA */ + writel(gpio_mux_mode1, &muxctl->pad_gpio_e); /* I2C3 SCL */ + + /* Setup of input daisy chains for I2C3 signals*/ + writel(input_select1, &inputselect->i2c3_ipp_sda_in); /* I2C3 SDA */ + writel(input_select2, &inputselect->i2c3_ipp_scl_in); /* I2C3 SCL */ + + /* board id for linux */ + gd->bd->bi_arch_number = MACH_TYPE_ZMX25; + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int board_late_init(void) +{ + const char *e; + +#ifdef CONFIG_FEC_MXC + struct iomuxc_mux_ctl *muxctl; + struct iomuxc_pad_ctl *padctl; + u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2); + u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5); + + /* + * fec pin init is generic + */ + mx25_fec_init_pins(); + + /* + * Set up LAN-RESET and FEC_RX_ERR + * + * LAN-RESET: GPIO3[16] is ALT 5 mode of pin U20 + * FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2 + */ + muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; + padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; + + writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk); + writel(gpio_mux_mode2, &muxctl->pad_uart2_cts); + + /* assert PHY reset (low) */ + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 0); + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 16), MXC_GPIO_DIRECTION_OUT); + + udelay(5000); + + /* deassert PHY reset */ + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 1); + + udelay(5000); +#endif + + e = getenv("gs_base_board"); + if (e != NULL) { + if (strcmp(e, "G283") == 0) { + int key = mxc_gpio_get(MXC_GPIO_PORT_TO_NUM(2, 29)); + + if (key) { + /* Switch on both LEDs to inidcate boot mode */ + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0); + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0); + + setenv("preboot", "run gs_slow_boot"); + } else + setenv("preboot", "run gs_fast_boot"); + } + } + + return 0; +} + +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, + PHYS_SDRAM_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = gd->ram_size; +} diff --git a/board/ti/omap1610inn/flash.c b/board/ti/omap1610inn/flash.c index 36200ad..1b67d08 100644 --- a/board/ti/omap1610inn/flash.c +++ b/board/ti/omap1610inn/flash.c @@ -278,7 +278,7 @@ void flash_unprotect_sectors (FPWV * addr) int flash_erase (flash_info_t * info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -311,10 +311,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("\n"); } - - start = get_timer (0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -329,7 +325,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) flash_unprotect_sectors (addr); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); *addr = (FPW) 0x00500050;/* clear status register */ *addr = (FPW) 0x00200020;/* erase setup */ @@ -338,7 +334,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); /* suspend erase */ @@ -458,6 +454,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) FPWV *addr = (FPWV *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -470,11 +467,11 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/ti/omap730p2/flash.c b/board/ti/omap730p2/flash.c index 5b56b98..185bc2d 100644 --- a/board/ti/omap730p2/flash.c +++ b/board/ti/omap730p2/flash.c @@ -261,7 +261,7 @@ void flash_unprotect_sectors (FPWV * addr) int flash_erase (flash_info_t * info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -294,10 +294,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("\n"); } - - start = get_timer (0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -312,7 +308,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) flash_unprotect_sectors (addr); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); *addr = (FPW) 0x00500050;/* clear status register */ *addr = (FPW) 0x00200020;/* erase setup */ @@ -321,7 +317,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); /* suspend erase */ @@ -441,6 +437,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) FPWV *addr = (FPWV *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -454,11 +451,11 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/xaeniax/flash.c b/board/xaeniax/flash.c index b051c89..6cb0aca 100644 --- a/board/xaeniax/flash.c +++ b/board/xaeniax/flash.c @@ -221,7 +221,7 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) int flash_erase (flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -254,9 +254,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - start = get_timer (0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -269,14 +266,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); *addr = (FPW) 0x00500050; /* clear status register */ *addr = (FPW) 0x00200020; /* erase setup */ *addr = (FPW) 0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -393,6 +390,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) FPWV *addr = (FPWV *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -406,11 +404,11 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/xm250/flash.c b/board/xm250/flash.c index b02149c..e825aba 100644 --- a/board/xm250/flash.c +++ b/board/xm250/flash.c @@ -250,7 +250,7 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) int flash_erase (flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -283,9 +283,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - start = get_timer (0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -298,14 +295,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); *addr = (FPW) 0x00500050; /* clear status register */ *addr = (FPW) 0x00200020; /* erase setup */ *addr = (FPW) 0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -422,6 +419,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) FPWV *addr = (FPWV *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -435,11 +433,11 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } @@ -470,6 +468,7 @@ int flash_real_protect(flash_info_t *info, long sector, int prot) int rc = 0; vu_long *addr = (vu_long *)(info->start[sector]); int flag = disable_interrupts(); + ulong start; *addr = INTEL_CLEAR; /* Clear status register */ if (prot) { /* Set sector lock bit */ @@ -481,10 +480,10 @@ int flash_real_protect(flash_info_t *info, long sector, int prot) *addr = INTEL_CONFIRM; /* clear */ } - reset_timer_masked (); + start = get_timer(0); while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) { printf("Flash lock bit operation timed out\n"); rc = 1; break; @@ -510,13 +509,13 @@ int flash_real_protect(flash_info_t *info, long sector, int prot) { if (info->protect[i]) { - reset_timer_masked (); + start = get_timer(0); addr = (vu_long *)(info->start[i]); *addr = INTEL_LOCKBIT; /* Sector lock bit */ *addr = INTEL_PROTECT; /* set */ while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) { printf("Flash lock bit operation timed out\n"); rc = 1; diff --git a/board/zylonite/flash.c b/board/zylonite/flash.c index 5ba84c6..3ee0ab8 100644 --- a/board/zylonite/flash.c +++ b/board/zylonite/flash.c @@ -224,7 +224,7 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) int flash_erase (flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -257,9 +257,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - start = get_timer (0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -272,14 +269,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); *addr = (FPW) 0x00500050; /* clear status register */ *addr = (FPW) 0x00200020; /* erase setup */ *addr = (FPW) 0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -396,6 +393,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) FPWV *addr = (FPWV *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -409,11 +407,11 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } @@ -131,6 +131,7 @@ rd6281a arm arm926ejs - Marvell sheevaplug arm arm926ejs - Marvell kirkwood dockstar arm arm926ejs - Seagate kirkwood jadecpu arm arm926ejs jadecpu syteco mb86r0x +zmx25 arm arm926ejs zmx25 syteco mx25 imx27lite arm arm926ejs imx27lite logicpd mx27 magnesium arm arm926ejs imx27lite logicpd mx27 nhk8815 arm arm926ejs nhk8815 st nomadik @@ -139,7 +140,7 @@ omap5912osk arm arm926ejs - ti edminiv2 arm arm926ejs - LaCie orion5x dkb arm arm926ejs - Marvell pantheon ca9x4_ct_vxp arm armv7 vexpress armltd -efikamx arm armv7 efikamx - mx5 mx51evk:IMX_CONFIG=board/efikamx/imximage.cfg +efikamx arm armv7 efikamx - mx5 efikamx:IMX_CONFIG=board/efikamx/imximage.cfg mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg mx53ard arm armv7 mx53ard freescale mx5 mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg @@ -597,6 +598,9 @@ P2020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freesca P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,NAND P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH +P2041RDB powerpc mpc85xx p2041rdb freescale +P2041RDB_SDCARD powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 +P2041RDB_SPIFLASH powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P3041DS powerpc mpc85xx corenet_ds freescale P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 diff --git a/common/fdt_support.c b/common/fdt_support.c index 496040b..19b2ef6 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -1195,6 +1195,46 @@ int fdt_alloc_phandle(void *blob) return phandle + 1; } +/* + * fdt_create_phandle: Create a phandle property for the given node + * + * @fdt: ptr to device tree + * @nodeoffset: node to update + * @phandle: phandle value to set (must be unique) +*/ +int fdt_create_phandle(void *fdt, int nodeoffset, uint32_t phandle) +{ + int ret; + +#ifdef DEBUG + int off = fdt_node_offset_by_phandle(fdt, phandle); + + if ((off >= 0) && (off != nodeoffset)) { + char buf[64]; + + fdt_get_path(fdt, nodeoffset, buf, sizeof(buf)); + printf("Trying to update node %s with phandle %u ", + buf, phandle); + + fdt_get_path(fdt, off, buf, sizeof(buf)); + printf("that already exists in node %s.\n", buf); + return -FDT_ERR_BADPHANDLE; + } +#endif + + ret = fdt_setprop_cell(fdt, nodeoffset, "phandle", phandle); + if (ret < 0) + return ret; + + /* + * For now, also set the deprecated "linux,phandle" property, so that we + * don't break older kernels. + */ + ret = fdt_setprop_cell(fdt, nodeoffset, "linux,phandle", phandle); + + return ret; +} + #if defined(CONFIG_VIDEO) int fdt_add_edid(void *blob, const char *compat, unsigned char *edid_buf) { @@ -1223,3 +1263,70 @@ err_size: return ret; } #endif + +/* + * Verify the physical address of device tree node for a given alias + * + * This function locates the device tree node of a given alias, and then + * verifies that the physical address of that device matches the given + * parameter. It displays a message if there is a mismatch. + * + * Returns 1 on success, 0 on failure + */ +int fdt_verify_alias_address(void *fdt, int anode, const char *alias, u64 addr) +{ + const char *path; + const u32 *reg; + int node, len; + u64 dt_addr; + + path = fdt_getprop(fdt, anode, alias, NULL); + if (!path) { + /* If there's no such alias, then it's not a failure */ + return 1; + } + + node = fdt_path_offset(fdt, path); + if (node < 0) { + printf("Warning: device tree alias '%s' points to invalid " + "node %s.\n", alias, path); + return 0; + } + + reg = fdt_getprop(fdt, node, "reg", &len); + if (!reg) { + printf("Warning: device tree node '%s' has no address.\n", + path); + return 0; + } + + dt_addr = fdt_translate_address(fdt, node, reg); + if (addr != dt_addr) { + printf("Warning: U-Boot configured device %s at address %llx,\n" + " but the device tree has it address %llx.\n", + alias, addr, dt_addr); + return 0; + } + + return 1; +} + +/* + * Returns the base address of an SOC or PCI node + */ +u64 fdt_get_base_address(void *fdt, int node) +{ + int size; + u32 naddr; + const u32 *prop; + + prop = fdt_getprop(fdt, node, "#address-cells", &size); + if (prop && size == 4) + naddr = *prop; + else + naddr = 2; + + prop = fdt_getprop(fdt, node, "ranges", &size); + + return prop ? fdt_translate_address(fdt, node, prop + naddr) : 0; +} diff --git a/common/image.c b/common/image.c index e542a57..5c7d4f4 100644 --- a/common/image.c +++ b/common/image.c @@ -1234,8 +1234,10 @@ int boot_relocate_fdt (struct lmb *lmb, char **of_flat_tree, ulong *of_size) { void *fdt_blob = *of_flat_tree; void *of_start = 0; + char *fdt_high; ulong of_len = 0; int err; + int disable_relocation = 0; /* nothing to do */ if (*of_size == 0) @@ -1249,26 +1251,62 @@ int boot_relocate_fdt (struct lmb *lmb, char **of_flat_tree, ulong *of_size) /* position on a 4K boundary before the alloc_current */ /* Pad the FDT by a specified amount */ of_len = *of_size + CONFIG_SYS_FDT_PAD; - of_start = (void *)(unsigned long)lmb_alloc_base(lmb, of_len, 0x1000, - getenv_bootm_mapsize() + getenv_bootm_low()); + + /* If fdt_high is set use it to select the relocation address */ + fdt_high = getenv("fdt_high"); + if (fdt_high) { + void *desired_addr = (void *)simple_strtoul(fdt_high, NULL, 16); + + if (((ulong) desired_addr) == ~0UL) { + /* All ones means use fdt in place */ + desired_addr = fdt_blob; + disable_relocation = 1; + } + if (desired_addr) { + of_start = + (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000, + ((ulong) + desired_addr) + + of_len); + if (desired_addr && of_start != desired_addr) { + puts("Failed using fdt_high value for Device Tree"); + goto error; + } + } else { + of_start = + (void *)(ulong) lmb_alloc(lmb, of_len, 0x1000); + } + } else { + of_start = + (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000, + getenv_bootm_mapsize() + + getenv_bootm_low()); + } if (of_start == 0) { puts("device tree - allocation error\n"); goto error; } - debug ("## device tree at %p ... %p (len=%ld [0x%lX])\n", - fdt_blob, fdt_blob + *of_size - 1, of_len, of_len); + if (disable_relocation) { + /* We assume there is space after the existing fdt to use for padding */ + fdt_set_totalsize(of_start, of_len); + printf(" Using Device Tree in place at %p, end %p\n", + of_start, of_start + of_len - 1); + } else { + debug ("## device tree at %p ... %p (len=%ld [0x%lX])\n", + fdt_blob, fdt_blob + *of_size - 1, of_len, of_len); - printf (" Loading Device Tree to %p, end %p ... ", - of_start, of_start + of_len - 1); + printf (" Loading Device Tree to %p, end %p ... ", + of_start, of_start + of_len - 1); - err = fdt_open_into (fdt_blob, of_start, of_len); - if (err != 0) { - fdt_error ("fdt move failed"); - goto error; + err = fdt_open_into (fdt_blob, of_start, of_len); + if (err != 0) { + fdt_error ("fdt move failed"); + goto error; + } + puts ("OK\n"); } - puts ("OK\n"); *of_flat_tree = of_start; *of_size = of_len; diff --git a/common/memsize.c b/common/memsize.c index 6c275c9..963e4f3 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -37,7 +37,7 @@ * the actually available RAM size between addresses `base' and * `base + maxsize'. */ -long get_ram_size(volatile long *base, long maxsize) +long get_ram_size(long *base, long maxsize) { volatile long *addr; long save[32]; diff --git a/doc/README.p2041rdb b/doc/README.p2041rdb new file mode 100644 index 0000000..292d0d3 --- /dev/null +++ b/doc/README.p2041rdb @@ -0,0 +1,123 @@ +Overview +========= +The P2041 Processor combines four Power Architecture processor cores +with high-performance datapath acceleration architecture(DPAA), CoreNet +fabric infrastructure, as well as network and peripheral bus interfaces +required for networking, telecom/datacom, wireless infrastructure, and +military/aerospace applications. + +P2041RDB board is a quad core platform supporting the P2041 processor +of QorIQ DPAA series. + +Boot from NOR flash +=================== +1. Build image + make P2041RDB_config + make all + +2. Program image + => tftp 1000000 u-boot.bin + => protect off all + => erase eff80000 efffffff + => cp.b 1000000 eff80000 80000 + +3. Program RCW + => tftp 1000000 rcw.bin + => protect off all + => erase e8000000 e801ffff + => cp.b 1000000 e8000000 50 + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => protect off all + => erase ef000000 ef0fffff + => cp.b 1000000 ef000000 2000 + +5. Change DIP-switch + SW1[1-5] = 10110 + Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SDCard +=================== +1. Build image + make P2041RDB_SDCARD_config + make all + +2. Generate PBL imge + Use PE tool to produce a image used to be programed to + SDCard which contains RCW and U-Boot image. + +3. Program the PBL image to SDCard + => tftp 1000000 pbl_sd.bin + => mmcinfo + => mmc write 1000000 8 441 + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => mmc write 1000000 46a 10 + +5. Change DIP-switch + SW1[1-5] = 01100 + Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SPI flash +=================== +1. Build image + make P2041RDB_SPIFLASH_config + make all + +2. Generate PBL imge + Use PE tool to produce a image used to be programed to + SPI flash which contains RCW and U-Boot image. + +3. Program the PBL image to SPI flash + => tftp 1000000 pbl_spi.bin + => spi probe 0 + => sf erase 0 100000 + => sf write 1000000 0 $filesize + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => sf erase 110000 10000 + => sf write 1000000 110000 $filesize + +5. Change DIP-switch + SW1[1-5] = 10100 + Note: 1 stands for 'on', 0 stands for 'off' + +CPLD command +============ +The CPLD is used to control the power sequence and some serdes lane +mux function. + +cpld reset - hard reset to default bank +cpld reset altbank - reset to alternate bank +cpld lane_mux <lane> <mux_value> - set multiplexed lane pin + lane 6: 0 -> slot1 (Default) + 1 -> SGMII + lane a: 0 -> slot2 (Default) + 1 -> AURORA + lane c: 0 -> slot2 (Default) + 1 -> SATA0 + lane d: 0 -> slot2 (Default) + 1 -> SATA1 + +Using the Device Tree Source File +================================= +To create the DTB (Device Tree Binary) image file, use a command +similar to this: + dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb + +Or use the following command: + {linux-2.6}/make p2041rdb.dtb ARCH=powerpc + +then the dtb file will be generated under the following directory: + {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb + +Booting Linux +============= +Place a linux uImage in the TFTP disk area. + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp 3000000 p2041rdb.dtb + bootm 1000000 2000000 3000000 diff --git a/drivers/mtd/spi/eeprom_m95xxx.c b/drivers/mtd/spi/eeprom_m95xxx.c index 632db4e..ef8ed6f 100644 --- a/drivers/mtd/spi/eeprom_m95xxx.c +++ b/drivers/mtd/spi/eeprom_m95xxx.c @@ -75,6 +75,7 @@ ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) { struct spi_slave *slave; char buf[3]; + ulong start; slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000, CONFIG_DEFAULT_SPI_MODE); @@ -102,7 +103,7 @@ ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) if(spi_xfer(slave, len * 8, buffer, NULL, SPI_XFER_END)) return -1; - reset_timer_masked(); + start = get_timer(0); do { buf[0] = SPI_EEPROM_RDSR; buf[1] = 0; @@ -111,7 +112,7 @@ ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) if (!(buf[1] & 1)) break; - } while (get_timer_masked() < CONFIG_SYS_SPI_WRITE_TOUT); + } while (get_timer(start) < CONFIG_SYS_SPI_WRITE_TOUT); if (buf[1] & 1) printf ("*** spi_write: Time out while writing!\n"); diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 4e4cd27..ab90afa 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -86,7 +86,7 @@ static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr, /* * wait for the related interrupt */ - start = get_timer_masked(); + start = get_timer(0); while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) { if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { printf("Read MDIO failed...\n"); @@ -138,7 +138,7 @@ static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr, /* * wait for the MII interrupt */ - start = get_timer_masked(); + start = get_timer(0); while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) { if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { printf("Write MDIO failed...\n"); @@ -189,7 +189,7 @@ static int miiphy_wait_aneg(struct eth_device *dev) /* * Wait for AN completion */ - start = get_timer_masked(); + start = get_timer(0); do { if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { printf("%s: Autonegotiation timeout\n", dev->name); diff --git a/drivers/net/netarm_eth.c b/drivers/net/netarm_eth.c index c9e324e..f54817e 100644 --- a/drivers/net/netarm_eth.c +++ b/drivers/net/netarm_eth.c @@ -81,9 +81,10 @@ static unsigned int na_mii_read (int reg) static int na_mii_poll_busy (void) { + ulong start; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - while (get_timer_masked () < NA_MII_POLL_BUSY_DELAY) { + start = get_timer(0)); + while (get_timer(start) < NA_MII_POLL_BUSY_DELAY) { if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) { return 1; } @@ -164,19 +165,20 @@ static unsigned int na_mii_check_speed (void) static int reset_eth (void) { int pt; + ulong start; na_get_mac_addr (); pt = na_mii_identify_phy (); /* reset the phy */ na_mii_write (MII_PHY_CONTROL, 0x8000); - reset_timer_masked (); - while (get_timer_masked () < NA_MII_NEGOTIATE_DELAY) { + start = get_timer(0); + while (get_timer(start) < NA_MII_NEGOTIATE_DELAY) { if ((na_mii_read (MII_PHY_STATUS) & 0x8000) == 0) { break; } } - if (get_timer_masked () >= NA_MII_NEGOTIATE_DELAY) + if (get_timer(start) >= NA_MII_NEGOTIATE_DELAY) printf ("phy reset timeout\n"); /* set the PCS reg */ diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 698e726..81381d9 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -60,8 +60,6 @@ static unsigned long spi_bases[] = { 0x53f84000, }; -#define mxc_get_clock(x) mx31_get_ipg_clk() - #elif defined(CONFIG_MX51) #define MXC_CSPICTRL_EN (1 << 0) diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index 6af35ab..a0cfbb7 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -29,6 +29,14 @@ #define USBCTRL_OTGBASE_OFFSET 0x600 +#ifdef CONFIG_MX25 +#define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6) +#define MX25_USB_CTRL_HSTD_BIT (1<<5) +#define MX25_USB_CTRL_USBTE_BIT (1<<4) +#define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3) +#endif + +#ifdef CONFIG_MX31 #define MX31_OTG_SIC_SHIFT 29 #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) #define MX31_OTG_PM_BIT (1 << 24) @@ -42,12 +50,19 @@ #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) #define MX31_H1_PM_BIT (1 << 8) #define MX31_H1_DT_BIT (1 << 4) +#endif static int mxc_set_usbcontrol(int port, unsigned int flags) { unsigned int v; + +#ifdef CONFIG_MX25 + v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT | + MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT; +#endif + #ifdef CONFIG_MX31 - v = readl(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET); + v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); switch (port) { case 0: /* OTG port */ @@ -85,36 +100,38 @@ static int mxc_set_usbcontrol(int port, unsigned int flags) default: return -EINVAL; } - - writel(v, MX31_OTG_BASE_ADDR + - USBCTRL_OTGBASE_OFFSET); #endif - return 0; + + writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); + return 0; } int ehci_hcd_init(void) { - u32 tmp; struct usb_ehci *ehci; +#ifdef CONFIG_MX31 + u32 tmp; struct clock_control_regs *sc_regs = (struct clock_control_regs *)CCM_BASE; tmp = __raw_readl(&sc_regs->ccmr); __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ; +#endif udelay(80); /* Take USB2 */ - ehci = (struct usb_ehci *)(MX31_OTG_BASE_ADDR + + ehci = (struct usb_ehci *)(IMX_USB_BASE + (0x200 * CONFIG_MXC_USB_PORT)); hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); setbits_le32(&ehci->usbmode, CM_HOST); +#ifdef CONFIG_MX31 setbits_le32(&ehci->control, USB_EN); __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); - +#endif mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); udelay(10000); diff --git a/include/common.h b/include/common.h index 2c8513a..c5d2dce 100644 --- a/include/common.h +++ b/include/common.h @@ -317,7 +317,7 @@ const char *symbol_lookup(unsigned long addr, unsigned long *caddr); void api_init (void); /* common/memsize.c */ -long get_ram_size (volatile long *, long); +long get_ram_size (long *, long); /* $(BOARD)/$(BOARD).c */ void reset_phy (void); diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 0c0ae02..c9a0f60 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -91,7 +91,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h new file mode 100644 index 0000000..2beb357 --- /dev/null +++ b/include/configs/P2041RDB.h @@ -0,0 +1,624 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * P2041 RDB board configuration file + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_P2041RDB +#define CONFIG_PHYS_64BIT +#define CONFIG_PPC_P2041 + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_MP /* support multiple processors */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#else +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#endif + +#if defined(CONFIG_SPIFLASH) + #define CONFIG_SYS_EXTRA_ENV_RELOC + #define CONFIG_ENV_IS_IN_SPI_FLASH + #define CONFIG_ENV_SPI_BUS 0 + #define CONFIG_ENV_SPI_CS 0 + #define CONFIG_ENV_SPI_MAX_HZ 10000000 + #define CONFIG_ENV_SPI_MODE 0 + #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ + #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ + #define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) + #define CONFIG_SYS_EXTRA_ENV_RELOC + #define CONFIG_ENV_IS_IN_MMC + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_ENV_SIZE 0x2000 + #define CONFIG_ENV_OFFSET (512 * 1097) +#else + #define CONFIG_ENV_IS_IN_FLASH + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ + - CONFIG_ENV_SECT_SIZE) + #define CONFIG_ENV_SIZE 0x2000 + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_SYS_CLK_FREQ 66666666 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ +#endif + +#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ + CONFIG_RAMBOOT_TEXT_BASE) +#else +#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR +#endif +#define CONFIG_SYS_L3_SIZE (1024 << 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull +#else +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#endif +/* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD +#define CONFIG_FSL_DDR3 + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x52 +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * Local Bus Definitions + */ + +/* Set the local bus clock 1/8 of platform clock */ +#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 + +#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* Start of PromJet */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_SYS_BR0_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ + | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) + +#define CONFIG_FSL_CPLD +#define CPLD_BASE 0xffdf0000 /* CPLD registers */ +#ifdef CONFIG_PHYS_64BIT +#define CPLD_BASE_PHYS 0xfffdf0000ull +#else +#define CPLD_BASE_PHYS CPLD_BASE +#endif + +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ + +#define PIXIS_LBMAP_SWITCH 7 +#define PIXIS_LBMAP_MASK 0xf0 +#define PIXIS_LBMAP_SHIFT 4 +#define PIXIS_LBMAP_ALTBANK 0x40 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x118000 +#define CONFIG_SYS_I2C2_OFFSET 0x118100 + +/* + * RapidIO + */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ + +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#else +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 +#endif +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 +#endif +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 +#endif +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 +#endif +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 +#endif +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* Qman/Bman */ +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#else +#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#endif +#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull +#else +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#endif +#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +/* Default address of microcode for the Linux Fman driver */ +#define CONFIG_SYS_FMAN_FW +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 545KB (1089 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + */ +#define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 +#endif +#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH) + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#endif + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 +#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 +#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 +#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 +#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 + +#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c +#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d +#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e +#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f + +#define CONFIG_SYS_TBIPA_VALUE 8 +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* +* USB +*/ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 + +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_HZ 1000 /* decrementer freq 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ + +#define CONFIG_BAUDRATE 115200 + +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ + "bank_intlv=cs0_cs1\0" \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "usb_phy_type=" MK_STR(__USB_PHY_TYPE) "\0" \ + "usb_dr_mode=host\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=p2041rdb/p2041rdb.dtb\0" \ + "bdev=sda3\0" \ + "c=ffe\0" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT + +#ifdef CONFIG_SECURE_BOOT +#include <asm/fsl_secure_boot.h> +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 80ad342..18aaadf 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -190,7 +190,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ - "console=ttyS2,115200n8\0" \ + "console=ttyO2,115200n8\0" \ "mmcargs=setenv bootargs console=${console} " \ "root=/dev/mmcblk0p2 rw " \ "rootfstype=ext3 rootwait\0" \ diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h index a04ac49..7d3363a 100644 --- a/include/configs/efikamx.h +++ b/include/configs/efikamx.h @@ -38,6 +38,8 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_TEXT_BASE 0x97800000 + #define CONFIG_SYS_L2CACHE_OFF /* @@ -47,6 +49,7 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_MMC #define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #undef CONFIG_CMD_IMLS diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 5f70023..35ceacd 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -162,8 +162,10 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_GBL_DATA_OFFSET) /*----------------------------------------------------------------------- * FLASH and environment organization diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h index 6a92ec3..1b5d931 100644 --- a/include/configs/scb9328.h +++ b/include/configs/scb9328.h @@ -126,6 +126,11 @@ #define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */ #define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */ +#define CONFIG_SYS_TEXT_BASE 0x10000000 + +#define CONFIG_SYS_SDRAM_BASE SCB9328_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (SCB9328_SDRAM_1 + 0xf00000) + /* * Configuration for FLASH memory for the Synertronixx board */ diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h index 3627ce7..4bced0c 100644 --- a/include/configs/tnetv107x_evm.h +++ b/include/configs/tnetv107x_evm.h @@ -57,6 +57,12 @@ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_STACKSIZE (256*1024) +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + /* Serial Driver Info */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h new file mode 100644 index 0000000..374c88a --- /dev/null +++ b/include/configs/zmx25.h @@ -0,0 +1,180 @@ +/* + * (c) 2011 Graf-Syteco, Matthias Weisser + * <weisserm@arcor.de> + * + * Configuation settings for the zmx25 board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_MX25 +#define CONFIG_MX25_CLK32 32768 /* OSC32K frequency */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_TEXT_BASE 0xA0000000 + +/* + * Environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "gs_fast_boot=setenv bootdelay 5\0" \ + "gs_slow_boot=setenv bootdelay 10\0" \ + "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \ + "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \ + "bootm 0x81000000; bootelf 0x81000000\0" + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define BOARD_LATE_INIT + +/* + * Compressions + */ +#define CONFIG_LZO + +/* + * Hardware drivers + */ + +/* + * GPIO + */ +#define CONFIG_MXC_GPIO + +/* + * Serial + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX25_UART2 +#define CONFIG_CONS_INDEX 1 /* use UART2 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Ethernet + */ +#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_PHYADDR 0x00 +#define CONFIG_MII +#define CONFIG_NET_MULTI + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#define CONFIG_CMD_NET +#define CONFIG_CMD_CACHE + +#define CONFIG_SYS_64BIT_VSPRINTF + +/* + * Additional command + */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_USB + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_MXC +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORT 2 +#define CONFIG_MXC_USB_PORTSC 0xC0000000 +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT +#endif /* CONFIG_CMD_USB */ + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */ +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */ + +/* + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE 0xA0000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 + +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE (128 * 1024) + +/* + * CFI FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* ~10x faster */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024)) +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE) + +#define CONFIG_SYS_PROMPT "zmx25> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_PREBOOT "" + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay +#define CONFIG_AUTOBOOT_DELAY_STR "delaygs" +#define CONFIG_AUTOBOOT_STOP_STR "stopgs" + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000) +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#endif /* __CONFIG_H */ diff --git a/include/fdt_support.h b/include/fdt_support.h index ce6817b..863024f 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -79,6 +79,7 @@ void ft_pci_setup(void *blob, bd_t *bd); void set_working_fdt_addr(void *addr); int fdt_resize(void *blob); +int fdt_increase_size(void *fdt, int add_len); int fdt_fixup_nor_flash_size(void *blob); @@ -88,7 +89,12 @@ u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr); int fdt_node_offset_by_compat_reg(void *blob, const char *compat, phys_addr_t compat_off); int fdt_alloc_phandle(void *blob); +int fdt_create_phandle(void *fdt, int nodeoffset, uint32_t phandle); int fdt_add_edid(void *blob, const char *compat, unsigned char *buf); +int fdt_verify_alias_address(void *fdt, int anode, const char *alias, + u64 addr); +u64 fdt_get_base_address(void *fdt, int node); + #endif /* ifdef CONFIG_OF_LIBFDT */ #endif /* ifndef __FDT_SUPPORT_H */ diff --git a/include/libfdt.h b/include/libfdt.h index d23d40e..de82ed5 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -343,6 +343,75 @@ int fdt_path_offset(const void *fdt, const char *path); const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp); /** + * fdt_first_property_offset - find the offset of a node's first property + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * + * fdt_first_property_offset() finds the first property of the node at + * the given structure block offset. + * + * returns: + * structure block offset of the property (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested node has no properties + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_first_property_offset(const void *fdt, int nodeoffset); + +/** + * fdt_next_property_offset - step through a node's properties + * @fdt: pointer to the device tree blob + * @offset: structure block offset of a property + * + * fdt_next_property_offset() finds the property immediately after the + * one at the given structure block offset. This will be a property + * of the same node as the given property. + * + * returns: + * structure block offset of the next property (>=0), on success + * -FDT_ERR_NOTFOUND, if the given property is the last in its node + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_next_property_offset(const void *fdt, int offset); + +/** + * fdt_get_property_by_offset - retrieve the property at a given offset + * @fdt: pointer to the device tree blob + * @offset: offset of the property to retrieve + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property_by_offset() retrieves a pointer to the + * fdt_property structure within the device tree blob at the given + * offset. If lenp is non-NULL, the length of the property value is + * also returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property_by_offset(const void *fdt, + int offset, + int *lenp); + +/** * fdt_get_property_namelen - find a property based on substring * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node whose property to find @@ -396,6 +465,40 @@ static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset, } /** + * fdt_getprop_by_offset - retrieve the value of a property at a given offset + * @fdt: pointer to the device tree blob + * @ffset: offset of the property to read + * @namep: pointer to a string variable (will be overwritten) or NULL + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop_by_offset() retrieves a pointer to the value of the + * property at structure block offset 'offset' (this will be a pointer + * to within the device blob itself, not a copy of the value). If + * lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. If namep is non-NULL, + * the property's namne will also be returned in the char * pointed to + * by namep (this will be a pointer to within the device tree's string + * block, not a new copy of the name). + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * if namep is non-NULL *namep contiains a pointer to the property + * name. + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_getprop_by_offset(const void *fdt, int offset, + const char **namep, int *lenp); + +/** * fdt_getprop_namelen - get property value based on substring * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node whose property to find diff --git a/include/mxc_gpio.h b/include/mxc_gpio.h index 002ba61..f673dce 100644 --- a/include/mxc_gpio.h +++ b/include/mxc_gpio.h @@ -24,6 +24,11 @@ #ifndef __MXC_GPIO_H #define __MXC_GPIO_H +/* Converts a GPIO port number and the internal bit position + * to the GPIO number + */ +#define MXC_GPIO_PORT_TO_NUM(port, bit) (((port - 1) << 5) + (bit & 0x1f)) + enum mxc_gpio_direction { MXC_GPIO_DIRECTION_IN, MXC_GPIO_DIRECTION_OUT, diff --git a/lib/libfdt/fdt.c b/lib/libfdt/fdt.c index b09ea6f..4157b21 100644 --- a/lib/libfdt/fdt.c +++ b/lib/libfdt/fdt.c @@ -153,6 +153,15 @@ int _fdt_check_node_offset(const void *fdt, int offset) return offset; } +int _fdt_check_prop_offset(const void *fdt, int offset) +{ + if ((offset < 0) || (offset % FDT_TAGSIZE) + || (fdt_next_tag(fdt, offset, &offset) != FDT_PROP)) + return -FDT_ERR_BADOFFSET; + + return offset; +} + int fdt_next_node(const void *fdt, int offset, int *depth) { int nextoffset = 0; diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c index 1e1e322..1933010 100644 --- a/lib/libfdt/fdt_ro.c +++ b/lib/libfdt/fdt_ro.c @@ -109,6 +109,30 @@ int fdt_num_mem_rsv(const void *fdt) return i; } +static int _nextprop(const void *fdt, int offset) +{ + uint32_t tag; + int nextoffset; + + do { + tag = fdt_next_tag(fdt, offset, &nextoffset); + + switch (tag) { + case FDT_END: + if (nextoffset >= 0) + return -FDT_ERR_BADSTRUCTURE; + else + return nextoffset; + + case FDT_PROP: + return offset; + } + offset = nextoffset; + } while (tag == FDT_NOP); + + return -FDT_ERR_NOTFOUND; +} + int fdt_subnode_offset_namelen(const void *fdt, int offset, const char *name, int namelen) { @@ -198,52 +222,66 @@ const char *fdt_get_name(const void *fdt, int nodeoffset, int *len) return NULL; } -const struct fdt_property *fdt_get_property_namelen(const void *fdt, - int nodeoffset, - const char *name, - int namelen, int *lenp) +int fdt_first_property_offset(const void *fdt, int nodeoffset) +{ + int offset; + + if ((offset = _fdt_check_node_offset(fdt, nodeoffset)) < 0) + return offset; + + return _nextprop(fdt, offset); +} + +int fdt_next_property_offset(const void *fdt, int offset) +{ + if ((offset = _fdt_check_prop_offset(fdt, offset)) < 0) + return offset; + + return _nextprop(fdt, offset); +} + +const struct fdt_property *fdt_get_property_by_offset(const void *fdt, + int offset, + int *lenp) { - uint32_t tag; - const struct fdt_property *prop; - int offset, nextoffset; int err; + const struct fdt_property *prop; - if (((err = fdt_check_header(fdt)) != 0) - || ((err = _fdt_check_node_offset(fdt, nodeoffset)) < 0)) - goto fail; + if ((err = _fdt_check_prop_offset(fdt, offset)) < 0) { + if (lenp) + *lenp = err; + return NULL; + } - nextoffset = err; - do { - offset = nextoffset; + prop = _fdt_offset_ptr(fdt, offset); - tag = fdt_next_tag(fdt, offset, &nextoffset); - switch (tag) { - case FDT_END: - if (nextoffset < 0) - err = nextoffset; - else - /* FDT_END tag with unclosed nodes */ - err = -FDT_ERR_BADSTRUCTURE; - goto fail; + if (lenp) + *lenp = fdt32_to_cpu(prop->len); - case FDT_PROP: - prop = _fdt_offset_ptr(fdt, offset); - if (_fdt_string_eq(fdt, fdt32_to_cpu(prop->nameoff), - name, namelen)) { - /* Found it! */ - if (lenp) - *lenp = fdt32_to_cpu(prop->len); - - return prop; - } + return prop; +} + +const struct fdt_property *fdt_get_property_namelen(const void *fdt, + int offset, + const char *name, + int namelen, int *lenp) +{ + for (offset = fdt_first_property_offset(fdt, offset); + (offset >= 0); + (offset = fdt_next_property_offset(fdt, offset))) { + const struct fdt_property *prop; + + if (!(prop = fdt_get_property_by_offset(fdt, offset, lenp))) { + offset = -FDT_ERR_INTERNAL; break; } - } while ((tag != FDT_BEGIN_NODE) && (tag != FDT_END_NODE)); + if (_fdt_string_eq(fdt, fdt32_to_cpu(prop->nameoff), + name, namelen)) + return prop; + } - err = -FDT_ERR_NOTFOUND; - fail: if (lenp) - *lenp = err; + *lenp = offset; return NULL; } @@ -267,6 +305,19 @@ const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, return prop->data; } +const void *fdt_getprop_by_offset(const void *fdt, int offset, + const char **namep, int *lenp) +{ + const struct fdt_property *prop; + + prop = fdt_get_property_by_offset(fdt, offset, lenp); + if (!prop) + return NULL; + if (namep) + *namep = fdt_string(fdt, fdt32_to_cpu(prop->nameoff)); + return prop->data; +} + const void *fdt_getprop(const void *fdt, int nodeoffset, const char *name, int *lenp) { @@ -278,9 +329,14 @@ uint32_t fdt_get_phandle(const void *fdt, int nodeoffset) const uint32_t *php; int len; - php = fdt_getprop(fdt, nodeoffset, "linux,phandle", &len); - if (!php || (len != sizeof(*php))) - return 0; + /* FIXME: This is a bit sub-optimal, since we potentially scan + * over all the properties twice. */ + php = fdt_getprop(fdt, nodeoffset, "phandle", &len); + if (!php || (len != sizeof(*php))) { + php = fdt_getprop(fdt, nodeoffset, "linux,phandle", &len); + if (!php || (len != sizeof(*php))) + return 0; + } return fdt32_to_cpu(*php); } @@ -440,11 +496,27 @@ int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle) { + int offset; + if ((phandle == 0) || (phandle == -1)) return -FDT_ERR_BADPHANDLE; - phandle = cpu_to_fdt32(phandle); - return fdt_node_offset_by_prop_value(fdt, -1, "linux,phandle", - &phandle, sizeof(phandle)); + + FDT_CHECK_HEADER(fdt); + + /* FIXME: The algorithm here is pretty horrible: we + * potentially scan each property of a node in + * fdt_get_phandle(), then if that didn't find what + * we want, we scan over them again making our way to the next + * node. Still it's the easiest to implement approach; + * performance can come later. */ + for (offset = fdt_next_node(fdt, -1, NULL); + offset >= 0; + offset = fdt_next_node(fdt, offset, NULL)) { + if (fdt_get_phandle(fdt, offset) == phandle) + return offset; + } + + return offset; /* error from fdt_next_node() */ } static int _fdt_stringlist_contains(const char *strlist, int listlen, diff --git a/lib/libfdt/libfdt_internal.h b/lib/libfdt/libfdt_internal.h index d2dcbd6..381133b 100644 --- a/lib/libfdt/libfdt_internal.h +++ b/lib/libfdt/libfdt_internal.h @@ -63,6 +63,7 @@ } int _fdt_check_node_offset(const void *fdt, int offset); +int _fdt_check_prop_offset(const void *fdt, int offset); const char *_fdt_find_string(const char *strtab, int tabsize, const char *s); int _fdt_node_end_offset(void *fdt, int nodeoffset); @@ -42,4 +42,14 @@ $(HOSTOBJS): $(obj)%.o: %.c $(NOPEDOBJS): $(obj)%.o: %.c $(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTCFLAGS_$(@F)) $(HOSTCFLAGS_$(BCURDIR)) -o $@ $< -c +$(TOPDIR)/include/asm/arch/asm-offsets.h: $(TOPDIR)/include/autoconf.mk.dep \ + $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.s + @echo Generating $@ + $(TOPDIR)/tools/scripts/make-asm-offsets $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.s $@ + +$(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.s: $(TOPDIR)/include/autoconf.mk.dep \ + $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.c + $(CC) -DDO_DEPS_ONLY \ + $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \ + -o $@ $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.c -c -S ######################################################################### |