diff options
| -rw-r--r-- | board/freescale/mx6q_sabreauto/flash_header.S | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/board/freescale/mx6q_sabreauto/flash_header.S b/board/freescale/mx6q_sabreauto/flash_header.S index 3dc4790..c63ed7a 100644 --- a/board/freescale/mx6q_sabreauto/flash_header.S +++ b/board/freescale/mx6q_sabreauto/flash_header.S @@ -156,9 +156,9 @@ MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) /* enable AXI cache for VDOA/VPU/IPU */ MXC_DCD_ITEM(81, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff) -/* set IPU Qos=0x7 */ -MXC_DCD_ITEM(82, IOMUXC_BASE_ADDR + 0x018, 0x00070007) -MXC_DCD_ITEM(83, IOMUXC_BASE_ADDR + 0x01c, 0x00070007) +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +MXC_DCD_ITEM(82, IOMUXC_BASE_ADDR + 0x018, 0x007f007f) +MXC_DCD_ITEM(83, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f) #elif defined CONFIG_LPDDR2 dcd_hdr: .word 0x400804D2 /* Tag=0xD2, Len=128*8 + 4 + 4, Ver=0x40 */ @@ -453,9 +453,9 @@ MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) /* enable AXI cache for VDOA/VPU/IPU */ MXC_DCD_ITEM(86, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff) -/* set IPU Qos=0x7 */ -MXC_DCD_ITEM(87, IOMUXC_BASE_ADDR + 0x018, 0x00070007) -MXC_DCD_ITEM(88, IOMUXC_BASE_ADDR + 0x01c, 0x00070007) +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +MXC_DCD_ITEM(87, IOMUXC_BASE_ADDR + 0x018, 0x007f007f) +MXC_DCD_ITEM(88, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f) #endif #endif |