diff options
| -rw-r--r-- | Makefile | 1 | ||||
| -rw-r--r-- | board/freescale/mx53_ard/flash_header.S | 62 | ||||
| -rwxr-xr-x | board/freescale/mx53_ard/mx53_ard.c | 44 | ||||
| -rw-r--r-- | include/configs/mx53_ard_ddr3.h | 310 |
4 files changed, 413 insertions, 4 deletions
@@ -3285,6 +3285,7 @@ mx53_loco_mfg_config \ mx53_loco_config :unconfig $(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53_loco freescale mx53 +mx53_ard_ddr3_config \ mx53_ard_mfg_config \ mx53_ard_config : unconfig $(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53_ard freescale mx53 diff --git a/board/freescale/mx53_ard/flash_header.S b/board/freescale/mx53_ard/flash_header.S index 4a0712c..4db120d 100644 --- a/board/freescale/mx53_ard/flash_header.S +++ b/board/freescale/mx53_ard/flash_header.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -53,6 +53,7 @@ image_len: .word _end - TEXT_BASE plugin: .word 0x0 /* TO1.0/TO2.0 DDR2 scripts for EVK, ARD and ARM2 CPU2 board */ +#if !defined(CONFIG_MX53_ARD_DDR3) dcd_hdr: .word 0x400802D2 /* Tag=0xD2, Len=64*8 + 4 + 4, Ver=0x40 */ write_dcd_cmd: .word 0x040402CC /* Tag=0xCC, Len=64*8 + 4, Param=4 */ @@ -122,4 +123,63 @@ MXC_DCD_ITEM(62, ESDCTL_BASE_ADDR + 0x058, 0x00033335) MXC_DCD_ITEM(63, ESDCTL_BASE_ADDR + 0x01c, 0x00000000) MXC_DCD_ITEM(64, ESDCTL_BASE_ADDR + 0x040, 0x04b80003) + +#elif defined(CONFIG_MX53_ARD_DDR3) +dcd_hdr: .word 0x40A001D2 /* Tag=0xD2, Len=51*8 + 4 + 4, Ver=0x40 */ +write_dcd_cmd: .word 0x049C01CC /* Tag=0xCC, Len=51*8 + 4, Param=4 */ + +/* DCD */ +MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x554, 0x00300000) +MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x558, 0x00300040) +MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x560, 0x00300000) +MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x564, 0x00300040) +MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x568, 0x00300040) +MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x570, 0x00300000) +MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x574, 0x00300000) +MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x578, 0x00300000) +MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x57c, 0x00300040) +MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x580, 0x00300040) +MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x584, 0x00300000) +MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x588, 0x00300000) +MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x590, 0x00300040) +MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x594, 0x00300000) +MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x6f0, 0x00300000) +MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x6f4, 0x00000000) +MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x6fc, 0x00000000) +MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x714, 0x00000000) +MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x718, 0x00300000) +MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x71c, 0x00300000) +MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x720, 0x00300000) +MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x724, 0x04000000) +MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x728, 0x00300000) +MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x72c, 0x00300000) +MXC_DCD_ITEM(25, ESDCTL_BASE_ADDR + 0x088, 0x35343535) +MXC_DCD_ITEM(26, ESDCTL_BASE_ADDR + 0x090, 0x4d444c44) +MXC_DCD_ITEM(27, ESDCTL_BASE_ADDR + 0x07c, 0x01370138) +MXC_DCD_ITEM(28, ESDCTL_BASE_ADDR + 0x080, 0x013b013c) +MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x018, 0x00011740) +MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x000, 0xc3190000) +MXC_DCD_ITEM(31, ESDCTL_BASE_ADDR + 0x00c, 0x9f5152e3) +MXC_DCD_ITEM(32, ESDCTL_BASE_ADDR + 0x010, 0xb68e8a63) +MXC_DCD_ITEM(33, ESDCTL_BASE_ADDR + 0x014, 0x01ff00db) +MXC_DCD_ITEM(34, ESDCTL_BASE_ADDR + 0x02c, 0x000026d2) +MXC_DCD_ITEM(35, ESDCTL_BASE_ADDR + 0x030, 0x009f0e21) +MXC_DCD_ITEM(36, ESDCTL_BASE_ADDR + 0x008, 0x12273030) +MXC_DCD_ITEM(37, ESDCTL_BASE_ADDR + 0x004, 0x0002002d) +MXC_DCD_ITEM(38, ESDCTL_BASE_ADDR + 0x01c, 0x00008032) +MXC_DCD_ITEM(39, ESDCTL_BASE_ADDR + 0x01c, 0x00008033) +MXC_DCD_ITEM(40, ESDCTL_BASE_ADDR + 0x01c, 0x00028031) +MXC_DCD_ITEM(41, ESDCTL_BASE_ADDR + 0x01c, 0x092080b0) +MXC_DCD_ITEM(42, ESDCTL_BASE_ADDR + 0x01c, 0x04008040) +MXC_DCD_ITEM(43, ESDCTL_BASE_ADDR + 0x01c, 0x0000803a) +MXC_DCD_ITEM(44, ESDCTL_BASE_ADDR + 0x01c, 0x0000803b) +MXC_DCD_ITEM(45, ESDCTL_BASE_ADDR + 0x01c, 0x00028039) +MXC_DCD_ITEM(46, ESDCTL_BASE_ADDR + 0x01c, 0x09208138) +MXC_DCD_ITEM(47, ESDCTL_BASE_ADDR + 0x01c, 0x04008048) +MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x020, 0x00001800) +MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x040, 0x04b80003) +MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x058, 0x00022227) +MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x01C, 0x00000000) + +#endif #endif diff --git a/board/freescale/mx53_ard/mx53_ard.c b/board/freescale/mx53_ard/mx53_ard.c index 94be65b..ad3f794 100755 --- a/board/freescale/mx53_ard/mx53_ard.c +++ b/board/freescale/mx53_ard/mx53_ard.c @@ -162,6 +162,20 @@ enum boot_device get_boot_device(void) return boot_dev; } +u32 get_board_rev_from_fuse(void) +{ + u32 board_rev = readl(IIM_BASE_ADDR + 0x878); + + return board_rev; +} + +u32 get_board_id_from_fuse(void) +{ + u32 board_id = readl(IIM_BASE_ADDR + 0x87c); + + return board_id; +} + u32 get_board_rev(void) { return system_rev; @@ -170,6 +184,7 @@ u32 get_board_rev(void) static inline void setup_soc_rev(void) { int reg; + u32 board_rev = get_board_rev_from_fuse(); /* Si rev is obtained from ROM */ reg = __REG(ROM_SI_REV); @@ -184,6 +199,15 @@ static inline void setup_soc_rev(void) default: system_rev = 0x53000 | CHIP_REV_2_0; } + switch (board_rev) { + case 0x01: + system_rev |= BOARD_REV_1; + break; + case 0x02: + default: + system_rev |= BOARD_REV_2; + } + } static inline void setup_board_rev(int rev) @@ -269,6 +293,11 @@ int dram_init(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + +#if defined(CONFIG_MX53_ARD_DDR3) + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +#endif return 0; } @@ -1094,11 +1123,20 @@ int board_late_init(void) int checkboard(void) { - printf("Board: "); + printf("Board: MX53-ARD "); - printf("MX53-ARD 1.0\n"); - printf("Boot Reason: ["); + switch (get_board_rev_from_fuse()) { + case 0x2: + printf("Rev. B\n"); + break; + case 0x1: + default: + printf("Rev. A\n"); + break; + } + + printf("Boot Reason: ["); switch (__REG(SRC_BASE_ADDR + 0x8)) { case 0x0001: printf("POR"); diff --git a/include/configs/mx53_ard_ddr3.h b/include/configs/mx53_ard_ddr3.h new file mode 100644 index 0000000..3b391da --- /dev/null +++ b/include/configs/mx53_ard_ddr3.h @@ -0,0 +1,310 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX53-ARD-DDR3 Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/mx53.h> + + /* High Level Configuration Options */ +#define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU core */ +#define CONFIG_MXC +#define CONFIG_MX53 +#define CONFIG_MX53_ARD_DDR3 +#define CONFIG_FLASH_HEADER +#define CONFIG_FLASH_HEADER_OFFSET 0x400 +#define CONFIG_MX53_CLK32 32768 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MMU + +#define CONFIG_MX53_HCLK_FREQ 24000000 +#define CONFIG_SYS_PLL2_FREQ 400 +#define CONFIG_SYS_AHB_PODF 2 +#define CONFIG_SYS_AXIA_PODF 0 +#define CONFIG_SYS_AXIB_PODF 1 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MXC_UART 1 +#define CONFIG_UART_BASE_ADDR UART1_BASE_ADDR + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_NET_MULTI 1 +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +/* Enable below configure when supporting nand */ +#define CONFIG_CMD_NAND +#define CONFIG_MXC_NAND +/* NAND FLASH driver setup */ +#define CONFIG_SYS_NAND_MAX_CHIPS 8 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_NAND_FW_16BIT 0 /* 1: 16bit 0: 8bit */ + +#define CONFIG_CMD_IIM +#define CONFIG_CMD_MMC +#define CONFIG_CMD_ENV + +#define CONFIG_CMD_CLOCK +#define CONFIG_REF_CLK_FREQ CONFIG_MX53_HCLK_FREQ + +#define CONFIG_CMD_SATA +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "smc911x" + +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=smc911x\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \ + "bootcmd=run bootcmd_net\0" \ + + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX53-ARD-DDR3 U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +/*Support LAN9217*/ +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_16_BIT 1 +#define CONFIG_SMC911X_BASE CS1_BASE_ADDR + +#define CONFIG_MII +#define CONFIG_MII_GASKET +#define CONFIG_DISCOVER_PHY + +/* + * FUSE Configs + * */ +#ifdef CONFIG_CMD_IIM + #define CONFIG_IMX_IIM + #define IMX_IIM_BASE IIM_BASE_ADDR + #define CONFIG_IIM_MAC_BANK 1 + #define CONFIG_IIM_MAC_ROW 9 +#endif + +/* + * I2C Configs + */ +#define CONFIG_CMD_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MXC 1 +#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + + +/* + * SPI Configs + */ +#define CONFIG_FSL_SF 1 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_IMX_ATMEL 1 +#define CONFIG_SPI_FLASH_CS 1 +#define CONFIG_IMX_ECSPI +#define IMX_CSPI_VER_2_3 1 +#define MAX_SPI_BYTES (64 * 4) + +/* + * MMC Configs + */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC 1 + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_ESDHC_NUM 2 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 + + /* detect whether ESDHC1 or ESDHC3 is boot device */ + #define CONFIG_DYNAMIC_MMC_DEVNO + + #define CONFIG_BOOT_PARTITION_ACCESS +#endif + +/* + * SATA Configs + */ +#ifdef CONFIG_CMD_SATA + #define CONFIG_DWC_AHSATA + #define CONFIG_SYS_SATA_MAX_DEVICE 1 + #define CONFIG_DWC_AHSATA_PORT_ID 0 + #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR + #define CONFIG_LBA48 + #define CONFIG_LIBATA +#endif + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + ((addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) \ + || (addr >= PHYS_SDRAM_2 && addr <= (PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE))) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* Monitor at beginning of flash */ +#define CONFIG_FSL_ENV_IN_MMC +/* #define CONFIG_FSL_ENV_IN_SATA */ + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x100000 +#elif defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SATA) + #define CONFIG_ENV_IS_IN_SATA 1 + #define CONFIG_SATA_ENV_DEV 0 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SF) + #define CONFIG_ENV_IS_IN_SPI_FLASH 1 + #define CONFIG_ENV_SPI_CS 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif + +#ifdef CONFIG_SPLASH_SCREEN + /* + * Framebuffer and LCD + */ + #define CONFIG_LCD + #define CONFIG_VIDEO_MX5 + #define CONFIG_IPU_CLKRATE 200000000 + #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE + #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE + #define CONFIG_SYS_CONSOLE_IS_IN_ENV + #define LCD_BPP LCD_COLOR16 + #define CONFIG_CMD_BMP + #define CONFIG_BMP_8BPP + #define CONFIG_FB_BASE (TEXT_BASE + 0x300000) + #define CONFIG_SPLASH_SCREEN_ALIGN + #define CONFIG_SYS_WHITE_ON_BLACK + + #define CONFIG_IMX_PWM + #define IMX_PWM1_BASE PWM1_BASE_ADDR + #define IMX_PWM2_BASE PWM2_BASE_ADDR +#endif +#endif /* __CONFIG_H */ |