diff options
| -rw-r--r-- | Makefile | 10 | ||||
| -rw-r--r-- | board/freescale/mx53_ard/Makefile (renamed from board/freescale/mx53_rd/Makefile) | 2 | ||||
| -rw-r--r-- | board/freescale/mx53_ard/config.mk (renamed from board/freescale/mx53_rd/config.mk) | 0 | ||||
| -rw-r--r-- | board/freescale/mx53_ard/flash_header.S | 125 | ||||
| -rw-r--r-- | board/freescale/mx53_ard/lowlevel_init.S | 228 | ||||
| -rwxr-xr-x | board/freescale/mx53_ard/mx53_ard.c | 953 | ||||
| -rw-r--r-- | board/freescale/mx53_ard/u-boot.lds (renamed from board/freescale/mx53_rd/u-boot.lds) | 4 | ||||
| -rw-r--r-- | board/freescale/mx53_evk/Makefile | 49 | ||||
| -rw-r--r-- | board/freescale/mx53_evk/config.mk | 3 | ||||
| -rw-r--r-- | board/freescale/mx53_evk/flash_header.S (renamed from board/freescale/mx53_rd/flash_header.S) | 0 | ||||
| -rw-r--r-- | board/freescale/mx53_evk/lowlevel_init.S (renamed from board/freescale/mx53_rd/lowlevel_init.S) | 0 | ||||
| -rw-r--r-- | board/freescale/mx53_evk/mx53_evk.c (renamed from board/freescale/mx53_rd/mx53_rd.c) | 334 | ||||
| -rw-r--r-- | board/freescale/mx53_evk/u-boot.lds | 73 |
13 files changed, 1444 insertions, 337 deletions
@@ -3277,15 +3277,15 @@ mx51_3stack_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51_3stack freescale mx51 mx53_ard_mfg_config \ -mx53_evk_mfg_config \ +mx53_ard_config : unconfig + $(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53_ard freescale mx53 + mx53_arm2_ddr3_config \ -mx53_arm2_config \ -mx53_arm2_android_config \ mx53_arm2_ddr3_android_config \ mx53_evk_android_config \ -mx53_ard_config \ +mx53_evk_mfg_config \ mx53_evk_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53_rd freescale mx53 + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53_evk freescale mx53 omap2420h4_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx diff --git a/board/freescale/mx53_rd/Makefile b/board/freescale/mx53_ard/Makefile index 52d53bf..bb9de46 100644 --- a/board/freescale/mx53_rd/Makefile +++ b/board/freescale/mx53_ard/Makefile @@ -23,7 +23,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := mx53_rd.o +COBJS := mx53_ard.o SOBJS := lowlevel_init.o flash_header.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/freescale/mx53_rd/config.mk b/board/freescale/mx53_ard/config.mk index 34f830a..34f830a 100644 --- a/board/freescale/mx53_rd/config.mk +++ b/board/freescale/mx53_ard/config.mk diff --git a/board/freescale/mx53_ard/flash_header.S b/board/freescale/mx53_ard/flash_header.S new file mode 100644 index 0000000..4a0712c --- /dev/null +++ b/board/freescale/mx53_ard/flash_header.S @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/mx53.h> + +#ifdef CONFIG_FLASH_HEADER +#ifndef CONFIG_FLASH_HEADER_OFFSET +# error "Must define the offset of flash header" +#endif + +#define CPU_2_BE_32(l) \ + ((((l) & 0x000000FF) << 24) | \ + (((l) & 0x0000FF00) << 8) | \ + (((l) & 0x00FF0000) >> 8) | \ + (((l) & 0xFF000000) >> 24)) + +#define MXC_DCD_ITEM(i, addr, val) \ +dcd_node_##i: \ + .word CPU_2_BE_32(addr) ; \ + .word CPU_2_BE_32(val) ; \ + +.section ".text.flasheader", "x" + b _start + .org CONFIG_FLASH_HEADER_OFFSET +ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */ +app_code_jump_v: .word _start +reserv1: .word 0x0 +dcd_ptr: .word dcd_hdr +boot_data_ptr: .word boot_data +self_ptr: .word ivt_header +app_code_csf: .word 0x0 +reserv2: .word 0x0 + +boot_data: .word 0x77800000 +image_len: .word _end - TEXT_BASE +plugin: .word 0x0 + +/* TO1.0/TO2.0 DDR2 scripts for EVK, ARD and ARM2 CPU2 board */ +dcd_hdr: .word 0x400802D2 /* Tag=0xD2, Len=64*8 + 4 + 4, Ver=0x40 */ +write_dcd_cmd: .word 0x040402CC /* Tag=0xCC, Len=64*8 + 4, Param=4 */ + +/* DCD */ +MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x554, 0x00200000) +MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x560, 0x00200000) +MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x594, 0x00200000) +MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x584, 0x00200000) +MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x558, 0x00200040) +MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x568, 0x00200040) +MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x590, 0x00200040) +MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00200040) +MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x564, 0x00200040) +MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x580, 0x00200040) +MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x570, 0x00200000) +MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x578, 0x00200000) +MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x72c, 0x00200000) +MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x728, 0x00200000) +MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x71c, 0x00200000) +MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x718, 0x00200000) +MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x574, 0x00280000) +MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x588, 0x00280000) +MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x6f0, 0x00280000) +MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x720, 0x00280000) +MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x6fc, 0x00000000) +MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x6f4, 0x00000200) +MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x714, 0x00000000) +MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x724, 0x06000000) +MXC_DCD_ITEM(25, ESDCTL_BASE_ADDR + 0x088, 0x34333936) +MXC_DCD_ITEM(26, ESDCTL_BASE_ADDR + 0x090, 0x49434942) +MXC_DCD_ITEM(27, ESDCTL_BASE_ADDR + 0x0f8, 0x00000800) +MXC_DCD_ITEM(28, ESDCTL_BASE_ADDR + 0x07c, 0x01350138) +MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x080, 0x01380139) +MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x018, 0x00001710) +MXC_DCD_ITEM(31, ESDCTL_BASE_ADDR + 0x000, 0xc4110000) +MXC_DCD_ITEM(32, ESDCTL_BASE_ADDR + 0x00c, 0x4d5122d2) +MXC_DCD_ITEM(33, ESDCTL_BASE_ADDR + 0x010, 0x92d18a22) +MXC_DCD_ITEM(34, ESDCTL_BASE_ADDR + 0x014, 0x00c70092) +MXC_DCD_ITEM(35, ESDCTL_BASE_ADDR + 0x02c, 0x000026d2) +MXC_DCD_ITEM(36, ESDCTL_BASE_ADDR + 0x030, 0x009f000e) +MXC_DCD_ITEM(37, ESDCTL_BASE_ADDR + 0x008, 0x12272000) +MXC_DCD_ITEM(38, ESDCTL_BASE_ADDR + 0x004, 0x00030012) +MXC_DCD_ITEM(39, ESDCTL_BASE_ADDR + 0x01c, 0x04008010) +MXC_DCD_ITEM(40, ESDCTL_BASE_ADDR + 0x01c, 0x00008032) +MXC_DCD_ITEM(41, ESDCTL_BASE_ADDR + 0x01c, 0x00008033) +MXC_DCD_ITEM(42, ESDCTL_BASE_ADDR + 0x01c, 0x00008031) +MXC_DCD_ITEM(43, ESDCTL_BASE_ADDR + 0x01c, 0x0b5280b0) +MXC_DCD_ITEM(44, ESDCTL_BASE_ADDR + 0x01c, 0x04008010) +MXC_DCD_ITEM(45, ESDCTL_BASE_ADDR + 0x01c, 0x00008020) +MXC_DCD_ITEM(46, ESDCTL_BASE_ADDR + 0x01c, 0x00008020) +MXC_DCD_ITEM(47, ESDCTL_BASE_ADDR + 0x01c, 0x0a528030) +MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x01c, 0x03c68031) +MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x01c, 0x00448031) +MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x01c, 0x04008018) +MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x01c, 0x0000803a) +MXC_DCD_ITEM(52, ESDCTL_BASE_ADDR + 0x01c, 0x0000803b) +MXC_DCD_ITEM(53, ESDCTL_BASE_ADDR + 0x01c, 0x00008039) +MXC_DCD_ITEM(54, ESDCTL_BASE_ADDR + 0x01c, 0x0b528138) +MXC_DCD_ITEM(55, ESDCTL_BASE_ADDR + 0x01c, 0x04008018) +MXC_DCD_ITEM(56, ESDCTL_BASE_ADDR + 0x01c, 0x00008028) +MXC_DCD_ITEM(57, ESDCTL_BASE_ADDR + 0x01c, 0x00008028) +MXC_DCD_ITEM(58, ESDCTL_BASE_ADDR + 0x01c, 0x0a528038) +MXC_DCD_ITEM(59, ESDCTL_BASE_ADDR + 0x01c, 0x03c68039) +MXC_DCD_ITEM(60, ESDCTL_BASE_ADDR + 0x01c, 0x00448039) +MXC_DCD_ITEM(61, ESDCTL_BASE_ADDR + 0x020, 0x00005800) +MXC_DCD_ITEM(62, ESDCTL_BASE_ADDR + 0x058, 0x00033335) +MXC_DCD_ITEM(63, ESDCTL_BASE_ADDR + 0x01c, 0x00000000) +MXC_DCD_ITEM(64, ESDCTL_BASE_ADDR + 0x040, 0x04b80003) + +#endif diff --git a/board/freescale/mx53_ard/lowlevel_init.S b/board/freescale/mx53_ard/lowlevel_init.S new file mode 100644 index 0000000..32f8ee3 --- /dev/null +++ b/board/freescale/mx53_ard/lowlevel_init.S @@ -0,0 +1,228 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/mx53.h> + +/* + * L2CC Cache setup/invalidation/disable + */ +.macro init_l2cc + /* explicitly disable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + bic r0, r0, #0x2 + mcr 15, 0, r0, c1, c0, 1 + + /* reconfigure L2 cache aux control reg */ + mov r0, #0xC0 /* tag RAM */ + add r0, r0, #0x4 /* data RAM */ + orr r0, r0, #(1 << 24) /* disable write allocate delay */ + orr r0, r0, #(1 << 23) /* disable write allocate combine */ + orr r0, r0, #(1 << 22) /* disable write allocate */ + + mcr 15, 1, r0, c9, c0, 2 +.endm /* init_l2cc */ + +/* AIPS setup - Only setup MPROTx registers. + * The PACR default values are good.*/ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =0x77777777 + str r1, [r0, #0x0] + str r1, [r0, #0x4] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x0] + str r1, [r0, #0x4] +.endm /* init_aips */ + +.macro setup_pll pll, freq + ldr r0, =\pll + ldr r1, =0x00001232 + str r1, [r0, #PLL_DP_CTL] + mov r1, #0x2 + str r1, [r0, #PLL_DP_CONFIG] + + ldr r1, W_DP_OP_\freq + str r1, [r0, #PLL_DP_OP] + str r1, [r0, #PLL_DP_HFS_OP] + + ldr r1, W_DP_MFD_\freq + str r1, [r0, #PLL_DP_MFD] + str r1, [r0, #PLL_DP_HFS_MFD] + + ldr r1, W_DP_MFN_\freq + str r1, [r0, #PLL_DP_MFN] + str r1, [r0, #PLL_DP_HFS_MFN] + + ldr r1, =0x00001232 + str r1, [r0, #PLL_DP_CTL] +1: ldr r1, [r0, #PLL_DP_CTL] + ands r1, r1, #0x1 + beq 1b +.endm + +.macro init_clock + ldr r0, =ROM_SI_REV + ldr r1, [r0] + cmp r1, #0x20 + + /* For TO2 only, set LDO to 1.3V */ + ldr r0, =0x53fa8000 + ldr r1, =0x00194005 + streq r1, [r0, #0x04] + + ldr r0, CCM_BASE_ADDR_W + + /* Switch ARM to step clock */ + mov r1, #0x4 + str r1, [r0, #CLKCTL_CCSR] + + setup_pll PLL1_BASE_ADDR, 800 + + setup_pll PLL3_BASE_ADDR, 400 + + /* Switch peripheral to PLL3 */ + ldr r0, CCM_BASE_ADDR_W + ldr r1, CCM_VAL_0x00015154 + str r1, [r0, #CLKCTL_CBCMR] + ldr r1, CCM_VAL_0x02888945 + orr r1, r1, #(1 << 16) + str r1, [r0, #CLKCTL_CBCDR] + /* make sure change is effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + setup_pll PLL2_BASE_ADDR, CONFIG_SYS_PLL2_FREQ + + /* Switch peripheral to PLL2 */ + ldr r0, CCM_BASE_ADDR_W + ldr r1, CCM_VAL_0x00808145 + orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10) + orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16) + orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19) + str r1, [r0, #CLKCTL_CBCDR] + + ldr r1, CCM_VAL_0x00016154 + str r1, [r0, #CLKCTL_CBCMR] + + /* make sure change is effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + setup_pll PLL3_BASE_ADDR, 216 + + /* Set the platform clock dividers */ + ldr r0, PLATFORM_BASE_ADDR_W + ldr r1, PLATFORM_CLOCK_DIV_W + str r1, [r0, #PLATFORM_ICGC] + + ldr r0, CCM_BASE_ADDR_W + mov r1, #0 + str r1, [r0, #CLKCTL_CACRR] + + /* Switch ARM back to PLL 1. */ + mov r1, #0x0 + str r1, [r0, #CLKCTL_CCSR] + + ldr r1, [r0, #CLKCTL_CSCDR1] + orr r1, r1, #0x3f + eor r1, r1, #0x3f + orr r1, r1, #0x21 + str r1, [r0, #CLKCTL_CSCDR1] + + /* Restore the default values in the Gate registers */ + ldr r1, =0xFFFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + str r1, [r0, #CLKCTL_CCGR4] + str r1, [r0, #CLKCTL_CCGR5] + str r1, [r0, #CLKCTL_CCGR6] + str r1, [r0, #CLKCTL_CCGR7] + + mov r1, #0x00000 + str r1, [r0, #CLKCTL_CCDR] + + /* for cko - for ARM div by 8 */ + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] +.endm + +.section ".text.init", "x" + +.globl lowlevel_init +lowlevel_init: + +#ifdef ENABLE_IMPRECISE_ABORT + mrs r1, spsr /* save old spsr */ + mrs r0, cpsr /* read out the cpsr */ + bic r0, r0, #0x100 /* clear the A bit */ + msr spsr, r0 /* update spsr */ + add lr, pc, #0x8 /* update lr */ + movs pc, lr /* update cpsr */ + nop + nop + nop + nop + msr spsr, r1 /* restore old spsr */ +#endif + + /* ARM errata ID #468414 */ + mrc 15, 0, r1, c1, c0, 1 + orr r1, r1, #(1 << 5) /* enable L1NEON bit */ + mcr 15, 0, r1, c1, c0, 1 + + init_l2cc + + init_aips + + init_clock + + mov pc, lr + +/* Board level setting value */ +CCM_BASE_ADDR_W: .word CCM_BASE_ADDR +CCM_VAL_0x00016154: .word 0x00016154 +CCM_VAL_0x00808145: .word 0x00808145 +CCM_VAL_0x00015154: .word 0x00015154 +CCM_VAL_0x02888945: .word 0x02888945 +W_DP_OP_800: .word DP_OP_800 +W_DP_MFD_800: .word DP_MFD_800 +W_DP_MFN_800: .word DP_MFN_800 +W_DP_OP_600: .word DP_OP_600 +W_DP_MFD_600: .word DP_MFD_600 +W_DP_MFN_600: .word DP_MFN_600 +W_DP_OP_400: .word DP_OP_400 +W_DP_MFD_400: .word DP_MFD_400 +W_DP_MFN_400: .word DP_MFN_400 +W_DP_OP_216: .word DP_OP_216 +W_DP_MFD_216: .word DP_MFD_216 +W_DP_MFN_216: .word DP_MFN_216 +PLATFORM_BASE_ADDR_W: .word ARM_BASE_ADDR +PLATFORM_CLOCK_DIV_W: .word 0x00000124 diff --git a/board/freescale/mx53_ard/mx53_ard.c b/board/freescale/mx53_ard/mx53_ard.c new file mode 100755 index 0000000..ffc2498 --- /dev/null +++ b/board/freescale/mx53_ard/mx53_ard.c @@ -0,0 +1,953 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mx53.h> +#include <asm/arch/mx53_pins.h> +#include <asm/arch/iomux.h> +#include <asm/errno.h> +#include <imx_spi.h> +#include <netdev.h> + +#if CONFIG_I2C_MXC +#include <i2c.h> +#endif + +#ifdef CONFIG_CMD_MMC +#include <mmc.h> +#include <fsl_esdhc.h> +#endif + +#ifdef CONFIG_ARCH_MMU +#include <asm/mmu.h> +#include <asm/arch/mmu.h> +#endif + +#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#include <asm/imx_iim.h> +#endif + +#ifdef CONFIG_CMD_CLOCK +#include <asm/clock.h> +#endif + +#ifdef CONFIG_ANDROID_RECOVERY +#include "../common/recovery.h" +#include <part.h> +#include <ext2fs.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <ubi_uboot.h> +#include <jffs2/load_kernel.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static u32 system_rev; +static enum boot_device boot_dev; + +static inline void setup_boot_device(void) +{ + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ; + uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3; + + switch (bt_mem_ctl) { + case 0x0: + if (bt_mem_type) + boot_dev = ONE_NAND_BOOT; + else + boot_dev = WEIM_NOR_BOOT; + break; + case 0x2: + if (bt_mem_type) + boot_dev = SATA_BOOT; + else + boot_dev = PATA_BOOT; + break; + case 0x3: + if (bt_mem_type) + boot_dev = SPI_NOR_BOOT; + else + boot_dev = I2C_BOOT; + break; + case 0x4: + case 0x5: + boot_dev = SD_BOOT; + break; + case 0x6: + case 0x7: + boot_dev = MMC_BOOT; + break; + case 0x8 ... 0xf: + boot_dev = NAND_BOOT; + break; + default: + boot_dev = UNKNOWN_BOOT; + break; + } +} + +enum boot_device get_boot_device(void) +{ + return boot_dev; +} + +u32 get_board_rev(void) +{ + return system_rev; +} + +static inline void setup_soc_rev(void) +{ + int reg; + + /* Si rev is obtained from ROM */ + reg = __REG(ROM_SI_REV); + + switch (reg) { + case 0x10: + system_rev = 0x53000 | CHIP_REV_1_0; + break; + case 0x20: + system_rev = 0x53000 | CHIP_REV_2_0; + break; + default: + system_rev = 0x53000 | CHIP_REV_2_0; + } +} + +static inline void setup_board_rev(int rev) +{ + system_rev |= (rev & 0xF) << 8; +} + +inline int is_soc_rev(int rev) +{ + return (system_rev & 0xFF) - rev; +} + +#ifdef CONFIG_ARCH_MMU +void board_mmu_init(void) +{ + unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000; + unsigned long i; + + /* + * Set the TTB register + */ + asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/); + + /* + * Set the Domain Access Control Register + */ + i = ARM_ACCESS_DACR_DEFAULT; + asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/); + + /* + * First clear all TT entries - ie Set them to Faulting + */ + memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); + /* Actual Virtual Size Attributes Function */ + /* Base Base MB cached? buffered? access permissions */ + /* xxx00000 xxx00000 */ + X_ARM_MMU_SECTION(0x000, 0x000, 0x10, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* ROM, 16M */ + X_ARM_MMU_SECTION(0x070, 0x070, 0x010, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* IRAM */ + X_ARM_MMU_SECTION(0x100, 0x100, 0x040, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* SATA */ + X_ARM_MMU_SECTION(0x180, 0x180, 0x100, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* IPUv3M */ + X_ARM_MMU_SECTION(0x200, 0x200, 0x200, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* GPU */ + X_ARM_MMU_SECTION(0x400, 0x400, 0x300, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* periperals */ + X_ARM_MMU_SECTION(0x700, 0x700, 0x400, + ARM_CACHEABLE, ARM_BUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */ + X_ARM_MMU_SECTION(0x700, 0xB00, 0x400, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */ + X_ARM_MMU_SECTION(0xF00, 0xF00, 0x100, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/ + X_ARM_MMU_SECTION(0xF7F, 0xF7F, 0x040, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* NAND Flash buffer */ + X_ARM_MMU_SECTION(0xF80, 0xF80, 0x001, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* iRam */ + + /* Workaround for arm errata #709718 */ + /* Setup PRRR so device is always mapped to non-shared */ + asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/); + i &= (~(3 << 0x10)); + asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/); + + /* Enable MMU */ + MMU_ON(); +} +#endif + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + return 0; +} + +static void setup_uart(void) +{ + /* UART1 TXD */ + mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX53_PIN_ATA_DIOW, 0x1E4); + + /* UART1 RXD */ + mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3); + mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3); + mxc_iomux_set_pad(MX53_PIN_ATA_DMACK, 0x1E4); +} + +#ifdef CONFIG_I2C_MXC +static void setup_i2c(unsigned int module_base) +{ + switch (module_base) { + case I2C1_BASE_ADDR: + /* No device is connected via I2C1 on ARD */ + break; + case I2C2_BASE_ADDR: + /* i2c2 SDA */ + mxc_request_iomux(MX53_PIN_KEY_ROW3, + IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_KEY_ROW3, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + + mxc_request_iomux(MX53_PIN_EIM_EB2, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH1); + mxc_iomux_set_pad(MX53_PIN_EIM_EB2, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + break; + case I2C3_BASE_ADDR: + /* GPIO_3 for I2C3_SCL */ + mxc_request_iomux(MX53_PIN_GPIO_3, + IOMUX_CONFIG_ALT2 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C3_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH1); + mxc_iomux_set_pad(MX53_PIN_GPIO_3, + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_360K_PD | + PAD_CTL_HYS_ENABLE); + /* GPIO_16 for I2C3_SDA */ + mxc_request_iomux(MX53_PIN_GPIO_16, + IOMUX_CONFIG_ALT6 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C3_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH2); + mxc_iomux_set_pad(MX53_PIN_GPIO_16, + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_360K_PD | + PAD_CTL_HYS_ENABLE); + break; + default: + printf("Invalid I2C base: 0x%x\n", module_base); + break; + } +} +#endif + +#ifdef CONFIG_IMX_ECSPI +s32 spi_get_cfg(struct imx_spi_dev_t *dev) +{ + switch (dev->slave.cs) { + case 0: + /* pmic */ + dev->base = CSPI1_BASE_ADDR; + dev->freq = 2500000; + dev->ss_pol = IMX_SPI_ACTIVE_HIGH; + dev->ss = 0; + dev->fifo_sz = 64 * 4; + dev->us_delay = 0; + break; + case 1: + /* spi_nor */ + dev->base = CSPI1_BASE_ADDR; + dev->freq = 2500000; + dev->ss_pol = IMX_SPI_ACTIVE_LOW; + dev->ss = 1; + dev->fifo_sz = 64 * 4; + dev->us_delay = 0; + break; + default: + printf("Invalid Bus ID!\n"); + break; + } + + return 0; +} + +void spi_io_init(struct imx_spi_dev_t *dev) +{ + switch (dev->base) { + case CSPI1_BASE_ADDR: + /* Select mux mode: ALT4 mux port: MOSI of instance: ecspi1 */ + mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0x104); + mxc_iomux_set_input( + MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT, 0x3); + + /* Select mux mode: ALT4 mux port: MISO of instance: ecspi1. */ + mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0x104); + mxc_iomux_set_input( + MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT, 0x3); + + if (dev->ss == 0) { + /* de-select SS1 of instance: ecspi1. */ + mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0x1E4); + + /* mux mode: ALT4 mux port: SS0 of instance: ecspi1. */ + mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_EB2, 0x104); + mxc_iomux_set_input( + MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, 0x3); + } else if (dev->ss == 1) { + /* de-select SS0 of instance: ecspi1. */ + mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX53_PIN_EIM_EB2, 0x1E4); + + /* mux mode: ALT0 mux port: SS1 of instance: ecspi1. */ + mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0x104); + mxc_iomux_set_input( + MUX_IN_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT, 0x2); + } + + /* Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ + mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0x104); + mxc_iomux_set_input( + MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x3); + break; + + case CSPI2_BASE_ADDR: + default: + + break; + } +} +#endif + +#ifdef CONFIG_NET_MULTI +int board_eth_init(bd_t *bis) +{ + int rc = -ENODEV; +#if defined(CONFIG_SMC911X) + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + + return rc; +} +#endif + +void weim_smc911x_iomux() +{ + unsigned int reg; + + /* ETHERNET_INT_B as GPIO2_31 */ + mxc_request_iomux(MX53_PIN_EIM_EB3, + IOMUX_CONFIG_ALT1); + reg = readl(GPIO2_BASE_ADDR + 0x4); + reg &= ~(0x80000000); + writel(reg, GPIO2_BASE_ADDR + 0x4); + + /* Data bus */ + mxc_request_iomux(MX53_PIN_EIM_D16, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D17, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D18, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D19, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D20, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D20, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D21, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D21, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D22, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D22, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D23, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D23, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D24, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D24, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D25, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D25, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D26, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D26, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D27, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D27, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D28, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D28, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D29, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D29, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D30, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D30, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D31, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D31, 0xA4); + + /* Address lines */ + mxc_request_iomux(MX53_PIN_EIM_DA0, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA0, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_DA1, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA1, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_DA2, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA2, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_DA3, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA3, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_DA4, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA4, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_DA5, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA5, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_DA6, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA6, 0xA4); + + /* other EIM signals for ethernet */ + mxc_request_iomux(MX53_PIN_EIM_OE, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_EIM_RW, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_EIM_CS1, + IOMUX_CONFIG_ALT0); + +} + +void weim_cs1_settings() +{ + unsigned int reg; + + writel(0x20001, (WEIM_BASE_ADDR + 0x18)); + writel(0x0, (WEIM_BASE_ADDR + 0x1C)); + writel(0x16000202, (WEIM_BASE_ADDR + 0x20)); + writel(0x00000002, (WEIM_BASE_ADDR + 0x24)); + writel(0x16002082, (WEIM_BASE_ADDR + 0x28)); + writel(0x00000000, (WEIM_BASE_ADDR + 0x2C)); + writel(0x00000000, (WEIM_BASE_ADDR + 0x90)); + + /* specify 64 MB on CS1 and CS0 */ + reg = readl(IOMUXC_BASE_ADDR + 0x4); + reg &= ~0x3F; + reg |= 0x1B; + writel(reg, (IOMUXC_BASE_ADDR + 0x4)); +} + +#ifdef CONFIG_CMD_MMC + +#if defined(CONFIG_MX53_ARD) +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR, 1, 1}, + {MMC_SDHC2_BASE_ADDR, 1, 1}, +}; +#else +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR, 1, 1}, + {MMC_SDHC3_BASE_ADDR, 1, 1}, +}; +#endif + +#ifdef CONFIG_DYNAMIC_MMC_DEVNO +int get_mmc_env_devno() +{ + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + return (soc_sbmr & 0x00300000) ? 1 : 0; +} +#endif + +#ifdef CONFIG_EMMC_DDR_PORT_DETECT +int detect_mmc_emmc_ddr_port(struct fsl_esdhc_cfg *cfg) +{ + return (MMC_SDHC3_BASE_ADDR == cfg->esdhc_base) ? 1 : 0; +} +#endif + +int esdhc_gpio_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; + ++index) { + switch (index) { + case 0: + mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0); + + mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4); + mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4); + break; + case 1: + mxc_request_iomux(MX53_PIN_SD2_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX53_PIN_SD2_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX53_PIN_SD2_DATA0, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD2_DATA1, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD2_DATA2, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD2_DATA3, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_ATA_DATA12, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_DATA13, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_DATA14, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_DATA15, + IOMUX_CONFIG_ALT2); + + mxc_iomux_set_pad(MX53_PIN_SD2_CMD, 0x1E4); + mxc_iomux_set_pad(MX53_PIN_SD2_CLK, 0xD4); + mxc_iomux_set_pad(MX53_PIN_SD2_DATA0, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD2_DATA1, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD2_DATA2, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD2_DATA3, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA12, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA13, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA14, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA15, 0x1D4); + + break; + default: + printf("Warning: you configured more ESDHC controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return status; + break; + } + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + } + + return status; +} + +int board_mmc_init(bd_t *bis) +{ + if (!esdhc_gpio_init(bis)) + return 0; + else + return -1; +} + +#endif + +#ifdef CONFIG_MXC_NAND +void setup_nfc(void) +{ + u32 i, reg; + #define M4IF_GENP_WEIM_MM_MASK 0x00000001 + #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000 + + reg = __raw_readl(M4IF_BASE_ADDR + 0xc); + reg &= ~M4IF_GENP_WEIM_MM_MASK; + __raw_writel(reg, M4IF_BASE_ADDR + 0xc); + for (i = 0x4; i < 0x94; i += 0x18) { + reg = __raw_readl(WEIM_BASE_ADDR + i); + reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK; + __raw_writel(reg, WEIM_BASE_ADDR + i); + } + + /* To be compatible with some old NAND flash, + * limit NFC clocks as 34MHZ. The user can modify + * it according to dedicate NAND flash + */ + clk_config(0, 34, NFC_CLK); + + mxc_request_iomux(MX53_PIN_NANDF_CS0, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, + PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_NANDF_CS1, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_CS1, + PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_NANDF_RB0, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_100K_PU); + mxc_request_iomux(MX53_PIN_NANDF_CLE, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, + PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_NANDF_ALE, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, + PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_NANDF_WP_B, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_100K_PU); + mxc_request_iomux(MX53_PIN_NANDF_RE_B, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, + PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_NANDF_WE_B, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, + PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA0, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA0, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA1, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA1, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA2, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA2, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA3, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA3, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA4, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA4, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA5, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA5, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA6, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA6, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA7, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA7, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_DRV_HIGH); +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_MFG +/* MFG firmware need reset usb to avoid host crash firstly */ +#define USBCMD 0x140 + int val = readl(OTG_BASE_ADDR + USBCMD); + val &= ~0x1; /*RS bit*/ + writel(val, OTG_BASE_ADDR + USBCMD); +#endif + setup_boot_device(); + setup_soc_rev(); + + gd->bd->bi_arch_number = MACH_TYPE_MX53_ARD; + + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + setup_uart(); + +#ifdef CONFIG_MXC_NAND + setup_nfc(); +#endif + +#ifdef CONFIG_I2C_MXC + setup_i2c(CONFIG_SYS_I2C_PORT); +#endif + + weim_smc911x_iomux(); + weim_cs1_settings(); + return 0; +} + + +#ifdef CONFIG_ANDROID_RECOVERY +struct reco_envs supported_reco_envs[BOOT_DEV_NUM] = { + { + .cmd = NULL, + .args = NULL, + }, + { + .cmd = NULL, + .args = NULL, + }, + { + .cmd = NULL, + .args = NULL, + }, + { + .cmd = NULL, + .args = NULL, + }, + { + .cmd = NULL, + .args = NULL, + }, + { + .cmd = NULL, + .args = NULL, + }, + { + .cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC, + .args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC, + }, + { + .cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC, + .args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC, + }, + { + .cmd = NULL, + .args = NULL, + }, +}; + +int check_recovery_cmd_file(void) +{ + disk_partition_t info; + ulong part_length; + int filelen; + char *env; + + /* For test only */ + /* When detecting android_recovery_switch, + * enter recovery mode directly */ + env = getenv("android_recovery_switch"); + if (!strcmp(env, "1")) { + printf("Env recovery detected!\nEnter recovery mode!\n"); + return 1; + } + + printf("Checking for recovery command file...\n"); + switch (get_boot_device()) { + case MMC_BOOT: + case SD_BOOT: + { + block_dev_desc_t *dev_desc = NULL; + struct mmc *mmc = find_mmc_device(0); + + dev_desc = get_dev("mmc", 0); + + if (NULL == dev_desc) { + puts("** Block device MMC 0 not supported\n"); + return 0; + } + + mmc_init(mmc); + + if (get_partition_info(dev_desc, + CONFIG_ANDROID_CACHE_PARTITION_MMC, + &info)) { + printf("** Bad partition %d **\n", + CONFIG_ANDROID_CACHE_PARTITION_MMC); + return 0; + } + + part_length = ext2fs_set_blk_dev(dev_desc, + CONFIG_ANDROID_CACHE_PARTITION_MMC); + if (part_length == 0) { + printf("** Bad partition - mmc 0:%d **\n", + CONFIG_ANDROID_CACHE_PARTITION_MMC); + ext2fs_close(); + return 0; + } + + if (!ext2fs_mount(part_length)) { + printf("** Bad ext2 partition or " + "disk - mmc 0:%d **\n", + CONFIG_ANDROID_CACHE_PARTITION_MMC); + ext2fs_close(); + return 0; + } + + filelen = ext2fs_open(CONFIG_ANDROID_RECOVERY_CMD_FILE); + + ext2fs_close(); + } + break; + case NAND_BOOT: + return 0; + break; + case SPI_NOR_BOOT: + return 0; + break; + case UNKNOWN_BOOT: + default: + return 0; + break; + } + + return (filelen > 0) ? 1 : 0; + +} +#endif + +int board_late_init(void) +{ + return 0; +} + +int checkboard(void) +{ + printf("Board: "); + + printf("MX53-ARD 1.0\n"); + printf("Boot Reason: ["); + + switch (__REG(SRC_BASE_ADDR + 0x8)) { + case 0x0001: + printf("POR"); + break; + case 0x0009: + printf("RST"); + break; + case 0x0010: + case 0x0011: + printf("WDOG"); + break; + default: + printf("unknown"); + } + printf("]\n"); + + printf("Boot Device: "); + switch (get_boot_device()) { + case WEIM_NOR_BOOT: + printf("NOR\n"); + break; + case ONE_NAND_BOOT: + printf("ONE NAND\n"); + break; + case PATA_BOOT: + printf("PATA\n"); + break; + case SATA_BOOT: + printf("SATA\n"); + break; + case I2C_BOOT: + printf("I2C\n"); + break; + case SPI_NOR_BOOT: + printf("SPI NOR\n"); + break; + case SD_BOOT: + printf("SD\n"); + break; + case MMC_BOOT: + printf("MMC\n"); + break; + case NAND_BOOT: + printf("NAND\n"); + break; + case UNKNOWN_BOOT: + default: + printf("UNKNOWN\n"); + break; + } + return 0; +} diff --git a/board/freescale/mx53_rd/u-boot.lds b/board/freescale/mx53_ard/u-boot.lds index c6315c9..acb2e28 100644 --- a/board/freescale/mx53_rd/u-boot.lds +++ b/board/freescale/mx53_ard/u-boot.lds @@ -38,9 +38,9 @@ SECTIONS { /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - board/freescale/mx53_rd/flash_header.o (.text.flasheader) + board/freescale/mx53_ard/flash_header.o (.text.flasheader) cpu/arm_cortexa8/start.o - board/freescale/mx53_rd/libmx53_rd.a (.text) + board/freescale/mx53_ard/libmx53_ard.a (.text) lib_arm/libarm.a (.text) net/libnet.a (.text) drivers/mtd/libmtd.a (.text) diff --git a/board/freescale/mx53_evk/Makefile b/board/freescale/mx53_evk/Makefile new file mode 100644 index 0000000..9e20903 --- /dev/null +++ b/board/freescale/mx53_evk/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2010 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx53_evk.o +SOBJS := lowlevel_init.o flash_header.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx53_evk/config.mk b/board/freescale/mx53_evk/config.mk new file mode 100644 index 0000000..34f830a --- /dev/null +++ b/board/freescale/mx53_evk/config.mk @@ -0,0 +1,3 @@ +LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds + +TEXT_BASE = 0x77800000 diff --git a/board/freescale/mx53_rd/flash_header.S b/board/freescale/mx53_evk/flash_header.S index 8496789..8496789 100644 --- a/board/freescale/mx53_rd/flash_header.S +++ b/board/freescale/mx53_evk/flash_header.S diff --git a/board/freescale/mx53_rd/lowlevel_init.S b/board/freescale/mx53_evk/lowlevel_init.S index 4c5d78d..4c5d78d 100644 --- a/board/freescale/mx53_rd/lowlevel_init.S +++ b/board/freescale/mx53_evk/lowlevel_init.S diff --git a/board/freescale/mx53_rd/mx53_rd.c b/board/freescale/mx53_evk/mx53_evk.c index 061b65b..bb682d8 100644 --- a/board/freescale/mx53_rd/mx53_rd.c +++ b/board/freescale/mx53_evk/mx53_evk.c @@ -227,17 +227,6 @@ int dram_init(void) static void setup_uart(void) { -#if defined(CONFIG_MX53_ARD) - /* UART1 TXD */ - mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3); - mxc_iomux_set_pad(MX53_PIN_ATA_DIOW, 0x1E4); - - /* UART1 RXD */ - mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3); - mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3); - mxc_iomux_set_pad(MX53_PIN_ATA_DMACK, 0x1E4); -#else - /* MX53 EVK and ARM2 board */ /* UART1 RXD */ mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2); mxc_iomux_set_pad(MX53_PIN_CSI0_D11, 0x1E4); @@ -246,7 +235,6 @@ static void setup_uart(void) /* UART1 TXD */ mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2); mxc_iomux_set_pad(MX53_PIN_CSI0_D10, 0x1E4); -#endif } #ifdef CONFIG_I2C_MXC @@ -254,10 +242,6 @@ static void setup_i2c(unsigned int module_base) { switch (module_base) { case I2C1_BASE_ADDR: -#if defined(CONFIG_MX53_ARD) - /* No device is connected via I2C1 on ARD */ - break; -#else /* i2c1 SDA */ mxc_request_iomux(MX53_PIN_CSI0_D8, IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); @@ -276,7 +260,6 @@ static void setup_i2c(unsigned int module_base) PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE); -#endif break; case I2C2_BASE_ADDR: /* i2c2 SDA */ @@ -290,17 +273,6 @@ static void setup_i2c(unsigned int module_base) PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE); -#if defined(CONFIG_MX53_ARD) - mxc_request_iomux(MX53_PIN_EIM_EB2, - IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); - mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, - INPUT_CTL_PATH1); - mxc_iomux_set_pad(MX53_PIN_EIM_EB2, - PAD_CTL_SRE_FAST | - PAD_CTL_ODE_OPENDRAIN_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | - PAD_CTL_HYS_ENABLE); -#else /* i2c2 SCL */ mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); @@ -312,31 +284,9 @@ static void setup_i2c(unsigned int module_base) PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE); -#endif break; case I2C3_BASE_ADDR: -#if defined(CONFIG_MX53_ARD) - /* GPIO_3 for I2C3_SCL */ - mxc_request_iomux(MX53_PIN_GPIO_3, - IOMUX_CONFIG_ALT2 | IOMUX_CONFIG_SION); - mxc_iomux_set_input(MUX_IN_I2C3_IPP_SCL_IN_SELECT_INPUT, - INPUT_CTL_PATH1); - mxc_iomux_set_pad(MX53_PIN_GPIO_3, - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_360K_PD | - PAD_CTL_HYS_ENABLE); - /* GPIO_16 for I2C3_SDA */ - mxc_request_iomux(MX53_PIN_GPIO_16, - IOMUX_CONFIG_ALT6 | IOMUX_CONFIG_SION); - mxc_iomux_set_input(MUX_IN_I2C3_IPP_SDA_IN_SELECT_INPUT, - INPUT_CTL_PATH1); - mxc_iomux_set_pad(MX53_PIN_GPIO_16, - PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_360K_PD | - PAD_CTL_HYS_ENABLE); -#else /* No device is connected via I2C3 in EVK and ARM2 */ -#endif break; default: printf("Invalid I2C base: 0x%x\n", module_base); @@ -346,7 +296,7 @@ static void setup_i2c(unsigned int module_base) void setup_core_voltages(void) { -#if !defined(CONFIG_MX53_ARD) + unsigned char buf[4] = { 0 }; i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); @@ -385,12 +335,11 @@ void setup_core_voltages(void) /* need to delay 100 ms to allow power supplies to ramp-up */ udelay(100000); -#endif + /* Raise the core frequency to 800MHz */ writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR); } -#if defined(CONFIG_MX53_EVK) || defined(CONFIG_MX53_ARM2_DDR3) static int __read_adc_channel(unsigned int chan) { unsigned char buf[4] = { 0 }; @@ -591,7 +540,6 @@ int identify_board_id(void) } #endif -#endif #ifdef CONFIG_IMX_ECSPI s32 spi_get_cfg(struct imx_spi_dev_t *dev) @@ -616,7 +564,7 @@ s32 spi_get_cfg(struct imx_spi_dev_t *dev) dev->us_delay = 0; break; default: - printf("Invalid Bus ID! \n"); + printf("Invalid Bus ID!\n"); break; } @@ -782,164 +730,17 @@ int setup_mxc_kpd(void) int board_eth_init(bd_t *bis) { int rc = -ENODEV; -#if defined(CONFIG_SMC911X) - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif return rc; } #endif -#if defined(CONFIG_MX53_ARD) -void weim_smc911x_iomux() -{ - unsigned int reg; - - /* ETHERNET_INT_B as GPIO2_31 */ - mxc_request_iomux(MX53_PIN_EIM_EB3, - IOMUX_CONFIG_ALT1); - reg = readl(GPIO2_BASE_ADDR + 0x4); - reg &= ~(0x80000000); - writel(reg, GPIO2_BASE_ADDR + 0x4); - - /* Data bus */ - mxc_request_iomux(MX53_PIN_EIM_D16, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D17, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D18, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D19, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D20, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D20, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D21, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D21, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D22, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D22, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D23, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D23, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D24, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D24, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D25, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D25, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D26, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D26, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D27, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D27, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D28, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D28, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D29, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D29, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D30, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D30, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_D31, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_D31, 0xA4); - - /* Address lines */ - mxc_request_iomux(MX53_PIN_EIM_DA0, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA0, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_DA1, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA1, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_DA2, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA2, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_DA3, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA3, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_DA4, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA4, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_DA5, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA5, 0xA4); - - mxc_request_iomux(MX53_PIN_EIM_DA6, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA6, 0xA4); - - /* other EIM signals for ethernet */ - mxc_request_iomux(MX53_PIN_EIM_OE, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_EIM_RW, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_EIM_CS1, - IOMUX_CONFIG_ALT0); - -} - -void weim_cs1_settings() -{ - unsigned int reg; - - writel(0x20001, (WEIM_BASE_ADDR + 0x18)); - writel(0x0, (WEIM_BASE_ADDR + 0x1C)); - writel(0x16000202, (WEIM_BASE_ADDR + 0x20)); - writel(0x00000002, (WEIM_BASE_ADDR + 0x24)); - writel(0x16002082, (WEIM_BASE_ADDR + 0x28)); - writel(0x00000000, (WEIM_BASE_ADDR + 0x2C)); - writel(0x00000000, (WEIM_BASE_ADDR + 0x90)); - - /* specify 64 MB on CS1 and CS0 */ - reg = readl(IOMUXC_BASE_ADDR + 0x4); - reg &= ~0x3F; - reg |= 0x1B; - writel(reg, (IOMUXC_BASE_ADDR + 0x4)); -} -#endif - - #ifdef CONFIG_CMD_MMC -#if defined(CONFIG_MX53_ARD) -struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC1_BASE_ADDR, 1, 1}, - {MMC_SDHC2_BASE_ADDR, 1, 1}, -}; -#else struct fsl_esdhc_cfg esdhc_cfg[2] = { {MMC_SDHC1_BASE_ADDR, 1, 1}, {MMC_SDHC3_BASE_ADDR, 1, 1}, }; -#endif #ifdef CONFIG_DYNAMIC_MMC_DEVNO int get_mmc_env_devno() @@ -984,40 +785,6 @@ int esdhc_gpio_init(bd_t *bis) mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4); break; case 1: -#if defined(CONFIG_MX53_ARD) - mxc_request_iomux(MX53_PIN_SD2_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX53_PIN_SD2_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_request_iomux(MX53_PIN_SD2_DATA0, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD2_DATA1, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD2_DATA2, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_SD2_DATA3, - IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_ATA_DATA12, - IOMUX_CONFIG_ALT2); - mxc_request_iomux(MX53_PIN_ATA_DATA13, - IOMUX_CONFIG_ALT2); - mxc_request_iomux(MX53_PIN_ATA_DATA14, - IOMUX_CONFIG_ALT2); - mxc_request_iomux(MX53_PIN_ATA_DATA15, - IOMUX_CONFIG_ALT2); - - mxc_iomux_set_pad(MX53_PIN_SD2_CMD, 0x1E4); - mxc_iomux_set_pad(MX53_PIN_SD2_CLK, 0xD4); - mxc_iomux_set_pad(MX53_PIN_SD2_DATA0, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_SD2_DATA1, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_SD2_DATA2, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_SD2_DATA3, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA12, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA13, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA14, 0x1D4); - mxc_iomux_set_pad(MX53_PIN_ATA_DATA15, 0x1D4); - -#else mxc_request_iomux(MX53_PIN_ATA_RESET_B, IOMUX_CONFIG_ALT2); mxc_request_iomux(MX53_PIN_ATA_IORDY, @@ -1049,7 +816,7 @@ int esdhc_gpio_init(bd_t *bis) mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, 0x1D4); mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, 0x1D4); mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, 0x1D4); -#endif + break; default: printf("Warning: you configured more ESDHC controller" @@ -1096,82 +863,6 @@ void setup_nfc(void) */ clk_config(0, 34, NFC_CLK); -#if defined(CONFIG_MX53_ARD) - mxc_request_iomux(MX53_PIN_NANDF_CS0, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, - PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_NANDF_CS1, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_NANDF_CS1, - PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_NANDF_RB0, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | - PAD_CTL_100K_PU); - mxc_request_iomux(MX53_PIN_NANDF_CLE, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, - PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_NANDF_ALE, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, - PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_NANDF_WP_B, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | - PAD_CTL_100K_PU); - mxc_request_iomux(MX53_PIN_NANDF_RE_B, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, - PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_NANDF_WE_B, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, - PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_EIM_DA0, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA0, - PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | - PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_EIM_DA1, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA1, - PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | - PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_EIM_DA2, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA2, - PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | - PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_EIM_DA3, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA3, - PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | - PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_EIM_DA4, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA4, - PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | - PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_EIM_DA5, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA5, - PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | - PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_EIM_DA6, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA6, - PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | - PAD_CTL_DRV_HIGH); - mxc_request_iomux(MX53_PIN_EIM_DA7, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX53_PIN_EIM_DA7, - PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | - PAD_CTL_DRV_HIGH); -#else mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, @@ -1254,7 +945,6 @@ void setup_nfc(void) mxc_iomux_set_pad(MX53_PIN_EIM_DA7, PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); -#endif } #endif @@ -1270,11 +960,8 @@ int board_init(void) setup_boot_device(); setup_soc_rev(); -#if defined(CONFIG_MX53_ARD) - gd->bd->bi_arch_number = MACH_TYPE_MX53_ARD; -#else gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK; /* board id for linux */ -#endif + /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; @@ -1293,10 +980,6 @@ int board_init(void) setup_core_voltages(); #endif -#if defined(CONFIG_MX53_ARD) - weim_smc911x_iomux(); - weim_cs1_settings(); -#endif return 0; } @@ -1430,18 +1113,11 @@ int checkboard(void) { printf("Board: "); -#if defined(CONFIG_MX53_ARD) - printf("MX53-ARD 1.0 ["); - printf("1.0 ["); -#elif defined(CONFIG_MX53_EVK) || defined(CONFIG_MX53_ARM2_DDR3) #ifdef CONFIG_I2C_MXC identify_board_id(); printf("Boot Reason: ["); #endif -#else - # error "Unknown board config!" -#endif switch (__REG(SRC_BASE_ADDR + 0x8)) { case 0x0001: diff --git a/board/freescale/mx53_evk/u-boot.lds b/board/freescale/mx53_evk/u-boot.lds new file mode 100644 index 0000000..fe5f4eb --- /dev/null +++ b/board/freescale/mx53_evk/u-boot.lds @@ -0,0 +1,73 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * (C) Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + board/freescale/mx53_evk/flash_header.o (.text.flasheader) + cpu/arm_cortexa8/start.o + board/freescale/mx53_evk/libmx53_evk.a (.text) + lib_arm/libarm.a (.text) + net/libnet.a (.text) + drivers/mtd/libmtd.a (.text) + drivers/mmc/libmmc.a (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o(.text) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} |