diff options
122 files changed, 2161 insertions, 396 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index b387207..9d447ea 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -126,8 +126,8 @@ F: arch/arm/cpu/armv7/s5p-common/ F: arch/arm/include/asm/arch-s3c24x0/ ARM STM SPEAR -M: Vipin Kumar <vipin.kumar@st.com> -S: Maintained +#M: Vipin Kumar <vipin.kumar@st.com> +S: Orphaned (Since 2016-02) T: git git://git.denx.de/u-boot-stm.git F: arch/arm/cpu/arm926ejs/spear/ F: arch/arm/include/asm/arch-spear/ @@ -309,8 +309,8 @@ T: git git://git.denx.de/u-boot-mpc82xx.git F: arch/powerpc/cpu/mpc82*/ POWERPC MPC83XX -M: Kim Phillips <kim.phillips@freescale.com> -S: Maintained +#M: Kim Phillips <kim.phillips@freescale.com> +S: Orphaned (Since 2016-02) T: git git://git.denx.de/u-boot-mpc83xx.git F: arch/powerpc/cpu/mpc83xx/ F: arch/powerpc/include/asm/arch-mpc83xx/ @@ -376,8 +376,8 @@ T: git git://git.denx.de/u-boot-sh.git F: arch/sh/ SPARC -M: Francois Retief <fgretief@spaceteq.co.za> -S: Maintained +#M: Francois Retief <fgretief@spaceteq.co.za> +S: Orphaned (Since 2016-02) T: git git://git.denx.de/u-boot-sparc.git F: arch/sparc/ @@ -390,8 +390,8 @@ F: drivers/spi/ F: include/spi* TQ GROUP -M: Martin Krause <martin.krause@tq-systems.de> -S: Maintained +#M: Martin Krause <martin.krause@tq-systems.de> +S: Orphaned (Since 2016-02) T: git git://git.denx.de/u-boot-tq-group.git UBI diff --git a/arch/arm/cpu/armv7/sunxi/usb_phy.c b/arch/arm/cpu/armv7/sunxi/usb_phy.c index 19bb5a1..6ac96cc 100644 --- a/arch/arm/cpu/armv7/sunxi/usb_phy.c +++ b/arch/arm/cpu/armv7/sunxi/usb_phy.c @@ -31,6 +31,9 @@ #define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8) #define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0) +#define REG_PHY_UNK_H3 0x420 +#define REG_PMU_UNK_H3 0x810 + static struct sunxi_usb_phy { int usb_rst_mask; int gpio_vbus; @@ -39,19 +42,30 @@ static struct sunxi_usb_phy { int id; int init_count; int power_on_count; + int base; } sunxi_usb_phy[] = { { .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK, .id = 0, + .base = SUNXI_USB0_BASE, }, { .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK, .id = 1, + .base = SUNXI_USB1_BASE, }, #if CONFIG_SUNXI_USB_PHYS >= 3 { .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK, .id = 2, + .base = SUNXI_USB2_BASE, + }, +#endif +#if CONFIG_SUNXI_USB_PHYS >= 4 + { + .usb_rst_mask = CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK, + .id = 3, + .base = SUNXI_USB3_BASE, } #endif }; @@ -114,6 +128,15 @@ static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, } } +#if defined CONFIG_MACH_SUN8I_H3 +static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) +{ + if (phy->id == 0) + clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); + + clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02); +} +#else static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) { /* The following comments are machine @@ -136,16 +159,14 @@ static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) return; } +#endif -static void sunxi_usb_phy_passby(int index, int enable) +static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable) { unsigned long bits = 0; void *addr; - if (index == 1) - addr = (void *)SUNXI_USB1_BASE + SUNXI_USB_PMU_IRQ_ENABLE; - else - addr = (void *)SUNXI_USB2_BASE + SUNXI_USB_PMU_IRQ_ENABLE; + addr = (void *)phy->base + SUNXI_USB_PMU_IRQ_ENABLE; bits = SUNXI_EHCI_AHB_ICHR8_EN | SUNXI_EHCI_AHB_INCR4_BURST_EN | @@ -181,7 +202,7 @@ void sunxi_usb_phy_init(int index) sunxi_usb_phy_config(phy); if (phy->id != 0) - sunxi_usb_phy_passby(index, SUNXI_USB_PASSBY_EN); + sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN); } void sunxi_usb_phy_exit(int index) @@ -194,7 +215,7 @@ void sunxi_usb_phy_exit(int index) return; if (phy->id != 0) - sunxi_usb_phy_passby(index, !SUNXI_USB_PASSBY_EN); + sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN); clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask); } diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts index e841a1d..793ab44 100644 --- a/arch/arm/dts/zynq-microzed.dts +++ b/arch/arm/dts/zynq-microzed.dts @@ -24,6 +24,7 @@ }; &qspi { + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index 1ba3a1c..1610520 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -306,6 +306,7 @@ }; &qspi { + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 5ec59e2..ec9b2f7 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -61,6 +61,7 @@ }; &qspi { + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index fbbb891..d04e962 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -31,8 +31,9 @@ }; usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio0 46 1>; }; }; diff --git a/arch/arm/include/asm/arch-stm32f1/stm32.h b/arch/arm/include/asm/arch-stm32f1/stm32.h index 4094a75..1af73c5 100644 --- a/arch/arm/include/asm/arch-stm32f1/stm32.h +++ b/arch/arm/include/asm/arch-stm32f1/stm32.h @@ -24,6 +24,14 @@ #define STM32_BUS_MASK 0xFFFF0000 +#define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800) +#define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00) +#define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000) +#define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400) +#define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800) +#define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00) +#define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000) + /* * Register maps */ diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h index 6b64d03..7d6331b 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -23,6 +23,16 @@ #define STM32_BUS_MASK 0xFFFF0000 +#define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000) +#define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400) +#define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800) +#define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00) +#define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000) +#define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400) +#define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800) +#define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00) +#define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000) + /* * Register maps */ diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_periph.h b/arch/arm/include/asm/arch-stm32f4/stm32_periph.h index a1af25c..38adc4e 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32_periph.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32_periph.h @@ -22,6 +22,17 @@ enum periph_id { enum periph_clock { USART1_CLOCK_CFG = 0, USART2_CLOCK_CFG, + GPIO_A_CLOCK_CFG, + GPIO_B_CLOCK_CFG, + GPIO_C_CLOCK_CFG, + GPIO_D_CLOCK_CFG, + GPIO_E_CLOCK_CFG, + GPIO_F_CLOCK_CFG, + GPIO_G_CLOCK_CFG, + GPIO_H_CLOCK_CFG, + GPIO_I_CLOCK_CFG, + GPIO_J_CLOCK_CFG, + GPIO_K_CLOCK_CFG, }; #endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-stm32f7/gpio.h b/arch/arm/include/asm/arch-stm32f7/gpio.h new file mode 100644 index 0000000..2942cd9 --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f7/gpio.h @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _STM32_GPIO_H_ +#define _STM32_GPIO_H_ + +enum stm32_gpio_port { + STM32_GPIO_PORT_A = 0, + STM32_GPIO_PORT_B, + STM32_GPIO_PORT_C, + STM32_GPIO_PORT_D, + STM32_GPIO_PORT_E, + STM32_GPIO_PORT_F, + STM32_GPIO_PORT_G, + STM32_GPIO_PORT_H, + STM32_GPIO_PORT_I +}; + +enum stm32_gpio_pin { + STM32_GPIO_PIN_0 = 0, + STM32_GPIO_PIN_1, + STM32_GPIO_PIN_2, + STM32_GPIO_PIN_3, + STM32_GPIO_PIN_4, + STM32_GPIO_PIN_5, + STM32_GPIO_PIN_6, + STM32_GPIO_PIN_7, + STM32_GPIO_PIN_8, + STM32_GPIO_PIN_9, + STM32_GPIO_PIN_10, + STM32_GPIO_PIN_11, + STM32_GPIO_PIN_12, + STM32_GPIO_PIN_13, + STM32_GPIO_PIN_14, + STM32_GPIO_PIN_15 +}; + +enum stm32_gpio_mode { + STM32_GPIO_MODE_IN = 0, + STM32_GPIO_MODE_OUT, + STM32_GPIO_MODE_AF, + STM32_GPIO_MODE_AN +}; + +enum stm32_gpio_otype { + STM32_GPIO_OTYPE_PP = 0, + STM32_GPIO_OTYPE_OD +}; + +enum stm32_gpio_speed { + STM32_GPIO_SPEED_2M = 0, + STM32_GPIO_SPEED_25M, + STM32_GPIO_SPEED_50M, + STM32_GPIO_SPEED_100M +}; + +enum stm32_gpio_pupd { + STM32_GPIO_PUPD_NO = 0, + STM32_GPIO_PUPD_UP, + STM32_GPIO_PUPD_DOWN +}; + +enum stm32_gpio_af { + STM32_GPIO_AF0 = 0, + STM32_GPIO_AF1, + STM32_GPIO_AF2, + STM32_GPIO_AF3, + STM32_GPIO_AF4, + STM32_GPIO_AF5, + STM32_GPIO_AF6, + STM32_GPIO_AF7, + STM32_GPIO_AF8, + STM32_GPIO_AF9, + STM32_GPIO_AF10, + STM32_GPIO_AF11, + STM32_GPIO_AF12, + STM32_GPIO_AF13, + STM32_GPIO_AF14, + STM32_GPIO_AF15 +}; + +struct stm32_gpio_dsc { + enum stm32_gpio_port port; + enum stm32_gpio_pin pin; +}; + +struct stm32_gpio_ctl { + enum stm32_gpio_mode mode; + enum stm32_gpio_otype otype; + enum stm32_gpio_speed speed; + enum stm32_gpio_pupd pupd; + enum stm32_gpio_af af; +}; + +static inline unsigned stm32_gpio_to_port(unsigned gpio) +{ + return gpio / 16; +} + +static inline unsigned stm32_gpio_to_pin(unsigned gpio) +{ + return gpio % 16; +} + +int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc, + const struct stm32_gpio_ctl *gpio_ctl); +int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state); + +#endif /* _STM32_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f7/gpt.h b/arch/arm/include/asm/arch-stm32f7/gpt.h new file mode 100644 index 0000000..903bdf6 --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f7/gpt.h @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _STM32_GPT_H +#define _STM32_GPT_H + +#include <asm/arch/stm32.h> + +struct gpt_regs { + u32 cr1; + u32 cr2; + u32 smcr; + u32 dier; + u32 sr; + u32 egr; + u32 ccmr1; + u32 ccmr2; + u32 ccer; + u32 cnt; + u32 psc; + u32 arr; + u32 reserved; + u32 ccr1; + u32 ccr2; + u32 ccr3; + u32 ccr4; + u32 reserved1; + u32 dcr; + u32 dmar; + u32 tim2_5_or; +}; + +struct gpt_regs *const gpt1_regs_ptr = + (struct gpt_regs *)TIM2_BASE; + +/* Timer control1 register */ +#define GPT_CR1_CEN 0x0001 +#define GPT_MODE_AUTO_RELOAD (1 << 7) + +/* Auto reload register for free running config */ +#define GPT_FREE_RUNNING 0xFFFFFFFF + +/* Timer, HZ specific defines */ +#define CONFIG_STM32_HZ 1000 + +/* Timer Event Generation registers */ +#define TIM_EGR_UG (1 << 0) + +#endif diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h new file mode 100644 index 0000000..8bfb7b6 --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f7/rcc.h @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _STM32_RCC_H +#define _STM32_RCC_H + +#define RCC_CR 0x00 /* clock control */ +#define RCC_PLLCFGR 0x04 /* PLL configuration */ +#define RCC_CFGR 0x08 /* clock configuration */ +#define RCC_CIR 0x0C /* clock interrupt */ +#define RCC_AHB1RSTR 0x10 /* AHB1 peripheral reset */ +#define RCC_AHB2RSTR 0x14 /* AHB2 peripheral reset */ +#define RCC_AHB3RSTR 0x18 /* AHB3 peripheral reset */ +#define RCC_APB1RSTR 0x20 /* APB1 peripheral reset */ +#define RCC_APB2RSTR 0x24 /* APB2 peripheral reset */ +#define RCC_AHB1ENR 0x30 /* AHB1 peripheral clock enable */ +#define RCC_AHB2ENR 0x34 /* AHB2 peripheral clock enable */ +#define RCC_AHB3ENR 0x38 /* AHB3 peripheral clock enable */ +#define RCC_APB1ENR 0x40 /* APB1 peripheral clock enable */ +#define RCC_APB2ENR 0x44 /* APB2 peripheral clock enable */ +#define RCC_AHB1LPENR 0x50 /* periph clk enable in low pwr mode */ +#define RCC_AHB2LPENR 0x54 /* AHB2 periph clk enable in low pwr mode */ +#define RCC_AHB3LPENR 0x58 /* AHB3 periph clk enable in low pwr mode */ +#define RCC_APB1LPENR 0x60 /* APB1 periph clk enable in low pwr mode */ +#define RCC_APB2LPENR 0x64 /* APB2 periph clk enable in low pwr mode */ +#define RCC_BDCR 0x70 /* Backup domain control */ +#define RCC_CSR 0x74 /* clock control & status */ +#define RCC_SSCGR 0x80 /* spread spectrum clock generation */ +#define RCC_PLLI2SCFGR 0x84 /* PLLI2S configuration */ +#define RCC_PLLSAICFG 0x88 /* PLLSAI configuration */ +#define RCC_DCKCFG1 0x8C /* dedicated clocks configuration register */ +#define RCC_DCKCFG2 0x90 /* dedicated clocks configuration register */ + +#define RCC_APB1ENR_TIM2EN (1 << 0) +#define RCC_APB1ENR_PWREN (1 << 28) + +/* + * RCC USART specific definitions + */ +#define RCC_ENR_USART1EN (1 << 4) +#define RCC_ENR_USART2EN (1 << 17) +#define RCC_ENR_USART3EN (1 << 18) +#define RCC_ENR_USART6EN (1 << 5) + +/* + * RCC GPIO specific definitions + */ +#define RCC_ENR_GPIO_A_EN (1 << 0) +#define RCC_ENR_GPIO_B_EN (1 << 1) +#define RCC_ENR_GPIO_C_EN (1 << 2) +#define RCC_ENR_GPIO_D_EN (1 << 3) +#define RCC_ENR_GPIO_E_EN (1 << 4) +#define RCC_ENR_GPIO_F_EN (1 << 5) +#define RCC_ENR_GPIO_G_EN (1 << 6) +#define RCC_ENR_GPIO_H_EN (1 << 7) +#define RCC_ENR_GPIO_I_EN (1 << 8) +#define RCC_ENR_GPIO_J_EN (1 << 9) +#define RCC_ENR_GPIO_K_EN (1 << 10) + +#endif diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h new file mode 100644 index 0000000..713eb2e --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f7/stm32.h @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +/* STM32F746 */ +#define ITCM_FLASH_BASE 0x00200000UL +#define AXIM_FLASH_BASE 0x08000000UL + +#define ITCM_SRAM_BASE 0x00000000UL +#define DTCM_SRAM_BASE 0x20000000UL +#define SRAM1_BASE 0x20010000UL +#define SRAM2_BASE 0x2004C000UL + +#define PERIPH_BASE 0x40000000UL + +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1_PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x20000000) + +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define USART2_BASE (APB1_PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1_PERIPH_BASE + 0x4800) +#define PWR_BASE (APB1_PERIPH_BASE + 0x7000) + +#define USART1_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x1400) + +#define STM32_GPIOA_BASE (AHB1_PERIPH_BASE + 0x0000) +#define STM32_GPIOB_BASE (AHB1_PERIPH_BASE + 0x0400) +#define STM32_GPIOC_BASE (AHB1_PERIPH_BASE + 0x0800) +#define STM32_GPIOD_BASE (AHB1_PERIPH_BASE + 0x0C00) +#define STM32_GPIOE_BASE (AHB1_PERIPH_BASE + 0x1000) +#define STM32_GPIOF_BASE (AHB1_PERIPH_BASE + 0x1400) +#define STM32_GPIOG_BASE (AHB1_PERIPH_BASE + 0x1800) +#define STM32_GPIOH_BASE (AHB1_PERIPH_BASE + 0x1C00) +#define STM32_GPIOI_BASE (AHB1_PERIPH_BASE + 0x2000) +#define STM32_GPIOJ_BASE (AHB1_PERIPH_BASE + 0x2400) +#define STM32_GPIOK_BASE (AHB1_PERIPH_BASE + 0x2800) +#define RCC_BASE (AHB1_PERIPH_BASE + 0x3800) +#define FLASH_CNTL_BASE (AHB1_PERIPH_BASE + 0x3C00) + + +#define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x4A0000140) + +enum clock { + CLOCK_CORE, + CLOCK_AHB, + CLOCK_APB1, + CLOCK_APB2 +}; +#define STM32_BUS_MASK 0xFFFF0000 + +int configure_clocks(void); + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_defs.h b/arch/arm/include/asm/arch-stm32f7/stm32_defs.h new file mode 100644 index 0000000..29b98ae --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f7/stm32_defs.h @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __STM32_DEFS_H__ +#define __STM32_DEFS_H__ +#include <asm/arch/stm32_periph.h> + +int clock_setup(enum periph_clock); + +#endif + diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h new file mode 100644 index 0000000..38adc4e --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H + +/* + * Peripherals required for pinmux configuration. List will + * grow with support for more devices getting added. + * Numbering based on interrupt table. + * + */ +enum periph_id { + UART1_GPIOA_9_10 = 0, + UART2_GPIOD_5_6, +}; + +enum periph_clock { + USART1_CLOCK_CFG = 0, + USART2_CLOCK_CFG, + GPIO_A_CLOCK_CFG, + GPIO_B_CLOCK_CFG, + GPIO_C_CLOCK_CFG, + GPIO_D_CLOCK_CFG, + GPIO_E_CLOCK_CFG, + GPIO_F_CLOCK_CFG, + GPIO_G_CLOCK_CFG, + GPIO_H_CLOCK_CFG, + GPIO_I_CLOCK_CFG, + GPIO_J_CLOCK_CFG, + GPIO_K_CLOCK_CFG, +}; + +#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 554d858..9de7754 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -229,8 +229,18 @@ struct sunxi_ccm_reg { /* ahb_gate0 offsets */ #define AHB_GATE_OFFSET_USB_OHCI1 30 #define AHB_GATE_OFFSET_USB_OHCI0 29 +#ifdef CONFIG_MACH_SUN8I_H3 +/* + * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call + * them 0 - 2 like they were called on older SoCs. + */ +#define AHB_GATE_OFFSET_USB_EHCI2 27 +#define AHB_GATE_OFFSET_USB_EHCI1 26 +#define AHB_GATE_OFFSET_USB_EHCI0 25 +#else #define AHB_GATE_OFFSET_USB_EHCI1 27 #define AHB_GATE_OFFSET_USB_EHCI0 26 +#endif #define AHB_GATE_OFFSET_USB0 24 #define AHB_GATE_OFFSET_MCTL 14 #define AHB_GATE_OFFSET_GMAC 17 @@ -263,13 +273,25 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY0_RST (0x1 << 0) #define CCM_USB_CTRL_PHY1_RST (0x1 << 1) #define CCM_USB_CTRL_PHY2_RST (0x1 << 2) +#define CCM_USB_CTRL_PHY3_RST (0x1 << 3) /* There is no global phy clk gate on sun6i, define as 0 */ #define CCM_USB_CTRL_PHYGATE 0 #define CCM_USB_CTRL_PHY0_CLK (0x1 << 8) #define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) +#define CCM_USB_CTRL_PHY3_CLK (0x1 << 11) +#ifdef CONFIG_MACH_SUN8I_H3 +/* + * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call + * them 0 - 2 like they were called on older SoCs. + */ +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17) +#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18) +#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19) +#else #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) +#endif #define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 #define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 0cdefdc..b6e11eb 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -52,10 +52,18 @@ #define SUNXI_USB2_BASE 0x01c1c000 #endif #ifdef CONFIG_SUNXI_GEN_SUN6I +#ifdef CONFIG_MACH_SUN8I_H3 +#define SUNXI_USBPHY_BASE 0x01c19000 +#define SUNXI_USB0_BASE 0x01c1a000 +#define SUNXI_USB1_BASE 0x01c1b000 +#define SUNXI_USB2_BASE 0x01c1c000 +#define SUNXI_USB3_BASE 0x01c1d000 +#else #define SUNXI_USB0_BASE 0x01c19000 #define SUNXI_USB1_BASE 0x01c1a000 #define SUNXI_USB2_BASE 0x01c1b000 #endif +#endif #define SUNXI_CSI1_BASE 0x01c1d000 #define SUNXI_TZASC_BASE 0x01c1e000 #define SUNXI_SPI3_BASE 0x01c1f000 diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index e223988..35964d6 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -13,9 +13,6 @@ #define ZYNQ_GEM_BASEADDR2 0xFF0D0000 #define ZYNQ_GEM_BASEADDR3 0xFF0E0000 -#define ZYNQ_SPI_BASEADDR0 0xFF040000 -#define ZYNQ_SPI_BASEADDR1 0xFF050000 - #define ZYNQ_I2C_BASEADDR0 0xFF020000 #define ZYNQ_I2C_BASEADDR1 0xFF030000 diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h index af94dff..4a14391 100644 --- a/arch/arm/mach-bcm283x/include/mach/mbox.h +++ b/arch/arm/mach-bcm283x/include/mach/mbox.h @@ -150,6 +150,17 @@ struct bcm2835_mbox_tag_get_mac_address { } body; }; +#define BCM2835_MBOX_TAG_GET_BOARD_SERIAL 0x00010004 + +struct bcm2835_mbox_tag_get_board_serial { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct __packed { + u64 serial; + } resp; + } body; +}; + #define BCM2835_MBOX_TAG_GET_ARM_MEMORY 0x00010005 struct bcm2835_mbox_tag_get_arm_mem { diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index 7dbeb04..ec6b3ff 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -6,7 +6,11 @@ config STM32F4 config STM32F1 bool "stm32f1 family" +config STM32F7 + bool "stm32f7 family" + source "arch/arm/mach-stm32/stm32f4/Kconfig" source "arch/arm/mach-stm32/stm32f1/Kconfig" +source "arch/arm/mach-stm32/stm32f7/Kconfig" endif diff --git a/arch/arm/mach-stm32/Makefile b/arch/arm/mach-stm32/Makefile index ea06034..ffc537f 100644 --- a/arch/arm/mach-stm32/Makefile +++ b/arch/arm/mach-stm32/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_STM32F1) += stm32f1/ obj-$(CONFIG_STM32F4) += stm32f4/ +obj-$(CONFIG_STM32F7) += stm32f7/ diff --git a/arch/arm/mach-stm32/stm32f4/clock.c b/arch/arm/mach-stm32/stm32f4/clock.c index 576d3e6..631f36a 100644 --- a/arch/arm/mach-stm32/stm32f4/clock.c +++ b/arch/arm/mach-stm32/stm32f4/clock.c @@ -71,6 +71,21 @@ #define FLASH_ACR_ICEN (1 << 9) #define FLASH_ACR_DCEN (1 << 10) +/* + * RCC GPIO specific definitions + */ +#define RCC_ENR_GPIO_A_EN (1 << 0) +#define RCC_ENR_GPIO_B_EN (1 << 1) +#define RCC_ENR_GPIO_C_EN (1 << 2) +#define RCC_ENR_GPIO_D_EN (1 << 3) +#define RCC_ENR_GPIO_E_EN (1 << 4) +#define RCC_ENR_GPIO_F_EN (1 << 5) +#define RCC_ENR_GPIO_G_EN (1 << 6) +#define RCC_ENR_GPIO_H_EN (1 << 7) +#define RCC_ENR_GPIO_I_EN (1 << 8) +#define RCC_ENR_GPIO_J_EN (1 << 9) +#define RCC_ENR_GPIO_K_EN (1 << 10) + struct pll_psc { u8 pll_m; u16 pll_n; @@ -237,6 +252,39 @@ void clock_setup(int peripheral) case USART1_CLOCK_CFG: setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN); break; + case GPIO_A_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_A_EN); + break; + case GPIO_B_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_B_EN); + break; + case GPIO_C_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_C_EN); + break; + case GPIO_D_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_D_EN); + break; + case GPIO_E_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_E_EN); + break; + case GPIO_F_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_F_EN); + break; + case GPIO_G_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_G_EN); + break; + case GPIO_H_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_H_EN); + break; + case GPIO_I_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_I_EN); + break; + case GPIO_J_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_J_EN); + break; + case GPIO_K_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_K_EN); + break; default: break; } diff --git a/arch/arm/mach-stm32/stm32f7/Kconfig b/arch/arm/mach-stm32/stm32f7/Kconfig new file mode 100644 index 0000000..287e5ad --- /dev/null +++ b/arch/arm/mach-stm32/stm32f7/Kconfig @@ -0,0 +1,8 @@ +if STM32F7 + +config TARGET_STM32F746_DISCO + bool "STM32F746 Discovery board" + +source "board/st/stm32f746-disco/Kconfig" + +endif diff --git a/arch/arm/mach-stm32/stm32f7/Makefile b/arch/arm/mach-stm32/stm32f7/Makefile new file mode 100644 index 0000000..40f1ad3 --- /dev/null +++ b/arch/arm/mach-stm32/stm32f7/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2016 +# Vikas Manocha, <vikas.manocha@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += timer.o clock.o diff --git a/arch/arm/mach-stm32/stm32f7/clock.c b/arch/arm/mach-stm32/stm32f7/clock.c new file mode 100644 index 0000000..17a715b --- /dev/null +++ b/arch/arm/mach-stm32/stm32f7/clock.c @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/rcc.h> +#include <asm/arch/stm32.h> +#include <asm/arch/stm32_periph.h> + +void clock_setup(int peripheral) +{ + switch (peripheral) { + case USART1_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_ENR_USART1EN); + break; + case GPIO_A_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_A_EN); + break; + case GPIO_B_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_B_EN); + break; + case GPIO_C_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_C_EN); + break; + case GPIO_D_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_D_EN); + break; + case GPIO_E_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_E_EN); + break; + case GPIO_F_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_F_EN); + break; + case GPIO_G_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_G_EN); + break; + case GPIO_H_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_H_EN); + break; + case GPIO_I_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_I_EN); + break; + case GPIO_J_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_J_EN); + break; + case GPIO_K_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_K_EN); + break; + default: + break; + } +} diff --git a/arch/arm/mach-stm32/stm32f7/timer.c b/arch/arm/mach-stm32/stm32f7/timer.c new file mode 100644 index 0000000..a7dee10 --- /dev/null +++ b/arch/arm/mach-stm32/stm32f7/timer.c @@ -0,0 +1,112 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/stm32.h> +#include <asm/arch/gpt.h> +#include <asm/arch/rcc.h> + +#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING) +#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK/CONFIG_STM32_HZ) + +DECLARE_GLOBAL_DATA_PTR; + +#define timestamp gd->arch.tbl +#define lastdec gd->arch.lastinc + +int timer_init(void) +{ + /* Timer2 clock configuration */ + setbits_le32(RCC_BASE + RCC_APB1ENR, RCC_APB1ENR_TIM2EN); + /* Stop the timer */ + writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1); + + writel((CONFIG_SYS_CLK_FREQ/CONFIG_SYS_HZ_CLOCK) - 1, + &gpt1_regs_ptr->psc); + + /* Configure timer for auto-reload */ + writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD, + &gpt1_regs_ptr->cr1); + + /* load value for free running */ + writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr); + + /* start timer */ + writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN, &gpt1_regs_ptr->cr1); + + writel(readl(&gpt1_regs_ptr->egr) | TIM_EGR_UG, &gpt1_regs_ptr->egr); + + /* Reset the timer */ + lastdec = READ_TIMER(); + timestamp = 0; + + return 0; +} + +/* + * timer without interrupts + */ +ulong get_timer(ulong base) +{ + return (get_timer_masked() / GPT_RESOLUTION) - base; +} + +void __udelay(unsigned long usec) +{ + ulong tmo; + ulong start = get_timer_masked(); + ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100); + ulong rndoff; + + rndoff = (usec % 10) ? 1 : 0; + + /* tenudelcnt timer tick gives 10 microsecconds delay */ + tmo = ((usec / 10) + rndoff) * tenudelcnt; + + while ((ulong) (get_timer_masked() - start) < tmo) + ; +} + +ulong get_timer_masked(void) +{ + ulong now = READ_TIMER(); + + if (now >= lastdec) { + /* normal mode */ + timestamp += now - lastdec; + } else { + /* we have an overflow ... */ + timestamp += now + GPT_FREE_RUNNING - lastdec; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked(unsigned long usec) +{ + return udelay(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_STM32_HZ; +} diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h index 830e1fe..79347a8 100644 --- a/arch/arm/mach-zynq/include/mach/hardware.h +++ b/arch/arm/mach-zynq/include/mach/hardware.h @@ -14,8 +14,6 @@ #define ZYNQ_GEM_BASEADDR1 0xE000C000 #define ZYNQ_I2C_BASEADDR0 0xE0004000 #define ZYNQ_I2C_BASEADDR1 0xE0005000 -#define ZYNQ_SPI_BASEADDR0 0xE0006000 -#define ZYNQ_SPI_BASEADDR1 0xE0007000 #define ZYNQ_QSPI_BASEADDR 0xE000D000 #define ZYNQ_SMC_BASEADDR 0xE000E000 #define ZYNQ_NAND_BASEADDR 0xE1000000 diff --git a/arch/microblaze/dts/microblaze-generic.dts b/arch/microblaze/dts/microblaze-generic.dts index 2033309..08a1396 100644 --- a/arch/microblaze/dts/microblaze-generic.dts +++ b/arch/microblaze/dts/microblaze-generic.dts @@ -4,4 +4,6 @@ #size-cells = <1>; aliases { } ; + chosen { + } ; } ; diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 441465c..ce4acc1 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -12,7 +12,6 @@ #include <version.h> #include <common.h> #include <errno.h> -#include <spl.h> #include <asm/arch/cpu.h> #include <asm/arch/hardware.h> #include <asm/arch/omap.h> @@ -640,8 +639,7 @@ static struct cpsw_platform_data cpsw_data = { }; #endif /* CONFIG_DRIVER_TI_CPSW, ... */ -#if defined(CONFIG_DRIVER_TI_CPSW) - +#if defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD) int board_eth_init(bd_t *bis) { int rv = 0; @@ -658,8 +656,6 @@ int board_eth_init(bd_t *bis) mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) if (!getenv("ethaddr")) { #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USE_FDT) printf("<ethaddr> not set. trying DTB ... "); @@ -685,10 +681,9 @@ int board_eth_init(bd_t *bis) printf("Error %d registering CPSW switch\n", rv); return 0; } -#endif /* CONFIG_DRIVER_TI_CPSW, ... */ return rv; } -#endif /* CONFIG_DRIVER_TI_CPSW */ +#endif /* defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD) */ #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { diff --git a/board/compulab/cm_t43/Makefile b/board/compulab/cm_t43/Makefile index 3993689..c749659 100644 --- a/board/compulab/cm_t43/Makefile +++ b/board/compulab/cm_t43/Makefile @@ -6,4 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += board.o mux.o +ifdef CONFIG_SPL_BUILD +obj-y += spl.o mux.o +else +obj-y += cm_t43.o mux.o +endif diff --git a/board/compulab/cm_t43/cm_t43.c b/board/compulab/cm_t43/cm_t43.c new file mode 100644 index 0000000..0d5da6f --- /dev/null +++ b/board/compulab/cm_t43/cm_t43.c @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2015 Compulab, Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <asm/gpio.h> +#include <asm/arch/sys_proto.h> +#include <asm/emif.h> +#include <power/pmic.h> +#include <power/tps65218.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +/* setup board specific PMIC */ +int power_init_board(void) +{ + struct pmic *p; + uchar tps_status = 0; + + power_tps65218_init(I2C_PMIC); + p = pmic_get("TPS65218_PMIC"); + if (p && !pmic_probe(p)) { + puts("PMIC: TPS65218\n"); + /* We don't care if fseal is locked, but we do need it set */ + tps65218_lock_fseal(); + tps65218_reg_read(TPS65218_STATUS, &tps_status); + if (!(tps_status & TPS65218_FSEAL)) + printf("WARNING: RTC not backed by battery!\n"); + } + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + set_i2c_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + i2c_probe(TPS65218_CHIP_PM); + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_CPSW + +static void cpsw_control(int enabled) +{ + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_RGMII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 1, + .phy_if = PHY_INTERFACE_MODE_RGMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 2, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +#define GPIO_PHY1_RST 170 +#define GPIO_PHY2_RST 168 + +int board_phy_config(struct phy_device *phydev) +{ + unsigned short val; + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + if (phydev->drv->config) + return phydev->drv->config(phydev); + + return 0; +} + +static void board_phy_init(void) +{ + set_mdio_pin_mux(); + writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */ + writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */ + writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */ + + /* For revision A */ + writel(0x2000009, 0x44df2e6c); + writel(0x38a, 0x44df2e70); + + mdelay(10); + + gpio_request(GPIO_PHY1_RST, "phy1_rst"); + gpio_request(GPIO_PHY2_RST, "phy2_rst"); + gpio_direction_output(GPIO_PHY1_RST, 0); + gpio_direction_output(GPIO_PHY2_RST, 0); + mdelay(2); + + gpio_set_value(GPIO_PHY1_RST, 1); + gpio_set_value(GPIO_PHY2_RST, 1); + mdelay(2); +} + +int board_eth_init(bd_t *bis) +{ + int rv; + + set_rgmii_pin_mux(); + writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); + board_phy_init(); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + + return rv; +} +#endif diff --git a/board/compulab/cm_t43/board.c b/board/compulab/cm_t43/spl.c index 4272c45..b7d118e 100644 --- a/board/compulab/cm_t43/board.c +++ b/board/compulab/cm_t43/spl.c @@ -1,31 +1,21 @@ /* - * Copyright (C) 2015 Compulab, Ltd. + * Copyright (C) 2016 Compulab, Ltd. * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> -#include <i2c.h> -#include <miiphy.h> -#include <cpsw.h> #include <spl.h> +#include <i2c.h> #include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/mux.h> #include <asm/arch/ddr_defs.h> -#include <asm/errno.h> #include <asm/gpio.h> -#include <asm/emif.h> #include <power/pmic.h> #include <power/tps65218.h> #include "board.h" DECLARE_GLOBAL_DATA_PTR; -static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 }; const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 }; const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 }; @@ -114,22 +104,21 @@ const struct dpll_params *get_dpll_per_params(void) return &dpll_per; } -static void enable_vtt_regulator(void) +void scale_vcores(void) { - u32 temp; + set_i2c_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + if (i2c_probe(TPS65218_CHIP_PM)) + return; - writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); - writel(GPIO_SETDATAOUT(7), AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); - temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); - temp = temp & ~(GPIO_OE_ENABLE(7)); - writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); + tps65218_voltage_update(TPS65218_DCDC1, TPS65218_DCDC_VOLT_SEL_1100MV); + tps65218_voltage_update(TPS65218_DCDC2, TPS65218_DCDC_VOLT_SEL_1100MV); } void sdram_init(void) { unsigned long ram_size; - enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (ram_size == 0x80000000 || @@ -145,128 +134,4 @@ void sdram_init(void) hang(); } -#endif - -/* setup board specific PMIC */ -int power_init_board(void) -{ - struct pmic *p; - - power_tps65218_init(I2C_PMIC); - p = pmic_get("TPS65218_PMIC"); - if (p && !pmic_probe(p)) - puts("PMIC: TPS65218\n"); - - return 0; -} -int board_init(void) -{ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - gpmc_init(); - set_i2c_pin_mux(); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - i2c_probe(TPS65218_CHIP_PM); - - return 0; -} - -#ifdef CONFIG_DRIVER_TI_CPSW - -static void cpsw_control(int enabled) -{ - return; -} - -static struct cpsw_slave_data cpsw_slaves[] = { - { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_addr = 0, - .phy_if = PHY_INTERFACE_MODE_RGMII, - }, - { - .slave_reg_ofs = 0x308, - .sliver_reg_ofs = 0xdc0, - .phy_addr = 1, - .phy_if = PHY_INTERFACE_MODE_RGMII, - }, -}; - -static struct cpsw_platform_data cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, - .cpsw_base = CPSW_BASE, - .mdio_div = 0xff, - .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 2, - .slave_data = cpsw_slaves, - .ale_reg_ofs = 0xd00, - .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, - .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, -}; - -#define GPIO_PHY1_RST 170 -#define GPIO_PHY2_RST 168 - -int board_phy_config(struct phy_device *phydev) -{ - unsigned short val; - - /* introduce tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - val |= 0x0100; - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); - - if (phydev->drv->config) - return phydev->drv->config(phydev); - - return 0; -} - -static void board_phy_init(void) -{ - set_mdio_pin_mux(); - writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */ - writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */ - writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */ - - /* For revision A */ - writel(0x2000009, 0x44df2e6c); - writel(0x38a, 0x44df2e70); - - mdelay(10); - - gpio_request(GPIO_PHY1_RST, "phy1_rst"); - gpio_request(GPIO_PHY2_RST, "phy2_rst"); - gpio_direction_output(GPIO_PHY1_RST, 0); - gpio_direction_output(GPIO_PHY2_RST, 0); - mdelay(2); - - gpio_set_value(GPIO_PHY1_RST, 1); - gpio_set_value(GPIO_PHY2_RST, 1); - mdelay(2); -} - -int board_eth_init(bd_t *bis) -{ - int rv; - - set_rgmii_pin_mux(); - writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); - board_phy_init(); - - rv = cpsw_register(&cpsw_data); - if (rv < 0) - printf("Error %d registering CPSW switch\n", rv); - - return rv; -} -#endif diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index b5c44f9..668f684 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -228,6 +228,30 @@ int board_init(void) return 0; } +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + switch (gd->bd->bi_arch_number) { + case MACH_TYPE_DM3730_TORPEDO: + setenv("fdtimage", "logicpd-torpedo-37xx-devkit.dtb"); + break; + case MACH_TYPE_DM3730_SOM_LV: + setenv("fdtimage", "logicpd-som-lv-37xx-devkit.dtb"); + break; + case MACH_TYPE_OMAP3_TORPEDO: + setenv("fdtimage", "logicpd-torpedo-35xx-devkit.dtb"); + break; + case MACH_TYPE_OMAP3530_LV_SOM: + setenv("fdtimage", "logicpd-som-lv-35xx-devkit.dtb"); + break; + default: + /* unknown machine type */ + break; + } + return 0; +} +#endif + #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 7f4fe64..1d3a4e0 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <inttypes.h> #include <config.h> #include <dm.h> #include <fdt_support.h> @@ -56,6 +57,12 @@ struct msg_get_board_rev { u32 end_tag; }; +struct msg_get_board_serial { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_get_board_serial get_board_serial; + u32 end_tag; +}; + struct msg_get_mac_address { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_get_mac_address get_mac_address; @@ -281,6 +288,30 @@ static void set_board_info(void) } #endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */ +static void set_serial_number(void) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_board_serial, msg, 1); + int ret; + char serial_string[17] = { 0 }; + + if (getenv("serial#")) + return; + + BCM2835_MBOX_INIT_HDR(msg); + BCM2835_MBOX_INIT_TAG_NO_REQ(&msg->get_board_serial, GET_BOARD_SERIAL); + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr); + if (ret) { + printf("bcm2835: Could not query board serial\n"); + /* Ignore error; not critical */ + return; + } + + snprintf(serial_string, sizeof(serial_string), "%016" PRIx64, + msg->get_board_serial.body.resp.serial); + setenv("serial#", serial_string); +} + int misc_init_r(void) { set_fdtfile(); @@ -288,6 +319,8 @@ int misc_init_r(void) #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG set_board_info(); #endif + set_serial_number(); + return 0; } diff --git a/board/samsung/origen/tools/mkorigenspl.c b/board/samsung/origen/tools/mkorigenspl.c index 8b0c3ac..7b5d93b 100644 --- a/board/samsung/origen/tools/mkorigenspl.c +++ b/board/samsung/origen/tools/mkorigenspl.c @@ -83,8 +83,8 @@ int main(int argc, char **argv) for (i = 0; i < IMG_SIZE - SPL_HEADER_SIZE; i++) checksum += buffer[i+16]; - *(ulong *)buffer ^= 0x1f; - *(ulong *)(buffer+4) ^= checksum; + *(unsigned long *)buffer ^= 0x1f; + *(unsigned long *)(buffer+4) ^= checksum; for (i = 1; i < SPL_HEADER_SIZE; i++) buffer[i] ^= buffer[i-1]; diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index fb8475f..d16d73f 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -50,6 +50,7 @@ int uart_setup_gpio(void) int i; int rv = 0; + clock_setup(GPIO_A_CLOCK_CFG); for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) { rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart); if (rv) @@ -115,6 +116,13 @@ static int fmc_setup_gpio(void) int rv = 0; int i; + clock_setup(GPIO_B_CLOCK_CFG); + clock_setup(GPIO_C_CLOCK_CFG); + clock_setup(GPIO_D_CLOCK_CFG); + clock_setup(GPIO_E_CLOCK_CFG); + clock_setup(GPIO_F_CLOCK_CFG); + clock_setup(GPIO_G_CLOCK_CFG); + for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) { rv = stm32_gpio_config(&ext_ram_fmc_gpio[i], &gpio_ctl_fmc); diff --git a/board/st/stm32f746-disco/Kconfig b/board/st/stm32f746-disco/Kconfig new file mode 100644 index 0000000..09289d2 --- /dev/null +++ b/board/st/stm32f746-disco/Kconfig @@ -0,0 +1,19 @@ +if TARGET_STM32F746_DISCO + +config SYS_BOARD + string + default "stm32f746-disco" + +config SYS_VENDOR + string + default "st" + +config SYS_SOC + string + default "stm32f7" + +config SYS_CONFIG_NAME + string + default "stm32f746-disco" + +endif diff --git a/board/st/stm32f746-disco/MAINTAINERS b/board/st/stm32f746-disco/MAINTAINERS new file mode 100644 index 0000000..2df0a65 --- /dev/null +++ b/board/st/stm32f746-disco/MAINTAINERS @@ -0,0 +1,6 @@ +STM32F746 DISCOVERY BOARD +M: Vikas Manocha <vikas.manocha@st.com> +S: Maintained +F: board/st/stm32f746-disco +F: include/configs/stm32f746-disco.h +F: configs/stm32f746-disco_defconfig diff --git a/board/st/stm32f746-disco/Makefile b/board/st/stm32f746-disco/Makefile new file mode 100644 index 0000000..db8a0a4 --- /dev/null +++ b/board/st/stm32f746-disco/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2016 +# Vikas Manocha <vikas.manocha@st.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := stm32f746-disco.o diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c new file mode 100644 index 0000000..0e04d14 --- /dev/null +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/armv7m.h> +#include <asm/arch/stm32.h> +#include <asm/arch/gpio.h> +#include <dm/platdata.h> +#include <dm/platform_data/serial_stm32x7.h> +#include <asm/arch/stm32_periph.h> +#include <asm/arch/stm32_defs.h> + +DECLARE_GLOBAL_DATA_PTR; + +const struct stm32_gpio_ctl gpio_ctl_gpout = { + .mode = STM32_GPIO_MODE_OUT, + .otype = STM32_GPIO_OTYPE_PP, + .speed = STM32_GPIO_SPEED_50M, + .pupd = STM32_GPIO_PUPD_NO, + .af = STM32_GPIO_AF0 +}; + +const struct stm32_gpio_ctl gpio_ctl_usart = { + .mode = STM32_GPIO_MODE_AF, + .otype = STM32_GPIO_OTYPE_PP, + .speed = STM32_GPIO_SPEED_50M, + .pupd = STM32_GPIO_PUPD_UP, + .af = STM32_GPIO_AF7 +}; + +static const struct stm32_gpio_dsc usart_gpio[] = { + {STM32_GPIO_PORT_A, STM32_GPIO_PIN_9}, /* TX */ + {STM32_GPIO_PORT_B, STM32_GPIO_PIN_7}, /* RX */ +}; + +int uart_setup_gpio(void) +{ + int i; + int rv = 0; + + clock_setup(GPIO_A_CLOCK_CFG); + clock_setup(GPIO_B_CLOCK_CFG); + for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) { + rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart); + if (rv) + goto out; + } + +out: + return rv; +} + +static const struct stm32x7_serial_platdata serial_platdata = { + .base = (struct stm32_usart *)USART1_BASE, + .clock = CONFIG_SYS_CLK_FREQ, +}; + +U_BOOT_DEVICE(stm32x7_serials) = { + .name = "serial_stm32x7", + .platdata = &serial_platdata, +}; + +u32 get_board_rev(void) +{ + return 0; +} + +int board_early_init_f(void) +{ + int res; + + res = uart_setup_gpio(); + clock_setup(USART1_CLOCK_CFG); + if (res) + return res; + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; + gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE; + + gd->ram_size = CONFIG_SYS_RAM_SIZE; + return 0; +} diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index a334aa3..5e9d3af 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -372,11 +372,14 @@ config I2C3_ENABLE See I2C0_ENABLE help text. endif +if SUNXI_GEN_SUN6I config R_I2C_ENABLE bool "Enable the PRCM I2C/TWI controller" - default n + # This is used for the pmic on H3 + default y if SY8106A_POWER ---help--- Set this to y to enable the I2C controller which is part of the PRCM. +endif if MACH_SUN7I config I2C4_ENABLE diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 420481a..15b7af6 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -25,6 +25,7 @@ #include <asm/io.h> #include <nand.h> #include <net.h> +#include <sy8106a.h> #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ @@ -436,6 +437,10 @@ void sunxi_board_init(void) int power_failed = 0; unsigned long ramsize; +#ifdef CONFIG_SY8106A_POWER + power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); +#endif + #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER power_failed = axp_init(); diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 01bae5d..2f17e97 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -100,7 +100,6 @@ int checkboard(void) int dram_init(void) { -#if CONFIG_IS_ENABLED(OF_CONTROL) int node; fdt_addr_t addr; fdt_size_t size; @@ -118,9 +117,6 @@ int dram_init(void) return -1; } gd->ram_size = size; -#else - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; -#endif zynq_ddrc_init(); return 0; diff --git a/cmd/bootm.c b/cmd/bootm.c index 48738ac..555ccbc 100644 --- a/cmd/bootm.c +++ b/cmd/bootm.c @@ -755,15 +755,15 @@ int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_LONGHELP static char booti_help_text[] = "[addr [initrd[:size]] [fdt]]\n" - " - boot Linux Image stored in memory\n" + " - boot arm64 Linux Image stored in memory\n" "\tThe argument 'initrd' is optional and specifies the address\n" - "\tof the initrd in memory. The optional argument ':size' allows\n" - "\tspecifying the size of RAW initrd.\n" + "\tof an initrd in memory. The optional parameter ':size' allows\n" + "\tspecifying the size of a RAW initrd.\n" #if defined(CONFIG_OF_LIBFDT) - "\tSince booting a Linux kernelrequires a flat device-tree\n" - "\ta third argument is required which is the address of the\n" - "\tdevice-tree blob. To boot that kernel without an initrd image,\n" - "\tuse a '-' for the second argument.\n" + "\tSince booting a Linux kernel requires a flat device-tree, a\n" + "\tthird argument providing the address of the device-tree blob\n" + "\tis required. To boot a kernel with a device-tree blob but\n" + "\twithout an initrd image, use a '-' for the initrd argument.\n" #endif ""; #endif @@ -1141,7 +1141,7 @@ static void decode_bits (u_char const b, char const *str[], int const do_once) */ static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { - enum { unknown, EDO, SDRAM, DDR2 } type; + enum { unknown, EDO, SDRAM, DDR, DDR2, DDR3, DDR4 } type; uint chip; u_char data[128]; @@ -1228,10 +1228,22 @@ static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) type = SDRAM; puts ("SDRAM\n"); break; + case 7: + type = DDR; + puts("DDR\n"); + break; case 8: type = DDR2; puts ("DDR2\n"); break; + case 11: + type = DDR3; + puts("DDR3\n"); + break; + case 12: + type = DDR4; + puts("DDR4\n"); + break; default: type = unknown; puts ("unknown\n"); @@ -1038,7 +1038,7 @@ static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int argc, return -1; } - printf("Testing %08x ... %08x:\n", (uint)start, (uint)end); + printf("Testing %08lx ... %08lx:\n", start, end); debug("%s:%d: start %#08lx end %#08lx\n", __func__, __LINE__, start, end); diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig index 9eb41f9..3e916db 100644 --- a/configs/am437x_sk_evm_defconfig +++ b/configs/am437x_sk_evm_defconfig @@ -23,3 +23,4 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y +CONFIG_DMA=y diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index 6044ae9..d1da759 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_CM_T43=y CONFIG_DM_GPIO=y CONFIG_SPL=y +CONFIG_SYS_PROMPT="CM-T43 # " # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_USB=y @@ -10,3 +11,15 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_NFS is not set CONFIG_DM=y CONFIG_SYS_NS16550=y +CONFIG_DM_SERIAL=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/kwb_defconfig b/configs/kwb_defconfig index 10d39eb..4d2aa6c 100644 --- a/configs/kwb_defconfig +++ b/configs/kwb_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_KWB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" -CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# " +CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_BOOTM is not set # CONFIG_CMD_GO is not set @@ -14,9 +14,18 @@ CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_NETCONSOLE=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_STORAGE=y diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig index ea9ed87..aaf0f68 100644 --- a/configs/orangepi_pc_defconfig +++ b/configs/orangepi_pc_defconfig @@ -12,4 +12,5 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y -CONFIG_R_I2C_ENABLE=y +CONFIG_SY8106A_POWER=y +CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig index 003a9c6..e52dcfc 100644 --- a/configs/orangepi_plus_defconfig +++ b/configs/orangepi_plus_defconfig @@ -12,3 +12,5 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y +CONFIG_SY8106A_POWER=y +CONFIG_USB_EHCI_HCD=y diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig new file mode 100644 index 0000000..7cfed4a --- /dev/null +++ b/configs/stm32f746-disco_defconfig @@ -0,0 +1,9 @@ +CONFIG_ARM=y +CONFIG_STM32=y +CONFIG_STM32F7=y +CONFIG_TARGET_STM32F746_DISCO=y +CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" +CONFIG_AUTOBOOT_STOP_STR=" " +# CONFIG_CMD_SETEXPR is not set diff --git a/configs/tseries_mmc_defconfig b/configs/tseries_mmc_defconfig index 7518774..168e379 100644 --- a/configs/tseries_mmc_defconfig +++ b/configs/tseries_mmc_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_TSERIES=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT" -CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# " +CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set @@ -11,9 +11,18 @@ CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_NETCONSOLE=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_STORAGE=y diff --git a/configs/tseries_nand_defconfig b/configs/tseries_nand_defconfig index 65d514a..8151caf 100644 --- a/configs/tseries_nand_defconfig +++ b/configs/tseries_nand_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_TSERIES=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND" -CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# " +CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set @@ -11,9 +11,19 @@ CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_NAND=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_NETCONSOLE=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_STORAGE=y diff --git a/configs/tseries_spi_defconfig b/configs/tseries_spi_defconfig index 11e4e6b..901c55e 100644 --- a/configs/tseries_spi_defconfig +++ b/configs/tseries_spi_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_TSERIES=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT" -CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# " +CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set @@ -11,11 +11,23 @@ CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_NETCONSOLE=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_STORAGE=y diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index 2811918..c2bbb47 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -25,5 +25,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ZYNQ_SDHCI=y CONFIG_ZYNQ_GEM=y # CONFIG_REGEX is not set diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index a3a66ec..4c5152f 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -13,6 +13,7 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ZYNQ_SDHCI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index fbc603f..f34e2e3 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -10,4 +10,5 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ZYNQ_SDHCI=y CONFIG_ZYNQ_GEM=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 3540653..f01874f 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -12,6 +12,7 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ZYNQ_SDHCI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index f333b7a..215f00d 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -13,6 +13,7 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ZYNQ_SDHCI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index ebfdeb0..cec722f 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -14,6 +14,7 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ZYNQ_SDHCI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 5868012..4a2a2fc 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -13,6 +13,7 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ZYNQ_SDHCI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index ebaae49..7c23fec 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -13,6 +13,7 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ZYNQ_SDHCI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_ZYNQ_GEM=y diff --git a/doc/driver-model/serial-howto.txt b/doc/driver-model/serial-howto.txt index 61f2da3..cddfb9f 100644 --- a/doc/driver-model/serial-howto.txt +++ b/doc/driver-model/serial-howto.txt @@ -4,7 +4,6 @@ How to port a serial driver to driver model Almost all of the serial drivers have been converted as at January 2016. These ones remain: - arm_dcc.c mcfuart.c serial_bfin.c serial_pxa.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index e69de29..1b92c77 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -0,0 +1,22 @@ +menu "DMA Support" + +config DMA + bool "Enable Driver Model for DMA drivers" + depends on DM + help + Enable driver model for DMA. DMA engines can do + asynchronous data transfers without involving the host + CPU. Currently, this framework can be used to offload + memory copies to and from devices like qspi, ethernet + etc Drivers provide methods to access the DMA devices + buses that is used to transfer data to and from memory. + The uclass interface is defined in include/dma.h. + +config TI_EDMA3 + bool "TI EDMA3 driver" + help + Enable the TI EDMA3 driver for DRA7xx and AM43xx evms. + This driver support data transfer between memory + regions. + +endmenu # menu "DMA Support" diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index f95fe70..39b78b2 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -5,6 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_DMA) += dma-uclass.o + obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o obj-$(CONFIG_APBH_DMA) += apbh_dma.o obj-$(CONFIG_FSL_DMA) += fsl_dma.o diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c new file mode 100644 index 0000000..ea21fd9 --- /dev/null +++ b/drivers/dma/dma-uclass.c @@ -0,0 +1,72 @@ +/* + * Direct Memory Access U-Class driver + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * + * Author: Mugunthan V N <mugunthanvnm@ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dma.h> +#include <dm.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> +#include <errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dma_get_device(u32 transfer_type, struct udevice **devp) +{ + struct udevice *dev; + int ret; + + for (ret = uclass_first_device(UCLASS_DMA, &dev); dev && !ret; + ret = uclass_next_device(&dev)) { + struct dma_dev_priv *uc_priv; + + uc_priv = dev_get_uclass_priv(dev); + if (uc_priv->supported & transfer_type) + break; + } + + if (!dev) { + error("No DMA device found that supports %x type\n", + transfer_type); + return -EPROTONOSUPPORT; + } + + *devp = dev; + + return ret; +} + +int dma_memcpy(void *dst, void *src, size_t len) +{ + struct udevice *dev; + const struct dma_ops *ops; + int ret; + + ret = dma_get_device(DMA_SUPPORTS_MEM_TO_MEM, &dev); + if (ret < 0) + return ret; + + ops = device_get_ops(dev); + if (!ops->transfer) + return -ENOSYS; + + /* Invalidate the area, so no writeback into the RAM races with DMA */ + invalidate_dcache_range((unsigned long)dst, (unsigned long)dst + + roundup(len, ARCH_DMA_MINALIGN)); + + return ops->transfer(dev, DMA_MEM_TO_MEM, dst, src, len); +} + +UCLASS_DRIVER(dma) = { + .id = UCLASS_DMA, + .name = "dma", + .flags = DM_UC_FLAG_SEQ_ALIAS, + .per_device_auto_alloc_size = sizeof(struct dma_dev_priv), +}; diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c index d6a427f..2478438 100644 --- a/drivers/dma/ti-edma3.c +++ b/drivers/dma/ti-edma3.c @@ -11,6 +11,9 @@ #include <asm/io.h> #include <common.h> +#include <dma.h> +#include <dm/device.h> +#include <asm/omap_common.h> #include <asm/ti-common/ti-edma3.h> #define EDMA3_SL_BASE(slot) (0x4000 + ((slot) << 5)) @@ -31,6 +34,10 @@ #define EDMA3_QEESR 0x108c #define EDMA3_QSECR 0x1094 +struct ti_edma3_priv { + u32 base; +}; + /** * qedma3_start - start qdma on a channel * @base: base address of edma @@ -383,8 +390,8 @@ void qedma3_stop(u32 base, struct edma3_channel_config *cfg) __raw_writel(0, base + EDMA3_QCHMAP(cfg->chnum)); } -void edma3_transfer(unsigned long edma3_base_addr, unsigned int - edma_slot_num, void *dst, void *src, size_t len) +void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, + void *dst, void *src, size_t len) { struct edma3_slot_config slot; struct edma3_channel_config edma_channel; @@ -460,3 +467,74 @@ void edma3_transfer(unsigned long edma3_base_addr, unsigned int qedma3_stop(edma3_base_addr, &edma_channel); } } + +#ifndef CONFIG_DMA + +void edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, + void *dst, void *src, size_t len) +{ + __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len); +} + +#else + +static int ti_edma3_transfer(struct udevice *dev, int direction, void *dst, + void *src, size_t len) +{ + struct ti_edma3_priv *priv = dev_get_priv(dev); + + /* enable edma3 clocks */ + enable_edma3_clocks(); + + switch (direction) { + case DMA_MEM_TO_MEM: + __edma3_transfer(priv->base, 1, dst, src, len); + break; + default: + error("Transfer type not implemented in DMA driver\n"); + break; + } + + /* disable edma3 clocks */ + disable_edma3_clocks(); + + return 0; +} + +static int ti_edma3_ofdata_to_platdata(struct udevice *dev) +{ + struct ti_edma3_priv *priv = dev_get_priv(dev); + + priv->base = dev_get_addr(dev); + + return 0; +} + +static int ti_edma3_probe(struct udevice *dev) +{ + struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM; + + return 0; +} + +static const struct dma_ops ti_edma3_ops = { + .transfer = ti_edma3_transfer, +}; + +static const struct udevice_id ti_edma3_ids[] = { + { .compatible = "ti,edma3" }, + { } +}; + +U_BOOT_DRIVER(ti_edma3) = { + .name = "ti_edma3", + .id = UCLASS_DMA, + .of_match = ti_edma3_ids, + .ops = &ti_edma3_ops, + .ofdata_to_platdata = ti_edma3_ofdata_to_platdata, + .probe = ti_edma3_probe, + .priv_auto_alloc_size = sizeof(struct ti_edma3_priv), +}; +#endif /* CONFIG_DMA */ diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c index 75a84e1..50f86d3 100644 --- a/drivers/gpio/stm32_gpio.c +++ b/drivers/gpio/stm32_gpio.c @@ -19,17 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_STM32F4) -#define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000) -#define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400) -#define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800) -#define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00) -#define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000) -#define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400) -#define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800) -#define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00) -#define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000) - +#if defined(CONFIG_STM32F4) || defined(CONFIG_STM32F7) static const unsigned long io_base[] = { STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE, STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE, @@ -70,8 +60,6 @@ int stm32_gpio_config(const struct stm32_gpio_dsc *dsc, gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port]; - setbits_le32(&STM32_RCC->ahb1enr, 1 << dsc->port); - i = (dsc->pin & 0x07) * 4; clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i); @@ -87,14 +75,6 @@ out: return rv; } #elif defined(CONFIG_STM32F1) -#define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800) -#define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00) -#define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000) -#define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400) -#define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800) -#define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00) -#define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000) - static const unsigned long io_base[] = { STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE, STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE, @@ -141,9 +121,6 @@ int stm32_gpio_config(const struct stm32_gpio_dsc *dsc, gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port]; - /* Enable clock for GPIO port */ - setbits_le32(&STM32_RCC->apb2enr, 0x04 << dsc->port); - if (p < 8) { cr = &gpio_regs->crl; crp = p; @@ -230,7 +207,7 @@ int gpio_direction_input(unsigned gpio) dsc.port = stm32_gpio_to_port(gpio); dsc.pin = stm32_gpio_to_pin(gpio); -#if defined(CONFIG_STM32F4) +#if defined(CONFIG_STM32F4) || defined(CONFIG_STM32F7) ctl.af = STM32_GPIO_AF0; ctl.mode = STM32_GPIO_MODE_IN; ctl.otype = STM32_GPIO_OTYPE_PP; @@ -256,7 +233,7 @@ int gpio_direction_output(unsigned gpio, int value) dsc.port = stm32_gpio_to_port(gpio); dsc.pin = stm32_gpio_to_pin(gpio); -#if defined(CONFIG_STM32F4) +#if defined(CONFIG_STM32F4) || defined(CONFIG_STM32F7) ctl.af = STM32_GPIO_AF0; ctl.mode = STM32_GPIO_MODE_OUT; ctl.pupd = STM32_GPIO_PUPD_NO; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 9f4b766..9d3f7e9 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -37,4 +37,10 @@ config PIC32_SDHCI help Support for Microchip PIC32 SDHCI controller. +config ZYNQ_SDHCI + bool "Arasan SDHCI controller support" + depends on DM_MMC && OF_CONTROL + help + Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform + endmenu diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 8a60c72..3c365d5 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -16,6 +16,7 @@ #include <spi.h> #include <spi_flash.h> #include <linux/log2.h> +#include <dma.h> #include "sf_internal.h" @@ -454,8 +455,16 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, return ret; } +/* + * TODO: remove the weak after all the other spi_flash_copy_mmap + * implementations removed from drivers + */ void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len) { +#ifdef CONFIG_DMA + if (!dma_memcpy(data, offset, len)) + return; +#endif memcpy(data, offset, len); } diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index bba48da..259a87f 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -203,6 +203,14 @@ static int rtl8211x_startup(struct phy_device *phydev) return 0; } +static int rtl8211e_startup(struct phy_device *phydev) +{ + genphy_update_link(phydev); + genphy_parse_link(phydev); + + return 0; +} + static int rtl8211f_startup(struct phy_device *phydev) { /* Read the Status (2x to make sure link is right) */ @@ -230,7 +238,7 @@ static struct phy_driver RTL8211E_driver = { .mask = 0xffffff, .features = PHY_GBIT_FEATURES, .config = &rtl8211x_config, - .startup = &rtl8211x_startup, + .startup = &rtl8211e_startup, .shutdown = &genphy_shutdown, }; diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index d5bf6f4..9eb605b 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -266,7 +266,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), int exec_method) { struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); - struct pci_rom_header *rom, *ram = NULL; + struct pci_rom_header *rom = NULL, *ram = NULL; int vesa_mode = -1; bool emulate, alloced; int ret; diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 10683a2..adc6455 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -48,6 +48,13 @@ config AXP818_POWER Say y here to enable support for the axp818 pmic found on A83T dev board. +config SY8106A_POWER + boolean "SY8106A pmic support" + depends on MACH_SUN8I_H3 + ---help--- + Select this to enable support for the SY8106A pmic found on some + H3 boards. + endchoice config AXP_DCDC1_VOLT @@ -232,4 +239,13 @@ config AXP_ELDO3_VOLT 1.2V for the SSD2828 chip (converter of parallel LCD interface into MIPI DSI). +config SY8106A_VOUT1_VOLT + int "SY8106A pmic VOUT1 voltage" + depends on SY8106A_POWER + default 1200 + ---help--- + Set the voltage (mV) to program the SY8106A pmic VOUT1. This + is typically used to power the VDD-CPU and should be 1200mV. + Values can range from 680mV till 1950mV. + endmenu diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 0fdbca3..690faa0 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_AXP221_POWER) += axp221.o obj-$(CONFIG_AXP818_POWER) += axp818.o obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o +obj-$(CONFIG_SY8106A_POWER) += sy8106a.o obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o obj-$(CONFIG_TWL4030_POWER) += twl4030.o obj-$(CONFIG_TWL6030_POWER) += twl6030.o diff --git a/drivers/power/pmic/pmic_tps65218.c b/drivers/power/pmic/pmic_tps65218.c index dbc7a73..0fd0ad4 100644 --- a/drivers/power/pmic/pmic_tps65218.c +++ b/drivers/power/pmic/pmic_tps65218.c @@ -11,6 +11,20 @@ #include <power/pmic.h> #include <power/tps65218.h> +int tps65218_reg_read(uchar dest_reg, uchar *dest_val) +{ + uchar read_val; + int ret; + + ret = i2c_read(TPS65218_CHIP_PM, dest_reg, 1, &read_val, 1); + if (ret) + return ret; + + *dest_val = read_val; + + return 0; +} + /** * tps65218_reg_write() - Generic function that can write a TPS65218 PMIC * register or bit field regardless of protection @@ -98,6 +112,48 @@ int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel) return 0; } +/** + * tps65218_toggle_fseal() - Perform the sequence that toggles the FSEAL bit. + * + * @return: 0 on success, -EBADE if the sequence was broken + */ +int tps65218_toggle_fseal(void) +{ + if (tps65218_reg_write(TPS65218_PROT_LEVEL_NONE, TPS65218_PASSWORD, + 0xb1, TPS65218_MASK_ALL_BITS)) + return -EBADE; + + if (tps65218_reg_write(TPS65218_PROT_LEVEL_NONE, TPS65218_PASSWORD, + 0xfe, TPS65218_MASK_ALL_BITS)) + return -EBADE; + + if (tps65218_reg_write(TPS65218_PROT_LEVEL_NONE, TPS65218_PASSWORD, + 0xa3, TPS65218_MASK_ALL_BITS)) + return -EBADE; + + return 0; +} + +/** + * tps65218_lock_fseal() - Perform the sequence that locks the FSEAL bit to 1. + * + * The FSEAL bit prevents the PMIC from turning off DCDC5 and DCDC6. It can be + * toggled at most 3 times: 0->1, 1->0, and finally 0->1. After the third switch + * its value is locked and can only be reset by powering off the PMIC entirely. + * + * @return: 0 on success, -EBADE if the sequence was broken + */ +int tps65218_lock_fseal(void) +{ + int i; + + for (i = 0; i < 3; i++) + if (tps65218_toggle_fseal()) + return -EBADE; + + return 0; +} + int power_tps65218_init(unsigned char bus) { static const char name[] = "TPS65218_PMIC"; diff --git a/drivers/power/sy8106a.c b/drivers/power/sy8106a.c new file mode 100644 index 0000000..bbf116f --- /dev/null +++ b/drivers/power/sy8106a.c @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2016 + * Jelle van der Waa <jelle@vdwaa.nl> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <i2c.h> +#include <sy8106a.h> + +#define SY8106A_I2C_ADDR 0x65 +#define SY8106A_VOUT1_SEL 1 +#define SY8106A_VOUT1_SEL_ENABLE (1 << 7) + +static u8 sy8106a_mvolt_to_cfg(int mvolt, int min, int max, int div) +{ + if (mvolt < min) + mvolt = min; + else if (mvolt > max) + mvolt = max; + + return (mvolt - min) / div; +} + +int sy8106a_set_vout1(unsigned int mvolt) +{ + u8 data = sy8106a_mvolt_to_cfg(mvolt, 680, 1950, 10) | SY8106A_VOUT1_SEL_ENABLE; + return i2c_write(SY8106A_I2C_ADDR, SY8106A_VOUT1_SEL, 1, &data, 1); +} diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index c63999a..05bdf56 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o +obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 93dad33..28da9dd 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -105,7 +105,7 @@ static void ns16550_writeb(NS16550_t port, int offset, int value) * As far as we know it doesn't make sense to support selection of * these options at run-time, so use the existing CONFIG options. */ - serial_out_shift(addr, plat->reg_shift, value); + serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); } static int ns16550_readb(NS16550_t port, int offset) @@ -116,7 +116,7 @@ static int ns16550_readb(NS16550_t port, int offset) offset *= 1 << plat->reg_shift; addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset; - return serial_in_shift(addr, plat->reg_shift); + return serial_in_shift(addr + plat->reg_offset, plat->reg_shift); } /* We can clean these up once everything is moved to driver model */ @@ -401,6 +401,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) return -EINVAL; plat->base = addr; + plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "reg-offset", 0); plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg-shift", 0); plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c new file mode 100644 index 0000000..cfbfab7 --- /dev/null +++ b/drivers/serial/serial_stm32x7.c @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <serial.h> +#include <dm/platform_data/serial_stm32x7.h> +#include "serial_stm32x7.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int stm32_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct stm32x7_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; + writel(plat->clock/baudrate, &usart->brr); + + return 0; +} + +static int stm32_serial_getc(struct udevice *dev) +{ + struct stm32x7_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; + + if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0) + return -EAGAIN; + + return readl(&usart->rd_dr); +} + +static int stm32_serial_putc(struct udevice *dev, const char c) +{ + struct stm32x7_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; + + if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0) + return -EAGAIN; + + writel(c, &usart->tx_dr); + + return 0; +} + +static int stm32_serial_pending(struct udevice *dev, bool input) +{ + struct stm32x7_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; + + if (input) + return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0; + else + return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1; +} + +static int stm32_serial_probe(struct udevice *dev) +{ + struct stm32x7_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; + setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE); + + return 0; +} + +static const struct dm_serial_ops stm32_serial_ops = { + .putc = stm32_serial_putc, + .pending = stm32_serial_pending, + .getc = stm32_serial_getc, + .setbrg = stm32_serial_setbrg, +}; + +U_BOOT_DRIVER(serial_stm32) = { + .name = "serial_stm32x7", + .id = UCLASS_SERIAL, + .ops = &stm32_serial_ops, + .probe = stm32_serial_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h new file mode 100644 index 0000000..6190d67 --- /dev/null +++ b/drivers/serial/serial_stm32x7.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SERIAL_STM32_X7_ +#define _SERIAL_STM32_X7_ + +struct stm32_usart { + u32 cr1; + u32 cr2; + u32 cr3; + u32 brr; + u32 gtpr; + u32 rtor; + u32 rqr; + u32 sr; + u32 icr; + u32 rd_dr; + u32 tx_dr; +}; + + +#define USART_CR1_RE (1 << 2) +#define USART_CR1_TE (1 << 3) +#define USART_CR1_UE (1 << 0) + +#define USART_SR_FLAG_RXNE (1 << 5) +#define USART_SR_FLAG_TXE (1 << 7) + +#define USART_BRR_F_MASK 0xFF +#define USART_BRR_M_SHIFT 4 +#define USART_BRR_M_MASK 0xFFF0 + +#endif diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index e79d997..66d54e3 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; -#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ +#define ZYNQ_UART_SR_TXEMPTY (1 << 3) /* TX FIFO empty */ #define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */ #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ @@ -97,7 +97,7 @@ static void _uart_zynq_serial_init(struct uart_zynq *regs) static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) { - if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) + if (!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXEMPTY)) return -EAGAIN; writel(c, ®s->tx_rx_fifo); diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 85f9e85..95cdfa3 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -336,7 +336,6 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, struct omap3_spi_slave *ds = to_omap3_spi(slave); ulong start; int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf); - int irqstatus = readl(&ds->regs->irqstatus); int i=0; /*Enable SPI channel*/ @@ -351,7 +350,6 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, /*Shift in and out 1 byte at time*/ for (i=0; i < len; i++){ /* Write: wait for TX empty (TXS == 1)*/ - irqstatus |= (1<< (4*(ds->slave.bus))); start = get_timer(0); while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) & OMAP3_MCSPI_CHSTAT_TXS)) { diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 677c020..5561f36 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -158,6 +158,7 @@ static int spi_child_pre_probe(struct udevice *dev) slave->max_hz = plat->max_hz; slave->mode = plat->mode; slave->mode_rx = plat->mode_rx; + slave->wordlen = SPI_DEFAULT_WORDLEN; return 0; } diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index b5c974c..409a5c4 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -277,7 +277,7 @@ static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen, } /* TODO: control from sf layer to here through dm-spi */ -#ifdef CONFIG_TI_EDMA3 +#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA) void spi_flash_copy_mmap(void *data, void *offset, size_t len) { unsigned int addr = (unsigned int) (data); diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c index d494ca1..cf3dcc4 100644 --- a/drivers/usb/host/ehci-sunxi.c +++ b/drivers/usb/host/ehci-sunxi.c @@ -35,13 +35,12 @@ static int ehci_usb_probe(struct udevice *dev) * This should go away once we've moved to the driver model for * clocks resp. phys. */ - if (hccr == (void *)SUNXI_USB1_BASE) { - priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; - priv->phy_index = 1; - } else { - priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1; - priv->phy_index = 2; - } + priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; +#ifdef CONFIG_MACH_SUN8I_H3 + priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_OHCI0; +#endif + priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / 0x1000 + 1; + priv->ahb_gate_mask <<= priv->phy_index - 1; setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask); #ifdef CONFIG_SUNXI_GEN_SUN6I @@ -83,6 +82,7 @@ static const struct udevice_id ehci_usb_ids[] = { { .compatible = "allwinner,sun6i-a31-ehci", }, { .compatible = "allwinner,sun7i-a20-ehci", }, { .compatible = "allwinner,sun8i-a23-ehci", }, + { .compatible = "allwinner,sun8i-h3-ehci", }, { .compatible = "allwinner,sun9i-a80-ehci", }, { } }; diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c index 6079272..1b1f651 100644 --- a/drivers/usb/host/ohci-sunxi.c +++ b/drivers/usb/host/ohci-sunxi.c @@ -37,15 +37,14 @@ static int ohci_usb_probe(struct udevice *dev) * This should go away once we've moved to the driver model for * clocks resp. phys. */ - if (regs == (void *)(SUNXI_USB1_BASE + 0x400)) { - priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; - priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; - priv->phy_index = 1; - } else { - priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI1; - priv->usb_gate_mask = CCM_USB_CTRL_OHCI1_CLK; - priv->phy_index = 2; - } + priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; +#ifdef CONFIG_MACH_SUN8I_H3 + priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_EHCI0; +#endif + priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; + priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / 0x1000 + 1; + priv->ahb_gate_mask <<= priv->phy_index - 1; + priv->usb_gate_mask <<= priv->phy_index - 1; setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask); setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask); @@ -86,6 +85,7 @@ static const struct udevice_id ohci_usb_ids[] = { { .compatible = "allwinner,sun6i-a31-ohci", }, { .compatible = "allwinner,sun7i-a20-ohci", }, { .compatible = "allwinner,sun8i-a23-ohci", }, + { .compatible = "allwinner,sun8i-h3-ohci", }, { .compatible = "allwinner,sun9i-a80-ohci", }, { } }; diff --git a/drivers/video/Makefile b/drivers/video/Makefile index d19a1d9..9b635fc 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o +obj-$(CONFIG_VIDEO_S3C) += s3c-fb.o videomodes.o obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o obj-$(CONFIG_VIDEO_SED13806) += sed13806.o obj-$(CONFIG_VIDEO_SM501) += sm501.o diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index f15c964..ef4984b 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -117,7 +117,7 @@ #define VIDEO_HW_BITBLT #endif -#ifdef CONFIG_VIDEO_MXS +#if defined(CONFIG_VIDEO_MXS) || defined(CONFIG_VIDEO_S3C) #define VIDEO_FB_16BPP_WORD_SWAP #endif diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c index c249f04..e16f95a 100644 --- a/drivers/video/console_truetype.c +++ b/drivers/video/console_truetype.c @@ -289,6 +289,7 @@ static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y, } #endif default: + free(data); return -ENOSYS; } diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c new file mode 100644 index 0000000..521eb75 --- /dev/null +++ b/drivers/video/s3c-fb.c @@ -0,0 +1,172 @@ +/* + * S3C24x0 LCD driver + * + * NOTE: Only 16/24 bpp operation with TFT LCD is supported. + * + * Copyright (C) 2014 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <malloc.h> +#include <video_fb.h> + +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/s3c24x0_cpu.h> + +#include "videomodes.h" + +static GraphicDevice panel; + +/* S3C requires the FB to be 4MiB aligned. */ +#define S3CFB_ALIGN (4 << 20) + +#define S3CFB_LCDCON1_CLKVAL(x) ((x) << 8) +#define S3CFB_LCDCON1_PNRMODE_TFT (0x3 << 5) +#define S3CFB_LCDCON1_BPPMODE_TFT_16BPP (0xc << 1) +#define S3CFB_LCDCON1_BPPMODE_TFT_24BPP (0xd << 1) + +#define S3CFB_LCDCON2_VBPD(x) ((x) << 24) +#define S3CFB_LCDCON2_LINEVAL(x) ((x) << 14) +#define S3CFB_LCDCON2_VFPD(x) ((x) << 6) +#define S3CFB_LCDCON2_VSPW(x) ((x) << 0) + +#define S3CFB_LCDCON3_HBPD(x) ((x) << 19) +#define S3CFB_LCDCON3_HOZVAL(x) ((x) << 8) +#define S3CFB_LCDCON3_HFPD(x) ((x) << 0) + +#define S3CFB_LCDCON4_HSPW(x) ((x) << 0) + +#define S3CFB_LCDCON5_BPP24BL (1 << 12) +#define S3CFB_LCDCON5_FRM565 (1 << 11) +#define S3CFB_LCDCON5_HWSWP (1 << 0) + +#define PS2KHZ(ps) (1000000000UL / (ps)) + +/* + * Example: + * setenv videomode video=ctfb:x:800,y:480,depth:16,mode:0,\ + * pclk:30066,le:41,ri:89,up:45,lo:12, + * hs:1,vs:1,sync:100663296,vmode:0 + */ +static void s3c_lcd_init(GraphicDevice *panel, + struct ctfb_res_modes *mode, int bpp) +{ + uint32_t clk_divider; + struct s3c24x0_lcd *regs = s3c24x0_get_base_lcd(); + + /* Stop the controller. */ + clrbits_le32(®s->lcdcon1, 1); + + /* Calculate clock divider. */ + clk_divider = (get_HCLK() / PS2KHZ(mode->pixclock)) / 1000; + clk_divider = DIV_ROUND_UP(clk_divider, 2); + if (clk_divider) + clk_divider -= 1; + + /* Program LCD configuration. */ + switch (bpp) { + case 16: + writel(S3CFB_LCDCON1_BPPMODE_TFT_16BPP | + S3CFB_LCDCON1_PNRMODE_TFT | + S3CFB_LCDCON1_CLKVAL(clk_divider), + ®s->lcdcon1); + writel(S3CFB_LCDCON5_HWSWP | S3CFB_LCDCON5_FRM565, + ®s->lcdcon5); + break; + case 24: + writel(S3CFB_LCDCON1_BPPMODE_TFT_24BPP | + S3CFB_LCDCON1_PNRMODE_TFT | + S3CFB_LCDCON1_CLKVAL(clk_divider), + ®s->lcdcon1); + writel(S3CFB_LCDCON5_BPP24BL, ®s->lcdcon5); + break; + } + + writel(S3CFB_LCDCON2_LINEVAL(mode->yres - 1) | + S3CFB_LCDCON2_VBPD(mode->upper_margin - 1) | + S3CFB_LCDCON2_VFPD(mode->lower_margin - 1) | + S3CFB_LCDCON2_VSPW(mode->vsync_len - 1), + ®s->lcdcon2); + + writel(S3CFB_LCDCON3_HBPD(mode->right_margin - 1) | + S3CFB_LCDCON3_HFPD(mode->left_margin - 1) | + S3CFB_LCDCON3_HOZVAL(mode->xres - 1), + ®s->lcdcon3); + + writel(S3CFB_LCDCON4_HSPW(mode->hsync_len - 1), + ®s->lcdcon4); + + /* Write FB address. */ + writel(panel->frameAdrs >> 1, ®s->lcdsaddr1); + writel((panel->frameAdrs + + (mode->xres * mode->yres * panel->gdfBytesPP)) >> 1, + ®s->lcdsaddr2); + writel(mode->xres * bpp / 16, ®s->lcdsaddr3); + + /* Start the controller. */ + setbits_le32(®s->lcdcon1, 1); +} + +void *video_hw_init(void) +{ + int bpp = -1; + char *penv; + void *fb; + struct ctfb_res_modes mode; + + puts("Video: "); + + /* Suck display configuration from "videomode" variable */ + penv = getenv("videomode"); + if (!penv) { + puts("S3CFB: 'videomode' variable not set!\n"); + return NULL; + } + + bpp = video_get_params(&mode, penv); + + /* fill in Graphic device struct */ + sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp); + + panel.winSizeX = mode.xres; + panel.winSizeY = mode.yres; + panel.plnSizeX = mode.xres; + panel.plnSizeY = mode.yres; + + switch (bpp) { + case 24: + panel.gdfBytesPP = 4; + panel.gdfIndex = GDF_32BIT_X888RGB; + break; + case 16: + panel.gdfBytesPP = 2; + panel.gdfIndex = GDF_16BIT_565RGB; + break; + default: + printf("S3CFB: Invalid BPP specified! (bpp = %i)\n", bpp); + return NULL; + } + + panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP; + + /* Allocate framebuffer */ + fb = memalign(S3CFB_ALIGN, roundup(panel.memSize, S3CFB_ALIGN)); + if (!fb) { + printf("S3CFB: Error allocating framebuffer!\n"); + return NULL; + } + + /* Wipe framebuffer */ + memset(fb, 0, panel.memSize); + + panel.frameAdrs = (u32)fb; + + printf("%s\n", panel.modeIdent); + + /* Start framebuffer */ + s3c_lcd_init(&panel, &mode, bpp); + + return (void *)&panel; +} diff --git a/drivers/video/stb_truetype.h b/drivers/video/stb_truetype.h index 91d8e6f..26e483c 100644 --- a/drivers/video/stb_truetype.h +++ b/drivers/video/stb_truetype.h @@ -2426,7 +2426,10 @@ STBTT_DEF unsigned char *stbtt_GetGlyphBitmapSubpixel(const stbtt_fontinfo *info if (scale_x == 0) scale_x = scale_y; if (scale_y == 0) { - if (scale_x == 0) return NULL; + if (scale_x == 0) { + STBTT_free(vertices, info->userdata); + return NULL; + } scale_y = scale_x; } diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index ffc6811..a94b1e2 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -3,7 +3,7 @@ * * common parts used by B&R AM335x based boards * - * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> - + * Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> - * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com * * SPDX-License-Identifier: GPL-2.0+ @@ -12,25 +12,9 @@ #ifndef __BUR_AM335X_COMMON_H__ #define __BUR_AM335X_COMMON_H__ /* ------------------------------------------------------------------------- */ -#define BUR_COMMON_ENV \ -"usbscript=usb start && fatload usb 0 0x80000000 usbscript.img && source\0" \ -"brdefaultip=if test -r ${ipaddr}; then; else" \ -" setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;" \ -" setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;\0" \ -"netconsole=echo switching to network console ...; " \ -"if dhcp; then; else run brdefaultip; fi; setenv ncip ${serverip}; " \ -"setcurs 1 9; lcdputs myip; setcurs 10 9; lcdputs ${ipaddr};" \ -"setcurs 1 10;lcdputs serverip; setcurs 10 10; lcdputs ${serverip};" \ -"setenv stdout nc;setenv stdin nc;setenv stderr nc\0" - -#define CONFIG_PREBOOT "run brdefaultip" -#define CONFIG_CMD_TIME - - #define CONFIG_AM33XX #define CONFIG_OMAP #define CONFIG_OMAP_COMMON -#define CONFIG_BOARD_LATE_INIT #define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ @@ -53,24 +37,11 @@ #define CONFIG_BAUDRATE 115200 /* Network defines */ -#define CONFIG_CMD_DHCP -#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_NET_RETRY_COUNT 2 -#define CONFIG_CMD_PING #define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ #define CONFIG_MII /* Required in net/eth.c */ -#define CONFIG_SPL_ETH_SUPPORT #define CONFIG_PHYLIB #define CONFIG_PHY_NATSEMI -#define CONFIG_SPL_NET_SUPPORT -#define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */ -#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" -/* Network console */ -#define CONFIG_NETCONSOLE 1 -#define CONFIG_BOOTP_MAY_FAIL /* if we don't have DHCP environment */ + /* * SPL related defines. The Public RAM memory map the ROM defines the * area between 0x402F0400 and 0x4030B800 as a download area and @@ -109,42 +80,8 @@ #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 #define CONFIG_SYS_I2C_OMAP24XX -#define CONFIG_CMD_I2C /* GPIO */ #define CONFIG_OMAP_GPIO -/* - * ---------------------------------------------------------------------------- - * The following are general good-enough settings for U-Boot. We set a - * large malloc pool as we generally have a lot of DDR, and we opt for - * function over binary size in the main portion of U-Boot as this is - * generally easily constrained later if needed. We enable the config - * options that give us information in the environment about what board - * we are on so we do not need to rely on the command prompt. We set a - * console baudrate of 115200 and use the default baud rate table. - */ -#define CONFIG_SYS_MALLOC_LEN (5120 << 10) -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE - -/* As stated above, the following choices are optional. */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_AUTO_COMPLETE -#define CONFIG_CMDLINE_EDITING -#define CONFIG_VERSION_VARIABLE - -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 64 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 512 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\ - sizeof(CONFIG_SYS_PROMPT) + 16) -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* * Our platforms make use of SPL to initalize the hardware (primarily diff --git a/include/configs/bur_cfg_common.h b/include/configs/bur_cfg_common.h new file mode 100644 index 0000000..f183775 --- /dev/null +++ b/include/configs/bur_cfg_common.h @@ -0,0 +1,64 @@ +/* + * bur_cfg_common.h + * + * common parts used over all B&R boards + * + * Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> - + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BUR_CFG_COMMON_H__ +#define __BUR_CFG_COMMON_H__ +/* ------------------------------------------------------------------------- */ +#define BUR_COMMON_ENV \ +"usbscript=usb start && fatload usb 0 ${scradr} usbscript.img &&" \ +" source ${scradr}\0" \ +"brdefaultip=if test -r ${ipaddr}; then; else" \ +" setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;" \ +" setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;\0" \ +"netconsole=echo switching to network console ...; " \ +"if dhcp; then; else run brdefaultip; fi; setenv ncip ${serverip}; " \ +"setcurs 1 9; lcdputs myip; setcurs 10 9; lcdputs ${ipaddr};" \ +"setcurs 1 10;lcdputs serverip; setcurs 10 10; lcdputs ${serverip};" \ +"setenv stdout nc;setenv stdin nc;setenv stderr nc\0" + +#define CONFIG_PREBOOT "run cfgscr; run brdefaultip" + +#define CONFIG_BOARD_LATE_INIT + +/* Network defines */ +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 2 + +/* Network console */ +#define CONFIG_NETCONSOLE 1 +#define CONFIG_BOOTP_MAY_FAIL /* if we don't have DHCP environment */ + +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE + +/* As stated above, the following choices are optional. */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_VERSION_VARIABLE + +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 64 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\ + sizeof(CONFIG_SYS_PROMPT) + 16) +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#endif /* __BUR_CFG_COMMON_H__ */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index d3cd38d..1c1951c 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -18,10 +18,12 @@ #include <asm/arch/omap.h> /* Serial support */ -#define CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 48000000 #define CONFIG_SYS_NS16550_COM1 0x44e09000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#endif /* NAND support */ #define CONFIG_NAND @@ -68,9 +70,7 @@ #define CONFIG_AM437X_USB2PHY2_HOST /* SPI Flash support */ -#define CONFIG_SPI_FLASH #define CONFIG_TI_SPI_MMAP -#define CONFIG_SPI_FLASH_BAR #define CONFIG_SF_DEFAULT_SPEED 48000000 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 @@ -98,9 +98,8 @@ #undef CONFIG_SPL_OS_BOOT #undef CONFIG_SPL_GPIO_SUPPORT #undef CONFIG_SPL_NAND_SUPPORT -#undef CONFIG_SPL_BOARD_INIT -#undef CONFIG_BOOTDELAY -#include <config_distro_defaults.h> +#undef CONFIG_SYS_MONITOR_LEN +#undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR #define CONFIG_ZERO_BOOTDELAY_CHECK #undef CONFIG_CMD_IMLS @@ -165,8 +164,12 @@ #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20)) #define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x480 #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT #endif /* __CONFIG_CM_T43_H */ diff --git a/include/configs/kwb.h b/include/configs/kwb.h index 45253b8..60e6496 100644 --- a/include/configs/kwb.h +++ b/include/configs/kwb.h @@ -12,6 +12,7 @@ #ifndef __CONFIG_KWB_H__ #define __CONFIG_KWB_H__ +#include <configs/bur_cfg_common.h> #include <configs/bur_am335x_common.h> /* ------------------------------------------------------------------------- */ #define CONFIG_AM335X_LCD @@ -27,6 +28,9 @@ #define CONFIG_BMP_24BMP #define CONFIG_BMP_32BPP +/* memory */ +#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) + /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -103,10 +107,9 @@ BUR_COMMON_ENV \ #define CONFIG_BOOTDELAY 0 /* undefine command which we not need here */ -#undef CONFIG_BOOTM_NETBSD -#undef CONFIG_BOOTM_PLAN9 -#undef CONFIG_BOOTM_RTEMS -#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS /* Support both device trees and ATAGs. */ #define CONFIG_OF_LIBFDT @@ -122,17 +125,11 @@ BUR_COMMON_ENV \ #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT /* attention! not only for gadget, enables also highspeed in hostmode */ #define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_MUSB_HOST #define CONFIG_AM335X_USB0 #define CONFIG_AM335X_USB0_MODE MUSB_HOST #define CONFIG_AM335X_USB1 #define CONFIG_AM335X_USB1_MODE MUSB_HOST -#ifdef CONFIG_USB_MUSB_HOST -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE -#endif /* CONFIG_USB_MUSB_HOST */ - #undef CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 @@ -151,4 +148,4 @@ BUR_COMMON_ENV \ #define CONFIG_CMD_FS_GENERIC #endif /* CONFIG_MMC, ... */ -#endif /* ! __CONFIG_TSERIES_H__ */ +#endif /* __CONFIG_KWB_H__ */ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index fba2a12..0fc9d1c 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -40,7 +40,7 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO - +#define CONFIG_BOARD_LATE_INIT #define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS diff --git a/include/configs/rpi-common.h b/include/configs/rpi-common.h index 97e5d2c..e07fa65 100644 --- a/include/configs/rpi-common.h +++ b/include/configs/rpi-common.h @@ -68,6 +68,7 @@ #define CONFIG_FB_ADDR 0 #define CONFIG_VIDEO_BCM2835 #define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10 /* SD/MMC configuration */ #define CONFIG_GENERIC_MMC diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h new file mode 100644 index 0000000..e1b8bcb --- /dev/null +++ b/include/configs/stm32f746-disco.h @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_OF_LIBFDT +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x20050000 +#define CONFIG_SYS_TEXT_BASE 0x08000000 + +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +/* + * Configuration of the external SDRAM memory + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_RAM_SIZE ((64 + 192) << 10) +#define CONFIG_SYS_RAM_CS 1 +#define CONFIG_SYS_RAM_FREQ_DIV 2 +#define CONFIG_SYS_RAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE +#define CONFIG_SYS_LOAD_ADDR 0x20000000 +#define CONFIG_LOADADDR 0x20000000 + +#define CONFIG_SYS_MAX_FLASH_SECT 12 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 + +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_FLASH +#else +#define CONFIG_ENV_IS_NOWHERE +#endif +#define CONFIG_ENV_SIZE (8 << 10) + +#define CONFIG_STM32_GPIO +#define CONFIG_STM32X7_SERIAL + +#define CONFIG_SYS_CLK_FREQ 16*1000*1000 /* 180 MHz */ +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN (16 * 1024) +#define CONFIG_STACKSIZE (64 << 10) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" +#define CONFIG_BOOTCOMMAND \ + "run bootcmd_romfs" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ + "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \ + "bootm 0x08044000 - 0x08042000\0" + +#define CONFIG_BOOTDELAY 3 + +/* + * Command line configuration. + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_CMD_MEM +#define CONFIG_CMD_TIMER +#undef CONFIG_CMD_IMLS +#endif /* __CONFIG_H */ diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h index 781ff6e..7c0ab1e 100644 --- a/include/configs/sun8i.h +++ b/include/configs/sun8i.h @@ -18,7 +18,11 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif -#define CONFIG_SUNXI_USB_PHYS 2 +#ifdef CONFIG_MACH_SUN8I_H3 + #define CONFIG_SUNXI_USB_PHYS 4 +#else + #define CONFIG_SUNXI_USB_PHYS 2 +#endif #ifndef CONFIG_MACH_SUN8I_A83T diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index b4dfb3c..40850e5 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -206,7 +206,8 @@ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK /* I2C */ -#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER +#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ + defined CONFIG_SY8106A_POWER #define CONFIG_SPL_I2C_SUPPORT #endif @@ -240,7 +241,8 @@ extern int soft_i2c_gpio_scl; /* PMU */ #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ - defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER + defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER || \ + defined CONFIG_SY8106A_POWER #define CONFIG_SPL_POWER_SUPPORT #endif diff --git a/include/configs/tseries.h b/include/configs/tseries.h index 93e3454..43cf965 100644 --- a/include/configs/tseries.h +++ b/include/configs/tseries.h @@ -12,6 +12,7 @@ #ifndef __CONFIG_TSERIES_H__ #define __CONFIG_TSERIES_H__ +#include <configs/bur_cfg_common.h> #include <configs/bur_am335x_common.h> /* ------------------------------------------------------------------------- */ #define CONFIG_AM335X_LCD @@ -30,6 +31,10 @@ #define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000 #define CONFIG_BOOTCOUNT_LIMIT #define CONFIG_BOOTCOUNT_AM33XX + +/* memory */ +#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) + /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -204,7 +209,6 @@ MMCARGS #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x8000000 #define CONFIG_NAND_OMAP_GPMC -#define CONFIG_CMD_NAND /* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */ #define CONFIG_NAND_OMAP_ELM #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW @@ -249,23 +253,15 @@ MMCARGS #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT /* attention! not only for gadget, enables also highspeed in hostmode */ #define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_MUSB_HOST #define CONFIG_AM335X_USB0 #define CONFIG_AM335X_USB0_MODE MUSB_HOST #define CONFIG_AM335X_USB1 #define CONFIG_AM335X_USB1_MODE MUSB_HOST -#ifdef CONFIG_USB_MUSB_HOST -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE -#endif /* CONFIG_USB_MUSB_HOST */ - #if defined(CONFIG_SPI_BOOT) /* McSPI IP block */ #define CONFIG_SPI #define CONFIG_OMAP3_SPI -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_SPL_SPI_SUPPORT diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 28622de..da868b8 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -89,18 +89,14 @@ # define CONFIG_CMD_SF #endif -#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) +#if defined(CONFIG_ZYNQ_SDHCI) # define CONFIG_MMC # define CONFIG_GENERIC_MMC # define CONFIG_SDHCI -# define CONFIG_ZYNQ_SDHCI # define CONFIG_CMD_MMC # ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ # define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000 # endif -#endif - -#if defined(CONFIG_ZYNQ_SDHCI) # define CONFIG_FAT_WRITE # define CONFIG_CMD_EXT4_WRITE #endif diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index 9906c42..337312e 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -13,7 +13,6 @@ #ifndef __CONFIG_ZYNQMP_EP_H #define __CONFIG_ZYNQMP_EP_H -#define CONFIG_ZYNQ_SDHCI0 #define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 #define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9) #define CONFIG_ZYNQ_I2C0 diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index e8c3ef0..4a81d41 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -50,6 +50,7 @@ # define CONFIG_MII # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # define CONFIG_PHY_MARVELL +# define CONFIG_PHY_REALTEK # define CONFIG_BOOTP_SERVERIP # define CONFIG_BOOTP_BOOTPATH # define CONFIG_BOOTP_GATEWAY @@ -86,11 +87,10 @@ #endif /* MMC */ -#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) +#if defined(CONFIG_ZYNQ_SDHCI) # define CONFIG_MMC # define CONFIG_GENERIC_MMC # define CONFIG_SDHCI -# define CONFIG_ZYNQ_SDHCI # define CONFIG_CMD_MMC # define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 #endif @@ -131,7 +131,7 @@ "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" -# if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) +# if defined(CONFIG_ZYNQ_SDHCI) # define CONFIG_DFU_MMC # define DFU_ALT_INFO_MMC \ "dfu_mmc_info=" \ @@ -197,7 +197,11 @@ /* Environment */ #ifndef CONFIG_ENV_IS_NOWHERE # ifndef CONFIG_SYS_NO_FLASH +/* Environment in NOR flash */ # define CONFIG_ENV_IS_IN_FLASH +# elif defined(CONFIG_ZYNQ_QSPI) +/* Environment in Serial Flash */ +# define CONFIG_ENV_IS_IN_SPI_FLASH # elif defined(CONFIG_SYS_NO_FLASH) # define CONFIG_ENV_IS_NOWHERE # endif @@ -227,8 +231,7 @@ "usbboot=if usb start; then " \ "echo Copying FIT from USB to RAM... && " \ "load usb 0 ${load_addr} ${fit_image} && " \ - "bootm ${load_addr}\0" \ - "fi\0" \ + "bootm ${load_addr}; fi\0" \ DFU_ALT_INFO #define CONFIG_BOOTCOMMAND "run $modeboot" @@ -288,9 +291,7 @@ #define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) /* Boot FreeBSD/vxWorks from an ELF image */ -#if defined(CONFIG_ZYNQ_BOOT_FREEBSD) -# define CONFIG_SYS_MMC_MAX_DEVICE 1 -#endif +#define CONFIG_SYS_MMC_MAX_DEVICE 1 #define CONFIG_SYS_LDSCRIPT "arch/arm/mach-zynq/u-boot.lds" @@ -307,11 +308,12 @@ #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_RAM_DEVICE #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-zynq/u-boot-spl.lds" /* MMC support */ -#ifdef CONFIG_ZYNQ_SDHCI0 +#ifdef CONFIG_ZYNQ_SDHCI #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h index 169ee36..e66088d 100644 --- a/include/configs/zynq_microzed.h +++ b/include/configs/zynq_microzed.h @@ -10,12 +10,8 @@ #ifndef __CONFIG_ZYNQ_MICROZED_H #define __CONFIG_ZYNQ_MICROZED_H -#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) - #define CONFIG_SYS_NO_FLASH -#define CONFIG_ZYNQ_SDHCI0 - #include <configs/zynq-common.h> #endif /* __CONFIG_ZYNQ_MICROZED_H */ diff --git a/include/configs/zynq_picozed.h b/include/configs/zynq_picozed.h index 47fad66..adc4d0f 100644 --- a/include/configs/zynq_picozed.h +++ b/include/configs/zynq_picozed.h @@ -10,13 +10,9 @@ #ifndef __CONFIG_ZYNQ_PICOZED_H #define __CONFIG_ZYNQ_PICOZED_H -#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) - #define CONFIG_SYS_NO_FLASH -#define CONFIG_ZYNQ_SDHCI1 #define CONFIG_ZYNQ_USB -#define CONFIG_ZYNQ_BOOT_FREEBSD #include <configs/zynq-common.h> diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h index c52a655..8a04590 100644 --- a/include/configs/zynq_zc70x.h +++ b/include/configs/zynq_zc70x.h @@ -10,15 +10,11 @@ #ifndef __CONFIG_ZYNQ_ZC70X_H #define __CONFIG_ZYNQ_ZC70X_H -#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) - #define CONFIG_SYS_NO_FLASH -#define CONFIG_ZYNQ_SDHCI0 #define CONFIG_ZYNQ_USB #define CONFIG_ZYNQ_I2C0 #define CONFIG_ZYNQ_EEPROM -#define CONFIG_ZYNQ_BOOT_FREEBSD #include <configs/zynq-common.h> diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h index 32ea1f3..35622ae 100644 --- a/include/configs/zynq_zc770.h +++ b/include/configs/zynq_zc770.h @@ -10,20 +10,11 @@ #ifndef __CONFIG_ZYNQ_ZC770_H #define __CONFIG_ZYNQ_ZC770_H -#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024) - #define CONFIG_SYS_NO_FLASH -#if defined(CONFIG_ZC770_XM010) -# define CONFIG_ZYNQ_SDHCI0 - -#elif defined(CONFIG_ZC770_XM011) - -#elif defined(CONFIG_ZC770_XM012) +#if defined(CONFIG_ZC770_XM012) # undef CONFIG_SYS_NO_FLASH -#elif defined(CONFIG_ZC770_XM013) - #endif #include <configs/zynq-common.h> diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h index 1488bfe..150cb4a 100644 --- a/include/configs/zynq_zed.h +++ b/include/configs/zynq_zed.h @@ -10,13 +10,9 @@ #ifndef __CONFIG_ZYNQ_ZED_H #define __CONFIG_ZYNQ_ZED_H -#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024) - #define CONFIG_SYS_NO_FLASH #define CONFIG_ZYNQ_USB -#define CONFIG_ZYNQ_SDHCI0 -#define CONFIG_ZYNQ_BOOT_FREEBSD #include <configs/zynq-common.h> diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h index c53ba79..0882fe3 100644 --- a/include/configs/zynq_zybo.h +++ b/include/configs/zynq_zybo.h @@ -11,13 +11,14 @@ #ifndef __CONFIG_ZYNQ_ZYBO_H #define __CONFIG_ZYNQ_ZYBO_H -#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024) - #define CONFIG_SYS_NO_FLASH #define CONFIG_ZYNQ_USB -#define CONFIG_ZYNQ_SDHCI0 -#define CONFIG_ZYNQ_BOOT_FREEBSD +#define CONFIG_ZYNQ_I2C0 +#define CONFIG_ZYNQ_I2C1 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_DISPLAY +#define CONFIG_I2C_EDID /* Define ZYBO PS Clock Frequency to 50MHz */ #define CONFIG_ZYNQ_PS_CLK_FREQ 50000000UL diff --git a/include/dm/platform_data/serial_stm32x7.h b/include/dm/platform_data/serial_stm32x7.h new file mode 100644 index 0000000..328a8a3 --- /dev/null +++ b/include/dm/platform_data/serial_stm32x7.h @@ -0,0 +1,17 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SERIAL_STM32x7_H +#define __SERIAL_STM32x7_H + +/* Information about a serial port */ +struct stm32x7_serial_platdata { + struct stm32_usart *base; /* address of registers in physical memory */ + unsigned int clock; +}; + +#endif /* __SERIAL_STM32x7_H */ diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 73cd3ac..3bea308 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -31,6 +31,7 @@ enum uclass_id { UCLASS_CROS_EC, /* Chrome OS EC */ UCLASS_DISK, /* Disk controller, e.g. SATA */ UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */ + UCLASS_DMA, /* Direct Memory Access */ UCLASS_RAM, /* RAM controller */ UCLASS_ETH, /* Ethernet device */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ diff --git a/include/dma.h b/include/dma.h new file mode 100644 index 0000000..71fa77f --- /dev/null +++ b/include/dma.h @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DMA_H_ +#define _DMA_H_ + +/* + * enum dma_direction - dma transfer direction indicator + * @DMA_MEM_TO_MEM: Memcpy mode + * @DMA_MEM_TO_DEV: From Memory to Device + * @DMA_DEV_TO_MEM: From Device to Memory + * @DMA_DEV_TO_DEV: From Device to Device + */ +enum dma_direction { + DMA_MEM_TO_MEM, + DMA_MEM_TO_DEV, + DMA_DEV_TO_MEM, + DMA_DEV_TO_DEV, +}; + +#define DMA_SUPPORTS_MEM_TO_MEM BIT(0) +#define DMA_SUPPORTS_MEM_TO_DEV BIT(1) +#define DMA_SUPPORTS_DEV_TO_MEM BIT(2) +#define DMA_SUPPORTS_DEV_TO_DEV BIT(3) + +/* + * struct dma_ops - Driver model DMA operations + * + * The uclass interface is implemented by all DMA devices which use + * driver model. + */ +struct dma_ops { + /* + * Get the current timer count + * + * @dev: The DMA device + * @direction: direction of data transfer should be one from + enum dma_direction + * @dst: Destination pointer + * @src: Source pointer + * @len: Length of the data to be copied. + * @return: 0 if OK, -ve on error + */ + int (*transfer)(struct udevice *dev, int direction, void *dst, + void *src, size_t len); +}; + +/* + * struct dma_dev_priv - information about a device used by the uclass + * + * @supported: mode of transfers that DMA can support, should be + * one/multiple of DMA_SUPPORTS_* + */ +struct dma_dev_priv { + u32 supported; +}; + +/* + * dma_get_device - get a DMA device which supports transfer + * type of transfer_type + * + * @transfer_type - transfer type should be one/multiple of + * DMA_SUPPORTS_* + * @devp - udevice pointer to return the found device + * @return - will return on success and devp will hold the + * pointer to the device + */ +int dma_get_device(u32 transfer_type, struct udevice **devp); + +/* + * dma_memcpy - try to use DMA to do a mem copy which will be + * much faster than CPU mem copy + * + * @dst - destination pointer + * @src - souce pointer + * @len - data length to be copied + * @return - on successful transfer returns no of bytes + transferred and on failure return error code. + */ +int dma_memcpy(void *dst, void *src, size_t len); + +#endif /* _DMA_H_ */ diff --git a/include/ns16550.h b/include/ns16550.h index 4e62067..5eeacd6 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -54,6 +54,7 @@ */ struct ns16550_platdata { unsigned long base; + int reg_offset; int reg_shift; int clock; }; diff --git a/include/power/tps65218.h b/include/power/tps65218.h index 63fc7b3..4d68faa 100644 --- a/include/power/tps65218.h +++ b/include/power/tps65218.h @@ -8,6 +8,8 @@ #ifndef __POWER_TPS65218_H__ #define __POWER_TPS65218_H__ +#include <linux/bitops.h> + /* I2C chip address */ #define TPS65218_CHIP_PM 0x24 @@ -60,8 +62,18 @@ enum { #define TPS65218_DCDC_VOLT_SEL_1260MV 0x29 #define TPS65218_DCDC_VOLT_SEL_1330MV 0x30 +#define TPS65218_CC_STAT (BIT(0) | BIT(1)) +#define TPS65218_STATE (BIT(2) | BIT(3)) +#define TPS65218_PB_STATE BIT(4) +#define TPS65218_AC_STATE BIT(5) +#define TPS65218_EE BIT(6) +#define TPS65218_FSEAL BIT(7) + +int tps65218_reg_read(uchar dest_reg, uchar *dest_val); int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, uchar mask); int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel); +int tps65218_toggle_fseal(void); +int tps65218_lock_fseal(void); int power_tps65218_init(unsigned char bus); #endif /* __POWER_TPS65218_H__ */ diff --git a/include/sy8106a.h b/include/sy8106a.h new file mode 100644 index 0000000..32e8c43 --- /dev/null +++ b/include/sy8106a.h @@ -0,0 +1,11 @@ +/* + * (C) Copyright 2016 + * Jelle van der Waa <jelle@vdwaa.nl> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _SY8106A_PMIC_H_ + +int sy8106a_set_vout1(unsigned int mvolt); + +#endif diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py index bc2bd76..d6502c6 100644 --- a/test/py/u_boot_console_base.py +++ b/test/py/u_boot_console_base.py @@ -303,8 +303,13 @@ class ConsoleBase(object): if not self.config.gdbserver: self.p.timeout = 30000 self.p.logfile_read = self.logstream - if self.config.buildconfig.get('config_spl', False) == 'y': - m = self.p.expect([pattern_u_boot_spl_signon] + self.bad_patterns) + bcfg = self.config.buildconfig + config_spl = bcfg.get('config_spl', 'n') == 'y' + config_spl_serial_support = bcfg.get('config_spl_serial_support', + 'n') == 'y' + if config_spl and config_spl_serial_support: + m = self.p.expect([pattern_u_boot_spl_signon] + + self.bad_patterns) if m != 0: raise Exception('Bad pattern found on console: ' + self.bad_pattern_ids[m - 1]) diff --git a/tools/Makefile b/tools/Makefile index 1382b05..2881a7c 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -129,6 +129,14 @@ endif ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_FIT_SIGNATURE),) HOSTLOADLIBES_mkimage += \ $(shell pkg-config --libs libssl libcrypto 2> /dev/null || echo "-lssl -lcrypto") + +# OS X deprecate openssl in favour of CommonCrypto, supress deprecation +# warnings on those systems +ifeq ($(HOSTOS),darwin) +HOSTCFLAGS_mxsimage.o += -Wno-deprecated-declarations +HOSTCFLAGS_image-sig.o += -Wno-deprecated-declarations +HOSTCFLAGS_rsa-sign.o += -Wno-deprecated-declarations +endif endif HOSTLOADLIBES_dumpimage := $(HOSTLOADLIBES_mkimage) diff --git a/tools/buildman/README b/tools/buildman/README index 66502af..6f41008 100644 --- a/tools/buildman/README +++ b/tools/buildman/README @@ -157,7 +157,7 @@ aarch64: /opt/linaro/gcc-linaro-aarch64-none-elf-4.8-2013.10_linux x86: i386 blackfin: bfin nds32: nds32le -openrisc: or32 +openrisc: or1k This selects the available toolchain paths. Add the base directory for @@ -362,6 +362,10 @@ nios2: http://sourcery.mentor.com/public/gnu_toolchain/nios2-linux-gnu/ sh: http://sourcery.mentor.com/public/gnu_toolchain/sh-linux-gnu/ renesas-4.4-200-sh-linux-gnu-i686-pc-linux-gnu.tar.bz2 +Note openrisc kernel.org toolchain is out of date, download latest one from +http://opencores.org/or1k/OpenRISC_GNU_tool_chain#Prebuilt_versions, eg: +ftp://ocuser:ocuser@openrisc.opencores.org/toolchain/gcc-or1k-elf-4.8.1-x86.tar.bz2. + Buildman should now be set up to use your new toolchain. At the time of writing, U-Boot has these architectures: diff --git a/tools/mkimage.c b/tools/mkimage.c index 8f8b6df..facebcd 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -129,7 +129,7 @@ int main(int argc, char **argv) case 'a': if (--argc <= 0) usage (); - params.addr = strtoul (*++argv, &ptr, 16); + params.addr = strtoull(*++argv, &ptr, 16); if (*ptr) { fprintf (stderr, "%s: invalid load address %s\n", @@ -146,7 +146,7 @@ int main(int argc, char **argv) case 'e': if (--argc <= 0) usage (); - params.ep = strtoul (*++argv, &ptr, 16); + params.ep = strtoull(*++argv, &ptr, 16); if (*ptr) { fprintf (stderr, "%s: invalid entry point %s\n", diff --git a/tools/moveconfig.py b/tools/moveconfig.py index 1b53f95..6f71b55 100755 --- a/tools/moveconfig.py +++ b/tools/moveconfig.py @@ -184,6 +184,9 @@ SLEEP_TIME=0.03 # nds32: http://osdk.andestech.com/packages/nds32le-linux-glibc-v1.tgz # nios2: https://sourcery.mentor.com/GNUToolchain/subscription42545 # sh: http://sourcery.mentor.com/public/gnu_toolchain/sh-linux-gnu +# +# openrisc kernel.org toolchain is out of date, download latest one from +# http://opencores.org/or1k/OpenRISC_GNU_tool_chain#Prebuilt_versions CROSS_COMPILE = { 'arc': 'arc-linux-', 'aarch64': 'aarch64-linux-', @@ -195,7 +198,7 @@ CROSS_COMPILE = { 'mips': 'mips-linux-', 'nds32': 'nds32le-linux-', 'nios2': 'nios2-linux-gnu-', - 'openrisc': 'or32-linux-', + 'openrisc': 'or1k-elf-', 'powerpc': 'powerpc-linux-', 'sh': 'sh-linux-gnu-', 'sparc': 'sparc-linux-', |