diff options
| -rw-r--r-- | board/freescale/mx6slevk/mx6slevk.c | 92 | ||||
| -rw-r--r-- | include/configs/mx6slevk.h | 15 |
2 files changed, 101 insertions, 6 deletions
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index a40c1be..1e2f67b 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -60,6 +60,10 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ PAD_CTL_SRE_FAST) + +#define ELAN_INTR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_HYS) + #define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS) @@ -132,6 +136,12 @@ static iomux_v3_cfg_t const fec_pads[] = { MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +static iomux_v3_cfg_t const elan_pads[] = { + MX6_PAD_EPDC_PWRCTRL2__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EPDC_PWRCTRL3__GPIO_2_10 | MUX_PAD_CTRL(ELAN_INTR_PAD_CTRL), + MX6_PAD_KEY_COL6__GPIO_4_4 | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + #ifdef CONFIG_MXC_SPI static iomux_v3_cfg_t ecspi1_pads[] = { MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -351,14 +361,45 @@ struct i2c_pads_info i2c_pad_info1 = { int power_init_board(void) { - struct pmic *p; + struct pmic *pfuze; + unsigned int reg; + int ret; - p = pfuze_common_init(I2C_PMIC); - if (!p) + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) return -ENODEV; - return pfuze_mode_init(p, APS_PFM); + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + /* set SW1AB staby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + + return 0; } + #endif #ifdef CONFIG_FEC_MXC @@ -603,6 +644,17 @@ void epdc_power_off(void) } #endif +void setup_elan_pads(void) +{ +#define TOUCH_CS IMX_GPIO_NR(2, 9) +#define TOUCH_INT IMX_GPIO_NR(2, 10) +#define TOUCH_RST IMX_GPIO_NR(4, 4) + imx_iomux_v3_setup_multiple_pads(elan_pads, ARRAY_SIZE(elan_pads)); + gpio_request(TOUCH_CS, "TOUCH CS"); + gpio_request(TOUCH_INT, "TOUCH Interrupt"); + gpio_request(TOUCH_RST, "TOUCH Reset"); +} + int board_init(void) { /* address of boot parameters */ @@ -610,6 +662,7 @@ int board_init(void) #ifdef CONFIG_SYS_I2C_MXC setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_elan_pads(); #endif #ifdef CONFIG_FEC_MXC @@ -627,6 +680,37 @@ int board_init(void) return 0; } +void elan_init(void) +{ + gpio_direction_input(TOUCH_INT); + /* + * If epdc panel not plugged in, gpio_get_value(TOUCH_INT) will + * return 1. And no need to mdelay, which will make i2c operation + * slow. + * If epdc panel plugged in, gpio_get_value(TOUCH_INT) will + * return 0. And elan init flow will be executed. + */ + if (gpio_get_value(TOUCH_INT)) + return; + gpio_direction_output(TOUCH_CS , 1); + gpio_set_value(TOUCH_CS, 0); + gpio_direction_output(TOUCH_RST , 1); + gpio_set_value(TOUCH_RST, 0); + mdelay(10); + gpio_set_value(TOUCH_RST, 1); + gpio_set_value(TOUCH_CS, 1); + mdelay(100); +} + +/* + * This function overwrite the function defined in + * drivers/i2c/mxc_i2c.c, which is a weak symbol + */ +void i2c_force_reset_slave(void) +{ + elan_init(); +} + int board_late_init(void) { #ifdef CONFIG_ENV_IS_IN_MMC diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index d9ae9a4..2a7102d 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -25,6 +25,9 @@ /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/ +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ /* I2C Configs */ #define CONFIG_SYS_I2C @@ -44,6 +47,7 @@ #define CONFIG_MII #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 0 #define CONFIG_PHYLIB @@ -73,9 +77,9 @@ "fdt_addr=0x83000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=1\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ @@ -159,6 +163,9 @@ /* Environment organization */ #define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #if defined CONFIG_SYS_BOOT_SPINOR #define CONFIG_ENV_IS_IN_SPI_FLASH @@ -173,6 +180,10 @@ #define CONFIG_ENV_IS_IN_MMC #endif +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + #ifdef CONFIG_CMD_SF #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 |