diff options
18 files changed, 3371 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig index 8dfb4c9..e64fa78 100644 --- a/arch/arm/cpu/armv7/mx7/Kconfig +++ b/arch/arm/cpu/armv7/mx7/Kconfig @@ -23,6 +23,13 @@ config TARGET_MX7DSABRESD select DM select DM_THERMAL +config TARGET_MX7D_12X12_LPDDR3_ARM2 + bool "Support mx7d_12x12_lpddr3_arm2" + select BOARD_LATE_INIT + select MX7D + select DM + select DM_THERMAL + config TARGET_WARP7 bool "warp7" select BOARD_LATE_INIT @@ -43,6 +50,7 @@ config SYS_SOC default "mx7" source "board/freescale/mx7dsabresd/Kconfig" +source "board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig" source "board/toradex/colibri_imx7/Kconfig" source "board/warp7/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5b3ae83..a5db6f3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -366,7 +366,10 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ imx7d-sdb-epdc.dtb \ imx7d-sdb-gpmi-weim.dtb \ imx7d-sdb-qspi.dtb \ - imx7d-sdb-reva.dtb + imx7d-sdb-reva.dtb \ + imx7d-12x12-lpddr3-arm2.dtb \ + imx7d-12x12-lpddr3-arm2-ecspi.dtb \ + imx7d-12x12-lpddr3-arm2-qspi.dtb \ dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ keystone-k2l-evm.dtb \ diff --git a/arch/arm/dts/imx7d-12x12-lpddr3-arm2-ecspi.dts b/arch/arm/dts/imx7d-12x12-lpddr3-arm2-ecspi.dts new file mode 100644 index 0000000..16dd447 --- /dev/null +++ b/arch/arm/dts/imx7d-12x12-lpddr3-arm2-ecspi.dts @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-12x12-lpddr3-arm2.dts" + +&epdc { + status = "disabled"; +}; + +&ecspi1{ + status = "okay"; +}; + +/* + * pin conflict with ecspi1 + * default hog setting conflicts with ECSPI1 MOSI and MISO + * EPDC PWRCTRL conflicts with ECSPI1 CS pin + */ +&iomuxc { + pinctrl-0 = <&pinctrl_hog_1>; + pinctrl-1 = <&pinctrl_hog_1>; +}; diff --git a/arch/arm/dts/imx7d-12x12-lpddr3-arm2-qspi.dts b/arch/arm/dts/imx7d-12x12-lpddr3-arm2-qspi.dts new file mode 100644 index 0000000..c26556d --- /dev/null +++ b/arch/arm/dts/imx7d-12x12-lpddr3-arm2-qspi.dts @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-12x12-lpddr3-arm2.dts" + +/* disable epdc, conflict with qspi */ +&epdc { + status = "disabled"; +}; + +&iomuxc { + qspi1 { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x51 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x51 + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x51 + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x51 + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x51 + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x51 + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x51 + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x51 + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x51 + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x51 + >; + }; + }; +}; + +&qspi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_qspi1_1>; + pinctrl-1 = <&pinctrl_qspi1_1>; + status = "okay"; + fsl,qspi-has-second-chip = <1>; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <1>; + }; + + flash2: n25q256a@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <2>; + }; + + flash3: n25q256a@3 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <3>; + }; +}; diff --git a/arch/arm/dts/imx7d-12x12-lpddr3-arm2.dts b/arch/arm/dts/imx7d-12x12-lpddr3-arm2.dts new file mode 100644 index 0000000..eb4af7d --- /dev/null +++ b/arch/arm/dts/imx7d-12x12-lpddr3-arm2.dts @@ -0,0 +1,1017 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx7d.dtsi" + +/ { + model = "Freescale i.MX7 LPDDR3 12x12 ARM2 Board"; + compatible = "fsl,imx7d-12x12-lpddr3-arm2", "fsl,imx7d"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_gpio_keys>; + pinctrl-1 = <&pinctrl_gpio_keys_sleep>; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; + + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_aud_1v8: aud_1v8 { + compatible = "regulator-fixed"; + regulator-name = "AUD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_3v3: can1-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + + reg_can2_3v3: can2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + + reg_coedc_5v: coedc_5v { + compatible = "regulator-fixed"; + regulator-name = "CODEC_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd1_vmmc: sd1_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "VCC_SD1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "VCC_SD2"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on { + compatible = "regulator-fixed"; + regulator-name = "mipi_dsi_pwr_on"; + gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + memory { + reg = <0x80000000 0x80000000>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&epdc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_epdc_0>; + pinctrl-1 = <&pinctrl_epdc_0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + +&epxp { + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 19 0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + pinctrl-1 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + status = "disabled"; + + spi_flash1: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet1>; + pinctrl-1 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet2>; + pinctrl-1 = <&pinctrl_enet2>; + pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-1 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_3v3>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-1 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + fsl,lpsr-mode; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + max17135@48 { + compatible = "maxim,max17135"; + reg = <0x48>; + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 31 0>; + gpio_pmic_vcom_ctrl = <&gpio4 14 0>; + gpio_pmic_wakeup = <&gpio4 23 0>; + gpio_pmic_v3p3 = <&gpio4 20 0>; + gpio_pmic_intr = <&gpio4 18 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* 2's-compliment, -4325000 */ + regulator-min-microvolt = <0xffbe0178>; + /* 2's-compliment, -500000 */ + regulator-max-microvolt = <0xfff85ee0>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; + + codec: wm8958@1a { + compatible = "wlf,wm8958"; + reg = <0x1a>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "mclk1", "mclk2"; + + DBVDD1-supply = <®_aud_1v8>; + DBVDD2-supply = <®_aud_1v8>; + DBVDD3-supply = <®_aud_1v8>; + AVDD2-supply = <®_aud_1v8>; + CPVDD-supply = <®_aud_1v8>; + SPKVDD1-supply = <®_coedc_5v>; + SPKVDD2-supply = <®_coedc_5v>; + wlf,ldo1ena; + wlf,ldo2ena; + }; +}; + +&iomuxc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect &pinctrl_hog_mipi>; + pinctrl-1 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect &pinctrl_hog_mipi>; + + imx7d-12x12-lpddr3-arm2 { + + pinctrl_bt: btgrp-1 { + fsl,pins = < + MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x80000000 /* BT REG on */ + >; + }; + + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { + fsl,pins = < + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x2 + >; + }; + + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_epdc_0: epdcgrp-0 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2 + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2 + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2 + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2 + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2 + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2 + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2 + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2 + MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2 + MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2 + MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2 + MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2 + MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2 + MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2 + MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2 + MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2 + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2 + MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2 + MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2 + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2 + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2 + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2 + MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 0x2 + MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 0x2 + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2 + MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2 + MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2 + MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2 + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 0x2 + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 0x2 + MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x80000000 /* pwr int */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59 + MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59 + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x59 /* STBY */ + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59 + MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59 + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x59 /* STBY */ + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32 + >; + }; + + pinctrl_gpio_keys_sleep: gpio_keysgrp_sleep { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 + >; + }; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x80000000 + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x80000000 + MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x80000000 + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x80000000 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 + MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 + >; + }; + + pinctrl_hog_mipi: hoggrp_mipi { + fsl,pins = < + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59 + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x59 + >; + }; + + pinctrl_hog_sd2_vselect: hoggrp_sd2vselect { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x59 + >; + }; + + pinctrl_hog_headphone_det: hoggrp_headphone_det { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 + >; + }; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT 0x0 + MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT 0x0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x2 + MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x2 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f + MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC 0x1f + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0 + >; + }; + + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x79 + >; + }; + + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_1_100mhz: usdhc2grp-1_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + >; + }; + + pinctrl_usdhc2_1_200mhz: usdhc2grp-1_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + >; + }; + + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; + + pinctrl_sim1_1: sim1grp-1 { + fsl,pins = < + MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B 0x77 + MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD 0x77 + MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN 0x77 + MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK 0x73 + MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD 0x73 + >; + }; + + }; +}; + +&iomuxc_lpsr { + imx7d-12x12-lpddr3-arm2 { + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x30 + >; + }; + }; + + imx7d-sdb { + pinctrl_usbotg1_vbus: usbotg1vbusgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 + >; + }; + + pinctrl_usbotg2_vbus: usbotg2vbusgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + pinctrl-1 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&ocrams { + fsl,enable-lpsr; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio6 21 GPIO_ACTIVE_LOW>; + power-on-gpio = <&gpio6 19 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&sim1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sim1_1>; + pinctrl-1 = <&pinctrl_sim1_1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_uart1_1>; + pinctrl-1 = <&pinctrl_uart1_1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_uart3_1 + &pinctrl_bt>; + pinctrl-1 = <&pinctrl_uart3_1 + &pinctrl_bt>; + fsl,uart-has-rtscts; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + /* pinctrl-0 = <&pinctrl_uart3dte_1>; */ +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1_1>; + pinctrl-1 = <&pinctrl_usdhc1_1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2_1>; + pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc2_1>; + cd-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_1>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,wdog_b; +}; diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig b/board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig new file mode 100644 index 0000000..34aa578 --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX7D_12X12_LPDDR3_ARM2 + +config SYS_BOARD + default "mx7d_12x12_lpddr3_arm2" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "mx7" + +config SYS_CONFIG_NAME + default "mx7d_12x12_lpddr3_arm2" + +endif diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/Makefile b/board/freescale/mx7d_12x12_lpddr3_arm2/Makefile new file mode 100644 index 0000000..cbe8a46 --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/Makefile @@ -0,0 +1,10 @@ +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx7d_12x12_lpddr3_arm2.o + +extra-$(CONFIG_USE_PLUGIN) := plugin.bin +$(obj)/plugin.bin: $(obj)/plugin.o + $(OBJCOPY) -O binary --gap-fill 0xff $< $@ diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg b/board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg new file mode 100644 index 0000000..ccc9426 --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_12x12_lpddr3_arm2/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x03040008 +DATA 4 0x307a0064 0x00200038 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00350001 +DATA 4 0x307a00dc 0x00c3000a +DATA 4 0x307a00e0 0x00010000 +DATA 4 0x307a00e4 0x00110006 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x0a0e110b +DATA 4 0x307a0104 0x00020211 +DATA 4 0x307a0108 0x03060708 +DATA 4 0x307a010c 0x00a0500c +DATA 4 0x307a0110 0x05020307 +DATA 4 0x307a0114 0x02020404 +DATA 4 0x307a0118 0x02020003 +DATA 4 0x307a011c 0x00000202 +DATA 4 0x307a0120 0x00000202 + +DATA 4 0x307a0180 0x00600018 +DATA 4 0x307a0184 0x00e00100 +DATA 4 0x307a0190 0x02098205 +DATA 4 0x307a0194 0x00060303 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 + +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00171717 +DATA 4 0x307a0210 0x00000f00 +DATA 4 0x307a0214 0x05050505 +DATA 4 0x307a0218 0x0f0f0505 + +DATA 4 0x307a0240 0x06000601 +DATA 4 0x307a0244 0x00000000 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17421e40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790008 0x00010000 +DATA 4 0x30790010 0x0007080c +DATA 4 0x307900b0 0x1010007e + +DATA 4 0x3079001C 0x01010000 +DATA 4 0x3079009c 0x0db60d6e + +DATA 4 0x30790030 0x06060606 +DATA 4 0x30790020 0x0a0a0a0a +DATA 4 0x30790050 0x01000008 +DATA 4 0x30790050 0x00000008 +DATA 4 0x30790018 0x0000000f +DATA 4 0x307900c0 0x1e487304 +DATA 4 0x307900c0 0x1e487304 +DATA 4 0x307900c0 0x1e487306 +DATA 4 0x307900c0 0x1e4c7304 +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x1e487304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 + +CHECK_BITS_SET 4 0x307a0004 0x1 +#endif diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg b/board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg new file mode 100644 index 0000000..d724d21 --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_12x12_lpddr3_arm2/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x03040008 +DATA 4 0x307a0064 0x00200038 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00350001 +DATA 4 0x307a00dc 0x00c3000a +DATA 4 0x307a00e0 0x00010000 +DATA 4 0x307a00e4 0x00110006 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x0a0e110b +DATA 4 0x307a0104 0x00020211 +DATA 4 0x307a0108 0x03060708 +DATA 4 0x307a010c 0x00a0500c +DATA 4 0x307a0110 0x05020307 +DATA 4 0x307a0114 0x02020404 +DATA 4 0x307a0118 0x02020003 +DATA 4 0x307a011c 0x00000202 +DATA 4 0x307a0120 0x00000202 + +DATA 4 0x307a0180 0x00600018 +DATA 4 0x307a0184 0x00e00100 +DATA 4 0x307a0190 0x02098205 +DATA 4 0x307a0194 0x00060303 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 + +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00171717 +DATA 4 0x307a0210 0x00000f00 +DATA 4 0x307a0214 0x05050505 +DATA 4 0x307a0218 0x0f0f0505 + +DATA 4 0x307a0240 0x06000601 +DATA 4 0x307a0244 0x00000000 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17421e40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790008 0x00010000 +DATA 4 0x30790010 0x0007080c +DATA 4 0x3079007c 0x1c1c1c1c +DATA 4 0x30790080 0x1c1c1c1c +DATA 4 0x30790084 0x30301c1c +DATA 4 0x30790088 0x00000030 +DATA 4 0x3079006c 0x30303030 +DATA 4 0x307900b0 0x1010007e + +DATA 4 0x3079001C 0x01010000 +DATA 4 0x3079009c 0x0db60d6e + +DATA 4 0x30790030 0x06060606 +DATA 4 0x30790020 0x0a0a0a0a +DATA 4 0x30790050 0x01000008 +DATA 4 0x30790050 0x00000008 +DATA 4 0x30790018 0x0000000f +DATA 4 0x307900c0 0x1e487304 +DATA 4 0x307900c0 0x1e487304 +DATA 4 0x307900c0 0x1e487306 +DATA 4 0x307900c0 0x1e4c7304 +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x1e487304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 + +CHECK_BITS_SET 4 0x307a0004 0x1 +#endif diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/mx7d_12x12_lpddr3_arm2.c b/board/freescale/mx7d_12x12_lpddr3_arm2/mx7d_12x12_lpddr3_arm2.c new file mode 100644 index 0000000..4f8425e --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/mx7d_12x12_lpddr3_arm2.c @@ -0,0 +1,659 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx7-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/io.h> +#include <linux/sizes.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <miiphy.h> +#include <netdev.h> +#include <power/pmic.h> +#include <power/pfuze3000_pmic.h> +#include "../common/pfuze.h" +#include <asm/arch/crm_regs.h> +#include <asm/imx-common/video.h> + +#ifdef CONFIG_VIDEO_MXS +#include <linux/fb.h> +#endif +#if defined(CONFIG_MXC_EPDC) +#include <lcd.h> +#include <mxc_epdc_fb.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) +#define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_49OHM) + +#define QSPI_PAD_CTRL \ + (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define EPDC_PAD_CTRL 0x0 + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + + MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL), +}; + +static iomux_v3_cfg_t const pwm_pads[] = { + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); + + /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd_pwr"); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 1), "lcd_backlight"); + gpio_direction_output(IMX_GPIO_NR(1, 1) , 1); +} + +struct display_info_t const displays[] = {{ + .bus = ELCDIF1_IPS_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + + +static iomux_v3_cfg_t const per_rst_pads[] = { + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec1_pads[] = { + MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec1(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI +static iomux_v3_cfg_t const quadspi_pads[] = { + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); +#endif + + /* Set the clock */ + set_clk_qspi(); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec1(); + + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return 0; +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); + + ret = set_clk_enet(ENET_125MHz); + if (ret) + return ret; + + return 0; +} + + +int board_phy_config(struct phy_device *phydev) +{ + /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on + Phy control debug reg 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + + /* CS0 */ + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void setup_spinor(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); + gpio_request(IMX_GPIO_NR(4, 19), "ecspi1_cs"); + gpio_direction_output(IMX_GPIO_NR(4, 19), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 19)) : -1; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_MXC_EPDC +static iomux_v3_cfg_t const epdc_enable_pads[] = { + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + MX7D_PAD_EPDC_DATA00__GPIO2_IO0, + MX7D_PAD_EPDC_DATA01__GPIO2_IO1, + MX7D_PAD_EPDC_DATA02__GPIO2_IO2, + MX7D_PAD_EPDC_DATA03__GPIO2_IO3, + MX7D_PAD_EPDC_DATA04__GPIO2_IO4, + MX7D_PAD_EPDC_DATA05__GPIO2_IO5, + MX7D_PAD_EPDC_DATA06__GPIO2_IO6, + MX7D_PAD_EPDC_DATA07__GPIO2_IO7, + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16, + MX7D_PAD_EPDC_SDLE__GPIO2_IO17, + MX7D_PAD_EPDC_SDOE__GPIO2_IO18, + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19, + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20, + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21, + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22, + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23, + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24, + MX7D_PAD_EPDC_GDOE__GPIO2_IO25, + MX7D_PAD_EPDC_GDRL__GPIO2_IO26, + MX7D_PAD_EPDC_GDSP__GPIO2_IO27, + MX7D_PAD_EPDC_BDR0__GPIO2_IO28, + MX7D_PAD_EPDC_BDR1__GPIO2_IO29, +}; + +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 1024, + .vl_row = 758, + .vl_pixclock = 40000000, + .vl_left_margin = 12, + .vl_right_margin = 76, + .vl_upper_margin = 4, + .vl_lower_margin = 5, + .vl_hsync = 12, + .vl_vsync = 2, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 524, + .gdsp_offs = 327, + .gdoe_offs = 0, + .gdclk_offs = 19, + .num_ce = 1, +}; + +static void setup_epdc_power(void) +{ + /* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0); + + /* Setup epdc voltage */ + + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + gpio_request(IMX_GPIO_NR(2, 31), "epdc_pwrstat"); + gpio_direction_input(IMX_GPIO_NR(2, 31)); + + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ + imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set as output */ + gpio_request(IMX_GPIO_NR(4, 14), "epdc_vcom0"); + gpio_direction_output(IMX_GPIO_NR(4, 14), 1); + + /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(4, 23), "epdc_pwrwakeup"); + gpio_direction_output(IMX_GPIO_NR(4, 23), 1); + + /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(4, 20), "epdc_pwrctrl0"); + gpio_direction_output(IMX_GPIO_NR(4, 20), 1); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, + ARRAY_SIZE(epdc_enable_pads)); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, + ARRAY_SIZE(epdc_disable_pads)); +} + +static void setup_epdc(void) +{ + /*** epdc Maxim PMIC settings ***/ + + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ + imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set pixel clock rates for EPDC in clock.c */ + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(4, 20), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(4, 23), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 31))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(4, 14), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(4, 23), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(4, 14), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(4, 20), 0); +} +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* Reset peripherals */ + imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads)); + + gpio_request(IMX_GPIO_NR(1, 3), "per_rst"); + gpio_direction_output(IMX_GPIO_NR(1, 3) , 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(1, 3), 1); + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_MXC_SPI + setup_spinor(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_MXC_EPDC + setup_epdc(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x10, 0x12, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x10, 0x16, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)}, + {"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +#ifdef CONFIG_DM_PMIC +int power_init_board(void) +{ + struct udevice *dev; + int ret, dev_id, rev_id, reg; + + ret = pmic_get("pfuze3000", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* disable Low Power Mode during standby mode */ + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); + reg |= 0x1; + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); + + /* SW1A/1B mode set to APS/APS */ + reg = 0x8; + pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg); + pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg); + + /* SW1A/1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg); + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg); + + /* below are for LPSR mode support */ + reg = pmic_reg_read(dev, PFUZE3000_SW3MODE); + reg |= 0x20; + pmic_reg_write(dev, PFUZE3000_SW3MODE, reg); + + reg = pmic_reg_read(dev, PFUZE3000_VLDO1CTL); + reg |= 0x80; + pmic_reg_write(dev, PFUZE3000_VLDO1CTL, reg); + + reg = pmic_reg_read(dev, PFUZE3000_VLDO3CTL); + reg |= 0x80; + pmic_reg_write(dev, PFUZE3000_VLDO3CTL, reg); + + pmic_reg_read(dev, PFUZE3000_SW2MODE); + reg |= 0x20; + pmic_reg_write(dev, PFUZE3000_SW2MODE, reg); + + /* set SW1B normal voltage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); + reg &= ~0x1f; + reg |= PFUZE3000_SW1AB_SETP(975); + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg); + + return 0; +} +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX7D 12x12 LPDDR3 ARM2\n"); + + return 0; +} diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S b/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S new file mode 100644 index 0000000..aaf65c2 --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S @@ -0,0 +1,577 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> + +/* DDR script */ +.macro imx7d_ddrphy_latency_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne TUNE_END + + /*TO 1.1*/ + ldr r1, =0x1c1c1c1c + str r1, [r0, #0x7c] + ldr r1, =0x1c1c1c1c + str r1, [r0, #0x80] + ldr r1, =0x30301c1c + str r1, [r0, #0x84] + ldr r1, =0x00000030 + str r1, [r0, #0x88] + ldr r1, =0x30303030 + str r1, [r0, #0x6c] + +TUNE_END: +.endm + +.macro imx7d_12x12_lpddr3_arm2_setting + + /* check whether it is a LPSR resume */ + ldr r1, =0x30270000 + ldr r7, [r1] + cmp r7, #0 + beq 16f + + /* disable wdog powerdown counter */ + ldr r0, =0x30280000 + ldrh r1, =0x0 + strh r1, [r0, #0x8] + + /* initialize AIPs 1-3 port */ + ldr r0, =0x301f0000 + ldr r1, =0x77777777 + str r1, [r0] + str r1, [r0, #0x4] + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4c] + str r1, [r0, #0x50] + + ldr r0, =0x305f0000 + ldr r1, =0x77777777 + str r1, [r0] + str r1, [r0, #0x4] + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4c] + str r1, [r0, #0x50] + + ldr r0, =0x309f0000 + ldr r1, =0x77777777 + str r1, [r0] + str r1, [r0, #0x4] + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4c] + str r1, [r0, #0x50] + + ldr r1, =0x30360000 + ldr r2, =0x30390000 + ldr r3, =0x307a0000 + ldr r4, =0x30790000 + ldr r10, =0x30380000 + ldr r11, =0x30340000 + + /* turn on ddr power */ + ldr r7, =(0x1 << 29) + str r7, [r1, #0x388] + + ldr r6, =50 +1: + subs r6, r6, #0x1 + bne 1b + + /* clear ddr_phy reset */ + ldr r6, =0x1000 + ldr r7, [r2, r6] + orr r7, r7, #0x3 + str r7, [r2, r6] + ldr r7, [r2, r6] + bic r7, r7, #0x1 + str r7, [r2, r6] + + /* restore DDRC */ + ldr r6, =0x0 + ldr r7, =0x03040008 + str r7, [r3, r6] + + ldr r6, =0x1a0 + ldr r7, =0x80400003 + str r7, [r3, r6] + + ldr r6, =0x1a4 + ldr r7, =0x00100020 + str r7, [r3, r6] + + ldr r6, =0x1a8 + ldr r7, =0x80100004 + str r7, [r3, r6] + + ldr r6, =0x64 + ldr r7, =0x00200038 + str r7, [r3, r6] + + ldr r6, =0xd0 + ldr r7, =0xc0350001 + str r7, [r3, r6] + + ldr r6, =0xdc + ldr r7, =0x00C3000A + str r7, [r3, r6] + + ldr r6, =0xe0 + ldr r7, =0x00010000 + str r7, [r3, r6] + + ldr r6, =0xe4 + ldr r7, =0x00110006 + str r7, [r3, r6] + + ldr r6, =0xf4 + ldr r7, =0x0000033F + str r7, [r3, r6] + + ldr r6, =0x100 + ldr r7, =0x0A0E110B + str r7, [r3, r6] + + ldr r6, =0x104 + ldr r7, =0x00020211 + str r7, [r3, r6] + + ldr r6, =0x108 + ldr r7, =0x03060708 + str r7, [r3, r6] + + ldr r6, =0x10c + ldr r7, =0x00A0500C + str r7, [r3, r6] + + ldr r6, =0x110 + ldr r7, =0x05020307 + str r7, [r3, r6] + + ldr r6, =0x114 + ldr r7, =0x02020404 + str r7, [r3, r6] + + ldr r6, =0x118 + ldr r7, =0x02020003 + str r7, [r3, r6] + + ldr r6, =0x11c + ldr r7, =0x00000202 + str r7, [r3, r6] + + ldr r6, =0x120 + ldr r7, =0x00000202 + str r7, [r3, r6] + + ldr r6, =0x180 + ldr r7, =0x00600018 + str r7, [r3, r6] + + ldr r6, =0x184 + ldr r7, =0x00e00100 + str r7, [r3, r6] + + ldr r6, =0x190 + ldr r7, =0x02098205 + str r7, [r3, r6] + + ldr r6, =0x194 + ldr r7, =0x00060303 + str r7, [r3, r6] + + ldr r6, =0x200 + ldr r7, =0x00000016 + str r7, [r3, r6] + + ldr r6, =0x204 + ldr r7, =0x00171717 + str r7, [r3, r6] + + ldr r6, =0x210 + ldr r7, =0xF00 + str r7, [r3, r6] + + ldr r6, =0x214 + ldr r7, =0x05050505 + str r7, [r3, r6] + + ldr r6, =0x218 + ldr r7, =0x0F0F0505 + str r7, [r3, r6] + + ldr r6, =0x240 + ldr r7, =0x06000601 + str r7, [r3, r6] + + ldr r6, =0x244 + ldr r7, =0x00000000 + str r7, [r3, r6] + + ldr r7, =0x20 + str r7, [r3, #0x30] + ldr r7, =0x0 + str r7, [r3, #0x1b0] + + /* do PHY, clear ddr_phy reset */ + ldr r6, =0x1000 + ldr r7, [r2, r6] + bic r7, r7, #0x2 + str r7, [r2, r6] + + ldr r7, [r1, #0x800] + and r7, r7, #0xFF + cmp r7, #0x11 + bne 2f + + /* for TO1.1 */ + ldr r7, [r11] + bic r7, r7, #(1 << 27) + str r7, [r11] + ldr r7, [r11] + bic r7, r7, #(1 << 29) + str r7, [r11] +2: + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ + ldr r7, =(0x1 << 30) + str r7, [r1, #0x388] + ldr r7, =(0x1 << 30) + str r7, [r1, #0x384] + + /* need to delay ~5mS */ + ldr r6, =0x100000 +3: + subs r6, r6, #0x1 + bne 3b + + /* restore DDR PHY */ + ldr r6, =0x0 + ldr r7, =0x17421E40 + str r7, [r4, r6] + + ldr r6, =0x4 + ldr r7, =0x10210100 + str r7, [r4, r6] + + ldr r6, =0x8 + ldr r7, =0x00010000 + str r7, [r4, r6] + + ldr r6, =0x10 + ldr r7, =0x0007080C + str r7, [r4, r6] + + ldr r6, =0xb0 + ldr r7, =0x1010007e + str r7, [r4, r6] + + ldr r7, [r1, #0x800] + and r7, r7, #0xFF + cmp r7, #0x11 + bne 4f + + ldr r6, =0x7c + ldr r7, =0x1c1c1c1c + str r7, [r4, r6] + + ldr r6, =0x80 + ldr r7, =0x1c1c1c1c + str r7, [r4, r6] + + ldr r6, =0x84 + ldr r7, =0x30301c1c + str r7, [r4, r6] + + ldr r6, =0x88 + ldr r7, =0x00000030 + str r7, [r4, r6] + + ldr r6, =0x6c + ldr r7, =0x30303030 + str r7, [r4, r6] + +4: + ldr r6, =0x1c + ldr r7, =0x01010000 + str r7, [r4, r6] + + ldr r6, =0x9c + ldr r7, =0x0DB60D6E + str r7, [r4, r6] + + ldr r6, =0x20 + ldr r7, =0x0a0a0a0a + str r7, [r4, r6] + + ldr r6, =0x30 + ldr r7, =0x06060606 + str r7, [r4, r6] + + ldr r6, =0x50 + ldr r7, =0x01000008 + str r7, [r4, r6] + + ldr r6, =0x50 + ldr r7, =0x00000008 + str r7, [r4, r6] + + ldr r6, =0xc0 + ldr r7, =0x0e407304 + str r7, [r4, r6] + + ldr r6, =0xc0 + ldr r7, =0x0e447304 + str r7, [r4, r6] + + ldr r6, =0xc0 + ldr r7, =0x0e447306 + str r7, [r4, r6] + + ldr r6, =0xc0 + ldr r7, =0x0e4c7304 + str r7, [r4, r6] + + ldr r6, =0xc0 + ldr r7, =0x0e487306 + str r7, [r4, r6] + + ldr r7, =0x0 + add r9, r10, #0x4000 + str r7, [r9, #0x130] + + ldr r7, =0x170 + orr r7, r7, #0x8 + str r7, [r11, #0x20] + + ldr r7, =0x2 + add r9, r10, #0x4000 + str r7, [r9, #0x130] + + ldr r7, =0xf + str r7, [r4, #0x18] + + /* wait until self-refresh mode entered */ +11: + ldr r7, [r3, #0x4] + and r7, r7, #0x3 + cmp r7, #0x3 + bne 11b + ldr r7, =0x0 + str r7, [r3, #0x320] + ldr r7, =0x1 + str r7, [r3, #0x1b0] + ldr r7, =0x1 + str r7, [r3, #0x320] +12: + ldr r7, [r3, #0x324] + and r7, r7, #0x1 + cmp r7, #0x1 + bne 12b +13: + ldr r7, [r3, #0x4] + and r7, r7, #0x20 + cmp r7, #0x20 + bne 13b + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r3, #0x30] +14: + ldr r7, [r3, #0x4] + and r7, r7, #0x30 + cmp r7, #0x0 + bne 14b + +15: + ldr r7, [r3, #0x4] + and r7, r7, #0x3 + cmp r7, #0x1 + bne 15b + + /* enable port */ + ldr r7, =0x1 + str r7, [r3, #0x490] + + /* jump to kernel resume */ + ldr r1, =0x30270000 + ldr r7, [r1] + + mov pc, r7 +16: + /* Configure ocram_epdc */ + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0x4f400005 + str r1, [r0, #0x4] + + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =(0x1 << 30) + str r1, [r0, #0x388] + str r1, [r0, #0x384] + + ldr r0, =SRC_BASE_ADDR + ldr r1, =0x2 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR + ldr r1, =0x03040008 + str r1, [r0] + ldr r1, =0x00200038 + str r1, [r0, #0x64] + ldr r1, =0x1 + str r1, [r0, #0x490] + ldr r1, =0x00350001 + str r1, [r0, #0xd0] + ldr r1, =0x00c3000a + str r1, [r0, #0xdc] + ldr r1, =0x00010000 + str r1, [r0, #0xe0] + ldr r1, =0x00110006 + str r1, [r0, #0xe4] + ldr r1, =0x33f + str r1, [r0, #0xf4] + ldr r1, =0x0a0e110b + str r1, [r0, #0x100] + ldr r1, =0x00020211 + str r1, [r0, #0x104] + ldr r1, =0x03060708 + str r1, [r0, #0x108] + ldr r1, =0x00a0500c + str r1, [r0, #0x10c] + ldr r1, =0x05020307 + str r1, [r0, #0x110] + ldr r1, =0x02020404 + str r1, [r0, #0x114] + ldr r1, =0x02020003 + str r1, [r0, #0x118] + ldr r1, =0x00000202 + str r1, [r0, #0x11c] + ldr r1, =0x00000202 + str r1, [r0, #0x120] + ldr r1, =0x00600018 + str r1, [r0, #0x180] + ldr r1, =0x00e00100 + str r1, [r0, #0x184] + ldr r1, =0x02098205 + str r1, [r0, #0x190] + ldr r1, =0x00060303 + str r1, [r0, #0x194] + ldr r1, =0x80400003 + str r1, [r0, #0x1a0] + ldr r1, =0x00100020 + str r1, [r0, #0x1a4] + ldr r1, =0x80100004 + str r1, [r0, #0x1a8] + + ldr r1, =0x00000016 + str r1, [r0, #0x200] + ldr r1, =0x00171717 + str r1, [r0, #0x204] + ldr r1, =0x00000f00 + str r1, [r0, #0x210] + ldr r1, =0x05050505 + str r1, [r0, #0x214] + ldr r1, =0x0f0f0505 + str r1, [r0, #0x218] + + ldr r1, =0x06000601 + str r1, [r0, #0x240] + mov r1, #0x0 + str r1, [r0, #0x244] + + ldr r0, =SRC_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x17421e40 + str r1, [r0] + ldr r1, =0x10210100 + str r1, [r0, #0x4] + ldr r1, =0x00010000 + str r1, [r0, #0x8] + ldr r1, =0x0007080c + str r1, [r0, #0x10] + imx7d_ddrphy_latency_setting + ldr r1, =0x1010007e + str r1, [r0, #0xb0] + ldr r1, =0x01010000 + str r1, [r0, #0x1c] + ldr r1, =0x0db60d6e + str r1, [r0, #0x9c] + + ldr r1, =0x06060606 + str r1, [r0, #0x30] + ldr r1, =0x0a0a0a0a + str r1, [r0, #0x20] + ldr r1, =0x01000008 + str r1, [r0, #0x50] + ldr r1, =0x00000008 + str r1, [r0, #0x50] + + ldr r1, =0x0000000f + str r1, [r0, #0x18] + ldr r1, =0x1e487304 + str r1, [r0, #0xc0] + ldr r1, =0x1e487304 + str r1, [r0, #0xc0] + ldr r1, =0x1e487306 + str r1, [r0, #0xc0] + ldr r1, =0x1e4c7304 + str r1, [r0, #0xc0] + +wait_zq: + ldr r1, [r0, #0xc4] + tst r1, #0x1 + beq wait_zq + + ldr r1, =0x1e487304 + str r1, [r0, #0xc0] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =IOMUXC_GPR_BASE_ADDR + mov r1, #0x178 + str r1, [r0, #0x20] + ldr r0, =CCM_BASE_ADDR + mov r1, #0x2 + ldr r2, =0x4130 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR +wait_stat: + ldr r1, [r0, #0x4] + tst r1, #0x1 + beq wait_stat +.endm + +.macro imx7_clock_gating +.endm + +.macro imx7_qos_setting +.endm + +.macro imx7_ddr_setting + imx7d_12x12_lpddr3_arm2_setting +.endm + +/* include the common plugin code here */ +#include <asm/arch/mx7_plugin.S> diff --git a/configs/mx7d_12x12_lpddr3_arm2_TO_1_1_defconfig b/configs/mx7d_12x12_lpddr3_arm2_TO_1_1_defconfig new file mode 100644 index 0000000..d4182fc --- /dev/null +++ b/configs/mx7d_12x12_lpddr3_arm2_TO_1_1_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7D_12X12_LPDDR3_ARM2=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_IMX_RDC=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y +CONFIG_OF_CONTROL=y +# CONFIG_BLK is not set +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="FSL" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y diff --git a/configs/mx7d_12x12_lpddr3_arm2_defconfig b/configs/mx7d_12x12_lpddr3_arm2_defconfig new file mode 100644 index 0000000..fa62968 --- /dev/null +++ b/configs/mx7d_12x12_lpddr3_arm2_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7D_12X12_LPDDR3_ARM2=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_IMX_RDC=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y +CONFIG_OF_CONTROL=y +# CONFIG_BLK is not set +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="FSL" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y diff --git a/configs/mx7d_12x12_lpddr3_arm2_epdc_defconfig b/configs/mx7d_12x12_lpddr3_arm2_epdc_defconfig new file mode 100644 index 0000000..48d4ce1 --- /dev/null +++ b/configs/mx7d_12x12_lpddr3_arm2_epdc_defconfig @@ -0,0 +1,66 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7D_12X12_LPDDR3_ARM2=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_IMX_RDC=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-arm2" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-arm2.dtb" +CONFIG_MXC_EPDC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y +CONFIG_OF_CONTROL=y +# CONFIG_BLK is not set +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="FSL" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y diff --git a/configs/mx7d_12x12_lpddr3_arm2_qspi1_defconfig b/configs/mx7d_12x12_lpddr3_arm2_qspi1_defconfig new file mode 100644 index 0000000..3a0f7ac --- /dev/null +++ b/configs/mx7d_12x12_lpddr3_arm2_qspi1_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7D_12X12_LPDDR3_ARM2=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-arm2-qspi" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y +CONFIG_OF_CONTROL=y +# CONFIG_BLK is not set +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="FSL" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y +CONFIG_QSPI_BOOT=y +CONFIG_DM_ETH=y diff --git a/configs/mx7d_12x12_lpddr3_arm2_spinor_defconfig b/configs/mx7d_12x12_lpddr3_arm2_spinor_defconfig new file mode 100644 index 0000000..ea90e09 --- /dev/null +++ b/configs/mx7d_12x12_lpddr3_arm2_spinor_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_TARGET_MX7D_12X12_LPDDR3_ARM2=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_IMX_RDC=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-arm2-ecspi" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-arm2.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y +CONFIG_OF_CONTROL=y +# CONFIG_BLK is not set +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="FSL" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y +CONFIG_SPI_BOOT=y diff --git a/include/configs/mx7d_12x12_lpddr3_arm2.h b/include/configs/mx7d_12x12_lpddr3_arm2.h new file mode 100644 index 0000000..305a50d --- /dev/null +++ b/include/configs/mx7d_12x12_lpddr3_arm2.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7D 12x12 LPDDR3 ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7D_12X12_LPDDR3_ARM2_CONFIG_H +#define __MX7D_12X12_LPDDR3_ARM2_CONFIG_H + +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +#define PHYS_SDRAM_SIZE SZ_2G + +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 1 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +/* ENET1 */ +#define IMX_FEC_BASE ENET_IPS_BASE_ADDR + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_FSL_QSPI +#define CONFIG_ENV_IS_IN_SPI_FLASH +#elif defined CONFIG_SPI_BOOT +#define CONFIG_MXC_SPI +#define CONFIG_ENV_IS_IN_SPI_FLASH +#else +#define CONFIG_ENV_IS_IN_MMC +#endif + +#ifdef CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_SF_DEFAULT_CS 0 +#endif + +/* #define CONFIG_SPLASH_SCREEN*/ +/* #define CONFIG_MXC_EPDC*/ + +#include "mx7d_arm2.h" + +#endif diff --git a/include/configs/mx7d_arm2.h b/include/configs/mx7d_arm2.h new file mode 100644 index 0000000..e16558b --- /dev/null +++ b/include/configs/mx7d_arm2.h @@ -0,0 +1,348 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7D ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7D_ARM2_CONFIG_H +#define __MX7D_ARM2_CONFIG_H + +#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> +#include "mx7_common.h" +#include <asm/imx-common/gpio.h> + +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_DBG_MONITOR + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + +#define CONFIG_IMX_THERMAL +#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_BAUDRATE 115200 + +#undef CONFIG_BOOTM_NETBSD +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 + +/* I2C configs */ +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +#undef CONFIG_CMD_IMLS + +#define CONFIG_LOADADDR 0x80800000 +#define CONFIG_SYS_TEXT_BASE 0x87800000 + +#ifdef CONFIG_DM_SPI +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x68000000 /* Set to QSPI1 B flash at default */ +#define SF_QSPI1_B_CS_NUM 2 +#define SF_QSPI1_B_BUS_NUM 1 +#else +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x62000000 /* Set to QSPI1 B flash at default */ +#define SF_QSPI1_B_CS_NUM 1 +#define SF_QSPI1_B_BUS_NUM 0 +#endif + +#ifdef CONFIG_IMX_BOOTAUX + +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "m4_qspi_cs="__stringify(SF_QSPI1_B_CS_NUM)"\0" \ + "m4_qspi_bus="__stringify(SF_QSPI1_B_BUS_NUM)"\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ + "update_m4_from_sd=" \ + "if sf probe ${m4_qspi_bus}:${m4_qspi_cs}; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x0 ${fw_sz}; " \ + "sf write ${loadaddr} 0x0 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=sf probe ${m4_qspi_bus}:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV "" +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) " \ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=MCIMX28LCD\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=5 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + UPDATE_M4_ENV \ + "epdc_waveform=epdc_splash.bin\0" \ + "panel=MCIMX28LCD\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_AUTO_COMPLETE + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x40000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_SIZE SZ_8K + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_FSL_QSPI_AHB +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#ifdef CONFIG_DM_SPI +#define FSL_QSPI_FLASH_NUM 4 +#define CONFIG_SF_DEFAULT_BUS 1 /* Have set the QSPI to SPI 1 in imx7d.dtsi alias*/ +#else +#define FSL_QSPI_FLASH_NUM 2 /* Non-DM driver only supports 2 flash, one is on A port, another is on B port*/ +#define CONFIG_SF_DEFAULT_BUS 0 +#endif +#define FSL_QSPI_FLASH_SIZE SZ_64M +#define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR +#define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_SECT_SIZE (256 * 1024) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_PROTECTION +#endif + +#ifdef CONFIG_NAND_MXS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (13 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (832 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_FLASH) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SIZE +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE +#define CONFIG_ENV_OFFSET (4 * CONFIG_SYS_FLASH_SECT_SIZE) +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (60 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +#define CONFIG_CMD_BMODE + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC) +/* + * Framebuffer and LCD + */ +#define CONFIG_CMD_BMP +#define CONFIG_LCD + +#undef LCD_TEST_PATTERN +/* #define CONFIG_SPLASH_IS_IN_MMC 1 */ +#define LCD_BPP LCD_MONOCHROME +/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + +#define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif + +/* USB Configs */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USBD_HS + +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#endif /* __CONFIG_H */ |