summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--board/mbx8xx/pcmcia.c4
-rw-r--r--board/tqc/tqm8xx/tqm8xx.c23
-rw-r--r--boards.cfg1
-rw-r--r--common/cmd_ide.c11
-rw-r--r--drivers/input/ps2ser.c109
-rw-r--r--drivers/pcmcia/mpc8xx_pcmcia.c29
-rw-r--r--drivers/pcmcia/tqm8xx_pcmcia.c42
-rw-r--r--include/configs/HMI10.h504
-rw-r--r--include/status_led.h17
9 files changed, 23 insertions, 717 deletions
diff --git a/board/mbx8xx/pcmcia.c b/board/mbx8xx/pcmcia.c
index 69368d8..e672d8c 100644
--- a/board/mbx8xx/pcmcia.c
+++ b/board/mbx8xx/pcmcia.c
@@ -117,11 +117,7 @@ int pcmcia_hardware_enable (int slot)
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__,__FUNCTION__,
&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
-#ifndef CONFIG_HMI10
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
-#else
if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) {
-#endif /* CONFIG_HMI10 */
printf (" No Card found\n");
return (1);
}
diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c
index cde780b..940cc8f 100644
--- a/board/tqc/tqm8xx/tqm8xx.c
+++ b/board/tqc/tqm8xx/tqm8xx.c
@@ -430,29 +430,6 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
/* ------------------------------------------------------------------------- */
-#ifdef CONFIG_PS2MULT
-
-#ifdef CONFIG_HMI10
-#define BASE_BAUD ( 1843200 / 16 )
-struct serial_state rs_table[] = {
- { BASE_BAUD, 4, (void*)0xec140000 },
- { BASE_BAUD, 2, (void*)0xec150000 },
- { BASE_BAUD, 6, (void*)0xec160000 },
- { BASE_BAUD, 10, (void*)0xec170000 },
-};
-
-#ifdef CONFIG_BOARD_EARLY_INIT_R
-int board_early_init_r (void)
-{
- ps2mult_early_init();
- return (0);
-}
-#endif
-#endif /* CONFIG_HMI10 */
-
-#endif /* CONFIG_PS2MULT */
-
-
#ifdef CONFIG_MISC_INIT_R
extern void load_sernum_ethaddr(void);
int misc_init_r (void)
diff --git a/boards.cfg b/boards.cfg
index 0bf9c93..25a58f4 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -170,7 +170,6 @@ QS823 powerpc mpc8xx qs850 snmc
QS850 powerpc mpc8xx qs850 snmc
QS860T powerpc mpc8xx qs860t snmc
stxxtc powerpc mpc8xx stxxtc stx
-HMI10 powerpc mpc8xx tqm8xx tqc
SM850 powerpc mpc8xx tqm8xx tqc
AMX860 powerpc mpc8xx amx860 westel
csb272 powerpc ppc4xx
diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index 6aeca76..ea0f4a7 100644
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -818,7 +818,7 @@ set_pcmcia_timing (int pmode)
static void
input_swap_data(int dev, ulong *sect_buf, int words)
{
-#if defined(CONFIG_HMI10) || defined(CONFIG_CPC45)
+#if defined(CONFIG_CPC45)
uchar i;
volatile uchar *pbuf_even = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_EVEN);
volatile uchar *pbuf_odd = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_ODD);
@@ -858,7 +858,7 @@ input_swap_data(int dev, ulong *sect_buf, int words)
static void
output_data(int dev, ulong *sect_buf, int words)
{
-#if defined(CONFIG_HMI10) || defined(CONFIG_CPC45)
+#if defined(CONFIG_CPC45)
uchar *dbuf;
volatile uchar *pbuf_even;
volatile uchar *pbuf_odd;
@@ -910,7 +910,7 @@ output_data(int dev, ulong *sect_buf, int words)
static void
input_data(int dev, ulong *sect_buf, int words)
{
-#if defined(CONFIG_HMI10) || defined(CONFIG_CPC45)
+#if defined(CONFIG_CPC45)
uchar *dbuf;
volatile uchar *pbuf_even;
volatile uchar *pbuf_odd;
@@ -1544,7 +1544,6 @@ static void ide_reset (void)
#if defined(CONFIG_IDE_LED) && \
!defined(CONFIG_CPC45) && \
- !defined(CONFIG_HMI10) && \
!defined(CONFIG_KUP4K) && \
!defined(CONFIG_KUP4X)
@@ -1586,7 +1585,7 @@ int ide_device_present(int dev)
static void
output_data_shorts(int dev, ushort *sect_buf, int shorts)
{
-#if defined(CONFIG_HMI10) || defined(CONFIG_CPC45)
+#if defined(CONFIG_CPC45)
uchar *dbuf;
volatile uchar *pbuf_even;
volatile uchar *pbuf_odd;
@@ -1618,7 +1617,7 @@ output_data_shorts(int dev, ushort *sect_buf, int shorts)
static void
input_data_shorts(int dev, ushort *sect_buf, int shorts)
{
-#if defined(CONFIG_HMI10) || defined(CONFIG_CPC45)
+#if defined(CONFIG_CPC45)
uchar *dbuf;
volatile uchar *pbuf_even;
volatile uchar *pbuf_odd;
diff --git a/drivers/input/ps2ser.c b/drivers/input/ps2ser.c
index 8d0b6d6..a655a16 100644
--- a/drivers/input/ps2ser.c
+++ b/drivers/input/ps2ser.c
@@ -46,8 +46,7 @@ DECLARE_GLOBAL_DATA_PTR;
#error CONFIG_PS2SERIAL must be in 1 ... 6
#endif
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
- defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
+#else
#if CONFIG_PS2SERIAL == 1
#define COM_BASE (CONFIG_SYS_CCSRBAR+0x4500)
@@ -57,17 +56,12 @@ DECLARE_GLOBAL_DATA_PTR;
#error CONFIG_PS2SERIAL must be in 1 ... 2
#endif
-#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */
+#endif /* CONFIG_MPC5xxx / other */
static int ps2ser_getc_hw(void);
static void ps2ser_interrupt(void *dev_id);
extern struct serial_state rs_table[]; /* in serial.c */
-#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && \
- !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8548) && \
- !defined(CONFIG_MPC8555)
-static struct serial_state *state;
-#endif
static u_char ps2buf[PS2BUF_SIZE];
static atomic_t ps2buf_cnt;
@@ -111,8 +105,8 @@ int ps2ser_init(void)
return (0);
}
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
- defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
+#else
+
int ps2ser_init(void)
{
NS16550_t com_port = (NS16550_t)COM_BASE;
@@ -128,76 +122,24 @@ int ps2ser_init(void)
return (0);
}
-#else /* !CONFIG_MPC5xxx && !CONFIG_MPC8540 / other */
-
-static inline unsigned int ps2ser_in(int offset)
-{
- return readb((unsigned long) state->iomem_base + offset);
-}
-
-static inline void ps2ser_out(int offset, int value)
-{
- writeb(value, (unsigned long) state->iomem_base + offset);
-}
-
-int ps2ser_init(void)
-{
- int quot;
- unsigned cval;
-
- state = rs_table + CONFIG_PS2SERIAL;
-
- quot = state->baud_base / PS2SER_BAUD;
- cval = 0x3; /* 8N1 - 8 data bits, no parity bits, 1 stop bit */
-
- /* Set speed, enable interrupts, enable FIFO
- */
- ps2ser_out(UART_LCR, cval | UART_LCR_DLAB);
- ps2ser_out(UART_DLL, quot & 0xff);
- ps2ser_out(UART_DLM, quot >> 8);
- ps2ser_out(UART_LCR, cval);
- ps2ser_out(UART_IER, UART_IER_RDI);
- ps2ser_out(UART_MCR, UART_MCR_OUT2 | UART_MCR_DTR | UART_MCR_RTS);
- ps2ser_out(UART_FCR,
- UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
-
- /* If we read 0xff from the LSR, there is no UART here
- */
- if (ps2ser_in(UART_LSR) == 0xff) {
- printf ("ps2ser.c: no UART found\n");
- return -1;
- }
-
- irq_install_handler(state->irq, ps2ser_interrupt, NULL);
-
- return 0;
-}
-#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */
+#endif /* CONFIG_MPC5xxx / other */
void ps2ser_putc(int chr)
{
#ifdef CONFIG_MPC5xxx
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
- defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
+#else
NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
-#ifdef DEBUG
- printf(">>>> 0x%02x\n", chr);
-#endif
+ debug(">>>> 0x%02x\n", chr);
#ifdef CONFIG_MPC5xxx
while (!(psc->psc_status & PSC_SR_TXRDY));
psc->psc_buffer_8 = chr;
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
- defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
+#else
while ((com_port->lsr & UART_LSR_THRE) == 0);
com_port->thr = chr;
-#else
- while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE));
-
- ps2ser_out(UART_TX, chr);
#endif
}
@@ -205,8 +147,7 @@ static int ps2ser_getc_hw(void)
{
#ifdef CONFIG_MPC5xxx
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
- defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
+#else
NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
int res = -1;
@@ -215,15 +156,10 @@ static int ps2ser_getc_hw(void)
if (psc->psc_status & PSC_SR_RXRDY) {
res = (psc->psc_buffer_8);
}
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
- defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
+#else
if (com_port->lsr & UART_LSR_DR) {
res = com_port->rbr;
}
-#else
- if (ps2ser_in(UART_LSR) & UART_LSR_DR) {
- res = (ps2ser_in(UART_RX));
- }
#endif
return res;
@@ -234,9 +170,7 @@ int ps2ser_getc(void)
volatile int chr;
int flags;
-#ifdef DEBUG
- printf("<< ");
-#endif
+ debug("<< ");
flags = disable_interrupts();
@@ -251,11 +185,10 @@ int ps2ser_getc(void)
}
while (chr < 0);
- if (flags) enable_interrupts();
+ if (flags)
+ enable_interrupts();
-#ifdef DEBUG
- printf("0x%02x\n", chr);
-#endif
+ debug("0x%02x\n", chr);
return chr;
}
@@ -275,8 +208,7 @@ static void ps2ser_interrupt(void *dev_id)
{
#ifdef CONFIG_MPC5xxx
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
- defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
+#else
NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
int chr;
@@ -286,11 +218,8 @@ static void ps2ser_interrupt(void *dev_id)
chr = ps2ser_getc_hw();
#ifdef CONFIG_MPC5xxx
status = psc->psc_status;
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
- defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
- status = com_port->lsr;
#else
- status = ps2ser_in(UART_IIR);
+ status = com_port->lsr;
#endif
if (chr < 0) continue;
@@ -303,13 +232,9 @@ static void ps2ser_interrupt(void *dev_id)
}
#ifdef CONFIG_MPC5xxx
} while (status & PSC_SR_RXRDY);
-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
- defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
- } while (status & UART_LSR_DR);
#else
- } while (status & UART_IIR_RDI);
+ } while (status & UART_LSR_DR);
#endif
-
if (atomic_read(&ps2buf_cnt)) {
ps2mult_callback(atomic_read(&ps2buf_cnt));
}
diff --git a/drivers/pcmcia/mpc8xx_pcmcia.c b/drivers/pcmcia/mpc8xx_pcmcia.c
index 7030574..74a50f1 100644
--- a/drivers/pcmcia/mpc8xx_pcmcia.c
+++ b/drivers/pcmcia/mpc8xx_pcmcia.c
@@ -57,12 +57,6 @@ static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] =
/* -------------------------------------------------------------------- */
-#ifdef CONFIG_HMI10
-#define HMI10_FRAM_TIMING ( PCMCIA_SHT(2) \
- | PCMCIA_SST(2) \
- | PCMCIA_SL(4))
-#endif
-
#if defined(CONFIG_LWMON) || defined(CONFIG_NSCU)
#define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(9) \
| PCMCIA_SST(3) \
@@ -106,17 +100,6 @@ int pcmcia_on (void)
switch (i) {
#ifdef CONFIG_IDE_8xx_PCCARD
case 4:
-#ifdef CONFIG_HMI10
- { /* map FRAM area */
- win->or = ( PCMCIA_BSIZE_256K
- | PCMCIA_PPS_8
- | PCMCIA_PRS_ATTR
- | slotbit
- | PCMCIA_PV
- | HMI10_FRAM_TIMING );
- break;
- }
-#endif
case 0: { /* map attribute memory */
win->or = ( PCMCIA_BSIZE_64M
| PCMCIA_PPS_8
@@ -147,18 +130,6 @@ int pcmcia_on (void)
break;
}
#endif /* CONFIG_IDE_8xx_PCCARD */
-#ifdef CONFIG_HMI10
- case 3: { /* map I/O window for 4xUART data/ctrl */
- win->br += 0x40000;
- win->or = ( PCMCIA_BSIZE_256K
- | PCMCIA_PPS_8
- | PCMCIA_PRS_IO
- | slotbit
- | PCMCIA_PV
- | CONFIG_SYS_PCMCIA_TIMING );
- break;
- }
-#endif /* CONFIG_HMI10 */
default: /* set to not valid */
win->or = 0;
break;
diff --git a/drivers/pcmcia/tqm8xx_pcmcia.c b/drivers/pcmcia/tqm8xx_pcmcia.c
index 6ba8b5c..ca1a9fe 100644
--- a/drivers/pcmcia/tqm8xx_pcmcia.c
+++ b/drivers/pcmcia/tqm8xx_pcmcia.c
@@ -36,39 +36,6 @@
#define power_on_5_0(slot) do {} while (0)
#define power_on_3_3(slot) do {} while (0)
-#elif defined(CONFIG_HMI10)
-
-static inline void power_config(int slot)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- /*
- * Configure Port B pins for
- * 5 Volts Enable and 3 Volts enable
- */
- immap->im_cpm.cp_pbpar &= ~(0x00000300);
-}
-
-static inline void power_off(int slot)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- /* remove all power */
- immap->im_cpm.cp_pbdat |= 0x00000300;
-}
-
-static inline void power_on_5_0(int slot)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- immap->im_cpm.cp_pbdat &= ~(0x0000100);
- immap->im_cpm.cp_pbdir |= 0x00000300;
-}
-
-static inline void power_on_3_3(int slot)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- immap->im_cpm.cp_pbdat &= ~(0x0000200);
- immap->im_cpm.cp_pbdir |= 0x00000300;
-}
-
#elif defined(CONFIG_VIRTLAB2)
#define power_config(slot) do {} while (0)
@@ -128,21 +95,12 @@ static inline void power_on_3_3(int slot)
#endif
-#ifdef CONFIG_HMI10
-static inline int check_card_is_absent(int slot)
-{
- volatile pcmconf8xx_t *pcmp =
- (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
- return pcmp->pcmc_pipr & (0x10000000 >> (slot << 4));
-}
-#else
static inline int check_card_is_absent(int slot)
{
volatile pcmconf8xx_t *pcmp =
(pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
return pcmp->pcmc_pipr & (0x18000000 >> (slot << 4));
}
-#endif
#ifdef NSCU_OE_INV
#define NSCU_GCRX_CXOE 0
diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h
deleted file mode 100644
index 2747d8c..0000000
--- a/include/configs/HMI10.h
+++ /dev/null
@@ -1,504 +0,0 @@
-/*
- * (C) Copyright 2000-2008
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_HMI10
-#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
-#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
-
-#define CONFIG_LCD
-#define CONFIG_NEC_NL6448BC33_54 /* NEC NL6448BC33_54 display */
-
-#ifdef CONFIG_LCD /* with LCD controller ? */
-#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
-#endif
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#define CONFIG_SYS_SMC_RXBUFLEN 128
-#define CONFIG_SYS_MAXIDLE 10
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
-
-#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
-#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
-#define CONFIG_PS2SERIAL 2 /* .. on COM3 */
-#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
-
-#define CONFIG_BOOTCOUNT_LIMIT
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/HMI10/uImage\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_BOARD_EARLY_INIT_R 1
-#define CONFIG_MISC_INIT_R 1
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-
-#define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SLAVE 0xFE
-
-/* Software (bit-bang) I2C driver configuration */
-#define PB_SCL 0x00000020 /* PB 26 */
-#define PB_SDA 0x00000010 /* PB 27 */
-
-#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
-#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
-#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
- else immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
- else immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-
-#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-#ifdef CONFIG_SPLASH_SCREEN
- #define CONFIG_CMD_BMP
-#endif
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-
-#if 0
-#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-
-/* use CFI flash driver */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#else /* we must activate GPL5 in the SIUMCR for CAN */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#endif /* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0100000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4100000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8100000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC100000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-#define PCMCIA_MEM_WIN_NO 5
-#define NSCU_OE_INV 1 /* PCMCIA_GCRX_CXOE is inverted */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-#ifndef CONFIG_STATUS_LED /* Status and IDE LED's are mutually exclusive */
-#define CONFIG_IDE_LED 1 /* LED for ide supported */
-#endif
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/*
- * FLASH timing:
- */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
- OR_SCY_3_CLK | OR_EHTR | OR_BI)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#ifndef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
-#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
-#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
- BR_PS_8 | BR_MS_UPMB | BR_V )
-#endif /* CONFIG_CAN_DRIVER */
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock!)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- *
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider = 98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-
-#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
-#define CONFIG_SYS_MAMR_PTA 98
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
- * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
- */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_HWCONFIG 1
-
-#endif /* __CONFIG_H */
diff --git a/include/status_led.h b/include/status_led.h
index f213595..b39ca64 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -43,7 +43,7 @@ void status_led_tick (unsigned long timestamp);
void status_led_set (int led, int state);
/***** TQM8xxL ********************************************************/
-#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_HMI10)
+#if defined(CONFIG_TQM8xxL)
# define STATUS_LED_PAR im_cpm.cp_pbpar
# define STATUS_LED_DIR im_cpm.cp_pbdir
# define STATUS_LED_ODR im_cpm.cp_pbodr
@@ -318,21 +318,6 @@ void status_led_set (int led, int state);
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-/***** HMI10 **********************************************************/
-#elif defined(CONFIG_HMI10)
-# define STATUS_LED_PAR im_ioport.iop_papar
-# define STATUS_LED_DIR im_ioport.iop_padir
-# define STATUS_LED_ODR im_ioport.iop_paodr
-# define STATUS_LED_DAT im_ioport.iop_padat
-
-# define STATUS_LED_BIT 0x00000001 /* LED is on PA15 */
-# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
/***** NetPhone ********************************************************/
#elif defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
/* XXX empty just to avoid the error */