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-rw-r--r--README5
-rw-r--r--drivers/ddr/fsl/ctrl_regs.c1
-rw-r--r--drivers/ddr/fsl/main.c1
-rw-r--r--drivers/ddr/fsl/options.c17
-rw-r--r--drivers/ddr/fsl/util.c3
-rw-r--r--include/fsl_ddr_sdram.h1
6 files changed, 26 insertions, 2 deletions
diff --git a/README b/README
index 355e898..f51f17e 100644
--- a/README
+++ b/README
@@ -497,6 +497,11 @@ The following options need to be configured:
same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
it could be different for ARM SoCs.
+ CONFIG_SYS_FSL_DDR_INTLV_256B
+ DDR controller interleaving on 256-byte. This is a special
+ interleaving mode, handled by Dickens for Freescale layerscape
+ SoCs with ARM core.
+
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 5acbc73..0882932 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -145,6 +145,7 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
if (!popts->memctl_interleaving)
break;
switch (popts->memctl_interleaving_mode) {
+ case FSL_DDR_256B_INTERLEAVING:
case FSL_DDR_CACHE_LINE_INTERLEAVING:
case FSL_DDR_PAGE_INTERLEAVING:
case FSL_DDR_BANK_INTERLEAVING:
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index dee50a0..d62ca63 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -291,6 +291,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
if (pinfo->memctl_opts[i].memctl_interleaving) {
switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
+ case FSL_DDR_256B_INTERLEAVING:
case FSL_DDR_CACHE_LINE_INTERLEAVING:
case FSL_DDR_PAGE_INTERLEAVING:
case FSL_DDR_BANK_INTERLEAVING:
diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index 4aafcce..b0cf046 100644
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -818,21 +818,33 @@ unsigned int populate_memctl_options(int all_dimms_registered,
* If memory controller interleaving is enabled, then the data
* bus widths must be programmed identically for all memory controllers.
*
- * XXX: Attempt to set all controllers to the same chip select
+ * Attempt to set all controllers to the same chip select
* interleaving mode. It will do a best effort to get the
* requested ranks interleaved together such that the result
* should be a subset of the requested configuration.
+ *
+ * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
+ * with 256 Byte is enabled.
*/
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
+#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
+ ;
+#else
goto done;
-
+#endif
if (pdimm[0].n_ranks == 0) {
printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
popts->memctl_interleaving = 0;
goto done;
}
popts->memctl_interleaving = 1;
+#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
+ popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
+ popts->memctl_interleaving = 1;
+ debug("256 Byte interleaving\n");
+ goto done;
+#endif
/*
* test null first. if CONFIG_HWCONFIG is not defined
* hwconfig_arg_cmp returns non-zero
@@ -1085,6 +1097,7 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo)
"Memory controller interleaving disabled.\n");
} else {
switch (check_intlv) {
+ case FSL_DDR_256B_INTERLEAVING:
case FSL_DDR_CACHE_LINE_INTERLEAVING:
case FSL_DDR_PAGE_INTERLEAVING:
case FSL_DDR_BANK_INTERLEAVING:
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index 450a488..ad53658 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -228,6 +228,9 @@ void board_add_ram_info(int use_default)
puts(" DDR Controller Interleaving Mode: ");
switch ((cs0_config >> 24) & 0xf) {
+ case FSL_DDR_256B_INTERLEAVING:
+ puts("256B");
+ break;
case FSL_DDR_CACHE_LINE_INTERLEAVING:
puts("cache line");
break;
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index 16cccc7..2a36431 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -76,6 +76,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define FSL_DDR_PAGE_INTERLEAVING 0x1
#define FSL_DDR_BANK_INTERLEAVING 0x2
#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
+#define FSL_DDR_256B_INTERLEAVING 0x8
#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA
#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC
#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD