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-rw-r--r--board/freescale/mx6sxsabresd/mx6sxsabresd.c115
-rw-r--r--configs/mx6sxsabresd_defconfig23
-rw-r--r--configs/mx6sxsabresd_emmc_defconfig23
-rw-r--r--configs/mx6sxsabresd_m4fastup_defconfig20
-rw-r--r--configs/mx6sxsabresd_plugin_defconfig27
-rw-r--r--configs/mx6sxsabresd_qspi2_defconfig23
-rw-r--r--include/configs/mx6sxsabresd.h26
7 files changed, 243 insertions, 14 deletions
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 9d40c9c..98ca4db 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -235,9 +235,11 @@ static int setup_fec(int fec_id)
ARRAY_SIZE(phy_control_pads));
/* Enable the ENET power, active low */
+ gpio_request(IMX_GPIO_NR(2, 6), "fec power en");
gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
/* Reset AR8031 PHY */
+ gpio_request(IMX_GPIO_NR(2, 7), "ar8031 reset");
gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
mdelay(10);
gpio_set_value(IMX_GPIO_NR(2, 7), 1);
@@ -256,8 +258,6 @@ int board_eth_init(bd_t *bis)
else
imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
- setup_fec(CONFIG_FEC_ENET_DEV);
-
return cpu_eth_init(bis);
}
@@ -290,7 +290,7 @@ struct i2c_pads_info i2c_pad_info2 = {
},
};
-
+#ifdef CONFIG_POWER
int power_init_board(void)
{
struct pmic *pfuze;
@@ -337,8 +337,56 @@ int power_init_board(void)
return 0;
}
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+int power_init_board(void)
+{
+ struct udevice *dev;
+ unsigned int reg;
+ int ret;
+
+ dev = pfuze_common_init();
+ if (!dev)
+ return -ENODEV;
+
+ ret = pfuze_mode_init(dev, APS_PFM);
+ if (ret < 0)
+ return ret;
+
+ /* set SW1AB staby volatage 0.975V*/
+ reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
+ reg &= ~0x3f;
+ reg |= PFUZE100_SW1ABC_SETP(11000);
+ pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
+
+ /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
+ reg &= ~0xc0;
+ reg |= 0x40;
+ pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
+
+ /* set SW1C staby volatage 0.975V*/
+ reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
+ reg &= ~0x3f;
+ reg |= PFUZE100_SW1ABC_SETP(11000);
+ pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
+
+ /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+ reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
+ reg &= ~0xc0;
+ reg |= 0x40;
+ pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
+
+ /* Enable power of VGEN5 3V3, needed for SD3 */
+ reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
+ reg &= ~LDO_VOL_MASK;
+ reg |= (LDOB_3_30V | (1 << LDO_EN));
+ pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
+ return 0;
+}
+#endif
#ifdef CONFIG_LDO_BYPASS_CHECK
+#ifdef CONFIG_POWER
void ldo_mode_set(int ldo_bypass)
{
unsigned int value;
@@ -387,6 +435,46 @@ void ldo_mode_set(int ldo_bypass)
}
}
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+void ldo_mode_set(int ldo_bypass)
+{
+ struct udevice *dev;
+ int ret;
+ int is_400M;
+ u32 vddarm;
+
+ ret = pmic_get("pfuze100", &dev);
+ if (ret == -ENODEV) {
+ printf("No PMIC found!\n");
+ return;
+ }
+
+ /* switch to ldo_bypass mode , boot on 800Mhz */
+ if (ldo_bypass) {
+ prep_anatop_bypass();
+
+ /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
+ pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750));
+
+ /* increase VDDSOC to 1.3V */
+ pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(13000));
+
+ is_400M = set_anatop_bypass(1);
+ if (is_400M)
+ vddarm = PFUZE100_SW1ABC_SETP(10750);
+ else
+ vddarm = PFUZE100_SW1ABC_SETP(11750);
+
+ pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
+
+ /* decrease VDDSOC to 1.175V */
+ pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(11750));
+
+ finish_anatop_bypass();
+ printf("switch to ldo_bypass mode!\n");
+ }
+}
+#endif
#endif
#ifdef CONFIG_USB_EHCI_MX6
@@ -542,6 +630,8 @@ int board_mmc_init(bd_t *bis)
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
+ gpio_request(USDHC3_PWR_GPIO, "usdhc3 pwr");
gpio_direction_input(USDHC3_CD_GPIO);
gpio_direction_output(USDHC3_PWR_GPIO, 1);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
@@ -553,6 +643,7 @@ int board_mmc_init(bd_t *bis)
#else
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ gpio_request(USDHC4_CD_GPIO, "usdhc4 cd");
gpio_direction_input(USDHC4_CD_GPIO);
#endif
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
@@ -595,6 +686,8 @@ int board_mmc_init(bd_t *bis)
case 2:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
+ gpio_request(USDHC3_PWR_GPIO, "usdhc3 pwr");
gpio_direction_input(USDHC3_CD_GPIO);
gpio_direction_output(USDHC3_PWR_GPIO, 1);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
@@ -603,6 +696,7 @@ int board_mmc_init(bd_t *bis)
case 3:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ gpio_request(USDHC4_CD_GPIO, "usdhc4 cd");
gpio_direction_input(USDHC4_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
@@ -616,6 +710,7 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_FSL_QSPI
+#ifndef CONFIG_DM_SPI
#define QSPI_PAD_CTRL1 \
(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
@@ -636,13 +731,15 @@ static iomux_v3_cfg_t const quadspi_pads[] = {
MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX6_PAD_NAND_DATA05__QSPI2_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
};
+#endif
int board_qspi_init(void)
{
+#ifndef CONFIG_DM_SPI
/* Set the iomux */
imx_iomux_v3_setup_multiple_pads(quadspi_pads,
ARRAY_SIZE(quadspi_pads));
-
+#endif
/* Set the clock */
enable_qspi_clk(1);
@@ -723,9 +820,11 @@ void do_enable_lvds(struct display_info_t const *dev)
ARRAY_SIZE(lvds_ctrl_pads));
/* Enable CABC */
+ gpio_request(IMX_GPIO_NR(4, 18), "CABC enable");
gpio_direction_output(IMX_GPIO_NR(4, 18) , 1);
/* Set Brightness to high */
+ gpio_request(IMX_GPIO_NR(6, 3), "lvds backlight");
gpio_direction_output(IMX_GPIO_NR(6, 3) , 1);
}
@@ -743,11 +842,13 @@ void do_enable_parallel_lcd(struct display_info_t const *dev)
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
/* Reset the LCD */
+ gpio_request(IMX_GPIO_NR(3, 27), "lcd reset");
gpio_direction_output(IMX_GPIO_NR(3, 27) , 0);
udelay(500);
gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
/* Set Brightness to high */
+ gpio_request(IMX_GPIO_NR(6, 4), "lcd backlight");
gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
}
@@ -812,6 +913,7 @@ int board_init(void)
ARRAY_SIZE(peri_3v3_pads));
/* Active high for ncp692 */
+ gpio_request(IMX_GPIO_NR(4, 16), "peri_3v3");
gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
#ifdef CONFIG_SYS_I2C_MXC
@@ -831,6 +933,11 @@ int board_init(void)
setup_pcie();
#endif
+ /* Also used for OF_CONTROL enabled */
+#ifdef CONFIG_FEC_MXC
+ setup_fec(CONFIG_FEC_ENET_DEV);
+#endif
+
return 0;
}
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index a721b26..522c7ca 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -22,17 +22,38 @@ CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
+CONFIG_OF_CONTROL=y
+# CONFIG_BLK is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_DM_USB=y
CONFIG_FSL_QSPI=y
CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sxsabresd_emmc_defconfig b/configs/mx6sxsabresd_emmc_defconfig
index 262b12b..cb19d7e 100644
--- a/configs/mx6sxsabresd_emmc_defconfig
+++ b/configs/mx6sxsabresd_emmc_defconfig
@@ -23,17 +23,38 @@ CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb-emmc"
+CONFIG_OF_CONTROL=y
+# CONFIG_BLK is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_DM_USB=y
CONFIG_FSL_QSPI=y
CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sxsabresd_m4fastup_defconfig b/configs/mx6sxsabresd_m4fastup_defconfig
index 2e7457a..6929a67 100644
--- a/configs/mx6sxsabresd_m4fastup_defconfig
+++ b/configs/mx6sxsabresd_m4fastup_defconfig
@@ -29,5 +29,23 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
+CONFIG_OF_CONTROL=y
+# CONFIG_BLK is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_DM_USB=y
CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sxsabresd_plugin_defconfig b/configs/mx6sxsabresd_plugin_defconfig
index c1c8390..f8c594e 100644
--- a/configs/mx6sxsabresd_plugin_defconfig
+++ b/configs/mx6sxsabresd_plugin_defconfig
@@ -13,8 +13,8 @@ CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
@@ -23,15 +23,38 @@ CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
+CONFIG_OF_CONTROL=y
+# CONFIG_BLK is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_DM_USB=y
CONFIG_FSL_QSPI=y
CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sxsabresd_qspi2_defconfig b/configs/mx6sxsabresd_qspi2_defconfig
index ac5af86..71ccb0b 100644
--- a/configs/mx6sxsabresd_qspi2_defconfig
+++ b/configs/mx6sxsabresd_qspi2_defconfig
@@ -23,17 +23,38 @@ CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
+CONFIG_OF_CONTROL=y
+# CONFIG_BLK is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_DM_USB=y
CONFIG_FSL_QSPI=y
CONFIG_IMX_BOOTAUX=y
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index b965191..78207b5 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -25,15 +25,25 @@
#ifdef CONFIG_IMX_BOOTAUX
/* Set to QSPI2 B flash at default */
+#ifdef CONFIG_DM_SPI
+#define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000
+#define SF_QSPI2_B_CS_NUM 2
+#elif defined(CONFIG_MX6SX_SABRESD_REVA)
+#define CONFIG_SYS_AUXCORE_BOOTDATA 0x71000000
+#define SF_QSPI2_B_CS_NUM 1
+#else
#define CONFIG_SYS_AUXCORE_BOOTDATA 0x72000000
+#define SF_QSPI2_B_CS_NUM 1
+#endif
/* When using M4 fastup demo, no need these M4 env, since QSPI is used by M4 */
#ifndef CONFIG_SYS_AUXCORE_FASTUP
#define UPDATE_M4_ENV \
"m4image=m4_qspi.bin\0" \
+ "m4_qspi_cs="__stringify(SF_QSPI2_B_CS_NUM)"\0" \
"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
"update_m4_from_sd=" \
- "if sf probe 1:0; then " \
+ "if sf probe 1:${m4_qspi_cs}; then " \
"if run loadm4image; then " \
"setexpr fw_sz ${filesize} + 0xffff; " \
"setexpr fw_sz ${fw_sz} / 0x10000; " \
@@ -42,7 +52,7 @@
"sf write ${loadaddr} 0x0 ${filesize}; " \
"fi; " \
"fi\0" \
- "m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
+ "m4boot=sf probe 1:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
#else
#define UPDATE_M4_ENV ""
#endif /* CONFIG_SYS_AUXCORE_FASTUP */
@@ -178,38 +188,46 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
/* I2C Configs */
+#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
+#endif
+#ifdef CONFIG_CMD_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
+#endif
/* PMIC */
+#ifndef CONFIG_DM_PMIC
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+#endif
/* Network */
#define CONFIG_FEC_MXC
#define CONFIG_MII
-#define CONFIG_FEC_ENET_DEV 0
+#define CONFIG_FEC_ENET_DEV 1
#if (CONFIG_FEC_ENET_DEV == 0)
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
+#define CONFIG_ETHPRIME "FEC0"
#elif (CONFIG_FEC_ENET_DEV == 1)
#define IMX_FEC_BASE ENET2_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x2
+#define CONFIG_ETHPRIME "FEC1"
#endif
#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
+#define CONFIG_FEC_MXC_MDIO_BASE ENET_BASE_ADDR
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
generated by cgit v1.1 at 2024-11-04 21:38:11 +0000