diff options
| -rw-r--r-- | arch/x86/Kconfig | 16 | ||||
| -rw-r--r-- | arch/x86/dts/Makefile | 1 | ||||
| -rw-r--r-- | arch/x86/dts/chromebox_panther.dts | 64 | ||||
| -rw-r--r-- | board/google/chromebox_panther/Kconfig | 34 | ||||
| -rw-r--r-- | board/google/chromebox_panther/MAINTAINERS | 6 | ||||
| -rw-r--r-- | board/google/chromebox_panther/Makefile | 7 | ||||
| -rw-r--r-- | board/google/chromebox_panther/panther.c | 22 | ||||
| -rw-r--r-- | configs/chromebox_panther_defconfig | 11 | ||||
| -rw-r--r-- | include/configs/chromebox_panther.h | 17 |
9 files changed, 178 insertions, 0 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index da27115..d171349 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -32,6 +32,20 @@ config TARGET_CHROMEBOOK_LINK and it provides a 2560x1700 high resolution touch-enabled LCD display. +config TARGET_CHROMEBOX_PANTHER + bool "Support Chromebox panther (not available)" + select n + help + Note: At present this must be used with Coreboot. See README.x86 + for instructions. + + This is the Asus Chromebox CN60 released in 2014. It uses an Intel + Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a + Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also + includes a USB SD reader, four USB3 ports, display port and HDMI + video output and a 16GB SATA solid state drive. There is no Chrome + OS EC on this model. + config TARGET_CROWNBAY bool "Support Intel Crown Bay CRB" help @@ -432,6 +446,8 @@ source "board/coreboot/coreboot/Kconfig" source "board/google/chromebook_link/Kconfig" +source "board/google/chromebox_panther/Kconfig" + source "board/intel/crownbay/Kconfig" source "board/intel/minnowmax/Kconfig" diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 7a66133..431bbd8 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -1,4 +1,5 @@ dtb-y += chromebook_link.dtb \ + chromebox_panther.dtb \ crownbay.dtb \ galileo.dtb \ minnowmax.dtb diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts new file mode 100644 index 0000000..4eccefd --- /dev/null +++ b/arch/x86/dts/chromebox_panther.dts @@ -0,0 +1,64 @@ +/dts-v1/; + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" + +/ { + model = "Google Panther"; + compatible = "google,panther", "intel,haswell"; + + aliases { + spi0 = "/spi"; + }; + + config { + silent-console = <0>; + no-keyboard; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x10>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x30 0x10>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x10>; + bank-name = "C"; + }; + + chosen { + stdout-path = "/serial"; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + #size-cells = <1>; + #address-cells = <1>; + reg = <0>; + compatible = "winbond,w25q64", "spi-flash"; + memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + /* Alignment: 4k (for updating) */ + reg = <0x003e0000 0x00010000>; + type = "wiped"; + wipe-value = [ff]; + }; + }; + }; + +}; diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig new file mode 100644 index 0000000..11df55a --- /dev/null +++ b/board/google/chromebox_panther/Kconfig @@ -0,0 +1,34 @@ +if TARGET_CHROMEBOX_PANTHER + +config SYS_BOARD + default "chromebox_panther" + +config SYS_VENDOR + default "google" + +config SYS_SOC + default "ivybridge" + +config SYS_CONFIG_NAME + default "chromebox_panther" + +# Panther actually uses haswell, not ivybridge, so this is just a placeholder +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select CPU_INTEL_SOCKET_RPGA989 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SOUTHBRIDGE_INTEL_C216 + select HAVE_ACPI_RESUME + select MARK_GRAPHICS_MEM_WRCOMB + select BOARD_ROMSIZE_KB_8192 + +config SYS_CAR_ADDR + hex + default 0xff7e0000 + +config SYS_CAR_SIZE + hex + default 0x20000 + +endif diff --git a/board/google/chromebox_panther/MAINTAINERS b/board/google/chromebox_panther/MAINTAINERS new file mode 100644 index 0000000..c88774b --- /dev/null +++ b/board/google/chromebox_panther/MAINTAINERS @@ -0,0 +1,6 @@ +CHROMEBOX PANTHER BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/google/chromebook_panther/ +F: include/configs/chromebox_panther.h +F: configs/chromebox_panther_defconfig diff --git a/board/google/chromebox_panther/Makefile b/board/google/chromebox_panther/Makefile new file mode 100644 index 0000000..ce8820f --- /dev/null +++ b/board/google/chromebox_panther/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += panther.o diff --git a/board/google/chromebox_panther/panther.c b/board/google/chromebox_panther/panther.c new file mode 100644 index 0000000..d492a03 --- /dev/null +++ b/board/google/chromebox_panther/panther.c @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/pch.h> + +int arch_early_init_r(void) +{ + return 0; +} + +int board_early_init_f(void) +{ + return 0; +} + +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) +{ +} diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig new file mode 100644 index 0000000..cbde39e --- /dev/null +++ b/configs/chromebox_panther_defconfig @@ -0,0 +1,11 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" +CONFIG_X86=y +CONFIG_TARGET_CHROMEBOX_PANTHER=y +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y +CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther" +CONFIG_HAVE_MRC=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y diff --git a/include/configs/chromebox_panther.h b/include/configs/chromebox_panther.h new file mode 100644 index 0000000..00fe26d --- /dev/null +++ b/include/configs/chromebox_panther.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> +#include <configs/x86-chromebook.h> + +#define CONFIG_RTL8169 +/* Avoid a warning in the Realtek Ethernet driver */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#endif /* __CONFIG_H */ |