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-rw-r--r--arch/powerpc/cpu/mpc85xx/cmd_errata.c3
-rw-r--r--arch/powerpc/cpu/mpc85xx/ddr-gen3.c5
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h7
3 files changed, 15 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 523f297..2ed5a98 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -56,6 +56,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
puts("Work-around for Erratum CPU-A003999 enabled\n");
#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
+ puts("Work-around for Erratum DDR-A003473 enabled\n");
+#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index c8c84a1..18e9cc5 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -115,6 +115,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
for (i = 0; i < 32; i++)
out_be32(&ddr->debug[i], regs->debug[i]);
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+ out_be32(&ddr->debug[12], 0x00000015);
+ out_be32(&ddr->debug[21], 0x24000000);
+#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
+
/* Set, but do not enable the memory */
temp_sdram_cfg = regs->ddr_sdram_cfg;
temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index f1da82e..2e4be34 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -314,6 +314,7 @@
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#elif defined(CONFIG_PPC_P2041)
#define CONFIG_MAX_CPUS 4
@@ -333,6 +334,7 @@
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#elif defined(CONFIG_PPC_P3041)
#define CONFIG_MAX_CPUS 4
@@ -352,6 +354,7 @@
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#elif defined(CONFIG_PPC_P3060)
#define CONFIG_MAX_CPUS 8
@@ -379,6 +382,7 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#elif defined(CONFIG_PPC_P4080)
#define CONFIG_MAX_CPUS 8
@@ -408,6 +412,7 @@
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
/* P5010 is single core version of P5020 */
#elif defined(CONFIG_PPC_P5010)
@@ -427,6 +432,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#elif defined(CONFIG_PPC_P5020)
#define CONFIG_MAX_CPUS 2
@@ -445,6 +451,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#else
#error Processor type not defined for this platform