diff options
| -rw-r--r-- | board/freescale/t208xqds/ddr.h | 28 | ||||
| -rw-r--r-- | include/configs/T208xQDS.h | 5 |
2 files changed, 17 insertions, 16 deletions
diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h index 9fc879a..ed52fef6 100644 --- a/board/freescale/t208xqds/ddr.h +++ b/board/freescale/t208xqds/ddr.h @@ -25,21 +25,21 @@ struct board_specific_parameters { static const struct board_specific_parameters udimm0[] = { /* * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ - {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, - {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, - {2, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, - {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, - {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, - {2, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b}, - {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, - {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, - {1, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, - {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, - {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, - {1, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b}, + {2, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {2, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09}, + {2, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, + {2, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {2, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {2, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b}, + {1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09}, + {1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, + {1, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b}, {} }; diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 8dd2e49..59d142e 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -227,8 +227,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR3 #undef CONFIG_FSL_DDR_INTERACTIVE |