diff options
| -rw-r--r-- | board/isee/igep0146/igep0146.c | 77 |
1 files changed, 73 insertions, 4 deletions
diff --git a/board/isee/igep0146/igep0146.c b/board/isee/igep0146/igep0146.c index a7d52a8..d508853 100644 --- a/board/isee/igep0146/igep0146.c +++ b/board/isee/igep0146/igep0146.c @@ -458,6 +458,73 @@ void ldo_mode_set(int ldo_bypass) #include <asm/arch/mx6-ddr.h> /* ENTIRE RAM CALIBRATION STRUCTURES MISSING */ +#define IMX6UL_DRIVE_STRENGTH 0x30 + +/* configure MX6UL mmdc DDR io registers */ +static struct mx6ul_iomux_grp_regs mx6ul_grp_ioregs = { + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = IMX6UL_DRIVE_STRENGTH, + .grp_ctlds = IMX6UL_DRIVE_STRENGTH, + .grp_ddrmode = 0x00020000, + .grp_b0ds = IMX6UL_DRIVE_STRENGTH, + .grp_b1ds = IMX6UL_DRIVE_STRENGTH, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba0 = 0x00000000, + .dram_sdba1 = 0x00000000, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0x415C015C, + .p0_mprddlctl = 0x40404244, + .p0_mpwrdlctl = 0x40405A58, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, /* MMDC_MDCTL */ + .cs_density = 20, /* MMDC_MDASP - (20*4 - 1) = 0x4F CS0_END = 4 Gb per CS */ + .ncs = 1, /* MMDC_MDCTL - SDE_0 SDE_1*/ + .cs1_mirror = 0, /* MMDC_MDMISC */ + .rtt_wr = 2, /* This parameter will go into MMDC_MDSCR to change DRAM MR2 register !! */ + .rtt_nom = 1, /* RTT_Nom = RZQ/2 - MMDC_MPODTCTRL */ + .walat = 0, /* Write additional latency - MMDC_MDMISC */ + .ralat = 5, /* Read additional latency - MMDC_MDMISC */ + .mif3_mode = 3, /* Command prediction working mode - MMDC_MDMISC */ + .bi_on = 1, /* Bank interleaving enabled - MMDC_MDMISC */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) - MMDC_MDOR */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) - MMDC_MDOR */ + .ddr_type = DDR_TYPE_DDR3, /* MMDC_MDMISC */ + .refsel = 0, /* Refresh cycles at 64KHz - MMDC_MDREF */ + .refr = 1, /* 2 refresh commands per refresh cycle MMDC_MDREF */ +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, /* test first with 1600 parameters (backwards compatible) tcwl - MMDC_MDCFG1*/ + .density = 4, /* Gb per Chip Select - MMDC_MDCFG0 will configure tRFC and tXS */ + .width = 16, /* MDCTL */ + .banks = 8, /* MDMISC */ + .rowaddr = 15, /* MDCTL */ + .coladdr = 10, /* MDCTL */ + .pagesz = 2, /* Internal parameter depends on your own DRAM conf */ + .trcd = 1375, /* MMDC_MDCFG1 */ + .trcmin = 4875, /* MMDC_MDCFG1 */ + .trasmin = 3500, /* MMDC_MDCFG1 */ +}; static void ccgr_init(void) { @@ -475,11 +542,8 @@ static void ccgr_init(void) static void spl_dram_init(void) { - /* COMMENTED UNTIL VALID RAM CONFIGURATION FOUND */ - /* - mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6ul_grp_ioregs); mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); - */ } /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */ @@ -488,6 +552,11 @@ void spl_board_init(void) { } +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = BOOT_DEVICE_MMC1; + spl_boot_list[1] = BOOT_DEVICE_MMC2; +} void board_init_f(ulong dummy) { |