diff options
| -rw-r--r-- | arch/arm/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx7ulp/soc.c | 36 | ||||
| -rw-r--r-- | arch/arm/imx-common/Makefile | 4 | ||||
| -rw-r--r-- | arch/arm/imx-common/hab.c | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-imx/cpu.h | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 5 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 11 |
7 files changed, 24 insertions, 39 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 6defdfb..29eb059 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -84,7 +84,7 @@ ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 libs-y += arch/arm/imx-common/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35 mxs vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35 mxs vf610 mx7ulp)) libs-y += arch/arm/imx-common/ endif endif diff --git a/arch/arm/cpu/armv7/mx7ulp/soc.c b/arch/arm/cpu/armv7/mx7ulp/soc.c index 19ca368..04b98a0 100644 --- a/arch/arm/cpu/armv7/mx7ulp/soc.c +++ b/arch/arm/cpu/armv7/mx7ulp/soc.c @@ -28,7 +28,7 @@ static char *get_reset_cause(char *); u32 get_cpu_rev(void) { /* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */ - return (0x73 << 12) | (1 << 4); + return (MXC_CPU_MX7ULP << 12) | (1 << 4); } #ifdef CONFIG_REVISION_TAG @@ -96,31 +96,6 @@ int arch_cpu_init(void) return 0; } -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) - enum dcache_option option = DCACHE_WRITETHROUGH; -#else - enum dcache_option option = DCACHE_WRITEBACK; -#endif - - /* Avoid random hang when download by usb */ - invalidate_dcache_all(); - - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); - - /* Enable caching on OCRAM and ROM */ - mmu_set_region_dcache_behaviour(CORE_B_ROM_BASE, - CORE_B_ROM_SIZE, - option); - mmu_set_region_dcache_behaviour(OCRAM_0_BASE, - SZ_128K + SZ_128K, - option); -} -#endif - #ifdef CONFIG_BOARD_POSTCLK_INIT int board_postclk_init(void) { @@ -279,6 +254,8 @@ int print_cpuinfo(void) #define CMC_SRS_POR (1 << 1) #define CMC_SRS_WUP (1 << 0) +static u32 reset_cause = -1; + static char *get_reset_cause(char *ret) { u32 cause1, cause = 0, srs = 0; @@ -292,6 +269,8 @@ static char *get_reset_cause(char *ret) cause1 = readl(reg_ssrs); writel(cause1, reg_ssrs); + reset_cause = cause1; + cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM); switch (cause) { @@ -328,6 +307,11 @@ static char *get_reset_cause(char *ret) return ret; } +u32 get_imx_reset_cause(void) +{ + return reset_cause; +} + #ifdef CONFIG_ENV_IS_IN_MMC __weak int board_mmc_get_env_dev(int devno) { diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index a9d64f6..d9d73a3 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -35,6 +35,10 @@ obj-$(CONFIG_SECURE_BOOT) += hab.o obj-$(CONFIG_GPT_TIMER) += timer.o obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o endif +ifeq ($(SOC),$(filter $(SOC),mx7ulp)) +obj-y += cache.o +obj-$(CONFIG_SECURE_BOOT) += hab.o +endif ifeq ($(SOC),$(filter $(SOC),vf610)) obj-y += ddrmc-vf610.o endif diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c index 1ff4bd9..ce5dd15 100644 --- a/arch/arm/imx-common/hab.c +++ b/arch/arm/imx-common/hab.c @@ -102,7 +102,7 @@ #define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0 #define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18 #define IS_HAB_ENABLED_BIT \ - (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2) + (is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)) /* * +------------+ 0x0 (DDR_UIMAGE_START) - diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 8dd9c04..1c0e12b 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -24,11 +24,12 @@ #define MXC_CPU_MX6DP 0x68 #define MXC_CPU_MX6QP 0x69 #define MXC_CPU_MX7D 0x72 -#define MXC_CPU_MX7ULP 0x73 /* Temporally hard code */ +#define MXC_CPU_MX7ULP 0x81 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ #define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 +#define MXC_SOC_MX7ULP 0x80 /* dummy */ #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_1 0x11 diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index ee38e01..fed22f6 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -97,6 +97,11 @@ #define CORE_B_ROM_SIZE (SZ_32K + SZ_64K) #define CORE_B_ROM_BASE (0x00000000) +#define ROMCP_ARB_BASE_ADDR CORE_B_ROM_BASE +#define ROMCP_ARB_END_ADDR CORE_B_ROM_SIZE +#define IRAM_BASE_ADDR OCRAM_0_BASE +#define IRAM_SIZE (SZ_128K + SZ_128K) + #define IOMUXC_PCR_MUX_ALT0 (0<<8) #define IOMUXC_PCR_MUX_ALT1 (1<<8) #define IOMUXC_PCR_MUX_ALT2 (2<<8) diff --git a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h index ec5c017..753a58d 100644 --- a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h +++ b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h @@ -3,9 +3,7 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ +#include <asm/imx-common/sys_proto.h> #define BT0CFG_LPBOOT_MASK 0x1 #define BT0CFG_DUALBOOT_MASK 0x2 @@ -15,10 +13,3 @@ enum bt_mode { DUAL_BOOT, /* LP_BT = 0, DUAL_BT = 1 */ SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */ }; - -u32 get_cpu_rev(void); - -int mmc_get_env_dev(void); -void board_late_mmc_env_init(void); - -#endif |