diff options
925 files changed, 29234 insertions, 23917 deletions
@@ -33,6 +33,7 @@ /u-boot.sha1 /u-boot.dis /u-boot.lds +/u-boot.ubl # # Generated files @@ -161,11 +161,6 @@ N: Thomas Frieden E: ThomasF@hyperion-entertainment.com D: Support for AmigaOne -N: Niklaus Giger -E: niklaus.giger@netstal.com -D: Support for HCU(x) boards -W: www.netstal.com - N: Paul Gortmaker E: paul.gortmaker@windriver.com D: Support for WRS SBC8347/8349 boards diff --git a/MAINTAINERS b/MAINTAINERS index c462ae2..fd4181f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -193,12 +193,6 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com> WUH405 PPC405EP CMS700 PPC405EP -Niklaus Giger <niklaus.giger@netstal.com> - - HCU4 PPC405GPr - MCU25 PPC405GPr - HCU5 PPC440EPx - Siddarth Gore <gores@marvell.com> guruplug ARM926EJS (Kirkwood SoC) @@ -302,6 +296,11 @@ Dan Malek <dan@embeddedalley.com> stxssa MPC85xx stxxtc MPC8xx +Ryan Mallon <ryan@bluewatersys.com> + + snapper9260 ARM926EJS (AT91SAM9260 SoC) + snapper9g20 ARM926EJS (AT91SAM9G20 SoC) + Eran Man <eran@nbase.co.il> EVB64260_750CX MPC750CX @@ -446,6 +445,7 @@ Peter De Schrijver <p2@mind.be> Andre Schwarz <andre.schwarz@matrix-vision.de> + mergerbox MPC8377 mvbc_p MPC5200 mvblm7 MPC8343 mvsmr MPC5200 @@ -511,6 +511,7 @@ Ilya Yanok <yanok@emcraft.com> Roy Zang <tie-fei.zang@freescale.com> mpc7448hpc2 MPC7448 + P1023RDS P1023 John Zhan <zhanz@sinovee.com> @@ -543,6 +544,10 @@ Unknown / orphaned boards: EVB64260 MPC7xx_74xx + integratorcp various + versatile ARM926EJ-S + versatile ARM926EJ-S + ######################################################################### # ARM Systems: # @@ -564,8 +569,8 @@ Stefano Babic <sbabic@denx.de> ea20 davinci mx35pdk i.MX35 mx51evk i.MX51 - polaris xscale - trizepsiv xscale + polaris xscale/pxa + trizepsiv xscale/pxa vision2 i.MX51 Jason Liu <r64343@freescale.com> @@ -595,10 +600,11 @@ Rishi Bhattacharya <rishi@ti.com> Andreas Bießmann <andreas.devel@gmail.com> at91rm9200ek at91rm9200 + grasshopper avr32 Cliff Brake <cliff.brake@gmail.com> - pxa255_idp xscale + pxa255_idp xscale/pxa Rick Bronson <rick@efn.org> @@ -636,6 +642,7 @@ Kristoffer Ericson <kristoffer.ericson@gmail.com> Fabio Estevam <fabio.estevam@freescale.com> mx31pdk i.MX31 + mx53ard i.MX53 mx53smd i.MX53 Daniel Gorsulowski <daniel.gorsulowski@esd.eu> @@ -647,6 +654,12 @@ Sedji Gaouaou<sedji.gaouaou@atmel.com> at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC) at91sam9m10g45ek ARM926EJS (AT91SAM9G45 SoC) +Simon Guinot <simon.guinot@sequanux.org> + + inetspace_v2 ARM926EJS (Kirkwood SoC) + netspace_v2 ARM926EJS (Kirkwood SoC) + netspace_max_v2 ARM926EJS (Kirkwood SoC) + Marius Gröger <mag@sysgo.de> impa7 ARM720T (EP7211) @@ -672,7 +685,6 @@ Grazvydas Ignotas <notasas@gmail.com> Gary Jennejohn <garyj@denx.de> smdk2400 ARM920T - trab ARM920T Matthias Kaehlcke <matthias@kaehlcke.net> edb9301 ARM920T (EP9301) @@ -684,9 +696,6 @@ Matthias Kaehlcke <matthias@kaehlcke.net> edb9315 ARM920T (EP9315) edb9315a ARM920T (EP9315) -Konstantin Kletschke <kletschke@synertronixx.de> - scb9328 ARM920T - Nishant Kamat <nskamat@ti.com> omap1610h2 ARM926EJS @@ -701,6 +710,9 @@ Chander Kashyap <k.chander@samsung.com> SMDKV310 ARM ARMV7 (S5PC210 SoC) +Torsten Koschorrek <koschorrek@synertronixx.de> + scb9328 ARM920T (i.MXL) + Frederik Kriewitz <frederik@kriewitz.eu> devkit8000 ARM ARMV7 (OMAP3530 SoC) @@ -713,7 +725,7 @@ Sergey Kubushyn <ksi@koi8.net> Prakash Kumar <prakash@embedx.com> - cerf250 xscale + cerf250 xscale/pxa Vipin Kumar <vipin.kumar@st.com> @@ -726,6 +738,11 @@ Sergey Lapin <slapin@ossfans.org> afeb9260 ARM926EJS (AT91SAM9260 SoC) +Valentin Longchamp <valentin.longchamp@keymile.com> + + km_kirkwood ARM926EJS (Kirkwood SoC) + portl2 ARM926EJS (Kirkwood SoC) + Nishanth Menon <nm@ti.com> omap3_sdp3430 ARM ARMV7 (OMAP3xx SoC) @@ -759,11 +776,8 @@ Sandeep Paulraj <s-paulraj@ti.com> davinci_dm365evm ARM926EJS davinci_dm6467evm ARM926EJS -Peter Pearse <peter.pearse@arm.com> - integratorcp All current ARM supplied & supported core modules - -see http://www.arm.com/products/DevTools/Hardware_Platforms.html - versatile ARM926EJ-S - versatile ARM926EJ-S +Linus Walleij <linus.walleij@linaro.org> + integratorap ARM920T Dave Peverley <dpeverley@mpc-data.co.uk> @@ -791,9 +805,9 @@ John Rigby <jcrigby@gmail.com> Stefan Roese <sr@denx.de> - ixdpg425 xscale - pdnb3 xscale - scpu xscale + ixdpg425 xscale/ixp + pdnb3 xscale/ixp + scpu xscale/ixp Alessandro Rubini <rubini@unipv.it> Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com> @@ -814,20 +828,19 @@ Heiko Schocher <hs@denx.de> magnesium i.MX27 mgcoge3un ARM926EJS (Kirkwood SoC) - suen3 ARM926EJS (Kirkwood SoC) - suen8 ARM926EJS (Kirkwood SoC) Robert Schwebel <r.schwebel@pengutronix.de> - csb226 xscale - innokom xscale + csb226 xscale/pxa + innokom xscale/pxa Michael Schwingen <michael@schwingen.org> - actux1 xscale - actux2 xscale - actux3 xscale - actux4 xscale + actux1 xscale/ixp + actux2 xscale/ixp + actux3 xscale/ixp + actux4 xscale/ixp + dvlhost xscale/ixp Andrea Scian <andrea.scian@dave-tech.it> @@ -851,12 +864,12 @@ Greg Ungerer <greg.ungerer@opengear.com> Marek Vasut <marek.vasut@gmail.com> - balloon3 xscale - colibri_pxa270 xscale - palmld xscale - palmtc xscale - vpac270 xscale - zipitz2 xscale + balloon3 xscale/pxa + colibri_pxa270 xscale/pxa + palmld xscale/pxa + palmtc xscale/pxa + vpac270 xscale/pxa + zipitz2 xscale/pxa efikamx i.MX51 Hugo Villeneuve <hugo.villeneuve@lyrtech.com> @@ -887,6 +900,7 @@ Lei Wen <leiwen@marvell.com> Matthias Weisser <weisserm@arcor.de> jadecpu ARM926EJS (MB86R01 SoC) + zmx25 ARM926EJS (imx25 SoC) Richard Woodruff <r-woodruff2@ti.com> @@ -907,9 +921,9 @@ Sughosh Ganu <urwithsughosh@gmail.com> Unknown / orphaned boards: Board CPU Last known maintainer / Comment ......................................................................... - cradle xscale Kyle Harris <kharris@nexus-tech.net> / dead address - ixdp425 xscale Kyle Harris <kharris@nexus-tech.net> / dead address - lubbock xscale Kyle Harris <kharris@nexus-tech.net> / dead address + cradle xscale/pxa Kyle Harris <kharris@nexus-tech.net> / dead address + ixdp425 xscale/ixp Kyle Harris <kharris@nexus-tech.net> / dead address + lubbock xscale/pxa Kyle Harris <kharris@nexus-tech.net> / dead address imx31_phycore_eet i.MX31 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned mx31ads i.MX31 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned @@ -1,58 +1,54 @@ #!/bin/bash - # Tool mainly for U-Boot Quality Assurance: build one or more board # configurations with minimal verbosity, showing only warnings and # errors. -# -# There are several ways to select which boards to build. -# -# Traditionally, architecture names (like "powerpc"), CPU family names -# (like "mpc83xx") or board names can be specified on the command -# line; without any arguments, MAKEALL defaults to building all Power -# Architecture systems (i. e. same as for "MAKEALL powerpc"). -# -# With the introduction of the board.cfg file, it has become possible -# to provide additional selections. We use standard command line -# options for this: -# -# -a or --arch : Select architecture -# -c or --cpu : Select CPU family -# -s or --soc : Select SoC type -# -v or --vendor: Select board vendor -# -# Selections by these options are logically ANDed; if the same option -# is used repeatedly, such selections are ORed. So "-v FOO -v BAR" -# will select all configurations where the vendor is either FOO or -# BAR. Any additional arguments specified on the command line are -# always build additionally. -# -# Examples: -# -# - build all Power Architecture boards: -# -# MAKEALL -a powerpc -# or -# MAKEALL --arch powerpc -# or -# MAKEALL powerpc -# -# - build all PowerPC boards manufactured by vendor "esd": -# -# MAKEALL -a powerpc -v esd -# -# - build all PowerPC boards manufactured either by "keymile" or -# "siemens": -# -# MAKEALL -a powerpc -v keymile -v siemens -# -# - build all Freescale boards with MPC83xx CPUs, plus all 4xx boards: -# -# MAKEALL -c mpc83xx -v freescale 4xx -# -######################################################################### - -SHORT_OPTS="a:c:v:s:" -LONG_OPTS="arch:,cpu:,vendor:,soc:" + +usage() +{ + # if exiting with 0, write to stdout, else write to stderr + local ret=${1:-0} + [ "${ret}" -eq 1 ] && exec 1>&2 + cat <<-EOF + Usage: MAKEALL [options] [--] [boards-to-build] + + Options: + -a ARCH, --arch ARCH Build all boards with arch ARCH + -c CPU, --cpu CPU Build all boards with cpu CPU + -v VENDOR, --vendor VENDOR Build all boards with vendor VENDOR + -s SOC, --soc SOC Build all boards with soc SOC + -h, --help This help output + + Selections by these options are logically ANDed; if the same option + is used repeatedly, such selections are ORed. So "-v FOO -v BAR" + will select all configurations where the vendor is either FOO or + BAR. Any additional arguments specified on the command line are + always build additionally. See the boards.cfg file for more info. + + If no boards are specified, then the default is "powerpc". + + Environment variables: + BUILD_NCPUS number of parallel make jobs (default: auto) + CROSS_COMPILE cross-compiler toolchain prefix (default: "") + MAKEALL_LOGDIR output all logs to here (default: ./LOG/) + BUILD_DIR output build directory (default: ./) + + Examples: + - build all Power Architecture boards: + MAKEALL -a powerpc + MAKEALL --arch powerpc + MAKEALL powerpc + - build all PowerPC boards manufactured by vendor "esd": + MAKEALL -a powerpc -v esd + - build all PowerPC boards manufactured either by "keymile" or "siemens": + MAKEALL -a powerpc -v keymile -v siemens + - build all Freescale boards with MPC83xx CPUs, plus all 4xx boards: + MAKEALL -c mpc83xx -v freescale 4xx + EOF + exit ${ret} +} + +SHORT_OPTS="ha:c:v:s:" +LONG_OPTS="help,arch:,cpu:,vendor:,soc:" # Option processing based on util-linux-2.13/getopt-parse.bash @@ -63,7 +59,7 @@ LONG_OPTS="arch:,cpu:,vendor:,soc:" TEMP=`getopt -o ${SHORT_OPTS} --long ${LONG_OPTS} \ -n 'MAKEALL' -- "$@"` -if [ $? != 0 ] ; then echo "Terminating..." >&2 ; exit 1 ; fi +[ $? != 0 ] && usage 1 # Note the quotes around `$TEMP': they are essential! eval set -- "$TEMP" @@ -108,6 +104,8 @@ while true ; do fi SELECTED='y' shift 2 ;; + -h|--help) + usage ;; --) shift ; break ;; *) @@ -347,6 +345,7 @@ LIST_ARM9=" \ guruplug \ imx27lite \ jadecpu \ + km_kirkwood \ lpd7a400 \ magnesium \ mv88f6281gtw_ge \ @@ -363,6 +362,7 @@ LIST_ARM9=" \ openrd_base \ openrd_client \ openrd_ultimate \ + portl2 \ rd6281a \ sbc2410x \ scb9328 \ @@ -373,8 +373,6 @@ LIST_ARM9=" \ spear310 \ spear320 \ spear600 \ - suen3 \ - trab \ VCMA9 \ versatile \ versatileab \ @@ -446,17 +444,7 @@ LIST_ARMV7=" \ ######################################################################### LIST_at91="$(boards_by_soc at91)\ - $(boards_by_soc at91rm9200)\ - at91sam9260ek \ - at91sam9261ek \ - at91sam9263ek \ - at91sam9g10ek \ - at91sam9g20ek \ at91sam9m10g45ek \ - at91sam9rlek \ - CPUAT91 \ - CPU9260 \ - CPU9G20 \ pm9g45 \ SBC35_A9G20 \ TNY_A9260 \ @@ -557,9 +545,7 @@ LIST_x86="$(boards_by_arch x86)" ## Nios-II Systems ######################################################################### -LIST_nios2="$(boards_by_arch nios2) - nios2-generic \ -" +LIST_nios2="$(boards_by_arch nios2)" ######################################################################### ## MicroBlaze Systems @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2010 +# (C) Copyright 2000-2011 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -24,7 +24,7 @@ VERSION = 2011 PATCHLEVEL = 06 SUBLEVEL = -EXTRAVERSION = -rc2 +EXTRAVERSION = ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else @@ -104,10 +104,11 @@ $(if $(BUILD_DIR),,$(error output directory "$(saved-output)" does not exist)) endif # ifneq ($(BUILD_DIR),) OBJTREE := $(if $(BUILD_DIR),$(BUILD_DIR),$(CURDIR)) +SPLTREE := $(OBJTREE)/spl SRCTREE := $(CURDIR) TOPDIR := $(SRCTREE) LNDIR := $(OBJTREE) -export TOPDIR SRCTREE OBJTREE +export TOPDIR SRCTREE OBJTREE SPLTREE MKCONFIG := $(SRCTREE)/mkconfig export MKCONFIG @@ -140,7 +141,7 @@ SUBDIRS = tools \ examples/standalone \ examples/api -.PHONY : $(SUBDIRS) +.PHONY : $(SUBDIRS) $(VERSION_FILE) ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk)) @@ -163,6 +164,36 @@ endif # load other configuration include $(TOPDIR)/config.mk +# If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use +# that (or fail if absent). Otherwise, search for a linker script in a +# standard location. + +ifndef LDSCRIPT + #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug + ifdef CONFIG_SYS_LDSCRIPT + # need to strip off double quotes + LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT)) + endif +endif + +ifndef LDSCRIPT + ifeq ($(CONFIG_NAND_U_BOOT),y) + LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds + ifeq ($(wildcard $(LDSCRIPT)),) + LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds + endif + endif + ifeq ($(wildcard $(LDSCRIPT)),) + LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds + endif + ifeq ($(wildcard $(LDSCRIPT)),) + LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot.lds + endif + ifeq ($(wildcard $(LDSCRIPT)),) +$(error could not find linker script) + endif +endif + ######################################################################### # U-Boot objects....order is important (i.e. start must be first) @@ -236,7 +267,7 @@ endif LIBS += drivers/rtc/librtc.o LIBS += drivers/serial/libserial.o LIBS += drivers/twserial/libtws.o -LIBS += drivers/usb/eth/libusb_eth.a +LIBS += drivers/usb/eth/libusb_eth.o LIBS += drivers/usb/gadget/libusb_gadget.o LIBS += drivers/usb/host/libusb_host.o LIBS += drivers/usb/musb/libusb_musb.o @@ -263,7 +294,7 @@ LIBS += $(CPUDIR)/s5p-common/libs5p-common.o endif LIBS := $(addprefix $(obj),$(sort $(LIBS))) -.PHONY : $(LIBS) $(TIMESTAMP_FILE) $(VERSION_FILE) +.PHONY : $(LIBS) $(TIMESTAMP_FILE) LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).o LIBBOARD := $(addprefix $(obj),$(LIBBOARD)) @@ -311,22 +342,15 @@ BOARD_SIZE_CHECK = endif # Always append ALL so that arch config.mk's can add custom ones -ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map - -ifeq ($(CONFIG_NAND_U_BOOT),y) -ALL += $(obj)u-boot-nand.bin -endif +ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map -ifeq ($(CONFIG_ONENAND_U_BOOT),y) -ALL += $(obj)u-boot-onenand.bin +ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin +ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin -endif - -ifeq ($(CONFIG_MMC_U_BOOT),y) -ALL += $(obj)mmc_spl/u-boot-mmc-spl.bin -endif +ALL-$(CONFIG_MMC_U_BOOT) += $(obj)mmc_spl/u-boot-mmc-spl.bin +ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin -all: $(ALL) +all: $(ALL-y) $(obj)u-boot.hex: $(obj)u-boot $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ @@ -351,7 +375,7 @@ $(obj)u-boot.ldr.srec: $(obj)u-boot.ldr $(obj)u-boot.img: $(obj)u-boot.bin $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \ - -a $(CONFIG_SYS_TEXT_BASE) -e 0 \ + -O u-boot -a $(CONFIG_SYS_TEXT_BASE) -e 0 \ -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \ sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ -d $< $@ @@ -370,6 +394,10 @@ $(obj)u-boot.sha1: $(obj)u-boot.bin $(obj)u-boot.dis: $(obj)u-boot $(OBJDUMP) -d $< > $@ +$(obj)u-boot.ubl: $(obj)u-boot-nand.bin + $(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \ + -e $(CONFIG_SYS_TEXT_BASE) -d $< $@ + GEN_UBOOT = \ UNDEF_SYM=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \ sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ @@ -422,18 +450,8 @@ mmc_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend $(obj)mmc_spl/u-boot-mmc-spl.bin: mmc_spl -$(VERSION_FILE): - @( localvers='$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ; \ - printf '#define PLAIN_VERSION "%s%s"\n' \ - "$(U_BOOT_VERSION)" "$${localvers}" ; \ - printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' \ - "$(U_BOOT_VERSION)" "$${localvers}" ; \ - ) > $@.tmp - @( printf '#define CC_VERSION_STRING "%s"\n' \ - '$(shell $(CC) --version | head -n 1)' )>> $@.tmp - @( printf '#define LD_VERSION_STRING "%s"\n' \ - '$(shell $(LD) -v | head -n 1)' )>> $@.tmp - @cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@ +$(obj)spl/u-boot-spl.bin: depend + $(MAKE) -C spl all $(TIMESTAMP_FILE): @LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"' > $@ @@ -454,15 +472,19 @@ TAG_SUBDIRS = $(SUBDIRS) TAG_SUBDIRS += $(dir $(__LIBS)) TAG_SUBDIRS += include +FIND := find +FINDFLAGS := -L + tags ctags: - ctags -w -o $(obj)ctags `find $(TAG_SUBDIRS) \ + ctags -w -o $(obj)ctags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \ -name '*.[chS]' -print` etags: - etags -a -o $(obj)etags `find $(TAG_SUBDIRS) \ + etags -a -o $(obj)etags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \ -name '*.[chS]' -print` cscope: - find $(TAG_SUBDIRS) -name '*.[chS]' -print > cscope.files + $(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) -name '*.[chS]' -print > \ + cscope.files cscope -b -q -k SYSTEM_MAP = \ @@ -509,20 +531,34 @@ $(obj)lib/asm-offsets.s: $(obj)include/autoconf.mk.dep \ else # !config.mk all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \ $(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \ -$(filter-out tools,$(SUBDIRS)) $(TIMESTAMP_FILE) $(VERSION_FILE) \ +$(filter-out tools,$(SUBDIRS)) $(TIMESTAMP_FILE) \ updater depend dep tags ctags etags cscope $(obj)System.map: @echo "System not configured - see README" >&2 @ exit 1 -tools: +tools: $(VERSION_FILE) $(MAKE) -C $@ all endif # config.mk +$(VERSION_FILE): + @mkdir -p $(dir $(VERSION_FILE)) + @( localvers='$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ; \ + printf '#define PLAIN_VERSION "%s%s"\n' \ + "$(U_BOOT_VERSION)" "$${localvers}" ; \ + printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' \ + "$(U_BOOT_VERSION)" "$${localvers}" ; \ + ) > $@.tmp + @( printf '#define CC_VERSION_STRING "%s"\n' \ + '$(shell $(CC) --version | head -n 1)' )>> $@.tmp + @( printf '#define LD_VERSION_STRING "%s"\n' \ + '$(shell $(LD) -v | head -n 1)' )>> $@.tmp + @cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@ + easylogo env gdb: $(MAKE) -C tools/$@ all MTD_VERSION=${MTD_VERSION} gdbtools: gdb -tools-all: easylogo env gdb +tools-all: easylogo env gdb $(VERSION_FILE) $(MAKE) -C tools HOST_TOOLS_ALL=y .PHONY : CHANGELOG @@ -766,105 +802,6 @@ M5485HFE_config : unconfig ## ARM926EJ-S Systems ######################################################################### -at91sam9260ek_nandflash_config \ -at91sam9260ek_dataflash_cs0_config \ -at91sam9260ek_dataflash_cs1_config \ -at91sam9260ek_config \ -at91sam9g20ek_nandflash_config \ -at91sam9g20ek_dataflash_cs0_config \ -at91sam9g20ek_dataflash_cs1_config \ -at91sam9g20ek_config : unconfig - @mkdir -p $(obj)include - @if [ "$(findstring 9g20,$@)" ] ; then \ - echo "#define CONFIG_AT91SAM9G20EK 1" >>$(obj)include/config.h ; \ - else \ - echo "#define CONFIG_AT91SAM9260EK 1" >>$(obj)include/config.h ; \ - fi; - @if [ "$(findstring _nandflash,$@)" ] ; then \ - echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ - elif [ "$(findstring dataflash_cs0,$@)" ] ; then \ - echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1" >>$(obj)include/config.h ; \ - else \ - echo "#define CONFIG_SYS_USE_DATAFLASH_CS1 1" >>$(obj)include/config.h ; \ - fi; - @$(MKCONFIG) -n $@ -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91 - -at91sam9xeek_nandflash_config \ -at91sam9xeek_dataflash_cs0_config \ -at91sam9xeek_dataflash_cs1_config \ -at91sam9xeek_config : unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _nandflash,$@)" ] ; then \ - echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ - elif [ "$(findstring dataflash_cs0,$@)" ] ; then \ - echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1" >>$(obj)include/config.h ; \ - else \ - echo "#define CONFIG_SYS_USE_DATAFLASH_CS1 1" >>$(obj)include/config.h ; \ - fi; - @$(MKCONFIG) -n $@ -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91 - -at91sam9261ek_nandflash_config \ -at91sam9261ek_dataflash_cs0_config \ -at91sam9261ek_dataflash_cs3_config \ -at91sam9261ek_config \ -at91sam9g10ek_nandflash_config \ -at91sam9g10ek_dataflash_cs0_config \ -at91sam9g10ek_dataflash_cs3_config \ -at91sam9g10ek_config : unconfig - @mkdir -p $(obj)include - @if [ "$(findstring 9g10,$@)" ] ; then \ - echo "#define CONFIG_AT91SAM9G10EK 1" >>$(obj)include/config.h ; \ - else \ - echo "#define CONFIG_AT91SAM9261EK 1" >>$(obj)include/config.h ; \ - fi; - @if [ "$(findstring _nandflash,$@)" ] ; then \ - echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ - elif [ "$(findstring dataflash_cs0,$@)" ] ; then \ - echo "#define CONFIG_SYS_USE_DATAFLASH_CS3 1" >>$(obj)include/config.h ; \ - else \ - echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1" >>$(obj)include/config.h ; \ - fi; - @$(MKCONFIG) -n $@ -a at91sam9261ek arm arm926ejs at91sam9261ek atmel at91 - -at91sam9263ek_norflash_config \ -at91sam9263ek_norflash_boot_config \ -at91sam9263ek_nandflash_config \ -at91sam9263ek_dataflash_config \ -at91sam9263ek_dataflash_cs0_config \ -at91sam9263ek_config : unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _nandflash,$@)" ] ; then \ - echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ - elif [ "$(findstring norflash,$@)" ] ; then \ - echo "#define CONFIG_SYS_USE_NORFLASH 1" >>$(obj)include/config.h ; \ - else \ - echo "#define CONFIG_SYS_USE_DATAFLASH 1" >>$(obj)include/config.h ; \ - fi; - @if [ "$(findstring norflash_boot,$@)" ] ; then \ - echo "#define CONFIG_SYS_USE_BOOT_NORFLASH 1" >>$(obj)include/config.h ; \ - fi; - @$(MKCONFIG) -n $@ -a at91sam9263ek arm arm926ejs at91sam9263ek atmel at91 - -at91sam9rlek_nandflash_config \ -at91sam9rlek_dataflash_config \ -at91sam9rlek_dataflash_cs0_config \ -at91sam9rlek_config : unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _nandflash,$@)" ] ; then \ - echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ - else \ - echo "#define CONFIG_SYS_USE_DATAFLASH 1" >>$(obj)include/config.h ; \ - fi; - @$(MKCONFIG) -n $@ -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91 - -CPU9G20_128M_config \ -CPU9G20_config \ -CPU9260_128M_config \ -CPU9260_config : unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h - @$(MKCONFIG) -n $@ -a cpu9260 arm arm926ejs cpu9260 eukrea at91 - at91sam9m10g45ek_nandflash_config \ at91sam9m10g45ek_dataflash_config \ at91sam9m10g45ek_dataflash_cs0_config \ @@ -982,29 +919,6 @@ SX1_config: unconfig fi; @$(MKCONFIG) -n $@ SX1 arm arm925t sx1 -# TRAB default configuration: 8 MB Flash, 32 MB RAM -trab_config \ -trab_bigram_config \ -trab_bigflash_config \ -trab_old_config: unconfig - @mkdir -p $(obj)include - @mkdir -p $(obj)board/trab - @[ -z "$(findstring _bigram,$@)" ] || \ - { echo "#define CONFIG_FLASH_8MB" >>$(obj)include/config.h ; \ - echo "#define CONFIG_RAM_32MB" >>$(obj)include/config.h ; \ - } - @[ -z "$(findstring _bigflash,$@)" ] || \ - { echo "#define CONFIG_FLASH_16MB" >>$(obj)include/config.h ; \ - echo "#define CONFIG_RAM_16MB" >>$(obj)include/config.h ; \ - echo "CONFIG_SYS_TEXT_BASE = 0x0CF40000" >$(obj)board/trab/config.tmp ; \ - } - @[ -z "$(findstring _old,$@)" ] || \ - { echo "#define CONFIG_FLASH_8MB" >>$(obj)include/config.h ; \ - echo "#define CONFIG_RAM_16MB" >>$(obj)include/config.h ; \ - echo "CONFIG_SYS_TEXT_BASE = 0x0CF40000" >$(obj)board/trab/config.tmp ; \ - } - @$(MKCONFIG) -n $@ -a trab arm arm920t trab - s3c24x0 - tx25_config : unconfig @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk @$(MKCONFIG) $@ arm arm926ejs tx25 karo mx25 @@ -1020,15 +934,6 @@ edb9315a_config: unconfig @$(MKCONFIG) -n $@ -t $(@:_config=) edb93xx arm arm920t edb93xx - ep93xx ######################################################################### -# ARM supplied Versatile development boards -######################################################################### - -versatile_config \ -versatileab_config \ -versatilepb_config : unconfig - @board/armltd/versatile/split_by_variant.sh $@ - -######################################################################### ## XScale Systems ######################################################################### @@ -1085,20 +990,6 @@ smdk6400_config : unconfig @$(MKCONFIG) smdk6400 arm arm1176 smdk6400 samsung s3c64xx @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk -#======================================================================== -# Nios -#======================================================================== - -######################################################################### -## Nios-II -######################################################################### - -# nios2 generic boards -NIOS2_GENERIC = nios2-generic - -$(NIOS2_GENERIC:%=%_config) : unconfig - @$(MKCONFIG) $@ nios2 nios2 nios2-generic altera - ######################################################################### ######################################################################### @@ -1124,17 +1015,19 @@ clean: @rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image} \ $(obj)board/matrix_vision/*/bootscript.img \ $(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \ - $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \ + $(obj)board/voiceblue/eeprom \ $(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds \ $(obj)u-boot.lds \ - $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] + $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \ + $(obj)arch/blackfin/cpu/init.{lds,elf} @rm -f $(obj)include/bmp_logo.h @rm -f $(obj)lib/asm-offsets.s - @rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map} + @rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map} @rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map} @rm -f $(obj)mmc_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,u-boot-spl.bin,u-boot-mmc-spl.bin} @rm -f $(ONENAND_BIN) @rm -f $(obj)onenand_ipl/u-boot.lds + @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map} @rm -f $(TIMESTAMP_FILE) $(VERSION_FILE) @find $(OBJTREE) -type f \ \( -name 'core' -o -name '*.bak' -o -name '*~' \ @@ -1148,9 +1041,10 @@ clobber: clean | xargs -0 rm -f @rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \ $(obj)cscope.* $(obj)*.*~ - @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL) + @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y) @rm -f $(obj)u-boot.kwb @rm -f $(obj)u-boot.imx + @rm -f $(obj)u-boot.ubl @rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes} @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c @rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm @@ -1159,12 +1053,9 @@ clobber: clean @[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f @[ ! -d $(obj)mmc_spl ] || find $(obj)mmc_spl -name "*" -type l -print | xargs rm -f -ifeq ($(OBJTREE),$(SRCTREE)) -mrproper \ -distclean: clobber unconfig -else mrproper \ distclean: clobber unconfig +ifneq ($(OBJTREE),$(SRCTREE)) rm -rf $(obj)* endif @@ -147,7 +147,7 @@ Directory Hierarchy: /cpu CPU specific files /arm720t Files specific to ARM 720 CPUs /arm920t Files specific to ARM 920 CPUs - /at91rm9200 Files specific to Atmel AT91RM9200 CPU + /at91 Files specific to Atmel AT91RM9200 CPU /imx Files specific to Freescale MC9328 i.MX CPUs /s3c24x0 Files specific to Samsung S3C24X0 CPUs /arm925t Files specific to ARM 925 CPUs @@ -180,6 +180,7 @@ Directory Hierarchy: /lib Architecture specific library files /mips Files generic to MIPS architecture /cpu CPU specific files + /mips32 Files specific to MIPS32 CPUs /lib Architecture specific library files /nios2 Files generic to Altera NIOS2 architecture /cpu CPU specific files @@ -382,6 +383,38 @@ The following options need to be configured: 2. The core frequency as calculated above is multiplied by this value. +- MIPS CPU options: + CONFIG_SYS_INIT_SP_OFFSET + + Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack + pointer. This is needed for the temporary stack before + relocation. + + CONFIG_SYS_MIPS_CACHE_MODE + + Cache operation mode for the MIPS CPU. + See also arch/mips/include/asm/mipsregs.h. + Possible values are: + CONF_CM_CACHABLE_NO_WA + CONF_CM_CACHABLE_WA + CONF_CM_UNCACHED + CONF_CM_CACHABLE_NONCOHERENT + CONF_CM_CACHABLE_CE + CONF_CM_CACHABLE_COW + CONF_CM_CACHABLE_CUW + CONF_CM_CACHABLE_ACCELERATED + + CONFIG_SYS_XWAY_EBU_BOOTCFG + + Special option for Lantiq XWAY SoCs for booting from NOR flash. + See also arch/mips/cpu/mips32/start.S. + + CONFIG_XWAY_SWAP_BYTES + + Enable compilation of tools/xway-swap-bytes needed for Lantiq + XWAY SoCs for booting from NOR flash. The U-Boot image needs to + be swapped if a flash programmer is used. + - Linux Kernel Interface: CONFIG_CLOCKS_IN_MHZ @@ -442,6 +475,16 @@ The following options need to be configured: crash. This is needed for buggy hardware (uc101) where no pull down resistor is connected to the signal IDE5V_DD7. + CONFIG_MACH_TYPE [relevant for ARM only][mandatory] + + This setting is mandatory for all boards that have only one + machine type and must be used to specify the machine type + number as it appears in the ARM machine registry + (see http://www.arm.linux.org.uk/developer/machines/). + Only boards that have multiple machine types supported + in a single configuration file and the machine type is + runtime discoverable, do not have to use this setting. + - vxWorks boot parameters: bootvx constructs a valid bootline using the following @@ -460,6 +503,17 @@ The following options need to be configured: Note: If a "bootargs" environment is defined, it will overwride the defaults discussed just above. +- Cache Configuration: + CONFIG_SYS_ICACHE_OFF - Do not enable instruction cache in U-Boot + CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot + CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot + +- Cache Configuration for ARM: + CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache + controller + CONFIG_SYS_PL310_BASE - Physical base address of PL310 + controller register space + - Serial Ports: CONFIG_PL010_SERIAL @@ -716,7 +770,6 @@ The following options need to be configured: CONFIG_CMD_SPI * SPI serial bus support CONFIG_CMD_TFTPSRV * TFTP transfer in server mode CONFIG_CMD_USB * USB support - CONFIG_CMD_VFD * VFD support (TRAB) CONFIG_CMD_CDP * Cisco Discover Protocol support CONFIG_CMD_FSL * Microblaze FSL support @@ -1044,6 +1097,15 @@ The following options need to be configured: enabled with CONFIG_CMD_MMC. The MMC driver also works with the FAT fs. This is enabled with CONFIG_CMD_FAT. + CONFIG_SH_MMCIF + Support for Renesas on-chip MMCIF controller + + CONFIG_SH_MMCIF_ADDR + Define the base address of MMCIF registers + + CONFIG_SH_MMCIF_CLK + Define the clock frequency for MMCIF + - Journaling Flash filesystem support: CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE, CONFIG_JFFS2_NAND_DEV @@ -1694,12 +1756,12 @@ The following options need to be configured: => If you now switch to the new I2C Bus 3 with "i2c dev 3" - u-boot sends First the Commando to the mux@70 to enable - channel 6, and then the Commando to the mux@71 to enable + u-boot first sends the command to the mux@70 to enable + channel 6, and then the command to the mux@71 to enable the channel 4. After that, you can use the "normal" i2c commands as - usual, to communicate with your I2C devices behind + usual to communicate with your I2C devices behind the 2 muxes. This option is actually implemented for the bitbanging @@ -2226,11 +2288,50 @@ FIT uImage format: Adds the MTD partitioning infrastructure from the Linux kernel. Needed for UBI support. +- SPL framework + CONFIG_SPL + Enable building of SPL globally. + + CONFIG_SPL_TEXT_BASE + TEXT_BASE for linking the SPL binary. + + CONFIG_SPL_LDSCRIPT + LDSCRIPT for linking the SPL binary. + + CONFIG_SPL_LIBCOMMON_SUPPORT + Support for common/libcommon.o in SPL binary + + CONFIG_SPL_LIBDISK_SUPPORT + Support for disk/libdisk.o in SPL binary + + CONFIG_SPL_I2C_SUPPORT + Support for drivers/i2c/libi2c.o in SPL binary + + CONFIG_SPL_GPIO_SUPPORT + Support for drivers/gpio/libgpio.o in SPL binary + + CONFIG_SPL_MMC_SUPPORT + Support for drivers/mmc/libmmc.o in SPL binary + + CONFIG_SPL_SERIAL_SUPPORT + Support for drivers/serial/libserial.o in SPL binary + + CONFIG_SPL_SPI_FLASH_SUPPORT + Support for drivers/mtd/spi/libspi_flash.o in SPL binary + + CONFIG_SPL_SPI_SUPPORT + Support for drivers/spi/libspi.o in SPL binary + + CONFIG_SPL_FAT_SUPPORT + Support for fs/fat/libfat.o in SPL binary + + CONFIG_SPL_LIBGENERIC_SUPPORT + Support for lib/libgeneric.o in SPL binary Modem Support: -------------- -[so far only for SMDK2400 and TRAB boards] +[so far only for SMDK2400 boards] - Modem support enable: CONFIG_MODEM_SUPPORT @@ -2495,6 +2596,11 @@ The following definitions that deal with the placement and management of environment data (variable area); in general, we support the following configurations: +- CONFIG_BUILD_ENVCRC: + + Builds up envcrc with the target environment so that external utils + may easily extract it and embed it in final U-Boot images. + - CONFIG_ENV_IS_IN_FLASH: Define this if the environment is in flash memory. @@ -2918,6 +3024,14 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_SRIOn_MEM_SIZE: Size of SRIO port 'n' memory region +- CONFIG_SYS_NDFC_16 + Defined to tell the NDFC that the NAND chip is using a + 16 bit bus. + +- CONFIG_SYS_NDFC_EBC0_CFG + Sets the EBC0_CFG register for the NDFC. If not defined + a default value will be used. + - CONFIG_SPD_EEPROM Get DDR timing information from an I2C EEPROM. Common with pluggable memory modules such as SODIMMs @@ -2930,6 +3044,12 @@ Low Level (hardware related) configuration options: one, specify here. Note that the value must resolve to something your driver can deal with. +- CONFIG_SYS_DDR_RAW_TIMING + Get DDR timing information from other than SPD. Common with + soldered DDR chips onboard without SPD. DDR raw timing + parameters are extracted from datasheet and hard-coded into + header files or board specific files. + - CONFIG_SYS_83XX_DDR_USES_CS0 Only for 83xx systems. If specified, then DDR should be configured using CS0 and CS1 instead of CS2 and CS3. @@ -2983,7 +3103,7 @@ Low Level (hardware related) configuration options: globally (CONFIG_CMD_MEM). - CONFIG_SKIP_LOWLEVEL_INIT - [ARM only] If this variable is defined, then certain + [ARM, MIPS only] If this variable is defined, then certain low level initializations (like setting up the memory controller) are omitted and/or U-Boot does not relocate itself into RAM. @@ -2993,7 +3113,7 @@ Low Level (hardware related) configuration options: other boot loader or by a debugger which performs these initializations itself. -- CONFIG_PRELOADER +- CONFIG_SPL_BUILD Modifies the behaviour of start.S when compiling a loader that is executed before the actual U-Boot. E.g. when compiling a NAND SPL. @@ -3281,6 +3401,15 @@ List of environment variables (most likely not complete): This can be used to load and uncompress arbitrary data. + fdt_high - if set this restricts the maximum address that the + flattened device tree will be copied into upon boot. + If this is set to the special value 0xFFFFFFFF then + the fdt will not be copied at all on boot. For this + to work it must reside in writable memory, have + sufficient padding on the end of it for u-boot to + add the information it needs into it, and the memory + must be accessible by the kernel. + i2cfast - (PPC405GP|PPC405EP only) if set to 'y' configures Linux I2C driver for fast mode (400kHZ). This environment variable is used in @@ -4383,9 +4512,7 @@ Coding Standards: All contributions to U-Boot should conform to the Linux kernel coding style; see the file "Documentation/CodingStyle" and the script -"scripts/Lindent" in your Linux kernel source directory. In sources -originating from U-Boot a style corresponding to "Lindent -pcs" (adding -spaces before parameters to function calls) is actually used. +"scripts/Lindent" in your Linux kernel source directory. Source files originating from a different project (for example the MTD subsystem) are generally exempt from these guidelines and are not @@ -4398,9 +4525,9 @@ in your code. Please also stick to the following formatting rules: - remove any trailing white space -- use TAB characters for indentation, not spaces +- use TAB characters for indentation and vertical alignment, not spaces - make sure NOT to use DOS '\r\n' line feeds -- do not add more than 2 empty lines to source files +- do not add more than 2 consecutive empty lines to source files - do not add trailing empty lines to source files Submissions which do not conform to the standards may be returned @@ -4434,14 +4561,14 @@ it: * For major contributions, your entry to the CREDITS file * When you add support for a new board, don't forget to add this - board to the MAKEALL script, too. + board to the MAINTAINERS file, too. * If your patch adds new configuration options, don't forget to document these in the README file. * The patch itself. If you are using git (which is *strongly* recommended) you can easily generate the patch using the - "git-format-patch". If you then use "git-send-email" to send it to + "git format-patch". If you then use "git send-email" to send it to the U-Boot mailing list, you will avoid most of the common problems with some other mail clients. diff --git a/arch/arm/config.mk b/arch/arm/config.mk index ec1b420..9b4e581 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -56,10 +56,24 @@ PLATFORM_CPPFLAGS += $(call cc-option,\ # For EABI, make sure to provide raise() ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) -# This file is parsed several times; make sure to add only once. -ifeq (,$(findstring arch/arm/lib/eabi_compat.o,$(PLATFORM_LIBS))) -PLATFORM_LIBS += $(OBJTREE)/arch/arm/lib/eabi_compat.o +# This file is parsed many times, so the string may get added multiple +# times. Also, the prefix needs to be different based on whether +# CONFIG_SPL_BUILD is defined or not. 'filter-out' the existing entry +# before adding the correct one. +ifdef CONFIG_SPL_BUILD +PLATFORM_LIBS := $(SPLTREE)/arch/arm/lib/eabi_compat.o \ + $(filter-out %/arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS)) +else +PLATFORM_LIBS := $(OBJTREE)/arch/arm/lib/eabi_compat.o \ + $(filter-out %/arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS)) +endif endif + +ifdef CONFIG_SYS_LDSCRIPT +# need to strip off double quotes +LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT)) +else +LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds endif # needed for relocation diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 4ebf38d..248431b 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -23,6 +23,7 @@ #include <common.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> #include <asm/io.h> static u32 mx31_decode_pll(u32 reg, u32 infreq) @@ -60,7 +61,7 @@ static u32 mx31_get_mcu_main_clk(void) return mx31_get_mpl_dpdgck_clk(); } -u32 mx31_get_ipg_clk(void) +static u32 mx31_get_ipg_clk(void) { u32 freq = mx31_get_mcu_main_clk(); u32 pdr0 = __REG(CCM_PDR0); @@ -78,6 +79,24 @@ void mx31_dump_clocks(void) printf("ipg clock : %dHz\n", mx31_get_ipg_clk()); } +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return mx31_get_mcu_main_clk(); + case MXC_IPG_CLK: + case MXC_CSPI_CLK: + case MXC_UART_CLK: + return mx31_get_ipg_clk(); + } + return -1; +} + +u32 imx_get_uartclk(void) +{ + return mxc_get_clock(MXC_UART_CLK); +} + void mx31_gpio_mux(unsigned long mode) { unsigned long reg, shift, tmp; diff --git a/arch/arm/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c index c4bc3b3..c05a39d 100644 --- a/arch/arm/cpu/arm1136/mx31/timer.c +++ b/arch/arm/cpu/arm1136/mx31/timer.c @@ -106,18 +106,6 @@ int timer_init (void) return 0; } -void reset_timer_masked (void) -{ - /* reset time */ - gd->lastinc = GPTCNT; /* capture current incrementer value time */ - gd->tbl = 0; /* start "advancing" time stamp from 0 */ -} - -void reset_timer(void) -{ - reset_timer_masked(); -} - unsigned long long get_ticks (void) { ulong now = GPTCNT; /* current tick value */ @@ -147,11 +135,6 @@ ulong get_timer (ulong base) return get_timer_masked () - base; } -void set_timer (ulong t) -{ - gd->tbl = time_to_tick(t); -} - /* delay x useconds AND preserve advance timestamp value */ void __udelay (unsigned long usec) { diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile index 20f36e3..284cdc5 100644 --- a/arch/arm/cpu/arm1136/mx35/Makefile +++ b/arch/arm/cpu/arm1136/mx35/Makefile @@ -50,14 +50,3 @@ include $(SRCTREE)/rules.mk sinclude $(obj).depend ######################################################################### - -$(TOPDIR)/include/asm/arch/asm-offsets.h: $(TOPDIR)/include/autoconf.mk.dep \ - ./asm-offsets.s - @echo Generating $@ - $(TOPDIR)/tools/scripts/make-asm-offsets ./asm-offsets.s $@ - -asm-offsets.s: $(TOPDIR)/include/autoconf.mk.dep \ - ./asm-offsets.c - $(CC) -DDO_DEPS_ONLY \ - $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \ - -o $@ ./asm-offsets.c -c -S diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c index db1e2c9..80c0675 100644 --- a/arch/arm/cpu/arm1136/mx35/timer.c +++ b/arch/arm/cpu/arm1136/mx35/timer.c @@ -73,11 +73,6 @@ inline ulong get_timer_masked(void) return val; } -void reset_timer(void) -{ - reset_timer_masked(); -} - ulong get_timer(ulong base) { ulong tmp; @@ -92,10 +87,6 @@ ulong get_timer(ulong base) return (tmp / 1000) - base; } -void set_timer(ulong t) -{ -} - /* * delay x useconds AND preserve advance timstamp value * GPTCNT is now supposed to tick 1 by 1 us. diff --git a/arch/arm/cpu/arm1136/omap24xx/timer.c b/arch/arm/cpu/arm1136/omap24xx/timer.c index 228ceba..73bf4a7 100644 --- a/arch/arm/cpu/arm1136/omap24xx/timer.c +++ b/arch/arm/cpu/arm1136/omap24xx/timer.c @@ -41,6 +41,13 @@ DECLARE_GLOBAL_DATA_PTR; +static void reset_timer_masked (void) +{ + /* reset time */ + gd->lastinc = READ_TIMER; /* capture current incrementer value time */ + gd->tbl = 0; /* start "advancing" time stamp from 0 */ +} + int timer_init (void) { int32_t val; @@ -57,21 +64,11 @@ int timer_init (void) /* * timer without interrupts */ -void reset_timer (void) -{ - reset_timer_masked (); -} - ulong get_timer (ulong base) { return get_timer_masked () - base; } -void set_timer (ulong t) -{ - gd->tbl = t; -} - /* delay x useconds AND preserve advance timestamp value */ void __udelay (unsigned long usec) { @@ -95,13 +92,6 @@ void __udelay (unsigned long usec) /*NOP*/; } -void reset_timer_masked (void) -{ - /* reset time */ - gd->lastinc = READ_TIMER; /* capture current incrementer value time */ - gd->tbl = 0; /* start "advancing" time stamp from 0 */ -} - ulong get_timer_masked (void) { ulong now = READ_TIMER; /* current tick value */ diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 3c5f3ef..f5a1134 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -33,7 +33,7 @@ #include <version.h> .globl _start _start: b reset -#ifdef CONFIG_PRELOADER +#ifdef CONFIG_SPL_BUILD ldr pc, _hang ldr pc, _hang ldr pc, _hang @@ -68,7 +68,7 @@ _not_used: .word not_used _irq: .word irq _fiq: .word fiq _pad: .word 0x12345678 /* now 16*4=64 */ -#endif /* CONFIG_PRELOADER */ +#endif /* CONFIG_SPL_BUILD */ .global _end_vect _end_vect: @@ -201,7 +201,7 @@ copy_loop: cmp r0, r2 /* until source end address [r2] */ blo copy_loop -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* * fix .rel.dyn relocations */ @@ -243,7 +243,7 @@ fixnext: #endif clear_bss: -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD ldr r0, _bss_start_ofs ldr r1, _bss_end_ofs mov r4, r6 /* reloc addr */ @@ -255,7 +255,7 @@ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 bne clbss_l -#endif /* #ifndef CONFIG_PRELOADER */ +#endif /* #ifndef CONFIG_SPL_BUILD */ /* * We are done. Do not return, instead branch to second part of board @@ -329,7 +329,7 @@ cpu_init_crit: mov pc, lr /* back to my caller */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* ************************************************************************* * @@ -436,17 +436,17 @@ cpu_init_crit: .macro get_fiq_stack @ setup FIQ stack ldr sp, FIQ_STACK_START .endm -#endif /* CONFIG_PRELOADER */ +#endif /* CONFIG_SPL_BUILD */ /* * exception handlers */ -#ifdef CONFIG_PRELOADER +#ifdef CONFIG_SPL_BUILD .align 5 do_hang: ldr sp, _TEXT_BASE /* use 32 words about stack */ bl hang /* hang and never return */ -#else /* !CONFIG_PRELOADER */ +#else /* !CONFIG_SPL_BUILD */ .align 5 undefined_instruction: get_bad_stack @@ -512,11 +512,11 @@ fiq: .align 5 .global arm1136_cache_flush arm1136_cache_flush: -#if !defined(CONFIG_SYS_NO_ICACHE) +#if !defined(CONFIG_SYS_ICACHE_OFF) mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache #endif -#if !defined(CONFIG_SYS_NO_DCACHE) +#if !defined(CONFIG_SYS_DCACHE_OFF) mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache #endif mov pc, lr @ back to caller -#endif /* CONFIG_PRELOADER */ +#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm1176/s3c64xx/timer.c b/arch/arm/cpu/arm1176/s3c64xx/timer.c index 9768319..f16a37b 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/timer.c +++ b/arch/arm/cpu/arm1176/s3c64xx/timer.c @@ -135,18 +135,6 @@ ulong get_tbclk(void) return (ulong)(timer_load_val / 100); } -void reset_timer_masked(void) -{ - /* reset time */ - lastdec = read_timer(); - timestamp = 0; -} - -void reset_timer(void) -{ - reset_timer_masked(); -} - ulong get_timer_masked(void) { unsigned long long res = get_ticks(); @@ -159,11 +147,6 @@ ulong get_timer(ulong base) return get_timer_masked() - base; } -void set_timer(ulong t) -{ - timestamp = t * (timer_load_val / (100 * CONFIG_SYS_HZ)); -} - void __udelay(unsigned long usec) { unsigned long long tmp; diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index b095f22..0aa613d 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -263,7 +263,7 @@ copy_loop: cmp r0, r2 /* until source end address [r2] */ blo copy_loop -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* * fix .rel.dyn relocations */ @@ -343,7 +343,7 @@ skip_hw_init: #endif clear_bss: -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD ldr r0, _bss_start_ofs ldr r1, _bss_end_ofs mov r4, r6 /* reloc addr */ diff --git a/arch/arm/cpu/arm1176/tnetv107x/timer.c b/arch/arm/cpu/arm1176/tnetv107x/timer.c index a7a400d..b3123c5 100644 --- a/arch/arm/cpu/arm1176/tnetv107x/timer.c +++ b/arch/arm/cpu/arm1176/tnetv107x/timer.c @@ -60,15 +60,6 @@ int timer_init(void) return 0; } -void reset_timer(void) -{ - lastinc = timestamp = 0; - - __raw_writel(0, ®s->tcr); - __raw_writel(0, ®s->tim34); - __raw_writel(2 << 22, ®s->tcr); -} - static ulong get_timer_raw(void) { ulong now = __raw_readl(®s->tim34); @@ -88,11 +79,6 @@ ulong get_timer(ulong base) return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base; } -void set_timer(ulong t) -{ - timestamp = t; -} - unsigned long long get_ticks(void) { return get_timer(0); diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index eb8d425..fa9c5a2 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -209,21 +209,11 @@ int timer_init (void) #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292) -void reset_timer (void) -{ - reset_timer_masked (); -} - ulong get_timer (ulong base) { return get_timer_masked () - base; } -void set_timer (ulong t) -{ - timestamp = t; -} - void __udelay (unsigned long usec) { ulong tmo; @@ -243,13 +233,6 @@ void __udelay (unsigned long usec) #endif } -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER; - timestamp = 0; -} - ulong get_timer_masked (void) { ulong now = READ_TIMER; diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c index b4dc4a6..bd6a5b1 100644 --- a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c +++ b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c @@ -148,7 +148,7 @@ unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer) /* Command 16 to read aBlocks from the MMC/SD - caed */ unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF}; - /* The addres on the MMC/SD-card is in bytes, + /* The address on the MMC/SD-card is in bytes, addr is transformed from blocks to bytes and the result is placed into the command */ @@ -173,7 +173,7 @@ unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer) /* Command 24 to write a block to the MMC/SD - card */ unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF}; - /* The addres on the MMC/SD-card is in bytes, + /* The address on the MMC/SD-card is in bytes, addr is transformed from blocks to bytes and the result is placed into the command */ diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index e774c3f..ecb92ef 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -178,7 +178,7 @@ copy_loop: cmp r0, r2 /* until source end address [r2] */ blo copy_loop -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* * fix .rel.dyn relocations */ @@ -220,7 +220,7 @@ fixnext: #endif clear_bss: -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD ldr r0, _bss_start_ofs ldr r1, _bss_end_ofs mov r4, r6 /* reloc addr */ @@ -274,7 +274,7 @@ _dynsym_start_ofs: #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) -/* Interupt-Controller base addresses */ +/* Interrupt-Controller base addresses */ INTMR1: .word 0x80000280 @ 32 bit size INTMR2: .word 0x80001280 @ 16 bit size INTMR3: .word 0x80002280 @ 8 bit size diff --git a/arch/arm/cpu/arm920t/a320/timer.c b/arch/arm/cpu/arm920t/a320/timer.c index 95cb8fd..443d31d 100644 --- a/arch/arm/cpu/arm920t/a320/timer.c +++ b/arch/arm/cpu/arm920t/a320/timer.c @@ -81,12 +81,6 @@ void reset_timer_masked(void) debug("%s(): lastdec = %lx\n", __func__, lastdec); } -void reset_timer(void) -{ - debug("%s()\n", __func__); - reset_timer_masked(); -} - /* * return timer ticks */ @@ -132,12 +126,6 @@ ulong get_timer(ulong base) return get_timer_masked() - base; } -void set_timer(ulong t) -{ - debug("%s(%lx)\n", __func__, t); - timestamp = t; -} - /* delay x useconds AND preserve advance timestamp value */ void __udelay(unsigned long usec) { diff --git a/arch/arm/cpu/arm920t/at91/Makefile b/arch/arm/cpu/arm920t/at91/Makefile index 5c71b77..309bcd6 100644 --- a/arch/arm/cpu/arm920t/at91/Makefile +++ b/arch/arm/cpu/arm920t/at91/Makefile @@ -28,6 +28,9 @@ LIB = $(obj)lib$(SOC).o SOBJS += lowlevel_init.o COBJS += reset.o COBJS += timer.o +COBJS += clock.o +COBJS += cpu.o +COBJS += at91rm9200_devices.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c b/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c new file mode 100644 index 0000000..f610a1e --- /dev/null +++ b/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c @@ -0,0 +1,85 @@ +/* + * [partely copied from arch/arm/cpu/arm926ejs/at91/arm9260_devices.c] + * + * (C) Copyright 2011 + * Andreas Bießmann <andreas.devel@googlemail.com> + * + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> + +/* + * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all + * peripheral pins. Good to have if hardware is soldered optionally + * or in case of SPI no slave is selected. Avoid lines to float + * needlessly. Use a short local PUP define. + * + * Due to errata "TXD floats when CTS is inactive" pullups are always + * on for TXD pins. + */ +#ifdef CONFIG_AT91_GPIO_PULLUP +# define PUP CONFIG_AT91_GPIO_PULLUP +#else +# define PUP 0 +#endif + +void at91_serial0_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 18, PUP); /* RXD0 */ + writel(1 << ATMEL_ID_USART0, &pmc->pcer); +} + +void at91_serial1_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTB, 20, PUP); /* RXD1 */ + at91_set_a_periph(AT91_PIO_PORTB, 21, 1); /* TXD1 */ + writel(1 << ATMEL_ID_USART1, &pmc->pcer); +} + +void at91_serial2_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* RXD2 */ + at91_set_a_periph(AT91_PIO_PORTA, 23, 1); /* TXD2 */ + writel(1 << ATMEL_ID_USART2, &pmc->pcer); +} + + +void at91_seriald_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTA, 30, PUP); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTA, 31, 1); /* DTXD */ + /* writing SYS to PCER has no effect on AT91RM9200 */ +} + diff --git a/arch/arm/cpu/arm920t/at91/clock.c b/arch/arm/cpu/arm920t/at91/clock.c new file mode 100644 index 0000000..02318b3 --- /dev/null +++ b/arch/arm/cpu/arm920t/at91/clock.c @@ -0,0 +1,160 @@ +/* + * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c] + * + * Copyright (C) 2011 Andreas Bießmann + * Copyright (C) 2005 David Brownell + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> + +#if !defined(CONFIG_AT91FAMILY) +# error You need to define CONFIG_AT91FAMILY in your board config! +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static unsigned long at91_css_to_rate(unsigned long css) +{ + switch (css) { + case AT91_PMC_MCKR_CSS_SLOW: + return CONFIG_SYS_AT91_SLOW_CLOCK; + case AT91_PMC_MCKR_CSS_MAIN: + return gd->main_clk_rate_hz; + case AT91_PMC_MCKR_CSS_PLLA: + return gd->plla_rate_hz; + case AT91_PMC_MCKR_CSS_PLLB: + return gd->pllb_rate_hz; + } + + return 0; +} + +#ifdef CONFIG_USB_ATMEL +static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) +{ + unsigned i, div = 0, mul = 0, diff = 1 << 30; + unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; + + /* PLL output max 240 MHz (or 180 MHz per errata) */ + if (out_freq > 240000000) + goto fail; + + for (i = 1; i < 256; i++) { + int diff1; + unsigned input, mul1; + + /* + * PLL input between 1MHz and 32MHz per spec, but lower + * frequences seem necessary in some cases so allow 100K. + * Warning: some newer products need 2MHz min. + */ + input = main_freq / i; + if (input < 100000) + continue; + if (input > 32000000) + continue; + + mul1 = out_freq / input; + if (mul1 > 2048) + continue; + if (mul1 < 2) + goto fail; + + diff1 = out_freq - input * mul1; + if (diff1 < 0) + diff1 = -diff1; + if (diff > diff1) { + diff = diff1; + div = i; + mul = mul1; + if (diff == 0) + break; + } + } + if (i == 256 && diff > (out_freq >> 5)) + goto fail; + return ret | ((mul - 1) << 16) | div; +fail: + return 0; +} +#endif + +static u32 at91_pll_rate(u32 freq, u32 reg) +{ + unsigned mul, div; + + div = reg & 0xff; + mul = (reg >> 16) & 0x7ff; + if (div && mul) { + freq /= div; + freq *= mul + 1; + } else + freq = 0; + + return freq; +} + + +int at91_clock_init(unsigned long main_clock) +{ + unsigned freq, mckr; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; +#ifndef CONFIG_SYS_AT91_MAIN_CLOCK + unsigned tmp; + /* + * When the bootloader initialized the main oscillator correctly, + * there's no problem using the cycle counter. But if it didn't, + * or when using oscillator bypass mode, we must be told the speed + * of the main clock. + */ + if (!main_clock) { + do { + tmp = readl(&pmc->mcfr); + } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); + tmp &= AT91_PMC_MCFR_MAINF_MASK; + main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); + } +#endif + gd->main_clk_rate_hz = main_clock; + + /* report if PLLA is more than mildly overclocked */ + gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); + +#ifdef CONFIG_USB_ATMEL + /* + * USB clock init: choose 48 MHz PLLB value, + * disable 48MHz clock during usb peripheral suspend. + * + * REVISIT: assumes MCK doesn't derive from PLLB! + */ + gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | + AT91_PMC_PLLBR_USBDIV_2; + gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init); +#endif + + /* + * MCK and CPU derive from one of those primary clocks. + * For now, assume this parentage won't change. + */ + mckr = readl(&pmc->mckr); + gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); + freq = gd->mck_rate_hz; + + freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ + /* mdiv */ + gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); + gd->cpu_clk_rate_hz = freq; + + return 0; +} + diff --git a/arch/arm/cpu/arm920t/at91/cpu.c b/arch/arm/cpu/arm920t/at91/cpu.c new file mode 100644 index 0000000..74a1158 --- /dev/null +++ b/arch/arm/cpu/arm920t/at91/cpu.c @@ -0,0 +1,43 @@ +/* + * [origin: arch/arm/cpu/arm926ejs/at91/cpu.c] + * + * (C) Copyright 2011 + * Andreas Bießmann, andreas.devel@googlemail.com + * (C) Copyright 2010 + * Reinhard Meyer, reinhard.meyer@emk-elektronik.de + * (C) Copyright 2009 + * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/clk.h> + +#ifndef CONFIG_SYS_AT91_MAIN_CLOCK +#define CONFIG_SYS_AT91_MAIN_CLOCK 0 +#endif + +int arch_cpu_init(void) +{ + return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); +} + diff --git a/arch/arm/cpu/arm920t/at91/reset.c b/arch/arm/cpu/arm920t/at91/reset.c index 51043ec..cd9c9f3 100644 --- a/arch/arm/cpu/arm920t/at91/reset.c +++ b/arch/arm/cpu/arm920t/at91/reset.c @@ -42,11 +42,7 @@ void __attribute__((weak)) board_reset(void) void reset_cpu(ulong ignored) { - at91_st_t *st = (at91_st_t *) AT91_ST_BASE; -#if defined(CONFIG_AT91RM9200_USART) - /*shutdown the console to avoid strange chars during reset */ - serial_exit(); -#endif + at91_st_t *st = (at91_st_t *) ATMEL_BASE_ST; board_reset(); diff --git a/arch/arm/cpu/arm920t/at91/timer.c b/arch/arm/cpu/arm920t/at91/timer.c index d9a024f..91607b5 100644 --- a/arch/arm/cpu/arm920t/at91/timer.c +++ b/arch/arm/cpu/arm920t/at91/timer.c @@ -32,7 +32,7 @@ #include <common.h> -#include <asm/arch/io.h> +#include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_tc.h> #include <asm/arch/at91_pmc.h> @@ -44,11 +44,11 @@ DECLARE_GLOBAL_DATA_PTR; int timer_init(void) { - at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; /* enables TC1.0 clock */ - writel(1 << AT91_ID_TC0, &pmc->pcer); /* enable clock */ + writel(1 << ATMEL_ID_TC0, &pmc->pcer); /* enable clock */ writel(0, &tc->bcr); writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE | @@ -59,7 +59,7 @@ int timer_init(void) when the value in TC_RC is reached */ writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr); - writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interupts */ + writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */ writel(TIMER_LOAD_VAL, &tc->tc[0].rc); writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr); @@ -72,38 +72,19 @@ int timer_init(void) /* * timer without interrupts */ - -void reset_timer(void) -{ - reset_timer_masked(); -} - ulong get_timer(ulong base) { return get_timer_masked() - base; } -void set_timer(ulong t) -{ - gd->tbl = t; -} - void __udelay(unsigned long usec) { udelay_masked(usec); } -void reset_timer_masked(void) -{ - /* reset time */ - at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE; - gd->lastinc = readl(&tc->tc[0].cv) & 0x0000ffff; - gd->tbl = 0; -} - ulong get_timer_raw(void) { - at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE; + at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC; u32 now; now = readl(&tc->tc[0].cv) & 0x0000ffff; diff --git a/arch/arm/cpu/arm920t/at91rm9200/bcm5221.c b/arch/arm/cpu/arm920t/at91rm9200/bcm5221.c deleted file mode 100644 index 8de3cba..0000000 --- a/arch/arm/cpu/arm920t/at91rm9200/bcm5221.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Broadcom BCM5221 Ethernet PHY - * - * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de> - * Anders Larsen <alarsen@rea.de> - * - * (C) Copyright 2003 - * Author : Hamid Ikdoumi (Atmel) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <at91rm9200_net.h> -#include <net.h> -#ifdef CONFIG_DRIVER_ETHER - -#include <bcm5221.h> - -#if defined(CONFIG_CMD_NET) - -/* - * Name: - * bcm5221_IsPhyConnected - * Description: - * Reads the 2 PHY ID registers - * Arguments: - * p_mac - pointer to AT91S_EMAC struct - * Return value: - * TRUE - if id read successfully - * FALSE- if error - */ -unsigned int bcm5221_IsPhyConnected (AT91PS_EMAC p_mac) -{ - unsigned short Id1, Id2; - - at91rm9200_EmacEnableMDIO (p_mac); - at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID1, &Id1); - at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID2, &Id2); - at91rm9200_EmacDisableMDIO (p_mac); - - if ((Id1 == (BCM5221_PHYID1_OUI >> 6)) && - ((Id2 >> 10) == (BCM5221_PHYID1_OUI & BCM5221_LSB_MASK))) - return TRUE; - - return FALSE; -} - -/* - * Name: - * bcm5221_GetLinkSpeed - * Description: - * Link parallel detection status of MAC is checked and set in the - * MAC configuration registers - * Arguments: - * p_mac - pointer to MAC - * Return value: - * TRUE - if link status set succesfully - * FALSE - if link status not set - */ -unsigned char bcm5221_GetLinkSpeed (AT91PS_EMAC p_mac) -{ - unsigned short stat1, stat2; - - if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &stat1)) - return FALSE; - - if (!(stat1 & BCM5221_LINK_STATUS)) /* link status up? */ - return FALSE; - - if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ACSR, &stat2)) - return FALSE; - - if ((stat1 & BCM5221_100BASE_TX_FD) && (stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) { - /*set Emac for 100BaseTX and Full Duplex */ - p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; - return TRUE; - } - - if ((stat1 & BCM5221_10BASE_T_FD) && !(stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) { - /*set MII for 10BaseT and Full Duplex */ - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_FD; - return TRUE; - } - - if ((stat1 & BCM5221_100BASE_TX_HD) && (stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) { - /*set MII for 100BaseTX and Half Duplex */ - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_SPD; - return TRUE; - } - - if ((stat1 & BCM5221_10BASE_T_HD) && !(stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) { - /*set MII for 10BaseT and Half Duplex */ - p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); - return TRUE; - } - return FALSE; -} - - -/* - * Name: - * bcm5221_InitPhy - * Description: - * MAC starts checking its link by using parallel detection and - * Autonegotiation and the same is set in the MAC configuration registers - * Arguments: - * p_mac - pointer to struct AT91S_EMAC - * Return value: - * TRUE - if link status set succesfully - * FALSE - if link status not set - */ -unsigned char bcm5221_InitPhy (AT91PS_EMAC p_mac) -{ - unsigned char ret = TRUE; - unsigned short IntValue; - - at91rm9200_EmacEnableMDIO (p_mac); - - if (!bcm5221_GetLinkSpeed (p_mac)) { - /* Try another time */ - ret = bcm5221_GetLinkSpeed (p_mac); - } - - /* Disable PHY Interrupts */ - at91rm9200_EmacReadPhy (p_mac, BCM5221_INTR, &IntValue); - /* clear FDX LED and INTR Enable */ - IntValue &= ~(BCM5221_FDX_LED | BCM5221_INTR_ENABLE); - /* set FDX, SPD, Link, INTR masks */ - IntValue |= (BCM5221_FDX_MASK | BCM5221_SPD_MASK | - BCM5221_LINK_MASK | BCM5221_INTR_MASK); - at91rm9200_EmacWritePhy (p_mac, BCM5221_INTR, &IntValue); - at91rm9200_EmacDisableMDIO (p_mac); - - return (ret); -} - - -/* - * Name: - * bcm5221_AutoNegotiate - * Description: - * MAC Autonegotiates with the partner status of same is set in the - * MAC configuration registers - * Arguments: - * dev - pointer to struct net_device - * Return value: - * TRUE - if link status set successfully - * FALSE - if link status not set - */ -unsigned char bcm5221_AutoNegotiate (AT91PS_EMAC p_mac, int *status) -{ - unsigned short value; - unsigned short PhyAnar; - unsigned short PhyAnalpar; - - /* Set bcm5221 control register */ - if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value)) - return FALSE; - value &= ~BCM5221_AUTONEG; /* remove autonegotiation enable */ - value |= BCM5221_ISOLATE; /* Electrically isolate PHY */ - if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value)) - return FALSE; - - /* Set the Auto_negotiation Advertisement Register */ - /* MII advertising for 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */ - PhyAnar = BCM5221_TX_FDX | BCM5221_TX_HDX | - BCM5221_10_FDX | BCM5221_10_HDX | BCM5221_AN_IEEE_802_3; - if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_ANAR, &PhyAnar)) - return FALSE; - - /* Read the Control Register */ - if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value)) - return FALSE; - - value |= BCM5221_SPEED_SELECT | BCM5221_AUTONEG | BCM5221_DUPLEX_MODE; - if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value)) - return FALSE; - /* Restart Auto_negotiation */ - value |= BCM5221_RESTART_AUTONEG; - value &= ~BCM5221_ISOLATE; - if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value)) - return FALSE; - - /*check AutoNegotiate complete */ - udelay (10000); - at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &value); - if (!(value & BCM5221_AUTONEG_COMP)) - return FALSE; - - /* Get the AutoNeg Link partner base page */ - if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ANLPAR, &PhyAnalpar)) - return FALSE; - - if ((PhyAnar & BCM5221_TX_FDX) && (PhyAnalpar & BCM5221_TX_FDX)) { - /*set MII for 100BaseTX and Full Duplex */ - p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; - return TRUE; - } - - if ((PhyAnar & BCM5221_10_FDX) && (PhyAnalpar & BCM5221_10_FDX)) { - /*set MII for 10BaseT and Full Duplex */ - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_FD; - return TRUE; - } - return FALSE; -} - -#endif - -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/arch/arm/cpu/arm920t/at91rm9200/dm9161.c b/arch/arm/cpu/arm920t/at91rm9200/dm9161.c deleted file mode 100644 index 6d4384f..0000000 --- a/arch/arm/cpu/arm920t/at91rm9200/dm9161.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - * (C) Copyright 2003 - * Author : Hamid Ikdoumi (Atmel) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <at91rm9200_net.h> -#include <net.h> -#ifdef CONFIG_DRIVER_ETHER -#include <dm9161.h> - -#if defined(CONFIG_CMD_NET) - -/* - * Name: - * dm9161_IsPhyConnected - * Description: - * Reads the 2 PHY ID registers - * Arguments: - * p_mac - pointer to AT91S_EMAC struct - * Return value: - * TRUE - if id read successfully - * FALSE- if error - */ -unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac) -{ - unsigned short Id1, Id2; - - at91rm9200_EmacEnableMDIO (p_mac); - at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1); - at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2); - at91rm9200_EmacDisableMDIO (p_mac); - - if ((Id1 == (DM9161_PHYID1_OUI >> 6)) && - ((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK))) - return TRUE; - - return FALSE; -} - -/* - * Name: - * dm9161_GetLinkSpeed - * Description: - * Link parallel detection status of MAC is checked and set in the - * MAC configuration registers - * Arguments: - * p_mac - pointer to MAC - * Return value: - * TRUE - if link status set succesfully - * FALSE - if link status not set - */ -UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac) -{ - unsigned short stat1, stat2; - - if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1)) - return FALSE; - - if (!(stat1 & DM9161_LINK_STATUS)) /* link status up? */ - return FALSE; - - if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2)) - return FALSE; - - if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) { - /*set Emac for 100BaseTX and Full Duplex */ - p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; - return TRUE; - } - - if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) { - /*set MII for 10BaseT and Full Duplex */ - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_FD; - return TRUE; - } - - if ((stat1 & DM9161_100BASE_TX_HD) && (stat2 & DM9161_100HDX)) { - /*set MII for 100BaseTX and Half Duplex */ - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_SPD; - return TRUE; - } - - if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) { - /*set MII for 10BaseT and Half Duplex */ - p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); - return TRUE; - } - return FALSE; -} - - -/* - * Name: - * dm9161_InitPhy - * Description: - * MAC starts checking its link by using parallel detection and - * Autonegotiation and the same is set in the MAC configuration registers - * Arguments: - * p_mac - pointer to struct AT91S_EMAC - * Return value: - * TRUE - if link status set succesfully - * FALSE - if link status not set - */ -UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac) -{ - UCHAR ret = TRUE; - unsigned short IntValue; - - at91rm9200_EmacEnableMDIO (p_mac); - - if (!dm9161_GetLinkSpeed (p_mac)) { - /* Try another time */ - ret = dm9161_GetLinkSpeed (p_mac); - } - - /* Disable PHY Interrupts */ - at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue); - /* set FDX, SPD, Link, INTR masks */ - IntValue |= (DM9161_FDX_MASK | DM9161_SPD_MASK | - DM9161_LINK_MASK | DM9161_INTR_MASK); - at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue); - at91rm9200_EmacDisableMDIO (p_mac); - - return (ret); -} - - -/* - * Name: - * dm9161_AutoNegotiate - * Description: - * MAC Autonegotiates with the partner status of same is set in the - * MAC configuration registers - * Arguments: - * dev - pointer to struct net_device - * Return value: - * TRUE - if link status set successfully - * FALSE - if link status not set - */ -UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status) -{ - unsigned short value; - unsigned short PhyAnar; - unsigned short PhyAnalpar; - - /* Set dm9161 control register */ - if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value)) - return FALSE; - value &= ~DM9161_AUTONEG; /* remove autonegotiation enable */ - value |= DM9161_ISOLATE; /* Electrically isolate PHY */ - if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value)) - return FALSE; - - /* Set the Auto_negotiation Advertisement Register */ - /* MII advertising for Next page, 100BaseTxFD and HD, */ - /* 10BaseTFD and HD, IEEE 802.3 */ - PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX | - DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3; - if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar)) - return FALSE; - - /* Read the Control Register */ - if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value)) - return FALSE; - - value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE; - if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value)) - return FALSE; - /* Restart Auto_negotiation */ - value |= DM9161_RESTART_AUTONEG; - value &= ~DM9161_ISOLATE; - if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value)) - return FALSE; - - /*check AutoNegotiate complete */ - udelay (10000); - at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value); - if (!(value & DM9161_AUTONEG_COMP)) - return FALSE; - - /* Get the AutoNeg Link partner base page */ - if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar)) - return FALSE; - - if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) { - /*set MII for 100BaseTX and Full Duplex */ - p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; - return TRUE; - } - - if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) { - /*set MII for 10BaseT and Full Duplex */ - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_FD; - return TRUE; - } - return FALSE; -} - -#endif - -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/arch/arm/cpu/arm920t/at91rm9200/ether.c b/arch/arm/cpu/arm920t/at91rm9200/ether.c deleted file mode 100644 index d7135c5..0000000 --- a/arch/arm/cpu/arm920t/at91rm9200/ether.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * (C) Copyright 2003 - * Author : Hamid Ikdoumi (Atmel) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <at91rm9200_net.h> -#include <net.h> -#include <miiphy.h> -#include <asm/mach-types.h> - -/* ----- Ethernet Buffer definitions ----- */ - -typedef struct { - unsigned long addr, size; -} rbf_t; - -#define RBF_ADDR 0xfffffffc -#define RBF_OWNER (1<<0) -#define RBF_WRAP (1<<1) -#define RBF_BROADCAST (1<<31) -#define RBF_MULTICAST (1<<30) -#define RBF_UNICAST (1<<29) -#define RBF_EXTERNAL (1<<28) -#define RBF_UNKNOWN (1<<27) -#define RBF_SIZE 0x07ff -#define RBF_LOCAL4 (1<<26) -#define RBF_LOCAL3 (1<<25) -#define RBF_LOCAL2 (1<<24) -#define RBF_LOCAL1 (1<<23) - -#define RBF_FRAMEMAX 64 -#define RBF_FRAMELEN 0x600 - -#ifdef CONFIG_DRIVER_ETHER - -#if defined(CONFIG_CMD_NET) - -/* alignment as per Errata #11 (64 bytes) is insufficient! */ -rbf_t rbfdt[RBF_FRAMEMAX] __attribute__((aligned(512))); -rbf_t *rbfp; - -unsigned char rbf_framebuf[RBF_FRAMEMAX][RBF_FRAMELEN] - __attribute__((aligned(4))); - -/* structure to interface the PHY */ -AT91S_PhyOps PhyOps; - -AT91PS_EMAC p_mac; - -/*********** EMAC Phy layer Management functions *************************/ -/* - * Name: - * at91rm9200_EmacEnableMDIO - * Description: - * Enables the MDIO bit in MAC control register - * Arguments: - * p_mac - pointer to struct AT91S_EMAC - * Return value: - * none - */ -void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac) -{ - /* Mac CTRL reg set for MDIO enable */ - p_mac->EMAC_CTL |= AT91C_EMAC_MPE; /* Management port enable */ -} - -/* - * Name: - * at91rm9200_EmacDisableMDIO - * Description: - * Disables the MDIO bit in MAC control register - * Arguments: - * p_mac - pointer to struct AT91S_EMAC - * Return value: - * none - */ -void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac) -{ - /* Mac CTRL reg set for MDIO disable */ - p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE; /* Management port disable */ -} - - -/* - * Name: - * at91rm9200_EmacReadPhy - * Description: - * Reads data from the PHY register - * Arguments: - * dev - pointer to struct net_device - * RegisterAddress - unsigned char - * pInput - pointer to value read from register - * Return value: - * TRUE - if data read successfully - */ -UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac, - unsigned char RegisterAddress, - unsigned short *pInput) -{ - p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) | - (AT91C_EMAC_RW_R) | - (RegisterAddress << 18) | - (AT91C_EMAC_CODE_802_3); - - udelay (10000); - - *pInput = (unsigned short) p_mac->EMAC_MAN; - - return TRUE; -} - - -/* - * Name: - * at91rm9200_EmacWritePhy - * Description: - * Writes data to the PHY register - * Arguments: - * dev - pointer to struct net_device - * RegisterAddress - unsigned char - * pOutput - pointer to value to be written in the register - * Return value: - * TRUE - if data read successfully - */ -UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac, - unsigned char RegisterAddress, - unsigned short *pOutput) -{ - p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) | - AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W | - (RegisterAddress << 18) | *pOutput; - - udelay (10000); - - return TRUE; -} - -int eth_init (bd_t * bd) -{ - int ret; - int i; - uchar enetaddr[6]; - - p_mac = AT91C_BASE_EMAC; - - /* PIO Disable Register */ - *AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER | - AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV | - AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN | - AT91C_PA7_ETXCK_EREFCK; - -#ifdef CONFIG_AT91C_USE_RMII - *AT91C_PIOB_PDR = AT91C_PB19_ERXCK; - *AT91C_PIOB_BSR = AT91C_PB19_ERXCK; -#else - *AT91C_PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV | - AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER | - AT91C_PB13_ETX3 | AT91C_PB12_ETX2; - - /* Select B Register */ - *AT91C_PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | - AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | - AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2; -#endif - - *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */ - - p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */ - - /* Init Ethernet buffers */ - for (i = 0; i < RBF_FRAMEMAX; i++) { - rbfdt[i].addr = (unsigned long)rbf_framebuf[i]; - rbfdt[i].size = 0; - } - rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP; - rbfp = &rbfdt[0]; - - eth_getenv_enetaddr("ethaddr", enetaddr); - - /* The CSB337 originally used a version of the MicroMonitor bootloader - * which saved Ethernet addresses in the "wrong" order. Operating - * systems (like Linux) know this, and apply a workaround. Replicate - * that MicroMonitor behavior so we avoid needing to make such OS code - * care about which bootloader was used. - */ - if (machine_is_csb337()) { - p_mac->EMAC_SA2H = (enetaddr[0] << 8) | (enetaddr[1]); - p_mac->EMAC_SA2L = (enetaddr[2] << 24) | (enetaddr[3] << 16) - | (enetaddr[4] << 8) | (enetaddr[5]); - } else { - p_mac->EMAC_SA2L = (enetaddr[3] << 24) | (enetaddr[2] << 16) - | (enetaddr[1] << 8) | (enetaddr[0]); - p_mac->EMAC_SA2H = (enetaddr[5] << 8) | (enetaddr[4]); - } - - p_mac->EMAC_RBQP = (long) (&rbfdt[0]); - p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA); - - p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC) - & ~AT91C_EMAC_CLK; - -#ifdef CONFIG_AT91C_USE_RMII - p_mac->EMAC_CFG |= AT91C_EMAC_RMII; -#endif - -#if (AT91C_MASTER_CLOCK > 40000000) - /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */ - p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64; -#endif - - p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE; - - at91rm9200_GetPhyInterface (& PhyOps); - - if (!PhyOps.IsPhyConnected (p_mac)) - printf ("PHY not connected!!\n\r"); - - /* MII management start from here */ - if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) { - if (!(ret = PhyOps.Init (p_mac))) { - printf ("MAC: error during MII initialization\n"); - return 0; - } - } else { - printf ("No link\n\r"); - return 0; - } - - return 0; -} - -int eth_send (volatile void *packet, int length) -{ - while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ)); - p_mac->EMAC_TAR = (long) packet; - p_mac->EMAC_TCR = length; - while (p_mac->EMAC_TCR & 0x7ff); - p_mac->EMAC_TSR |= AT91C_EMAC_COMP; - return 0; -} - -int eth_rx (void) -{ - int size; - - if (!(rbfp->addr & RBF_OWNER)) - return 0; - - size = rbfp->size & RBF_SIZE; - NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size); - - rbfp->addr &= ~RBF_OWNER; - if (rbfp->addr & RBF_WRAP) - rbfp = &rbfdt[0]; - else - rbfp++; - - p_mac->EMAC_RSR |= AT91C_EMAC_REC; - - return size; -} - -void eth_halt (void) -{ -}; - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) -int at91rm9200_miiphy_read(const char *devname, unsigned char addr, - unsigned char reg, unsigned short * value) -{ - at91rm9200_EmacEnableMDIO (p_mac); - at91rm9200_EmacReadPhy (p_mac, reg, value); - at91rm9200_EmacDisableMDIO (p_mac); - return 0; -} - -int at91rm9200_miiphy_write(const char *devname, unsigned char addr, - unsigned char reg, unsigned short value) -{ - at91rm9200_EmacEnableMDIO (p_mac); - at91rm9200_EmacWritePhy (p_mac, reg, &value); - at91rm9200_EmacDisableMDIO (p_mac); - return 0; -} - -#endif - -int at91rm9200_miiphy_initialize(bd_t *bis) -{ -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write); -#endif - return 0; -} - -#endif - -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/arch/arm/cpu/arm920t/at91rm9200/i2c.c b/arch/arm/cpu/arm920t/at91rm9200/i2c.c deleted file mode 100644 index 1711088..0000000 --- a/arch/arm/cpu/arm920t/at91rm9200/i2c.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * i2c Support for Atmel's AT91RM9200 Two-Wire Interface - * - * (c) Rick Bronson - * - * Borrowed heavily from original work by: - * Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com> - * - * Modified to work with u-boot by (C) 2004 Gary Jennejohn garyj@denx.de - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * -*/ -#include <common.h> - -#ifdef CONFIG_HARD_I2C - -#include <i2c.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> - -#include <at91rm9200_i2c.h> - -/* define DEBUG */ - -/* - * Poll the i2c status register until the specified bit is set. - * Returns 0 if timed out (100 msec) - */ -static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) { - int loop_cntr = 10000; - do { - udelay(10); - } while (!(twi->TWI_SR & bit) && (--loop_cntr > 0)); - - return (loop_cntr > 0); -} - -/* - * Generic i2c master transfer entrypoint - * - * rw == 1 means that this is a read - */ -static int -at91_xfer(unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len, int rw) -{ - AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE; - int length; - unsigned char *buf; - /* Set the TWI Master Mode Register */ - twi->TWI_MMR = (chip << 16) | (alen << 8) - | ((rw == 1) ? AT91C_TWI_MREAD : 0); - - /* Set TWI Internal Address Register with first messages data field */ - if (alen > 0) - twi->TWI_IADR = addr; - - length = len; - buf = buffer; - if (length && buf) { /* sanity check */ - if (rw) { - twi->TWI_CR = AT91C_TWI_START; - while (length--) { - if (!length) - twi->TWI_CR = AT91C_TWI_STOP; - /* Wait until transfer is finished */ - if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) { - debug ("at91_i2c: timeout 1\n"); - return 1; - } - *buf++ = twi->TWI_RHR; - } - if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) { - debug ("at91_i2c: timeout 2\n"); - return 1; - } - } else { - twi->TWI_CR = AT91C_TWI_START; - while (length--) { - twi->TWI_THR = *buf++; - if (!length) - twi->TWI_CR = AT91C_TWI_STOP; - if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) { - debug ("at91_i2c: timeout 3\n"); - return 1; - } - } - /* Wait until transfer is finished */ - if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) { - debug ("at91_i2c: timeout 4\n"); - return 1; - } - } - } - return 0; -} - -int -i2c_probe(unsigned char chip) -{ - unsigned char buffer[1]; - - return at91_xfer(chip, 0, 0, buffer, 1, 1); -} - -int -i2c_read (unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len) -{ -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - /* we only allow one address byte */ - if (alen > 1) - return 1; - /* XXX assume an ATMEL AT24C16 */ - if (alen == 1) { -#if 0 /* EEPROM code already sets this correctly */ - chip |= (addr >> 8) & 0xff; -#endif - addr = addr & 0xff; - } -#endif - return at91_xfer(chip, addr, alen, buffer, len, 1); -} - -int -i2c_write(unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len) -{ -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - int i; - unsigned char *buf; - - /* we only allow one address byte */ - if (alen > 1) - return 1; - /* XXX assume an ATMEL AT24C16 */ - if (alen == 1) { - buf = buffer; - /* do single byte writes */ - for (i = 0; i < len; i++) { -#if 0 /* EEPROM code already sets this correctly */ - chip |= (addr >> 8) & 0xff; -#endif - addr = addr & 0xff; - if (at91_xfer(chip, addr, alen, buf++, 1, 0)) - return 1; - addr++; - } - return 0; - } -#endif - return at91_xfer(chip, addr, alen, buffer, len, 0); -} - -/* - * Main initialization routine - */ -void -i2c_init(int speed, int slaveaddr) -{ - AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE; - - *AT91C_PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK; - *AT91C_PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK; - *AT91C_PIOA_MDER = AT91C_PA25_TWD | AT91C_PA26_TWCK; - *AT91C_PMC_PCER = 1 << AT91C_ID_TWI; /* enable peripheral clock */ - - twi->TWI_IDR = 0x3ff; /* Disable all interrupts */ - twi->TWI_CR = AT91C_TWI_SWRST; /* Reset peripheral */ - twi->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; /* Set Master mode */ - - /* Here, CKDIV = 1 and CHDIV=CLDIV ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */ - twi->TWI_CWGR = AT91C_TWI_CKDIV1 | AT91C_TWI_CLDIV3 | (AT91C_TWI_CLDIV3 << 8); - - debug ("Found AT91 i2c\n"); - return; -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/arch/arm/cpu/arm920t/at91rm9200/ks8721.c b/arch/arm/cpu/arm920t/at91rm9200/ks8721.c deleted file mode 100644 index 9fe3793..0000000 --- a/arch/arm/cpu/arm920t/at91rm9200/ks8721.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * (C) Copyright 2006 - * Author : Eric Benard (Eukrea Electromatique) - * based on dm9161.c which is : - * (C) Copyright 2003 - * Author : Hamid Ikdoumi (Atmel) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <at91rm9200_net.h> -#include <net.h> -#include <ks8721.h> - -#ifdef CONFIG_DRIVER_ETHER - -#if defined(CONFIG_CMD_NET) - -/* - * Name: - * ks8721_isphyconnected - * Description: - * Reads the 2 PHY ID registers - * Arguments: - * p_mac - pointer to AT91S_EMAC struct - * Return value: - * 1 - if id read successfully - * 0 - if error - */ -unsigned int ks8721_isphyconnected(AT91PS_EMAC p_mac) -{ - unsigned short id1, id2; - - at91rm9200_EmacEnableMDIO(p_mac); - at91rm9200_EmacReadPhy(p_mac, - CONFIG_PHY_ADDRESS | KS8721_PHYID1, &id1); - at91rm9200_EmacReadPhy(p_mac, - CONFIG_PHY_ADDRESS | KS8721_PHYID2, &id2); - at91rm9200_EmacDisableMDIO(p_mac); - - if ((id1 == (KS8721_PHYID_OUI >> 6)) && - ((id2 >> 10) == (KS8721_PHYID_OUI & KS8721_LSB_MASK))) { - if ((id2 & KS8721_MODELMASK) == KS8721BL_MODEL) - printf("Micrel KS8721bL PHY detected : "); - else - printf("Unknown Micrel PHY detected : "); - return 1; - } - return 0; -} - -/* - * Name: - * ks8721_getlinkspeed - * Description: - * Link parallel detection status of MAC is checked and set in the - * MAC configuration registers - * Arguments: - * p_mac - pointer to MAC - * Return value: - * 1 - if link status set succesfully - * 0 - if link status not set - */ -unsigned char ks8721_getlinkspeed(AT91PS_EMAC p_mac) -{ - unsigned short stat1; - - if (!at91rm9200_EmacReadPhy(p_mac, KS8721_BMSR, &stat1)) - return 0; - - if (!(stat1 & KS8721_LINK_STATUS)) { - /* link status up? */ - printf("Link Down !\n"); - return 0; - } - - if (stat1 & KS8721_100BASE_TX_FD) { - /* set Emac for 100BaseTX and Full Duplex */ - printf("100BT FD\n"); - p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; - return 1; - } - - if (stat1 & KS8721_10BASE_T_FD) { - /* set MII for 10BaseT and Full Duplex */ - printf("10BT FD\n"); - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_FD; - return 1; - } - - if (stat1 & KS8721_100BASE_T4_HD) { - /* set MII for 100BaseTX and Half Duplex */ - printf("100BT HD\n"); - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_SPD; - return 1; - } - - if (stat1 & KS8721_10BASE_T_HD) { - /* set MII for 10BaseT and Half Duplex */ - printf("10BT HD\n"); - p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); - return 1; - } - return 0; -} - -/* - * Name: - * ks8721_initphy - * Description: - * MAC starts checking its link by using parallel detection and - * Autonegotiation and the same is set in the MAC configuration registers - * Arguments: - * p_mac - pointer to struct AT91S_EMAC - * Return value: - * 1 - if link status set succesfully - * 0 - if link status not set - */ -unsigned char ks8721_initphy(AT91PS_EMAC p_mac) -{ - unsigned char ret = 1; - unsigned short intvalue; - - at91rm9200_EmacEnableMDIO(p_mac); - - /* Try another time */ - if (!ks8721_getlinkspeed(p_mac)) - ret = ks8721_getlinkspeed(p_mac); - - /* Disable PHY Interrupts */ - intvalue = 0; - at91rm9200_EmacWritePhy(p_mac, - CONFIG_PHY_ADDRESS | KS8721_MDINTR, &intvalue); - at91rm9200_EmacDisableMDIO(p_mac); - - return ret; -} - -/* - * Name: - * ks8721_autonegotiate - * Description: - * MAC Autonegotiates with the partner status of same is set in the - * MAC configuration registers - * Arguments: - * dev - pointer to struct net_device - * Return value: - * 1 - if link status set successfully - * 0 - if link status not set - */ -unsigned char ks8721_autonegotiate(AT91PS_EMAC p_mac, int *status) -{ - unsigned short value; - unsigned short phyanar; - unsigned short phyanalpar; - - /* Set ks8721 control register */ - if (!at91rm9200_EmacReadPhy(p_mac, - CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) - return 0; - - /* remove autonegotiation enable */ - value &= ~KS8721_AUTONEG; - /* Electrically isolate PHY */ - value |= KS8721_ISOLATE; - if (!at91rm9200_EmacWritePhy(p_mac, - CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) { - return 0; - } - /* - * Set the Auto_negotiation Advertisement Register - * MII advertising for Next page, 100BaseTxFD and HD, - * 10BaseTFD and HD, IEEE 802.3 - */ - phyanar = KS8721_NP | KS8721_TX_FDX | KS8721_TX_HDX | - KS8721_10_FDX | KS8721_10_HDX | KS8721_AN_IEEE_802_3; - if (!at91rm9200_EmacWritePhy(p_mac, - CONFIG_PHY_ADDRESS | KS8721_ANAR, &phyanar)) { - return 0; - } - /* Read the Control Register */ - if (!at91rm9200_EmacReadPhy(p_mac, - CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) { - return 0; - } - value |= KS8721_SPEED_SELECT | KS8721_AUTONEG | KS8721_DUPLEX_MODE; - if (!at91rm9200_EmacWritePhy(p_mac, - CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) { - return 0; - } - /* Restart Auto_negotiation */ - value |= KS8721_RESTART_AUTONEG; - value &= ~KS8721_ISOLATE; - if (!at91rm9200_EmacWritePhy(p_mac, - CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) { - return 0; - } - /* Check AutoNegotiate complete */ - udelay(10000); - at91rm9200_EmacReadPhy(p_mac, - CONFIG_PHY_ADDRESS | KS8721_BMSR, &value); - if (!(value & KS8721_AUTONEG_COMP)) - return 0; - - /* Get the AutoNeg Link partner base page */ - if (!at91rm9200_EmacReadPhy(p_mac, - CONFIG_PHY_ADDRESS | KS8721_ANLPAR, &phyanalpar)) { - return 0; - } - - if ((phyanar & KS8721_TX_FDX) && (phyanalpar & KS8721_TX_FDX)) { - /* Set MII for 100BaseTX and Full Duplex */ - p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; - return 1; - } - - if ((phyanar & KS8721_10_FDX) && (phyanalpar & KS8721_10_FDX)) { - /* Set MII for 10BaseT and Full Duplex */ - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_FD; - return 1; - } - return 0; -} - -#endif /* CONFIG_CMD_NET */ - -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S b/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S deleted file mode 100644 index 2e7160f..0000000 --- a/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the at91rm9200dk board by - * (C) Copyright 2004 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -/* - * some parameters for the board - * - * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in - * turn is based on the boot.bin code from ATMEL - * - */ -#include <asm/arch/AT91RM9200.h> - -_MTEXT_BASE: -#undef START_FROM_MEM -#ifdef START_FROM_MEM - .word CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1 -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -.globl lowlevel_init -lowlevel_init: - /* Get the CKGR Base Address */ - ldr r1, =AT91C_BASE_CKGR - /* Main oscillator Enable register */ -#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR - ldr r0, =0x0000FF01 /* Enable main oscillator, OSCOUNT = 0xFF */ -#else - ldr r0, =0x0000FF00 /* Disable main oscillator, OSCOUNT = 0xFF */ -#endif - str r0, [r1, #AT91C_CKGR_MOR] - /* Add loop to compensate Main Oscillator startup time */ - ldr r0, =0x00000010 -LoopOsc: - subs r0, r0, #1 - bhi LoopOsc - - /* memory control configuration */ - /* this isn't very elegant, but what the heck */ - ldr r0, =SMRDATA - ldr r1, _MTEXT_BASE - sub r0, r0, r1 - add r2, r0, #80 -0: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 0b - /* delay - this is all done by guess */ - ldr r0, =0x00010000 - /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */ -1: - subs r0, r0, #1 - bhi 1b - ldr r0, =SMRDATA1 - ldr r1, _MTEXT_BASE - sub r0, r0, r1 - add r2, r0, #176 -2: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 2b - - /* switch from FastBus to Asynchronous clock mode */ - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #0xC0000000 @ set bit 31 (iA) and 30 (nF) - mcr p15, 0, r0, c1, c0, 0 - - /* everything is fine now */ - mov pc, lr - - .ltorg - -SMRDATA: - .word AT91C_EBI_CFGR - .word CONFIG_SYS_EBI_CFGR_VAL - .word AT91C_SMC_CSR0 - .word CONFIG_SYS_SMC_CSR0_VAL - .word AT91C_PLLAR - .word CONFIG_SYS_PLLAR_VAL - .word AT91C_PLLBR - .word CONFIG_SYS_PLLBR_VAL - .word AT91C_MCKR - .word CONFIG_SYS_MCKR_VAL - /* here there's a delay */ -SMRDATA1: - .word AT91C_PIOC_ASR - .word CONFIG_SYS_PIOC_ASR_VAL - .word AT91C_PIOC_BSR - .word CONFIG_SYS_PIOC_BSR_VAL - .word AT91C_PIOC_PDR - .word CONFIG_SYS_PIOC_PDR_VAL - .word AT91C_EBI_CSA - .word CONFIG_SYS_EBI_CSA_VAL - .word AT91C_SDRC_CR - .word CONFIG_SYS_SDRC_CR_VAL - .word AT91C_SDRC_MR - .word CONFIG_SYS_SDRC_MR_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word AT91C_SDRC_MR - .word CONFIG_SYS_SDRC_MR_VAL1 - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word AT91C_SDRC_MR - .word CONFIG_SYS_SDRC_MR_VAL2 - .word CONFIG_SYS_SDRAM1 - .word CONFIG_SYS_SDRAM_VAL - .word AT91C_SDRC_TR - .word CONFIG_SYS_SDRC_TR_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word AT91C_SDRC_MR - .word CONFIG_SYS_SDRC_MR_VAL3 - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - /* SMRDATA1 is 176 bytes long */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/arch/arm/cpu/arm920t/at91rm9200/lxt972.c b/arch/arm/cpu/arm920t/at91rm9200/lxt972.c deleted file mode 100644 index f02cfdd..0000000 --- a/arch/arm/cpu/arm920t/at91rm9200/lxt972.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * - * (C) Copyright 2003 - * Author : Hamid Ikdoumi (Atmel) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Adapted for KwikByte KB920x board: 22APR2005 - */ - -#include <common.h> -#include <at91rm9200_net.h> -#include <net.h> -#include <miiphy.h> -#include <lxt971a.h> - -#ifdef CONFIG_DRIVER_ETHER - -#if defined(CONFIG_CMD_NET) - -/* - * Name: - * lxt972_IsPhyConnected - * Description: - * Reads the 2 PHY ID registers - * Arguments: - * p_mac - pointer to AT91S_EMAC struct - * Return value: - * TRUE - if id read successfully - * FALSE- if error - */ -unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac) -{ - unsigned short Id1, Id2; - - at91rm9200_EmacEnableMDIO (p_mac); - at91rm9200_EmacReadPhy(p_mac, MII_PHYSID1, &Id1); - at91rm9200_EmacReadPhy(p_mac, MII_PHYSID2, &Id2); - at91rm9200_EmacDisableMDIO (p_mac); - - if ((Id1 == (0x0013)) && ((Id2 & 0xFFF0) == 0x78E0)) - return TRUE; - - return FALSE; -} - -/* - * Name: - * lxt972_GetLinkSpeed - * Description: - * Link parallel detection status of MAC is checked and set in the - * MAC configuration registers - * Arguments: - * p_mac - pointer to MAC - * Return value: - * TRUE - if link status set succesfully - * FALSE - if link status not set - */ -UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac) -{ - unsigned short stat1; - - if (!at91rm9200_EmacReadPhy (p_mac, PHY_LXT971_STAT2, &stat1)) - return FALSE; - - if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link status up? */ - return FALSE; - - if (stat1 & PHY_LXT971_STAT2_100BTX) { - - if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { - - /*set Emac for 100BaseTX and Full Duplex */ - p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; - } else { - - /*set Emac for 100BaseTX and Half Duplex */ - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_SPD; - } - - return TRUE; - - } else { - - if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { - - /*set MII for 10BaseT and Full Duplex */ - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_FD; - } else { - - /*set MII for 10BaseT and Half Duplex */ - p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); - } - - return TRUE; - } - - return FALSE; -} - - -/* - * Name: - * lxt972_InitPhy - * Description: - * MAC starts checking its link by using parallel detection and - * Autonegotiation and the same is set in the MAC configuration registers - * Arguments: - * p_mac - pointer to struct AT91S_EMAC - * Return value: - * TRUE - if link status set succesfully - * FALSE - if link status not set - */ -UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac) -{ - UCHAR ret = TRUE; - - at91rm9200_EmacEnableMDIO (p_mac); - - if (!lxt972_GetLinkSpeed (p_mac)) { - /* Try another time */ - ret = lxt972_GetLinkSpeed (p_mac); - } - - /* Disable PHY Interrupts */ - at91rm9200_EmacWritePhy (p_mac, PHY_LXT971_INT_ENABLE, 0); - - at91rm9200_EmacDisableMDIO (p_mac); - - return (ret); -} - - -/* - * Name: - * lxt972_AutoNegotiate - * Description: - * MAC Autonegotiates with the partner status of same is set in the - * MAC configuration registers - * Arguments: - * dev - pointer to struct net_device - * Return value: - * TRUE - if link status set successfully - * FALSE - if link status not set - */ -UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status) -{ - unsigned short value; - - /* Set lxt972 control register */ - if (!at91rm9200_EmacReadPhy (p_mac, MII_BMCR, &value)) - return FALSE; - - /* Restart Auto_negotiation */ - value |= BMCR_ANRESTART; - if (!at91rm9200_EmacWritePhy (p_mac, MII_BMCR, &value)) - return FALSE; - - /*check AutoNegotiate complete */ - udelay (10000); - at91rm9200_EmacReadPhy(p_mac, MII_BMSR, &value); - if (!(value & BMSR_ANEGCOMPLETE)) - return FALSE; - - return (lxt972_GetLinkSpeed (p_mac)); -} - -#endif - -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/arch/arm/cpu/arm920t/at91rm9200/reset.c b/arch/arm/cpu/arm920t/at91rm9200/reset.c deleted file mode 100644 index 945ea2c..0000000 --- a/arch/arm/cpu/arm920t/at91rm9200/reset.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * (C) Copyright 2002 - * Lineo, Inc. <www.lineo.com> - * Bernhard Kuhn <bkuhn@lineo.com> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/hardware.h> - -void board_reset(void) __attribute__((__weak__)); - -/* - * Reset the cpu by setting up the watchdog timer and let him time out - * or toggle a GPIO pin on the AT91RM9200DK board - */ -void reset_cpu (ulong ignored) -{ - -#if defined(CONFIG_AT91RM9200_USART) - /*shutdown the console to avoid strange chars during reset */ - serial_exit(); -#endif - - if (board_reset) - board_reset(); - - /* this is the way Linux does it */ - - /* FIXME: - * These defines should be moved into - * include/asm-arm/arch-at91rm9200/AT91RM9200.h - * as soon as the whitespace fix gets applied. - */ - #define AT91C_ST_RSTEN (0x1 << 16) - #define AT91C_ST_EXTEN (0x1 << 17) - #define AT91C_ST_WDRST (0x1 << 0) - #define ST_WDMR *((unsigned long *)0xfffffd08) /* watchdog mode register */ - #define ST_CR *((unsigned long *)0xfffffd00) /* system clock control register */ - - ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ; - ST_CR = AT91C_ST_WDRST; - - while (1); - /* Never reached */ -} diff --git a/arch/arm/cpu/arm920t/at91rm9200/spi.c b/arch/arm/cpu/arm920t/at91rm9200/spi.c deleted file mode 100644 index f3cb5d8..0000000 --- a/arch/arm/cpu/arm920t/at91rm9200/spi.c +++ /dev/null @@ -1,151 +0,0 @@ -/* Driver for ATMEL DataFlash support - * Author : Hamid Ikdoumi (Atmel) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include <config.h> -#include <common.h> -#include <asm/hardware.h> - -#ifdef CONFIG_HAS_DATAFLASH -#include <dataflash.h> - -#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to - the Continuous Array Read function */ - -/* AC Characteristics */ -/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ -#define DATAFLASH_TCSS (0xC << 16) -#define DATAFLASH_TCHS (0x1 << 24) - -#define AT91C_TIMEOUT_WRDY 200000 -#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0: NPCS0%1110 */ -#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */ - -/*-------------------------------------------------------------------*/ -/* SPI DataFlash Init */ -/*-------------------------------------------------------------------*/ -void AT91F_SpiInit(void) -{ - /* Configure PIOs */ - AT91C_BASE_PIOA->PIO_ASR = - AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | - AT91C_PA5_NPCS2 | AT91C_PA6_NPCS3 | AT91C_PA0_MISO | - AT91C_PA2_SPCK; - AT91C_BASE_PIOA->PIO_PDR = - AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | - AT91C_PA5_NPCS2 | AT91C_PA6_NPCS3 | AT91C_PA0_MISO | - AT91C_PA2_SPCK; - /* Enable CLock */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI; - - /* Reset the SPI */ - AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; - - /* Configure SPI in Master Mode with No CS selected !!! */ - AT91C_BASE_SPI->SPI_MR = - AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; - - /* Configure CS0 and CS3 */ - *(AT91C_SPI_CSR + 0) = - AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | - (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | - ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); - - *(AT91C_SPI_CSR + 3) = - AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | - (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | - ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); -} - -void AT91F_SpiEnable(int cs) -{ - switch(cs) { - case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ - AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI->SPI_MR |= - ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & - AT91C_SPI_PCS); - break; - case 3: /* Configure SPI CS3 for Serial DataFlash Card */ - /* Set up PIO SDC_TYPE to switch on DataFlash Card */ - /* and not MMC/SDCard */ - AT91C_BASE_PIOB->PIO_PER = - AT91C_PIO_PB7; /* Set in PIO mode */ - AT91C_BASE_PIOB->PIO_OER = - AT91C_PIO_PB7; /* Configure in output */ - /* Clear Output */ - AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7; - /* Configure PCS */ - AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI->SPI_MR |= - ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); - break; - } - - /* SPI_Enable */ - AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; } - -/*---------------------------------------------------------------------------*/ -/* \fn AT91F_SpiWrite */ -/* \brief Set the PDC registers for a transfert */ -/*---------------------------------------------------------------------------*/ -unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ) -{ - unsigned int timeout; - - pDesc->state = BUSY; - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - - /* Initialize the Transmit and Receive Pointer */ - AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ; - AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ; - - /* Intialize the Transmit and Receive Counters */ - AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size; - AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size; - - if ( pDesc->tx_data_size != 0 ) { - /* Initialize the Next Transmit and Next Receive Pointer */ - AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ; - AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ; - - /* Intialize the Next Transmit and Next Receive Counters */ - AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ; - AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ; - } - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - timeout = 0; - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; - while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && - ((timeout = get_timer_masked() ) < CONFIG_SYS_SPI_WRITE_TOUT)); - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - pDesc->state = IDLE; - - if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT){ - printf("Error Timeout\n\r"); - return DATAFLASH_ERROR; - } - - return DATAFLASH_OK; -} -#endif diff --git a/arch/arm/cpu/arm920t/at91rm9200/timer.c b/arch/arm/cpu/arm920t/at91rm9200/timer.c deleted file mode 100644 index 9c54bbe..0000000 --- a/arch/arm/cpu/arm920t/at91rm9200/timer.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * (C) Copyright 2002 - * Lineo, Inc. <www.lineo.com> - * Bernhard Kuhn <bkuhn@lineo.com> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -/*#include <asm/io.h>*/ -#include <asm/arch/hardware.h> -/*#include <asm/proc/ptrace.h>*/ - -/* the number of clocks per CONFIG_SYS_HZ */ -#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ) - -/* macro to read the 16 bit timer */ -#define READ_TIMER (tmr->TC_CV & 0x0000ffff) -AT91PS_TC tmr; - -static ulong timestamp; -static ulong lastinc; - -int timer_init (void) -{ - tmr = AT91C_BASE_TC0; - - /* enables TC1.0 clock */ - *AT91C_PMC_PCER = 1 << AT91C_ID_TC0; /* enable clock */ - - *AT91C_TCB0_BCR = 0; - *AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE; - tmr->TC_CCR = AT91C_TC_CLKDIS; -#define AT91C_TC_CMR_CPCTRG (1 << 14) - /* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */ - tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG; - - tmr->TC_IDR = ~0ul; - tmr->TC_RC = TIMER_LOAD_VAL; - lastinc = 0; - tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN; - timestamp = 0; - - return (0); -} - -/* - * timer without interrupts - */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void set_timer (ulong t) -{ - timestamp = t; -} - -void __udelay (unsigned long usec) -{ - udelay_masked(usec); -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastinc = READ_TIMER; - timestamp = 0; -} - -ulong get_timer_raw (void) -{ - ulong now = READ_TIMER; - - if (now >= lastinc) { - /* normal mode */ - timestamp += now - lastinc; - } else { - /* we have an overflow ... */ - timestamp += now + TIMER_LOAD_VAL - lastinc; - } - lastinc = now; - - return timestamp; -} - -ulong get_timer_masked (void) -{ - return get_timer_raw()/TIMER_LOAD_VAL; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - tmo = CONFIG_SYS_HZ_CLOCK / 1000; - tmo *= usec; - tmo /= 1000; - - endtime = get_timer_raw () + tmo; - - do { - ulong now = get_timer_raw (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - - tbclk = CONFIG_SYS_HZ; - return tbclk; -} diff --git a/arch/arm/cpu/arm920t/cpu.c b/arch/arm/cpu/arm920t/cpu.c index be82c87..34adb11 100644 --- a/arch/arm/cpu/arm920t/cpu.c +++ b/arch/arm/cpu/arm920t/cpu.c @@ -33,10 +33,6 @@ #include <command.h> #include <asm/system.h> -#ifdef CONFIG_AT91_LEGACY -#warning Your board is using legacy AT91RM9200 SoC access. Please update! -#endif - static void cache_flush(void); int cleanup_before_linux (void) diff --git a/arch/arm/cpu/arm920t/ep93xx/timer.c b/arch/arm/cpu/arm920t/ep93xx/timer.c index 4a0ce4d..a3990a7 100644 --- a/arch/arm/cpu/arm920t/ep93xx/timer.c +++ b/arch/arm/cpu/arm920t/ep93xx/timer.c @@ -91,17 +91,6 @@ unsigned long get_timer(unsigned long base) return get_timer_masked() - base; } -void reset_timer_masked(void) -{ - read_timer(); - timer.ticks = 0; -} - -void reset_timer(void) -{ - reset_timer_masked(); -} - void __udelay(unsigned long usec) { unsigned long long target; @@ -128,7 +117,9 @@ int timer_init(void) writel(TIMER_ENABLE | TIMER_CLKSEL, &timer_regs->timer3.control); - reset_timer_masked(); + /* Reset the timer */ + read_timer(); + timer.ticks = 0; return 0; } diff --git a/arch/arm/cpu/arm920t/imx/timer.c b/arch/arm/cpu/arm920t/imx/timer.c index b06b518..6141bd4 100644 --- a/arch/arm/cpu/arm920t/imx/timer.c +++ b/arch/arm/cpu/arm920t/imx/timer.c @@ -43,7 +43,9 @@ int timer_init (void) TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */ TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */ - reset_timer_masked(); + /* Reset the timer */ + TCTL1 &= ~TCTL_TEN; + TCTL1 |= TCTL_TEN; /* Enable timer */ return (0); } @@ -51,28 +53,11 @@ int timer_init (void) /* * timer without interrupts */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - ulong get_timer (ulong base) { return get_timer_masked() - base; } -void set_timer (ulong t) -{ - /* nop */ -} - -void reset_timer_masked (void) -{ - TCTL1 &= ~TCTL_TEN; - TCTL1 |= TCTL_TEN; /* Enable timer */ -} - ulong get_timer_masked (void) { return TCN1; diff --git a/arch/arm/cpu/arm920t/ks8695/timer.c b/arch/arm/cpu/arm920t/ks8695/timer.c index 886e370..234fe91 100644 --- a/arch/arm/cpu/arm920t/ks8695/timer.c +++ b/arch/arm/cpu/arm920t/ks8695/timer.c @@ -33,7 +33,11 @@ ulong timer_ticks; int timer_init (void) { - reset_timer(); + /* Set the hadware timer for 1ms */ + ks8695_write(KS8695_TIMER1, TIMER_COUNT); + ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE); + ks8695_write(KS8695_TIMER_CTRL, 0x2); + timer_ticks = 0; return 0; } @@ -46,20 +50,6 @@ int timer_init (void) #define TIMER_COUNT (TIMER_INTERVAL / 2) #define TIMER_PULSE TIMER_COUNT -void reset_timer_masked(void) -{ - /* Set the hadware timer for 1ms */ - ks8695_write(KS8695_TIMER1, TIMER_COUNT); - ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE); - ks8695_write(KS8695_TIMER_CTRL, 0x2); - timer_ticks = 0; -} - -void reset_timer(void) -{ - reset_timer_masked(); -} - ulong get_timer_masked(void) { /* Check for timer wrap */ @@ -76,11 +66,6 @@ ulong get_timer(ulong base) return (get_timer_masked() - base); } -void set_timer(ulong t) -{ - timer_ticks = t; -} - void __udelay(ulong usec) { ulong start = get_timer_masked(); diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c b/arch/arm/cpu/arm920t/s3c24x0/timer.c index 8cf9ff6..9571870 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/timer.c +++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c @@ -83,22 +83,11 @@ int timer_init(void) /* * timer without interrupts */ - -void reset_timer(void) -{ - reset_timer_masked(); -} - ulong get_timer(ulong base) { return get_timer_masked() - base; } -void set_timer(ulong t) -{ - timestamp = t; -} - void __udelay (unsigned long usec) { ulong tmo; @@ -112,13 +101,6 @@ void __udelay (unsigned long usec) /*NOP*/; } -void reset_timer_masked(void) -{ - /* reset time */ - lastdec = READ_TIMER(); - timestamp = 0; -} - ulong get_timer_masked(void) { ulong tmr = get_ticks(); @@ -177,7 +159,7 @@ ulong get_tbclk(void) { ulong tbclk; -#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB) +#if defined(CONFIG_SMDK2400) tbclk = timer_load_val * 100; #elif defined(CONFIG_SBC2410X) || \ defined(CONFIG_SMDK2410) || \ @@ -198,12 +180,6 @@ void reset_cpu(ulong ignored) { struct s3c24x0_watchdog *watchdog; -#ifdef CONFIG_TRAB - extern void disable_vfd(void); - - disable_vfd(); -#endif - watchdog = s3c24x0_get_base_watchdog(); /* Disable watchdog */ diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index a7476b0..0090f89 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -142,11 +142,11 @@ copyex: # if defined(CONFIG_S3C2400) # define pWTCON 0x15300000 -# define INTMSK 0x14400008 /* Interupt-Controller base addresses */ +# define INTMSK 0x14400008 /* Interrupt-Controller base addresses */ # define CLKDIVN 0x14800014 /* clock divisor register */ #else # define pWTCON 0x53000000 -# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ +# define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */ # define INTSUBMSK 0x4A00001C # define CLKDIVN 0x4C000014 /* clock divisor register */ # endif @@ -221,7 +221,7 @@ copy_loop: cmp r0, r2 /* until source end address [r2] */ blo copy_loop -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* * fix .rel.dyn relocations */ @@ -263,7 +263,7 @@ fixnext: #endif clear_bss: -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD ldr r0, _bss_start_ofs ldr r1, _bss_end_ofs mov r4, r6 /* reloc addr */ diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index 39f2e99..23ccf31 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -215,7 +215,7 @@ copy_loop: cmp r0, r2 /* until source end address [r2] */ blo copy_loop -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* * fix .rel.dyn relocations */ @@ -257,7 +257,7 @@ fixnext: #endif clear_bss: -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD ldr r0, _bss_start_ofs ldr r1, _bss_end_ofs mov r4, r6 /* reloc addr */ diff --git a/arch/arm/cpu/arm925t/timer.c b/arch/arm/cpu/arm925t/timer.c index 7dfe2b5..1b9386b 100644 --- a/arch/arm/cpu/arm925t/timer.c +++ b/arch/arm/cpu/arm925t/timer.c @@ -56,7 +56,9 @@ int timer_init (void) CONFIG_SYS_TIMERBASE + CNTL_TIMER); /* init the timestamp and lastdec value */ - reset_timer_masked(); + lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) / + (TIMER_CLOCK / CONFIG_SYS_HZ); + timestamp = 0; /* start "advancing" time stamp from 0 */ return 0; } @@ -64,22 +66,11 @@ int timer_init (void) /* * timer without interrupts */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - ulong get_timer (ulong base) { return get_timer_masked () - base; } -void set_timer (ulong t) -{ - timestamp = t; -} - /* delay x useconds AND preserve advance timestamp value */ void __udelay (unsigned long usec) { @@ -96,14 +87,6 @@ void __udelay (unsigned long usec) } } -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) / - (TIMER_CLOCK / CONFIG_SYS_HZ); - timestamp = 0; /* start "advancing" time stamp from 0 */ -} - ulong get_timer_masked (void) { uint32_t now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) / diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c index 5d911c5..82a6d7b 100644 --- a/arch/arm/cpu/arm926ejs/armada100/timer.c +++ b/arch/arm/cpu/arm926ejs/armada100/timer.c @@ -77,13 +77,6 @@ ulong read_timer(void) return(readl(&armd1timers->cvwr)); } -void reset_timer_masked(void) -{ - /* reset time */ - gd->tbl = read_timer(); - gd->tbu = 0; -} - ulong get_timer_masked(void) { ulong now = read_timer(); @@ -100,22 +93,12 @@ ulong get_timer_masked(void) return gd->tbu; } -void reset_timer(void) -{ - reset_timer_masked(); -} - ulong get_timer(ulong base) { return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) - base); } -void set_timer(ulong t) -{ - gd->tbu = t; -} - void __udelay(unsigned long usec) { ulong delayticks; @@ -152,7 +135,8 @@ int timer_init(void) /* Enable timer 0 */ writel(0x1, &armd1timers->cer); /* init the gd->tbu and gd->tbl value */ - reset_timer_masked(); + gd->tbl = read_timer(); + gd->tbu = 0; return 0; } diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c index 6bdc75c..65b8d51 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -138,7 +138,7 @@ void at91_spi1_hw_init(unsigned long cs_mask) at91_set_b_periph(AT91_PIO_PORTC, 4, 1); } if (cs_mask & (1 << 3)) { - at91_set_pio_output(AT91_PIO_PORTC, 3, 1); + at91_set_b_periph(AT91_PIO_PORTC, 3, 1); } if (cs_mask & (1 << 4)) { at91_set_pio_output(AT91_PIO_PORTB, 3, 1); diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c index b4353ef..edc7972 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c @@ -23,77 +23,73 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> + +/* + * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all + * peripheral pins. Good to have if hardware is soldered optionally + * or in case of SPI no slave is selected. Avoid lines to float + * needlessly. Use a short local PUP define. + * + * Due to errata "TXD floats when CTS is inactive" pullups are always + * on for TXD pins. + */ +#ifdef CONFIG_AT91_GPIO_PULLUP +# define PUP CONFIG_AT91_GPIO_PULLUP +#else +# define PUP 0 +#endif void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTC, 8, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* RXD0 */ - writel(1 << AT91SAM9261_ID_US0, &pmc->pcer); + writel(1 << ATMEL_ID_USART0, &pmc->pcer); } void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */ - writel(1 << AT91SAM9261_ID_US1, &pmc->pcer); + writel(1 << ATMEL_ID_USART1, &pmc->pcer); } void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */ - writel(1 << AT91SAM9261_ID_US2, &pmc->pcer); + writel(1 << ATMEL_ID_USART2, &pmc->pcer); } -void at91_serial3_hw_init(void) +void at91_seriald_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ - writel(1 << AT91_ID_SYS, &pmc->pcer); -} - -void at91_serial_hw_init(void) -{ -#ifdef CONFIG_USART0 - at91_serial0_hw_init(); -#endif - -#ifdef CONFIG_USART1 - at91_serial1_hw_init(); -#endif - -#ifdef CONFIG_USART2 - at91_serial2_hw_init(); -#endif - -#ifdef CONFIG_USART3 /* DBGU */ - at91_serial3_hw_init(); -#endif + writel(1 << ATMEL_ID_SYS, &pmc->pcer); } -#ifdef CONFIG_HAS_DATAFLASH +#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */ + at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9261_ID_SPI0, &pmc->pcer); + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTA, 3, 1); @@ -123,14 +119,14 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* SPI1_MISO */ - at91_set_a_periph(AT91_PIO_PORTB, 31, 0); /* SPI1_MOSI */ - at91_set_a_periph(AT91_PIO_PORTB, 29, 0); /* SPI1_SPCK */ + at91_set_a_periph(AT91_PIO_PORTB, 30, PUP); /* SPI1_MISO */ + at91_set_a_periph(AT91_PIO_PORTB, 31, PUP); /* SPI1_MOSI */ + at91_set_a_periph(AT91_PIO_PORTB, 29, PUP); /* SPI1_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9261_ID_SPI1, &pmc->pcer); + writel(1 << ATMEL_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 28, 1); diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c index 15e880a..6eb0f30 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -28,17 +28,31 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/hardware.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_pio.h> +#include <asm/arch/gpio.h> + +/* + * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all + * peripheral pins. Good to have if hardware is soldered optionally + * or in case of SPI no slave is selected. Avoid lines to float + * needlessly. Use a short local PUP define. + * + * Due to errata "TXD floats when CTS is inactive" pullups are always + * on for TXD pins. + */ +#ifdef CONFIG_AT91_GPIO_PULLUP +# define PUP CONFIG_AT91_GPIO_PULLUP +#else +# define PUP 0 +#endif void at91_serial0_hw_init(void) { at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */ - at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* RXD0 */ writel(1 << ATMEL_ID_USART0, &pmc->pcer); } @@ -47,7 +61,7 @@ void at91_serial1_hw_init(void) at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */ - at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* RXD1 */ + at91_set_a_periph(AT91_PIO_PORTD, 1, PUP); /* RXD1 */ writel(1 << ATMEL_ID_USART1, &pmc->pcer); } @@ -56,7 +70,7 @@ void at91_serial2_hw_init(void) at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */ - at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* RXD2 */ + at91_set_a_periph(AT91_PIO_PORTD, 3, PUP); /* RXD2 */ writel(1 << ATMEL_ID_USART2, &pmc->pcer); } @@ -64,7 +78,7 @@ void at91_seriald_hw_init(void) { at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTC, 30, PUP); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */ writel(1 << ATMEL_ID_SYS, &pmc->pcer); } @@ -74,9 +88,9 @@ void at91_spi0_hw_init(unsigned long cs_mask) { at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ - at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ - at91_set_b_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */ + at91_set_b_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */ + at91_set_b_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */ + at91_set_b_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */ /* Enable clock */ writel(1 << ATMEL_ID_SPI0, &pmc->pcer); @@ -111,9 +125,9 @@ void at91_spi1_hw_init(unsigned long cs_mask) { at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* SPI1_MISO */ - at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* SPI1_MOSI */ - at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_SPCK */ + at91_set_a_periph(AT91_PIO_PORTB, 12, PUP); /* SPI1_MISO */ + at91_set_a_periph(AT91_PIO_PORTB, 13, PUP); /* SPI1_MOSI */ + at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_SPCK */ /* Enable clock */ writel(1 << ATMEL_ID_SPI1, &pmc->pcer); diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c index 4f570f4..b0a1687 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c @@ -23,77 +23,73 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> + +/* + * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all + * peripheral pins. Good to have if hardware is soldered optionally + * or in case of SPI no slave is selected. Avoid lines to float + * needlessly. Use a short local PUP define. + * + * Due to errata "TXD floats when CTS is inactive" pullups are always + * on for TXD pins. + */ +#ifdef CONFIG_AT91_GPIO_PULLUP +# define PUP CONFIG_AT91_GPIO_PULLUP +#else +# define PUP 0 +#endif void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* TXD0 */ - at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* RXD0 */ - writel(1 << AT91SAM9RL_ID_US0, &pmc->pcer); + at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* RXD0 */ + writel(1 << ATMEL_ID_USART0, &pmc->pcer); } void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */ - at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* RXD1 */ - writel(1 << AT91SAM9RL_ID_US1, &pmc->pcer); + at91_set_a_periph(AT91_PIO_PORTA, 12, PUP); /* RXD1 */ + writel(1 << ATMEL_ID_USART1, &pmc->pcer); } void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */ - at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* RXD2 */ - writel(1 << AT91SAM9RL_ID_US2, &pmc->pcer); + at91_set_a_periph(AT91_PIO_PORTA, 14, PUP); /* RXD2 */ + writel(1 << ATMEL_ID_USART2, &pmc->pcer); } -void at91_serial3_hw_init(void) +void at91_seriald_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */ - writel(1 << AT91_ID_SYS, &pmc->pcer); -} - -void at91_serial_hw_init(void) -{ -#ifdef CONFIG_USART0 - at91_serial0_hw_init(); -#endif - -#ifdef CONFIG_USART1 - at91_serial1_hw_init(); -#endif - -#ifdef CONFIG_USART2 - at91_serial2_hw_init(); -#endif - -#ifdef CONFIG_USART3 /* DBGU */ - at91_serial3_hw_init(); -#endif + writel(1 << ATMEL_ID_SYS, &pmc->pcer); } -#ifdef CONFIG_HAS_DATAFLASH +#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* SPI0_SPCK */ + at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTA, 26, PUP); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* SPI0_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9RL_ID_SPI, &pmc->pcer); + writel(1 << ATMEL_ID_SPI, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTA, 28, 1); diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c index 608af2c..a7085de 100644 --- a/arch/arm/cpu/arm926ejs/at91/clock.c +++ b/arch/arm/cpu/arm926ejs/at91/clock.c @@ -23,36 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; -unsigned long get_cpu_clk_rate(void) -{ - return gd->cpu_clk_rate_hz; -} - -unsigned long get_main_clk_rate(void) -{ - return gd->main_clk_rate_hz; -} - -unsigned long get_mck_clk_rate(void) -{ - return gd->mck_rate_hz; -} - -unsigned long get_plla_clk_rate(void) -{ - return gd->plla_rate_hz; -} - -unsigned long get_pllb_clk_rate(void) -{ - return gd->pllb_rate_hz; -} - -u32 get_pllb_init(void) -{ - return gd->at91_pllb_usb_init; -} - static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { @@ -192,10 +162,7 @@ int at91_clock_init(unsigned long main_clock) freq = gd->mck_rate_hz; freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ -#if defined(CONFIG_AT91RM9200) - /* mdiv */ - gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); -#elif defined(CONFIG_AT91SAM9G20) +#if defined(CONFIG_AT91SAM9G20) /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; diff --git a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S index 7f7ca5e..d102195 100644 --- a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S @@ -35,7 +35,7 @@ #include <asm/arch/at91sam9_sdramc.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_rstc.h> -#ifdef CONFIG_AT91_LEGACY +#ifdef CONFIG_ATMEL_LEGACY #include <asm/arch/at91sam9_matrix.h> #endif #ifndef CONFIG_SYS_MATRIX_EBICSA_VAL @@ -230,37 +230,37 @@ SMRDATA1: .word CONFIG_SYS_SDRC_MDR_VAL .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL2 - .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL1 .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL3 - .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL2 - .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL3 - .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL4 - .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL5 - .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL6 - .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL7 - .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL8 - .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL9 .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL4 - .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL10 .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL5 - .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL11 .word AT91_ASM_SDRAMC_TR .word CONFIG_SYS_SDRC_TR_VAL2 - .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL12 /* User reset enable*/ .word AT91_ASM_RSTC_MR diff --git a/arch/arm/cpu/arm926ejs/davinci/timer.c b/arch/arm/cpu/arm926ejs/davinci/timer.c index 1c6fa4a..8b1734c 100644 --- a/arch/arm/cpu/arm926ejs/davinci/timer.c +++ b/arch/arm/cpu/arm926ejs/davinci/timer.c @@ -78,11 +78,6 @@ int timer_init(void) return(0); } -void reset_timer(void) -{ - gd->timer_reset_value = get_ticks(); -} - /* * Get the current 64 bit timer tick count */ diff --git a/arch/arm/cpu/arm926ejs/kirkwood/timer.c b/arch/arm/cpu/arm926ejs/kirkwood/timer.c index 3e80329..b4f6cf8 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/timer.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/timer.c @@ -88,13 +88,6 @@ DECLARE_GLOBAL_DATA_PTR; #define timestamp gd->tbl #define lastdec gd->lastinc -void reset_timer_masked(void) -{ - /* reset time */ - lastdec = READ_TIMER; - timestamp = 0; -} - ulong get_timer_masked(void) { ulong now = READ_TIMER; @@ -112,21 +105,11 @@ ulong get_timer_masked(void) return timestamp; } -void reset_timer(void) -{ - reset_timer_masked(); -} - ulong get_timer(ulong base) { return get_timer_masked() - base; } -void set_timer(ulong t) -{ - timestamp = t; -} - void __udelay(unsigned long usec) { uint current; @@ -164,7 +147,8 @@ int timer_init(void) writel(cntmrctrl, CNTMR_CTRL_REG); /* init the timestamp and lastdec value */ - reset_timer_masked(); + lastdec = READ_TIMER; + timestamp = 0; return 0; } diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile index bab048b..974d0be 100644 --- a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile +++ b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile @@ -37,6 +37,8 @@ all: $(obj).depend $(LIB) $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) +$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h + ######################################################################### # defines $(obj).depend target diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c b/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c new file mode 100644 index 0000000..6f9c722 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c @@ -0,0 +1,65 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <common.h> +#include <asm/arch/mb86r0x.h> + +#include <linux/kbuild.h> + +int main(void) +{ + /* ddr2 controller */ + DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric)); + DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1)); + DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2)); + DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca)); + DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm)); + DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1)); + DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2)); + DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr)); + DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf)); + DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr)); + DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims)); + DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros)); + DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1)); + DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba)); + DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs)); + + /* clock reset generator */ + DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr)); + DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha)); + DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa)); + DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb)); + DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb)); + DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram)); + + /* chip control module */ + DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc)); + + /* external bus interface */ + DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0])); + DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2])); + DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4])); + DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0])); + DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2])); + DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4])); + DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0])); + DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2])); + DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4])); + + return 0; +} diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c index 6966b0d..8f38056 100644 --- a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c +++ b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c @@ -68,7 +68,9 @@ int timer_init(void) writel(ctrl, &timer->control); - reset_timer_masked(); + /* capture current value time */ + lastdec = readl(&timer->value); + timestamp = 0; /* start "advancing" time stamp from 0 */ return 0; } @@ -94,16 +96,6 @@ unsigned long long get_ticks(void) return timestamp; } -void reset_timer_masked(void) -{ - struct mb86r0x_timer * timer = (struct mb86r0x_timer *) - MB86R0x_TIMER_BASE; - - /* capture current value time */ - lastdec = readl(&timer->value); - timestamp = 0; /* start "advancing" time stamp from 0 */ -} - ulong get_timer_masked(void) { return tick_to_time(get_ticks()); @@ -121,11 +113,6 @@ void __udelay(unsigned long usec) /*NOP*/; } -void reset_timer(void) -{ - reset_timer_masked(); -} - ulong get_timer(ulong base) { return get_timer_masked() - base; diff --git a/arch/arm/cpu/arm926ejs/mx25/Makefile b/arch/arm/cpu/arm926ejs/mx25/Makefile index 38d7f03..9219c06 100644 --- a/arch/arm/cpu/arm926ejs/mx25/Makefile +++ b/arch/arm/cpu/arm926ejs/mx25/Makefile @@ -24,18 +24,18 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS = generic.o timer.o -MX27OBJS = reset.o +COBJS = generic.o timer.o reset.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -SRCS += $(addprefix $(SRCTREE)/arch/arm/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(MX27OBJS)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) all: $(obj).depend $(LIB) $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) +$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h + ######################################################################### # defines $(obj).depend target diff --git a/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c new file mode 100644 index 0000000..ba8dfd4 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c @@ -0,0 +1,60 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <common.h> +#include <asm/arch/imx-regs.h> + +#include <linux/kbuild.h> + +int main(void) +{ + /* Clock Control Module */ + DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); + DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0)); + DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1)); + DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2)); + DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2])); + DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr)); + + /* Enhanced SDRAM Controller */ + DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0)); + DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0)); + DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc)); + + /* Multi-Layer AHB Crossbar Switch */ + DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); + DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); + DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); + DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); + DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); + DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); + DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); + DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); + DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); + DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); + DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); + DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); + DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); + DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); + DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); + + /* AHB <-> IP-Bus Interface */ + DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); + DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); + + return 0; +} diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c index 14f0c2d..5eb2747 100644 --- a/arch/arm/cpu/arm926ejs/mx25/timer.c +++ b/arch/arm/cpu/arm926ejs/mx25/timer.c @@ -121,20 +121,6 @@ int timer_init(void) return 0; } -void reset_timer_masked(void) -{ - struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE; - /* reset time */ - /* capture current incrementer value time */ - lastinc = readl(&gpt->counter); - timestamp = 0; /* start "advancing" time stamp from 0 */ -} - -void reset_timer(void) -{ - reset_timer_masked(); -} - unsigned long long get_ticks (void) { struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE; @@ -170,11 +156,6 @@ ulong get_timer (ulong base) return get_timer_masked () - base; } -void set_timer (ulong t) -{ - timestamp = time_to_tick(t); -} - /* delay x useconds AND preserve advance timstamp value */ void __udelay (unsigned long usec) { @@ -187,3 +168,15 @@ void __udelay (unsigned long usec) while (get_ticks() < tmp) /* loop till event */ /*NOP*/; } + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + + tbclk = CONFIG_MX25_CLK32; + return tbclk; +} diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile index 0e112b3..7ac1a21 100644 --- a/arch/arm/cpu/arm926ejs/mx27/Makefile +++ b/arch/arm/cpu/arm926ejs/mx27/Makefile @@ -34,6 +34,8 @@ all: $(obj).depend $(LIB) $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) +$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h + ######################################################################### # defines $(obj).depend target diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c new file mode 100644 index 0000000..f3a8d7b --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c @@ -0,0 +1,45 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <common.h> +#include <asm/arch/imx-regs.h> + +#include <linux/kbuild.h> + +int main(void) +{ + DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0)); + DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1)); + DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0)); + DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1)); + + DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); + DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); + DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); + DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); + DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); + DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); + DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); + + DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0)); + DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0)); + DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1)); + DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1)); + DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc)); + + return 0; +} diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c index 27642bf..222a8e9 100644 --- a/arch/arm/cpu/arm926ejs/mx27/generic.c +++ b/arch/arm/cpu/arm926ejs/mx27/generic.c @@ -271,7 +271,7 @@ void imx_gpio_mode(int gpio_mode) } #ifdef CONFIG_MXC_UART -void mx27_uart_init_pins(void) +void mx27_uart1_init_pins(void) { int i; unsigned int mode[] = { diff --git a/arch/arm/cpu/arm926ejs/mx27/timer.c b/arch/arm/cpu/arm926ejs/mx27/timer.c index 5c1cf01..df76d16 100644 --- a/arch/arm/cpu/arm926ejs/mx27/timer.c +++ b/arch/arm/cpu/arm926ejs/mx27/timer.c @@ -124,20 +124,6 @@ int timer_init(void) return 0; } -void reset_timer_masked(void) -{ - struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE; - /* reset time */ - /* capture current incrementer value time */ - lastinc = readl(®s->gpt_tcn); - timestamp = 0; /* start "advancing" time stamp from 0 */ -} - -void reset_timer(void) -{ - reset_timer_masked(); -} - unsigned long long get_ticks (void) { struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE; @@ -173,11 +159,6 @@ ulong get_timer (ulong base) return get_timer_masked () - base; } -void set_timer (ulong t) -{ - timestamp = time_to_tick(t); -} - /* delay x useconds AND preserve advance timstamp value */ void __udelay (unsigned long usec) { diff --git a/arch/arm/cpu/arm926ejs/nomadik/timer.c b/arch/arm/cpu/arm926ejs/nomadik/timer.c index 1d98ef3..1cd0e1f 100644 --- a/arch/arm/cpu/arm926ejs/nomadik/timer.c +++ b/arch/arm/cpu/arm926ejs/nomadik/timer.c @@ -40,16 +40,12 @@ /* Configure a free-running, auto-wrap counter with no prescaler */ int timer_init(void) { + ulong val; + writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS, CONFIG_SYS_TIMERBASE + MTU_CR(0)); - reset_timer(); - return 0; -} -/* Restart counting from 0 */ -void reset_timer(void) -{ - ulong val; + /* Reset the timer */ writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); /* * The load-register isn't really immediate: it changes on clock @@ -59,6 +55,8 @@ void reset_timer(void) val = READ_TIMER(); while (READ_TIMER() == val) ; + + return 0; } /* Return how many HZ passed since "base" */ diff --git a/arch/arm/cpu/arm926ejs/omap/timer.c b/arch/arm/cpu/arm926ejs/omap/timer.c index 88a0ee6..390c9c8 100644 --- a/arch/arm/cpu/arm926ejs/omap/timer.c +++ b/arch/arm/cpu/arm926ejs/omap/timer.c @@ -65,22 +65,11 @@ int timer_init (void) /* * timer without interrupts */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - ulong get_timer (ulong base) { return get_timer_masked () - base; } -void set_timer (ulong t) -{ - timestamp = t; -} - /* delay x useconds AND preserve advance timestamp value */ void __udelay (unsigned long usec) { diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c b/arch/arm/cpu/arm926ejs/orion5x/dram.c index 3e1ff7d..5cc31a9 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/dram.c +++ b/arch/arm/cpu/arm926ejs/orion5x/dram.c @@ -53,7 +53,7 @@ int dram_init (void) { /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (volatile long *) orion5x_sdram_bar(0), + (long *) orion5x_sdram_bar(0), CONFIG_MAX_RAM_BANK_SIZE); return 0; } @@ -65,7 +65,7 @@ void dram_init_banksize (void) for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { gd->bd->bi_dram[i].start = orion5x_sdram_bar(i); gd->bd->bi_dram[i].size = get_ram_size( - (volatile long *) (gd->bd->bi_dram[i].start), + (long *) (gd->bd->bi_dram[i].start), CONFIG_MAX_RAM_BANK_SIZE); } } diff --git a/arch/arm/cpu/arm926ejs/orion5x/timer.c b/arch/arm/cpu/arm926ejs/orion5x/timer.c index 9d45260..17df68f 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/timer.c +++ b/arch/arm/cpu/arm926ejs/orion5x/timer.c @@ -95,13 +95,6 @@ DECLARE_GLOBAL_DATA_PTR; #define timestamp gd->tbl #define lastdec gd->lastinc -void reset_timer_masked(void) -{ - /* reset time */ - lastdec = read_timer(); - timestamp = 0; -} - ulong get_timer_masked(void) { ulong now = read_timer(); @@ -119,21 +112,11 @@ ulong get_timer_masked(void) return timestamp; } -void reset_timer(void) -{ - reset_timer_masked(); -} - ulong get_timer(ulong base) { return get_timer_masked() - base; } -void set_timer(ulong t) -{ - timestamp = t; -} - static inline ulong uboot_cntr_val(void) { return readl(CNTMR_VAL_REG(UBOOT_CNTR)); @@ -181,5 +164,6 @@ int timer_init(void) void timer_init_r(void) { /* init the timestamp and lastdec value */ - reset_timer_masked(); + lastdec = read_timer(); + timestamp = 0; } diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c index ca7f7f0..c71162a 100644 --- a/arch/arm/cpu/arm926ejs/pantheon/timer.c +++ b/arch/arm/cpu/arm926ejs/pantheon/timer.c @@ -85,13 +85,6 @@ ulong read_timer(void) return val; } -void reset_timer_masked(void) -{ - /* reset time */ - gd->tbl = read_timer(); - gd->tbu = 0; -} - ulong get_timer_masked(void) { ulong now = read_timer(); @@ -108,22 +101,12 @@ ulong get_timer_masked(void) return gd->tbu; } -void reset_timer(void) -{ - reset_timer_masked(); -} - ulong get_timer(ulong base) { return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) - base); } -void set_timer(ulong t) -{ - gd->tbu = t; -} - void __udelay(unsigned long usec) { ulong delayticks; @@ -161,7 +144,8 @@ int timer_init(void) /* Enable timer 0 */ writel(0x1, &panthtimers->cer); /* init the gd->tbu and gd->tbl value */ - reset_timer_masked(); + gd->tbl = read_timer(); + gd->tbu = 0; return 0; } diff --git a/arch/arm/cpu/arm926ejs/spear/timer.c b/arch/arm/cpu/arm926ejs/spear/timer.c index 66cf4de..1dc7860 100644 --- a/arch/arm/cpu/arm926ejs/spear/timer.c +++ b/arch/arm/cpu/arm926ejs/spear/timer.c @@ -68,7 +68,9 @@ int timer_init(void) /* auto reload, start timer */ writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control); - reset_timer_masked(); + /* Reset the timer */ + lastdec = READ_TIMER(); + timestamp = 0; return 0; } @@ -76,22 +78,11 @@ int timer_init(void) /* * timer without interrupts */ - -void reset_timer(void) -{ - reset_timer_masked(); -} - ulong get_timer(ulong base) { return (get_timer_masked() / GPT_RESOLUTION) - base; } -void set_timer(ulong t) -{ - timestamp = t; -} - void __udelay(unsigned long usec) { ulong tmo; @@ -108,13 +99,6 @@ void __udelay(unsigned long usec) ; } -void reset_timer_masked(void) -{ - /* reset time */ - lastdec = READ_TIMER(); - timestamp = 0; -} - ulong get_timer_masked(void) { ulong now = READ_TIMER(); diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 0940937..636be75 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -54,7 +54,7 @@ .globl _start _start: b reset -#ifdef CONFIG_PRELOADER +#ifdef CONFIG_SPL_BUILD /* No exception handlers in preloader */ ldr pc, _hang ldr pc, _hang @@ -98,7 +98,7 @@ _irq: _fiq: .word fiq -#endif /* CONFIG_PRELOADER */ +#endif /* CONFIG_SPL_BUILD */ .balignl 16,0xdeadbeef @@ -214,7 +214,7 @@ copy_loop: cmp r0, r2 /* until source end address [r2] */ blo copy_loop -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* * fix .rel.dyn relocations */ @@ -256,7 +256,7 @@ fixnext: #endif clear_bss: -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD ldr r0, _bss_start_ofs ldr r1, _bss_end_ofs mov r4, r6 /* reloc addr */ @@ -343,7 +343,7 @@ cpu_init_crit: mov pc, lr /* back to my caller */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* ************************************************************************* * @@ -440,18 +440,18 @@ cpu_init_crit: .macro get_fiq_stack @ setup FIQ stack ldr sp, FIQ_STACK_START .endm -#endif /* CONFIG_PRELOADER */ +#endif /* CONFIG_SPL_BUILD */ /* * exception handlers */ -#ifdef CONFIG_PRELOADER +#ifdef CONFIG_SPL_BUILD .align 5 do_hang: ldr sp, _TEXT_BASE /* switch to abort stack */ 1: bl 1b /* hang and never return */ -#else /* !CONFIG_PRELOADER */ +#else /* !CONFIG_SPL_BUILD */ .align 5 undefined_instruction: get_bad_stack @@ -514,4 +514,4 @@ fiq: bl do_fiq #endif -#endif /* CONFIG_PRELOADER */ +#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm926ejs/versatile/timer.c b/arch/arm/cpu/arm926ejs/versatile/timer.c index 2e243b1..f58e151 100644 --- a/arch/arm/cpu/arm926ejs/versatile/timer.c +++ b/arch/arm/cpu/arm926ejs/versatile/timer.c @@ -94,22 +94,11 @@ int timer_init (void) /* * timer without interrupts */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - ulong get_timer (ulong base) { return get_timer_masked () - base; } -void set_timer (ulong t) -{ - timestamp = t; -} - /* delay x useconds AND preserve advance timestamp value */ void __udelay (unsigned long usec) { diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 0054b22..09374d5 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -186,7 +186,7 @@ copy_loop: cmp r0, r2 /* until source end address [r2] */ blo copy_loop -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* * fix .rel.dyn relocations */ @@ -228,7 +228,7 @@ fixnext: #endif clear_bss: -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD ldr r0, _bss_start_ofs ldr r1, _bss_end_ofs mov r4, r6 /* reloc addr */ diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index 2fd3b9a..1a93277 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -182,7 +182,7 @@ copy_loop: cmp r0, r2 /* until source end address [r2] */ blo copy_loop -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* * fix .rel.dyn relocations */ @@ -224,7 +224,7 @@ fixnext: #endif clear_bss: -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD ldr r0, _bss_start_ofs ldr r1, _bss_end_ofs mov r4, r6 /* reloc addr */ diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 8c0e915..92a5a96 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -26,7 +26,12 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).o START := start.o -COBJS := cpu.o + +ifndef CONFIG_SPL_BUILD +COBJS += cache_v7.o +COBJS += cpu.o +endif + COBJS += syslib.o SRCS := $(START:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c new file mode 100644 index 0000000..3e1e1bf --- /dev/null +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -0,0 +1,394 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <linux/types.h> +#include <common.h> +#include <asm/armv7.h> +#include <asm/utils.h> + +#define ARMV7_DCACHE_INVAL_ALL 1 +#define ARMV7_DCACHE_CLEAN_INVAL_ALL 2 +#define ARMV7_DCACHE_INVAL_RANGE 3 +#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4 + +#ifndef CONFIG_SYS_DCACHE_OFF +/* + * Write the level and type you want to Cache Size Selection Register(CSSELR) + * to get size details from Current Cache Size ID Register(CCSIDR) + */ +static void set_csselr(u32 level, u32 type) +{ u32 csselr = level << 1 | type; + + /* Write to Cache Size Selection Register(CSSELR) */ + asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr)); +} + +static u32 get_ccsidr(void) +{ + u32 ccsidr; + + /* Read current CP15 Cache Size ID Register */ + asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr)); + return ccsidr; +} + +static u32 get_clidr(void) +{ + u32 clidr; + + /* Read current CP15 Cache Level ID Register */ + asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr)); + return clidr; +} + +static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, + u32 num_ways, u32 way_shift, + u32 log2_line_len) +{ + int way, set, setway; + + /* + * For optimal assembly code: + * a. count down + * b. have bigger loop inside + */ + for (way = num_ways - 1; way >= 0 ; way--) { + for (set = num_sets - 1; set >= 0; set--) { + setway = (level << 1) | (set << log2_line_len) | + (way << way_shift); + /* Invalidate data/unified cache line by set/way */ + asm volatile (" mcr p15, 0, %0, c7, c6, 2" + : : "r" (setway)); + } + } + /* DMB to make sure the operation is complete */ + CP15DMB; +} + +static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, + u32 num_ways, u32 way_shift, + u32 log2_line_len) +{ + int way, set, setway; + + /* + * For optimal assembly code: + * a. count down + * b. have bigger loop inside + */ + for (way = num_ways - 1; way >= 0 ; way--) { + for (set = num_sets - 1; set >= 0; set--) { + setway = (level << 1) | (set << log2_line_len) | + (way << way_shift); + /* + * Clean & Invalidate data/unified + * cache line by set/way + */ + asm volatile (" mcr p15, 0, %0, c7, c14, 2" + : : "r" (setway)); + } + } + /* DMB to make sure the operation is complete */ + CP15DMB; +} + +static void v7_maint_dcache_level_setway(u32 level, u32 operation) +{ + u32 ccsidr; + u32 num_sets, num_ways, log2_line_len, log2_num_ways; + u32 way_shift; + + set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED); + + ccsidr = get_ccsidr(); + + log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >> + CCSIDR_LINE_SIZE_OFFSET) + 2; + /* Converting from words to bytes */ + log2_line_len += 2; + + num_ways = ((ccsidr & CCSIDR_ASSOCIATIVITY_MASK) >> + CCSIDR_ASSOCIATIVITY_OFFSET) + 1; + num_sets = ((ccsidr & CCSIDR_NUM_SETS_MASK) >> + CCSIDR_NUM_SETS_OFFSET) + 1; + /* + * According to ARMv7 ARM number of sets and number of ways need + * not be a power of 2 + */ + log2_num_ways = log_2_n_round_up(num_ways); + + way_shift = (32 - log2_num_ways); + if (operation == ARMV7_DCACHE_INVAL_ALL) { + v7_inval_dcache_level_setway(level, num_sets, num_ways, + way_shift, log2_line_len); + } else if (operation == ARMV7_DCACHE_CLEAN_INVAL_ALL) { + v7_clean_inval_dcache_level_setway(level, num_sets, num_ways, + way_shift, log2_line_len); + } +} + +static void v7_maint_dcache_all(u32 operation) +{ + u32 level, cache_type, level_start_bit = 0; + + u32 clidr = get_clidr(); + + for (level = 0; level < 7; level++) { + cache_type = (clidr >> level_start_bit) & 0x7; + if ((cache_type == ARMV7_CLIDR_CTYPE_DATA_ONLY) || + (cache_type == ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA) || + (cache_type == ARMV7_CLIDR_CTYPE_UNIFIED)) + v7_maint_dcache_level_setway(level, operation); + level_start_bit += 3; + } +} + +static void v7_dcache_clean_inval_range(u32 start, + u32 stop, u32 line_len) +{ + u32 mva; + + /* Align start to cache line boundary */ + start &= ~(line_len - 1); + for (mva = start; mva < stop; mva = mva + line_len) { + /* DCCIMVAC - Clean & Invalidate data cache by MVA to PoC */ + asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva)); + } +} + +static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len) +{ + u32 mva; + + /* + * If start address is not aligned to cache-line flush the first + * line to prevent affecting somebody else's buffer + */ + if (start & (line_len - 1)) { + v7_dcache_clean_inval_range(start, start + 1, line_len); + /* move to next cache line */ + start = (start + line_len - 1) & ~(line_len - 1); + } + + /* + * If stop address is not aligned to cache-line flush the last + * line to prevent affecting somebody else's buffer + */ + if (stop & (line_len - 1)) { + v7_dcache_clean_inval_range(stop, stop + 1, line_len); + /* align to the beginning of this cache line */ + stop &= ~(line_len - 1); + } + + for (mva = start; mva < stop; mva = mva + line_len) { + /* DCIMVAC - Invalidate data cache by MVA to PoC */ + asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva)); + } +} + +static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) +{ + u32 line_len, ccsidr; + + ccsidr = get_ccsidr(); + line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >> + CCSIDR_LINE_SIZE_OFFSET) + 2; + /* Converting from words to bytes */ + line_len += 2; + /* converting from log2(linelen) to linelen */ + line_len = 1 << line_len; + + switch (range_op) { + case ARMV7_DCACHE_CLEAN_INVAL_RANGE: + v7_dcache_clean_inval_range(start, stop, line_len); + break; + case ARMV7_DCACHE_INVAL_RANGE: + v7_dcache_inval_range(start, stop, line_len); + break; + } + + /* DMB to make sure the operation is complete */ + CP15DMB; +} + +/* Invalidate TLB */ +static void v7_inval_tlb(void) +{ + /* Invalidate entire unified TLB */ + asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); + /* Invalidate entire data TLB */ + asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0)); + /* Invalidate entire instruction TLB */ + asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); + /* Full system DSB - make sure that the invalidation is complete */ + CP15DSB; + /* Full system ISB - make sure the instruction stream sees it */ + CP15ISB; +} + +void invalidate_dcache_all(void) +{ + v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL); + + v7_outer_cache_inval_all(); +} + +/* + * Performs a clean & invalidation of the entire data cache + * at all levels + */ +void flush_dcache_all(void) +{ + v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL); + + v7_outer_cache_flush_all(); +} + +/* + * Invalidates range in all levels of D-cache/unified cache used: + * Affects the range [start, stop - 1] + */ +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + + v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); + + v7_outer_cache_inval_range(start, stop); +} + +/* + * Flush range(clean & invalidate) from all levels of D-cache/unified + * cache used: + * Affects the range [start, stop - 1] + */ +void flush_dcache_range(unsigned long start, unsigned long stop) +{ + v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE); + + v7_outer_cache_flush_range(start, stop); +} + +void arm_init_before_mmu(void) +{ + v7_outer_cache_enable(); + invalidate_dcache_all(); + v7_inval_tlb(); +} + +/* + * Flush range from all levels of d-cache/unified-cache used: + * Affects the range [start, start + size - 1] + */ +void flush_cache(unsigned long start, unsigned long size) +{ + flush_dcache_range(start, start + size); +} +#else /* #ifndef CONFIG_SYS_DCACHE_OFF */ +void invalidate_dcache_all(void) +{ +} + +void flush_dcache_all(void) +{ +} + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void arm_init_before_mmu(void) +{ +} + +void flush_cache(unsigned long start, unsigned long size) +{ +} +#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ + +#ifndef CONFIG_SYS_ICACHE_OFF +/* Invalidate entire I-cache and branch predictor array */ +void invalidate_icache_all(void) +{ + /* + * Invalidate all instruction caches to PoU. + * Also flushes branch target cache. + */ + asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); + + /* Invalidate entire branch predictor array */ + asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); + + /* Full system DSB - make sure that the invalidation is complete */ + CP15DSB; + + /* ISB - make sure the instruction stream sees it */ + CP15ISB; +} +#else +void invalidate_icache_all(void) +{ +} +#endif + +/* + * Stub implementations for outer cache operations + */ +void __v7_outer_cache_enable(void) +{ +} +void v7_outer_cache_enable(void) + __attribute__((weak, alias("__v7_outer_cache_enable"))); + +void __v7_outer_cache_disable(void) +{ +} +void v7_outer_cache_disable(void) + __attribute__((weak, alias("__v7_outer_cache_disable"))); + +void __v7_outer_cache_flush_all(void) +{ +} +void v7_outer_cache_flush_all(void) + __attribute__((weak, alias("__v7_outer_cache_flush_all"))); + +void __v7_outer_cache_inval_all(void) +{ +} +void v7_outer_cache_inval_all(void) + __attribute__((weak, alias("__v7_outer_cache_inval_all"))); + +void __v7_outer_cache_flush_range(u32 start, u32 end) +{ +} +void v7_outer_cache_flush_range(u32 start, u32 end) + __attribute__((weak, alias("__v7_outer_cache_flush_range"))); + +void __v7_outer_cache_inval_range(u32 start, u32 end) +{ +} +void v7_outer_cache_inval_range(u32 start, u32 end) + __attribute__((weak, alias("__v7_outer_cache_inval_range"))); diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index a01e0d6..091e3e0 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -35,16 +35,17 @@ #include <command.h> #include <asm/system.h> #include <asm/cache.h> -#ifndef CONFIG_L2_OFF -#include <asm/arch/sys_proto.h> -#endif +#include <asm/armv7.h> -static void cache_flush(void); +void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3) +{ +} + +void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) + __attribute__((weak, alias("save_boot_params_default"))); int cleanup_before_linux(void) { - unsigned int i; - /* * this function is called just before we call linux * it prepares the processor for linux @@ -53,31 +54,29 @@ int cleanup_before_linux(void) */ disable_interrupts(); - /* turn off I/D-cache */ + /* + * Turn off I-cache and invalidate it + */ icache_disable(); - dcache_disable(); - - /* invalidate I-cache */ - cache_flush(); + invalidate_icache_all(); -#ifndef CONFIG_L2_OFF - /* turn off L2 cache */ - l2_cache_disable(); - /* invalidate L2 cache also */ - invalidate_dcache(get_device_type()); -#endif - i = 0; - /* mem barrier to sync up things */ - asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); + /* + * turn off D-cache + * dcache_disable() in turn flushes the d-cache and disables MMU + */ + dcache_disable(); -#ifndef CONFIG_L2_OFF - l2_cache_enable(); -#endif + /* + * After D-cache is flushed and before it is disabled there may + * be some new valid entries brought into the cache. We are sure + * that these lines are not dirty and will not affect our execution. + * (because unwinding the call-stack and setting a bit in CP15 SCTRL + * is all we did during this. We have not pushed anything on to the + * stack. Neither have we affected any static data) + * So just invalidate the entire d-cache again to avoid coherency + * problems for kernel + */ + invalidate_dcache_all(); return 0; } - -static void cache_flush(void) -{ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); -} diff --git a/arch/arm/cpu/armv7/mx5/Makefile b/arch/arm/cpu/armv7/mx5/Makefile index e8be9c9..6e13cc3 100644 --- a/arch/arm/cpu/armv7/mx5/Makefile +++ b/arch/arm/cpu/armv7/mx5/Makefile @@ -45,4 +45,6 @@ include $(SRCTREE)/rules.mk sinclude $(obj).depend +lowlevel_init.o : $(TOPDIR)/include/asm/arch/asm-offsets.h + ######################################################################### diff --git a/arch/arm/cpu/armv7/mx5/asm-offsets.c b/arch/arm/cpu/armv7/mx5/asm-offsets.c new file mode 100644 index 0000000..f972498 --- /dev/null +++ b/arch/arm/cpu/armv7/mx5/asm-offsets.c @@ -0,0 +1,76 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <common.h> +#include <asm/arch/imx-regs.h> + +#include <linux/kbuild.h> + +int main(void) +{ + + /* Round up to make sure size gives nice stack alignment */ + DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr)); + DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr)); + DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr)); + DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr)); + DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr)); + DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr)); + DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr)); + DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1)); + DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2)); + DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1)); + DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr)); + DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr)); + DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr)); + DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr)); + DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2)); + DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3)); + DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4)); + DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr)); + DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr)); + DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr)); + DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor)); + DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr)); + DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr)); + DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr)); + DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr)); + DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr)); + DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0)); + DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1)); + DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2)); + DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3)); + DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4)); + DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5)); + DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6)); + DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor)); +#if defined(CONFIG_MX53) + DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7)); +#endif + + /* DPLL */ + DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl)); + DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config)); + DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op)); + DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd)); + DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn)); + DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op)); + DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd)); + DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn)); + + return 0; +} diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 96ebfe2..94de9f1 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -39,10 +39,14 @@ orr r0, r0, #(1 << 23) /* disable write allocate combine */ orr r0, r0, #(1 << 22) /* disable write allocate */ - cmp r3, #0x10 /* r3 contains the silicon rev */ +#if defined(CONFIG_MX51) + ldr r1, =0x0 + ldr r3, [r1, #ROM_SI_REV] + cmp r3, #0x10 /* disable write combine for TO 2 and lower revs */ orrls r0, r0, #(1 << 25) +#endif mcr 15, 1, r0, c9, c0, 2 .endm /* init_l2cc */ diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c index 40b8b56..c6106d5 100644 --- a/arch/arm/cpu/armv7/mx5/soc.c +++ b/arch/arm/cpu/armv7/mx5/soc.c @@ -163,6 +163,36 @@ int cpu_mmc_init(bd_t *bis) #endif } +void set_chipselect_size(int const cs_size) +{ + unsigned int reg; + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + reg = readl(&iomuxc_regs->gpr1); + + switch (cs_size) { + case CS0_128: + reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */ + reg |= 0x5; + break; + case CS0_64M_CS1_64M: + reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */ + reg |= 0x1B; + break; + case CS0_64M_CS1_32M_CS2_32M: + reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */ + reg |= 0x4B; + break; + case CS0_32M_CS1_32M_CS2_32M_CS3_32M: + reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */ + reg |= 0x249; + break; + default: + printf("Unknown chip select size: %d\n", cs_size); + break; + } + + writel(reg, &iomuxc_regs->gpr1); +} void reset_cpu(ulong addr) { diff --git a/arch/arm/cpu/armv7/mx5/timer.c b/arch/arm/cpu/armv7/mx5/timer.c index 1972f64..2544b08 100644 --- a/arch/arm/cpu/armv7/mx5/timer.c +++ b/arch/arm/cpu/armv7/mx5/timer.c @@ -52,6 +52,7 @@ DECLARE_GLOBAL_DATA_PTR; int timer_init(void) { int i; + ulong val; /* setup GP Timer 1 */ __raw_writel(GPTCR_SWR, &cur_gpt->control); @@ -65,20 +66,12 @@ int timer_init(void) /* Freerun Mode, PERCLK1 input */ i = __raw_readl(&cur_gpt->control); __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control); - reset_timer_masked(); - return 0; -} - -void reset_timer(void) -{ - reset_timer_masked(); -} -void reset_timer_masked(void) -{ - ulong val = __raw_readl(&cur_gpt->counter); + val = __raw_readl(&cur_gpt->counter); lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ); timestamp = 0; + + return 0; } ulong get_timer_masked(void) @@ -99,11 +92,6 @@ ulong get_timer(ulong base) return get_timer_masked() - base; } -void set_timer(ulong t) -{ - timestamp = t; -} - /* delay x useconds AND preserve advance timestamp value */ void __udelay(unsigned long usec) { diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index dc01ee5..ea9f8ec 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -28,6 +28,12 @@ LIB = $(obj)libomap-common.o SOBJS := reset.o COBJS := timer.o +COBJS += utils.o +COBJS += gpio.o + +ifdef CONFIG_SPL_BUILD +COBJS += spl.o +endif SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/arm/cpu/armv7/omap3/gpio.c b/arch/arm/cpu/armv7/omap-common/gpio.c index aeb6066..f4c3479 100644 --- a/arch/arm/cpu/armv7/omap3/gpio.c +++ b/arch/arm/cpu/armv7/omap-common/gpio.c @@ -36,24 +36,13 @@ * published by the Free Software Foundation. */ #include <common.h> -#include <asm/arch/gpio.h> +#include <asm/omap_gpio.h> #include <asm/io.h> #include <asm/errno.h> -static struct gpio_bank gpio_bank_34xx[6] = { - { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX }, -}; - -static struct gpio_bank *gpio_bank = &gpio_bank_34xx[0]; - -static inline struct gpio_bank *get_gpio_bank(int gpio) +static inline const struct gpio_bank *get_gpio_bank(int gpio) { - return &gpio_bank[gpio >> 5]; + return &omap_gpio_bank[gpio >> 5]; } static inline int get_gpio_index(int gpio) @@ -79,14 +68,15 @@ static int check_gpio(int gpio) return 0; } -static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) +static void _set_gpio_direction(const struct gpio_bank *bank, int gpio, + int is_input) { void *reg = bank->base; u32 l; switch (bank->method) { case METHOD_GPIO_24XX: - reg += OMAP24XX_GPIO_OE; + reg += OMAP_GPIO_OE; break; default: return; @@ -101,7 +91,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) void omap_set_gpio_direction(int gpio, int is_input) { - struct gpio_bank *bank; + const struct gpio_bank *bank; if (check_gpio(gpio) < 0) return; @@ -109,7 +99,8 @@ void omap_set_gpio_direction(int gpio, int is_input) _set_gpio_direction(bank, get_gpio_index(gpio), is_input); } -static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) +static void _set_gpio_dataout(const struct gpio_bank *bank, int gpio, + int enable) { void *reg = bank->base; u32 l = 0; @@ -117,9 +108,9 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) switch (bank->method) { case METHOD_GPIO_24XX: if (enable) - reg += OMAP24XX_GPIO_SETDATAOUT; + reg += OMAP_GPIO_SETDATAOUT; else - reg += OMAP24XX_GPIO_CLEARDATAOUT; + reg += OMAP_GPIO_CLEARDATAOUT; l = 1 << gpio; break; default: @@ -132,7 +123,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) void omap_set_gpio_dataout(int gpio, int enable) { - struct gpio_bank *bank; + const struct gpio_bank *bank; if (check_gpio(gpio) < 0) return; @@ -142,7 +133,7 @@ void omap_set_gpio_dataout(int gpio, int enable) int omap_get_gpio_datain(int gpio) { - struct gpio_bank *bank; + const struct gpio_bank *bank; void *reg; if (check_gpio(gpio) < 0) @@ -151,7 +142,7 @@ int omap_get_gpio_datain(int gpio) reg = bank->base; switch (bank->method) { case METHOD_GPIO_24XX: - reg += OMAP24XX_GPIO_DATAIN; + reg += OMAP_GPIO_DATAIN; break; default: return -EINVAL; @@ -160,7 +151,7 @@ int omap_get_gpio_datain(int gpio) & (1 << get_gpio_index(gpio))) != 0; } -static void _reset_gpio(struct gpio_bank *bank, int gpio) +static void _reset_gpio(const struct gpio_bank *bank, int gpio) { _set_gpio_direction(bank, get_gpio_index(gpio), 1); } @@ -175,7 +166,7 @@ int omap_request_gpio(int gpio) void omap_free_gpio(int gpio) { - struct gpio_bank *bank; + const struct gpio_bank *bank; if (check_gpio(gpio) < 0) return; diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c new file mode 100644 index 0000000..d177652 --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/spl.c @@ -0,0 +1,272 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <asm/arch/sys_proto.h> +#include <mmc.h> +#include <fat.h> +#include <timestamp_autogenerated.h> +#include <version_autogenerated.h> +#include <asm/omap_common.h> +#include <asm/arch/mmc_host_def.h> +#include <i2c.h> +#include <image.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Define global data structure pointer to it*/ +static gd_t gdata __attribute__ ((section(".data"))); +static bd_t bdata __attribute__ ((section(".data"))); +static const char *image_name; +static u8 image_os; +static u32 image_load_addr; +static u32 image_entry_point; +static u32 image_size; + +inline void hang(void) +{ + puts("### ERROR ### Please RESET the board ###\n"); + for (;;) + ; +} + +void board_init_f(ulong dummy) +{ + /* + * We call relocate_code() with relocation target same as the + * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting + * skipped. Instead, only .bss initialization will happen. That's + * all we need + */ + debug(">>board_init_f()\n"); + relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE); +} + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + switch (omap_boot_device()) { + case BOOT_DEVICE_MMC1: + omap_mmc_init(0); + break; + case BOOT_DEVICE_MMC2: + omap_mmc_init(1); + break; + } + return 0; +} +#endif + +static void parse_image_header(const struct image_header *header) +{ + u32 header_size = sizeof(struct image_header); + + if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) { + image_size = __be32_to_cpu(header->ih_size) + header_size; + image_entry_point = __be32_to_cpu(header->ih_load); + /* Load including the header */ + image_load_addr = image_entry_point - header_size; + image_os = header->ih_os; + image_name = (const char *)&header->ih_name; + debug("spl: payload image: %s load addr: 0x%x size: %d\n", + image_name, image_load_addr, image_size); + } else { + /* Signature not found - assume u-boot.bin */ + printf("mkimage signature not found - ih_magic = %x\n", + header->ih_magic); + puts("Assuming u-boot.bin ..\n"); + /* Let's assume U-Boot will not be more than 200 KB */ + image_size = 200 * 1024; + image_entry_point = CONFIG_SYS_TEXT_BASE; + image_load_addr = CONFIG_SYS_TEXT_BASE; + image_os = IH_OS_U_BOOT; + image_name = "U-Boot"; + } +} + +static void mmc_load_image_raw(struct mmc *mmc) +{ + u32 image_size_sectors, err; + const struct image_header *header; + + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - + sizeof(struct image_header)); + + /* read image header to find the image size & load address */ + err = mmc->block_dev.block_read(0, + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, 1, + (void *)header); + + if (err <= 0) + goto end; + + parse_image_header(header); + + /* convert size to sectors - round up */ + image_size_sectors = (image_size + MMCSD_SECTOR_SIZE - 1) / + MMCSD_SECTOR_SIZE; + + /* Read the header too to avoid extra memcpy */ + err = mmc->block_dev.block_read(0, + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, + image_size_sectors, (void *)image_load_addr); + +end: + if (err <= 0) { + printf("spl: mmc blk read err - %d\n", err); + hang(); + } +} + +static void mmc_load_image_fat(struct mmc *mmc) +{ + s32 err; + struct image_header *header; + + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - + sizeof(struct image_header)); + + err = fat_register_device(&mmc->block_dev, + CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION); + if (err) { + printf("spl: fat register err - %d\n", err); + hang(); + } + + err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME, + (u8 *)header, sizeof(struct image_header)); + if (err <= 0) + goto end; + + parse_image_header(header); + + err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME, + (u8 *)image_load_addr, 0); + +end: + if (err <= 0) { + printf("spl: error reading image %s, err - %d\n", + CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME, err); + hang(); + } +} + +static void mmc_load_image(void) +{ + struct mmc *mmc; + int err; + u32 boot_mode; + + mmc_initialize(gd->bd); + /* We register only one device. So, the dev id is always 0 */ + mmc = find_mmc_device(0); + if (!mmc) { + puts("spl: mmc device not found!!\n"); + hang(); + } + + err = mmc_init(mmc); + if (err) { + printf("spl: mmc init failed: err - %d\n", err); + hang(); + } + + boot_mode = omap_boot_mode(); + if (boot_mode == MMCSD_MODE_RAW) { + debug("boot mode - RAW\n"); + mmc_load_image_raw(mmc); + } else if (boot_mode == MMCSD_MODE_FAT) { + debug("boot mode - FAT\n"); + mmc_load_image_fat(mmc); + } else { + puts("spl: wrong MMC boot mode\n"); + hang(); + } +} + +void jump_to_image_no_args(void) +{ + typedef void (*image_entry_noargs_t)(void)__attribute__ ((noreturn)); + image_entry_noargs_t image_entry = + (image_entry_noargs_t) image_entry_point; + + image_entry(); +} + +void jump_to_image_no_args(void) __attribute__ ((noreturn)); +void board_init_r(gd_t *id, ulong dummy) +{ + u32 boot_device; + debug(">>spl:board_init_r()\n"); + + timer_init(); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + boot_device = omap_boot_device(); + debug("boot device - %d\n", boot_device); + switch (boot_device) { + case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: + mmc_load_image(); + break; + default: + printf("SPL: Un-supported Boot Device - %d!!!\n", boot_device); + hang(); + break; + } + + switch (image_os) { + case IH_OS_U_BOOT: + debug("Jumping to U-Boot\n"); + jump_to_image_no_args(); + break; + default: + puts("Unsupported OS image.. Jumping nevertheless..\n"); + jump_to_image_no_args(); + } +} + +void preloader_console_init(void) +{ + const char *u_boot_rev = U_BOOT_VERSION; + char rev_string_buffer[50]; + + gd = &gdata; + gd->bd = &bdata; + gd->flags |= GD_FLG_RELOC; + gd->baudrate = CONFIG_BAUDRATE; + + setup_clocks_for_console(); + serial_init(); /* serial communications setup */ + + /* Avoid a second "U-Boot" coming from this string */ + u_boot_rev = &u_boot_rev[7]; + + printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE, + U_BOOT_TIME); + omap_rev_string(rev_string_buffer); + printf("Texas Instruments %s\n", rev_string_buffer); +} diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c index 9beebb1..9f8bc93 100644 --- a/arch/arm/cpu/armv7/omap-common/timer.c +++ b/arch/arm/cpu/armv7/omap-common/timer.c @@ -43,8 +43,9 @@ static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; * Nothing really to do with interrupts, just starts up a counter. */ -#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV)) -#define TIMER_LOAD_VAL 0xffffffff +#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV)) +#define TIMER_OVERFLOW_VAL 0xffffffff +#define TIMER_LOAD_VAL 0 int timer_init(void) { @@ -54,7 +55,9 @@ int timer_init(void) writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, &timer_base->tclr); - reset_timer_masked(); /* init the timestamp and lastinc value */ + /* reset time, capture current incrementer value time */ + gd->lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); + gd->tbl = 0; /* start "advancing" time stamp from 0 */ return 0; } @@ -62,21 +65,11 @@ int timer_init(void) /* * timer without interrupts */ -void reset_timer(void) -{ - reset_timer_masked(); -} - ulong get_timer(ulong base) { return get_timer_masked() - base; } -void set_timer(ulong t) -{ - gd->tbl = t; -} - /* delay x useconds */ void __udelay(unsigned long usec) { @@ -86,20 +79,13 @@ void __udelay(unsigned long usec) while (tmo > 0) { now = readl(&timer_base->tcrr); if (last > now) /* count up timer overflow */ - tmo -= TIMER_LOAD_VAL - last + now; + tmo -= TIMER_OVERFLOW_VAL - last + now + 1; else tmo -= now - last; last = now; } } -void reset_timer_masked(void) -{ - /* reset time, capture current incrementer value time */ - gd->lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); - gd->tbl = 0; /* start "advancing" time stamp from 0 */ -} - ulong get_timer_masked(void) { /* current tick value */ diff --git a/board/trab/u-boot.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds index 4594401..8867e06 100644 --- a/board/trab/u-boot.lds +++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds @@ -2,6 +2,10 @@ * (C) Copyright 2002 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Aneesh V <aneesh@ti.com> + * * See file CREDITS for list of people who contributed to this * project. * @@ -12,7 +16,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -21,44 +25,38 @@ * MA 02111-1307 USA */ +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { - . = 0x00000000; - - . = ALIGN(4); .text : { - arch/arm/cpu/arm920t/start.o (.text) - lib/zlib.o (.text) - lib/crc32.o (.text) - lib/string.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.ppcenv) - - *(.text) - } + __start = .; + arch/arm/cpu/armv7/start.o (.text) + *(.text*) + } >.sram . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram . = ALIGN(4); - .data : { *(.data) } - + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + __image_copy_end = .; + _end = .; - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } - __bss_end__ = .; + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } >.sdram } diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c new file mode 100644 index 0000000..ea935da --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/utils.c @@ -0,0 +1,57 @@ +/* + * Copyright 2011 Linaro Limited + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +static void do_cancel_out(u32 *num, u32 *den, u32 factor) +{ + while (1) { + if (((*num)/factor*factor == (*num)) && + ((*den)/factor*factor == (*den))) { + (*num) /= factor; + (*den) /= factor; + } else + break; + } +} + +/* + * Cancel out the denominator and numerator of a fraction + * to get smaller numerator and denominator. + */ +void cancel_out(u32 *num, u32 *den, u32 den_limit) +{ + do_cancel_out(num, den, 2); + do_cancel_out(num, den, 3); + do_cancel_out(num, den, 5); + do_cancel_out(num, den, 7); + do_cancel_out(num, den, 11); + do_cancel_out(num, den, 13); + do_cancel_out(num, den, 17); + while ((*den) > den_limit) { + *num /= 2; + /* + * Round up the denominator so that the final fraction + * (num/den) is always <= the desired value + */ + *den = (*den + 1) / 2; + } +} diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index 7164d50..8e85891 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -26,11 +26,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o -SOBJS += cache.o COBJS += board.o COBJS += clock.o -COBJS += gpio.o COBJS += mem.o COBJS += sys_info.o diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 6c2a132..4aaf97b 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -37,8 +37,24 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/mem.h> #include <asm/cache.h> +#include <asm/armv7.h> +#include <asm/omap_gpio.h> +/* Declarations */ extern omap3_sysinfo sysinfo; +static void omap3_setup_aux_cr(void); +static void omap3_invalidate_l2_cache_secure(void); + +static const struct gpio_bank gpio_bank_34xx[6] = { + { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX }, +}; + +const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx; /****************************************************************************** * Routine: delay @@ -166,27 +182,13 @@ void s_init(void) try_unlock_memory(); - /* - * Right now flushing at low MPU speed. - * Need to move after clock init - */ - invalidate_dcache(get_device_type()); -#ifndef CONFIG_ICACHE_OFF - icache_enable(); -#endif + /* Errata workarounds */ + omap3_setup_aux_cr(); -#ifdef CONFIG_L2_OFF - l2_cache_disable(); -#else - l2_cache_enable(); +#ifndef CONFIG_SYS_L2CACHE_OFF + /* Invalidate L2-cache from secure mode */ + omap3_invalidate_l2_cache_secure(); #endif - /* - * Writing to AuxCR in U-boot using SMI for GP DEV - * Currently SMI in Kernel on ES2 devices seems to have an issue - * Once that is resolved, we can postpone this config to kernel - */ - if (get_device_type() == GP_DEVICE) - setup_auxcr(); set_muxconf_regs(); delay(100); @@ -292,3 +294,111 @@ int checkboard (void) return 0; } #endif /* CONFIG_DISPLAY_BOARDINFO */ + +static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) +{ + u32 i, num_params = *parameters; + u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA; + + /* + * copy the parameters to an un-cached area to avoid coherency + * issues + */ + for (i = 0; i < num_params; i++) { + __raw_writel(*parameters, sram_scratch_space); + parameters++; + sram_scratch_space++; + } + + /* Now make the PPA call */ + do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); +} + +static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) +{ + u32 acr; + + /* Read ACR */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); + acr &= ~clear_bits; + acr |= set_bits; + + if (get_device_type() == GP_DEVICE) { + omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR, + acr); + } else { + struct emu_hal_params emu_romcode_params; + emu_romcode_params.num_params = 1; + emu_romcode_params.param1 = acr; + omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, + (u32 *)&emu_romcode_params); + } +} + +static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) +{ + u32 acr; + + /* Read ACR */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); + acr &= ~clear_bits; + acr |= set_bits; + + /* Write ACR - affects non-secure banked bits */ + asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); +} + +static void omap3_setup_aux_cr(void) +{ + /* Workaround for Cortex-A8 errata: #454179 #430973 + * Set "IBE" bit + * Set "Disable Brach Size Mispredicts" bit + * Workaround for erratum #621766 + * Enable L1NEON bit + * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0 + */ + omap3_update_aux_cr_secure(0xE0, 0); +} + +#ifndef CONFIG_SYS_L2CACHE_OFF +/* Invalidate the entire L2 cache from secure mode */ +static void omap3_invalidate_l2_cache_secure(void) +{ + if (get_device_type() == GP_DEVICE) { + omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL, + 0); + } else { + struct emu_hal_params emu_romcode_params; + emu_romcode_params.num_params = 1; + emu_romcode_params.param1 = 0; + omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL, + (u32 *)&emu_romcode_params); + } +} + +void v7_outer_cache_enable(void) +{ + /* Set L2EN */ + omap3_update_aux_cr_secure(0x2, 0); + + /* + * On some revisions L2EN bit is banked on some revisions it's not + * No harm in setting both banked bits(in fact this is required + * by an erratum) + */ + omap3_update_aux_cr(0x2, 0); +} + +void v7_outer_cache_disable(void) +{ + /* Clear L2EN */ + omap3_update_aux_cr_secure(0, 0x2); + + /* + * On some revisions L2EN bit is banked on some revisions it's not + * No harm in clearing both banked bits(in fact this is required + * by an erratum) + */ + omap3_update_aux_cr(0, 0x2); +} +#endif diff --git a/arch/arm/cpu/armv7/omap3/cache.S b/arch/arm/cpu/armv7/omap3/cache.S deleted file mode 100644 index cda87ba..0000000 --- a/arch/arm/cpu/armv7/omap3/cache.S +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix <Tom.Rix@windriver.com> - * - * This file is based on and replaces the existing cache.c file - * The copyrights for the cache.c file are: - * - * (C) Copyright 2008 Texas Insturments - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <asm/arch/omap3.h> - -/* - * omap3 cache code - */ - -.align 5 -.global invalidate_dcache -.global l2_cache_enable -.global l2_cache_disable -.global setup_auxcr - -/* - * invalidate_dcache() - * - * Invalidate the whole D-cache. - * - * Corrupted registers: r0-r5, r7, r9-r11 - * - * - mm - mm_struct describing address space - */ -invalidate_dcache: - stmfd r13!, {r0 - r5, r7, r9 - r12, r14} - - mov r7, r0 @ take a backup of device type - cmp r0, #0x3 @ check if the device type is - @ GP - moveq r12, #0x1 @ set up to invalide L2 -smi: .word 0x01600070 @ Call SMI monitor (smieq) - cmp r7, #0x3 @ compare again in case its - @ lost - beq finished_inval @ if GP device, inval done - @ above - - mrc p15, 1, r0, c0, c0, 1 @ read clidr - ands r3, r0, #0x7000000 @ extract loc from clidr - mov r3, r3, lsr #23 @ left align loc bit field - beq finished_inval @ if loc is 0, then no need to - @ clean - mov r10, #0 @ start clean at cache level 0 -inval_loop1: - add r2, r10, r10, lsr #1 @ work out 3x current cache - @ level - mov r1, r0, lsr r2 @ extract cache type bits from - @ clidr - and r1, r1, #7 @ mask of the bits for current - @ cache only - cmp r1, #2 @ see what cache we have at - @ this level - blt skip_inval @ skip if no cache, or just - @ i-cache - mcr p15, 2, r10, c0, c0, 0 @ select current cache level - @ in cssr - mov r2, #0 @ operand for mcr SBZ - mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to - @ sych the new cssr&csidr, - @ with armv7 this is 'isb', - @ but we compile with armv5 - mrc p15, 1, r1, c0, c0, 0 @ read the new csidr - and r2, r1, #7 @ extract the length of the - @ cache lines - add r2, r2, #4 @ add 4 (line length offset) - ldr r4, =0x3ff - ands r4, r4, r1, lsr #3 @ find maximum number on the - @ way size - clz r5, r4 @ find bit position of way - @ size increment - ldr r7, =0x7fff - ands r7, r7, r1, lsr #13 @ extract max number of the - @ index size -inval_loop2: - mov r9, r4 @ create working copy of max - @ way size -inval_loop3: - orr r11, r10, r9, lsl r5 @ factor way and cache number - @ into r11 - orr r11, r11, r7, lsl r2 @ factor index number into r11 - mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way - subs r9, r9, #1 @ decrement the way - bge inval_loop3 - subs r7, r7, #1 @ decrement the index - bge inval_loop2 -skip_inval: - add r10, r10, #2 @ increment cache number - cmp r3, r10 - bgt inval_loop1 -finished_inval: - mov r10, #0 @ swith back to cache level 0 - mcr p15, 2, r10, c0, c0, 0 @ select current cache level - @ in cssr - mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, - @ with armv7 this is 'isb', - @ but we compile with armv5 - - ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} - -l2_cache_set: - stmfd r13!, {r4 - r6, lr} - mov r5, r0 - bl get_cpu_rev - mov r4, r0 - bl get_cpu_family - @ ES2 onwards we can disable/enable L2 ourselves - cmp r0, #CPU_OMAP34XX - cmpeq r4, #CPU_3XX_ES10 - mrc 15, 0, r0, cr1, cr0, 1 - bic r0, r0, #2 - orr r0, r0, r5, lsl #1 - mcreq 15, 0, r0, cr1, cr0, 1 - @ GP Device ROM code API usage here - @ r12 = AUXCR Write function and r0 value - mov ip, #3 - @ SMCNE instruction to call ROM Code API - .word 0x11600070 - ldmfd r13!, {r4 - r6, pc} - -l2_cache_enable: - mov r0, #1 - b l2_cache_set - -l2_cache_disable: - mov r0, #0 - b l2_cache_set - -/****************************************************************************** - * Routine: setup_auxcr() - * Description: Write to AuxCR desired value using SMI. - * general use. - *****************************************************************************/ -setup_auxcr: - mrc p15, 0, r0, c0, c0, 0 @ read main ID register - and r2, r0, #0x00f00000 @ variant - and r3, r0, #0x0000000f @ revision - orr r1, r3, r2, lsr #20-4 @ combine variant and revision - mov r12, #0x3 - mrc p15, 0, r0, c1, c0, 1 - orr r0, r0, #0x10 @ Enable ASA - @ Enable L1NEON on pre-r2p1 (erratum 621766 workaround) - cmp r1, #0x21 - orrlt r0, r0, #1 << 5 - .word 0xE1600070 @ SMC - mov r12, #0x2 - mrc p15, 1, r0, c9, c0, 2 - @ Set PLD_FWD bit in L2AUXCR on pre-r2p1 (erratum 725233 workaround) - cmp r1, #0x21 - orrlt r0, r0, #1 << 27 - .word 0xE1600070 @ SMC - bx lr - -.align 5 -.global v7_flush_dcache_all -.global v7_flush_cache_all - -/* - * v7_flush_dcache_all() - * - * Flush the whole D-cache. - * - * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) - * - * - mm - mm_struct describing address space - */ -v7_flush_dcache_all: -# dmb @ ensure ordering with previous memory accesses - mrc p15, 1, r0, c0, c0, 1 @ read clidr - ands r3, r0, #0x7000000 @ extract loc from clidr - mov r3, r3, lsr #23 @ left align loc bit field - beq finished @ if loc is 0, then no need to clean - mov r10, #0 @ start clean at cache level 0 -loop1: - add r2, r10, r10, lsr #1 @ work out 3x current cache level - mov r1, r0, lsr r2 @ extract cache type bits from clidr - and r1, r1, #7 @ mask of the bits for current cache only - cmp r1, #2 @ see what cache we have at this level - blt skip @ skip if no cache, or just i-cache - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr - mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, - @ with armv7 this is 'isb', - @ but we compile with armv5 - mrc p15, 1, r1, c0, c0, 0 @ read the new csidr - and r2, r1, #7 @ extract the length of the cache lines - add r2, r2, #4 @ add 4 (line length offset) - ldr r4, =0x3ff - ands r4, r4, r1, lsr #3 @ find maximum number on the way size - clz r5, r4 @ find bit position of way size increment - ldr r7, =0x7fff - ands r7, r7, r1, lsr #13 @ extract max number of the index size -loop2: - mov r9, r4 @ create working copy of max way size -loop3: - orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 - orr r11, r11, r7, lsl r2 @ factor index number into r11 - mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way - subs r9, r9, #1 @ decrement the way - bge loop3 - subs r7, r7, #1 @ decrement the index - bge loop2 -skip: - add r10, r10, #2 @ increment cache number - cmp r3, r10 - bgt loop1 -finished: - mov r10, #0 @ swith back to cache level 0 - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr -# dsb - mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, - @ with armv7 this is 'isb', - @ but we compile with armv5 - mov pc, lr - -/* - * v7_flush_cache_all() - * - * Flush the entire cache system. - * The data cache flush is now achieved using atomic clean / invalidates - * working outwards from L1 cache. This is done using Set/Way based cache - * maintainance instructions. - * The instruction cache can still be invalidated back to the point of - * unification in a single instruction. - * - */ -v7_flush_cache_all: - stmfd sp!, {r0-r7, r9-r11, lr} - bl v7_flush_dcache_all - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate - ldmfd sp!, {r0-r7, r9-r11, lr} - mov pc, lr diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 1458072..67e8ceb 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -35,6 +35,38 @@ _TEXT_BASE: .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ +.global omap3_gp_romcode_call +omap3_gp_romcode_call: + PUSH {r4-r12, lr} @ Save all registers from ROM code! + MOV r12, r0 @ Copy the Service ID in R12 + MOV r0, r1 @ Copy parameter to R0 + mcr p15, 0, r0, c7, c10, 4 @ DSB + mcr p15, 0, r0, c7, c10, 5 @ DMB + .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled + @ because we use -march=armv5 + POP {r4-r12, pc} + +/* + * Funtion for making PPA HAL API calls in secure devices + * Input: + * R0 - Service ID + * R1 - paramer list + */ +.global do_omap3_emu_romcode_call +do_omap3_emu_romcode_call: + PUSH {r4-r12, lr} @ Save all registers from ROM code! + MOV r12, r0 @ Copy the Secure Service ID in R12 + MOV r3, r1 @ Copy the pointer to va_list in R3 + MOV r1, #0 @ Process ID - 0 + MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer + @ to va_list in R3 + MOV r6, #0xFF @ Indicate new Task call + mcr p15, 0, r0, c7, c10, 4 @ DSB + mcr p15, 0, r0, c7, c10, 5 @ DMB + .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled + @ because we use -march=armv5 + POP {r4-r12, pc} + #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT) /************************************************************************** * cpy_clk_code: relocates clock code into SRAM where its safer to execute diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c index 549ac19..8d0496c 100644 --- a/arch/arm/cpu/armv7/omap3/sys_info.c +++ b/arch/arm/cpu/armv7/omap3/sys_info.c @@ -33,6 +33,8 @@ extern omap3_sysinfo sysinfo; static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + +#ifdef CONFIG_DISPLAY_CPUINFO static char *rev_s[CPU_3XX_MAX_REV] = { "1.0", "2.0", @@ -42,6 +44,7 @@ static char *rev_s[CPU_3XX_MAX_REV] = { "UNKNOWN", "UNKNOWN", "3.1.2"}; +#endif /* CONFIG_DISPLAY_CPUINFO */ /***************************************************************** * dieid_num_r(void) - read and set die ID diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile index 987dc9d..e7ee0b8 100644 --- a/arch/arm/cpu/armv7/omap4/Makefile +++ b/arch/arm/cpu/armv7/omap4/Makefile @@ -28,8 +28,14 @@ LIB = $(obj)lib$(SOC).o SOBJS += lowlevel_init.o COBJS += board.o +COBJS += clocks.o +COBJS += emif.o +COBJS += sdram_elpida.o + +ifndef CONFIG_SPL_BUILD COBJS += mem.o COBJS += sys_info.o +endif SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index fcd29a7..5943d61 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -28,20 +28,181 @@ * MA 02111-1307 USA */ #include <common.h> +#include <asm/armv7.h> #include <asm/arch/cpu.h> #include <asm/arch/sys_proto.h> #include <asm/sizes.h> +#include <asm/arch/emif.h> +#include <asm/omap_gpio.h> +#include "omap4_mux_data.h" DECLARE_GLOBAL_DATA_PTR; +u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV; + +static const struct gpio_bank gpio_bank_44xx[6] = { + { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX }, +}; + +const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx; + +#ifdef CONFIG_SPL_BUILD +/* + * We use static variables because global data is not ready yet. + * Initialized data is available in SPL right from the beginning. + * We would not typically need to save these parameters in regular + * U-Boot. This is needed only in SPL at the moment. + */ +u32 omap4_boot_device = BOOT_DEVICE_MMC1; +u32 omap4_boot_mode = MMCSD_MODE_FAT; + +u32 omap_boot_device(void) +{ + return omap4_boot_device; +} + +u32 omap_boot_mode(void) +{ + return omap4_boot_mode; +} +#endif + +void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) +{ + int i; + struct pad_conf_entry *pad = (struct pad_conf_entry *) array; + + for (i = 0; i < size; i++, pad++) + writew(pad->val, base + pad->offset); +} + +static void set_muxconf_regs_essential(void) +{ + do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential, + sizeof(wkup_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + /* gpio_wk7 is used for controlling TPS on 4460 */ + if (omap_revision() >= OMAP4460_ES1_0) + writew(M3, CONTROL_WKUP_PAD1_FREF_CLK4_REQ); +} + +static void set_mux_conf_regs(void) +{ + switch (omap4_hw_init_context()) { + case OMAP_INIT_CONTEXT_SPL: + set_muxconf_regs_essential(); + break; + case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: + set_muxconf_regs_non_essential(); + break; + case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: + case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: + set_muxconf_regs_essential(); + set_muxconf_regs_non_essential(); + break; + } +} + +static u32 cortex_a9_rev(void) +{ + + unsigned int rev; + + /* Read Main ID Register (MIDR) */ + asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev)); + + return rev; +} + +static void init_omap4_revision(void) +{ + /* + * For some of the ES2/ES1 boards ID_CODE is not reliable: + * Also, ES1 and ES2 have different ARM revisions + * So use ARM revision for identification + */ + unsigned int arm_rev = cortex_a9_rev(); + + switch (arm_rev) { + case MIDR_CORTEX_A9_R0P1: + *omap4_revision = OMAP4430_ES1_0; + break; + case MIDR_CORTEX_A9_R1P2: + switch (readl(CONTROL_ID_CODE)) { + case OMAP4_CONTROL_ID_CODE_ES2_0: + *omap4_revision = OMAP4430_ES2_0; + break; + case OMAP4_CONTROL_ID_CODE_ES2_1: + *omap4_revision = OMAP4430_ES2_1; + break; + case OMAP4_CONTROL_ID_CODE_ES2_2: + *omap4_revision = OMAP4430_ES2_2; + break; + default: + *omap4_revision = OMAP4430_ES2_0; + break; + } + break; + case MIDR_CORTEX_A9_R1P3: + *omap4_revision = OMAP4430_ES2_3; + break; + case MIDR_CORTEX_A9_R2P10: + *omap4_revision = OMAP4460_ES1_0; + break; + default: + *omap4_revision = OMAP4430_SILICON_ID_INVALID; + break; + } +} + +void omap_rev_string(char *omap4_rev_string) +{ + u32 omap4_rev = omap_revision(); + u32 omap4_variant = (omap4_rev & 0xFFFF0000) >> 16; + u32 major_rev = (omap4_rev & 0x00000F00) >> 8; + u32 minor_rev = (omap4_rev & 0x000000F0) >> 4; + + sprintf(omap4_rev_string, "OMAP%x ES%x.%x", omap4_variant, major_rev, + minor_rev); +} + /* * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called path is with SRAM stack. + * Description: Does early system init of watchdog, muxing, andclocks + * Watchdog disable is done always. For the rest what gets done + * depends on the boot mode in which this function is executed + * 1. s_init of SPL running from SRAM + * 2. s_init of U-Boot running from FLASH + * 3. s_init of U-Boot loaded to SDRAM by SPL + * 4. s_init of U-Boot loaded to SDRAM by ROM code using the + * Configuration Header feature + * Please have a look at the respective functions to see what gets + * done in each of these cases + * This function is called with SRAM stack. */ void s_init(void) { + init_omap4_revision(); watchdog_init(); + set_mux_conf_regs(); +#ifdef CONFIG_SPL_BUILD + preloader_console_init(); +#endif + prcm_init(); +#ifdef CONFIG_SPL_BUILD + /* For regular u-boot sdram_init() is called from dram_init() */ + sdram_init(); +#endif } /* @@ -76,17 +237,17 @@ void watchdog_init(void) * This is needed because the size of memory installed may be * different on different versions of the board */ -u32 sdram_size(void) +u32 omap4_sdram_size(void) { u32 section, i, total_size = 0, size, addr; for (i = 0; i < 4; i++) { - section = __raw_readl(DMM_LISA_MAP_BASE + i*4); - addr = section & DMM_LISA_MAP_SYS_ADDR_MASK; + section = __raw_readl(OMAP44XX_DMM_LISA_MAP_BASE + i*4); + addr = section & OMAP44XX_SYS_ADDR_MASK; /* See if the address is valid */ if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) && (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) { - size = ((section & DMM_LISA_MAP_SYS_SIZE_MASK) >> - DMM_LISA_MAP_SYS_SIZE_SHIFT); + size = ((section & OMAP44XX_SYS_SIZE_MASK) >> + OMAP44XX_SYS_SIZE_SHIFT); size = 1 << size; size *= SZ_16M; total_size += size; @@ -102,8 +263,8 @@ u32 sdram_size(void) */ int dram_init(void) { - - gd->ram_size = sdram_size(); + sdram_init(); + gd->ram_size = omap4_sdram_size(); return 0; } @@ -124,6 +285,17 @@ int checkboard(void) */ int arch_cpu_init(void) { - set_muxconf_regs(); return 0; } + +#ifndef CONFIG_SYS_L2CACHE_OFF +void v7_outer_cache_enable(void) +{ + set_pl310_ctrl_reg(1); +} + +void v7_outer_cache_disable(void) +{ + set_pl310_ctrl_reg(0); +} +#endif diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c new file mode 100644 index 0000000..eda960c --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -0,0 +1,940 @@ +/* + * + * Clock initialization for OMAP4 + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V <aneesh@ti.com> + * + * Based on previous work by: + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * Rajendra Nayak <rnayak@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/omap_common.h> +#include <asm/arch/clocks.h> +#include <asm/arch/sys_proto.h> +#include <asm/utils.h> +#include <asm/omap_gpio.h> + +#ifndef CONFIG_SPL_BUILD +/* + * printing to console doesn't work unless + * this code is executed from SPL + */ +#define printf(fmt, args...) +#define puts(s) +#endif + +#define abs(x) (((x) < 0) ? ((x)*-1) : (x)) + +struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100; + +static const u32 sys_clk_array[8] = { + 12000000, /* 12 MHz */ + 13000000, /* 13 MHz */ + 16800000, /* 16.8 MHz */ + 19200000, /* 19.2 MHz */ + 26000000, /* 26 MHz */ + 27000000, /* 27 MHz */ + 38400000, /* 38.4 MHz */ +}; + +/* + * The M & N values in the following tables are created using the + * following tool: + * tools/omap/clocks_get_m_n.c + * Please use this tool for creating the table for any new frequency. + */ + +/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */ +static const struct dpll_params mpu_dpll_params_1840mhz[NUM_SYS_CLKS] = { + {230, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {920, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {219, 3, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {575, 11, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {460, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {920, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {575, 23, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */ +static const struct dpll_params mpu_dpll_params_1584mhz[NUM_SYS_CLKS] = { + {66, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {792, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {330, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {165, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {396, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {88, 2, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {165, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* dpll locked at 1200 MHz - MPU clk at 600 MHz */ +static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { + {50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { + {200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ + {800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ + {619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ + {125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ + {400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ + {800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ + {125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ +}; + +static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { + {127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ + {762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ + {635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ + {635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ + {381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ + {254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ + {496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { + {200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */ + {800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */ + {619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */ + {125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */ + {400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */ + {800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */ + {125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */ +}; + +static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { + {64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */ + {768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */ + {320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */ + {40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */ + {384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */ + {256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */ + {20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */ +}; + +static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { + {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */ + {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */ + {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */ + {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */ + {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */ + {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */ + {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with sys_clk as source */ +static const struct dpll_params + abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { + {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */ + {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */ + {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */ + {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */ + {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */ + {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */ + {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with 32K clock as source */ +static const struct dpll_params abe_dpll_params_32k_196608khz = { + 750, 0, 1, 1, -1, -1, -1, -1 +}; + + +static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { + {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */ + {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */ + {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */ + {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */ + {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static inline u32 __get_sys_clk_index(void) +{ + u32 ind; + /* + * For ES1 the ROM code calibration of sys clock is not reliable + * due to hw issue. So, use hard-coded value. If this value is not + * correct for any board over-ride this function in board file + * From ES2.0 onwards you will get this information from + * CM_SYS_CLKSEL + */ + if (omap_revision() == OMAP4430_ES1_0) + ind = OMAP_SYS_CLK_IND_38_4_MHZ; + else { + /* SYS_CLKSEL - 1 to match the dpll param array indices */ + ind = (readl(&prcm->cm_sys_clksel) & + CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; + } + return ind; +} + +u32 get_sys_clk_index(void) + __attribute__ ((weak, alias("__get_sys_clk_index"))); + +u32 get_sys_clk_freq(void) +{ + u8 index = get_sys_clk_index(); + return sys_clk_array[index]; +} + +static inline void do_bypass_dpll(u32 *const base) +{ + struct dpll_regs *dpll_regs = (struct dpll_regs *)base; + + clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, + CM_CLKMODE_DPLL_DPLL_EN_MASK, + DPLL_EN_FAST_RELOCK_BYPASS << + CM_CLKMODE_DPLL_EN_SHIFT); +} + +static inline void wait_for_bypass(u32 *const base) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll, + LDELAY)) { + printf("Bypassing DPLL failed %p\n", base); + } +} + +static inline void do_lock_dpll(u32 *const base) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, + CM_CLKMODE_DPLL_DPLL_EN_MASK, + DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); +} + +static inline void wait_for_lock(u32 *const base) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, + &dpll_regs->cm_idlest_dpll, LDELAY)) { + printf("DPLL locking failed for %p\n", base); + hang(); + } +} + +static void do_setup_dpll(u32 *const base, const struct dpll_params *params, + u8 lock) +{ + u32 temp; + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + bypass_dpll(base); + + /* Set M & N */ + temp = readl(&dpll_regs->cm_clksel_dpll); + + temp &= ~CM_CLKSEL_DPLL_M_MASK; + temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK; + + temp &= ~CM_CLKSEL_DPLL_N_MASK; + temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK; + + writel(temp, &dpll_regs->cm_clksel_dpll); + + /* Lock */ + if (lock) + do_lock_dpll(base); + + /* Setup post-dividers */ + if (params->m2 >= 0) + writel(params->m2, &dpll_regs->cm_div_m2_dpll); + if (params->m3 >= 0) + writel(params->m3, &dpll_regs->cm_div_m3_dpll); + if (params->m4 >= 0) + writel(params->m4, &dpll_regs->cm_div_m4_dpll); + if (params->m5 >= 0) + writel(params->m5, &dpll_regs->cm_div_m5_dpll); + if (params->m6 >= 0) + writel(params->m6, &dpll_regs->cm_div_m6_dpll); + if (params->m7 >= 0) + writel(params->m7, &dpll_regs->cm_div_m7_dpll); + + /* Wait till the DPLL locks */ + if (lock) + wait_for_lock(base); +} + +const struct dpll_params *get_core_dpll_params(void) +{ + u32 sysclk_ind = get_sys_clk_index(); + + switch (omap_revision()) { + case OMAP4430_ES1_0: + return &core_dpll_params_es1_1524mhz[sysclk_ind]; + case OMAP4430_ES2_0: + case OMAP4430_SILICON_ID_INVALID: + /* safest */ + return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind]; + default: + return &core_dpll_params_1600mhz[sysclk_ind]; + } +} + +u32 omap4_ddr_clk(void) +{ + u32 ddr_clk, sys_clk_khz; + const struct dpll_params *core_dpll_params; + + sys_clk_khz = get_sys_clk_freq() / 1000; + + core_dpll_params = get_core_dpll_params(); + + debug("sys_clk %d\n ", sys_clk_khz * 1000); + + /* Find Core DPLL locked frequency first */ + ddr_clk = sys_clk_khz * 2 * core_dpll_params->m / + (core_dpll_params->n + 1); + /* + * DDR frequency is PHY_ROOT_CLK/2 + * PHY_ROOT_CLK = Fdpll/2/M2 + */ + ddr_clk = ddr_clk / 4 / core_dpll_params->m2; + + ddr_clk *= 1000; /* convert to Hz */ + debug("ddr_clk %d\n ", ddr_clk); + + return ddr_clk; +} + +/* + * Lock MPU dpll + * + * Resulting MPU frequencies: + * 4430 ES1.0 : 600 MHz + * 4430 ES2.x : 792 MHz (OPP Turbo) + * 4460 : 920 MHz (OPP Turbo) - DCC disabled + */ +void configure_mpu_dpll(void) +{ + const struct dpll_params *params; + struct dpll_regs *mpu_dpll_regs; + u32 omap4_rev, sysclk_ind; + + omap4_rev = omap_revision(); + sysclk_ind = get_sys_clk_index(); + + if (omap4_rev == OMAP4430_ES1_0) + params = &mpu_dpll_params_1200mhz[sysclk_ind]; + else if (omap4_rev < OMAP4460_ES1_0) + params = &mpu_dpll_params_1584mhz[sysclk_ind]; + else + params = &mpu_dpll_params_1840mhz[sysclk_ind]; + + /* DCC and clock divider settings for 4460 */ + if (omap4_rev >= OMAP4460_ES1_0) { + mpu_dpll_regs = + (struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu; + bypass_dpll(&prcm->cm_clkmode_dpll_mpu); + clrbits_le32(&prcm->cm_mpu_mpu_clkctrl, + MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK); + setbits_le32(&prcm->cm_mpu_mpu_clkctrl, + MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); + clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll, + CM_CLKSEL_DCC_EN_MASK); + } + + do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK); + debug("MPU DPLL locked\n"); +} + +static void setup_dplls(void) +{ + u32 sysclk_ind, temp; + const struct dpll_params *params; + debug("setup_dplls\n"); + + sysclk_ind = get_sys_clk_index(); + + /* CORE dpll */ + params = get_core_dpll_params(); /* default - safest */ + /* + * Do not lock the core DPLL now. Just set it up. + * Core DPLL will be locked after setting up EMIF + * using the FREQ_UPDATE method(freq_update_core()) + */ + do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK); + /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ + temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | + (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | + (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT); + writel(temp, &prcm->cm_clksel_core); + debug("Core DPLL configured\n"); + + /* lock PER dpll */ + do_setup_dpll(&prcm->cm_clkmode_dpll_per, + &per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK); + debug("PER DPLL locked\n"); + + /* MPU dpll */ + configure_mpu_dpll(); +} + +static void setup_non_essential_dplls(void) +{ + u32 sys_clk_khz, abe_ref_clk; + u32 sysclk_ind, sd_div, num, den; + const struct dpll_params *params; + + sysclk_ind = get_sys_clk_index(); + sys_clk_khz = get_sys_clk_freq() / 1000; + + /* IVA */ + clrsetbits_le32(&prcm->cm_bypclk_dpll_iva, + CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); + + do_setup_dpll(&prcm->cm_clkmode_dpll_iva, + &iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK); + + /* + * USB: + * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction + * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250) + * - where CLKINP is sys_clk in MHz + * Use CLKINP in KHz and adjust the denominator accordingly so + * that we have enough accuracy and at the same time no overflow + */ + params = &usb_dpll_params_1920mhz[sysclk_ind]; + num = params->m * sys_clk_khz; + den = (params->n + 1) * 250 * 1000; + num += den - 1; + sd_div = num / den; + clrsetbits_le32(&prcm->cm_clksel_dpll_usb, + CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, + sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT); + + /* Now setup the dpll with the regular function */ + do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK); + +#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK + params = &abe_dpll_params_sysclk_196608khz[sysclk_ind]; + abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; +#else + params = &abe_dpll_params_32k_196608khz; + abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; + /* + * We need to enable some additional options to achieve + * 196.608MHz from 32768 Hz + */ + setbits_le32(&prcm->cm_clkmode_dpll_abe, + CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| + CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| + CM_CLKMODE_DPLL_LPMODE_EN_MASK| + CM_CLKMODE_DPLL_REGM4XEN_MASK); + /* Spend 4 REFCLK cycles at each stage */ + clrsetbits_le32(&prcm->cm_clkmode_dpll_abe, + CM_CLKMODE_DPLL_RAMP_RATE_MASK, + 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); +#endif + + /* Select the right reference clk */ + clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel, + CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, + abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); + /* Lock the dpll */ + do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK); +} + +static void do_scale_tps62361(u32 reg, u32 volt_mv) +{ + u32 temp, step; + + step = volt_mv - TPS62361_BASE_VOLT_MV; + step /= 10; + + /* + * Select SET1 in TPS62361: + * VSEL1 is grounded on board. So the following selects + * VSEL1 = 0 and VSEL0 = 1 + */ + omap_set_gpio_direction(TPS62361_VSEL0_GPIO, 0); + omap_set_gpio_dataout(TPS62361_VSEL0_GPIO, 1); + + temp = TPS62361_I2C_SLAVE_ADDR | + (reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) | + (step << PRM_VC_VAL_BYPASS_DATA_SHIFT) | + PRM_VC_VAL_BYPASS_VALID_BIT; + debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step); + + writel(temp, &prcm->prm_vc_val_bypass); + if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0, + &prcm->prm_vc_val_bypass, LDELAY)) { + puts("Scaling voltage failed for vdd_mpu from TPS\n"); + } +} + +static void do_scale_vcore(u32 vcore_reg, u32 volt_mv) +{ + u32 temp, offset_code; + u32 step = 12660; /* 12.66 mV represented in uV */ + u32 offset = volt_mv; + + /* convert to uV for better accuracy in the calculations */ + offset *= 1000; + + if (omap_revision() == OMAP4430_ES1_0) + offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV; + else + offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV; + + offset_code = (offset + step - 1) / step; + /* The code starts at 1 not 0 */ + offset_code++; + + debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv, + offset_code); + + temp = SMPS_I2C_SLAVE_ADDR | + (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) | + (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) | + PRM_VC_VAL_BYPASS_VALID_BIT; + writel(temp, &prcm->prm_vc_val_bypass); + if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0, + &prcm->prm_vc_val_bypass, LDELAY)) { + printf("Scaling voltage failed for 0x%x\n", vcore_reg); + } +} + +/* + * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva + * We set the maximum voltages allowed here because Smart-Reflex is not + * enabled in bootloader. Voltage initialization in the kernel will set + * these to the nominal values after enabling Smart-Reflex + */ +static void scale_vcores(void) +{ + u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp, omap4_rev; + + sys_clk_khz = get_sys_clk_freq() / 1000; + + /* + * Setup the dedicated I2C controller for Voltage Control + * I2C clk - high period 40% low period 60% + */ + cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; + cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; + /* values to be set in register - less by 5 & 7 respectively */ + cycles_hi -= 5; + cycles_low -= 7; + temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) | + (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); + writel(temp, &prcm->prm_vc_cfg_i2c_clk); + + /* Disable high speed mode and all advanced features */ + writel(0x0, &prcm->prm_vc_cfg_i2c_mode); + + omap4_rev = omap_revision(); + /* TPS - supplies vdd_mpu on 4460 */ + if (omap4_rev >= OMAP4460_ES1_0) { + volt = 1430; + do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt); + } + + /* + * VCORE 1 + * + * 4430 : supplies vdd_mpu + * Setting a high voltage for Nitro mode as smart reflex is not enabled. + * We use the maximum possible value in the AVS range because the next + * higher voltage in the discrete range (code >= 0b111010) is way too + * high + * + * 4460 : supplies vdd_core + */ + if (omap4_rev < OMAP4460_ES1_0) { + volt = 1417; + do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); + } else { + volt = 1200; + do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); + } + + /* VCORE 2 - supplies vdd_iva */ + volt = 1200; + do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); + + /* + * VCORE 3 + * 4430 : supplies vdd_core + * 4460 : not connected + */ + if (omap4_rev < OMAP4460_ES1_0) { + volt = 1200; + do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt); + } +} + +static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode) +{ + clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, + enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); + debug("Enable clock domain - 0x%08x\n", clkctrl_reg); +} + +static inline void wait_for_clk_enable(u32 *clkctrl_addr) +{ + u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; + u32 bound = LDELAY; + + while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || + (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { + + clkctrl = readl(clkctrl_addr); + idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> + MODULE_CLKCTRL_IDLEST_SHIFT; + if (--bound == 0) { + printf("Clock enable failed for 0x%p idlest 0x%x\n", + clkctrl_addr, clkctrl); + return; + } + } +} + +static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode, + u32 wait_for_enable) +{ + clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, + enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); + debug("Enable clock module - 0x%08x\n", clkctrl_addr); + if (wait_for_enable) + wait_for_clk_enable(clkctrl_addr); +} + +/* + * Enable essential clock domains, modules and + * do some additional special settings needed + */ +static void enable_basic_clocks(void) +{ + u32 i, max = 100, wait_for_enable = 1; + u32 *const clk_domains_essential[] = { + &prcm->cm_l4per_clkstctrl, + &prcm->cm_l3init_clkstctrl, + &prcm->cm_memif_clkstctrl, + &prcm->cm_l4cfg_clkstctrl, + 0 + }; + + u32 *const clk_modules_hw_auto_essential[] = { + &prcm->cm_wkup_gpio1_clkctrl, + &prcm->cm_l4per_gpio2_clkctrl, + &prcm->cm_l4per_gpio3_clkctrl, + &prcm->cm_l4per_gpio4_clkctrl, + &prcm->cm_l4per_gpio5_clkctrl, + &prcm->cm_l4per_gpio6_clkctrl, + &prcm->cm_memif_emif_1_clkctrl, + &prcm->cm_memif_emif_2_clkctrl, + &prcm->cm_l3init_hsusbotg_clkctrl, + &prcm->cm_l3init_usbphy_clkctrl, + &prcm->cm_l4cfg_l4_cfg_clkctrl, + 0 + }; + + u32 *const clk_modules_explicit_en_essential[] = { + &prcm->cm_l4per_gptimer2_clkctrl, + &prcm->cm_l3init_hsmmc1_clkctrl, + &prcm->cm_l3init_hsmmc2_clkctrl, + &prcm->cm_l4per_mcspi1_clkctrl, + &prcm->cm_wkup_gptimer1_clkctrl, + &prcm->cm_l4per_i2c1_clkctrl, + &prcm->cm_l4per_i2c2_clkctrl, + &prcm->cm_l4per_i2c3_clkctrl, + &prcm->cm_l4per_i2c4_clkctrl, + &prcm->cm_wkup_wdtimer2_clkctrl, + &prcm->cm_l4per_uart3_clkctrl, + 0 + }; + + /* Enable optional additional functional clock for GPIO4 */ + setbits_le32(&prcm->cm_l4per_gpio4_clkctrl, + GPIO4_CLKCTRL_OPTFCLKEN_MASK); + + /* Enable 96 MHz clock for MMC1 & MMC2 */ + setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl, + HSMMC_CLKCTRL_CLKSEL_MASK); + setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl, + HSMMC_CLKCTRL_CLKSEL_MASK); + + /* Select 32KHz clock as the source of GPTIMER1 */ + setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl, + GPTIMER1_CLKCTRL_CLKSEL_MASK); + + /* Enable optional 48M functional clock for USB PHY */ + setbits_le32(&prcm->cm_l3init_usbphy_clkctrl, + USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); + + /* Put the clock domains in SW_WKUP mode */ + for (i = 0; (i < max) && clk_domains_essential[i]; i++) { + enable_clock_domain(clk_domains_essential[i], + CD_CLKCTRL_CLKTRCTRL_SW_WKUP); + } + + /* Clock modules that need to be put in HW_AUTO */ + for (i = 0; (i < max) && clk_modules_hw_auto_essential[i]; i++) { + enable_clock_module(clk_modules_hw_auto_essential[i], + MODULE_CLKCTRL_MODULEMODE_HW_AUTO, + wait_for_enable); + }; + + /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ + for (i = 0; (i < max) && clk_modules_explicit_en_essential[i]; i++) { + enable_clock_module(clk_modules_explicit_en_essential[i], + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, + wait_for_enable); + }; + + /* Put the clock domains in HW_AUTO mode now */ + for (i = 0; (i < max) && clk_domains_essential[i]; i++) { + enable_clock_domain(clk_domains_essential[i], + CD_CLKCTRL_CLKTRCTRL_HW_AUTO); + } +} + +/* + * Enable non-essential clock domains, modules and + * do some additional special settings needed + */ +static void enable_non_essential_clocks(void) +{ + u32 i, max = 100, wait_for_enable = 0; + u32 *const clk_domains_non_essential[] = { + &prcm->cm_mpu_m3_clkstctrl, + &prcm->cm_ivahd_clkstctrl, + &prcm->cm_dsp_clkstctrl, + &prcm->cm_dss_clkstctrl, + &prcm->cm_sgx_clkstctrl, + &prcm->cm1_abe_clkstctrl, + &prcm->cm_c2c_clkstctrl, + &prcm->cm_cam_clkstctrl, + &prcm->cm_dss_clkstctrl, + &prcm->cm_sdma_clkstctrl, + 0 + }; + + u32 *const clk_modules_hw_auto_non_essential[] = { + &prcm->cm_mpu_m3_mpu_m3_clkctrl, + &prcm->cm_ivahd_ivahd_clkctrl, + &prcm->cm_ivahd_sl2_clkctrl, + &prcm->cm_dsp_dsp_clkctrl, + &prcm->cm_l3_2_gpmc_clkctrl, + &prcm->cm_l3instr_l3_3_clkctrl, + &prcm->cm_l3instr_l3_instr_clkctrl, + &prcm->cm_l3instr_intrconn_wp1_clkctrl, + &prcm->cm_l3init_hsi_clkctrl, + &prcm->cm_l3init_hsusbtll_clkctrl, + 0 + }; + + u32 *const clk_modules_explicit_en_non_essential[] = { + &prcm->cm1_abe_aess_clkctrl, + &prcm->cm1_abe_pdm_clkctrl, + &prcm->cm1_abe_dmic_clkctrl, + &prcm->cm1_abe_mcasp_clkctrl, + &prcm->cm1_abe_mcbsp1_clkctrl, + &prcm->cm1_abe_mcbsp2_clkctrl, + &prcm->cm1_abe_mcbsp3_clkctrl, + &prcm->cm1_abe_slimbus_clkctrl, + &prcm->cm1_abe_timer5_clkctrl, + &prcm->cm1_abe_timer6_clkctrl, + &prcm->cm1_abe_timer7_clkctrl, + &prcm->cm1_abe_timer8_clkctrl, + &prcm->cm1_abe_wdt3_clkctrl, + &prcm->cm_l4per_gptimer9_clkctrl, + &prcm->cm_l4per_gptimer10_clkctrl, + &prcm->cm_l4per_gptimer11_clkctrl, + &prcm->cm_l4per_gptimer3_clkctrl, + &prcm->cm_l4per_gptimer4_clkctrl, + &prcm->cm_l4per_hdq1w_clkctrl, + &prcm->cm_l4per_mcbsp4_clkctrl, + &prcm->cm_l4per_mcspi2_clkctrl, + &prcm->cm_l4per_mcspi3_clkctrl, + &prcm->cm_l4per_mcspi4_clkctrl, + &prcm->cm_l4per_mmcsd3_clkctrl, + &prcm->cm_l4per_mmcsd4_clkctrl, + &prcm->cm_l4per_mmcsd5_clkctrl, + &prcm->cm_l4per_uart1_clkctrl, + &prcm->cm_l4per_uart2_clkctrl, + &prcm->cm_l4per_uart4_clkctrl, + &prcm->cm_wkup_keyboard_clkctrl, + &prcm->cm_wkup_wdtimer2_clkctrl, + &prcm->cm_cam_iss_clkctrl, + &prcm->cm_cam_fdif_clkctrl, + &prcm->cm_dss_dss_clkctrl, + &prcm->cm_sgx_sgx_clkctrl, + &prcm->cm_l3init_hsusbhost_clkctrl, + &prcm->cm_l3init_fsusb_clkctrl, + 0 + }; + + /* Enable optional functional clock for ISS */ + setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); + + /* Enable all optional functional clocks of DSS */ + setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); + + + /* Put the clock domains in SW_WKUP mode */ + for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) { + enable_clock_domain(clk_domains_non_essential[i], + CD_CLKCTRL_CLKTRCTRL_SW_WKUP); + } + + /* Clock modules that need to be put in HW_AUTO */ + for (i = 0; (i < max) && clk_modules_hw_auto_non_essential[i]; i++) { + enable_clock_module(clk_modules_hw_auto_non_essential[i], + MODULE_CLKCTRL_MODULEMODE_HW_AUTO, + wait_for_enable); + }; + + /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ + for (i = 0; (i < max) && clk_modules_explicit_en_non_essential[i]; + i++) { + enable_clock_module(clk_modules_explicit_en_non_essential[i], + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, + wait_for_enable); + }; + + /* Put the clock domains in HW_AUTO mode now */ + for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) { + enable_clock_domain(clk_domains_non_essential[i], + CD_CLKCTRL_CLKTRCTRL_HW_AUTO); + } + + /* Put camera module in no sleep mode */ + clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, + CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << + MODULE_CLKCTRL_MODULEMODE_SHIFT); +} + + +void freq_update_core(void) +{ + u32 freq_config1 = 0; + const struct dpll_params *core_dpll_params; + + core_dpll_params = get_core_dpll_params(); + /* Put EMIF clock domain in sw wakeup mode */ + enable_clock_domain(&prcm->cm_memif_clkstctrl, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP); + wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); + wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); + + freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK | + SHADOW_FREQ_CONFIG1_DLL_RESET_MASK; + + freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) & + SHADOW_FREQ_CONFIG1_DPLL_EN_MASK; + + freq_config1 |= (core_dpll_params->m2 << + SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) & + SHADOW_FREQ_CONFIG1_M2_DIV_MASK; + + writel(freq_config1, &prcm->cm_shadow_freq_config1); + if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0, + &prcm->cm_shadow_freq_config1, LDELAY)) { + puts("FREQ UPDATE procedure failed!!"); + hang(); + } + + /* Put EMIF clock domain back in hw auto mode */ + enable_clock_domain(&prcm->cm_memif_clkstctrl, + CD_CLKCTRL_CLKTRCTRL_HW_AUTO); + wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); + wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); +} + +void bypass_dpll(u32 *const base) +{ + do_bypass_dpll(base); + wait_for_bypass(base); +} + +void lock_dpll(u32 *const base) +{ + do_lock_dpll(base); + wait_for_lock(base); +} + +void setup_clocks_for_console(void) +{ + /* Do not add any spl_debug prints in this function */ + clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + + /* Enable all UARTs - console will be on one of them */ + clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_HW_AUTO << + CD_CLKCTRL_CLKTRCTRL_SHIFT); +} + +void prcm_init(void) +{ + switch (omap4_hw_init_context()) { + case OMAP_INIT_CONTEXT_SPL: + case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: + case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: + enable_basic_clocks(); + scale_vcores(); + setup_dplls(); + setup_non_essential_dplls(); + enable_non_essential_clocks(); + break; + default: + break; + } +} diff --git a/board/netstal/hcu5/config.mk b/arch/arm/cpu/armv7/omap4/config.mk index f641d54..b34fa64 100644 --- a/board/netstal/hcu5/config.mk +++ b/arch/arm/cpu/armv7/omap4/config.mk @@ -1,6 +1,13 @@ # -# (C) Copyright 2005 Netstal Maschinen AG -# Niklaus Giger (ng@netstal.com) +# Copyright 2011 Linaro Limited +# See file CREDITS for list of people who contributed to this +# project. +# +# (C) Copyright 2010 +# Texas Instruments, <www.ti.com> +# +# Aneesh V <aneesh@ti.com> +# # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of @@ -16,12 +23,8 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # - -# -# Netstal Maschinen AG: HCU5 boards -# -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -g +ifdef CONFIG_SPL_BUILD +ALL-y += $(OBJTREE)/MLO +else +ALL-y += $(obj)u-boot.img endif diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c new file mode 100644 index 0000000..487ec42 --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/emif.c @@ -0,0 +1,1310 @@ +/* + * EMIF programming + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/emif.h> +#include <asm/arch/clocks.h> +#include <asm/arch/sys_proto.h> +#include <asm/omap_common.h> +#include <asm/utils.h> + +static inline u32 emif_num(u32 base) +{ + if (base == OMAP44XX_EMIF1) + return 1; + else if (base == OMAP44XX_EMIF2) + return 2; + else + return 0; +} + +static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) +{ + u32 mr; + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + mr_addr |= cs << OMAP44XX_REG_CS_SHIFT; + writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); + if (omap_revision() == OMAP4430_ES2_0) + mr = readl(&emif->emif_lpddr2_mode_reg_data_es2); + else + mr = readl(&emif->emif_lpddr2_mode_reg_data); + debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base), + cs, mr_addr, mr); + return mr; +} + +static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + mr_addr |= cs << OMAP44XX_REG_CS_SHIFT; + writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); + writel(mr_val, &emif->emif_lpddr2_mode_reg_data); +} + +void emif_reset_phy(u32 base) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 iodft; + + iodft = readl(&emif->emif_iodft_tlgc); + iodft |= OMAP44XX_REG_RESET_PHY_MASK; + writel(iodft, &emif->emif_iodft_tlgc); +} + +static void do_lpddr2_init(u32 base, u32 cs) +{ + u32 mr_addr; + + /* Wait till device auto initialization is complete */ + while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) + ; + set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT); + /* + * tZQINIT = 1 us + * Enough loops assuming a maximum of 2GHz + */ + sdelay(2000); + set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3); + set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY); + /* + * Enable refresh along with writing MR2 + * Encoding of RL in MR2 is (RL - 2) + */ + mr_addr = LPDDR2_MR2 | OMAP44XX_REG_REFRESH_EN_MASK; + set_mr(base, cs, mr_addr, RL_FINAL - 2); +} + +static void lpddr2_init(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + /* Not NVM */ + clrbits_le32(&emif->emif_lpddr2_nvm_config, OMAP44XX_REG_CS1NVMEN_MASK); + + /* + * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM + * when EMIF_SDRAM_CONFIG register is written + */ + setbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK); + + /* + * Set the SDRAM_CONFIG and PHY_CTRL for the + * un-locked frequency & default RL + */ + writel(regs->sdram_config_init, &emif->emif_sdram_config); + writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); + + do_lpddr2_init(base, CS0); + if (regs->sdram_config & OMAP44XX_REG_EBANK_MASK) + do_lpddr2_init(base, CS1); + + writel(regs->sdram_config, &emif->emif_sdram_config); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); + + /* Enable refresh now */ + clrbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK); + +} + +static void emif_update_timings(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); + writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); + writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw); + writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw); + if (omap_revision() == OMAP4430_ES1_0) { + /* ES1 bug EMIF should be in force idle during freq_update */ + writel(0, &emif->emif_pwr_mgmt_ctrl); + } else { + writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl); + writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw); + } + writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw); + writel(regs->zq_config, &emif->emif_zq_config); + writel(regs->temp_alert_config, &emif->emif_temp_alert_config); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + + if (omap_revision() >= OMAP4460_ES1_0) { + writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0, + &emif->emif_l3_config); + } else { + writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0, + &emif->emif_l3_config); + } +} + +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) + +static u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM; +static u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN; +static u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE; + +/* + * Organization and refresh requirements for LPDDR2 devices of different + * types and densities. Derived from JESD209-2 section 2.4 + */ +const struct lpddr2_addressing addressing_table[] = { + /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */ + {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */ + {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */ + {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */ + {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */ + {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */ + {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */ + {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */ + {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */ + {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */ + {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */ +}; + +static const u32 lpddr2_density_2_size_in_mbytes[] = { + 8, /* 64Mb */ + 16, /* 128Mb */ + 32, /* 256Mb */ + 64, /* 512Mb */ + 128, /* 1Gb */ + 256, /* 2Gb */ + 512, /* 4Gb */ + 1024, /* 8Gb */ + 2048, /* 16Gb */ + 4096 /* 32Gb */ +}; + +/* + * Calculate the period of DDR clock from frequency value and set the + * denominator and numerator in global variables for easy access later + */ +static void set_ddr_clk_period(u32 freq) +{ + /* + * period = 1/freq + * period_in_ns = 10^9/freq + */ + *T_num = 1000000000; + *T_den = freq; + cancel_out(T_num, T_den, 200); + +} + +/* + * Convert time in nano seconds to number of cycles of DDR clock + */ +static inline u32 ns_2_cycles(u32 ns) +{ + return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num); +} + +/* + * ns_2_cycles with the difference that the time passed is 2 times the actual + * value(to avoid fractions). The cycles returned is for the original value of + * the timing parameter + */ +static inline u32 ns_x2_2_cycles(u32 ns) +{ + return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2); +} + +/* + * Find addressing table index based on the device's type(S2 or S4) and + * density + */ +s8 addressing_table_index(u8 type, u8 density, u8 width) +{ + u8 index; + if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8)) + return -1; + + /* + * Look at the way ADDR_TABLE_INDEX* values have been defined + * in emif.h compared to LPDDR2_DENSITY_* values + * The table is layed out in the increasing order of density + * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed + * at the end + */ + if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb)) + index = ADDR_TABLE_INDEX1GS2; + else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb)) + index = ADDR_TABLE_INDEX2GS2; + else + index = density; + + debug("emif: addressing table index %d\n", index); + + return index; +} + +/* + * Find the the right timing table from the array of timing + * tables of the device using DDR clock frequency + */ +static const struct lpddr2_ac_timings *get_timings_table(const struct + lpddr2_ac_timings const *const *device_timings, + u32 freq) +{ + u32 i, temp, freq_nearest; + const struct lpddr2_ac_timings *timings = 0; + + emif_assert(freq <= MAX_LPDDR2_FREQ); + emif_assert(device_timings); + + /* + * Start with the maximum allowed frequency - that is always safe + */ + freq_nearest = MAX_LPDDR2_FREQ; + /* + * Find the timings table that has the max frequency value: + * i. Above or equal to the DDR frequency - safe + * ii. The lowest that satisfies condition (i) - optimal + */ + for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) { + temp = device_timings[i]->max_freq; + if ((temp >= freq) && (temp <= freq_nearest)) { + freq_nearest = temp; + timings = device_timings[i]; + } + } + debug("emif: timings table: %d\n", freq_nearest); + return timings; +} + +/* + * Finds the value of emif_sdram_config_reg + * All parameters are programmed based on the device on CS0. + * If there is a device on CS1, it will be same as that on CS0 or + * it will be NVM. We don't support NVM yet. + * If cs1_device pointer is NULL it is assumed that there is no device + * on CS1 + */ +static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device, + const struct lpddr2_device_details *cs1_device, + const struct lpddr2_addressing *addressing, + u8 RL) +{ + u32 config_reg = 0; + + config_reg |= (cs0_device->type + 4) << OMAP44XX_REG_SDRAM_TYPE_SHIFT; + config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING << + OMAP44XX_REG_IBANK_POS_SHIFT; + + config_reg |= cs0_device->io_width << OMAP44XX_REG_NARROW_MODE_SHIFT; + + config_reg |= RL << OMAP44XX_REG_CL_SHIFT; + + config_reg |= addressing->row_sz[cs0_device->io_width] << + OMAP44XX_REG_ROWSIZE_SHIFT; + + config_reg |= addressing->num_banks << OMAP44XX_REG_IBANK_SHIFT; + + config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) << + OMAP44XX_REG_EBANK_SHIFT; + + config_reg |= addressing->col_sz[cs0_device->io_width] << + OMAP44XX_REG_PAGESIZE_SHIFT; + + return config_reg; +} + +static u32 get_sdram_ref_ctrl(u32 freq, + const struct lpddr2_addressing *addressing) +{ + u32 ref_ctrl = 0, val = 0, freq_khz; + freq_khz = freq / 1000; + /* + * refresh rate to be set is 'tREFI * freq in MHz + * division by 10000 to account for khz and x10 in t_REFI_us_x10 + */ + val = addressing->t_REFI_us_x10 * freq_khz / 10000; + ref_ctrl |= val << OMAP44XX_REG_REFRESH_RATE_SHIFT; + + return ref_ctrl; +} + +static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings, + const struct lpddr2_min_tck *min_tck, + const struct lpddr2_addressing *addressing) +{ + u32 tim1 = 0, val = 0; + val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1; + tim1 |= val << OMAP44XX_REG_T_WTR_SHIFT; + + if (addressing->num_banks == BANKS8) + val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) / + (4 * (*T_num)) - 1; + else + val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1; + + tim1 |= val << OMAP44XX_REG_T_RRD_SHIFT; + + val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1; + tim1 |= val << OMAP44XX_REG_T_RC_SHIFT; + + val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1; + tim1 |= val << OMAP44XX_REG_T_RAS_SHIFT; + + val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1; + tim1 |= val << OMAP44XX_REG_T_WR_SHIFT; + + val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1; + tim1 |= val << OMAP44XX_REG_T_RCD_SHIFT; + + val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1; + tim1 |= val << OMAP44XX_REG_T_RP_SHIFT; + + return tim1; +} + +static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings, + const struct lpddr2_min_tck *min_tck) +{ + u32 tim2 = 0, val = 0; + val = max(min_tck->tCKE, timings->tCKE) - 1; + tim2 |= val << OMAP44XX_REG_T_CKE_SHIFT; + + val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1; + tim2 |= val << OMAP44XX_REG_T_RTP_SHIFT; + + /* + * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the + * same value + */ + val = ns_2_cycles(timings->tXSR) - 1; + tim2 |= val << OMAP44XX_REG_T_XSRD_SHIFT; + tim2 |= val << OMAP44XX_REG_T_XSNR_SHIFT; + + val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1; + tim2 |= val << OMAP44XX_REG_T_XP_SHIFT; + + return tim2; +} + +static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings, + const struct lpddr2_min_tck *min_tck, + const struct lpddr2_addressing *addressing) +{ + u32 tim3 = 0, val = 0; + val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF); + tim3 |= val << OMAP44XX_REG_T_RAS_MAX_SHIFT; + + val = ns_2_cycles(timings->tRFCab) - 1; + tim3 |= val << OMAP44XX_REG_T_RFC_SHIFT; + + val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1; + tim3 |= val << OMAP44XX_REG_T_TDQSCKMAX_SHIFT; + + val = ns_2_cycles(timings->tZQCS) - 1; + tim3 |= val << OMAP44XX_REG_ZQ_ZQCS_SHIFT; + + val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1; + tim3 |= val << OMAP44XX_REG_T_CKESR_SHIFT; + + return tim3; +} + +static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device, + const struct lpddr2_addressing *addressing, + u8 volt_ramp) +{ + u32 zq = 0, val = 0; + if (volt_ramp) + val = + EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 / + addressing->t_REFI_us_x10; + else + val = + EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 / + addressing->t_REFI_us_x10; + zq |= val << OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT; + + zq |= (REG_ZQ_ZQCL_MULT - 1) << OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT; + + zq |= (REG_ZQ_ZQINIT_MULT - 1) << OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT; + + zq |= REG_ZQ_SFEXITEN_ENABLE << OMAP44XX_REG_ZQ_SFEXITEN_SHIFT; + + /* + * Assuming that two chipselects have a single calibration resistor + * If there are indeed two calibration resistors, then this flag should + * be enabled to take advantage of dual calibration feature. + * This data should ideally come from board files. But considering + * that none of the boards today have calibration resistors per CS, + * it would be an unnecessary overhead. + */ + zq |= REG_ZQ_DUALCALEN_DISABLE << OMAP44XX_REG_ZQ_DUALCALEN_SHIFT; + + zq |= REG_ZQ_CS0EN_ENABLE << OMAP44XX_REG_ZQ_CS0EN_SHIFT; + + zq |= (cs1_device ? 1 : 0) << OMAP44XX_REG_ZQ_CS1EN_SHIFT; + + return zq; +} + +static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device, + const struct lpddr2_addressing *addressing, + u8 is_derated) +{ + u32 alert = 0, interval; + interval = + TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10; + if (is_derated) + interval *= 4; + alert |= interval << OMAP44XX_REG_TA_REFINTERVAL_SHIFT; + + alert |= TEMP_ALERT_CONFIG_DEVCT_1 << OMAP44XX_REG_TA_DEVCNT_SHIFT; + + alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << OMAP44XX_REG_TA_DEVWDT_SHIFT; + + alert |= 1 << OMAP44XX_REG_TA_SFEXITEN_SHIFT; + + alert |= 1 << OMAP44XX_REG_TA_CS0EN_SHIFT; + + alert |= (cs1_device ? 1 : 0) << OMAP44XX_REG_TA_CS1EN_SHIFT; + + return alert; +} + +static u32 get_read_idle_ctrl_reg(u8 volt_ramp) +{ + u32 idle = 0, val = 0; + if (volt_ramp) + val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1; + else + /*Maximum value in normal conditions - suggested by hw team */ + val = 0x1FF; + idle |= val << OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT; + + idle |= EMIF_REG_READ_IDLE_LEN_VAL << OMAP44XX_REG_READ_IDLE_LEN_SHIFT; + + return idle; +} + +static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) +{ + u32 phy = 0, val = 0; + + phy |= (RL + 2) << OMAP44XX_REG_READ_LATENCY_SHIFT; + + if (freq <= 100000000) + val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS; + else if (freq <= 200000000) + val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ; + else + val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ; + phy |= val << OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT; + + /* Other fields are constant magic values. Hardcode them together */ + phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL << + OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT; + + return phy; +} + +static u32 get_emif_mem_size(struct emif_device_details *devices) +{ + u32 size_mbytes = 0, temp; + + if (!devices) + return 0; + + if (devices->cs0_device_details) { + temp = devices->cs0_device_details->density; + size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; + } + + if (devices->cs1_device_details) { + temp = devices->cs1_device_details->density; + size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; + } + /* convert to bytes */ + return size_mbytes << 20; +} + +/* Gets the encoding corresponding to a given DMM section size */ +u32 get_dmm_section_size_map(u32 section_size) +{ + /* + * Section size mapping: + * 0x0: 16-MiB section + * 0x1: 32-MiB section + * 0x2: 64-MiB section + * 0x3: 128-MiB section + * 0x4: 256-MiB section + * 0x5: 512-MiB section + * 0x6: 1-GiB section + * 0x7: 2-GiB section + */ + section_size >>= 24; /* divide by 16 MB */ + return log_2_n_round_down(section_size); +} + +static void emif_calculate_regs( + const struct emif_device_details *emif_dev_details, + u32 freq, struct emif_regs *regs) +{ + u32 temp, sys_freq; + const struct lpddr2_addressing *addressing; + const struct lpddr2_ac_timings *timings; + const struct lpddr2_min_tck *min_tck; + const struct lpddr2_device_details *cs0_dev_details = + emif_dev_details->cs0_device_details; + const struct lpddr2_device_details *cs1_dev_details = + emif_dev_details->cs1_device_details; + const struct lpddr2_device_timings *cs0_dev_timings = + emif_dev_details->cs0_device_timings; + + emif_assert(emif_dev_details); + emif_assert(regs); + /* + * You can not have a device on CS1 without one on CS0 + * So configuring EMIF without a device on CS0 doesn't + * make sense + */ + emif_assert(cs0_dev_details); + emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM); + /* + * If there is a device on CS1 it should be same type as CS0 + * (or NVM. But NVM is not supported in this driver yet) + */ + emif_assert((cs1_dev_details == NULL) || + (cs1_dev_details->type == LPDDR2_TYPE_NVM) || + (cs0_dev_details->type == cs1_dev_details->type)); + emif_assert(freq <= MAX_LPDDR2_FREQ); + + set_ddr_clk_period(freq); + + /* + * The device on CS0 is used for all timing calculations + * There is only one set of registers for timings per EMIF. So, if the + * second CS(CS1) has a device, it should have the same timings as the + * device on CS0 + */ + timings = get_timings_table(cs0_dev_timings->ac_timings, freq); + emif_assert(timings); + min_tck = cs0_dev_timings->min_tck; + + temp = addressing_table_index(cs0_dev_details->type, + cs0_dev_details->density, + cs0_dev_details->io_width); + + emif_assert((temp >= 0)); + addressing = &(addressing_table[temp]); + emif_assert(addressing); + + sys_freq = get_sys_clk_freq(); + + regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details, + cs1_dev_details, + addressing, RL_BOOT); + + regs->sdram_config = get_sdram_config_reg(cs0_dev_details, + cs1_dev_details, + addressing, RL_FINAL); + + regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing); + + regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing); + + regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck); + + regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing); + + regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE); + + regs->temp_alert_config = + get_temp_alert_config(cs1_dev_details, addressing, 0); + + regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing, + LPDDR2_VOLTAGE_STABLE); + + regs->emif_ddr_phy_ctlr_1_init = + get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT); + + regs->emif_ddr_phy_ctlr_1 = + get_ddr_phy_ctrl_1(freq, RL_FINAL); + + regs->freq = freq; + + print_timing_reg(regs->sdram_config_init); + print_timing_reg(regs->sdram_config); + print_timing_reg(regs->ref_ctrl); + print_timing_reg(regs->sdram_tim1); + print_timing_reg(regs->sdram_tim2); + print_timing_reg(regs->sdram_tim3); + print_timing_reg(regs->read_idle_ctrl); + print_timing_reg(regs->temp_alert_config); + print_timing_reg(regs->zq_config); + print_timing_reg(regs->emif_ddr_phy_ctlr_1); + print_timing_reg(regs->emif_ddr_phy_ctlr_1_init); +} +#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ + +#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +/* Base AC Timing values specified by JESD209-2 for 400MHz operation */ +static const struct lpddr2_ac_timings timings_jedec_400_mhz = { + .max_freq = 400000000, + .RL = 6, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 15, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +/* Base AC Timing values specified by JESD209-2 for 333 MHz operation */ +static const struct lpddr2_ac_timings timings_jedec_333_mhz = { + .max_freq = 333000000, + .RL = 5, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 15, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */ +static const struct lpddr2_ac_timings timings_jedec_200_mhz = { + .max_freq = 200000000, + .RL = 3, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 20, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +/* + * Min tCK values specified by JESD209-2 + * Min tCK specifies the minimum duration of some AC timing parameters in terms + * of the number of cycles. If the calculated number of cycles based on the + * absolute time value is less than the min tCK value, min tCK value should + * be used instead. This typically happens at low frequencies. + */ +static const struct lpddr2_min_tck min_tck_jedec = { + .tRL = 3, + .tRP_AB = 3, + .tRCD = 3, + .tWR = 3, + .tRAS_MIN = 3, + .tRRD = 2, + .tWTR = 2, + .tXP = 2, + .tRTP = 2, + .tCKE = 3, + .tCKESR = 3, + .tFAW = 8 +}; + +static const struct lpddr2_ac_timings const* + jedec_ac_timings[MAX_NUM_SPEEDBINS] = { + &timings_jedec_200_mhz, + &timings_jedec_333_mhz, + &timings_jedec_400_mhz +}; + +static const struct lpddr2_device_timings jedec_default_timings = { + .ac_timings = jedec_ac_timings, + .min_tck = &min_tck_jedec +}; + +void emif_get_device_timings(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings) +{ + /* Assume Identical devices on EMIF1 & EMIF2 */ + *cs0_device_timings = &jedec_default_timings; + *cs1_device_timings = &jedec_default_timings; +} +#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ + +#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +const char *get_lpddr2_type(u8 type_id) +{ + switch (type_id) { + case LPDDR2_TYPE_S4: + return "LPDDR2-S4"; + case LPDDR2_TYPE_S2: + return "LPDDR2-S2"; + default: + return NULL; + } +} + +const char *get_lpddr2_io_width(u8 width_id) +{ + switch (width_id) { + case LPDDR2_IO_WIDTH_8: + return "x8"; + case LPDDR2_IO_WIDTH_16: + return "x16"; + case LPDDR2_IO_WIDTH_32: + return "x32"; + default: + return NULL; + } +} + +const char *get_lpddr2_manufacturer(u32 manufacturer) +{ + switch (manufacturer) { + case LPDDR2_MANUFACTURER_SAMSUNG: + return "Samsung"; + case LPDDR2_MANUFACTURER_QIMONDA: + return "Qimonda"; + case LPDDR2_MANUFACTURER_ELPIDA: + return "Elpida"; + case LPDDR2_MANUFACTURER_ETRON: + return "Etron"; + case LPDDR2_MANUFACTURER_NANYA: + return "Nanya"; + case LPDDR2_MANUFACTURER_HYNIX: + return "Hynix"; + case LPDDR2_MANUFACTURER_MOSEL: + return "Mosel"; + case LPDDR2_MANUFACTURER_WINBOND: + return "Winbond"; + case LPDDR2_MANUFACTURER_ESMT: + return "ESMT"; + case LPDDR2_MANUFACTURER_SPANSION: + return "Spansion"; + case LPDDR2_MANUFACTURER_SST: + return "SST"; + case LPDDR2_MANUFACTURER_ZMOS: + return "ZMOS"; + case LPDDR2_MANUFACTURER_INTEL: + return "Intel"; + case LPDDR2_MANUFACTURER_NUMONYX: + return "Numonyx"; + case LPDDR2_MANUFACTURER_MICRON: + return "Micron"; + default: + return NULL; + } +} + +static void display_sdram_details(u32 emif_nr, u32 cs, + struct lpddr2_device_details *device) +{ + const char *mfg_str; + const char *type_str; + char density_str[10]; + u32 density; + + debug("EMIF%d CS%d\t", emif_nr, cs); + + if (!device) { + debug("None\n"); + return; + } + + mfg_str = get_lpddr2_manufacturer(device->manufacturer); + type_str = get_lpddr2_type(device->type); + + density = lpddr2_density_2_size_in_mbytes[device->density]; + if ((density / 1024 * 1024) == density) { + density /= 1024; + sprintf(density_str, "%d GB", density); + } else + sprintf(density_str, "%d MB", density); + if (mfg_str && type_str) + debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str); +} + +static u8 is_lpddr2_sdram_present(u32 base, u32 cs, + struct lpddr2_device_details *lpddr2_device) +{ + u32 mr = 0, temp; + + mr = get_mr(base, cs, LPDDR2_MR0); + if (mr > 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT; + if (temp) { + /* Not SDRAM */ + return 0; + } + temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT; + + if (temp) { + /* DNV supported - But DNV is only supported for NVM */ + return 0; + } + + mr = get_mr(base, cs, LPDDR2_MR4); + if (mr > 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + mr = get_mr(base, cs, LPDDR2_MR5); + if (mr >= 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + if (!get_lpddr2_manufacturer(mr)) { + /* Manufacturer not identified */ + return 0; + } + lpddr2_device->manufacturer = mr; + + mr = get_mr(base, cs, LPDDR2_MR6); + if (mr >= 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + mr = get_mr(base, cs, LPDDR2_MR7); + if (mr >= 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + mr = get_mr(base, cs, LPDDR2_MR8); + if (mr >= 0xFF) { + /* Mode register value bigger than 8 bit */ + return 0; + } + + temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT; + if (!get_lpddr2_type(temp)) { + /* Not SDRAM */ + return 0; + } + lpddr2_device->type = temp; + + temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT; + if (temp > LPDDR2_DENSITY_32Gb) { + /* Density not supported */ + return 0; + } + lpddr2_device->density = temp; + + temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT; + if (!get_lpddr2_io_width(temp)) { + /* IO width unsupported value */ + return 0; + } + lpddr2_device->io_width = temp; + + /* + * If all the above tests pass we should + * have a device on this chip-select + */ + return 1; +} + +static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs, + struct lpddr2_device_details *lpddr2_dev_details) +{ + u32 phy; + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + if (!lpddr2_dev_details) + return NULL; + + /* Do the minimum init for mode register accesses */ + if (!running_from_sdram()) { + phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT); + writel(phy, &emif->emif_ddr_phy_ctrl_1); + } + + if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details))) + return NULL; + + display_sdram_details(emif_num(base), cs, lpddr2_dev_details); + + return lpddr2_dev_details; +} + +void emif_get_device_details(u32 emif_nr, + struct lpddr2_device_details *cs0_device_details, + struct lpddr2_device_details *cs1_device_details) +{ + u32 base = (emif_nr == 1) ? OMAP44XX_EMIF1 : OMAP44XX_EMIF2; + + if (running_from_sdram()) { + /* + * We can not do automatic discovery running from SDRAM + * Most likely we came here by mistake. Indicate error + * by returning NULL + */ + cs0_device_details = NULL; + cs1_device_details = NULL; + } else { + /* + * Automatically find the device details: + * + * Reset the PHY after each call to get_lpddr2_details(). + * If there is nothing connected to a given chip select + * (typically CS1) mode register reads will mess up with + * the PHY state and subsequent initialization won't work. + * PHY reset brings back PHY to a good state. + */ + cs0_device_details = + get_lpddr2_details(base, CS0, cs0_device_details); + emif_reset_phy(base); + + cs1_device_details = + get_lpddr2_details(base, CS1, cs1_device_details); + emif_reset_phy(base); + } +} +#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */ + +static void do_sdram_init(u32 base) +{ + const struct emif_regs *regs; + u32 in_sdram, emif_nr; + + debug(">>do_sdram_init() %x\n", base); + + in_sdram = running_from_sdram(); + emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2; + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS + emif_get_reg_dump(emif_nr, ®s); + if (!regs) { + debug("EMIF: reg dump not provided\n"); + return; + } +#else + /* + * The user has not provided the register values. We need to + * calculate it based on the timings and the DDR frequency + */ + struct emif_device_details dev_details; + struct emif_regs calculated_regs; + + /* + * Get device details: + * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set + * - Obtained from user otherwise + */ + struct lpddr2_device_details cs0_dev_details, cs1_dev_details; + emif_get_device_details(emif_nr, &cs0_dev_details, + &cs1_dev_details); + dev_details.cs0_device_details = &cs0_dev_details; + dev_details.cs1_device_details = &cs1_dev_details; + + /* Return if no devices on this EMIF */ + if (!dev_details.cs0_device_details && + !dev_details.cs1_device_details) { + emif_sizes[emif_nr - 1] = 0; + return; + } + + if (!in_sdram) + emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details); + + /* + * Get device timings: + * - Default timings specified by JESD209-2 if + * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set + * - Obtained from user otherwise + */ + emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings, + &dev_details.cs1_device_timings); + + /* Calculate the register values */ + emif_calculate_regs(&dev_details, omap4_ddr_clk(), &calculated_regs); + regs = &calculated_regs; +#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ + + /* + * Initializing the LPDDR2 device can not happen from SDRAM. + * Changing the timing registers in EMIF can happen(going from one + * OPP to another) + */ + if (!in_sdram) + lpddr2_init(base, regs); + + /* Write to the shadow registers */ + emif_update_timings(base, regs); + + debug("<<do_sdram_init() %x\n", base); +} + +void sdram_init_pads(void) +{ + u32 lpddr2io; + struct control_lpddr2io_regs *lpddr2io_regs = + (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE; + u32 omap4_rev = omap_revision(); + + if (omap4_rev == OMAP4430_ES1_0) + lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN; + else if (omap4_rev == OMAP4430_ES2_0) + lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER; + else + return; /* Post ES2.1 reset values will work */ + + writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0); + writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1); + writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_2); + writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0); + writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1); + writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_2); + + writel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2); +} + +static void emif_post_init_config(u32 base) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 omap4_rev = omap_revision(); + + /* reset phy on ES2.0 */ + if (omap4_rev == OMAP4430_ES2_0) + emif_reset_phy(base); + + /* Put EMIF back in smart idle on ES1.0 */ + if (omap4_rev == OMAP4430_ES1_0) + writel(0x80000000, &emif->emif_pwr_mgmt_ctrl); +} + +static void dmm_init(u32 base) +{ + const struct dmm_lisa_map_regs *lisa_map_regs; + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS + emif_get_dmm_regs(&lisa_map_regs); +#else + u32 emif1_size, emif2_size, mapped_size, section_map = 0; + u32 section_cnt, sys_addr; + struct dmm_lisa_map_regs lis_map_regs_calculated = {0}; + + mapped_size = 0; + section_cnt = 3; + sys_addr = CONFIG_SYS_SDRAM_BASE; + emif1_size = emif_sizes[0]; + emif2_size = emif_sizes[1]; + debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size); + + if (!emif1_size && !emif2_size) + return; + + /* symmetric interleaved section */ + if (emif1_size && emif2_size) { + mapped_size = min(emif1_size, emif2_size); + section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL; + section_map |= 0 << OMAP44XX_SDRC_ADDR_SHIFT; + /* only MSB */ + section_map |= (sys_addr >> 24) << + OMAP44XX_SYS_ADDR_SHIFT; + section_map |= get_dmm_section_size_map(mapped_size * 2) + << OMAP44XX_SYS_SIZE_SHIFT; + lis_map_regs_calculated.dmm_lisa_map_3 = section_map; + emif1_size -= mapped_size; + emif2_size -= mapped_size; + sys_addr += (mapped_size * 2); + section_cnt--; + } + + /* + * Single EMIF section(we can have a maximum of 1 single EMIF + * section- either EMIF1 or EMIF2 or none, but not both) + */ + if (emif1_size) { + section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL; + section_map |= get_dmm_section_size_map(emif1_size) + << OMAP44XX_SYS_SIZE_SHIFT; + /* only MSB */ + section_map |= (mapped_size >> 24) << + OMAP44XX_SDRC_ADDR_SHIFT; + /* only MSB */ + section_map |= (sys_addr >> 24) << OMAP44XX_SYS_ADDR_SHIFT; + section_cnt--; + } + if (emif2_size) { + section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL; + section_map |= get_dmm_section_size_map(emif2_size) << + OMAP44XX_SYS_SIZE_SHIFT; + /* only MSB */ + section_map |= mapped_size >> 24 << OMAP44XX_SDRC_ADDR_SHIFT; + /* only MSB */ + section_map |= sys_addr >> 24 << OMAP44XX_SYS_ADDR_SHIFT; + section_cnt--; + } + + if (section_cnt == 2) { + /* Only 1 section - either symmetric or single EMIF */ + lis_map_regs_calculated.dmm_lisa_map_3 = section_map; + lis_map_regs_calculated.dmm_lisa_map_2 = 0; + lis_map_regs_calculated.dmm_lisa_map_1 = 0; + } else { + /* 2 sections - 1 symmetric, 1 single EMIF */ + lis_map_regs_calculated.dmm_lisa_map_2 = section_map; + lis_map_regs_calculated.dmm_lisa_map_1 = 0; + } + + /* TRAP for invalid TILER mappings in section 0 */ + lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP; + + lisa_map_regs = &lis_map_regs_calculated; +#endif + struct dmm_lisa_map_regs *hw_lisa_map_regs = + (struct dmm_lisa_map_regs *)base; + + writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); + + writel(lisa_map_regs->dmm_lisa_map_3, + &hw_lisa_map_regs->dmm_lisa_map_3); + writel(lisa_map_regs->dmm_lisa_map_2, + &hw_lisa_map_regs->dmm_lisa_map_2); + writel(lisa_map_regs->dmm_lisa_map_1, + &hw_lisa_map_regs->dmm_lisa_map_1); + writel(lisa_map_regs->dmm_lisa_map_0, + &hw_lisa_map_regs->dmm_lisa_map_0); + + if (omap_revision() >= OMAP4460_ES1_0) { + hw_lisa_map_regs = + (struct dmm_lisa_map_regs *)OMAP44XX_MA_LISA_MAP_BASE; + + writel(lisa_map_regs->dmm_lisa_map_3, + &hw_lisa_map_regs->dmm_lisa_map_3); + writel(lisa_map_regs->dmm_lisa_map_2, + &hw_lisa_map_regs->dmm_lisa_map_2); + writel(lisa_map_regs->dmm_lisa_map_1, + &hw_lisa_map_regs->dmm_lisa_map_1); + writel(lisa_map_regs->dmm_lisa_map_0, + &hw_lisa_map_regs->dmm_lisa_map_0); + } +} + +/* + * SDRAM initialization: + * SDRAM initialization has two parts: + * 1. Configuring the SDRAM device + * 2. Update the AC timings related parameters in the EMIF module + * (1) should be done only once and should not be done while we are + * running from SDRAM. + * (2) can and should be done more than once if OPP changes. + * Particularly, this may be needed when we boot without SPL and + * and using Configuration Header(CH). ROM code supports only at 50% OPP + * at boot (low power boot). So u-boot has to switch to OPP100 and update + * the frequency. So, + * Doing (1) and (2) makes sense - first time initialization + * Doing (2) and not (1) makes sense - OPP change (when using CH) + * Doing (1) and not (2) doen't make sense + * See do_sdram_init() for the details + */ +void sdram_init(void) +{ + u32 in_sdram, size_prog, size_detect; + + debug(">>sdram_init()\n"); + + if (omap4_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) + return; + + in_sdram = running_from_sdram(); + debug("in_sdram = %d\n", in_sdram); + + if (!in_sdram) { + sdram_init_pads(); + bypass_dpll(&prcm->cm_clkmode_dpll_core); + } + + do_sdram_init(OMAP44XX_EMIF1); + do_sdram_init(OMAP44XX_EMIF2); + + if (!in_sdram) { + dmm_init(OMAP44XX_DMM_LISA_MAP_BASE); + emif_post_init_config(OMAP44XX_EMIF1); + emif_post_init_config(OMAP44XX_EMIF2); + + } + + /* for the shadow registers to take effect */ + freq_update_core(); + + /* Do some testing after the init */ + if (!in_sdram) { + size_prog = omap4_sdram_size(); + size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + size_prog); + /* Compare with the size programmed */ + if (size_detect != size_prog) { + printf("SDRAM: identified size not same as expected" + " size identified: %x expected: %x\n", + size_detect, + size_prog); + } else + debug("get_ram_size() successful"); + } + + debug("<<sdram_init()\n"); +} diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S index 026dfa4..91525ec 100644 --- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S @@ -27,6 +27,37 @@ */ #include <asm/arch/omap4.h> +#ifdef CONFIG_SPL_BUILD +.global save_boot_params +save_boot_params: + /* + * See if the rom code passed pointer is valid: + * It is not valid if it is not in non-secure SRAM + * This may happen if you are booting with the help of + * debugger + */ + ldr r2, =NON_SECURE_SRAM_START + cmp r2, r0 + bgt 1f + ldr r2, =NON_SECURE_SRAM_END + cmp r2, r0 + blt 1f + + /* Store the boot device in omap4_boot_device */ + ldr r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device + and r2, #BOOT_DEVICE_MASK + ldr r3, =omap4_boot_device + str r2, [r3] @ omap4_boot_device <- r1 + + /* Store the boot mode (raw/FAT) in omap4_boot_mode */ + ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr + ldr r2, [r2, #DEV_DATA_PTR_OFFSET] @ get the pDeviceData ptr + ldr r2, [r2, #BOOT_MODE_OFFSET] @ get the boot mode + ldr r3, =omap4_boot_mode + str r2, [r3] +1: + bx lr +#endif .globl lowlevel_init lowlevel_init: @@ -45,3 +76,12 @@ lowlevel_init: */ bl s_init pop {ip, pc} + +.globl set_pl310_ctrl_reg +set_pl310_ctrl_reg: + PUSH {r4-r11, lr} @ save registers - ROM code may pollute + @ our registers + LDR r12, =0x102 @ Set PL310 control register - value in R0 + .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 + @ call ROM Code API to set control register + POP {r4-r11, pc} diff --git a/arch/arm/cpu/armv7/omap4/omap4_mux_data.h b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h new file mode 100644 index 0000000..00c52f8 --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h @@ -0,0 +1,76 @@ + /* + * (C) Copyright 2010 + * Texas Instruments Incorporated, <www.ti.com> + * + * Balaji Krishnamoorthy <balajitk@ti.com> + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP4_MUX_DATA_H_ +#define _OMAP4_MUX_DATA_H_ + +#include <asm/arch/mux_omap4.h> + +const struct pad_conf_entry core_padconf_array_essential[] = { + +{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ +{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ +{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ +{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ +{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ +{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ +{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ +{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ +{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ +{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ +{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ +{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ +{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ +{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ +{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ +{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ +{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ +{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ +{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ +{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ +{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ +{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ +{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ +{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ +{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ +{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ +{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ +{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ +{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ +{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ +{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ +{UART3_TX_IRTX, (M0)} /* uart3_tx */ + +}; + +const struct pad_conf_entry wkup_padconf_array_essential[] = { + +{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ +{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ +{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ + +}; + +#endif /* _OMAP4_MUX_DATA_H_ */ diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c new file mode 100644 index 0000000..7757aad --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -0,0 +1,282 @@ +/* + * Timing and Organization details of the Elpida parts used in OMAP4 + * SDPs and Panda + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/emif.h> +#include <asm/arch/sys_proto.h> + +/* + * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430 + * SDP and Panda. Since the parts used and geometry are identical for + * SDP and Panda for a given OMAP4 revision, this information is kept + * here instead of being in board directory. However the key functions + * exported are weakly linked so that they can be over-ridden in the board + * directory if there is a OMAP4 board in the future that uses a different + * memory device or geometry. + * + * For any new board with different memory devices over-ride one or more + * of the following functions as per the CONFIG flags you intend to enable: + * - emif_get_reg_dump() + * - emif_get_dmm_regs() + * - emif_get_device_details() + * - emif_get_device_timings() + */ + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS + +static const struct emif_regs emif_regs_elpida_200_mhz_2cs = { + .sdram_config_init = 0x80000eb9, + .sdram_config = 0x80001ab9, + .ref_ctrl = 0x0000030c, + .sdram_tim1 = 0x08648311, + .sdram_tim2 = 0x101b06ca, + .sdram_tim3 = 0x0048a19f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3214, + .temp_alert_config = 0xd8016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff808 +}; + +static const struct emif_regs emif_regs_elpida_380_mhz_1cs = { + .sdram_config_init = 0x80000eb1, + .sdram_config = 0x80001ab1, + .ref_ctrl = 0x000005cd, + .sdram_tim1 = 0x10cb0622, + .sdram_tim2 = 0x20350d52, + .sdram_tim3 = 0x00b1431f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3214, + .temp_alert_config = 0x58016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; + +const struct emif_regs emif_regs_elpida_400_mhz_2cs = { + .sdram_config_init = 0x80000eb9, + .sdram_config = 0x80001ab9, + .ref_ctrl = 0x00000618, + .sdram_tim1 = 0x10eb0662, + .sdram_tim2 = 0x20370dd2, + .sdram_tim3 = 0x00b1c33f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0xd00b3214, + .temp_alert_config = 0xd8016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; +const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80540300 +}; + +const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80640300 +}; + +static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) +{ + u32 omap4_rev = omap_revision(); + + /* Same devices and geometry on both EMIFs */ + if (omap4_rev == OMAP4430_ES1_0) + *regs = &emif_regs_elpida_380_mhz_1cs; + else if (omap4_rev == OMAP4430_ES2_0) + *regs = &emif_regs_elpida_200_mhz_2cs; + else + *regs = &emif_regs_elpida_400_mhz_2cs; +} +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) + __attribute__((weak, alias("emif_get_reg_dump_sdp"))); + +static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs + **dmm_lisa_regs) +{ + u32 omap_rev = omap_revision(); + + if (omap_rev == OMAP4430_ES1_0) + *dmm_lisa_regs = &lisa_map_2G_x_1_x_2; + else + *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; +} + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) + __attribute__((weak, alias("emif_get_dmm_regs_sdp"))); + +#else + +static const struct lpddr2_device_details elpida_2G_S4_details = { + .type = LPDDR2_TYPE_S4, + .density = LPDDR2_DENSITY_2Gb, + .io_width = LPDDR2_IO_WIDTH_32, + .manufacturer = LPDDR2_MANUFACTURER_ELPIDA +}; + +static void emif_get_device_details_sdp(u32 emif_nr, + struct lpddr2_device_details *cs0_device_details, + struct lpddr2_device_details *cs1_device_details) +{ + u32 omap_rev = omap_revision(); + + /* EMIF1 & EMIF2 have identical configuration */ + *cs0_device_details = elpida_2G_S4_details; + + if (omap_rev == OMAP4430_ES1_0) + cs1_device_details = NULL; + else + *cs1_device_details = elpida_2G_S4_details; +} + +void emif_get_device_details(u32 emif_nr, + struct lpddr2_device_details *cs0_device_details, + struct lpddr2_device_details *cs1_device_details) + __attribute__((weak, alias("emif_get_device_details_sdp"))); + +#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ + +#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +static const struct lpddr2_ac_timings timings_elpida_400_mhz = { + .max_freq = 400000000, + .RL = 6, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 15, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +static const struct lpddr2_ac_timings timings_elpida_333_mhz = { + .max_freq = 333000000, + .RL = 5, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 15, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +static const struct lpddr2_ac_timings timings_elpida_200_mhz = { + .max_freq = 200000000, + .RL = 3, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 20, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +static const struct lpddr2_min_tck min_tck_elpida = { + .tRL = 3, + .tRP_AB = 3, + .tRCD = 3, + .tWR = 3, + .tRAS_MIN = 3, + .tRRD = 2, + .tWTR = 2, + .tXP = 2, + .tRTP = 2, + .tCKE = 3, + .tCKESR = 3, + .tFAW = 8 +}; + +static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = { + &timings_elpida_200_mhz, + &timings_elpida_333_mhz, + &timings_elpida_400_mhz +}; + +static const struct lpddr2_device_timings elpida_2G_S4_timings = { + .ac_timings = elpida_ac_timings, + .min_tck = &min_tck_elpida, +}; + +void emif_get_device_timings_sdp(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings) +{ + u32 omap_rev = omap_revision(); + + /* Identical devices on EMIF1 & EMIF2 */ + *cs0_device_timings = &elpida_2G_S4_timings; + + if (omap_rev == OMAP4430_ES1_0) + *cs1_device_timings = NULL; + else + *cs1_device_timings = &elpida_2G_S4_timings; +} + +void emif_get_device_timings(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings) + __attribute__((weak, alias("emif_get_device_timings_sdp"))); + +#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c index b750d16..359c21f 100644 --- a/arch/arm/cpu/armv7/s5p-common/timer.c +++ b/arch/arm/cpu/armv7/s5p-common/timer.c @@ -50,21 +50,11 @@ int timer_init(void) /* * timer without interrupts */ -void reset_timer(void) -{ - reset_timer_masked(); -} - unsigned long get_timer(unsigned long base) { return get_timer_masked() - base; } -void set_timer(unsigned long t) -{ - gd->tbl = t; -} - /* delay x useconds */ void __udelay(unsigned long usec) { diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S index 7734b32..c7d6221 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/cache.S +++ b/arch/arm/cpu/armv7/s5pc1xx/cache.S @@ -23,98 +23,22 @@ * MA 02111-1307 USA */ -#include <asm/arch/cpu.h> - .align 5 -.global invalidate_dcache -.global l2_cache_enable -.global l2_cache_disable - -/* - * invalidate_dcache() - * Invalidate the whole D-cache. - * - * Corrupted registers: r0-r5, r7, r9-r11 - */ -invalidate_dcache: - stmfd r13!, {r0 - r5, r7, r9 - r12, r14} - - cmp r0, #0xC100 @ check if the cpu is s5pc100 - - beq finished_inval @ s5pc100 doesn't need this - @ routine - mrc p15, 1, r0, c0, c0, 1 @ read clidr - ands r3, r0, #0x7000000 @ extract loc from clidr - mov r3, r3, lsr #23 @ left align loc bit field - beq finished_inval @ if loc is 0, then no need to - @ clean - mov r10, #0 @ start clean at cache level 0 -inval_loop1: - add r2, r10, r10, lsr #1 @ work out 3x current cache - @ level - mov r1, r0, lsr r2 @ extract cache type bits from - @ clidr - and r1, r1, #7 @ mask of the bits for current - @ cache only - cmp r1, #2 @ see what cache we have at - @ this level - blt skip_inval @ skip if no cache, or just - @ i-cache - mcr p15, 2, r10, c0, c0, 0 @ select current cache level - @ in cssr - mov r2, #0 @ operand for mcr SBZ - mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to - @ sych the new cssr&csidr, - @ with armv7 this is 'isb', - @ but we compile with armv5 - mrc p15, 1, r1, c0, c0, 0 @ read the new csidr - and r2, r1, #7 @ extract the length of the - @ cache lines - add r2, r2, #4 @ add 4 (line length offset) - ldr r4, =0x3ff - ands r4, r4, r1, lsr #3 @ find maximum number on the - @ way size - clz r5, r4 @ find bit position of way - @ size increment - ldr r7, =0x7fff - ands r7, r7, r1, lsr #13 @ extract max number of the - @ index size -inval_loop2: - mov r9, r4 @ create working copy of max - @ way size -inval_loop3: - orr r11, r10, r9, lsl r5 @ factor way and cache number - @ into r11 - orr r11, r11, r7, lsl r2 @ factor index number into r11 - mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way - subs r9, r9, #1 @ decrement the way - bge inval_loop3 - subs r7, r7, #1 @ decrement the index - bge inval_loop2 -skip_inval: - add r10, r10, #2 @ increment cache number - cmp r3, r10 - bgt inval_loop1 -finished_inval: - mov r10, #0 @ swith back to cache level 0 - mcr p15, 2, r10, c0, c0, 0 @ select current cache level - @ in cssr - mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, - @ with armv7 this is 'isb', - @ but we compile with armv5 - - ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} -l2_cache_enable: +#ifndef CONFIG_SYS_L2CACHE_OFF +.global v7_outer_cache_enable +v7_outer_cache_enable: push {r0, r1, r2, lr} mrc 15, 0, r3, cr1, cr0, 1 orr r3, r3, #2 mcr 15, 0, r3, cr1, cr0, 1 pop {r1, r2, r3, pc} -l2_cache_disable: +.global v7_outer_cache_disable +v7_outer_cache_disable: push {r0, r1, r2, lr} mrc 15, 0, r3, cr1, cr0, 1 bic r3, r3, #2 mcr 15, 0, r3, cr1, cr0, 1 pop {r1, r2, r3, pc} +#endif diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index d91ae12..db8e9d2 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -42,7 +42,16 @@ _start: b reset ldr pc, _not_used ldr pc, _irq ldr pc, _fiq - +#ifdef CONFIG_SPL_BUILD +_undefined_instruction: .word _undefined_instruction +_software_interrupt: .word _software_interrupt +_prefetch_abort: .word _prefetch_abort +_data_abort: .word _data_abort +_not_used: .word _not_used +_irq: .word _irq +_fiq: .word _fiq +_pad: .word 0x12345678 /* now 16*4=64 */ +#else _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort @@ -51,6 +60,8 @@ _not_used: .word not_used _irq: .word irq _fiq: .word fiq _pad: .word 0x12345678 /* now 16*4=64 */ +#endif /* CONFIG_SPL_BUILD */ + .global _end_vect _end_vect: @@ -89,6 +100,10 @@ _armboot_start: _bss_start_ofs: .word __bss_start - _start +.global _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: .word __bss_end__ - _start @@ -119,6 +134,7 @@ IRQ_STACK_START_IN: */ reset: + bl save_boot_params /* * set the cpu to SVC32 mode */ @@ -182,12 +198,11 @@ stack_setup: mov sp, r4 adr r0, _start -#ifndef CONFIG_PRELOADER cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ -#endif mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ copy_loop: @@ -196,7 +211,7 @@ copy_loop: cmp r0, r2 /* until source end address [r2] */ blo copy_loop -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* * fix .rel.dyn relocations */ @@ -235,26 +250,48 @@ fixnext: add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ cmp r2, r3 blo fixloop + b clear_bss +_rel_dyn_start_ofs: + .word __rel_dyn_start - _start +_rel_dyn_end_ofs: + .word __rel_dyn_end - _start +_dynsym_start_ofs: + .word __dynsym_start - _start + +#endif /* #ifndef CONFIG_SPL_BUILD */ clear_bss: +#ifdef CONFIG_SPL_BUILD + /* No relocation for SPL */ + ldr r0, =__bss_start + ldr r1, =__bss_end__ +#else ldr r0, _bss_start_ofs ldr r1, _bss_end_ofs mov r4, r6 /* reloc addr */ add r0, r0, r4 add r1, r1, r4 +#endif mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 bne clbss_l -#endif /* #ifndef CONFIG_PRELOADER */ /* * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ jump_2_ram: +/* + * If I-cache is enabled invalidate it + */ +#ifndef CONFIG_SYS_ICACHE_OFF + mcr p15, 0, r0, c7, c5, 0 @ invalidate icache + mcr p15, 0, r0, c7, c10, 4 @ DSB + mcr p15, 0, r0, c7, c5, 4 @ ISB +#endif ldr r0, _board_init_r_ofs adr r1, _start add lr, r0, r1 @@ -268,13 +305,8 @@ jump_2_ram: _board_init_r_ofs: .word board_init_r - _start -_rel_dyn_start_ofs: - .word __rel_dyn_start - _start -_rel_dyn_end_ofs: - .word __rel_dyn_end - _start -_dynsym_start_ofs: - .word __dynsym_start - _start +#ifndef CONFIG_SKIP_LOWLEVEL_INIT /************************************************************************* * * CPU_init_critical registers @@ -290,6 +322,9 @@ cpu_init_crit: mov r0, #0 @ set up for MCR mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs mcr p15, 0, r0, c7, c5, 0 @ invalidate icache + mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array + mcr p15, 0, r0, c7, c10, 4 @ DSB + mcr p15, 0, r0, c7, c5, 4 @ ISB /* * disable MMU stuff and caches @@ -298,7 +333,12 @@ cpu_init_crit: bic r0, r0, #0x00002000 @ clear bits 13 (--V-) bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align - orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB + orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB +#ifdef CONFIG_SYS_ICACHE_OFF + bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache +#else + orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache +#endif mcr p15, 0, r0, c1, c0, 0 /* @@ -311,6 +351,9 @@ cpu_init_crit: bl lowlevel_init @ go setup pll,mux,memory mov lr, ip @ restore link mov pc, lr @ back to my caller +#endif + +#ifndef CONFIG_SPL_BUILD /* ************************************************************************* * @@ -498,4 +541,5 @@ fiq: bad_save_user_regs bl do_fiq -#endif +#endif /* CONFIG_USE_IRQ */ +#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/armv7/tegra2/timer.c b/arch/arm/cpu/armv7/tegra2/timer.c index fb061d0..0b9fa64 100644 --- a/arch/arm/cpu/armv7/tegra2/timer.c +++ b/arch/arm/cpu/armv7/tegra2/timer.c @@ -48,21 +48,11 @@ struct timerus *timer_base = (struct timerus *)NV_PA_TMRUS_BASE; #define TIMER_LOAD_VAL 0xffffffff /* timer without interrupts */ -void reset_timer(void) -{ - reset_timer_masked(); -} - ulong get_timer(ulong base) { return get_timer_masked() - base; } -void set_timer(ulong t) -{ - gd->tbl = t; -} - /* delay x useconds */ void __udelay(unsigned long usec) { @@ -79,13 +69,6 @@ void __udelay(unsigned long usec) } } -void reset_timer_masked(void) -{ - /* reset time, capture current incrementer value time */ - gd->lastinc = readl(&timer_base->cntr_1us) / (TIMER_CLK/CONFIG_SYS_HZ); - gd->tbl = 0; /* start "advancing" time stamp from 0 */ -} - ulong get_timer_masked(void) { ulong now; diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds index dbae54d..40ecf78 100644 --- a/arch/arm/cpu/armv7/u-boot.lds +++ b/arch/arm/cpu/armv7/u-boot.lds @@ -55,6 +55,8 @@ SECTIONS . = ALIGN(4); + __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/arch/arm/cpu/armv7/u8500/timer.c b/arch/arm/cpu/armv7/u8500/timer.c index 8e96eaa..79aad99 100644 --- a/arch/arm/cpu/armv7/u8500/timer.c +++ b/arch/arm/cpu/armv7/u8500/timer.c @@ -129,11 +129,6 @@ ulong get_timer(ulong base) return get_timer_masked() - base; } -void set_timer(ulong t) -{ - gd->tbl = t; -} - /* * Emulation of Power architecture long long timebase. * diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk index deca3f4..5868cba 100644 --- a/arch/arm/cpu/ixp/config.mk +++ b/arch/arm/cpu/ixp/config.mk @@ -27,6 +27,11 @@ BIG_ENDIAN = y PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -mbig-endian PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100 + +# -fdata-sections triggers "section .bss overlaps section .rel.dyn" linker error +PLATFORM_RELFLAGS += -ffunction-sections +LDFLAGS_u-boot += --gc-sections + # ========================================================================= # # Supply options according to compiler version diff --git a/arch/arm/cpu/ixp/cpu.c b/arch/arm/cpu/ixp/cpu.c index ce275e5..942845d 100644 --- a/arch/arm/cpu/ixp/cpu.c +++ b/arch/arm/cpu/ixp/cpu.c @@ -36,8 +36,6 @@ #include <asm/arch/ixp425.h> #include <asm/system.h> -ulong loops_per_jiffy; - static void cache_flush(void); #if defined(CONFIG_DISPLAY_CPUINFO) @@ -51,17 +49,14 @@ int print_cpuinfo (void) puts("CPU: Intel IXP425 at "); switch ((id & 0x000003f0) >> 4) { case 0x1c: - loops_per_jiffy = 887467; speed = 533; break; case 0x1d: - loops_per_jiffy = 666016; speed = 400; break; case 0x1f: - loops_per_jiffy = 442901; speed = 266; break; } diff --git a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c b/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c index 09f69ce..642e67a 100644 --- a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c +++ b/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c @@ -386,7 +386,7 @@ ixQMgrNotificationEnable (IxQMgrQId qId, &dispatchQInfo[qId].statusMask); - /* Set the interupt source is this queue is in the range 0-31 */ + /* Set the interrupt source is this queue is in the range 0-31 */ if (qId < IX_QMGR_MIN_QUEUPP_QID) { ixQMgrAqmIfIntSrcSelWrite (qId, srcSel); diff --git a/arch/arm/cpu/ixp/npe/Makefile b/arch/arm/cpu/ixp/npe/Makefile index c756a1d..14ab3c7 100644 --- a/arch/arm/cpu/ixp/npe/Makefile +++ b/arch/arm/cpu/ixp/npe/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libnpe.o LOCAL_CFLAGS += -I$(TOPDIR)/arch/arm/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux CFLAGS += $(LOCAL_CFLAGS) +CPPFLAGS += $(LOCAL_CFLAGS) # needed for depend HOSTCFLAGS += $(LOCAL_CFLAGS) COBJS-$(CONFIG_IXP4XX_NPE) := npe.o \ diff --git a/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h b/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h index 0ee4123..4e0de82 100644 --- a/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h +++ b/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h @@ -279,7 +279,7 @@ typedef struct BOOL portInitialized; UINT32 npeId; /**< NpeId for this port */ IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */ - IxEthAccRxDataInfo ixEthAccRxData; /**< Recieve data control structures */ + IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */ } IxEthAccPortDataInfo; extern IxEthAccPortDataInfo ixEthAccPortData[]; diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeA.h b/arch/arm/cpu/ixp/npe/include/IxNpeA.h index 7427cc4..90669c2 100644 --- a/arch/arm/cpu/ixp/npe/include/IxNpeA.h +++ b/arch/arm/cpu/ixp/npe/include/IxNpeA.h @@ -717,7 +717,7 @@ typedef struct */ typedef struct { - UINT32 rxBitField; /**< Recieved bit field */ + UINT32 rxBitField; /**< Received bit field */ UINT32 atmCellHeader; /**< ATM Cell Header */ UINT32 rsvdWord0; /**< Reserved field */ UINT16 currMbufLen; /**< Mbuf Length */ diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgr.h b/arch/arm/cpu/ixp/npe/include/IxQMgr.h index 165ed96..03d7e07 100644 --- a/arch/arm/cpu/ixp/npe/include/IxQMgr.h +++ b/arch/arm/cpu/ixp/npe/include/IxQMgr.h @@ -570,7 +570,7 @@ typedef enum * @brief Queue interrupt source select. * * This enum defines the different source conditions on a queue that result in - * an interupt being fired by the AQM. Interrupt source is configurable for + * an interrupt being fired by the AQM. Interrupt source is configurable for * queues 0-31 only. The interrupt source for queues 32-63 is hardwired to the * NE(Nearly Empty) status flag. * diff --git a/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h b/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h index f7194e7..b65d621 100644 --- a/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h +++ b/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h @@ -404,7 +404,7 @@ * * @def IX_ETH_ACC_RX_FRAME_ETH_Q * -* @brief Eth0/Eth1 NPE Frame Recieve Q. +* @brief Eth0/Eth1 NPE Frame Receive Q. * * @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration * diff --git a/arch/arm/cpu/ixp/npe/npe.c b/arch/arm/cpu/ixp/npe/npe.c index 857bcad..f0e02bf 100644 --- a/arch/arm/cpu/ixp/npe/npe.c +++ b/arch/arm/cpu/ixp/npe/npe.c @@ -359,36 +359,53 @@ static int npe_init(struct eth_device *dev, bd_t * bis) debug("%s: 1\n", __FUNCTION__); - miiphy_read (dev->name, p_npe->phy_no, MII_BMSR, ®_short); - - /* - * Wait if PHY is capable of autonegotiation and autonegotiation is not complete - */ - if ((reg_short & BMSR_ANEGCAPABLE) && !(reg_short & BMSR_ANEGCOMPLETE)) { - puts ("Waiting for PHY auto negotiation to complete"); - i = 0; - while (!(reg_short & BMSR_ANEGCOMPLETE)) { - /* - * Timeout reached ? - */ - if (i > PHY_AUTONEGOTIATE_TIMEOUT) { - puts (" TIMEOUT !\n"); - break; - } +#ifdef CONFIG_MII_NPE0_FIXEDLINK + if (0 == p_npe->eth_id) { + speed = CONFIG_MII_NPE0_SPEED; + duplex = CONFIG_MII_NPE0_FULLDUPLEX ? FULL : HALF; + } else +#endif +#ifdef CONFIG_MII_NPE1_FIXEDLINK + if (1 == p_npe->eth_id) { + speed = CONFIG_MII_NPE1_SPEED; + duplex = CONFIG_MII_NPE1_FULLDUPLEX ? FULL : HALF; + } else +#endif + { + miiphy_read(dev->name, p_npe->phy_no, MII_BMSR, ®_short); + + /* + * Wait if PHY is capable of autonegotiation and + * autonegotiation is not complete + */ + if ((reg_short & BMSR_ANEGCAPABLE) && + !(reg_short & BMSR_ANEGCOMPLETE)) { + puts("Waiting for PHY auto negotiation to complete"); + i = 0; + while (!(reg_short & BMSR_ANEGCOMPLETE)) { + /* + * Timeout reached ? + */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts(" TIMEOUT !\n"); + break; + } - if ((i++ % 1000) == 0) { - putc ('.'); - miiphy_read (dev->name, p_npe->phy_no, MII_BMSR, ®_short); + if ((i++ % 1000) == 0) { + putc('.'); + miiphy_read(dev->name, p_npe->phy_no, + MII_BMSR, ®_short); + } + udelay(1000); /* 1 ms */ } - udelay (1000); /* 1 ms */ + puts(" done\n"); + /* another 500 ms (results in faster booting) */ + udelay(500000); } - puts (" done\n"); - udelay (500000); /* another 500 ms (results in faster booting) */ + speed = miiphy_speed(dev->name, p_npe->phy_no); + duplex = miiphy_duplex(dev->name, p_npe->phy_no); } - speed = miiphy_speed (dev->name, p_npe->phy_no); - duplex = miiphy_duplex (dev->name, p_npe->phy_no); - if (p_npe->print_speed) { p_npe->print_speed = 0; printf ("ENET Speed is %d Mbps - %s duplex connection\n", @@ -621,9 +638,12 @@ int npe_initialize(bd_t * bis) if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X) { switch (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) { case IX_FEATURE_CTRL_SILICON_TYPE_B0: + default: /* newer than B0 */ /* - * If it is B0 Silicon, we only enable port when its corresponding - * Eth Coprocessor is available. + * If it is B0 or newer Silicon, we + * only enable port when its + * corresponding Eth Coprocessor is + * available. */ if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == IX_FEATURE_CTRL_COMPONENT_ENABLED) diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S index 561c1f4..b17d267 100644 --- a/arch/arm/cpu/ixp/start.S +++ b/arch/arm/cpu/ixp/start.S @@ -65,7 +65,8 @@ .endm .globl _start -_start: b reset +_start: + ldr pc, _reset ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -74,6 +75,7 @@ _start: b reset ldr pc, _irq ldr pc, _fiq +_reset: .word reset _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort @@ -167,12 +169,6 @@ reset: str r1, [r2] /* make sure flash is visible at 0 */ -#if 0 - ldr r2, =IXP425_EXP_CFG0 - ldr r1, [r2] - orr r1, r1, #0x80000000 - str r1, [r2] -#endif mov r1, #CONFIG_SYS_SDR_CONFIG ldr r2, =IXP425_SDR_CONFIG str r1, [r2] @@ -216,19 +212,6 @@ reset: str r1, [r4] DELAY_FOR 0x4000, r0 - /* copy */ - mov r0, #0 - mov r4, r0 - add r2, r0, #CONFIG_SYS_MONITOR_LEN - mov r1, #0x10000000 - mov r5, r1 - - 30: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r0, r2 - bne 30b - /* invalidate I & D caches & BTB */ mcr p15, 0, r0, c7, c7, 0 CPWAIT r0 @@ -241,19 +224,12 @@ reset: mcr p15, 0, r0, c7, c10, 4 CPWAIT r0 - /* move flash to 0x50000000 */ + /* remove flash mirror at 0x00000000 */ ldr r2, =IXP425_EXP_CFG0 ldr r1, [r2] bic r1, r1, #0x80000000 str r1, [r2] - nop - nop - nop - nop - nop - nop - /* invalidate I & Data TLB */ mcr p15, 0, r0, c8, c7, 0 CPWAIT r0 @@ -269,7 +245,7 @@ reset: orr r0,r0,#0x13 msr cpsr,r0 -/* Set stackpointer in internal RAM to call board_init_f */ +/* Set initial stackpointer in SDRAM to call board_init_f */ call_board_init_f: ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ @@ -308,7 +284,7 @@ copy_loop: cmp r0, r2 /* until source end address [r2] */ blo copy_loop -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* * fix .rel.dyn relocations */ @@ -350,7 +326,7 @@ fixnext: #endif clear_bss: -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD ldr r0, _bss_start_ofs ldr r1, _bss_end_ofs mov r4, r6 /* reloc addr */ @@ -575,33 +551,5 @@ reset_cpu: str r1, [r2] b reset_endless - reset_endless: - b reset_endless - -#ifdef CONFIG_USE_IRQ - -.LC0: .word loops_per_jiffy - -/* - * 0 <= r0 <= 2000 - */ -.globl __udelay -__udelay: - mov r2, #0x6800 - orr r2, r2, #0x00db - mul r0, r2, r0 - ldr r2, .LC0 - ldr r2, [r2] @ max = 0x0fffffff - mov r0, r0, lsr #11 @ max = 0x00003fff - mov r2, r2, lsr #11 @ max = 0x0003ffff - mul r0, r2, r0 @ max = 2^32-1 - movs r0, r0, lsr #6 - -delay_loop: - subs r0, r0, #1 - bne delay_loop - mov pc, lr - -#endif /* CONFIG_USE_IRQ */ diff --git a/arch/arm/cpu/ixp/timer.c b/arch/arm/cpu/ixp/timer.c index edf341f..087ddf8 100644 --- a/arch/arm/cpu/ixp/timer.c +++ b/arch/arm/cpu/ixp/timer.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2010 + * Michael Schwingen, michael@schwingen.org + * * (C) Copyright 2006 * Stefan Roese, DENX Software Engineering, sr@denx.de. * @@ -31,105 +34,84 @@ #include <common.h> #include <asm/arch/ixp425.h> +#include <asm/io.h> +#include <div64.h> -#ifdef CONFIG_TIMER_IRQ - -#define FREQ 66666666 -#define CLOCK_TICK_RATE (((FREQ / CONFIG_SYS_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CONFIG_SYS_HZ) -#define LATCH ((CLOCK_TICK_RATE + CONFIG_SYS_HZ/2) / CONFIG_SYS_HZ) /* For divider */ +DECLARE_GLOBAL_DATA_PTR; /* - * When interrupts are enabled, use timer 2 for time/delay generation... + * The IXP42x time-stamp timer runs at 2*OSC_IN (66.666MHz when using a + * 33.333MHz crystal). */ - -static volatile ulong timestamp; - -static void timer_isr(void *data) +static inline unsigned long long tick_to_time(unsigned long long tick) { - unsigned int *pTime = (unsigned int *)data; - - (*pTime)++; - - /* - * Reset IRQ source - */ - *IXP425_OSST = IXP425_OSST_TIMER_2_PEND; + tick *= CONFIG_SYS_HZ; + do_div(tick, CONFIG_IXP425_TIMER_CLK); + return tick; } -ulong get_timer (ulong base) +static inline unsigned long long time_to_tick(unsigned long long time) { - return timestamp - base; + time *= CONFIG_IXP425_TIMER_CLK; + do_div(time, CONFIG_SYS_HZ); + return time; } -void reset_timer (void) +static inline unsigned long long us_to_tick(unsigned long long us) { - timestamp = 0; + us = us * CONFIG_IXP425_TIMER_CLK + 999999; + do_div(us, 1000000); + return us; } -int timer_init (void) +unsigned long long get_ticks(void) { - /* install interrupt handler for timer */ - irq_install_handler(IXP425_TIMER_2_IRQ, timer_isr, (void *)×tamp); - - /* setup the Timer counter value */ - *IXP425_OSRT2 = (LATCH & ~IXP425_OST_RELOAD_MASK) | IXP425_OST_ENABLE; + ulong now = readl(IXP425_OSTS_B); + + if (readl(IXP425_OSST) & IXP425_OSST_TIMER_TS_PEND) { + /* rollover of timestamp timer register */ + gd->timestamp += (0xFFFFFFFF - gd->lastinc) + now + 1; + writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST); + } else { + /* move stamp forward with absolut diff ticks */ + gd->timestamp += (now - gd->lastinc); + } + gd->lastinc = now; + return gd->timestamp; +} - /* enable timer irq */ - *IXP425_ICMR = (1 << IXP425_TIMER_2_IRQ); - return 0; -} -#else -ulong get_timer (ulong base) +void reset_timer_masked(void) { - return get_timer_masked () - base; + /* capture current timestamp counter */ + gd->lastinc = readl(IXP425_OSTS_B); + /* start "advancing" time stamp from 0 */ + gd->timestamp = 0; } -void ixp425_udelay(unsigned long usec) +ulong get_timer_masked(void) { - /* - * This function has a max usec, but since it is called from udelay - * we should not have to worry... be happy - */ - unsigned long usecs = CONFIG_SYS_HZ/1000000L & ~IXP425_OST_RELOAD_MASK; - - *IXP425_OSST = IXP425_OSST_TIMER_1_PEND; - usecs |= IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE; - *IXP425_OSRT1 = usecs; - while (!(*IXP425_OSST & IXP425_OSST_TIMER_1_PEND)); + return tick_to_time(get_ticks()); } -void __udelay (unsigned long usec) +ulong get_timer(ulong base) { - while (usec--) ixp425_udelay(1); + return get_timer_masked() - base; } -static ulong reload_constant = 0xfffffff0; - -void reset_timer_masked (void) +/* delay x useconds AND preserve advance timestamp value */ +void __udelay(unsigned long usec) { - ulong reload = reload_constant | IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE; + unsigned long long tmp; - *IXP425_OSST = IXP425_OSST_TIMER_1_PEND; - *IXP425_OSRT1 = reload; -} + tmp = get_ticks() + us_to_tick(usec); -ulong get_timer_masked (void) -{ - /* - * Note that it is possible for this to wrap! - * In this case we return max. - */ - ulong current = *IXP425_OST1; - if (*IXP425_OSST & IXP425_OSST_TIMER_1_PEND) - { - return reload_constant; - } - return (reload_constant - current); + while (get_ticks() < tmp) + ; } int timer_init(void) { + writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST); return 0; } -#endif diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds index 3587f8a..7199de4 100644 --- a/arch/arm/cpu/ixp/u-boot.lds +++ b/arch/arm/cpu/ixp/u-boot.lds @@ -31,8 +31,8 @@ SECTIONS . = ALIGN(4); .text : { - arch/arm/cpu/ixp/start.o(.text) - *(.text) + arch/arm/cpu/ixp/start.o(.text*) + *(.text*) } . = ALIGN(4); @@ -40,7 +40,7 @@ SECTIONS . = ALIGN(4); .data : { - *(.data) + *(.data*) } . = ALIGN(4); @@ -67,7 +67,7 @@ SECTIONS .bss __rel_dyn_start (OVERLAY) : { __bss_start = .; - *(.bss) + *(.bss*) . = ALIGN(4); __bss_end__ = .; } diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S index 81242b1..14e9854 100644 --- a/arch/arm/cpu/lh7a40x/start.S +++ b/arch/arm/cpu/lh7a40x/start.S @@ -124,7 +124,7 @@ reset: msr cpsr,r0 #define pWDTCTL 0x80001400 /* Watchdog Timer control register */ -#define pINTENC 0x8000050C /* Interupt-Controller enable clear register */ +#define pINTENC 0x8000050C /* Interrupt-Controller enable clear register */ #define pCLKSET 0x80000420 /* clock divisor register */ /* disable watchdog, set watchdog control register to @@ -195,7 +195,7 @@ copy_loop: cmp r0, r2 /* until source end address [r2] */ blo copy_loop -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* * fix .rel.dyn relocations */ @@ -237,7 +237,7 @@ fixnext: #endif clear_bss: -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD ldr r0, _bss_start_ofs ldr r1, _bss_end_ofs mov r4, r6 /* reloc addr */ diff --git a/arch/arm/cpu/lh7a40x/timer.c b/arch/arm/cpu/lh7a40x/timer.c index 2691315..58b35b1 100644 --- a/arch/arm/cpu/lh7a40x/timer.c +++ b/arch/arm/cpu/lh7a40x/timer.c @@ -74,22 +74,11 @@ int timer_init (void) /* * timer without interrupts */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - ulong get_timer (ulong base) { return (get_timer_masked() - base); } -void set_timer (ulong t) -{ - timestamp = t; -} - void __udelay (unsigned long usec) { ulong tmo,tmp; diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index f1dbc3b..6191a73 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -43,7 +43,7 @@ sub pc,pc,#4 .globl _start _start: b reset -#ifdef CONFIG_PRELOADER +#ifdef CONFIG_SPL_BUILD ldr pc, _hang ldr pc, _hang ldr pc, _hang @@ -77,7 +77,7 @@ _data_abort: .word data_abort _not_used: .word not_used _irq: .word irq _fiq: .word fiq -#endif /* CONFIG_PRELOADER */ +#endif /* CONFIG_SPL_BUILD */ .balignl 16,0xdeadbeef @@ -122,7 +122,7 @@ FIQ_STACK_START: .word 0x0badc0de #endif /* CONFIG_USE_IRQ */ -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* IRQ stack memory (calculated at run-time) + 8 bytes */ .globl IRQ_STACK_START_IN IRQ_STACK_START_IN: @@ -262,7 +262,7 @@ copy_loop: blo copy_loop ldmfd sp!, {r0-r12} -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* * fix .rel.dyn relocations */ @@ -301,10 +301,10 @@ fixnext: add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ cmp r2, r3 blo fixloop -#endif /* #ifndef CONFIG_PRELOADER */ +#endif /* #ifndef CONFIG_SPL_BUILD */ clear_bss: -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD ldr r0, _bss_start_ofs ldr r1, _bss_end_ofs mov r4, r6 /* reloc addr */ @@ -316,7 +316,7 @@ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 bne clbss_l -#endif /* #ifndef CONFIG_PRELOADER */ +#endif /* #ifndef CONFIG_SPL_BUILD */ /* * We are done. Do not return, instead branch to second part of board @@ -350,7 +350,7 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start -#else /* CONFIG_PRELOADER */ +#else /* CONFIG_SPL_BUILD */ /****************************************************************************/ /* */ @@ -375,9 +375,9 @@ reset: /* Start OneNAND IPL */ ldr pc, =start_oneboot -#endif /* CONFIG_PRELOADER */ +#endif /* CONFIG_SPL_BUILD */ -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /****************************************************************************/ /* */ /* Interrupt handling */ @@ -471,7 +471,7 @@ reset: .macro get_fiq_stack @ setup FIQ stack ldr sp, FIQ_STACK_START .endm -#endif /* CONFIG_PRELOADER +#endif /* CONFIG_SPL_BUILD /****************************************************************************/ @@ -480,7 +480,7 @@ reset: /* */ /****************************************************************************/ -#ifdef CONFIG_PRELOADER +#ifdef CONFIG_SPL_BUILD .align 5 do_hang: ldr sp, _TEXT_BASE /* use 32 words abort stack */ @@ -545,7 +545,7 @@ fiq: get_bad_stack bad_save_user_regs bl do_fiq -#endif /* CONFIG_PRELOADER */ +#endif /* CONFIG_SPL_BUILD */ #endif /* CONFIG_USE_IRQ */ /****************************************************************************/ @@ -584,7 +584,7 @@ reset_endless: b reset_endless -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD .section .mmudata, "a" .align 14 .globl mmu_table @@ -604,4 +604,4 @@ mmu_table: .word (__base << 20) | 0xc12 .set __base, __base + 1 .endr -#endif /* CONFIG_PRELOADER */ +#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c index ec950c7..2866745 100644 --- a/arch/arm/cpu/pxa/timer.c +++ b/arch/arm/cpu/pxa/timer.c @@ -59,37 +59,21 @@ static inline unsigned long long us_to_tick(unsigned long long us) int timer_init (void) { - reset_timer(); + writel(0, OSCR); return 0; } -void reset_timer (void) -{ - reset_timer_masked (); -} - ulong get_timer (ulong base) { return get_timer_masked () - base; } -void set_timer (ulong t) -{ - /* nop */ -} - void __udelay (unsigned long usec) { udelay_masked (usec); } - -void reset_timer_masked (void) -{ - writel(0, OSCR); -} - ulong get_timer_masked (void) { return tick_to_time(get_ticks()); diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S index 10f5284..2545cf6 100644 --- a/arch/arm/cpu/s3c44b0/start.S +++ b/arch/arm/cpu/s3c44b0/start.S @@ -167,7 +167,7 @@ copy_loop: cmp r0, r2 /* until source end address [r2] */ blo copy_loop -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* * fix .rel.dyn relocations */ @@ -209,7 +209,7 @@ fixnext: #endif clear_bss: -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD ldr r0, _bss_start_ofs ldr r1, _bss_end_ofs mov r4, r6 /* reloc addr */ diff --git a/arch/arm/cpu/s3c44b0/timer.c b/arch/arm/cpu/s3c44b0/timer.c index 6f1d8f6..6c2f066 100644 --- a/arch/arm/cpu/s3c44b0/timer.c +++ b/arch/arm/cpu/s3c44b0/timer.c @@ -59,22 +59,11 @@ int timer_init (void) /* * timer without interrupts */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - ulong get_timer (ulong base) { return get_timer_masked () - base; } -void set_timer (ulong t) -{ - timestamp = t; -} - void __udelay (unsigned long usec) { ulong tmo; @@ -89,13 +78,6 @@ void __udelay (unsigned long usec) /*NOP*/; } -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER; - timestamp = 0; -} - ulong get_timer_masked (void) { ulong now = READ_TIMER; diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index b27e970..7223c47 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -171,7 +171,7 @@ copy_loop: cmp r0, r2 /* until source end address [r2] */ blo copy_loop -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* * fix .rel.dyn relocations */ @@ -213,7 +213,7 @@ fixnext: #endif clear_bss: -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD ldr r0, _bss_start_ofs ldr r1, _bss_end_ofs mov r4, r6 /* reloc addr */ @@ -263,7 +263,7 @@ _dynsym_start_ofs: */ -/* Interupt-Controller base address */ +/* Interrupt-Controller base address */ IC_BASE: .word 0x90050000 #define ICMR 0x04 diff --git a/arch/arm/cpu/sa1100/timer.c b/arch/arm/cpu/sa1100/timer.c index 0207501..53bec0b 100644 --- a/arch/arm/cpu/sa1100/timer.c +++ b/arch/arm/cpu/sa1100/timer.c @@ -34,32 +34,16 @@ int timer_init (void) return 0; } -void reset_timer (void) -{ - reset_timer_masked (); -} - ulong get_timer (ulong base) { return get_timer_masked (); } -void set_timer (ulong t) -{ - /* nop */ -} - void __udelay (unsigned long usec) { udelay_masked (usec); } - -void reset_timer_masked (void) -{ - OSCR = 0; -} - ulong get_timer_masked (void) { return OSCR; diff --git a/arch/arm/include/asm/arch-at91/at91_matrix.h b/arch/arm/include/asm/arch-at91/at91_matrix.h index f99b1d4..a9ba9e9 100644 --- a/arch/arm/include/asm/arch-at91/at91_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91_matrix.h @@ -26,18 +26,18 @@ #ifdef __ASSEMBLY__ #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) -#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x11C) +#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x11C) #elif defined(CONFIG_AT91SAM9261) -#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x30) +#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x30) #elif defined(CONFIG_AT91SAM9263) -#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x120) +#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x120) #elif defined(CONFIG_AT91SAM9G45) -#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x128) +#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x128) #else #error AT91_ASM_MATRIX_CSA0 is not definied for current CPU #endif -#define AT91_ASM_MATRIX_MCFG AT91_MATRIX_BASE +#define AT91_ASM_MATRIX_MCFG ATMEL_BASE_MATRIX #else #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) diff --git a/arch/arm/include/asm/arch-at91/at91_mc.h b/arch/arm/include/asm/arch-at91/at91_mc.h index 09453a9..e00cb68 100644 --- a/arch/arm/include/asm/arch-at91/at91_mc.h +++ b/arch/arm/include/asm/arch-at91/at91_mc.h @@ -23,12 +23,12 @@ #ifndef AT91_MC_H #define AT91_MC_H -#define AT91_ASM_MC_EBI_CSA (AT91_MC_BASE + 0x60) -#define AT91_ASM_MC_EBI_CFG (AT91_MC_BASE + 0x64) -#define AT91_ASM_MC_SMC_CSR0 (AT91_MC_BASE + 0x70) -#define AT91_ASM_MC_SDRAMC_MR (AT91_MC_BASE + 0x90) -#define AT91_ASM_MC_SDRAMC_TR (AT91_MC_BASE + 0x94) -#define AT91_ASM_MC_SDRAMC_CR (AT91_MC_BASE + 0x98) +#define AT91_ASM_MC_EBI_CSA (ATMEL_BASE_MC + 0x60) +#define AT91_ASM_MC_EBI_CFG (ATMEL_BASE_MC + 0x64) +#define AT91_ASM_MC_SMC_CSR0 (ATMEL_BASE_MC + 0x70) +#define AT91_ASM_MC_SDRAMC_MR (ATMEL_BASE_MC + 0x90) +#define AT91_ASM_MC_SDRAMC_TR (ATMEL_BASE_MC + 0x94) +#define AT91_ASM_MC_SDRAMC_CR (ATMEL_BASE_MC + 0x98) #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h index 0b5bd69..416cabf 100644 --- a/arch/arm/include/asm/arch-at91/at91_pio.h +++ b/arch/arm/include/asm/arch-at91/at91_pio.h @@ -20,20 +20,20 @@ #define AT91_ASM_PIO_RANGE 0x200 #define AT91_ASM_PIOC_ASR \ - (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70) + (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70) #define AT91_ASM_PIOC_BSR \ - (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74) + (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74) #define AT91_ASM_PIOC_PDR \ - (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04) + (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04) #define AT91_ASM_PIOC_PUDR \ - (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60) + (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60) #define AT91_ASM_PIOD_PDR \ - (AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04) + (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04) #define AT91_ASM_PIOD_PUDR \ - (AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60) + (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60) #define AT91_ASM_PIOD_ASR \ - (AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70) + (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70) #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h index fb8bb17..086cb9b 100644 --- a/arch/arm/include/asm/arch-at91/at91_pmc.h +++ b/arch/arm/include/asm/arch-at91/at91_pmc.h @@ -17,11 +17,11 @@ #ifndef AT91_PMC_H #define AT91_PMC_H -#define AT91_ASM_PMC_MOR (AT91_PMC_BASE + 0x20) -#define AT91_ASM_PMC_PLLAR (AT91_PMC_BASE + 0x28) -#define AT91_ASM_PMC_PLLBR (AT91_PMC_BASE + 0x2c) -#define AT91_ASM_PMC_MCKR (AT91_PMC_BASE + 0x30) -#define AT91_ASM_PMC_SR (AT91_PMC_BASE + 0x68) +#define AT91_ASM_PMC_MOR (ATMEL_BASE_PMC + 0x20) +#define AT91_ASM_PMC_PLLAR (ATMEL_BASE_PMC + 0x28) +#define AT91_ASM_PMC_PLLBR (ATMEL_BASE_PMC + 0x2c) +#define AT91_ASM_PMC_MCKR (ATMEL_BASE_PMC + 0x30) +#define AT91_ASM_PMC_SR (ATMEL_BASE_PMC + 0x68) #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/arch-at91/at91_rstc.h b/arch/arm/include/asm/arch-at91/at91_rstc.h index 510eed5..15ffd18 100644 --- a/arch/arm/include/asm/arch-at91/at91_rstc.h +++ b/arch/arm/include/asm/arch-at91/at91_rstc.h @@ -16,7 +16,7 @@ #ifndef AT91_RSTC_H #define AT91_RSTC_H -#define AT91_ASM_RSTC_MR (AT91_RSTC_BASE + 0x08) +#define AT91_ASM_RSTC_MR (ATMEL_BASE_RSTC + 0x08) #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h b/arch/arm/include/asm/arch-at91/at91_spi.h index c520e89..afe724d 100644 --- a/arch/arm/include/asm/arch-at91/at91_spi.h +++ b/arch/arm/include/asm/arch-at91/at91_spi.h @@ -33,7 +33,7 @@ typedef struct at91_spi { at91_pdc_t pdc; } at91_spi_t; -#ifdef CONFIG_AT91_LEGACY +#ifdef CONFIG_ATMEL_LEGACY #define AT91_SPI_CR 0x00 /* Control Register */ #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ diff --git a/arch/arm/include/asm/arch-at91/at91_wdt.h b/arch/arm/include/asm/arch-at91/at91_wdt.h index cf08daf..dc22ea1 100644 --- a/arch/arm/include/asm/arch-at91/at91_wdt.h +++ b/arch/arm/include/asm/arch-at91/at91_wdt.h @@ -19,7 +19,7 @@ #ifdef __ASSEMBLY__ -#define AT91_ASM_WDT_MR (AT91_WDT_BASE + 0x04) +#define AT91_ASM_WDT_MR (ATMEL_BASE_WDT + 0x04) #else diff --git a/arch/arm/include/asm/arch-at91/at91rm9200.h b/arch/arm/include/asm/arch-at91/at91rm9200.h index 1bee6f2..42a32d3 100644 --- a/arch/arm/include/asm/arch-at91/at91rm9200.h +++ b/arch/arm/include/asm/arch-at91/at91rm9200.h @@ -21,115 +21,132 @@ #ifndef __AT91RM9200_H__ #define __AT91RM9200_H__ +#define CONFIG_AT91FAMILY /* it's a member of AT91 family */ +#define CONFIG_ARM920T /* it's an ARM920T Core */ +#define CONFIG_ARCH_CPU_INIT /* we need arch_cpu_init() for hw timers */ +#define CONFIG_AT91_GPIO /* and require always gpio features */ + /* Periperial Identifiers */ -#define AT91_ID_SYS 1 /* System Peripheral */ -#define AT91_ID_PIOA 2 /* PIO port A */ -#define AT91_ID_PIOB 3 /* PIO port B */ -#define AT91_ID_PIOC 4 /* PIO port C */ -#define AT91_ID_PIOD 5 /* PIO port D BGA only */ -#define AT91_ID_USART0 6 /* USART 0 */ -#define AT91_ID_USART1 7 /* USART 1 */ -#define AT91_ID_USART2 8 /* USART 2 */ -#define AT91_ID_USART3 9 /* USART 3 */ -#define AT91_ID_MCI 10 /* Multimedia Card Interface */ -#define AT91_ID_UDP 11 /* USB Device Port */ -#define AT91_ID_TWI 12 /* Two Wire Interface */ -#define AT91_ID_SPI 13 /* Serial Peripheral Interface */ -#define AT91_ID_SSC0 14 /* Synch. Serial Controller 0 */ -#define AT91_ID_SSC1 15 /* Synch. Serial Controller 1 */ -#define AT91_ID_SSC2 16 /* Synch. Serial Controller 2 */ -#define AT91_ID_TC0 17 /* Timer Counter 0 */ -#define AT91_ID_TC1 18 /* Timer Counter 1 */ -#define AT91_ID_TC2 19 /* Timer Counter 2 */ -#define AT91_ID_TC3 20 /* Timer Counter 3 */ -#define AT91_ID_TC4 21 /* Timer Counter 4 */ -#define AT91_ID_TC5 22 /* Timer Counter 5 */ -#define AT91_ID_UHP 23 /* OHCI USB Host Port */ -#define AT91_ID_EMAC 24 /* Ethernet MAC */ -#define AT91_ID_IRQ0 25 /* Advanced Interrupt Controller */ -#define AT91_ID_IRQ1 26 /* Advanced Interrupt Controller */ -#define AT91_ID_IRQ2 27 /* Advanced Interrupt Controller */ -#define AT91_ID_IRQ3 28 /* Advanced Interrupt Controller */ -#define AT91_ID_IRQ4 29 /* Advanced Interrupt Controller */ -#define AT91_ID_IRQ5 30 /* Advanced Interrupt Controller */ -#define AT91_ID_IRQ6 31 /* Advanced Interrupt Controller */ - -#define AT91_USB_HOST_BASE 0x00300000 - -#define AT91_TC_BASE 0xFFFA0000 -#define AT91_UDP_BASE 0xFFFB0000 -#define AT91_MCI_BASE 0xFFFB4000 -#define AT91_TWI_BASE 0xFFFB8000 -#define AT91_EMAC_BASE 0xFFFBC000 -#define AT91_USART_BASE 0xFFFC0000 /* 4x 0x4000 Offset */ -#define AT91_SCC_BASE 0xFFFD0000 /* 4x 0x4000 Offset */ -#define AT91_SPI_BASE 0xFFFE0000 - -#define AT91_AIC_BASE 0xFFFFF000 -#define AT91_DBGU_BASE 0xFFFFF200 -#define AT91_PIO_BASE 0xFFFFF400 /* 4x 0x200 Offset */ -#define AT91_PMC_BASE 0xFFFFFC00 -#define AT91_ST_BASE 0xFFFFFD00 -#define AT91_ST_BASE 0xFFFFFD00 -#define AT91_RTC_BASE 0xFFFFFE00 -#define AT91_MC_BASE 0xFFFFFF00 +#define ATMEL_ID_SYS 1 /* System Peripheral */ +#define ATMEL_ID_PIOA 2 /* PIO port A */ +#define ATMEL_ID_PIOB 3 /* PIO port B */ +#define ATMEL_ID_PIOC 4 /* PIO port C */ +#define ATMEL_ID_PIOD 5 /* PIO port D BGA only */ +#define ATMEL_ID_USART0 6 /* USART 0 */ +#define ATMEL_ID_USART1 7 /* USART 1 */ +#define ATMEL_ID_USART2 8 /* USART 2 */ +#define ATMEL_ID_USART3 9 /* USART 3 */ +#define ATMEL_ID_MCI 10 /* Multimedia Card Interface */ +#define ATMEL_ID_UDP 11 /* USB Device Port */ +#define ATMEL_ID_TWI 12 /* Two Wire Interface */ +#define ATMEL_ID_SPI 13 /* Serial Peripheral Interface */ +#define ATMEL_ID_SSC0 14 /* Synch. Serial Controller 0 */ +#define ATMEL_ID_SSC1 15 /* Synch. Serial Controller 1 */ +#define ATMEL_ID_SSC2 16 /* Synch. Serial Controller 2 */ +#define ATMEL_ID_TC0 17 /* Timer Counter 0 */ +#define ATMEL_ID_TC1 18 /* Timer Counter 1 */ +#define ATMEL_ID_TC2 19 /* Timer Counter 2 */ +#define ATMEL_ID_TC3 20 /* Timer Counter 3 */ +#define ATMEL_ID_TC4 21 /* Timer Counter 4 */ +#define ATMEL_ID_TC5 22 /* Timer Counter 5 */ +#define ATMEL_ID_UHP 23 /* OHCI USB Host Port */ +#define ATMEL_ID_EMAC 24 /* Ethernet MAC */ +#define ATMEL_ID_IRQ0 25 /* Advanced Interrupt Controller */ +#define ATMEL_ID_IRQ1 26 /* Advanced Interrupt Controller */ +#define ATMEL_ID_IRQ2 27 /* Advanced Interrupt Controller */ +#define ATMEL_ID_IRQ3 28 /* Advanced Interrupt Controller */ +#define ATMEL_ID_IRQ4 29 /* Advanced Interrupt Controller */ +#define ATMEL_ID_IRQ5 30 /* Advanced Interrupt Controller */ +#define ATMEL_ID_IRQ6 31 /* Advanced Interrupt Controller */ + +#define ATMEL_USB_HOST_BASE 0x00300000 + +#define ATMEL_BASE_TC 0xFFFA0000 +#define ATMEL_BASE_UDP 0xFFFB0000 +#define ATMEL_BASE_MCI 0xFFFB4000 +#define ATMEL_BASE_TWI 0xFFFB8000 +#define ATMEL_BASE_EMAC 0xFFFBC000 +#define ATMEL_BASE_USART 0xFFFC0000 /* 4x 0x4000 Offset */ +#define ATMEL_BASE_USART0 ATMEL_BASE_USART +#define ATMEL_BASE_USART1 (ATMEL_BASE_USART + 0x4000) +#define ATMEL_BASE_USART2 (ATMEL_BASE_USART + 0x8000) +#define ATMEL_BASE_USART3 (ATMEL_BASE_USART + 0xC000) + +#define ATMEL_BASE_SCC 0xFFFD0000 /* 4x 0x4000 Offset */ +#define ATMEL_BASE_SPI 0xFFFE0000 + +#define ATMEL_BASE_AIC 0xFFFFF000 +#define ATMEL_BASE_DBGU 0xFFFFF200 +#define ATMEL_BASE_PIO 0xFFFFF400 /* 4x 0x200 Offset */ +#define ATMEL_BASE_PIOA 0xFFFFF400 +#define ATMEL_BASE_PIOB 0xFFFFF600 +#define ATMEL_BASE_PIOC 0xFFFFF800 +#define ATMEL_BASE_PIOD 0xFFFFFA00 +#define ATMEL_BASE_PMC 0xFFFFFC00 +#define ATMEL_BASE_ST 0xFFFFFD00 +#define ATMEL_BASE_RTC 0xFFFFFE00 +#define ATMEL_BASE_MC 0xFFFFFF00 +#define AT91_PIO_BASE ATMEL_BASE_PIO /* AT91RM9200 Periperial Multiplexing A */ /* Port A */ -#define AT91_PMX_AA_EREFCK 0x00000080 -#define AT91_PMX_AA_ETXCK 0x00000080 -#define AT91_PMX_AA_ETXEN 0x00000100 -#define AT91_PMX_AA_ETX0 0x00000200 -#define AT91_PMX_AA_ETX1 0x00000400 -#define AT91_PMX_AA_ECRS 0x00000800 -#define AT91_PMX_AA_ECRSDV 0x00000800 -#define AT91_PMX_AA_ERX0 0x00001000 -#define AT91_PMX_AA_ERX1 0x00002000 -#define AT91_PMX_AA_ERXER 0x00004000 -#define AT91_PMX_AA_EMDC 0x00008000 -#define AT91_PMX_AA_EMDIO 0x00010000 - -#define AT91_PMX_AA_TXD2 0x00810000 - -#define AT91_PMX_AA_TWD 0x02000000 -#define AT91_PMX_AA_TWCK 0x04000000 +#define ATMEL_PMX_AA_EREFCK 0x00000080 +#define ATMEL_PMX_AA_ETXCK 0x00000080 +#define ATMEL_PMX_AA_ETXEN 0x00000100 +#define ATMEL_PMX_AA_ETX0 0x00000200 +#define ATMEL_PMX_AA_ETX1 0x00000400 +#define ATMEL_PMX_AA_ECRS 0x00000800 +#define ATMEL_PMX_AA_ECRSDV 0x00000800 +#define ATMEL_PMX_AA_ERX0 0x00001000 +#define ATMEL_PMX_AA_ERX1 0x00002000 +#define ATMEL_PMX_AA_ERXER 0x00004000 +#define ATMEL_PMX_AA_EMDC 0x00008000 +#define ATMEL_PMX_AA_EMDIO 0x00010000 + +#define ATMEL_PMX_AA_TXD2 0x00800000 + +#define ATMEL_PMX_AA_TWD 0x02000000 +#define ATMEL_PMX_AA_TWCK 0x04000000 /* Port B */ -#define AT91_PMX_BA_ERXCK 0x00080000 -#define AT91_PMX_BA_ECOL 0x00040000 -#define AT91_PMX_BA_ERXDV 0x00020000 -#define AT91_PMX_BA_ERX3 0x00010000 -#define AT91_PMX_BA_ERX2 0x00008000 -#define AT91_PMX_BA_ETXER 0x00004000 -#define AT91_PMX_BA_ETX3 0x00002000 -#define AT91_PMX_BA_ETX2 0x00001000 +#define ATMEL_PMX_BA_ERXCK 0x00080000 +#define ATMEL_PMX_BA_ECOL 0x00040000 +#define ATMEL_PMX_BA_ERXDV 0x00020000 +#define ATMEL_PMX_BA_ERX3 0x00010000 +#define ATMEL_PMX_BA_ERX2 0x00008000 +#define ATMEL_PMX_BA_ETXER 0x00004000 +#define ATMEL_PMX_BA_ETX3 0x00002000 +#define ATMEL_PMX_BA_ETX2 0x00001000 /* Port B */ -#define AT91_PMX_CA_BFCK 0x00000001 -#define AT91_PMX_CA_BFRDY 0x00000002 -#define AT91_PMX_CA_SMOE 0x00000002 -#define AT91_PMX_CA_BFAVD 0x00000004 -#define AT91_PMX_CA_BFBAA 0x00000008 -#define AT91_PMX_CA_SMWE 0x00000008 -#define AT91_PMX_CA_BFOE 0x00000010 -#define AT91_PMX_CA_BFWE 0x00000020 -#define AT91_PMX_CA_NWAIT 0x00000040 -#define AT91_PMX_CA_A23 0x00000080 -#define AT91_PMX_CA_A24 0x00000100 -#define AT91_PMX_CA_A25 0x00000200 -#define AT91_PMX_CA_CFRNW 0x00000200 -#define AT91_PMX_CA_NCS4 0x00000400 -#define AT91_PMX_CA_CFCS 0x00000400 -#define AT91_PMX_CA_NCS5 0x00000800 -#define AT91_PMX_CA_CFCE1 0x00001000 -#define AT91_PMX_CA_NCS6 0x00001000 -#define AT91_PMX_CA_CFCE2 0x00002000 -#define AT91_PMX_CA_NCS7 0x00002000 -#define AT91_PMX_CA_D16_31 0xFFFF0000 - -#define CONFIG_SYS_AT91_CPU_NAME "AT91RM9200" +#define ATMEL_PMX_CA_BFCK 0x00000001 +#define ATMEL_PMX_CA_BFRDY 0x00000002 +#define ATMEL_PMX_CA_SMOE 0x00000002 +#define ATMEL_PMX_CA_BFAVD 0x00000004 +#define ATMEL_PMX_CA_BFBAA 0x00000008 +#define ATMEL_PMX_CA_SMWE 0x00000008 +#define ATMEL_PMX_CA_BFOE 0x00000010 +#define ATMEL_PMX_CA_BFWE 0x00000020 +#define ATMEL_PMX_CA_NWAIT 0x00000040 +#define ATMEL_PMX_CA_A23 0x00000080 +#define ATMEL_PMX_CA_A24 0x00000100 +#define ATMEL_PMX_CA_A25 0x00000200 +#define ATMEL_PMX_CA_CFRNW 0x00000200 +#define ATMEL_PMX_CA_NCS4 0x00000400 +#define ATMEL_PMX_CA_CFCS 0x00000400 +#define ATMEL_PMX_CA_NCS5 0x00000800 +#define ATMEL_PMX_CA_CFCE1 0x00001000 +#define ATMEL_PMX_CA_NCS6 0x00001000 +#define ATMEL_PMX_CA_CFCE2 0x00002000 +#define ATMEL_PMX_CA_NCS7 0x00002000 +#define ATMEL_PMX_CA_D16_31 0xFFFF0000 + +#define ATMEL_PIO_PORTS 4 /* theese SoCs have 4 PIO */ +#define ATMEL_PMC_UHP AT91RM9200_PMC_UHP + +#define CONFIG_SYS_ATMEL_CPU_NAME "AT91RM9200" #endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/include/asm/arch-at91/at91sam9260.h index dd68485..08cb42d 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9260.h +++ b/arch/arm/include/asm/arch-at91/at91sam9260.h @@ -141,6 +141,7 @@ */ #define ATMEL_PIO_PORTS 3 /* these SoCs have 3 PIO */ #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP +#define ATMEL_BASE_PIO ATMEL_BASE_PIOA /* * SoC specific defines diff --git a/arch/arm/include/asm/arch-at91/at91sam9261.h b/arch/arm/include/asm/arch-at91/at91sam9261.h index f8048d5..59b1864 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9261.h +++ b/arch/arm/include/asm/arch-at91/at91sam9261.h @@ -104,7 +104,7 @@ #define ATMEL_SIZE_SRAM 0x00028000 /* Internal SRAM size (160Kb) */ #define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */ -#define ATMEL_SIZE_ROM SZ_32K /* Internal ROM size (32Kb) */ +#define ATMEL_SIZE_ROM 0x00008000 /* Internal ROM size (32Kb) */ #define ATMEL_BASE_UHP 0x00500000 /* USB Host controller */ #define ATMEL_BASE_LCDC 0x00600000 /* LDC controller */ @@ -125,6 +125,8 @@ * Other misc defines */ #define ATMEL_PIO_PORTS 3 /* theese SoCs have 3 PIO */ +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP +#define ATMEL_BASE_PIO ATMEL_BASE_PIOA /* * SoC specific defines diff --git a/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h index e2bfc4b..913b4d7 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h @@ -15,50 +15,45 @@ #ifndef AT91SAM9261_MATRIX_H #define AT91SAM9261_MATRIX_H -#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ +#ifndef __ASSEMBLY__ -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ +struct at91_matrix { + u32 mcfg; /* Master Configuration Registers */ + u32 scfg[5]; /* Slave Configuration Registers */ + u32 filler[6]; + u32 ebicsa; /* EBI Chip Select Assignment Register */ +}; +#endif /* __ASSEMBLY__ */ -#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_16 (5 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_ITCM_64 (7 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_16 (5 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) -#define AT91_MATRIX_DTCM_64 (7 << 4) +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_CS1A_SMC (0 << 1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_CS3A_SMC (0 << 3) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_CS4A_SMC (0 << 4) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_CS5A_SMC (0 << 5) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) -#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ -#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ +#define AT91_MATRIX_M0PR_SHIFT 0 +#define AT91_MATRIX_M1PR_SHIFT 4 +#define AT91_MATRIX_M2PR_SHIFT 8 +#define AT91_MATRIX_M3PR_SHIFT 12 +#define AT91_MATRIX_M4PR_SHIFT 16 +#define AT91_MATRIX_M5PR_SHIFT 20 + +#define AT91_MATRIX_RCB0 (1 << 0) +#define AT91_MATRIX_RCB1 (1 << 1) + +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) #endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9263.h b/arch/arm/include/asm/arch-at91/at91sam9263.h index bfd408b..bf9ff76 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9263.h +++ b/arch/arm/include/asm/arch-at91/at91sam9263.h @@ -125,9 +125,23 @@ #define ATMEL_BASE_UHP 0x00a00000 /* USB Host controller */ /* + * External memory + */ +#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */ +#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ +#define ATMEL_BASE_CS2 0x30000000 +#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */ +#define ATMEL_BASE_CS4 0x50000000 +#define ATMEL_BASE_CS5 0x60000000 +#define ATMEL_BASE_CS6 0x70000000 +#define ATMEL_BASE_CS7 0x80000000 + +/* * Other misc defines */ #define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */ +#define ATMEL_BASE_PIO ATMEL_BASE_PIOA +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP /* * Cpu Name diff --git a/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h index 83aaaab..3f67093 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h @@ -15,115 +15,53 @@ #ifndef AT91SAM9263_MATRIX_H #define AT91SAM9263_MATRIX_H -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ -#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ -#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) +#ifndef __ASSEMBLY__ -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ -#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ -#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) +/* + * This struct defines access to the matrix' maximum of + * 16 masters and 16 slaves. + * Note: not all masters/slaves are available + */ +struct at91_matrix { + u32 mcfg[16]; /* Master Configuration Registers */ + u32 scfg[16]; /* Slave Configuration Registers */ + u32 pras[16][2]; /* Priority Assignment Slave Registers */ + u32 mrcr; /* Master Remap Control Register */ + u32 filler[0x06]; + u32 ebicsa; /* EBI Chip Select Assignment Register */ +}; + +#endif /* __ASSEMBLY__ */ -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ -#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ -#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ -#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ -#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ -#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ -#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ -#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ -#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) -#define AT91_MATRIX_RCB6 (1 << 6) -#define AT91_MATRIX_RCB7 (1 << 7) -#define AT91_MATRIX_RCB8 (1 << 8) +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) -#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_16 (5 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_16 (5 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) +#define AT91_MATRIX_M0PR_SHIFT 0 +#define AT91_MATRIX_M1PR_SHIFT 4 +#define AT91_MATRIX_M2PR_SHIFT 8 +#define AT91_MATRIX_M3PR_SHIFT 12 +#define AT91_MATRIX_M4PR_SHIFT 16 +#define AT91_MATRIX_M5PR_SHIFT 20 -#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ -#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3) -#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4) -#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5) -#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_RCB0 (1 << 0) +#define AT91_MATRIX_RCB1 (1 << 1) -#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */ -#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3) -#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) #endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h index c3da3a6..2d4c49e 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h +++ b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h @@ -19,19 +19,19 @@ #ifdef __ASSEMBLY__ -#ifndef AT91_SDRAMC_BASE -#define AT91_SDRAMC_BASE AT91_SDRAMC0_BASE +#ifndef ATMEL_BASE_SDRAMC +#define ATMEL_BASE_SDRAMC ATMEL_BASE_SDRAMC0 #endif -#define AT91_ASM_SDRAMC_MR AT91_SDRAMC_BASE -#define AT91_ASM_SDRAMC_TR (AT91_SDRAMC_BASE + 0x04) -#define AT91_ASM_SDRAMC_CR (AT91_SDRAMC_BASE + 0x08) -#define AT91_ASM_SDRAMC_MDR (AT91_SDRAMC_BASE + 0x24) +#define AT91_ASM_SDRAMC_MR ATMEL_BASE_SDRAMC +#define AT91_ASM_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04) +#define AT91_ASM_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) +#define AT91_ASM_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24) #endif /* SDRAM Controller (SDRAMC) registers */ -#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ +#define AT91_SDRAMC_MR (ATMEL_BASE_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ #define AT91_SDRAMC_MODE_NORMAL 0 #define AT91_SDRAMC_MODE_NOP 1 @@ -41,10 +41,10 @@ #define AT91_SDRAMC_MODE_EXT_LMR 5 #define AT91_SDRAMC_MODE_DEEP 6 -#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ +#define AT91_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ -#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ +#define AT91_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ #define AT91_SDRAMC_NC_8 (0 << 0) #define AT91_SDRAMC_NC_9 (1 << 0) @@ -71,7 +71,7 @@ #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ -#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ +#define AT91_SDRAMC_LPR (ATMEL_BASE_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ #define AT91_SDRAMC_LPCB_DISABLE 0 #define AT91_SDRAMC_LPCB_SELF_REFRESH 1 @@ -85,13 +85,13 @@ #define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) #define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) -#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ -#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ -#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ -#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ +#define AT91_SDRAMC_IER (ATMEL_BASE_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ +#define AT91_SDRAMC_IDR (ATMEL_BASE_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ +#define AT91_SDRAMC_IMR (ATMEL_BASE_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ +#define AT91_SDRAMC_ISR (ATMEL_BASE_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ -#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ +#define AT91_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24) /* SDRAM Memory Device Register */ #define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ #define AT91_SDRAMC_MD_SDRAM 0 #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 diff --git a/arch/arm/include/asm/arch-at91/at91sam9_smc.h b/arch/arm/include/asm/arch-at91/at91sam9_smc.h index d180c8a..2ea2791 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9_smc.h +++ b/arch/arm/include/asm/arch-at91/at91sam9_smc.h @@ -18,14 +18,14 @@ #ifdef __ASSEMBLY__ -#ifndef AT91_SMC_BASE -#define AT91_SMC_BASE AT91_SMC0_BASE +#ifndef ATMEL_BASE_SMC +#define ATMEL_BASE_SMC ATMEL_BASE_SMC0 #endif -#define AT91_ASM_SMC_SETUP0 AT91_SMC_BASE -#define AT91_ASM_SMC_PULSE0 (AT91_SMC_BASE + 0x04) -#define AT91_ASM_SMC_CYCLE0 (AT91_SMC_BASE + 0x08) -#define AT91_ASM_SMC_MODE0 (AT91_SMC_BASE + 0x0C) +#define AT91_ASM_SMC_SETUP0 ATMEL_BASE_SMC +#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x04) +#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x08) +#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x0C) #else diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl.h b/arch/arm/include/asm/arch-at91/at91sam9rl.h index 8eb0d4f..00b6aa4 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9rl.h +++ b/arch/arm/include/asm/arch-at91/at91sam9rl.h @@ -15,116 +15,117 @@ #define AT91SAM9RL_H /* - * Peripheral identifiers/interrupts. + * defines to be used in other places */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Controller */ -#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */ -#define AT91SAM9RL_ID_US0 6 /* USART 0 */ -#define AT91SAM9RL_ID_US1 7 /* USART 1 */ -#define AT91SAM9RL_ID_US2 8 /* USART 2 */ -#define AT91SAM9RL_ID_US3 9 /* USART 3 */ -#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */ -#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */ -#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */ -#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */ -#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */ -#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */ -#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */ -#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */ -#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */ -#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */ -#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */ -#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */ -#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ -#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ - -#define AT91_SDRAMC_BASE 0xffffea00 -#define AT91_SMC_BASE 0xffffec00 -#define AT91_MATRIX_BASE 0xffffee00 -#define AT91_PIO_BASE 0xfffff400 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 +#define CONFIG_ARM926EJS /* ARM926EJS Core */ +#define CONFIG_AT91FAMILY /* it's a member of AT91 */ -#ifdef CONFIG_AT91_LEGACY +/* + * Peripheral identifiers/interrupts. + */ +#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define ATMEL_ID_SYS 1 /* System Peripherals */ +#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ +#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ +#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */ +#define ATMEL_ID_PIOD 5 /* Parallel IO Controller D */ +#define ATMEL_ID_USART0 6 /* USART 0 */ +#define ATMEL_ID_USART1 7 /* USART 1 */ +#define ATMEL_ID_USART2 8 /* USART 2 */ +#define ATMEL_ID_USART3 9 /* USART 3 */ +#define ATMEL_ID_MCI 10 /* Multimedia Card Interface */ +#define ATMEL_ID_TWI0 11 /* TWI 0 */ +#define ATMEL_ID_TWI1 12 /* TWI 1 */ +#define ATMEL_ID_SPI 13 /* Serial Peripheral Interface */ +#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ +#define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ +#define ATMEL_ID_TC0 16 /* Timer Counter 0 */ +#define ATMEL_ID_TC1 17 /* Timer Counter 1 */ +#define ATMEL_ID_TC2 18 /* Timer Counter 2 */ +#define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */ +#define ATMEL_ID_TSC 20 /* Touch Screen Controller */ +#define ATMEL_ID_DMA 21 /* DMA Controller */ +#define ATMEL_ID_UDPHS 22 /* USB Device HS */ +#define ATMEL_ID_LCDC 23 /* LCD Controller */ +#define ATMEL_ID_AC97C 24 /* AC97 Controller */ +#define ATMEL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ /* * User Peripheral physical base addresses. */ -#define AT91SAM9RL_BASE_TCB0 0xfffa0000 -#define AT91SAM9RL_BASE_TC0 0xfffa0000 -#define AT91SAM9RL_BASE_TC1 0xfffa0040 -#define AT91SAM9RL_BASE_TC2 0xfffa0080 -#define AT91SAM9RL_BASE_MCI 0xfffa4000 -#define AT91SAM9RL_BASE_TWI0 0xfffa8000 -#define AT91SAM9RL_BASE_TWI1 0xfffac000 -#define AT91SAM9RL_BASE_US0 0xfffb0000 -#define AT91SAM9RL_BASE_US1 0xfffb4000 -#define AT91SAM9RL_BASE_US2 0xfffb8000 -#define AT91SAM9RL_BASE_US3 0xfffbc000 -#define AT91SAM9RL_BASE_SSC0 0xfffc0000 -#define AT91SAM9RL_BASE_SSC1 0xfffc4000 -#define AT91SAM9RL_BASE_PWMC 0xfffc8000 -#define AT91SAM9RL_BASE_SPI 0xfffcc000 -#define AT91SAM9RL_BASE_TSC 0xfffd0000 -#define AT91SAM9RL_BASE_UDPHS 0xfffd4000 -#define AT91SAM9RL_BASE_AC97C 0xfffd8000 -#define AT91_BASE_SYS 0xffffc000 +#define ATMEL_BASE_TCB0 0xfffa0000 +#define ATMEL_BASE_TC0 0xfffa0000 +#define ATMEL_BASE_TC1 0xfffa0040 +#define ATMEL_BASE_TC2 0xfffa0080 +#define ATMEL_BASE_MCI 0xfffa4000 +#define ATMEL_BASE_TWI0 0xfffa8000 +#define ATMEL_BASE_TWI1 0xfffac000 +#define ATMEL_BASE_USART0 0xfffb0000 +#define ATMEL_BASE_USART1 0xfffb4000 +#define ATMEL_BASE_USART2 0xfffb8000 +#define ATMEL_BASE_USART3 0xfffbc000 +#define ATMEL_BASE_SSC0 0xfffc0000 +#define ATMEL_BASE_SSC1 0xfffc4000 +#define ATMEL_BASE_PWMC 0xfffc8000 +#define ATMEL_BASE_SPI0 0xfffcc000 +#define ATMEL_BASE_TSC 0xfffd0000 +#define ATMEL_BASE_UDPHS 0xfffd4000 +#define ATMEL_BASE_AC97C 0xfffd8000 +#define ATMEL_BASE_SYS 0xffffc000 /* - * System Peripherals (offset from AT91_BASE_SYS) + * System Peripherals */ -#define AT91_DMA (0xffffe600 - AT91_BASE_SYS) -#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) -#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9RL_BASE_US0 -#define AT91_USART1 AT91SAM9RL_BASE_US1 -#define AT91_USART2 AT91SAM9RL_BASE_US2 -#define AT91_USART3 AT91SAM9RL_BASE_US3 - -#endif /* CONFIG_AT91_LEGACY */ +#define ATMEL_BASE_DMA 0xffffe600 +#define ATMEL_BASE_ECC 0xffffe800 +#define ATMEL_BASE_SDRAMC 0xffffea00 +#define ATMEL_BASE_SMC 0xffffec00 +#define ATMEL_BASE_MATRIX 0xffffee00 +#define ATMEL_BASE_CCFG 0xffffef10 +#define ATMEL_BASE_AIC 0xfffff000 +#define ATMEL_BASE_DBGU 0xfffff200 +#define ATMEL_BASE_PIOA 0xfffff400 +#define ATMEL_BASE_PIOB 0xfffff600 +#define ATMEL_BASE_PIOC 0xfffff800 +#define ATMEL_BASE_PIOD 0xfffffa00 +#define ATMEL_BASE_PMC 0xfffffc00 +#define ATMEL_BASE_RSTC 0xfffffd00 +#define ATMEL_BASE_SHDWC 0xfffffd10 +#define ATMEL_BASE_RTT 0xfffffd20 +#define ATMEL_BASE_PIT 0xfffffd30 +#define ATMEL_BASE_WDT 0xfffffd40 +#define ATMEL_BASE_SCKCR 0xfffffd50 +#define ATMEL_BASE_GPBR 0xfffffd60 +#define ATMEL_BASE_RTC 0xfffffe00 /* * Internal Memory. */ -#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ +#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ +#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */ + +#define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */ +#define ATMEL_UHP_BASE 0x00600000 /* USB Device HS controller */ -#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ +/* + * External memory + */ +#define ATMEL_BASE_CS0 0x10000000 +#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ +#define ATMEL_BASE_CS2 0x30000000 +#define ATMEL_BASE_CS3 0x40000000 /* NAND */ +#define ATMEL_BASE_CS4 0x50000000 /* Compact Flash Slot 0 */ +#define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */ -#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */ +/* + * Other misc defines + */ +#define ATMEL_PIO_PORTS 4 /* this SoC has 4 PIO */ +#define ATMEL_BASE_PIO ATMEL_BASE_PIOA /* * Cpu Name */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9RL" +#define ATMEL_CPU_NAME "AT91SAM9RL" #endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h index af8d914..295f768 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h @@ -14,83 +14,48 @@ #ifndef AT91SAM9RL_MATRIX_H #define AT91SAM9RL_MATRIX_H -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ - -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) - -#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_16 (5 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_16 (5 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) - -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ -#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_CS1A_SMC (0 << 1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_CS3A_SMC (0 << 3) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_CS4A_SMC (0 << 4) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_CS5A_SMC (0 << 5) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) - +#ifndef __ASSEMBLY__ + +struct at91_matrix { + u32 mcfg[16]; /* Master Configuration Registers */ + u32 scfg[16]; /* Slave Configuration Registers */ + u32 pras[16][2]; /* Priority Assignment Slave Registers */ + u32 mrcr; /* Master Remap Control Register */ + u32 filler[7]; + u32 ebicsa; /* EBI Chip Select Assignment Register */ +}; + +#endif /* __ASSEMBLY__ */ + +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) + +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) + +#define AT91_MATRIX_M0PR_SHIFT 0 +#define AT91_MATRIX_M1PR_SHIFT 4 +#define AT91_MATRIX_M2PR_SHIFT 8 +#define AT91_MATRIX_M3PR_SHIFT 12 +#define AT91_MATRIX_M4PR_SHIFT 16 +#define AT91_MATRIX_M5PR_SHIFT 20 + +#define AT91_MATRIX_RCB0 (1 << 0) +#define AT91_MATRIX_RCB1 (1 << 1) + +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) #endif diff --git a/arch/arm/include/asm/arch-at91/clk.h b/arch/arm/include/asm/arch-at91/clk.h index 457e6c9..f645327 100644 --- a/arch/arm/include/asm/arch-at91/clk.h +++ b/arch/arm/include/asm/arch-at91/clk.h @@ -26,13 +26,43 @@ #define __ASM_ARM_ARCH_CLK_H__ #include <asm/arch/hardware.h> +#include <asm/global_data.h> -unsigned long get_cpu_clk_rate(void); -unsigned long get_main_clk_rate(void); -unsigned long get_mck_clk_rate(void); -unsigned long get_plla_clk_rate(void); -unsigned long get_pllb_clk_rate(void); -unsigned int get_pllb_init(void); +static inline unsigned long get_cpu_clk_rate(void) +{ + DECLARE_GLOBAL_DATA_PTR; + return gd->cpu_clk_rate_hz; +} + +static inline unsigned long get_main_clk_rate(void) +{ + DECLARE_GLOBAL_DATA_PTR; + return gd->main_clk_rate_hz; +} + +static inline unsigned long get_mck_clk_rate(void) +{ + DECLARE_GLOBAL_DATA_PTR; + return gd->mck_rate_hz; +} + +static inline unsigned long get_plla_clk_rate(void) +{ + DECLARE_GLOBAL_DATA_PTR; + return gd->plla_rate_hz; +} + +static inline unsigned long get_pllb_clk_rate(void) +{ + DECLARE_GLOBAL_DATA_PTR; + return gd->pllb_rate_hz; +} + +static inline u32 get_pllb_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + return gd->at91_pllb_usb_init; +} static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) { diff --git a/arch/arm/include/asm/arch-at91rm9200/AT91RM9200.h b/arch/arm/include/asm/arch-at91rm9200/AT91RM9200.h deleted file mode 100644 index 00bae1c..0000000 --- a/arch/arm/include/asm/arch-at91rm9200/AT91RM9200.h +++ /dev/null @@ -1,812 +0,0 @@ -/* - * (C) Copyright 2003 - * AT91RM9200 definitions - * Author : ATMEL AT91 application group - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef AT91RM9200_H -#define AT91RM9200_H - -#ifndef __ASSEMBLY__ -typedef volatile unsigned int AT91_REG; /* Hardware register definition */ - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ -/*****************************************************************************/ -typedef struct _AT91S_TC -{ - AT91_REG TC_CCR; /* Channel Control Register */ - AT91_REG TC_CMR; /* Channel Mode Register */ - AT91_REG Reserved0[2]; /* */ - AT91_REG TC_CV; /* Counter Value */ - AT91_REG TC_RA; /* Register A */ - AT91_REG TC_RB; /* Register B */ - AT91_REG TC_RC; /* Register C */ - AT91_REG TC_SR; /* Status Register */ - AT91_REG TC_IER; /* Interrupt Enable Register */ - AT91_REG TC_IDR; /* Interrupt Disable Register */ - AT91_REG TC_IMR; /* Interrupt Mask Register */ -} AT91S_TC, *AT91PS_TC; - -#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */ -#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */ -#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */ -#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */ -#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK*/ -#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */ -#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */ -#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */ -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */ -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */ -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */ -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */ -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */ -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */ - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Usart */ -/*****************************************************************************/ -typedef struct _AT91S_USART -{ - AT91_REG US_CR; /* Control Register */ - AT91_REG US_MR; /* Mode Register */ - AT91_REG US_IER; /* Interrupt Enable Register */ - AT91_REG US_IDR; /* Interrupt Disable Register */ - AT91_REG US_IMR; /* Interrupt Mask Register */ - AT91_REG US_CSR; /* Channel Status Register */ - AT91_REG US_RHR; /* Receiver Holding Register */ - AT91_REG US_THR; /* Transmitter Holding Register */ - AT91_REG US_BRGR; /* Baud Rate Generator Register */ - AT91_REG US_RTOR; /* Receiver Time-out Register */ - AT91_REG US_TTGR; /* Transmitter Time-guard Register */ - AT91_REG Reserved0[5]; /* */ - AT91_REG US_FIDI; /* FI_DI_Ratio Register */ - AT91_REG US_NER; /* Nb Errors Register */ - AT91_REG US_XXR; /* XON_XOFF Register */ - AT91_REG US_IF; /* IRDA_FILTER Register */ - AT91_REG Reserved1[44]; /* */ - AT91_REG US_RPR; /* Receive Pointer Register */ - AT91_REG US_RCR; /* Receive Counter Register */ - AT91_REG US_TPR; /* Transmit Pointer Register */ - AT91_REG US_TCR; /* Transmit Counter Register */ - AT91_REG US_RNPR; /* Receive Next Pointer Register */ - AT91_REG US_RNCR; /* Receive Next Counter Register */ - AT91_REG US_TNPR; /* Transmit Next Pointer Register */ - AT91_REG US_TNCR; /* Transmit Next Counter Register */ - AT91_REG US_PTCR; /* PDC Transfer Control Register */ - AT91_REG US_PTSR; /* PDC Transfer Status Register */ -} AT91S_USART, *AT91PS_USART; - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Clock Generator Controler */ -/*****************************************************************************/ -typedef struct _AT91S_CKGR -{ - AT91_REG CKGR_MOR; /* Main Oscillator Register */ - AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ - AT91_REG CKGR_PLLAR; /* PLL A Register */ - AT91_REG CKGR_PLLBR; /* PLL B Register */ -} AT91S_CKGR, *AT91PS_CKGR; - -/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) /* (CKGR) Main Oscillator Enable */ -#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) /* (CKGR) Oscillator Test */ -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) /* (CKGR) Main Oscillator Start-up Time */ - -/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) /* (CKGR) Main Clock Frequency */ -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) /* (CKGR) Main Clock Ready */ - -/* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */ -#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */ -#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */ -#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */ -#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL A Counter */ -#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) /* (CKGR) PLL A Output Frequency Range */ -#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLA datasheet */ -#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLA datasheet */ -#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLA datasheet */ -#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLA datasheet */ -#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) /* (CKGR) PLL A Multiplier */ -#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) /* (CKGR) PLL A Source */ - -/* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */ -#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */ -#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */ -#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */ -#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL B Counter */ -#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) /* (CKGR) PLL B Output Frequency Range */ -#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLB datasheet */ -#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLB datasheet */ -#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLB datasheet */ -#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLB datasheet */ -#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) /* (CKGR) PLL B Multiplier */ -#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */ -#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */ - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */ -/*****************************************************************************/ -typedef struct _AT91S_PIO -{ - AT91_REG PIO_PER; /* PIO Enable Register */ - AT91_REG PIO_PDR; /* PIO Disable Register */ - AT91_REG PIO_PSR; /* PIO Status Register */ - AT91_REG Reserved0[1]; /* */ - AT91_REG PIO_OER; /* Output Enable Register */ - AT91_REG PIO_ODR; /* Output Disable Registerr */ - AT91_REG PIO_OSR; /* Output Status Register */ - AT91_REG Reserved1[1]; /* */ - AT91_REG PIO_IFER; /* Input Filter Enable Register */ - AT91_REG PIO_IFDR; /* Input Filter Disable Register */ - AT91_REG PIO_IFSR; /* Input Filter Status Register */ - AT91_REG Reserved2[1]; /* */ - AT91_REG PIO_SODR; /* Set Output Data Register */ - AT91_REG PIO_CODR; /* Clear Output Data Register */ - AT91_REG PIO_ODSR; /* Output Data Status Register */ - AT91_REG PIO_PDSR; /* Pin Data Status Register */ - AT91_REG PIO_IER; /* Interrupt Enable Register */ - AT91_REG PIO_IDR; /* Interrupt Disable Register */ - AT91_REG PIO_IMR; /* Interrupt Mask Register */ - AT91_REG PIO_ISR; /* Interrupt Status Register */ - AT91_REG PIO_MDER; /* Multi-driver Enable Register */ - AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ - AT91_REG PIO_MDSR; /* Multi-driver Status Register */ - AT91_REG Reserved3[1]; /* */ - AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ - AT91_REG PIO_PPUER; /* Pull-up Enable Register */ - AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */ - AT91_REG Reserved4[1]; /* */ - AT91_REG PIO_ASR; /* Select A Register */ - AT91_REG PIO_BSR; /* Select B Register */ - AT91_REG PIO_ABSR; /* AB Select Status Register */ - AT91_REG Reserved5[9]; /* */ - AT91_REG PIO_OWER; /* Output Write Enable Register */ - AT91_REG PIO_OWDR; /* Output Write Disable Register */ - AT91_REG PIO_OWSR; /* Output Write Status Register */ -} AT91S_PIO, *AT91PS_PIO; - - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Debug Unit */ -/*****************************************************************************/ -typedef struct _AT91S_DBGU -{ - AT91_REG DBGU_CR; /* Control Register */ - AT91_REG DBGU_MR; /* Mode Register */ - AT91_REG DBGU_IER; /* Interrupt Enable Register */ - AT91_REG DBGU_IDR; /* Interrupt Disable Register */ - AT91_REG DBGU_IMR; /* Interrupt Mask Register */ - AT91_REG DBGU_CSR; /* Channel Status Register */ - AT91_REG DBGU_RHR; /* Receiver Holding Register */ - AT91_REG DBGU_THR; /* Transmitter Holding Register */ - AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ - AT91_REG Reserved0[7]; /* */ - AT91_REG DBGU_C1R; /* Chip ID1 Register */ - AT91_REG DBGU_C2R; /* Chip ID2 Register */ - AT91_REG DBGU_FNTR; /* Force NTRST Register */ - AT91_REG Reserved1[45]; /* */ - AT91_REG DBGU_RPR; /* Receive Pointer Register */ - AT91_REG DBGU_RCR; /* Receive Counter Register */ - AT91_REG DBGU_TPR; /* Transmit Pointer Register */ - AT91_REG DBGU_TCR; /* Transmit Counter Register */ - AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ - AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ - AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ - AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ - AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ - AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ -} AT91S_DBGU, *AT91PS_DBGU; - -/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */ -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */ -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */ -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */ -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */ -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */ -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */ -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */ -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */ -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */ -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */ -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */ - -/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */ -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */ -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */ -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */ -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */ -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */ - -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */ -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */ -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */ -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */ - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */ -/*****************************************************************************/ -typedef struct _AT91S_SMC2 -{ - AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */ -} AT91S_SMC2, *AT91PS_SMC2; - -/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */ -#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */ -#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ -#define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) /* (SMC2) Data Float Time */ -#define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */ -#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */ -#define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */ -#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ -#define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */ -#define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */ -#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ -#define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */ -#define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */ -#define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */ -#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */ -#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */ - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Power Management Controler */ -/*****************************************************************************/ -typedef struct _AT91S_PMC -{ - AT91_REG PMC_SCER; /* System Clock Enable Register */ - AT91_REG PMC_SCDR; /* System Clock Disable Register */ - AT91_REG PMC_SCSR; /* System Clock Status Register */ - AT91_REG Reserved0[1]; /* */ - AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ - AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ - AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ - AT91_REG Reserved1[5]; /* */ - AT91_REG PMC_MCKR; /* Master Clock Register */ - AT91_REG Reserved2[3]; /* */ - AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */ - AT91_REG PMC_IER; /* Interrupt Enable Register */ - AT91_REG PMC_IDR; /* Interrupt Disable Register */ - AT91_REG PMC_SR; /* Status Register */ - AT91_REG PMC_IMR; /* Interrupt Mask Register */ -} AT91S_PMC, *AT91PS_PMC; - -/*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/ -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) /* (PMC) Processor Clock */ -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) /* (PMC) USB Device Port Clock */ -#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */ -#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) /* (PMC) USB Host Port Clock */ -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */ -#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */ -/*-------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ------*/ -/*-------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------*/ -/*-------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------*/ -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) /* (PMC) Programmable Clock Selection */ -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) /* (PMC) Slow Clock is selected */ -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) /* (PMC) Main Clock is selected */ -#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) /* (PMC) Clock from PLL A is selected */ -#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) /* (PMC) Clock from PLL B is selected */ -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) /* (PMC) Programmable Clock Prescaler */ -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) /* (PMC) Selected clock */ -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) /* (PMC) Selected clock divided by 2 */ -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) /* (PMC) Selected clock divided by 4 */ -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) /* (PMC) Selected clock divided by 8 */ -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) /* (PMC) Selected clock divided by 16 */ -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) /* (PMC) Selected clock divided by 32 */ -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) /* (PMC) Selected clock divided by 64 */ -#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) /* (PMC) Master Clock Division */ -#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) /* (PMC) The master clock and the processor clock are the same */ -#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) /* (PMC) The processor clock is twice as fast as the master clock */ -#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) /* (PMC) The processor clock is three times faster than the master clock */ -#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) /* (PMC) The processor clock is four times faster than the master clock */ -/*------ PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------*/ -/*------ PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------*/ -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) /* (PMC) MOSC Status/Enable/Disable/Mask */ -#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) /* (PMC) PLL A Status/Enable/Disable/Mask */ -#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) /* (PMC) PLL B Status/Enable/Disable/Mask */ -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */ -#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */ -/*---- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------*/ -/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/ -/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/ - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Ethernet MAC */ -/*****************************************************************************/ -typedef struct _AT91S_EMAC -{ - AT91_REG EMAC_CTL; /* Network Control Register */ - AT91_REG EMAC_CFG; /* Network Configuration Register */ - AT91_REG EMAC_SR; /* Network Status Register */ - AT91_REG EMAC_TAR; /* Transmit Address Register */ - AT91_REG EMAC_TCR; /* Transmit Control Register */ - AT91_REG EMAC_TSR; /* Transmit Status Register */ - AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ - AT91_REG Reserved0[1]; /* */ - AT91_REG EMAC_RSR; /* Receive Status Register */ - AT91_REG EMAC_ISR; /* Interrupt Status Register */ - AT91_REG EMAC_IER; /* Interrupt Enable Register */ - AT91_REG EMAC_IDR; /* Interrupt Disable Register */ - AT91_REG EMAC_IMR; /* Interrupt Mask Register */ - AT91_REG EMAC_MAN; /* PHY Maintenance Register */ - AT91_REG Reserved1[2]; /* */ - AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */ - AT91_REG EMAC_SCOL; /* Single Collision Frame Register */ - AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */ - AT91_REG EMAC_OK; /* Frames Received OK Register */ - AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */ - AT91_REG EMAC_ALE; /* Alignment Error Register */ - AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */ - AT91_REG EMAC_LCOL; /* Late Collision Register */ - AT91_REG EMAC_ECOL; /* Excessive Collision Register */ - AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ - AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */ - AT91_REG EMAC_CDE; /* Code Error Register */ - AT91_REG EMAC_ELR; /* Excessive Length Error Register */ - AT91_REG EMAC_RJB; /* Receive Jabber Register */ - AT91_REG EMAC_USF; /* Undersize Frame Register */ - AT91_REG EMAC_SQEE; /* SQE Test Error Register */ - AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */ - AT91_REG Reserved2[3]; /* */ - AT91_REG EMAC_HSH; /* Hash Address High[63:32] */ - AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */ - AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */ - AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */ - AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */ - AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */ - AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */ - AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */ - AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */ - AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */ -} AT91S_EMAC, *AT91PS_EMAC; - -/* -------- EMAC_CTL : (EMAC Offset: 0x0) -------- */ -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ -#define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) /* (EMAC) Loopback local. */ -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) /* (EMAC) Receive enable. */ -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) /* (EMAC) Transmit enable. */ -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) /* (EMAC) Management port enable. */ -#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) /* (EMAC) Clear statistics registers. */ -#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) /* (EMAC) Increment statistics registers. */ -#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) /* (EMAC) Write enable for statistics registers. */ -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) /* (EMAC) Back pressure. */ - -/* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- */ -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */ -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */ -#define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) /* (EMAC) Bit rate. */ -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */ -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */ -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) /* (EMAC) Multicast hash enable */ -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) /* (EMAC) Unicast hash enable. */ -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) /* (EMAC) Receive 1522 bytes. */ -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) /* (EMAC) External address match enable. */ -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) /* (EMAC) */ -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */ -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */ -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */ -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */ -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) /* (EMAC) */ -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */ - -/* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- */ -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */ -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */ - -/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register ------- */ -#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */ -#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */ - -/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register ------- */ -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */ -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */ -#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */ -#define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) /* (EMAC) */ -#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */ -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */ -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) /* (EMAC) */ - -/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */ -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */ -#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */ - -/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register ------- */ -#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */ -#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */ -#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */ -#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) /* (EMAC) */ -#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) /* (EMAC) */ -#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) /* (EMAC) */ -#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) /* (EMAC) */ -#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) /* (EMAC) */ -#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) /* (EMAC) */ -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) /* (EMAC) */ -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */ -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */ - -/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register ------- */ -/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register ------ */ -/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ -/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */ -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) /* (EMAC) */ -#define AT91C_EMAC_CODE_802_3 ((unsigned int) 0x2 << 16) /* (EMAC) Write Operation */ -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) /* (EMAC) */ -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) /* (EMAC) */ -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) /* (EMAC) */ -#define AT91C_EMAC_RW_R ((unsigned int) 0x2 << 28) /* (EMAC) Read Operation */ -#define AT91C_EMAC_RW_W ((unsigned int) 0x1 << 28) /* (EMAC) Write Operation */ -#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */ -#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */ - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ -/*****************************************************************************/ -typedef struct _AT91S_SPI -{ - AT91_REG SPI_CR; /* Control Register */ - AT91_REG SPI_MR; /* Mode Register */ - AT91_REG SPI_RDR; /* Receive Data Register */ - AT91_REG SPI_TDR; /* Transmit Data Register */ - AT91_REG SPI_SR; /* Status Register */ - AT91_REG SPI_IER; /* Interrupt Enable Register */ - AT91_REG SPI_IDR; /* Interrupt Disable Register */ - AT91_REG SPI_IMR; /* Interrupt Mask Register */ - AT91_REG Reserved0[4]; /* */ - AT91_REG SPI_CSR[4]; /* Chip Select Register */ - AT91_REG Reserved1[48]; /* */ - AT91_REG SPI_RPR; /* Receive Pointer Register */ - AT91_REG SPI_RCR; /* Receive Counter Register */ - AT91_REG SPI_TPR; /* Transmit Pointer Register */ - AT91_REG SPI_TCR; /* Transmit Counter Register */ - AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ - AT91_REG SPI_RNCR; /* Receive Next Counter Register */ - AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ - AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ - AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ - AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ -} AT91S_SPI, *AT91PS_SPI; - -/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) /* (SPI) SPI Enable */ -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) /* (SPI) SPI Disable */ -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) /* (SPI) SPI Software reset */ - -/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) /* (SPI) Master/Slave Mode */ -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) /* (SPI) Peripheral Select */ -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) /* (SPI) Fixed Peripheral Select */ -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) /* (SPI) Variable Peripheral Select */ -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) /* (SPI) Chip Select Decode */ -#define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) /* (SPI) Clock Selection */ -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) /* (SPI) Mode Fault Detection */ -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) /* (SPI) Clock Selection */ -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */ -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */ - -/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) /* (SPI) Receive Data */ -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */ - -/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) /* (SPI) Transmit Data */ -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */ - -/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) /* (SPI) Receive Data Register Full */ -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) /* (SPI) Transmit Data Register Empty */ -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) /* (SPI) Mode Fault Error */ -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) /* (SPI) Overrun Error Status */ -#define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) /* (SPI) End of Receiver Transfer */ -#define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) /* (SPI) End of Receiver Transfer */ -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) /* (SPI) RXBUFF Interrupt */ -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) /* (SPI) TXBUFE Interrupt */ -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */ - -/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ -/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register ------- */ -/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ -/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */ -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) /* (SPI) Clock Phase */ -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) /* (SPI) Bits Per Transfer */ -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) /* (SPI) 8 Bits Per transfer */ -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) /* (SPI) 9 Bits Per transfer */ -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) /* (SPI) 10 Bits Per transfer */ -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) /* (SPI) 11 Bits Per transfer */ -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) /* (SPI) 12 Bits Per transfer */ -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) /* (SPI) 13 Bits Per transfer */ -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) /* (SPI) 14 Bits Per transfer */ -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) /* (SPI) 15 Bits Per transfer */ -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) /* (SPI) 16 Bits Per transfer */ -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) /* (SPI) Serial Clock Baud Rate */ -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */ -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */ - -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ -/*****************************************************************************/ -typedef struct _AT91S_PDC -{ - AT91_REG PDC_RPR; /* Receive Pointer Register */ - AT91_REG PDC_RCR; /* Receive Counter Register */ - AT91_REG PDC_TPR; /* Transmit Pointer Register */ - AT91_REG PDC_TCR; /* Transmit Counter Register */ - AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ - AT91_REG PDC_RNCR; /* Receive Next Counter Register */ - AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ - AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ - AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ - AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ -} AT91S_PDC, *AT91PS_PDC; - -/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) /* (PDC) Receiver Transfer Enable */ -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) /* (PDC) Receiver Transfer Disable */ -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) /* (PDC) Transmitter Transfer Enable */ -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) /* (PDC) Transmitter Transfer Disable */ -/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ - -/* ========== Register definition ==================================== */ -#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) /* (SPI) Chip Select Register */ -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */ -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) /* (PMC) Peripheral Clock Enable Register */ -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) /* (PMC) Peripheral Clock Enable Register */ -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) /* (PMC) Peripheral Clock Enable Register */ -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) /* (PIOA) PIO Enable Register */ -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) /* (PIOA) PIO Disable Register */ -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) /* (PIOA) PIO Status Register */ -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) /* (PIOA) PIO Output Enable Register */ -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) /* (PIOA) PIO Output Disable Register */ -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) /* (PIOA) PIO Output Status Register */ -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) /* (PIOA) PIO Glitch Input Filter Enable Register */ -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) /* (PIOA) PIO Glitch Input Filter Disable Register */ -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) /* (PIOA) PIO Glitch Input Filter Status Register */ -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) /* (PIOA) PIO Set Output Data Register */ -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) /* (PIOA) PIO Clear Output Data Register */ -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) /* (PIOA) PIO Output Data Status Register */ -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) /* (PIOA) PIO Pin Data Status Register */ -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) /* (PIOA) PIO Interrupt Enable Register */ -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) /* (PIOA) PIO Interrupt Disable Register */ -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) /* (PIOA) PIO Interrupt Mask Register */ -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) /* (PIOA) PIO Interrupt Status Register */ -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) /* (PIOA) PIO Multi-drive Enable Register */ -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) /* (PIOA) PIO Multi-drive Disable Register */ -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) /* (PIOA) PIO Multi-drive Status Register */ -#define AT91C_PIOA_PUDR ((AT91_REG *) 0xFFFFF460) /* (PIOA) PIO Pull-up Disable Register */ -#define AT91C_PIOA_PUER ((AT91_REG *) 0xFFFFF464) /* (PIOA) PIO Pull-up Enable Register */ -#define AT91C_PIOA_PUSR ((AT91_REG *) 0xFFFFF468) /* (PIOA) PIO Pull-up Status Register */ -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) /* (PIOA) PIO Peripheral A Select Register */ -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) /* (PIOA) PIO Peripheral B Select Register */ -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) /* (PIOA) PIO Peripheral AB Select Register */ -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) /* (PIOA) PIO Output Write Enable Register */ -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) /* (PIOA) PIO Output Write Disable Register */ -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) /* (PIOA) PIO Output Write Status Register */ -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ - -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */ -#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) /* Pin Controlled by PC0 */ -#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) /* Burst Flash Clock */ -#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) /* DBGU Debug Receive Data */ -#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) /* Pin Controlled by PA31 */ -#define AT91C_PA25_TWD ((unsigned int) 1 << 25) -#define AT91C_PA26_TWCK ((unsigned int) 1 << 26) -#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) /* DBGU Debug Transmit Data */ -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) /* Pin Controlled by PA17 */ -#define AT91C_PA17_TXD0 AT91C_PIO_PA17 /* USART0 Transmit Data */ -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) /* Pin Controlled by PA18 */ -#define AT91C_PA18_RXD0 AT91C_PIO_PA18 /* USART0 Receive Data */ -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) /* Pin Controlled by PB20 */ -#define AT91C_PB20_RXD1 AT91C_PIO_PB20 /* USART1 Receive Data */ -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) /* Pin Controlled by PB21 */ -#define AT91C_PB21_TXD1 AT91C_PIO_PB21 /* USART1 Transmit Data */ - -#define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */ -#define AT91C_ID_PIOA ((unsigned int) 2) /* PIO port A */ -#define AT91C_ID_PIOB ((unsigned int) 3) /* PIO port B */ -#define AT91C_ID_PIOC ((unsigned int) 4) /* PIO port C */ -#define AT91C_ID_USART0 ((unsigned int) 6) /* USART 0 */ -#define AT91C_ID_USART1 ((unsigned int) 7) /* USART 1 */ -#define AT91C_ID_TWI ((unsigned int) 12) /* Two Wire Interface */ -#define AT91C_ID_SPI ((unsigned int) 13) /* Serial Peripheral Interface */ -#define AT91C_ID_TC0 ((unsigned int) 17) /* Timer Counter 0 */ -#define AT91C_ID_UHP ((unsigned int) 23) /* OHCI USB Host Port */ -#define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC */ - -#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) /* Pin Controlled by PC1 */ -#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /* Burst Flash Ready */ -#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) /* Pin Controlled by PC3 */ -#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) /* Burst Flash Address Advance / SmartMedia Write Enable */ -#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) /* Pin Controlled by PC2 */ -#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) /* Burst Flash Address Valid */ -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB1 */ - -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) /* Pin Controlled by PA23 */ -#define AT91C_PA23_TXD2 ((unsigned int) AT91C_PIO_PA23) /* USART 2 Transmit Data */ - -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) /* Pin Controlled by PA0 */ -#define AT91C_PA0_MISO ((unsigned int) AT91C_PIO_PA0) /* SPI Master In Slave */ -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) /* Pin Controlled by PA1 */ -#define AT91C_PA1_MOSI ((unsigned int) AT91C_PIO_PA1) /* SPI Master Out Slave */ -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) /* Pin Controlled by PA2 */ -#define AT91C_PA2_SPCK ((unsigned int) AT91C_PIO_PA2) /* SPI Serial Clock */ -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) /* Pin Controlled by PA3 */ -#define AT91C_PA3_NPCS0 ((unsigned int) AT91C_PIO_PA3) /* SPI Peripheral Chip Select 0 */ -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) /* Pin Controlled by PA4 */ -#define AT91C_PA4_NPCS1 ((unsigned int) AT91C_PIO_PA4) /* SPI Peripheral Chip Select 1 */ -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) /* Pin Controlled by PA5 */ -#define AT91C_PA5_NPCS2 ((unsigned int) AT91C_PIO_PA5) /* SPI Peripheral Chip Select 2 */ -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) /* Pin Controlled by PA6 */ -#define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) /* SPI Peripheral Chip Select 3 */ - -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */ -#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */ -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */ -#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock */ -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) /* Pin Controlled by PA14 */ -#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error */ -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) /* Pin Controlled by PA13 */ -#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1 */ -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) /* Pin Controlled by PA12 */ -#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0 */ -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) /* Pin Controlled by PA11 */ -#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */ -#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1 */ -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9 */ -#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) /* Ethernet MAC Transmit Data 0 */ -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) /* Pin Controlled by PA8 */ -#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable */ -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */ -#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */ - -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) /* Pin Controlled by PB3 */ -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB3 */ -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PB3 */ -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */ -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */ -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */ -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */ -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */ -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) /* Pin Controlled by PB22 */ -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */ -#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */ -#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */ -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) /* Pin Controlled by PB19 */ -#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) /* USART 1 Data Terminal ready */ -#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) /* Ethernet MAC Receive Clock */ -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) /* Pin Controlled by PB18 */ -#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) /* USART 1 Ring Indicator */ -#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) /* Ethernet MAC Collision Detected */ -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) /* Pin Controlled by PB17 */ -#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) /* SSC Receive Frame Sync 2 */ -#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) /* Ethernet MAC Receive Data Valid */ -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) /* Pin Controlled by PB16 */ -#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) /* SSC Receive Clock 2 */ -#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) /* Ethernet MAC Receive Data 3 */ -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) /* Pin Controlled by PB15 */ -#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) /* SSC Receive Data 2 */ -#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) /* Ethernet MAC Receive Data 2 */ -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) /* Pin Controlled by PB14 */ -#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) /* SSC Transmit Data 2 */ -#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) /* Ethernet MAC Transmikt Coding Error */ -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) /* Pin Controlled by PB13 */ -#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) /* SSC Transmit Clock 2 */ -#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) /* Ethernet MAC Transmit Data 3 */ -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) /* Pin Controlled by PB12 */ -#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */ -#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */ - -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */ -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ - -#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */ -#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ -#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ -#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ -#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */ -#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) /* (PIOC) Set Output Data Register */ -#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */ -#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */ - -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) /* (AIC) Base Address */ -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */ -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */ -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */ -#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */ -#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) /* (PIOC) Base Address */ -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */ -#if 0 -#define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) /* (PMC) Base Address */ -#define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) /* (PMC) Base Address */ -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) /* (PMC) Base Address */ -#endif - -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */ -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA4000) /* (TC0) Base Address */ -#if 0 -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) /* (TC0) Base Address */ -#define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) /* (TC0) Base Address */ -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) /* (TC0) Base Address */ -#endif -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */ -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */ -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */ -#define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) /* (US1) Base Address */ -#define AT91C_BASE_US3 ((AT91PS_USART) 0xFFFCC000) /* (US1) Base Address */ -#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */ - -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */ -#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */ -#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */ -#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */ -#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */ -#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */ -#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */ -#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */ -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */ -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ - -#else -/* flash */ -#define AT91C_MC_PUIA 0xFFFFFF10 -#define AT91C_MC_PUP 0xFFFFFF50 -#define AT91C_MC_PUER 0xFFFFFF54 -#define AT91C_MC_ASR 0xFFFFFF04 -#define AT91C_MC_AASR 0xFFFFFF08 -#define AT91C_EBI_CFGR 0xFFFFFF64 -#define AT91C_SMC_CSR0 0xFFFFFF70 - -/* clocks */ -#define AT91C_PLLAR 0xFFFFFC28 -#define AT91C_PLLBR 0xFFFFFC2C -#define AT91C_MCKR 0xFFFFFC30 - -#define AT91C_BASE_CKGR 0xFFFFFC20 -#define AT91C_CKGR_MOR 0 - -/* sdram */ -#define AT91C_PIOC_ASR 0xFFFFF870 -#define AT91C_PIOC_BSR 0xFFFFF874 -#define AT91C_PIOC_PDR 0xFFFFF804 -#define AT91C_EBI_CSA 0xFFFFFF60 -#define AT91C_SDRC_CR 0xFFFFFF98 -#define AT91C_SDRC_MR 0xFFFFFF90 -#define AT91C_SDRC_TR 0xFFFFFF94 - -#endif /* __ASSEMBLY__ */ -#endif /* AT91RM9200_H */ diff --git a/arch/arm/include/asm/arch-at91rm9200/hardware.h b/arch/arm/include/asm/arch-at91rm9200/hardware.h deleted file mode 100644 index b868e38..0000000 --- a/arch/arm/include/asm/arch-at91rm9200/hardware.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * linux/include/asm-arm/arch-at91/hardware.h - * - * Copyright (C) 2003 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <asm/sizes.h> - -#ifndef __ASSEMBLY__ -#include "AT91RM9200.h" -#endif - -/* Virtual and Physical base address for system peripherals */ -#define AT91_SYS_BASE 0xFFFFF000 /*4K */ - -/* Virtual and Physical base addresses of user peripherals */ -#define AT91_SPI_BASE 0xFFFE0000 /*16K */ -#define AT91_SSC2_BASE 0xFFFD8000 /*16K */ -#define AT91_SSC1_BASE 0xFFFD4000 /*16K */ -#define AT91_SSC0_BASE 0xFFFD0000 /*16K */ -#define AT91_USART3_BASE 0xFFFCC000 /*16K */ -#define AT91_USART2_BASE 0xFFFC8000 /*16K */ -#define AT91_USART1_BASE 0xFFFC4000 /*16K */ -#define AT91_USART0_BASE 0xFFFC0000 /*16K */ -#define AT91_EMAC_BASE 0xFFFBC000 /*16K */ -#define AT91_TWI_BASE 0xFFFB8000 /*16K */ -#define AT91_MCI_BASE 0xFFFB4000 /*16K */ -#define AT91_UDP_BASE 0xFFFB0000 /*16K */ -#define AT91_TCB1_BASE 0xFFFA4000 /*16K */ -#define AT91_TCB0_BASE 0xFFFA0000 /*16K */ - -#define AT91_USB_HOST_BASE 0x00300000 - -/* - * Where in virtual memory the IO devices (timers, system controllers - * and so on) - */ -#define AT91_IO_BASE 0xF0000000 /* Virt/Phys Address of IO */ - -/* FLASH */ -#define AT91_FLASH_BASE 0x10000000 /* NCS0 */ - -/* SDRAM */ -#define AT91_SDRAM_BASE 0x20000000 /* NCS1 */ - -/* SmartMedia */ -#define AT91_SMARTMEDIA_BASE 0x40000000 /* NCS3 */ - -/* Definition of interrupt priority levels */ -#define AT91C_AIC_PRIOR_0 AT91C_AIC_PRIOR_LOWEST -#define AT91C_AIC_PRIOR_1 ((unsigned int) 0x1) -#define AT91C_AIC_PRIOR_2 ((unsigned int) 0x2) -#define AT91C_AIC_PRIOR_3 ((unsigned int) 0x3) -#define AT91C_AIC_PRIOR_4 ((unsigned int) 0x4) -#define AT91C_AIC_PRIOR_5 ((unsigned int) 0x5) -#define AT91C_AIC_PRIOR_6 ((unsigned int) 0x6) -#define AT91C_AIC_PRIOR_7 AT91C_AIC_PRIOR_HIGEST - -#endif diff --git a/arch/arm/include/asm/arch-davinci/davinci_misc.h b/arch/arm/include/asm/arch-davinci/davinci_misc.h index 347aa89..211b769 100644 --- a/arch/arm/include/asm/arch-davinci/davinci_misc.h +++ b/arch/arm/include/asm/arch-davinci/davinci_misc.h @@ -57,7 +57,7 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr); int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins); int davinci_configure_pin_mux_items(const struct pinmux_resource *item, int n_items); -#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_MACH_DAVINCI_DA850_EVM) +#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_SOC_DA8XX) void davinci_emac_mii_mode_sel(int mode_sel); #endif #if defined(CONFIG_SOC_DA8XX) diff --git a/arch/arm/include/asm/arch-davinci/gpio_defs.h b/arch/arm/include/asm/arch-davinci/gpio.h index 1be2ac2..29dcccf 100644 --- a/arch/arm/include/asm/arch-davinci/gpio_defs.h +++ b/arch/arm/include/asm/arch-davinci/gpio.h @@ -63,4 +63,12 @@ struct davinci_gpio_bank { #define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45) #define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67) +#define gpio_status() gpio_info() +#define GPIO_NAME_SIZE 20 +#define MAX_NUM_GPIOS 144 +#define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5)) +#define GPIO_BIT(gp) ((gp) & 0x1F) + +void gpio_info(void); + #endif diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index df3f549..f537c4b 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -140,6 +140,8 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000 #define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000 #define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000 +#define DAVINCI_MMC_SD0_BASE 0x01c40000 +#define DAVINCI_MMC_SD1_BASE 0x01e1b000 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000 @@ -213,47 +215,65 @@ typedef volatile unsigned int * dv_reg_p; #else /* CONFIG_SOC_DA8XX */ -enum davinci_lpsc_ids { - DAVINCI_LPSC_TPCC = 0, - DAVINCI_LPSC_TPTC0, - DAVINCI_LPSC_TPTC1, - DAVINCI_LPSC_AEMIF, - DAVINCI_LPSC_SPI0, - DAVINCI_LPSC_MMC_SD, - DAVINCI_LPSC_AINTC, - DAVINCI_LPSC_ARM_RAM_ROM, - DAVINCI_LPSC_SECCTL_KEYMGR, - DAVINCI_LPSC_UART0, - DAVINCI_LPSC_SCR0, - DAVINCI_LPSC_SCR1, - DAVINCI_LPSC_SCR2, - DAVINCI_LPSC_DMAX, - DAVINCI_LPSC_ARM, - DAVINCI_LPSC_GEM, - /* for LPSCs in PSC1, offset from 32 for differentiation */ - DAVINCI_LPSC_PSC1_BASE = 32, - DAVINCI_LPSC_USB11, - DAVINCI_LPSC_USB20, - DAVINCI_LPSC_GPIO, - DAVINCI_LPSC_UHPI, - DAVINCI_LPSC_EMAC, - DAVINCI_LPSC_DDR_EMIF, - DAVINCI_LPSC_McASP0, - DAVINCI_LPSC_McASP1, - DAVINCI_LPSC_McASP2, - DAVINCI_LPSC_SPI1, - DAVINCI_LPSC_I2C1, - DAVINCI_LPSC_UART1, - DAVINCI_LPSC_UART2, - DAVINCI_LPSC_LCDC, - DAVINCI_LPSC_ePWM, - DAVINCI_LPSC_eCAP, - DAVINCI_LPSC_eQEP, - DAVINCI_LPSC_SCR_P0, - DAVINCI_LPSC_SCR_P1, - DAVINCI_LPSC_CR_P3, - DAVINCI_LPSC_L3_CBA_RAM -}; +#define DAVINCI_LPSC_TPCC 0 +#define DAVINCI_LPSC_TPTC0 1 +#define DAVINCI_LPSC_TPTC1 2 +#define DAVINCI_LPSC_AEMIF 3 +#define DAVINCI_LPSC_SPI0 4 +#define DAVINCI_LPSC_MMC_SD 5 +#define DAVINCI_LPSC_AINTC 6 +#define DAVINCI_LPSC_ARM_RAM_ROM 7 +#define DAVINCI_LPSC_SECCTL_KEYMGR 8 +#define DAVINCI_LPSC_UART0 9 +#define DAVINCI_LPSC_SCR0 10 +#define DAVINCI_LPSC_SCR1 11 +#define DAVINCI_LPSC_SCR2 12 +#define DAVINCI_LPSC_DMAX 13 +#define DAVINCI_LPSC_ARM 14 +#define DAVINCI_LPSC_GEM 15 + +/* for LPSCs in PSC1, offset from 32 for differentiation */ +#define DAVINCI_LPSC_PSC1_BASE 32 +#define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 1) +#define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 2) +#define DAVINCI_LPSC_GPIO (DAVINCI_LPSC_PSC1_BASE + 3) +#define DAVINCI_LPSC_UHPI (DAVINCI_LPSC_PSC1_BASE + 4) +#define DAVINCI_LPSC_EMAC (DAVINCI_LPSC_PSC1_BASE + 5) +#define DAVINCI_LPSC_DDR_EMIF (DAVINCI_LPSC_PSC1_BASE + 6) +#define DAVINCI_LPSC_McASP0 (DAVINCI_LPSC_PSC1_BASE + 7) +#define DAVINCI_LPSC_SPI1 (DAVINCI_LPSC_PSC1_BASE + 10) +#define DAVINCI_LPSC_I2C1 (DAVINCI_LPSC_PSC1_BASE + 11) +#define DAVINCI_LPSC_UART1 (DAVINCI_LPSC_PSC1_BASE + 12) +#define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13) +#define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 16) +#define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 17) +#define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 20) +#define DAVINCI_LPSC_L3_CBA_RAM (DAVINCI_LPSC_PSC1_BASE + 31) + +/* DA830-specific peripherals */ +#define DAVINCI_LPSC_McASP1 (DAVINCI_LPSC_PSC1_BASE + 8) +#define DAVINCI_LPSC_McASP2 (DAVINCI_LPSC_PSC1_BASE + 9) +#define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 21) +#define DAVINCI_LPSC_SCR8 (DAVINCI_LPSC_PSC1_BASE + 24) +#define DAVINCI_LPSC_SCR7 (DAVINCI_LPSC_PSC1_BASE + 25) +#define DAVINCI_LPSC_SCR12 (DAVINCI_LPSC_PSC1_BASE + 26) + +/* DA850-specific peripherals */ +#define DAVINCI_LPSC_TPCC1 (DAVINCI_LPSC_PSC1_BASE + 0) +#define DAVINCI_LPSC_SATA (DAVINCI_LPSC_PSC1_BASE + 8) +#define DAVINCI_LPSC_VPIF (DAVINCI_LPSC_PSC1_BASE + 9) +#define DAVINCI_LPSC_McBSP0 (DAVINCI_LPSC_PSC1_BASE + 14) +#define DAVINCI_LPSC_McBSP1 (DAVINCI_LPSC_PSC1_BASE + 15) +#define DAVINCI_LPSC_MMC_SD1 (DAVINCI_LPSC_PSC1_BASE + 18) +#define DAVINCI_LPSC_uPP (DAVINCI_LPSC_PSC1_BASE + 19) +#define DAVINCI_LPSC_TPTC2 (DAVINCI_LPSC_PSC1_BASE + 21) +#define DAVINCI_LPSC_SCR_F0 (DAVINCI_LPSC_PSC1_BASE + 24) +#define DAVINCI_LPSC_SCR_F1 (DAVINCI_LPSC_PSC1_BASE + 25) +#define DAVINCI_LPSC_SCR_F2 (DAVINCI_LPSC_PSC1_BASE + 26) +#define DAVINCI_LPSC_SCR_F6 (DAVINCI_LPSC_PSC1_BASE + 27) +#define DAVINCI_LPSC_SCR_F7 (DAVINCI_LPSC_PSC1_BASE + 28) +#define DAVINCI_LPSC_SCR_F8 (DAVINCI_LPSC_PSC1_BASE + 29) +#define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30) #endif /* CONFIG_SOC_DA8XX */ diff --git a/arch/arm/include/asm/arch-ixp/ixp425.h b/arch/arm/include/asm/arch-ixp/ixp425.h index 2114437..5132607 100644 --- a/arch/arm/include/asm/arch-ixp/ixp425.h +++ b/arch/arm/include/asm/arch-ixp/ixp425.h @@ -391,9 +391,8 @@ #define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x)) #endif -#if 0 /* test-only: also defined in npe/include/... */ -#define IXP425_OSTS IXP425_TIMER_REG(IXP425_OSTS_OFFSET) -#endif +/* _B to avoid collision: also defined in npe/include/... */ +#define IXP425_OSTS_B IXP425_TIMER_REG(IXP425_OSTS_OFFSET) #define IXP425_OST1 IXP425_TIMER_REG(IXP425_OST1_OFFSET) #define IXP425_OSRT1 IXP425_TIMER_REG(IXP425_OSRT1_OFFSET) #define IXP425_OST2 IXP425_TIMER_REG(IXP425_OST2_OFFSET) diff --git a/arch/arm/include/asm/arch-ixp/ixp425pci.h b/arch/arm/include/asm/arch-ixp/ixp425pci.h index 9ea3319..acafea7 100644 --- a/arch/arm/include/asm/arch-ixp/ixp425pci.h +++ b/arch/arm/include/asm/arch-ixp/ixp425pci.h @@ -22,88 +22,21 @@ * MA 02111-1307 USA */ -#ifndef _IXP425PCI_H_ -#define _IXP425PCI_H_ +#ifndef _IXP425PCI_H +#define _IXP425PCI_H -#define TRUE 1 -#define FALSE 0 #define OK 0 #define ERROR -1 -#define BOOL int -#define IXP425_PCI_MAX_BAR_PER_FUNC 6 -#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \ - IXP425_PCI_MAX_FUNC_ON_BUS) - -enum PciBarId -{ - CSR_BAR=0, - IO_BAR, - SD_BAR, - NO_BAR -}; - -/*Base address register descriptor*/ -typedef struct -{ - unsigned int size; - unsigned int address; -} PciBar; - -typedef struct -{ - unsigned int bus; - unsigned int device; - unsigned int func; - unsigned int irq; - BOOL error; - unsigned short vendor_id; - unsigned short device_id; - /*We need an extra entry in this array for dummy placeholder*/ - PciBar bar[IXP425_PCI_MAX_BAR_PER_FUNC + 1]; -} PciDevice; +struct pci_controller; +extern void pci_ixp_init(struct pci_controller *hose); /* Mask definitions*/ -#define IXP425_PCI_TOP_WORD_OF_LONG_MASK 0xffff0000 -#define IXP425_PCI_TOP_BYTE_OF_LONG_MASK 0xff000000 -#define IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK 0x0000ffff -#define IXP425_PCI_BOTTOM_TRIBYTES_OF_LONG_MASK 0x00ffffff #define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f -#define IXP425_PCI_MAX_UINT32 0xffffffff - - -#define IXP425_PCI_BAR_QUERY 0xffffffff - -#define IXP425_PCI_BAR_MEM_BASE 0x100000 -#define IXP425_PCI_BAR_IO_BASE 0x000000 - -/*define the maximum number of bus segments - we support a single segment*/ -#define IXP425_PCI_MAX_BUS 1 -/*define the maximum number of cards per bus segment*/ -#define IXP425_PCI_MAX_DEV 4 -/*define the maximum number of functions per device*/ -#define IXP425_PCI_MAX_FUNC 8 -/* define the maximum number of separate functions that we can - potentially have on the bus*/ -#define IXP425_PCI_MAX_FUNC_ON_BUS (1+ IXP425_PCI_MAX_FUNC * \ - IXP425_PCI_MAX_DEV * \ - IXP425_PCI_MAX_BUS) -/*define the maximum number of BARs per function*/ -#define IXP425_PCI_MAX_BAR_PER_FUNC 6 -#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \ - IXP425_PCI_MAX_FUNC_ON_BUS) #define PCI_NP_CBE_BESL (4) #define PCI_NP_AD_FUNCSL (8) -#define REG_WRITE(b,o,v) (*(volatile unsigned int*)((b+o))=(v)) -#define REG_READ(b,o,v) ((v)=(*(volatile unsigned int*)((b+o)))) - -#define PCI_DELAY 500 -#define USEC_LOOP_COUNT 533 -#define PCI_SETTLE_USEC 200 -#define PCI_MIN_RESET_ASSERT_USEC 2000 - /*Register addressing definitions for PCI controller configuration and status registers*/ @@ -150,28 +83,6 @@ typedef struct #define NP_CMD_CONFIGWRITE (0xb) */ -/*define the default setting of the AHB memory base reg*/ -#define IXP425_PCI_AHBMEMBASE_DEFAULT 0x00010203 -#define IXP425_PCI_AHBIOBASE_DEFAULT 0x0 -#define IXP425_PCI_PCIMEMBASE_DEFAULT 0x0 - -/*define the default settings for the controller's BARs*/ -#ifdef IXP425_PCI_SIMPLE_MAPPING -#define IXP425_PCI_BAR_0_DEFAULT 0x00000000 -#define IXP425_PCI_BAR_1_DEFAULT 0x01000000 -#define IXP425_PCI_BAR_2_DEFAULT 0x02000000 -#define IXP425_PCI_BAR_3_DEFAULT 0x03000000 -#define IXP425_PCI_BAR_4_DEFAULT 0x00000000 -#define IXP425_PCI_BAR_5_DEFAULT 0x00000000 -#else -#define IXP425_PCI_BAR_0_DEFAULT 0x40000000 -#define IXP425_PCI_BAR_1_DEFAULT 0x41000000 -#define IXP425_PCI_BAR_2_DEFAULT 0x42000000 -#define IXP425_PCI_BAR_3_DEFAULT 0x43000000 -#define IXP425_PCI_BAR_4_DEFAULT 0x00000000 -#define IXP425_PCI_BAR_5_DEFAULT 0x00000000 -#endif - /*Configuration Port register bit definitions*/ #define PCI_CRP_WRITE BIT(16) @@ -228,17 +139,6 @@ typedef struct #define PCI_CFG_SPECIAL_USE 0x41 #define PCI_CFG_MODE 0x43 -/*Specify the initial command we send to PCI devices*/ -#define INITIAL_PCI_CMD (PCI_CMD_IO_ENABLE \ - | PCI_CMD_MEM_ENABLE \ - | PCI_CMD_MASTER_ENABLE \ - | PCI_CMD_WI_ENABLE) - -/*define the sub vendor and subsystem to be used */ -#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000 - -#define PCI_IRQ_LINES 4 - #define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */ #define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */ #define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */ @@ -287,26 +187,4 @@ typedef struct #define PCI_DMACTRL_PADC1 BIT(14) #define PCI_DMACTRL_PADE1 BIT(15) -/* GPIO related register */ -#undef IXP425_GPIO_GPOUTR -#undef IXP425_GPIO_GPOER -#undef IXP425_GPIO_GPINR -#undef IXP425_GPIO_GPISR -#undef IXP425_GPIO_GPIT1R -#undef IXP425_GPIO_GPIT2R -#undef IXP425_GPIO_GPCLKR - -#define IXP425_GPIO_GPOUTR 0xC8004000 -#define IXP425_GPIO_GPOER 0xC8004004 -#define IXP425_GPIO_GPINR 0xC8004008 -#define IXP425_GPIO_GPISR 0xC800400C -#define IXP425_GPIO_GPIT1R 0xC8004010 -#define IXP425_GPIO_GPIT2R 0xC8004014 -#define IXP425_GPIO_GPCLKR 0xC8004018 - -#define READ_GPIO_REG(addr,val) \ - (val) = *((volatile int *)(addr)); -#define WRITE_GPIO_REG(addr,val) \ - *((volatile int *)(addr)) = (val); - #endif diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h index 71ba464..b7dae1e 100644 --- a/arch/arm/include/asm/arch-kirkwood/config.h +++ b/arch/arm/include/asm/arch-kirkwood/config.h @@ -137,7 +137,9 @@ * I2C related stuff */ #ifdef CONFIG_CMD_I2C +#ifndef CONFIG_SOFT_I2C #define CONFIG_I2C_MVTWSI +#endif #define CONFIG_SYS_I2C_SLAVE 0x0 #define CONFIG_SYS_I2C_SPEED 100000 #endif diff --git a/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h b/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h deleted file mode 100644 index 0bc5279..0000000 --- a/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2010 - * Matthias Weisser <weisserm@arcor.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef ASM_OFFSETS_H -#define ASM_OFFSETS_H - -/* - * Offset definitions for DDR controller - */ -#define DDR2_DRIC 0x00 -#define DDR2_DRIC1 0x02 -#define DDR2_DRIC2 0x04 -#define DDR2_DRCA 0x06 -#define DDR2_DRCM 0x08 -#define DDR2_DRCST1 0x0a -#define DDR2_DRCST2 0x0c -#define DDR2_DRCR 0x0e -#define DDR2_DRCF 0x20 -#define DDR2_DRASR 0x30 -#define DDR2_DRIMS 0x50 -#define DDR2_DROS 0x60 -#define DDR2_DRIBSODT1 0x64 -#define DDR2_DROABA 0x70 -#define DDR2_DROBS 0x84 - -/* - * Offset definitions Chip Control Module - */ -#define CCNT_CDCRC 0xec - -/* - * Offset definitions clock reset generator - */ -#define CRG_CRPR 0x00 -#define CRG_CRHA 0x18 -#define CRG_CRPA 0x1c -#define CRG_CRPB 0x20 -#define CRG_CRHB 0x24 -#define CRG_CRAM 0x28 - -/* - * Offset definitions External bus interface - */ -#define MEMC_MCFMODE0 0x00 -#define MEMC_MCFMODE2 0x08 -#define MEMC_MCFMODE4 0x10 -#define MEMC_MCFTIM0 0x20 -#define MEMC_MCFTIM2 0x28 -#define MEMC_MCFTIM4 0x30 -#define MEMC_MCFAREA0 0x40 -#define MEMC_MCFAREA2 0x48 -#define MEMC_MCFAREA4 0x50 - -#endif /* ASM_OFFSETS_H */ diff --git a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h index 36a28b7..cb9eee5 100644 --- a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h +++ b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h @@ -498,6 +498,48 @@ struct mb86r0x_gdc { uint32_t pad08[7*1024]; }; +/* mb86r0x ddr2c */ +struct mb86r0x_ddr2c { + uint16_t dric; + uint16_t dric1; + uint16_t dric2; + uint16_t drca; + uint16_t drcm; + uint16_t drcst1; + uint16_t drcst2; + uint16_t drcr; + uint16_t pad00[8]; + uint16_t drcf; + uint16_t pad01[7]; + uint16_t drasr; + uint16_t pad02[15]; + uint16_t drims; + uint16_t pad03[7]; + uint16_t dros; + uint16_t pad04; + uint16_t dribsodt1; + uint16_t dribsocd; + uint16_t dribsocd2; + uint16_t pad05[3]; + uint16_t droaba; + uint16_t pad06[9]; + uint16_t drobs; + uint16_t pad07[5]; + uint16_t drimr1; + uint16_t drimr2; + uint16_t drimr3; + uint16_t drimr4; + uint16_t droisr1; + uint16_t droisr2; +}; + +/* mb86r0x memc */ +struct mb86r0x_memc { + uint32_t mcfmode[8]; + uint32_t mcftim[8]; + uint32_t mcfarea[8]; +}; + #endif /* __ASSEMBLY__ */ /* diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index 55ad115..2ccb445 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -86,8 +86,8 @@ struct esdramc_regs { /* GPIO registers */ struct gpio_regs { - u32 dr; /* data */ - u32 dir; /* direction */ + u32 gpio_dr; /* data */ + u32 gpio_dir; /* direction */ u32 psr; /* pad satus */ u32 icr1; /* interrupt config 1 */ u32 icr2; /* interrupt config 2 */ @@ -141,6 +141,45 @@ struct fuse_bank0_regs { u32 mac_addr[6]; }; +/* Multi-Layer AHB Crossbar Switch (MAX) registers */ +struct max_regs { + u32 mpr0; + u32 pad00[3]; + u32 sgpcr0; + u32 pad01[59]; + u32 mpr1; + u32 pad02[3]; + u32 sgpcr1; + u32 pad03[59]; + u32 mpr2; + u32 pad04[3]; + u32 sgpcr2; + u32 pad05[59]; + u32 mpr3; + u32 pad06[3]; + u32 sgpcr3; + u32 pad07[59]; + u32 mpr4; + u32 pad08[3]; + u32 sgpcr4; + u32 pad09[251]; + u32 mgpcr0; + u32 pad10[63]; + u32 mgpcr1; + u32 pad11[63]; + u32 mgpcr2; + u32 pad12[63]; + u32 mgpcr3; + u32 pad13[63]; + u32 mgpcr4; +}; + +/* AHB <-> IP-Bus Interface (AIPS) */ +struct aips_regs { + u32 mpr_0_7; + u32 mpr_8_15; +}; + #endif /* AIPS 1 */ @@ -318,4 +357,10 @@ struct fuse_bank0_regs { #define WSR_UNLOCK1 0x5555 #define WSR_UNLOCK2 0xAAAA +/* Names used in GPIO driver */ +#define GPIO1_BASE_ADDR IMX_GPIO1_BASE +#define GPIO2_BASE_ADDR IMX_GPIO2_BASE +#define GPIO3_BASE_ADDR IMX_GPIO3_BASE +#define GPIO4_BASE_ADDR IMX_GPIO4_BASE + #endif /* _IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-mx25/macro.h b/arch/arm/include/asm/arch-mx25/macro.h new file mode 100644 index 0000000..276c71c --- /dev/null +++ b/arch/arm/include/asm/arch-mx25/macro.h @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2011 + * Matthias Weisser <weisserm@arcor.de> + * + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby <jrigby@gmail.com> + * + * Common asm macros for imx25 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_MACRO_H__ +#define __ASM_ARM_ARCH_MACRO_H__ +#ifdef __ASSEMBLY__ + +#include <asm/arch/imx-regs.h> +#include <asm/arch/asm-offsets.h> + +.macro init_aips + write32 IMX_AIPS1_BASE + AIPS_MPR_0_7, 0x77777777 + write32 IMX_AIPS1_BASE + AIPS_MPR_8_15, 0x77777777 + write32 IMX_AIPS2_BASE + AIPS_MPR_0_7, 0x77777777 + write32 IMX_AIPS2_BASE + AIPS_MPR_8_15, 0x77777777 +.endm + +.macro init_max + write32 IMX_MAX_BASE + MAX_MPR0, 0x43210 + write32 IMX_MAX_BASE + MAX_MPR1, 0x43210 + write32 IMX_MAX_BASE + MAX_MPR2, 0x43210 + write32 IMX_MAX_BASE + MAX_MPR3, 0x43210 + write32 IMX_MAX_BASE + MAX_MPR4, 0x43210 + + write32 IMX_MAX_BASE + MAX_SGPCR0, 0x10 + write32 IMX_MAX_BASE + MAX_SGPCR1, 0x10 + write32 IMX_MAX_BASE + MAX_SGPCR2, 0x10 + write32 IMX_MAX_BASE + MAX_SGPCR3, 0x10 + write32 IMX_MAX_BASE + MAX_SGPCR4, 0x10 + + write32 IMX_MAX_BASE + MAX_MGPCR0, 0x0 + write32 IMX_MAX_BASE + MAX_MGPCR1, 0x0 + write32 IMX_MAX_BASE + MAX_MGPCR2, 0x0 + write32 IMX_MAX_BASE + MAX_MGPCR3, 0x0 + write32 IMX_MAX_BASE + MAX_MGPCR4, 0x0 +.endm + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARM_ARCH_MACRO_H__ */ diff --git a/arch/arm/include/asm/arch-mx27/asm-offsets.h b/arch/arm/include/asm/arch-mx27/asm-offsets.h deleted file mode 100644 index 497afe5..0000000 --- a/arch/arm/include/asm/arch-mx27/asm-offsets.h +++ /dev/null @@ -1,16 +0,0 @@ -#define AIPI1_PSR0 0x10000000 -#define AIPI1_PSR1 0x10000004 -#define AIPI2_PSR0 0x10020000 -#define AIPI2_PSR1 0x10020004 -#define CSCR 0x10027000 -#define MPCTL0 0x10027004 -#define SPCTL0 0x1002700c -#define PCDR0 0x10027018 -#define PCDR1 0x1002701c -#define PCCR0 0x10027020 -#define PCCR1 0x10027024 -#define ESDCTL0_ROF 0x00 -#define ESDCFG0_ROF 0x04 -#define ESDCTL1_ROF 0x08 -#define ESDCFG1_ROF 0x0C -#define ESDMISC_ROF 0x10 diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index 8f40aa7..b4b2fe6 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -29,7 +29,7 @@ extern void imx_gpio_mode (int gpio_mode); #ifdef CONFIG_MXC_UART -extern void mx27_uart_init_pins(void); +extern void mx27_uart1_init_pins(void); #endif /* CONFIG_MXC_UART */ #ifdef CONFIG_FEC_MXC diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h index 9f7ae80..fb035c4 100644 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ b/arch/arm/include/asm/arch-mx31/clock.h @@ -24,8 +24,15 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H -extern u32 mx31_get_ipg_clk(void); -#define imx_get_uartclk mx31_get_ipg_clk +enum mxc_clock { + MXC_ARM_CLK, + MXC_IPG_CLK, + MXC_CSPI_CLK, + MXC_UART_CLK, +}; + +unsigned int mxc_get_clock(enum mxc_clock clk); +extern u32 imx_get_uartclk(); extern void mx31_gpio_mux(unsigned long mode); extern void mx31_set_pad(enum iomux_pins pin, u32 config); diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 306f966..3c8d607 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -746,7 +746,7 @@ enum iomux_pins { #define IRAM_SIZE (16 * 1024) #define MX31_AIPS1_BASE_ADDR 0x43f00000 -#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) +#define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000) /* USB portsc */ /* values for portsc field */ diff --git a/arch/arm/include/asm/arch-mx5/asm-offsets.h b/arch/arm/include/asm/arch-mx5/asm-offsets.h deleted file mode 100644 index 793f69c..0000000 --- a/arch/arm/include/asm/arch-mx5/asm-offsets.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * needed for arch/arm/cpu/armv7/mx51/lowlevel_init.S - * - * These should be auto-generated - */ -/* CCM */ -#define CLKCTL_CCR 0x00 -#define CLKCTL_CCDR 0x04 -#define CLKCTL_CSR 0x08 -#define CLKCTL_CCSR 0x0C -#define CLKCTL_CACRR 0x10 -#define CLKCTL_CBCDR 0x14 -#define CLKCTL_CBCMR 0x18 -#define CLKCTL_CSCMR1 0x1C -#define CLKCTL_CSCMR2 0x20 -#define CLKCTL_CSCDR1 0x24 -#define CLKCTL_CS1CDR 0x28 -#define CLKCTL_CS2CDR 0x2C -#define CLKCTL_CDCDR 0x30 -#define CLKCTL_CHSCCDR 0x34 -#define CLKCTL_CSCDR2 0x38 -#define CLKCTL_CSCDR3 0x3C -#define CLKCTL_CSCDR4 0x40 -#define CLKCTL_CWDR 0x44 -#define CLKCTL_CDHIPR 0x48 -#define CLKCTL_CDCR 0x4C -#define CLKCTL_CTOR 0x50 -#define CLKCTL_CLPCR 0x54 -#define CLKCTL_CISR 0x58 -#define CLKCTL_CIMR 0x5C -#define CLKCTL_CCOSR 0x60 -#define CLKCTL_CGPR 0x64 -#define CLKCTL_CCGR0 0x68 -#define CLKCTL_CCGR1 0x6C -#define CLKCTL_CCGR2 0x70 -#define CLKCTL_CCGR3 0x74 -#define CLKCTL_CCGR4 0x78 -#define CLKCTL_CCGR5 0x7C -#define CLKCTL_CCGR6 0x80 -#if defined(CONFIG_MX53) -#define CLKCTL_CCGR7 0x84 -#define CLKCTL_CMEOR 0x88 -#elif defined(CONFIG_MX51) -#define CLKCTL_CMEOR 0x84 -#endif - -/* DPLL */ -#define PLL_DP_CTL 0x00 -#define PLL_DP_CONFIG 0x04 -#define PLL_DP_OP 0x08 -#define PLL_DP_MFD 0x0C -#define PLL_DP_MFN 0x10 -#define PLL_DP_HFS_OP 0x1C -#define PLL_DP_HFS_MFD 0x20 -#define PLL_DP_HFS_MFN 0x24 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index a1849f8..e83ca29 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -32,6 +32,7 @@ #define CSD0_BASE_ADDR 0x90000000 #define CSD1_BASE_ADDR 0xA0000000 #define NFC_BASE_ADDR_AXI 0xCFFF0000 +#define CS1_BASE_ADDR 0xB8000000 #elif defined(CONFIG_MX53) #define IPU_CTRL_BASE_ADDR 0x18000000 #define SPBA0_BASE_ADDR 0x50000000 @@ -41,6 +42,7 @@ #define CSD1_BASE_ADDR 0xB0000000 #define NFC_BASE_ADDR_AXI 0xF7FF0000 #define IRAM_BASE_ADDR 0xF8000000 +#define CS1_BASE_ADDR 0xF4000000 #else #error "CPU_TYPE not defined" #endif @@ -129,6 +131,95 @@ #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) /* + * WEIM CSnGCR1 + */ +#define CSEN 1 +#define SWR (1 << 1) +#define SRD (1 << 2) +#define MUM (1 << 3) +#define WFL (1 << 4) +#define RFL (1 << 5) +#define CRE (1 << 6) +#define CREP (1 << 7) +#define BL(x) (((x) & 0x7) << 8) +#define WC (1 << 11) +#define BCD(x) (((x) & 0x3) << 12) +#define BCS(x) (((x) & 0x3) << 14) +#define DSZ(x) (((x) & 0x7) << 16) +#define SP (1 << 19) +#define CSREC(x) (((x) & 0x7) << 20) +#define AUS (1 << 23) +#define GBC(x) (((x) & 0x7) << 24) +#define WP (1 << 27) +#define PSZ(x) (((x) & 0x0f << 28) + +/* + * WEIM CSnGCR2 + */ +#define ADH(x) (((x) & 0x3)) +#define DAPS(x) (((x) & 0x0f << 4) +#define DAE (1 << 8) +#define DAP (1 << 9) +#define MUX16_BYP (1 << 12) + +/* + * WEIM CSnRCR1 + */ +#define RCSN(x) (((x) & 0x7)) +#define RCSA(x) (((x) & 0x7) << 4) +#define OEN(x) (((x) & 0x7) << 8) +#define OEA(x) (((x) & 0x7) << 12) +#define RADVN(x) (((x) & 0x7) << 16) +#define RAL (1 << 19) +#define RADVA(x) (((x) & 0x7) << 20) +#define RWSC(x) (((x) & 0x3f) << 24) + +/* + * WEIM CSnRCR2 + */ +#define RBEN(x) (((x) & 0x7)) +#define RBE (1 << 3) +#define RBEA(x) (((x) & 0x7) << 4) +#define RL(x) (((x) & 0x3) << 8) +#define PAT(x) (((x) & 0x7) << 12) +#define APR (1 << 15) + +/* + * WEIM CSnWCR1 + */ +#define WCSN(x) (((x) & 0x7)) +#define WCSA(x) (((x) & 0x7) << 3) +#define WEN(x) (((x) & 0x7) << 6) +#define WEA(x) (((x) & 0x7) << 9) +#define WBEN(x) (((x) & 0x7) << 12) +#define WBEA(x) (((x) & 0x7) << 15) +#define WADVN(x) (((x) & 0x7) << 18) +#define WADVA(x) (((x) & 0x7) << 21) +#define WWSC(x) (((x) & 0x3f) << 24) +#define WBED1 (1 << 30) +#define WAL (1 << 31) + +/* + * WEIM CSnWCR2 + */ +#define WBED 1 + +/* + * WEIM WCR + */ +#define BCM 1 +#define GBCD(x) (((x) & 0x3) << 1) +#define INTEN (1 << 4) +#define INTPOL (1 << 5) +#define WDOG_EN (1 << 8) +#define WDOG_LIMIT(x) (((x) & 0x3) << 9) + +#define CS0_128 0 +#define CS0_64M_CS1_64M 1 +#define CS0_64M_CS1_32M_CS2_32M 2 +#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 + +/* * Number of GPIO pins per port */ #define GPIO_NUM_PIN 32 @@ -226,18 +317,92 @@ struct clkctl { u32 ccgr4; u32 ccgr5; u32 ccgr6; +#if defined(CONFIG_MX53) + u32 ccgr7; +#endif u32 cmeor; }; +/* DPLL registers */ +struct dpll { + u32 dp_ctl; + u32 dp_config; + u32 dp_op; + u32 dp_mfd; + u32 dp_mfn; + u32 dp_mfn_minus; + u32 dp_mfn_plus; + u32 dp_hfs_op; + u32 dp_hfs_mfd; + u32 dp_hfs_mfn; + u32 dp_mfn_togc; + u32 dp_destat; +}; /* WEIM registers */ struct weim { - u32 csgcr1; - u32 csgcr2; - u32 csrcr1; - u32 csrcr2; - u32 cswcr1; - u32 cswcr2; + u32 cs0gcr1; + u32 cs0gcr2; + u32 cs0rcr1; + u32 cs0rcr2; + u32 cs0wcr1; + u32 cs0wcr2; + u32 cs1gcr1; + u32 cs1gcr2; + u32 cs1rcr1; + u32 cs1rcr2; + u32 cs1wcr1; + u32 cs1wcr2; + u32 cs2gcr1; + u32 cs2gcr2; + u32 cs2rcr1; + u32 cs2rcr2; + u32 cs2wcr1; + u32 cs2wcr2; + u32 cs3gcr1; + u32 cs3gcr2; + u32 cs3rcr1; + u32 cs3rcr2; + u32 cs3wcr1; + u32 cs3wcr2; + u32 cs4gcr1; + u32 cs4gcr2; + u32 cs4rcr1; + u32 cs4rcr2; + u32 cs4wcr1; + u32 cs4wcr2; + u32 cs5gcr1; + u32 cs5gcr2; + u32 cs5rcr1; + u32 cs5rcr2; + u32 cs5wcr1; + u32 cs5wcr2; + u32 wcr; + u32 wiar; + u32 ear; +}; + +#if defined(CONFIG_MX51) +struct iomuxc { + u32 gpr0; + u32 gpr1; + u32 omux0; + u32 omux1; + u32 omux2; + u32 omux3; + u32 omux4; }; +#elif defined(CONFIG_MX53) +struct iomuxc { + u32 gpr0; + u32 gpr1; + u32 gpr2; + u32 omux0; + u32 omux1; + u32 omux2; + u32 omux3; + u32 omux4; +}; +#endif /* GPIO Registers */ struct gpio_regs { diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index f687503..ce63675 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -27,5 +27,5 @@ u32 get_cpu_rev(void); #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) void sdelay(unsigned long); - +void set_chipselect_size(int const); #endif diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index e944de7..08a725d 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -498,4 +498,30 @@ struct pm { /* MUSB base */ #define MUSB_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000) +/* OMAP3 GPIO registers */ +#define OMAP_GPIO_REVISION 0x0000 +#define OMAP_GPIO_SYSCONFIG 0x0010 +#define OMAP_GPIO_SYSSTATUS 0x0014 +#define OMAP_GPIO_IRQSTATUS1 0x0018 +#define OMAP_GPIO_IRQSTATUS2 0x0028 +#define OMAP_GPIO_IRQENABLE2 0x002c +#define OMAP_GPIO_IRQENABLE1 0x001c +#define OMAP_GPIO_WAKE_EN 0x0020 +#define OMAP_GPIO_CTRL 0x0030 +#define OMAP_GPIO_OE 0x0034 +#define OMAP_GPIO_DATAIN 0x0038 +#define OMAP_GPIO_DATAOUT 0x003c +#define OMAP_GPIO_LEVELDETECT0 0x0040 +#define OMAP_GPIO_LEVELDETECT1 0x0044 +#define OMAP_GPIO_RISINGDETECT 0x0048 +#define OMAP_GPIO_FALLINGDETECT 0x004c +#define OMAP_GPIO_DEBOUNCE_EN 0x0050 +#define OMAP_GPIO_DEBOUNCE_VAL 0x0054 +#define OMAP_GPIO_CLEARIRQENABLE1 0x0060 +#define OMAP_GPIO_SETIRQENABLE1 0x0064 +#define OMAP_GPIO_CLEARWKUENA 0x0080 +#define OMAP_GPIO_SETWKUENA 0x0084 +#define OMAP_GPIO_CLEARDATAOUT 0x0090 +#define OMAP_GPIO_SETDATAOUT 0x0094 + #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h index cc2b541..d9d49da 100644 --- a/arch/arm/include/asm/arch-omap3/omap3.h +++ b/arch/arm/include/asm/arch-omap3/omap3.h @@ -159,8 +159,14 @@ struct gpio { #define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \ SRAM_OFFSET2) +#define OMAP3_PUBLIC_SRAM_BASE 0x40208000 /* Works for GP & EMU */ +#define OMAP3_PUBLIC_SRAM_END 0x40210000 + #define LOW_LEVEL_SRAM_STACK 0x4020FFFC +/* scratch area - accessible on both EMU and GP */ +#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA OMAP3_PUBLIC_SRAM_BASE + #define DEBUG_LED1 149 /* gpio */ #define DEBUG_LED2 150 /* gpio */ @@ -227,4 +233,18 @@ struct gpio { #define OMAP3730 0x0c00 +/* + * ROM code API related flags + */ +#define OMAP3_GP_ROMCODE_API_L2_INVAL 1 +#define OMAP3_GP_ROMCODE_API_WRITE_ACR 3 + +/* + * EMU device PPA HAL related flags + */ +#define OMAP3_EMU_HAL_API_L2_INVAL 40 +#define OMAP3_EMU_HAL_API_WRITE_ACR 42 + +#define OMAP3_EMU_HAL_START_HAL_CRITICAL 4 + #endif diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 4a28ba1..995e7cb 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -27,6 +27,11 @@ typedef struct { char *nand_string; } omap3_sysinfo; +struct emu_hal_params { + u32 num_params; + u32 param1; +}; + void prcm_init(void); void per_clocks_enable(void); @@ -53,9 +58,7 @@ u32 is_running_in_sdram(void); u32 is_running_in_sram(void); u32 is_running_in_flash(void); u32 get_device_type(void); -void l2cache_enable(void); void secureworld_exit(void); -void setup_auxcr(void); void try_unlock_memory(void); u32 get_boot_type(void); void invalidate_dcache(u32); @@ -66,5 +69,6 @@ void make_cs1_contiguous(void); void omap_nand_switch_ecc(int); void power_init_r(void); void dieid_num_r(void); - +void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); +void omap3_gp_romcode_call(u32 service_id, u32 parameter); #endif diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h new file mode 100644 index 0000000..374e064 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -0,0 +1,690 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _CLOCKS_OMAP4_H_ +#define _CLOCKS_OMAP4_H_ +#include <common.h> + +/* + * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per + * loop, allow for a minimum of 2 ms wait (in reality the wait will be + * much more than that) + */ +#define LDELAY 1000000 + +#define CM_CLKMODE_DPLL_CORE 0x4A004120 +#define CM_CLKMODE_DPLL_PER 0x4A008140 +#define CM_CLKMODE_DPLL_MPU 0x4A004160 +#define CM_CLKSEL_CORE 0x4A004100 + +struct omap4_prcm_regs { + /* cm1.ckgen */ + u32 cm_clksel_core; + u32 pad001[1]; + u32 cm_clksel_abe; + u32 pad002[1]; + u32 cm_dll_ctrl; + u32 pad003[3]; + u32 cm_clkmode_dpll_core; + u32 cm_idlest_dpll_core; + u32 cm_autoidle_dpll_core; + u32 cm_clksel_dpll_core; + u32 cm_div_m2_dpll_core; + u32 cm_div_m3_dpll_core; + u32 cm_div_m4_dpll_core; + u32 cm_div_m5_dpll_core; + u32 cm_div_m6_dpll_core; + u32 cm_div_m7_dpll_core; + u32 cm_ssc_deltamstep_dpll_core; + u32 cm_ssc_modfreqdiv_dpll_core; + u32 cm_emu_override_dpll_core; + u32 pad004[3]; + u32 cm_clkmode_dpll_mpu; + u32 cm_idlest_dpll_mpu; + u32 cm_autoidle_dpll_mpu; + u32 cm_clksel_dpll_mpu; + u32 cm_div_m2_dpll_mpu; + u32 pad005[5]; + u32 cm_ssc_deltamstep_dpll_mpu; + u32 cm_ssc_modfreqdiv_dpll_mpu; + u32 pad006[3]; + u32 cm_bypclk_dpll_mpu; + u32 cm_clkmode_dpll_iva; + u32 cm_idlest_dpll_iva; + u32 cm_autoidle_dpll_iva; + u32 cm_clksel_dpll_iva; + u32 pad007[2]; + u32 cm_div_m4_dpll_iva; + u32 cm_div_m5_dpll_iva; + u32 pad008[2]; + u32 cm_ssc_deltamstep_dpll_iva; + u32 cm_ssc_modfreqdiv_dpll_iva; + u32 pad009[3]; + u32 cm_bypclk_dpll_iva; + u32 cm_clkmode_dpll_abe; + u32 cm_idlest_dpll_abe; + u32 cm_autoidle_dpll_abe; + u32 cm_clksel_dpll_abe; + u32 cm_div_m2_dpll_abe; + u32 cm_div_m3_dpll_abe; + u32 pad010[4]; + u32 cm_ssc_deltamstep_dpll_abe; + u32 cm_ssc_modfreqdiv_dpll_abe; + u32 pad011[4]; + u32 cm_clkmode_dpll_ddrphy; + u32 cm_idlest_dpll_ddrphy; + u32 cm_autoidle_dpll_ddrphy; + u32 cm_clksel_dpll_ddrphy; + u32 cm_div_m2_dpll_ddrphy; + u32 pad012[1]; + u32 cm_div_m4_dpll_ddrphy; + u32 cm_div_m5_dpll_ddrphy; + u32 cm_div_m6_dpll_ddrphy; + u32 pad013[1]; + u32 cm_ssc_deltamstep_dpll_ddrphy; + u32 pad014[5]; + u32 cm_shadow_freq_config1; + u32 pad0141[47]; + u32 cm_mpu_mpu_clkctrl; + + /* cm1.dsp */ + u32 pad015[55]; + u32 cm_dsp_clkstctrl; + u32 pad016[7]; + u32 cm_dsp_dsp_clkctrl; + + /* cm1.abe */ + u32 pad017[55]; + u32 cm1_abe_clkstctrl; + u32 pad018[7]; + u32 cm1_abe_l4abe_clkctrl; + u32 pad019[1]; + u32 cm1_abe_aess_clkctrl; + u32 pad020[1]; + u32 cm1_abe_pdm_clkctrl; + u32 pad021[1]; + u32 cm1_abe_dmic_clkctrl; + u32 pad022[1]; + u32 cm1_abe_mcasp_clkctrl; + u32 pad023[1]; + u32 cm1_abe_mcbsp1_clkctrl; + u32 pad024[1]; + u32 cm1_abe_mcbsp2_clkctrl; + u32 pad025[1]; + u32 cm1_abe_mcbsp3_clkctrl; + u32 pad026[1]; + u32 cm1_abe_slimbus_clkctrl; + u32 pad027[1]; + u32 cm1_abe_timer5_clkctrl; + u32 pad028[1]; + u32 cm1_abe_timer6_clkctrl; + u32 pad029[1]; + u32 cm1_abe_timer7_clkctrl; + u32 pad030[1]; + u32 cm1_abe_timer8_clkctrl; + u32 pad031[1]; + u32 cm1_abe_wdt3_clkctrl; + + /* cm2.ckgen */ + u32 pad032[3805]; + u32 cm_clksel_mpu_m3_iss_root; + u32 cm_clksel_usb_60mhz; + u32 cm_scale_fclk; + u32 pad033[1]; + u32 cm_core_dvfs_perf1; + u32 cm_core_dvfs_perf2; + u32 cm_core_dvfs_perf3; + u32 cm_core_dvfs_perf4; + u32 pad034[1]; + u32 cm_core_dvfs_current; + u32 cm_iva_dvfs_perf_tesla; + u32 cm_iva_dvfs_perf_ivahd; + u32 cm_iva_dvfs_perf_abe; + u32 pad035[1]; + u32 cm_iva_dvfs_current; + u32 pad036[1]; + u32 cm_clkmode_dpll_per; + u32 cm_idlest_dpll_per; + u32 cm_autoidle_dpll_per; + u32 cm_clksel_dpll_per; + u32 cm_div_m2_dpll_per; + u32 cm_div_m3_dpll_per; + u32 cm_div_m4_dpll_per; + u32 cm_div_m5_dpll_per; + u32 cm_div_m6_dpll_per; + u32 cm_div_m7_dpll_per; + u32 cm_ssc_deltamstep_dpll_per; + u32 cm_ssc_modfreqdiv_dpll_per; + u32 cm_emu_override_dpll_per; + u32 pad037[3]; + u32 cm_clkmode_dpll_usb; + u32 cm_idlest_dpll_usb; + u32 cm_autoidle_dpll_usb; + u32 cm_clksel_dpll_usb; + u32 cm_div_m2_dpll_usb; + u32 pad038[5]; + u32 cm_ssc_deltamstep_dpll_usb; + u32 cm_ssc_modfreqdiv_dpll_usb; + u32 pad039[1]; + u32 cm_clkdcoldo_dpll_usb; + u32 pad040[2]; + u32 cm_clkmode_dpll_unipro; + u32 cm_idlest_dpll_unipro; + u32 cm_autoidle_dpll_unipro; + u32 cm_clksel_dpll_unipro; + u32 cm_div_m2_dpll_unipro; + u32 pad041[5]; + u32 cm_ssc_deltamstep_dpll_unipro; + u32 cm_ssc_modfreqdiv_dpll_unipro; + + /* cm2.core */ + u32 pad0411[324]; + u32 cm_l3_1_clkstctrl; + u32 pad042[1]; + u32 cm_l3_1_dynamicdep; + u32 pad043[5]; + u32 cm_l3_1_l3_1_clkctrl; + u32 pad044[55]; + u32 cm_l3_2_clkstctrl; + u32 pad045[1]; + u32 cm_l3_2_dynamicdep; + u32 pad046[5]; + u32 cm_l3_2_l3_2_clkctrl; + u32 pad047[1]; + u32 cm_l3_2_gpmc_clkctrl; + u32 pad048[1]; + u32 cm_l3_2_ocmc_ram_clkctrl; + u32 pad049[51]; + u32 cm_mpu_m3_clkstctrl; + u32 cm_mpu_m3_staticdep; + u32 cm_mpu_m3_dynamicdep; + u32 pad050[5]; + u32 cm_mpu_m3_mpu_m3_clkctrl; + u32 pad051[55]; + u32 cm_sdma_clkstctrl; + u32 cm_sdma_staticdep; + u32 cm_sdma_dynamicdep; + u32 pad052[5]; + u32 cm_sdma_sdma_clkctrl; + u32 pad053[55]; + u32 cm_memif_clkstctrl; + u32 pad054[7]; + u32 cm_memif_dmm_clkctrl; + u32 pad055[1]; + u32 cm_memif_emif_fw_clkctrl; + u32 pad056[1]; + u32 cm_memif_emif_1_clkctrl; + u32 pad057[1]; + u32 cm_memif_emif_2_clkctrl; + u32 pad058[1]; + u32 cm_memif_dll_clkctrl; + u32 pad059[3]; + u32 cm_memif_emif_h1_clkctrl; + u32 pad060[1]; + u32 cm_memif_emif_h2_clkctrl; + u32 pad061[1]; + u32 cm_memif_dll_h_clkctrl; + u32 pad062[39]; + u32 cm_c2c_clkstctrl; + u32 cm_c2c_staticdep; + u32 cm_c2c_dynamicdep; + u32 pad063[5]; + u32 cm_c2c_sad2d_clkctrl; + u32 pad064[1]; + u32 cm_c2c_modem_icr_clkctrl; + u32 pad065[1]; + u32 cm_c2c_sad2d_fw_clkctrl; + u32 pad066[51]; + u32 cm_l4cfg_clkstctrl; + u32 pad067[1]; + u32 cm_l4cfg_dynamicdep; + u32 pad068[5]; + u32 cm_l4cfg_l4_cfg_clkctrl; + u32 pad069[1]; + u32 cm_l4cfg_hw_sem_clkctrl; + u32 pad070[1]; + u32 cm_l4cfg_mailbox_clkctrl; + u32 pad071[1]; + u32 cm_l4cfg_sar_rom_clkctrl; + u32 pad072[49]; + u32 cm_l3instr_clkstctrl; + u32 pad073[7]; + u32 cm_l3instr_l3_3_clkctrl; + u32 pad074[1]; + u32 cm_l3instr_l3_instr_clkctrl; + u32 pad075[5]; + u32 cm_l3instr_intrconn_wp1_clkctrl; + + + /* cm2.ivahd */ + u32 pad076[47]; + u32 cm_ivahd_clkstctrl; + u32 pad077[7]; + u32 cm_ivahd_ivahd_clkctrl; + u32 pad078[1]; + u32 cm_ivahd_sl2_clkctrl; + + /* cm2.cam */ + u32 pad079[53]; + u32 cm_cam_clkstctrl; + u32 pad080[7]; + u32 cm_cam_iss_clkctrl; + u32 pad081[1]; + u32 cm_cam_fdif_clkctrl; + + /* cm2.dss */ + u32 pad082[53]; + u32 cm_dss_clkstctrl; + u32 pad083[7]; + u32 cm_dss_dss_clkctrl; + + /* cm2.sgx */ + u32 pad084[55]; + u32 cm_sgx_clkstctrl; + u32 pad085[7]; + u32 cm_sgx_sgx_clkctrl; + + /* cm2.l3init */ + u32 pad086[55]; + u32 cm_l3init_clkstctrl; + + /* cm2.l3init */ + u32 pad087[9]; + u32 cm_l3init_hsmmc1_clkctrl; + u32 pad088[1]; + u32 cm_l3init_hsmmc2_clkctrl; + u32 pad089[1]; + u32 cm_l3init_hsi_clkctrl; + u32 pad090[7]; + u32 cm_l3init_hsusbhost_clkctrl; + u32 pad091[1]; + u32 cm_l3init_hsusbotg_clkctrl; + u32 pad092[1]; + u32 cm_l3init_hsusbtll_clkctrl; + u32 pad093[3]; + u32 cm_l3init_p1500_clkctrl; + u32 pad094[21]; + u32 cm_l3init_fsusb_clkctrl; + u32 pad095[3]; + u32 cm_l3init_usbphy_clkctrl; + + /* cm2.l4per */ + u32 pad096[7]; + u32 cm_l4per_clkstctrl; + u32 pad097[1]; + u32 cm_l4per_dynamicdep; + u32 pad098[5]; + u32 cm_l4per_adc_clkctrl; + u32 pad100[1]; + u32 cm_l4per_gptimer10_clkctrl; + u32 pad101[1]; + u32 cm_l4per_gptimer11_clkctrl; + u32 pad102[1]; + u32 cm_l4per_gptimer2_clkctrl; + u32 pad103[1]; + u32 cm_l4per_gptimer3_clkctrl; + u32 pad104[1]; + u32 cm_l4per_gptimer4_clkctrl; + u32 pad105[1]; + u32 cm_l4per_gptimer9_clkctrl; + u32 pad106[1]; + u32 cm_l4per_elm_clkctrl; + u32 pad107[1]; + u32 cm_l4per_gpio2_clkctrl; + u32 pad108[1]; + u32 cm_l4per_gpio3_clkctrl; + u32 pad109[1]; + u32 cm_l4per_gpio4_clkctrl; + u32 pad110[1]; + u32 cm_l4per_gpio5_clkctrl; + u32 pad111[1]; + u32 cm_l4per_gpio6_clkctrl; + u32 pad112[1]; + u32 cm_l4per_hdq1w_clkctrl; + u32 pad113[1]; + u32 cm_l4per_hecc1_clkctrl; + u32 pad114[1]; + u32 cm_l4per_hecc2_clkctrl; + u32 pad115[1]; + u32 cm_l4per_i2c1_clkctrl; + u32 pad116[1]; + u32 cm_l4per_i2c2_clkctrl; + u32 pad117[1]; + u32 cm_l4per_i2c3_clkctrl; + u32 pad118[1]; + u32 cm_l4per_i2c4_clkctrl; + u32 pad119[1]; + u32 cm_l4per_l4per_clkctrl; + u32 pad1191[3]; + u32 cm_l4per_mcasp2_clkctrl; + u32 pad120[1]; + u32 cm_l4per_mcasp3_clkctrl; + u32 pad121[1]; + u32 cm_l4per_mcbsp4_clkctrl; + u32 pad122[1]; + u32 cm_l4per_mgate_clkctrl; + u32 pad123[1]; + u32 cm_l4per_mcspi1_clkctrl; + u32 pad124[1]; + u32 cm_l4per_mcspi2_clkctrl; + u32 pad125[1]; + u32 cm_l4per_mcspi3_clkctrl; + u32 pad126[1]; + u32 cm_l4per_mcspi4_clkctrl; + u32 pad127[5]; + u32 cm_l4per_mmcsd3_clkctrl; + u32 pad128[1]; + u32 cm_l4per_mmcsd4_clkctrl; + u32 pad129[1]; + u32 cm_l4per_msprohg_clkctrl; + u32 pad130[1]; + u32 cm_l4per_slimbus2_clkctrl; + u32 pad131[1]; + u32 cm_l4per_uart1_clkctrl; + u32 pad132[1]; + u32 cm_l4per_uart2_clkctrl; + u32 pad133[1]; + u32 cm_l4per_uart3_clkctrl; + u32 pad134[1]; + u32 cm_l4per_uart4_clkctrl; + u32 pad135[1]; + u32 cm_l4per_mmcsd5_clkctrl; + u32 pad136[1]; + u32 cm_l4per_i2c5_clkctrl; + u32 pad137[5]; + u32 cm_l4sec_clkstctrl; + u32 cm_l4sec_staticdep; + u32 cm_l4sec_dynamicdep; + u32 pad138[5]; + u32 cm_l4sec_aes1_clkctrl; + u32 pad139[1]; + u32 cm_l4sec_aes2_clkctrl; + u32 pad140[1]; + u32 cm_l4sec_des3des_clkctrl; + u32 pad141[1]; + u32 cm_l4sec_pkaeip29_clkctrl; + u32 pad142[1]; + u32 cm_l4sec_rng_clkctrl; + u32 pad143[1]; + u32 cm_l4sec_sha2md51_clkctrl; + u32 pad144[3]; + u32 cm_l4sec_cryptodma_clkctrl; + u32 pad145[776841]; + + /* l4 wkup regs */ + u32 pad201[6211]; + u32 cm_abe_pll_ref_clksel; + u32 cm_sys_clksel; + u32 pad202[1467]; + u32 cm_wkup_clkstctrl; + u32 pad203[7]; + u32 cm_wkup_l4wkup_clkctrl; + u32 pad204; + u32 cm_wkup_wdtimer1_clkctrl; + u32 pad205; + u32 cm_wkup_wdtimer2_clkctrl; + u32 pad206; + u32 cm_wkup_gpio1_clkctrl; + u32 pad207; + u32 cm_wkup_gptimer1_clkctrl; + u32 pad208; + u32 cm_wkup_gptimer12_clkctrl; + u32 pad209; + u32 cm_wkup_synctimer_clkctrl; + u32 pad210; + u32 cm_wkup_usim_clkctrl; + u32 pad211; + u32 cm_wkup_sarram_clkctrl; + u32 pad212[5]; + u32 cm_wkup_keyboard_clkctrl; + u32 pad213; + u32 cm_wkup_rtc_clkctrl; + u32 pad214; + u32 cm_wkup_bandgap_clkctrl; + u32 pad215[197]; + u32 prm_vc_val_bypass; + u32 prm_vc_cfg_channel; + u32 prm_vc_cfg_i2c_mode; + u32 prm_vc_cfg_i2c_clk; + +}; + +/* DPLL register offsets */ +#define CM_CLKMODE_DPLL 0 +#define CM_IDLEST_DPLL 0x4 +#define CM_AUTOIDLE_DPLL 0x8 +#define CM_CLKSEL_DPLL 0xC +#define CM_DIV_M2_DPLL 0x10 +#define CM_DIV_M3_DPLL 0x14 +#define CM_DIV_M4_DPLL 0x18 +#define CM_DIV_M5_DPLL 0x1C +#define CM_DIV_M6_DPLL 0x20 +#define CM_DIV_M7_DPLL 0x24 + +#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ + +/* CM_CLKMODE_DPLL */ +#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 +#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) +#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 +#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) +#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 +#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) +#define CM_CLKMODE_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) + +#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 + +#define DPLL_EN_STOP 1 +#define DPLL_EN_MN_BYPASS 4 +#define DPLL_EN_LOW_POWER_BYPASS 5 +#define DPLL_EN_FAST_RELOCK_BYPASS 6 +#define DPLL_EN_LOCK 7 + +/* CM_IDLEST_DPLL fields */ +#define ST_DPLL_CLK_MASK 1 + +/* CM_CLKSEL_DPLL */ +#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 +#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) +#define CM_CLKSEL_DPLL_M_SHIFT 8 +#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) +#define CM_CLKSEL_DPLL_N_SHIFT 0 +#define CM_CLKSEL_DPLL_N_MASK 0x7F +#define CM_CLKSEL_DCC_EN_SHIFT 22 +#define CM_CLKSEL_DCC_EN_MASK (1 << 22) + +#define OMAP4_DPLL_MAX_N 127 + +/* CM_SYS_CLKSEL */ +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 + +/* CM_CLKSEL_CORE */ +#define CLKSEL_CORE_SHIFT 0 +#define CLKSEL_L3_SHIFT 4 +#define CLKSEL_L4_SHIFT 8 + +#define CLKSEL_CORE_X2_DIV_1 0 +#define CLKSEL_L3_CORE_DIV_2 1 +#define CLKSEL_L4_L3_DIV_2 1 + +/* CM_ABE_PLL_REF_CLKSEL */ +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 + +/* CM_BYPCLK_DPLL_IVA */ +#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 +#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 + +#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 + +/* CM_SHADOW_FREQ_CONFIG1 */ +#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 +#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 +#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 + +#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 +#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) + +#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 +#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) + +/*CM_<clock_domain>__CLKCTRL */ +#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 +#define CD_CLKCTRL_CLKTRCTRL_MASK 3 + +#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 +#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 +#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 +#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 + + +/* CM_<clock_domain>_<module>_CLKCTRL */ +#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 +#define MODULE_CLKCTRL_MODULEMODE_MASK 3 +#define MODULE_CLKCTRL_IDLEST_SHIFT 16 +#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) + +#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 +#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 +#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 + +#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 +#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 +#define MODULE_CLKCTRL_IDLEST_IDLE 2 +#define MODULE_CLKCTRL_IDLEST_DISABLED 3 + +/* CM_L4PER_GPIO4_CLKCTRL */ +#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_L3INIT_HSMMCn_CLKCTRL */ +#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) + +/* CM_WKUP_GPTIMER1_CLKCTRL */ +#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) + +/* CM_CAM_ISS_CLKCTRL */ +#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_DSS_DSS_CLKCTRL */ +#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 + +/* CM_L3INIT_USBPHY_CLKCTRL */ +#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 + +/* CM_MPU_MPU_CLKCTRL */ +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) + +/* Clock frequencies */ +#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 +#define OMAP_SYS_CLK_IND_38_4_MHZ 6 +#define OMAP_32K_CLK_FREQ 32768 + +/* PRM_VC_CFG_I2C_CLK */ +#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0 +#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF +#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8 +#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8) + +/* PRM_VC_VAL_BYPASS */ +#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 + +#define PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000 +#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0 +#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F +#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8 +#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF +#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16 +#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF + +/* SMPS */ +#define SMPS_I2C_SLAVE_ADDR 0x12 +#define SMPS_REG_ADDR_VCORE1 0x55 +#define SMPS_REG_ADDR_VCORE2 0x5B +#define SMPS_REG_ADDR_VCORE3 0x61 + +#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 +#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 + +/* TPS */ +#define TPS62361_I2C_SLAVE_ADDR 0x60 +#define TPS62361_REG_ADDR_SET0 0x0 +#define TPS62361_REG_ADDR_SET1 0x1 +#define TPS62361_REG_ADDR_SET2 0x2 +#define TPS62361_REG_ADDR_SET3 0x3 +#define TPS62361_REG_ADDR_CTRL 0x4 +#define TPS62361_REG_ADDR_TEMP 0x5 +#define TPS62361_REG_ADDR_RMP_CTRL 0x6 +#define TPS62361_REG_ADDR_CHIP_ID 0x8 +#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 + +#define TPS62361_BASE_VOLT_MV 500 +#define TPS62361_VSEL0_GPIO 7 + +/* Defines for DPLL setup */ +#define DPLL_LOCKED_FREQ_TOLERANCE_0 0 +#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 +#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 + +#define DPLL_NO_LOCK 0 +#define DPLL_LOCK 1 + +#define NUM_SYS_CLKS 7 + +struct dpll_regs { + u32 cm_clkmode_dpll; + u32 cm_idlest_dpll; + u32 cm_autoidle_dpll; + u32 cm_clksel_dpll; + u32 cm_div_m2_dpll; + u32 cm_div_m3_dpll; + u32 cm_div_m4_dpll; + u32 cm_div_m5_dpll; + u32 cm_div_m6_dpll; + u32 cm_div_m7_dpll; +}; + +/* DPLL parameter table */ +struct dpll_params { + u32 m; + u32 n; + u8 m2; + u8 m3; + u8 m4; + u8 m5; + u8 m6; + u8 m7; +}; + +#endif /* _CLOCKS_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h index 7d5748a..08b9c99 100644 --- a/arch/arm/include/asm/arch-omap4/cpu.h +++ b/arch/arm/include/asm/arch-omap4/cpu.h @@ -142,4 +142,30 @@ struct watchdog { /* MUSB base */ #define MUSB_BASE (OMAP44XX_L4_CORE_BASE + 0xAB000) +/* OMAP4 GPIO registers */ +#define OMAP_GPIO_REVISION 0x0000 +#define OMAP_GPIO_SYSCONFIG 0x0010 +#define OMAP_GPIO_SYSSTATUS 0x0114 +#define OMAP_GPIO_IRQSTATUS1 0x0118 +#define OMAP_GPIO_IRQSTATUS2 0x0128 +#define OMAP_GPIO_IRQENABLE2 0x012c +#define OMAP_GPIO_IRQENABLE1 0x011c +#define OMAP_GPIO_WAKE_EN 0x0120 +#define OMAP_GPIO_CTRL 0x0130 +#define OMAP_GPIO_OE 0x0134 +#define OMAP_GPIO_DATAIN 0x0138 +#define OMAP_GPIO_DATAOUT 0x013c +#define OMAP_GPIO_LEVELDETECT0 0x0140 +#define OMAP_GPIO_LEVELDETECT1 0x0144 +#define OMAP_GPIO_RISINGDETECT 0x0148 +#define OMAP_GPIO_FALLINGDETECT 0x014c +#define OMAP_GPIO_DEBOUNCE_EN 0x0150 +#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 +#define OMAP_GPIO_CLEARIRQENABLE1 0x0160 +#define OMAP_GPIO_SETIRQENABLE1 0x0164 +#define OMAP_GPIO_CLEARWKUENA 0x0180 +#define OMAP_GPIO_SETWKUENA 0x0184 +#define OMAP_GPIO_CLEARDATAOUT 0x0190 +#define OMAP_GPIO_SETDATAOUT 0x0194 + #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h new file mode 100644 index 0000000..37ad1fd --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/emif.h @@ -0,0 +1,1040 @@ +/* + * OMAP44xx EMIF header + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Aneesh V <aneesh@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _EMIF_H_ +#define _EMIF_H_ +#include <asm/types.h> +#include <common.h> + +/* Base address */ +#define OMAP44XX_EMIF1 0x4c000000 +#define OMAP44XX_EMIF2 0x4d000000 + +/* Registers shifts and masks */ + +/* EMIF_MOD_ID_REV */ +#define OMAP44XX_REG_SCHEME_SHIFT 30 +#define OMAP44XX_REG_SCHEME_MASK (0x3 << 30) +#define OMAP44XX_REG_MODULE_ID_SHIFT 16 +#define OMAP44XX_REG_MODULE_ID_MASK (0xfff << 16) +#define OMAP44XX_REG_RTL_VERSION_SHIFT 11 +#define OMAP44XX_REG_RTL_VERSION_MASK (0x1f << 11) +#define OMAP44XX_REG_MAJOR_REVISION_SHIFT 8 +#define OMAP44XX_REG_MAJOR_REVISION_MASK (0x7 << 8) +#define OMAP44XX_REG_MINOR_REVISION_SHIFT 0 +#define OMAP44XX_REG_MINOR_REVISION_MASK (0x3f << 0) + +/* STATUS */ +#define OMAP44XX_REG_BE_SHIFT 31 +#define OMAP44XX_REG_BE_MASK (1 << 31) +#define OMAP44XX_REG_DUAL_CLK_MODE_SHIFT 30 +#define OMAP44XX_REG_DUAL_CLK_MODE_MASK (1 << 30) +#define OMAP44XX_REG_FAST_INIT_SHIFT 29 +#define OMAP44XX_REG_FAST_INIT_MASK (1 << 29) +#define OMAP44XX_REG_PHY_DLL_READY_SHIFT 2 +#define OMAP44XX_REG_PHY_DLL_READY_MASK (1 << 2) + +/* SDRAM_CONFIG */ +#define OMAP44XX_REG_SDRAM_TYPE_SHIFT 29 +#define OMAP44XX_REG_SDRAM_TYPE_MASK (0x7 << 29) +#define OMAP44XX_REG_IBANK_POS_SHIFT 27 +#define OMAP44XX_REG_IBANK_POS_MASK (0x3 << 27) +#define OMAP44XX_REG_DDR_TERM_SHIFT 24 +#define OMAP44XX_REG_DDR_TERM_MASK (0x7 << 24) +#define OMAP44XX_REG_DDR2_DDQS_SHIFT 23 +#define OMAP44XX_REG_DDR2_DDQS_MASK (1 << 23) +#define OMAP44XX_REG_DYN_ODT_SHIFT 21 +#define OMAP44XX_REG_DYN_ODT_MASK (0x3 << 21) +#define OMAP44XX_REG_DDR_DISABLE_DLL_SHIFT 20 +#define OMAP44XX_REG_DDR_DISABLE_DLL_MASK (1 << 20) +#define OMAP44XX_REG_SDRAM_DRIVE_SHIFT 18 +#define OMAP44XX_REG_SDRAM_DRIVE_MASK (0x3 << 18) +#define OMAP44XX_REG_CWL_SHIFT 16 +#define OMAP44XX_REG_CWL_MASK (0x3 << 16) +#define OMAP44XX_REG_NARROW_MODE_SHIFT 14 +#define OMAP44XX_REG_NARROW_MODE_MASK (0x3 << 14) +#define OMAP44XX_REG_CL_SHIFT 10 +#define OMAP44XX_REG_CL_MASK (0xf << 10) +#define OMAP44XX_REG_ROWSIZE_SHIFT 7 +#define OMAP44XX_REG_ROWSIZE_MASK (0x7 << 7) +#define OMAP44XX_REG_IBANK_SHIFT 4 +#define OMAP44XX_REG_IBANK_MASK (0x7 << 4) +#define OMAP44XX_REG_EBANK_SHIFT 3 +#define OMAP44XX_REG_EBANK_MASK (1 << 3) +#define OMAP44XX_REG_PAGESIZE_SHIFT 0 +#define OMAP44XX_REG_PAGESIZE_MASK (0x7 << 0) + +/* SDRAM_CONFIG_2 */ +#define OMAP44XX_REG_CS1NVMEN_SHIFT 30 +#define OMAP44XX_REG_CS1NVMEN_MASK (1 << 30) +#define OMAP44XX_REG_EBANK_POS_SHIFT 27 +#define OMAP44XX_REG_EBANK_POS_MASK (1 << 27) +#define OMAP44XX_REG_RDBNUM_SHIFT 4 +#define OMAP44XX_REG_RDBNUM_MASK (0x3 << 4) +#define OMAP44XX_REG_RDBSIZE_SHIFT 0 +#define OMAP44XX_REG_RDBSIZE_MASK (0x7 << 0) + +/* SDRAM_REF_CTRL */ +#define OMAP44XX_REG_INITREF_DIS_SHIFT 31 +#define OMAP44XX_REG_INITREF_DIS_MASK (1 << 31) +#define OMAP44XX_REG_SRT_SHIFT 29 +#define OMAP44XX_REG_SRT_MASK (1 << 29) +#define OMAP44XX_REG_ASR_SHIFT 28 +#define OMAP44XX_REG_ASR_MASK (1 << 28) +#define OMAP44XX_REG_PASR_SHIFT 24 +#define OMAP44XX_REG_PASR_MASK (0x7 << 24) +#define OMAP44XX_REG_REFRESH_RATE_SHIFT 0 +#define OMAP44XX_REG_REFRESH_RATE_MASK (0xffff << 0) + +/* SDRAM_REF_CTRL_SHDW */ +#define OMAP44XX_REG_REFRESH_RATE_SHDW_SHIFT 0 +#define OMAP44XX_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0) + +/* SDRAM_TIM_1 */ +#define OMAP44XX_REG_T_RP_SHIFT 25 +#define OMAP44XX_REG_T_RP_MASK (0xf << 25) +#define OMAP44XX_REG_T_RCD_SHIFT 21 +#define OMAP44XX_REG_T_RCD_MASK (0xf << 21) +#define OMAP44XX_REG_T_WR_SHIFT 17 +#define OMAP44XX_REG_T_WR_MASK (0xf << 17) +#define OMAP44XX_REG_T_RAS_SHIFT 12 +#define OMAP44XX_REG_T_RAS_MASK (0x1f << 12) +#define OMAP44XX_REG_T_RC_SHIFT 6 +#define OMAP44XX_REG_T_RC_MASK (0x3f << 6) +#define OMAP44XX_REG_T_RRD_SHIFT 3 +#define OMAP44XX_REG_T_RRD_MASK (0x7 << 3) +#define OMAP44XX_REG_T_WTR_SHIFT 0 +#define OMAP44XX_REG_T_WTR_MASK (0x7 << 0) + +/* SDRAM_TIM_1_SHDW */ +#define OMAP44XX_REG_T_RP_SHDW_SHIFT 25 +#define OMAP44XX_REG_T_RP_SHDW_MASK (0xf << 25) +#define OMAP44XX_REG_T_RCD_SHDW_SHIFT 21 +#define OMAP44XX_REG_T_RCD_SHDW_MASK (0xf << 21) +#define OMAP44XX_REG_T_WR_SHDW_SHIFT 17 +#define OMAP44XX_REG_T_WR_SHDW_MASK (0xf << 17) +#define OMAP44XX_REG_T_RAS_SHDW_SHIFT 12 +#define OMAP44XX_REG_T_RAS_SHDW_MASK (0x1f << 12) +#define OMAP44XX_REG_T_RC_SHDW_SHIFT 6 +#define OMAP44XX_REG_T_RC_SHDW_MASK (0x3f << 6) +#define OMAP44XX_REG_T_RRD_SHDW_SHIFT 3 +#define OMAP44XX_REG_T_RRD_SHDW_MASK (0x7 << 3) +#define OMAP44XX_REG_T_WTR_SHDW_SHIFT 0 +#define OMAP44XX_REG_T_WTR_SHDW_MASK (0x7 << 0) + +/* SDRAM_TIM_2 */ +#define OMAP44XX_REG_T_XP_SHIFT 28 +#define OMAP44XX_REG_T_XP_MASK (0x7 << 28) +#define OMAP44XX_REG_T_ODT_SHIFT 25 +#define OMAP44XX_REG_T_ODT_MASK (0x7 << 25) +#define OMAP44XX_REG_T_XSNR_SHIFT 16 +#define OMAP44XX_REG_T_XSNR_MASK (0x1ff << 16) +#define OMAP44XX_REG_T_XSRD_SHIFT 6 +#define OMAP44XX_REG_T_XSRD_MASK (0x3ff << 6) +#define OMAP44XX_REG_T_RTP_SHIFT 3 +#define OMAP44XX_REG_T_RTP_MASK (0x7 << 3) +#define OMAP44XX_REG_T_CKE_SHIFT 0 +#define OMAP44XX_REG_T_CKE_MASK (0x7 << 0) + +/* SDRAM_TIM_2_SHDW */ +#define OMAP44XX_REG_T_XP_SHDW_SHIFT 28 +#define OMAP44XX_REG_T_XP_SHDW_MASK (0x7 << 28) +#define OMAP44XX_REG_T_ODT_SHDW_SHIFT 25 +#define OMAP44XX_REG_T_ODT_SHDW_MASK (0x7 << 25) +#define OMAP44XX_REG_T_XSNR_SHDW_SHIFT 16 +#define OMAP44XX_REG_T_XSNR_SHDW_MASK (0x1ff << 16) +#define OMAP44XX_REG_T_XSRD_SHDW_SHIFT 6 +#define OMAP44XX_REG_T_XSRD_SHDW_MASK (0x3ff << 6) +#define OMAP44XX_REG_T_RTP_SHDW_SHIFT 3 +#define OMAP44XX_REG_T_RTP_SHDW_MASK (0x7 << 3) +#define OMAP44XX_REG_T_CKE_SHDW_SHIFT 0 +#define OMAP44XX_REG_T_CKE_SHDW_MASK (0x7 << 0) + +/* SDRAM_TIM_3 */ +#define OMAP44XX_REG_T_CKESR_SHIFT 21 +#define OMAP44XX_REG_T_CKESR_MASK (0x7 << 21) +#define OMAP44XX_REG_ZQ_ZQCS_SHIFT 15 +#define OMAP44XX_REG_ZQ_ZQCS_MASK (0x3f << 15) +#define OMAP44XX_REG_T_TDQSCKMAX_SHIFT 13 +#define OMAP44XX_REG_T_TDQSCKMAX_MASK (0x3 << 13) +#define OMAP44XX_REG_T_RFC_SHIFT 4 +#define OMAP44XX_REG_T_RFC_MASK (0x1ff << 4) +#define OMAP44XX_REG_T_RAS_MAX_SHIFT 0 +#define OMAP44XX_REG_T_RAS_MAX_MASK (0xf << 0) + +/* SDRAM_TIM_3_SHDW */ +#define OMAP44XX_REG_T_CKESR_SHDW_SHIFT 21 +#define OMAP44XX_REG_T_CKESR_SHDW_MASK (0x7 << 21) +#define OMAP44XX_REG_ZQ_ZQCS_SHDW_SHIFT 15 +#define OMAP44XX_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15) +#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_SHIFT 13 +#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13) +#define OMAP44XX_REG_T_RFC_SHDW_SHIFT 4 +#define OMAP44XX_REG_T_RFC_SHDW_MASK (0x1ff << 4) +#define OMAP44XX_REG_T_RAS_MAX_SHDW_SHIFT 0 +#define OMAP44XX_REG_T_RAS_MAX_SHDW_MASK (0xf << 0) + +/* LPDDR2_NVM_TIM */ +#define OMAP44XX_REG_NVM_T_XP_SHIFT 28 +#define OMAP44XX_REG_NVM_T_XP_MASK (0x7 << 28) +#define OMAP44XX_REG_NVM_T_WTR_SHIFT 24 +#define OMAP44XX_REG_NVM_T_WTR_MASK (0x7 << 24) +#define OMAP44XX_REG_NVM_T_RP_SHIFT 20 +#define OMAP44XX_REG_NVM_T_RP_MASK (0xf << 20) +#define OMAP44XX_REG_NVM_T_WRA_SHIFT 16 +#define OMAP44XX_REG_NVM_T_WRA_MASK (0xf << 16) +#define OMAP44XX_REG_NVM_T_RRD_SHIFT 8 +#define OMAP44XX_REG_NVM_T_RRD_MASK (0xff << 8) +#define OMAP44XX_REG_NVM_T_RCDMIN_SHIFT 0 +#define OMAP44XX_REG_NVM_T_RCDMIN_MASK (0xff << 0) + +/* LPDDR2_NVM_TIM_SHDW */ +#define OMAP44XX_REG_NVM_T_XP_SHDW_SHIFT 28 +#define OMAP44XX_REG_NVM_T_XP_SHDW_MASK (0x7 << 28) +#define OMAP44XX_REG_NVM_T_WTR_SHDW_SHIFT 24 +#define OMAP44XX_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24) +#define OMAP44XX_REG_NVM_T_RP_SHDW_SHIFT 20 +#define OMAP44XX_REG_NVM_T_RP_SHDW_MASK (0xf << 20) +#define OMAP44XX_REG_NVM_T_WRA_SHDW_SHIFT 16 +#define OMAP44XX_REG_NVM_T_WRA_SHDW_MASK (0xf << 16) +#define OMAP44XX_REG_NVM_T_RRD_SHDW_SHIFT 8 +#define OMAP44XX_REG_NVM_T_RRD_SHDW_MASK (0xff << 8) +#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_SHIFT 0 +#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0) + +/* PWR_MGMT_CTRL */ +#define OMAP44XX_REG_IDLEMODE_SHIFT 30 +#define OMAP44XX_REG_IDLEMODE_MASK (0x3 << 30) +#define OMAP44XX_REG_PD_TIM_SHIFT 12 +#define OMAP44XX_REG_PD_TIM_MASK (0xf << 12) +#define OMAP44XX_REG_DPD_EN_SHIFT 11 +#define OMAP44XX_REG_DPD_EN_MASK (1 << 11) +#define OMAP44XX_REG_LP_MODE_SHIFT 8 +#define OMAP44XX_REG_LP_MODE_MASK (0x7 << 8) +#define OMAP44XX_REG_SR_TIM_SHIFT 4 +#define OMAP44XX_REG_SR_TIM_MASK (0xf << 4) +#define OMAP44XX_REG_CS_TIM_SHIFT 0 +#define OMAP44XX_REG_CS_TIM_MASK (0xf << 0) + +/* PWR_MGMT_CTRL_SHDW */ +#define OMAP44XX_REG_PD_TIM_SHDW_SHIFT 8 +#define OMAP44XX_REG_PD_TIM_SHDW_MASK (0xf << 8) +#define OMAP44XX_REG_SR_TIM_SHDW_SHIFT 4 +#define OMAP44XX_REG_SR_TIM_SHDW_MASK (0xf << 4) +#define OMAP44XX_REG_CS_TIM_SHDW_SHIFT 0 +#define OMAP44XX_REG_CS_TIM_SHDW_MASK (0xf << 0) + +/* LPDDR2_MODE_REG_DATA */ +#define OMAP44XX_REG_VALUE_0_SHIFT 0 +#define OMAP44XX_REG_VALUE_0_MASK (0x7f << 0) + +/* LPDDR2_MODE_REG_CFG */ +#define OMAP44XX_REG_CS_SHIFT 31 +#define OMAP44XX_REG_CS_MASK (1 << 31) +#define OMAP44XX_REG_REFRESH_EN_SHIFT 30 +#define OMAP44XX_REG_REFRESH_EN_MASK (1 << 30) +#define OMAP44XX_REG_ADDRESS_SHIFT 0 +#define OMAP44XX_REG_ADDRESS_MASK (0xff << 0) + +/* OCP_CONFIG */ +#define OMAP44XX_REG_SYS_THRESH_MAX_SHIFT 24 +#define OMAP44XX_REG_SYS_THRESH_MAX_MASK (0xf << 24) +#define OMAP44XX_REG_MPU_THRESH_MAX_SHIFT 20 +#define OMAP44XX_REG_MPU_THRESH_MAX_MASK (0xf << 20) +#define OMAP44XX_REG_LL_THRESH_MAX_SHIFT 16 +#define OMAP44XX_REG_LL_THRESH_MAX_MASK (0xf << 16) +#define OMAP44XX_REG_PR_OLD_COUNT_SHIFT 0 +#define OMAP44XX_REG_PR_OLD_COUNT_MASK (0xff << 0) + +/* OCP_CFG_VAL_1 */ +#define OMAP44XX_REG_SYS_BUS_WIDTH_SHIFT 30 +#define OMAP44XX_REG_SYS_BUS_WIDTH_MASK (0x3 << 30) +#define OMAP44XX_REG_LL_BUS_WIDTH_SHIFT 28 +#define OMAP44XX_REG_LL_BUS_WIDTH_MASK (0x3 << 28) +#define OMAP44XX_REG_WR_FIFO_DEPTH_SHIFT 8 +#define OMAP44XX_REG_WR_FIFO_DEPTH_MASK (0xff << 8) +#define OMAP44XX_REG_CMD_FIFO_DEPTH_SHIFT 0 +#define OMAP44XX_REG_CMD_FIFO_DEPTH_MASK (0xff << 0) + +/* OCP_CFG_VAL_2 */ +#define OMAP44XX_REG_RREG_FIFO_DEPTH_SHIFT 16 +#define OMAP44XX_REG_RREG_FIFO_DEPTH_MASK (0xff << 16) +#define OMAP44XX_REG_RSD_FIFO_DEPTH_SHIFT 8 +#define OMAP44XX_REG_RSD_FIFO_DEPTH_MASK (0xff << 8) +#define OMAP44XX_REG_RCMD_FIFO_DEPTH_SHIFT 0 +#define OMAP44XX_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0) + +/* IODFT_TLGC */ +#define OMAP44XX_REG_TLEC_SHIFT 16 +#define OMAP44XX_REG_TLEC_MASK (0xffff << 16) +#define OMAP44XX_REG_MT_SHIFT 14 +#define OMAP44XX_REG_MT_MASK (1 << 14) +#define OMAP44XX_REG_ACT_CAP_EN_SHIFT 13 +#define OMAP44XX_REG_ACT_CAP_EN_MASK (1 << 13) +#define OMAP44XX_REG_OPG_LD_SHIFT 12 +#define OMAP44XX_REG_OPG_LD_MASK (1 << 12) +#define OMAP44XX_REG_RESET_PHY_SHIFT 10 +#define OMAP44XX_REG_RESET_PHY_MASK (1 << 10) +#define OMAP44XX_REG_MMS_SHIFT 8 +#define OMAP44XX_REG_MMS_MASK (1 << 8) +#define OMAP44XX_REG_MC_SHIFT 4 +#define OMAP44XX_REG_MC_MASK (0x3 << 4) +#define OMAP44XX_REG_PC_SHIFT 1 +#define OMAP44XX_REG_PC_MASK (0x7 << 1) +#define OMAP44XX_REG_TM_SHIFT 0 +#define OMAP44XX_REG_TM_MASK (1 << 0) + +/* IODFT_CTRL_MISR_RSLT */ +#define OMAP44XX_REG_DQM_TLMR_SHIFT 16 +#define OMAP44XX_REG_DQM_TLMR_MASK (0x3ff << 16) +#define OMAP44XX_REG_CTL_TLMR_SHIFT 0 +#define OMAP44XX_REG_CTL_TLMR_MASK (0x7ff << 0) + +/* IODFT_ADDR_MISR_RSLT */ +#define OMAP44XX_REG_ADDR_TLMR_SHIFT 0 +#define OMAP44XX_REG_ADDR_TLMR_MASK (0x1fffff << 0) + +/* IODFT_DATA_MISR_RSLT_1 */ +#define OMAP44XX_REG_DATA_TLMR_31_0_SHIFT 0 +#define OMAP44XX_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0) + +/* IODFT_DATA_MISR_RSLT_2 */ +#define OMAP44XX_REG_DATA_TLMR_63_32_SHIFT 0 +#define OMAP44XX_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0) + +/* IODFT_DATA_MISR_RSLT_3 */ +#define OMAP44XX_REG_DATA_TLMR_66_64_SHIFT 0 +#define OMAP44XX_REG_DATA_TLMR_66_64_MASK (0x7 << 0) + +/* PERF_CNT_1 */ +#define OMAP44XX_REG_COUNTER1_SHIFT 0 +#define OMAP44XX_REG_COUNTER1_MASK (0xffffffff << 0) + +/* PERF_CNT_2 */ +#define OMAP44XX_REG_COUNTER2_SHIFT 0 +#define OMAP44XX_REG_COUNTER2_MASK (0xffffffff << 0) + +/* PERF_CNT_CFG */ +#define OMAP44XX_REG_CNTR2_MCONNID_EN_SHIFT 31 +#define OMAP44XX_REG_CNTR2_MCONNID_EN_MASK (1 << 31) +#define OMAP44XX_REG_CNTR2_REGION_EN_SHIFT 30 +#define OMAP44XX_REG_CNTR2_REGION_EN_MASK (1 << 30) +#define OMAP44XX_REG_CNTR2_CFG_SHIFT 16 +#define OMAP44XX_REG_CNTR2_CFG_MASK (0xf << 16) +#define OMAP44XX_REG_CNTR1_MCONNID_EN_SHIFT 15 +#define OMAP44XX_REG_CNTR1_MCONNID_EN_MASK (1 << 15) +#define OMAP44XX_REG_CNTR1_REGION_EN_SHIFT 14 +#define OMAP44XX_REG_CNTR1_REGION_EN_MASK (1 << 14) +#define OMAP44XX_REG_CNTR1_CFG_SHIFT 0 +#define OMAP44XX_REG_CNTR1_CFG_MASK (0xf << 0) + +/* PERF_CNT_SEL */ +#define OMAP44XX_REG_MCONNID2_SHIFT 24 +#define OMAP44XX_REG_MCONNID2_MASK (0xff << 24) +#define OMAP44XX_REG_REGION_SEL2_SHIFT 16 +#define OMAP44XX_REG_REGION_SEL2_MASK (0x3 << 16) +#define OMAP44XX_REG_MCONNID1_SHIFT 8 +#define OMAP44XX_REG_MCONNID1_MASK (0xff << 8) +#define OMAP44XX_REG_REGION_SEL1_SHIFT 0 +#define OMAP44XX_REG_REGION_SEL1_MASK (0x3 << 0) + +/* PERF_CNT_TIM */ +#define OMAP44XX_REG_TOTAL_TIME_SHIFT 0 +#define OMAP44XX_REG_TOTAL_TIME_MASK (0xffffffff << 0) + +/* READ_IDLE_CTRL */ +#define OMAP44XX_REG_READ_IDLE_LEN_SHIFT 16 +#define OMAP44XX_REG_READ_IDLE_LEN_MASK (0xf << 16) +#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT 0 +#define OMAP44XX_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0) + +/* READ_IDLE_CTRL_SHDW */ +#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_SHIFT 16 +#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16) +#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0 +#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0) + +/* IRQ_EOI */ +#define OMAP44XX_REG_EOI_SHIFT 0 +#define OMAP44XX_REG_EOI_MASK (1 << 0) + +/* IRQSTATUS_RAW_SYS */ +#define OMAP44XX_REG_DNV_SYS_SHIFT 2 +#define OMAP44XX_REG_DNV_SYS_MASK (1 << 2) +#define OMAP44XX_REG_TA_SYS_SHIFT 1 +#define OMAP44XX_REG_TA_SYS_MASK (1 << 1) +#define OMAP44XX_REG_ERR_SYS_SHIFT 0 +#define OMAP44XX_REG_ERR_SYS_MASK (1 << 0) + +/* IRQSTATUS_RAW_LL */ +#define OMAP44XX_REG_DNV_LL_SHIFT 2 +#define OMAP44XX_REG_DNV_LL_MASK (1 << 2) +#define OMAP44XX_REG_TA_LL_SHIFT 1 +#define OMAP44XX_REG_TA_LL_MASK (1 << 1) +#define OMAP44XX_REG_ERR_LL_SHIFT 0 +#define OMAP44XX_REG_ERR_LL_MASK (1 << 0) + +/* IRQSTATUS_SYS */ + +/* IRQSTATUS_LL */ + +/* IRQENABLE_SET_SYS */ +#define OMAP44XX_REG_EN_DNV_SYS_SHIFT 2 +#define OMAP44XX_REG_EN_DNV_SYS_MASK (1 << 2) +#define OMAP44XX_REG_EN_TA_SYS_SHIFT 1 +#define OMAP44XX_REG_EN_TA_SYS_MASK (1 << 1) +#define OMAP44XX_REG_EN_ERR_SYS_SHIFT 0 +#define OMAP44XX_REG_EN_ERR_SYS_MASK (1 << 0) + +/* IRQENABLE_SET_LL */ +#define OMAP44XX_REG_EN_DNV_LL_SHIFT 2 +#define OMAP44XX_REG_EN_DNV_LL_MASK (1 << 2) +#define OMAP44XX_REG_EN_TA_LL_SHIFT 1 +#define OMAP44XX_REG_EN_TA_LL_MASK (1 << 1) +#define OMAP44XX_REG_EN_ERR_LL_SHIFT 0 +#define OMAP44XX_REG_EN_ERR_LL_MASK (1 << 0) + +/* IRQENABLE_CLR_SYS */ + +/* IRQENABLE_CLR_LL */ + +/* ZQ_CONFIG */ +#define OMAP44XX_REG_ZQ_CS1EN_SHIFT 31 +#define OMAP44XX_REG_ZQ_CS1EN_MASK (1 << 31) +#define OMAP44XX_REG_ZQ_CS0EN_SHIFT 30 +#define OMAP44XX_REG_ZQ_CS0EN_MASK (1 << 30) +#define OMAP44XX_REG_ZQ_DUALCALEN_SHIFT 29 +#define OMAP44XX_REG_ZQ_DUALCALEN_MASK (1 << 29) +#define OMAP44XX_REG_ZQ_SFEXITEN_SHIFT 28 +#define OMAP44XX_REG_ZQ_SFEXITEN_MASK (1 << 28) +#define OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT 18 +#define OMAP44XX_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18) +#define OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT 16 +#define OMAP44XX_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16) +#define OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT 0 +#define OMAP44XX_REG_ZQ_REFINTERVAL_MASK (0xffff << 0) + +/* TEMP_ALERT_CONFIG */ +#define OMAP44XX_REG_TA_CS1EN_SHIFT 31 +#define OMAP44XX_REG_TA_CS1EN_MASK (1 << 31) +#define OMAP44XX_REG_TA_CS0EN_SHIFT 30 +#define OMAP44XX_REG_TA_CS0EN_MASK (1 << 30) +#define OMAP44XX_REG_TA_SFEXITEN_SHIFT 28 +#define OMAP44XX_REG_TA_SFEXITEN_MASK (1 << 28) +#define OMAP44XX_REG_TA_DEVWDT_SHIFT 26 +#define OMAP44XX_REG_TA_DEVWDT_MASK (0x3 << 26) +#define OMAP44XX_REG_TA_DEVCNT_SHIFT 24 +#define OMAP44XX_REG_TA_DEVCNT_MASK (0x3 << 24) +#define OMAP44XX_REG_TA_REFINTERVAL_SHIFT 0 +#define OMAP44XX_REG_TA_REFINTERVAL_MASK (0x3fffff << 0) + +/* OCP_ERR_LOG */ +#define OMAP44XX_REG_MADDRSPACE_SHIFT 14 +#define OMAP44XX_REG_MADDRSPACE_MASK (0x3 << 14) +#define OMAP44XX_REG_MBURSTSEQ_SHIFT 11 +#define OMAP44XX_REG_MBURSTSEQ_MASK (0x7 << 11) +#define OMAP44XX_REG_MCMD_SHIFT 8 +#define OMAP44XX_REG_MCMD_MASK (0x7 << 8) +#define OMAP44XX_REG_MCONNID_SHIFT 0 +#define OMAP44XX_REG_MCONNID_MASK (0xff << 0) + +/* DDR_PHY_CTRL_1 */ +#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHIFT 4 +#define OMAP44XX_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4) +#define OMAP44XX_REG_READ_LATENCY_SHIFT 0 +#define OMAP44XX_REG_READ_LATENCY_MASK (0xf << 0) +#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4 +#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4) +#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12 +#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12) + +/* DDR_PHY_CTRL_1_SHDW */ +#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4 +#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4) +#define OMAP44XX_REG_READ_LATENCY_SHDW_SHIFT 0 +#define OMAP44XX_REG_READ_LATENCY_SHDW_MASK (0xf << 0) +#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4 +#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4) +#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12 +#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12) + +/* DDR_PHY_CTRL_2 */ +#define OMAP44XX_REG_DDR_PHY_CTRL_2_SHIFT 0 +#define OMAP44XX_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0) + +/* DMM */ +#define OMAP44XX_DMM_LISA_MAP_BASE 0x4E000040 + +/* Memory Adapter (4460 onwards) */ +#define OMAP44XX_MA_LISA_MAP_BASE 0x482AF040 + +/* DMM_LISA_MAP */ +#define OMAP44XX_SYS_ADDR_SHIFT 24 +#define OMAP44XX_SYS_ADDR_MASK (0xff << 24) +#define OMAP44XX_SYS_SIZE_SHIFT 20 +#define OMAP44XX_SYS_SIZE_MASK (0x7 << 20) +#define OMAP44XX_SDRC_INTL_SHIFT 18 +#define OMAP44XX_SDRC_INTL_MASK (0x3 << 18) +#define OMAP44XX_SDRC_ADDRSPC_SHIFT 16 +#define OMAP44XX_SDRC_ADDRSPC_MASK (0x3 << 16) +#define OMAP44XX_SDRC_MAP_SHIFT 8 +#define OMAP44XX_SDRC_MAP_MASK (0x3 << 8) +#define OMAP44XX_SDRC_ADDR_SHIFT 0 +#define OMAP44XX_SDRC_ADDR_MASK (0xff << 0) + +/* DMM_LISA_MAP fields */ +#define DMM_SDRC_MAP_UNMAPPED 0 +#define DMM_SDRC_MAP_EMIF1_ONLY 1 +#define DMM_SDRC_MAP_EMIF2_ONLY 2 +#define DMM_SDRC_MAP_EMIF1_AND_EMIF2 3 + +#define DMM_SDRC_INTL_NONE 0 +#define DMM_SDRC_INTL_128B 1 +#define DMM_SDRC_INTL_256B 2 +#define DMM_SDRC_INTL_512 3 + +#define DMM_SDRC_ADDR_SPC_SDRAM 0 +#define DMM_SDRC_ADDR_SPC_NVM 1 +#define DMM_SDRC_ADDR_SPC_INVALID 2 + +#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL (\ + (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << OMAP44XX_SDRC_MAP_SHIFT) |\ + (DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT) |\ + (DMM_SDRC_INTL_128B << OMAP44XX_SDRC_INTL_SHIFT) |\ + (CONFIG_SYS_SDRAM_BASE << OMAP44XX_SYS_ADDR_SHIFT)) + +#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\ + (DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ + (DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ + (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)) + +#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL (\ + (DMM_SDRC_MAP_EMIF2_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ + (DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ + (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)) + +/* Trap for invalid TILER PAT entries */ +#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\ + (0 << OMAP44XX_SDRC_ADDR_SHIFT) |\ + (DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ + (DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ + (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\ + (0xFF << OMAP44XX_SYS_ADDR_SHIFT)) + + +/* Reg mapping structure */ +struct emif_reg_struct { + u32 emif_mod_id_rev; + u32 emif_status; + u32 emif_sdram_config; + u32 emif_lpddr2_nvm_config; + u32 emif_sdram_ref_ctrl; + u32 emif_sdram_ref_ctrl_shdw; + u32 emif_sdram_tim_1; + u32 emif_sdram_tim_1_shdw; + u32 emif_sdram_tim_2; + u32 emif_sdram_tim_2_shdw; + u32 emif_sdram_tim_3; + u32 emif_sdram_tim_3_shdw; + u32 emif_lpddr2_nvm_tim; + u32 emif_lpddr2_nvm_tim_shdw; + u32 emif_pwr_mgmt_ctrl; + u32 emif_pwr_mgmt_ctrl_shdw; + u32 emif_lpddr2_mode_reg_data; + u32 padding1[1]; + u32 emif_lpddr2_mode_reg_data_es2; + u32 padding11[1]; + u32 emif_lpddr2_mode_reg_cfg; + u32 emif_l3_config; + u32 emif_l3_cfg_val_1; + u32 emif_l3_cfg_val_2; + u32 emif_iodft_tlgc; + u32 padding2[7]; + u32 emif_perf_cnt_1; + u32 emif_perf_cnt_2; + u32 emif_perf_cnt_cfg; + u32 emif_perf_cnt_sel; + u32 emif_perf_cnt_tim; + u32 padding3; + u32 emif_read_idlectrl; + u32 emif_read_idlectrl_shdw; + u32 padding4; + u32 emif_irqstatus_raw_sys; + u32 emif_irqstatus_raw_ll; + u32 emif_irqstatus_sys; + u32 emif_irqstatus_ll; + u32 emif_irqenable_set_sys; + u32 emif_irqenable_set_ll; + u32 emif_irqenable_clr_sys; + u32 emif_irqenable_clr_ll; + u32 padding5; + u32 emif_zq_config; + u32 emif_temp_alert_config; + u32 emif_l3_err_log; + u32 padding6[4]; + u32 emif_ddr_phy_ctrl_1; + u32 emif_ddr_phy_ctrl_1_shdw; + u32 emif_ddr_phy_ctrl_2; +}; + +struct dmm_lisa_map_regs { + u32 dmm_lisa_map_0; + u32 dmm_lisa_map_1; + u32 dmm_lisa_map_2; + u32 dmm_lisa_map_3; +}; + +struct control_lpddr2io_regs { + u32 control_lpddr2io1_0; + u32 control_lpddr2io1_1; + u32 control_lpddr2io1_2; + u32 control_lpddr2io1_3; + u32 control_lpddr2io2_0; + u32 control_lpddr2io2_1; + u32 control_lpddr2io2_2; + u32 control_lpddr2io2_3; +}; + +#define CS0 0 +#define CS1 1 +/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/ +#define MAX_LPDDR2_FREQ 400000000 /* 400 MHz */ + +/* + * The period of DDR clk is represented as numerator and denominator for + * better accuracy in integer based calculations. However, if the numerator + * and denominator are very huge there may be chances of overflow in + * calculations. So, as a trade-off keep denominator(and consequently + * numerator) within a limit sacrificing some accuracy - but not much + * If denominator and numerator are already small (such as at 400 MHz) + * no adjustment is needed + */ +#define EMIF_PERIOD_DEN_LIMIT 1000 +/* + * Maximum number of different frequencies supported by EMIF driver + * Determines the number of entries in the pointer array for register + * cache + */ +#define EMIF_MAX_NUM_FREQUENCIES 6 +/* + * Indices into the Addressing Table array. + * One entry each for all the different types of devices with different + * addressing schemes + */ +#define ADDR_TABLE_INDEX64M 0 +#define ADDR_TABLE_INDEX128M 1 +#define ADDR_TABLE_INDEX256M 2 +#define ADDR_TABLE_INDEX512M 3 +#define ADDR_TABLE_INDEX1GS4 4 +#define ADDR_TABLE_INDEX2GS4 5 +#define ADDR_TABLE_INDEX4G 6 +#define ADDR_TABLE_INDEX8G 7 +#define ADDR_TABLE_INDEX1GS2 8 +#define ADDR_TABLE_INDEX2GS2 9 +#define ADDR_TABLE_INDEXMAX 10 + +/* Number of Row bits */ +#define ROW_9 0 +#define ROW_10 1 +#define ROW_11 2 +#define ROW_12 3 +#define ROW_13 4 +#define ROW_14 5 +#define ROW_15 6 +#define ROW_16 7 + +/* Number of Column bits */ +#define COL_8 0 +#define COL_9 1 +#define COL_10 2 +#define COL_11 3 +#define COL_7 4 /*Not supported by OMAP included for completeness */ + +/* Number of Banks*/ +#define BANKS1 0 +#define BANKS2 1 +#define BANKS4 2 +#define BANKS8 3 + +/* Refresh rate in micro seconds x 10 */ +#define T_REFI_15_6 156 +#define T_REFI_7_8 78 +#define T_REFI_3_9 39 + +#define EBANK_CS1_DIS 0 +#define EBANK_CS1_EN 1 + +/* Read Latency used by the device at reset */ +#define RL_BOOT 3 +/* Read Latency for the highest frequency you want to use */ +#define RL_FINAL 6 + +/* Interleaving policies at EMIF level- between banks and Chip Selects */ +#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0 +#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3 + +/* + * Interleaving policy to be used + * Currently set to MAX interleaving for better performance + */ +#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING + +/* State of the core voltage: + * This is important for some parameters such as read idle control and + * ZQ calibration timings. Timings are much stricter when voltage ramp + * is happening compared to when the voltage is stable. + * We need to calculate two sets of values for these parameters and use + * them accordingly + */ +#define LPDDR2_VOLTAGE_STABLE 0 +#define LPDDR2_VOLTAGE_RAMPING 1 + +/* Length of the forced read idle period in terms of cycles */ +#define EMIF_REG_READ_IDLE_LEN_VAL 5 + +/* Interval between forced 'read idles' */ +/* To be used when voltage is changed for DPS/DVFS - 1us */ +#define READ_IDLE_INTERVAL_DVFS (1*1000) +/* + * To be used when voltage is not scaled except by Smart Reflex + * 50us - or maximum value will do + */ +#define READ_IDLE_INTERVAL_NORMAL (50*1000) + + +/* + * Unless voltage is changing due to DVFS one ZQCS command every 50ms should + * be enough. This shoule be enough also in the case when voltage is changing + * due to smart-reflex. + */ +#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US (50*1000) +/* + * If voltage is changing due to DVFS ZQCS should be performed more + * often(every 50us) + */ +#define EMIF_ZQCS_INTERVAL_DVFS_IN_US 50 + +/* The interval between ZQCL commands as a multiple of ZQCS interval */ +#define REG_ZQ_ZQCL_MULT 4 +/* The interval between ZQINIT commands as a multiple of ZQCL interval */ +#define REG_ZQ_ZQINIT_MULT 3 +/* Enable ZQ Calibration on exiting Self-refresh */ +#define REG_ZQ_SFEXITEN_ENABLE 1 +/* + * ZQ Calibration simultaneously on both chip-selects: + * Needs one calibration resistor per CS + * None of the boards that we know of have this capability + * So disabled by default + */ +#define REG_ZQ_DUALCALEN_DISABLE 0 +/* + * Enable ZQ Calibration by default on CS0. If we are asked to program + * the EMIF there will be something connected to CS0 for sure + */ +#define REG_ZQ_CS0EN_ENABLE 1 + +/* EMIF_PWR_MGMT_CTRL register */ +/* Low power modes */ +#define LP_MODE_DISABLE 0 +#define LP_MODE_CLOCK_STOP 1 +#define LP_MODE_SELF_REFRESH 2 +#define LP_MODE_PWR_DN 3 + +/* REG_DPD_EN */ +#define DPD_DISABLE 0 +#define DPD_ENABLE 1 + +/* Maximum delay before Low Power Modes */ +#define REG_CS_TIM 0xF +#define REG_SR_TIM 0xF +#define REG_PD_TIM 0xF + +/* EMIF_PWR_MGMT_CTRL register */ +#define EMIF_PWR_MGMT_CTRL (\ + ((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHIFT) & OMAP44XX_REG_CS_TIM_MASK)|\ + ((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHIFT) & OMAP44XX_REG_SR_TIM_MASK)|\ + ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\ + ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\ + ((LP_MODE_DISABLE << OMAP44XX_REG_LP_MODE_SHIFT)\ + & OMAP44XX_REG_LP_MODE_MASK) |\ + ((DPD_DISABLE << OMAP44XX_REG_DPD_EN_SHIFT)\ + & OMAP44XX_REG_DPD_EN_MASK))\ + +#define EMIF_PWR_MGMT_CTRL_SHDW (\ + ((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHDW_SHIFT)\ + & OMAP44XX_REG_CS_TIM_SHDW_MASK) |\ + ((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHDW_SHIFT)\ + & OMAP44XX_REG_SR_TIM_SHDW_MASK) |\ + ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\ + & OMAP44XX_REG_PD_TIM_SHDW_MASK) |\ + ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\ + & OMAP44XX_REG_PD_TIM_SHDW_MASK)) + +/* EMIF_L3_CONFIG register value */ +#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF +#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000 +/* + * Value of bits 12:31 of DDR_PHY_CTRL_1 register: + * All these fields have magic values dependent on frequency and + * determined by PHY and DLL integration with EMIF. Setting the magic + * values suggested by hw team. + */ +#define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF +#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41 +#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80 +#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF + +/* +* MR1 value: +* Burst length : 8 +* Burst type : sequential +* Wrap : enabled +* nWR : 3(default). EMIF does not do pre-charge. +* : So nWR is don't care +*/ +#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23 + +/* MR2 */ +#define MR2_RL3_WL1 1 +#define MR2_RL4_WL2 2 +#define MR2_RL5_WL2 3 +#define MR2_RL6_WL3 4 + +/* MR10: ZQ calibration codes */ +#define MR10_ZQ_ZQCS 0x56 +#define MR10_ZQ_ZQCL 0xAB +#define MR10_ZQ_ZQINIT 0xFF +#define MR10_ZQ_ZQRESET 0xC3 + +/* TEMP_ALERT_CONFIG */ +#define TEMP_ALERT_POLL_INTERVAL_MS 360 /* for temp gradient - 5 C/s */ +#define TEMP_ALERT_CONFIG_DEVCT_1 0 +#define TEMP_ALERT_CONFIG_DEVWDT_32 2 + +/* MR16 value: refresh full array(no partial array self refresh) */ +#define MR16_REF_FULL_ARRAY 0 + +/* LPDDR2 IO regs */ +#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C +#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E + +/* CONTROL_EFUSE_2 */ +#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 + +/* + * Maximum number of entries we keep in our array of timing tables + * We need not keep all the speed bins supported by the device + * We need to keep timing tables for only the speed bins that we + * are interested in + */ +#define MAX_NUM_SPEEDBINS 4 + +/* LPDDR2 Densities */ +#define LPDDR2_DENSITY_64Mb 0 +#define LPDDR2_DENSITY_128Mb 1 +#define LPDDR2_DENSITY_256Mb 2 +#define LPDDR2_DENSITY_512Mb 3 +#define LPDDR2_DENSITY_1Gb 4 +#define LPDDR2_DENSITY_2Gb 5 +#define LPDDR2_DENSITY_4Gb 6 +#define LPDDR2_DENSITY_8Gb 7 +#define LPDDR2_DENSITY_16Gb 8 +#define LPDDR2_DENSITY_32Gb 9 + +/* LPDDR2 type */ +#define LPDDR2_TYPE_S4 0 +#define LPDDR2_TYPE_S2 1 +#define LPDDR2_TYPE_NVM 2 + +/* LPDDR2 IO width */ +#define LPDDR2_IO_WIDTH_32 0 +#define LPDDR2_IO_WIDTH_16 1 +#define LPDDR2_IO_WIDTH_8 2 + +/* Mode register numbers */ +#define LPDDR2_MR0 0 +#define LPDDR2_MR1 1 +#define LPDDR2_MR2 2 +#define LPDDR2_MR3 3 +#define LPDDR2_MR4 4 +#define LPDDR2_MR5 5 +#define LPDDR2_MR6 6 +#define LPDDR2_MR7 7 +#define LPDDR2_MR8 8 +#define LPDDR2_MR9 9 +#define LPDDR2_MR10 10 +#define LPDDR2_MR11 11 +#define LPDDR2_MR16 16 +#define LPDDR2_MR17 17 +#define LPDDR2_MR18 18 + +/* MR0 */ +#define LPDDR2_MR0_DAI_SHIFT 0 +#define LPDDR2_MR0_DAI_MASK 1 +#define LPDDR2_MR0_DI_SHIFT 1 +#define LPDDR2_MR0_DI_MASK (1 << 1) +#define LPDDR2_MR0_DNVI_SHIFT 2 +#define LPDDR2_MR0_DNVI_MASK (1 << 2) + +/* MR4 */ +#define MR4_SDRAM_REF_RATE_SHIFT 0 +#define MR4_SDRAM_REF_RATE_MASK 7 +#define MR4_TUF_SHIFT 7 +#define MR4_TUF_MASK (1 << 7) + +/* MR4 SDRAM Refresh Rate field values */ +#define SDRAM_TEMP_LESS_LOW_SHUTDOWN 0x0 +#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS 0x1 +#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS 0x2 +#define SDRAM_TEMP_NOMINAL 0x3 +#define SDRAM_TEMP_RESERVED_4 0x4 +#define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5 +#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6 +#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7 + +#define LPDDR2_MANUFACTURER_SAMSUNG 1 +#define LPDDR2_MANUFACTURER_QIMONDA 2 +#define LPDDR2_MANUFACTURER_ELPIDA 3 +#define LPDDR2_MANUFACTURER_ETRON 4 +#define LPDDR2_MANUFACTURER_NANYA 5 +#define LPDDR2_MANUFACTURER_HYNIX 6 +#define LPDDR2_MANUFACTURER_MOSEL 7 +#define LPDDR2_MANUFACTURER_WINBOND 8 +#define LPDDR2_MANUFACTURER_ESMT 9 +#define LPDDR2_MANUFACTURER_SPANSION 11 +#define LPDDR2_MANUFACTURER_SST 12 +#define LPDDR2_MANUFACTURER_ZMOS 13 +#define LPDDR2_MANUFACTURER_INTEL 14 +#define LPDDR2_MANUFACTURER_NUMONYX 254 +#define LPDDR2_MANUFACTURER_MICRON 255 + +/* MR8 register fields */ +#define MR8_TYPE_SHIFT 0x0 +#define MR8_TYPE_MASK 0x3 +#define MR8_DENSITY_SHIFT 0x2 +#define MR8_DENSITY_MASK (0xF << 0x2) +#define MR8_IO_WIDTH_SHIFT 0x6 +#define MR8_IO_WIDTH_MASK (0x3 << 0x6) + +struct lpddr2_addressing { + u8 num_banks; + u8 t_REFI_us_x10; + u8 row_sz[2]; /* One entry each for x32 and x16 */ + u8 col_sz[2]; /* One entry each for x32 and x16 */ +}; + +/* Structure for timings from the DDR datasheet */ +struct lpddr2_ac_timings { + u32 max_freq; + u8 RL; + u8 tRPab; + u8 tRCD; + u8 tWR; + u8 tRASmin; + u8 tRRD; + u8 tWTRx2; + u8 tXSR; + u8 tXPx2; + u8 tRFCab; + u8 tRTPx2; + u8 tCKE; + u8 tCKESR; + u8 tZQCS; + u32 tZQCL; + u32 tZQINIT; + u8 tDQSCKMAXx2; + u8 tRASmax; + u8 tFAW; + +}; + +/* + * Min tCK values for some of the parameters: + * If the calculated clock cycles for the respective parameter is + * less than the corresponding min tCK value, we need to set the min + * tCK value. This may happen at lower frequencies. + */ +struct lpddr2_min_tck { + u32 tRL; + u32 tRP_AB; + u32 tRCD; + u32 tWR; + u32 tRAS_MIN; + u32 tRRD; + u32 tWTR; + u32 tXP; + u32 tRTP; + u8 tCKE; + u32 tCKESR; + u32 tFAW; +}; + +struct lpddr2_device_details { + u8 type; + u8 density; + u8 io_width; + u8 manufacturer; +}; + +struct lpddr2_device_timings { + const struct lpddr2_ac_timings **ac_timings; + const struct lpddr2_min_tck *min_tck; +}; + +/* Details of the devices connected to each chip-select of an EMIF instance */ +struct emif_device_details { + const struct lpddr2_device_details *cs0_device_details; + const struct lpddr2_device_details *cs1_device_details; + const struct lpddr2_device_timings *cs0_device_timings; + const struct lpddr2_device_timings *cs1_device_timings; +}; + +/* + * Structure containing shadow of important registers in EMIF + * The calculation function fills in this structure to be later used for + * initialization and DVFS + */ +struct emif_regs { + u32 freq; + u32 sdram_config_init; + u32 sdram_config; + u32 ref_ctrl; + u32 sdram_tim1; + u32 sdram_tim2; + u32 sdram_tim3; + u32 read_idle_ctrl; + u32 zq_config; + u32 temp_alert_config; + u32 emif_ddr_phy_ctlr_1_init; + u32 emif_ddr_phy_ctlr_1; +}; + +/* assert macros */ +#if defined(DEBUG) +#define emif_assert(c) ({ if (!(c)) for (;;); }) +#else +#define emif_assert(c) ({ if (0) hang(); }) +#endif + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs); +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs); +#else +void emif_get_device_details(u32 emif_nr, + struct lpddr2_device_details *cs0_device_details, + struct lpddr2_device_details *cs1_device_details); +void emif_get_device_timings(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings); +#endif + +#endif diff --git a/arch/arm/include/asm/arch-omap4/mux_omap4.h b/arch/arm/include/asm/arch-omap4/mux_omap4.h index 019574b..30bfad7 100644 --- a/arch/arm/include/asm/arch-omap4/mux_omap4.h +++ b/arch/arm/include/asm/arch-omap4/mux_omap4.h @@ -341,4 +341,5 @@ struct pad_conf_entry { #define CONTROL_SPARE_R 0x0618 #define CONTROL_SPARE_R_C0 0x061C +#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ 0x4A31E05A #endif /* _MUX_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h index a30bb33..9aad0e6 100644 --- a/arch/arm/include/asm/arch-omap4/omap4.h +++ b/arch/arm/include/asm/arch-omap4/omap4.h @@ -51,6 +51,20 @@ #define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000) #define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000) +/* LPDDR2 IO regs */ +#define LPDDR2_IO_REGS_BASE 0x4A100638 + +#define CONTROL_EFUSE_2 0x4A100704 + +/* CONTROL_ID_CODE */ +#define CONTROL_ID_CODE 0x4A002204 + +#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F +#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F +#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F +#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F +#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F + /* UART */ #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) #define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) @@ -70,12 +84,6 @@ /* GPMC */ #define OMAP44XX_GPMC_BASE 0x50000000 -/* DMM */ -#define OMAP44XX_DMM_BASE 0x4E000000 -#define DMM_LISA_MAP_BASE (OMAP44XX_DMM_BASE + 0x40) -#define DMM_LISA_MAP_SYS_SIZE_MASK (7 << 20) -#define DMM_LISA_MAP_SYS_SIZE_SHIFT 20 -#define DMM_LISA_MAP_SYS_ADDR_MASK (0xFF << 24) /* * Hardware Register Details */ @@ -119,13 +127,38 @@ struct s32ktimer { /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4030D000 /* Temporary SRAM stack used while low level init is done */ -#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END - -/* - * OMAP4 real hardware: - * TODO: Change this to the IDCODE in the hw regsiter - */ -#define CPU_OMAP4430_ES10 1 -#define CPU_OMAP4430_ES20 2 +#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END +#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START +/* SRAM scratch space entries */ +#define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR +#define OMAP4_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) +#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) +#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) +#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14) + +/* Silicon revisions */ +#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF +#define OMAP4430_ES1_0 0x44300100 +#define OMAP4430_ES2_0 0x44300200 +#define OMAP4430_ES2_1 0x44300210 +#define OMAP4430_ES2_2 0x44300220 +#define OMAP4430_ES2_3 0x44300230 +#define OMAP4460_ES1_0 0x44600100 + +/* ROM code defines */ +/* Boot device */ +#define BOOT_DEVICE_MASK 0xFF +#define BOOT_DEVICE_OFFSET 0x8 +#define DEV_DESC_PTR_OFFSET 0x4 +#define DEV_DATA_PTR_OFFSET 0x18 +#define BOOT_MODE_OFFSET 0x8 + +/* GPIO */ +#define OMAP44XX_GPIO1_BASE 0x4A310000 +#define OMAP44XX_GPIO2_BASE 0x48055000 +#define OMAP44XX_GPIO3_BASE 0x48057000 +#define OMAP44XX_GPIO4_BASE 0x48059000 +#define OMAP44XX_GPIO5_BASE 0x4805B000 +#define OMAP44XX_GPIO6_BASE 0x4805D000 #endif diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index 4813e9e..a81f8e5 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -22,21 +22,89 @@ #define _SYS_PROTO_H_ #include <asm/arch/omap4.h> +#include <asm/arch/clocks.h> #include <asm/io.h> +#include <asm/omap_common.h> +#include <asm/arch/mux_omap4.h> struct omap_sysinfo { char *board_string; }; +extern const struct omap_sysinfo sysinfo; + +extern struct omap4_prcm_regs *const prcm; void gpmc_init(void); void watchdog_init(void); u32 get_device_type(void); -void invalidate_dcache(u32); -void set_muxconf_regs(void); +void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); +void set_muxconf_regs_non_essential(void); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); +void set_pl310_ctrl_reg(u32 val); +void omap_rev_string(char *omap4_rev_string); +void setup_clocks_for_console(void); +void prcm_init(void); +void bypass_dpll(u32 *const base); +void freq_update_core(void); +u32 get_sys_clk_freq(void); +u32 omap4_ddr_clk(void); +void cancel_out(u32 *num, u32 *den, u32 den_limit); +void sdram_init(void); +u32 omap4_sdram_size(void); -extern const struct omap_sysinfo sysinfo; +static inline u32 running_from_sdram(void) +{ + u32 pc; + asm volatile ("mov %0, pc" : "=r" (pc)); + return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) && + (pc < OMAP44XX_DRAM_ADDR_SPACE_END)); +} + +static inline u8 uboot_loaded_by_spl(void) +{ + /* + * Configuration Header is not supported yet, so u-boot init running + * from SDRAM implies that it was loaded by SPL. When this situation + * changes one of these approaches could be taken: + * i. Pass a magic from SPL to U-Boot and U-Boot save it at a known + * location. + * ii. Check the OPP. CH can support only 50% OPP while SPL initializes + * the DPLLs at 100% OPP. + */ + return running_from_sdram(); +} +/* + * The basic hardware init of OMAP(s_init()) can happen in 4 + * different contexts: + * 1. SPL running from SRAM + * 2. U-Boot running from FLASH + * 3. Non-XIP U-Boot loaded to SDRAM by SPL + * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the + * Configuration Header feature + * + * This function finds this context. + * Defining as inline may help in compiling out unused functions in SPL + */ +static inline u32 omap4_hw_init_context(void) +{ +#ifdef CONFIG_SPL_BUILD + return OMAP_INIT_CONTEXT_SPL; +#else + if (uboot_loaded_by_spl()) + return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL; + else if (running_from_sdram()) + return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH; + else + return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR; +#endif +} + +static inline u32 omap_revision(void) +{ + extern u32 *const omap4_revision; + return *omap4_revision; +} #endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h b/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h index 3078aaf..7b83c5a 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h +++ b/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h @@ -25,8 +25,5 @@ #define _SYS_PROTO_H_ u32 get_device_type(void); -void invalidate_dcache(u32); -void l2_cache_disable(void); -void l2_cache_enable(void); #endif diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h index bd8ad2c..36e27b5 100644 --- a/arch/arm/include/asm/arch-tegra2/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h @@ -191,4 +191,9 @@ struct clk_rst_ctlr { #define CPCON (1 << 8) +#define SWR_SDMMC4_RST (1 << 15) +#define CLK_ENB_SDMMC4 (1 << 15) +#define SWR_SDMMC3_RST (1 << 5) +#define CLK_ENB_SDMMC3 (1 << 5) + #endif /* CLK_RST_H */ diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h b/arch/arm/include/asm/arch-tegra2/gpio.h index 0fb8f0d..41e66fe 100644 --- a/arch/arm/include/asm/arch-tegra2/gpio.h +++ b/arch/arm/include/asm/arch-tegra2/gpio.h @@ -23,11 +23,13 @@ #define _TEGRA2_GPIO_H_ /* - * The Tegra 2x GPIO controller has 222 GPIOs arranged in 8 banks of 4 ports, + * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports, * each with 8 GPIOs. */ -#define TEGRA_GPIO_PORTS 4 /* The number of ports per bank */ -#define TEGRA_GPIO_BANKS 8 /* The number of banks */ +#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ +#define TEGRA_GPIO_BANKS 7 /* number of banks */ +#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8) +#define GPIO_NAME_SIZE 20 /* gpio_request max label len */ /* GPIO Controller registers for a single bank */ struct gpio_ctlr_bank { @@ -45,15 +47,243 @@ struct gpio_ctlr { struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; }; -#define GPIO_BANK(x) ((x) >> 5) -#define GPIO_PORT(x) (((x) >> 3) & 0x3) -#define GPIO_BIT(x) ((x) & 0x7) +#define GPIO_BANK(x) ((x) >> 5) +#define GPIO_PORT(x) (((x) >> 3) & 0x3) +#define GPIO_FULLPORT(x) ((x) >> 3) +#define GPIO_BIT(x) ((x) & 0x7) + +enum gpio_pin { + GPIO_PA0 = 0, /* pin 0 */ + GPIO_PA1, + GPIO_PA2, + GPIO_PA3, + GPIO_PA4, + GPIO_PA5, + GPIO_PA6, + GPIO_PA7, + GPIO_PB0, /* pin 8 */ + GPIO_PB1, + GPIO_PB2, + GPIO_PB3, + GPIO_PB4, + GPIO_PB5, + GPIO_PB6, + GPIO_PB7, + GPIO_PC0, /* pin 16 */ + GPIO_PC1, + GPIO_PC2, + GPIO_PC3, + GPIO_PC4, + GPIO_PC5, + GPIO_PC6, + GPIO_PC7, + GPIO_PD0, /* pin 24 */ + GPIO_PD1, + GPIO_PD2, + GPIO_PD3, + GPIO_PD4, + GPIO_PD5, + GPIO_PD6, + GPIO_PD7, + GPIO_PE0, /* pin 32 */ + GPIO_PE1, + GPIO_PE2, + GPIO_PE3, + GPIO_PE4, + GPIO_PE5, + GPIO_PE6, + GPIO_PE7, + GPIO_PF0, /* pin 40 */ + GPIO_PF1, + GPIO_PF2, + GPIO_PF3, + GPIO_PF4, + GPIO_PF5, + GPIO_PF6, + GPIO_PF7, + GPIO_PG0, /* pin 48 */ + GPIO_PG1, + GPIO_PG2, + GPIO_PG3, + GPIO_PG4, + GPIO_PG5, + GPIO_PG6, + GPIO_PG7, + GPIO_PH0, /* pin 56 */ + GPIO_PH1, + GPIO_PH2, + GPIO_PH3, + GPIO_PH4, + GPIO_PH5, + GPIO_PH6, + GPIO_PH7, + GPIO_PI0, /* pin 64 */ + GPIO_PI1, + GPIO_PI2, + GPIO_PI3, + GPIO_PI4, + GPIO_PI5, + GPIO_PI6, + GPIO_PI7, + GPIO_PJ0, /* pin 72 */ + GPIO_PJ1, + GPIO_PJ2, + GPIO_PJ3, + GPIO_PJ4, + GPIO_PJ5, + GPIO_PJ6, + GPIO_PJ7, + GPIO_PK0, /* pin 80 */ + GPIO_PK1, + GPIO_PK2, + GPIO_PK3, + GPIO_PK4, + GPIO_PK5, + GPIO_PK6, + GPIO_PK7, + GPIO_PL0, /* pin 88 */ + GPIO_PL1, + GPIO_PL2, + GPIO_PL3, + GPIO_PL4, + GPIO_PL5, + GPIO_PL6, + GPIO_PL7, + GPIO_PM0, /* pin 96 */ + GPIO_PM1, + GPIO_PM2, + GPIO_PM3, + GPIO_PM4, + GPIO_PM5, + GPIO_PM6, + GPIO_PM7, + GPIO_PN0, /* pin 104 */ + GPIO_PN1, + GPIO_PN2, + GPIO_PN3, + GPIO_PN4, + GPIO_PN5, + GPIO_PN6, + GPIO_PN7, + GPIO_PO0, /* pin 112 */ + GPIO_PO1, + GPIO_PO2, + GPIO_PO3, + GPIO_PO4, + GPIO_PO5, + GPIO_PO6, + GPIO_PO7, + GPIO_PP0, /* pin 120 */ + GPIO_PP1, + GPIO_PP2, + GPIO_PP3, + GPIO_PP4, + GPIO_PP5, + GPIO_PP6, + GPIO_PP7, + GPIO_PQ0, /* pin 128 */ + GPIO_PQ1, + GPIO_PQ2, + GPIO_PQ3, + GPIO_PQ4, + GPIO_PQ5, + GPIO_PQ6, + GPIO_PQ7, + GPIO_PR0, /* pin 136 */ + GPIO_PR1, + GPIO_PR2, + GPIO_PR3, + GPIO_PR4, + GPIO_PR5, + GPIO_PR6, + GPIO_PR7, + GPIO_PS0, /* pin 144 */ + GPIO_PS1, + GPIO_PS2, + GPIO_PS3, + GPIO_PS4, + GPIO_PS5, + GPIO_PS6, + GPIO_PS7, + GPIO_PT0, /* pin 152 */ + GPIO_PT1, + GPIO_PT2, + GPIO_PT3, + GPIO_PT4, + GPIO_PT5, + GPIO_PT6, + GPIO_PT7, + GPIO_PU0, /* pin 160 */ + GPIO_PU1, + GPIO_PU2, + GPIO_PU3, + GPIO_PU4, + GPIO_PU5, + GPIO_PU6, + GPIO_PU7, + GPIO_PV0, /* pin 168 */ + GPIO_PV1, + GPIO_PV2, + GPIO_PV3, + GPIO_PV4, + GPIO_PV5, + GPIO_PV6, + GPIO_PV7, + GPIO_PW0, /* pin 176 */ + GPIO_PW1, + GPIO_PW2, + GPIO_PW3, + GPIO_PW4, + GPIO_PW5, + GPIO_PW6, + GPIO_PW7, + GPIO_PX0, /* pin 184 */ + GPIO_PX1, + GPIO_PX2, + GPIO_PX3, + GPIO_PX4, + GPIO_PX5, + GPIO_PX6, + GPIO_PX7, + GPIO_PY0, /* pin 192 */ + GPIO_PY1, + GPIO_PY2, + GPIO_PY3, + GPIO_PY4, + GPIO_PY5, + GPIO_PY6, + GPIO_PY7, + GPIO_PZ0, /* pin 200 */ + GPIO_PZ1, + GPIO_PZ2, + GPIO_PZ3, + GPIO_PZ4, + GPIO_PZ5, + GPIO_PZ6, + GPIO_PZ7, + GPIO_PAA0, /* pin 208 */ + GPIO_PAA1, + GPIO_PAA2, + GPIO_PAA3, + GPIO_PAA4, + GPIO_PAA5, + GPIO_PAA6, + GPIO_PAA7, + GPIO_PBB0, /* pin 216 */ + GPIO_PBB1, + GPIO_PBB2, + GPIO_PBB3, + GPIO_PBB4, + GPIO_PBB5, + GPIO_PBB6, + GPIO_PBB7, /* pin 223 */ +}; /* - * GPIO_PI3 = Port I = 8, bit = 3. - * Seaboard: used for UART/SPI selection - * Harmony: not used + * Tegra2-specific GPIO API */ -#define GPIO_PI3 ((8 << 3) | 3) +void gpio_info(void); + +#define gpio_status() gpio_info() #endif /* TEGRA2_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra2/pinmux.h b/arch/arm/include/asm/arch-tegra2/pinmux.h index 8b4bd8d..cce936d 100644 --- a/arch/arm/include/asm/arch-tegra2/pinmux.h +++ b/arch/arm/include/asm/arch-tegra2/pinmux.h @@ -51,5 +51,11 @@ struct pmux_tri_ctlr { #define Z_GMC (1 << 29) #define Z_IRRX (1 << 20) #define Z_IRTX (1 << 19) +#define Z_GMA (1 << 28) +#define Z_GME (1 << 0) +#define Z_ATB (1 << 1) +#define Z_SDB (1 << 15) +#define Z_SDC (1 << 1) +#define Z_SDD (1 << 2) #endif /* PINMUX_H */ diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h new file mode 100644 index 0000000..9adc563 --- /dev/null +++ b/arch/arm/include/asm/armv7.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef ARMV7_H +#define ARMV7_H +#include <linux/types.h> + +/* Cortex-A9 revisions */ +#define MIDR_CORTEX_A9_R0P1 0x410FC091 +#define MIDR_CORTEX_A9_R1P2 0x411FC092 +#define MIDR_CORTEX_A9_R1P3 0x411FC093 +#define MIDR_CORTEX_A9_R2P10 0x412FC09A + +/* CCSIDR */ +#define CCSIDR_LINE_SIZE_OFFSET 0 +#define CCSIDR_LINE_SIZE_MASK 0x7 +#define CCSIDR_ASSOCIATIVITY_OFFSET 3 +#define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3) +#define CCSIDR_NUM_SETS_OFFSET 13 +#define CCSIDR_NUM_SETS_MASK (0x7FFF << 13) + +/* + * Values for InD field in CSSELR + * Selects the type of cache + */ +#define ARMV7_CSSELR_IND_DATA_UNIFIED 0 +#define ARMV7_CSSELR_IND_INSTRUCTION 1 + +/* Values for Ctype fields in CLIDR */ +#define ARMV7_CLIDR_CTYPE_NO_CACHE 0 +#define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1 +#define ARMV7_CLIDR_CTYPE_DATA_ONLY 2 +#define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 +#define ARMV7_CLIDR_CTYPE_UNIFIED 4 + +/* + * CP15 Barrier instructions + * Please note that we have separate barrier instructions in ARMv7 + * However, we use the CP15 based instructtions because we use + * -march=armv5 in U-Boot + */ +#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) +#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) +#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) + +void v7_outer_cache_enable(void); +void v7_outer_cache_disable(void); +void v7_outer_cache_flush_all(void); +void v7_outer_cache_inval_all(void); +void v7_outer_cache_flush_range(u32 start, u32 end); +void v7_outer_cache_inval_range(u32 start, u32 end); + +#endif diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index 270f163..879e20e 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -106,6 +106,11 @@ static inline int test_bit(int nr, const void * addr) return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7)); } +static inline int __ilog2(unsigned int x) +{ + return generic_fls(x) - 1; +} + /* * ffz = Find First Zero in word. Undefined if no zero exists, * so code should check against ~0UL first.. diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 2a84d27..4fc51fd 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -24,7 +24,7 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H /* - * The following data structure is placed in some memory wich is + * The following data structure is placed in some memory which is * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or * some locked parts of the data cache) to allow for a minimum set of * global variables during system initialization (until we have set @@ -41,9 +41,6 @@ typedef struct global_data { unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long fb_base; /* base address of frame buffer */ -#ifdef CONFIG_VFD - unsigned char vfd_type; /* display type */ -#endif #ifdef CONFIG_FSL_ESDHC unsigned long sdhc_clk; #endif @@ -64,13 +61,16 @@ typedef struct global_data { unsigned long long timer_reset_value; unsigned long lastinc; #endif +#ifdef CONFIG_IXP425 + unsigned long timestamp; +#endif unsigned long relocaddr; /* Start address of U-Boot in RAM */ phys_size_t ram_size; /* RAM size */ unsigned long mon_len; /* monitor len */ unsigned long irq_sp; /* irq stack pointer */ unsigned long start_addr_sp; /* start_addr_stackpointer */ unsigned long reloc_off; -#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) unsigned long tlb_addr; #endif void **jt; /* jump table */ diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h new file mode 100644 index 0000000..eb071d1 --- /dev/null +++ b/arch/arm/include/asm/gpio.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2011, NVIDIA Corp. All rights reserved. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _GPIO_H_ +#define _GPIO_H_ + +#include <asm/arch/gpio.h> +/* + * Generic GPIO API + */ + +int gpio_request(int gp, const char *label); +void gpio_free(int gp); +void gpio_toggle_value(int gp); +int gpio_direction_input(int gp); +int gpio_direction_output(int gp, int value); +int gpio_get_value(int gp); +void gpio_set_value(int gp, int value); + +#endif /* _GPIO_H_ */ diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h new file mode 100644 index 0000000..d3cb857 --- /dev/null +++ b/arch/arm/include/asm/omap_common.h @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP_COMMON_H_ +#define _OMAP_COMMON_H_ + +/* Max value for DPLL multiplier M */ +#define OMAP_DPLL_MAX_N 127 + +/* HW Init Context */ +#define OMAP_INIT_CONTEXT_SPL 0 +#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1 +#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2 +#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3 + +void preloader_console_init(void); + +/* Boot device */ +#define BOOT_DEVICE_NONE 0 +#define BOOT_DEVICE_XIP 1 +#define BOOT_DEVICE_XIPWAIT 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_ONE_NAND 4 +#define BOOT_DEVICE_MMC1 5 +#define BOOT_DEVICE_MMC2 6 + +/* Boot type */ +#define MMCSD_MODE_UNDEFINED 0 +#define MMCSD_MODE_RAW 1 +#define MMCSD_MODE_FAT 2 + +u32 omap_boot_device(void); +u32 omap_boot_mode(void); + +#endif /* _OMAP_COMMON_H_ */ diff --git a/arch/arm/include/asm/arch-omap3/gpio.h b/arch/arm/include/asm/omap_gpio.h index 30f633c..3089e1c 100644 --- a/arch/arm/include/asm/arch-omap3/gpio.h +++ b/arch/arm/include/asm/omap_gpio.h @@ -38,36 +38,15 @@ #ifndef _GPIO_H #define _GPIO_H -#define OMAP24XX_GPIO_REVISION 0x0000 -#define OMAP24XX_GPIO_SYSCONFIG 0x0010 -#define OMAP24XX_GPIO_SYSSTATUS 0x0014 -#define OMAP24XX_GPIO_IRQSTATUS1 0x0018 -#define OMAP24XX_GPIO_IRQSTATUS2 0x0028 -#define OMAP24XX_GPIO_IRQENABLE2 0x002c -#define OMAP24XX_GPIO_IRQENABLE1 0x001c -#define OMAP24XX_GPIO_WAKE_EN 0x0020 -#define OMAP24XX_GPIO_CTRL 0x0030 -#define OMAP24XX_GPIO_OE 0x0034 -#define OMAP24XX_GPIO_DATAIN 0x0038 -#define OMAP24XX_GPIO_DATAOUT 0x003c -#define OMAP24XX_GPIO_LEVELDETECT0 0x0040 -#define OMAP24XX_GPIO_LEVELDETECT1 0x0044 -#define OMAP24XX_GPIO_RISINGDETECT 0x0048 -#define OMAP24XX_GPIO_FALLINGDETECT 0x004c -#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 -#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 -#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 -#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 -#define OMAP24XX_GPIO_CLEARWKUENA 0x0080 -#define OMAP24XX_GPIO_SETWKUENA 0x0084 -#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 -#define OMAP24XX_GPIO_SETDATAOUT 0x0094 +#include <asm/arch/cpu.h> struct gpio_bank { void *base; int method; }; +extern const struct gpio_bank *const omap_gpio_bank; + #define METHOD_GPIO_24XX 4 /* This is the interface */ diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h new file mode 100644 index 0000000..fb506e6 --- /dev/null +++ b/arch/arm/include/asm/pl310.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _PL310_H_ +#define _PL310_H_ + +#include <linux/types.h> + +/* Register bit fields */ +#define PL310_AUX_CTRL_ASSOCIATIVITY_MASK (1 << 16) + +struct pl310_regs { + u32 pl310_cache_id; + u32 pl310_cache_type; + u32 pad1[62]; + u32 pl310_ctrl; + u32 pl310_aux_ctrl; + u32 pl310_tag_latency_ctrl; + u32 pl310_data_latency_ctrl; + u32 pad2[60]; + u32 pl310_event_cnt_ctrl; + u32 pl310_event_cnt1_cfg; + u32 pl310_event_cnt0_cfg; + u32 pl310_event_cnt1_val; + u32 pl310_event_cnt0_val; + u32 pl310_intr_mask; + u32 pl310_masked_intr_stat; + u32 pl310_raw_intr_stat; + u32 pl310_intr_clear; + u32 pad3[323]; + u32 pl310_cache_sync; + u32 pad4[15]; + u32 pl310_inv_line_pa; + u32 pad5[2]; + u32 pl310_inv_way; + u32 pad6[12]; + u32 pl310_clean_line_pa; + u32 pad7[1]; + u32 pl310_clean_line_idx; + u32 pl310_clean_way; + u32 pad8[12]; + u32 pl310_clean_inv_line_pa; + u32 pad9[1]; + u32 pl310_clean_inv_line_idx; + u32 pl310_clean_inv_way; +}; + +void pl310_inval_all(void); +void pl310_clean_inval_all(void); +void pl310_inval_range(u32 start, u32 end); +void pl310_clean_inval_range(u32 start, u32 end); + +#endif diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h index 3904027..d3308f7 100644 --- a/arch/arm/include/asm/u-boot-arm.h +++ b/arch/arm/include/asm/u-boot-arm.h @@ -57,21 +57,10 @@ void dram_init_banksize (void); void setup_serial_tag (struct tag **params); void setup_revision_tag (struct tag **params); -/* ------------------------------------------------------------ */ -/* Here is a list of some prototypes which are incompatible to */ -/* the U-Boot implementation */ -/* To be fixed! */ -/* ------------------------------------------------------------ */ -/* common/cmd_nvedit.c */ -int setenv (char *, char *); - /* cpu/.../interrupt.c */ int arch_interrupt_init (void); void reset_timer_masked (void); ulong get_timer_masked (void); void udelay_masked (unsigned long usec); -/* cpu/.../timer.c */ -int timer_init (void); - #endif /* _U_BOOT_ARM_H_ */ diff --git a/arch/arm/include/asm/utils.h b/arch/arm/include/asm/utils.h new file mode 100644 index 0000000..828b86c --- /dev/null +++ b/arch/arm/include/asm/utils.h @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _UTILS_H_ +#define _UTILS_H_ + +static inline s32 log_2_n_round_up(u32 n) +{ + s32 log2n = -1; + u32 temp = n; + + while (temp) { + log2n++; + temp >>= 1; + } + + if (n & (n - 1)) + return log2n + 1; /* not power of 2 - round up */ + else + return log2n; /* power of 2 */ +} + +static inline s32 log_2_n_round_down(u32 n) +{ + s32 log2n = -1; + u32 temp = n; + + while (temp) { + log2n++; + temp >>= 1; + } + + return log2n; +} + +#endif diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 03b1b5e..300c8fa 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(ARCH).o LIBGCC = $(obj)libgcc.o +ifndef CONFIG_SPL_BUILD GLSOBJS += _ashldi3.o GLSOBJS += _ashrdi3.o GLSOBJS += _divsi3.o @@ -39,13 +40,13 @@ GLCOBJS += div0.o COBJS-y += board.o COBJS-y += bootm.o COBJS-y += cache.o -ifndef CONFIG_SYS_NO_CP15_CACHE COBJS-y += cache-cp15.o -endif +COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o COBJS-y += interrupts.o COBJS-y += reset.o SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o +endif SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \ $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 1a784a1..14a56f6 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -42,7 +42,6 @@ #include <command.h> #include <malloc.h> #include <stdio_dev.h> -#include <timestamp.h> #include <version.h> #include <net.h> #include <serial.h> @@ -70,13 +69,6 @@ extern int AT91F_DataflashInit(void); extern void dataflash_print_info(void); #endif -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -const char version_string[] = - U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"CONFIG_IDENT_STRING; - #ifdef CONFIG_DRIVER_RTL8019 extern void rtl8019_get_enetaddr (uchar * addr); #endif @@ -92,26 +84,28 @@ extern void rtl8019_get_enetaddr (uchar * addr); ************************************************************************ * May be supplied by boards if desired */ -void inline __coloured_LED_init (void) {} -void coloured_LED_init (void) __attribute__((weak, alias("__coloured_LED_init"))); -void inline __red_LED_on (void) {} -void red_LED_on (void) __attribute__((weak, alias("__red_LED_on"))); -void inline __red_LED_off(void) {} +inline void __coloured_LED_init(void) {} +void coloured_LED_init(void) + __attribute__((weak, alias("__coloured_LED_init"))); +inline void __red_LED_on(void) {} +void red_LED_on(void) __attribute__((weak, alias("__red_LED_on"))); +inline void __red_LED_off(void) {} void red_LED_off(void) __attribute__((weak, alias("__red_LED_off"))); -void inline __green_LED_on(void) {} +inline void __green_LED_on(void) {} void green_LED_on(void) __attribute__((weak, alias("__green_LED_on"))); -void inline __green_LED_off(void) {} +inline void __green_LED_off(void) {} void green_LED_off(void) __attribute__((weak, alias("__green_LED_off"))); -void inline __yellow_LED_on(void) {} +inline void __yellow_LED_on(void) {} void yellow_LED_on(void) __attribute__((weak, alias("__yellow_LED_on"))); -void inline __yellow_LED_off(void) {} +inline void __yellow_LED_off(void) {} void yellow_LED_off(void) __attribute__((weak, alias("__yellow_LED_off"))); -void inline __blue_LED_on(void) {} +inline void __blue_LED_on(void) {} void blue_LED_on(void) __attribute__((weak, alias("__blue_LED_on"))); -void inline __blue_LED_off(void) {} +inline void __blue_LED_off(void) {} void blue_LED_off(void) __attribute__((weak, alias("__blue_LED_off"))); -/************************************************************************ +/* + ************************************************************************ * Init Utilities * ************************************************************************ * Some of this code should be moved into the core functions, @@ -122,30 +116,30 @@ void blue_LED_off(void) __attribute__((weak, alias("__blue_LED_off"))); #if defined(CONFIG_ARM_DCC) && !defined(CONFIG_BAUDRATE) #define CONFIG_BAUDRATE 115200 #endif -static int init_baudrate (void) +static int init_baudrate(void) { char tmp[64]; /* long enough for environment variables */ - int i = getenv_f("baudrate", tmp, sizeof (tmp)); + int i = getenv_f("baudrate", tmp, sizeof(tmp)); gd->baudrate = (i > 0) - ? (int) simple_strtoul (tmp, NULL, 10) + ? (int) simple_strtoul(tmp, NULL, 10) : CONFIG_BAUDRATE; return (0); } -static int display_banner (void) +static int display_banner(void) { - printf ("\n\n%s\n\n", version_string); - debug ("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", + printf("\n\n%s\n\n", version_string); + debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", _TEXT_BASE, - _bss_start_ofs+_TEXT_BASE, _bss_end_ofs+_TEXT_BASE); + _bss_start_ofs + _TEXT_BASE, _bss_end_ofs + _TEXT_BASE); #ifdef CONFIG_MODEM_SUPPORT - debug ("Modem Support enabled\n"); + debug("Modem Support enabled\n"); #endif #ifdef CONFIG_USE_IRQ - debug ("IRQ Stack: %08lx\n", IRQ_STACK_START); - debug ("FIQ Stack: %08lx\n", FIQ_STACK_START); + debug("IRQ Stack: %08lx\n", IRQ_STACK_START); + debug("FIQ Stack: %08lx\n", FIQ_STACK_START); #endif return (0); @@ -158,23 +152,23 @@ static int display_banner (void) * gives a simple yet clear indication which part of the * initialization if failing. */ -static int display_dram_config (void) +static int display_dram_config(void) { int i; #ifdef DEBUG - puts ("RAM Configuration:\n"); + puts("RAM Configuration:\n"); - for(i=0; i<CONFIG_NR_DRAM_BANKS; i++) { - printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); - print_size (gd->bd->bi_dram[i].size, "\n"); + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); + print_size(gd->bd->bi_dram[i].size, "\n"); } #else ulong size = 0; - for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) { + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) size += gd->bd->bi_dram[i].size; - } + puts("DRAM: "); print_size(size, "\n"); #endif @@ -183,11 +177,11 @@ static int display_dram_config (void) } #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) -static int init_func_i2c (void) +static int init_func_i2c(void) { - puts ("I2C: "); - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - puts ("ready\n"); + puts("I2C: "); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + puts("ready\n"); return (0); } #endif @@ -226,7 +220,7 @@ static int arm_pci_init(void) */ typedef int (init_fnc_t) (void); -int print_cpuinfo (void); +int print_cpuinfo(void); void __dram_init_banksize(void) { @@ -262,13 +256,10 @@ init_fnc_t *init_sequence[] = { init_func_i2c, #endif dram_init, /* configure available RAM banks */ -#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI) - arm_pci_init, -#endif NULL, }; -void board_init_f (ulong bootflag) +void board_init_f(ulong bootflag) { bd_t *bd; init_fnc_t **init_fnc_ptr; @@ -280,21 +271,25 @@ void board_init_f (ulong bootflag) /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("": : :"memory"); - memset ((void*)gd, 0, sizeof (gd_t)); + memset((void *)gd, 0, sizeof(gd_t)); gd->mon_len = _bss_end_ofs; +#ifdef CONFIG_MACH_TYPE + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ +#endif + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { if ((*init_fnc_ptr)() != 0) { hang (); } } - debug ("monitor len: %08lX\n", gd->mon_len); + debug("monitor len: %08lX\n", gd->mon_len); /* * Ram is setup, size stored in gd !! */ - debug ("ramsize: %08lX\n", gd->ram_size); + debug("ramsize: %08lX\n", gd->ram_size); #if defined(CONFIG_SYS_MEM_TOP_HIDE) /* * Subtract specified amount of memory to hide so that it won't @@ -315,7 +310,8 @@ void board_init_f (ulong bootflag) #ifndef CONFIG_ALT_LB_ADDR /* reserve kernel log buffer */ addr -= (LOGBUFF_RESERVE); - debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr); + debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, + addr); #endif #endif @@ -323,13 +319,14 @@ void board_init_f (ulong bootflag) /* * reserve protected RAM */ - i = getenv_r ("pram", (char *)tmp, sizeof (tmp)); - reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM; + i = getenv_r("pram", (char *)tmp, sizeof(tmp)); + reg = (i > 0) ? simple_strtoul((const char *)tmp, NULL, 10) : + CONFIG_PRAM; addr -= (reg << 10); /* size is in kB */ - debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr); + debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr); #endif /* CONFIG_PRAM */ -#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) /* reserve TLB table */ addr -= (4096 * 4); @@ -337,30 +334,19 @@ void board_init_f (ulong bootflag) addr &= ~(0x10000 - 1); gd->tlb_addr = addr; - debug ("TLB table at: %08lx\n", addr); + debug("TLB table at: %08lx\n", addr); #endif /* round down to next 4 kB limit */ addr &= ~(4096 - 1); - debug ("Top of RAM usable for U-Boot at: %08lx\n", addr); - -#ifdef CONFIG_VFD -# ifndef PAGE_SIZE -# define PAGE_SIZE 4096 -# endif - /* - * reserve memory for VFD display (always full pages) - */ - addr -= vfd_setmem (addr); - gd->fb_base = addr; -#endif /* CONFIG_VFD */ + debug("Top of RAM usable for U-Boot at: %08lx\n", addr); #ifdef CONFIG_LCD #ifdef CONFIG_FB_ADDR gd->fb_base = CONFIG_FB_ADDR; #else /* reserve memory for LCD display (always full pages) */ - addr = lcd_setmem (addr); + addr = lcd_setmem(addr); gd->fb_base = addr; #endif /* CONFIG_FB_ADDR */ #endif /* CONFIG_LCD */ @@ -372,14 +358,14 @@ void board_init_f (ulong bootflag) addr -= gd->mon_len; addr &= ~(4096 - 1); - debug ("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr); + debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr); -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD /* * reserve memory for malloc() arena */ addr_sp = addr - TOTAL_MALLOC_LEN; - debug ("Reserving %dk for malloc() at: %08lx\n", + debug("Reserving %dk for malloc() at: %08lx\n", TOTAL_MALLOC_LEN >> 10, addr_sp); /* * (permanently) allocate a Board Info struct @@ -388,18 +374,18 @@ void board_init_f (ulong bootflag) addr_sp -= sizeof (bd_t); bd = (bd_t *) addr_sp; gd->bd = bd; - debug ("Reserving %zu Bytes for Board Info at: %08lx\n", + debug("Reserving %zu Bytes for Board Info at: %08lx\n", sizeof (bd_t), addr_sp); addr_sp -= sizeof (gd_t); id = (gd_t *) addr_sp; - debug ("Reserving %zu Bytes for Global Data at: %08lx\n", + debug("Reserving %zu Bytes for Global Data at: %08lx\n", sizeof (gd_t), addr_sp); /* setup stackpointer for exeptions */ gd->irq_sp = addr_sp; #ifdef CONFIG_USE_IRQ addr_sp -= (CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ); - debug ("Reserving %zu Bytes for IRQ stack at: %08lx\n", + debug("Reserving %zu Bytes for IRQ stack at: %08lx\n", CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp); #endif /* leave 3 words for abort-stack */ @@ -412,11 +398,11 @@ void board_init_f (ulong bootflag) gd->irq_sp = addr_sp; #endif - debug ("New Stack Pointer is: %08lx\n", addr_sp); + debug("New Stack Pointer is: %08lx\n", addr_sp); #ifdef CONFIG_POST post_bootmode_init(); - post_run (NULL, POST_ROM | post_bootmode_get(0)); + post_run(NULL, POST_ROM | post_bootmode_get(0)); #endif gd->bd->bi_baudrate = gd->baudrate; @@ -427,10 +413,10 @@ void board_init_f (ulong bootflag) gd->relocaddr = addr; gd->start_addr_sp = addr_sp; gd->reloc_off = addr - _TEXT_BASE; - debug ("relocation Offset is: %08lx\n", gd->reloc_off); - memcpy (id, (void *)gd, sizeof (gd_t)); + debug("relocation Offset is: %08lx\n", gd->reloc_off); + memcpy(id, (void *)gd, sizeof(gd_t)); - relocate_code (addr_sp, id, addr); + relocate_code(addr_sp, id, addr); /* NOTREACHED - relocate_code() does not return */ } @@ -439,7 +425,8 @@ void board_init_f (ulong bootflag) static char *failed = "*** failed ***\n"; #endif -/************************************************************************ +/* + ************************************************************************ * * This is the next part if the initialization sequence: we are now * running from RAM and have a "normal" C environment, i. e. global @@ -449,7 +436,7 @@ static char *failed = "*** failed ***\n"; ************************************************************************ */ -void board_init_r (gd_t *id, ulong dest_addr) +void board_init_r(gd_t *id, ulong dest_addr) { char *s; bd_t *bd; @@ -464,20 +451,26 @@ void board_init_r (gd_t *id, ulong dest_addr) gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ monitor_flash_len = _end_ofs; - debug ("monitor flash len: %08lX\n", monitor_flash_len); + /* + * Enable D$: + * I$, if needed, must be already enabled in start.S + */ + dcache_enable(); + + debug("monitor flash len: %08lX\n", monitor_flash_len); board_init(); /* Setup chipselects */ #ifdef CONFIG_SERIAL_MULTI serial_initialize(); #endif - debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); + debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr); #ifdef CONFIG_LOGBUFFER - logbuff_init_ptrs (); + logbuff_init_ptrs(); #endif #ifdef CONFIG_POST - post_output_backlog (); + post_output_backlog(); #endif /* The Malloc area is immediately below the monitor copy in DRAM */ @@ -485,34 +478,35 @@ void board_init_r (gd_t *id, ulong dest_addr) mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN); #if !defined(CONFIG_SYS_NO_FLASH) - puts ("Flash: "); + puts("Flash: "); - if ((flash_size = flash_init ()) > 0) { + flash_size = flash_init(); + if (flash_size > 0) { # ifdef CONFIG_SYS_FLASH_CHECKSUM - print_size (flash_size, ""); + print_size(flash_size, ""); /* * Compute and print flash CRC if flashchecksum is set to 'y' * * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX */ - s = getenv ("flashchecksum"); + s = getenv("flashchecksum"); if (s && (*s == 'y')) { - printf (" CRC: %08X", - crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size) - ); + printf(" CRC: %08X", crc32(0, + (const unsigned char *) CONFIG_SYS_FLASH_BASE, + flash_size)); } - putc ('\n'); + putc('\n'); # else /* !CONFIG_SYS_FLASH_CHECKSUM */ - print_size (flash_size, "\n"); + print_size(flash_size, "\n"); # endif /* CONFIG_SYS_FLASH_CHECKSUM */ } else { - puts (failed); - hang (); + puts(failed); + hang(); } #endif #if defined(CONFIG_CMD_NAND) - puts ("NAND: "); + puts("NAND: "); nand_init(); /* go init the NAND */ #endif @@ -531,45 +525,44 @@ void board_init_r (gd_t *id, ulong dest_addr) #endif /* initialize environment */ - env_relocate (); + env_relocate(); -#ifdef CONFIG_VFD - /* must do this after the framebuffer is allocated */ - drv_vfd_init(); -#endif /* CONFIG_VFD */ +#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) + arm_pci_init(); +#endif /* IP Address */ - gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); + gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr"); - stdio_init (); /* get the devices list going. */ + stdio_init(); /* get the devices list going. */ - jumptable_init (); + jumptable_init(); #if defined(CONFIG_API) /* Initialize API */ - api_init (); + api_init(); #endif - console_init_r (); /* fully init console as a device */ + console_init_r(); /* fully init console as a device */ #if defined(CONFIG_ARCH_MISC_INIT) /* miscellaneous arch dependent initialisations */ - arch_misc_init (); + arch_misc_init(); #endif #if defined(CONFIG_MISC_INIT_R) /* miscellaneous platform dependent initialisations */ - misc_init_r (); + misc_init_r(); #endif /* set up exceptions */ - interrupt_init (); + interrupt_init(); /* enable exceptions */ - enable_interrupts (); + enable_interrupts(); /* Perform network card initialisation if necessary */ #if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96) /* XXX: this needs to be moved to board init */ - if (getenv ("ethaddr")) { + if (getenv("ethaddr")) { uchar enetaddr[6]; eth_getenv_enetaddr("ethaddr", enetaddr); smc_set_mac_addr(enetaddr); @@ -577,17 +570,17 @@ void board_init_r (gd_t *id, ulong dest_addr) #endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */ /* Initialize from environment */ - if ((s = getenv ("loadaddr")) != NULL) { - load_addr = simple_strtoul (s, NULL, 16); - } + s = getenv("loadaddr"); + if (s != NULL) + load_addr = simple_strtoul(s, NULL, 16); #if defined(CONFIG_CMD_NET) - if ((s = getenv ("bootfile")) != NULL) { - copy_filename (BootFile, s, sizeof (BootFile)); - } + s = getenv("bootfile"); + if (s != NULL) + copy_filename(BootFile, s, sizeof(BootFile)); #endif #ifdef BOARD_LATE_INIT - board_late_init (); + board_late_init(); #endif #ifdef CONFIG_BITBANGMII @@ -595,17 +588,17 @@ void board_init_r (gd_t *id, ulong dest_addr) #endif #if defined(CONFIG_CMD_NET) #if defined(CONFIG_NET_MULTI) - puts ("Net: "); + puts("Net: "); #endif eth_initialize(gd->bd); #if defined(CONFIG_RESET_PHY_R) - debug ("Reset Ethernet PHY\n"); + debug("Reset Ethernet PHY\n"); reset_phy(); #endif #endif #ifdef CONFIG_POST - post_run (NULL, POST_RAM | post_bootmode_get(0)); + post_run(NULL, POST_RAM | post_bootmode_get(0)); #endif #if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) @@ -619,35 +612,35 @@ void board_init_r (gd_t *id, ulong dest_addr) #ifdef CONFIG_PRAM char *s; - if ((s = getenv ("pram")) != NULL) { - pram = simple_strtoul (s, NULL, 10); - } else { + s = getenv("pram"); + if (s != NULL) + pram = simple_strtoul(s, NULL, 10); + else pram = CONFIG_PRAM; - } #else - pram=0; + pram = 0; #endif #ifdef CONFIG_LOGBUFFER #ifndef CONFIG_ALT_LB_ADDR /* Also take the logbuffer into account (pram is in kB) */ - pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024; + pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024; #endif #endif - sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram); - setenv ("mem", (char *)memsz); + sprintf((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram); + setenv("mem", (char *)memsz); } #endif /* main_loop() can return to retry autoboot, if so just run it again. */ for (;;) { - main_loop (); + main_loop(); } /* NOTREACHED - no way out of command loop except booting */ } -void hang (void) +void hang(void) { - puts ("### ERROR ### Please RESET the board ###\n"); + puts("### ERROR ### Please RESET the board ###\n"); for (;;); } diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index d9175f0..e6c3eae 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -24,7 +24,7 @@ #include <common.h> #include <asm/system.h> -#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) #define CACHE_SETUP 0x1a @@ -34,6 +34,12 @@ DECLARE_GLOBAL_DATA_PTR; +void __arm_init_before_mmu(void) +{ +} +void arm_init_before_mmu(void) + __attribute__((weak, alias("__arm_init_before_mmu"))); + static void cp_delay (void) { volatile int i; @@ -65,6 +71,7 @@ static inline void mmu_setup(void) int i; u32 reg; + arm_init_before_mmu(); /* Set up an identity-mapping for all 4GB, rw for everyone */ for (i = 0; i < 4096; i++) page_table[i] = i << 20 | (3 << 10) | 0x12; @@ -85,13 +92,18 @@ static inline void mmu_setup(void) set_cr(reg | CR_M); } +static int mmu_enabled(void) +{ + return get_cr() & CR_M; +} + /* cache_bit must be either CR_I or CR_C */ static void cache_enable(uint32_t cache_bit) { uint32_t reg; /* The data cache is not active unless the mmu is enabled too */ - if (cache_bit == CR_C) + if ((cache_bit == CR_C) && !mmu_enabled()) mmu_setup(); reg = get_cr(); /* get control reg. */ cp_delay(); @@ -110,7 +122,7 @@ static void cache_disable(uint32_t cache_bit) return; /* if disabling data cache, disable mmu too */ cache_bit |= CR_M; - flush_cache(0, ~0); + flush_dcache_all(); } reg = get_cr(); cp_delay(); @@ -118,7 +130,7 @@ static void cache_disable(uint32_t cache_bit) } #endif -#ifdef CONFIG_SYS_NO_ICACHE +#ifdef CONFIG_SYS_ICACHE_OFF void icache_enable (void) { return; @@ -150,7 +162,7 @@ int icache_status(void) } #endif -#ifdef CONFIG_SYS_NO_DCACHE +#ifdef CONFIG_SYS_DCACHE_OFF void dcache_enable (void) { return; diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c new file mode 100644 index 0000000..36c629c --- /dev/null +++ b/arch/arm/lib/cache-pl310.c @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <linux/types.h> +#include <asm/io.h> +#include <asm/armv7.h> +#include <asm/pl310.h> +#include <config.h> + +struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + +static void pl310_cache_sync(void) +{ + writel(0, &pl310->pl310_cache_sync); +} + +static void pl310_background_op_all_ways(u32 *op_reg) +{ + u32 assoc_16, associativity, way_mask; + + assoc_16 = readl(&pl310->pl310_aux_ctrl) & + PL310_AUX_CTRL_ASSOCIATIVITY_MASK; + if (assoc_16) + associativity = 16; + else + associativity = 8; + + way_mask = (1 << associativity) - 1; + /* Invalidate all ways */ + writel(way_mask, op_reg); + /* Wait for all ways to be invalidated */ + while (readl(op_reg) && way_mask) + ; + pl310_cache_sync(); +} + +void v7_outer_cache_inval_all(void) +{ + pl310_background_op_all_ways(&pl310->pl310_inv_way); +} + +void v7_outer_cache_flush_all(void) +{ + pl310_background_op_all_ways(&pl310->pl310_clean_inv_way); +} + +/* Flush(clean invalidate) memory from start to stop-1 */ +void v7_outer_cache_flush_range(u32 start, u32 stop) +{ + /* PL310 currently supports only 32 bytes cache line */ + u32 pa, line_size = 32; + + /* + * Align to the beginning of cache-line - this ensures that + * the first 5 bits are 0 as required by PL310 TRM + */ + start &= ~(line_size - 1); + + for (pa = start; pa < stop; pa = pa + line_size) + writel(pa, &pl310->pl310_clean_inv_line_pa); + + pl310_cache_sync(); +} + +/* invalidate memory from start to stop-1 */ +void v7_outer_cache_inval_range(u32 start, u32 stop) +{ + /* PL310 currently supports only 32 bytes cache line */ + u32 pa, line_size = 32; + + /* + * If start address is not aligned to cache-line flush the first + * line to prevent affecting somebody else's buffer + */ + if (start & (line_size - 1)) { + v7_outer_cache_flush_range(start, start + 1); + /* move to next cache line */ + start = (start + line_size - 1) & ~(line_size - 1); + } + + /* + * If stop address is not aligned to cache-line flush the last + * line to prevent affecting somebody else's buffer + */ + if (stop & (line_size - 1)) { + v7_outer_cache_flush_range(stop, stop + 1); + /* align to the beginning of this cache line */ + stop &= ~(line_size - 1); + } + + for (pa = start; pa < stop; pa = pa + line_size) + writel(pa, &pl310->pl310_inv_line_pa); + + pl310_cache_sync(); +} diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 30686fe..92b61a2 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -25,7 +25,7 @@ #include <common.h> -void flush_cache (unsigned long dummy1, unsigned long dummy2) +void __flush_cache(unsigned long start, unsigned long size) { #if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136) void arm1136_cache_flush(void); @@ -38,10 +38,18 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); #endif -#ifdef CONFIG_OMAP34XX - void v7_flush_cache_all(void); - - v7_flush_cache_all(); -#endif return; } +void flush_cache(unsigned long start, unsigned long size) + __attribute__((weak, alias("__flush_cache"))); + +/* + * Default implementation: + * do a range flush for the entire range + */ +void __flush_dcache_all(void) +{ + flush_cache(0, ~0); +} +void flush_dcache_all(void) + __attribute__((weak, alias("__flush_dcache_all"))); diff --git a/arch/avr32/cpu/interrupts.c b/arch/avr32/cpu/interrupts.c index c6ea435..6681e13 100644 --- a/arch/avr32/cpu/interrupts.c +++ b/arch/avr32/cpu/interrupts.c @@ -62,13 +62,6 @@ unsigned long long get_ticks(void) return ((unsigned long long)hi_now << 32) | lo; } -void reset_timer(void) -{ - sysreg_write(COUNT, 0); - cpu_sync_pipeline(); /* process any pending interrupts */ - timer_overflow = 0; -} - unsigned long get_timer(unsigned long base) { u64 now = get_ticks(); @@ -77,22 +70,6 @@ unsigned long get_timer(unsigned long base) return (unsigned long)(now >> 32) - base; } -void set_timer(unsigned long t) -{ - unsigned long long ticks = t; - unsigned long lo, hi, hi_new; - - ticks = (ticks * get_tbclk()) / CONFIG_SYS_HZ; - hi = ticks >> 32; - lo = ticks & 0xffffffffUL; - - do { - timer_overflow = hi; - sysreg_write(COUNT, lo); - hi_new = timer_overflow; - } while (hi_new != hi); -} - /* * For short delays only. It will overflow after a few seconds. */ diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c index 5edef8f..65473a1 100644 --- a/arch/avr32/lib/board.c +++ b/arch/avr32/lib/board.c @@ -23,7 +23,6 @@ #include <command.h> #include <malloc.h> #include <stdio_dev.h> -#include <timestamp.h> #include <version.h> #include <net.h> @@ -31,7 +30,6 @@ #include <miiphy.h> #endif -#include <asm/initcalls.h> #include <asm/sections.h> #include <asm/arch/mmu.h> @@ -41,9 +39,6 @@ DECLARE_GLOBAL_DATA_PTR; -const char version_string[] = - U_BOOT_VERSION " ("U_BOOT_DATE" - "U_BOOT_TIME") " CONFIG_IDENT_STRING; - unsigned long monitor_flash_len; /* Weak aliases for optional board functions */ diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk index 71fd53f..f9d46de 100644 --- a/arch/blackfin/config.mk +++ b/arch/blackfin/config.mk @@ -44,7 +44,7 @@ PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU) ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) -ALL += $(obj)u-boot.ldr +ALL-y += $(obj)u-boot.ldr endif ifeq ($(CONFIG_ENV_IS_EMBEDDED_IN_LDR),y) CREATE_LDR_ENV = $(obj)tools/envcrc --binary > $(obj)env-ldr.o diff --git a/arch/blackfin/cpu/.gitignore b/arch/blackfin/cpu/.gitignore index 0ec9d56..ba986d8 100644 --- a/arch/blackfin/cpu/.gitignore +++ b/arch/blackfin/cpu/.gitignore @@ -1 +1,4 @@ bootrom-asm-offsets.[chs] + +init.lds +init.elf diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile index df10f1b..5deaa9e 100644 --- a/arch/blackfin/cpu/Makefile +++ b/arch/blackfin/cpu/Makefile @@ -13,7 +13,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).o -EXTRA := +EXTRA := init.elf CEXTRA := initcode.o SEXTRA := start.o SOBJS := interrupt.o cache.o @@ -61,6 +61,11 @@ ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) fi endif +$(obj)init.lds: init.lds.S + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P $^ -o $@ +$(obj)init.elf: $(obj)init.lds $(obj)init.o $(obj)initcode.o + $(LD) $(LDFLAGS) -T $^ -o $@ + ######################################################################### # defines $(obj).depend target diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c index 18dbdf7..6a0bcca 100644 --- a/arch/blackfin/cpu/cpu.c +++ b/arch/blackfin/cpu/cpu.c @@ -19,6 +19,7 @@ #include "cpu.h" #include "serial.h" +#include "initcode.h" ulong bfin_poweron_retx; @@ -44,13 +45,16 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[]; memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len); } -#if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) - /* The BF537 bootrom will reset the EBIU_AMGCTL register on us - * after it has finished loading the LDR. So configure it again. + + /* + * Make sure our async settings are committed. Some bootroms + * (like the BF537) will reset some registers on us after it + * has finished loading the LDR. Or if we're booting over + * JTAG, the initcode never got a chance to run. Or if we + * aren't booting from parallel flash, the initcode skipped + * this step completely. */ - else - bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL); -#endif + program_async_controller(NULL); /* Save RETX so we can pass it while booting Linux */ bfin_poweron_retx = bootflag; diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c index cb96721..5674d42 100644 --- a/arch/blackfin/cpu/gpio.c +++ b/arch/blackfin/cpu/gpio.c @@ -665,6 +665,7 @@ int bfin_gpio_request(unsigned gpio, const char *label) return 0; } +#ifdef CONFIG_BFIN_GPIO_TRACK void bfin_gpio_free(unsigned gpio) { if (check_gpio(gpio) < 0) @@ -679,6 +680,7 @@ void bfin_gpio_free(unsigned gpio) set_label(gpio, "free"); } +#endif #ifdef BFIN_SPECIAL_GPIO_BANKS DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES)); diff --git a/arch/blackfin/cpu/init.S b/arch/blackfin/cpu/init.S new file mode 100644 index 0000000..f48c113 --- /dev/null +++ b/arch/blackfin/cpu/init.S @@ -0,0 +1,9 @@ +#include <asm/blackfin.h> +ENTRY(_start) + sp.l = LO(L1_SRAM_SCRATCH_END - 20); + sp.h = HI(L1_SRAM_SCRATCH_END - 20); + call _initcode; +1: + emuexcpt; + jump 1b; +END(_start) diff --git a/arch/blackfin/cpu/init.lds.S b/arch/blackfin/cpu/init.lds.S new file mode 100644 index 0000000..602e7c8 --- /dev/null +++ b/arch/blackfin/cpu/init.lds.S @@ -0,0 +1,25 @@ +/* + * linker script for simple init.elf + * + * Copyright (c) 2005-2011 Analog Device Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <config.h> +#include <asm/blackfin.h> +#undef ALIGN +#undef ENTRY + +OUTPUT_ARCH(bfin) + +MEMORY +{ + l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE +} + +ENTRY(_start) +SECTIONS +{ + .text.l1 : { *(.text .text.*) } >l1_code +} diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index 750add0..fb3a101 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -4,7 +4,7 @@ * cannot make any function calls as it may be executed all by itself by * the Blackfin's bootrom in LDR format. * - * Copyright (c) 2004-2008 Analog Devices Inc. + * Copyright (c) 2004-2011 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -19,11 +19,15 @@ #include <asm/mach-common/bits/pll.h> #include <asm/mach-common/bits/uart.h> +#define BUG() while (1) { asm volatile("emuexcpt;"); } + #include "serial.h" __attribute__((always_inline)) static inline void serial_init(void) { + uint32_t uart_base = UART_DLL; + #ifdef __ADSPBF54x__ # ifdef BFIN_BOOT_UART_USE_RTS # define BFIN_UART_USE_RTS 1 @@ -65,13 +69,13 @@ static inline void serial_init(void) if (BFIN_DEBUG_EARLY_SERIAL) { int ucen = bfin_read16(&pUART->gctl) & UCEN; - serial_early_init(); + serial_early_init(uart_base); /* If the UART is off, that means we need to program * the baud rate ourselves initially. */ if (ucen != UCEN) - serial_early_set_baud(CONFIG_BAUDRATE); + serial_early_set_baud(uart_base, CONFIG_BAUDRATE); } } @@ -79,6 +83,8 @@ __attribute__((always_inline)) static inline void serial_deinit(void) { #ifdef __ADSPBF54x__ + uint32_t uart_base = UART_DLL; + if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { /* clear forced RTS rather than relying on auto RTS */ bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL); @@ -89,6 +95,8 @@ static inline void serial_deinit(void) __attribute__((always_inline)) static inline void serial_putc(char c) { + uint32_t uart_base = UART_DLL; + if (!BFIN_DEBUG_EARLY_SERIAL) return; @@ -101,6 +109,8 @@ static inline void serial_putc(char c) continue; } +#include "initcode.h" + __attribute__((always_inline)) static inline void program_nmi_handler(void) { @@ -166,21 +176,6 @@ program_nmi_handler(void) # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF) #endif -#ifndef CONFIG_EBIU_RSTCTL_VAL -# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */ -#endif -#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0) -# error invalid EBIU_RSTCTL value: must not set reserved bits -#endif - -#ifndef CONFIG_EBIU_MBSCTL_VAL -# define CONFIG_EBIU_MBSCTL_VAL 0 -#endif - -#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0) -# error invalid EBIU_DDRQUE value: must not set reserved bits -#endif - /* Make sure our voltage value is sane so we don't blow up! */ #ifndef CONFIG_VR_CTL_VAL # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV) @@ -519,7 +514,7 @@ update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB) unsigned int quotient; for (quotient = 0; dividend > 0; ++quotient) dividend -= divisor; - serial_early_put_div(quotient - ANOMALY_05000230); + serial_early_put_div(UART_DLL, quotient - ANOMALY_05000230); serial_putc('c'); } @@ -636,34 +631,6 @@ check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs) serial_putc('e'); } -__attribute__((always_inline)) static inline void -program_async_controller(ADI_BOOT_DATA *bs) -{ - serial_putc('a'); - - /* Program the async banks controller. */ - bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL); - bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL); - bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL); - - serial_putc('b'); - - /* Not all parts have these additional MMRs. */ -#ifdef EBIU_MBSCTL - bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL); -#endif -#ifdef EBIU_MODE -# ifdef CONFIG_EBIU_MODE_VAL - bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL); -# endif -# ifdef CONFIG_EBIU_FCTL_VAL - bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL); -# endif -#endif - - serial_putc('c'); -} - BOOTROM_CALLED_FUNC_ATTR void initcode(ADI_BOOT_DATA *bs) { diff --git a/arch/blackfin/cpu/initcode.h b/arch/blackfin/cpu/initcode.h new file mode 100644 index 0000000..e0aad6d --- /dev/null +++ b/arch/blackfin/cpu/initcode.h @@ -0,0 +1,71 @@ +/* + * Code for early processor initialization + * + * Copyright (c) 2004-2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_INITCODE_H__ +#define __BFIN_INITCODE_H__ + +#include <asm/mach-common/bits/bootrom.h> + +#ifndef BFIN_IN_INITCODE +# define serial_putc(c) +#endif + +#ifndef CONFIG_EBIU_RSTCTL_VAL +# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */ +#endif +#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0) +# error invalid EBIU_RSTCTL value: must not set reserved bits +#endif + +#ifndef CONFIG_EBIU_MBSCTL_VAL +# define CONFIG_EBIU_MBSCTL_VAL 0 +#endif + +#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0) +# error invalid EBIU_DDRQUE value: must not set reserved bits +#endif + +__attribute__((always_inline)) static inline void +program_async_controller(ADI_BOOT_DATA *bs) +{ +#ifdef BFIN_IN_INITCODE + /* + * We really only need to setup the async banks early if we're + * booting out of it. Otherwise, do it later on in cpu_init. + */ + if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && + CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_PARA) + return; +#endif + + serial_putc('a'); + + /* Program the async banks controller. */ + bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL); + bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL); + bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL); + + serial_putc('b'); + + /* Not all parts have these additional MMRs. */ +#ifdef EBIU_MBSCTL + bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL); +#endif +#ifdef EBIU_MODE +# ifdef CONFIG_EBIU_MODE_VAL + bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL); +# endif +# ifdef CONFIG_EBIU_FCTL_VAL + bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL); +# endif +#endif + + serial_putc('c'); +} + +#endif diff --git a/arch/blackfin/cpu/interrupts.c b/arch/blackfin/cpu/interrupts.c index 54a67b4..9189816 100644 --- a/arch/blackfin/cpu/interrupts.c +++ b/arch/blackfin/cpu/interrupts.c @@ -152,8 +152,3 @@ ulong get_timer(ulong base) return (milisec - base); } - -void reset_timer(void) -{ - timer_init(); -} diff --git a/arch/blackfin/cpu/jtag-console.c b/arch/blackfin/cpu/jtag-console.c index e0f2975..a77358a 100644 --- a/arch/blackfin/cpu/jtag-console.c +++ b/arch/blackfin/cpu/jtag-console.c @@ -48,11 +48,11 @@ static inline uint32_t bfin_read_emudat(void) static bool jtag_write_emudat(uint32_t emudat) { static bool overflowed = false; - ulong timeout = get_timer(0) + CONFIG_JTAG_CONSOLE_TIMEOUT; + ulong timeout = get_timer(0); while (bfin_read_DBGSTAT() & 0x1) { if (overflowed) return overflowed; - if (timeout < get_timer(0)) + if (get_timer(timeout) > CONFIG_JTAG_CONSOLE_TIMEOUT) overflowed = true; } overflowed = false; diff --git a/arch/blackfin/cpu/reset.c b/arch/blackfin/cpu/reset.c index e23dcc7..ff39035 100644 --- a/arch/blackfin/cpu/reset.c +++ b/arch/blackfin/cpu/reset.c @@ -51,7 +51,9 @@ static void bfin_reset(void) /* The BF526 ROM will crash during reset */ #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) - bfin_read_SWRST(); + /* Seems to be fixed with newer parts though ... */ + if (__SILICON_REVISION__ < 1 && bfin_revid() < 1) + bfin_read_SWRST(); #endif /* Wait for the SWRST write to complete. Cannot rely on SSYNC diff --git a/arch/blackfin/cpu/serial.c b/arch/blackfin/cpu/serial.c index 650202e..030160f 100644 --- a/arch/blackfin/cpu/serial.c +++ b/arch/blackfin/cpu/serial.c @@ -39,6 +39,8 @@ #include <common.h> #include <watchdog.h> +#include <serial.h> +#include <linux/compiler.h> #include <asm/blackfin.h> #include <asm/mach-common/bits/uart.h> @@ -49,9 +51,9 @@ DECLARE_GLOBAL_DATA_PTR; #include "serial.h" #ifdef CONFIG_DEBUG_SERIAL -uint16_t cached_lsr[256]; -uint16_t cached_rbr[256]; -size_t cache_count; +static uint16_t cached_lsr[256]; +static uint16_t cached_rbr[256]; +static size_t cache_count; /* The LSR is read-to-clear on some parts, so we have to make sure status * bits aren't inadvertently lost when doing various tests. This also @@ -59,68 +61,34 @@ size_t cache_count; * tally of all the status bits. */ static uint16_t uart_lsr_save; -static uint16_t uart_lsr_read(void) +static uint16_t uart_lsr_read(uint32_t uart_base) { - uint16_t lsr = bfin_read16(&pUART->lsr); + uint16_t lsr = bfin_read(&pUART->lsr); uart_lsr_save |= (lsr & (OE|PE|FE|BI)); return lsr | uart_lsr_save; } /* Just do the clear for everyone since it can't hurt. */ -static void uart_lsr_clear(void) +static void uart_lsr_clear(uint32_t uart_base) { uart_lsr_save = 0; - bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1); + bfin_write(&pUART->lsr, bfin_read(&pUART->lsr) | -1); } #else /* When debugging is disabled, we only care about the DR bit, so if other * bits get set/cleared, we don't really care since we don't read them * anyways (and thus anomaly 05000099 is irrelevant). */ -static uint16_t uart_lsr_read(void) +static inline uint16_t uart_lsr_read(uint32_t uart_base) { - return bfin_read16(&pUART->lsr); + return bfin_read(&pUART->lsr); } -static void uart_lsr_clear(void) +static void uart_lsr_clear(uint32_t uart_base) { - bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1); + bfin_write(&pUART->lsr, bfin_read(&pUART->lsr) | -1); } #endif -/* Symbol for our assembly to call. */ -void serial_set_baud(uint32_t baud) -{ - serial_early_set_baud(baud); -} - -/* Symbol for common u-boot code to call. - * Setup the baudrate (brg: baudrate generator). - */ -void serial_setbrg(void) -{ - serial_set_baud(gd->baudrate); -} - -/* Symbol for our assembly to call. */ -void serial_initialize(void) -{ - serial_early_init(); -} - -/* Symbol for common u-boot code to call. */ -int serial_init(void) -{ - serial_initialize(); - serial_setbrg(); - uart_lsr_clear(); -#ifdef CONFIG_DEBUG_SERIAL - cache_count = 0; - memset(cached_lsr, 0x00, sizeof(cached_lsr)); - memset(cached_rbr, 0x00, sizeof(cached_rbr)); -#endif - return 0; -} - -void serial_putc(const char c) +static void uart_putc(uint32_t uart_base, const char c) { /* send a \r for compatibility */ if (c == '\n') @@ -129,36 +97,36 @@ void serial_putc(const char c) WATCHDOG_RESET(); /* wait for the hardware fifo to clear up */ - while (!(uart_lsr_read() & THRE)) + while (!(uart_lsr_read(uart_base) & THRE)) continue; /* queue the character for transmission */ - bfin_write16(&pUART->thr, c); + bfin_write(&pUART->thr, c); SSYNC(); WATCHDOG_RESET(); } -int serial_tstc(void) +static int uart_tstc(uint32_t uart_base) { WATCHDOG_RESET(); - return (uart_lsr_read() & DR) ? 1 : 0; + return (uart_lsr_read(uart_base) & DR) ? 1 : 0; } -int serial_getc(void) +static int uart_getc(uint32_t uart_base) { uint16_t uart_rbr_val; /* wait for data ! */ - while (!serial_tstc()) + while (!uart_tstc(uart_base)) continue; /* grab the new byte */ - uart_rbr_val = bfin_read16(&pUART->rbr); + uart_rbr_val = bfin_read(&pUART->rbr); #ifdef CONFIG_DEBUG_SERIAL /* grab & clear the LSR */ - uint16_t uart_lsr_val = uart_lsr_read(); + uint16_t uart_lsr_val = uart_lsr_read(uart_base); cached_lsr[cache_count] = uart_lsr_val; cached_rbr[cache_count] = uart_rbr_val; @@ -168,23 +136,171 @@ int serial_getc(void) uint16_t dll, dlh; printf("\n[SERIAL ERROR]\n"); ACCESS_LATCH(); - dll = bfin_read16(&pUART->dll); - dlh = bfin_read16(&pUART->dlh); + dll = bfin_read(&pUART->dll); + dlh = bfin_read(&pUART->dlh); ACCESS_PORT_IER(); printf("\tDLL=0x%x DLH=0x%x\n", dll, dlh); do { --cache_count; - printf("\t%3i: RBR=0x%02x LSR=0x%02x\n", cache_count, + printf("\t%3zu: RBR=0x%02x LSR=0x%02x\n", cache_count, cached_rbr[cache_count], cached_lsr[cache_count]); } while (cache_count > 0); return -1; } #endif - uart_lsr_clear(); + uart_lsr_clear(uart_base); return uart_rbr_val; } +#ifdef CONFIG_SYS_BFIN_UART + +static void uart_puts(uint32_t uart_base, const char *s) +{ + while (*s) + uart_putc(uart_base, *s++); +} + +#define DECL_BFIN_UART(n) \ +static int uart##n##_init(void) \ +{ \ + const unsigned short pins[] = { _P_UART(n, RX), _P_UART(n, TX), 0, }; \ + peripheral_request_list(pins, "bfin-uart"); \ + uart_init(MMR_UART(n)); \ + serial_early_set_baud(MMR_UART(n), gd->baudrate); \ + uart_lsr_clear(MMR_UART(n)); \ + return 0; \ +} \ +\ +static int uart##n##_uninit(void) \ +{ \ + return serial_early_uninit(MMR_UART(n)); \ +} \ +\ +static void uart##n##_setbrg(void) \ +{ \ + serial_early_set_baud(MMR_UART(n), gd->baudrate); \ +} \ +\ +static int uart##n##_getc(void) \ +{ \ + return uart_getc(MMR_UART(n)); \ +} \ +\ +static int uart##n##_tstc(void) \ +{ \ + return uart_tstc(MMR_UART(n)); \ +} \ +\ +static void uart##n##_putc(const char c) \ +{ \ + uart_putc(MMR_UART(n), c); \ +} \ +\ +static void uart##n##_puts(const char *s) \ +{ \ + uart_puts(MMR_UART(n), s); \ +} \ +\ +struct serial_device bfin_serial##n##_device = { \ + .name = "bfin_uart"#n, \ + .init = uart##n##_init, \ + .uninit = uart##n##_uninit, \ + .setbrg = uart##n##_setbrg, \ + .getc = uart##n##_getc, \ + .tstc = uart##n##_tstc, \ + .putc = uart##n##_putc, \ + .puts = uart##n##_puts, \ +}; + +#ifdef UART0_DLL +DECL_BFIN_UART(0) +#endif +#ifdef UART1_DLL +DECL_BFIN_UART(1) +#endif +#ifdef UART2_DLL +DECL_BFIN_UART(2) +#endif +#ifdef UART3_DLL +DECL_BFIN_UART(3) +#endif + +__weak struct serial_device *default_serial_console(void) +{ +#if CONFIG_UART_CONSOLE == 0 + return &bfin_serial0_device; +#elif CONFIG_UART_CONSOLE == 1 + return &bfin_serial1_device; +#elif CONFIG_UART_CONSOLE == 2 + return &bfin_serial2_device; +#elif CONFIG_UART_CONSOLE == 3 + return &bfin_serial3_device; +#endif +} + +void serial_register_bfin_uart(void) +{ +#ifdef UART0_DLL + serial_register(&bfin_serial0_device); +#endif +#ifdef UART1_DLL + serial_register(&bfin_serial1_device); +#endif +#ifdef UART2_DLL + serial_register(&bfin_serial2_device); +#endif +#ifdef UART3_DLL + serial_register(&bfin_serial3_device); +#endif +} + +#else + +/* Symbol for our assembly to call. */ +void serial_set_baud(uint32_t baud) +{ + serial_early_set_baud(UART_DLL, baud); +} + +/* Symbol for common u-boot code to call. + * Setup the baudrate (brg: baudrate generator). + */ +void serial_setbrg(void) +{ + serial_set_baud(gd->baudrate); +} + +/* Symbol for our assembly to call. */ +void serial_initialize(void) +{ + serial_early_init(UART_DLL); +} + +/* Symbol for common u-boot code to call. */ +int serial_init(void) +{ + serial_initialize(); + serial_setbrg(); + uart_lsr_clear(UART_DLL); + return 0; +} + +int serial_tstc(void) +{ + return uart_tstc(UART_DLL); +} + +int serial_getc(void) +{ + return uart_getc(UART_DLL); +} + +void serial_putc(const char c) +{ + uart_putc(UART_DLL, c); +} + void serial_puts(const char *s) { while (*s) @@ -192,3 +308,5 @@ void serial_puts(const char *s) } #endif + +#endif diff --git a/arch/blackfin/cpu/serial.h b/arch/blackfin/cpu/serial.h index 7999a19..8a076dd 100644 --- a/arch/blackfin/cpu/serial.h +++ b/arch/blackfin/cpu/serial.h @@ -82,26 +82,28 @@ struct bfin_mmr_serial { #define __PASTE_UART(num, pfx, sfx) pfx##num##_##sfx #define _PASTE_UART(num, pfx, sfx) __PASTE_UART(num, pfx, sfx) -#define MMR_UART(mmr) _PASTE_UART(CONFIG_UART_CONSOLE, UART, DLL) -#define P_UART(pin) _PASTE_UART(CONFIG_UART_CONSOLE, P_UART, pin) +#define MMR_UART(n) _PASTE_UART(n, UART, DLL) +#define _P_UART(n, pin) _PASTE_UART(n, P_UART, pin) +#define P_UART(pin) _P_UART(CONFIG_UART_CONSOLE, pin) #ifndef UART_DLL -# define UART_DLL MMR_UART(DLL) +# define UART_DLL MMR_UART(CONFIG_UART_CONSOLE) #else +# define UART0_DLL UART_DLL # if CONFIG_UART_CONSOLE != 0 # error CONFIG_UART_CONSOLE must be 0 on parts with only one UART # endif #endif -#define pUART ((volatile struct bfin_mmr_serial *)UART_DLL) +#define pUART ((volatile struct bfin_mmr_serial *)uart_base) #if BFIN_UART_HW_VER == 2 # define ACCESS_LATCH() # define ACCESS_PORT_IER() #else # define ACCESS_LATCH() \ - bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) | DLAB) + bfin_write(&pUART->lcr, bfin_read(&pUART->lcr) | DLAB) # define ACCESS_PORT_IER() \ - bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) & ~DLAB) + bfin_write(&pUART->lcr, bfin_read(&pUART->lcr) & ~DLAB) #endif __attribute__((always_inline)) @@ -168,30 +170,47 @@ static inline void serial_do_portmux(void) } __attribute__((always_inline)) -static inline void serial_early_init(void) +static inline int uart_init(uint32_t uart_base) { - /* handle portmux crap on different Blackfins */ - serial_do_portmux(); - /* always enable UART -- avoids anomalies 05000309 and 05000350 */ - bfin_write16(&pUART->gctl, UCEN); + bfin_write(&pUART->gctl, UCEN); /* Set LCR to Word Lengh 8-bit word select */ - bfin_write16(&pUART->lcr, WLS_8); + bfin_write(&pUART->lcr, WLS_8); SSYNC(); + + return 0; } __attribute__((always_inline)) -static inline void serial_early_put_div(uint16_t divisor) +static inline int serial_early_init(uint32_t uart_base) +{ + /* handle portmux crap on different Blackfins */ + serial_do_portmux(); + + return uart_init(uart_base); +} + +__attribute__((always_inline)) +static inline int serial_early_uninit(uint32_t uart_base) +{ + /* disable the UART by clearing UCEN */ + bfin_write(&pUART->gctl, 0); + + return 0; +} + +__attribute__((always_inline)) +static inline void serial_early_put_div(uint32_t uart_base, uint16_t divisor) { /* Set DLAB in LCR to Access DLL and DLH */ ACCESS_LATCH(); SSYNC(); /* Program the divisor to get the baud rate we want */ - bfin_write16(&pUART->dll, LOB(divisor)); - bfin_write16(&pUART->dlh, HIB(divisor)); + bfin_write(&pUART->dll, LOB(divisor)); + bfin_write(&pUART->dlh, HIB(divisor)); SSYNC(); /* Clear DLAB in LCR to Access THR RBR IER */ @@ -202,12 +221,14 @@ static inline void serial_early_put_div(uint16_t divisor) __attribute__((always_inline)) static inline uint16_t serial_early_get_div(void) { + uint32_t uart_base = UART_DLL; + /* Set DLAB in LCR to Access DLL and DLH */ ACCESS_LATCH(); SSYNC(); - uint8_t dll = bfin_read16(&pUART->dll); - uint8_t dlh = bfin_read16(&pUART->dlh); + uint8_t dll = bfin_read(&pUART->dll); + uint8_t dlh = bfin_read(&pUART->dlh); uint16_t divisor = (dlh << 8) | dll; /* Clear DLAB in LCR to Access THR RBR IER */ @@ -223,13 +244,14 @@ static inline uint16_t serial_early_get_div(void) #endif __attribute__((always_inline)) -static inline void serial_early_set_baud(uint32_t baud) +static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) { /* Translate from baud into divisor in terms of SCLK. The * weird multiplication is to make sure we over sample just * a little rather than under sample the incoming signals. */ - serial_early_put_div((get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230); + serial_early_put_div(uart_base, + (get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230); } #ifndef BFIN_IN_INITCODE @@ -266,16 +288,16 @@ static inline void serial_early_puts(const char *s) */ #ifdef CONFIG_DEBUG_EARLY_SERIAL # define serial_early_puts(str) \ - call _get_pc; \ - jump 1f; \ + .section .rodata; \ + 7: \ .ascii "Early:"; \ .ascii __FILE__; \ .ascii ": "; \ .ascii str; \ .asciz "\n"; \ - .align 4; \ -1: \ - R0 += 2; \ + .previous; \ + R0.L = 7b; \ + R0.H = 7b; \ call _serial_puts; #else # define serial_early_puts(str) diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S index 15ecb1e..90b4d1a 100644 --- a/arch/blackfin/cpu/start.S +++ b/arch/blackfin/cpu/start.S @@ -33,7 +33,6 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mach-common/bits/core.h> -#include <asm/mach-common/bits/dma.h> #include <asm/mach-common/bits/pll.h> #include "serial.h" diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h index 48f793a..27034d3 100644 --- a/arch/blackfin/include/asm/blackfin_local.h +++ b/arch/blackfin/include/asm/blackfin_local.h @@ -93,65 +93,61 @@ extern void blackfin_dcache_flush_invalidate_range(const void *, const void *); # define NOP_PAD_ANOMALY_05000198 #endif -#define bfin_read8(addr) ({ \ - uint8_t __v; \ +#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \ + u32 __v; \ __asm__ __volatile__( \ NOP_PAD_ANOMALY_05000198 \ - "%0 = b[%1] (z);" \ + "%0 = " #asm_size "[%1]" #asm_ext ";" \ : "=d" (__v) \ : "a" (addr) \ ); \ __v; }) - -#define bfin_read16(addr) ({ \ - uint16_t __v; \ - __asm__ __volatile__( \ - NOP_PAD_ANOMALY_05000198 \ - "%0 = w[%1] (z);" \ - : "=d" (__v) \ - : "a" (addr) \ - ); \ - __v; }) - -#define bfin_read32(addr) ({ \ - uint32_t __v; \ +#define _bfin_writeX(addr, val, size, asm_size) \ __asm__ __volatile__( \ NOP_PAD_ANOMALY_05000198 \ - "%0 = [%1];" \ - : "=d" (__v) \ - : "a" (addr) \ - ); \ - __v; }) - -#define bfin_readPTR(addr) bfin_read32(addr) - -#define bfin_write8(addr, val) \ - __asm__ __volatile__( \ - NOP_PAD_ANOMALY_05000198 \ - "b[%0] = %1;" \ - : \ - : "a" (addr), "d" (val) \ - : "memory" \ - ) - -#define bfin_write16(addr, val) \ - __asm__ __volatile__( \ - NOP_PAD_ANOMALY_05000198 \ - "w[%0] = %1;" \ + #asm_size "[%0] = %1;" \ : \ - : "a" (addr), "d" (val) \ + : "a" (addr), "d" ((u##size)(val)) \ : "memory" \ ) -#define bfin_write32(addr, val) \ - __asm__ __volatile__( \ - NOP_PAD_ANOMALY_05000198 \ - "[%0] = %1;" \ - : \ - : "a" (addr), "d" (val) \ - : "memory" \ - ) +#define bfin_read8(addr) _bfin_readX(addr, 8, b, (z)) +#define bfin_read16(addr) _bfin_readX(addr, 16, w, (z)) +#define bfin_read32(addr) _bfin_readX(addr, 32, , ) +#define bfin_write8(addr, val) _bfin_writeX(addr, val, 8, b) +#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w) +#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, ) + +#define bfin_read(addr) \ +({ \ + sizeof(*(addr)) == 1 ? bfin_read8(addr) : \ + sizeof(*(addr)) == 2 ? bfin_read16(addr) : \ + sizeof(*(addr)) == 4 ? bfin_read32(addr) : \ + ({ BUG(); 0; }); \ +}) +#define bfin_write(addr, val) \ +do { \ + switch (sizeof(*(addr))) { \ + case 1: bfin_write8(addr, val); break; \ + case 2: bfin_write16(addr, val); break; \ + case 4: bfin_write32(addr, val); break; \ + default: BUG(); \ + } \ +} while (0) + +#define bfin_write_or(addr, bits) \ +do { \ + typeof(addr) __addr = (addr); \ + bfin_write(__addr, bfin_read(__addr) | (bits)); \ +} while (0) + +#define bfin_write_and(addr, bits) \ +do { \ + typeof(addr) __addr = (addr); \ + bfin_write(__addr, bfin_read(__addr) & (bits)); \ +} while (0) +#define bfin_readPTR(addr) bfin_read32(addr) #define bfin_writePTR(addr, val) bfin_write32(addr, val) /* SSYNC implementation for C file */ diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h index 89814cd..bc3c252 100644 --- a/arch/blackfin/include/asm/config.h +++ b/arch/blackfin/include/asm/config.h @@ -121,6 +121,9 @@ #ifndef CONFIG_SYS_MEMTEST_END # define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 8192 + 4) #endif +#ifndef CONFIG_SYS_POST_WORD_ADDR +# define CONFIG_SYS_POST_WORD_ADDR (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE - 4) +#endif /* Check to make sure everything fits in external RAM */ #if CONFIG_SYS_MAX_RAM_SIZE && \ diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h index 9c0e5d1..224688f 100644 --- a/arch/blackfin/include/asm/gpio.h +++ b/arch/blackfin/include/asm/gpio.h @@ -142,8 +142,10 @@ struct gpio_port_t { #ifdef CONFIG_BFIN_GPIO_TRACK void bfin_gpio_labels(void); +void bfin_gpio_free(unsigned gpio); #else #define bfin_gpio_labels() +#define bfin_gpio_free(gpio) #define bfin_gpio_request(gpio, label) bfin_gpio_request(gpio) #define bfin_special_gpio_request(gpio, label) bfin_special_gpio_request(gpio) #endif @@ -154,7 +156,6 @@ int bfin_special_gpio_request(unsigned gpio, const char *label); #endif int bfin_gpio_request(unsigned gpio, const char *label); -void bfin_gpio_free(unsigned gpio); int bfin_gpio_direction_input(unsigned gpio); int bfin_gpio_direction_output(unsigned gpio, int value); int bfin_gpio_get_value(unsigned gpio); diff --git a/arch/blackfin/include/asm/mach-bf506/anomaly.h b/arch/blackfin/include/asm/mach-bf506/anomaly.h index e767233..5b3227a 100644 --- a/arch/blackfin/include/asm/mach-bf506/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf506/anomaly.h @@ -5,12 +5,13 @@ * and can be replaced with that version at any time * DO NOT EDIT THIS FILE * - * Copyright 2004-2010 Analog Devices Inc. + * Copyright 2004-2011 Analog Devices Inc. * Licensed under the ADI BSD license. * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: + * - Revision A, 02/18/2011; ADSP-BF504/BF504F/BF506F Blackfin Processor Anomaly List */ #if __SILICON_REVISION__ < 0 @@ -36,8 +37,6 @@ #define ANOMALY_05000310 (1) /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ #define ANOMALY_05000366 (1) -/* Speculative Fetches Can Cause Undesired External FIFO Operations */ -#define ANOMALY_05000416 (1) /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ #define ANOMALY_05000426 (1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ @@ -52,12 +51,28 @@ #define ANOMALY_05000472 (1) /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) +/* SPORT0 Data Transmit Error in Multi-Channel Mode with Internal Clock */ +#define ANOMALY_05000476 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) +/* Disabling ACM During an Ongoing Transfer Can Lead to Undefined ACM Behavior */ +#define ANOMALY_05000478 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ #define ANOMALY_05000481 (1) -/* IFLUSH sucks at life */ +/* TWI Vbus Minimum Specification Can Be Violated under Certain Conditions */ +#define ANOMALY_05000486 (1) +/* SPI Master Boot Can Fail Under Certain Conditions */ +#define ANOMALY_05000490 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* Maximum Idd-deepsleep Specifications Can Be Exceeded under Certain Conditions */ +#define ANOMALY_05000495 (1) +/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */ +#define ANOMALY_05000498 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -109,6 +124,7 @@ #define ANOMALY_05000364 (0) #define ANOMALY_05000371 (0) #define ANOMALY_05000380 (0) +#define ANOMALY_05000383 (0) #define ANOMALY_05000386 (0) #define ANOMALY_05000389 (0) #define ANOMALY_05000400 (0) @@ -123,6 +139,7 @@ #define ANOMALY_05000467 (0) #define ANOMALY_05000474 (0) #define ANOMALY_05000475 (0) +#define ANOMALY_05000480 (0) #define ANOMALY_05000485 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf518/anomaly.h b/arch/blackfin/include/asm/mach-bf518/anomaly.h index 24918c5..56383f7 100644 --- a/arch/blackfin/include/asm/mach-bf518/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf518/anomaly.h @@ -5,16 +5,15 @@ * and can be replaced with that version at any time * DO NOT EDIT THIS FILE * - * Copyright 2004-2010 Analog Devices Inc. + * Copyright 2004-2011 Analog Devices Inc. * Licensed under the ADI BSD license. * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: - * - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List + * - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List */ -/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */ #if __SILICON_REVISION__ < 0 # error will not work on BF518 silicon version #endif @@ -77,19 +76,29 @@ /* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ -#define ANOMALY_05000462 (1) -/* PLL Latches Incorrect Settings During Reset */ -#define ANOMALY_05000469 (1) +#define ANOMALY_05000462 (__SILICON_REVISION__ < 2) /* Incorrect Default MSEL Value in PLL_CTL */ -#define ANOMALY_05000472 (1) +#define ANOMALY_05000472 (__SILICON_REVISION__ < 2) /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ #define ANOMALY_05000481 (1) -/* IFLUSH sucks at life */ +/* PLL Latches Incorrect Settings During Reset */ +#define ANOMALY_05000482 (__SILICON_REVISION__ < 2) +/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ +#define ANOMALY_05000485 (__SILICON_REVISION__ < 2) +/* SPI Master Boot Can Fail Under Certain Conditions */ +#define ANOMALY_05000490 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */ +#define ANOMALY_05000498 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -141,6 +150,7 @@ #define ANOMALY_05000364 (0) #define ANOMALY_05000371 (0) #define ANOMALY_05000380 (0) +#define ANOMALY_05000383 (0) #define ANOMALY_05000386 (0) #define ANOMALY_05000389 (0) #define ANOMALY_05000400 (0) @@ -155,6 +165,6 @@ #define ANOMALY_05000467 (0) #define ANOMALY_05000474 (0) #define ANOMALY_05000475 (0) -#define ANOMALY_05000485 (0) +#define ANOMALY_05000480 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf527/anomaly.h b/arch/blackfin/include/asm/mach-bf527/anomaly.h index 72a6369..6884706 100644 --- a/arch/blackfin/include/asm/mach-bf527/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf527/anomaly.h @@ -5,14 +5,14 @@ * and can be replaced with that version at any time * DO NOT EDIT THIS FILE * - * Copyright 2004-2010 Analog Devices Inc. + * Copyright 2004-2011 Analog Devices Inc. * Licensed under the ADI BSD license. * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: - * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List - * - Revision H, 04/29/2010; ADSP-BF527 Blackfin Processor Anomaly List + * - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List + * - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -57,7 +57,7 @@ /* Incorrect Access of OTP_STATUS During otp_write() Function */ #define ANOMALY_05000328 (_ANOMALY_BF527(< 2)) /* Host DMA Boot Modes Are Not Functional */ -#define ANOMALY_05000330 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000330 (_ANOMALY_BF527(< 2)) /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ #define ANOMALY_05000337 (_ANOMALY_BF527(< 2)) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ @@ -135,7 +135,7 @@ /* Incorrect Default Internal Voltage Regulator Setting */ #define ANOMALY_05000410 (_ANOMALY_BF527(< 2)) /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ -#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2)) +#define ANOMALY_05000411 (_ANOMALY_BF526(< 1)) /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ #define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2)) /* DEB2_URGENT Bit Not Functional */ @@ -181,11 +181,11 @@ /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) /* The WURESET Bit in the SYSCR Register is not Functional */ -#define ANOMALY_05000445 (1) -/* USB DMA Mode 1 Short Packet Data Corruption */ +#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0)) +/* USB DMA Short Packet Data Corruption */ #define ANOMALY_05000450 (1) /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ -#define ANOMALY_05000451 (1) +#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0)) /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ #define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0)) /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ @@ -198,19 +198,19 @@ #define ANOMALY_05000461 (1) /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ #define ANOMALY_05000462 (1) -/* USB Rx DMA hang */ +/* USB Rx DMA Hang */ #define ANOMALY_05000465 (1) /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ #define ANOMALY_05000466 (1) -/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ +/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */ #define ANOMALY_05000467 (1) /* PLL Latches Incorrect Settings During Reset */ #define ANOMALY_05000469 (1) /* Incorrect Default MSEL Value in PLL_CTL */ #define ANOMALY_05000472 (_ANOMALY_BF526(>= 0)) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Possible Lockup Condition whem Modifying PLL from External Memory */ +/* Possible Lockup Condition when Modifying PLL from External Memory */ #define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) @@ -219,11 +219,19 @@ /* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */ #define ANOMALY_05000483 (1) /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ -#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3)) +#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0)) /* The CODEC Zero-Cross Detect Feature is not Functional */ #define ANOMALY_05000487 (1) -/* IFLUSH sucks at life */ +/* SPI Master Boot Can Fail Under Certain Conditions */ +#define ANOMALY_05000490 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */ +#define ANOMALY_05000498 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -270,11 +278,13 @@ #define ANOMALY_05000323 (0) #define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) +#define ANOMALY_05000383 (0) #define ANOMALY_05000400 (0) #define ANOMALY_05000402 (0) #define ANOMALY_05000412 (0) #define ANOMALY_05000447 (0) #define ANOMALY_05000448 (0) #define ANOMALY_05000474 (0) +#define ANOMALY_05000480 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf533/anomaly.h b/arch/blackfin/include/asm/mach-bf533/anomaly.h index 30e0eba..03f2b40 100644 --- a/arch/blackfin/include/asm/mach-bf533/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf533/anomaly.h @@ -5,13 +5,13 @@ * and can be replaced with that version at any time * DO NOT EDIT THIS FILE * - * Copyright 2004-2010 Analog Devices Inc. + * Copyright 2004-2011 Analog Devices Inc. * Licensed under the ADI BSD license. * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: - * - Revision F, 05/25/2010; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List + * - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -152,7 +152,7 @@ #define ANOMALY_05000277 (__SILICON_REVISION__ < 6) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 6) -/* False Hardware Error Exception when ISR Context Is Not Restored */ +/* False Hardware Error when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 6) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 6) @@ -210,18 +210,25 @@ #define ANOMALY_05000462 (1) /* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */ #define ANOMALY_05000471 (1) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Possible Lockup Condition whem Modifying PLL from External Memory */ +/* Possible Lockup Condition when Modifying PLL from External Memory */ #define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ #define ANOMALY_05000481 (1) -/* IFLUSH sucks at life */ +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) -/* These anomalies have been "phased" out of analog.com anomaly sheets and are +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are * here to show running on older silicon just isn't feasible. */ @@ -355,6 +362,7 @@ #define ANOMALY_05000362 (1) #define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) +#define ANOMALY_05000383 (0) #define ANOMALY_05000386 (1) #define ANOMALY_05000389 (0) #define ANOMALY_05000412 (0) @@ -369,6 +377,7 @@ #define ANOMALY_05000465 (0) #define ANOMALY_05000467 (0) #define ANOMALY_05000474 (0) +#define ANOMALY_05000480 (0) #define ANOMALY_05000485 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf537/anomaly.h b/arch/blackfin/include/asm/mach-bf537/anomaly.h index d3a2966..543cd3f 100644 --- a/arch/blackfin/include/asm/mach-bf537/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf537/anomaly.h @@ -5,13 +5,13 @@ * and can be replaced with that version at any time * DO NOT EDIT THIS FILE * - * Copyright 2004-2010 Analog Devices Inc. + * Copyright 2004-2011 Analog Devices Inc. * Licensed under the ADI BSD license. * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: - * - Revision E, 05/25/2010; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List + * - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -44,18 +44,12 @@ #define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ -#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ #define ANOMALY_05000180 (1) -/* Instruction Cache Is Not Functional */ -#define ANOMALY_05000237 (__SILICON_REVISION__ < 2) /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ #define ANOMALY_05000244 (__SILICON_REVISION__ < 3) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) -/* Buffered CLKIN Output Is Disabled by Default */ -#define ANOMALY_05000247 (1) /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ < 3) /* EMAC TX DMA Error After an Early Frame Abort */ @@ -98,7 +92,7 @@ #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) /* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */ #define ANOMALY_05000280 (1) -/* False Hardware Error Exception when ISR Context Is Not Restored */ +/* False Hardware Error when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 3) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 3) @@ -162,9 +156,9 @@ #define ANOMALY_05000461 (1) /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ #define ANOMALY_05000462 (1) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Possible Lockup Condition whem Modifying PLL from External Memory */ +/* Possible Lockup Condition when Modifying PLL from External Memory */ #define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) @@ -172,8 +166,26 @@ #define ANOMALY_05000480 (__SILICON_REVISION__ < 3) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ #define ANOMALY_05000481 (1) -/* IFLUSH sucks at life */ +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) + +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are + * here to show running on older silicon just isn't feasible. + */ + +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ +#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) +/* Instruction Cache Is Not Functional */ +#define ANOMALY_05000237 (__SILICON_REVISION__ < 2) +/* Buffered CLKIN Output Is Disabled by Default */ +#define ANOMALY_05000247 (__SILICON_REVISION__ < 2) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -208,6 +220,7 @@ #define ANOMALY_05000363 (0) #define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) +#define ANOMALY_05000383 (0) #define ANOMALY_05000386 (1) #define ANOMALY_05000389 (0) #define ANOMALY_05000400 (0) diff --git a/arch/blackfin/include/asm/mach-bf538/anomaly.h b/arch/blackfin/include/asm/mach-bf538/anomaly.h index 4bc1f4a..b6ca997 100644 --- a/arch/blackfin/include/asm/mach-bf538/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf538/anomaly.h @@ -5,14 +5,14 @@ * and can be replaced with that version at any time * DO NOT EDIT THIS FILE * - * Copyright 2004-2010 Analog Devices Inc. + * Copyright 2004-2011 Analog Devices Inc. * Licensed under the ADI BSD license. * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: - * - Revision I, 05/25/2010; ADSP-BF538/BF538F Blackfin Processor Anomaly List - * - Revision N, 05/25/2010; ADSP-BF539/BF539F Blackfin Processor Anomaly List + * - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List + * - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -56,25 +56,21 @@ #define ANOMALY_05000229 (1) /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ #define ANOMALY_05000233 (1) -/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ -#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Maximum External Clock Speed for Timers */ #define ANOMALY_05000253 (1) -/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ -#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ #define ANOMALY_05000270 (__SILICON_REVISION__ < 4) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ -#define ANOMALY_05000272 (1) +#define ANOMALY_05000272 (ANOMALY_BF538) /* Writes to Synchronous SDRAM Memory May Be Lost */ #define ANOMALY_05000273 (__SILICON_REVISION__ < 4) /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ #define ANOMALY_05000277 (__SILICON_REVISION__ < 4) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 4) -/* False Hardware Error Exception when ISR Context Is Not Restored */ +/* False Hardware Error when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 4) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 4) @@ -102,8 +98,10 @@ #define ANOMALY_05000313 (__SILICON_REVISION__ < 4) /* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 4) +/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */ +#define ANOMALY_05000317 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000318 */ /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ -#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4) +#define ANOMALY_05000318 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000317 */ /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ #define ANOMALY_05000355 (__SILICON_REVISION__ < 5) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ @@ -134,16 +132,32 @@ #define ANOMALY_05000461 (1) /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ #define ANOMALY_05000462 (1) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Possible Lockup Condition whem Modifying PLL from External Memory */ +/* Possible Lockup Condition when Modifying PLL from External Memory */ #define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ #define ANOMALY_05000481 (1) -/* IFLUSH sucks at life */ +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) + +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are + * here to show running on older silicon just isn't feasible. + */ + +/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ +#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) +/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ +#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -179,6 +193,7 @@ #define ANOMALY_05000363 (0) #define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) +#define ANOMALY_05000383 (0) #define ANOMALY_05000386 (1) #define ANOMALY_05000389 (0) #define ANOMALY_05000400 (0) @@ -194,6 +209,7 @@ #define ANOMALY_05000465 (0) #define ANOMALY_05000467 (0) #define ANOMALY_05000474 (0) +#define ANOMALY_05000480 (0) #define ANOMALY_05000485 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf548/anomaly.h b/arch/blackfin/include/asm/mach-bf548/anomaly.h index b9f4ecc..021fb19 100644 --- a/arch/blackfin/include/asm/mach-bf548/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf548/anomaly.h @@ -5,13 +5,13 @@ * and can be replaced with that version at any time * DO NOT EDIT THIS FILE * - * Copyright 2004-2010 Analog Devices Inc. + * Copyright 2004-2011 Analog Devices Inc. * Licensed under the ADI BSD license. * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: - * - Revision J, 06/03/2010; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List + * - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -31,111 +31,37 @@ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) /* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */ -#define ANOMALY_05000220 (1) +#define ANOMALY_05000220 (__SILICON_REVISION__ < 4) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) -/* False Hardware Error Exception when ISR Context Is Not Restored */ -#define ANOMALY_05000281 (__SILICON_REVISION__ < 1) -/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ -#define ANOMALY_05000304 (__SILICON_REVISION__ < 1) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (__SILICON_REVISION__ < 1) -/* TWI Slave Boot Mode Is Not Functional */ -#define ANOMALY_05000324 (__SILICON_REVISION__ < 1) /* FIFO Boot Mode Not Functional */ #define ANOMALY_05000325 (__SILICON_REVISION__ < 2) -/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ -#define ANOMALY_05000327 (__SILICON_REVISION__ < 1) -/* Incorrect Access of OTP_STATUS During otp_write() Function */ -#define ANOMALY_05000328 (__SILICON_REVISION__ < 1) -/* Synchronous Burst Flash Boot Mode Is Not Functional */ -#define ANOMALY_05000329 (__SILICON_REVISION__ < 1) -/* Host DMA Boot Modes Are Not Functional */ -#define ANOMALY_05000330 (__SILICON_REVISION__ < 1) -/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ -#define ANOMALY_05000334 (__SILICON_REVISION__ < 1) -/* Inadequate Rotary Debounce Logic Duration */ -#define ANOMALY_05000335 (__SILICON_REVISION__ < 1) -/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ -#define ANOMALY_05000336 (__SILICON_REVISION__ < 1) -/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ -#define ANOMALY_05000337 (__SILICON_REVISION__ < 1) -/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ -#define ANOMALY_05000338 (__SILICON_REVISION__ < 1) -/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ -#define ANOMALY_05000340 (__SILICON_REVISION__ < 1) -/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ -#define ANOMALY_05000344 (__SILICON_REVISION__ < 1) -/* USB Calibration Value Is Not Initialized */ -#define ANOMALY_05000346 (__SILICON_REVISION__ < 1) -/* USB Calibration Value to use */ -#define ANOMALY_05000346_value 0x5411 -/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ -#define ANOMALY_05000347 (__SILICON_REVISION__ < 1) -/* Data Lost when Core Reads SDH Data FIFO */ -#define ANOMALY_05000349 (__SILICON_REVISION__ < 1) -/* PLL Status Register Is Inaccurate */ -#define ANOMALY_05000351 (__SILICON_REVISION__ < 1) /* bfrom_SysControl() Firmware Function Performs Improper System Reset */ -#define ANOMALY_05000353 (__SILICON_REVISION__ < 2) -/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ -#define ANOMALY_05000355 (__SILICON_REVISION__ < 1) -/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */ -#define ANOMALY_05000356 (__SILICON_REVISION__ < 1) +/* + * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing + * shows that the fix itself does not cover all cases. + */ +#define ANOMALY_05000353 (1) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ #define ANOMALY_05000357 (1) /* External Memory Read Access Hangs Core With PLL Bypass */ #define ANOMALY_05000360 (1) /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ #define ANOMALY_05000365 (1) -/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */ -#define ANOMALY_05000367 (__SILICON_REVISION__ < 1) /* Addressing Conflict between Boot ROM and Asynchronous Memory */ #define ANOMALY_05000369 (1) -/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */ -#define ANOMALY_05000370 (__SILICON_REVISION__ < 1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (__SILICON_REVISION__ < 2) -/* USB DP/DM Data Pins May Lose State When Entering Hibernate */ -#define ANOMALY_05000372 (__SILICON_REVISION__ < 1) /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ #define ANOMALY_05000378 (__SILICON_REVISION__ < 2) /* 16-Bit NAND FLASH Boot Mode Is Not Functional */ #define ANOMALY_05000379 (1) -/* 8-Bit NAND Flash Boot Mode Not Functional */ -#define ANOMALY_05000382 (__SILICON_REVISION__ < 1) -/* Boot from OTP Memory Not Functional */ -#define ANOMALY_05000385 (__SILICON_REVISION__ < 1) -/* bfrom_SysControl() Firmware Routine Not Functional */ -#define ANOMALY_05000386 (__SILICON_REVISION__ < 1) -/* Programmable Preboot Settings Not Functional */ -#define ANOMALY_05000387 (__SILICON_REVISION__ < 1) -/* CRC32 Checksum Support Not Functional */ -#define ANOMALY_05000388 (__SILICON_REVISION__ < 1) -/* Reset Vector Must Not Be in SDRAM Memory Space */ -#define ANOMALY_05000389 (__SILICON_REVISION__ < 1) -/* Changed Meaning of BCODE Field in SYSCR Register */ -#define ANOMALY_05000390 (__SILICON_REVISION__ < 1) -/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */ -#define ANOMALY_05000391 (__SILICON_REVISION__ < 1) -/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000392 (__SILICON_REVISION__ < 1) -/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000393 (__SILICON_REVISION__ < 1) -/* Log Buffer Not Functional */ -#define ANOMALY_05000394 (__SILICON_REVISION__ < 1) -/* Hook Routine Not Functional */ -#define ANOMALY_05000395 (__SILICON_REVISION__ < 1) -/* Header Indirect Bit Not Functional */ -#define ANOMALY_05000396 (__SILICON_REVISION__ < 1) -/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ -#define ANOMALY_05000397 (__SILICON_REVISION__ < 1) /* Lockbox SESR Disallows Certain User Interrupts */ #define ANOMALY_05000404 (__SILICON_REVISION__ < 2) /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ @@ -157,7 +83,7 @@ /* Speculative Fetches Can Cause Undesired External FIFO Operations */ #define ANOMALY_05000416 (1) /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ -#define ANOMALY_05000425 (1) +#define ANOMALY_05000425 (__SILICON_REVISION__ < 4) /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ #define ANOMALY_05000426 (1) /* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */ @@ -170,8 +96,6 @@ #define ANOMALY_05000431 (__SILICON_REVISION__ < 3) /* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ #define ANOMALY_05000434 (1) -/* OTP Write Accesses Not Supported */ -#define ANOMALY_05000442 (__SILICON_REVISION__ < 1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) /* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */ @@ -182,34 +106,32 @@ #define ANOMALY_05000448 (__SILICON_REVISION__ == 1) /* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */ #define ANOMALY_05000449 (__SILICON_REVISION__ == 1) -/* USB DMA Mode 1 Short Packet Data Corruption */ +/* USB DMA Short Packet Data Corruption */ #define ANOMALY_05000450 (1) -/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ -#define ANOMALY_05000452 (__SILICON_REVISION__ < 1) /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ #define ANOMALY_05000456 (1) /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ #define ANOMALY_05000457 (1) /* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ -#define ANOMALY_05000460 (1) +#define ANOMALY_05000460 (__SILICON_REVISION__ < 4) /* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ -#define ANOMALY_05000462 (1) +#define ANOMALY_05000462 (__SILICON_REVISION__ < 4) /* USB DMA RX Data Corruption */ -#define ANOMALY_05000463 (1) +#define ANOMALY_05000463 (__SILICON_REVISION__ < 4) /* USB TX DMA Hang */ -#define ANOMALY_05000464 (1) -/* USB Rx DMA hang */ +#define ANOMALY_05000464 (__SILICON_REVISION__ < 4) +/* USB Rx DMA Hang */ #define ANOMALY_05000465 (1) /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ -#define ANOMALY_05000466 (1) -/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ -#define ANOMALY_05000467 (1) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +#define ANOMALY_05000466 (__SILICON_REVISION__ < 4) +/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */ +#define ANOMALY_05000467 (__SILICON_REVISION__ < 4) +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */ -#define ANOMALY_05000474 (1) +/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */ +#define ANOMALY_05000474 (__SILICON_REVISION__ < 4) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ @@ -219,9 +141,111 @@ /* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */ #define ANOMALY_05000484 (__SILICON_REVISION__ < 3) /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ -#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2) -/* IFLUSH sucks at life */ +#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4) +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* SPI Master Boot Can Fail Under Certain Conditions */ +#define ANOMALY_05000490 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */ +#define ANOMALY_05000498 (1) +/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */ +#define ANOMALY_05000500 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) +/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */ +#define ANOMALY_05000502 (1) + +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are + * here to show running on older silicon just isn't feasible. + */ + +/* False Hardware Error when ISR Context Is Not Restored */ +#define ANOMALY_05000281 (__SILICON_REVISION__ < 1) +/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ +#define ANOMALY_05000304 (__SILICON_REVISION__ < 1) +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +#define ANOMALY_05000312 (__SILICON_REVISION__ < 1) +/* TWI Slave Boot Mode Is Not Functional */ +#define ANOMALY_05000324 (__SILICON_REVISION__ < 1) +/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ +#define ANOMALY_05000327 (__SILICON_REVISION__ < 1) +/* Incorrect Access of OTP_STATUS During otp_write() Function */ +#define ANOMALY_05000328 (__SILICON_REVISION__ < 1) +/* Synchronous Burst Flash Boot Mode Is Not Functional */ +#define ANOMALY_05000329 (__SILICON_REVISION__ < 1) +/* Host DMA Boot Modes Are Not Functional */ +#define ANOMALY_05000330 (__SILICON_REVISION__ < 1) +/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ +#define ANOMALY_05000334 (__SILICON_REVISION__ < 1) +/* Inadequate Rotary Debounce Logic Duration */ +#define ANOMALY_05000335 (__SILICON_REVISION__ < 1) +/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ +#define ANOMALY_05000336 (__SILICON_REVISION__ < 1) +/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ +#define ANOMALY_05000337 (__SILICON_REVISION__ < 1) +/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ +#define ANOMALY_05000338 (__SILICON_REVISION__ < 1) +/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ +#define ANOMALY_05000340 (__SILICON_REVISION__ < 1) +/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ +#define ANOMALY_05000344 (__SILICON_REVISION__ < 1) +/* USB Calibration Value Is Not Initialized */ +#define ANOMALY_05000346 (__SILICON_REVISION__ < 1) +/* USB Calibration Value to use */ +#define ANOMALY_05000346_value 0x5411 +/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ +#define ANOMALY_05000347 (__SILICON_REVISION__ < 1) +/* Data Lost when Core Reads SDH Data FIFO */ +#define ANOMALY_05000349 (__SILICON_REVISION__ < 1) +/* PLL Status Register Is Inaccurate */ +#define ANOMALY_05000351 (__SILICON_REVISION__ < 1) +/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ +#define ANOMALY_05000355 (__SILICON_REVISION__ < 1) +/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */ +#define ANOMALY_05000356 (__SILICON_REVISION__ < 1) +/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */ +#define ANOMALY_05000367 (__SILICON_REVISION__ < 1) +/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */ +#define ANOMALY_05000370 (__SILICON_REVISION__ < 1) +/* USB DP/DM Data Pins May Lose State When Entering Hibernate */ +#define ANOMALY_05000372 (__SILICON_REVISION__ < 1) +/* 8-Bit NAND Flash Boot Mode Not Functional */ +#define ANOMALY_05000382 (__SILICON_REVISION__ < 1) +/* Boot from OTP Memory Not Functional */ +#define ANOMALY_05000385 (__SILICON_REVISION__ < 1) +/* bfrom_SysControl() Firmware Routine Not Functional */ +#define ANOMALY_05000386 (__SILICON_REVISION__ < 1) +/* Programmable Preboot Settings Not Functional */ +#define ANOMALY_05000387 (__SILICON_REVISION__ < 1) +/* CRC32 Checksum Support Not Functional */ +#define ANOMALY_05000388 (__SILICON_REVISION__ < 1) +/* Reset Vector Must Not Be in SDRAM Memory Space */ +#define ANOMALY_05000389 (__SILICON_REVISION__ < 1) +/* Changed Meaning of BCODE Field in SYSCR Register */ +#define ANOMALY_05000390 (__SILICON_REVISION__ < 1) +/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */ +#define ANOMALY_05000391 (__SILICON_REVISION__ < 1) +/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ +#define ANOMALY_05000392 (__SILICON_REVISION__ < 1) +/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ +#define ANOMALY_05000393 (__SILICON_REVISION__ < 1) +/* Log Buffer Not Functional */ +#define ANOMALY_05000394 (__SILICON_REVISION__ < 1) +/* Hook Routine Not Functional */ +#define ANOMALY_05000395 (__SILICON_REVISION__ < 1) +/* Header Indirect Bit Not Functional */ +#define ANOMALY_05000396 (__SILICON_REVISION__ < 1) +/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ +#define ANOMALY_05000397 (__SILICON_REVISION__ < 1) +/* OTP Write Accesses Not Supported */ +#define ANOMALY_05000442 (__SILICON_REVISION__ < 1) +/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ +#define ANOMALY_05000452 (__SILICON_REVISION__ < 1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -274,5 +298,6 @@ #define ANOMALY_05000435 (0) #define ANOMALY_05000440 (0) #define ANOMALY_05000475 (0) +#define ANOMALY_05000480 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf561/anomaly.h b/arch/blackfin/include/asm/mach-bf561/anomaly.h index 9313c27..b27173c 100644 --- a/arch/blackfin/include/asm/mach-bf561/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf561/anomaly.h @@ -5,13 +5,13 @@ * and can be replaced with that version at any time * DO NOT EDIT THIS FILE * - * Copyright 2004-2010 Analog Devices Inc. + * Copyright 2004-2011 Analog Devices Inc. * Licensed under the ADI BSD license. * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: - * - Revision R, 05/25/2010; ADSP-BF561 Blackfin Processor Anomaly List + * - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -26,62 +26,16 @@ #define ANOMALY_05000074 (1) /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) -/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ -#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) /* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */ #define ANOMALY_05000120 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Erroneous Exception when Enabling Cache */ -#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) /* SIGNBITS Instruction Not Functional under Certain Conditions */ #define ANOMALY_05000127 (1) -/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ -#define ANOMALY_05000134 (__SILICON_REVISION__ < 3) -/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */ -#define ANOMALY_05000135 (__SILICON_REVISION__ < 3) -/* Stall in multi-unit DMA operations */ -#define ANOMALY_05000136 (__SILICON_REVISION__ < 3) -/* Allowing the SPORT RX FIFO to fill will cause an overflow */ -#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ -#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) -/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ -#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) -/* DMA and TESTSET conflict when both are accessing external memory */ -#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) -/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ -#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) -/* MDMA may lose the first few words of a descriptor chain */ -#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) -/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ -#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) /* IMDMA S1/D1 Channel May Stall */ #define ANOMALY_05000149 (1) -/* DMA engine may lose data due to incorrect handshaking */ -#define ANOMALY_05000150 (__SILICON_REVISION__ < 3) -/* DMA stalls when all three controllers read data from the same source */ -#define ANOMALY_05000151 (__SILICON_REVISION__ < 3) -/* Execution stall when executing in L2 and doing external accesses */ -#define ANOMALY_05000152 (__SILICON_REVISION__ < 3) -/* Frame Delay in SPORT Multichannel Mode */ -#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) -/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ -#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) /* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ #define ANOMALY_05000156 (__SILICON_REVISION__ < 4) -/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ -#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) -/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ -#define ANOMALY_05000159 (__SILICON_REVISION__ < 3) -/* A read from external memory may return a wrong value with data cache enabled */ -#define ANOMALY_05000160 (__SILICON_REVISION__ < 3) -/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */ -#define ANOMALY_05000161 (__SILICON_REVISION__ < 3) -/* DMEM_CONTROL<12> is not set on Reset */ -#define ANOMALY_05000162 (__SILICON_REVISION__ < 3) -/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ -#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ @@ -92,10 +46,6 @@ #define ANOMALY_05000169 (__SILICON_REVISION__ < 5) /* Boot-ROM Modifies SICA_IWRx Wakeup Registers */ #define ANOMALY_05000171 (__SILICON_REVISION__ < 5) -/* DSPID register values incorrect */ -#define ANOMALY_05000172 (__SILICON_REVISION__ < 3) -/* DMA vs Core accesses to external memory */ -#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) /* Cache Fill Buffer Data lost */ #define ANOMALY_05000174 (__SILICON_REVISION__ < 5) /* Overlapping Sequencer and Memory Stalls */ @@ -124,8 +74,6 @@ #define ANOMALY_05000189 (__SILICON_REVISION__ < 5) /* PPI Not Functional at Core Voltage < 1Volt */ #define ANOMALY_05000190 (1) -/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ -#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ #define ANOMALY_05000193 (__SILICON_REVISION__ < 5) /* Restarting SPORT in Specific Modes May Cause Data Corruption */ @@ -213,10 +161,10 @@ /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ #define ANOMALY_05000276 (__SILICON_REVISION__ < 5) /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ -#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) +#define ANOMALY_05000277 (__SILICON_REVISION__ < 5) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 5) -/* False Hardware Error Exception when ISR Context Is Not Restored */ +/* False Hardware Error when ISR Context Is Not Restored */ /* Temporarily walk around for bug 5423 till this issue is confirmed by * official anomaly document. It looks 05000281 still exists on bf561 * v0.5. @@ -270,8 +218,6 @@ #define ANOMALY_05000366 (1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (1) -/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ == 4) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ #define ANOMALY_05000403 (1) /* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ @@ -294,16 +240,82 @@ #define ANOMALY_05000462 (1) /* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */ #define ANOMALY_05000471 (1) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Possible Lockup Condition whem Modifying PLL from External Memory */ +/* Possible Lockup Condition when Modifying PLL from External Memory */ #define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ #define ANOMALY_05000481 (1) -/* IFLUSH sucks at life */ +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) + +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are + * here to show running on older silicon just isn't feasible. + */ + +/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ +#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) +/* Erroneous Exception when Enabling Cache */ +#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) +/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ +#define ANOMALY_05000134 (__SILICON_REVISION__ < 3) +/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */ +#define ANOMALY_05000135 (__SILICON_REVISION__ < 3) +/* Stall in multi-unit DMA operations */ +#define ANOMALY_05000136 (__SILICON_REVISION__ < 3) +/* Allowing the SPORT RX FIFO to fill will cause an overflow */ +#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) +/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ +#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) +/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ +#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) +/* DMA and TESTSET conflict when both are accessing external memory */ +#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) +/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ +#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) +/* MDMA may lose the first few words of a descriptor chain */ +#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) +/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ +#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) +/* DMA engine may lose data due to incorrect handshaking */ +#define ANOMALY_05000150 (__SILICON_REVISION__ < 3) +/* DMA stalls when all three controllers read data from the same source */ +#define ANOMALY_05000151 (__SILICON_REVISION__ < 3) +/* Execution stall when executing in L2 and doing external accesses */ +#define ANOMALY_05000152 (__SILICON_REVISION__ < 3) +/* Frame Delay in SPORT Multichannel Mode */ +#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) +/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ +#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ +#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) +/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ +#define ANOMALY_05000159 (__SILICON_REVISION__ < 3) +/* A read from external memory may return a wrong value with data cache enabled */ +#define ANOMALY_05000160 (__SILICON_REVISION__ < 3) +/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */ +#define ANOMALY_05000161 (__SILICON_REVISION__ < 3) +/* DMEM_CONTROL<12> is not set on Reset */ +#define ANOMALY_05000162 (__SILICON_REVISION__ < 3) +/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ +#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) +/* DSPID register values incorrect */ +#define ANOMALY_05000172 (__SILICON_REVISION__ < 3) +/* DMA vs Core accesses to external memory */ +#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) +/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ +#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) +/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ +#define ANOMALY_05000402 (__SILICON_REVISION__ == 4) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000119 (0) @@ -316,6 +328,7 @@ #define ANOMALY_05000353 (1) #define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) +#define ANOMALY_05000383 (0) #define ANOMALY_05000386 (1) #define ANOMALY_05000389 (0) #define ANOMALY_05000400 (0) @@ -330,6 +343,7 @@ #define ANOMALY_05000465 (0) #define ANOMALY_05000467 (0) #define ANOMALY_05000474 (0) +#define ANOMALY_05000480 (0) #define ANOMALY_05000485 (0) #endif diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h index b17207f..300ef44 100644 --- a/arch/blackfin/include/asm/portmux.h +++ b/arch/blackfin/include/asm/portmux.h @@ -22,11 +22,15 @@ #define peripheral_request_list(per, label) peripheral_request_list(per) #endif +#ifndef __ASSEMBLY__ + int peripheral_request(unsigned short per, const char *label); void peripheral_free(unsigned short per); int peripheral_request_list(const unsigned short per[], const char *label); void peripheral_free_list(const unsigned short per[]); +#endif + #include <asm/blackfin.h> #ifndef P_SPORT2_TFS diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 362b8c4..bfdb586 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -12,11 +12,11 @@ #include <common.h> #include <command.h> #include <stdio_dev.h> +#include <serial.h> #include <environment.h> #include <malloc.h> #include <mmc.h> #include <net.h> -#include <timestamp.h> #include <status_led.h> #include <version.h> @@ -39,8 +39,6 @@ int post_flag; DECLARE_GLOBAL_DATA_PTR; -const char version_string[] = U_BOOT_VERSION " ("U_BOOT_DATE" - "U_BOOT_TIME")"; - __attribute__((always_inline)) static inline void serial_early_puts(const char *s) { @@ -52,7 +50,7 @@ static inline void serial_early_puts(const char *s) static int display_banner(void) { - printf("\n\n%s\n\n", version_string); + display_options(); printf("CPU: ADSP %s " "(Detected Rev: 0.%d) " "(%s boot)\n", @@ -265,6 +263,9 @@ void board_init_f(ulong bootflag) init_baudrate(); serial_early_puts("Serial init\n"); serial_init(); +#ifdef CONFIG_SERIAL_MULTI + serial_initialize(); +#endif serial_early_puts("Console init flash\n"); console_init_f(); serial_early_puts("End of early debugging\n"); diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S index d09d492..c5096a8 100644 --- a/arch/m68k/cpu/mcf5227x/start.S +++ b/arch/m68k/cpu/mcf5227x/start.S @@ -23,7 +23,6 @@ #include <asm-offsets.h> #include <config.h> -#include <timestamp.h> #include "version.h" #include <asm/cache.h> @@ -508,7 +507,5 @@ _int_handler: .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .align 4 diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S index a726b59..e6a69ab 100644 --- a/arch/m68k/cpu/mcf523x/start.S +++ b/arch/m68k/cpu/mcf523x/start.S @@ -23,7 +23,6 @@ #include <asm-offsets.h> #include <config.h> -#include <timestamp.h> #include "version.h" #include <asm/cache.h> @@ -270,7 +269,5 @@ _int_handler: .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .align 4 diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S index f0cfa6f..ee17792 100644 --- a/arch/m68k/cpu/mcf52x2/start.S +++ b/arch/m68k/cpu/mcf52x2/start.S @@ -23,7 +23,6 @@ #include <asm-offsets.h> #include <config.h> -#include <timestamp.h> #include "version.h" #include <asm/cache.h> @@ -330,7 +329,5 @@ _int_handler: .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .align 4 diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S index 53ac471..fe98d76 100644 --- a/arch/m68k/cpu/mcf532x/start.S +++ b/arch/m68k/cpu/mcf532x/start.S @@ -26,7 +26,6 @@ #include <asm-offsets.h> #include <config.h> -#include <timestamp.h> #include "version.h" #include <asm/cache.h> @@ -283,7 +282,5 @@ _int_handler: /*------------------------------------------------------------------------------*/ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .align 4 diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index 5255f37..9906014 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -23,7 +23,6 @@ #include <asm-offsets.h> #include <config.h> -#include <timestamp.h> #include "version.h" #include <asm/cache.h> @@ -540,7 +539,5 @@ _int_handler: .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .align 4 diff --git a/arch/m68k/cpu/mcf547x_8x/slicetimer.c b/arch/m68k/cpu/mcf547x_8x/slicetimer.c index 8dc010a..467a807 100644 --- a/arch/m68k/cpu/mcf547x_8x/slicetimer.c +++ b/arch/m68k/cpu/mcf547x_8x/slicetimer.c @@ -95,18 +95,9 @@ void timer_init(void) timerp->cr = SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN; } -void reset_timer(void) -{ - timestamp = 0; -} - ulong get_timer(ulong base) { return (timestamp - base); } -void set_timer(ulong t) -{ - timestamp = t; -} #endif /* CONFIG_SLTTMR */ diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S index e30923f..ec65cae 100644 --- a/arch/m68k/cpu/mcf547x_8x/start.S +++ b/arch/m68k/cpu/mcf547x_8x/start.S @@ -23,7 +23,6 @@ #include <asm-offsets.h> #include <config.h> -#include <timestamp.h> #include "version.h" #include <asm/cache.h> @@ -277,7 +276,5 @@ _int_handler: .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .align 4 diff --git a/arch/m68k/include/asm/fec.h b/arch/m68k/include/asm/fec.h index cecec59..e8cea45 100644 --- a/arch/m68k/include/asm/fec.h +++ b/arch/m68k/include/asm/fec.h @@ -39,7 +39,7 @@ typedef struct cpm_buf_desc { uint cbd_bufaddr; /* Buffer address in host memory */ } cbd_t; -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c index 6a892db..945ab66 100644 --- a/arch/m68k/lib/board.c +++ b/arch/m68k/lib/board.c @@ -574,8 +574,6 @@ void board_init_r (gd_t *id, ulong dest_addr) udelay (20); - set_timer (0); - /* Insert function pointers now that we have relocated the code */ /* Initialize from environment */ diff --git a/arch/m68k/lib/time.c b/arch/m68k/lib/time.c index 7eaea5e..a316cdf 100644 --- a/arch/m68k/lib/time.c +++ b/arch/m68k/lib/time.c @@ -116,20 +116,11 @@ void timer_init(void) DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN; } -void reset_timer(void) -{ - timestamp = 0; -} - ulong get_timer(ulong base) { return (timestamp - base); } -void set_timer(ulong t) -{ - timestamp = t; -} #endif /* CONFIG_MCFTMR */ #if defined(CONFIG_MCFPIT) @@ -173,14 +164,6 @@ void timer_init(void) timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN; } -void set_timer(ulong t) -{ - volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE); - - timestamp = 0; - timerp->pmr = lastinc = 0; -} - ulong get_timer(ulong base) { unsigned short now, diff; @@ -196,8 +179,8 @@ ulong get_timer(ulong base) void wait_ticks(unsigned long ticks) { - set_timer(0); - while (get_timer(0) < ticks) ; + u32 start = get_timer(0); + while (get_timer(start) < ticks) ; } #endif /* CONFIG_MCFPIT */ diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c index 4936c62..a167755 100644 --- a/arch/microblaze/cpu/timer.c +++ b/arch/microblaze/cpu/timer.c @@ -28,11 +28,6 @@ volatile int timestamp = 0; -void reset_timer (void) -{ - timestamp = 0; -} - #ifdef CONFIG_SYS_TIMER_0 ulong get_timer (ulong base) { @@ -45,11 +40,6 @@ ulong get_timer (ulong base) } #endif -void set_timer (ulong t) -{ - timestamp = t; -} - #ifdef CONFIG_SYS_INTC_0 #ifdef CONFIG_SYS_TIMER_0 microblaze_timer_t *tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR); @@ -66,7 +56,7 @@ int timer_init (void) tmr->control = TIMER_INTERRUPT | TIMER_RESET; tmr->control = TIMER_ENABLE | TIMER_ENABLE_INTR | TIMER_RELOAD | TIMER_DOWN_COUNT; - reset_timer (); + timestamp = 0; install_interrupt_handler (CONFIG_SYS_TIMER_0_IRQ, timer_isr, (void *)tmr); return 0; } diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c index c5f7ac4..d97543b 100644 --- a/arch/microblaze/lib/board.c +++ b/arch/microblaze/lib/board.c @@ -27,7 +27,6 @@ #include <common.h> #include <command.h> #include <malloc.h> -#include <timestamp.h> #include <version.h> #include <watchdog.h> #include <stdio_dev.h> @@ -35,8 +34,6 @@ DECLARE_GLOBAL_DATA_PTR; -const char version_string[] = U_BOOT_VERSION " ("U_BOOT_DATE" - "U_BOOT_TIME")"; - #ifdef CONFIG_SYS_GPIO_0 extern int gpio_init (void); #endif diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 5d7467d..9c1b2f7 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -27,6 +27,10 @@ #include <asm/regdef.h> #include <asm/mipsregs.h> +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + /* * For the moment disable interrupts, mark the kernel mode and * set ST0_KX so that the CPU does not spit fire when using @@ -64,9 +68,16 @@ _start: RVECENT(reset,0) # U-boot entry point RVECENT(reset,1) # software reboot -#ifdef CONFIG_INCA_IP - .word INFINEON_EBU_BOOTCFG # EBU init code, fetched during - .word 0x00000000 # booting phase of the flash +#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG + /* + * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to + * access external NOR flashes. If the board boots from NOR flash the + * internal BootROM does a blind read at address 0xB0000010 to read the + * initial configuration for that EBU in order to access the flash + * device with correct parameters. This config option is board-specific. + */ + .word CONFIG_SYS_XWAY_EBU_BOOTCFG + .word 0x00000000 #else RVECENT(romReserved,2) #endif @@ -242,7 +253,7 @@ reset: nop /* ... and enable them */ - li t0, CONF_CM_CACHABLE_NONCOHERENT + li t0, CONFIG_SYS_MIPS_CACHE_MODE mtc0 t0, CP0_CONFIG #endif diff --git a/arch/mips/cpu/mips32/time.c b/arch/mips/cpu/mips32/time.c index 0e66441..350896a 100644 --- a/arch/mips/cpu/mips32/time.c +++ b/arch/mips/cpu/mips32/time.c @@ -42,12 +42,6 @@ int timer_init(void) return 0; } -void reset_timer(void) -{ - timestamp = 0; - write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY); -} - ulong get_timer(ulong base) { unsigned int count; @@ -64,12 +58,6 @@ ulong get_timer(ulong base) return (timestamp - base); } -void set_timer(ulong t) -{ - timestamp = t; - write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY); -} - void __udelay(unsigned long usec) { unsigned int tmo; diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c index 623c4d7..4f85bbd 100644 --- a/arch/mips/lib/board.c +++ b/arch/mips/lib/board.c @@ -25,7 +25,6 @@ #include <command.h> #include <malloc.h> #include <stdio_dev.h> -#include <timestamp.h> #include <version.h> #include <net.h> #include <environment.h> @@ -50,9 +49,6 @@ extern ulong uboot_end; ulong monitor_flash_len; -const char version_string[] = - U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"; - static char *failed = "*** failed ***\n"; /* diff --git a/arch/nios2/cpu/interrupts.c b/arch/nios2/cpu/interrupts.c index 63acfa9..0a97fa6 100644 --- a/arch/nios2/cpu/interrupts.c +++ b/arch/nios2/cpu/interrupts.c @@ -98,12 +98,6 @@ ulong get_timer (ulong base) return (timestamp - base); } -void set_timer (ulong t) -{ - timestamp = t; -} - - /* The board must handle this interrupt if a timer is not * provided. */ diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index bf5d672..0f4ab28 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -23,7 +23,6 @@ #include <asm-offsets.h> #include <config.h> -#include <timestamp.h> #include <version.h> /************************************************************************* @@ -196,14 +195,8 @@ dly_clks: bge r4, r0, dly_clks ret - -#if !defined(CONFIG_IDENT_STRING) -#define CONFIG_IDENT_STRING "" -#endif .data .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" diff --git a/arch/powerpc/cpu/74xx_7xx/start.S b/arch/powerpc/cpu/74xx_7xx/start.S index f6011fc..75fb773 100644 --- a/arch/powerpc/cpu/74xx_7xx/start.S +++ b/arch/powerpc/cpu/74xx_7xx/start.S @@ -35,7 +35,6 @@ #include <asm-offsets.h> #include <config.h> #include <74xx_7xx.h> -#include <timestamp.h> #include <version.h> #include <ppc_asm.tmpl> @@ -52,10 +51,6 @@ #include <galileo/gt64260R.h> #endif -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - /* We don't want the MMU yet. */ #undef MSR_KERNEL @@ -89,9 +84,7 @@ .long 0x27051956 /* U-Boot Magic Number */ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" . = EXC_OFF_SYS_RESET .globl _start diff --git a/arch/powerpc/cpu/mpc512x/serial.c b/arch/powerpc/cpu/mpc512x/serial.c index cb5bbf0..5ee9cef 100644 --- a/arch/powerpc/cpu/mpc512x/serial.c +++ b/arch/powerpc/cpu/mpc512x/serial.c @@ -30,6 +30,7 @@ */ #include <common.h> +#include <linux/compiler.h> #include <asm/io.h> #include <asm/processor.h> #include <serial.h> @@ -318,9 +319,8 @@ int serial_getcts_dev(unsigned int idx) serial_puts_dev(port, s); \ } -#define INIT_PSC_SERIAL_STRUCTURE(port, name, bus) { \ +#define INIT_PSC_SERIAL_STRUCTURE(port, name) { \ name, \ - bus, \ serial##port##_init, \ serial##port##_uninit, \ serial##port##_setbrg, \ @@ -333,27 +333,38 @@ int serial_getcts_dev(unsigned int idx) #if defined(CONFIG_SYS_PSC1) DECLARE_PSC_SERIAL_FUNCTIONS(1); struct serial_device serial1_device = -INIT_PSC_SERIAL_STRUCTURE(1, "psc1", "UART1"); +INIT_PSC_SERIAL_STRUCTURE(1, "psc1"); #endif #if defined(CONFIG_SYS_PSC3) DECLARE_PSC_SERIAL_FUNCTIONS(3); struct serial_device serial3_device = -INIT_PSC_SERIAL_STRUCTURE(3, "psc3", "UART3"); +INIT_PSC_SERIAL_STRUCTURE(3, "psc3"); #endif #if defined(CONFIG_SYS_PSC4) DECLARE_PSC_SERIAL_FUNCTIONS(4); struct serial_device serial4_device = -INIT_PSC_SERIAL_STRUCTURE(4, "psc4", "UART4"); +INIT_PSC_SERIAL_STRUCTURE(4, "psc4"); #endif #if defined(CONFIG_SYS_PSC6) DECLARE_PSC_SERIAL_FUNCTIONS(6); struct serial_device serial6_device = -INIT_PSC_SERIAL_STRUCTURE(6, "psc6", "UART6"); +INIT_PSC_SERIAL_STRUCTURE(6, "psc6"); #endif +__weak struct serial_device *default_serial_console(void) +{ +#if (CONFIG_PSC_CONSOLE == 3) + return &serial3_device; +#elif (CONFIG_PSC_CONSOLE == 6) + return &serial6_device; +#else +#error "invalid CONFIG_PSC_CONSOLE" +#endif +} + #else void serial_setbrg(void) diff --git a/arch/powerpc/cpu/mpc512x/start.S b/arch/powerpc/cpu/mpc512x/start.S index 9c2e488..ed362d8 100644 --- a/arch/powerpc/cpu/mpc512x/start.S +++ b/arch/powerpc/cpu/mpc512x/start.S @@ -31,7 +31,9 @@ #include <asm-offsets.h> #include <config.h> -#include <timestamp.h> +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "MPC512X" +#endif #include <version.h> #define CONFIG_521X 1 /* needed for Linux kernel header files*/ @@ -46,10 +48,6 @@ #include <asm/mmu.h> #include <asm/u-boot.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "MPC512X" -#endif - /* * Floating Point enable, Machine Check and Recoverable Interr. */ @@ -89,9 +87,7 @@ .long 0x27051956 /* U-Boot Magic Number */ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii " ", CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" /* * Vector Table diff --git a/arch/powerpc/cpu/mpc5xx/start.S b/arch/powerpc/cpu/mpc5xx/start.S index cc11c8f..cc4c33e 100644 --- a/arch/powerpc/cpu/mpc5xx/start.S +++ b/arch/powerpc/cpu/mpc5xx/start.S @@ -33,7 +33,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc5xx.h> -#include <timestamp.h> #include <version.h> #define CONFIG_5xx 1 /* needed for Linux kernel header files */ @@ -46,10 +45,6 @@ #include <asm/processor.h> #include <asm/u-boot.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - /* We don't have a MMU. */ #undef MSR_KERNEL @@ -82,9 +77,7 @@ .long 0x27051956 /* U-Boot Magic Number */ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" . = EXC_OFF_SYS_RESET .globl _start diff --git a/arch/powerpc/cpu/mpc5xxx/serial.c b/arch/powerpc/cpu/mpc5xxx/serial.c index 0127065..aa09f67 100644 --- a/arch/powerpc/cpu/mpc5xxx/serial.c +++ b/arch/powerpc/cpu/mpc5xxx/serial.c @@ -34,6 +34,7 @@ */ #include <common.h> +#include <linux/compiler.h> #include <mpc5xxx.h> #if defined (CONFIG_SERIAL_MULTI) @@ -338,7 +339,6 @@ int serial1_tstc(void) struct serial_device serial0_device = { "serial0", - "UART0", serial0_init, NULL, serial0_setbrg, @@ -348,10 +348,14 @@ struct serial_device serial0_device = serial0_puts, }; +__weak struct serial_device *default_serial_console(void) +{ + return &serial0_device; +} + struct serial_device serial1_device = { "serial1", - "UART1", serial1_init, NULL, serial1_setbrg, diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S index 192aa50..51cc4e2 100644 --- a/arch/powerpc/cpu/mpc5xxx/start.S +++ b/arch/powerpc/cpu/mpc5xxx/start.S @@ -28,7 +28,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc5xxx.h> -#include <timestamp.h> #include <version.h> #define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */ @@ -41,10 +40,6 @@ #include <asm/mmu.h> #include <asm/u-boot.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - /* We don't want the MMU yet. */ #undef MSR_KERNEL @@ -80,9 +75,7 @@ .data .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" /* * Exception vectors diff --git a/arch/powerpc/cpu/mpc8220/start.S b/arch/powerpc/cpu/mpc8220/start.S index 300b35c..a1a2dc5 100644 --- a/arch/powerpc/cpu/mpc8220/start.S +++ b/arch/powerpc/cpu/mpc8220/start.S @@ -28,7 +28,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc8220.h> -#include <timestamp.h> #include <version.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ @@ -40,10 +39,6 @@ #include <asm/mmu.h> #include <asm/u-boot.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - /* We don't want the MMU yet. */ #undef MSR_KERNEL @@ -79,9 +74,7 @@ .data .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" /* * Exception vectors diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S index fc4e922..70db73e 100644 --- a/arch/powerpc/cpu/mpc824x/start.S +++ b/arch/powerpc/cpu/mpc824x/start.S @@ -40,7 +40,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc824x.h> -#include <timestamp.h> #include <version.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ @@ -52,10 +51,6 @@ #include <asm/mmu.h> #include <asm/u-boot.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - /* We don't want the MMU yet. */ #undef MSR_KERNEL @@ -92,9 +87,7 @@ .long 0x27051956 /* U-Boot Magic Number */ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" . = EXC_OFF_SYS_RESET .globl _start diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S index 702546e..3299d72 100644 --- a/arch/powerpc/cpu/mpc8260/start.S +++ b/arch/powerpc/cpu/mpc8260/start.S @@ -28,7 +28,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc8260.h> -#include <timestamp.h> #include <version.h> #define CONFIG_8260 1 /* needed for Linux kernel header files */ @@ -41,10 +40,6 @@ #include <asm/mmu.h> #include <asm/u-boot.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - /* We don't want the MMU yet. */ #undef MSR_KERNEL @@ -87,9 +82,7 @@ .data .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" /* * Hard Reset Configuration Word (HRCW) table diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 44aaa9a..9b01f0d 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -68,6 +68,12 @@ void board_add_ram_info(int use_default) #ifndef CONFIG_SYS_READ_SPD #define CONFIG_SYS_READ_SPD i2c_read #endif +#ifndef SPD_EEPROM_OFFSET +#define SPD_EEPROM_OFFSET 0 +#endif +#ifndef SPD_EEPROM_ADDR_LEN +#define SPD_EEPROM_ADDR_LEN 1 +#endif /* * Convert picoseconds into clock cycles (rounding up if needed). @@ -160,7 +166,8 @@ long int spd_sdram() isync(); /* Read SPD parameters with I2C */ - CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); + CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET, + SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd)); #ifdef SPD_DEBUG spd_debug(&spd); #endif @@ -562,6 +569,9 @@ long int spd_sdram() * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266. */ wr_data_delay = 2; +#ifdef CONFIG_SYS_DDR_WRITE_DATA_DELAY + wr_data_delay = CONFIG_SYS_DDR_WRITE_DATA_DELAY; +#endif /* * Write Latency @@ -601,6 +611,9 @@ long int spd_sdram() */ cpo = 0; if (spd.mem_type == SPD_MEMTYPE_DDR2) { +#ifdef CONFIG_SYS_DDR_CPO + cpo = CONFIG_SYS_DDR_CPO; +#else if (effective_data_rate == 266) { cpo = 0x4; /* READ_LAT + 1/2 */ } else if (effective_data_rate == 333) { @@ -611,6 +624,7 @@ long int spd_sdram() /* Automatic calibration */ cpo = 0x1f; } +#endif } ddr->timing_cfg_2 = (0 @@ -679,6 +693,9 @@ long int spd_sdram() ddr->sdram_mode = (0 | (1 << (16 + 10)) /* DQS Differential disable */ +#ifdef CONFIG_SYS_DDR_MODE_WEAK + | (1 << (16 + 1)) /* weak driver (~60%) */ +#endif | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */ | ((twr_clk - 1) << 9) /* Write Recovery Autopre */ diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 5e616dd..4542ab1 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -327,6 +327,8 @@ int get_clocks(void) i2c1_clk = enc_clk; #elif defined(CONFIG_FSL_ESDHC) i2c1_clk = sdhc_clk; +#elif defined(CONFIG_MPC837x) + i2c1_clk = enc_clk; #endif #if !defined(CONFIG_MPC832x) i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ @@ -481,7 +483,8 @@ int get_clocks(void) gd->qe_clk = qe_clk; gd->brg_clk = brg_clk; #endif -#if defined(CONFIG_MPC837x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC837x) gd->pciexp1_clk = pciexp1_clk; gd->pciexp2_clk = pciexp2_clk; #endif @@ -541,7 +544,8 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_MPC834x) printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk)); #endif -#if defined(CONFIG_MPC837x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC837x) printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->pciexp1_clk)); printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->pciexp2_clk)); #endif diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 7e60315..b70b4ca 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -30,7 +30,9 @@ #include <asm-offsets.h> #include <config.h> #include <mpc83xx.h> -#include <timestamp.h> +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "MPC83XX" +#endif #include <version.h> #define CONFIG_83XX 1 /* needed for Linux kernel header files*/ @@ -43,10 +45,6 @@ #include <asm/mmu.h> #include <asm/u-boot.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "MPC83XX" -#endif - /* We don't want the MMU yet. */ #undef MSR_KERNEL @@ -107,9 +105,7 @@ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii " ", CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .align 2 diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index d61d34c..7026bca 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -64,6 +64,8 @@ COBJS-$(CONFIG_P1024) += ddr-gen3.o COBJS-$(CONFIG_P1025) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_PPC_P2040) += ddr-gen3.o +COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o @@ -76,6 +78,8 @@ COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o # various SoC specific assignments +COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o +COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o @@ -107,6 +111,8 @@ COBJS-$(CONFIG_P1024) += p1021_serdes.o COBJS-$(CONFIG_P1025) += p1021_serdes.o COBJS-$(CONFIG_P2010) += p2020_serdes.o COBJS-$(CONFIG_P2020) += p2020_serdes.o +COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o +COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index f863f4a..22fa461 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -46,7 +46,6 @@ int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; - uint fam; uint ver; uint major, minor; struct cpu_type *cpu; @@ -94,30 +93,25 @@ int checkcpu (void) printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); - fam = PVR_FAM(pvr); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); - if (PVR_FAM(PVR_85xx)) { - switch(PVR_MEM(pvr)) { - case 0x1: - case 0x2: - puts("E500"); - break; - case 0x3: - puts("E500MC"); - break; - case 0x4: - puts("E5500"); - break; - default: - puts("Unknown"); - break; - } - } else { + switch(ver) { + case PVR_VER_E500_V1: + case PVR_VER_E500_V2: + puts("E500"); + break; + case PVR_VER_E500MC: + puts("E500MC"); + break; + case PVR_VER_E5500: + puts("E5500"); + break; + default: puts("Unknown"); + break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); @@ -336,7 +330,9 @@ phys_size_t initdram(int board_type) } #endif -#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) +#if defined(CONFIG_SPD_EEPROM) || \ + defined(CONFIG_DDR_SPD) || \ + defined(CONFIG_SYS_DDR_RAW_TIMING) dram_size = fsl_ddr_sdram(); #else dram_size = fixed_sdram(); @@ -356,7 +352,7 @@ phys_size_t initdram(int board_type) lbc_sdram_init(); #endif - puts("DDR: "); + debug("DDR: "); return dram_size; } #endif /* CONFIG_SYS_RAMBOOT */ @@ -372,6 +368,8 @@ void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); +void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); + static void dump_spd_ddr_reg(void) { int i, j, k, m; @@ -458,19 +456,9 @@ static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; unsigned long epn; u32 tsize, valid, ptr; - phys_addr_t rpn = 0; int ddr_esel; - ptr = vstart; - - while (ptr < (vstart + size)) { - ddr_esel = find_tlb_idx((void *)ptr, 1); - if (ddr_esel != -1) { - read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); - disable_tlb(ddr_esel); - } - ptr += TSIZE_TO_BYTES(tsize); - } + clear_ddr_tlbs_phys(p_addr, size>>20); /* Setup new tlb to cover the physical address */ setup_ddr_tlbs_phys(p_addr, size>>20); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index b3da970..6aca166 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -222,6 +222,10 @@ static void corenet_tb_init(void) void cpu_init_f (void) { extern void m8560_cpm_reset (void); +#ifdef CONFIG_SYS_DCSRBAR_PHYS + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif + #ifdef CONFIG_MPC8548 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); uint svr = get_svr(); @@ -262,6 +266,13 @@ void cpu_init_f (void) /* Invalidate the CPC before DDR gets enabled */ invalidate_cpc(); + + #ifdef CONFIG_SYS_DCSRBAR_PHYS + /* set DCSRCR so that DCSR space is 1G */ + setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); + in_be32(&gur->dcsrcr); +#endif + } /* Implement a dummy function for those platforms w/o SERDES */ @@ -381,6 +392,12 @@ int cpu_init_r(void) puts("enabled\n"); } #elif defined(CONFIG_BACKSIDE_L2_CACHE) + if ((SVR_SOC_VER(get_svr()) == SVR_P2040) || + (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) { + puts("N/A\n"); + goto skip_l2; + } + u32 l2cfg0 = mfspr(SPRN_L2CFG0); /* invalidate the L2 cache */ @@ -401,6 +418,8 @@ int cpu_init_r(void) ; printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); } + +skip_l2: #else puts("disabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 97d3928..8f13cd8 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -33,6 +33,7 @@ #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> #endif +#include "../../../../drivers/qe/qe.h" /* For struct qe_firmware */ DECLARE_GLOBAL_DATA_PTR; @@ -227,6 +228,12 @@ static inline void ft_fixup_l2cache(void *blob) u32 *ph; u32 l2cfg0 = mfspr(SPRN_L2CFG0); u32 size, line_size, num_ways, num_sets; + int has_l2 = 1; + + /* P2040/P2040E has no L2, so dont set any L2 props */ + if ((SVR_SOC_VER(get_svr()) == SVR_P2040) || + (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) + has_l2 = 0; size = (l2cfg0 & 0x3fff) * 64 * 1024; num_ways = ((l2cfg0 >> 14) & 0x1f) + 1; @@ -249,21 +256,22 @@ static inline void ft_fixup_l2cache(void *blob) goto next; } + if (has_l2) { #ifdef CONFIG_SYS_CACHE_STASHING - { u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); if (reg) fdt_setprop_cell(blob, l2_off, "cache-stash-id", (*reg * 2) + 32 + 1); - } #endif - fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); - fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size); - fdt_setprop_cell(blob, l2_off, "cache-size", size); - fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); - fdt_setprop_cell(blob, l2_off, "cache-level", 2); - fdt_setprop(blob, l2_off, "compatible", "cache", 6); + fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); + fdt_setprop_cell(blob, l2_off, "cache-block-size", + line_size); + fdt_setprop_cell(blob, l2_off, "cache-size", size); + fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); + fdt_setprop_cell(blob, l2_off, "cache-level", 2); + fdt_setprop(blob, l2_off, "compatible", "cache", 6); + } if (l3_off < 0) { ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); @@ -406,6 +414,126 @@ static void ft_fixup_qe_snum(void *blob) } #endif +/** + * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree + * + * The binding for an Fman firmware node is documented in + * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains + * the actual Fman firmware binary data. The operating system is expected to + * be able to parse the binary data to determine any attributes it needs. + */ +#ifdef CONFIG_SYS_DPAA_FMAN +void fdt_fixup_fman_firmware(void *blob) +{ + int rc, fmnode, fwnode = -1; + uint32_t phandle; + struct qe_firmware *fmanfw; + const struct qe_header *hdr; + unsigned int length; + uint32_t crc; + const char *p; + + /* The first Fman we find will contain the actual firmware. */ + fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman"); + if (fmnode < 0) + /* Exit silently if there are no Fman devices */ + return; + + /* If we already have a firmware node, then also exit silently. */ + if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0) + return; + + /* If the environment variable is not set, then exit silently */ + p = getenv("fman_ucode"); + if (!p) + return; + + fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 0); + if (!fmanfw) + return; + + hdr = &fmanfw->header; + length = be32_to_cpu(hdr->length); + + /* Verify the firmware. */ + if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || + (hdr->magic[2] != 'F')) { + printf("Data at %p is not an Fman firmware\n", fmanfw); + return; + } + + if (length > CONFIG_SYS_FMAN_FW_LENGTH) { + printf("Fman firmware at %p is too large (size=%u)\n", + fmanfw, length); + return; + } + + length -= sizeof(u32); /* Subtract the size of the CRC */ + crc = be32_to_cpu(*(u32 *)((void *)fmanfw + length)); + if (crc != crc32_no_comp(0, (void *)fmanfw, length)) { + printf("Fman firmware at %p has invalid CRC\n", fmanfw); + return; + } + + /* Increase the size of the fdt to make room for the node. */ + rc = fdt_increase_size(blob, fmanfw->header.length); + if (rc < 0) { + printf("Unable to make room for Fman firmware: %s\n", + fdt_strerror(rc)); + return; + } + + /* Create the firmware node. */ + fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware"); + if (fwnode < 0) { + char s[64]; + fdt_get_path(blob, fmnode, s, sizeof(s)); + printf("Could not add firmware node to %s: %s\n", s, + fdt_strerror(fwnode)); + return; + } + rc = fdt_setprop_string(blob, fwnode, "compatible", "fsl,fman-firmware"); + if (rc < 0) { + char s[64]; + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add compatible property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + phandle = fdt_alloc_phandle(blob); + rc = fdt_setprop_cell(blob, fwnode, "linux,phandle", phandle); + if (rc < 0) { + char s[64]; + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add phandle property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, fmanfw->header.length); + if (rc < 0) { + char s[64]; + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add firmware property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + + /* Find all other Fman nodes and point them to the firmware node. */ + while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode, "fsl,fman")) > 0) { + rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle", phandle); + if (rc < 0) { + char s[64]; + fdt_get_path(blob, fmnode, s, sizeof(s)); + printf("Could not add pointer property to node %s: %s\n", + s, fdt_strerror(rc)); + return; + } + } +} +#else +#define fdt_fixup_fman_firmware(x) +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { int off; @@ -445,6 +573,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) ft_fixup_qe_snum(blob); #endif + fdt_fixup_fman_firmware(blob); + #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); @@ -505,4 +635,79 @@ void ft_cpu_setup(void *blob, bd_t *bd) */ do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer", "timer-frequency", gd->bus_clk/2, 1); + + do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", + "clock_freq", gd->bus_clk, 1); +} + +/* + * For some CCSR devices, we only have the virtual address, not the physical + * address. This is because we map CCSR as a whole, so we typically don't need + * a macro for the physical address of any device within CCSR. In this case, + * we calculate the physical address of that device using it's the difference + * between the virtual address of the device and the virtual address of the + * beginning of CCSR. + */ +#define CCSR_VIRT_TO_PHYS(x) \ + (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR)) + +/* + * Verify the device tree + * + * This function compares several CONFIG_xxx macros that contain physical + * addresses with the corresponding nodes in the device tree, to see if + * the physical addresses are all correct. For example, if + * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address + * of the first UART. We convert this to a physical address and compare + * that with the physical address of the first ns16550-compatible node + * in the device tree. If they don't match, then we display a warning. + * + * Returns 1 on success, 0 on failure + */ +int ft_verify_fdt(void *fdt) +{ + uint64_t ccsr = 0; + int aliases; + int off; + + /* First check the CCSR base address */ + off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4); + if (off > 0) + ccsr = fdt_get_base_address(fdt, off); + + if (!ccsr) { + printf("Warning: could not determine base CCSR address in " + "device tree\n"); + /* No point in checking anything else */ + return 0; + } + + if (ccsr != CONFIG_SYS_CCSRBAR_PHYS) { + printf("Warning: U-Boot configured CCSR at address %llx,\n" + "but the device tree has it at %llx\n", + (uint64_t) CONFIG_SYS_CCSRBAR_PHYS, ccsr); + /* No point in checking anything else */ + return 0; + } + + /* + * Get the 'aliases' node. If there isn't one, then there's nothing + * left to do. + */ + aliases = fdt_path_offset(fdt, "/aliases"); + if (aliases > 0) { +#ifdef CONFIG_SYS_NS16550_COM1 + if (!fdt_verify_alias_address(fdt, aliases, "serial0", + CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1))) + return 0; +#endif + +#ifdef CONFIG_SYS_NS16550_COM2 + if (!fdt_verify_alias_address(fdt, aliases, "serial1", + CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2))) + return 0; +#endif + } + + return 1; } diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 741a0f8..4307a4c 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -32,6 +32,18 @@ #include <asm/errno.h> #include "fsl_corenet_serdes.h" +/* + * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together. + * The code is already very complicated as it is, and separating the two + * completely would just make things worse. We try to keep them as separate + * as possible, but for now we require SERDES8 if SERDES_A001 is defined. + */ +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 +#ifndef CONFIG_SYS_P4080_ERRATUM_SERDES8 +#error "CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8" +#endif +#endif + static u32 serdes_prtcl_map; #define HWCONFIG_BUFFER_SIZE 128 @@ -259,9 +271,28 @@ void serdes_reset_rx(enum srds_prtcl device) #endif #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 +/* + * Enable a SERDES bank that was disabled via the RCW + * + * We only call this function for SERDES8 and SERDES-A001 in cases we really + * want to enable the bank, whether we actually want to use the lanes or not, + * so make sure at least one lane is enabled. We're only enabling this one + * lane to satisfy errata requirements that the bank be enabled. + * + * We use a local variable instead of srds_lpd_b[] because we want drivers to + * think that the lanes actually are disabled. + */ static void enable_bank(ccsr_gur_t *gur, int bank) { u32 rcw5; + u32 temp_lpd_b = srds_lpd_b[bank]; + + /* + * If we're asked to disable all lanes, just pretend we're doing + * that. + */ + if (temp_lpd_b == 0xF) + temp_lpd_b = 0xE; /* * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in @@ -270,10 +301,10 @@ static void enable_bank(ccsr_gur_t *gur, int bank) rcw5 = in_be32(gur->rcwsr + 5); if (bank == FSL_SRDS_BANK_2) { rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2; - rcw5 |= srds_lpd_b[bank] << 26; + rcw5 |= temp_lpd_b << 26; } else if (bank == FSL_SRDS_BANK_3) { rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3; - rcw5 |= srds_lpd_b[bank] << 18; + rcw5 |= temp_lpd_b << 18; } else { printf("SERDES: enable_bank: bad bank %d\n", bank + 1); return; @@ -343,8 +374,6 @@ static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur, */ setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, SRDS_PLLCR1_PLL_BWSEL); - - enable_bank(gur, FSL_SRDS_BANK_3); break; case 0x0f: @@ -379,10 +408,9 @@ static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur, SRDS_PLLCR0_FRATE_SEL_MASK, SRDS_PLLCR0_FRATE_SEL_6_25); break; - default: - enable_bank(gur, FSL_SRDS_BANK_3); } + enable_bank(gur, FSL_SRDS_BANK_3); } #endif @@ -451,7 +479,7 @@ static void wait_for_rstdone(unsigned int bank) } while (end_tick > get_ticks()); if (!(rstctl & SRDS_RSTCTL_RSTDONE)) - printf("SERDES: timeout resetting bank %u\n", bank); + printf("SERDES: timeout resetting bank %u\n", bank + 1); } void fsl_serdes_init(void) @@ -523,6 +551,14 @@ void fsl_serdes_init(void) srds_lpd_b[bank] = simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf; } + + if ((cfg == 0xf) || (cfg == 0x10)) { + /* + * For SERDES protocols 0xF and 0x10, force bank 3 to be + * disabled, because it is not supported. + */ + srds_lpd_b[FSL_SRDS_BANK_3] = 0xF; + } #endif /* Look for banks with all lanes disabled, and power down the bank. */ @@ -546,7 +582,10 @@ void fsl_serdes_init(void) #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 /* * The work-aroud for erratum SERDES-A001 is needed only if bank two - * is disabled and bank three is enabled. + * is disabled and bank three is enabled. The converse is also true, + * but SERDES8 ensures that bank 3 is always enabled if bank 2 is + * enabled, so there's no point in complicating the code to handle + * that situation. */ need_serdes_a001 = !have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3]; @@ -724,29 +763,17 @@ void fsl_serdes_init(void) p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr, serdes8_devdisr2, cfg); } else if (idx == 2) { - /* Eable bank two now that bank three is enabled. */ + /* Enable bank two now that bank three is enabled. */ enable_bank(gur, FSL_SRDS_BANK_2); } #endif - /* reset banks for errata */ - setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_RST); - wait_for_rstdone(bank); } #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 if (need_serdes_a001) { - /* - * Bank three has been enabled, so enable bank two and then - * disable it. - */ - srds_lpd_b[FSL_SRDS_BANK_2] = 0; - enable_bank(gur, FSL_SRDS_BANK_2); - - wait_for_rstdone(FSL_SRDS_BANK_2); - - /* Disable bank 2 */ + /* Bank 3 has been enabled, so now we can disable bank 2 */ setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl, SRDS_RSTCTL_SDPD); } diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c new file mode 100644 index 0000000..112ea56 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -0,0 +1,109 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO( 1, 2, 1, 0), + SET_QP_INFO( 3, 4, 2, 1), + SET_QP_INFO( 5, 6, 3, 2), + SET_QP_INFO( 7, 8, 4, 3), + SET_QP_INFO( 9, 10, 5, 4), + SET_QP_INFO( 0, 0, 0, 5), + SET_QP_INFO( 0, 0, 0, 6), + SET_QP_INFO( 0, 0, 0, 7), + SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ + SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ +}; +#endif + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(31), + SET_BMAN_LIODN(32), +#endif + + SET_SDHC_LIODN(1, 64), + + SET_PME_LIODN(117), + + SET_USB_LIODN(1, "fsl-usb2-mph", 125), + SET_USB_LIODN(2, "fsl-usb2-dr", 126), + + SET_SATA_LIODN(1, 127), + SET_SATA_LIODN(2, 128), + + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), + + SET_DMA_LIODN(1, 197), + SET_DMA_LIODN(2, 198), + + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 10), + SET_FMAN_RX_1G_LIODN(1, 1, 11), + SET_FMAN_RX_1G_LIODN(1, 2, 12), + SET_FMAN_RX_1G_LIODN(1, 3, 13), + SET_FMAN_RX_1G_LIODN(1, 4, 14), +#if (CONFIG_SYS_NUM_FM1_10GEC == 1) + SET_FMAN_RX_10G_LIODN(1, 0, 15), +#endif +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 129, 130), + SET_SEC_JR_LIODN_ENTRY(1, 131, 132), + SET_SEC_JR_LIODN_ENTRY(2, 133, 134), + SET_SEC_JR_LIODN_ENTRY(3, 135, 136), + SET_SEC_RTIC_LIODN_ENTRY(a, 154), + SET_SEC_RTIC_LIODN_ENTRY(b, 155), + SET_SEC_RTIC_LIODN_ENTRY(c, 156), + SET_SEC_RTIC_LIODN_ENTRY(d, 157), + SET_SEC_DECO_LIODN_ENTRY(0, 97, 98), + SET_SEC_DECO_LIODN_ENTRY(1, 99, 100), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), +#endif +}; diff --git a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c index a96eff4..f68f281 100644 --- a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c @@ -36,6 +36,9 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { [0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, + [0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, PCIE2, PCIE2, NONE, NONE, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, NONE, NONE, NONE, NONE, }, [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, NONE, NONE, }, @@ -49,6 +52,12 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { [0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, + [0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, XAUI_FM1, XAUI_FM1, XAUI_FM1, + XAUI_FM1, NONE, NONE, NONE, NONE, }, + [0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, + NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, [0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, @@ -59,8 +68,39 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { enum srds_prtcl serdes_get_prtcl(int cfg, int lane) { + enum srds_prtcl prtcl; + u32 svr = get_svr(); + u32 ver = SVR_SOC_VER(svr); + if (!serdes_lane_enabled(lane)) return NONE; - return serdes_cfg_tbl[cfg][lane]; + prtcl = serdes_cfg_tbl[cfg][lane]; + + /* P2040[e] does not support XAUI */ + if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1)) + prtcl = NONE; + + return prtcl; +} + +int is_serdes_prtcl_valid(u32 prtcl) +{ + int i; + u32 svr = get_svr(); + u32 ver = SVR_SOC_VER(svr); + + if (prtcl > ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + /* P2040[e] does not support XAUI */ + if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1)) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index 1255898..9836588 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -24,6 +24,7 @@ #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> +#ifdef CONFIG_SYS_DPAA_QBMAN struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO( 1, 2, 1, 0), @@ -37,10 +38,13 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ }; +#endif struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN SET_QMAN_LIODN(31), SET_BMAN_LIODN(32), +#endif SET_SDHC_LIODN(1, 64), @@ -65,6 +69,7 @@ struct liodn_id_table liodn_tbl[] = { SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), }; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN struct liodn_id_table fman1_liodn_tbl[] = { @@ -75,6 +80,7 @@ struct liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 4, 14), SET_FMAN_RX_10G_LIODN(1, 0, 15), }; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #endif struct liodn_id_table sec_liodn_tbl[] = { @@ -89,6 +95,7 @@ struct liodn_id_table sec_liodn_tbl[] = { SET_SEC_DECO_LIODN_ENTRY(0, 97, 98), SET_SEC_DECO_LIODN_ENTRY(1, 99, 100), }; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), @@ -99,7 +106,3 @@ struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), #endif }; - -int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); -int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); -int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index fd155c8..560c02a 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -24,6 +24,7 @@ #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> +#ifdef CONFIG_SYS_DPAA_QBMAN struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO( 1, 2, 1, 0), @@ -37,6 +38,7 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */ SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */ }; +#endif struct liodn_id_table liodn_tbl[] = { SET_USB_LIODN(1, "fsl-usb2-mph", 127), @@ -55,10 +57,13 @@ struct liodn_id_table liodn_tbl[] = { SET_GUTS_LIODN(NULL, 199, rio2liodnr, 0), SET_GUTS_LIODN(NULL, 200, rmuliodnr, 0), +#ifdef CONFIG_SYS_DPAA_QBMAN SET_QMAN_LIODN(31), SET_BMAN_LIODN(32), +#endif SET_PME_LIODN(128), }; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN struct liodn_id_table fman1_liodn_tbl[] = { @@ -68,6 +73,7 @@ struct liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 3, 14), SET_FMAN_RX_10G_LIODN(1, 0, 15), }; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #if (CONFIG_SYS_NUM_FMAN == 2) struct liodn_id_table fman2_liodn_tbl[] = { @@ -77,6 +83,7 @@ struct liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 3, 19), SET_FMAN_RX_10G_LIODN(2, 0, 20), }; +int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl); #endif #endif @@ -101,6 +108,7 @@ struct liodn_id_table sec_liodn_tbl[] = { SET_SEC_DECO_LIODN_ENTRY(3, 132, 164), SET_SEC_DECO_LIODN_ENTRY(4, 133, 165), }; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(96, 106), @@ -114,8 +122,3 @@ struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(116, 133), #endif }; - -int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); -int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); -int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl); -int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index 1255898..9836588 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -24,6 +24,7 @@ #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> +#ifdef CONFIG_SYS_DPAA_QBMAN struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO( 1, 2, 1, 0), @@ -37,10 +38,13 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ }; +#endif struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN SET_QMAN_LIODN(31), SET_BMAN_LIODN(32), +#endif SET_SDHC_LIODN(1, 64), @@ -65,6 +69,7 @@ struct liodn_id_table liodn_tbl[] = { SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), }; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN struct liodn_id_table fman1_liodn_tbl[] = { @@ -75,6 +80,7 @@ struct liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 4, 14), SET_FMAN_RX_10G_LIODN(1, 0, 15), }; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #endif struct liodn_id_table sec_liodn_tbl[] = { @@ -89,6 +95,7 @@ struct liodn_id_table sec_liodn_tbl[] = { SET_SEC_DECO_LIODN_ENTRY(0, 97, 98), SET_SEC_DECO_LIODN_ENTRY(1, 99, 100), }; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), @@ -99,7 +106,3 @@ struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), #endif }; - -int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); -int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); -int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c index c014163..ecaa30d 100644 --- a/arch/powerpc/cpu/mpc85xx/portals.c +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -151,8 +151,10 @@ static int fdt_qportal(void *blob, int off, int id, char *name, dev_handle = fdt_get_phandle(blob, dev_off); if (dev_handle <= 0) { dev_handle = fdt_alloc_phandle(blob); - fdt_setprop_cell(blob, dev_off, - "linux,phandle", dev_handle); + ret = fdt_create_phandle(blob, dev_off, + dev_handle); + if (ret < 0) + return ret; } ret = fdt_setprop(blob, childoff, "dev-handle", diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 56a853e..6678ed4 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * Kumar Gala <kumar.gala@freescale.com> * * See file CREDITS for list of people who contributed to this @@ -144,6 +144,18 @@ __secondary_start_page: #endif #ifdef CONFIG_BACKSIDE_L2_CACHE + /* skip L2 setup on P2040/P2040E as they have no L2 */ + mfspr r2,SPRN_SVR + lis r3,SVR_P2040@h + ori r3,r3,SVR_P2040@l + cmpw r2,r3 + beq 3f + + lis r3,SVR_P2040_E@h + ori r3,r3,SVR_P2040_E@l + cmpw r2,r3 + beq 3f + /* Enable/invalidate the L2 cache */ msync lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h @@ -169,6 +181,7 @@ __secondary_start_page: andis. r1,r3,L2CSR0_L2E@h beq 2b #endif +3: #define EPAPR_MAGIC (0x45504150) #define ENTRY_ADDR_UPPER 0 diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 5777493..878a3d6 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -31,7 +31,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc85xx.h> -#include <timestamp.h> #include <version.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ @@ -42,10 +41,6 @@ #include <asm/cache.h> #include <asm/mmu.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - #undef MSR_KERNEL #define MSR_KERNEL ( MSR_ME ) /* Machine Check */ @@ -399,9 +394,7 @@ _start: .long 0x27051956 /* U-BOOT Magic Number */ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .align 4 .globl _start_cont @@ -683,6 +676,8 @@ mck_return: /* Cache functions. */ +.globl flush_icache +flush_icache: .globl invalidate_icache invalidate_icache: mfspr r0,L1CSR1 diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 295f175..01a3561 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -300,4 +300,33 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) return setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); } + +/* Invalidate the DDR TLBs for the requested size */ +void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) +{ + u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; + unsigned long epn; + u32 tsize, valid, ptr; + phys_addr_t rpn = 0; + int ddr_esel; + u64 memsize = (u64)memsize_in_meg << 20; + + ptr = vstart; + + while (ptr < (vstart + memsize)) { + ddr_esel = find_tlb_idx((void *)ptr, 1); + if (ddr_esel != -1) { + read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); + disable_tlb(ddr_esel); + } + ptr += TSIZE_TO_BYTES(tsize); + } +} + +void clear_ddr_tlbs(unsigned int memsize_in_meg) +{ + clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); +} + + #endif /* !CONFIG_NAND_SPL */ diff --git a/arch/powerpc/cpu/mpc86xx/start.S b/arch/powerpc/cpu/mpc86xx/start.S index 3e3c21e..32896d4 100644 --- a/arch/powerpc/cpu/mpc86xx/start.S +++ b/arch/powerpc/cpu/mpc86xx/start.S @@ -33,7 +33,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc86xx.h> -#include <timestamp.h> #include <version.h> #include <ppc_asm.tmpl> @@ -43,10 +42,6 @@ #include <asm/mmu.h> #include <asm/u-boot.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - /* * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions */ @@ -78,9 +73,7 @@ .long 0x27051956 /* U-Boot Magic Number */ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" . = EXC_OFF_SYS_RESET .globl _start diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c index 9514c66..9239b24 100644 --- a/arch/powerpc/cpu/mpc8xx/serial.c +++ b/arch/powerpc/cpu/mpc8xx/serial.c @@ -26,6 +26,7 @@ #include <command.h> #include <serial.h> #include <watchdog.h> +#include <linux/compiler.h> DECLARE_GLOBAL_DATA_PTR; @@ -390,7 +391,6 @@ smc_tstc(void) struct serial_device serial_smc_device = { "serial_smc", - "SMC", smc_init, NULL, smc_setbrg, @@ -661,7 +661,6 @@ scc_tstc(void) struct serial_device serial_scc_device = { "serial_scc", - "SCC", scc_init, NULL, scc_setbrg, @@ -673,6 +672,15 @@ struct serial_device serial_scc_device = #endif /* CONFIG_8xx_CONS_SCCx */ +__weak struct serial_device *default_serial_console(void) +{ +#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) + return &serial_smc_device; +#else + return &serial_scc_device; +#endif +} + #ifdef CONFIG_MODEM_SUPPORT void disable_putc(void) { @@ -692,7 +700,7 @@ kgdb_serial_init(void) { int i = -1; - if (strcmp(default_serial_console()->ctlr, "SMC") == 0) + if (strcmp(default_serial_console()->name, "serial_smc") == 0) { #if defined(CONFIG_8xx_CONS_SMC1) i = 1; @@ -700,7 +708,7 @@ kgdb_serial_init(void) i = 2; #endif } - else if (strcmp(default_serial_console()->ctlr, "SMC") == 0) + else if (strcmp(default_serial_console()->name, "serial_scc") == 0) { #if defined(CONFIG_8xx_CONS_SCC1) i = 1; @@ -715,7 +723,7 @@ kgdb_serial_init(void) if (i >= 0) { - serial_printf("[on %s%d] ", default_serial_console()->ctlr, i); + serial_printf("[on %s%d] ", default_serial_console()->name, i); } } diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index fe3daa2..ebca3ac 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -40,7 +40,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc8xx.h> -#include <timestamp.h> #include <version.h> #define CONFIG_8xx 1 /* needed for Linux kernel header files */ @@ -53,10 +52,6 @@ #include <asm/mmu.h> #include <asm/u-boot.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - /* We don't want the MMU yet. */ #undef MSR_KERNEL @@ -89,9 +84,7 @@ .long 0x27051956 /* U-Boot Magic Number */ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" . = EXC_OFF_SYS_RESET .globl _start diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c index c79c499..7725c67 100644 --- a/arch/powerpc/cpu/mpc8xx/video.c +++ b/arch/powerpc/cpu/mpc8xx/video.c @@ -33,7 +33,6 @@ #include <common.h> #include <config.h> #include <version.h> -#include <timestamp.h> #include <i2c.h> #include <linux/types.h> #include <stdio_dev.h> diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 39b304a..767bc52 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -79,7 +79,7 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P1016, P1016_E, 1), CPU_TYPE_ENTRY(P1016, P1016, 1), CPU_TYPE_ENTRY(P1017, P1017, 1), - CPU_TYPE_ENTRY(P1017, P1017, 1), + CPU_TYPE_ENTRY(P1017, P1017_E, 1), CPU_TYPE_ENTRY(P1020, P1020, 2), CPU_TYPE_ENTRY(P1020, P1020_E, 2), CPU_TYPE_ENTRY(P1021, P1021, 2), @@ -98,6 +98,8 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P2020, P2020_E, 2), CPU_TYPE_ENTRY(P2040, P2040, 4), CPU_TYPE_ENTRY(P2040, P2040_E, 4), + CPU_TYPE_ENTRY(P2041, P2041, 4), + CPU_TYPE_ENTRY(P2041, P2041_E, 4), CPU_TYPE_ENTRY(P3041, P3041, 4), CPU_TYPE_ENTRY(P3041, P3041_E, 4), CPU_TYPE_ENTRY(P4040, P4040, 4), diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile index 4a5a785..d1b4c4b 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile @@ -12,15 +12,24 @@ LIB = $(obj)libddr.o COBJS-$(CONFIG_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \ lc_common_dimm_params.o -COBJS-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o COBJS-$(CONFIG_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \ lc_common_dimm_params.o -COBJS-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o COBJS-$(CONFIG_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \ lc_common_dimm_params.o +ifdef CONFIG_DDR_SPD +SPD := y +endif +ifdef CONFIG_SPD_EEPROM +SPD := y +endif +ifdef SPD +COBJS-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o +COBJS-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o COBJS-$(CONFIG_FSL_DDR3) += ddr3_dimm_params.o +endif + SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 02d069c..3824aad 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -267,6 +267,9 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, tmrd_mclk = 2; #endif + if (popts->trwt_override) + trwt_mclk = popts->trwt; + ddr->timing_cfg_0 = (0 | ((trwt_mclk & 0x3) << 30) /* RWT */ | ((twrt_mclk & 0x3) << 28) /* WRT */ diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h index 1e866fe..f59aa33 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h @@ -14,6 +14,7 @@ #include "common_timing_params.h" +#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) /* * Bind the main DDR setup driver's generic names * to this specific DDR technology. @@ -25,6 +26,7 @@ compute_dimm_parameters(const generic_spd_eeprom_t *spd, { return ddr_compute_dimm_parameters(spd, pdimm, dimm_number); } +#endif /* * Data Structures @@ -80,4 +82,9 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo); extern unsigned int mclk_to_picos(unsigned int mclk); extern unsigned int get_memory_clk_period_ps(void); extern unsigned int picos_to_mclk(unsigned int picos); + +/* board specific function */ +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number); #endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index 756b15f..838cebe 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -114,7 +114,8 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * and copying the part name in ASCII from the SPD onto it */ memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); + if ((spd->info_size_crc & 0xF) > 1) + memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); /* DIMM organization parameters */ pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1; diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index c8fa123..249fd7d 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -174,7 +174,19 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo, switch (pinfo->memctl_opts[i].data_bus_width) { case 2: /* 16-bit */ - printf("can't handle 16-bit mode yet\n"); + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + unsigned int dw; + if (!pinfo->dimm_params[i][j].n_ranks) + continue; + dw = pinfo->dimm_params[i][j].primary_sdram_width; + if ((dw == 72 || dw == 64)) { + dbw_cap_adj[i] = 2; + break; + } else if ((dw == 40 || dw == 32)) { + dbw_cap_adj[i] = 1; + break; + } + } break; case 1: @@ -313,6 +325,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, switch (start_step) { case STEP_GET_SPD: +#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) /* STEP 1: Gather all DIMM SPD data */ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i); @@ -330,12 +343,20 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, &(pinfo->dimm_params[i][j]); retval = compute_dimm_parameters(spd, pdimm, i); +#ifdef CONFIG_SYS_DDR_RAW_TIMING + if (retval != 0) { + printf("SPD error! Trying fallback to " + "raw timing calculation\n"); + fsl_ddr_get_dimm_params(pdimm, i, j); + } +#else if (retval == 2) { printf("Error: compute_dimm_parameters" " non-zero returned FATAL value " "for memctl=%u dimm=%u\n", i, j); return 0; } +#endif if (retval) { debug("Warning: compute_dimm_parameters" " non-zero return value for memctl=%u " @@ -344,6 +365,17 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, } } +#else + case STEP_COMPUTE_DIMM_PARMS: + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + dimm_params_t *pdimm = + &(pinfo->dimm_params[i][j]); + fsl_ddr_get_dimm_params(pdimm, i, j); + } + } + debug("Filling dimm parameters from board specific file\n"); +#endif case STEP_COMPUTE_COMMON_PARMS: /* * STEP 3: Compute a common set of timing parameters diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 6ccc3b0..bd9c466 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -418,8 +418,38 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, /* Choose dynamic power management mode. */ popts->dynamic_power = 0; - /* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */ - popts->data_bus_width = 0; + /* + * check first dimm for primary sdram width + * presuming all dimms are similar + * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit + */ +#if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2) + if (pdimm[0].n_ranks != 0) { + if ((pdimm[0].data_width >= 64) && \ + (pdimm[0].data_width <= 72)) + popts->data_bus_width = 0; + else if ((pdimm[0].data_width >= 32) || \ + (pdimm[0].data_width <= 40)) + popts->data_bus_width = 1; + else { + panic("Error: data width %u is invalid!\n", + pdimm[0].data_width); + } + } +#else + if (pdimm[0].n_ranks != 0) { + if (pdimm[0].primary_sdram_width == 64) + popts->data_bus_width = 0; + else if (pdimm[0].primary_sdram_width == 32) + popts->data_bus_width = 1; + else if (pdimm[0].primary_sdram_width == 16) + popts->data_bus_width = 2; + else { + panic("Error: primary sdram width %u is invalid!\n", + pdimm[0].primary_sdram_width); + } + } +#endif /* Choose burst length. */ #if defined(CONFIG_FSL_DDR3) @@ -427,8 +457,14 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */ popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ #else - popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */ - popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ + if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) { + /* 32-bit or 16-bit bus */ + popts->OTF_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + } else { + popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */ + popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ + } #endif #else popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */ diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 520cb90..285051d 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -29,6 +29,9 @@ #include <asm/mp.h> #include <asm/fsl_serdes.h> #include <phy.h> +#include <hwconfig.h> + +#define FSL_MAX_NUM_USB_CTRLS 2 #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) @@ -84,22 +87,18 @@ void ft_fixup_num_cores(void *blob) { #endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */ #ifdef CONFIG_HAS_FSL_DR_USB -void fdt_fixup_dr_usb(void *blob, bd_t *bd) +static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, + const char *phy_type) { - char *mode; - char *type; const char *compat = "fsl-usb2-dr"; const char *prop_mode = "dr_mode"; const char *prop_type = "phy_type"; + static int start_offset = -1; int node_offset; int err; - mode = getenv("usb_dr_mode"); - type = getenv("usb_phy_type"); - if (!mode && !type) - return; - - node_offset = fdt_node_offset_by_compatible(blob, 0, compat); + node_offset = fdt_node_offset_by_compatible(blob, + start_offset, compat); if (node_offset < 0) { printf("WARNING: could not find compatible node %s: %s.\n", compat, fdt_strerror(node_offset)); @@ -114,13 +113,64 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) prop_mode, compat, fdt_strerror(err)); } - if (type) { - err = fdt_setprop(blob, node_offset, prop_type, type, - strlen(type) + 1); + if (phy_type) { + err = fdt_setprop(blob, node_offset, prop_type, phy_type, + strlen(phy_type) + 1); if (err < 0) printf("WARNING: could not set %s for %s: %s.\n", prop_type, compat, fdt_strerror(err)); } + + start_offset = node_offset; +} + +void fdt_fixup_dr_usb(void *blob, bd_t *bd) +{ + const char *modes[] = { "host", "peripheral", "otg" }; + const char *phys[] = { "ulpi", "umti" }; + const char *mode = NULL; + const char *phy_type = NULL; + char usb1_defined = 0; + char str[5]; + int i, j; + + for (i = 1; i <= FSL_MAX_NUM_USB_CTRLS; i++) { + int mode_idx = -1, phy_idx = -1; + sprintf(str, "%s%d", "usb", i); + if (hwconfig(str)) { + for (j = 0; j < sizeof(modes); j++) { + if (hwconfig_subarg_cmp(str, "dr_mode", + modes[j])) { + mode_idx = j; + break; + } + } + for (j = 0; j < sizeof(phys); j++) { + if (hwconfig_subarg_cmp(str, "phy_type", + phys[j])) { + phy_idx = j; + break; + } + } + if (mode_idx >= 0) + fdt_fixup_usb_mode_phy_type(blob, + modes[mode_idx], NULL); + if (phy_idx >= 0) + fdt_fixup_usb_mode_phy_type(blob, + NULL, phys[phy_idx]); + if (!strcmp(str, "usb1")) + usb1_defined = 1; + if (mode_idx < 0 && phy_idx < 0) + printf("WARNING: invalid phy or mode\n"); + } + } + if (!usb1_defined) { + mode = getenv("usb_dr_mode"); + phy_type = getenv("usb_phy_type"); + if (!mode && !phy_type) + return; + fdt_fixup_usb_mode_phy_type(blob, mode, phy_type); + } } #endif /* CONFIG_HAS_FSL_DR_USB */ diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index 7598ebf..d78962f 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -58,8 +58,10 @@ void init_early_memctl_regs(void) #endif /* now restrict to preliminary range */ if (init_br1) { +#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM) set_lbc_br(0, CONFIG_SYS_BR0_PRELIM); set_lbc_or(0, CONFIG_SYS_OR0_PRELIM); +#endif #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) set_lbc_or(1, CONFIG_SYS_OR1_PRELIM); diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index b43e22c..3b0e364 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -68,7 +68,6 @@ #include <asm-offsets.h> #include <config.h> #include <asm/ppc4xx.h> -#include <timestamp.h> #include <version.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ @@ -80,10 +79,6 @@ #include <asm/mmu.h> #include <asm/ppc4xx-isram.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - #ifdef CONFIG_SYS_INIT_DCACHE_CS # if (CONFIG_SYS_INIT_DCACHE_CS == 0) # define PBxAP PB1AP @@ -549,9 +544,7 @@ tlbnx2: addi r4,r4,1 /* Next TLB */ .long 0x27051956 /* U-Boot Magic Number */ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" . = EXC_OFF_SYS_RESET .globl _start_of_vectors diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index d5c0aee..04ca989 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -273,6 +273,22 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#elif defined(CONFIG_PPC_P2041) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 diff --git a/arch/powerpc/include/asm/cpm_8260.h b/arch/powerpc/include/asm/cpm_8260.h index 8302404..6a4a51a 100644 --- a/arch/powerpc/include/asm/cpm_8260.h +++ b/arch/powerpc/include/asm/cpm_8260.h @@ -117,7 +117,7 @@ typedef struct cpm_buf_desc { uint cbd_bufaddr; /* Buffer address in host memory */ } cbd_t; -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h index a74a3a1..1681ecd 100644 --- a/arch/powerpc/include/asm/cpm_85xx.h +++ b/arch/powerpc/include/asm/cpm_85xx.h @@ -110,7 +110,7 @@ typedef struct cpm_buf_desc { uint cbd_bufaddr; /* Buffer address in host memory */ } cbd_t; -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 127a840..bc063ea 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -181,6 +181,9 @@ typedef struct memctl_options_partial_s { unsigned int all_DIMMs_minimum_tRCD_ps; } memctl_options_partial_t; +#define DDR_DATA_BUS_WIDTH_64 0 +#define DDR_DATA_BUS_WIDTH_32 1 +#define DDR_DATA_BUS_WIDTH_16 2 /* * Generalized parameters for memory controller configuration, * might be a little specific to the FSL memory controller @@ -268,6 +271,9 @@ typedef struct memctl_options_s { unsigned int rcw_2; /* control register 1 */ unsigned int ddr_cdr1; + + unsigned int trwt_override; + unsigned int trwt; /* read-to-write turnaround */ } memctl_options_t; extern phys_size_t fsl_ddr_sdram(void); diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index f85cee2..6aaade0 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1759,7 +1759,8 @@ typedef struct ccsr_gur { u32 cgencrl; /* Core general control */ u8 res31[184]; u32 sriopstecr; /* SRIO prescaler timer enable control */ - u8 res32[1788]; + u32 dcsrcr; /* DCSR Control register */ + u8 res32[1784]; u32 pmuxcr; /* Pin multiplexing control */ u8 res33[60]; u32 iovselsr; /* I/O voltage selection status */ @@ -1772,6 +1773,10 @@ typedef struct ccsr_gur { u8 res37[380]; } ccsr_gur_t; +#define FSL_CORENET_DCSR_SZ_MASK 0x00000003 +#define FSL_CORENET_DCSR_SZ_4M 0x0 +#define FSL_CORENET_DCSR_SZ_1G 0x3 + /* * On p4080 we have an LIODN for msg unit (rmu) but not maintenance * everything after has RMan thus msg unit LIODN is used for maintenance @@ -2017,7 +2022,7 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000 #endif #if defined(CONFIG_P1013) || defined(CONFIG_P1022) -#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f1000 +#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000 #define MPC85xx_PMUXCR2_USB 0x00150000 #endif u8 res6[8]; diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index c01c85f..ef5076b 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -489,6 +489,7 @@ extern int find_free_tlbcam(void); extern void print_tlbcam(void); extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); +extern void clear_ddr_tlbs(unsigned int memsize_in_meg); extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7); diff --git a/arch/powerpc/include/asm/ppc440ep_gr.h b/arch/powerpc/include/asm/ppc440ep_gr.h index dfd1532..e790963 100644 --- a/arch/powerpc/include/asm/ppc440ep_gr.h +++ b/arch/powerpc/include/asm/ppc440ep_gr.h @@ -182,7 +182,7 @@ #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ -#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */ #define PRADV_MASK 0x07000000 /* Primary Divisor A */ #define PRBDV_MASK 0x07000000 /* Primary Divisor B */ #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ @@ -192,7 +192,7 @@ #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ -#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */ #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ diff --git a/arch/powerpc/include/asm/ppc440epx_grx.h b/arch/powerpc/include/asm/ppc440epx_grx.h index 6c21472..c841f0f 100644 --- a/arch/powerpc/include/asm/ppc440epx_grx.h +++ b/arch/powerpc/include/asm/ppc440epx_grx.h @@ -398,7 +398,7 @@ #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ -#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */ #define PRADV_MASK 0x07000000 /* Primary Divisor A */ #define PRBDV_MASK 0x07000000 /* Primary Divisor B */ #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ @@ -408,7 +408,7 @@ #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ -#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */ #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ diff --git a/arch/powerpc/include/asm/ppc440gx.h b/arch/powerpc/include/asm/ppc440gx.h index 6f8581b..9924525 100644 --- a/arch/powerpc/include/asm/ppc440gx.h +++ b/arch/powerpc/include/asm/ppc440gx.h @@ -71,7 +71,7 @@ #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ -#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */ #define PRADV_MASK 0x07000000 /* Primary Divisor A */ #define PRBDV_MASK 0x07000000 /* Primary Divisor B */ #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ @@ -81,7 +81,7 @@ #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ -#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */ #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ diff --git a/arch/powerpc/include/asm/ppc440sp.h b/arch/powerpc/include/asm/ppc440sp.h index 4387495..cc2ff68 100644 --- a/arch/powerpc/include/asm/ppc440sp.h +++ b/arch/powerpc/include/asm/ppc440sp.h @@ -67,7 +67,7 @@ #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ -#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */ #define PRADV_MASK 0x07000000 /* Primary Divisor A */ #define PRBDV_MASK 0x07000000 /* Primary Divisor B */ #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ @@ -77,7 +77,7 @@ #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ -#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */ #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ diff --git a/arch/powerpc/include/asm/ppc440spe.h b/arch/powerpc/include/asm/ppc440spe.h index bad9a40..d59d7d2 100644 --- a/arch/powerpc/include/asm/ppc440spe.h +++ b/arch/powerpc/include/asm/ppc440spe.h @@ -83,7 +83,7 @@ #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ -#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */ #define PRADV_MASK 0x07000000 /* Primary Divisor A */ #define PRBDV_MASK 0x07000000 /* Primary Divisor B */ #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ @@ -93,7 +93,7 @@ #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ -#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */ #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index c5b03b4..0c4cc25 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -938,6 +938,10 @@ #define PVR_85xx 0x80200000 #define PVR_85xx_REV1 (PVR_85xx | 0x0010) #define PVR_85xx_REV2 (PVR_85xx | 0x0020) +#define PVR_VER_E500_V1 0x8020 +#define PVR_VER_E500_V2 0x8021 +#define PVR_VER_E500MC 0x8023 +#define PVR_VER_E5500 0x8024 #define PVR_86xx 0x80040000 @@ -1103,6 +1107,8 @@ #define SVR_P2020_E 0x80EA00 #define SVR_P2040 0x821000 #define SVR_P2040_E 0x821800 +#define SVR_P2041 0x821001 +#define SVR_P2041_E 0x821801 #define SVR_P3041 0x821103 #define SVR_P3041_E 0x821903 #define SVR_P4040 0x820100 diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index aaa5add..22bbc52 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -932,8 +932,6 @@ void board_init_r (gd_t *id, ulong dest_addr) udelay (20); - set_timer (0); - /* Initialize from environment */ if ((s = getenv ("loadaddr")) != NULL) { load_addr = simple_strtoul (s, NULL, 16); diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index e01787d..1375474 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -87,7 +87,7 @@ static void boot_jump_linux(bootm_headers_t *images) * r8: 0 * r9: 0 */ -#if defined(CONFIG_85xx) || defined(CONFIG_440) +#if defined(CONFIG_MPC85xx) || defined(CONFIG_440) #define EPAPR_MAGIC (0x45504150) #else #define EPAPR_MAGIC (0x65504150) @@ -226,6 +226,24 @@ static int boot_bd_t_linux(bootm_headers_t *images) return ret; } +/* + * Verify the device tree. + * + * This function is called after all device tree fix-ups have been enacted, + * so that the final device tree can be verified. The definition of "verified" + * is up to the specific implementation. However, it generally means that the + * addresses of some of the devices in the device tree are compared with the + * actual addresses at which U-Boot has placed them. + * + * Returns 1 on success, 0 on failure. If 0 is returned, U-boot will halt the + * boot process. + */ +static int __ft_verify_fdt(void *fdt) +{ + return 1; +} +__attribute__((weak, alias("__ft_verify_fdt"))) int ft_verify_fdt(void *fdt); + static int boot_body_linux(bootm_headers_t *images) { ulong rd_len; @@ -288,14 +306,19 @@ static int boot_body_linux(bootm_headers_t *images) return ret; of_size = ret; - if (*initrd_start && *initrd_end) + if (*initrd_start && *initrd_end) { of_size += FDT_RAMDISK_OVERHEAD; + fdt_set_totalsize(*of_flat_tree, of_size); + } /* Create a new LMB reservation */ lmb_reserve(lmb, (ulong)*of_flat_tree, of_size); /* fixup the initrd now that we know where it should be */ if (*initrd_start && *initrd_end) fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1); + + if (!ft_verify_fdt(*of_flat_tree)) + return -1; } #endif /* CONFIG_OF_LIBFDT */ return 0; diff --git a/arch/powerpc/lib/interrupts.c b/arch/powerpc/lib/interrupts.c index f603170..aeae413 100644 --- a/arch/powerpc/lib/interrupts.c +++ b/arch/powerpc/lib/interrupts.c @@ -137,17 +137,7 @@ void timer_interrupt (struct pt_regs *regs) #endif /* CONFIG_SHOW_ACTIVITY */ } -void reset_timer (void) -{ - timestamp = 0; -} - ulong get_timer (ulong base) { return (timestamp - base); } - -void set_timer (ulong t) -{ - timestamp = t; -} diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index ed91643..90fe796 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -22,7 +22,6 @@ #include <command.h> #include <malloc.h> #include <stdio_dev.h> -#include <timestamp.h> #include <version.h> #include <watchdog.h> #include <net.h> @@ -39,8 +38,6 @@ extern int board_init(void); extern int dram_init(void); extern int timer_init(void); -const char version_string[] = U_BOOT_VERSION" ("U_BOOT_DATE" - "U_BOOT_TIME")"; - unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; #ifndef CONFIG_SYS_NO_FLASH diff --git a/arch/sh/lib/time.c b/arch/sh/lib/time.c index bc1656f..c70baed 100644 --- a/arch/sh/lib/time.c +++ b/arch/sh/lib/time.c @@ -139,18 +139,6 @@ unsigned long get_timer (unsigned long base) return tick_to_time(get_ticks()) - base; } -void set_timer (unsigned long t) -{ - writel((0 - t), TCNT0); -} - -void reset_timer (void) -{ - tmu_timer_stop(0); - set_timer (0); - tmu_timer_start(0); -} - unsigned long get_tbclk (void) { return timer_freq; diff --git a/arch/sh/lib/time_sh2.c b/arch/sh/lib/time_sh2.c index 789b46f..5827118 100644 --- a/arch/sh/lib/time_sh2.c +++ b/arch/sh/lib/time_sh2.c @@ -54,7 +54,7 @@ int timer_init(void) /* User Device 0 only */ cmt_timer_stop(0); - set_timer(CMT_TIMER_RESET); + writew(CMT_TIMER_RESET, CMCOR_0); cmt_timer_start(0); return 0; @@ -90,19 +90,6 @@ ulong get_timer(ulong base) return (get_usec() / 1000) - base; } -void set_timer(ulong t) -{ - writew((u16) t, CMCOR_0); -} - -void reset_timer(void) -{ - cmt_timer_stop(0); - set_timer(CMT_TIMER_RESET); - cmt0_timer = 0; - cmt_timer_start(0); -} - void __udelay(unsigned long usec) { unsigned long end = get_usec() + usec; diff --git a/arch/sparc/cpu/leon2/start.S b/arch/sparc/cpu/leon2/start.S index f22fb7e..9cd6c66 100644 --- a/arch/sparc/cpu/leon2/start.S +++ b/arch/sparc/cpu/leon2/start.S @@ -28,7 +28,6 @@ #include <asm/psr.h> #include <asm/stack.h> #include <asm/leon.h> -#include <timestamp.h> #include <version.h> /* Entry for traps which jump to a programmer-specified trap handler. */ @@ -200,9 +199,7 @@ _trap_table: .data .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .section ".text" .align 4 diff --git a/arch/sparc/cpu/leon3/start.S b/arch/sparc/cpu/leon3/start.S index 56ae88d..1e393a5 100644 --- a/arch/sparc/cpu/leon3/start.S +++ b/arch/sparc/cpu/leon3/start.S @@ -28,7 +28,6 @@ #include <asm/psr.h> #include <asm/stack.h> #include <asm/leon.h> -#include <timestamp.h> #include <version.h> /* Entry for traps which jump to a programmer-specified trap handler. */ @@ -201,9 +200,7 @@ _trap_table: .extern leon3_snooping_avail .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .section ".text" .align 4 diff --git a/arch/sparc/cpu/leon3/usb_uhci.c b/arch/sparc/cpu/leon3/usb_uhci.c index 8f99e1d..b1269d2 100644 --- a/arch/sparc/cpu/leon3/usb_uhci.c +++ b/arch/sparc/cpu/leon3/usb_uhci.c @@ -70,7 +70,7 @@ * * Interrupt Transfers. * -------------------- - * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They + * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They * will be inserted after the appropriate (depending the interval setting) skeleton TD. * If an interrupt has been detected the dev->irqhandler is called. The status and number * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c index 386cd04..6b705e5 100644 --- a/arch/sparc/lib/board.c +++ b/arch/sparc/lib/board.c @@ -365,8 +365,6 @@ void board_init_f(ulong bootflag) udelay(20); - set_timer(0); - /* Initialize from environment */ if ((s = getenv("loadaddr")) != NULL) { load_addr = simple_strtoul(s, NULL, 16); diff --git a/arch/sparc/lib/interrupts.c b/arch/sparc/lib/interrupts.c index 4c73b82..61ee90b 100644 --- a/arch/sparc/lib/interrupts.c +++ b/arch/sparc/lib/interrupts.c @@ -90,26 +90,16 @@ void timer_interrupt(struct pt_regs *regs) timestamp++; } -void reset_timer(void) -{ - timestamp = 0; -} - ulong get_timer(ulong base) { return (timestamp - base); } -void set_timer(ulong t) -{ - timestamp = t; -} - void timer_interrupt_init(void) { int irq; - reset_timer(); + timestamp = 0; irq = timer_interrupt_init_cpu(); diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 7ccc076..6c84c43 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -66,7 +66,7 @@ _start: movw %ax, %es movw %ax, %ss - /* Clear the interupt vectors */ + /* Clear the interrupt vectors */ lidt blank_idt_ptr /* Early platform init (setup gpio, etc ) */ diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h index be52fe4..f33f8ed 100644 --- a/arch/x86/include/asm/interrupt.h +++ b/arch/x86/include/asm/interrupt.h @@ -32,7 +32,7 @@ /* arch/x86/cpu/interrupts.c */ void set_vector(u8 intnum, void *routine); -/* arch/x86/lib/interupts.c */ +/* arch/x86/lib/interrupts.c */ void disable_irq(int irq); void enable_irq(int irq); diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 944e1a2..4f0d2c7 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -36,7 +36,6 @@ typedef void (timer_fnc_t) (void); int register_timer_isr (timer_fnc_t *isr_func); /* Architecture specific - can be in arch/x86/cpu/, arch/x86/lib/, or $(BOARD)/ */ -int timer_init(void); int dram_init_f(void); /* cpu/.../interrupts.c */ diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c index df54222..af375dd 100644 --- a/arch/x86/lib/board.c +++ b/arch/x86/lib/board.c @@ -35,7 +35,6 @@ #include <watchdog.h> #include <command.h> #include <stdio_dev.h> -#include <timestamp.h> #include <version.h> #include <malloc.h> #include <net.h> @@ -66,9 +65,6 @@ extern ulong __rel_dyn_end; extern ulong __bss_start; extern ulong __bss_end; -const char version_string[] = - U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"; - /************************************************************************ * Init Utilities * ************************************************************************ @@ -363,8 +359,6 @@ void board_init_r(gd_t *id, ulong dest_addr) udelay(20); - set_timer (0); - /* Initialize from environment */ if ((s = getenv ("loadaddr")) != NULL) { load_addr = simple_strtoul (s, NULL, 16); diff --git a/arch/x86/lib/timer.c b/arch/x86/lib/timer.c index 8fc68cd..a822d66 100644 --- a/arch/x86/lib/timer.c +++ b/arch/x86/lib/timer.c @@ -94,17 +94,7 @@ void timer_isr(void *unused) } } -void reset_timer (void) -{ - system_ticks = 0; -} - ulong get_timer (ulong base) { return (system_ticks - base); } - -void set_timer (ulong t) -{ - system_ticks = t; -} diff --git a/board/BuS/EB+MCF-EV123/flash.c b/board/BuS/EB+MCF-EV123/flash.c index 3c36367..8b7f957 100644 --- a/board/BuS/EB+MCF-EV123/flash.c +++ b/board/BuS/EB+MCF-EV123/flash.c @@ -157,6 +157,7 @@ int amd_flash_erase_sector(flash_info_t * info, int sector) { int state; ulong result; + ulong start; volatile u16 *addr = (volatile u16 *) (info->start[sector]); @@ -171,13 +172,13 @@ int amd_flash_erase_sector(flash_info_t * info, int sector) /* wait until flash is ready */ state = 0; - set_timer (0); + start = get_timer(0); do { result = *addr; /* check timeout */ - if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; state = ERR_TIMOUT; } @@ -267,6 +268,7 @@ volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data) ulong result; int cflag, iflag; int state; + ulong start; /* * Check if Flash is (sufficiently) erased @@ -295,7 +297,7 @@ volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data) *addr = data; /* arm simple, non interrupt dependent timer */ - set_timer (0); + start = get_timer(0); /* wait until flash is ready */ state = 0; @@ -303,7 +305,7 @@ volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data) result = *addr; /* check timeout */ - if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { state = ERR_TIMOUT; } if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK))) diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c index fe62a0f..856d798 100644 --- a/board/BuS/eb_cpux9k2/cpux9k2.c +++ b/board/BuS/eb_cpux9k2/cpux9k2.c @@ -33,6 +33,7 @@ #include <asm/arch/at91_pio.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_mc.h> +#include <asm/arch/at91_common.h> #ifdef CONFIG_STATUS_LED #include <status_led.h> @@ -57,12 +58,12 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; /* Enable Ctrlc */ console_init_f(); /* Correct IRDA resistor problem / Set PA23_TXD in Output */ - writel(AT91_PMX_AA_TXD2, &pio->pioa.oer); + writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer); gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2; /* adress of boot parameters */ @@ -77,6 +78,12 @@ int board_init(void) return 0; } +int board_early_init_f(void) +{ + at91_seriald_hw_init(); + return 0; +} + #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) @@ -134,7 +141,7 @@ void reset_phy(void) int dram_init(void) { - gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); return 0; } @@ -147,7 +154,7 @@ int dram_init(void) int board_eth_init(bd_t *bis) { int rc = 0; - rc = at91emac_register(bis, (u32) AT91_EMAC_BASE); + rc = at91emac_register(bis, (u32) ATMEL_BASE_EMAC); return rc; } #endif @@ -164,9 +171,9 @@ int board_eth_init(bd_t *bis) void cpux9k2_nand_hw_init(void) { unsigned long csr; - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_mc_t *mc = (at91_mc_t *) AT91_MC_BASE; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_mc_t *mc = (at91_mc_t *) ATMEL_BASE_MC; /* Setup Smart Media, fitst enable the address range of CS3 */ writel(readl(&mc->ebi.csa) | AT91_EBI_CSA_CS3A, &mc->ebi.csa); @@ -178,23 +185,23 @@ void cpux9k2_nand_hw_init(void) AT91_SMC_CSR_WSEN; writel(csr, &mc->smc.csr[3]); - writel(AT91_PMX_CA_SMOE | AT91_PMX_CA_SMWE, &pio->pioc.asr); - writel(AT91_PMX_CA_BFCK | AT91_PMX_CA_SMOE | AT91_PMX_CA_SMWE, + writel(ATMEL_PMX_CA_SMOE | ATMEL_PMX_CA_SMWE, &pio->pioc.asr); + writel(ATMEL_PMX_CA_BFCK | ATMEL_PMX_CA_SMOE | ATMEL_PMX_CA_SMWE, &pio->pioc.pdr); /* Configure PC2 as input (signal Nand READY ) */ - writel(AT91_PMX_CA_BFAVD, &pio->pioc.per); - writel(AT91_PMX_CA_BFAVD, &pio->pioc.odr); /* disable output */ - writel(AT91_PMX_CA_BFCK, &pio->pioc.codr); + writel(ATMEL_PMX_CA_BFAVD, &pio->pioc.per); + writel(ATMEL_PMX_CA_BFAVD, &pio->pioc.odr); /* disable output */ + writel(ATMEL_PMX_CA_BFCK, &pio->pioc.codr); /* PIOC clock enabling */ - writel(1 << AT91_ID_PIOC, &pmc->pcer); + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); } static void board_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; struct nand_chip *this = mtd->priv; ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; @@ -219,7 +226,7 @@ static void board_nand_hwcontrol(struct mtd_info *mtd, static int board_nand_dev_ready(struct mtd_info *mtd) { - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; return ((readl(&pio->pioc.pdsr) & (1 << 2)) != 0); } @@ -248,8 +255,8 @@ int drv_video_init(void) #endif char *s; unsigned long csr; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_mc_t *mc = (at91_mc_t *) AT91_MC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_mc_t *mc = (at91_mc_t *) ATMEL_BASE_MC; printf("Init Video as "); s = getenv("displaywidth"); @@ -270,7 +277,7 @@ int drv_video_init(void) AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 | AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN; writel(csr, &mc->smc.csr[2]); - writel(1 << AT91_ID_PIOB, &pmc->pcer); + writel(1 << ATMEL_ID_PIOB, &pmc->pcer); vcxk_init(display_width, display_height); #ifdef CONFIG_SPLASH_SCREEN @@ -290,11 +297,11 @@ int drv_video_init(void) void i2c_init_board(void) { u32 pin; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - writel(1 << AT91_ID_PIOA, &pmc->pcer); - pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; + writel(1 << ATMEL_ID_PIOA, &pmc->pcer); + pin = ATMEL_PMX_AA_TWD | ATMEL_PMX_AA_TWCK; writel(pin, &pio->pioa.idr); writel(pin, &pio->pioa.pudr); writel(pin, &pio->pioa.per); @@ -310,7 +317,7 @@ void i2c_init_board(void) void __led_toggle(led_id_t mask) { - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; if (readl(&pio->piod.odsr) & mask) writel(mask, &pio->piod.codr); @@ -320,10 +327,10 @@ void __led_toggle(led_id_t mask) void __led_init(led_id_t mask, int state) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - writel(1 << AT91_ID_PIOD, &pmc->pcer); /* Enable PIOB clock */ + writel(1 << ATMEL_ID_PIOD, &pmc->pcer); /* Enable PIOB clock */ /* Disable peripherals on LEDs */ writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.per); /* Enable pins as outputs */ @@ -336,7 +343,7 @@ void __led_init(led_id_t mask, int state) void __led_set(led_id_t mask, int state) { - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; if (state == STATUS_LED_ON) writel(mask, &pio->piod.codr); else diff --git a/board/LaCie/netspace_v2/Makefile b/board/LaCie/netspace_v2/Makefile new file mode 100644 index 0000000..a245f2c --- /dev/null +++ b/board/LaCie/netspace_v2/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := netspace_v2.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/LaCie/netspace_v2/kwbimage.cfg b/board/LaCie/netspace_v2/kwbimage.cfg new file mode 100644 index 0000000..361feeb --- /dev/null +++ b/board/LaCie/netspace_v2/kwbimage.cfg @@ -0,0 +1,162 @@ +# +# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1B1B1B9B + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000618 # DDR Configuration register +# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x35143000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x0000CCCC # DDR Address Control +# bit1-0: 01, Cs0width=x16 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs2width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000632 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000004 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 1, DDR drive strenght reduced +# bit2: 1, DDR ODT control lsd enabled +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, enabled +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F07F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 1 , D2P Latency enabled +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x07, Size (i.e. 128MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control +# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 +# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0 +# bit11-10:1, DQ_ODTSel. ODT select turned on + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c new file mode 100644 index 0000000..3bb83f3 --- /dev/null +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <miiphy.h> +#include <netdev.h> +#include <command.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include <asm/arch/gpio.h> +#include "netspace_v2.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* Gpio configuration */ + kw_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH, + NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_SPI_SCn, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, /* Fan speed (bit 1) */ + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, /* Red led */ + MPP14_GPIO, /* USB fuse */ + MPP16_GPIO, /* SATA 0 power */ + MPP17_GPIO, /* SATA 1 power */ + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_SATA1_ACTn, + MPP21_SATA0_ACTn, + MPP22_GPIO, /* Fan speed (bit 0) */ + MPP23_GPIO, /* Fan power */ + MPP24_GPIO, /* USB mode select */ + MPP25_GPIO, /* Fan rotation fail */ + MPP26_GPIO, /* USB vbus-in detection */ + MPP28_GPIO, /* USB enable vbus-out */ + MPP29_GPIO, /* Blue led (slow register) */ + MPP30_GPIO, /* Blue led (command register) */ + MPP31_GPIO, /* Board power off */ + MPP32_GPIO, /* Button (0 = Released, 1 = Pushed) */ + MPP33_GPIO, /* Fan speed (bit 2) */ + 0 + }; + kirkwood_mpp_conf(kwmpp_config); + + return 0; +} + +int board_init(void) +{ + /* Machine number */ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + + /* Boot parameters address */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} + +void mv_phy_88e1116_init(char *name) +{ + u16 reg; + u16 devadr; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..(%s) could not read PHY dev address\n", __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + if (miiphy_read(name, devadr, MII_BMCR, ®) != 0) { + printf("Err..(%s) PHY status read failed\n", __func__); + return; + } + if (miiphy_write(name, devadr, MII_BMCR, reg | 0x8000) != 0) { + printf("Err..(%s) PHY reset failed\n", __func__); + return; + } + + debug("88E1116 Initialized on %s\n", name); +} + +/* Configure and initialize PHY */ +void reset_phy(void) +{ + mv_phy_88e1116_init("egiga0"); +} + +/* Return GPIO button status */ +static int +do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + return kw_gpio_get_value(NETSPACE_V2_GPIO_BUTTON); +} + +U_BOOT_CMD(button, 1, 1, do_read_button, + "Return GPIO button status 0=off 1=on", ""); diff --git a/board/LaCie/netspace_v2/netspace_v2.h b/board/LaCie/netspace_v2/netspace_v2.h new file mode 100644 index 0000000..3f3d51c --- /dev/null +++ b/board/LaCie/netspace_v2/netspace_v2.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef NETSPACE_V2_H +#define NETSPACE_V2_H + +/* GPIO configuration */ +#define NETSPACE_V2_OE_LOW 0x06004000 +#define NETSPACE_V2_OE_HIGH 0x00000031 +#define NETSPACE_V2_OE_VAL_LOW 0x10030000 +#define NETSPACE_V2_OE_VAL_HIGH 0x00000000 + +#define NETSPACE_V2_GPIO_BUTTON 32 + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* NETSPACE_V2_H */ diff --git a/board/Marvell/common/bootseq.txt b/board/Marvell/common/bootseq.txt index e4fefb3..6cae9ea 100644 --- a/board/Marvell/common/bootseq.txt +++ b/board/Marvell/common/bootseq.txt @@ -62,7 +62,7 @@ in_flash: remap gt regs? map PCI mem/io map device space - clear out interupts + clear out interrupts init_timebase env_init serial_init diff --git a/board/Marvell/common/i2c.c b/board/Marvell/common/i2c.c index 8d87b2d..d53495c 100644 --- a/board/Marvell/common/i2c.c +++ b/board/Marvell/common/i2c.c @@ -420,7 +420,7 @@ i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data, status = i2c_get_data (data, len); if (status) { #ifdef DEBUG_I2C - printf ("Data not recieved: 0x%02x\n", status); + printf ("Data not received: 0x%02x\n", status); #endif return status; } diff --git a/board/Marvell/common/ns16550.h b/board/Marvell/common/ns16550.h index 0a2951b..9306381 100644 --- a/board/Marvell/common/ns16550.h +++ b/board/Marvell/common/ns16550.h @@ -51,7 +51,7 @@ struct NS16550 #define dlm ier #define FCR_FIFO_EN 0x01 /*fifo enable*/ -#define FCR_RXSR 0x02 /*reciever soft reset*/ +#define FCR_RXSR 0x02 /*receiver soft reset*/ #define FCR_TXSR 0x04 /*transmitter soft reset*/ diff --git a/board/Marvell/include/mv_gen_reg.h b/board/Marvell/include/mv_gen_reg.h index 5e4f076..03fcd88 100644 --- a/board/Marvell/include/mv_gen_reg.h +++ b/board/Marvell/include/mv_gen_reg.h @@ -2237,7 +2237,7 @@ #define CHANNEL2_REGISTER10 0x9070 #define CHANNEL2_REGISTER11 0x9074 -/* MPSCs Interupts */ +/* MPSCs Interrupts */ #define MPSC0_CAUSE 0xb824 #define MPSC0_MASK 0xb8a4 diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c index 85e3f9e..2f631b7 100644 --- a/board/actux1/actux1.c +++ b/board/actux1/actux1.c @@ -37,49 +37,57 @@ #include <asm/arch/ixp425.h> #include <asm/io.h> #include <miiphy.h> +#ifdef CONFIG_PCI +#include <pci.h> +#include <asm/arch/ixp425pci.h> +#endif #include "actux1_hw.h" DECLARE_GLOBAL_DATA_PTR; -int board_init (void) +int board_early_init_f(void) +{ + /* CS5: Debug port */ + writel(0x9d520003, IXP425_EXP_CS5); + /* CS6: HwRel */ + writel(0x81860001, IXP425_EXP_CS6); + /* CS7: LEDs */ + writel(0x80900003, IXP425_EXP_CS7); + return 0; +} + +int board_init(void) { gd->bd->bi_arch_number = MACH_TYPE_ACTUX1; /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; - GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); - /* Setup GPIO's for PCI INTA */ - GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI1_INTA); - GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI1_INTA); + /* Setup GPIOs for PCI INTA */ + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI1_INTA); + GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI1_INTA); - /* Setup GPIO's for 33MHz clock output */ - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK); - *IXP425_GPIO_GPCLKR = 0x011001FF; + /* Setup GPIOs for 33MHz clock output */ + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); + writel(0x011001FF, IXP425_GPIO_GPCLKR); - /* CS5: Debug port */ - *IXP425_EXP_CS5 = 0x9d520003; - /* CS6: HwRel */ - *IXP425_EXP_CS6 = 0x81860001; - /* CS7: LEDs */ - *IXP425_EXP_CS7 = 0x80900003; - - udelay (533); - GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST); + udelay(533); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); - ACTUX1_LED1 (2); - ACTUX1_LED2 (2); - ACTUX1_LED3 (0); - ACTUX1_LED4 (0); - ACTUX1_LED5 (0); - ACTUX1_LED6 (0); - ACTUX1_LED7 (0); + ACTUX1_LED1(2); + ACTUX1_LED2(2); + ACTUX1_LED3(0); + ACTUX1_LED4(0); + ACTUX1_LED5(0); + ACTUX1_LED6(0); + ACTUX1_LED7(0); - ACTUX1_HS (ACTUX1_HS_DCD); + ACTUX1_HS(ACTUX1_HS_DCD); return 0; } @@ -87,21 +95,21 @@ int board_init (void) /* * Check Board Identity */ -int checkboard (void) +int checkboard(void) { char buf[64]; int i = getenv_f("serial#", buf, sizeof(buf)); - puts ("Board: AcTux-1 rev."); - putc (ACTUX1_BOARDREL + 'A' - 1); + puts("Board: AcTux-1 rev."); + putc(ACTUX1_BOARDREL + 'A' - 1); if (i > 0) { puts(", serial# "); puts(buf); } - putc ('\n'); + putc('\n'); - return (0); + return 0; } /************************************************************************* @@ -110,39 +118,36 @@ int checkboard (void) * 1 = Rev. A * 2 = Rev. B *************************************************************************/ -u32 get_board_rev (void) +u32 get_board_rev(void) { return ACTUX1_BOARDREL; } -int dram_init (void) +int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); + gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); + return 0; } -#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) -extern struct pci_controller hose; -extern void pci_ixp_init (struct pci_controller *hose); -void pci_init_board (void) +#ifdef CONFIG_PCI +struct pci_controller hose; + +void pci_init_board(void) { - extern void pci_ixp_init (struct pci_controller *hose); - pci_ixp_init (&hose); + pci_ixp_init(&hose); } #endif -void reset_phy (void) +void reset_phy(void) { u16 id1, id2; /* initialize the PHY */ - miiphy_reset ("NPE0", CONFIG_PHY_ADDR); + miiphy_reset("NPE0", CONFIG_PHY_ADDR); - miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1); - miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2); + miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1); + miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2); id2 &= 0xFFF0; /* mask out revision bits */ @@ -153,9 +158,9 @@ void reset_phy (void) * LED2 (unused) = LINK, * LED3(red) = Coll */ - miiphy_write ("NPE0", CONFIG_PHY_ADDR, 20, 0xD432); + miiphy_write("NPE0", CONFIG_PHY_ADDR, 20, 0xD432); } else if (id1 == 0x143 && id2 == 0xbc30) { /* BCM5241: default values are OK */ } else - printf ("unknown ethernet PHY ID: %x %x\n", id1, id2); + printf("unknown ethernet PHY ID: %x %x\n", id1, id2); } diff --git a/board/actux1/config.mk b/board/actux1/config.mk deleted file mode 100644 index 9cb838b..0000000 --- a/board/actux1/config.mk +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x00e00000 - -# include NPE ethernet driver -BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds index 8be2b20..9dbaa6f 100644 --- a/board/actux1/u-boot.lds +++ b/board/actux1/u-boot.lds @@ -30,15 +30,15 @@ SECTIONS . = ALIGN (4); .text : { - arch/arm/cpu/ixp/start.o(.text) - lib/string.o(.text) - lib/vsprintf.o(.text) - arch/arm/lib/board.o(.text) - common/dlmalloc.o(.text) - arch/arm/cpu/ixp/cpu.o(.text) + arch/arm/cpu/ixp/start.o(.text*) + net/libnet.o(.text*) + board/actux1/libactux1.o(.text*) + arch/arm/cpu/ixp/libixp.o(.text*) + drivers/serial/libserial.o(.text*) + . = env_offset; common/env_embedded.o(.ppcenv) - * (.text) + *(.text*) } . = ALIGN (4); @@ -47,7 +47,7 @@ SECTIONS } . = ALIGN (4); .data : { - *(.data) + *(.data*) } . = ALIGN (4); .got : { @@ -61,10 +61,27 @@ SECTIONS __u_boot_cmd_end =.; . = ALIGN (4); - __bss_start =.; - .bss (NOLOAD): { - *(.bss) - . = ALIGN(4); + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + _end = .; } __bss_end__ =.; + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } } diff --git a/board/actux2/actux2.c b/board/actux2/actux2.c index 0d67f80..9040a09 100644 --- a/board/actux2/actux2.c +++ b/board/actux2/actux2.c @@ -43,50 +43,55 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init (void) +int board_early_init_f(void) +{ + /* CS1: IPAC-X */ + writel(0x94d10013, IXP425_EXP_CS1); + /* CS5: Debug port */ + writel(0x9d520003, IXP425_EXP_CS5); + /* CS6: HW release register */ + writel(0x81860001, IXP425_EXP_CS6); + /* CS7: LEDs */ + writel(0x80900003, IXP425_EXP_CS7); + + return 0; +} + +int board_init(void) { gd->bd->bi_arch_number = MACH_TYPE_ACTUX2; /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD); - GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST); - GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR); - GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD); - /* Setup GPIO's for Interrupt inputs */ - GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT); - GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT); + /* Setup GPIOs for Interrupt inputs */ + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT); - /* Setup GPIO's for 33MHz clock output */ - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK); - *IXP425_GPIO_GPCLKR = 0x011001FF; + /* Setup GPIOs for 33MHz clock output */ + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); + writel(0x011001FF, IXP425_GPIO_GPCLKR); - /* CS1: IPAC-X */ - *IXP425_EXP_CS1 = 0x94d10013; - /* CS5: Debug port */ - *IXP425_EXP_CS5 = 0x9d520003; - /* CS6: HW release register */ - *IXP425_EXP_CS6 = 0x81860001; - /* CS7: LEDs */ - *IXP425_EXP_CS7 = 0x80900003; + udelay(533); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST); - udelay (533); - GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST); - - ACTUX2_LED1 (1); - ACTUX2_LED2 (0); - ACTUX2_LED3 (0); - ACTUX2_LED4 (0); + ACTUX2_LED1(1); + ACTUX2_LED2(0); + ACTUX2_LED3(0); + ACTUX2_LED4(0); return 0; } @@ -94,29 +99,27 @@ int board_init (void) /* * Check Board Identity */ -int checkboard (void) +int checkboard(void) { char buf[64]; int i = getenv_f("serial#", buf, sizeof(buf)); - puts ("Board: AcTux-2 rev."); - putc (ACTUX2_BOARDREL + 'A' - 1); + puts("Board: AcTux-2 rev."); + putc(ACTUX2_BOARDREL + 'A' - 1); if (i > 0) { puts(", serial# "); puts(buf); } - putc ('\n'); + putc('\n'); - return (0); + return 0; } -int dram_init (void) +int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); + gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); + return 0; } /************************************************************************* @@ -125,13 +128,13 @@ int dram_init (void) * 1 = Rev. A * 2 = Rev. B *************************************************************************/ -u32 get_board_rev (void) +u32 get_board_rev(void) { return ACTUX2_BOARDREL; } -void reset_phy (void) +void reset_phy(void) { /* init IcPlus IP175C ethernet switch to native IP175C mode */ - miiphy_write ("NPE0", 29, 31, 0x175C); + miiphy_write("NPE0", 29, 31, 0x175C); } diff --git a/board/actux2/config.mk b/board/actux2/config.mk deleted file mode 100644 index 9cb838b..0000000 --- a/board/actux2/config.mk +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x00e00000 - -# include NPE ethernet driver -BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds index a405f55..3575ed9 100644 --- a/board/actux2/u-boot.lds +++ b/board/actux2/u-boot.lds @@ -30,34 +30,29 @@ SECTIONS . = ALIGN (4); .text : { - arch/arm/cpu/ixp/start.o(.text) - lib/string.o(.text) - lib/vsprintf.o(.text) - arch/arm/lib/board.o(.text) - common/dlmalloc.o(.text) - arch/arm/cpu/ixp/cpu.o(.text) + arch/arm/cpu/ixp/start.o(.text*) + net/libnet.o(.text*) + board/actux2/libactux2.o(.text*) + arch/arm/cpu/ixp/libixp.o(.text*) + drivers/serial/libserial.o(.text*) . = env_offset; - common/env_embedded.o (.ppcenv) - - * (.text) + common/env_embedded.o(.ppcenv) + *(.text*) } . = ALIGN (4); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - . = ALIGN (4); .data : { - *(.data) + *(.data*) } - . = ALIGN (4); .got : { *(.got) } - . =.; __u_boot_cmd_start =.; .u_boot_cmd : { @@ -66,10 +61,27 @@ SECTIONS __u_boot_cmd_end =.; . = ALIGN (4); - __bss_start =.; - .bss (NOLOAD): { - *(.bss) - . = ALIGN(4); + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + _end = .; } __bss_end__ =.; + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } } diff --git a/board/actux3/actux3.c b/board/actux3/actux3.c index bace254..64e5215 100644 --- a/board/actux3/actux3.c +++ b/board/actux3/actux3.c @@ -36,72 +36,76 @@ #include <malloc.h> #include <asm/arch/ixp425.h> #include <asm/io.h> - #include <miiphy.h> - #include "actux3_hw.h" DECLARE_GLOBAL_DATA_PTR; -int board_init (void) +int board_early_init_f(void) +{ + /* CS1: IPAC-X */ + writel(0x94d10013, IXP425_EXP_CS1); + /* CS5: Debug port */ + writel(0x9d520003, IXP425_EXP_CS5); + /* CS6: Release/Option register */ + writel(0x81860001, IXP425_EXP_CS6); + /* CS7: LEDs */ + writel(0x80900003, IXP425_EXP_CS7); + + return 0; +} + +int board_init(void) { gd->bd->bi_arch_number = MACH_TYPE_ACTUX3; /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED5_GN); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_RT); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_GN); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED5_GN); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_RT); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_GN); - GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST); - GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR); - GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD); - GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED5_GN); - GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_RT); - GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_GN); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED5_GN); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_RT); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_GN); /* * Setup GPIO's for Interrupt inputs */ - GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT); - GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT); /* * Setup GPIO's for 33MHz clock output */ - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK); - *IXP425_GPIO_GPCLKR = 0x011001FF; - - /* CS1: IPAC-X */ - *IXP425_EXP_CS1 = 0x94d10013; - /* CS5: Debug port */ - *IXP425_EXP_CS5 = 0x9d520003; - /* CS6: Release/Option register */ - *IXP425_EXP_CS6 = 0x81860001; - /* CS7: LEDs */ - *IXP425_EXP_CS7 = 0x80900003; - - udelay (533); - GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST); - - ACTUX3_LED1_RT (1); - ACTUX3_LED1_GN (0); - ACTUX3_LED2_RT (0); - ACTUX3_LED2_GN (0); - ACTUX3_LED3_RT (0); - ACTUX3_LED3_GN (0); - ACTUX3_LED4_GN (0); - ACTUX3_LED5_RT (0); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); + writel(0x011001FF, IXP425_GPIO_GPCLKR); + + /* we need a minimum PCI reset pulse width after enabling the clock */ + udelay(533); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST); + + ACTUX3_LED1_RT(1); + ACTUX3_LED1_GN(0); + ACTUX3_LED2_RT(0); + ACTUX3_LED2_GN(0); + ACTUX3_LED3_RT(0); + ACTUX3_LED3_GN(0); + ACTUX3_LED4_GN(0); + ACTUX3_LED5_RT(0); return 0; } @@ -109,21 +113,21 @@ int board_init (void) /* * Check Board Identity */ -int checkboard (void) +int checkboard(void) { char buf[64]; int i = getenv_f("serial#", buf, sizeof(buf)); - puts ("Board: AcTux-3 rev."); - putc (ACTUX3_BOARDREL + 'A' - 1); + puts("Board: AcTux-3 rev."); + putc(ACTUX3_BOARDREL + 'A' - 1); if (i > 0) { puts (", serial# "); puts (buf); } - putc ('\n'); + putc('\n'); - return (0); + return 0; } /************************************************************************* @@ -132,34 +136,32 @@ int checkboard (void) * 1 = Rev. A * 2 = Rev. B *************************************************************************/ -u32 get_board_rev (void) +u32 get_board_rev(void) { return ACTUX3_BOARDREL; } -int dram_init (void) +int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); + gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); + return 0; } -void reset_phy (void) +void reset_phy(void) { int i; /* initialize the PHY */ - miiphy_reset ("NPE0", CONFIG_PHY_ADDR); + miiphy_reset("NPE0", CONFIG_PHY_ADDR); /* all LED outputs = Link/Act */ - miiphy_write ("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA); + miiphy_write("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA); /* * The Marvell 88E6060 switch comes up with all ports disabled. * set all ethernet switch ports to forwarding state */ for (i = 1; i <= 5; i++) - miiphy_write ("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03); + miiphy_write("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03); } diff --git a/board/actux3/config.mk b/board/actux3/config.mk deleted file mode 100644 index 9cb838b..0000000 --- a/board/actux3/config.mk +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x00e00000 - -# include NPE ethernet driver -BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds index d3463cd..35aab29 100644 --- a/board/actux3/u-boot.lds +++ b/board/actux3/u-boot.lds @@ -30,34 +30,29 @@ SECTIONS . = ALIGN (4); .text : { - arch/arm/cpu/ixp/start.o (.text) - lib/string.o (.text) - lib/vsprintf.o (.text) - arch/arm/lib/board.o (.text) - common/dlmalloc.o (.text) - arch/arm/cpu/ixp/cpu.o (.text) + arch/arm/cpu/ixp/start.o(.text*) + net/libnet.o(.text*) + board/actux3/libactux3.o(.text*) + arch/arm/cpu/ixp/libixp.o(.text*) + drivers/serial/libserial.o(.text*) . = env_offset; - common/env_embedded.o (.ppcenv) - - * (.text) + common/env_embedded.o(.ppcenv) + *(.text*) } - . = ALIGN (4); + . = ALIGN(4); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN (4); + . = ALIGN(4); .data : { - *(.data) + *(.data*) } - - . = ALIGN (4); + . = ALIGN(4); .got : { *(.got) } - . =.; __u_boot_cmd_start =.; .u_boot_cmd : { @@ -66,10 +61,27 @@ SECTIONS __u_boot_cmd_end =.; . = ALIGN (4); - __bss_start =.; - .bss (NOLOAD): { - *(.bss) - . = ALIGN(4); + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + _end = .; } __bss_end__ =.; + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } } diff --git a/board/actux4/actux4.c b/board/actux4/actux4.c index f373b58..d20d881 100644 --- a/board/actux4/actux4.c +++ b/board/actux4/actux4.c @@ -35,92 +35,107 @@ #include <command.h> #include <malloc.h> #include <asm/arch/ixp425.h> - +#include <asm/io.h> #include <miiphy.h> +#ifdef CONFIG_PCI +#include <pci.h> +#include <asm/arch/ixp425pci.h> +#endif #include "actux4_hw.h" DECLARE_GLOBAL_DATA_PTR; -int board_init (void) +int board_early_init_f(void) +{ + writel(0xbd113c42, IXP425_EXP_CS1); + return 0; +} + +int board_init(void) { gd->bd->bi_arch_number = MACH_TYPE_ACTUX4; /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; - GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_nPWRON); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_nPWRON); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_nPWRON); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_nPWRON); - GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); /* led not populated on board*/ - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED3); - GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED3); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED3); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED3); /* middle LED */ - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED2); - GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED2); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED2); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED2); /* right LED */ /* weak pulldown = LED weak on */ - GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_LED1); - GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED1); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_LED1); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED1); /* Setup GPIO's for Interrupt inputs */ - GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTA); - GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTB); - GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTC); - GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_RTCINT); - GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTA); - GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTB); - - GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTA); - GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTB); - GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTC); - GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_RTCINT); - GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTA); - GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTB); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTA); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTB); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTC); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RTCINT); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB); + + GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTA); + GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTB); + GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTC); + GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RTCINT); + GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA); + GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB); /* Setup GPIO's for 33MHz clock output */ - *IXP425_GPIO_GPCLKR = 0x011001FF; - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK); - GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK); - - *IXP425_EXP_CS1 = 0xbd113c42; + writel(0x011001FF, IXP425_GPIO_GPCLKR); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); - udelay (10000); - GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST); - udelay (10000); - GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST); - udelay (10000); - GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST); + udelay(10000); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); + udelay(10000); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); + udelay(10000); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); return 0; } /* Check Board Identity */ -int checkboard (void) +int checkboard(void) { - puts ("Board: AcTux-4\n"); - return (0); + puts("Board: AcTux-4\n"); + return 0; } -int dram_init (void) +int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); + return 0; +} - return (0); +#ifdef CONFIG_PCI +struct pci_controller hose; + +void pci_init_board(void) +{ + pci_ixp_init(&hose); } +#endif /* * Hardcoded flash setup: * Flash 0 is a non-CFI SST 39VF020 flash, 8 bit flash / 8 bit bus. * Flash 1 is an Intel *16 flash using the CFI driver. */ -ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) { if (banknum == 0) { /* non-CFI boot flash */ info->portwidth = 1; diff --git a/board/actux4/config.mk b/board/actux4/config.mk deleted file mode 100644 index 9cb838b..0000000 --- a/board/actux4/config.mk +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x00e00000 - -# include NPE ethernet driver -BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c index 3c37557..f0e2e80 100644 --- a/board/afeb9260/afeb9260.c +++ b/board/afeb9260/afeb9260.c @@ -31,7 +31,7 @@ #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#include <asm/io.h> #include <asm/arch/hardware.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) #include <netdev.h> @@ -48,28 +48,28 @@ DECLARE_GLOBAL_DATA_PTR; static void afeb9260_nand_hw_init(void) { unsigned long csa; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + /* Assign CS3 to NAND/SmartMedia Interface */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | - AT91_SMC_DBW_8 | - AT91_SMC_TDF_(2)); - - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -81,10 +81,15 @@ static void afeb9260_nand_hw_init(void) #ifdef CONFIG_MACB static void afeb9260_macb_hw_init(void) { - unsigned long rstc; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + unsigned long erstl; + + + /* Enable EMAC clock */ + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); /* * Disable pull-up on: @@ -103,24 +108,22 @@ static void afeb9260_macb_hw_init(void) pin_to_mask(AT91_PIN_PA25) | pin_to_mask(AT91_PIN_PA26) | pin_to_mask(AT91_PIN_PA28), - pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); + &pioa->pudr); - rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; /* Need to reset PHY -> 500ms reset */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - AT91_RSTC_ERSTL | (0x0D << 8) | - AT91_RSTC_URSTEN); - - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | + AT91_RSTC_MR_URSTEN, &rstc->mr); + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); /* Wait for end hardware reset */ - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); - + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; /* Restore NRST value */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (rstc) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, + &rstc->mr); + /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA14) | @@ -129,23 +132,29 @@ static void afeb9260_macb_hw_init(void) pin_to_mask(AT91_PIN_PA25) | pin_to_mask(AT91_PIN_PA26) | pin_to_mask(AT91_PIN_PA28), - pin_to_controller(AT91_PIN_PA0) + PIO_PUER); + &pioa->puer); at91_macb_hw_init(); } #endif - +int board_early_init_f(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + /* Enable clocks for all PIOs */ + writel((1 << ATMEL_ID_PIOA) | + (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOC), + &pmc->pcer); + return 0; +} int board_init(void) { - /* Enable Ctrlc */ - console_init_f(); - /* arch number of AT91SAM9260EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AFEB9260; /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND afeb9260_nand_hw_init(); #endif @@ -159,8 +168,10 @@ int board_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; } @@ -174,7 +185,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x01); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x01); #endif return rc; } diff --git a/board/armadillo/flash.c b/board/armadillo/flash.c index cdbbfd0..cf7d7f6 100644 --- a/board/armadillo/flash.c +++ b/board/armadillo/flash.c @@ -162,6 +162,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) int rc = ERR_OK; unsigned long base; unsigned long addr; + ulong start; if ((info->flash_id & FLASH_VENDMASK) != (FUJ_MANUFACT & FLASH_VENDMASK)) { @@ -192,7 +193,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { /* ARM simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ @@ -232,6 +233,7 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) { int flag; unsigned long base; + ulong start; /* Check if Flash is (sufficiently) erased */ @@ -250,7 +252,7 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) flag = disable_interrupts (); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); base = dest & 0xF0000000; FL_WORD (base + (0x555 << 1)) = 0xAA; diff --git a/board/armltd/integrator/split_by_variant.sh b/board/armltd/integrator/split_by_variant.sh index d869dd2..19fc832 100755 --- a/board/armltd/integrator/split_by_variant.sh +++ b/board/armltd/integrator/split_by_variant.sh @@ -103,16 +103,16 @@ case "$cpu" in #undef CONFIG_CM_INIT /* CM may not have initialization reg */ #undef CONFIG_CM_TCRAM /* CM may not have TCRAM */ /* May not be processor without cache support */ -#define CONFIG_SYS_NO_ICACHE 1 -#define CONFIG_SYS_NO_DCACHE 1 +#define CONFIG_SYS_ICACHE_OFF 1 +#define CONFIG_SYS_DCACHE_OFF 1 _EOF ;; arm720t) cat >> ${config_file} << _EOF /* May not be processor without cache support */ -#define CONFIG_SYS_NO_ICACHE 1 -#define CONFIG_SYS_NO_DCACHE 1 +#define CONFIG_SYS_ICACHE_OFF 1 +#define CONFIG_SYS_DCACHE_OFF 1 _EOF ;; esac diff --git a/board/armltd/integrator/timer.c b/board/armltd/integrator/timer.c index 7562ffa..f10a026 100644 --- a/board/armltd/integrator/timer.c +++ b/board/armltd/integrator/timer.c @@ -95,7 +95,10 @@ int timer_init (void) /* init the timestamp */ total_count = 0ULL; - reset_timer_masked(); + /* capure current decrementer value */ + lastdec = READ_TIMER; + /* start "advancing" time stamp from 0 */ + timestamp = 0L; div_timer = CONFIG_SYS_HZ_CLOCK; do_div(div_timer, CONFIG_SYS_HZ); @@ -107,22 +110,11 @@ int timer_init (void) /* * timer without interrupts */ -void reset_timer (void) -{ - reset_timer_masked (); -} - ulong get_timer (ulong base_ticks) { return get_timer_masked () - base_ticks; } -void set_timer (ulong ticks) -{ - timestamp = ticks; - total_count = ticks * div_timer; -} - /* delay usec useconds */ void __udelay (unsigned long usec) { @@ -140,14 +132,6 @@ void __udelay (unsigned long usec) } } -void reset_timer_masked (void) -{ - /* capure current decrementer value */ - lastdec = READ_TIMER; - /* start "advancing" time stamp from 0 */ - timestamp = 0L; -} - /* converts the timer reading to U-Boot ticks */ /* the timestamp is the number of ticks since reset */ ulong get_timer_masked (void) diff --git a/board/armltd/versatile/config.mk b/board/armltd/versatile/config.mk deleted file mode 100644 index 8b57af1..0000000 --- a/board/armltd/versatile/config.mk +++ /dev/null @@ -1,5 +0,0 @@ -# -# image should be loaded at 0x01000000 -# - -CONFIG_SYS_TEXT_BASE = 0x01000000 diff --git a/board/armltd/versatile/versatile.c b/board/armltd/versatile/versatile.c index 6e836dd..ee8cb5e 100644 --- a/board/armltd/versatile/versatile.c +++ b/board/armltd/versatile/versatile.c @@ -51,7 +51,7 @@ void show_boot_progress(int progress) * Miscellaneous platform dependent initialisations */ -int board_init (void) +int board_early_init_f (void) { /* * set clock frequency: @@ -62,6 +62,11 @@ int board_init (void) ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel)); + return 0; +} + +int board_init (void) +{ /* arch number of Versatile Board */ gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB; @@ -88,6 +93,9 @@ int misc_init_r (void) ******************************/ int dram_init (void) { + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/armltd/vexpress/ca9x4_ct_vxp.c b/board/armltd/vexpress/ca9x4_ct_vxp.c index 6e5884b..da6f14d 100644 --- a/board/armltd/vexpress/ca9x4_ct_vxp.c +++ b/board/armltd/vexpress/ca9x4_ct_vxp.c @@ -199,11 +199,6 @@ void reset_timer_masked(void) timestamp = 0; } -void reset_timer(void) -{ - reset_timer_masked(); -} - ulong get_timer_masked(void) { ulong now = readl(&systimer_base->timer0value) / 1000; diff --git a/board/atmel/at91rm9200dk/flash.c b/board/atmel/at91rm9200dk/flash.c index 902c3c4..be22743 100644 --- a/board/atmel/at91rm9200dk/flash.c +++ b/board/atmel/at91rm9200dk/flash.c @@ -285,6 +285,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) int iflag, cflag, prot, sect; int rc = ERR_OK; int chip1; + ulong start; /* first look for protection bits */ @@ -325,7 +326,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ volatile u16 *addr = (volatile u16 *) (info->start[sect]); @@ -345,7 +346,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) result = *addr; /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; chip1 = TMO; break; @@ -400,6 +401,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) int rc = ERR_OK; int cflag, iflag; int chip1; + ulong start; /* * Check if Flash is (sufficiently) erased @@ -425,7 +427,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait until flash is ready */ chip1 = 0; @@ -433,7 +435,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) result = *addr; /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { chip1 = ERR | TMO; break; } diff --git a/board/atmel/at91rm9200ek/at91rm9200ek.c b/board/atmel/at91rm9200ek/at91rm9200ek.c index d242583..2b4d845 100644 --- a/board/atmel/at91rm9200ek/at91rm9200ek.c +++ b/board/atmel/at91rm9200ek/at91rm9200ek.c @@ -31,6 +31,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/at91_pio.h> #include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_common.h> #include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -44,7 +45,7 @@ int board_init(void) * Correct IRDA resistor problem * Set PA23_TXD in Output */ - writel(AT91_PMX_AA_TXD2, &pio->pioa.oer); + writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer); /* arch number of AT91RM9200EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK; @@ -54,10 +55,16 @@ int board_init(void) return 0; } +int board_early_init_f(void) +{ + at91_seriald_hw_init(); + return 0; +} + int dram_init (void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); return 0; } @@ -65,6 +72,6 @@ int dram_init (void) #ifdef CONFIG_DRIVER_AT91EMAC int board_eth_init(bd_t *bis) { - return at91emac_register(bis, (u32) AT91_EMAC_BASE); + return at91emac_register(bis, (u32) ATMEL_BASE_EMAC); } #endif diff --git a/board/atmel/at91rm9200ek/led.c b/board/atmel/at91rm9200ek/led.c index 8d512e0..1766ddf 100644 --- a/board/atmel/at91rm9200ek/led.c +++ b/board/atmel/at91rm9200ek/led.c @@ -26,8 +26,10 @@ */ #include <common.h> -#include <asm/arch/gpio.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> #include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_pio.h> /* bit mask in PIO port B */ #define GREEN_LED (1<<0) @@ -36,47 +38,47 @@ void green_LED_on(void) { - at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO; writel(GREEN_LED, &pio->piob.codr); } void yellow_LED_on(void) { - at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO; writel(YELLOW_LED, &pio->piob.codr); } void red_LED_on(void) { - at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO; writel(RED_LED, &pio->piob.codr); } void green_LED_off(void) { - at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO; writel(GREEN_LED, &pio->piob.sodr); } void yellow_LED_off(void) { - at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO; writel(YELLOW_LED, &pio->piob.sodr); } void red_LED_off(void) { - at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO; writel(RED_LED, &pio->piob.sodr); } void coloured_LED_init (void) { - at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE; - at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE; + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO; /* Enable PIOB clock */ - writel(1 << AT91_ID_PIOB, &pmc->pcer); + writel(1 << ATMEL_ID_PIOB, &pmc->pcer); /* Disable peripherals on LEDs */ writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per); diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index 64c6d17..b3ed91d 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -23,17 +23,16 @@ */ #include <common.h> -#include <asm/arch/at91sam9260.h> +#include <asm/io.h> #include <asm/arch/at91sam9260_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> -#include <asm/arch/hardware.h> + #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) -#include <net.h> +# include <net.h> #endif #include <netdev.h> @@ -47,49 +46,53 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_CMD_NAND static void at91sam9260ek_nand_hw_init(void) { + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; unsigned long csa; - /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + /* Assign CS3 to NAND/SmartMedia Interface */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(2)); - - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + } #endif #ifdef CONFIG_MACB static void at91sam9260ek_macb_hw_init(void) { - unsigned long rstc; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + unsigned long erstl; - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); + /* Enable EMAC clock */ + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); /* * Disable pull-up on: @@ -103,48 +106,57 @@ static void at91sam9260ek_macb_hw_init(void) * PHY has internal pull-down */ writel(pin_to_mask(AT91_PIN_PA14) | - pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA17) | - pin_to_mask(AT91_PIN_PA25) | - pin_to_mask(AT91_PIN_PA26) | - pin_to_mask(AT91_PIN_PA28), - pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); + pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA17) | + pin_to_mask(AT91_PIN_PA25) | + pin_to_mask(AT91_PIN_PA26) | + pin_to_mask(AT91_PIN_PA28), + &pioa->pudr); - rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; /* Need to reset PHY -> 500ms reset */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (AT91_RSTC_ERSTL & (0x0D << 8)) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | + AT91_RSTC_MR_URSTEN, &rstc->mr); - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); /* Wait for end hardware reset */ - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; /* Restore NRST value */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (rstc) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, + &rstc->mr); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA14) | - pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA17) | - pin_to_mask(AT91_PIN_PA25) | - pin_to_mask(AT91_PIN_PA26) | - pin_to_mask(AT91_PIN_PA28), - pin_to_controller(AT91_PIN_PA0) + PIO_PUER); - + pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA17) | + pin_to_mask(AT91_PIN_PA25) | + pin_to_mask(AT91_PIN_PA26) | + pin_to_mask(AT91_PIN_PA28), + &pioa->puer); + + /* Initialize EMAC=MACB hardware */ at91_macb_hw_init(); } #endif -int board_init(void) +int board_early_init_f(void) { - /* Enable Ctrlc */ - console_init_f(); + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable clocks for all PIOs */ + writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOC), + &pmc->pcer); + return 0; +} + +int board_init(void) +{ #ifdef CONFIG_AT91SAM9G20EK /* arch number of AT91SAM9260EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK; @@ -153,9 +165,9 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK; #endif /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND at91sam9260ek_nand_hw_init(); #endif @@ -171,8 +183,9 @@ int board_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; } @@ -186,7 +199,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); #endif return rc; } diff --git a/board/atmel/at91sam9260ek/config.mk b/board/atmel/at91sam9260ek/config.mk deleted file mode 100644 index e554a45..0000000 --- a/board/atmel/at91sam9260ek/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x23f00000 diff --git a/board/atmel/at91sam9260ek/led.c b/board/atmel/at91sam9260ek/led.c index 2424d27..daf81e8 100644 --- a/board/atmel/at91sam9260ek/led.c +++ b/board/atmel/at91sam9260ek/led.c @@ -23,16 +23,12 @@ */ #include <common.h> -#include <asm/arch/at91sam9260.h> -#include <asm/arch/at91_pmc.h> +#include <asm/io.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> void coloured_LED_init(void) { - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); - + /* Clock is enabled in board_early_init_f() */ at91_set_gpio_output(CONFIG_RED_LED, 1); at91_set_gpio_output(CONFIG_GREEN_LED, 1); diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index de5cfae..b6c7d9e 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -23,6 +23,7 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/at91sam9261.h> #include <asm/arch/at91sam9261_matrix.h> #include <asm/arch/at91sam9_smc.h> @@ -31,7 +32,6 @@ #include <asm/arch/at91_rstc.h> #include <asm/arch/clk.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> #include <lcd.h> #include <atmel_lcdc.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) @@ -49,44 +49,48 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_CMD_NAND static void at91sam9261ek_nand_hw_init(void) { + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; unsigned long csa; /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + + writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ #ifdef CONFIG_AT91SAM9G10EK - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(7) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(7)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), + &smc->cs[3].cycle); #else - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); #endif - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(2)); + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -102,35 +106,37 @@ static void at91sam9261ek_nand_hw_init(void) #ifdef CONFIG_DRIVER_DM9000 static void at91sam9261ek_dm9000_hw_init(void) { + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + /* Configure SMC CS2 for DM9000 */ #ifdef CONFIG_AT91SAM9G10EK - at91_sys_write(AT91_SMC_SETUP(2), - AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(3) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(2), - AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(8) | - AT91_SMC_NRDPULSE_(6) | AT91_SMC_NCS_RDPULSE_(8)); - at91_sys_write(AT91_SMC_CYCLE(2), - AT91_SMC_NWECYCLE_(20) | AT91_SMC_NRDCYCLE_(20)); - at91_sys_write(AT91_SMC_MODE(2), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | - AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | - AT91_SMC_TDF_(1)); + writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[2].setup); + writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) | + AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8), + &smc->cs[2].pulse); + writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20), + &smc->cs[2].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[2].mode); #else - at91_sys_write(AT91_SMC_SETUP(2), - AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(2), - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | - AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); - at91_sys_write(AT91_SMC_CYCLE(2), - AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); - at91_sys_write(AT91_SMC_MODE(2), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | - AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | - AT91_SMC_TDF_(1)); + writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[2].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8), + &smc->cs[2].pulse); + writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16), + &smc->cs[2].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[2].mode); #endif /* Configure Reset signal as output */ @@ -156,7 +162,7 @@ vidinfo_t panel_info = { vl_vsync_len: 1, vl_upper_margin:1, vl_lower_margin:0, - mmio: AT91SAM9261_LCDC_BASE, + mmio: ATMEL_BASE_LCDC, }; void lcd_enable(void) @@ -171,6 +177,8 @@ void lcd_disable(void) static void at91sam9261ek_lcd_hw_init(void) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ @@ -194,12 +202,11 @@ static void at91sam9261ek_lcd_hw_init(void) at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ - at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1); + writel(AT91_PMC_HCK1, &pmc->scer); -#ifdef CONFIG_AT91SAM9G10EK - gd->fb_base = CONFIG_AT91SAM9G10_LCD_BASE; -#else - gd->fb_base = AT91SAM9261_SRAM_BASE; + /* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */ +#ifdef CONFIG_AT91SAM9261EK + gd->fb_base = ATMEL_BASE_SRAM; #endif } @@ -217,7 +224,7 @@ void lcd_show_board_info(void) lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", - CONFIG_SYS_AT91_CPU_NAME, + ATMEL_CPU_NAME, strmhz(temp, get_cpu_clk_rate())); dram_size = 0; @@ -246,9 +253,9 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK; #endif /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND at91sam9261ek_nand_hw_init(); #endif @@ -273,8 +280,9 @@ int board_eth_init(bd_t *bis) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; } diff --git a/board/atmel/at91sam9261ek/config.mk b/board/atmel/at91sam9261ek/config.mk deleted file mode 100644 index e554a45..0000000 --- a/board/atmel/at91sam9261ek/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x23f00000 diff --git a/board/atmel/at91sam9261ek/led.c b/board/atmel/at91sam9261ek/led.c index 5d1c5f2..0c2f522 100644 --- a/board/atmel/at91sam9261ek/led.c +++ b/board/atmel/at91sam9261ek/led.c @@ -26,12 +26,15 @@ #include <asm/arch/at91sam9261.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#include <asm/arch/at91_pio.h> +#include <asm/io.h> void coloured_LED_init(void) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA); + writel(ATMEL_ID_PIOA, &pmc->pcer); at91_set_gpio_output(CONFIG_RED_LED, 1); at91_set_gpio_output(CONFIG_GREEN_LED, 1); diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 91efc07..4d2937d 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -32,7 +32,8 @@ #include <asm/arch/at91_matrix.h> #include <asm/arch/at91_pio.h> #include <asm/arch/clk.h> -#include <asm/arch/io.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> #include <asm/arch/hardware.h> #include <lcd.h> #include <atmel_lcdc.h> @@ -52,9 +53,9 @@ DECLARE_GLOBAL_DATA_PTR; static void at91sam9263ek_nand_hw_init(void) { unsigned long csa; - at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE; - at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; + at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; /* Enable CS3 */ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; @@ -83,14 +84,14 @@ static void at91sam9263ek_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode); - writel(1 << AT91SAM9263_ID_PIOA | 1 << AT91SAM9263_ID_PIOCDE, + writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE, &pmc->pcer); /* Configure RDY/BSY */ - at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } #endif @@ -98,11 +99,11 @@ static void at91sam9263ek_nand_hw_init(void) static void at91sam9263ek_macb_hw_init(void) { unsigned long erstl; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; - at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; /* Enable clock */ - writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer); + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); /* * Disable pull-up on: @@ -153,7 +154,7 @@ vidinfo_t panel_info = { vl_vsync_len: 1, vl_upper_margin:1, vl_lower_margin:0, - mmio: AT91SAM9263_LCDC_BASE, + mmio: ATMEL_BASE_LCDC, }; void lcd_enable(void) @@ -168,7 +169,7 @@ void lcd_disable(void) static void at91sam9263ek_lcd_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ @@ -193,8 +194,8 @@ static void at91sam9263ek_lcd_hw_init(void) at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ - writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer); - gd->fb_base = AT91SAM9263_SRAM0_BASE; + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); + gd->fb_base = ATMEL_BASE_SRAM0; } #ifdef CONFIG_LCD_INFO @@ -218,7 +219,7 @@ void lcd_show_board_info(void) lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", - CONFIG_SYS_AT91_CPU_NAME, + ATMEL_CPU_NAME, strmhz(temp, get_cpu_clk_rate())); dram_size = 0; @@ -244,6 +245,18 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif +int board_early_init_f(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable clocks for all PIOs */ + writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOCDE), + &pmc->pcer); + + return 0; +} + int board_init(void) { /* Enable Ctrlc */ @@ -252,9 +265,9 @@ int board_init(void) /* arch number of AT91SAM9263EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK; /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND at91sam9263ek_nand_hw_init(); #endif @@ -276,8 +289,9 @@ int board_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; } @@ -291,7 +305,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *) AT91_EMAC_BASE, 0x00); + rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x00); #endif return rc; } diff --git a/board/atmel/at91sam9263ek/config.mk b/board/atmel/at91sam9263ek/config.mk deleted file mode 100644 index e554a45..0000000 --- a/board/atmel/at91sam9263ek/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x23f00000 diff --git a/board/atmel/at91sam9263ek/led.c b/board/atmel/at91sam9263ek/led.c index fa1f05b..c44455e 100644 --- a/board/atmel/at91sam9263ek/led.c +++ b/board/atmel/at91sam9263ek/led.c @@ -23,25 +23,24 @@ */ #include <common.h> -#include <asm/arch/hardware.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_pio.h> +#include <asm/io.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91sam9263.h> void coloured_LED_init(void) { /* Enable clock */ - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - writel(1 << AT91SAM9263_ID_PIOB | 1 << AT91SAM9263_ID_PIOCDE, + writel(1 << ATMEL_ID_PIOB | 1 << ATMEL_ID_PIOCDE, &pmc->pcer); - at91_set_pio_output(CONFIG_RED_LED, 1); - at91_set_pio_output(CONFIG_GREEN_LED, 1); - at91_set_pio_output(CONFIG_YELLOW_LED, 1); + at91_set_gpio_output(CONFIG_RED_LED, 1); + at91_set_gpio_output(CONFIG_GREEN_LED, 1); + at91_set_gpio_output(CONFIG_YELLOW_LED, 1); - at91_set_pio_value(CONFIG_RED_LED, 0); - at91_set_pio_value(CONFIG_GREEN_LED, 1); - at91_set_pio_value(CONFIG_YELLOW_LED, 1); + at91_set_gpio_value(CONFIG_RED_LED, 0); + at91_set_gpio_value(CONFIG_GREEN_LED, 1); + at91_set_gpio_value(CONFIG_YELLOW_LED, 1); } diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index e374917..e559084 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -23,6 +23,7 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/at91sam9rl.h> #include <asm/arch/at91sam9rl_matrix.h> #include <asm/arch/at91sam9_smc.h> @@ -31,7 +32,7 @@ #include <asm/arch/at91_rstc.h> #include <asm/arch/clk.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> + #include <lcd.h> #include <atmel_lcdc.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) @@ -48,33 +49,37 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_CMD_NAND static void at91sam9rlek_nand_hw_init(void) { + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; unsigned long csa; /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + + writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(2)); + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD); + writel(1 << ATMEL_ID_PIOD, &pmc->pcer); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -102,7 +107,7 @@ vidinfo_t panel_info = { vl_vsync_len: 1, vl_upper_margin:1, vl_lower_margin:0, - mmio: AT91SAM9RL_LCDC_BASE, + mmio: ATMEL_BASE_LCDC, }; void lcd_enable(void) @@ -116,6 +121,8 @@ void lcd_disable(void) } static void at91sam9rlek_lcd_hw_init(void) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */ at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */ at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */ @@ -138,9 +145,7 @@ static void at91sam9rlek_lcd_hw_init(void) at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */ at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_LCDC); - - gd->fb_base = 0; + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); } #ifdef CONFIG_LCD_INFO @@ -157,7 +162,7 @@ void lcd_show_board_info(void) lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", - CONFIG_SYS_AT91_CPU_NAME, + ATMEL_CPU_NAME, strmhz(temp, get_cpu_clk_rate())); dram_size = 0; @@ -173,6 +178,17 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif +int board_early_init_f(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable clocks for all PIOs */ + writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOC) | (1 << ATMEL_ID_PIOD), + &pmc->pcer); + + return 0; +} int board_init(void) { @@ -182,9 +198,9 @@ int board_init(void) /* arch number of AT91SAM9RLEK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK; /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND at91sam9rlek_nand_hw_init(); #endif @@ -199,7 +215,8 @@ int board_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/at91sam9rlek/config.mk b/board/atmel/at91sam9rlek/config.mk deleted file mode 100644 index e554a45..0000000 --- a/board/atmel/at91sam9rlek/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x23f00000 diff --git a/board/atmel/at91sam9rlek/led.c b/board/atmel/at91sam9rlek/led.c index 9634cc0..987e8c0 100644 --- a/board/atmel/at91sam9rlek/led.c +++ b/board/atmel/at91sam9rlek/led.c @@ -26,12 +26,14 @@ #include <asm/arch/at91sam9rl.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#include <asm/io.h> void coloured_LED_init(void) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD); + writel(ATMEL_ID_PIOD, &pmc->pcer); at91_set_gpio_output(CONFIG_RED_LED, 1); at91_set_gpio_output(CONFIG_GREEN_LED, 1); diff --git a/board/atmel/atstk1000/Makefile b/board/atmel/atstk1000/Makefile index ae47396..a02ccf1 100644 --- a/board/atmel/atstk1000/Makefile +++ b/board/atmel/atstk1000/Makefile @@ -27,7 +27,6 @@ include $(TOPDIR)/config.mk LIB := $(obj)lib$(BOARD).o COBJS-y += $(BOARD).o -COBJS-y += flash.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/board/atmel/atstk1000/flash.c b/board/atmel/atstk1000/flash.c deleted file mode 100644 index 0ba06dd..0000000 --- a/board/atmel/atstk1000/flash.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> - -#ifdef CONFIG_ATSTK1000_EXT_FLASH -#include <asm/arch/cacheflush.h> -#include <asm/io.h> -#include <asm/sections.h> - -DECLARE_GLOBAL_DATA_PTR; - -flash_info_t flash_info[1]; - -static void flash_identify(uint16_t *flash, flash_info_t *info) -{ - unsigned long flags; - - flags = disable_interrupts(); - - dcache_flush_unlocked(); - - writew(0xaa, flash + 0x555); - writew(0x55, flash + 0xaaa); - writew(0x90, flash + 0x555); - info->flash_id = readl(flash); - writew(0xff, flash); - - readw(flash); - - if (flags) - enable_interrupts(); -} - -unsigned long flash_init(void) -{ - unsigned long addr; - unsigned int i; - - flash_info[0].size = CONFIG_SYS_FLASH_SIZE; - flash_info[0].sector_count = 135; - - flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]); - - for (i = 0, addr = 0; i < 8; i++, addr += 0x2000) - flash_info[0].start[i] = addr; - for (; i < flash_info[0].sector_count; i++, addr += 0x10000) - flash_info[0].start[i] = addr; - - return CONFIG_SYS_FLASH_SIZE; -} - -void flash_print_info(flash_info_t *info) -{ - printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n", - info->flash_id >> 16, info->flash_id & 0xffff); - printf("Size: %ld MB in %d sectors\n", - info->size >> 10, info->sector_count); -} - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - unsigned long flags; - unsigned long start_time; - uint16_t *fb, *sb; - unsigned int i; - int ret; - uint16_t status; - - if ((s_first < 0) || (s_first > s_last) - || (s_last >= info->sector_count)) { - puts("Error: first and/or last sector out of range\n"); - return ERR_INVAL; - } - - for (i = s_first; i < s_last; i++) - if (info->protect[i]) { - printf("Error: sector %d is protected\n", i); - return ERR_PROTECTED; - } - - fb = (uint16_t *)uncached(info->start[0]); - - dcache_flush_unlocked(); - - for (i = s_first; (i <= s_last) && !ctrlc(); i++) { - printf("Erasing sector %3d...", i); - - sb = (uint16_t *)uncached(info->start[i]); - - flags = disable_interrupts(); - - start_time = get_timer(0); - - /* Unlock sector */ - writew(0xaa, fb + 0x555); - writew(0x70, sb); - - /* Erase sector */ - writew(0xaa, fb + 0x555); - writew(0x55, fb + 0xaaa); - writew(0x80, fb + 0x555); - writew(0xaa, fb + 0x555); - writew(0x55, fb + 0xaaa); - writew(0x30, sb); - - /* Wait for completion */ - ret = ERR_OK; - do { - /* TODO: Timeout */ - status = readw(sb); - } while ((status != 0xffff) && !(status & 0x28)); - - writew(0xf0, fb); - - /* - * Make sure the command actually makes it to the bus - * before we re-enable interrupts. - */ - readw(fb); - - if (flags) - enable_interrupts(); - - if (status != 0xffff) { - printf("Flash erase error at address 0x%p: 0x%02x\n", - sb, status); - ret = ERR_PROG_ERROR; - break; - } - } - - if (ctrlc()) - printf("User interrupt!\n"); - - return ERR_OK; -} - -int write_buff(flash_info_t *info, uchar *src, - ulong addr, ulong count) -{ - unsigned long flags; - uint16_t *base, *p, *s, *end; - uint16_t word, status, status1; - int ret = ERR_OK; - - if (addr < info->start[0] - || (addr + count) > (info->start[0] + info->size) - || (addr + count) < addr) { - puts("Error: invalid address range\n"); - return ERR_INVAL; - } - - if (addr & 1 || count & 1 || (unsigned int)src & 1) { - puts("Error: misaligned source, destination or count\n"); - return ERR_ALIGN; - } - - base = (uint16_t *)uncached(info->start[0]); - end = (uint16_t *)uncached(addr + count); - - flags = disable_interrupts(); - - dcache_flush_unlocked(); - sync_write_buffer(); - - for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src; - p < end && !ctrlc(); p++, s++) { - word = *s; - - writew(0xaa, base + 0x555); - writew(0x55, base + 0xaaa); - writew(0xa0, base + 0x555); - writew(word, p); - - sync_write_buffer(); - - /* Wait for completion */ - status1 = readw(p); - do { - /* TODO: Timeout */ - status = status1; - status1 = readw(p); - } while (((status ^ status1) & 0x40) /* toggled */ - && !(status1 & 0x28)); /* error bits */ - - /* - * We'll need to check once again for toggle bit - * because the toggle bit may stop toggling as I/O5 - * changes to "1" (ref at49bv642.pdf p9) - */ - status1 = readw(p); - status = readw(p); - if ((status ^ status1) & 0x40) { - printf("Flash write error at address 0x%p: " - "0x%02x != 0x%02x\n", - p, status,word); - ret = ERR_PROG_ERROR; - writew(0xf0, base); - readw(base); - break; - } - - writew(0xf0, base); - readw(base); - } - - if (flags) - enable_interrupts(); - - return ret; -} - -#endif /* CONFIG_ATSTK1000_EXT_FLASH */ diff --git a/board/bluewater/snapper9260/Makefile b/board/bluewater/snapper9260/Makefile new file mode 100644 index 0000000..4fccdaa --- /dev/null +++ b/board/bluewater/snapper9260/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2011 Bluewater Systems +# Ryan Mallon <ryan@bluewatersys.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += snapper9260.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/bluewater/snapper9260/snapper9260.c b/board/bluewater/snapper9260/snapper9260.c new file mode 100644 index 0000000..60c55e9 --- /dev/null +++ b/board/bluewater/snapper9260/snapper9260.c @@ -0,0 +1,169 @@ +/* + * Bluewater Systems Snapper 9260/9G20 modules + * + * (C) Copyright 2011 Bluewater Systems + * Author: Andre Renaud <andre@bluewatersys.com> + * Author: Ryan Mallon <ryan@bluewatersys.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91sam9260_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <net.h> +#include <netdev.h> +#include <i2c.h> +#include <pca953x.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* IO Expander pins */ +#define IO_EXP_ETH_RESET (0 << 1) +#define IO_EXP_ETH_POWER (1 << 1) + +static void macb_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + unsigned long erstl; + + /* Enable clock */ + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); + + /* Disable pull-ups to prevent PHY going into test mode */ + writel(pin_to_mask(AT91_PIN_PA14) | + pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA18), + &pioa->pudr); + + /* Power down ethernet */ + pca953x_set_dir(0x28, IO_EXP_ETH_POWER, PCA953X_DIR_OUT); + pca953x_set_val(0x28, IO_EXP_ETH_POWER, 1); + + /* Hold ethernet in reset */ + pca953x_set_dir(0x28, IO_EXP_ETH_RESET, PCA953X_DIR_OUT); + pca953x_set_val(0x28, IO_EXP_ETH_RESET, 0); + + /* Enable ethernet power */ + pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0); + + /* Need to reset PHY -> 500ms reset */ + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | + AT91_RSTC_MR_URSTEN, &rstc->mr); + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); + + /* Wait for end hardware reset */ + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; + + /* Restore NRST value */ + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); + + /* Bring the ethernet out of reset */ + pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1); + + /* The phy internal reset take 21ms */ + udelay(21 * 1000); + + /* Re-enable pull-up */ + writel(pin_to_mask(AT91_PIN_PA14) | + pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA18), + &pioa->puer); + + at91_macb_hw_init(); +} + +static void nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Enable CS3 as NAND/SmartMedia */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} + +int board_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable PIO clocks */ + writel((1 << ATMEL_ID_PIOA) | + (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOC), &pmc->pcer); + + /* The mach-type is the same for both Snapper 9260 and 9G20 */ + gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260; + + /* Address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + /* Initialise peripherals */ + at91_seriald_hw_init(); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + nand_hw_init(); + macb_hw_init(); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x1f); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +void reset_phy(void) +{ +} diff --git a/board/bmw/ns16550.h b/board/bmw/ns16550.h index 8aa251d..2087a4a 100644 --- a/board/bmw/ns16550.h +++ b/board/bmw/ns16550.h @@ -37,7 +37,7 @@ struct NS16550 { #define afr iirfcrafr #define FCR_FIFO_EN 0x01 /*fifo enable */ -#define FCR_RXSR 0x02 /*reciever soft reset */ +#define FCR_RXSR 0x02 /*receiver soft reset */ #define FCR_TXSR 0x04 /*transmitter soft reset */ #define FCR_DMS 0x08 /* DMA Mode Select */ diff --git a/board/cerf250/flash.c b/board/cerf250/flash.c index a4b201e..e1e7807 100644 --- a/board/cerf250/flash.c +++ b/board/cerf250/flash.c @@ -221,7 +221,7 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) int flash_erase (flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -254,9 +254,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - start = get_timer (0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -269,14 +266,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); *addr = (FPW) 0x00500050; /* clear status register */ *addr = (FPW) 0x00200020; /* erase setup */ *addr = (FPW) 0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -393,6 +390,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) FPWV *addr = (FPWV *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -406,11 +404,11 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/cm-bf537e/cm-bf537e.c b/board/cm-bf537e/cm-bf537e.c index 1e350dc..38dbc6e 100644 --- a/board/cm-bf537e/cm-bf537e.c +++ b/board/cm-bf537e/cm-bf537e.c @@ -24,27 +24,37 @@ int checkboard(void) return 0; } -#ifdef CONFIG_BFIN_MAC -static void board_init_enetaddr(uchar *mac_addr) +static void board_init_enetaddr(char *var) { - puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); - eth_setenv_enetaddr("ethaddr", mac_addr); +#ifdef CONFIG_NET_MULTI + uchar enetaddr[6]; + + if (eth_getenv_enetaddr(var, enetaddr)) + return; + + printf("Warning: %s: generating 'random' MAC address\n", var); + bfin_gen_rand_mac(enetaddr); + eth_setenv_enetaddr(var, enetaddr); +#endif } +#ifndef CONFIG_BFIN_MAC +# define bfin_EMAC_initialize(x) 1 +#endif +#ifndef CONFIG_SMC911X +# define smc911x_initialize(n, x) 1 +#endif int board_eth_init(bd_t *bis) { - return bfin_EMAC_initialize(bis); + /* return ok if at least 1 eth device works */ + return bfin_EMAC_initialize(bis) & + smc911x_initialize(0, CONFIG_SMC911X_BASE); } -#endif int misc_init_r(void) { -#ifdef CONFIG_BFIN_MAC - uchar enetaddr[6]; - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) - board_init_enetaddr(enetaddr); -#endif + board_init_enetaddr("ethaddr"); + board_init_enetaddr("eth1addr"); gpio_cfi_flash_init(); diff --git a/board/cm-bf537u/cm-bf537u.c b/board/cm-bf537u/cm-bf537u.c index 4b7e864..a62ddd6 100644 --- a/board/cm-bf537u/cm-bf537u.c +++ b/board/cm-bf537u/cm-bf537u.c @@ -24,34 +24,37 @@ int checkboard(void) return 0; } -#ifdef CONFIG_BFIN_MAC -static void board_init_enetaddr(uchar *mac_addr) +static void board_init_enetaddr(char *var) { - puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); - eth_setenv_enetaddr("ethaddr", mac_addr); -} +#ifdef CONFIG_NET_MULTI + uchar enetaddr[6]; -int board_eth_init(bd_t *bis) -{ - return bfin_EMAC_initialize(bis); -} + if (eth_getenv_enetaddr(var, enetaddr)) + return; + + printf("Warning: %s: generating 'random' MAC address\n", var); + bfin_gen_rand_mac(enetaddr); + eth_setenv_enetaddr(var, enetaddr); #endif +} -#ifdef CONFIG_SMC911X +#ifndef CONFIG_BFIN_MAC +# define bfin_EMAC_initialize(x) 1 +#endif +#ifndef CONFIG_SMC911X +# define smc911x_initialize(n, x) 1 +#endif int board_eth_init(bd_t *bis) { - return smc911x_initialize(0, CONFIG_SMC911X_BASE); + /* return ok if at least 1 eth device works */ + return bfin_EMAC_initialize(bis) & + smc911x_initialize(0, CONFIG_SMC911X_BASE); } -#endif int misc_init_r(void) { -#ifdef CONFIG_BFIN_MAC - uchar enetaddr[6]; - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) - board_init_enetaddr(enetaddr); -#endif + board_init_enetaddr("ethaddr"); + board_init_enetaddr("eth1addr"); gpio_cfi_flash_init(); diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c index 2e66872..d6fd519 100644 --- a/board/cm4008/flash.c +++ b/board/cm4008/flash.c @@ -209,6 +209,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) int flag, prot, sect; ulong type; int rcode = 0; + ulong start; if ((s_first < 0) || (s_first > s_last)) { if (info->flash_id == FLASH_UNKNOWN) { @@ -250,7 +251,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); addr = (volatile unsigned char *) (info->start[sect]); *addr = 0x50; /* clear status register */ @@ -258,7 +259,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr = 0xD0; /* erase confirm */ while (((status = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = 0xB0; /* suspend erase */ @@ -370,6 +371,7 @@ static int write_data (flash_info_t * info, ulong dest, unsigned char data) volatile unsigned char *addr = (volatile unsigned char *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -384,11 +386,11 @@ static int write_data (flash_info_t * info, ulong dest, unsigned char data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = 0xFF; /* restore read mode */ return (1); } diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c index 2e66872..d6fd519 100644 --- a/board/cm41xx/flash.c +++ b/board/cm41xx/flash.c @@ -209,6 +209,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) int flag, prot, sect; ulong type; int rcode = 0; + ulong start; if ((s_first < 0) || (s_first > s_last)) { if (info->flash_id == FLASH_UNKNOWN) { @@ -250,7 +251,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); addr = (volatile unsigned char *) (info->start[sect]); *addr = 0x50; /* clear status register */ @@ -258,7 +259,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr = 0xD0; /* erase confirm */ while (((status = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = 0xB0; /* suspend erase */ @@ -370,6 +371,7 @@ static int write_data (flash_info_t * info, ulong dest, unsigned char data) volatile unsigned char *addr = (volatile unsigned char *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -384,11 +386,11 @@ static int write_data (flash_info_t * info, ulong dest, unsigned char data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = 0xFF; /* restore read mode */ return (1); } diff --git a/board/cmc_pu2/flash.c b/board/cmc_pu2/flash.c index d832e62..d10faab 100644 --- a/board/cmc_pu2/flash.c +++ b/board/cmc_pu2/flash.c @@ -264,7 +264,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) { vu_short *addr = (vu_short *)(info->start[0]); int flag, prot, sect, ssect, l_sect; - ulong now, last; + ulong now, last, start; debug ("flash_erase: first: %d last: %d\n", s_first, s_last); @@ -335,11 +335,11 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) if (l_sect < 0) goto DONE; - reset_timer_masked (); + start = get_timer(0); last = 0; addr = (vu_short *)(info->start[l_sect]); while ((addr[0] & 0x0080) != 0x0080) { - if ((now = get_timer_masked ()) > CONFIG_SYS_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -434,6 +434,7 @@ static int write_word_amd (flash_info_t *info, vu_short *dest, ushort data) { int flag; vu_short *base; /* first address in flash bank */ + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*dest & data) != data) { @@ -455,11 +456,11 @@ static int write_word_amd (flash_info_t *info, vu_short *dest, ushort data) if (flag) enable_interrupts(); - reset_timer_masked (); + start = get_timer(0); /* data polling for D7 */ while ((*dest & 0x0080) != (data & 0x0080)) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = 0x00F0; /* reset bank */ return (1); } diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c index 33c9361..e8f02eb 100644 --- a/board/cobra5272/flash.c +++ b/board/cobra5272/flash.c @@ -147,6 +147,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) int iflag, cflag, prot, sect; int rc = ERR_OK; int chip1; + ulong start; /* first look for protection bits */ @@ -190,7 +191,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - set_timer (0); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ volatile u16 *addr = @@ -211,7 +212,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) result = *addr; /* check timeout */ - if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; chip1 = TMO; break; @@ -264,6 +265,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) int rc = ERR_OK; int cflag, iflag; int chip1; + ulong start; /* * Check if Flash is (sufficiently) erased @@ -291,7 +293,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) *addr = data; /* arm simple, non interrupt dependent timer */ - set_timer (0); + start = get_timer(0); /* wait until flash is ready */ chip1 = 0; @@ -299,7 +301,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) result = *addr; /* check timeout */ - if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { chip1 = ERR | TMO; break; } diff --git a/board/cradle/flash.c b/board/cradle/flash.c index b5635fb..1601782 100644 --- a/board/cradle/flash.c +++ b/board/cradle/flash.c @@ -136,6 +136,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) { int flag, prot, sect; int rc = ERR_OK; + ulong start; if (info->flash_id == FLASH_UNKNOWN) return ERR_UNKNOWN_FLASH_TYPE; @@ -173,7 +174,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ vu_short *addr = (vu_short *) (info->start[sect]); @@ -182,7 +183,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr = 0xD0; /* erase confirm */ while ((*addr & 0x80) != 0x80) { - if (get_timer_masked () > + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = 0xB0; /* suspend erase */ *addr = 0xFF; /* reset to read mode */ @@ -221,6 +222,7 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) vu_short *addr = (vu_short *) dest, val; int rc = ERR_OK; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ @@ -246,11 +248,11 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((val = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { rc = ERR_TIMOUT; /* suspend program command */ *addr = 0xB0; diff --git a/board/csb226/flash.c b/board/csb226/flash.c index 02ded1c..e103470 100644 --- a/board/csb226/flash.c +++ b/board/csb226/flash.c @@ -141,6 +141,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; int rc = ERR_OK; + ulong start; if (info->flash_id == FLASH_UNKNOWN) return ERR_UNKNOWN_FLASH_TYPE; @@ -175,7 +176,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) printf("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ u32 * volatile addr = (u32 * volatile)(info->start[sect]); @@ -189,7 +190,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) *addr = 0x00D000D0; /* erase confirm */ while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = 0x00B000B0; /* suspend erase*/ *addr = 0x00FF00FF; /* read mode */ rc = ERR_TIMOUT; @@ -221,6 +222,7 @@ static int write_long (flash_info_t *info, ulong dest, ulong data) u32 * volatile addr = (u32 * volatile)dest, val; int rc = ERR_OK; int flag; + ulong start; /* read array command - just for the case... */ *addr = 0x00FF00FF; @@ -247,11 +249,11 @@ static int write_long (flash_info_t *info, ulong dest, ulong data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); /* wait while polling the status register */ while(((val = *addr) & 0x00800080) != 0x00800080) { - if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { rc = ERR_TIMOUT; /* suspend program command */ *addr = 0x00B000B0; diff --git a/board/davedenx/qong/config.mk b/board/davedenx/qong/config.mk deleted file mode 100644 index ea1c1b0..0000000 --- a/board/davedenx/qong/config.mk +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0xa0000000 - -# PLATFORM_CPPFLAGS += -DDEBUG diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index b1238d5..ec22627 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -44,7 +44,7 @@ void hw_watchdog_reset(void) int dram_init (void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c index 2bfdf23..6103339 100644 --- a/board/davinci/common/misc.c +++ b/board/davinci/common/misc.c @@ -38,7 +38,7 @@ int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (volatile void *)CONFIG_SYS_SDRAM_BASE, + (void *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); return 0; } diff --git a/board/davinci/dm355leopard/dm355leopard.c b/board/davinci/dm355leopard/dm355leopard.c index 0ee0d11..0ad5678 100644 --- a/board/davinci/dm355leopard/dm355leopard.c +++ b/board/davinci/dm355leopard/dm355leopard.c @@ -20,7 +20,7 @@ #include <nand.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/gpio_defs.h> +#include <asm/arch/gpio.h> #include <asm/arch/nand_defs.h> #include <asm/arch/davinci_misc.h> #include <net.h> diff --git a/board/davinci/dm365evm/dm365evm.c b/board/davinci/dm365evm/dm365evm.c index 5fb7611..ac54106 100644 --- a/board/davinci/dm365evm/dm365evm.c +++ b/board/davinci/dm365evm/dm365evm.c @@ -22,7 +22,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/emif_defs.h> #include <asm/arch/nand_defs.h> -#include <asm/arch/gpio_defs.h> +#include <asm/arch/gpio.h> #include <netdev.h> #include <asm/arch/davinci_misc.h> #ifdef CONFIG_DAVINCI_MMC diff --git a/board/dnp1110/flash.c b/board/dnp1110/flash.c index c81abc5..53f89ee 100644 --- a/board/dnp1110/flash.c +++ b/board/dnp1110/flash.c @@ -212,7 +212,7 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) int flash_erase (flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -245,9 +245,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - start = get_timer (0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -260,14 +257,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); *addr = (FPW)0x00500050; /* clear status register */ *addr = (FPW)0x00200020; /* erase setup */ *addr = (FPW)0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW)0x00B000B0; /* suspend erase */ *addr = (FPW)0x00FF00FF; /* reset to read mode */ @@ -385,6 +382,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) FPWV *addr = (FPWV *)dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -398,11 +396,11 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (start = get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW)0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/netstal/hcu4/Makefile b/board/dvlhost/Makefile index a983de9..af9a644 100644 --- a/board/netstal/hcu4/Makefile +++ b/board/dvlhost/Makefile @@ -1,6 +1,9 @@ # -# (C) Copyright 2007-2008 Netstal Maschinen AG -# Niklaus Giger (ng@netstal.com) +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as @@ -9,7 +12,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -19,24 +22,20 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif LIB = $(obj)lib$(BOARD).o -COBJS = $(BOARD).o \ - ../common/fixed_sdram.o \ - ../common/nm_bsp.o +COBJS := dvlhost.o watchdog.o -SRCS := $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) - $(call cmd_link_o_target, $^) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) clean: - rm -f $(OBJS) + rm -f $(SOBJS) $(OBJS) distclean: clean rm -f $(LIB) core *.bak $(obj).depend diff --git a/board/dvlhost/dvlhost.c b/board/dvlhost/dvlhost.c new file mode 100644 index 0000000..561e47f --- /dev/null +++ b/board/dvlhost/dvlhost.c @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2009 + * Michael Schwingen, michael@schwingen.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <command.h> +#include <malloc.h> +#include <asm/arch/ixp425.h> +#include <asm/io.h> +#include <miiphy.h> +#ifdef CONFIG_PCI +#include <pci.h> +#include <asm/arch/ixp425pci.h> +#endif + +#include "dvlhost_hw.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* CS1: LED Latch */ + writel(0xBFFF0002, IXP425_EXP_CS1); + return 0; +} + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_DVLHOST; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + /* Setup GPIOs used as output */ + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDGTRIGGER); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DLAN_PAIRING); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PCIRST); + + /* + * LED latch enable and watchdog enable are tied to the same GPIO, + * so we need to trigger the watchdog if we want to enable the LEDs. + */ +#ifdef CONFIG_HW_WATCHDOG + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDG_LED_EN); +#else + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_WDG_LED_EN); +#endif + + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDGTRIGGER); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DLAN_PAIRING); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDG_LED_EN); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCIRST); + + /* Setup GPIOs for Interrupt inputs */ + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_WLAN); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_PAIRING); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_RESET); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_IRQA); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_IRQB); + + /* Setup GPIO's for 33MHz clock output */ + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); + writel(0x01FF01FF, IXP425_GPIO_GPCLKR); + + /* turn off all LEDs */ + writew(0x0000, DVLHOST_LED_LATCH); + + udelay(533); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_PCIRST); + + return 0; +} + +/* Check Board Identity */ +int checkboard(void) +{ + char *s = getenv("serial#"); + + puts("Board: dLAN 200AV (dvlhost)"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); + return 0; +} + +#ifdef CONFIG_PCI +struct pci_controller hose; + +void pci_init_board(void) +{ + pci_ixp_init(&hose); +} +#endif + +void reset_phy(void) +{ + /* init IcPlus IP175C ethernet switch to native IP175C mode */ + miiphy_write("NPE1", 29, 31, 0x175C); +} diff --git a/board/dvlhost/dvlhost_hw.h b/board/dvlhost/dvlhost_hw.h new file mode 100644 index 0000000..5e2d0b0 --- /dev/null +++ b/board/dvlhost/dvlhost_hw.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2009 + * Michael Schwingen, michael@schwingen.org + * + * hardware register definitions for the + * dLAN200 AV Wireless G ("dvlhost") board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DVLHOST_HW_H +#define _DVLHOST_HW_H + +/* + * GPIO settings + */ +#define CONFIG_SYS_GPIO_WDGTRIGGER 0 /* Out */ +#define CONFIG_SYS_GPIO_BTN_WLAN 1 +#define CONFIG_SYS_GPIO_BTN_PAIRING 6 +#define CONFIG_SYS_GPIO_DLAN_PAIRING 7 /* Out */ +#define CONFIG_SYS_GPIO_BTN_RESET 9 +#define CONFIG_SYS_GPIO_IRQB 10 +#define CONFIG_SYS_GPIO_IRQA 11 +#define CONFIG_SYS_GPIO_WDG_LED_EN 12 /* Out */ +#define CONFIG_SYS_GPIO_PCIRST 13 /* Out */ +#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ +#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ + +#define DVLHOST_LED_LATCH IXP425_EXP_BUS_CS1_BASE_PHYS + +#endif diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds new file mode 100644 index 0000000..01ec390 --- /dev/null +++ b/board/dvlhost/u-boot.lds @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") +OUTPUT_ARCH (arm) +ENTRY (_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN (4); + .text : { + arch/arm/cpu/ixp/start.o(.text*) + net/libnet.o(.text*) + board/dvlhost/libdvlhost.o(.text*) + arch/arm/cpu/ixp/libixp.o(.text*) + drivers/serial/libserial.o(.text*) + + . = env_offset; + common/env_embedded.o(.ppcenv) + *(.text*) + } + + . = ALIGN (4); + .rodata : { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + . = ALIGN (4); + .data : { + *(.data*) + } + . = ALIGN (4); + .got : { + *(.got) + } + . =.; + __u_boot_cmd_start =.; + .u_boot_cmd : { + *(.u_boot_cmd) + } + __u_boot_cmd_end =.; + + . = ALIGN (4); + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + _end = .; + } + __bss_end__ =.; + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/board/dvlhost/watchdog.c b/board/dvlhost/watchdog.c new file mode 100644 index 0000000..bf83684 --- /dev/null +++ b/board/dvlhost/watchdog.c @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2009 + * Michael Schwingen, michael@schwingen.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include "dvlhost_hw.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_HW_WATCHDOG +#include <watchdog.h> +#include <asm/arch/ixp425.h> + +void hw_watchdog_reset(void) +{ + unsigned int x; + x = readl(IXP425_GPIO_GPOUTR); + x ^= (1 << (CONFIG_SYS_GPIO_WDGTRIGGER)); + writel(x, IXP425_GPIO_GPOUTR); +} + +#endif /* CONFIG_HW_WATCHDOG */ diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c index 16be532..4b36918 100644 --- a/board/efikamx/efikamx.c +++ b/board/efikamx/efikamx.c @@ -113,7 +113,7 @@ u32 get_board_rev(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/emk/top9000/top9000.c b/board/emk/top9000/top9000.c index 73dd706..61dee62 100644 --- a/board/emk/top9000/top9000.c +++ b/board/emk/top9000/top9000.c @@ -31,7 +31,8 @@ #include <mmc.h> #include <i2c.h> #include <spi.h> -#include <asm/arch/at91sam9260.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> #include <asm/arch/at91sam9260_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> @@ -39,35 +40,35 @@ #include <asm/arch/at91_rstc.h> #include <asm/arch/at91_shdwn.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> -#include <asm/arch/hardware.h> DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_CMD_NAND static void nand_hw_init(void) { + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; unsigned long csa; - /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + /* Assign CS3 to NAND/SmartMedia Interface */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | - AT91_SMC_DBW_8 | - AT91_SMC_TDF_(2)); + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -80,8 +81,10 @@ static void nand_hw_init(void) #ifdef CONFIG_MACB static void macb_hw_init(void) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + /* Enable EMAC clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); /* Initialize EMAC=MACB hardware */ at91_macb_hw_init(); @@ -92,14 +95,16 @@ static void macb_hw_init(void) /* this is a weak define that we are overriding */ int board_mmc_init(bd_t *bd) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + /* Enable MCI clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); + writel(1 << ATMEL_ID_MCI, &pmc->pcer); /* Initialize MCI hardware */ at91_mci_hw_init(); /* This calls the atmel_mmc_init in gen_atmel_mci.c */ - return atmel_mci_init((void *)AT91_BASE_MCI); + return atmel_mci_init((void *)ATMEL_BASE_MCI); } /* this is a weak define that we are overriding */ @@ -120,7 +125,8 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) int board_early_init_f(void) { - struct at91_shdwn *shdwn = (struct at91_shdwn *)AT91_SHDWN_BASE; + struct at91_shdwn *shdwn = (struct at91_shdwn *)ATMEL_BASE_SHDWN; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* * make sure the board can be powered on by @@ -130,9 +136,9 @@ int board_early_init_f(void) &shdwn->mr); /* Enable clocks for all PIOs */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOB); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); + writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOC), + &pmc->pcer); /* set SCL0 and SDA0 to open drain */ at91_set_pio_output(I2C0_PORT, SCL0_PIN, 1); @@ -159,7 +165,7 @@ int board_init(void) /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND nand_hw_init(); #endif @@ -211,7 +217,7 @@ int board_eth_init(bd_t *bis) int num = 0; #ifdef CONFIG_MACB rc = macb_eth_initialize(0, - (void *)AT91_EMAC_BASE, + (void *)ATMEL_BASE_EMAC0, CONFIG_SYS_PHY_ID); if (!rc) num++; diff --git a/board/ep7312/flash.c b/board/ep7312/flash.c index 0c2b3ae..2ed9c9a 100644 --- a/board/ep7312/flash.c +++ b/board/ep7312/flash.c @@ -119,6 +119,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) { int flag, prot, sect; int rc = ERR_OK; + ulong start; if (info->flash_id == FLASH_UNKNOWN) return ERR_UNKNOWN_FLASH_TYPE; @@ -156,7 +157,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ vu_short *addr = (vu_short *) (info->start[sect]); @@ -165,7 +166,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr = 0xD0; /* erase confirm */ while ((*addr & 0x80) != 0x80) { - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = 0xB0; /* suspend erase */ *addr = 0xFF; /* reset to read mode */ rc = ERR_TIMOUT; @@ -203,6 +204,7 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) vu_short *addr = (vu_short *) dest, val; int rc = ERR_OK; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ @@ -228,11 +230,11 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((val = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { rc = ERR_TIMOUT; /* suspend program command */ *addr = 0xB0; diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c index 9ec48a0..402f19f 100644 --- a/board/eukrea/cpu9260/cpu9260.c +++ b/board/eukrea/cpu9260/cpu9260.c @@ -4,7 +4,7 @@ * Lead Tech Design <www.leadtechdesign.com> * Ilko Iliev <www.ronetix.at> * - * (C) Copyright 2009 + * (C) Copyright 2009-2011 * Eric Benard <eric@eukrea.com> * * See file CREDITS for list of people who contributed to this @@ -27,16 +27,15 @@ */ #include <common.h> -#include <asm/sizes.h> +#include <asm/io.h> #include <asm/arch/at91sam9260.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> +#include <asm/arch/at91_matrix.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> -#include <asm/arch/at91_matrix.h> #include <asm/arch/at91_pio.h> #include <asm/arch/clk.h> -#include <asm/arch/io.h> #include <asm/arch/hardware.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) #include <net.h> @@ -54,9 +53,9 @@ DECLARE_GLOBAL_DATA_PTR; static void cpu9260_nand_hw_init(void) { unsigned long csa; - at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE; - at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC; + at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; /* Enable CS3 */ csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A; @@ -93,7 +92,7 @@ static void cpu9260_nand_hw_init(void) &smc->cs[3].mode); #endif - writel(1 << AT91SAM9260_ID_PIOC, &pmc->pcer); + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); /* Configure RDY/BSY */ at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -107,11 +106,11 @@ static void cpu9260_nand_hw_init(void) static void cpu9260_macb_hw_init(void) { unsigned long rstcmr; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; /* Enable clock */ - writel(1 << AT91SAM9260_ID_EMAC, &pmc->pcer); + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1); @@ -136,14 +135,14 @@ static void cpu9260_macb_hw_init(void) int board_early_init_f(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - writel((1 << AT91SAM9260_ID_PIOA) | - (1 << AT91SAM9260_ID_PIOC) | - (1 << AT91SAM9260_ID_PIOB), + writel((1 << ATMEL_ID_PIOA) | + (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOC), &pmc->pcer); - at91_serial_hw_init(); + at91_seriald_hw_init(); return 0; } @@ -175,7 +174,7 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); return 0; } @@ -184,7 +183,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0); #endif return rc; } diff --git a/board/eukrea/cpu9260/led.c b/board/eukrea/cpu9260/led.c index d0906bc..8d865eb 100644 --- a/board/eukrea/cpu9260/led.c +++ b/board/eukrea/cpu9260/led.c @@ -28,17 +28,17 @@ #include <asm/arch/at91sam9260.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#include <asm/io.h> static unsigned int saved_state[4] = {STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_OFF}; void coloured_LED_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; /* Enable clock */ - writel(1 << AT91SAM9260_ID_PIOC, &pmc->pcer); + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); at91_set_pio_output(CONFIG_RED_LED, 1); at91_set_pio_output(CONFIG_GREEN_LED, 1); diff --git a/board/eukrea/cpuat91/cpuat91.c b/board/eukrea/cpuat91/cpuat91.c index 4c4dad6..f654f87 100644 --- a/board/eukrea/cpuat91/cpuat91.c +++ b/board/eukrea/cpuat91/cpuat91.c @@ -32,6 +32,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/at91_pio.h> #include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_common.h> DECLARE_GLOBAL_DATA_PTR; @@ -52,10 +53,17 @@ int board_init(void) return 0; } +int board_early_init_f(void) +{ + at91_seriald_hw_init(); + return 0; +} + + int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); return 0; } @@ -63,7 +71,7 @@ int dram_init(void) #ifdef CONFIG_DRIVER_AT91EMAC int board_eth_init(bd_t *bis) { - return at91emac_register(bis, (u32) AT91_EMAC_BASE); + return at91emac_register(bis, (u32) ATMEL_BASE_EMAC); } #endif @@ -71,8 +79,8 @@ int board_eth_init(bd_t *bis) void i2c_init_board(void) { u32 pin; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; writel(1 << AT91_ID_PIOA, &pmc->pcer); pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; diff --git a/board/evb64260/bootseq.txt b/board/evb64260/bootseq.txt index e4fefb3..6cae9ea 100644 --- a/board/evb64260/bootseq.txt +++ b/board/evb64260/bootseq.txt @@ -62,7 +62,7 @@ in_flash: remap gt regs? map PCI mem/io map device space - clear out interupts + clear out interrupts init_timebase env_init serial_init diff --git a/board/evb64260/i2c.c b/board/evb64260/i2c.c index c62b647..88d0dac 100644 --- a/board/evb64260/i2c.c +++ b/board/evb64260/i2c.c @@ -306,7 +306,7 @@ i2c_read(uchar dev_addr, unsigned int offset, int len, uchar* data, status = i2c_get_data(data, len); if (status) { #ifdef DEBUG_I2C - printf("Data not recieved: 0x%02x\n", status); + printf("Data not received: 0x%02x\n", status); #endif return status; } diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 9324125..b1e7823 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -142,7 +142,9 @@ int board_early_init_r(void) 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN setup_portals(); +#endif return 0; } @@ -234,6 +236,7 @@ void ft_board_setup(void *blob, bd_t *bd) #endif fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); } int board_eth_init(bd_t *bis) diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 98024c7..b937015 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -192,10 +192,16 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->twoT_en = pbsp->force_2T; + break; } pbsp++; } + if (i == num_params) { + printf("Warning: board specific timing not found " + "for data rate %lu MT/s!\n", ddr_freq); + } + /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed @@ -219,7 +225,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->ddr_cdr1 = DDR_CDR1_DHC_EN; /* override SPD values. rcw_2 should vary at differnt speed */ - if (pdimm[0].n_ranks == 4) { + if (pdimm[0].registered_dimm == 1) { popts->rcw_override = 1; popts->rcw_1 = 0x000a5a00; if (ddr_freq <= 800) @@ -250,6 +256,6 @@ phys_size_t initdram(int board_type) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - puts(" DDR: "); + debug(" DDR: "); return dram_size; } diff --git a/board/freescale/corenet_ds/law.c b/board/freescale/corenet_ds/law.c index d2ba556..58f23c5 100644 --- a/board/freescale/corenet_ds/law.c +++ b/board/freescale/corenet_ds/law.c @@ -29,11 +29,16 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_BMAN_MEM_PHYS SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), +#endif SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), #ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CONFIG_SYS_NAND_BASE_PHYS SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c index 38736b4..2ce7004 100644 --- a/board/freescale/corenet_ds/tlb.c +++ b/board/freescale/corenet_ds/tlb.c @@ -98,6 +98,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 6, BOOKE_PAGESZ_256K, 1), /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_1M, 1), @@ -105,6 +106,8 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_1M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 11, BOOKE_PAGESZ_1M, 1), @@ -112,6 +115,7 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_1M, 1), +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/mpc8266ads/mpc8266ads.c b/board/freescale/mpc8266ads/mpc8266ads.c index 66acc41..2caf4aa 100644 --- a/board/freescale/mpc8266ads/mpc8266ads.c +++ b/board/freescale/mpc8266ads/mpc8266ads.c @@ -392,7 +392,7 @@ phys_size_t initdram(int board_type) The 11th column addre will still be mucxed correctly onto the bus. Also be aware that the MPC8266ADS board Rev B has not connected - Row addres 13 to anything. + Row address 13 to anything. The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126) */ diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 7a0ff18..f29b2f4 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -66,11 +66,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ }; -int board_early_init_f(void) -{ - return 0; -} - int fixed_sdram(void); phys_size_t initdram(int board_type) diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c index 2baa11a..99c0fbb 100644 --- a/board/freescale/mpc8360erdk/mpc8360erdk.c +++ b/board/freescale/mpc8360erdk/mpc8360erdk.c @@ -207,11 +207,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {0, 0, 0, 0, QE_IOP_TAB_END}, }; -int board_early_init_f(void) -{ - return 0; -} - int board_early_init_r(void) { void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8); diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c index ab471af..adcbd58 100644 --- a/board/freescale/mpc8572ds/ddr.c +++ b/board/freescale/mpc8572ds/ddr.c @@ -104,7 +104,6 @@ void fsl_ddr_board_options(memctl_options_t *popts, u32 num_params; u32 i; ulong ddr_freq; - int matched = 0; if (!pdimm->n_ranks) return; @@ -151,14 +150,15 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; popts->twoT_en = pbsp->force_2T; - matched = 1; break; } pbsp++; } - if (!matched) - printf("Warning: board specific timing not found!\n"); + if (i == num_params) { + printf("Warning: board specific timing not found " + "for data rate %lu MT/s!\n", ddr_freq); + } /* * Factors to consider for half-strength driver enable: diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index d7dd470..8aceddb 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -94,11 +94,32 @@ int checkboard(void) volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; u8 *pixis_base = (u8 *)PIXIS_BASE; - printf ("Board: MPC8610HPCD, System ID: 0x%02x, " - "System Version: 0x%02x, FPGA Version: 0x%02x\n", + printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, " + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), in_8(pixis_base + PIXIS_PVER)); + /* + * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot + * bank and LBMAP=00 is the alternate bank. However, the pixis + * altbank code can only set bits, not clear them, so we treat 00 as + * the normal bank and 11 as the alternate. + */ + switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) { + case 0: + puts("vBank: Standard\n"); + break; + case 0x40: + puts("Promjet\n"); + break; + case 0x80: + puts("NAND\n"); + break; + case 0xC0: + puts("vBank: Alternate\n"); + break; + } + mcm->abcr |= 0x00010000; /* 0 */ mcm->hpmr3 = 0x80000008; /* 4c */ mcm->hpmr0 = 0; @@ -124,7 +145,7 @@ initdram(int board_type) setup_ddr_bat(dram_size); - puts(" DDR: "); + debug(" DDR: "); return dram_size; } diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c index bd0b299..4f2e853 100644 --- a/board/freescale/mpc8641hpcn/ddr.c +++ b/board/freescale/mpc8641hpcn/ddr.c @@ -127,6 +127,11 @@ void fsl_ddr_board_options(memctl_options_t *popts, } } + if (i == num_params) { + printf("Warning: board specific timing not found " + "for data rate %lu MT/s!\n", ddr_freq); + } + /* 2T timing enable */ popts->twoT_en = 1; } diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index e3916fc..455569e 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -69,7 +69,7 @@ initdram(int board_type) setup_ddr_bat(dram_size); - puts(" DDR: "); + debug(" DDR: "); return dram_size; } diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c index 9bf9c18..7637c92 100644 --- a/board/freescale/mx31ads/mx31ads.c +++ b/board/freescale/mx31ads/mx31ads.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1, + gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index 08addd2..f6e190a 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -42,7 +42,7 @@ void hw_watchdog_reset(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index e2d3d74..fd7342f 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -53,7 +53,7 @@ u32 get_board_rev(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/netstal/hcu5/Makefile b/board/freescale/mx53ard/Makefile index 280c2f6..c48ece8 100644 --- a/board/netstal/hcu5/Makefile +++ b/board/freescale/mx53ard/Makefile @@ -1,6 +1,7 @@ # -# (C) Copyright 2007-2008 Netstal Maschinen AG -# Niklaus Giger (ng@netstal.com) +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as @@ -19,31 +20,23 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif LIB = $(obj)lib$(BOARD).o -COBJS = $(BOARD).o \ - sdram.o \ - ../common/nm_bsp.o -SOBJS = init.o +COBJS := mx53ard.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -all: $(LIB) $(SOBJS) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $^) +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### diff --git a/board/freescale/mx53ard/imximage_dd3.cfg b/board/freescale/mx53ard/imximage_dd3.cfg new file mode 100644 index 0000000..0f298ab --- /dev/null +++ b/board/freescale/mx53ard/imximage_dd3.cfg @@ -0,0 +1,96 @@ +# +# (C) Copyright 2009 +# Stefano Babic DENX Software Engineering sbabic@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer docs/README.imxmage for more details about how-to configure +# and create imximage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# image version + +IMAGE_VERSION 2 + +# Boot Device : one of +# spi, sd (the board has no nand neither onenand) + +BOOT_FROM sd + +# Device Configuration Data (DCD) +# +# Each entry must have the format: +# Addr-type Address Value +# +# where: +# Addr-type register length (1,2 or 4 bytes) +# Address absolute address of the register +# value value to be stored in the register +DATA 4 0x53fa8554 0x00300000 +DATA 4 0x53fa8558 0x00300040 +DATA 4 0x53fa8560 0x00300000 +DATA 4 0x53fa8564 0x00300040 +DATA 4 0x53fa8568 0x00300040 +DATA 4 0x53fa8570 0x00300000 +DATA 4 0x53fa8574 0x00300000 +DATA 4 0x53fa8578 0x00300000 +DATA 4 0x53fa857c 0x00300040 +DATA 4 0x53fa8580 0x00300040 +DATA 4 0x53fa8584 0x00300000 +DATA 4 0x53fa8588 0x00300000 +DATA 4 0x53fa8590 0x00300040 +DATA 4 0x53fa8594 0x00300000 +DATA 4 0x53fa86f0 0x00300000 +DATA 4 0x53fa86f4 0x00000000 +DATA 4 0x53fa86fc 0x00000000 +DATA 4 0x53fa8714 0x00000000 +DATA 4 0x53fa8718 0x00300000 +DATA 4 0x53fa871c 0x00300000 +DATA 4 0x53fa8720 0x00300000 +DATA 4 0x53fa8724 0x04000000 +DATA 4 0x53fa8728 0x00300000 +DATA 4 0x53fa872c 0x00300000 +DATA 4 0x63fd9088 0x35343535 +DATA 4 0x63fd9090 0x4d444c44 +DATA 4 0x63fd907c 0x01370138 +DATA 4 0x63fd9080 0x013b013c +DATA 4 0x63fd9018 0x00011740 +DATA 4 0x63fd9000 0xc3190000 +DATA 4 0x63fd900c 0x9f5152e3 +DATA 4 0x63fd9010 0xb68e8a63 +DATA 4 0x63fd9014 0x01ff00db +DATA 4 0x63fd902c 0x000026d2 +DATA 4 0x63fd9030 0x009f0e21 +DATA 4 0x63fd9008 0x12273030 +DATA 4 0x63fd9004 0x0002002d +DATA 4 0x63fd901c 0x00008032 +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00028031 +DATA 4 0x63fd901c 0x092080b0 +DATA 4 0x63fd901c 0x04008040 +DATA 4 0x63fd901c 0x0000803a +DATA 4 0x63fd901c 0x0000803b +DATA 4 0x63fd901c 0x00028039 +DATA 4 0x63fd901c 0x09208138 +DATA 4 0x63fd901c 0x04008048 +DATA 4 0x63fd9020 0x00001800 +DATA 4 0x63fd9040 0x04b80003 +DATA 4 0x63fd9058 0x00022227 +DATA 4 0x63fd901C 0x00000000 diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c new file mode 100644 index 0000000..134603a --- /dev/null +++ b/board/freescale/mx53ard/mx53ard.c @@ -0,0 +1,306 @@ +/* + * (C) Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx5x_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/errno.h> +#include <netdev.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <mxc_gpio.h> + +#define ETHERNET_INT (1 * 32 + 31) /* GPIO2_31 */ + +DECLARE_GLOBAL_DATA_PTR; + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int dram_init(void) +{ + u32 size1, size2; + + size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + + gd->ram_size = size1 + size2; + + return 0; +} +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +} + +static void setup_iomux_uart(void) +{ + /* UART1 RXD */ + mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX53_PIN_ATA_DMACK, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3); + + /* UART1 TXD */ + mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX53_PIN_ATA_DIOW, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_ODE_OPENDRAIN_ENABLE); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR, 1 }, + {MMC_SDHC2_BASE_ADDR, 1 }, +}; + +int board_mmc_getcd(u8 *cd, struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) + *cd = mxc_gpio_get(1); /*GPIO1_1*/ + else + *cd = mxc_gpio_get(4); /*GPIO1_4*/ + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + u32 index; + s32 status = 0; + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { + switch (index) { + case 0: + mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0); + + mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4); + mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4); + break; + case 1: + mxc_request_iomux(MX53_PIN_SD2_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX53_PIN_SD2_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX53_PIN_SD2_DATA0, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD2_DATA1, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD2_DATA2, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD2_DATA3, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_ATA_DATA12, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_DATA13, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_DATA14, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_DATA15, + IOMUX_CONFIG_ALT2); + + mxc_iomux_set_pad(MX53_PIN_SD2_CMD, 0x1E4); + mxc_iomux_set_pad(MX53_PIN_SD2_CLK, 0xD4); + mxc_iomux_set_pad(MX53_PIN_SD2_DATA0, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD2_DATA1, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD2_DATA2, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD2_DATA3, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA12, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA13, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA14, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA15, 0x1D4); + break; + default: + printf("Warning: you configured more ESDHC controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return status; + } + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + } + + return status; +} +#endif + +static void weim_smc911x_iomux(void) +{ + /* ETHERNET_INT as GPIO2_31 */ + mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1); + mxc_gpio_direction(ETHERNET_INT, MXC_GPIO_DIRECTION_IN); + + /* Data bus */ + mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D20, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D21, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D21, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D22, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D22, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D23, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D23, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D24, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D25, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D25, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D26, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D26, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D27, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D27, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D28, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D29, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D30, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D30, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D31, 0xA4); + + /* Address lines */ + mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA0, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA1, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA2, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA3, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA4, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA5, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA6, 0xA4); + + /* other EIM signals for ethernet */ + mxc_request_iomux(MX53_PIN_EIM_OE, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_EIM_RW, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_EIM_CS1, IOMUX_CONFIG_ALT0); +} + +static void weim_cs1_settings(void) +{ + struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; + + writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1); + writel(0x0, &weim_regs->cs1gcr2); + writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1); + writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2); + writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1); + writel(0x0, &weim_regs->cs1wcr2); + writel(0x0, &weim_regs->wcr); + + set_chipselect_size(CS0_64M_CS1_64M); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_MX53_ARD; + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + + weim_smc911x_iomux(); + weim_cs1_settings(); + +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} + +int checkboard(void) +{ + puts("Board: MX53ARD\n"); + + return 0; +} diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index a89aa25..88095dc 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -46,7 +46,7 @@ u32 get_board_rev(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index d032428..18b388e 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -47,8 +47,8 @@ int dram_init(void) { u32 size1, size2; - size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); gd->ram_size = size1 + size2; diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c index f3c433f..21b5d14 100644 --- a/board/freescale/mx53smd/mx53smd.c +++ b/board/freescale/mx53smd/mx53smd.c @@ -44,8 +44,8 @@ int dram_init(void) { u32 size1, size2; - size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); gd->ram_size = size1 + size2; diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 8ef627f..456d9b0 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -308,7 +308,8 @@ int board_eth_init(bd_t *bis) * ft_codec_setup - fix up the clock-frequency property of the codec node * * Update the clock-frequency property based on the value of the 'audclk' - * hwconfig option. If audclk is not specified, then default to 12.288MHz. + * hwconfig option. If audclk is not specified, then don't write anything + * to the device tree, because it means that the codec clock is disabled. */ static void ft_codec_setup(void *blob, const char *compatible) { @@ -317,12 +318,15 @@ static void ft_codec_setup(void *blob, const char *compatible) u32 freq; audclk = hwconfig_arg("audclk", &arglen); - if (audclk && (strncmp(audclk, "11", 2) == 0)) - freq = 11289600; - else - freq = 12288000; + if (audclk) { + if (strncmp(audclk, "11", 2) == 0) + freq = 11289600; + else + freq = 12288000; - do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1); + do_fixup_by_compat_u32(blob, compatible, "clock-frequency", + freq, 1); + } } void ft_board_setup(void *blob, bd_t *bd) diff --git a/board/freescale/p1023rds/Makefile b/board/freescale/p1023rds/Makefile new file mode 100644 index 0000000..bf87580 --- /dev/null +++ b/board/freescale/p1023rds/Makefile @@ -0,0 +1,38 @@ +# +# Copyright 2010-2011 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/p1023rds/bcsr.h b/board/freescale/p1023rds/bcsr.h new file mode 100644 index 0000000..0995aa4 --- /dev/null +++ b/board/freescale/p1023rds/bcsr.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * Authors: Chunhe Lan <b25806@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ + +#ifndef __BCSR_H_ +#define __BCSR_H_ + +#include <common.h> + +/* + * BCSR Bit definitions + * BCSR 15 * + 0 device insertion oriention + 1 stack processor present + 2 power supply shut down/normal operation + 3 I2C bus0 drive enable + 4 reserved + 5:7 I2C bus0 select + 5 - I2C_BUS_0_SS0 + 6 - I2C_BUS_0_SS1 + 7 - I2C_BUS_0_SS2 +*/ + +/* BCSR register base address is 0xFX000020 */ +#define BCSR_BASE_REG_OFFSET 0x20 +#define BCSR_ACCESS_REG_ADDR (CONFIG_SYS_BCSR_BASE + BCSR_BASE_REG_OFFSET) + +#define BCSR15_DEV_INS_ORI 0x80 +#define BCSR15_STACK_PRO_PRE 0x40 +#define BCSR15_POWER_SUPPLY 0x20 +#define BCSR15_I2C_BUS0_EN 0x10 +#define BCSR15_I2C_BUS0_SEG0 0x00 +#define BCSR15_I2C_BUS0_SEG1 0x04 +#define BCSR15_I2C_BUS0_SEG2 0x02 +#define BCSR15_I2C_BUS0_SEG3 0x06 +#define BCSR15_I2C_BUS0_SEG4 0x01 +#define BCSR15_I2C_BUS0_SEG5 0x05 +#define BCSR15_I2C_BUS0_SEG6 0x03 +#define BCSR15_I2C_BUS0_SEG7 0x07 +#define BCSR15_I2C_BUS0_SEG_CLR 0x07 +#define BCSR19_SGMII_SEL_L 0x01 + +/*BCSR Utils functions*/ +void fixup_i2c_bus0_sel_seg0(void); +#endif /* __BCSR_H_ */ diff --git a/board/freescale/p1023rds/law.c b/board/freescale/p1023rds/law.c new file mode 100644 index 0000000..f140f64 --- /dev/null +++ b/board/freescale/p1023rds/law.c @@ -0,0 +1,35 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M, + LAW_TRGT_IF_DPAA_SWP_SRAM), + /* The LAW 0xe0000000 ~ 0xefffffff for BCSR and NOR flash */ + SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c new file mode 100644 index 0000000..8cfd199 --- /dev/null +++ b/board/freescale/p1023rds/p1023rds.c @@ -0,0 +1,162 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * Authors: Roy Zang <tie-fei.zang@freescale.com> + * Chunhe Lan <b25806@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/io.h> +#include <asm/cache.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_pci.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_portals.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <netdev.h> +#include <malloc.h> + +#include "bcsr.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + fsl_lbc_t *lbc = LBC_BASE_ADDR; + + /* Set ABSWP to implement conversion of addresses in the LBC */ + setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); + + return 0; +} + +int checkboard(void) +{ + u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR; + + printf("Board: P1023 RDS\n"); + + clrbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG_CLR); + setbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG0); + + return 0; +} + +/* Fixed sdram init -- doesn't use serial presence detect. */ +phys_size_t fixed_sdram(void) +{ +#ifndef CONFIG_SYS_RAMBOOT + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + + set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); + + out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); + out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); + out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); + out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); + out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); + out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); + out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2); + out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); + out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); + out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); + out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); + out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); + out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); + out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); + out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); + out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); + out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1); + out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2); + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); +#endif + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024ul; +} + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} +#endif + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_BCSR_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + BCSR region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + bcsr */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_BCSR_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + setup_portals(); + + return 0; +} + +unsigned long get_board_sys_clk(ulong dummy) +{ + return gd->bus_clk; +} + +unsigned long get_board_ddr_clk(ulong dummy) +{ + return gd->mem_clk; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); +} +#endif diff --git a/board/freescale/p1023rds/tlb.c b/board/freescale/p1023rds/tlb.c new file mode 100644 index 0000000..2b3b679 --- /dev/null +++ b/board/freescale/p1023rds/tlb.c @@ -0,0 +1,118 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_4M, 1), + +#ifndef CONFIG_NAND_SPL + /* *W*G* - BCSR and NOR flash on local bus*/ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 9, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_1M, 1), +#endif + + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 11, BOOKE_PAGESZ_1M, 1), + +#ifdef CONFIG_SYS_RAMBOOT + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, + CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 12, BOOKE_PAGESZ_1G, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 13, BOOKE_PAGESZ_1G, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index d66b130..864b3ce 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -37,6 +37,7 @@ #include <netdev.h> #include <rtc.h> #include <i2c.h> +#include <hwconfig.h> DECLARE_GLOBAL_DATA_PTR; @@ -247,6 +248,8 @@ extern void ft_pci_board_setup(void *blob); void ft_board_setup(void *blob, bd_t *bd) { + const char *soc_usb_compat = "fsl-usb2-dr"; + int err, usb1_off, usb2_off; phys_addr_t base; phys_size_t size; @@ -260,5 +263,49 @@ void ft_board_setup(void *blob, bd_t *bd) #endif /* #if defined(CONFIG_PCI) */ fdt_fixup_memory(blob, (u64)base, (u64)size); + + fdt_fixup_dr_usb(blob, bd); + +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) + /* Delete eLBC node as it is muxed with USB2 controller */ + if (hwconfig("usb2")) { + const char *soc_elbc_compat = "fsl,p1020-elbc"; + int off = fdt_node_offset_by_compatible(blob, -1, + soc_elbc_compat); + if (off < 0) { + printf("WARNING: could not find compatible node" + " %s: %s.\n", soc_elbc_compat, + fdt_strerror(off)); + return; + } + err = fdt_del_node(blob, off); + if (err < 0) { + printf("WARNING: could not remove %s: %s.\n", + soc_elbc_compat, fdt_strerror(err)); + } + return; + } +#endif + /* Delete USB2 node as it is muxed with eLBC */ + usb1_off = fdt_node_offset_by_compatible(blob, -1, + soc_usb_compat); + if (usb1_off < 0) { + printf("WARNING: could not find compatible node" + " %s: %s.\n", soc_usb_compat, + fdt_strerror(usb1_off)); + return; + } + usb2_off = fdt_node_offset_by_compatible(blob, usb1_off, + soc_usb_compat); + if (usb2_off < 0) { + printf("WARNING: could not find compatible node" + " %s: %s.\n", soc_usb_compat, + fdt_strerror(usb2_off)); + return; + } + err = fdt_del_node(blob, usb2_off); + if (err < 0) + printf("WARNING: could not remove %s: %s.\n", + soc_usb_compat, fdt_strerror(err)); } #endif diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index 9bf7d2f..926fd19 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -83,10 +83,16 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; popts->twoT_en = pbsp->force_2T; + break; } pbsp++; } + if (i == num_params) { + printf("Warning: board specific timing not found " + "for data rate %lu MT/s!\n", ddr_freq); + } + /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed diff --git a/board/freescale/p2041rdb/Makefile b/board/freescale/p2041rdb/Makefile new file mode 100644 index 0000000..65f348f --- /dev/null +++ b/board/freescale/p2041rdb/Makefile @@ -0,0 +1,56 @@ +# +# Copyright 2011 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += cpld.o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o +COBJS-$(CONFIG_PCI) += pci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c new file mode 100644 index 0000000..8e1f46e --- /dev/null +++ b/board/freescale/p2041rdb/cpld.c @@ -0,0 +1,171 @@ +/** + * Copyright 2011 Freescale Semiconductor + * Author: Mingkai Hu <Mingkai.hu@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CPLD_BASE - The virtual address of the base of the CPLD register map + * + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#include "cpld.h" + +static u8 __cpld_read(unsigned int reg) +{ + void *p = (void *)CPLD_BASE; + + return in_8(p + reg); +} +u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read"))); + +static void __cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CPLD_BASE; + + out_8(p + reg, value); +} +void cpld_write(unsigned int reg, u8 value) + __attribute__((weak, alias("__cpld_write"))); + +/* + * Reset the board. This honors the por_cfg registers. + */ +void __cpld_reset(void) +{ + CPLD_WRITE(system_rst, 1); +} +void cpld_reset(void) __attribute__((weak, alias("__cpld_reset"))); + +/** + * Set the boot bank to the alternate bank + */ +void __cpld_set_altbank(void) +{ + CPLD_WRITE(fbank_sel, 1); +} +void cpld_set_altbank(void) + __attribute__((weak, alias("__cpld_set_altbank"))); + +/** + * Set the boot bank to the default bank + */ +void __cpld_clear_altbank(void) +{ + CPLD_WRITE(fbank_sel, 0); +} +void cpld_clear_altbank(void) + __attribute__((weak, alias("__cpld_clear_altbank"))); + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); + printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver)); + printf("system_rst = 0x%02x\n", CPLD_READ(system_rst)); + printf("wd_cfg = 0x%02x\n", CPLD_READ(wd_cfg)); + printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on)); + printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg)); + printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe)); + printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel)); + printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk)); + printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk)); + printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel)); + printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux)); + printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2))); + putc('\n'); +} +#endif + +int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + unsigned int i; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_clear_altbank(); + + cpld_reset(); + } else if (strcmp(argv[1], "watchdog") == 0) { + static char *period[8] = {"1ms", "10ms", "30ms", "disable", + "100ms", "1s", "10s", "60s"}; + for (i = 0; i < ARRAY_SIZE(period); i++) { + if (strcmp(argv[2], period[i]) == 0) + CPLD_WRITE(wd_cfg, i); + } + } else if (strcmp(argv[1], "lane_mux") == 0) { + u32 lane = simple_strtoul(argv[2], NULL, 16); + u8 val = (u8)simple_strtoul(argv[3], NULL, 16); + u8 reg = CPLD_READ(serdes_mux); + + switch (lane) { + case 0x6: + reg &= ~SERDES_MUX_LANE_6_MASK; + reg |= val << SERDES_MUX_LANE_6_SHIFT; + break; + case 0xa: + reg &= ~SERDES_MUX_LANE_A_MASK; + reg |= val << SERDES_MUX_LANE_A_SHIFT; + break; + case 0xc: + reg &= ~SERDES_MUX_LANE_C_MASK; + reg |= val << SERDES_MUX_LANE_C_SHIFT; + break; + case 0xd: + reg &= ~SERDES_MUX_LANE_D_MASK; + reg |= val << SERDES_MUX_LANE_D_SHIFT; + break; + default: + printf("Invalid value\n"); + break; + } + + CPLD_WRITE(serdes_mux, reg); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd, + "Reset the board or pin mulexing selection using the CPLD sequencer", + "reset - hard reset to default bank\n" + "cpld_cmd reset altbank - reset to alternate bank\n" + "cpld_cmd watchdog <watchdog_period> - set the watchdog period\n" + " period: 1ms 10ms 30ms 100ms 1s 10s 60s disable\n" + "cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n" + " lane 6: 0 -> slot1 (Default)\n" + " 1 -> SGMII\n" + " lane a: 0 -> slot2 (Default)\n" + " 1 -> AURORA\n" + " lane c: 0 -> slot2 (Default)\n" + " 1 -> SATA0\n" + " lane d: 0 -> slot2 (Default)\n" + " 1 -> SATA1\n" +#ifdef DEBUG + "cpld_cmd dump - display the CPLD registers\n" +#endif + ); diff --git a/board/freescale/p2041rdb/cpld.h b/board/freescale/p2041rdb/cpld.h new file mode 100644 index 0000000..3b24cb0 --- /dev/null +++ b/board/freescale/p2041rdb/cpld.h @@ -0,0 +1,53 @@ +/** + * Copyright 2011 Freescale Semiconductor + * Author: Mingkai Hu <Mingkai.hu@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +typedef struct cpld_data { + u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ + u8 pcba_ver; /* 0x2 - PCBA Revision Register */ + u8 system_rst; /* 0x3 - system reset register */ + u8 wd_cfg; /* 0x4 - Watchdog Period Setting Register */ + u8 sw_ctl_on; /* 0x5 - Switch Control Enable Register */ + u8 por_cfg; /* 0x6 - POR Control Register */ + u8 switch_strobe; /* 0x7 - Multiplexed pin Select Register */ + u8 jtag_sel; /* 0x8 - JTAG or AURORA Selection */ + u8 sdbank1_clk; /* 0x9 - SerDes Bank1 Reference clock */ + u8 sdbank2_clk; /* 0xa - SerDes Bank2 Reference clock */ + u8 fbank_sel; /* 0xb - Flash bank selection */ + u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */ + u8 sw[1]; /* 0xd - SW2 Status */ +} __attribute__ ((packed)) cpld_data_t; + +#define SERDES_MUX_LANE_6_MASK 0x2 +#define SERDES_MUX_LANE_6_SHIFT 1 +#define SERDES_MUX_LANE_A_MASK 0x1 +#define SERDES_MUX_LANE_A_SHIFT 0 +#define SERDES_MUX_LANE_C_MASK 0x4 +#define SERDES_MUX_LANE_C_SHIFT 2 +#define SERDES_MUX_LANE_D_MASK 0x8 +#define SERDES_MUX_LANE_D_SHIFT 3 + +/* Pointer to the CPLD register set */ +#define cpld ((cpld_data_t *)CPLD_BASE) + +/* The CPLD SW register that corresponds to board switch X, where x >= 1 */ +#define CPLD_SW(x) (cpld->sw[(x) - 2]) + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg)) +#define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value) diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c new file mode 100644 index 0000000..e9c699c --- /dev/null +++ b/board/freescale/p2041rdb/ddr.c @@ -0,0 +1,115 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <i2c.h> +#include <hwconfig.h> +#include <asm/mmu.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> +#include <asm/fsl_law.h> + +typedef struct { + u32 datarate_mhz_low; + u32 datarate_mhz_high; + u32 n_ranks; + u32 clk_adjust; + u32 wrlvl_start; + u32 cpo; + u32 write_data_delay; + u32 force_2T; +} board_specific_parameters_t; + +/* + * ranges for parameters: + * wr_data_delay = 0-6 + * clk adjust = 0-8 + * cpo 2-0x1E (30) + */ +const board_specific_parameters_t board_specific_parameters[] = { + /* + * memory controller 0 + * lo| hi| num| clk| wrlvl | cpo |wrdata|2T + * mhz| mhz|ranks|adjst| start | delay| + */ + { 1017, 1116, 2, 4, 6, 0xff, 2, 0}, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const board_specific_parameters_t *pbsp = + &board_specific_parameters[0]; + u32 num_params = ARRAY_SIZE(board_specific_parameters); + u32 i; + ulong ddr_freq; + + /* + * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + for (i = 0; i < num_params; i++) { + if (ddr_freq >= pbsp->datarate_mhz_low && + ddr_freq <= pbsp->datarate_mhz_high && + pdimm[0].n_ranks == pbsp->n_ranks) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->twoT_en = pbsp->force_2T; + break; + } + pbsp++; + } + + if (i == num_params) { + printf("Warning: board specific timing not found " + "for data rate %lu MT/s!\n", ddr_freq); + } + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* Write leveling override */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* Rtt and Rtt_WR override */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 60 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = 0; + + puts("Initializing...."); + + if (fsl_use_spd()) { + puts("using SPD\n"); + dram_size = fsl_ddr_sdram(); + } else { + puts("no SPD and fixed parameters\n"); + return dram_size; + } + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + debug(" DDR: "); + return dram_size; +} diff --git a/board/freescale/p2041rdb/law.c b/board/freescale/p2041rdb/law.c new file mode 100644 index 0000000..127a478 --- /dev/null +++ b/board/freescale/p2041rdb/law.c @@ -0,0 +1,37 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), + SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c new file mode 100644 index 0000000..52269d3 --- /dev/null +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -0,0 +1,203 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <linux/compiler.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +extern void pci_of_setup(void *blob, bd_t *bd); + +#include "cpld.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + u8 sw; + struct cpu_type *cpu = gd->cpu; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + unsigned int i; + + printf("Board: %sRDB, ", cpu->name); + printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver), + CPLD_READ(cpld_ver_sub)); + + sw = CPLD_READ(fbank_sel); + printf("vBank: %d\n", sw & 0x1); + +#ifdef CONFIG_PHYS_64BIT + puts("36-bit Addressing\n"); +#endif + + /* + * Display the RCW, so that no one gets confused as to what RCW + * we're actually using for this boot. + */ + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + u32 rcw = in_be32(&gur->rcwsr[i]); + + if ((i % 4) == 0) + printf("\n %08x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); + + /* + * Display the actual SERDES reference clocks as configured by the + * dip switches on the board. Note that the SWx registers could + * technically be set to force the reference clocks to match the + * values that the SERDES expects (or vice versa). For now, however, + * we just display both values and hope the user notices when they + * don't match. + */ + puts("SERDES Reference Clocks: "); + sw = in_8(&CPLD_SW(2)) >> 2; + for (i = 0; i < 2; i++) { + static const char * const freq[] = {"0", "100", "125"}; + unsigned int clock = (sw >> (2 * i)) & 3; + + printf("Bank%u=%sMhz ", i+1, freq[clock]); + } + puts("\n"); + + return 0; +} + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */ + setbits_be32(&gur->ddrclkdr, 0x000f000f); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); + setup_portals(); + + return 0; +} + +static const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + default: + return "150"; + } +} + +#define NUM_SRDS_BANKS 2 + +int misc_init_r(void) +{ + serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + u32 actual[NUM_SRDS_BANKS]; + unsigned int i; + u8 sw; + + sw = in_8(&CPLD_SW(2)) >> 2; + for (i = 0; i < NUM_SRDS_BANKS; i++) { + unsigned int clock = (sw >> (2 * i)) & 3; + switch (clock) { + case 1: + actual[i] = SRDS_PLLCR0_RFCK_SEL_100; + break; + case 2: + actual[i] = SRDS_PLLCR0_RFCK_SEL_125; + break; + default: + printf("Warning: SDREFCLK%u switch setting of '11' is " + "unsupported\n", i + 1); + break; + } + } + + for (i = 0; i < NUM_SRDS_BANKS; i++) { + u32 expected = in_be32(®s->bank[i].pllcr0); + expected &= SRDS_PLLCR0_RFCK_SEL_MASK; + if (expected != actual[i]) { + printf("Warning: SERDES bank %u expects reference clock" + " %sMHz, but actual is %sMHz\n", i + 1, + serdes_clock_to_string(expected), + serdes_clock_to_string(actual[i])); + } + } + + return 0; +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); +} diff --git a/arch/avr32/include/asm/initcalls.h b/board/freescale/p2041rdb/pci.c index 57a278b..1ab4cdf 100644 --- a/arch/avr32/include/asm/initcalls.h +++ b/board/freescale/p2041rdb/pci.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2005, 2006 Atmel Corporation + * Copyright 2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -19,12 +19,21 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef __ASM_AVR32_INITCALLS_H__ -#define __ASM_AVR32_INITCALLS_H__ -#include <config.h> +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/fsl_pci.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/fsl_serdes.h> -extern int cpu_init(void); -extern int timer_init(void); +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} -#endif /* __ASM_AVR32_INITCALLS_H__ */ +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/p2041rdb/tlb.c b/board/freescale/p2041rdb/tlb.c new file mode 100644 index 0000000..43f28ed --- /dev/null +++ b/board/freescale/p2041rdb/tlb.c @@ -0,0 +1,119 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_1M, 1), +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_4M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/gcplus/flash.c b/board/gcplus/flash.c index 8511582..ab567e8 100644 --- a/board/gcplus/flash.c +++ b/board/gcplus/flash.c @@ -225,7 +225,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -258,9 +258,6 @@ flash_erase(flash_info_t * info, int s_first, int s_last) printf("\n"); } - start = get_timer(0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -273,7 +270,7 @@ flash_erase(flash_info_t * info, int s_first, int s_last) printf("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); *addr = (FPW) 0x00500050; /* clear status register */ *addr = (FPW) 0x00200020; /* erase setup */ @@ -282,7 +279,7 @@ flash_erase(flash_info_t * info, int s_first, int s_last) while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -401,6 +398,7 @@ write_data(flash_info_t * info, ulong dest, FPW data) FPWV *addr = (FPWV *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -414,11 +412,11 @@ write_data(flash_info_t * info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/hymod/bsp.c b/board/hymod/bsp.c index 9a92941..2cd3707 100644 --- a/board/hymod/bsp.c +++ b/board/hymod/bsp.c @@ -75,14 +75,14 @@ DECLARE_GLOBAL_DATA_PTR; */ int -fpga_load (int mezz, uchar *addr, ulong size) +fpga_load(int mezz, const uchar *addr, ulong size) { hymod_conf_t *cp = &gd->bd->bi_hymod_conf; xlx_info_t *fp; xlx_iopins_t *fpgaio; volatile uchar *fpgabase; volatile uint cnt; - uchar *eaddr = addr + size; + const uchar *eaddr = addr + size; int result; if (mezz) diff --git a/board/idmr/flash.c b/board/idmr/flash.c index 57c9948..9f4ff2b 100644 --- a/board/idmr/flash.c +++ b/board/idmr/flash.c @@ -130,6 +130,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) int iflag, prot, sect; int rc = ERR_OK; int chip1; + ulong start; /* first look for protection bits */ @@ -170,7 +171,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - set_timer (0); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ volatile u16 *addr = @@ -191,7 +192,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) result = *addr; /* check timeout */ - if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; chip1 = TMO; break; @@ -248,6 +249,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) int rc = ERR_OK; int iflag; int chip1; + ulong start; /* * Check if Flash is (sufficiently) erased @@ -272,7 +274,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) *addr = data; /* arm simple, non interrupt dependent timer */ - set_timer (0); + start = get_timer(0); /* wait until flash is ready */ chip1 = 0; @@ -280,7 +282,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) result = *addr; /* check timeout */ - if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) { chip1 = ERR | TMO; break; } diff --git a/board/impa7/flash.c b/board/impa7/flash.c index d0c5880..6eae428 100644 --- a/board/impa7/flash.c +++ b/board/impa7/flash.c @@ -128,6 +128,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) { int flag, prot, sect; int rc = ERR_OK; + ulong start; if (info->flash_id == FLASH_UNKNOWN) return ERR_UNKNOWN_FLASH_TYPE; @@ -165,7 +166,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ vu_long *addr = (vu_long *) (info->start[sect]); @@ -174,7 +175,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr = 0x00D000D0; /* erase confirm */ while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer_masked () > + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = 0x00B000B0; /* suspend erase */ *addr = 0x00FF00FF; /* reset to read mode */ @@ -211,6 +212,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) ulong barf; int rc = ERR_OK; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ @@ -236,14 +238,14 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* read status register command */ *addr = 0x00700070; /* wait while polling the status register */ while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { rc = ERR_TIMOUT; /* suspend program command */ *addr = 0x00B000B0; diff --git a/board/imx31_phycore/config.mk b/board/imx31_phycore/config.mk deleted file mode 100644 index 0131edf..0000000 --- a/board/imx31_phycore/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x87f00000 diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c index 82daaa3..773900e 100644 --- a/board/imx31_phycore/imx31_phycore.c +++ b/board/imx31_phycore/imx31_phycore.c @@ -30,15 +30,24 @@ DECLARE_GLOBAL_DATA_PTR; -int dram_init (void) +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + return 0; +} + +int board_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */ + gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ return 0; } -int board_init (void) +int board_early_init_f(void) { __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ __REG(CSCR_L(0)) = 0x10000d03; @@ -62,9 +71,6 @@ int board_init (void) mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL); mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA); - gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */ - gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ - return 0; } diff --git a/arch/arm/cpu/arm920t/at91rm9200/Makefile b/board/in-circuit/grasshopper/Makefile index 7530e6a..a6c36c7 100644 --- a/arch/arm/cpu/arm920t/at91rm9200/Makefile +++ b/board/in-circuit/grasshopper/Makefile @@ -1,7 +1,10 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2001-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # +# Copyright (C) 2011 +# Corscience GmbH & Co.KG, Andreas Bießmann <biessmann@corscience.de> +# # See file CREDITS for list of people who contributed to this # project. # @@ -19,31 +22,17 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA -# include $(TOPDIR)/config.mk -LIB = $(obj)lib$(SOC).o - -SOBJS += lowlevel_init.o - -COBJS += bcm5221.o -COBJS += dm9161.o -COBJS += ether.o -COBJS += i2c.o -COBJS-$(CONFIG_KS8721_PHY) += ks8721.o -COBJS += lxt972.o -COBJS += reset.o -COBJS += spi.o -COBJS += timer.o -COBJS += usb.o +LIB := $(obj)lib$(BOARD).o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS-y)) +COBJS-y += $(BOARD).o -all: $(obj).depend $(LIB) +SRCS := $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) -$(LIB): $(OBJS) +$(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/in-circuit/grasshopper/grasshopper.c b/board/in-circuit/grasshopper/grasshopper.c new file mode 100644 index 0000000..475a759 --- /dev/null +++ b/board/in-circuit/grasshopper/grasshopper.c @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2011 + * Corscience GmbH & Co.KG, Andreas Bießmann <biessmann@corscience.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#include <asm/io.h> +#include <asm/sdram.h> +#include <asm/arch/clk.h> +#include <asm/arch/hmatrix.h> +#include <asm/arch/mmu.h> +#include <asm/arch/portmux.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { + { + .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, + .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, + .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_NONE, + }, { + .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, + .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, + .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_WRBACK, + }, +}; + +static const struct sdram_config sdram_config = { + /* Dual MT48LC16M16A2-7E (or equal) */ + .data_bits = SDRAM_DATA_32BIT, + .row_bits = 13, + .col_bits = 9, + .bank_bits = 2, + .cas = 2, + .twr = 2, + .trc = 7, + .trp = 2, + .trcd = 2, + .tras = 4, + .txsr = 7, + /* 7.81 us */ + .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, +}; + +int board_early_init_f(void) +{ + /* Enable SDRAM in the EBI mux */ + hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); + + portmux_enable_ebi(SDRAM_DATA_32BIT, 23, 0, PORTMUX_DRIVE_HIGH); + portmux_enable_usart0(PORTMUX_DRIVE_MIN); + portmux_enable_usart1(PORTMUX_DRIVE_MIN); +#if defined(CONFIG_MACB) + portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW); +#endif + + return 0; +} + +phys_size_t initdram(int board_type) +{ + unsigned long expected_size; + unsigned long actual_size; + void *sdram_base; + + sdram_base = uncached(EBI_SDRAM_BASE); + + expected_size = sdram_init(sdram_base, &sdram_config); + actual_size = get_ram_size(sdram_base, expected_size); + + if (expected_size != actual_size) + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + + return actual_size; +} + +int board_early_init_r(void) +{ + gd->bd->bi_phy_id[0] = 0x00; + return 0; +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bi) +{ + macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]); + return 0; +} +#endif +/* vim: set noet ts=8: */ diff --git a/board/innokom/flash.c b/board/innokom/flash.c index 8c95341..ed4b987 100644 --- a/board/innokom/flash.c +++ b/board/innokom/flash.c @@ -182,6 +182,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; int rc = ERR_OK; + ulong start; if (info->flash_id == FLASH_UNKNOWN) return ERR_UNKNOWN_FLASH_TYPE; @@ -218,7 +219,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) PRINTK("\n"); /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ u16 * volatile addr = (u16 * volatile)(info->start[sect]); @@ -235,7 +236,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) while ((*addr & 0x0080) != 0x0080) { PRINTK("."); - if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = 0x00B0; /* suspend erase*/ *addr = 0x00FF; /* read mode */ rc = ERR_TIMOUT; @@ -279,6 +280,7 @@ static int write_word (flash_info_t *info, ulong dest, ushort data) volatile u16 *addr = (u16 *)dest, val; int rc = ERR_OK; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) return ERR_NOT_ERASED; @@ -302,11 +304,11 @@ static int write_word (flash_info_t *info, ulong dest, ushort data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); /* wait while polling the status register */ while(((val = *addr) & 0x80) != 0x80) { - if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { rc = ERR_TIMOUT; *addr = 0xB0; /* suspend program command */ goto outahere; diff --git a/board/digsy_mtc/Makefile b/board/intercontrol/digsy_mtc/Makefile index a40076c..19f5b3a 100644 --- a/board/digsy_mtc/Makefile +++ b/board/intercontrol/digsy_mtc/Makefile @@ -7,10 +7,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := $(BOARD).o cmd_mtc.o +COBJS-y := $(BOARD).o cmd_mtc.o +COBJS-$(CONFIG_VIDEO) += cmd_disp.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) diff --git a/arch/arm/cpu/arm920t/at91rm9200/usb.c b/board/intercontrol/digsy_mtc/cmd_disp.c index 72355dc..d5f5efb 100644 --- a/arch/arm/cpu/arm920t/at91rm9200/usb.c +++ b/board/intercontrol/digsy_mtc/cmd_disp.c @@ -1,6 +1,6 @@ /* - * (C) Copyright 2006 - * DENX Software Engineering <mk@denx.de> + * (C) Copyright 2011 DENX Software Engineering, + * Anatolij Gustschin <agust@denx.de> * * See file CREDITS for list of people who contributed to this * project. @@ -22,32 +22,36 @@ */ #include <common.h> +#include <command.h> +#include <mpc5xxx.h> +#include <asm/io.h> -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) -# ifdef CONFIG_AT91RM9200 +#define GPIO_USB1_0 0x00010000 -#include <asm/arch/hardware.h> - -int usb_cpu_init(void) +static int cmd_disp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - /* Enable USB host clock. */ - *AT91C_PMC_SCER = AT91C_PMC_UHP; /* 48MHz clock enabled for UHP */ - *AT91C_PMC_PCER = 1 << AT91C_ID_UHP; /* Peripheral Clock Enable Register */ - return 0; -} + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; -int usb_cpu_stop(void) -{ - /* Initialization failed */ - *AT91C_PMC_PCDR = 1 << AT91C_ID_UHP; /* Peripheral Clock Disable Register */ - *AT91C_PMC_SCDR = AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */ - return 0; -} + if (argc < 2) { + printf("%s\n", + in_be32(&gpio->simple_dvo) & GPIO_USB1_0 ? "on" : "off"); + return 0; + } -int usb_cpu_init_fail(void) -{ - return usb_cpu_stop(); + if (!strncmp(argv[1], "on", 2)) { + setbits_be32(&gpio->simple_dvo, GPIO_USB1_0); + } else if (!strncmp(argv[1], "off", 3)) { + clrbits_be32(&gpio->simple_dvo, GPIO_USB1_0); + } else { + cmd_usage(cmdtp); + return 1; + } + return 0; } -# endif /* CONFIG_AT91RM9200 */ -#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ +U_BOOT_CMD(disp, 2, 1, cmd_disp, + "disp [on/off] - switch display on/off", + "\n - print display on/off status\n" + "on\n - turn on\n" + "off\n - turn off\n" +); diff --git a/board/digsy_mtc/cmd_mtc.c b/board/intercontrol/digsy_mtc/cmd_mtc.c index ba0c367..fffcee9 100644 --- a/board/digsy_mtc/cmd_mtc.c +++ b/board/intercontrol/digsy_mtc/cmd_mtc.c @@ -31,6 +31,8 @@ DECLARE_GLOBAL_DATA_PTR; +static uchar user_out; + static const char *led_names[] = { "diag", "can1", @@ -112,6 +114,8 @@ static int do_mtc_led(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) else pcmd.cmd_val2 = 0; + pcmd.user_out = user_out; + mtc_calculate_checksum(&pcmd); err = msp430_xfer(&pcmd, &prx); @@ -128,6 +132,7 @@ static int do_mtc_key(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) memset(&prx, 0, sizeof(prx)); pcmd.cmd = CMD_GET_VIM; + pcmd.user_out = user_out; mtc_calculate_checksum(&pcmd); err = msp430_xfer(&pcmd, &prx); @@ -160,6 +165,7 @@ static int do_mtc_digout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv pcmd.cmd = CMD_GET_VIM; pcmd.user_out = channel_mask; + user_out = channel_mask; mtc_calculate_checksum(&pcmd); err = msp430_xfer(&pcmd, &prx); @@ -187,6 +193,7 @@ static int do_mtc_digin(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[ memset(&prx, 0, sizeof(prx)); pcmd.cmd = CMD_GET_VIM; + pcmd.user_out = user_out; mtc_calculate_checksum(&pcmd); err = msp430_xfer(&pcmd, &prx); @@ -205,6 +212,7 @@ static int do_mtc_appreg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv rx_msp_cmd prx; int err; char buf[5]; + uchar appreg; /* read appreg */ memset(&pcmd, 0, sizeof(pcmd)); @@ -214,13 +222,34 @@ static int do_mtc_appreg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv pcmd.cmd_val0 = 5; /* max. Count */ pcmd.cmd_val1 = 5; /* max. Time */ pcmd.cmd_val2 = 0; /* =0 means read appreg */ + pcmd.user_out = user_out; mtc_calculate_checksum(&pcmd); err = msp430_xfer(&pcmd, &prx); + /* on success decide between read or write */ if (!err) { - sprintf(buf, "%d", prx.ack2); - setenv("appreg", buf); + if (argc == 2) { + appreg = simple_strtol(argv[1], NULL, 10); + if (appreg == 0) { + printf("mtc appreg: invalid parameter - " + "must be between 1 and 255\n"); + return -1; + } + memset(&pcmd, 0, sizeof(pcmd)); + pcmd.cmd = CMD_WD_PARA; + pcmd.cmd_val0 = prx.ack3; /* max. Count */ + pcmd.cmd_val1 = prx.ack0; /* max. Time */ + pcmd.cmd_val2 = appreg; /* !=0 means write appreg */ + pcmd.user_out = user_out; + memset(&prx, 0, sizeof(prx)); + + mtc_calculate_checksum(&pcmd); + err = msp430_xfer(&pcmd, &prx); + } else { + sprintf(buf, "%d", prx.ack2); + setenv("appreg", buf); + } } return err; @@ -236,6 +265,7 @@ static int do_mtc_version(cmd_tbl_t *cmdtp, int flag, int argc, char * const arg memset(&prx, 0, sizeof(prx)); pcmd.cmd = CMD_FW_VERSION; + pcmd.user_out = user_out; mtc_calculate_checksum(&pcmd); err = msp430_xfer(&pcmd, &prx); @@ -259,6 +289,7 @@ static int do_mtc_state(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[ pcmd.cmd = CMD_WD_WDSTATE; pcmd.cmd_val2 = 1; + pcmd.user_out = user_out; mtc_calculate_checksum(&pcmd); err = msp430_xfer(&pcmd, &prx); @@ -288,8 +319,10 @@ cmd_tbl_t cmd_mtc_sub[] = { "returns state of user key", ""), U_BOOT_CMD_MKENT(version, 0, 1, do_mtc_version, "returns firmware version of supervisor uC", ""), - U_BOOT_CMD_MKENT(appreg, 0, 1, do_mtc_appreg, - "reads appreg value and stores in environment variable 'appreg'", ""), + U_BOOT_CMD_MKENT(appreg, 1, 1, do_mtc_appreg, + "reads or writes appreg value and stores in environment " + "variable 'appreg'", + "[value] - value (1 - 255) to write to appreg"), U_BOOT_CMD_MKENT(digin, 1, 1, do_mtc_digin, "returns state of digital input", "<channel_num> - get state of digital input (1 or 2)\n"), @@ -342,8 +375,9 @@ U_BOOT_CMD(mtc, 5, 1, cmd_mtc, " [blink]: blink interval in 100ms steps (1 - 10; 0 = static)\n" "key - returns state of user key\n" "version - returns firmware version of supervisor uC\n" - "appreg - reads appreg value and stores in environment variable" - " 'appreg'\n" + "appreg [value] - reads (in environment variable 'appreg') or writes" + " appreg value\n" + " [value]: value (1 - 255) to write to appreg\n" "digin [channel] - returns state of digital input (1 or 2)\n" "digout <on|off> <on|off> - sets state of two digital outputs\n" "state - displays state\n" diff --git a/board/digsy_mtc/cmd_mtc.h b/board/intercontrol/digsy_mtc/cmd_mtc.h index 81714e3..81714e3 100644 --- a/board/digsy_mtc/cmd_mtc.h +++ b/board/intercontrol/digsy_mtc/cmd_mtc.h diff --git a/board/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c index 588face..784ba2a 100644 --- a/board/digsy_mtc/digsy_mtc.c +++ b/board/intercontrol/digsy_mtc/digsy_mtc.c @@ -48,6 +48,7 @@ #endif #include <libfdt.h> #include <fdt_support.h> +#include <i2c.h> DECLARE_GLOBAL_DATA_PTR; @@ -207,6 +208,69 @@ int checkboard(void) return 0; } +#if defined(CONFIG_VIDEO) + +#define GPIO_USB1_0 0x00010000 /* Power-On pin */ +#define GPIO_USB1_9 0x08 /* PX_~EN pin */ + +#define GPIO_EE_DO 0x10 /* PSC6_0 (DO) pin */ +#define GPIO_EE_CTS 0x20 /* PSC6_1 (CTS) pin */ +#define GPIO_EE_DI 0x10000000 /* PSC6_2 (DI) pin */ +#define GPIO_EE_CLK 0x20000000 /* PSC6_3 (CLK) pin */ + +#define GPT_GPIO_ON 0x00000034 /* GPT as simple GPIO, high */ + +/* ExBo I2C Addresses */ +#define EXBO_EE_I2C_ADDRESS 0x56 + +static void exbo_hw_init(void) +{ + struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT; + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_wu_gpio *wu_gpio = + (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; + unsigned char val; + + /* 1st, check if extension board is present */ + if (i2c_read(EXBO_EE_I2C_ADDRESS, 0, 1, &val, 1)) + return; + + /* configure IrDA pins (PSC6 port) as gpios */ + gpio->port_config &= 0xFF8FFFFF; + + /* Init for USB1_0, EE_CLK and EE_DI - Low */ + setbits_be32(&gpio->simple_ddr, + GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI); + clrbits_be32(&gpio->simple_ode, + GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI); + clrbits_be32(&gpio->simple_dvo, + GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI); + setbits_be32(&gpio->simple_gpioe, + GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI); + + /* Init for EE_DO, EE_CTS - Input */ + clrbits_8(&wu_gpio->ddr, GPIO_EE_DO | GPIO_EE_CTS); + setbits_8(&wu_gpio->enable, GPIO_EE_DO | GPIO_EE_CTS); + + /* Init for PX_~EN (USB1_9) - High */ + clrbits_8(&gpio->sint_ode, GPIO_USB1_9); + setbits_8(&gpio->sint_ddr, GPIO_USB1_9); + clrbits_8(&gpio->sint_inten, GPIO_USB1_9); + setbits_8(&gpio->sint_dvo, GPIO_USB1_9); + setbits_8(&gpio->sint_gpioe, GPIO_USB1_9); + + /* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */ + out_be32(&gpt[0].emsr, GPT_GPIO_ON); + /* Init for S Switch (GPIO4) - Timer_1 GPIO High */ + out_be32(&gpt[1].emsr, GPT_GPIO_ON); + + /* Power-On camera supply */ + setbits_be32(&gpio->simple_dvo, GPIO_USB1_0); +} +#else +static inline void exbo_hw_init(void) {} +#endif /* CONFIG_VIDEO */ + int board_early_init_r(void) { #ifdef CONFIG_MPC52XX_SPI @@ -224,6 +288,8 @@ int board_early_init_r(void) /* enable CS0 */ setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16)); + exbo_hw_init(); + #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) /* Low level USB init, required for proper kernel operation */ usb_cpu_init(); diff --git a/board/digsy_mtc/eeprom.h b/board/intercontrol/digsy_mtc/eeprom.h index 39e0378..fd11555 100644 --- a/board/digsy_mtc/eeprom.h +++ b/board/intercontrol/digsy_mtc/eeprom.h @@ -27,6 +27,6 @@ #define EEPROM_ADDR_IDENT 0 /* identification word offset */ #define EEPROM_ADDR_LEN_SYS 2 /* system area lenght offset */ #define EEPROM_ADDR_LEN_SYSCFG 4 /* system config area length offset */ -#define EEPROM_ADDR_ETHADDR 23 /* ethernet addres offset */ +#define EEPROM_ADDR_ETHADDR 23 /* ethernet address offset */ #endif diff --git a/board/digsy_mtc/is42s16800a-7t.h b/board/intercontrol/digsy_mtc/is42s16800a-7t.h index 64a81f4..64a81f4 100644 --- a/board/digsy_mtc/is42s16800a-7t.h +++ b/board/intercontrol/digsy_mtc/is42s16800a-7t.h diff --git a/board/digsy_mtc/is45s16800a2.h b/board/intercontrol/digsy_mtc/is45s16800a2.h index 6ab5c12..6ab5c12 100644 --- a/board/digsy_mtc/is45s16800a2.h +++ b/board/intercontrol/digsy_mtc/is45s16800a2.h diff --git a/board/ixdp425/config.mk b/board/ixdp425/config.mk deleted file mode 100644 index 509c894..0000000 --- a/board/ixdp425/config.mk +++ /dev/null @@ -1,2 +0,0 @@ -# -CONFIG_SYS_TEXT_BASE = 0x00f80000 diff --git a/board/ixdp425/flash.c b/board/ixdp425/flash.c deleted file mode 100644 index f1d9190..0000000 --- a/board/ixdp425/flash.c +++ /dev/null @@ -1,427 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <linux/byteorder/swab.h> - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) x -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer_masked () > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = (FPW) 0x00500050; /* clear status register cmd. */ - *addr = (FPW) 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, - (ulong) * addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/ixdp425/ixdp425.c b/board/ixdp425/ixdp425.c index a29d584..7269458 100644 --- a/board/ixdp425/ixdp425.c +++ b/board/ixdp425/ixdp425.c @@ -33,24 +33,82 @@ #include <malloc.h> #include <netdev.h> #include <asm/arch/ixp425.h> +#include <asm/io.h> +#ifdef CONFIG_PCI +#include <pci.h> +#include <asm/arch/ixp425pci.h> +#endif DECLARE_GLOBAL_DATA_PTR; +#define IXDP425_LED_PORT 0x52000000 /* 4-digit hex display */ + +int board_early_init_f(void) +{ + /* CS2: LED port */ + writel(0xbcff0002, IXP425_EXP_CS2); + writew(0x0001, IXDP425_LED_PORT); /* output postcode to LEDs */ + + return 0; +} + +#ifdef CONFIG_PCI +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_ixpdp425_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, PCI_ANY_ID, + pci_cfgfunc_config_device, + { 0x400, + 0x40000000, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } }, + + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x01, PCI_ANY_ID, + pci_cfgfunc_config_device, + { 0x800, + 0x40010000, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } }, + + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x02, PCI_ANY_ID, + pci_cfgfunc_config_device, + { 0xc00, + 0x40020000, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } }, + + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x03, PCI_ANY_ID, + pci_cfgfunc_config_device, + { 0x1000, + 0x40030000, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } }, + { } +}; +#endif + +struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_ixpdp425_config_table, +#endif +}; +#endif /* CONFIG_PCI */ + + /* * Miscelaneous platform dependent initialisations */ -int board_init (void) +int board_init(void) { + writew(0x0002, IXDP425_LED_PORT); /* output postcode to LEDs */ + +#ifdef CONFIG_IXDPG425 + /* arch number of IXDP */ + gd->bd->bi_arch_number = MACH_TYPE_IXDPG425; +#else /* arch number of IXDP */ gd->bd->bi_arch_number = MACH_TYPE_IXDP425; +#endif /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; #ifdef CONFIG_IXDPG425 - /* arch number of IXDP */ - gd->bd->bi_arch_number = MACH_TYPE_IXDPG425; - /* * Get realtek RTL8305 switch and SLIC out of reset */ @@ -60,19 +118,56 @@ int board_init (void) GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SLIC_RESET_N); /* - * Setup GPIO's for PCI INTA & INTB + * Setup GPIOs for PCI INTA & INTB */ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA_N); GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA_N); GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB_N); GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB_N); - /* - * Setup GPIO's for 33MHz clock output - */ - *IXP425_GPIO_GPCLKR = 0x01FF01FF; + /* Setup GPIOs for 33MHz clock output */ + writel(0x01FF01FF, IXP425_GPIO_GPCLKR); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); + + /* set GPIO8..11 interrupt type to active low */ + writel((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1, IXP425_GPIO_GPIT2R); + + /* clear pending interrupts */ + writel(-1, IXP425_GPIO_GPISR); + + /* assert PCI reset */ + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_SLIC_RESET_N); + + udelay(533); + + /* deassert PCI reset */ + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SLIC_RESET_N); + + udelay(533); + +#else /* IXDP425 */ + /* Setup GPIOs for 33MHz ExpBus and PCI clock output */ + writel(0x01FF01FF, IXP425_GPIO_GPCLKR); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_RESET_N); + + /* set GPIO8..11 interrupt type to active low */ + writel((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1, IXP425_GPIO_GPIT2R); + /* clear pending interrupts */ + writel(-1, IXP425_GPIO_GPISR); + + /* assert PCI reset */ + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PCI_RESET_N); + + udelay(533); + + /* deassert PCI reset */ + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_PCI_RESET_N); + + udelay(533); #endif return 0; @@ -98,30 +193,46 @@ int checkboard(void) } putc('\n'); - return (0); + return 0; } -int dram_init (void) +int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); + /* we can only map 64MB via PCI, so we limit memory + until a better solution is implemented. */ +#ifdef CONFIG_PCI + gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 64<<20); +#else + gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 256<<20); +#endif + return 0; } -#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) -extern struct pci_controller hose; -extern void pci_ixp_init(struct pci_controller * hose); - +#ifdef CONFIG_PCI void pci_init_board(void) { - extern void pci_ixp_init (struct pci_controller *hose); - pci_ixp_init(&hose); } + +/* + * dev 0 on the PCI bus is not the host bridge, so we have to override + * these functions in order to not skip PCI slot 0 during configuration. +*/ +int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) +{ + return 0; +} +int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) +{ + return 1; +} + #endif int board_eth_init(bd_t *bis) { - return pci_eth_init(bis); +#ifdef CONFIG_PCI + pci_eth_init(bis); +#endif + return cpu_eth_init(bis); } diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c index 269858c..25b99e8 100644 --- a/board/karo/tx25/tx25.c +++ b/board/karo/tx25/tx25.c @@ -70,18 +70,18 @@ void tx25_fec_init(void) writel(0x0, &padctl->pad_d11); /* drop PHY power and assert reset (low) */ - val = readl(&gpio4->dr) & ~((1 << 7) | (1 << 9)); - writel(val, &gpio4->dr); - val = readl(&gpio4->dir) | (1 << 7) | (1 << 9); - writel(val, &gpio4->dir); + val = readl(&gpio4->gpio_dr) & ~((1 << 7) | (1 << 9)); + writel(val, &gpio4->gpio_dr); + val = readl(&gpio4->gpio_dir) | (1 << 7) | (1 << 9); + writel(val, &gpio4->gpio_dir); mdelay(5); debug("resetting phy\n"); /* turn on PHY power leaving reset asserted */ - val = readl(&gpio4->dr) | 1 << 9; - writel(val, &gpio4->dr); + val = readl(&gpio4->gpio_dr) | 1 << 9; + writel(val, &gpio4->gpio_dr); mdelay(10); @@ -111,19 +111,19 @@ void tx25_fec_init(void) /* * set each to 1 and make each an output */ - val = readl(&gpio3->dr) | (1 << 10) | (1 << 11) | (1 << 12); - writel(val, &gpio3->dr); - val = readl(&gpio3->dir) | (1 << 10) | (1 << 11) | (1 << 12); - writel(val, &gpio3->dir); + val = readl(&gpio3->gpio_dr) | (1 << 10) | (1 << 11) | (1 << 12); + writel(val, &gpio3->gpio_dr); + val = readl(&gpio3->gpio_dir) | (1 << 10) | (1 << 11) | (1 << 12); + writel(val, &gpio3->gpio_dir); mdelay(22); /* this value came from RedBoot */ /* * deassert PHY reset */ - val = readl(&gpio4->dr) | 1 << 7; - writel(val, &gpio4->dr); - writel(val, &gpio4->dr); + val = readl(&gpio4->gpio_dr) | 1 << 7; + writel(val, &gpio4->gpio_dr); + writel(val, &gpio4->gpio_dr); mdelay(5); @@ -160,7 +160,7 @@ int board_late_init(void) int dram_init (void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1, + gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); return 0; } @@ -168,11 +168,11 @@ int dram_init (void) void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1, + gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); #if CONFIG_NR_DRAM_BANKS > 1 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2, + gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); #else diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 9be4c72..fce9d58 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -2,6 +2,9 @@ * (C) Copyright 2008 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * + * (C) Copyright 2011 + * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com + * * See file CREDITS for list of people who contributed to this * project. * @@ -22,9 +25,6 @@ */ #include <common.h> -#if defined(CONFIG_KM82XX) -#include <mpc8260.h> -#endif #include <ioports.h> #include <command.h> #include <malloc.h> @@ -38,44 +38,14 @@ #include <libfdt.h> #endif -#include "../common/common.h" +#include "common.h" #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) #include <i2c.h> +#endif static void i2c_write_start_seq(void); -static int i2c_make_abort(void); DECLARE_GLOBAL_DATA_PTR; -int ivm_calc_crc(unsigned char *buf, int len) -{ - const unsigned short crc_tab[16] = { - 0x0000, 0xCC01, 0xD801, 0x1400, - 0xF001, 0x3C00, 0x2800, 0xE401, - 0xA001, 0x6C00, 0x7800, 0xB401, - 0x5000, 0x9C01, 0x8801, 0x4400}; - - unsigned short crc = 0; /* final result */ - unsigned short r1 = 0; /* temp */ - unsigned char byte = 0; /* input buffer */ - int i; - - /* calculate CRC from array data */ - for (i = 0; i < len; i++) { - byte = buf[i]; - - /* lower 4 bits */ - r1 = crc_tab[crc & 0xF]; - crc = ((crc) >> 4) & 0x0FFF; - crc = crc ^ r1 ^ crc_tab[byte & 0xF]; - - /* upper 4 bits */ - r1 = crc_tab[crc & 0xF]; - crc = (crc >> 4) & 0x0FFF; - crc = crc ^ r1 ^ crc_tab[(byte >> 4) & 0xF]; - } - return crc; -} - /* * Set Keymile specific environment variables * Currently only some memory layout variables are calculated here @@ -111,355 +81,9 @@ int set_km_env(void) return 0; } -static int ivm_set_value(char *name, char *value) -{ - char tempbuf[256]; - - if (value != NULL) { - sprintf(tempbuf, "%s=%s", name, value); - return set_local_var(tempbuf, 0); - } else { - unset_local_var(name); - } - return 0; -} - -static int ivm_get_value(unsigned char *buf, int len, char *name, int off, - int check) -{ - unsigned short val; - unsigned char valbuf[30]; - - if ((buf[off + 0] != buf[off + 2]) && - (buf[off + 2] != buf[off + 4])) { - printf("%s Error corrupted %s\n", __func__, name); - val = -1; - } else { - val = buf[off + 0] + (buf[off + 1] << 8); - if ((val == 0) && (check == 1)) - val = -1; - } - sprintf((char *)valbuf, "%x", val); - ivm_set_value(name, (char *)valbuf); - return val; -} - -#define INV_BLOCKSIZE 0x100 -#define INV_DATAADDRESS 0x21 -#define INVENTORYDATASIZE (INV_BLOCKSIZE - INV_DATAADDRESS - 3) - -#define IVM_POS_SHORT_TEXT 0 -#define IVM_POS_MANU_ID 1 -#define IVM_POS_MANU_SERIAL 2 -#define IVM_POS_PART_NUMBER 3 -#define IVM_POS_BUILD_STATE 4 -#define IVM_POS_SUPPLIER_PART_NUMBER 5 -#define IVM_POS_DELIVERY_DATE 6 -#define IVM_POS_SUPPLIER_BUILD_STATE 7 -#define IVM_POS_CUSTOMER_ID 8 -#define IVM_POS_CUSTOMER_PROD_ID 9 -#define IVM_POS_HISTORY 10 -#define IVM_POS_SYMBOL_ONLY 11 - -static char convert_char(char c) -{ - return (c < ' ' || c > '~') ? '.' : c; -} - -static int ivm_findinventorystring(int type, - unsigned char* const string, - unsigned long maxlen, - unsigned char *buf) -{ - int xcode = 0; - unsigned long cr = 0; - unsigned long addr = INV_DATAADDRESS; - unsigned long size = 0; - unsigned long nr = type; - int stop = 0; /* stop on semicolon */ - - memset(string, '\0', maxlen); - switch (type) { - case IVM_POS_SYMBOL_ONLY: - nr = 0; - stop= 1; - break; - default: - nr = type; - stop = 0; - } - - /* Look for the requested number of CR. */ - while ((cr != nr) && (addr < INVENTORYDATASIZE)) { - if ((buf[addr] == '\r')) { - cr++; - } - addr++; - } - - /* - * the expected number of CR was found until the end of the IVM - * content --> fill string - */ - if (addr < INVENTORYDATASIZE) { - /* Copy the IVM string in the corresponding string */ - for (; (buf[addr] != '\r') && - ((buf[addr] != ';') || (!stop)) && - (size < (maxlen - 1) && - (addr < INVENTORYDATASIZE)); addr++) - { - size += sprintf((char *)string + size, "%c", - convert_char (buf[addr])); - } - - /* - * copy phase is done: check if everything is ok. If not, - * the inventory data is most probably corrupted: tell - * the world there is a problem! - */ - if (addr == INVENTORYDATASIZE) { - xcode = -1; - printf("Error end of string not found\n"); - } else if ((size >= (maxlen - 1)) && - (buf[addr] != '\r')) { - xcode = -1; - printf("string too long till next CR\n"); - } - } else { - /* - * some CR are missing... - * the inventory data is most probably corrupted - */ - xcode = -1; - printf("not enough cr found\n"); - } - return xcode; -} - -#define GET_STRING(name, which, len) \ - if (ivm_findinventorystring(which, valbuf, len, buf) == 0) { \ - ivm_set_value(name, (char *)valbuf); \ - } - -static int ivm_check_crc(unsigned char *buf, int block) -{ - unsigned long crc; - unsigned long crceeprom; - - crc = ivm_calc_crc(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2); - crceeprom = (buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 1] + \ - buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2] * 256); - if (crc != crceeprom) { - if (block == 0) - printf("Error CRC Block: %d EEprom: calculated: \ - %lx EEprom: %lx\n", block, crc, crceeprom); - return -1; - } - return 0; -} - -static int ivm_analyze_block2(unsigned char *buf, int len) -{ - unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN]; - unsigned long count; - - /* IVM_MacAddress */ - sprintf((char *)valbuf, "%pM", buf); - ivm_set_value("IVM_MacAddress", (char *)valbuf); - /* if an offset is defined, add it */ -#if defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET) - if (CONFIG_PIGGY_MAC_ADRESS_OFFSET > 0) { - unsigned long val = (buf[4] << 16) + (buf[5] << 8) + buf[6]; - - val += CONFIG_PIGGY_MAC_ADRESS_OFFSET; - buf[4] = (val >> 16) & 0xff; - buf[5] = (val >> 8) & 0xff; - buf[6] = val & 0xff; - sprintf((char *)valbuf, "%pM", buf); - } -#endif - if (getenv("ethaddr") == NULL) - setenv((char *)"ethaddr", (char *)valbuf); - - /* IVM_MacCount */ - count = (buf[10] << 24) + - (buf[11] << 16) + - (buf[12] << 8) + - buf[13]; - if (count == 0xffffffff) - count = 1; - sprintf((char *)valbuf, "%lx", count); - ivm_set_value("IVM_MacCount", (char *)valbuf); - return 0; -} - -int ivm_analyze_eeprom(unsigned char *buf, int len) -{ - unsigned short val; - unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN]; - unsigned char *tmp; - - if (ivm_check_crc(buf, 0) != 0) - return -1; - - ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, - "IVM_BoardId", 0, 1); - val = ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, - "IVM_HWKey", 6, 1); - if (val != 0xffff) { - sprintf((char *)valbuf, "%x", ((val / 100) % 10)); - ivm_set_value("IVM_HWVariant", (char *)valbuf); - sprintf((char *)valbuf, "%x", (val % 100)); - ivm_set_value("IVM_HWVersion", (char *)valbuf); - } - ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, - "IVM_Functions", 12, 0); - - GET_STRING("IVM_Symbol", IVM_POS_SYMBOL_ONLY, 8) - GET_STRING("IVM_DeviceName", IVM_POS_SHORT_TEXT, 64) - tmp = (unsigned char *) getenv("IVM_DeviceName"); - if (tmp) { - int len = strlen((char *)tmp); - int i = 0; - - while (i < len) { - if (tmp[i] == ';') { - ivm_set_value("IVM_ShortText", - (char *)&tmp[i + 1]); - break; - } - i++; - } - if (i >= len) - ivm_set_value("IVM_ShortText", NULL); - } else { - ivm_set_value("IVM_ShortText", NULL); - } - GET_STRING("IVM_ManufacturerID", IVM_POS_MANU_ID, 32) - GET_STRING("IVM_ManufacturerSerialNumber", IVM_POS_MANU_SERIAL, 20) - GET_STRING("IVM_ManufacturerPartNumber", IVM_POS_PART_NUMBER, 32) - GET_STRING("IVM_ManufacturerBuildState", IVM_POS_BUILD_STATE, 32) - GET_STRING("IVM_SupplierPartNumber", IVM_POS_SUPPLIER_PART_NUMBER, 32) - GET_STRING("IVM_DelieveryDate", IVM_POS_DELIVERY_DATE, 32) - GET_STRING("IVM_SupplierBuildState", IVM_POS_SUPPLIER_BUILD_STATE, 32) - GET_STRING("IVM_CustomerID", IVM_POS_CUSTOMER_ID, 32) - GET_STRING("IVM_CustomerProductID", IVM_POS_CUSTOMER_PROD_ID, 32) - - if (ivm_check_crc(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], 2) != 0) - return 0; - ivm_analyze_block2(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], - CONFIG_SYS_IVM_EEPROM_PAGE_LEN); - - return 0; -} - -int ivm_read_eeprom(void) -{ -#if defined(CONFIG_I2C_MUX) - I2C_MUX_DEVICE *dev = NULL; -#endif - uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; - uchar *buf; - unsigned dev_addr = CONFIG_SYS_IVM_EEPROM_ADR; - int ret; - -#if defined(CONFIG_I2C_MUX) - /* First init the Bus, select the Bus */ -#if defined(CONFIG_SYS_I2C_IVM_BUS) - dev = i2c_mux_ident_muxstring((uchar *)CONFIG_SYS_I2C_IVM_BUS); -#else - buf = (unsigned char *) getenv("EEprom_ivm"); - if (buf != NULL) - dev = i2c_mux_ident_muxstring(buf); -#endif - if (dev == NULL) { - printf("Error couldnt add Bus for IVM\n"); - return -1; - } - i2c_set_bus_num(dev->busid); -#endif - - buf = (unsigned char *) getenv("EEprom_ivm_addr"); - if (buf != NULL) - dev_addr = simple_strtoul((char *)buf, NULL, 16); - - /* add deblocking here */ - i2c_make_abort(); - - ret = i2c_read(dev_addr, 0, 1, i2c_buffer, - CONFIG_SYS_IVM_EEPROM_MAX_LEN); - if (ret != 0) { - printf ("Error reading EEprom\n"); - return -2; - } - - return ivm_analyze_eeprom(i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN); -} - -#if defined(CONFIG_SYS_I2C_INIT_BOARD) #define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */ #define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000)) -#if defined(CONFIG_KM_82XX) -#define SDA_MASK 0x00010000 -#define SCL_MASK 0x00020000 -void set_pin(int state, unsigned long mask) -{ - ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3); - - if (state) - setbits_be32(&iop->pdat, mask); - else - clrbits_be32(&iop->pdat, mask); - - setbits_be32(&iop->pdir, mask); -} - -static int get_pin(unsigned long mask) -{ - ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3); - - clrbits_be32(&iop->pdir, mask); - return 0 != (in_be32(&iop->pdat) & mask); -} - -static void set_sda(int state) -{ - set_pin(state, SDA_MASK); -} - -static void set_scl(int state) -{ - set_pin(state, SCL_MASK); -} - -static int get_sda(void) -{ - return get_pin(SDA_MASK); -} - -static int get_scl(void) -{ - return get_pin(SCL_MASK); -} - -#if defined(CONFIG_HARD_I2C) -static void setports(int gpio) -{ - ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3); - - if (gpio) { - clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK)); - clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK)); - } else { - setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK)); - clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK)); - setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK)); - } -} -#endif -#endif - #if !defined(CONFIG_MPC83xx) static void i2c_write_start_seq(void) { @@ -481,7 +105,7 @@ static void i2c_write_start_seq(void) * This I2C Deblocking mechanism was developed by Keymile in association * with Anatech and Atmel in 1998. */ -static int i2c_make_abort(void) +int i2c_make_abort(void) { #if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD) @@ -515,6 +139,7 @@ static int i2c_make_abort(void) sda_state = get_sda(); if (scl_state && sda_state) { ret = 0; + printf("[INFO] i2c abort after %d clocks\n", i); break; } } @@ -522,6 +147,8 @@ static int i2c_make_abort(void) if (ret == 0) for (i = 0; i < 5; i++) i2c_write_start_seq(); + else + printf("[ERROR] i2c abort failed\n"); /* respect stop setup time */ udelay(DELAY_ABORT_SEQ); @@ -536,7 +163,7 @@ static int i2c_make_abort(void) #endif return ret; } -#endif +#endif /* !MPC83xx */ #if defined(CONFIG_MPC83xx) static void i2c_write_start_seq(void) @@ -549,7 +176,7 @@ static void i2c_write_start_seq(void) out_8(&dev->cr, (I2C_CR_MEN)); } -static int i2c_make_abort(void) +int i2c_make_abort(void) { struct fsl_i2c *dev; dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); @@ -609,63 +236,6 @@ void i2c_init_board(void) /* Now run the AbortSequence() */ i2c_make_abort(); } -#endif -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -int fdt_set_node_and_value(void *blob, - char *nodename, - char *regname, - void *var, - int size) -{ - int ret = 0; - int nodeoffset = 0; - - nodeoffset = fdt_path_offset(blob, nodename); - if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, regname, var, - size); - if (ret < 0) - printf("ft_blob_update(): cannot set %s/%s " - "property err:%s\n", nodename, regname, - fdt_strerror(ret)); - } else { - printf("ft_blob_update(): cannot find %s node " - "err:%s\n", nodename, fdt_strerror(nodeoffset)); - } - return ret; -} - -int fdt_get_node_and_value(void *blob, - char *nodename, - char *propname, - void **var) -{ - int len; - int nodeoffset = 0; - - nodeoffset = fdt_path_offset(blob, nodename); - if (nodeoffset >= 0) { - *var = (void *)fdt_getprop(blob, nodeoffset, propname, &len); - if (len == 0) { - /* no value */ - printf("%s no value\n", __func__); - return -1; - } else if (len > 0) { - return len; - } else { - printf("libfdt fdt_getprop(): %s\n", - fdt_strerror(len)); - return -2; - } - } else { - printf("%s: cannot find %s node err:%s\n", __func__, - nodename, fdt_strerror(nodeoffset)); - return -3; - } -} -#endif #if !defined(MACH_TYPE_KM_KIRKWOOD) int ethernet_present(void) @@ -703,6 +273,7 @@ static int do_setboardid(cmd_tbl_t *cmdtp, int flag, int argc, } sprintf((char *)buf, "%s", p); setenv("boardid", (char *)buf); + printf("set boardid=%s\n", buf); p = get_local_var("IVM_HWKey"); if (p == NULL) { @@ -711,6 +282,8 @@ static int do_setboardid(cmd_tbl_t *cmdtp, int flag, int argc, } sprintf((char *)buf, "%s", p); setenv("hwkey", (char *)buf); + printf("set hwkey=%s\n", buf); + printf("Execute manually saveenv for persistent storage.\n"); return 0; } @@ -832,11 +405,7 @@ int do_checkboardidhwk(cmd_tbl_t *cmdtp, int flag, int argc, * Compare the values of the found entry in the * list with the valid values which are stored * in the inventory eeprom. If they are equal - * store the values in environment variables - * and save the environment. - * This can only happen once for the lifetime - * of a board, because once saved the function - * will never reach the while loop. + * set the values in environment variables. */ if ((bid == ivmbid) && (hwkey == ivmhwkey)) { char buf[10]; @@ -848,7 +417,6 @@ int do_checkboardidhwk(cmd_tbl_t *cmdtp, int flag, int argc, setenv("boardid", buf); sprintf(buf, "%lx", hwkey); setenv("hwkey", buf); - saveenv(); } } /* end while( ! found ) */ } @@ -859,7 +427,8 @@ int do_checkboardidhwk(cmd_tbl_t *cmdtp, int flag, int argc, printf("boardid=0x%3lX, hwkey=%ld\n", envbid, envhwkey); rc = 0; /* match */ } else { - printf("Error: env bId=0x%3lX, hwKey=%ld\n", envbid, envhwkey); + printf("Error: env boardid=0x%3lX, hwkey=%ld\n", envbid, + envhwkey); printf(" IVM bId=0x%3lX, hwKey=%ld\n", ivmbid, ivmhwkey); rc = 1; /* don't match */ } diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h index cee24d4..0fb19cf 100644 --- a/board/keymile/common/common.h +++ b/board/keymile/common/common.h @@ -124,7 +124,6 @@ struct bfticu_iomap { int ethernet_present(void); int ivm_read_eeprom(void); -void set_pin(int state, unsigned long mask); int set_km_env(void); int fdt_set_node_and_value(void *blob, @@ -138,4 +137,5 @@ int fdt_get_node_and_value(void *blob, void **var); int i2c_soft_read_pin(void); +int i2c_make_abort(void); #endif /* __KEYMILE_COMMON_H */ diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c new file mode 100644 index 0000000..d0cb0d2 --- /dev/null +++ b/board/keymile/common/ivm.c @@ -0,0 +1,342 @@ +/* + * (C) Copyright 2011 + * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <hush.h> +#include <i2c.h> +#include "common.h" + +int ivm_calc_crc(unsigned char *buf, int len) +{ + const unsigned short crc_tab[16] = { + 0x0000, 0xCC01, 0xD801, 0x1400, + 0xF001, 0x3C00, 0x2800, 0xE401, + 0xA001, 0x6C00, 0x7800, 0xB401, + 0x5000, 0x9C01, 0x8801, 0x4400}; + + unsigned short crc = 0; /* final result */ + unsigned short r1 = 0; /* temp */ + unsigned char byte = 0; /* input buffer */ + int i; + + /* calculate CRC from array data */ + for (i = 0; i < len; i++) { + byte = buf[i]; + + /* lower 4 bits */ + r1 = crc_tab[crc & 0xF]; + crc = ((crc) >> 4) & 0x0FFF; + crc = crc ^ r1 ^ crc_tab[byte & 0xF]; + + /* upper 4 bits */ + r1 = crc_tab[crc & 0xF]; + crc = (crc >> 4) & 0x0FFF; + crc = crc ^ r1 ^ crc_tab[(byte >> 4) & 0xF]; + } + return crc; +} + +static int ivm_set_value(char *name, char *value) +{ + char tempbuf[256]; + + if (value != NULL) { + sprintf(tempbuf, "%s=%s", name, value); + return set_local_var(tempbuf, 0); + } else { + unset_local_var(name); + } + return 0; +} + +static int ivm_get_value(unsigned char *buf, int len, char *name, int off, + int check) +{ + unsigned short val; + unsigned char valbuf[30]; + + if ((buf[off + 0] != buf[off + 2]) && + (buf[off + 2] != buf[off + 4])) { + printf("%s Error corrupted %s\n", __func__, name); + val = -1; + } else { + val = buf[off + 0] + (buf[off + 1] << 8); + if ((val == 0) && (check == 1)) + val = -1; + } + sprintf((char *)valbuf, "%x", val); + ivm_set_value(name, (char *)valbuf); + return val; +} + +#define INV_BLOCKSIZE 0x100 +#define INV_DATAADDRESS 0x21 +#define INVENTORYDATASIZE (INV_BLOCKSIZE - INV_DATAADDRESS - 3) + +#define IVM_POS_SHORT_TEXT 0 +#define IVM_POS_MANU_ID 1 +#define IVM_POS_MANU_SERIAL 2 +#define IVM_POS_PART_NUMBER 3 +#define IVM_POS_BUILD_STATE 4 +#define IVM_POS_SUPPLIER_PART_NUMBER 5 +#define IVM_POS_DELIVERY_DATE 6 +#define IVM_POS_SUPPLIER_BUILD_STATE 7 +#define IVM_POS_CUSTOMER_ID 8 +#define IVM_POS_CUSTOMER_PROD_ID 9 +#define IVM_POS_HISTORY 10 +#define IVM_POS_SYMBOL_ONLY 11 + +static char convert_char(char c) +{ + return (c < ' ' || c > '~') ? '.' : c; +} + +static int ivm_findinventorystring(int type, + unsigned char *const string, + unsigned long maxlen, + unsigned char *buf) +{ + int xcode = 0; + unsigned long cr = 0; + unsigned long addr = INV_DATAADDRESS; + unsigned long size = 0; + unsigned long nr = type; + int stop = 0; /* stop on semicolon */ + + memset(string, '\0', maxlen); + switch (type) { + case IVM_POS_SYMBOL_ONLY: + nr = 0; + stop = 1; + break; + default: + nr = type; + stop = 0; + } + + /* Look for the requested number of CR. */ + while ((cr != nr) && (addr < INVENTORYDATASIZE)) { + if ((buf[addr] == '\r')) + cr++; + addr++; + } + + /* + * the expected number of CR was found until the end of the IVM + * content --> fill string + */ + if (addr < INVENTORYDATASIZE) { + /* Copy the IVM string in the corresponding string */ + for (; (buf[addr] != '\r') && + ((buf[addr] != ';') || (!stop)) && + (size < (maxlen - 1) && + (addr < INVENTORYDATASIZE)); addr++) { + size += sprintf((char *)string + size, "%c", + convert_char (buf[addr])); + } + + /* + * copy phase is done: check if everything is ok. If not, + * the inventory data is most probably corrupted: tell + * the world there is a problem! + */ + if (addr == INVENTORYDATASIZE) { + xcode = -1; + printf("Error end of string not found\n"); + } else if ((size >= (maxlen - 1)) && + (buf[addr] != '\r')) { + xcode = -1; + printf("string too long till next CR\n"); + } + } else { + /* + * some CR are missing... + * the inventory data is most probably corrupted + */ + xcode = -1; + printf("not enough cr found\n"); + } + return xcode; +} + +#define GET_STRING(name, which, len) \ + if (ivm_findinventorystring(which, valbuf, len, buf) == 0) { \ + ivm_set_value(name, (char *)valbuf); \ + } + +static int ivm_check_crc(unsigned char *buf, int block) +{ + unsigned long crc; + unsigned long crceeprom; + + crc = ivm_calc_crc(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2); + crceeprom = (buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 1] + \ + buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2] * 256); + if (crc != crceeprom) { + if (block == 0) + printf("Error CRC Block: %d EEprom: calculated: \ + %lx EEprom: %lx\n", block, crc, crceeprom); + return -1; + } + return 0; +} + +static int ivm_analyze_block2(unsigned char *buf, int len) +{ + unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN]; + unsigned long count; + + /* IVM_MacAddress */ + sprintf((char *)valbuf, "%pM", buf); + ivm_set_value("IVM_MacAddress", (char *)valbuf); + /* if an offset is defined, add it */ +#if defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET) + if (CONFIG_PIGGY_MAC_ADRESS_OFFSET > 0) { + unsigned long val = (buf[4] << 16) + (buf[5] << 8) + buf[6]; + + val += CONFIG_PIGGY_MAC_ADRESS_OFFSET; + buf[4] = (val >> 16) & 0xff; + buf[5] = (val >> 8) & 0xff; + buf[6] = val & 0xff; + sprintf((char *)valbuf, "%pM", buf); + } +#endif + setenv((char *)"ethaddr", (char *)valbuf); + + /* IVM_MacCount */ + count = (buf[10] << 24) + + (buf[11] << 16) + + (buf[12] << 8) + + buf[13]; + if (count == 0xffffffff) + count = 1; + sprintf((char *)valbuf, "%lx", count); + ivm_set_value("IVM_MacCount", (char *)valbuf); + return 0; +} + +int ivm_analyze_eeprom(unsigned char *buf, int len) +{ + unsigned short val; + unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN]; + unsigned char *tmp; + + if (ivm_check_crc(buf, 0) != 0) + return -1; + + ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, + "IVM_BoardId", 0, 1); + val = ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, + "IVM_HWKey", 6, 1); + if (val != 0xffff) { + sprintf((char *)valbuf, "%x", ((val / 100) % 10)); + ivm_set_value("IVM_HWVariant", (char *)valbuf); + sprintf((char *)valbuf, "%x", (val % 100)); + ivm_set_value("IVM_HWVersion", (char *)valbuf); + } + ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, + "IVM_Functions", 12, 0); + + GET_STRING("IVM_Symbol", IVM_POS_SYMBOL_ONLY, 8) + GET_STRING("IVM_DeviceName", IVM_POS_SHORT_TEXT, 64) + tmp = (unsigned char *) getenv("IVM_DeviceName"); + if (tmp) { + int len = strlen((char *)tmp); + int i = 0; + + while (i < len) { + if (tmp[i] == ';') { + ivm_set_value("IVM_ShortText", + (char *)&tmp[i + 1]); + break; + } + i++; + } + if (i >= len) + ivm_set_value("IVM_ShortText", NULL); + } else { + ivm_set_value("IVM_ShortText", NULL); + } + GET_STRING("IVM_ManufacturerID", IVM_POS_MANU_ID, 32) + GET_STRING("IVM_ManufacturerSerialNumber", IVM_POS_MANU_SERIAL, 20) + GET_STRING("IVM_ManufacturerPartNumber", IVM_POS_PART_NUMBER, 32) + GET_STRING("IVM_ManufacturerBuildState", IVM_POS_BUILD_STATE, 32) + GET_STRING("IVM_SupplierPartNumber", IVM_POS_SUPPLIER_PART_NUMBER, 32) + GET_STRING("IVM_DelieveryDate", IVM_POS_DELIVERY_DATE, 32) + GET_STRING("IVM_SupplierBuildState", IVM_POS_SUPPLIER_BUILD_STATE, 32) + GET_STRING("IVM_CustomerID", IVM_POS_CUSTOMER_ID, 32) + GET_STRING("IVM_CustomerProductID", IVM_POS_CUSTOMER_PROD_ID, 32) + + if (ivm_check_crc(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], 2) != 0) + return 0; + ivm_analyze_block2(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], + CONFIG_SYS_IVM_EEPROM_PAGE_LEN); + + return 0; +} + +int ivm_read_eeprom(void) +{ +#if defined(CONFIG_I2C_MUX) + I2C_MUX_DEVICE *dev = NULL; +#endif + uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; + uchar *buf; + unsigned long dev_addr = CONFIG_SYS_IVM_EEPROM_ADR; + int ret; + +#if defined(CONFIG_I2C_MUX) + /* First init the Bus, select the Bus */ +#if defined(CONFIG_SYS_I2C_IVM_BUS) + dev = i2c_mux_ident_muxstring((uchar *)CONFIG_SYS_I2C_IVM_BUS); +#else + buf = (unsigned char *) getenv("EEprom_ivm"); + if (buf != NULL) + dev = i2c_mux_ident_muxstring(buf); +#endif + if (dev == NULL) { + printf("Error couldnt add Bus for IVM\n"); + return -1; + } + i2c_set_bus_num(dev->busid); +#endif + + buf = (unsigned char *) getenv("EEprom_ivm_addr"); + if (buf != NULL) { + ret = strict_strtoul((char *)buf, 16, &dev_addr); + if (ret != 0) + return -3; + } + + /* add deblocking here */ + i2c_make_abort(); + + ret = i2c_read(dev_addr, 0, 1, i2c_buffer, + CONFIG_SYS_IVM_EEPROM_MAX_LEN); + if (ret != 0) { + printf("Error reading EEprom\n"); + return -2; + } + + return ivm_analyze_eeprom(i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN); +} diff --git a/board/keymile/common/keymile_hdlc_enet.h b/board/keymile/common/keymile_hdlc_enet.h deleted file mode 100644 index db1560f..0000000 --- a/board/keymile/common/keymile_hdlc_enet.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * (C) Copyright 2008 - * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _KEYMILE_HDLC_ENET_H_ -#define _KEYMILE_HDLC_ENET_H_ - -/* Unfortuantely, we have do this to get the flag defines in the cbd_t */ -#ifdef CONFIG_KM8XX -#include <commproc.h> -#endif -#ifdef CONFIG_MGCOGE -#include <mpc8260.h> -#include <asm/cpm_8260.h> -#endif - -/* - * Defines for the ICN protocol used for communication over HDLC - * on the backplane between MGSUVDs and MGCOGEs. - */ - -/* - * MAC which is reserved for communication (0x00 - 0xff in the last byte, - * which is the slot number) - */ - -/* - * A DLL frame looks like this: - * 8 bit | 8 bit | 8 bit | 8 bit | n * 8 bit| 16 bit| 8 bit - * opening| destination| source | application| data | FCS | closing - * flag | address | address| | | | flag - * (HW) (APP) (APP) (APP) (APP) (HW) (HW) - */ - -/* - * The opening flag, the FCS and the closing flag are set by the hardware so - * they are not reflected in this struct. - */ -struct icn_hdr { - unsigned char dest_addr; - unsigned char src_addr; - unsigned char application; -} __attribute__((packed)); - -#define ICNHDR_LEN (sizeof(struct icn_hdr)) -#define CRC_LEN (sizeof(short)) -/* bytes to remove from packet before sending it upstream */ -#define REMOVE (ICNHDR_LEN + CRC_LEN) - -struct icn_frame { - struct icn_hdr hdr; - unsigned char data[0]; /* a place holder */ -} __attribute__((packed)); - -/* Address field */ -#define HDLC_UUA 0x00 /* Unicast Unit Address */ -#define HDLC_UUA_MASK 0x3f /* the last 6 bits contain the slot number */ -#define SET_HDLC_UUA(x) ((HDLC_UUA | ((x) & HDLC_UUA_MASK))) -#define HDLC_UACUA 0x7f /* Unicast Active Control Unit Address */ -#define HDLC_BCAST 0xff /* broadcast */ - -/* Application field */ -#define MGS_UUSP 0x00 -#define MGS_UREP 0x01 -#define MGS_IUP 0x02 -#define MGS_UTA 0x03 -#define MGS_MDS 0x04 -#define MGS_ITIME 0x05 -/* added by DENX */ -#define MGS_NETCONS 0x06 /* netconsole */ -#define MGS_TFTP 0x07 - -/* Useful defines for buffer sizes, etc. */ -#define HDLC_PKTBUFSRX 32 -#define MAX_FRAME_LENGTH 1500 /* ethernet frame size */ - /* 14 + 28 */ -#define INET_HDR_SIZE (ETHER_HDR_SIZE + IP_HDR_SIZE) -#define INET_HDR_ALIGN (((INET_HDR_SIZE + PKTALIGN - 1) / PKTALIGN) * PKTALIGN) -/* INET_HDR_SIZE is stripped off */ -#define PKT_MAXBLR_SIZE (MAX_FRAME_LENGTH + INET_HDR_ALIGN) - -/* - * It is too slow to read always the port numbers and IP addresses from the - * string variables. - * cachedNumbers is meant to cache it. - * THIS IS ONLY A SPEED IMPROVEMENT! - */ -enum { - IP_ADDR = 0, /* getenv_IPaddr("serverip"); */ - IP_SERVER, /* getenv_IPaddr("ipaddr"); */ - TFTP_SRC_PORT, /* simple_strtol(getenv("tftpsrcp"), NULL, 10); */ - TFTP_DST_PORT, /* simple_strtol(getenv("tftpdstp"), NULL, 10); */ - NETCONS_PORT, /* simple_strtol(getenv("ncip"), NULL, 10); */ - CACHEDNUMBERS -}; - -#define WELL_KNOWN_PORT 69 /* Well known TFTP port # */ - -/* define this to create a test commend (htest) */ -#undef TEST_IT -#ifdef TEST_IT -/* have to save a copy of the eth_device for the test command's use */ -struct eth_device *seth; -#endif -/* define this for outputting of received packets */ -#undef TEST_RX -/* define this for outputting of packets being sent */ -#undef TEST_TX - -#endif /* _KEYMILE_HDLC_ENET_H_ */ diff --git a/board/keymile/km82xx/Makefile b/board/keymile/km82xx/Makefile index a2b9da4..b9709d9 100644 --- a/board/keymile/km82xx/Makefile +++ b/board/keymile/km82xx/Makefile @@ -28,7 +28,7 @@ endif LIB = $(obj)lib$(BOARD).o -COBJS := $(BOARD).o ../common/common.o +COBJS := $(BOARD).o ../common/common.o ../common/ivm.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c index d453d25..0e50b0b 100644 --- a/board/keymile/km82xx/km82xx.c +++ b/board/keymile/km82xx/km82xx.c @@ -315,6 +315,8 @@ int last_stage_init(void) } #ifdef CONFIG_MGCOGE3NE +static void set_pin(int state, unsigned long mask); + /* * For mgcoge3ne boards, the mgcoge3un control is controlled from * a GPIO line on the PPC CPU. If bobcatreset is set the line @@ -363,6 +365,64 @@ int hush_init_var(void) return 0; } +#define SDA_MASK 0x00010000 +#define SCL_MASK 0x00020000 + +static void set_pin(int state, unsigned long mask) +{ + ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3); + + if (state) + setbits_be32(&iop->pdat, mask); + else + clrbits_be32(&iop->pdat, mask); + + setbits_be32(&iop->pdir, mask); +} + +static int get_pin(unsigned long mask) +{ + ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3); + + clrbits_be32(&iop->pdir, mask); + return 0 != (in_be32(&iop->pdat) & mask); +} + +void set_sda(int state) +{ + set_pin(state, SDA_MASK); +} + +void set_scl(int state) +{ + set_pin(state, SCL_MASK); +} + +int get_sda(void) +{ + return get_pin(SDA_MASK); +} + +int get_scl(void) +{ + return get_pin(SCL_MASK); +} + +#if defined(CONFIG_HARD_I2C) +static void setports(int gpio) +{ + ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3); + + if (gpio) { + clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK)); + clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK)); + } else { + setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK)); + clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK)); + setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK)); + } +} +#endif #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/board/keymile/km83xx/Makefile b/board/keymile/km83xx/Makefile index 2fa84f3..7bf64b4 100644 --- a/board/keymile/km83xx/Makefile +++ b/board/keymile/km83xx/Makefile @@ -28,7 +28,7 @@ endif LIB = $(obj)lib$(BOARD).o -COBJS += $(BOARD).o ../common/common.o +COBJS += $(BOARD).o ../common/common.o ../common/ivm.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile index 6bcfb25..4907030 100644 --- a/board/keymile/km_arm/Makefile +++ b/board/keymile/km_arm/Makefile @@ -29,7 +29,7 @@ endif LIB = $(obj)lib$(BOARD).o -COBJS := $(BOARD).o ../common/common.o +COBJS := $(BOARD).o ../common/common.o ../common/ivm.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index d86acc9..a8f2b23 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -130,10 +130,12 @@ int startup_allowed(void) return 1; return 0; } +#endif +#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) /* - * mgcoge3un has always ethernet present. Its connected to the 6061 switch - * and provides ICNev and piggy4 connections. + * These two boards have always ethernet present. Its connected to the mv + * switch. */ int ethernet_present(void) { @@ -319,7 +321,7 @@ int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ /* Fix this */ - gd->ram_size = get_ram_size((volatile void *)kw_sdram_bar(0), + gd->ram_size = get_ram_size((void *)kw_sdram_bar(0), kw_sdram_bs(0)); return 0; } @@ -335,7 +337,42 @@ void dram_init_banksize(void) } } -/* Configure and enable MV88E1118 PHY */ +#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) + +#define PHY_LED_SEL 0x18 +#define PHY_LED0_LINK (0x5) +#define PHY_LED1_ACT (0x8<<4) +#define PHY_LED2_INT (0xe<<8) +#define PHY_SPEC_CTRL 0x1c +#define PHY_RGMII_CLK_STABLE (0x1<<10) +#define PHY_CLSA (0x1<<1) + +/* Configure and enable MV88E3018 PHY */ +void reset_phy(void) +{ + char *name = "egiga0"; + unsigned short reg; + + if (miiphy_set_current_dev(name)) + return; + + /* RGMII clk transition on data stable */ + if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, ®) != 0) + printf("Error reading PHY spec ctrl reg\n"); + if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, + reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0) + printf("Error writing PHY spec ctrl reg\n"); + + /* leds setup */ + if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL, + PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0) + printf("Error writing PHY LED reg\n"); + + /* reset the phy */ + miiphy_reset(name, CONFIG_PHY_BASE_ADR); +} +#else +/* Configure and enable MV88E1118 PHY on the piggy*/ void reset_phy(void) { char *name = "egiga0"; @@ -346,6 +383,8 @@ void reset_phy(void) /* reset the phy */ miiphy_reset(name, CONFIG_PHY_BASE_ADR); } +#endif + #if defined(CONFIG_HUSH_INIT_VAR) int hush_init_var(void) diff --git a/board/keymile/scripts/README b/board/keymile/scripts/README index 86c2b5a..7fbcf74 100644 --- a/board/keymile/scripts/README +++ b/board/keymile/scripts/README @@ -1,23 +1,31 @@ -debug-common-env.txt +These scripts are needed for our development usecases. Copy this directory +into your tftp root directory to be able to use this scripts. +cp -r <u-boot-repo>/board/keymile/scripts <your_tftp_root>/ + +To load and configure these usecase, two environment variables in the u-boot +default environment must be parsed: +run develop : setup environment to configure for rootfs via nfs +run ramfs : setup environment to configure for rootfs in ram + +Last change: 20.05.2011 + +develop-common.txt +============================ +This file defines variables for working with rootfs via nfs for powerpc and +arm. + +develop-<arch>.txt ============================ -This file defines environment variables which are valid for powerpc boards -and for arm boards. +This file defines architecture specific variables for working with rootfs via +nfs arm. -addramfs: add phram device for the rootfilesysten in ram -develop: for development, laod kernel via tftp and mount rootfs via NFS -nfsargs: default arguments for nfs boot -ramfs: load rootfilesystem in RAM kernel -rootfsfile: loacation of the rootfs file for ramfs -setramfspram: compute PRAM size for ramfs target -setrootfsaddr: compute rootfilesystem address for phram -tftpkernel: load a kernel with tftp into ram -tftpramfs: load rootfs with tftp into ram -debug-ppc-env.txt +ramfs-common.txt ============================ -fdt_file: location of the dtb file on the tftp server -tftpfdt: load dtb file and set fdt address +This file defines variables for working with rootfs inside the ram for powerpc +and arm. -debug-arm-env.txt +ramfs-<arch>.txt ============================ -tftpfdt: for arm only a dummy variable, because we have no fdt on arm +This file defines architecture specific variables for working with rootfs inside +ram. diff --git a/board/keymile/scripts/debug-arm-env.txt b/board/keymile/scripts/debug-arm-env.txt deleted file mode 100644 index 84498af..0000000 --- a/board/keymile/scripts/debug-arm-env.txt +++ /dev/null @@ -1,2 +0,0 @@ -debug_env_common=tftpboot 0x200000 scripts/debug-common-env.txt && env import -t 0x200000 ${filesize} -tftpfdt=true diff --git a/board/keymile/scripts/debug-common-env.txt b/board/keymile/scripts/debug-common-env.txt deleted file mode 100644 index 1fd4b0c..0000000 --- a/board/keymile/scripts/debug-common-env.txt +++ /dev/null @@ -1,9 +0,0 @@ -addramfs=setenv bootargs "${bootargs} phram.phram=rootfs${boot_bank},${rootfsaddr},${rootfssize}" -develop=setenv subbootcmds "tftpfdt tftpkernel nfsargs ${commonargs} boot " && setenv bootcmd 'run bootrunner' && setenv altbootcmd 'run bootcmd' && km_setboardid && saveenv && reset -nfsargs=setenv bootargs ubi.mtd=ubi0 root=/dev/nfs rw nfsroot=${serverip}:${rootpath} -ramfs=setenv actual_bank -1 && setenv subbootcmds "tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs ${commonargs} addpanic addramfs boot " && setenv bootcmd 'run bootrunner' && setenv altbootcmd 'run bootcmd' && run setboardid && run setramfspram && run setpnvramaddr && saveenv && reset -rootfsfile=${hostname}/rootfsImage -setramfspram=setexpr value 0 + ${reservedpram} && setexpr value 0x${value} + ${rootfssize} && setexpr value 0x${value} + ${varsize} && setexpr value 0x${value} + ${pnvramsize} && setexpr value 0x${value} / 0x400 && setenv pram 0x${value} -tftpkernel=tftpboot ${kernel_addr_r} ${hostname}/uImage && setenv actual_kernel_addr ${kernel_addr_r} -tftpramfs=tftpboot ${rootfsaddr} ${hostname}/rootfsImage && setenv loadaddr -setrootfsaddr=setexpr value ${pnvramsize} - ${rootfssize} && setenv rootfsaddr 0x${value} diff --git a/board/keymile/scripts/debug-ppc-env.txt b/board/keymile/scripts/debug-ppc-env.txt deleted file mode 100644 index 3c06ff1..0000000 --- a/board/keymile/scripts/debug-ppc-env.txt +++ /dev/null @@ -1,2 +0,0 @@ -debug_env_common=tftpboot 0x200000 scripts/debug-common-env.txt && env import -t 0x200000 ${filesize} -tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb && setenv actual_fdt_addr ${fdt_addr_r} diff --git a/board/keymile/scripts/develop-arm.txt b/board/keymile/scripts/develop-arm.txt new file mode 100644 index 0000000..922afea --- /dev/null +++ b/board/keymile/scripts/develop-arm.txt @@ -0,0 +1,2 @@ +setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure +tftpfdt=true diff --git a/board/keymile/scripts/develop-common.txt b/board/keymile/scripts/develop-common.txt new file mode 100644 index 0000000..3ccd039 --- /dev/null +++ b/board/keymile/scripts/develop-common.txt @@ -0,0 +1,6 @@ +altbootcmd=run ${subbootcmds} +bootcmd=run ${subbootcmds} +configure=km_setboardid && saveenv && reset +subbootcmds=tftpfdt tftpkernel nfsargs add_default boot +nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:/opt/eldk/${arch} +tftpkernel=tftpboot ${load_addr_r} ${hostname}/uImage diff --git a/board/keymile/scripts/develop-ppc_82xx.txt b/board/keymile/scripts/develop-ppc_82xx.txt new file mode 100644 index 0000000..909f6a3 --- /dev/null +++ b/board/keymile/scripts/develop-ppc_82xx.txt @@ -0,0 +1,2 @@ +setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure +tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb diff --git a/board/keymile/scripts/develop-ppc_8xx.txt b/board/keymile/scripts/develop-ppc_8xx.txt new file mode 100644 index 0000000..909f6a3 --- /dev/null +++ b/board/keymile/scripts/develop-ppc_8xx.txt @@ -0,0 +1,2 @@ +setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure +tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb diff --git a/board/keymile/scripts/ramfs-arm.txt b/board/keymile/scripts/ramfs-arm.txt new file mode 100644 index 0000000..79974f1 --- /dev/null +++ b/board/keymile/scripts/ramfs-arm.txt @@ -0,0 +1,2 @@ +setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure +tftpfdt=true diff --git a/board/keymile/scripts/ramfs-common.txt b/board/keymile/scripts/ramfs-common.txt new file mode 100644 index 0000000..9315500 --- /dev/null +++ b/board/keymile/scripts/ramfs-common.txt @@ -0,0 +1,12 @@ +addramfs=setenv bootargs "${bootargs} mem=${rootfsaddr} phram.phram=rootfs${boot_bank},${rootfsaddr},${rootfssize}" +actual_bank=-1 +altbootcmd=run ${subbootcmds} +bootcmd=run ${subbootcmds} +subbootcmds=tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs add_default addpanic addramfs boot +nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} +configure=km_setboardid && run setramfspram && saveenv && reset +setramfspram=setexpr value 0 + ${rootfssize} && setexpr value 0x${value} / 0x400 && setexpr value 0x${value} + ${pram} && setenv pram 0x${value} +rootfsfile=${hostname}/rootfsImage +setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value} +tftpkernel=tftpboot ${load_addr_r} ${hostname}/uImage +tftpramfs=tftpboot ${rootfsaddr} ${hostname}/rootfsImage diff --git a/board/keymile/scripts/ramfs-ppc_82xx.txt b/board/keymile/scripts/ramfs-ppc_82xx.txt new file mode 100644 index 0000000..970927a --- /dev/null +++ b/board/keymile/scripts/ramfs-ppc_82xx.txt @@ -0,0 +1,2 @@ +setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure +tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb diff --git a/board/keymile/scripts/ramfs-ppc_8xx.txt b/board/keymile/scripts/ramfs-ppc_8xx.txt new file mode 100644 index 0000000..970927a --- /dev/null +++ b/board/keymile/scripts/ramfs-ppc_8xx.txt @@ -0,0 +1,2 @@ +setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure +tftpfdt=tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb diff --git a/board/lart/flash.c b/board/lart/flash.c index 29a331e..408c884 100644 --- a/board/lart/flash.c +++ b/board/lart/flash.c @@ -250,6 +250,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) ulong result; int iflag, cflag, prot, sect; int rc = ERR_OK; + ulong start; /* first look for protection bits */ @@ -291,7 +292,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ @@ -305,7 +306,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) do { /* check timeout */ - if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = PUZZLE_TO_FLASH(CMD_SUSPEND); result = BIT_TIMEOUT; @@ -354,6 +355,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) ulong result; int rc = ERR_OK; int cflag, iflag; + ulong start; /* Check if Flash is (sufficiently) erased */ @@ -377,13 +379,13 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); /* wait until flash is ready */ do { /* check timeout */ - if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = PUZZLE_TO_FLASH(CMD_SUSPEND); result = BIT_TIMEOUT; diff --git a/board/logicpd/imx27lite/imx27lite.c b/board/logicpd/imx27lite/imx27lite.c index 6eb5cc2..2b273ac 100644 --- a/board/logicpd/imx27lite/imx27lite.c +++ b/board/logicpd/imx27lite/imx27lite.c @@ -38,7 +38,7 @@ int board_init (void) gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; #ifdef CONFIG_MXC_UART - mx27_uart_init_pins(); + mx27_uart1_init_pins(); #endif #ifdef CONFIG_FEC_MXC mx27_fec_init_pins(); @@ -67,7 +67,7 @@ int board_init (void) int dram_init (void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } @@ -75,11 +75,11 @@ int dram_init (void) void dram_init_banksize(void) { gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + gd->bd->bi_dram[0].size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); #if CONFIG_NR_DRAM_BANKS > 1 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2, + gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); #endif } diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c index bf635c3..09cc9c5 100644 --- a/board/logicpd/imx31_litekit/imx31_litekit.c +++ b/board/logicpd/imx31_litekit/imx31_litekit.c @@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1, + gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/logicpd/zoom2/zoom2_serial.c b/board/logicpd/zoom2/zoom2_serial.c index fcfe624..74f165f 100644 --- a/board/logicpd/zoom2/zoom2_serial.c +++ b/board/logicpd/zoom2/zoom2_serial.c @@ -132,3 +132,8 @@ QUAD_INIT (0) QUAD_INIT (1) QUAD_INIT (2) QUAD_INIT (3) + +struct serial_device *default_serial_console(void) +{ + return ZOOM2_DEFAULT_SERIAL_DEVICE; +} diff --git a/board/logicpd/zoom2/zoom2_serial.h b/board/logicpd/zoom2/zoom2_serial.h index a6d2427..4e30587 100644 --- a/board/logicpd/zoom2/zoom2_serial.h +++ b/board/logicpd/zoom2/zoom2_serial.h @@ -33,7 +33,6 @@ extern int zoom2_debug_board_connected (void); #define S(a) #a #define N(a) S(quad##a) -#define U(a) S(UART##a) #define QUAD_INIT(n) \ int quad_init_##n(void) \ @@ -63,7 +62,6 @@ int quad_tstc_##n(void) \ struct serial_device zoom2_serial_device##n = \ { \ N(n), \ - U(n), \ quad_init_##n, \ NULL, \ quad_setbrg_##n, \ diff --git a/board/lpd7a40x/flash.c b/board/lpd7a40x/flash.c index a3ba75b..f5c0713 100644 --- a/board/lpd7a40x/flash.c +++ b/board/lpd7a40x/flash.c @@ -229,6 +229,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) ulong result, result1; int iflag, prot, sect; int rc = ERR_OK; + ulong start; #ifdef USE_920T_MMU int cflag; @@ -284,7 +285,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) sect, info->start[sect]); /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ vu_long *addr = (vu_long *) (info->start[sect]); @@ -297,7 +298,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* wait until flash is ready */ do { /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = CMD_STATUS_RESET; result = BIT_TIMEOUT; break; @@ -357,6 +358,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) ulong result; int rc = ERR_OK; int iflag; + ulong start; #ifdef USE_920T_MMU int cflag; @@ -387,12 +389,12 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait until flash is ready */ do { /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = CMD_SUSPEND; result = BIT_TIMEOUT; break; diff --git a/board/lubbock/flash.c b/board/lubbock/flash.c index a4b201e..1ea2893 100644 --- a/board/lubbock/flash.c +++ b/board/lubbock/flash.c @@ -221,7 +221,7 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) int flash_erase (flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -254,9 +254,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - start = get_timer (0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -269,14 +266,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); *addr = (FPW) 0x00500050; /* clear status register */ *addr = (FPW) 0x00200020; /* erase setup */ *addr = (FPW) 0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -393,6 +390,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) FPWV *addr = (FPWV *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -406,11 +404,11 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/matrix_vision/common/mv_common.c b/board/matrix_vision/common/mv_common.c index 0afc535..404c8b4 100644 --- a/board/matrix_vision/common/mv_common.c +++ b/board/matrix_vision/common/mv_common.c @@ -38,6 +38,7 @@ static char* entries_to_keep[] = { #define MV_MAX_ENV_ENTRY_LENGTH 64 #define MV_KEEP_ENTRIES ARRAY_SIZE(entries_to_keep) +#ifndef CONFIG_ENV_IS_NOWHERE void mv_reset_environment(void) { int i; @@ -67,6 +68,7 @@ void mv_reset_environment(void) saveenv(); } +#endif int mv_load_fpga(void) { diff --git a/board/matrix_vision/mergerbox/Makefile b/board/matrix_vision/mergerbox/Makefile new file mode 100644 index 0000000..2b78c98 --- /dev/null +++ b/board/matrix_vision/mergerbox/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o pci.o fpga.o sm107.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/matrix_vision/mergerbox/fpga.c b/board/matrix_vision/mergerbox/fpga.c new file mode 100644 index 0000000..021e9c4 --- /dev/null +++ b/board/matrix_vision/mergerbox/fpga.c @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * (C) Copyright 2011 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ACEX1K.h> +#include <command.h> +#include "mergerbox.h" +#include "fpga.h" + +Altera_CYC2_Passive_Serial_fns altera_fns = { + fpga_null_fn, + fpga_config_fn, + fpga_status_fn, + fpga_done_fn, + fpga_wr_fn, + fpga_null_fn, + fpga_null_fn, +}; + +Altera_desc cyclone2 = { + Altera_CYC2, + passive_serial, + Altera_EP2C20_SIZE, + (void *) &altera_fns, + NULL, + 0 +}; + +DECLARE_GLOBAL_DATA_PTR; + +int mergerbox_init_fpga(void) +{ + debug("Initialize FPGA interface\n"); + fpga_init(); + fpga_add(fpga_altera, &cyclone2); + + return 1; +} + +int fpga_null_fn(int cookie) +{ + return 0; +} + +int fpga_config_fn(int assert, int flush, int cookie) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; + u32 dvo = gpio->dat; + + dvo &= ~FPGA_CONFIG; + gpio->dat = dvo; + udelay(5); + dvo |= FPGA_CONFIG; + gpio->dat = dvo; + + return assert; +} + +int fpga_done_fn(int cookie) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; + int result = 0; + + udelay(10); + debug("CONF_DONE check ... "); + if (gpio->dat & FPGA_CONF_DONE) { + debug("high\n"); + result = 1; + } else + debug("low\n"); + + return result; +} + +int fpga_status_fn(int cookie) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; + int result = 0; + + debug("STATUS check ... "); + if (gpio->dat & FPGA_STATUS) { + debug("high\n"); + result = 1; + } else + debug("low\n"); + + return result; +} + +int fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; + u32 dvo = gpio->dat; + + debug("CLOCK %s\n", assert_clk ? "high" : "low"); + if (assert_clk) + dvo |= FPGA_CCLK; + else + dvo &= ~FPGA_CCLK; + + if (flush) + gpio->dat = dvo; + + return assert_clk; +} + +static inline int _write_fpga(u8 val, int dump) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; + int i; + u32 dvo = gpio->dat; + + if (dump) + debug(" %02x -> ", val); + for (i = 0; i < 8; i++) { + dvo &= ~FPGA_CCLK; + gpio->dat = dvo; + dvo &= ~FPGA_DIN; + if (dump) + debug("%d ", val&1); + if (val & 1) + dvo |= FPGA_DIN; + gpio->dat = dvo; + dvo |= FPGA_CCLK; + gpio->dat = dvo; + val >>= 1; + } + if (dump) + debug("\n"); + + return 0; +} + +int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) +{ + unsigned char *data = (unsigned char *) buf; + int i; + + debug("fpga_wr: buf %p / size %d\n", buf, len); + for (i = 0; i < len; i++) + _write_fpga(data[i], 0); + debug("\n"); + + return FPGA_SUCCESS; +} diff --git a/board/matrix_vision/mergerbox/fpga.h b/board/matrix_vision/mergerbox/fpga.h new file mode 100644 index 0000000..89f879a --- /dev/null +++ b/board/matrix_vision/mergerbox/fpga.h @@ -0,0 +1,30 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +extern int mergerbox_init_fpga(void); + +extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); +extern int fpga_status_fn(int cookie); +extern int fpga_config_fn(int assert, int flush, int cookie); +extern int fpga_done_fn(int cookie); +extern int fpga_clk_fn(int assert_clk, int flush, int cookie); +extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); +extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mergerbox/mergerbox.c b/board/matrix_vision/mergerbox/mergerbox.c new file mode 100644 index 0000000..8616205 --- /dev/null +++ b/board/matrix_vision/mergerbox/mergerbox.c @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * Copyright (C) 2011 Matrix Vision GmbH + * Andre Schwarz <andre.schwarz@matrix-vision.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <common.h> +#include <hwconfig.h> +#include <i2c.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/fsl_mpc83xx_serdes.h> +#include <fdt_support.h> +#include <spd_sdram.h> +#include "mergerbox.h" +#include "fpga.h" +#include "../common/mv_common.h" + +static void setup_serdes(void) +{ + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); +} + +#if defined(CONFIG_SYS_DRAM_TEST) +int testdram(void) +{ + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; + uint *p; + + printf("Testing DRAM from 0x%08x to 0x%08x\n", + CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); + + printf("DRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test passed.\n"); + return 0; +} +#endif + +phys_size_t initdram(int board_type) +{ + u32 msize; + + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk; + + /* Enable PCI_CLK[0:1] */ + clk->occr |= 0xc0000000; + udelay(2000); + +#if defined(CONFIG_SPD_EEPROM) + msize = spd_sdram(); +#else + immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msize_log2; + + msize = CONFIG_SYS_DDR_SIZE; + msize_log2 = __ilog2(msize); + + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); + + im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; + udelay(50000); + + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; + udelay(1000); + + im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + udelay(1000); + + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + __asm__ __volatile__("sync"); + udelay(1000); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + udelay(2000); +#endif + setup_serdes(); + + return msize << 20; +} + +int checkboard(void) +{ + puts("Board: Matrix Vision MergerBox\n"); + + return 0; +} + +int misc_init_r(void) +{ + u16 dim; + int result; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (gpio83xx_t *)&immr->gpio[1]; + unsigned char mac[6], mac_verify[6]; + char *s = getenv("reset_env"); + + for (dim = 10; dim < 180; dim += 5) { + mergerbox_tft_dim(dim); + udelay(100000); + } + + if (s) + mv_reset_environment(); + + i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac, sizeof(mac)); + + /* check if Matrix Vision prefix present and export to env */ + if (mac[0] == 0x00 && mac[1] == 0x0c && mac[2] == 0x8d) { + printf("valid MAC found in eeprom: %pM\n", mac); + eth_setenv_enetaddr("ethaddr", mac); + } else { + printf("no valid MAC found in eeprom.\n"); + + /* no: check the env */ + if (!eth_getenv_enetaddr("ethaddr", mac)) { + printf("no valid MAC found in env either.\n"); + /* TODO: ask for valid MAC */ + } else { + printf("valid MAC found in env: %pM\n", mac); + printf("updating MAC in eeprom.\n"); + + do { + result = test_and_clear_bit(20, &gpio->dat); + if (result) + printf("unprotect EEPROM failed !\n"); + udelay(20000); + } while(result); + + i2c_write(SPD_EEPROM_ADDRESS, 0x80, 2, mac, 6); + udelay(20000); + + do { + result = test_and_set_bit(20, &gpio->dat); + if (result) + printf("protect EEPROM failed !\n"); + udelay(20000); + } while(result); + + printf("verify MAC %pM ... ", mac); + i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac_verify, 6); + + if (!strncmp((char *)mac, (char *)mac_verify, 6)) + printf("ok.\n"); + else + /* TODO: retry or do something useful */ + printf("FAILED (got %pM) !\n", mac_verify); + } + } + + return 0; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; + + iopd->dat &= ~TFT_SPI_CPLD_CS; +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; + + iopd->dat |= TFT_SPI_CPLD_CS; +} + +/* control backlight pwm (display brightness). + * allow values 0-250 with 0 = turn off and 250 = max brightness + */ +void mergerbox_tft_dim(u16 value) +{ + struct spi_slave *slave; + u16 din; + u16 dout = 0; + + if (value > 0 && value < 250) + dout = 0x4000 | value; + + slave = spi_setup_slave(0, 0, 1000000, SPI_MODE_0 | SPI_CS_HIGH); + spi_claim_bus(slave); + spi_xfer(slave, 16, &dout, &din, SPI_XFER_BEGIN | SPI_XFER_END); + spi_release_bus(slave); + spi_free_slave(slave); +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + fdt_fixup_dr_usb(blob, bd); + ft_pci_setup(blob, bd); +} diff --git a/board/matrix_vision/mergerbox/mergerbox.h b/board/matrix_vision/mergerbox/mergerbox.h new file mode 100644 index 0000000..d666d07 --- /dev/null +++ b/board/matrix_vision/mergerbox/mergerbox.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2011 Matrix Vision GmbH + * Andre Schwarz <andre.schwarz@matrix-vision.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __MERGERBOX_H__ +#define __MERGERBOX_H__ + +#define MV_GPIO + +/* + * GPIO Bank 1 + */ +#define TFT_SPI_EN (0x80000000>>0) +#define FPGA_CONFIG (0x80000000>>1) +#define FPGA_STATUS (0x80000000>>2) +#define FPGA_CONF_DONE (0x80000000>>3) +#define FPGA_DIN (0x80000000>>4) +#define FPGA_CCLK (0x80000000>>5) +#define MAN_RST (0x80000000>>6) +#define FPGA_SYS_RST (0x80000000>>7) +#define WD_WDI (0x80000000>>8) +#define TFT_RST (0x80000000>>9) +#define HISCON_GPIO1 (0x80000000>>10) +#define HISCON_GPIO2 (0x80000000>>11) +#define B2B_GPIO2 (0x80000000>>12) +#define CCU_GPIN (0x80000000>>13) +#define CCU_GPOUT (0x80000000>>14) +#define TFT_GPIO0 (0x80000000>>15) +#define TFT_GPIO1 (0x80000000>>16) +#define TFT_GPIO2 (0x80000000>>17) +#define TFT_GPIO3 (0x80000000>>18) +#define B2B_GPIO0 (0x80000000>>19) +#define B2B_GPIO1 (0x80000000>>20) +#define TFT_SPI_CPLD_CS (0x80000000>>21) +#define TFT_SPI_CS (0x80000000>>22) +#define CCU_PWR_EN (0x80000000>>23) +#define B2B_GPIO3 (0x80000000>>24) +#define CCU_PWR_STAT (0x80000000>>25) + +#define MV_GPIO1_DAT (FPGA_CONFIG|CCU_PWR_EN|TFT_SPI_CPLD_CS) +#define MV_GPIO1_OUT (TFT_SPI_EN|FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|CCU_PWR_EN| \ + TFT_SPI_CPLD_CS) +#define MV_GPIO1_ODE (FPGA_CONFIG|MAN_RST) + +/* + * GPIO Bank 2 + */ +#define SPI_FLASH_WP (0x80000000>>10) +#define SYS_EEPROM_WP (0x80000000>>11) +#define SPI_FLASH_CS (0x80000000>>22) + +#define MV_GPIO2_DAT (SYS_EEPROM_WP|SPI_FLASH_CS) +#define MV_GPIO2_OUT (SPI_FLASH_WP|SYS_EEPROM_WP|SPI_FLASH_CS) +#define MV_GPIO2_ODE 0 + +void mergerbox_tft_dim(u16 value); + +#endif diff --git a/board/matrix_vision/mergerbox/pci.c b/board/matrix_vision/mergerbox/pci.c new file mode 100644 index 0000000..8bc8342 --- /dev/null +++ b/board/matrix_vision/mergerbox/pci.c @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. + * + * Copyright (C) 2011 Matrix Vision GmbH + * Andre Schwarz <andre.schwarz@matrix-vision.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <common.h> +#include <mpc83xx.h> +#include <pci.h> +#include <asm/io.h> +#include <asm/fsl_mpc83xx_serdes.h> +#include "mergerbox.h" +#include "fpga.h" +#include "../common/mv_common.h" + +static struct pci_region pci_regions[] = { + { + .bus_start = CONFIG_SYS_PCI_MEM_BASE, + .phys_start = CONFIG_SYS_PCI_MEM_PHYS, + .size = CONFIG_SYS_PCI_MEM_SIZE, + .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + .bus_start = CONFIG_SYS_PCI_MMIO_BASE, + .phys_start = CONFIG_SYS_PCI_MMIO_PHYS, + .size = CONFIG_SYS_PCI_MMIO_SIZE, + .flags = PCI_REGION_MEM + }, + { + .bus_start = CONFIG_SYS_PCI_IO_BASE, + .phys_start = CONFIG_SYS_PCI_IO_PHYS, + .size = CONFIG_SYS_PCI_IO_SIZE, + .flags = PCI_REGION_IO + } +}; + +static struct pci_region pcie_regions_0[] = { + { + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, + .size = CONFIG_SYS_PCIE1_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE1_IO_BASE, + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, + .size = CONFIG_SYS_PCIE1_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +static struct pci_region pcie_regions_1[] = { + { + .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, + .size = CONFIG_SYS_PCIE2_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE2_IO_BASE, + .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, + .size = CONFIG_SYS_PCIE2_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +void pci_init_board(void) +{ + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + volatile sysconf83xx_t *sysconf = &immr->sysconf; + volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + volatile law83xx_t *pcie_law = sysconf->pcielaw; + struct pci_region *reg[] = { pci_regions }; + struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; + + volatile gpio83xx_t *gpio; + gpio = (gpio83xx_t *)&immr->gpio[0]; + + gpio->dat = MV_GPIO1_DAT; + gpio->odr = MV_GPIO1_ODE; + gpio->dir = MV_GPIO1_OUT; + + gpio = (gpio83xx_t *)&immr->gpio[1]; + + gpio->dat = MV_GPIO2_DAT; + gpio->odr = MV_GPIO2_ODE; + gpio->dir = MV_GPIO2_OUT; + + printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, + immr->sysconf.sicrl); + + /* Enable PCI_CLK[0:1] */ + clk->occr |= 0xc0000000; + udelay(2000); + + mergerbox_init_fpga(); + mv_load_fpga(); + + mergerbox_tft_dim(0); + + /* Configure PCI Local Access Windows */ + pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + udelay(2000); + + mpc83xx_pci_init(1, reg); + + /* Deassert the resets in the control register */ + out_be32(&sysconf->pecr1, 0xE0008000); + out_be32(&sysconf->pecr2, 0xE0008000); + udelay(2000); + + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); + out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); + + mpc83xx_pcie_init(2, pcie_reg); +} diff --git a/board/matrix_vision/mergerbox/sm107.c b/board/matrix_vision/mergerbox/sm107.c new file mode 100644 index 0000000..db716b2 --- /dev/null +++ b/board/matrix_vision/mergerbox/sm107.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2011 Matrix Vision GmbH + * Andre Schwarz <andre.schwarz@matrix-vision.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <common.h> +#include <asm/io.h> +#include <ns16550.h> +#include <netdev.h> +#include <sm501.h> +#include <pci.h> +#include "../common/mv_common.h" + +#ifdef CONFIG_VIDEO +static const SMI_REGS init_regs_800x480[] = { + /* set endianess to little endian */ + {0x0005c, 0x00000000}, + /* PCI drive 12mA */ + {0x00004, 0x42401001}, + /* current clock */ + {0x0003c, 0x310a1818}, + /* clocks for pm0... */ + {0x00040, 0x0002184f}, + {0x00044, 0x2a1a0a01}, + /* GPIO */ + {0x10008, 0x00000000}, + {0x1000C, 0x00000000}, + /* panel control regs */ + {0x80000, 0x0f017106}, + {0x80004, 0x0}, + {0x80008, 0x0}, + {0x8000C, 0x00000000}, + {0x80010, 0x0c800c80}, + /* width 0x320 */ + {0x80014, 0x03200000}, + /* height 0x1e0 */ + {0x80018, 0x01E00000}, + {0x8001C, 0x0}, + {0x80020, 0x01df031f}, + {0x80024, 0x041f031f}, + {0x80028, 0x00800347}, + {0x8002C, 0x020c01df}, + {0x80030, 0x000201e9}, + {0x80200, 0x00000000}, + /* ZV[0:7] */ + {0x00008, 0x00ff0000}, + /* 24-Bit TFT */ + {0x0000c, 0x3f000000}, + {0, 0} +}; + +/* + * Returns SM107 register base address. First thing called in the driver. + */ +unsigned int board_video_init(void) +{ + pci_dev_t devbusfn; + u32 addr; + + devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); + if (devbusfn != -1) { + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, + (u32 *)&addr); + return addr & 0xfffffffe; + } + + return 0; +} + +/* + * Called after initializing the SM501 and before clearing the screen. + */ +void board_validate_screen(unsigned int base) +{ +} + +/* + * Returns SM107 framebuffer address + */ +unsigned int board_video_get_fb(void) +{ + pci_dev_t devbusfn; + u32 addr; + + devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); + if (devbusfn != -1) { + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, + (u32 *)&addr); + addr &= 0xfffffffe; +#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET + addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET; +#endif + return addr; + } + + printf("board_video_get_fb(): FAILED\n"); + + return 0; +} + +/* + * Return a pointer to the initialization sequence. + */ +const SMI_REGS *board_get_regs(void) +{ + return init_regs_800x480; +} + +int board_get_width(void) +{ + return 800; +} + +int board_get_height(void) +{ + return 480; +} +#endif diff --git a/board/matrix_vision/mvbc_p/fpga.c b/board/matrix_vision/mvbc_p/fpga.c index 3ed46fe..6ce96ba 100644 --- a/board/matrix_vision/mvbc_p/fpga.c +++ b/board/matrix_vision/mvbc_p/fpga.c @@ -160,7 +160,7 @@ static inline int _write_fpga(u8 val) return 0; } -int fpga_wr_fn(void *buf, size_t len, int flush, int cookie) +int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) { unsigned char *data = (unsigned char *) buf; int i; diff --git a/board/matrix_vision/mvbc_p/fpga.h b/board/matrix_vision/mvbc_p/fpga.h index 3723073..8f74a00 100644 --- a/board/matrix_vision/mvbc_p/fpga.h +++ b/board/matrix_vision/mvbc_p/fpga.h @@ -30,5 +30,5 @@ extern int fpga_status_fn(int cookie); extern int fpga_config_fn(int assert, int flush, int cookie); extern int fpga_done_fn(int cookie); extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie); +extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mvblm7/fpga.c b/board/matrix_vision/mvblm7/fpga.c index 7b03d6f..dc5a738 100644 --- a/board/matrix_vision/mvblm7/fpga.c +++ b/board/matrix_vision/mvblm7/fpga.c @@ -172,7 +172,7 @@ static inline int _write_fpga(u8 val, int dump) return 0; } -int fpga_wr_fn(void *buf, size_t len, int flush, int cookie) +int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) { unsigned char *data = (unsigned char *) buf; int i; diff --git a/board/matrix_vision/mvblm7/fpga.h b/board/matrix_vision/mvblm7/fpga.h index 19277eb..f422f20 100644 --- a/board/matrix_vision/mvblm7/fpga.h +++ b/board/matrix_vision/mvblm7/fpga.h @@ -30,5 +30,5 @@ extern int fpga_status_fn(int cookie); extern int fpga_config_fn(int assert, int flush, int cookie); extern int fpga_done_fn(int cookie); extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie); +extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); extern int fpga_null_fn(int cookie); diff --git a/board/modnet50/flash.c b/board/modnet50/flash.c index 4c31143..4834e21 100644 --- a/board/modnet50/flash.c +++ b/board/modnet50/flash.c @@ -291,6 +291,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) { int flag, sect, setup_offset = 0; int rc = ERR_OK; + ulong start; if (info->flash_id == FLASH_UNKNOWN) { printf ("- missing\n"); @@ -338,14 +339,14 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) (__u16) SECERASE_CMD; /* wait some time */ - reset_timer_masked (); - while (get_timer_masked () < 1000) { + start = get_timer(0); + while (get_timer(start) < 1000) { } /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); while (flash_check_erase_amd (info->start[sect])) { - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("timeout!\n"); /* OOPS: reach timeout, * try to reset chip @@ -411,6 +412,7 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) { int rc = ERR_OK; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*(__u16 *) (dest) & data) != data) @@ -446,10 +448,10 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) } /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); while (flash_check_write_amd (dest)) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { printf ("timeout! @ %08lX\n", dest); /* OOPS: reach timeout, * try to reset chip */ diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c index a009437..89d2e0a 100644 --- a/board/mpl/common/usb_uhci.c +++ b/board/mpl/common/usb_uhci.c @@ -67,7 +67,7 @@ * * Interrupt Transfers. * -------------------- - * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They + * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They * will be inserted after the appropriate (depending the interval setting) skeleton TD. * If an interrupt has been detected the dev->irqhandler is called. The status and number * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile index 27cef1d..6228762 100644 --- a/board/mpl/vcma9/Makefile +++ b/board/mpl/vcma9/Makefile @@ -28,8 +28,8 @@ endif LIB = $(obj)lib$(BOARD).o -COBJS := vcma9.o flash.o cmd_vcma9.o -COBJS += ../common/common_util.o +COBJS := ../common/common_util.o +COBJS += $(BOARD).o cmd_$(BOARD).o SOBJS := lowlevel_init.o diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c index 0d5f46e..fa49918 100644 --- a/board/mpl/vcma9/cmd_vcma9.c +++ b/board/mpl/vcma9/cmd_vcma9.c @@ -43,15 +43,6 @@ static uchar cs8900_chksum(ushort data) DECLARE_GLOBAL_DATA_PTR; -extern void print_vcma9_info(void); -extern int vcma9_cantest(int); -extern int vcma9_nandtest(void); -extern int vcma9_nanderase(void); -extern int vcma9_nandread(ulong); -extern int vcma9_nandwrite(ulong); -extern int vcma9_dactest(int); -extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); - /* ------------------------------------------------------------------------- */ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -60,7 +51,7 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char cs8900_name[10]; if (strcmp(argv[1], "info") == 0) { - print_vcma9_info(); + vcma9_print_info(); return 0; } #if defined(CONFIG_CS8900) @@ -133,48 +124,6 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } #endif -#if 0 - if (strcmp(argv[1], "cantest") == 0) { - if (argc >= 3) - vcma9_cantest(strcmp(argv[2], "s") ? 0 : 1); - else - vcma9_cantest(0); - return 0; - } - if (strcmp(argv[1], "nandtest") == 0) { - vcma9_nandtest(); - return 0; - } - if (strcmp(argv[1], "nanderase") == 0) { - vcma9_nanderase(); - return 0; - } - if (strcmp(argv[1], "nandread") == 0) { - ulong offset = 0; - - if (argc >= 3) - offset = simple_strtoul(argv[2], NULL, 16); - - vcma9_nandread(offset); - return 0; - } - if (strcmp(argv[1], "nandwrite") == 0) { - ulong offset = 0; - - if (argc >= 3) - offset = simple_strtoul(argv[2], NULL, 16); - - vcma9_nandwrite(offset); - return 0; - } - if (strcmp(argv[1], "dactest") == 0) { - if (argc >= 3) - vcma9_dactest(strcmp(argv[2], "s") ? 0 : 1); - else - vcma9_dactest(0); - return 0; - } -#endif return (do_mplcommon(cmdtp, flag, argc, argv)); } @@ -182,5 +131,6 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( vcma9, 6, 1, do_vcma9, "VCMA9 specific commands", - "flash mem [SrcAddr]\n - updates U-Boot with image in memory" + "flash mem [SrcAddr] - updates U-Boot with image in memory\n" + "vcma9 info - displays board information" ); diff --git a/board/mpl/vcma9/config.mk b/board/mpl/vcma9/config.mk deleted file mode 100644 index e345913..0000000 --- a/board/mpl/vcma9/config.mk +++ /dev/null @@ -1,24 +0,0 @@ -# -# (C) Copyright 2002, 2003 -# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> -# -# MPL VCMA9 board with S3C2410X (ARM920T) cpu -# -# see http://www.mpl.ch/ for more information about the MPL VCMA9 -# - -# -# MPL VCMA9 has 1 bank of minimal 16 MB DRAM -# from 0x30000000 -# -# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 -# optionally with a ramdisk at 3040'0000 -# -# we load ourself to 33F8'0000 -# -# download area is 3080'0000 -# - - -#CONFIG_SYS_TEXT_BASE = 0x30F80000 -CONFIG_SYS_TEXT_BASE = 0x33F80000 diff --git a/board/mpl/vcma9/flash.c b/board/mpl/vcma9/flash.c deleted file mode 100644 index 7abf9cf..0000000 --- a/board/mpl/vcma9/flash.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -ulong myflush (void); - - -#define FLASH_BANK_SIZE PHYS_FLASH_SIZE -#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x000000F0 -#define CMD_UNLOCK1 0x000000AA -#define CMD_UNLOCK2 0x00000055 -#define CMD_ERASE_SETUP 0x00000080 -#define CMD_ERASE_CONFIRM 0x00000030 -#define CMD_PROGRAM 0x000000A0 -#define CMD_UNLOCK_BYPASS 0x00000020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1))) - -#define BIT_ERASE_DONE 0x00000080 -#define BIT_RDY_MASK 0x00000080 -#define BIT_PROGRAM_ERROR 0x00000020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = -#if defined(CONFIG_AMD_LV400) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV400B & FLASH_TYPEMASK); -#elif defined(CONFIG_AMD_LV800) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV800B & FLASH_TYPEMASK); -#else -#error "Unknown flash configured" -#endif - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j <= 3) { - /* 1st one is 16 KB */ - if (j == 0) { - flash_info[i].start[j] = - flashbase + 0; - } - - /* 2nd and 3rd are both 8 KB */ - if ((j == 1) || (j == 2)) { - flash_info[i].start[j] = - flashbase + 0x4000 + (j - - 1) * - 0x2000; - } - - /* 4th 32 KB */ - if (j == 3) { - flash_info[i].start[j] = - flashbase + 0x8000; - } - } else { - flash_info[i].start[j] = - flashbase + (j - 3) * MAIN_SECT_SIZE; - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - puts ("AMD: "); - break; - default: - puts ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_LV400B & FLASH_TYPEMASK): - puts ("1x Amd29LV400BB (4Mbit)\n"); - break; - case (AMD_ID_LV800B & FLASH_TYPEMASK): - puts ("1x Amd29LV800BB (8Mbit)\n"); - break; - default: - puts ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - puts (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - puts ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - puts ("\n"); - -Done: ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ushort result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > - CONFIG_SYS_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip = TMO; - break; - } - - if (!chip - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip = READY; - - if (!chip - && (result & 0xFFFF) & BIT_PROGRAM_ERROR) - chip = ERR; - - } while (!chip); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - puts ("ok.\n"); - } else { /* it was protected */ - - puts ("protected!\n"); - } - } - - if (ctrlc ()) - puts ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_hword (flash_info_t * info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) dest; - ushort result; - int rc = ERR_OK; - int cflag, iflag; - int chip; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait until flash is ready */ - chip = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { - chip = ERR | TMO; - break; - } - if (!chip && ((result & 0x80) == (data & 0x80))) - chip = READY; - - if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { - result = *addr; - - if ((result & 0x80) == (data & 0x80)) - chip = READY; - else - chip = ERR; - } - - } while (!chip); - - *addr = CMD_READ_ARRAY; - - if (chip == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - int l; - int i, rc; - ushort data; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_hword (info, wp, data); -} diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S index 062e868..dadaac7 100644 --- a/board/mpl/vcma9/lowlevel_init.S +++ b/board/mpl/vcma9/lowlevel_init.S @@ -4,9 +4,9 @@ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) * - * Modified for the Samsung SMDK2410 by - * (C) Copyright 2002 + * Modified for MPL VCMA9 by * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> + * (C) Copyright 2002, 2003, 2004, 2005 * * See file CREDITS for list of people who contributed to this * project. @@ -32,12 +32,21 @@ #include <version.h> -/* some parameters for the board */ +/* register definitions */ +#define PLD_BASE 0x28000000 +#define MISC_REG 0x103 +#define SDRAM_REG 0x106 #define BWSCON 0x48000000 -#define PLD_BASE 0x2C000000 -#define SDRAM_REG 0x2C000106 +#define CLKBASE 0x4C000000 +#define LOCKTIME 0x0 +#define MPLLCON 0x4 +#define UPLLCON 0x8 +#define GPIOBASE 0x56000000 +#define GSTATUS1 0xB0 +#define FASTCPU 0x02 +/* some parameters for the board */ /* BWSCON */ #define DW8 (0x0) #define DW16 (0x1) @@ -48,83 +57,160 @@ /* BANKSIZE */ #define BURST_EN (0x1<<7) -#define B1_BWSCON (DW16) -#define B2_BWSCON (DW32) -#define B3_BWSCON (DW32) -#define B4_BWSCON (DW16 + WAIT + UBLB) -#define B5_BWSCON (DW8 + UBLB) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) - -/* BANK0CON */ -#define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x1 /* 1clk */ -/*#define B0_Tcos 0x0 0clk */ -#define B0_Tacc 0x7 /* 14clk */ -/*#define B0_Tacc 0x5 8clk */ -#define B0_Tcoh 0x0 /* 0clk */ -#define B0_Tah 0x0 /* 0clk */ -#define B0_Tacp 0x0 /* page mode is not used */ -#define B0_PMC 0x0 /* page mode disabled */ - -/* BANK1CON */ -#define B1_Tacs 0x0 /* 0clk */ -#define B1_Tcos 0x1 /* 1clk */ -/*#define B1_Tcos 0x0 0clk */ -#define B1_Tacc 0x7 /* 14clk */ -/*#define B1_Tacc 0x5 8clk */ -#define B1_Tcoh 0x0 /* 0clk */ -#define B1_Tah 0x0 /* 0clk */ -#define B1_Tacp 0x0 /* page mode is not used */ -#define B1_PMC 0x0 /* page mode disabled */ +/* BANK0CON 200 */ +#define B0_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */ +#define B0_Tcoh_200 0x0 /* 0clk */ +#define B0_Tcah_200 0x3 /* 4clk (or0x01 1clk) */ +#define B0_Tacp_200 0x0 /* page mode is not used */ +#define B0_PMC_200 0x0 /* page mode disabled */ + +/* BANK0CON 250 */ +#define B0_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */ +#define B0_Tcoh_250 0x0 /* 0clk */ +#define B0_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */ +#define B0_Tacp_250 0x0 /* page mode is not used */ +#define B0_PMC_250 0x0 /* page mode disabled */ + +/* BANK0CON 266 */ +#define B0_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */ +#define B0_Tcoh_266 0x0 /* 0clk */ +#define B0_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */ +#define B0_Tacp_266 0x0 /* page mode is not used */ +#define B0_PMC_266 0x0 /* page mode disabled */ + +/* BANK1CON 200 */ +#define B1_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */ +#define B1_Tcoh_200 0x0 /* 0clk */ +#define B1_Tcah_200 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_200 0x0 /* page mode is not used */ +#define B1_PMC_200 0x0 /* page mode disabled */ + +/* BANK1CON 250 */ +#define B1_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */ +#define B1_Tcoh_250 0x0 /* 0clk */ +#define B1_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_250 0x0 /* page mode is not used */ +#define B1_PMC_250 0x0 /* page mode disabled */ + +/* BANK1CON 266 */ +#define B1_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */ +#define B1_Tcoh_266 0x0 /* 0clk */ +#define B1_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_266 0x0 /* page mode is not used */ +#define B1_PMC_266 0x0 /* page mode disabled */ +/* BANK2CON 200 + 250 + 266 */ #define B2_Tacs 0x3 /* 4clk */ #define B2_Tcos 0x3 /* 4clk */ #define B2_Tacc 0x7 /* 14clk */ #define B2_Tcoh 0x3 /* 4clk */ -#define B2_Tah 0x3 /* 4clk */ +#define B2_Tcah 0x3 /* 4clk */ #define B2_Tacp 0x0 /* page mode is not used */ #define B2_PMC 0x0 /* page mode disabled */ +/* BANK3CON 200 + 250 + 266 */ #define B3_Tacs 0x3 /* 4clk */ #define B3_Tcos 0x3 /* 4clk */ #define B3_Tacc 0x7 /* 14clk */ #define B3_Tcoh 0x3 /* 4clk */ -#define B3_Tah 0x3 /* 4clk */ +#define B3_Tcah 0x3 /* 4clk */ #define B3_Tacp 0x0 /* page mode is not used */ #define B3_PMC 0x0 /* page mode disabled */ -#define B4_Tacs 0x3 /* 4clk */ -#define B4_Tcos 0x1 /* 1clk */ -#define B4_Tacc 0x7 /* 14clk */ -#define B4_Tcoh 0x1 /* 1clk */ -#define B4_Tah 0x0 /* 0clk */ -#define B4_Tacp 0x0 /* page mode is not used */ -#define B4_PMC 0x0 /* page mode disabled */ - -#define B5_Tacs 0x0 /* 0clk */ -#define B5_Tcos 0x3 /* 4clk */ -#define B5_Tacc 0x5 /* 8clk */ -#define B5_Tcoh 0x2 /* 2clk */ -#define B5_Tah 0x1 /* 1clk */ -#define B5_Tacp 0x0 /* page mode is not used */ -#define B5_PMC 0x0 /* page mode disabled */ +/* BANK4CON 200 */ +#define B4_Tacs_200 0x1 /* 1clk */ +#define B4_Tcos_200 0x3 /* 4clk */ +#define B4_Tacc_200 0x7 /* 14clk */ +#define B4_Tcoh_200 0x3 /* 4clk */ +#define B4_Tcah_200 0x2 /* 2clk */ +#define B4_Tacp_200 0x0 /* page mode is not used */ +#define B4_PMC_200 0x0 /* page mode disabled */ + +/* BANK4CON 250 */ +#define B4_Tacs_250 0x1 /* 1clk */ +#define B4_Tcos_250 0x3 /* 4clk */ +#define B4_Tacc_250 0x7 /* 14clk */ +#define B4_Tcoh_250 0x3 /* 4clk */ +#define B4_Tcah_250 0x2 /* 2clk */ +#define B4_Tacp_250 0x0 /* page mode is not used */ +#define B4_PMC_250 0x0 /* page mode disabled */ + +/* BANK4CON 266 */ +#define B4_Tacs_266 0x1 /* 1clk */ +#define B4_Tcos_266 0x3 /* 4clk */ +#define B4_Tacc_266 0x7 /* 14clk */ +#define B4_Tcoh_266 0x3 /* 4clk */ +#define B4_Tcah_266 0x2 /* 2clk */ +#define B4_Tacp_266 0x0 /* page mode is not used */ +#define B4_PMC_266 0x0 /* page mode disabled */ + +/* BANK5CON 200 */ +#define B5_Tacs_200 0x0 /* 0clk */ +#define B5_Tcos_200 0x3 /* 4clk */ +#define B5_Tacc_200 0x4 /* 6clk */ +#define B5_Tcoh_200 0x3 /* 4clk */ +#define B5_Tcah_200 0x1 /* 1clk */ +#define B5_Tacp_200 0x0 /* page mode is not used */ +#define B5_PMC_200 0x0 /* page mode disabled */ + +/* BANK5CON 250 */ +#define B5_Tacs_250 0x0 /* 0clk */ +#define B5_Tcos_250 0x3 /* 4clk */ +#define B5_Tacc_250 0x5 /* 8clk */ +#define B5_Tcoh_250 0x3 /* 4clk */ +#define B5_Tcah_250 0x1 /* 1clk */ +#define B5_Tacp_250 0x0 /* page mode is not used */ +#define B5_PMC_250 0x0 /* page mode disabled */ + +/* BANK5CON 266 */ +#define B5_Tacs_266 0x0 /* 0clk */ +#define B5_Tcos_266 0x3 /* 4clk */ +#define B5_Tacc_266 0x5 /* 8clk */ +#define B5_Tcoh_266 0x3 /* 4clk */ +#define B5_Tcah_266 0x1 /* 1clk */ +#define B5_Tacp_266 0x0 /* page mode is not used */ +#define B5_PMC_266 0x0 /* page mode disabled */ #define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 /* 3clk */ +#define B6_Trcd_200 0x0 /* 2clk */ +#define B6_Trcd_250 0x1 /* 3clk */ +#define B6_Trcd_266 0x1 /* 3clk */ #define B6_SCAN 0x2 /* 10bit */ #define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ +#define B7_Trcd_200 0x0 /* 2clk */ +#define B7_Trcd_250 0x1 /* 3clk */ +#define B7_Trcd_266 0x1 /* 3clk */ #define B7_SCAN 0x2 /* 10bit */ /* REFRESH parameter */ #define REFEN 0x1 /* Refresh enable */ #define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x0 /* 2clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x2 /* 3clk */ -#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ +#define Trp_200 0x0 /* 2clk */ +#define Trp_250 0x1 /* 3clk */ +#define Trp_266 0x1 /* 3clk */ +#define Tsrc_200 0x1 /* 5clk */ +#define Tsrc_250 0x2 /* 6clk */ +#define Tsrc_266 0x3 /* 7clk */ + +/* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */ +#define REFCNT_200 489 +/* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */ +#define REFCNT_250 99 +/* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */ +#define REFCNT_266 0 /**************************************/ _TEXT_BASE: @@ -132,81 +218,304 @@ _TEXT_BASE: .globl lowlevel_init lowlevel_init: + /* use r0 to relocate DATA read/write to flash rather than memory ! */ + ldr r0, _TEXT_BASE + ldr r13, =BWSCON + + /* enable minimal access to PLD */ + ldr r1, [r13] /* load default BWSCON */ + orr r1, r1, #(DW8 + UBLB) << 20 /* set necessary CS attrs */ + str r1, [r13] /* set BWSCON */ + ldr r1, =0x7FF0 /* select slowest timing */ + str r1, [r13, #0x18] /* set BANKCON5 */ + + ldr r1, =PLD_BASE + ldr r2, =SETUPDATA + ldrb r1, [r1, #MISC_REG] + sub r2, r2, r0 + tst r1, #FASTCPU /* FASTCPU available ? */ + addeq r2, r2, #SETUPENTRY_SIZE + /* memory control configuration */ - /* make r0 relative the current location so that it */ - /* reads SMRDATA out of FLASH rather than memory ! */ - ldr r0, =CSDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #CSDATA_END-CSDATA + /* r2 = pointer into timing table */ + /* r13 = pointer to MEM controller regs (starting with BWSCON) */ + add r3, r2, #CSDATA_OFFSET + add r4, r3, #CSDATAENTRY_SIZE 0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 + ldr r1, [r3], #4 + str r1, [r13], #4 + cmp r3, r4 bne 0b /* PLD access is now possible */ - /* r0 == SDRAMDATA */ - /* r1 == SDRAM controller regs */ - ldr r2, =PLD_BASE - ldrb r3, [r2, #SDRAM_REG-PLD_BASE] - mov r4, #SDRAMDATA1_END-SDRAMDATA + /* r3 = SDRAMDATA + /* r13 = pointer to MEM controller regs */ + ldr r1, =PLD_BASE + mov r4, #SDRAMENTRY_SIZE + ldrb r1, [r1, #SDRAM_REG] /* calculate start and end point */ - mla r0, r3, r4, r0 - add r2, r0, r4 + mla r3, r4, r1, r3 + add r4, r3, r4 0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 + ldr r1, [r3], #4 + str r1, [r13], #4 + cmp r3, r4 bne 0b + /* setup MPLL registers */ + ldr r1, =CLKBASE + ldr r4, =0xFFFFFF + add r3, r2, #4 /* r3 points to PLL values */ + str r4, [r1, #LOCKTIME] + ldmia r3, {r4,r5} + str r5, [r1, #UPLLCON] /* writing PLL register */ + /* !! order seems to be important !! */ + /* a little delay */ + ldr r3, =0x4000 +0: + subs r3, r3, #1 + bne 0b + + str r4, [r1, #MPLLCON] /* writing PLL register */ + /* !! order seems to be important !! */ + /* a little delay */ + ldr r3, =0x4000 +0: + subs r3, r3, #1 + bne 0b + /* everything is fine now */ mov pc, lr .ltorg /* the literal pools origin */ -CSDATA: - .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) -CSDATA_END: - -SDRAMDATA: -/* 4Mx8x4 */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 -SDRAMDATA1_END: - -/* 8Mx8x4 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - -/* 2Mx8x4 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - -/* 4Mx8x2 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 +#define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \ + ((bws1) << 4) + \ + ((bws2) << 8) + \ + ((bws3) << 12) + \ + ((bws4) << 16) + \ + ((bws5) << 20) + \ + ((bws6) << 24) + \ + ((bws7) << 28) + +#define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \ + ((tacs) << 13) + \ + ((tcos) << 11) + \ + ((tacc) << 8) + \ + ((tcoh) << 6) + \ + ((tcah) << 4) + \ + ((tacp) << 2) + \ + (pmc) + +#define MK_BANKCON_SDRAM(trcd, scan) \ + ((0x03) << 15) + \ + ((trcd) << 2) + \ + (scan) + +#define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \ + ((enable) << 23) + \ + ((trefmd) << 22) + \ + ((trp) << 20) + \ + ((tsrc) << 18) + \ + (cnt) + +SETUPDATA: + .word 0x32410002 + /* PLL values (MDIV, PDIV, SDIV) for 250 MHz */ + .word (0x75 << 12) + (0x01 << 4) + (0x01 << 0) + /* PLL values for USB clock */ + .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0) + + /* timing for 250 MHz*/ +0: + .equiv CSDATA_OFFSET, (. - SETUPDATA) + .word MK_BWSCON(DW16, \ + DW32, \ + DW32, \ + DW16 + WAIT + UBLB, \ + DW8 + UBLB, \ + DW32, \ + DW32) + + .word MK_BANKCON(B0_Tacs_250, \ + B0_Tcos_250, \ + B0_Tacc_250, \ + B0_Tcoh_250, \ + B0_Tcah_250, \ + B0_Tacp_250, \ + B0_PMC_250) + + .word MK_BANKCON(B1_Tacs_250, \ + B1_Tcos_250, \ + B1_Tacc_250, \ + B1_Tcoh_250, \ + B1_Tcah_250, \ + B1_Tacp_250, \ + B1_PMC_250) + + .word MK_BANKCON(B2_Tacs, \ + B2_Tcos, \ + B2_Tacc, \ + B2_Tcoh, \ + B2_Tcah, \ + B2_Tacp, \ + B2_PMC) + + .word MK_BANKCON(B3_Tacs, \ + B3_Tcos, \ + B3_Tacc, \ + B3_Tcoh, \ + B3_Tcah, \ + B3_Tacp, \ + B3_PMC) + + .word MK_BANKCON(B4_Tacs_250, \ + B4_Tcos_250, \ + B4_Tacc_250, \ + B4_Tcoh_250, \ + B4_Tcah_250, \ + B4_Tacp_250, \ + B4_PMC_250) + + .word MK_BANKCON(B5_Tacs_250, \ + B5_Tcos_250, \ + B5_Tacc_250, \ + B5_Tcoh_250, \ + B5_Tcah_250, \ + B5_Tacp_250, \ + B5_PMC_250) + + .equiv CSDATAENTRY_SIZE, (. - 0b) + /* 4Mx8x4 */ +0: + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + .equiv SDRAMENTRY_SIZE, (. - 0b) + + /* 8Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 2Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 4Mx8x2 */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + .equiv SETUPENTRY_SIZE, (. - SETUPDATA) + + .word 0x32410000 + /* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */ + .word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0) + /* PLL values for USB clock */ + .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0) + + /* timing for 200 MHz and default*/ + .word MK_BWSCON(DW16, \ + DW32, \ + DW32, \ + DW16 + WAIT + UBLB, \ + DW8 + UBLB, \ + DW32, \ + DW32) + + .word MK_BANKCON(B0_Tacs_200, \ + B0_Tcos_200, \ + B0_Tacc_200, \ + B0_Tcoh_200, \ + B0_Tcah_200, \ + B0_Tacp_200, \ + B0_PMC_200) + + .word MK_BANKCON(B1_Tacs_200, \ + B1_Tcos_200, \ + B1_Tacc_200, \ + B1_Tcoh_200, \ + B1_Tcah_200, \ + B1_Tacp_200, \ + B1_PMC_200) + + .word MK_BANKCON(B2_Tacs, \ + B2_Tcos, \ + B2_Tacc, \ + B2_Tcoh, \ + B2_Tcah, \ + B2_Tacp, \ + B2_PMC) + + .word MK_BANKCON(B3_Tacs, \ + B3_Tcos, \ + B3_Tacc, \ + B3_Tcoh, \ + B3_Tcah, \ + B3_Tacp, \ + B3_PMC) + + .word MK_BANKCON(B4_Tacs_200, \ + B4_Tcos_200, \ + B4_Tacc_200, \ + B4_Tcoh_200, \ + B4_Tcah_200, \ + B4_Tacp_200, \ + B4_PMC_200) + + .word MK_BANKCON(B5_Tacs_200, \ + B5_Tcos_200, \ + B5_Tacc_200, \ + B5_Tcoh_200, \ + B5_Tcah_200, \ + B5_Tacp_200, \ + B5_PMC_200) + + /* 4Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 8Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 2Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 4Mx8x2 */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + .equiv SETUPDATA_SIZE, (. - SETUPDATA) diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index 978e6fd..e63625b 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -3,7 +3,7 @@ * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Marius Groeger <mgroeger@sysgo.de> * - * (C) Copyright 2002 + * (C) Copyright 2002, 2010 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> * * See file CREDITS for list of people who contributed to this @@ -27,100 +27,51 @@ #include <common.h> #include <netdev.h> -#include <asm/arch/s3c24x0_cpu.h> -#include <stdio_dev.h> #include <i2c.h> +#include <asm/io.h> +#include <asm/arch/s3c24x0_cpu.h> #include "vcma9.h" #include "../common/common_util.h" DECLARE_GLOBAL_DATA_PTR; -#define FCLK_SPEED 1 - -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ -#define M_MDIV 0xC3 -#define M_PDIV 0x4 -#define M_SDIV 0x1 -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ -#define M_MDIV 0xA1 -#define M_PDIV 0x3 -#define M_SDIV 0x1 -#endif - -#define USB_CLOCK 1 - -#if USB_CLOCK==0 -#define U_M_MDIV 0xA1 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x1 -#elif USB_CLOCK==1 -#define U_M_MDIV 0x48 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x2 -#endif - -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - /* * Miscellaneous platform dependent initialisations */ -int board_init(void) +int board_early_init_f(void) { - struct s3c24x0_clock_power * const clk_power = - s3c24x0_get_base_clock_power(); struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->locktime = 0xFFFFFF; - - /* configure MPLL */ - clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (4000); - - /* configure UPLL */ - clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (8000); - /* set up the I/O ports */ - gpio->gpacon = 0x007FFFFF; - gpio->gpbcon = 0x002AAAAA; - gpio->gpbup = 0x000002BF; - gpio->gpccon = 0xAAAAAAAA; - gpio->gpcup = 0x0000FFFF; - gpio->gpdcon = 0xAAAAAAAA; - gpio->gpdup = 0x0000FFFF; - gpio->gpecon = 0xAAAAAAAA; - gpio->gpeup = 0x000037F7; - gpio->gpfcon = 0x00000000; - gpio->gpfup = 0x00000000; - gpio->gpgcon = 0xFFEAFF5A; - gpio->gpgup = 0x0000F0DC; - gpio->gphcon = 0x0028AAAA; - gpio->gphup = 0x00000656; - - /* setup correct IRQ modes for NIC */ - /* rising edge mode */ - gpio->extint2 = (gpio->extint2 & ~(7<<8)) | (4<<8); - - /* select USB port 2 to be host or device (fix to host for now) */ - gpio->misccr |= 0x08; - - /* init serial */ - gd->baudrate = CONFIG_BAUDRATE; - gd->have_console = 1; - serial_init(); + writel(0x007FFFFF, &gpio->gpacon); + writel(0x002AAAAA, &gpio->gpbcon); + writel(0x000002BF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x000037F7, &gpio->gpeup); + writel(0x00000000, &gpio->gpfcon); + writel(0x00000000, &gpio->gpfup); + writel(0xFFEAFF5A, &gpio->gpgcon); + writel(0x0000F0DC, &gpio->gpgup); + writel(0x0028AAAA, &gpio->gphcon); + writel(0x00000656, &gpio->gphup); + + /* setup correct IRQ modes for NIC (rising edge mode) */ + writel((readl(&gpio->extint2) & ~(7<<8)) | (4<<8), &gpio->extint2); + + /* select USB port 2 to be host or device (setup as host for now) */ + writel(readl(&gpio->misccr) | 0x08, &gpio->misccr); + + return 0; +} +int board_init(void) +{ /* arch number of VCMA9-Board */ gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9; @@ -134,113 +85,32 @@ int board_init(void) } /* - * NAND flash initialization. - */ -#if defined(CONFIG_CMD_NAND) -extern ulong -nand_probe(ulong physadr); - - -static inline void NF_Reset(void) -{ - int i; - - NF_SetCE(NFCE_LOW); - NF_Cmd(0xFF); /* reset command */ - for(i = 0; i < 10; i++); /* tWB = 100ns. */ - NF_WaitRB(); /* wait 200~500us; */ - NF_SetCE(NFCE_HIGH); -} - - -static inline void NF_Init(void) -{ -#if 0 /* a little bit too optimistic */ -#define TACLS 0 -#define TWRPH0 3 -#define TWRPH1 0 -#else -#define TACLS 0 -#define TWRPH0 4 -#define TWRPH1 2 -#endif - - NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0)); - /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */ - /* 1 1 1 1, 1 xxx, r xxx, r xxx */ - /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */ - - NF_Reset(); -} - -void -nand_init(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - NF_Init(); -#ifdef DEBUG - printf("NAND flash probing at 0x%.8lX\n", (ulong)nand); -#endif - printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20); -} -#endif - -/* * Get some Board/PLD Info */ -static u8 Get_PLD_ID(void) +static u8 get_pld_reg(enum vcma9_pld_regs reg) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->ID); + return readb(VCMA9_PLD_BASE + reg); } -static u8 Get_PLD_BOARD(void) +static u8 get_pld_version(void) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->BOARD); + return (get_pld_reg(VCMA9_PLD_ID) >> 4) & 0x0F; } -static u8 Get_PLD_SDRAM(void) +static u8 get_pld_revision(void) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->SDRAM); + return get_pld_reg(VCMA9_PLD_ID) & 0x0F; } -static u8 Get_PLD_Version(void) +static uchar get_board_pcb(void) { - return((Get_PLD_ID() >> 4) & 0x0F); + return ((get_pld_reg(VCMA9_PLD_BOARD) >> 4) & 0x03) + 'A'; } -static u8 Get_PLD_Revision(void) +static u8 get_nr_chips(void) { - return(Get_PLD_ID() & 0x0F); -} - -#if 0 /* not used */ -static int Get_Board_Config(void) -{ - u8 config = Get_PLD_BOARD() & 0x03; - - if (config == 3) - return 1; - else - return 0; -} -#endif - -static uchar Get_Board_PCB(void) -{ - return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A'); -} - -static u8 Get_SDRAM_ChipNr(void) -{ - switch ((Get_PLD_SDRAM() >> 4) & 0x0F) { + switch ((get_pld_reg(VCMA9_PLD_SDRAM) >> 4) & 0x0F) { case 0: return 4; case 1: return 1; case 2: return 2; @@ -248,9 +118,9 @@ static u8 Get_SDRAM_ChipNr(void) } } -static ulong Get_SDRAM_ChipSize(void) +static ulong get_chip_size(void) { - switch (Get_PLD_SDRAM() & 0x0F) { + switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { case 0: return 16 * (1024*1024); case 1: return 32 * (1024*1024); case 2: return 8 * (1024*1024); @@ -258,9 +128,10 @@ static ulong Get_SDRAM_ChipSize(void) default: return 0; } } -static const char * Get_SDRAM_ChipGeom(void) + +static const char *get_chip_geom(void) { - switch (Get_PLD_SDRAM() & 0x0F) { + switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { case 0: return "4Mx8x4"; case 1: return "8Mx8x4"; case 2: return "2Mx8x4"; @@ -269,23 +140,21 @@ static const char * Get_SDRAM_ChipGeom(void) } } -static void Show_VCMA9_Info(char *board_name, char *serial) +static void vcma9_show_info(char *board_name, char *serial) { printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n", - board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision()); - printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom()); + board_name, serial, + get_board_pcb(), get_pld_version(), get_pld_revision()); + printf("SDRAM: %d chips %s\n", get_nr_chips(), get_chip_geom()); } int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr(); - + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_chip_size() * get_nr_chips(); return 0; } -/* ------------------------------------------------------------------------- */ - /* * Check Board Identity: */ @@ -303,50 +172,35 @@ int checkboard(void) puts ("### No HW ID - assuming VCMA9"); } else { b->serial_name[5] = 0; - Show_VCMA9_Info(b->serial_name, &b->serial_name[6]); + vcma9_show_info(b->serial_name, &b->serial_name[6]); } } else { s[5] = 0; - Show_VCMA9_Info(s, &s[6]); + vcma9_show_info(s, &s[6]); } - /*printf("\n");*/ - return(0); -} - -int last_stage_init(void) -{ - checkboard(); - stdio_print_current_devices(); - check_env(); return 0; } -/*************************************************************************** - * some helping routines - */ -#if !CONFIG_USB_KEYBOARD -int overwrite_console(void) +int board_late_init(void) { - /* return TRUE if console should be overwritten */ + /* + * check if environment is healthy, otherwise restore values + * from shadow copy + */ + check_env(); return 0; } -#endif -/************************************************************************ -* Print VCMA9 Info -************************************************************************/ -void print_vcma9_info(void) +void vcma9_print_info(void) { - char s[50]; - int i; + char *s = getenv("serial#"); - if ((i = getenv_f("serial#", s, 32)) < 0) { + if (!s) { puts ("### No HW ID - assuming VCMA9"); - printf("i %d", i*24); } else { s[5] = 0; - Show_VCMA9_Info(s, &s[6]); + vcma9_show_info(s, &s[6]); } } @@ -360,3 +214,15 @@ int board_eth_init(bd_t *bis) return rc; } #endif + +/* + * Hardcoded flash setup: + * Flash 0 is a non-CFI AMD AM29F400BB flash. + */ +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + info->portwidth = FLASH_CFI_16BIT; + info->chipwidth = FLASH_CFI_BY16; + info->interface = FLASH_CFI_X16; + return 1; +} diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h index 94fd2fa..7c44194 100644 --- a/board/mpl/vcma9/vcma9.h +++ b/board/mpl/vcma9/vcma9.h @@ -27,108 +27,19 @@ #include <asm/arch/s3c24x0_cpu.h> -extern int mem_test(unsigned long start, unsigned long ramsize,int mode); - -void print_vcma9_info(void); - -#if defined(CONFIG_CMD_NAND) -typedef enum { - NFCE_LOW, - NFCE_HIGH -} NFCE_STATE; - -static inline void NF_Conf(u16 conf) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCONF = conf; -} - -static inline void NF_Cmd(u8 cmd) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCMD = cmd; -} - -static inline void NF_CmdW(u8 cmd) -{ - NF_Cmd(cmd); - udelay(1); -} - -static inline void NF_Addr(u8 addr) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFADDR = addr; -} - -static inline void NF_SetCE(NFCE_STATE s) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - switch (s) { - case NFCE_LOW: - nand->NFCONF &= ~(1<<11); - break; - - case NFCE_HIGH: - nand->NFCONF |= (1<<11); - break; - } -} - -static inline void NF_WaitRB(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - while (!(nand->NFSTAT & (1<<0))); -} - -static inline void NF_Write(u8 data) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFDATA = data; -} - -static inline u8 NF_Read(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - return(nand->NFDATA); -} - -static inline void NF_Init_ECC(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCONF |= (1<<12); -} - -static inline u32 NF_Read_ECC(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - return(nand->NFECC); -} - -#endif - -/* VCMA9 PLD regsiters */ -typedef struct { - u8 ID; - u8 NIC; - u8 CAN; - u8 MISC; - u8 GPCD; - u8 BOARD; - u8 SDRAM; -} /*__attribute__((__packed__))*/ VCMA9_PLD; - -#define VCMA9_PLD_BASE 0x2C000100 -static inline VCMA9_PLD *VCMA9_get_base_PLD(void) -{ - return (VCMA9_PLD * const)VCMA9_PLD_BASE; -} +extern void vcma9_print_info(void); +extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, + int argc, char *const argv[]); + +/* VCMA9 PLD registers */ +enum vcma9_pld_regs { + VCMA9_PLD_ID, + VCMA9_PLD_NIC, + VCMA9_PLD_CAN, + VCMA9_PLD_MISC, + VCMA9_PLD_GPCD, + VCMA9_PLD_BOARD, + VCMA9_PLD_SDRAM +}; + +#define VCMA9_PLD_BASE (0x2C000100) diff --git a/board/mx1ads/config.mk b/board/mx1ads/config.mk deleted file mode 100644 index 2bc5b15..0000000 --- a/board/mx1ads/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# board/mx1ads/config.mk -# -# (c) Copyright 2004 -# Techware Information Technology, Inc. -# http://www.techware.com.tw/ -# -# Ming-Len Wu <minglen_wu@techware.com.tw> -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -CONFIG_SYS_TEXT_BASE = 0x08400000 diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c index f8ce210..86b49fb 100644 --- a/board/mx1ads/mx1ads.c +++ b/board/mx1ads/mx1ads.c @@ -78,7 +78,7 @@ void SetAsynchMode (void) static u32 mc9328sid; -int board_init (void) +int board_early_init_f(void) { volatile unsigned int tmp; @@ -112,10 +112,6 @@ int board_init (void) SetAsynchMode (); - gd->bd->bi_arch_number = MACH_TYPE_MX1ADS; - - gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */ - icache_enable (); dcache_enable (); @@ -133,6 +129,15 @@ int board_init (void) return 0; } +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_MX1ADS; + + gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */ + + return 0; +} + int board_late_init (void) { @@ -161,12 +166,18 @@ int board_late_init (void) return 0; } -int dram_init (void) +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + return 0; +} + +void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; } #ifdef CONFIG_CMD_NET diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c index 47f613c..7331efa 100644 --- a/board/mx1ads/syncflash.c +++ b/board/mx1ads/syncflash.c @@ -276,7 +276,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) { /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + get_timer(0); SF_NvmodeErase(); SF_NvmodeWrite(); diff --git a/board/netstal/common/fixed_sdram.c b/board/netstal/common/fixed_sdram.c deleted file mode 100644 index 51b34b2..0000000 --- a/board/netstal/common/fixed_sdram.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - *(C) Copyright 2005-2008 Netstal Maschinen AG - * Niklaus Giger (Niklaus.Giger@netstal.com) - * - * This source code is free software; you can redistribute it - * and/or modify it in source code form under the terms of the GNU - * General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include "nm.h" - -#if defined(DEBUG) -void show_sdram_registers(void) -{ - u32 value; - - printf("SDRAM Controller Registers --\n"); - mfsdram(SDRAM0_CFG, value); - printf(" SDRAM0_CFG : 0x%08x\n", value); - mfsdram(SDRAM0_STATUS, value); - printf(" SDRAM0_STATUS: 0x%08x\n", value); - mfsdram(SDRAM0_B0CR, value); - printf(" SDRAM0_B0CR : 0x%08x\n", value); - mfsdram(SDRAM0_B1CR, value); - printf(" SDRAM0_B1CR : 0x%08x\n", value); - mfsdram(SDRAM0_TR, value); - printf(" SDRAM0_TR : 0x%08x\n", value); - mfsdram(SDRAM0_RTR, value); - printf(" SDRAM0_RTR : 0x%08x\n", value); -} -#endif - -long int init_ppc405_sdram(unsigned int dram_size) -{ -#ifdef DEBUG - printf(__FUNCTION__); -#endif - /* disable memory controller */ - mtsdram(SDRAM0_CFG, 0x00000000); - - udelay (500); - - /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ - mtsdram(SDRAM0_BESR0, 0xffffffff); - - /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ - mtsdram(SDRAM0_BESR1, 0xffffffff); - - /* Clear SDRAM0_ECCCFG (disable ECC) */ - mtsdram(SDRAM0_ECCCFG, 0x00000000); - - /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ - mtsdram(SDRAM0_ECCESR, 0xffffffff); - - /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 - */ - mtsdram(SDRAM0_TR, 0x008a4015); - - /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 - * and refresh timer - */ - switch (dram_size >> 20) { - case 32: - mtsdram(SDRAM0_B0CR, 0x00062001); - mtsdram(SDRAM0_RTR, 0x07F00000); - break; - case 64: - mtsdram(SDRAM0_B0CR, 0x00084001); - mtsdram(SDRAM0_RTR, 0x04100000); - break; - case 128: - mtsdram(SDRAM0_B0CR, 0x000A4001); - mtsdram(SDRAM0_RTR, 0x04100000); - break; - default: - printf("Invalid memory size of %d MB given\n", dram_size >> 20); - } - - /* Power management idle timer set to the default. */ - mtsdram(SDRAM0_PMIT, 0x07c00000); - - udelay (500); - - /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */ - mtsdram(SDRAM0_CFG, 0x90800000); - -#ifdef DEBUG - printf("%s: done\n", __FUNCTION__); -#endif - return dram_size; -} diff --git a/board/netstal/common/nm.h b/board/netstal/common/nm.h deleted file mode 100644 index 3dff1d6..0000000 --- a/board/netstal/common/nm.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - *(C) Copyright 2005-2007 Netstal Maschinen AG - * Niklaus Giger (Niklaus.Giger@netstal.com) - * - * This source code is free software; you can redistribute it - * and/or modify it in source code form under the terms of the GNU - * General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA - */ - -extern void hcu_led_set(u32 value); -extern u32 get_serial_number(void); -extern u32 hcu_get_slot(void); -extern int board_with_pci(void); -extern void nm_show_print(int generation, int index, int hw_capabilities); -extern void set_params_for_sw_install(int install_requested, char *board_name ); -extern void common_misc_init_r(void); - -enum { - /* HW_GENERATION_HCU1/2 is no longer supported */ - HW_GENERATION_HCU3 = 0x10, - HW_GENERATION_HCU4 = 0x20, - HW_GENERATION_HCU5 = 0x30, - HW_GENERATION_MCU = 0x08, - HW_GENERATION_MCU20 = 0x0a, - HW_GENERATION_MCU25 = 0x09, -}; - -#ifdef CONFIG_405GP -#if defined(DEBUG) -void show_sdram_registers(void); -#endif -long int init_ppc405_sdram(unsigned int dram_size); -#endif diff --git a/board/netstal/common/nm_bsp.c b/board/netstal/common/nm_bsp.c deleted file mode 100644 index 237f4ed..0000000 --- a/board/netstal/common/nm_bsp.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - *(C) Copyright 2005-2008 Netstal Maschinen AG - * Niklaus Giger (Niklaus.Giger@netstal.com) - * - * This source code is free software; you can redistribute it - * and/or modify it in source code form under the terms of the GNU - * General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA - */ - -#include <common.h> -#include <command.h> -#include <net.h> -#include "nm.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define DEFAULT_ETH_ADDR "ethaddr" - -typedef struct {u8 id; char *name;} generation_info; - -generation_info generations[6] = { - {HW_GENERATION_HCU3, "HCU3"}, - {HW_GENERATION_HCU4, "HCU4"}, - {HW_GENERATION_HCU5, "HCU5"}, - {HW_GENERATION_MCU, "MCU"}, - {HW_GENERATION_MCU20, "MCU20"}, - {HW_GENERATION_MCU25, "MCU25"}, -}; - -void nm_show_print(int generation, int index, int hw_capabilities) -{ - int j; - char *generationName=0; - - /* reset ANSI terminal color mode */ - printf("\x1B""[0m""Netstal Maschinen AG: "); - for (j=0; j < (sizeof(generations)/sizeof(generations[0])); j++) { - if (generations[j].id == generation) { - generationName = generations[j].name; - break; - } - } - printf("%s: index %d HW 0x%x\n", generationName, index, hw_capabilities); - for (j = 0;j < 6; j++) { - hcu_led_set(1 << j); - udelay(200 * 1000); - } -} - -void set_params_for_sw_install(int install_requested, char *board_name ) -{ - if (install_requested) { - char string[128]; - - printf("\n\n%s SW-Installation: %d patching boot parameters\n", - board_name, install_requested); - setenv("bootdelay", "0"); - setenv("loadaddr", "0x01000000"); - setenv("serverip", "172.25.1.1"); - setenv("bootcmd", "run install"); - sprintf(string, "tftp ${loadaddr} admin/sw_on_hd; " - "tftp ${loadaddr} installer/%s_sw_inst; " - "run boot_sw_inst", board_name); - setenv("install", string); - sprintf(string, "setenv bootargs emac(0,0)c:%s/%s_sw_inst " - "e=${ipaddr} h=${serverip} f=0x1000; " - "bootvx ${loadaddr}%c", - board_name, board_name, 0); - setenv("boot_sw_inst", string); - } -} - -void common_misc_init_r(void) -{ - IPaddr_t ipaddr; - char *ipstring; - uchar ethaddr[6]; - - if (!eth_getenv_enetaddr(DEFAULT_ETH_ADDR, ethaddr)) { - /* Must be in sync with CONFIG_ETHADDR */ - u32 serial = get_serial_number(); - ethaddr[0] = 0x00; - ethaddr[1] = 0x60; - ethaddr[2] = 0x13; - ethaddr[3] = (serial >> 16) & 0xff; - ethaddr[4] = (serial >> 8) & 0xff; - ethaddr[5] = hcu_get_slot(); - eth_setenv_enetaddr(DEFAULT_ETH_ADDR, ethaddr); - } - - /* IP-Adress update */ - ipstring = getenv("ipaddr"); - if (ipstring == 0) - ipaddr = string_to_ip("172.25.1.99"); - else - ipaddr = string_to_ip(ipstring); - if ((ipaddr & 0xff) != (32 + hcu_get_slot())) { - char tmp[22]; - - ipaddr = (ipaddr & 0xffffff00) + 32 + hcu_get_slot(); - ip_to_string (ipaddr, tmp); - printf("%s: enforce %s\n", __FUNCTION__, tmp); - setenv("ipaddr", tmp); - saveenv(); - } -} diff --git a/board/netstal/hcu4/README.txt b/board/netstal/hcu4/README.txt deleted file mode 100644 index 1e9c64a..0000000 --- a/board/netstal/hcu4/README.txt +++ /dev/null @@ -1,59 +0,0 @@ -HCU4 Configuration Details - -Memory Bank 0 -- Flash chip ---------------------------- - -0xfff00000 - 0xffffffff - -The flash chip is really only 512Kbytes, but the high address bit of -the 1Meg region is ignored, so the flash is replicated through the -region. Thus, this is consistent with a flash base address 0xfff80000. - -The placement at the end is to be consistent with reset behavior, -where the processor itself initially uses this bus to load the branch -vector and start running. - -On-Chip Memory --------------- - -0xf4000000 - 0xf4000fff - -The 405GPr includes a 4K on-chip memory that can be placed however -software chooses. I choose to place the memory at this address, to -keep it out of the cachable areas. - - -Internal Peripherals --------------------- - -0xef600300 - 0xef6008ff - -These are scattered various peripherals internal to the PPC405GPr -chip. - -Chip-Select 2: Flash Memory ---------------------------- - -0x70000000 - -Chip-Select 3: CAN Interface ----------------------------- -0x7800000 - - -Chip-Select 4: IMC-bus standard -------------------------------- - -Our IO-Bus (slow version) - - -Chip-Select 5: IMC-bus fast (inactive) --------------------------------------- - -Our IO-Bus (fast, but not yet use) - - -Memory Bank 1 -- SDRAM -------------------------------------- - -0x00000000 - 0x1ffffff # Default 32 MB diff --git a/board/netstal/hcu4/config.mk b/board/netstal/hcu4/config.mk deleted file mode 100644 index fd3e889..0000000 --- a/board/netstal/hcu4/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2005 Netstal Maschinen AG -# Niklaus Giger (ng@netstal.com) -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Netstal Maschinen AG: HCU4 boards -# -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -g -endif diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c deleted file mode 100644 index aaf3616..0000000 --- a/board/netstal/hcu4/hcu4.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - *(C) Copyright 2005-2008 Netstal Maschinen AG - * Niklaus Giger (Niklaus.Giger@netstal.com) - * - * This source code is free software; you can redistribute it - * and/or modify it in source code form under the terms of the GNU - * General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/u-boot.h> -#include "../common/nm.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define HCU_MACH_VERSIONS_REGISTER (0x7C000000 + 0xF00000) -#define HCU_SLOT_ADDRESS (0x7C000000 + 0x400000) -#define HCU_DIGITAL_IO_REGISTER (0x7C000000 + 0x500000) -#define HCU_SW_INSTALL_REQUESTED 0x10 - -/* - * This function is run very early, out of flash, and before devices are - * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue - * of being in the init_sequence array. - * - * The SDRAM has been initialized already -- start.S:start called - * init.S:init_sdram early on -- but it is not yet being used for - * anything, not even stack. So be careful. - */ - -/* Attention: If you want 1 microsecs times from the external oscillator - * 0x00004051 is okay for u-boot/linux, but different from old vxworks values - * 0x00804051 causes problems with u-boot and linux! - */ -#define CPC0_CR0_VALUE 0x0030103c -#define CPC0_CR1_VALUE 0x00004051 - -int board_early_init_f (void) -{ - /* - * Interrupt controller setup for the HCU4 board. - * Note: IRQ 0-15 405GP internally generated; high; level sensitive - * IRQ 16 405GP internally generated; low; level sensitive - * IRQ 17-24 RESERVED/UNUSED - * IRQ 31 (EXT IRQ 6) (unused) - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */ - mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - mtdcr(CPC0_CR1, CPC0_CR1_VALUE); - mtdcr(CPC0_ECR, 0x60606000); - mtdcr(CPC0_EIRR, 0x7C000000); - - return 0; -} - -#ifdef CONFIG_BOARD_PRE_INIT -int board_pre_init (void) -{ - return board_early_init_f (); -} -#endif - -int sys_install_requested(void) -{ - u16 ioValue = in_be16((u16 *)HCU_DIGITAL_IO_REGISTER); - return (ioValue & HCU_SW_INSTALL_REQUESTED) != 0; -} - -int checkboard (void) -{ - u16 boardVersReg = in_be16((u16 *)HCU_MACH_VERSIONS_REGISTER); - u16 generation = boardVersReg & 0xf0; - u16 index = boardVersReg & 0x0f; - - /* Cannot be done in board_early_init */ - mtdcr(CPC0_CR0, CPC0_CR0_VALUE); - - /* Force /RTS to active. The board it not wired quite - * correctly to use cts/rtc flow control, so just force the - * /RST active and forget about it. - */ - writeb (readb (0xef600404) | 0x03, 0xef600404); - nm_show_print(generation, index, 0); - - return 0; -} - -u32 hcu_led_get(void) -{ - return (~(in_be32((u32 *)GPIO0_OR)) >> 23) & 0xff; -} - -/* - * hcu_led_set value to be placed into the LEDs (max 6 bit) - */ -void hcu_led_set(u32 value) -{ - u32 tmp = ~value; - - tmp = (tmp << 23) | 0x7FFFFF; - out_be32((u32 *)GPIO0_OR, tmp); -} - -/* - * hcu_get_slot - */ -u32 hcu_get_slot(void) -{ - u16 slot = in_be16((u16 *)HCU_SLOT_ADDRESS); - return slot & 0x7f; -} - -/* - * get_serial_number - */ -u32 get_serial_number(void) -{ - u32 serial = in_be32((u32 *)CONFIG_SYS_FLASH_BASE); - - if (serial == 0xffffffff) - return 0; - - return serial; -} - - -/* - * misc_init_r. - */ - -int misc_init_r(void) -{ - common_misc_init_r(); - set_params_for_sw_install( sys_install_requested(), "hcu4" ); - return 0; -} - -phys_size_t initdram(int board_type) -{ - long dram_size = 0; - u16 boardVersReg = in_be16((u16 *)HCU_MACH_VERSIONS_REGISTER); - u16 generation = boardVersReg & 0xf0; - u16 index = boardVersReg & 0x0f; - - if (generation == HW_GENERATION_HCU3 && index < 0xf) - dram_size = 32 << 20; /* 32 MB - RAM */ - else - dram_size = 64 << 20; /* 64 MB - RAM */ - init_ppc405_sdram(dram_size); - -#ifdef DEBUG - show_sdram_registers(); -#endif - - return dram_size; -} - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - -} -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ - -/* - * Hardcoded flash setup: - * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus. - */ -ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) -{ - if (banknum == 0) { /* non-CFI boot flash */ - info->portwidth = 1; - info->chipwidth = 1; - info->interface = FLASH_CFI_X8; - return 1; - } else - return 0; -} diff --git a/board/netstal/hcu5/README.txt b/board/netstal/hcu5/README.txt deleted file mode 100644 index c5737d0..0000000 --- a/board/netstal/hcu5/README.txt +++ /dev/null @@ -1,171 +0,0 @@ -HCU5 configuration details and startup sequence - -(C) Copyright 2007 Netstal Maschinen AG - Niklaus Giger (Niklaus.Giger@netstal.com) - -TODO: ------ -- Fix error: Waiting for PHY auto negotiation to complete..... TIMEOUT ! - - Does not occur if both EMAC are connected -- Fix RTS/CTS problem (HW?) - CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after - Switching to interrupt driven serial input mode - -Caveats: --------- -Errata CHIP_8: Incorrect Write to DDR SDRAM. (was not applied to sequoia.c) -see hcu5.c. - - -Memory Bank 0 -- Flash chip ---------------------------- - -0xfff00000 - 0xffffffff - -The flash chip is really only 512Kbytes, but the high address bit of -the 1Meg region is ignored, so the flash is replicated through the -region. Thus, this is consistent with a flash base address 0xfff80000. - -The placement at the end is to be consistent with reset behavior, -where the processor itself initially uses this bus to load the branch -vector and start running. - -On-Chip Memory --------------- - -0xe0010000- 0xe0013fff CONFIG_SYS_OCM_BASE -The 440EPx includes a 16K on-chip memory that can be placed however -software chooses. - -Internal Peripherals --------------------- - -0xef600300 - 0xef6008ff - -These are scattered various peripherals internal to the PPC440EPX -chip. - -Chip-Select 2: Flash Memory ---------------------------- - -Not used - -Chip-Select 3: CAN Interface ----------------------------- -0xc800000: 2 Intel 82527 CAN-Controller - - -Chip-Select 4: IMC-bus standard -------------------------------- - -0xcc00000: Netstal specific IO-Bus - - -Chip-Select 5: IMC-bus fast (inactive) --------------------------------------- - -0xce00000: Netstal specific IO-Bus (fast, but not yet used) - - -Memory Bank 1 -- DDR2 -------------------------------------- - -0x00000000 - 0xfffffff # Default 256 MB - -PCI ?? - -USB ?? -Only USB_STORAGE is enabled to load vxWorks -from a memory stick. - -System-LEDs ??? (Analog zu HCU4 ???) - -Startup sequence ----------------- - -(arch/powerpc/cpu/ppc4xx/resetvec.S) -depending on configs option -call _start_440 _start_pci oder _start - -(arch/powerpc/cpu/ppc4xx/start.S) - -_start_440: - initialize register like - CCR0 - debug - setup interrupt vectors - configure cache regions - clear and setup TLB - enable internal RAM - jump start_ram - which in turn will jump to start -_start: - Clear and set up some registers. - Debug setup - Setup the internal SRAM - Setup the stack in internal SRAM - setup stack pointer (r1) - setup GOT - call cpu_init_f /* run low-level CPU init code (from Flash) */ - - call cpu_init_f - board_init_f: (arch/powerpc/lib\board.c) - init_sequence defines a list of function to be called - board_early_init_f: (board/netstal/hcu5/hcu5.c) - We are using Bootstrap-Option A - if CPR0_ICFG_RLI_MASK == 0 then set some registers and reboot - Setup the GPIO pins - Setup the interrupt controller polarities, triggers, etc. - Ethernet, PCI, USB enable - setup BOOT FLASH (Chip timing) - init_baudrate, - serial_init - checkcpu - misc_init_f #ifdef - init_func_i2c #ifdef - post_init_f #ifdef - init_func_ram -> calls init_dram board/netstal/hcu5/sdram.c - (EYE function removed!!) - test_dram call - - * Reserve memory at end of RAM for (top down in that order): - * - kernel log buffer - * - protected RAM - * - LCD framebuffer - * - monitor code - * - board info struct - Save local variables to board info struct - call relocate_code() does not return - relocate_code: (arch/powerpc/cpu/ppc4xx/start.S) -------------------------------------------------------- -From now on our copy is in RAM and we will run from there, - starting with board_init_r -------------------------------------------------------- - board_init_r: (arch/powerpc/lib\board.c) - setup bd function pointers - trap_init - flash_init: (board/netstal/hcu5/flash.c) - /* setup for u-boot erase, update */ - setup bd flash info - cpu_init_r: (arch/powerpc/cpu/ppc4xx/cpu_init.c) - peripheral chip select in using defines like - CONFIG_SYS_EBC_PB0A, CONFIG_SYS_EBC_PB0C from hcu5.h - mem_malloc_init - malloc_bin_reloc - spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM) - env_relocated - misc_init_r(bd): (board/netstal/hcu5.c) - ethaddr mit serial number ergänzen - Then we will somehow go into the command loop - -Most of the HW specific code for the HCU5 may be found in -include/configs/hcu5.h -board/netstal/hcu5/* -arch/powerpc/cpu/ppc4xx/* -arch/powerpc/lib/* -include/ppc440.h - -Drivers for serial etc are found under drivers/ - -Don't ask question if you did not look at the README !! -Most CONFIG_SYS_* and CONFIG_* switches are mentioned/explained there. diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c deleted file mode 100644 index f94d05b..0000000 --- a/board/netstal/hcu5/hcu5.c +++ /dev/null @@ -1,414 +0,0 @@ -/* - *(C) Copyright 2005-2008 Netstal Maschinen AG - * Niklaus Giger (Niklaus.Giger@netstal.com) - * - * This source code is free software; you can redistribute it - * and/or modify it in source code form under the terms of the GNU - * General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/ppc440.h> -#include <asm/io.h> -#include <asm/4xx_pci.h> - -#include "../common/nm.h" - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -#undef BOOTSTRAP_OPTION_A_ACTIVE - -#define SDR0_CP440 0x0180 - -#define SYSTEM_RESET 0x30000000 -#define CHIP_RESET 0x20000000 - -#define SDR0_ECID0 0x0080 -#define SDR0_ECID1 0x0081 -#define SDR0_ECID2 0x0082 -#define SDR0_ECID3 0x0083 - -#define SYS_IO_ADDRESS (CONFIG_SYS_CS_2 + 0x00e00000) -#define SYS_SLOT_ADDRESS (CONFIG_SYS_CPLD + 0x00400000) -#define HCU_DIGITAL_IO_REGISTER (CONFIG_SYS_CPLD + 0x0500000) -#define HCU_SW_INSTALL_REQUESTED 0x10 - -/* - * This function is run very early, out of flash, and before devices are - * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue - * of being in the init_sequence array. - * - * The SDRAM has been initialized already -- start.S:start called - * init.S:init_sdram early on -- but it is not yet being used for - * anything, not even stack. So be careful. - */ - -int board_early_init_f(void) -{ - -#ifdef BOOTSTRAP_OPTION_A_ACTIVE - /* Booting with Bootstrap Option A - * First boot, with CPR0_ICFG_RLI_MASK == 0 - * no we setup varios boot strapping register, - * then we do reset the PPC440 using a chip reset - * Unfortunately, we cannot use this option, as Nto1 is not set - * with Bootstrap Option A and cannot be changed later on by SW - * There are no other possible boostrap options with a 8 bit ROM - * See Errata (Version 1.04) CHIP_9 - */ - - u32 cpr0icfg; - u32 dbcr; - - mfcpr(CPR0_ICFG, cpr0icfg); - if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) { - mtcpr(CPR0_MALD, 0x02000000); - mtcpr(CPR0_OPBD, 0x02000000); - mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */ - mtcpr(CPR0_PLLC, 0x40000238); - mtcpr(CPR0_PLLD, 0x01010414); - mtcpr(CPR0_PRIMAD, 0x01000000); - mtcpr(CPR0_PRIMBD, 0x01000000); - mtcpr(CPR0_SPCID, 0x03000000); - mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */ - mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ - mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK); - - /* - * Initiate system reset in debug control register DBCR - */ - dbcr = mfspr(SPRN_DBCR0); - mtspr(SPRN_DBCR0, dbcr | CHIP_RESET); - } - mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ -#endif - mtdcr(EBC0_CFGADDR, EBC0_CFG); - mtdcr(EBC0_CFGDATA, 0xb8400000); - - /* - * Setup the GPIO pins - */ - out32(GPIO0_OR, 0x00000000); - out32(GPIO0_TCR, 0x7C2FF1CF); - out32(GPIO0_OSRL, 0x40055000); - out32(GPIO0_OSRH, 0x00000000); - out32(GPIO0_TSRL, 0x40055000); - out32(GPIO0_TSRH, 0x00000400); - out32(GPIO0_ISR1L, 0x40000000); - out32(GPIO0_ISR1H, 0x00000000); - out32(GPIO0_ISR2L, 0x00000000); - out32(GPIO0_ISR2H, 0x00000000); - out32(GPIO0_ISR3L, 0x00000000); - out32(GPIO0_ISR3H, 0x00000000); - - out32(GPIO1_OR, 0x00000000); - out32(GPIO1_TCR, 0xC6007FFF); - out32(GPIO1_OSRL, 0x00140000); - out32(GPIO1_OSRH, 0x00000000); - out32(GPIO1_TSRL, 0x00000000); - out32(GPIO1_TSRH, 0x00000000); - out32(GPIO1_ISR1L, 0x05415555); - out32(GPIO1_ISR1H, 0x40000000); - out32(GPIO1_ISR2L, 0x00000000); - out32(GPIO1_ISR2H, 0x00000000); - out32(GPIO1_ISR3L, 0x00000000); - out32(GPIO1_ISR3H, 0x00000000); - - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtsdr(SDR0_PFC0, 0x00003E00); /* Pin function: */ - mtsdr(SDR0_PFC1, 0x00848000); /* Pin function: UART0 has 4 pins */ - - /* setup BOOT FLASH */ - mtsdr(SDR0_CUST0, 0xC0082350); - - return 0; -} - -#ifdef CONFIG_BOARD_PRE_INIT -int board_pre_init(void) -{ - return board_early_init_f(); -} - -#endif - -int sys_install_requested(void) -{ - u16 *ioValuePtr = (u16 *)HCU_DIGITAL_IO_REGISTER; - return (in_be16(ioValuePtr) & HCU_SW_INSTALL_REQUESTED) != 0; -} - -int checkboard(void) -{ - u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER; - u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER; - u16 generation = in_be16(boardVersReg) & 0xf0; - u16 index = in_be16(boardVersReg) & 0x0f; - u32 ecid0, ecid1, ecid2, ecid3; - - nm_show_print(generation, index, in_be16(hwVersReg) & 0xff); - mfsdr(SDR0_ECID0, ecid0); - mfsdr(SDR0_ECID1, ecid1); - mfsdr(SDR0_ECID2, ecid2); - mfsdr(SDR0_ECID3, ecid3); - - printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3); - - return 0; -} - -u32 hcu_led_get(void) -{ - return in16(SYS_IO_ADDRESS) & 0x3f; -} - -/* - * hcu_led_set value to be placed into the LEDs (max 6 bit) - */ -void hcu_led_set(u32 value) -{ - out16(SYS_IO_ADDRESS, value); -} - -/* - * get_serial_number - */ -u32 get_serial_number(void) -{ - u32 *serial = (u32 *)CONFIG_SYS_FLASH_BASE; - - if (in_be32(serial) == 0xffffffff) - return 0; - - return in_be32(serial); -} - - -/* - * hcu_get_slot - */ -u32 hcu_get_slot(void) -{ - u16 *slot = (u16 *)SYS_SLOT_ADDRESS; - return in_be16(slot) & 0x7f; -} - - -/* - * misc_init_r. - */ -int misc_init_r(void) -{ - unsigned long usb2d0cr = 0; - unsigned long usb2phy0cr, usb2h0cr = 0; - unsigned long sdr0_pfc1; - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - -#ifdef CONFIG_ENV_ADDR_REDUND - /* Env protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif -#endif - - /* - * USB stuff... - */ - - /* SDR Setting */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - mfsdr(SDR0_USB2D0CR, usb2d0cr); - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mfsdr(SDR0_USB2H0CR, usb2h0cr); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ - - /* An 8-bit/60MHz interface is the only possible alternative - * when connecting the Device to the PHY - */ - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ - - /* To enable the USB 2.0 Device function through the UTMI interface */ - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/ - - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/ - - mtsdr(SDR0_PFC1, sdr0_pfc1); - mtsdr(SDR0_USB2D0CR, usb2d0cr); - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mtsdr(SDR0_USB2H0CR, usb2h0cr); - - /*clear resets*/ - udelay(1000); - mtsdr(SDR0_SRST1, 0x00000000); - udelay(1000); - mtsdr(SDR0_SRST0, 0x00000000); - printf("USB: Host(int phy) Device(ext phy)\n"); - - common_misc_init_r(); - set_params_for_sw_install( sys_install_requested(), "hcu5" ); - /* We cannot easily enable trace before, as there are other - * routines messing around with sdr0_pfc1. And I do not need it. - */ - if (mfspr(SPRN_DBCR0) & 0x80000000) { - /* External debugger alive - * enable trace facilty for Lauterbach - * CCR0[DTB]=0 Enable broadcast of trace information - * SDR0_PFC0[TRE] Trace signals are enabled instead of - * GPIO49-63 - */ - mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) &~ (CCR0_DTB)); - mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE); - } - return 0; -} -#ifdef CONFIG_PCI -int board_with_pci(void) -{ - u32 reg; - - mfsdr(SDR0_PCI0, reg); - return (reg & SDR0_PCI0_PAE_MASK); -} - -/* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - */ -int pci_pre_init(struct pci_controller *hose) -{ - unsigned long addr; - - if (!board_with_pci()) { return 0; } - - /* - * Set priority for all PLB3 devices to 0. - * Set PLB3 arbiter to fair mode. - */ - mfsdr(SDR0_AMP1, addr); - mtsdr(SDR0_AMP1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB3A0_ACR); - mtdcr(PLB3A0_ACR, addr | 0x80000000); /* Sequoia */ - - /* - * Set priority for all PLB4 devices to 0. - */ - mfsdr(SDR0_AMP0, addr); - mtsdr(SDR0_AMP0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB4A0_ACR) | 0xa0000000; /* Was 0x8---- */ - mtdcr(PLB4A0_ACR, addr); /* Sequoia */ - - /* - * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM. - * Workaround: Disable write pipelining to DDR SDRAM by setting - * PLB4A0_ACR[WRP] = 0. - */ - mtdcr(PLB4A0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ - - /* Segment1 */ - mtdcr(PLB4A1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ - - return board_with_pci(); -} - -/* - * Override weak default pci_master_init() - */ -void pci_master_init(struct pci_controller *hose) -{ - if (!board_with_pci()) - return; - - __pci_master_init(hose); -} -#endif /* defined(CONFIG_PCI) */ - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - -} -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ - -/* - * Hardcoded flash setup: - * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus. - */ -ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) -{ - if (banknum == 0) { /* non-CFI boot flash */ - info->portwidth = 1; - info->chipwidth = 1; - info->interface = FLASH_CFI_X8; - return 1; - } else - return 0; -} diff --git a/board/netstal/hcu5/init.S b/board/netstal/hcu5/init.S deleted file mode 100644 index 45e63dd..0000000 --- a/board/netstal/hcu5/init.S +++ /dev/null @@ -1,106 +0,0 @@ -/* - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */ - tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG ) - /* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */ - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, - AC_RWX | SA_IG ) - - /* TLB#2: TLB-entry for EBC */ - tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_RWX | SA_IG) - - /* - * TLB#3: BOOT_CS (FLASH) must be forth. Before relocation SA_I can be - * off to use the speed up boot process. It is patched after relocation - * to enable SA_I - */ - tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_1M, CONFIG_SYS_BOOT_BASE_ADDR, 1, - AC_RWX | SA_G) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - /* TLB#4: */ - tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, - AC_RW | SA_IG ) - /* TLB#5: */ - tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, - AC_RW | SA_IG ) - /* TLB#6: */ - tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, - AC_RW | SA_IG ) - - /* TLB-entry for Internal Registers & OCM */ - /* TLB#7: */ - tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, - AC_RWX | SA_IG ) - - /*TLB-entry PCI registers*/ - /* TLB#8: */ - tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG ) - - /* TLB-entry for peripherals */ - /* TLB#9: */ - tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) - - /* CAN */ - /* TLB#10: */ - tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_RWX | SA_IG ) - - /* TLB#11: CPLD and IMC-Standard 32 MB */ - tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_RWX | SA_IG ) - - /* TLB#12: */ - tlbentry( CONFIG_SYS_CS_2 + 0x1000000, SZ_16M, CONFIG_SYS_CS_2 + 0x1000000, 1, - AC_RWX | SA_IG ) - - /* IMC-Fast 32 MB */ - /* TLB#13: */ - tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_RWX | SA_IG ) - /* TLB#14: */ - tlbentry( CONFIG_SYS_CS_3 + 0x1000000, SZ_16M, CONFIG_SYS_CS_3, 1, - AC_RWX | SA_IG ) - - tlbtab_end diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c deleted file mode 100644 index e5ac46b..0000000 --- a/board/netstal/hcu5/sdram.c +++ /dev/null @@ -1,283 +0,0 @@ -/* - * (C) Copyright 2007 - * Niklaus Giger (Niklaus.Giger@netstal.com) - * (C) Copyright 2006 - * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* define DEBUG for debug output */ -#undef DEBUG - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmu.h> -#include <asm/cache.h> -#include <asm/ppc440.h> - -void hcu_led_set(u32 value); -void dcbz_area(u32 start_address, u32 num_bytes); - -#define ECC_RAM 0x03267F0B -#define NO_ECC_RAM 0x00267F0B - -#define HCU_HW_SDRAM_CONFIG_MASK 0x7 - -#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE - /* disable caching on DDR2 */ - -void board_add_ram_info(int use_default) -{ - PPC4xx_SYS_INFO board_cfg; - u32 val; - - mfsdram(DDR0_22, val); - val &= DDR0_22_CTRL_RAW_MASK; - switch (val) { - case DDR0_22_CTRL_RAW_ECC_DISABLE: - puts(" (ECC disabled"); - break; - case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY: - puts(" (ECC check only"); - break; - case DDR0_22_CTRL_RAW_NO_ECC_RAM: - puts(" (no ECC ram"); - break; - case DDR0_22_CTRL_RAW_ECC_ENABLE: - puts(" (ECC enabled"); - break; - } - - get_sys_info(&board_cfg); - printf(", %lu MHz", (board_cfg.freqPLB * 2) / 1000000); - - mfsdram(DDR0_03, val); - val = DDR0_03_CASLAT_DECODE(val); - printf(", CL%d)", val); -} - -/*-------------------------------------------------------------------- - * wait_for_dlllock. - *--------------------------------------------------------------------*/ -static int wait_for_dlllock(void) -{ - unsigned long val; - int wait = 0; - - /* -----------------------------------------------------------+ - * Wait for the DCC master delay line to finish calibration - * ----------------------------------------------------------*/ - mtdcr(SDRAM0_CFGADDR, DDR0_17); - val = DDR0_17_DLLLOCKREG_UNLOCKED; - - while (wait != 0xffff) { - val = mfdcr(SDRAM0_CFGDATA); - if ((val & DDR0_17_DLLLOCKREG_MASK) == - DDR0_17_DLLLOCKREG_LOCKED) - /* dlllockreg bit on */ - return 0; - else - wait++; - } - debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val); - debug("Waiting for dlllockreg bit to raise\n"); - - return -1; -} - -/*********************************************************************** - * - * sdram_panic -- Panic if we cannot configure the sdram correctly - * - ************************************************************************/ -void sdram_panic(const char *reason) -{ - printf("\n%s: reason %s", __FUNCTION__, reason); - hcu_led_set(0xff); - while (1) { - } - /* Never return */ -} - -#ifdef CONFIG_DDR_ECC -void blank_string(int size) -{ - int i; - - for (i=0; i<size; i++) - putc('\b'); - for (i=0; i<size; i++) - putc(' '); - for (i=0; i<size; i++) - putc('\b'); -} -/*---------------------------------------------------------------------------+ - * program_ecc. - *---------------------------------------------------------------------------*/ -static void program_ecc(unsigned long start_address, unsigned long num_bytes) -{ - u32 val; - char str[] = "ECC generation -"; -#if defined(CONFIG_PRAM) - u32 *magicPtr; - u32 magic; - - if ((mfspr(SPRN_DBCR0) & 0x80000000) == 0) { - /* only if no external debugger is alive! - * Check whether vxWorks is using EDR logging, if yes zero - * also PostMortem and user reserved memory - */ - magicPtr = (u32 *)(start_address + num_bytes - - (CONFIG_PRAM*1024) + sizeof(u32)); - magic = in_be32(magicPtr); - debug("%s: CONFIG_PRAM %d kB magic 0x%x 0x%p\n", - __FUNCTION__, CONFIG_PRAM, - magicPtr, magic); - if (magic == 0xbeefbabe) { - printf("%s: preserving at %p\n", __FUNCTION__, magicPtr); - num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM; - } - } -#endif - - sync(); - - puts(str); - - /* ECC bit set method for cached memory */ - /* Fast method, no noticeable delay */ - dcbz_area(start_address, num_bytes); - /* Write modified dcache lines back to memory */ - clean_dcache_range(start_address, start_address + num_bytes); - blank_string(strlen(str)); - - /* Clear error status */ - mfsdram(DDR0_00, val); - mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); - - /* - * Clear possible ECC errors - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - mtspr(SPRN_MCSR, mfspr(SPRN_MCSR)); - - /* Set 'int_mask' parameter to functionnal value */ - mfsdram(DDR0_01, val); - mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | - DDR0_01_INT_MASK_ALL_OFF)); - - return; -} -#endif - - -/*********************************************************************** - * - * initdram -- 440EPx's DDR controller is a DENALI Core - * - ************************************************************************/ -phys_size_t initdram (int board_type) -{ - unsigned int dram_size = 0; - - mtsdram(DDR0_02, 0x00000000); - - /* Values must be kept in sync with Excel-table <<A0001492.>> ! */ - mtsdram(DDR0_00, 0x0000190A); - mtsdram(DDR0_01, 0x01000000); - mtsdram(DDR0_03, 0x02030602); - mtsdram(DDR0_04, 0x0A020200); - mtsdram(DDR0_05, 0x02020307); - switch (in_be16((u16 *)HCU_HW_VERSION_REGISTER) & HCU_HW_SDRAM_CONFIG_MASK) { - case 1: - dram_size = 256 * 1024 * 1024 ; - mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */ - mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */ - mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */ - break; - case 0: - default: - dram_size = 128 * 1024 * 1024 ; - mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */ - mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */ - mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */ - break; - } - mtsdram(DDR0_07, 0x00090100); - - /* - * TCPD=200 cycles of clock input is required to lock the DLL. - * CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001); - */ - mtsdram(DDR0_08, 0x02C80001); - mtsdram(DDR0_09, 0x00011D5F); - mtsdram(DDR0_10, 0x00000100); - mtsdram(DDR0_12, 0x00000003); - mtsdram(DDR0_14, 0x00000000); - mtsdram(DDR0_17, 0x1D000000); - mtsdram(DDR0_18, 0x1D1D1D1D); - mtsdram(DDR0_19, 0x1D1D1D1D); - mtsdram(DDR0_20, 0x0B0B0B0B); - mtsdram(DDR0_21, 0x0B0B0B0B); -#ifdef CONFIG_DDR_ECC - mtsdram(DDR0_22, ECC_RAM); -#else - mtsdram(DDR0_22, NO_ECC_RAM); -#endif - - mtsdram(DDR0_23, 0x00000000); - mtsdram(DDR0_24, 0x01020001); - mtsdram(DDR0_26, 0x2D930517); - mtsdram(DDR0_27, 0x00008236); - mtsdram(DDR0_28, 0x00000000); - mtsdram(DDR0_31, 0x00000000); - mtsdram(DDR0_42, 0x01000006); - mtsdram(DDR0_44, 0x00000003); - mtsdram(DDR0_02, 0x00000001); - wait_for_dlllock(); - mtsdram(DDR0_00, 0x40000000); /* Zero init bit */ - - /* - * Program tlb entries for this size (dynamic) - */ - remove_tlb(CONFIG_SYS_SDRAM_BASE, 256 << 20); - program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE); - - /* - * Setup 2nd TLB with same physical address but different virtual - * address with cache enabled. This is done for fast ECC generation. - */ - program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, dram_size, 0); - -#ifdef CONFIG_DDR_ECC - /* - * If ECC is enabled, initialize the parity bits. - */ - program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, dram_size); -#endif - - return (dram_size); -} diff --git a/board/netstal/mcu25/README.txt b/board/netstal/mcu25/README.txt deleted file mode 100644 index d25fddd..0000000 --- a/board/netstal/mcu25/README.txt +++ /dev/null @@ -1,59 +0,0 @@ -MCU25 Configuration Details - -Memory Bank 0 -- Flash chip ---------------------------- - -0xfff00000 - 0xffffffff - -The flash chip is really only 512Kbytes, but the high address bit of -the 1Meg region is ignored, so the flash is replicated through the -region. Thus, this is consistent with a flash base address 0xfff80000. - -The placement at the end is to be consistent with reset behavior, -where the processor itself initially uses this bus to load the branch -vector and start running. - -On-Chip Memory --------------- - -0xf4000000 - 0xf4000fff - -The 405GPr includes a 4K on-chip memory that can be placed however -software chooses. I choose to place the memory at this address, to -keep it out of the cachable areas. - - -Internal Peripherals --------------------- - -0xef600300 - 0xef6008ff - -These are scattered various peripherals internal to the PPC405GPr -chip. - -Chip-Select 2: Flash Memory ---------------------------- - -0x70000000 - -Chip-Select 3: CAN Interface ----------------------------- -0x7800000 - - -Chip-Select 4: IMC-bus standard -------------------------------- - -Our IO-Bus (slow version) - - -Chip-Select 5: IMC-bus fast (inactive) --------------------------------------- - -Our IO-Bus (fast, but not yet use) - - -Memory Bank 1 -- SDRAM -------------------------------------- - -0x00000000 - 0x2ffffff # Default 64 MB diff --git a/board/netstal/mcu25/config.mk b/board/netstal/mcu25/config.mk deleted file mode 100644 index 61dc091..0000000 --- a/board/netstal/mcu25/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2005 Netstal Maschinen AG -# Niklaus Giger (ng@netstal.com) -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Netstal Maschinen AG: MCU25 board -# -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -g -endif diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c deleted file mode 100644 index 36fb388..0000000 --- a/board/netstal/mcu25/mcu25.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - *(C) Copyright 2005-2008 Netstal Maschinen AG - * Niklaus Giger (Niklaus.Giger@netstal.com) - * - * This source code is free software; you can redistribute it - * and/or modify it in source code form under the terms of the GNU - * General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/u-boot.h> -#include "../common/nm.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define MCU25_SLOT_ADDRESS (0x7A000000 + 0x0A) -#define MCU25_DIGITAL_IO_REGISTER (0x7A000000 + 0xc0) - -#define MCU25_LED_REGISTER_ADDRESS (0x7C000000 + 0x10) -#define MCU25_VERSIONS_REGISTER (0x7C000000 + 0x0C) -#define MCU25_IO_CONFIGURATION (0x7C000000 + 0x0e) -#define MCU_SW_INSTALL_REQUESTED 0x08 - -#define SDRAM_LEN (32 << 20) /* 32 MB - RAM */ - -/* - * This function is run very early, out of flash, and before devices are - * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue - * of being in the init_sequence array. - * - * The SDRAM has been initialized already -- start.S:start called - * init.S:init_sdram early on -- but it is not yet being used for - * anything, not even stack. So be careful. - */ - -/* Attention: If you want 1 microsecs times from the external oscillator - * 0x00004051 is okay for u-boot/linux, but different from old vxworks values - * 0x00804051 causes problems with u-boot and linux! - */ -#define CPC0_CR0_VALUE 0x0007F03C -#define CPC0_CR1_VALUE 0x00004051 - -int board_early_init_f (void) -{ - /* Documented in A-1171 - * - * Interrupt controller setup for the MCU25 board. - * Note: IRQ 0-15 405GP internally generated; high; level sensitive - * IRQ 16 405GP internally generated; low; level sensitive - * IRQ 17-24 RESERVED/UNUSED - * IRQ 31 (EXT IRQ 6) (unused) - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */ - mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - mtdcr(CPC0_CR1, CPC0_CR1_VALUE); - mtdcr(CPC0_ECR, 0x60606000); - mtdcr(CPC0_EIRR, 0x7C000000); - out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR ); - out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); - out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR); - mtspr(SPRN_CCR0, 0x00700000); - - return 0; -} - -#ifdef CONFIG_BOARD_PRE_INIT -int board_pre_init (void) -{ - return board_early_init_f (); -} -#endif - -int sys_install_requested(void) -{ - u16 ioValue = in_be16((u16 *)MCU25_DIGITAL_IO_REGISTER); - return (ioValue & MCU_SW_INSTALL_REQUESTED) != 0; -} - -int checkboard (void) -{ - u16 boardVersReg = in_be16((u16 *)MCU25_VERSIONS_REGISTER); - u16 hwConfig = in_be16((u16 *)MCU25_IO_CONFIGURATION); - u16 generation = boardVersReg & 0x0f; - u16 index = boardVersReg & 0xf0; - - /* Cannot be done in board_early_init */ - mtdcr(CPC0_CR0, CPC0_CR0_VALUE); - - /* Force /RTS to active. The board it not wired quite - * correctly to use cts/rtc flow control, so just force the - * /RST active and forget about it. - */ - writeb (readb (0xef600404) | 0x03, 0xef600404); - nm_show_print(generation, index, hwConfig); - return 0; -} - -u32 hcu_led_get(void) -{ - return in_be16((u16 *)MCU25_LED_REGISTER_ADDRESS) & 0x3ff; -} - -/* - * hcu_led_set value to be placed into the LEDs (max 6 bit) - */ -void hcu_led_set(u32 value) -{ - out_be16((u16 *)MCU25_LED_REGISTER_ADDRESS, value); -} - -/* - * hcu_get_slot - */ -u32 hcu_get_slot(void) -{ - u16 slot = in_be16((u16 *)MCU25_SLOT_ADDRESS); - return slot & 0x7f; -} - -/* - * get_serial_number - */ -u32 get_serial_number(void) -{ - u32 serial = in_be32((u32 *)CONFIG_SYS_FLASH_BASE); - - if (serial == 0xffffffff) - return 0; - - return serial; -} - - -/* - * misc_init_r. - */ - -int misc_init_r(void) -{ - common_misc_init_r(); - set_params_for_sw_install( sys_install_requested(), "mcu25" ); - return 0; -} - -phys_size_t initdram(int board_type) -{ - unsigned int dram_size = 64*1024*1024; - init_ppc405_sdram(dram_size); - -#ifdef DEBUG - show_sdram_registers(); -#endif - - return dram_size; -} - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - -} -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ - -/* - * Hardcoded flash setup: - * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus. - */ -ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) -{ - if (banknum == 0) { /* non-CFI boot flash */ - info->portwidth = 1; - info->chipwidth = 1; - info->interface = FLASH_CFI_X8; - return 1; - } else - return 0; -} diff --git a/board/ns9750dev/flash.c b/board/ns9750dev/flash.c index 5b56b98..185bc2d 100644 --- a/board/ns9750dev/flash.c +++ b/board/ns9750dev/flash.c @@ -261,7 +261,7 @@ void flash_unprotect_sectors (FPWV * addr) int flash_erase (flash_info_t * info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -294,10 +294,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("\n"); } - - start = get_timer (0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -312,7 +308,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) flash_unprotect_sectors (addr); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); *addr = (FPW) 0x00500050;/* clear status register */ *addr = (FPW) 0x00200020;/* erase setup */ @@ -321,7 +317,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); /* suspend erase */ @@ -441,6 +437,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) FPWV *addr = (FPWV *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -454,11 +451,11 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 3d6c248..8ab9440 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -32,6 +32,10 @@ #include <asm/arch/uart.h> #include "board.h" +#ifdef CONFIG_TEGRA2_MMC +#include <mmc.h> +#endif + DECLARE_GLOBAL_DATA_PTR; const struct tegra2_sysinfo sysinfo = { @@ -62,7 +66,6 @@ int board_early_init_f(void) */ int timer_init(void) { - reset_timer(); return 0; } @@ -171,6 +174,116 @@ static void pin_mux_uart(void) } /* + * Routine: clock_init_mmc + * Description: init the PLL and clocks for the SDMMC controllers + */ +static void clock_init_mmc(void) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; + + /* Do the SDMMC resets/clock enables */ + + /* Assert Reset to SDMMC4 */ + reg = readl(&clkrst->crc_rst_dev_l); + reg |= SWR_SDMMC4_RST; /* SWR_SDMMC4_RST = 1 */ + writel(reg, &clkrst->crc_rst_dev_l); + + /* Enable clk to SDMMC4 */ + reg = readl(&clkrst->crc_clk_out_enb_l); + reg |= CLK_ENB_SDMMC4; /* CLK_ENB_SDMMC4 = 1 */ + writel(reg, &clkrst->crc_clk_out_enb_l); + + /* Enable pllp_out0 to SDMMC4 */ + reg = readl(&clkrst->crc_clk_src_sdmmc4); + reg &= 0x3FFFFF00; /* SDMMC4_CLK_SRC = 00, PLLP_OUT0 */ + reg |= (10 << 1); /* n-1, 11-1 shl 1 */ + writel(reg, &clkrst->crc_clk_src_sdmmc4); + + /* + * As per the Tegra2 TRM, section 5.3.4: + * 'Wait 2 us for the clock to flush through the pipe/logic' + */ + udelay(2); + + /* De-assert reset to SDMMC4 */ + reg = readl(&clkrst->crc_rst_dev_l); + reg &= ~SWR_SDMMC4_RST; /* SWR_SDMMC4_RST = 0 */ + writel(reg, &clkrst->crc_rst_dev_l); + + /* Assert Reset to SDMMC3 */ + reg = readl(&clkrst->crc_rst_dev_u); + reg |= SWR_SDMMC3_RST; /* SWR_SDMMC3_RST = 1 */ + writel(reg, &clkrst->crc_rst_dev_u); + + /* Enable clk to SDMMC3 */ + reg = readl(&clkrst->crc_clk_out_enb_u); + reg |= CLK_ENB_SDMMC3; /* CLK_ENB_SDMMC3 = 1 */ + writel(reg, &clkrst->crc_clk_out_enb_u); + + /* Enable pllp_out0 to SDMMC4, set divisor to 11 for 20MHz */ + reg = readl(&clkrst->crc_clk_src_sdmmc3); + reg &= 0x3FFFFF00; /* SDMMC3_CLK_SRC = 00, PLLP_OUT0 */ + reg |= (10 << 1); /* n-1, 11-1 shl 1 */ + writel(reg, &clkrst->crc_clk_src_sdmmc3); + + /* wait for 2us */ + udelay(2); + + /* De-assert reset to SDMMC3 */ + reg = readl(&clkrst->crc_rst_dev_u); + reg &= ~SWR_SDMMC3_RST; /* SWR_SDMMC3_RST = 0 */ + writel(reg, &clkrst->crc_rst_dev_u); +} + +/* + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) + */ +static void pin_mux_mmc(void) +{ + struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 reg; + + /* SDMMC4 */ + /* config 2, x8 on 2nd set of pins */ + reg = readl(&pmt->pmt_ctl_a); + reg |= (3 << 16); /* ATB_SEL [17:16] = 11 SDIO4 */ + writel(reg, &pmt->pmt_ctl_a); + reg = readl(&pmt->pmt_ctl_b); + reg |= (3 << 0); /* GMA_SEL [1:0] = 11 SDIO4 */ + writel(reg, &pmt->pmt_ctl_b); + reg = readl(&pmt->pmt_ctl_d); + reg |= (3 << 0); /* GME_SEL [1:0] = 11 SDIO4 */ + writel(reg, &pmt->pmt_ctl_d); + + reg = readl(&pmt->pmt_tri_a); + reg &= ~Z_ATB; /* Z_ATB = normal (0) */ + reg &= ~Z_GMA; /* Z_GMA = normal (0) */ + writel(reg, &pmt->pmt_tri_a); + reg = readl(&pmt->pmt_tri_b); + reg &= ~Z_GME; /* Z_GME = normal (0) */ + writel(reg, &pmt->pmt_tri_b); + + /* SDMMC3 */ + /* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */ + reg = readl(&pmt->pmt_ctl_d); + reg &= 0xFFFF03FF; + reg |= (2 << 10); /* SDB_SEL [11:10] = 01 SDIO3 */ + reg |= (2 << 12); /* SDC_SEL [13:12] = 01 SDIO3 */ + reg |= (2 << 14); /* SDD_SEL [15:14] = 01 SDIO3 */ + writel(reg, &pmt->pmt_ctl_d); + + reg = readl(&pmt->pmt_tri_b); + reg &= ~Z_SDC; /* Z_SDC = normal (0) */ + reg &= ~Z_SDD; /* Z_SDD = normal (0) */ + writel(reg, &pmt->pmt_tri_b); + reg = readl(&pmt->pmt_tri_d); + reg &= ~Z_SDB; /* Z_SDB = normal (0) */ + writel(reg, &pmt->pmt_tri_d); +} + +/* * Routine: clock_init * Description: Do individual peripheral clock reset/enables */ @@ -210,3 +323,36 @@ int board_init(void) return 0; } + +#ifdef CONFIG_TEGRA2_MMC +/* this is a weak define that we are overriding */ +int board_mmc_init(bd_t *bd) +{ + debug("board_mmc_init called\n"); + /* Enable clocks, muxes, etc. for SDMMC controllers */ + clock_init_mmc(); + pin_mux_mmc(); + + debug("board_mmc_init: init eMMC\n"); + /* init dev 0, eMMC chip, with 4-bit bus */ + tegra2_mmc_init(0, 4); + + debug("board_mmc_init: init SD slot\n"); + /* init dev 1, SD slot, with 4-bit bus */ + tegra2_mmc_init(1, 4); + + return 0; +} + +/* this is a weak define that we are overriding */ +int board_mmc_getcd(u8 *cd, struct mmc *mmc) +{ + debug("board_mmc_getcd called\n"); + /* + * Hard-code CD presence for now. Need to add GPIO inputs + * for Seaboard & Harmony (& Kaen/Aebl/Wario?) + */ + *cd = 1; + return 0; +} +#endif diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h index 350bc57..4334c02 100644 --- a/board/nvidia/common/board.h +++ b/board/nvidia/common/board.h @@ -29,5 +29,6 @@ void clock_init(void); void pinmux_init(void); void gpio_init(void); void gpio_config_uart(void); +int tegra2_mmc_init(int dev_index, int bus_width); #endif /* BOARD_H */ diff --git a/board/pcs440ep/config.mk b/board/pcs440ep/config.mk index 23631c5..f560ec6 100644 --- a/board/pcs440ep/config.mk +++ b/board/pcs440ep/config.mk @@ -26,7 +26,7 @@ # # Check the U-Boot Image with a SHA1 checksum -ALL += $(obj)u-boot.sha1 +ALL-y += $(obj)u-boot.sha1 PLATFORM_CPPFLAGS += -DCONFIG_440=1 diff --git a/board/pleb2/flash.c b/board/pleb2/flash.c index a8897dc..2406c5f 100644 --- a/board/pleb2/flash.c +++ b/board/pleb2/flash.c @@ -472,7 +472,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) FPWV *addr; int flag, prot, sect; int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong now, last; + ulong start, now, last; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -516,8 +516,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("\n"); } - reset_timer_masked (); - /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last && rcode == 0; sect++) { @@ -527,7 +525,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); - reset_timer_masked (); + start = get_timer(0); last = 0; addr = (FPWV *) (info->start[sect]); @@ -559,7 +557,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { if ((now = - get_timer_masked ()) > CONFIG_SYS_FLASH_ERASE_TOUT) { + get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); if (intel) { @@ -661,6 +659,7 @@ static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) int flag; int res = 0; /* result, assume success */ FPWV *base; /* first address in flash bank */ + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*dest & data) != data) { @@ -683,12 +682,12 @@ static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) if (flag) enable_interrupts (); - reset_timer_masked (); + start = get_timer(0); /* data polling for D7 */ while (res == 0 && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW) 0x00F000F0; /* reset bank */ res = 1; } @@ -711,6 +710,7 @@ static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data) { int flag; int res = 0; /* result, assume success */ + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*dest & data) != data) { @@ -730,10 +730,10 @@ static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data) if (flag) enable_interrupts (); - reset_timer_masked (); + start = get_timer(0); while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW) 0x00B000B0; /* Suspend program */ res = 1; } diff --git a/board/prodrive/pdnb3/config.mk b/board/prodrive/pdnb3/config.mk deleted file mode 100644 index 817541f..0000000 --- a/board/prodrive/pdnb3/config.mk +++ /dev/null @@ -1,2 +0,0 @@ -# -CONFIG_SYS_TEXT_BASE = 0x01f00000 diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index e0f44dd..2c50fe8 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -282,7 +282,7 @@ int board_eth_init(bd_t *bis) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM, + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; } diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index ec9f865..8071600 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -379,7 +379,7 @@ int board_init(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM, + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; } diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 79b7c9d..fa69599 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -160,7 +160,7 @@ int board_init(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM, + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; } diff --git a/board/samsung/smdk2400/flash.c b/board/samsung/smdk2400/flash.c index fb69c21..47382fe 100644 --- a/board/samsung/smdk2400/flash.c +++ b/board/samsung/smdk2400/flash.c @@ -231,6 +231,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) ulong result, result1; int iflag, prot, sect; int rc = ERR_OK; + ulong start; #ifdef USE_920T_MMU int cflag; @@ -286,7 +287,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) sect, info->start[sect]); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ vu_long *addr = (vu_long *) (info->start[sect]); @@ -299,7 +300,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* wait until flash is ready */ do { /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = CMD_STATUS_RESET; result = BIT_TIMEOUT; break; @@ -359,6 +360,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) ulong result; int rc = ERR_OK; int iflag; + ulong start; #ifdef USE_920T_MMU int cflag; @@ -389,12 +391,12 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait until flash is ready */ do { /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = CMD_SUSPEND; result = BIT_TIMEOUT; break; diff --git a/board/sbc2410x/flash.c b/board/sbc2410x/flash.c index abb0935..d209a6f 100644 --- a/board/sbc2410x/flash.c +++ b/board/sbc2410x/flash.c @@ -173,6 +173,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) int iflag, cflag, prot, sect; int rc = ERR_OK; int chip; + ulong start; /* first look for protection bits */ @@ -213,7 +214,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ vu_short *addr = (vu_short *) (info->start[sect]); @@ -233,7 +234,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) result = *addr; /* check timeout */ - if (get_timer_masked () > + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; chip = TMO; @@ -295,6 +296,7 @@ static int write_hword (flash_info_t * info, ulong dest, ushort data) int rc = ERR_OK; int cflag, iflag; int chip; + ulong start; /* * Check if Flash is (sufficiently) erased @@ -322,7 +324,7 @@ static int write_hword (flash_info_t * info, ulong dest, ushort data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + get_timer(start); /* wait until flash is ready */ chip = 0; @@ -330,7 +332,7 @@ static int write_hword (flash_info_t * info, ulong dest, ushort data) result = *addr; /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { chip = ERR | TMO; break; } diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index dd58541..bed8f53 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -63,7 +63,7 @@ phys_size_t initdram (int board_type) dram_size = fixed_sdram (); #endif - puts (" DDR: "); + debug (" DDR: "); return dram_size; } diff --git a/board/scb9328/config.mk b/board/scb9328/config.mk deleted file mode 100644 index 7c5e067..0000000 --- a/board/scb9328/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# This config file is used for compilation of scb93328 sources -# -# You might change location of U-Boot in memory by setting right CONFIG_SYS_TEXT_BASE. -# This allows for example having one copy located at the end of ram and stored -# in flash device and later on while developing use other location to test -# the code in RAM device only. -# - -CONFIG_SYS_TEXT_BASE = 0x08f00000 diff --git a/board/scb9328/flash.c b/board/scb9328/flash.c index c6f94ae..00c660a 100644 --- a/board/scb9328/flash.c +++ b/board/scb9328/flash.c @@ -97,11 +97,12 @@ static FLASH_BUS_RET flash_status_reg (void) static int flash_ready (ulong timeout) { int ok = 1; + ulong start; - reset_timer_masked (); + start = get_timer(0); while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) != FLASH_CMD (CFI_INTEL_SR_READY)) { - if (get_timer_masked () > timeout && timeout != 0) { + if (get_timer(start) > timeout && timeout != 0) { ok = 0; break; } diff --git a/board/scb9328/scb9328.c b/board/scb9328/scb9328.c index 428e8c9..2e31e8c 100644 --- a/board/scb9328/scb9328.c +++ b/board/scb9328/scb9328.c @@ -39,23 +39,17 @@ int board_init (void) int dram_init (void) { -#if ( CONFIG_NR_DRAM_BANKS > 0 ) + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((volatile void *)SCB9328_SDRAM_1, + SCB9328_SDRAM_1_SIZE); + + return 0; +} + +void dram_init_banksize(void) +{ gd->bd->bi_dram[0].start = SCB9328_SDRAM_1; gd->bd->bi_dram[0].size = SCB9328_SDRAM_1_SIZE; -#endif -#if ( CONFIG_NR_DRAM_BANKS > 1 ) - gd->bd->bi_dram[1].start = SCB9328_SDRAM_2; - gd->bd->bi_dram[1].size = SCB9328_SDRAM_2_SIZE; -#endif -#if ( CONFIG_NR_DRAM_BANKS > 2 ) - gd->bd->bi_dram[2].start = SCB9328_SDRAM_3; - gd->bd->bi_dram[2].size = SCB9328_SDRAM_3_SIZE; -#endif -#if ( CONFIG_NR_DRAM_BANKS > 3 ) - gd->bd->bi_dram[3].start = SCB9328_SDRAM_4; - gd->bd->bi_dram[3].size = SCB9328_SDRAM_4_SIZE; -#endif - return 0; } /** diff --git a/board/shannon/flash.c b/board/shannon/flash.c index 0455afa..179ec5f 100644 --- a/board/shannon/flash.c +++ b/board/shannon/flash.c @@ -190,6 +190,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) int iflag, cflag, prot, sect; int rc = ERR_OK; int chip1, chip2; + ulong start; /* first look for protection bits */ @@ -231,7 +232,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); if (info->protect[sect] == 0) { /* not protected */ @@ -253,7 +254,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) result = *addr; /* check timeout */ - if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; chip1 = TMO; @@ -322,6 +323,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) int rc = ERR_OK; int cflag, iflag; int chip1, chip2; + ulong start; /* * Check if Flash is (sufficiently) erased @@ -349,7 +351,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + start = get_timer(0); /* wait until flash is ready */ chip1 = chip2 = 0; @@ -358,7 +360,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) result = *addr; /* check timeout */ - if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { chip1 = ERR | TMO; break; diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c index 0562222..0812c20 100644 --- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -46,9 +46,7 @@ int dram_init(void) struct xloader_table_1_2 *table_1_2; struct chip_data *chip = &chip_data; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size(PHYS_SDRAM_1, - PHYS_SDRAM_1_MAXSIZE); + gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE); if (XLOADER_TABLE_VERSION_1_1 == xloader_tb->table_version) { table_1_1 = &xloader_tb->table.table_1_1; @@ -66,6 +64,12 @@ int dram_init(void) return 0; } +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = gd->ram_size; +} + int misc_init_r(void) { #if defined(CONFIG_CMD_NET) diff --git a/board/spear/spear300/config.mk b/board/spear/spear300/config.mk index 11da2c3..5848ef8 100644 --- a/board/spear/spear300/config.mk +++ b/board/spear/spear300/config.mk @@ -25,7 +25,7 @@ CONFIG_SYS_TEXT_BASE = 0x00700000 -ALL += $(obj)u-boot.img +ALL-y += $(obj)u-boot.img # Environment variables in NAND ifeq ($(ENV),NAND) diff --git a/board/spear/spear310/config.mk b/board/spear/spear310/config.mk index 2b59c39..f8a6bdb 100644 --- a/board/spear/spear310/config.mk +++ b/board/spear/spear310/config.mk @@ -25,7 +25,7 @@ CONFIG_SYS_TEXT_BASE = 0x00700000 -ALL += $(obj)u-boot.img +ALL-y += $(obj)u-boot.img # Environment variables in NAND ifeq ($(ENV),NAND) diff --git a/board/spear/spear320/config.mk b/board/spear/spear320/config.mk index 2b59c39..f8a6bdb 100644 --- a/board/spear/spear320/config.mk +++ b/board/spear/spear320/config.mk @@ -25,7 +25,7 @@ CONFIG_SYS_TEXT_BASE = 0x00700000 -ALL += $(obj)u-boot.img +ALL-y += $(obj)u-boot.img # Environment variables in NAND ifeq ($(ENV),NAND) diff --git a/board/spear/spear600/config.mk b/board/spear/spear600/config.mk index 11da2c3..5848ef8 100644 --- a/board/spear/spear600/config.mk +++ b/board/spear/spear600/config.mk @@ -25,7 +25,7 @@ CONFIG_SYS_TEXT_BASE = 0x00700000 -ALL += $(obj)u-boot.img +ALL-y += $(obj)u-boot.img # Environment variables in NAND ifeq ($(ENV),NAND) diff --git a/board/st-ericsson/u8500/u8500_href.c b/board/st-ericsson/u8500/u8500_href.c index 525633e..9283fab 100644 --- a/board/st-ericsson/u8500/u8500_href.c +++ b/board/st-ericsson/u8500/u8500_href.c @@ -27,6 +27,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #ifdef CONFIG_MMC +#include "prcmu-fw.h" #include "../../../drivers/mmc/arm_pl180_mmci.h" #endif diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c index 83ffcd2..3077eb3 100644 --- a/board/stx/stxssa/stxssa.c +++ b/board/stx/stxssa/stxssa.c @@ -34,6 +34,7 @@ #include <asm/processor.h> #include <asm/mmu.h> #include <asm/immap_85xx.h> +#include <asm/fsl_pci.h> #include <asm/fsl_ddr_sdram.h> #include <ioports.h> #include <asm/io.h> @@ -247,6 +248,13 @@ reset_phy(void) #endif } +#ifdef CONFIG_OF_BOARD_SETUP +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup (blob, bd); +} +#endif /* CONFIG_OF_BOARD_SETUP */ + int board_early_init_f(void) { diff --git a/board/syteco/jadecpu/config.mk b/board/syteco/jadecpu/config.mk deleted file mode 100644 index 617603d..0000000 --- a/board/syteco/jadecpu/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x10000000 diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c index 69476f8..63a0d33 100644 --- a/board/syteco/jadecpu/jadecpu.c +++ b/board/syteco/jadecpu/jadecpu.c @@ -44,6 +44,7 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000; icache_enable(); + dcache_enable(); return 0; } @@ -125,9 +126,6 @@ int board_late_init(void) setenv("preboot", "run gs_slow_boot"); } else if ((in_word & 0xC0) != 0) { setenv("stdout", "vga"); - setenv("gs_bootcmd", "mw.l 0x40000000 0 1024; usb start;" - "fatls usb 0; fatload usb 0 0x40000000 mcq5resq.bin;" - "bootelf 0x40000000; bootelf 0x10080000"); setenv("preboot", "run gs_slow_boot"); } else { setenv("stdin", "serial"); @@ -136,7 +134,6 @@ int board_late_init(void) if (getenv("gs_devel")) { setenv("preboot", "run gs_slow_boot"); } else { - setenv("gs_bootcmd", "bootelf 0x10080000"); setenv("preboot", "run gs_fast_boot"); } } @@ -155,7 +152,7 @@ int misc_init_r(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM, + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; diff --git a/board/netstal/mcu25/Makefile b/board/syteco/zmx25/Makefile index a983de9..5a0e5b3 100644 --- a/board/netstal/mcu25/Makefile +++ b/board/syteco/zmx25/Makefile @@ -1,6 +1,9 @@ # -# (C) Copyright 2007-2008 Netstal Maschinen AG -# Niklaus Giger (ng@netstal.com) +# (c) 2010 Graf-Syteco, Matthias Weisser +# <weisserm@arcor.de> +# +# See file CREDITS for list of people who contributed to this +# project. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as @@ -19,24 +22,21 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif LIB = $(obj)lib$(BOARD).o -COBJS = $(BOARD).o \ - ../common/fixed_sdram.o \ - ../common/nm_bsp.o +COBJS-y += zmx25.o +SOBJS := lowlevel_init.o -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) - $(call cmd_link_o_target, $^) +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) clean: - rm -f $(OBJS) + rm -f $(SOBJS) $(OBJS) distclean: clean rm -f $(LIB) core *.bak $(obj).depend diff --git a/board/syteco/zmx25/lowlevel_init.S b/board/syteco/zmx25/lowlevel_init.S new file mode 100644 index 0000000..8e63de0 --- /dev/null +++ b/board/syteco/zmx25/lowlevel_init.S @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2011 + * Matthias Weisser <weisserm@arcor.de> + * + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby <jrigby@gmail.com> + * + * Based on U-Boot and RedBoot sources for several different i.mx + * platforms. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/macro.h> +#include <asm/arch/macro.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/asm-offsets.h> + +/* + * clocks + */ +.macro init_clocks + + /* disable clock output */ + write32 IMX_CCM_BASE + CCM_MCR, 0x00000000 + write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000 + + /* + * enable all implemented clocks in all three + * clock control registers + */ + write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff + write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff + write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff + + /* Devide NAND clock by 32 */ + write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F +.endm + +/* + * sdram controller init + */ +.macro init_lpddr + ldr r0, =IMX_ESDRAMC_BASE + ldr r2, =IMX_SDRAM_BANK0_BASE + + /* + * reset SDRAM controller + * then wait for initialization to complete + */ + ldr r1, =(1 << 1) | (1 << 2) + str r1, [r0, #ESDRAMC_ESDMISC] +1: ldr r3, [r0, #ESDRAMC_ESDMISC] + tst r3, #(1 << 31) + beq 1b + ldr r1, =(1 << 2) + str r1, [r0, #ESDRAMC_ESDMISC] + + ldr r1, =0x002a7420 + str r1, [r0, #ESDRAMC_ESDCFG0] + + /* control | precharge */ + ldr r1, =0x92216008 + str r1, [r0, #ESDRAMC_ESDCTL0] + /* dram command encoded in address */ + str r1, [r2, #0x400] + + /* auto refresh */ + ldr r1, =0xa2216008 + str r1, [r0, #ESDRAMC_ESDCTL0] + /* read dram twice to auto refresh */ + ldr r3, [r2] + ldr r3, [r2] + + /* control | load mode */ + ldr r1, =0xb2216008 + str r1, [r0, #ESDRAMC_ESDCTL0] + + /* mode register of lpddram */ + strb r1, [r2, #0x33] + + /* extended mode register of lpddrram */ + ldr r2, =0x81000000 + strb r1, [r2] + + /* control | normal */ + ldr r1, =0x82216008 + str r1, [r0, #ESDRAMC_ESDCTL0] +.endm + +.globl lowlevel_init +lowlevel_init: + init_aips + init_max + init_clocks + init_lpddr + mov pc, lr diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c new file mode 100644 index 0000000..f055038 --- /dev/null +++ b/board/syteco/zmx25/zmx25.c @@ -0,0 +1,203 @@ +/* + * (c) 2011 Graf-Syteco, Matthias Weisser + * <weisserm@arcor.de> + * + * Based on tx25.c: + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby <jrigby@gmail.com> + * + * Based on imx27lite.c: + * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net> + * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com> + * And: + * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> +#include <mxc_gpio.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/imx25-pinmux.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init() +{ + struct iomuxc_mux_ctl *muxctl; + struct iomuxc_pad_ctl *padctl; + struct iomuxc_pad_input_select *inputselect; + u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION; + u32 gpio_mux_mode1 = MX25_PIN_MUX_MODE(1); + u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5); + u32 gpio_mux_mode6 = MX25_PIN_MUX_MODE(6); + u32 input_select1 = MX25_PAD_INPUT_SELECT_DAISY(1); + u32 input_select2 = MX25_PAD_INPUT_SELECT_DAISY(2); + + icache_enable(); + + muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; + padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; + inputselect = (struct iomuxc_pad_input_select *)IMX_IOPADINPUTSEL_BASE; + + /* Setup of core volatage selection pin to run at 1.4V */ + writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */ + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 15), MXC_GPIO_DIRECTION_OUT); + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 15), 1); + + /* Setup of input daisy chains for SD card pins*/ + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_clk); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data0); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data1); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data2); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data3); + + /* Setup of digital output for USB power and OC */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */ + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 28), MXC_GPIO_DIRECTION_OUT); + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 28), 1); + + writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */ + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 18), MXC_GPIO_DIRECTION_IN); + + /* Setup of digital output control pins */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d7); /* Ouput 2 Ctrl GPIO1[6] */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d6); /* Ouput 1 Stat GPIO1[31]*/ + writel(gpio_mux_mode5, &muxctl->pad_csi_d5); /* Ouput 2 Stat GPIO1[30]*/ + + writel(0, &padctl->pad_csi_d6); /* Ouput 1 Stat pull up off */ + writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */ + + /* Switch both output drivers off */ + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 7), 0); + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 7), MXC_GPIO_DIRECTION_OUT); + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 6), 0); + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 6), MXC_GPIO_DIRECTION_OUT); + + /* Setup of key input pin GPIO2[29]*/ + writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0); + writel(0, &padctl->pad_kpp_row0); /* Key pull up off */ + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(2, 29), MXC_GPIO_DIRECTION_IN); + + /* Setup of status LED outputs */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */ + + /* Switch both LEDs off */ + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0); + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(4, 21), MXC_GPIO_DIRECTION_OUT); + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0); + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 29), MXC_GPIO_DIRECTION_OUT); + + /* Setup of CAN1 and CAN2 signals */ + writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */ + writel(gpio_mux_mode6, &muxctl->pad_gpio_b); /* CAN1 RX */ + writel(gpio_mux_mode6, &muxctl->pad_gpio_c); /* CAN2 TX */ + writel(gpio_mux_mode6, &muxctl->pad_gpio_d); /* CAN2 RX */ + + /* Setup of input daisy chains for CAN signals*/ + writel(input_select1, &inputselect->can1_ipp_ind_canrx); /* CAN1 RX */ + writel(input_select1, &inputselect->can2_ipp_ind_canrx); /* CAN2 RX */ + + /* Setup of I2C3 signals */ + writel(gpio_mux_mode1, &muxctl->pad_cspi1_ss1); /* I2C3 SDA */ + writel(gpio_mux_mode1, &muxctl->pad_gpio_e); /* I2C3 SCL */ + + /* Setup of input daisy chains for I2C3 signals*/ + writel(input_select1, &inputselect->i2c3_ipp_sda_in); /* I2C3 SDA */ + writel(input_select2, &inputselect->i2c3_ipp_scl_in); /* I2C3 SCL */ + + /* board id for linux */ + gd->bd->bi_arch_number = MACH_TYPE_ZMX25; + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int board_late_init(void) +{ + const char *e; + +#ifdef CONFIG_FEC_MXC + struct iomuxc_mux_ctl *muxctl; + struct iomuxc_pad_ctl *padctl; + u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2); + u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5); + + /* + * fec pin init is generic + */ + mx25_fec_init_pins(); + + /* + * Set up LAN-RESET and FEC_RX_ERR + * + * LAN-RESET: GPIO3[16] is ALT 5 mode of pin U20 + * FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2 + */ + muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; + padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; + + writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk); + writel(gpio_mux_mode2, &muxctl->pad_uart2_cts); + + /* assert PHY reset (low) */ + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 0); + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 16), MXC_GPIO_DIRECTION_OUT); + + udelay(5000); + + /* deassert PHY reset */ + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 1); + + udelay(5000); +#endif + + e = getenv("gs_base_board"); + if (e != NULL) { + if (strcmp(e, "G283") == 0) { + int key = mxc_gpio_get(MXC_GPIO_PORT_TO_NUM(2, 29)); + + if (key) { + /* Switch on both LEDs to inidcate boot mode */ + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0); + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0); + + setenv("preboot", "run gs_slow_boot"); + } else + setenv("preboot", "run gs_fast_boot"); + } + } + + return 0; +} + +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, + PHYS_SDRAM_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = gd->ram_size; +} diff --git a/board/tcm-bf537/tcm-bf537.c b/board/tcm-bf537/tcm-bf537.c index 04d6bdb..004e0d9 100644 --- a/board/tcm-bf537/tcm-bf537.c +++ b/board/tcm-bf537/tcm-bf537.c @@ -24,27 +24,37 @@ int checkboard(void) return 0; } -#ifdef CONFIG_BFIN_MAC -static void board_init_enetaddr(uchar *mac_addr) +static void board_init_enetaddr(char *var) { - puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); - eth_setenv_enetaddr("ethaddr", mac_addr); +#ifdef CONFIG_NET_MULTI + uchar enetaddr[6]; + + if (eth_getenv_enetaddr(var, enetaddr)) + return; + + printf("Warning: %s: generating 'random' MAC address\n", var); + bfin_gen_rand_mac(enetaddr); + eth_setenv_enetaddr(var, enetaddr); +#endif } +#ifndef CONFIG_BFIN_MAC +# define bfin_EMAC_initialize(x) 1 +#endif +#ifndef CONFIG_SMC911X +# define smc911x_initialize(n, x) 1 +#endif int board_eth_init(bd_t *bis) { - return bfin_EMAC_initialize(bis); + /* return ok if at least 1 eth device works */ + return bfin_EMAC_initialize(bis) & + smc911x_initialize(0, CONFIG_SMC911X_BASE); } -#endif int misc_init_r(void) { -#ifdef CONFIG_BFIN_MAC - uchar enetaddr[6]; - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) - board_init_enetaddr(enetaddr); -#endif + board_init_enetaddr("ethaddr"); + board_init_enetaddr("eth1addr"); gpio_cfi_flash_init(); diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index aaf3033..30c1c57 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -33,10 +33,14 @@ #include <asm/arch/mem.h> #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> #include <i2c.h> #include <asm/mach-types.h> #include "evm.h" +#define OMAP3EVM_GPIO_ETH_RST_GEN1 64 +#define OMAP3EVM_GPIO_ETH_RST_GEN2 7 + DECLARE_GLOBAL_DATA_PTR; static u32 omap3_evm_version; @@ -130,6 +134,9 @@ int misc_init_r(void) #endif omap3_evm_get_revision(); +#if defined(CONFIG_CMD_NET) + reset_net_chip(); +#endif dieid_num_r(); return 0; @@ -146,6 +153,7 @@ void set_muxconf_regs(void) MUX_EVM(); } +#ifdef CONFIG_CMD_NET /* * Routine: setup_net_chip * Description: Setting up the configuration GPMC registers specific to the @@ -153,7 +161,6 @@ void set_muxconf_regs(void) */ static void setup_net_chip(void) { - struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE; struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; /* Configure GPMC registers */ @@ -172,16 +179,37 @@ static void setup_net_chip(void) /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, &ctrl_base->gpmc_nadv_ale); +} - /* Make GPIO 64 as output pin */ - writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe); - - /* Now send a pulse on the GPIO pin */ - writel(GPIO0, &gpio3_base->setdataout); +/** + * Reset the ethernet chip. + */ +static void reset_net_chip(void) +{ + int ret; + int rst_gpio; + + if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) { + rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1; + } else { + rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2; + } + + ret = omap_request_gpio(rst_gpio); + if (ret < 0) { + printf("Unable to get GPIO %d\n", rst_gpio); + return ; + } + + /* Configure as output */ + omap_set_gpio_direction(rst_gpio, 0); + + /* Send a pulse on the GPIO pin */ + omap_set_gpio_dataout(rst_gpio, 1); udelay(1); - writel(GPIO0, &gpio3_base->cleardataout); + omap_set_gpio_dataout(rst_gpio, 0); udelay(1); - writel(GPIO0, &gpio3_base->setdataout); + omap_set_gpio_dataout(rst_gpio, 1); } int board_eth_init(bd_t *bis) @@ -192,3 +220,4 @@ int board_eth_init(bd_t *bis) #endif return rc; } +#endif /* CONFIG_CMD_NET */ diff --git a/board/ti/evm/evm.h b/board/ti/evm/evm.h index b721ad6..623cf1b 100644 --- a/board/ti/evm/evm.h +++ b/board/ti/evm/evm.h @@ -49,6 +49,7 @@ u32 get_omap3_evm_rev(void); #if defined(CONFIG_CMD_NET) static void setup_net_chip(void); +static void reset_net_chip(void); #endif /* diff --git a/board/ti/omap1610inn/flash.c b/board/ti/omap1610inn/flash.c index 36200ad..1b67d08 100644 --- a/board/ti/omap1610inn/flash.c +++ b/board/ti/omap1610inn/flash.c @@ -278,7 +278,7 @@ void flash_unprotect_sectors (FPWV * addr) int flash_erase (flash_info_t * info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -311,10 +311,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("\n"); } - - start = get_timer (0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -329,7 +325,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) flash_unprotect_sectors (addr); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); *addr = (FPW) 0x00500050;/* clear status register */ *addr = (FPW) 0x00200020;/* erase setup */ @@ -338,7 +334,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); /* suspend erase */ @@ -458,6 +454,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) FPWV *addr = (FPWV *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -470,11 +467,11 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/ti/omap730p2/flash.c b/board/ti/omap730p2/flash.c index 5b56b98..185bc2d 100644 --- a/board/ti/omap730p2/flash.c +++ b/board/ti/omap730p2/flash.c @@ -261,7 +261,7 @@ void flash_unprotect_sectors (FPWV * addr) int flash_erase (flash_info_t * info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -294,10 +294,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("\n"); } - - start = get_timer (0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -312,7 +308,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) flash_unprotect_sectors (addr); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); *addr = (FPW) 0x00500050;/* clear status register */ *addr = (FPW) 0x00200020;/* erase setup */ @@ -321,7 +317,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); /* suspend erase */ @@ -441,6 +437,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) FPWV *addr = (FPWV *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -454,11 +451,11 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/ti/panda/Makefile b/board/ti/panda/Makefile index 2186403..09f88ee 100644 --- a/board/ti/panda/Makefile +++ b/board/ti/panda/Makefile @@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +ifndef CONFIG_SPL_BUILD COBJS := panda.o +endif SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/ti/panda/config.mk b/board/ti/panda/config.mk deleted file mode 100644 index 33901a7..0000000 --- a/board/ti/panda/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2006-2009 -# Texas Instruments Incorporated, <www.ti.com> -# -# OMAP 4430 SDP -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# SDRAM Address Space: -# 8000'0000 - 9fff'ffff (512 MB) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -CONFIG_SYS_TEXT_BASE = 0x80e80000 diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index 78e1910..9afed80 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -25,7 +25,7 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h> -#include "panda.h" +#include "panda_mux_data.h" DECLARE_GLOBAL_DATA_PTR; @@ -65,27 +65,14 @@ int misc_init_r(void) return 0; } -void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) +void set_muxconf_regs_non_essential(void) { - int i; - struct pad_conf_entry *pad = (struct pad_conf_entry *) array; - - for (i = 0; i < size; i++, pad++) - writew(pad->val, base + pad->offset); -} - -/** - * @brief set_muxconf_regs Setting up the configuration Mux registers - * specific to the board. - */ -void set_muxconf_regs(void) -{ - do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array, - sizeof(core_padconf_array) / + do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, + sizeof(core_padconf_array_non_essential) / sizeof(struct pad_conf_entry)); - do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array, - sizeof(wkup_padconf_array) / + do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, + sizeof(wkup_padconf_array_non_essential) / sizeof(struct pad_conf_entry)); } diff --git a/board/ti/sdp4430/sdp.h b/board/ti/panda/panda_mux_data.h index bf41067..16cc0ad 100644 --- a/board/ti/sdp4430/sdp.h +++ b/board/ti/panda/panda_mux_data.h @@ -23,22 +23,12 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ +#ifndef _SDP4430_MUX_DATA_H +#define _SDP4430_MUX_DATA_H -#ifndef _SDP_H_ -#define _SDP_H_ - -#include <asm/io.h> #include <asm/arch/mux_omap4.h> -const struct pad_conf_entry core_padconf_array[] = { - {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ - {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ - {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ - {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ - {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ - {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ - {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ - {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ +const struct pad_conf_entry core_padconf_array_non_essential[] = { {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ @@ -64,8 +54,6 @@ const struct pad_conf_entry core_padconf_array[] = { {GPMC_NWP, (M3)}, /* gpio_54 */ {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ - {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ - {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ @@ -96,14 +84,14 @@ const struct pad_conf_entry core_padconf_array[] = { {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ - {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ - {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ - {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ - {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ - {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ - {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ - {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ - {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ + {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */ + {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */ + {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */ + {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */ + {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */ + {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ + {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ + {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ @@ -112,22 +100,12 @@ const struct pad_conf_entry core_padconf_array[] = { {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ - {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ - {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ - {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ - {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ - {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ - {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ - {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ - {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ - {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ - {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (IEN | M1)}, /* abe_slimbus1_clock */ - {ABE_MCBSP1_DR, (IEN | M1)}, /* abe_slimbus1_data */ + {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ + {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ @@ -144,14 +122,6 @@ const struct pad_conf_entry core_padconf_array[] = { {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ {UART2_TX, (M0)}, /* uart2_tx */ {HDQ_SIO, (M3)}, /* gpio_127 */ - {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ - {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ - {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ - {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ - {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ - {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ - {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ - {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ @@ -159,10 +129,6 @@ const struct pad_conf_entry core_padconf_array[] = { {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ - {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ - {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ - {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ - {UART3_TX_IRTX, (M0)}, /* uart3_tx */ {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ @@ -175,7 +141,7 @@ const struct pad_conf_entry core_padconf_array[] = { {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ {UART4_RX, (IEN | M0)}, /* uart4_rx */ {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ + {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ @@ -207,11 +173,11 @@ const struct pad_conf_entry core_padconf_array[] = { {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ + {SYS_NIRQ2, (M7)}, /* sys_nirq2 */ {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ {SYS_BOOT1, (M3)}, /* gpio_185 */ {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (M3)}, /* gpio_187 */ + {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ {SYS_BOOT4, (M3)}, /* gpio_188 */ {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ @@ -236,14 +202,12 @@ const struct pad_conf_entry core_padconf_array[] = { {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ }; -const struct pad_conf_entry wkup_padconf_array[] = { +const struct pad_conf_entry wkup_padconf_array_non_essential[] = { {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ {PAD1_SIM_CLK, (M0)}, /* sim_clk */ {PAD0_SIM_RESET, (M0)}, /* sim_reset */ {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ - {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ {PAD1_FREF_XTAL_IN, (M0)}, /* # */ {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ @@ -252,13 +216,15 @@ const struct pad_conf_entry wkup_padconf_array[] = { {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ {PAD0_FREF_CLK4_OUT, (M0)}, /* # */ - {PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */ {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ + {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */ + {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 */ + {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 */ }; -#endif +#endif /* _SDP4430_MUX_DATA_H */ diff --git a/board/ti/sdp4430/Makefile b/board/ti/sdp4430/Makefile index f1ee544..12f2743 100644 --- a/board/ti/sdp4430/Makefile +++ b/board/ti/sdp4430/Makefile @@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +ifndef CONFIG_SPL_BUILD COBJS := sdp.o cmd_bat.o +endif SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/ti/sdp4430/config.mk b/board/ti/sdp4430/config.mk deleted file mode 100644 index 33901a7..0000000 --- a/board/ti/sdp4430/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2006-2009 -# Texas Instruments Incorporated, <www.ti.com> -# -# OMAP 4430 SDP -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# SDRAM Address Space: -# 8000'0000 - 9fff'ffff (512 MB) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -CONFIG_SYS_TEXT_BASE = 0x80e80000 diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index b13c4c5..a5ea682 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -27,7 +27,7 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h> -#include "sdp.h" +#include "sdp4430_mux_data.h" DECLARE_GLOBAL_DATA_PTR; @@ -70,27 +70,14 @@ int misc_init_r(void) return 0; } -void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) +void set_muxconf_regs_non_essential(void) { - int i; - struct pad_conf_entry *pad = (struct pad_conf_entry *) array; - - for (i = 0; i < size; i++, pad++) - writew(pad->val, base + pad->offset); -} - -/** - * @brief set_muxconf_regs Setting up the configuration Mux registers - * specific to the board. - */ -void set_muxconf_regs(void) -{ - do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array, - sizeof(core_padconf_array) / + do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, + sizeof(core_padconf_array_non_essential) / sizeof(struct pad_conf_entry)); - do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array, - sizeof(wkup_padconf_array) / + do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, + sizeof(wkup_padconf_array_non_essential) / sizeof(struct pad_conf_entry)); } diff --git a/board/ti/panda/panda.h b/board/ti/sdp4430/sdp4430_mux_data.h index e3d090e..16cc0ad 100644 --- a/board/ti/panda/panda.h +++ b/board/ti/sdp4430/sdp4430_mux_data.h @@ -23,22 +23,12 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ +#ifndef _SDP4430_MUX_DATA_H +#define _SDP4430_MUX_DATA_H -#ifndef _PANDA_H_ -#define _PANDA_H_ - -#include <asm/io.h> #include <asm/arch/mux_omap4.h> -const struct pad_conf_entry core_padconf_array[] = { - {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ - {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ - {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ - {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ - {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ - {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ - {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ - {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ +const struct pad_conf_entry core_padconf_array_non_essential[] = { {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ @@ -53,7 +43,7 @@ const struct pad_conf_entry core_padconf_array[] = { {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ {GPMC_A20, (IEN | M3)}, /* gpio_44 */ {GPMC_A21, (M3)}, /* gpio_45 */ - {GPMC_A22, (M3)}, /* gpio_46 */ + {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ {GPMC_A24, (PTD | M3)}, /* gpio_48 */ {GPMC_A25, (PTD | M3)}, /* gpio_49 */ @@ -64,14 +54,12 @@ const struct pad_conf_entry core_padconf_array[] = { {GPMC_NWP, (M3)}, /* gpio_54 */ {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ - {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ - {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ - {GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */ + {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ - {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101 */ + {C2C_DATA12, (M1)}, /* dsi1_te0 */ {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ {C2C_DATA14, (M1)}, /* dsi2_te0 */ {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ @@ -96,14 +84,14 @@ const struct pad_conf_entry core_padconf_array[] = { {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ - {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ - {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ - {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ - {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ - {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ - {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ - {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ - {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ + {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */ + {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */ + {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */ + {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */ + {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */ + {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ + {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ + {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ @@ -112,22 +100,12 @@ const struct pad_conf_entry core_padconf_array[] = { {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ - {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ - {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ - {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ - {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ - {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ - {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ - {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ - {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ - {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ - {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (IEN | M1)}, /* abe_slimbus1_clock */ - {ABE_MCBSP1_DR, (IEN | M1)}, /* abe_slimbus1_data */ + {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ + {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ @@ -144,14 +122,6 @@ const struct pad_conf_entry core_padconf_array[] = { {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ {UART2_TX, (M0)}, /* uart2_tx */ {HDQ_SIO, (M3)}, /* gpio_127 */ - {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ - {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ - {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ - {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ - {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ - {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ - {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ - {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ @@ -159,10 +129,6 @@ const struct pad_conf_entry core_padconf_array[] = { {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ - {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ - {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ - {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ - {UART3_TX_IRTX, (M0)}, /* uart3_tx */ {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ @@ -175,7 +141,7 @@ const struct pad_conf_entry core_padconf_array[] = { {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ {UART4_RX, (IEN | M0)}, /* uart4_rx */ {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ + {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ @@ -189,12 +155,12 @@ const struct pad_conf_entry core_padconf_array[] = { {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ - {UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */ + {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ - {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */ - {UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */ + {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ + {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ @@ -205,13 +171,13 @@ const struct pad_conf_entry core_padconf_array[] = { {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ - {FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182 */ + {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ + {SYS_NIRQ2, (M7)}, /* sys_nirq2 */ {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ {SYS_BOOT1, (M3)}, /* gpio_185 */ {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (M3)}, /* gpio_187 */ + {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ {SYS_BOOT4, (M3)}, /* gpio_188 */ {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ @@ -236,29 +202,29 @@ const struct pad_conf_entry core_padconf_array[] = { {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ }; -const struct pad_conf_entry wkup_padconf_array[] = { - {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ - {PAD1_SIM_CLK, (M0)}, /* sim_clk */ - {PAD0_SIM_RESET, (M0)}, /* sim_reset */ - {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ - {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ - {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ - {PAD1_FREF_XTAL_IN, (M0)}, /* # */ - {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ - {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ - {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */ - {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ - {PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */ - {PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_2 */ - {PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */ - {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ +const struct pad_conf_entry wkup_padconf_array_non_essential[] = { + {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ + {PAD1_SIM_CLK, (M0)}, /* sim_clk */ + {PAD0_SIM_RESET, (M0)}, /* sim_reset */ + {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ + {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ + {PAD1_FREF_XTAL_IN, (M0)}, /* # */ + {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ + {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ + {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ + {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */ + {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ + {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ + {PAD0_FREF_CLK4_OUT, (M0)}, /* # */ + {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ + {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ + {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ + {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ + {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ + {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ + {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */ + {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 */ + {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 */ }; -#endif +#endif /* _SDP4430_MUX_DATA_H */ diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index 2aa97f2..260e392 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -59,7 +59,7 @@ ulong flash_get_size (ulong base, int banknum); /* Local functions */ static int detect_num_flash_banks(void); -static long int get_ddr_bank_size(short cs, volatile long *base); +static long int get_ddr_bank_size(short cs, long *base); static void set_cs_bounds(short cs, long base, long size); static void set_cs_config(short cs, long config); static void set_ddr_config(void); @@ -120,7 +120,7 @@ phys_size_t initdram (int board_type) debug("\nDetecting Bank%d\n", cs); bank_size = get_ddr_bank_size(cs, - (volatile long*)(CONFIG_SYS_DDR_BASE + size)); + (long *)(CONFIG_SYS_DDR_BASE + size)); size += bank_size; debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20); @@ -262,7 +262,7 @@ static int detect_num_flash_banks(void) /************************************************************************* * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly. */ -static long int get_ddr_bank_size(short cs, volatile long *base) +static long int get_ddr_bank_size(short cs, long *base) { /* This array lists all valid DDR SDRAM configurations, with * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM). diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index 39a9e21..baf073e 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -363,6 +363,12 @@ static phys_size_t sdram_setup(int casl) udelay (1000); #endif /* CONFIG_TQM8548 */ + /* + * get_ram_size() depends on having tlbs for the DDR, but they are + * not yet setup because we don't know the size. Set up a temp + * mapping and delete it when done. + */ + setup_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB); for (i = 0; i < N_DDR_CS_CONF; i++) { ddr->cs0_config = ddr_cs_conf[i].reg; @@ -376,6 +382,7 @@ static phys_size_t sdram_setup(int casl) break; } } + clear_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB); #ifdef CONFIG_TQM8548 if (i < N_DDR_CS_CONF) { diff --git a/board/trab/Makefile b/board/trab/Makefile deleted file mode 100644 index 82da40c..0000000 --- a/board/trab/Makefile +++ /dev/null @@ -1,71 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := trab.o flash.o vfd.o cmd_trab.o memory.o tsc2000.o auto_update.o -SOBJS := lowlevel_init.o - -COBJS_FKT := trab_fkt.o rs485.o tsc2000.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(COBJS_FKT:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -OBJS_FKT := $(addprefix $(obj),$(COBJS_FKT)) - -LOAD_ADDR = 0xc100000 - -######################################################################### - -all: $(LIB) $(obj)trab_fkt.srec $(obj)trab_fkt.bin - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -$(obj)trab_fkt.srec: $(OBJS_FKT) $(LIB) - $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e trab_fkt $^ $(LIB) \ - -L$(obj)../../examples/standalone -lstubs \ - -L$(obj)../../lib -lgeneric \ - $(PLATFORM_LIBS) - $(OBJCOPY) -O srec $(<:.o=) $@ - -$(obj)trab_fkt.bin: $(obj)trab_fkt.srec - $(OBJCOPY) -I srec -O binary $< $@ - -clean: - rm -f $(SOBJS) $(OBJS) $(OBJS_FKT) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/trab/Pt1000_temp_data.h b/board/trab/Pt1000_temp_data.h deleted file mode 100644 index 17e9ed7..0000000 --- a/board/trab/Pt1000_temp_data.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Data file for tsc2000 driver. - * Copyright (C) 2002, 2003 DENX Software Engineering, Wolfgang Denk, wd@denx.de - */ - -#ifndef _PT1000_TEMP_DATA_H -#define _PT1000_TEMP_DATA_H - -long Pt1000_temp_table[][2] = { - /* For quick range checking the largest element - * is placed at index 0. - * U, nV T, C*100 - */ - { 44000000 , 12165 }, - { -10000000 , -2644 }, - { -9000000 , -2381 }, - { -8000000 , -2118 }, - { -7000000 , -1855 }, - { -6000000 , -1591 }, - { -5000000 , -1327 }, - { -4000000 , -1063 }, - { -3000000 , -798 }, - { -2000000 , -532 }, - { -1000000 , -266 }, - { 0 , 000 }, - { 1000000 , 267 }, - { 2000000 , 534 }, - { 3000000 , 802 }, - { 4000000 , 1070 }, - { 5000000 , 1338 }, - { 6000000 , 1607 }, - { 7000000 , 1876 }, - { 8000000 , 2146 }, - { 9000000 , 2416 }, - { 10000000 , 2687 }, - { 11000000 , 2958 }, - { 12000000 , 3230 }, - { 13000000 , 3502 }, - { 14000000 , 3774 }, - { 15000000 , 4047 }, - { 16000000 , 4321 }, - { 17000000 , 4595 }, - { 18000000 , 4869 }, - { 19000000 , 5144 }, - { 20000000 , 5419 }, - { 21000000 , 5694 }, - { 22000000 , 5971 }, - { 23000000 , 6247 }, - { 24000000 , 6524 }, - { 25000000 , 6802 }, - { 26000000 , 7080 }, - { 27000000 , 7358 }, - { 28000000 , 7637 }, - { 29000000 , 7916 }, - { 30000000 , 8196 }, - { 31000000 , 8476 }, - { 32000000 , 8757 }, - { 33000000 , 9039 }, - { 34000000 , 9320 }, - { 35000000 , 9602 }, - { 36000000 , 9885 }, - { 37000000 , 10168 }, - { 38000000 , 10452 }, - { 39000000 , 10736 }, - { 40000000 , 11021 }, - { 41000000 , 11306 }, - { 42000000 , 11592 }, - { 43000000 , 11879 }, - { 44000000 , 12165 }, -}; -#endif /* _PT1000_TEMP_DATA_H */ diff --git a/board/trab/README.kbd b/board/trab/README.kbd deleted file mode 100644 index 3db00bc..0000000 --- a/board/trab/README.kbd +++ /dev/null @@ -1,44 +0,0 @@ - -The TRAB keyboard implementation is similar to that for LWMON and -R360MPI boards. The only difference concerns key naming. There are 4 -keys on TRAB: 1, 2, 3, 4. - -1) The "kbd" command provides information about the current state of - the keys. For example, - - TRAB # kbd - Keys: 1 0 1 0 - - means that keys 1 and 3 are pressed. The keyboard status is also - stored in the "keybd" environment variable. In this example we get - - keybd=1010 - -2) The "preboot" variable is set according to current environment - settings and keys pressed. This is an example: - - TRAB # setenv magic_keys XY - TRAB # setenv key_magicX 12 - TRAB # setenv key_cmdX echo ## Keys 1 + 2 pressed ##\;echo - TRAB # setenv key_magicY 13 - TRAB # setenv key_cmdY echo ## Keys 1 + 3 pressed ##\;echo - - Here "magic_keys=XY" means that the "key_magicX" and "key_magicY" - variables will be checked for a match. Each variable "key_magic*" - defines a set of keys. In the our example, if keys 1 and 3 are - pressed during reset, then "key_magicY" matches, so the "preboot" - variable will be set to the contents of "key_cmdY": - - preboot=echo ## Keys 1 + 3 pressed ##;echo - -3) The TRAB board has optional modem support. When a certain key - combination is pressed on the keyboard at power-on, the firmware - performs the necessary initialization of the modem and allows for - dial-in. The key combination is specified in the - "include/configs/trab.h" file. For example: - - #define CONFIG_MODEM_KEY_MAGIC "23" - - means that modem will be initialized if and only if both keys 2, 3 - are pressed. Note that the format of this string is similar to the - format of "key_magic*" environment variables described above. diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c deleted file mode 100644 index bcb8505..0000000 --- a/board/trab/auto_update.c +++ /dev/null @@ -1,676 +0,0 @@ -/* - * (C) Copyright 2003 - * Gary Jennejohn, DENX Software Engineering, garyj@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <malloc.h> -#include <image.h> -#include <asm/byteorder.h> -#include <usb.h> - -#ifdef CONFIG_SYS_HUSH_PARSER -#include <hush.h> -#endif - -#ifdef CONFIG_AUTO_UPDATE - -#ifndef CONFIG_USB_OHCI_NEW -#error "must define CONFIG_USB_OHCI" -#endif - -#ifndef CONFIG_USB_STORAGE -#error "must define CONFIG_USB_STORAGE" -#endif - -#ifndef CONFIG_SYS_HUSH_PARSER -#error "must define CONFIG_SYS_HUSH_PARSER" -#endif - -#if !defined(CONFIG_CMD_FAT) -#error "must define CONFIG_CMD_FAT" -#endif - -/* - * Check whether a USB memory stick is plugged in. - * If one is found: - * 1) if prepare.img ist found load it into memory. If it is - * valid then run it. - * 2) if preinst.img is found load it into memory. If it is - * valid then run it. Update the EEPROM. - * 3) if firmw_01.img is found load it into memory. If it is valid, - * burn it into FLASH and update the EEPROM. - * 4) if kernl_01.img is found load it into memory. If it is valid, - * burn it into FLASH and update the EEPROM. - * 5) if app.img is found load it into memory. If it is valid, - * burn it into FLASH and update the EEPROM. - * 6) if disk.img is found load it into memory. If it is valid, - * burn it into FLASH and update the EEPROM. - * 7) if postinst.img is found load it into memory. If it is - * valid then run it. Update the EEPROM. - */ - -#undef AU_DEBUG - -#undef debug -#ifdef AU_DEBUG -#define debug(fmt,args...) printf (fmt ,##args) -#else -#define debug(fmt,args...) -#endif /* AU_DEBUG */ - -/* possible names of files on the USB stick. */ -#define AU_PREPARE "prepare.img" -#define AU_PREINST "preinst.img" -#define AU_FIRMWARE "firmw_01.img" -#define AU_KERNEL "kernl_01.img" -#define AU_APP "app.img" -#define AU_DISK "disk.img" -#define AU_POSTINST "postinst.img" - -struct flash_layout -{ - long start; - long end; -}; - -/* layout of the FLASH. ST = start address, ND = end address. */ -#ifndef CONFIG_FLASH_8MB /* 16 MB Flash, 32 MB RAM */ -#define AU_FL_FIRMWARE_ST 0x00000000 -#define AU_FL_FIRMWARE_ND 0x0009FFFF -#define AU_FL_VFD_ST 0x000A0000 -#define AU_FL_VFD_ND 0x000BFFFF -#define AU_FL_KERNEL_ST 0x000C0000 -#define AU_FL_KERNEL_ND 0x001BFFFF -#define AU_FL_APP_ST 0x001C0000 -#define AU_FL_APP_ND 0x005BFFFF -#define AU_FL_DISK_ST 0x005C0000 -#define AU_FL_DISK_ND 0x00FFFFFF -#else /* 8 MB Flash, 32 MB RAM */ -#define AU_FL_FIRMWARE_ST 0x00000000 -#define AU_FL_FIRMWARE_ND 0x0005FFFF -#define AU_FL_KERNEL_ST 0x00060000 -#define AU_FL_KERNEL_ND 0x0013FFFF -#define AU_FL_APP_ST 0x00140000 -#define AU_FL_APP_ND 0x0067FFFF -#define AU_FL_DISK_ST 0x00680000 -#define AU_FL_DISK_ND 0x007DFFFF -#define AU_FL_VFD_ST 0x007E0000 -#define AU_FL_VFD_ND 0x007FFFFF -#endif /* CONFIG_FLASH_8MB */ - -/* a structure with the offsets to values in the EEPROM */ -struct eeprom_layout -{ - int time; - int size; - int dcrc; -}; - -/* layout of the EEPROM - offset from the start. All entries are 32 bit. */ -#define AU_EEPROM_TIME_PREINST 64 -#define AU_EEPROM_SIZE_PREINST 68 -#define AU_EEPROM_DCRC_PREINST 72 -#define AU_EEPROM_TIME_FIRMWARE 76 -#define AU_EEPROM_SIZE_FIRMWARE 80 -#define AU_EEPROM_DCRC_FIRMWARE 84 -#define AU_EEPROM_TIME_KERNEL 88 -#define AU_EEPROM_SIZE_KERNEL 92 -#define AU_EEPROM_DCRC_KERNEL 96 -#define AU_EEPROM_TIME_APP 100 -#define AU_EEPROM_SIZE_APP 104 -#define AU_EEPROM_DCRC_APP 108 -#define AU_EEPROM_TIME_DISK 112 -#define AU_EEPROM_SIZE_DISK 116 -#define AU_EEPROM_DCRC_DISK 120 -#define AU_EEPROM_TIME_POSTINST 124 -#define AU_EEPROM_SIZE_POSTINST 128 -#define AU_EEPROM_DCRC_POSTINST 132 - -static int au_usb_stor_curr_dev; /* current device */ - -/* index of each file in the following arrays */ -#define IDX_PREPARE 0 -#define IDX_PREINST 1 -#define IDX_FIRMWARE 2 -#define IDX_KERNEL 3 -#define IDX_APP 4 -#define IDX_DISK 5 -#define IDX_POSTINST 6 -/* max. number of files which could interest us */ -#define AU_MAXFILES 7 -/* pointers to file names */ -char *aufile[AU_MAXFILES]; -/* sizes of flash areas for each file */ -long ausize[AU_MAXFILES]; -/* offsets into the EEEPROM */ -struct eeprom_layout auee_off[AU_MAXFILES] = { \ - {0}, \ - {AU_EEPROM_TIME_PREINST, AU_EEPROM_SIZE_PREINST, AU_EEPROM_DCRC_PREINST,}, \ - {AU_EEPROM_TIME_FIRMWARE, AU_EEPROM_SIZE_FIRMWARE, AU_EEPROM_DCRC_FIRMWARE,}, \ - {AU_EEPROM_TIME_KERNEL, AU_EEPROM_SIZE_KERNEL, AU_EEPROM_DCRC_KERNEL,}, \ - {AU_EEPROM_TIME_APP, AU_EEPROM_SIZE_APP, AU_EEPROM_DCRC_APP,}, \ - {AU_EEPROM_TIME_DISK, AU_EEPROM_SIZE_DISK, AU_EEPROM_DCRC_DISK,}, \ - {AU_EEPROM_TIME_POSTINST, AU_EEPROM_SIZE_POSTINST, AU_EEPROM_DCRC_POSTINST,} \ - }; -/* array of flash areas start and end addresses */ -struct flash_layout aufl_layout[AU_MAXFILES - 3] = { \ - {AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND,}, \ - {AU_FL_KERNEL_ST, AU_FL_KERNEL_ND,}, \ - {AU_FL_APP_ST, AU_FL_APP_ND,}, \ - {AU_FL_DISK_ST, AU_FL_DISK_ND,}, \ -}; -/* convert the index into aufile[] to an index into aufl_layout[] */ -#define FIDX_TO_LIDX(idx) ((idx) - 2) - -/* where to load files into memory */ -#define LOAD_ADDR ((unsigned char *)0x0C100000) -/* the app is the largest image */ -#define MAX_LOADSZ ausize[IDX_APP] - -/* externals */ -extern int fat_register_device(block_dev_desc_t *, int); -extern int file_fat_detectfs(void); -extern long file_fat_read(const char *, void *, unsigned long); -extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int); -extern int i2c_write (uchar, uint, int , uchar* , int); -#ifdef CONFIG_VFD -extern int trab_vfd (ulong); -extern int transfer_pic(unsigned char, unsigned char *, int, int); -#endif -extern int flash_sect_erase(ulong, ulong); -extern int flash_sect_protect (int, ulong, ulong); -extern int flash_write (char *, ulong, ulong); -/* change char* to void* to shutup the compiler */ -extern int i2c_write_multiple (uchar, uint, int, void *, int); -extern int i2c_read_multiple (uchar, uint, int, void *, int); -extern int u_boot_hush_start(void); - -int -au_check_cksum_valid(int idx, long nbytes) -{ - image_header_t *hdr; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - if (nbytes != image_get_image_size (hdr)) { - printf ("Image %s bad total SIZE\n", aufile[idx]); - return -1; - } - /* check the data CRC */ - if (!image_check_dcrc (hdr)) { - printf ("Image %s bad data checksum\n", aufile[idx]); - return -1; - } - return 0; -} - -int -au_check_header_valid(int idx, long nbytes) -{ - image_header_t *hdr; - unsigned long checksum; - unsigned char buf[4]; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - /* check the easy ones first */ -#undef CHECK_VALID_DEBUG -#ifdef CHECK_VALID_DEBUG - printf("magic %#x %#x ", image_get_magic (hdr), IH_MAGIC); - printf("arch %#x %#x ", image_get_arch (hdr), IH_ARCH_ARM); - printf("size %#x %#lx ", image_get_data_size (hdr), nbytes); - printf("type %#x %#x ", image_get_type (hdr), IH_TYPE_KERNEL); -#endif - if (nbytes < image_get_header_size ()) { - printf ("Image %s bad header SIZE\n", aufile[idx]); - return -1; - } - if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_ARM)) { - printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]); - return -1; - } - /* check the hdr CRC */ - if (!image_check_hcrc (hdr)) { - printf ("Image %s bad header checksum\n", aufile[idx]); - return -1; - } - /* check the type - could do this all in one gigantic if() */ - if ((idx == IDX_FIRMWARE) && - !image_check_type (hdr, IH_TYPE_FIRMWARE)) { - printf ("Image %s wrong type\n", aufile[idx]); - return -1; - } - if ((idx == IDX_KERNEL) && !image_check_type (hdr, IH_TYPE_KERNEL)) { - printf ("Image %s wrong type\n", aufile[idx]); - return -1; - } - if ((idx == IDX_DISK) && !image_check_type (hdr, IH_TYPE_FILESYSTEM)) { - printf ("Image %s wrong type\n", aufile[idx]); - return -1; - } - if ((idx == IDX_APP) && !image_check_type (hdr, IH_TYPE_RAMDISK) - && !image_check_type (hdr, IH_TYPE_FILESYSTEM)) { - printf ("Image %s wrong type\n", aufile[idx]); - return -1; - } - if ((idx == IDX_PREPARE || idx == IDX_PREINST || idx == IDX_POSTINST) - && !image_check_type (hdr, IH_TYPE_SCRIPT)) { - printf ("Image %s wrong type\n", aufile[idx]); - return -1; - } - /* special case for prepare.img */ - if (idx == IDX_PREPARE) - return 0; - /* recycle checksum */ - checksum = image_get_data_size (hdr); - /* for kernel and app the image header must also fit into flash */ - if ((idx != IDX_DISK) && (idx != IDX_FIRMWARE)) - checksum += image_get_header_size (); - /* check the size does not exceed space in flash. HUSH scripts */ - /* all have ausize[] set to 0 */ - if ((ausize[idx] != 0) && (ausize[idx] < checksum)) { - printf ("Image %s is bigger than FLASH\n", aufile[idx]); - return -1; - } - /* check the time stamp from the EEPROM */ - /* read it in */ - i2c_read_multiple(0x54, auee_off[idx].time, 1, buf, sizeof(buf)); -#ifdef CHECK_VALID_DEBUG - printf ("buf[0] %#x buf[1] %#x buf[2] %#x buf[3] %#x " - "as int %#x time %#x\n", - buf[0], buf[1], buf[2], buf[3], - *((unsigned int *)buf), image_get_time (hdr)); -#endif - /* check it */ - if (*((unsigned int *)buf) >= image_get_time (hdr)) { - printf ("Image %s is too old\n", aufile[idx]); - return -1; - } - - return 0; -} - -/* power control defines */ -#define CPLD_VFD_BK ((volatile char *)0x04038002) -#define POWER_OFF (1 << 1) - -int -au_do_update(int idx, long sz) -{ - image_header_t *hdr; - char *addr; - long start, end; - int off, rc; - uint nbytes; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - /* disable the power switch */ - *CPLD_VFD_BK |= POWER_OFF; - - /* execute a script */ - if (image_check_type (hdr, IH_TYPE_SCRIPT)) { - addr = (char *)((char *)hdr + image_get_header_size ()); - /* stick a NULL at the end of the script, otherwise */ - /* parse_string_outer() runs off the end. */ - addr[image_get_data_size (hdr)] = 0; - addr += 8; - parse_string_outer(addr, FLAG_PARSE_SEMICOLON); - return 0; - } - - start = aufl_layout[FIDX_TO_LIDX(idx)].start; - end = aufl_layout[FIDX_TO_LIDX(idx)].end; - - /* unprotect the address range */ - /* this assumes that ONLY the firmware is protected! */ - if (idx == IDX_FIRMWARE) { -#undef AU_UPDATE_TEST -#ifdef AU_UPDATE_TEST - /* erase it where Linux goes */ - start = aufl_layout[1].start; - end = aufl_layout[1].end; -#endif - flash_sect_protect(0, start, end); - } - - /* - * erase the address range. - */ - debug ("flash_sect_erase(%lx, %lx);\n", start, end); - flash_sect_erase(start, end); - wait_ms(100); - /* strip the header - except for the kernel and ramdisk */ - if (image_check_type (hdr, IH_TYPE_KERNEL) || - image_check_type (hdr, IH_TYPE_RAMDISK)) { - addr = (char *)hdr; - off = image_get_header_size (); - nbytes = image_get_image_size (hdr); - } else { - addr = (char *)((char *)hdr + image_get_header_size ()); -#ifdef AU_UPDATE_TEST - /* copy it to where Linux goes */ - if (idx == IDX_FIRMWARE) - start = aufl_layout[1].start; -#endif - off = 0; - nbytes = image_get_data_size (hdr); - } - - /* copy the data from RAM to FLASH */ - debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes); - rc = flash_write(addr, start, nbytes); - if (rc != 0) { - printf("Flashing failed due to error %d\n", rc); - return -1; - } - - /* check the dcrc of the copy */ - if (crc32 (0, (uchar *)(start + off), image_get_data_size (hdr)) != - image_get_dcrc (hdr)) { - printf ("Image %s Bad Data Checksum After COPY\n", aufile[idx]); - return -1; - } - - /* protect the address range */ - /* this assumes that ONLY the firmware is protected! */ - if (idx == IDX_FIRMWARE) - flash_sect_protect(1, start, end); - return 0; -} - -int -au_update_eeprom(int idx) -{ - image_header_t *hdr; - int off; - uint32_t val; - - /* special case for prepare.img */ - if (idx == IDX_PREPARE) { - /* enable the power switch */ - *CPLD_VFD_BK &= ~POWER_OFF; - return 0; - } - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - /* write the time field into EEPROM */ - off = auee_off[idx].time; - val = image_get_time (hdr); - i2c_write_multiple(0x54, off, 1, &val, sizeof(val)); - /* write the size field into EEPROM */ - off = auee_off[idx].size; - val = image_get_data_size (hdr); - i2c_write_multiple(0x54, off, 1, &val, sizeof(val)); - /* write the dcrc field into EEPROM */ - off = auee_off[idx].dcrc; - val = image_get_dcrc (hdr); - i2c_write_multiple(0x54, off, 1, &val, sizeof(val)); - /* enable the power switch */ - *CPLD_VFD_BK &= ~POWER_OFF; - return 0; -} - -/* - * this is called from board_init() after the hardware has been set up - * and is usable. That seems like a good time to do this. - * Right now the return value is ignored. - */ -int -do_auto_update(void) -{ - block_dev_desc_t *stor_dev; - long sz; - int i, res = 0, bitmap_first, cnt, old_ctrlc, got_ctrlc; - char *env; - long start, end; - -#undef ERASE_EEPROM -#ifdef ERASE_EEPROM - int arr[18]; - memset(arr, 0, sizeof(arr)); - i2c_write_multiple(0x54, 64, 1, arr, sizeof(arr)); -#endif - au_usb_stor_curr_dev = -1; - /* start USB */ - if (usb_stop() < 0) { - debug ("usb_stop failed\n"); - return -1; - } - if (usb_init() < 0) { - debug ("usb_init failed\n"); - return -1; - } - /* - * check whether a storage device is attached (assume that it's - * a USB memory stick, since nothing else should be attached). - */ - au_usb_stor_curr_dev = usb_stor_scan(0); - if (au_usb_stor_curr_dev == -1) { - debug ("No device found. Not initialized?\n"); - res = -1; - goto xit; - } - /* check whether it has a partition table */ - stor_dev = get_dev("usb", 0); - if (stor_dev == NULL) { - debug ("uknown device type\n"); - res = -1; - goto xit; - } - if (fat_register_device(stor_dev, 1) != 0) { - debug ("Unable to use USB %d:%d for fatls\n", - au_usb_stor_curr_dev, 1); - res = -1; - goto xit; - } - if (file_fat_detectfs() != 0) { - debug ("file_fat_detectfs failed\n"); - } - - /* initialize the array of file names */ - memset(aufile, 0, sizeof(aufile)); - aufile[IDX_PREPARE] = AU_PREPARE; - aufile[IDX_PREINST] = AU_PREINST; - aufile[IDX_FIRMWARE] = AU_FIRMWARE; - aufile[IDX_KERNEL] = AU_KERNEL; - aufile[IDX_APP] = AU_APP; - aufile[IDX_DISK] = AU_DISK; - aufile[IDX_POSTINST] = AU_POSTINST; - /* initialize the array of flash sizes */ - memset(ausize, 0, sizeof(ausize)); - ausize[IDX_FIRMWARE] = (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST; - ausize[IDX_KERNEL] = (AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST; - ausize[IDX_APP] = (AU_FL_APP_ND + 1) - AU_FL_APP_ST; - ausize[IDX_DISK] = (AU_FL_DISK_ND + 1) - AU_FL_DISK_ST; - /* - * now check whether start and end are defined using environment - * variables. - */ - start = -1; - end = 0; - env = getenv("firmware_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("firmware_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_FIRMWARE] = (end + 1) - start; - aufl_layout[0].start = start; - aufl_layout[0].end = end; - } - start = -1; - end = 0; - env = getenv("kernel_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("kernel_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_KERNEL] = (end + 1) - start; - aufl_layout[1].start = start; - aufl_layout[1].end = end; - } - start = -1; - end = 0; - env = getenv("app_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("app_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_APP] = (end + 1) - start; - aufl_layout[2].start = start; - aufl_layout[2].end = end; - } - start = -1; - end = 0; - env = getenv("disk_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("disk_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_DISK] = (end + 1) - start; - aufl_layout[3].start = start; - aufl_layout[3].end = end; - } - /* make certain that HUSH is runnable */ - u_boot_hush_start(); - /* make sure that we see CTRL-C and save the old state */ - old_ctrlc = disable_ctrlc(0); - - bitmap_first = 0; - /* just loop thru all the possible files */ - for (i = 0; i < AU_MAXFILES; i++) { - /* just read the header */ - sz = file_fat_read(aufile[i], LOAD_ADDR, image_get_header_size ()); - debug ("read %s sz %ld hdr %d\n", - aufile[i], sz, image_get_header_size ()); - if (sz <= 0 || sz < image_get_header_size ()) { - debug ("%s not found\n", aufile[i]); - continue; - } - if (au_check_header_valid(i, sz) < 0) { - debug ("%s header not valid\n", aufile[i]); - continue; - } - sz = file_fat_read(aufile[i], LOAD_ADDR, MAX_LOADSZ); - debug ("read %s sz %ld hdr %d\n", - aufile[i], sz, image_get_header_size ()); - if (sz <= 0 || sz <= image_get_header_size ()) { - debug ("%s not found\n", aufile[i]); - continue; - } - if (au_check_cksum_valid(i, sz) < 0) { - debug ("%s checksum not valid\n", aufile[i]); - continue; - } -#ifdef CONFIG_VFD - /* now that we have a valid file we can display the */ - /* bitmap. */ - if (bitmap_first == 0) { - env = getenv("bitmap2"); - if (env == NULL) { - trab_vfd(0); - } else { - /* not so simple - bitmap2 is supposed to */ - /* contain the address of the bitmap */ - env = (char *)simple_strtoul(env, NULL, 16); -/* NOTE: these are taken from vfd_logo.h. If that file changes then */ -/* these defines MUST also be updated! These may be wrong for bitmap2. */ -#define VFD_LOGO_WIDTH 112 -#define VFD_LOGO_HEIGHT 72 - /* must call transfer_pic directly */ - transfer_pic(3, (unsigned char *)env, - VFD_LOGO_HEIGHT, VFD_LOGO_WIDTH); - } - bitmap_first = 1; - } -#endif - /* this is really not a good idea, but it's what the */ - /* customer wants. */ - cnt = 0; - got_ctrlc = 0; - do { - res = au_do_update(i, sz); - /* let the user break out of the loop */ - if (ctrlc() || had_ctrlc()) { - clear_ctrlc(); - if (res < 0) - got_ctrlc = 1; - break; - } - cnt++; -#ifdef AU_TEST_ONLY - } while (res < 0 && cnt < 3); - if (cnt < 3) -#else - } while (res < 0); -#endif - /* - * it doesn't make sense to update the EEPROM if the - * update was interrupted by the user due to errors. - */ - if (got_ctrlc == 0) - au_update_eeprom(i); - else - /* enable the power switch */ - *CPLD_VFD_BK &= ~POWER_OFF; - } - /* restore the old state */ - disable_ctrlc(old_ctrlc); -xit: - usb_stop(); - return res; -} -#endif /* CONFIG_AUTO_UPDATE */ diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c deleted file mode 100644 index dec3c61..0000000 --- a/board/trab/cmd_trab.c +++ /dev/null @@ -1,879 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#undef DEBUG - -#include <common.h> -#include <command.h> -#include <asm/arch/s3c24x0_cpu.h> -#include <rtc.h> - -/* - * TRAB board specific commands. Especially commands for burn-in and function - * test. - */ -#if defined(CONFIG_CMD_BSP) - -/* limits for valid range of VCC5V in mV */ -#define VCC5V_MIN 4500 -#define VCC5V_MAX 5500 - -/* - * Test strings for EEPROM test. Length of string 2 must not exceed length of - * string 1. Otherwise a buffer overrun could occur! - */ -#define EEPROM_TEST_STRING_1 "0987654321 :tset a si siht" -#define EEPROM_TEST_STRING_2 "this is a test: 1234567890" - -/* - * min/max limits for valid contact temperature during burn in test (in - * degree Centigrade * 100) - */ -#define MIN_CONTACT_TEMP -1000 -#define MAX_CONTACT_TEMP +9000 - -/* blinking frequency of status LED */ -#define LED_BLINK_FREQ 5 - -/* delay time between burn in cycles in seconds */ -#ifndef BURN_IN_CYCLE_DELAY /* if not defined in include/configs/trab.h */ -#define BURN_IN_CYCLE_DELAY 5 -#endif - -/* physical SRAM parameters */ -#define SRAM_ADDR 0x02000000 /* GCS1 */ -#define SRAM_SIZE 0x40000 /* 256 kByte */ - -/* CPLD-Register for controlling TRAB hardware functions */ -#define CPLD_BUTTONS ((volatile unsigned long *)0x04020000) -#define CPLD_FILL_LEVEL ((volatile unsigned long *)0x04008000) -#define CPLD_ROTARY_SWITCH ((volatile unsigned long *)0x04018000) -#define CPLD_RS485_RE ((volatile unsigned long *)0x04028000) - -/* I2C EEPROM device address */ -#define I2C_EEPROM_DEV_ADDR 0x54 - -/* EEPROM address map */ -#define EE_ADDR_TEST 192 -#define EE_ADDR_MAX_CYCLES 256 -#define EE_ADDR_STATUS 258 -#define EE_ADDR_PASS_CYCLES 259 -#define EE_ADDR_FIRST_ERROR_CYCLE 261 -#define EE_ADDR_FIRST_ERROR_NUM 263 -#define EE_ADDR_FIRST_ERROR_NAME 264 -#define EE_ADDR_ACT_CYCLE 280 - -/* Bit definitions for ADCCON */ -#define ADC_ENABLE_START 0x1 -#define ADC_READ_START 0x2 -#define ADC_STDBM 0x4 -#define ADC_INP_AIN0 (0x0 << 3) -#define ADC_INP_AIN1 (0x1 << 3) -#define ADC_INP_AIN2 (0x2 << 3) -#define ADC_INP_AIN3 (0x3 << 3) -#define ADC_INP_AIN4 (0x4 << 3) -#define ADC_INP_AIN5 (0x5 << 3) -#define ADC_INP_AIN6 (0x6 << 3) -#define ADC_INP_AIN7 (0x7 << 3) -#define ADC_PRSCEN 0x4000 -#define ADC_ECFLG 0x800 - -/* misc */ - -/* externals */ -extern int memory_post_tests (unsigned long start, unsigned long size); -extern int i2c_write (uchar, uint, int , uchar* , int); -extern int i2c_read (uchar, uint, int , uchar* , int); -extern void tsc2000_reg_init (void); -extern s32 tsc2000_contact_temp (void); -extern void tsc2000_spi_init(void); - -/* function declarations */ -int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); -int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); -int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); -int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); -int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); -int i2c_write_multiple (uchar chip, uint addr, int alen, - uchar *buffer, int len); -int i2c_read_multiple (uchar chip, uint addr, int alen, - uchar *buffer, int len); -int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); - -/* helper functions */ -static void adc_init (void); -static int adc_read (unsigned int channel); -static int read_dip (void); -static int read_vcc5v (void); -static int test_dip (void); -static int test_vcc5v (void); -static int test_rotary_switch (void); -static int test_sram (void); -static int test_eeprom (void); -static int test_contact_temp (void); -static void led_set (unsigned int); -static void led_blink (void); -static void led_init (void); -static void sdelay (unsigned long seconds); /* delay in seconds */ -static int dummy (void); -static int read_max_cycles(void); -static void test_function_table_init (void); -static void global_vars_init (void); -static int global_vars_write_to_eeprom (void); - -/* globals */ -u16 max_cycles; -u8 status; -u16 pass_cycles; -u16 first_error_cycle; -u8 first_error_num; -char first_error_name[16]; -u16 act_cycle; - -typedef struct test_function_s { - char *name; - int (*pf)(void); -} test_function_t; - -/* max number of Burn In Functions */ -#define BIF_MAX 6 - -/* table with burn in functions */ -test_function_t test_function[BIF_MAX]; - - -int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int i; - int cycle_status; - - if (argc > 1) - return cmd_usage(cmdtp); - - led_init (); - global_vars_init (); - test_function_table_init (); - tsc2000_spi_init (); - - if (global_vars_write_to_eeprom () != 0) { - printf ("%s: error writing global_vars to eeprom\n", - __FUNCTION__); - return (1); - } - - if (read_max_cycles () != 0) { - printf ("%s: error reading max_cycles from eeprom\n", - __FUNCTION__); - return (1); - } - - if (max_cycles == 0) { - printf ("%s: error, burn in max_cycles = 0\n", __FUNCTION__); - return (1); - } - - status = 0; - for (act_cycle = 1; act_cycle <= max_cycles; act_cycle++) { - - cycle_status = 0; - - /* - * avoid timestamp overflow problem after about 68 minutes of - * udelay() time. - */ - reset_timer_masked (); - for (i = 0; i < BIF_MAX; i++) { - - /* call test function */ - if ((*test_function[i].pf)() != 0) { - printf ("error in %s test\n", - test_function[i].name); - - /* is it the first error? */ - if (status == 0) { - status = 1; - first_error_cycle = act_cycle; - - /* do not use error_num 0 */ - first_error_num = i+1; - strncpy (first_error_name, - test_function[i].name, - sizeof (first_error_name)); - led_set (0); - } - cycle_status = 1; - } - } - /* were all tests of actual cycle OK? */ - if (cycle_status == 0) - pass_cycles++; - - /* set status LED if no error is occoured since yet */ - if (status == 0) - led_set (1); - - printf ("%s: cycle %d finished\n", __FUNCTION__, act_cycle); - - /* pause between cycles */ - sdelay (BURN_IN_CYCLE_DELAY); - } - - if (global_vars_write_to_eeprom () != 0) { - led_set (0); - printf ("%s: error writing global_vars to eeprom\n", - __FUNCTION__); - status = 1; - } - - if (status == 0) { - led_blink (); /* endless loop!! */ - return (0); - } else { - led_set (0); - return (1); - } -} - -U_BOOT_CMD( - burn_in, 1, 1, do_burn_in, - "start burn-in test application on TRAB", - "\n" - " - start burn-in test application\n" - " The burn-in test could took a while to finish!\n" - " The content of the onboard EEPROM is modified!" -); - - -int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int i, dip; - - if (argc > 1) - return cmd_usage(cmdtp); - - if ((dip = read_dip ()) == -1) - return 1; - - for (i = 0; i < 4; i++) { - if ((dip & (1 << i)) == 0) - printf("0"); - else - printf("1"); - } - printf("\n"); - - return 0; -} - -U_BOOT_CMD( - dip, 1, 1, do_dip, - "read dip switch on TRAB", - "\n" - " - read state of dip switch (S1) on TRAB board\n" - " read sequence: 1-2-3-4; ON=1; OFF=0; e.g.: \"0100\"" -); - - -int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int vcc5v; - - if (argc > 1) - return cmd_usage(cmdtp); - - if ((vcc5v = read_vcc5v ()) == -1) - return (1); - - printf ("%d", (vcc5v / 1000)); - printf (".%d", (vcc5v % 1000) / 100); - printf ("%d V\n", (vcc5v % 100) / 10) ; - - return 0; -} - -U_BOOT_CMD( - vcc5v, 1, 1, do_vcc5v, - "read VCC5V on TRAB", - "\n" - " - read actual value of voltage VCC5V" -); - - -int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int contact_temp; - - if (argc > 1) - return cmd_usage(cmdtp); - - tsc2000_spi_init (); - - contact_temp = tsc2000_contact_temp(); - printf ("%d degree C * 100\n", contact_temp) ; - - return 0; -} - -U_BOOT_CMD( - c_temp, 1, 1, do_contact_temp, - "read contact temperature on TRAB", - "" - " - reads the onboard temperature (=contact temperature)\n" -); - - -int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc > 1) - return cmd_usage(cmdtp); - - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1, - (unsigned char*) &status, 1)) - return (1); - - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1, - (unsigned char*) &pass_cycles, 2)) - return (1); - - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE, - 1, (unsigned char*) &first_error_cycle, 2)) - return (1); - - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM, - 1, (unsigned char*) &first_error_num, 1)) - return (1); - - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME, - 1, (unsigned char*)first_error_name, - sizeof (first_error_name))) - return (1); - - if (read_max_cycles () != 0) - return (1); - - printf ("max_cycles = %d\n", max_cycles); - printf ("status = %d\n", status); - printf ("pass_cycles = %d\n", pass_cycles); - printf ("first_error_cycle = %d\n", first_error_cycle); - printf ("first_error_num = %d\n", first_error_num); - printf ("first_error_name = %.*s\n",(int) sizeof(first_error_name), - first_error_name); - - return 0; -} - -U_BOOT_CMD( - bis, 1, 1, do_burn_in_status, - "print burn in status on TRAB", - "\n" - " - prints the status variables of the last burn in test\n" - " stored in the onboard EEPROM on TRAB board" -); - -static int read_dip (void) -{ - unsigned int result = 0; - int adc_val; - int i; - - /*********************************************************** - DIP switch connection (according to wa4-cpu.sp.301.pdf, page 3): - SW1 - AIN4 - SW2 - AIN5 - SW3 - AIN6 - SW4 - AIN7 - - "On" DIP switch position short-circuits the voltage from - the input channel (i.e. '0' conversion result means "on"). - *************************************************************/ - - for (i = 7; i > 3; i--) { - - if ((adc_val = adc_read (i)) == -1) { - printf ("%s: Channel %d could not be read\n", - __FUNCTION__, i); - return (-1); - } - - /* - * Input voltage (switch open) is 1.8 V. - * (Vin_High/VRef)*adc_res = (1,8V/2,5V)*1023) = 736 - * Set trigger at halve that value. - */ - if (adc_val < 368) - result |= (1 << (i-4)); - } - return (result); -} - - -static int read_vcc5v (void) -{ - s32 result; - - /* VCC5V is connected to channel 2 */ - - if ((result = adc_read (2)) == -1) { - printf ("%s: VCC5V could not be read\n", __FUNCTION__); - return (-1); - } - /* - * Calculate voltage value. Split in two parts because there is no - * floating point support. VCC5V is connected over an resistor divider: - * VCC5V=ADCval*2,5V/1023*(10K+30K)/10K. - */ - result = result * 10 * 1000 / 1023; /* result in mV */ - - return (result); -} - - -static int test_dip (void) -{ - static int first_run = 1; - static int first_dip; - - if (first_run) { - if ((first_dip = read_dip ()) == -1) { - return (1); - } - first_run = 0; - debug ("%s: first_dip=%d\n", __FUNCTION__, first_dip); - } - if (first_dip != read_dip ()) { - return (1); - } else { - return (0); - } -} - - -static int test_vcc5v (void) -{ - int vcc5v; - - if ((vcc5v = read_vcc5v ()) == -1) { - return (1); - } - - if ((vcc5v > VCC5V_MAX) || (vcc5v < VCC5V_MIN)) { - printf ("%s: vcc5v[V/100]=%d\n", __FUNCTION__, vcc5v); - return (1); - } else { - return (0); - } -} - - -static int test_rotary_switch (void) -{ - static int first_run = 1; - static int first_rs; - - if (first_run) { - /* - * clear bits in CPLD, because they have random values after - * power-up or reset. - */ - *CPLD_ROTARY_SWITCH |= (1 << 16) | (1 << 17); - - first_rs = ((*CPLD_ROTARY_SWITCH >> 16) & 0x7); - first_run = 0; - debug ("%s: first_rs=%d\n", __FUNCTION__, first_rs); - } - - if (first_rs != ((*CPLD_ROTARY_SWITCH >> 16) & 0x7)) { - return (1); - } else { - return (0); - } -} - - -static int test_sram (void) -{ - return (memory_post_tests (SRAM_ADDR, SRAM_SIZE)); -} - - -static int test_eeprom (void) -{ - unsigned char temp[sizeof (EEPROM_TEST_STRING_1)]; - int result = 0; - - /* write test string 1, read back and verify */ - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1, - (unsigned char*)EEPROM_TEST_STRING_1, - sizeof (EEPROM_TEST_STRING_1))) { - return (1); - } - - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1, - temp, sizeof (EEPROM_TEST_STRING_1))) { - return (1); - } - - if (strcmp ((char *)temp, EEPROM_TEST_STRING_1) != 0) { - result = 1; - printf ("%s: error; read_str = \"%s\"\n", __FUNCTION__, temp); - } - - /* write test string 2, read back and verify */ - if (result == 0) { - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1, - (unsigned char*)EEPROM_TEST_STRING_2, - sizeof (EEPROM_TEST_STRING_2))) { - return (1); - } - - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1, - temp, sizeof (EEPROM_TEST_STRING_2))) { - return (1); - } - - if (strcmp ((char *)temp, EEPROM_TEST_STRING_2) != 0) { - result = 1; - printf ("%s: error; read str = \"%s\"\n", - __FUNCTION__, temp); - } - } - return (result); -} - - -static int test_contact_temp (void) -{ - int contact_temp; - - contact_temp = tsc2000_contact_temp (); - - if ((contact_temp < MIN_CONTACT_TEMP) - || (contact_temp > MAX_CONTACT_TEMP)) - return (1); - else - return (0); -} - - -int i2c_write_multiple (uchar chip, uint addr, int alen, - uchar *buffer, int len) -{ - int i; - - if (alen != 1) { - printf ("%s: addr len other than 1 not supported\n", - __FUNCTION__); - return (1); - } - - for (i = 0; i < len; i++) { - if (i2c_write (chip, addr+i, alen, buffer+i, 1)) { - printf ("%s: could not write to i2c device %d" - ", addr %d\n", __FUNCTION__, chip, addr); - return (1); - } -#if 0 - printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i=" - "%#x+%d=%p=\"%.1s\"\n", chip, addr, i, addr+i, - alen, buffer, i, buffer+i, buffer+i); -#endif - - udelay (30000); - } - return (0); -} - - -int i2c_read_multiple ( uchar chip, uint addr, int alen, - uchar *buffer, int len) -{ - int i; - - if (alen != 1) { - printf ("%s: addr len other than 1 not supported\n", - __FUNCTION__); - return (1); - } - - for (i = 0; i < len; i++) { - if (i2c_read (chip, addr+i, alen, buffer+i, 1)) { - printf ("%s: could not read from i2c device %#x" - ", addr %d\n", __FUNCTION__, chip, addr); - return (1); - } - } - return (0); -} - - -static int adc_read (unsigned int channel) -{ - int j = 1000; /* timeout value for wait loop in us */ - int result; - struct s3c2400_adc *padc; - - padc = s3c2400_get_base_adc(); - channel &= 0x7; - - adc_init (); - - padc->adccon &= ~ADC_STDBM; /* select normal mode */ - padc->adccon &= ~(0x7 << 3); /* clear the channel bits */ - padc->adccon |= ((channel << 3) | ADC_ENABLE_START); - - while (j--) { - if ((padc->adccon & ADC_ENABLE_START) == 0) - break; - udelay (1); - } - - if (j == 0) { - printf("%s: ADC timeout\n", __FUNCTION__); - padc->adccon |= ADC_STDBM; /* select standby mode */ - return -1; - } - - result = padc->adcdat & 0x3FF; - - padc->adccon |= ADC_STDBM; /* select standby mode */ - - debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__, - (padc->adccon >> 3) & 0x7, result); - - /* - * Wait for ADC to be ready for next conversion. This delay value was - * estimated, because the datasheet does not specify a value. - */ - udelay (1000); - - return (result); -} - - -static void adc_init (void) -{ - struct s3c2400_adc *padc; - - padc = s3c2400_get_base_adc(); - - padc->adccon &= ~(0xff << 6); /* clear prescaler bits */ - padc->adccon |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */ - - /* - * Wait some time to avoid problem with very first call of - * adc_read(). Without this delay, sometimes the first read - * adc value is 0. Perhaps because the adjustment of prescaler - * takes some clock cycles? - */ - udelay (1000); - - return; -} - - -static void led_set (unsigned int state) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - led_init (); - - switch (state) { - case 0: /* turn LED off */ - gpio->padat |= (1 << 12); - break; - case 1: /* turn LED on */ - gpio->padat &= ~(1 << 12); - break; - default: - break; - } -} - -static void led_blink (void) -{ - led_init (); - - /* blink LED. This function does not return! */ - while (1) { - reset_timer_masked (); - led_set (1); - udelay (1000000 / LED_BLINK_FREQ / 2); - led_set (0); - udelay (1000000 / LED_BLINK_FREQ / 2); - } -} - - -static void led_init (void) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* configure GPA12 as output and set to High -> LED off */ - gpio->pacon &= ~(1 << 12); - gpio->padat |= (1 << 12); -} - - -static void sdelay (unsigned long seconds) -{ - unsigned long i; - - for (i = 0; i < seconds; i++) { - udelay (1000000); - } -} - - -static int global_vars_write_to_eeprom (void) -{ - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1, - (unsigned char*) &status, 1)) { - return (1); - } - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1, - (unsigned char*) &pass_cycles, 2)) { - return (1); - } - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE, - 1, (unsigned char*) &first_error_cycle, 2)) { - return (1); - } - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM, - 1, (unsigned char*) &first_error_num, 1)) { - return (1); - } - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME, - 1, (unsigned char*) first_error_name, - sizeof(first_error_name))) { - return (1); - } - return (0); -} - -static void global_vars_init (void) -{ - status = 1; /* error */ - pass_cycles = 0; - first_error_cycle = 0; - first_error_num = 0; - first_error_name[0] = '\0'; - act_cycle = 0; - max_cycles = 0; -} - - -static void test_function_table_init (void) -{ - int i; - - for (i = 0; i < BIF_MAX; i++) - test_function[i].pf = dummy; - - /* - * the length of "name" must not exceed 16, including the '\0' - * termination. See also the EEPROM address map. - */ - test_function[0].pf = test_dip; - test_function[0].name = "dip"; - - test_function[1].pf = test_vcc5v; - test_function[1].name = "vcc5v"; - - test_function[2].pf = test_rotary_switch; - test_function[2].name = "rotary_switch"; - - test_function[3].pf = test_sram; - test_function[3].name = "sram"; - - test_function[4].pf = test_eeprom; - test_function[4].name = "eeprom"; - - test_function[5].pf = test_contact_temp; - test_function[5].name = "contact_temp"; -} - - -static int read_max_cycles (void) -{ - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_MAX_CYCLES, 1, - (unsigned char *) &max_cycles, 2) != 0) { - return (1); - } - - return (0); -} - -static int dummy(void) -{ - return (0); -} - -int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int contact_temp; - int delay = 0; -#if defined(CONFIG_CMD_DATE) - struct rtc_time tm; -#endif - - if (argc > 2) - return cmd_usage(cmdtp); - - if (argc > 1) - delay = simple_strtoul(argv[1], NULL, 10); - - tsc2000_spi_init (); - while (1) { - -#if defined(CONFIG_CMD_DATE) - rtc_get (&tm); - printf ("%4d-%02d-%02d %2d:%02d:%02d - ", - tm.tm_year, tm.tm_mon, tm.tm_mday, - tm.tm_hour, tm.tm_min, tm.tm_sec); -#endif - - contact_temp = tsc2000_contact_temp(); - printf ("%d\n", contact_temp) ; - - if (delay != 0) - /* - * reset timer to avoid timestamp overflow problem - * after about 68 minutes of udelay() time. - */ - reset_timer_masked (); - sdelay (delay); - } - - return 0; -} - -U_BOOT_CMD( - tlog, 2, 1, do_temp_log, - "log contact temperature [1/100 C] to console (endlessly)", - "delay\n" - " - contact temperature [1/100 C] is printed endlessly to console\n" - " <delay> specifies the seconds to wait between two measurements\n" - " For each measurment a timestamp is printeted" -); - -#endif diff --git a/board/trab/config.mk b/board/trab/config.mk deleted file mode 100644 index 367f0b7..0000000 --- a/board/trab/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# TRAB board with S3C2400X (arm920t) cpu -# -# see http://www.samsung.com/ for more information on SAMSUNG -# - -# -# TRAB has 1 bank of 16 MB or 32 MB DRAM -# -# 0c00'0000 to 0e00'0000 -# -# Linux-Kernel is expected to be at 0c00'8000, entry 0c00'8000 -# -# we load ourself to 0CF0'0000 / 0DF0'0000 -# -# download areas is 0C80'0000 -# - -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -ifndef CONFIG_SYS_TEXT_BASE -CONFIG_SYS_TEXT_BASE = 0x0DF40000 -endif diff --git a/board/trab/flash.c b/board/trab/flash.c deleted file mode 100644 index 4e89c41..0000000 --- a/board/trab/flash.c +++ /dev/null @@ -1,569 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* #define DEBUG */ - -#include <common.h> -#include <environment.h> - -static ulong flash_get_size (vu_long *addr, flash_info_t *info); - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x00F000F0 -#define CMD_UNLOCK1 0x00AA00AA -#define CMD_UNLOCK2 0x00550055 -#define CMD_ERASE_SETUP 0x00800080 -#define CMD_ERASE_CONFIRM 0x00300030 -#define CMD_PROGRAM 0x00A000A0 -#define CMD_UNLOCK_BYPASS 0x00200020 -#define CMD_READ_MANF_ID 0x00900090 -#define CMD_UNLOCK_BYPASS_RES1 0x00900090 -#define CMD_UNLOCK_BYPASS_RES2 0x00000000 - -#define MEM_FLASH_ADDR (*(volatile u32 *)CONFIG_SYS_FLASH_BASE) -#define MEM_FLASH_ADDR1 (*(volatile u32 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 2))) -#define MEM_FLASH_ADDR2 (*(volatile u32 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 2))) - -#define BIT_ERASE_DONE 0x00800080 -#define BIT_RDY_MASK 0x00800080 -#define BIT_PROGRAM_ERROR 0x00200020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - ulong flashbase = 0; - flash_info_t *info = &flash_info[i]; - - /* Init: no FLASHes known */ - info->flash_id = FLASH_UNKNOWN; - - size += flash_get_size (CONFIG_SYS_FLASH_BASE, info); - - if (i == 0) - flashbase = CONFIG_SYS_FLASH_BASE; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < info->sector_count; j++) { - - info->protect[j] = 0; - info->start[j] = flashbase; - - switch (info->flash_id & FLASH_TYPEMASK) { - case (FLASH_AM320B & FLASH_TYPEMASK): - case (FLASH_MXLV320B & FLASH_TYPEMASK): - /* Boot sector type: 8 x 8 + N x 128 kB */ - flashbase += (j < 8) ? 0x4000 : 0x20000; - break; - case (FLASH_AM640U & FLASH_TYPEMASK): - /* Uniform sector type: 128 kB */ - flashbase += 0x20000; - break; - default: - printf ("## Bad flash chip type 0x%04lX\n", - info->flash_id & FLASH_TYPEMASK); - } - } - } - - /* - * Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); - -#ifdef CONFIG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (FLASH_MAN_AMD & FLASH_VENDMASK): - printf ("AMD "); break; - case (FLASH_MAN_FUJ & FLASH_VENDMASK): - printf ("FUJITSU "); break; - case (FLASH_MAN_MX & FLASH_VENDMASK): - printf ("MACRONIX "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (FLASH_AM320B & FLASH_TYPEMASK): - printf ("2x Am29LV320DB (32Mbit)\n"); - break; - case (FLASH_MXLV320B & FLASH_TYPEMASK): - printf ("2x MX29LV320DB (32Mbit)\n"); - break; - case (FLASH_AM640U & FLASH_TYPEMASK): - printf ("2x Am29LV640D (64Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -Done: ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result; - -#if 0 - int cflag; -#endif - int iflag, prot, sect; - int rc = ERR_OK; - int chip1, chip2; - - debug ("flash_erase: s_first %d s_last %d\n", s_first, s_last); - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case (FLASH_MAN_AMD & FLASH_VENDMASK): break; /* OK */ - case (FLASH_MAN_FUJ & FLASH_VENDMASK): break; /* OK */ - case (FLASH_MAN_MX & FLASH_VENDMASK): break; /* OK */ - default: - debug ("## flash_erase: unknown manufacturer\n"); - return (ERR_UNKNOWN_FLASH_VENDOR); - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ -#if 0 - cflag = icache_status (); - icache_disable (); -#endif - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - - debug ("Erasing sector %2d @ %08lX... ", - sect, info->start[sect]); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = chip2 = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; - } - - if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR) - chip1 = ERR; - - if (!chip2 && (result >> 16) & BIT_ERASE_DONE) - chip2 = READY; - - if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR) - chip2 = ERR; - - } while (!chip1 || !chip2); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR || chip2 == ERR) { - rc = ERR_PROG_ERROR; - printf ("Flash erase error\n"); - goto outahere; - } - if (chip1 == TMO) { - rc = ERR_TIMOUT; - printf ("Flash erase timeout error\n"); - goto outahere; - } - } - } - -outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - -#if 0 - if (cflag) - icache_enable (); -#endif - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *) dest; - ulong result; - int rc = ERR_OK; - -#if 0 - int cflag; -#endif - int iflag; - int chip1, chip2; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ -#if 0 - cflag = icache_status (); - icache_disable (); -#endif - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait until flash is ready */ - chip1 = chip2 = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { - chip1 = ERR | TMO; - break; - } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { - result = *addr; - - if ((result & 0x80) == (data & 0x80)) - chip1 = READY; - else - chip1 = ERR; - } - - if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16)))) - chip2 = READY; - - if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR)) { - result = *addr; - - if ((result & (0x80 << 16)) == (data & (0x80 << 16))) - chip2 = READY; - else - chip2 = ERR; - } - - } while (!chip1 || !chip2); - - *addr = CMD_READ_ARRAY; - - if (chip1 == ERR || chip2 == ERR || *addr != data) { - rc = ERR_PROG_ERROR; - printf ("Flash program error\n"); - debug ("chip1: %#x, chip2: %#x, addr: %#lx *addr: %#lx, " - "data: %#lx\n", - chip1, chip2, addr, *addr, data); - } - - if (iflag) - enable_interrupts (); - -#if 0 - if (cflag) - icache_enable (); -#endif - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int l; - int i, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 24); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - - if ((rc = write_word (info, wp, data)) != 0) { - goto Done; - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - if (((ulong)src) & 0x3) { - for (i = 0; i < 4; i++) { - ((char *)&data)[i] = ((vu_char *)src)[i]; - } - } - else { - data = *((vu_long *) src); - } - - if ((rc = write_word (info, wp, data)) != 0) { - goto Done; - } - src += 4; - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - rc = ERR_OK; - goto Done; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 24); - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - - rc = write_word (info, wp, data); - - Done: - - return (rc); -} - -/*----------------------------------------------------------------------- - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - ulong value; - - /* Write auto select command sequence and read Manufacturer ID */ - addr[0x0555] = CMD_UNLOCK1; - addr[0x02AA] = CMD_UNLOCK2; - addr[0x0555] = CMD_READ_MANF_ID; - - value = addr[0]; - - debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case MX_MANUFACT: - info->flash_id = FLASH_MAN_MX; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = CMD_READ_ARRAY; /* restore read mode */ - debug ("## flash_init: unknown manufacturer\n"); - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); - - switch (value) { - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00800000; - - addr[0] = CMD_READ_ARRAY; /* restore read mode */ - break; /* => 8 MB */ - - case AMD_ID_LV640U: - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x01000000; - - addr[0] = CMD_READ_ARRAY; /* restore read mode */ - break; /* => 16 MB */ - - case MX_ID_LV320B: - info->flash_id += FLASH_MXLV320B; - info->sector_count = 71; - info->size = 0x00800000; - - addr[0] = CMD_READ_ARRAY; /* restore read mode */ - break; /* => 8 MB */ - - default: - debug ("## flash_init: unknown flash chip\n"); - info->flash_id = FLASH_UNKNOWN; - addr[0] = CMD_READ_ARRAY; /* restore read mode */ - return (0); /* => no or unknown flash */ - - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - return (info->size); -} diff --git a/board/trab/lowlevel_init.S b/board/trab/lowlevel_init.S deleted file mode 100644 index 3cef414..0000000 --- a/board/trab/lowlevel_init.S +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the TRAB board by - * (C) Copyright 2002-2003 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include <config.h> -#include <version.h> - - -/* some parameters for the board */ - -/* - * - * Copied from linux/arch/arm/boot/compressed/head-s3c2400.S - * - * Copyright (C) 2001 Samsung Electronics by chc, 010406 - * - * TRAB specific tweaks. - * - */ - -/* memory controller */ -#define BWSCON 0x14000000 - -/* Bank0 */ -#define B0_Tacs 0x1 /* 1 clk */ -#define B0_Tcos 0x1 /* 1 clk */ -#define B0_Tacc 0x5 /* 8 clk */ -#define B0_Tcoh 0x1 /* 1 clk */ -#define B0_Tah 0x1 /* 1 clk */ -#define B0_Tacp 0x0 -#define B0_PMC 0x0 /* normal */ - -/* Bank1 - SRAM */ -#define B1_Tacs 0x1 /* 1 clk */ -#define B1_Tcos 0x1 /* 1 clk */ -#define B1_Tacc 0x5 /* 8 clk */ -#define B1_Tcoh 0x1 /* 1 clk */ -#define B1_Tah 0x1 /* 1 clk */ -#define B1_Tacp 0x0 -#define B1_PMC 0x0 /* normal */ - -/* Bank2 - CPLD */ -#define B2_Tacs 0x1 /* 1 clk */ -#define B2_Tcos 0x1 /* 1 clk */ -#define B2_Tacc 0x5 /* 8 clk */ -#define B2_Tcoh 0x1 /* 1 clk */ -#define B2_Tah 0x1 /* 1 clk */ -#define B2_Tacp 0x0 -#define B2_PMC 0x0 /* normal */ - -/* Bank3 - setup for the cs8900 */ -#define B3_Tacs 0x3 /* 4 clk */ -#define B3_Tcos 0x3 /* 4 clk */ -#define B3_Tacc 0x7 /* 14 clk */ -#define B3_Tcoh 0x1 /* 1 clk */ -#define B3_Tah 0x0 /* 0 clk */ -#define B3_Tacp 0x3 /* 6 clk */ -#define B3_PMC 0x0 /* normal */ - -/* Bank4 */ -#define B4_Tacs 0x0 /* 0 clk */ -#define B4_Tcos 0x0 /* 0 clk */ -#define B4_Tacc 0x7 /* 14 clk */ -#define B4_Tcoh 0x0 /* 0 clk */ -#define B4_Tah 0x0 /* 0 clk */ -#define B4_Tacp 0x0 -#define B4_PMC 0x0 /* normal */ - -/* Bank5 */ -#define B5_Tacs 0x0 /* 0 clk */ -#define B5_Tcos 0x0 /* 0 clk */ -#define B5_Tacc 0x7 /* 14 clk */ -#define B5_Tcoh 0x0 /* 0 clk */ -#define B5_Tah 0x0 /* 0 clk */ -#define B5_Tacp 0x0 -#define B5_PMC 0x0 /* normal */ - -#ifndef CONFIG_RAM_16MB /* 32 MB RAM */ -/* Bank6 */ -#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x0 /* 2clk */ -#define B6_SCAN 0x1 /* 9 bit */ - -/* Bank7 */ -#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x0 /* 2clk */ -#define B7_SCAN 0x1 /* 9 bit */ -#else /* CONFIG_RAM_16MB = 16 MB RAM */ -/* Bank6 */ -#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 /* 2clk */ -#define B6_SCAN 0x0 /* 8 bit */ - -/* Bank7 */ -#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 2clk */ -#define B7_SCAN 0x0 /* 8 bit */ -#endif /* CONFIG_RAM_16MB */ - -/* refresh parameter */ -#define REFEN 0x1 /* enable refresh */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */ -#define Trp 0x0 /* 2 clk */ -#define Trc 0x3 /* 7 clk */ -#define Tchr 0x2 /* 3 clk */ - -#ifdef CONFIG_TRAB_50MHZ -#define REFCNT 1269 /* period=15.6 us, HCLK=50Mhz, (2048+1-15.6*50) */ -#else -#define REFCNT 1011 /* period=15.6 us, HCLK=66.5Mhz, (2048+1-15.6*66.5) */ -#endif - - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - -.globl lowlevel_init -lowlevel_init: - /* memory control configuration */ - /* make r0 relative the current location so that it */ - /* reads SMRDATA out of FLASH rather than memory ! */ - ldr r0, =SMRDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #52 -0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 - bne 0b - - /* everything is fine now */ - mov pc, lr - - .ltorg -/* the literal pools origin */ - -SMRDATA: - .word 0x2211d644 /* d->Ethernet, 6->CPLD, 4->SRAM, 4->FLASH */ - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */ - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */ - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */ - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */ - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */ - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */ - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */ - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) -#ifndef CONFIG_RAM_16MB /* 32 MB RAM */ - .word 0x10 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */ -#else /* CONFIG_RAM_16MB = 16 MB RAM */ - .word 0x17 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 16M/16M */ -#endif /* CONFIG_RAM_16MB */ - .word 0x20 /* MRSR6, CL=2clk */ - .word 0x20 /* MRSR7 */ diff --git a/board/trab/memory.c b/board/trab/memory.c deleted file mode 100644 index 895b68e..0000000 --- a/board/trab/memory.c +++ /dev/null @@ -1,486 +0,0 @@ -/* - * (C) Copyright 2002-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* Memory test - * - * General observations: - * o The recommended test sequence is to test the data lines: if they are - * broken, nothing else will work properly. Then test the address - * lines. Finally, test the cells in the memory now that the test - * program knows that the address and data lines work properly. - * This sequence also helps isolate and identify what is faulty. - * - * o For the address line test, it is a good idea to use the base - * address of the lowest memory location, which causes a '1' bit to - * walk through a field of zeros on the address lines and the highest - * memory location, which causes a '0' bit to walk through a field of - * '1's on the address line. - * - * o Floating buses can fool memory tests if the test routine writes - * a value and then reads it back immediately. The problem is, the - * write will charge the residual capacitance on the data bus so the - * bus retains its state briefely. When the test program reads the - * value back immediately, the capacitance of the bus can allow it - * to read back what was written, even though the memory circuitry - * is broken. To avoid this, the test program should write a test - * pattern to the target location, write a different pattern elsewhere - * to charge the residual capacitance in a differnt manner, then read - * the target location back. - * - * o Always read the target location EXACTLY ONCE and save it in a local - * variable. The problem with reading the target location more than - * once is that the second and subsequent reads may work properly, - * resulting in a failed test that tells the poor technician that - * "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which - * doesn't help him one bit and causes puzzled phone calls. Been there, - * done that. - * - * Data line test: - * --------------- - * This tests data lines for shorts and opens by forcing adjacent data - * to opposite states. Because the data lines could be routed in an - * arbitrary manner the must ensure test patterns ensure that every case - * is tested. By using the following series of binary patterns every - * combination of adjacent bits is test regardless of routing. - * - * ...101010101010101010101010 - * ...110011001100110011001100 - * ...111100001111000011110000 - * ...111111110000000011111111 - * - * Carrying this out, gives us six hex patterns as follows: - * - * 0xaaaaaaaaaaaaaaaa - * 0xcccccccccccccccc - * 0xf0f0f0f0f0f0f0f0 - * 0xff00ff00ff00ff00 - * 0xffff0000ffff0000 - * 0xffffffff00000000 - * - * To test for short and opens to other signals on our boards, we - * simply test with the 1's complemnt of the paterns as well, resulting - * in twelve patterns total. - * - * After writing a test pattern. a special pattern 0x0123456789ABCDEF is - * written to a different address in case the data lines are floating. - * Thus, if a byte lane fails, you will see part of the special - * pattern in that byte lane when the test runs. For example, if the - * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa - * (for the 'a' test pattern). - * - * Address line test: - * ------------------ - * This function performs a test to verify that all the address lines - * hooked up to the RAM work properly. If there is an address line - * fault, it usually shows up as two different locations in the address - * map (related by the faulty address line) mapping to one physical - * memory storage location. The artifact that shows up is writing to - * the first location "changes" the second location. - * - * To test all address lines, we start with the given base address and - * xor the address with a '1' bit to flip one address line. For each - * test, we shift the '1' bit left to test the next address line. - * - * In the actual code, we start with address sizeof(ulong) since our - * test pattern we use is a ulong and thus, if we tried to test lower - * order address bits, it wouldn't work because our pattern would - * overwrite itself. - * - * Example for a 4 bit address space with the base at 0000: - * 0000 <- base - * 0001 <- test 1 - * 0010 <- test 2 - * 0100 <- test 3 - * 1000 <- test 4 - * Example for a 4 bit address space with the base at 0010: - * 0010 <- base - * 0011 <- test 1 - * 0000 <- (below the base address, skipped) - * 0110 <- test 2 - * 1010 <- test 3 - * - * The test locations are successively tested to make sure that they are - * not "mirrored" onto the base address due to a faulty address line. - * Note that the base and each test location are related by one address - * line flipped. Note that the base address need not be all zeros. - * - * Memory tests 1-4: - * ----------------- - * These tests verify RAM using sequential writes and reads - * to/from RAM. There are several test cases that use different patterns to - * verify RAM. Each test case fills a region of RAM with one pattern and - * then reads the region back and compares its contents with the pattern. - * The following patterns are used: - * - * 1a) zero pattern (0x00000000) - * 1b) negative pattern (0xffffffff) - * 1c) checkerboard pattern (0x55555555) - * 1d) checkerboard pattern (0xaaaaaaaa) - * 2) bit-flip pattern ((1 << (offset % 32)) - * 3) address pattern (offset) - * 4) address pattern (~offset) - * - * Being run in normal mode, the test verifies only small 4Kb - * regions of RAM around each 1Mb boundary. For example, for 64Mb - * RAM the following areas are verified: 0x00000000-0x00000800, - * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800- - * 0x04000000. If the test is run in slow-test mode, it verifies - * the whole RAM. - */ - -/* #ifdef CONFIG_POST */ - -#include <post.h> -#include <watchdog.h> - -/* #if CONFIG_POST & CONFIG_SYS_POST_MEMORY */ - -/* - * Define INJECT_*_ERRORS for testing error detection in the presence of - * _good_ hardware. - */ -#undef INJECT_DATA_ERRORS -#undef INJECT_ADDRESS_ERRORS - -#ifdef INJECT_DATA_ERRORS -#warning "Injecting data line errors for testing purposes" -#endif - -#ifdef INJECT_ADDRESS_ERRORS -#warning "Injecting address line errors for testing purposes" -#endif - - -/* - * This function performs a double word move from the data at - * the source pointer to the location at the destination pointer. - * This is helpful for testing memory on processors which have a 64 bit - * wide data bus. - * - * On those PowerPC with FPU, use assembly and a floating point move: - * this does a 64 bit move. - * - * For other processors, let the compiler generate the best code it can. - */ -static void move64(const unsigned long long *src, unsigned long long *dest) -{ -#if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X) - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0" ); /* Clobbers fr0 */ - return; -#else - *dest = *src; -#endif -} - -/* - * This is 64 bit wide test patterns. Note that they reside in ROM - * (which presumably works) and the tests write them to RAM which may - * not work. - * - * The "otherpattern" is written to drive the data bus to values other - * than the test pattern. This is for detecting floating bus lines. - * - */ -const static unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaULL, - 0xccccccccccccccccULL, - 0xf0f0f0f0f0f0f0f0ULL, - 0xff00ff00ff00ff00ULL, - 0xffff0000ffff0000ULL, - 0xffffffff00000000ULL, - 0x00000000ffffffffULL, - 0x0000ffff0000ffffULL, - 0x00ff00ff00ff00ffULL, - 0x0f0f0f0f0f0f0f0fULL, - 0x3333333333333333ULL, - 0x5555555555555555ULL, -}; -const unsigned long long otherpattern = 0x0123456789abcdefULL; - - -static int memory_post_dataline(unsigned long long * pmem) -{ - unsigned long long temp64; - int num_patterns = sizeof(pattern)/ sizeof(pattern[0]); - int i; - unsigned int hi, lo, pathi, patlo; - int ret = 0; - - for ( i = 0; i < num_patterns; i++) { - move64(&(pattern[i]), pmem++); - /* - * Put a different pattern on the data lines: otherwise they - * may float long enough to read back what we wrote. - */ - move64(&otherpattern, pmem--); - move64(pmem, &temp64); - -#ifdef INJECT_DATA_ERRORS - temp64 ^= 0x00008000; -#endif - - if (temp64 != pattern[i]){ - pathi = (pattern[i]>>32) & 0xffffffff; - patlo = pattern[i] & 0xffffffff; - - hi = (temp64>>32) & 0xffffffff; - lo = temp64 & 0xffffffff; - - printf ("Memory (date line) error at %08lx, " - "wrote %08x%08x, read %08x%08x !\n", - (ulong)pmem, pathi, patlo, hi, lo); - ret = -1; - } - } - return ret; -} - -static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size) -{ - ulong *target; - ulong *end; - ulong readback; - ulong xor; - int ret = 0; - - end = (ulong *)((ulong)base + size); /* pointer arith! */ - xor = 0; - for(xor = sizeof(ulong); xor > 0; xor <<= 1) { - target = (ulong *)((ulong)testaddr ^ xor); - if((target >= base) && (target < end)) { - *testaddr = ~*target; - readback = *target; - -#ifdef INJECT_ADDRESS_ERRORS - if(xor == 0x00008000) { - readback = *testaddr; - } -#endif - if(readback == *testaddr) { - printf ("Memory (address line) error at %08lx<->%08lx, " - "XOR value %08lx !\n", - (ulong)testaddr, (ulong)target, - xor); - ret = -1; - } - } - } - return ret; -} - -static int memory_post_test1 (unsigned long start, - unsigned long size, - unsigned long val) -{ - unsigned long i; - ulong *mem = (ulong *) start; - ulong readback; - int ret = 0; - - for (i = 0; i < size / sizeof (ulong); i++) { - mem[i] = val; - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { - readback = mem[i]; - if (readback != val) { - printf ("Memory error at %08lx, " - "wrote %08lx, read %08lx !\n", - (ulong)(mem + i), val, readback); - - ret = -1; - break; - } - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - return ret; -} - -static int memory_post_test2 (unsigned long start, unsigned long size) -{ - unsigned long i; - ulong *mem = (ulong *) start; - ulong readback; - int ret = 0; - - for (i = 0; i < size / sizeof (ulong); i++) { - mem[i] = 1 << (i % 32); - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { - readback = mem[i]; - if (readback != (1 << (i % 32))) { - printf ("Memory error at %08lx, " - "wrote %08x, read %08lx !\n", - (ulong)(mem + i), 1 << (i % 32), readback); - - ret = -1; - break; - } - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - return ret; -} - -static int memory_post_test3 (unsigned long start, unsigned long size) -{ - unsigned long i; - ulong *mem = (ulong *) start; - ulong readback; - int ret = 0; - - for (i = 0; i < size / sizeof (ulong); i++) { - mem[i] = i; - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { - readback = mem[i]; - if (readback != i) { - printf ("Memory error at %08lx, " - "wrote %08lx, read %08lx !\n", - (ulong)(mem + i), i, readback); - - ret = -1; - break; - } - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - return ret; -} - -static int memory_post_test4 (unsigned long start, unsigned long size) -{ - unsigned long i; - ulong *mem = (ulong *) start; - ulong readback; - int ret = 0; - - for (i = 0; i < size / sizeof (ulong); i++) { - mem[i] = ~i; - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { - readback = mem[i]; - if (readback != ~i) { - printf ("Memory error at %08lx, " - "wrote %08lx, read %08lx !\n", - (ulong)(mem + i), ~i, readback); - - ret = -1; - break; - } - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - return ret; -} - -int memory_post_tests (unsigned long start, unsigned long size) -{ - int ret = 0; - - if (ret == 0) - ret = memory_post_dataline ((unsigned long long *)start); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_addrline ((ulong *)start, (ulong *)start, size); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_addrline ((ulong *)(start + size - 8), - (ulong *)start, size); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test1 (start, size, 0x00000000); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test1 (start, size, 0xffffffff); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test1 (start, size, 0x55555555); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test1 (start, size, 0xaaaaaaaa); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test2 (start, size); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test3 (start, size); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test4 (start, size); - WATCHDOG_RESET (); - - return ret; -} - -#if 0 -DECLARE_GLOBAL_DATA_PTR; - -int memory_post_test (int flags) -{ - int ret = 0; - bd_t *bd = gd->bd; - phys_size_t memsize = (bd->bi_memsize >= 256 << 20 ? - 256 << 20 : bd->bi_memsize) - (1 << 20); - - - if (flags & POST_SLOWTEST) { - ret = memory_post_tests (CONFIG_SYS_SDRAM_BASE, memsize); - } else { /* POST_NORMAL */ - - unsigned long i; - - for (i = 0; i < (memsize >> 20) && ret == 0; i++) { - if (ret == 0) - ret = memory_post_tests (i << 20, 0x800); - if (ret == 0) - ret = memory_post_tests ((i << 20) + 0xff800, 0x800); - } - } - - return ret; -} -#endif /* 0 */ - -/* #endif */ /* CONFIG_POST & CONFIG_SYS_POST_MEMORY */ -/* #endif */ /* CONFIG_POST */ diff --git a/board/trab/rs485.c b/board/trab/rs485.c deleted file mode 100644 index 30336f2..0000000 --- a/board/trab/rs485.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de> - * - * Based on arch/arm/cpu/arm920t/serial.c, by Gary Jennejohn - * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include <common.h> -#include <asm/arch/s3c24x0_cpu.h> -#include "rs485.h" - -static void rs485_setbrg (void); -static void rs485_cfgio (void); -static void set_rs485re(unsigned char rs485re_state); -static void set_rs485de(unsigned char rs485de_state); -static void rs485_setbrg (void); -#ifdef NOT_USED -static void trab_rs485_disable_tx(void); -static void trab_rs485_disable_rx(void); -#endif - -#define UART_NR S3C24X0_UART1 - -/* CPLD-Register for controlling TRAB hardware functions */ -#define CPLD_RS485_RE ((volatile unsigned long *)0x04028000) - -static void rs485_setbrg (void) -{ - struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR); - int i; - unsigned int reg = 0; - - /* value is calculated so : (int)(PCLK/16./baudrate) -1 */ - /* reg = (33000000 / (16 * gd->baudrate)) - 1; */ - reg = (33000000 / (16 * 38400)) - 1; - - /* FIFO enable, Tx/Rx FIFO clear */ - uart->ufcon = 0x07; - uart->umcon = 0x0; - /* Normal,No parity,1 stop,8 bit */ - uart->ulcon = 0x3; - /* - * tx=level,rx=edge,disable timeout int.,enable rx error int., - * normal,interrupt or polling - */ - uart->ucon = 0x245; - uart->ubrdiv = reg; - - for (i = 0; i < 100; i++); -} - -static void rs485_cfgio (void) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - gpio->pfcon &= ~(0x3 << 2); - gpio->pfcon |= (0x2 << 2); /* configure GPF1 as RXD1 */ - - gpio->pfcon &= ~(0x3 << 6); - gpio->pfcon |= (0x2 << 6); /* configure GPF3 as TXD1 */ - - gpio->pfup |= (1 << 1); /* disable pullup on GPF1 */ - gpio->pfup |= (1 << 3); /* disable pullup on GPF3 */ - - gpio->pacon &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */ -} - -/* - * Initialise the rs485 port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int rs485_init (void) -{ - rs485_cfgio (); - rs485_setbrg (); - - return (0); -} - -/* - * Read a single byte from the rs485 port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int rs485_getc (void) -{ - struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR); - - /* wait for character to arrive */ - while (!(uart->utrstat & 0x1)) - ; - - return uart->urxh & 0xff; -} - -/* - * Output a single byte to the rs485 port. - */ -void rs485_putc (const char c) -{ - struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR); - - /* wait for room in the tx FIFO */ - while (!(uart->utrstat & 0x2)) - ; - - uart->utxh = c; - - /* If \n, also do \r */ - if (c == '\n') - rs485_putc ('\r'); -} - -/* - * Test whether a character is in the RX buffer - */ -int rs485_tstc (void) -{ - struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR); - - return uart->utrstat & 0x1; -} - -void rs485_puts (const char *s) -{ - while (*s) { - rs485_putc (*s++); - } -} - - -/* - * State table: - * RE DE Result - * 1 1 XMIT - * 0 0 RCV - * 1 0 Shutdown - */ - -/* function that controls the receiver enable for the rs485 */ -/* rs485re_state reflects the level (0/1) of the RE pin */ - -static void set_rs485re(unsigned char rs485re_state) -{ - if(rs485re_state) - *CPLD_RS485_RE = 0x010000; - else - *CPLD_RS485_RE = 0x0; -} - -/* function that controls the sender enable for the rs485 */ -/* rs485de_state reflects the level (0/1) of the DE pin */ - -static void set_rs485de(unsigned char rs485de_state) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* This is on PORT A bit 11 */ - if(rs485de_state) - gpio->padat |= (1 << 11); - else - gpio->padat &= ~(1 << 11); -} - - -void trab_rs485_enable_tx(void) -{ - set_rs485de(1); - set_rs485re(1); -} - -void trab_rs485_enable_rx(void) -{ - set_rs485re(0); - set_rs485de(0); -} - -#ifdef NOT_USED -static void trab_rs485_disable_tx(void) -{ - set_rs485de(0); -} - -static void trab_rs485_disable_rx(void) -{ - set_rs485re(1); -} -#endif diff --git a/board/trab/rs485.h b/board/trab/rs485.h deleted file mode 100644 index 19e3244..0000000 --- a/board/trab/rs485.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de> - * - * Based on arch/arm/cpu/arm920t/serial.c, by Gary Jennejohn - * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef _RS485_H_ -#define _RS485_H_ - -#include <asm/arch/s3c24x0_cpu.h> - -int rs485_init (void); -int rs485_getc (void); -void rs485_putc (const char c); -int rs485_tstc (void); -void rs485_puts (const char *s); -void trab_rs485_enable_tx(void); -void trab_rs485_enable_rx(void); - -#endif /* _RS485_H_ */ diff --git a/board/trab/trab.c b/board/trab/trab.c deleted file mode 100644 index 0f74e8f..0000000 --- a/board/trab/trab.c +++ /dev/null @@ -1,436 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* #define DEBUG */ - -#include <common.h> -#include <netdev.h> -#include <malloc.h> -#include <asm/arch/s3c24x0_cpu.h> -#include <command.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SYS_BRIGHTNESS -static void spi_init(void); -static void wait_transmit_done(void); -static void tsc2000_write(unsigned int page, unsigned int reg, - unsigned int data); -static void tsc2000_set_brightness(void); -#endif -#ifdef CONFIG_MODEM_SUPPORT -static int key_pressed(void); -extern void disable_putc(void); -extern int do_mdm_init; /* defined in common/main.c */ - -/* - * We need a delay of at least 500 us after turning on the VFD clock - * before we can read any useful information for the CPLD controlling - * the keyboard switches. Let's play safe and wait 5 ms. The problem - * is that timers are not available yet, so we use a manually timed - * loop. - */ -#define KBD_MDELAY 5000 -static void udelay_no_timer (int usec) -{ - int i; - int delay = usec * 3; - - for (i = 0; i < delay; i ++) gd->bd->bi_arch_number = MACH_TYPE_TRAB; -} -#endif /* CONFIG_MODEM_SUPPORT */ - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init () -{ -#if defined(CONFIG_VFD) - extern int vfd_init_clocks(void); -#endif - struct s3c24x0_clock_power * const clk_power = - s3c24x0_get_base_clock_power(); - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* memory and cpu-speed are setup before relocation */ -#ifdef CONFIG_TRAB_50MHZ - /* change the clock to be 50 MHz 1:1:1 */ - /* MDIV:0x5c PDIV:4 SDIV:2 */ - clk_power->mpllcon = 0x5c042; - clk_power->clkdivn = 0; -#else - /* change the clock to be 133 MHz 1:2:4 */ - /* MDIV:0x7d PDIV:4 SDIV:1 */ - clk_power->mpllcon = 0x7d041; - clk_power->clkdivn = 3; -#endif - - /* set up the I/O ports */ - gpio->pacon = 0x3ffff; - gpio->pbcon = 0xaaaaaaaa; - gpio->pbup = 0xffff; - /* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0] */ - /* 00, 10, 10, 10, 10, 10, 10 */ - gpio->pfcon = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10); -#ifdef CONFIG_HWFLOW - /* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */ - gpio->pfup = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5); -#else - /* do not pull up RXD0, RXD1, TXD0, TXD1 */ - gpio->pfup = (1<<0) | (1<<1) | (1<<2) | (1<<3); -#endif - gpio->pgcon = 0x0; - gpio->pgup = 0x0; - gpio->opencr = 0x0; - - /* suppress flicker of the VFDs */ - gpio->misccr = 0x40; - gpio->pfcon |= (2<<12); - - gd->bd->bi_arch_number = MACH_TYPE_TRAB; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x0c000100; - - /* Make sure both buzzers are turned off */ - gpio->pdcon |= 0x5400; - gpio->pddat &= ~0xE0; - -#ifdef CONFIG_VFD - vfd_init_clocks(); -#endif /* CONFIG_VFD */ - -#ifdef CONFIG_MODEM_SUPPORT - udelay_no_timer (KBD_MDELAY); - - if (key_pressed()) { - disable_putc(); /* modem doesn't understand banner etc */ - do_mdm_init = 1; - } -#endif /* CONFIG_MODEM_SUPPORT */ - -#ifdef CONFIG_DRIVER_S3C24X0_I2C - /* Configure I/O ports PG5 und PG6 for I2C */ - gpio->pgcon = (gpio->pgcon & 0x003c00) | 0x003c00; -#endif /* CONFIG_DRIVER_S3C24X0_I2C */ - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - return 0; -} - -/*----------------------------------------------------------------------- - * Keyboard Controller - */ - -/* Maximum key number */ -#define KEYBD_KEY_NUM 4 - -#define KBD_DATA (((*(volatile ulong *)0x04020000) >> 16) & 0xF) - -static char *key_match (ulong); - -int misc_init_r (void) -{ - ulong kbd_data = KBD_DATA; - char *str; - char keybd_env[KEYBD_KEY_NUM + 1]; - int i; - -#ifdef CONFIG_VERSION_VARIABLE - { - /* Set version variable. Please note, that this variable is - * also set in main_loop() later in the boot process. The - * version variable has to be set this early, because so it - * could be used in script files on an usb stick, which - * might be called during do_auto_update() */ - extern char version_string[]; - - setenv ("ver", version_string); - } -#endif /* CONFIG_VERSION_VARIABLE */ - -#ifdef CONFIG_AUTO_UPDATE - { - extern int do_auto_update(void); - /* this has priority over all else */ - do_auto_update(); - } -#endif - - for (i = 0; i < KEYBD_KEY_NUM; ++i) { - keybd_env[i] = '0' + ((kbd_data >> i) & 1); - } - keybd_env[i] = '\0'; - debug ("** Setting keybd=\"%s\"\n", keybd_env); - setenv ("keybd", keybd_env); - - str = strdup (key_match (kbd_data)); /* decode keys */ - -#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */ - debug ("** Setting preboot=\"%s\"\n", str); - setenv ("preboot", str); /* set or delete definition */ -#endif /* CONFIG_PREBOOT */ - if (str != NULL) { - free (str); - } - -#ifdef CONFIG_SYS_BRIGHTNESS - tsc2000_set_brightness(); -#endif - return (0); -} - -#ifdef CONFIG_PREBOOT - -static uchar kbd_magic_prefix[] = "key_magic"; -static uchar kbd_command_prefix[] = "key_cmd"; - -static int compare_magic (ulong kbd_data, char *str) -{ - uchar key_mask; - - debug ("compare_magic: kbd: %04lx str: \"%s\"\n",kbd_data,str); - for (; *str; str++) - { - uchar c = *str - '1'; - - if (c >= KEYBD_KEY_NUM) /* bad key number */ - return -1; - - key_mask = 1 << c; - - if (!(kbd_data & key_mask)) { /* key not pressed */ - debug ( "compare_magic: " - "kbd: %04lx mask: %04lx - key not pressed\n", - kbd_data, key_mask ); - return -1; - } - - kbd_data &= ~key_mask; - } - - if (kbd_data) { /* key(s) not released */ - debug ( "compare_magic: " - "kbd: %04lx - key(s) not released\n", kbd_data); - return -1; - } - - return 0; -} - -/*----------------------------------------------------------------------- - * Check if pressed key(s) match magic sequence, - * and return the command string associated with that key(s). - * - * If no key press was decoded, NULL is returned. - * - * Note: the first character of the argument will be overwritten with - * the "magic charcter code" of the decoded key(s), or '\0'. - * - * - * Note: the string points to static environment data and must be - * saved before you call any function that modifies the environment. - */ -static char *key_match (ulong kbd_data) -{ - char magic[sizeof (kbd_magic_prefix) + 1]; - char cmd_name[sizeof (kbd_command_prefix) + 1]; - char *suffix; - char *kbd_magic_keys; - - /* - * The following string defines the characters that can pe appended - * to "key_magic" to form the names of environment variables that - * hold "magic" key codes, i. e. such key codes that can cause - * pre-boot actions. If the string is empty (""), then only - * "key_magic" is checked (old behaviour); the string "125" causes - * checks for "key_magic1", "key_magic2" and "key_magic5", etc. - */ - if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) - kbd_magic_keys = ""; - - debug ("key_match: magic_keys=\"%s\"\n", kbd_magic_keys); - - /* loop over all magic keys; - * use '\0' suffix in case of empty string - */ - for (suffix=kbd_magic_keys; *suffix || suffix==kbd_magic_keys; ++suffix) - { - sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); - - debug ("key_match: magic=\"%s\"\n", - getenv(magic) ? getenv(magic) : "<UNDEFINED>"); - - if (compare_magic(kbd_data, getenv(magic)) == 0) - { - sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); - debug ("key_match: cmdname %s=\"%s\"\n", - cmd_name, - getenv (cmd_name) ? - getenv (cmd_name) : - "<UNDEFINED>"); - return (getenv (cmd_name)); - } - } - debug ("key_match: no match\n"); - return (NULL); -} -#endif /* CONFIG_PREBOOT */ - -/* Read Keyboard status */ -int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - ulong kbd_data = KBD_DATA; - char keybd_env[KEYBD_KEY_NUM + 1]; - int i; - - puts ("Keys:"); - for (i = 0; i < KEYBD_KEY_NUM; ++i) { - keybd_env[i] = '0' + ((kbd_data >> i) & 1); - printf (" %c", keybd_env[i]); - } - keybd_env[i] = '\0'; - putc ('\n'); - setenv ("keybd", keybd_env); - return 0; -} - -U_BOOT_CMD( - kbd, 1, 1, do_kbd, - "read keyboard status", - "" -); - -#ifdef CONFIG_MODEM_SUPPORT -static int key_pressed(void) -{ - return (compare_magic(KBD_DATA, CONFIG_MODEM_KEY_MAGIC) == 0); -} -#endif /* CONFIG_MODEM_SUPPORT */ - -#ifdef CONFIG_SYS_BRIGHTNESS - -static inline void SET_CS_TOUCH(void) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - gpio->pddat &= 0x5FF; -} - -static inline void CLR_CS_TOUCH(void) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - gpio->pddat |= 0x200; -} - -static void spi_init(void) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - struct s3c24x0_spi * const spi = s3c24x0_get_base_spi(); - int i; - - /* Configure I/O ports. */ - gpio->pdcon = (gpio->pdcon & 0xF3FFFF) | 0x040000; - gpio->pgcon = (gpio->pgcon & 0x0F3FFF) | 0x008000; - gpio->pgcon = (gpio->pgcon & 0x0CFFFF) | 0x020000; - gpio->pgcon = (gpio->pgcon & 0x03FFFF) | 0x080000; - - CLR_CS_TOUCH(); - - spi->ch[0].sppre = 0x1F; /* Baudrate ca. 514kHz */ - spi->ch[0].sppin = 0x01; /* SPI-MOSI holds Level after last bit */ - spi->ch[0].spcon = 0x1A; /* Polling, Prescale, Master, CPOL=0, CPHA=1 */ - - /* Dummy byte ensures clock to be low. */ - for (i = 0; i < 10; i++) { - spi->ch[0].sptdat = 0xFF; - } - wait_transmit_done(); -} - -static void wait_transmit_done(void) -{ - struct s3c24x0_spi * const spi = s3c24x0_get_base_spi(); - - while (!(spi->ch[0].spsta & 0x01)) /* wait until transfer is done */ - ; -} - -static void tsc2000_write(unsigned int page, unsigned int reg, - unsigned int data) -{ - struct s3c24x0_spi * const spi = s3c24x0_get_base_spi(); - unsigned int command; - - SET_CS_TOUCH(); - command = 0x0000; - command |= (page << 11); - command |= (reg << 5); - - spi->ch[0].sptdat = (command & 0xFF00) >> 8; - wait_transmit_done(); - spi->ch[0].sptdat = (command & 0x00FF); - wait_transmit_done(); - spi->ch[0].sptdat = (data & 0xFF00) >> 8; - wait_transmit_done(); - spi->ch[0].sptdat = (data & 0x00FF); - wait_transmit_done(); - - CLR_CS_TOUCH(); -} - -static void tsc2000_set_brightness(void) -{ - char tmp[10]; - int i, br; - - spi_init(); - tsc2000_write(1, 2, 0x0); /* Power up DAC */ - - i = getenv_f("brightness", tmp, sizeof(tmp)); - br = (i > 0) - ? (int) simple_strtoul (tmp, NULL, 10) - : CONFIG_SYS_BRIGHTNESS; - - tsc2000_write(0, 0xb, br & 0xff); -} -#endif - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c deleted file mode 100644 index fe3dab3..0000000 --- a/board/trab/trab_fkt.c +++ /dev/null @@ -1,1418 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define DEBUG - -#include <common.h> -#include <exports.h> -#include <timestamp.h> -#include <asm/arch/s3c24x0_cpu.h> -#include "tsc2000.h" -#include "rs485.h" - -/* - * define, to wait for the touch to be pressed, before reading coordinates in - * command do_touch. If not defined, an error message is printed, when the - * command do_touch is invoked and the touch is not pressed within an specific - * interval. - */ -#undef CONFIG_TOUCH_WAIT_PRESSED - -/* max time to wait for touch is pressed */ -#ifndef CONFIG_TOUCH_WAIT_PRESSED -#define TOUCH_TIMEOUT 5 -#endif /* !CONFIG_TOUCH_WAIT_PRESSED */ - -/* assignment of CPU internal ADC channels with TRAB hardware */ -#define VCC5V 2 -#define VCC12V 3 - -/* CPLD-Register for controlling TRAB hardware functions */ -#define CPLD_BUTTONS ((volatile unsigned long *)0x04020000) -#define CPLD_FILL_LEVEL ((volatile unsigned long *)0x04008000) -#define CPLD_ROTARY_SWITCH ((volatile unsigned long *)0x04018000) -#define CPLD_RS485_RE ((volatile unsigned long *)0x04028000) - -/* timer configuration bits for buzzer and PWM */ -#define START2 (1 << 12) -#define UPDATE2 (1 << 13) -#define INVERT2 (1 << 14) -#define RELOAD2 (1 << 15) -#define START3 (1 << 16) -#define UPDATE3 (1 << 17) -#define INVERT3 (1 << 18) -#define RELOAD3 (1 << 19) - -#define PCLK 66000000 -#define BUZZER_FREQ 1000 /* frequency in Hz */ -#define PWM_FREQ 500 - - -/* definitions of I2C EEPROM device address */ -#define I2C_EEPROM_DEV_ADDR 0x54 - -/* definition for touch panel calibration points */ -#define CALIB_TL 0 /* calibration point in (T)op (L)eft corner */ -#define CALIB_DR 1 /* calibration point in (D)own (R)ight corner */ - -/* EEPROM address map */ -#define SERIAL_NUMBER 8 -#define TOUCH_X0 52 -#define TOUCH_Y0 54 -#define TOUCH_X1 56 -#define TOUCH_Y1 58 -#define CRC16 60 - -/* EEPROM stuff */ -#define EEPROM_MAX_CRC_BUF 64 - -/* RS485 stuff */ -#define RS485_MAX_RECEIVE_BUF_LEN 100 - -/* Bit definitions for ADCCON */ -#define ADC_ENABLE_START 0x1 -#define ADC_READ_START 0x2 -#define ADC_STDBM 0x4 -#define ADC_INP_AIN0 (0x0 << 3) -#define ADC_INP_AIN1 (0x1 << 3) -#define ADC_INP_AIN2 (0x2 << 3) -#define ADC_INP_AIN3 (0x3 << 3) -#define ADC_INP_AIN4 (0x4 << 3) -#define ADC_INP_AIN5 (0x5 << 3) -#define ADC_INP_AIN6 (0x6 << 3) -#define ADC_INP_AIN7 (0x7 << 3) -#define ADC_PRSCEN 0x4000 -#define ADC_ECFLG 0x8000 - -/* function test functions */ -int do_dip (void); -int do_info (void); -int do_vcc5v (void); -int do_vcc12v (void); -int do_buttons (void); -int do_fill_level (void); -int do_rotary_switch (void); -int do_pressure (void); -int do_v_bat (void); -int do_vfd_id (void); -int do_buzzer (char * const *); -int do_led (char * const *); -int do_full_bridge (char * const *); -int do_dac (char * const *); -int do_motor_contact (void); -int do_motor (char * const *); -int do_pwm (char * const *); -int do_thermo (char * const *); -int do_touch (char * const *); -int do_rs485 (char * const *); -int do_serial_number (char * const *); -int do_crc16 (void); -int do_power_switch (void); -int do_gain (char * const *); -int do_eeprom (char * const *); - -/* helper functions */ -static void adc_init (void); -static int adc_read (unsigned int channel); -static void print_identifier (void); - -#ifdef CONFIG_TOUCH_WAIT_PRESSED -static void touch_wait_pressed (void); -#else -static int touch_check_pressed (void); -#endif /* CONFIG_TOUCH_WAIT_PRESSED */ - -static void touch_read_x_y (int *x, int *y); -static int touch_write_clibration_values (int calib_point, int x, int y); -static int rs485_send_line (const char *data); -static int rs485_receive_chars (char *data, int timeout); -static unsigned short updcrc(unsigned short icrc, unsigned char *icp, - unsigned int icnt); - -#if defined(CONFIG_CMD_I2C) -static int trab_eeprom_read (char * const *argv); -static int trab_eeprom_write (char * const *argv); -int i2c_write_multiple (uchar chip, uint addr, int alen, uchar *buffer, - int len); -int i2c_read_multiple ( uchar chip, uint addr, int alen, uchar *buffer, - int len); -#endif - -/* - * TRAB board specific commands. Especially commands for burn-in and function - * test. - */ - -int trab_fkt (int argc, char * const argv[]) -{ - int i; - - app_startup(argv); - if (get_version () != XF_VERSION) { - printf ("Wrong XF_VERSION. Please re-compile with actual " - "u-boot sources\n"); - printf ("Example expects ABI version %d\n", XF_VERSION); - printf ("Actual U-Boot ABI version %d\n", (int)get_version()); - return 1; - } - - debug ("argc = %d\n", argc); - - for (i=0; i<=argc; ++i) { - debug ("argv[%d] = \"%s\"\n", i, argv[i] ? argv[i] : "<NULL>"); - } - - adc_init (); - - switch (argc) { - - case 0: - case 1: - break; - - case 2: - if (strcmp (argv[1], "info") == 0) { - return (do_info ()); - } - if (strcmp (argv[1], "dip") == 0) { - return (do_dip ()); - } - if (strcmp (argv[1], "vcc5v") == 0) { - return (do_vcc5v ()); - } - if (strcmp (argv[1], "vcc12v") == 0) { - return (do_vcc12v ()); - } - if (strcmp (argv[1], "buttons") == 0) { - return (do_buttons ()); - } - if (strcmp (argv[1], "fill_level") == 0) { - return (do_fill_level ()); - } - if (strcmp (argv[1], "rotary_switch") == 0) { - return (do_rotary_switch ()); - } - if (strcmp (argv[1], "pressure") == 0) { - return (do_pressure ()); - } - if (strcmp (argv[1], "v_bat") == 0) { - return (do_v_bat ()); - } - if (strcmp (argv[1], "vfd_id") == 0) { - return (do_vfd_id ()); - } - if (strcmp (argv[1], "motor_contact") == 0) { - return (do_motor_contact ()); - } - if (strcmp (argv[1], "crc16") == 0) { - return (do_crc16 ()); - } - if (strcmp (argv[1], "power_switch") == 0) { - return (do_power_switch ()); - } - break; - - case 3: - if (strcmp (argv[1], "full_bridge") == 0) { - return (do_full_bridge (argv)); - } - if (strcmp (argv[1], "dac") == 0) { - return (do_dac (argv)); - } - if (strcmp (argv[1], "motor") == 0) { - return (do_motor (argv)); - } - if (strcmp (argv[1], "pwm") == 0) { - return (do_pwm (argv)); - } - if (strcmp (argv[1], "thermo") == 0) { - return (do_thermo (argv)); - } - if (strcmp (argv[1], "touch") == 0) { - return (do_touch (argv)); - } - if (strcmp (argv[1], "serial_number") == 0) { - return (do_serial_number (argv)); - } - if (strcmp (argv[1], "buzzer") == 0) { - return (do_buzzer (argv)); - } - if (strcmp (argv[1], "gain") == 0) { - return (do_gain (argv)); - } - break; - - case 4: - if (strcmp (argv[1], "led") == 0) { - return (do_led (argv)); - } - if (strcmp (argv[1], "rs485") == 0) { - return (do_rs485 (argv)); - } - if (strcmp (argv[1], "serial_number") == 0) { - return (do_serial_number (argv)); - } - break; - - case 5: - if (strcmp (argv[1], "eeprom") == 0) { - return (do_eeprom (argv)); - } - break; - - case 6: - if (strcmp (argv[1], "eeprom") == 0) { - return (do_eeprom (argv)); - } - break; - - default: - break; - } - - printf ("Usage:\n<command> <parameter1> <parameter2> ...\n"); - return 1; -} - -void hang (void) -{ - puts ("### ERROR ### Please RESET the board ###\n"); - for (;;); -} - -int do_info (void) -{ - printf ("Stand-alone application for TRAB board function test\n"); - printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); - - return 0; -} - -int do_dip (void) -{ - unsigned int result = 0; - int adc_val; - int i; - - /*********************************************************** - DIP switch connection (according to wa4-cpu.sp.301.pdf, page 3): - SW1 - AIN4 - SW2 - AIN5 - SW3 - AIN6 - SW4 - AIN7 - - "On" DIP switch position short-circuits the voltage from - the input channel (i.e. '0' conversion result means "on"). - *************************************************************/ - - for (i = 7; i > 3; i--) { - - if ((adc_val = adc_read (i)) == -1) { - printf ("Channel %d could not be read\n", i); - return 1; - } - - /* - * Input voltage (switch open) is 1.8 V. - * (Vin_High/VRef)*adc_res = (1,8V/2,5V)*1023) = 736 - * Set trigger at halve that value. - */ - if (adc_val < 368) - result |= (1 << (i-4)); - } - - /* print result to console */ - print_identifier (); - for (i = 0; i < 4; i++) { - if ((result & (1 << i)) == 0) - printf("0"); - else - printf("1"); - } - printf("\n"); - - return 0; -} - - -int do_vcc5v (void) -{ - int result; - - /* VCC5V is connected to channel 2 */ - - if ((result = adc_read (VCC5V)) == -1) { - printf ("VCC5V could not be read\n"); - return 1; - } - - /* - * Calculate voltage value. Split in two parts because there is no - * floating point support. VCC5V is connected over an resistor divider: - * VCC5V=ADCval*2,5V/1023*(10K+30K)/10K. - */ - print_identifier (); - printf ("%d", (result & 0x3FF)* 10 / 1023); - printf (".%d", ((result & 0x3FF)* 10 % 1023)* 10 / 1023); - printf ("%d V\n", (((result & 0x3FF) * 10 % 1023 ) * 10 % 1023) - * 10 / 1024); - - return 0; -} - - -int do_vcc12v (void) -{ - int result; - - if ((result = adc_read (VCC12V)) == -1) { - printf ("VCC12V could not be read\n"); - return 1; - } - - /* - * Calculate voltage value. Split in two parts because there is no - * floating point support. VCC5V is connected over an resistor divider: - * VCC12V=ADCval*2,5V/1023*(30K+270K)/30K. - */ - print_identifier (); - printf ("%d", (result & 0x3FF)* 25 / 1023); - printf (".%d V\n", ((result & 0x3FF)* 25 % 1023) * 10 / 1023); - - return 0; -} - -static int adc_read (unsigned int channel) -{ - int j = 1000; /* timeout value for wait loop in us */ - int result; - struct s3c2400_adc *padc; - - padc = s3c2400_get_base_adc(); - channel &= 0x7; - - padc->adccon &= ~ADC_STDBM; /* select normal mode */ - padc->adccon &= ~(0x7 << 3); /* clear the channel bits */ - padc->adccon |= ((channel << 3) | ADC_ENABLE_START); - - while (j--) { - if ((padc->adccon & ADC_ENABLE_START) == 0) - break; - udelay (1); - } - - if (j == 0) { - printf("%s: ADC timeout\n", __FUNCTION__); - padc->adccon |= ADC_STDBM; /* select standby mode */ - return -1; - } - - result = padc->adcdat & 0x3FF; - - padc->adccon |= ADC_STDBM; /* select standby mode */ - - debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__, - (padc->adccon >> 3) & 0x7, result); - - /* - * Wait for ADC to be ready for next conversion. This delay value was - * estimated, because the datasheet does not specify a value. - */ - udelay (1000); - - return (result); -} - - -static void adc_init (void) -{ - struct s3c2400_adc *padc; - - padc = s3c2400_get_base_adc(); - - padc->adccon &= ~(0xff << 6); /* clear prescaler bits */ - padc->adccon |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */ - - /* - * Wait some time to avoid problem with very first call of - * adc_read(). Without * this delay, sometimes the first read adc - * value is 0. Perhaps because the * adjustment of prescaler takes - * some clock cycles? - */ - udelay (1000); - - return; -} - - -int do_buttons (void) -{ - int result; - int i; - - result = *CPLD_BUTTONS; /* read CPLD */ - debug ("%s: cpld_taster (32 bit) %#x\n", __FUNCTION__, result); - - /* print result to console */ - print_identifier (); - for (i = 16; i <= 19; i++) { - if ((result & (1 << i)) == 0) - printf("0"); - else - printf("1"); - } - printf("\n"); - return 0; -} - - -int do_power_switch (void) -{ - int result; - - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* configure GPE7 as input */ - gpio->pecon &= ~(0x3 << (2 * 7)); - - /* signal GPE7 from power switch is low active: 0=on , 1=off */ - result = ((gpio->pedat & (1 << 7)) == (1 << 7)) ? 0 : 1; - - print_identifier (); - printf("%d\n", result); - return 0; -} - - -int do_fill_level (void) -{ - int result; - - result = *CPLD_FILL_LEVEL; /* read CPLD */ - debug ("%s: cpld_fuellstand (32 bit) %#x\n", __FUNCTION__, result); - - /* print result to console */ - print_identifier (); - if ((result & (1 << 16)) == 0) - printf("0\n"); - else - printf("1\n"); - return 0; -} - - -int do_rotary_switch (void) -{ - int result; - /* - * Please note, that the default values of the direction bits are - * undefined after reset. So it is a good idea, to make first a dummy - * call to this function, to clear the direction bits and set so to - * proper values. - */ - - result = *CPLD_ROTARY_SWITCH; /* read CPLD */ - debug ("%s: cpld_inc (32 bit) %#x\n", __FUNCTION__, result); - - *CPLD_ROTARY_SWITCH |= (3 << 16); /* clear direction bits in CPLD */ - - /* print result to console */ - print_identifier (); - if ((result & (1 << 16)) == (1 << 16)) - printf("R"); - if ((result & (1 << 17)) == (1 << 17)) - printf("L"); - if (((result & (1 << 16)) == 0) && ((result & (1 << 17)) == 0)) - printf("0"); - if ((result & (1 << 18)) == 0) - printf("0\n"); - else - printf("1\n"); - return 0; -} - - -int do_vfd_id (void) -{ - int i; - long int pcup_old, pccon_old; - int vfd_board_id; - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* try to red vfd board id from the value defined by pull-ups */ - - pcup_old = gpio->pcup; - pccon_old = gpio->pccon; - - gpio->pcup = (gpio->pcup & 0xFFF0); /* activate GPC0...GPC3 pull-ups */ - gpio->pccon = (gpio->pccon & 0xFFFFFF00); /* configure GPC0...GPC3 as - * inputs */ - udelay (10); /* allow signals to settle */ - vfd_board_id = (~gpio->pcdat) & 0x000F; /* read GPC0...GPC3 port pins */ - - gpio->pccon = pccon_old; - gpio->pcup = pcup_old; - - /* print vfd_board_id to console */ - print_identifier (); - for (i = 0; i < 4; i++) { - if ((vfd_board_id & (1 << i)) == 0) - printf("0"); - else - printf("1"); - } - printf("\n"); - return 0; -} - -int do_buzzer (char * const *argv) -{ - int counter; - - struct s3c24x0_timers * const timers = s3c24x0_get_base_timers(); - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* set prescaler for timer 2, 3 and 4 */ - timers->tcfg0 &= ~0xFF00; - timers->tcfg0 |= 0x0F00; - - /* set divider for timer 2 */ - timers->tcfg1 &= ~0xF00; - timers->tcfg1 |= 0x300; - - /* set frequency */ - counter = (PCLK / BUZZER_FREQ) >> 9; - timers->ch[2].tcntb = counter; - timers->ch[2].tcmpb = counter / 2; - - if (strcmp (argv[2], "on") == 0) { - debug ("%s: frequency: %d\n", __FUNCTION__, - BUZZER_FREQ); - - /* configure pin GPD7 as TOUT2 */ - gpio->pdcon &= ~0xC000; - gpio->pdcon |= 0x8000; - - /* start */ - timers->tcon = (timers->tcon | UPDATE2 | RELOAD2) & - ~INVERT2; - timers->tcon = (timers->tcon | START2) & ~UPDATE2; - return (0); - } - else if (strcmp (argv[2], "off") == 0) { - /* stop */ - timers->tcon &= ~(START2 | RELOAD2); - - /* configure GPD7 as output and set to low */ - gpio->pdcon &= ~0xC000; - gpio->pdcon |= 0x4000; - gpio->pddat &= ~0x80; - return (0); - } - - printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); - return 1; -} - - -int do_led (char * const *argv) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* configure PC14 and PC15 as output */ - gpio->pccon &= ~(0xF << 28); - gpio->pccon |= (0x5 << 28); - - /* configure PD0 and PD4 as output */ - gpio->pdcon &= ~((0x3 << 8) | 0x3); - gpio->pdcon |= ((0x1 << 8) | 0x1); - - switch (simple_strtoul(argv[2], NULL, 10)) { - - case 0: - case 1: - break; - - case 2: - if (strcmp (argv[3], "on") == 0) - gpio->pcdat |= (1 << 14); - else - gpio->pcdat &= ~(1 << 14); - return 0; - - case 3: - if (strcmp (argv[3], "on") == 0) - gpio->pcdat |= (1 << 15); - else - gpio->pcdat &= ~(1 << 15); - return 0; - - case 4: - if (strcmp (argv[3], "on") == 0) - gpio->pddat |= (1 << 0); - else - gpio->pddat &= ~(1 << 0); - return 0; - - case 5: - if (strcmp (argv[3], "on") == 0) - gpio->pddat |= (1 << 4); - else - gpio->pddat &= ~(1 << 4); - return 0; - - default: - break; - - } - printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); - return 1; -} - - -int do_full_bridge (char * const *argv) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* configure PD5 and PD6 as output */ - gpio->pdcon &= ~((0x3 << 5*2) | (0x3 << 6*2)); - gpio->pdcon |= ((0x1 << 5*2) | (0x1 << 6*2)); - - if (strcmp (argv[2], "+") == 0) { - gpio->pddat |= (1 << 5); - gpio->pddat |= (1 << 6); - return 0; - } - else if (strcmp (argv[2], "-") == 0) { - gpio->pddat &= ~(1 << 5); - gpio->pddat |= (1 << 6); - return 0; - } - else if (strcmp (argv[2], "off") == 0) { - gpio->pddat &= ~(1 << 5); - gpio->pddat &= ~(1 << 6); - return 0; - } - printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); - return 1; -} - -/* val must be in [0, 4095] */ -static inline unsigned long tsc2000_to_uv (u16 val) -{ - return ((250000 * val) / 4096) * 10; -} - - -int do_dac (char * const *argv) -{ - int brightness; - - /* initialize SPI */ - tsc2000_spi_init (); - - if (((brightness = simple_strtoul (argv[2], NULL, 10)) < 0) || - (brightness > 255)) { - printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); - return 1; - } - tsc2000_write(TSC2000_REG_DACCTL, 0x0); /* Power up DAC */ - tsc2000_write(TSC2000_REG_DAC, brightness & 0xff); - - return 0; -} - - -int do_v_bat (void) -{ - unsigned long ret, res; - - /* initialize SPI */ - spi_init (); - - tsc2000_write(TSC2000_REG_ADC, 0x1836); - - /* now wait for data available */ - adc_wait_conversion_done(); - - ret = tsc2000_read(TSC2000_REG_BAT1); - res = (tsc2000_to_uv(ret) + 1250) / 2500; - res += (ERROR_BATTERY * res) / 1000; - - print_identifier (); - printf ("%ld", (res / 100)); - printf (".%ld", ((res % 100) / 10)); - printf ("%ld V\n", (res % 10)); - return 0; -} - - -int do_pressure (void) -{ - /* initialize SPI */ - spi_init (); - - tsc2000_write(TSC2000_REG_ADC, 0x2436); - - /* now wait for data available */ - adc_wait_conversion_done(); - - print_identifier (); - printf ("%d\n", tsc2000_read(TSC2000_REG_AUX2)); - return 0; -} - - -int do_motor_contact (void) -{ - int result; - - result = *CPLD_FILL_LEVEL; /* read CPLD */ - debug ("%s: cpld_fuellstand (32 bit) %#x\n", __FUNCTION__, result); - - /* print result to console */ - print_identifier (); - if ((result & (1 << 17)) == 0) - printf("0\n"); - else - printf("1\n"); - return 0; -} - -int do_motor (char * const *argv) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* Configure I/O port */ - gpio->pgcon &= ~(0x3 << 0); - gpio->pgcon |= (0x1 << 0); - - if (strcmp (argv[2], "on") == 0) { - gpio->pgdat &= ~(1 << 0); - return 0; - } - if (strcmp (argv[2], "off") == 0) { - gpio->pgdat |= (1 << 0); - return 0; - } - printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); - return 1; -} - -static void print_identifier (void) -{ - printf ("## FKT: "); -} - -int do_pwm (char * const *argv) -{ - int counter; - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - struct s3c24x0_timers * const timers = s3c24x0_get_base_timers(); - - if (strcmp (argv[2], "on") == 0) { - /* configure pin GPD8 as TOUT3 */ - gpio->pdcon &= ~(0x3 << 8*2); - gpio->pdcon |= (0x2 << 8*2); - - /* set prescaler for timer 2, 3 and 4 */ - timers->tcfg0 &= ~0xFF00; - timers->tcfg0 |= 0x0F00; - - /* set divider for timer 3 */ - timers->tcfg1 &= ~(0xf << 12); - timers->tcfg1 |= (0x3 << 12); - - /* set frequency */ - counter = (PCLK / PWM_FREQ) >> 9; - timers->ch[3].tcntb = counter; - timers->ch[3].tcmpb = counter / 2; - - /* start timer */ - timers->tcon = (timers->tcon | UPDATE3 | RELOAD3) & ~INVERT3; - timers->tcon = (timers->tcon | START3) & ~UPDATE3; - return 0; - } - if (strcmp (argv[2], "off") == 0) { - - /* stop timer */ - timers->tcon &= ~(START2 | RELOAD2); - - /* configure pin GPD8 as output and set to 0 */ - gpio->pdcon &= ~(0x3 << 8*2); - gpio->pdcon |= (0x1 << 8*2); - gpio->pddat &= ~(1 << 8); - return 0; - } - printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); - return 1; -} - - -int do_thermo (char * const *argv) -{ - int channel, res; - - tsc2000_reg_init (); - - if (strcmp (argv[2], "all") == 0) { - int i; - for (i=0; i <= 15; i++) { - res = tsc2000_read_channel(i); - print_identifier (); - printf ("c%d: %d\n", i, res); - } - return 0; - } - channel = simple_strtoul (argv[2], NULL, 10); - res = tsc2000_read_channel(channel); - print_identifier (); - printf ("%d\n", res); - return 0; /* return OK */ -} - - -int do_touch (char * const *argv) -{ - int x, y; - - if (strcmp (argv[2], "tl") == 0) { -#ifdef CONFIG_TOUCH_WAIT_PRESSED - touch_wait_pressed(); -#else - { - int i; - for (i = 0; i < (TOUCH_TIMEOUT * 1000); i++) { - if (touch_check_pressed ()) { - break; - } - udelay (1000); /* pause 1 ms */ - } - } - if (!touch_check_pressed()) { - print_identifier (); - printf ("error: touch not pressed\n"); - return 1; - } -#endif /* CONFIG_TOUCH_WAIT_PRESSED */ - touch_read_x_y (&x, &y); - - print_identifier (); - printf ("x=%d y=%d\n", x, y); - return touch_write_clibration_values (CALIB_TL, x, y); - } - else if (strcmp (argv[2], "dr") == 0) { -#ifdef CONFIG_TOUCH_WAIT_PRESSED - touch_wait_pressed(); -#else - { - int i; - for (i = 0; i < (TOUCH_TIMEOUT * 1000); i++) { - if (touch_check_pressed ()) { - break; - } - udelay (1000); /* pause 1 ms */ - } - } - if (!touch_check_pressed()) { - print_identifier (); - printf ("error: touch not pressed\n"); - return 1; - } -#endif /* CONFIG_TOUCH_WAIT_PRESSED */ - touch_read_x_y (&x, &y); - - print_identifier (); - printf ("x=%d y=%d\n", x, y); - - return touch_write_clibration_values (CALIB_DR, x, y); - } - return 1; /* not "tl", nor "dr", so return error */ -} - - -#ifdef CONFIG_TOUCH_WAIT_PRESSED -static void touch_wait_pressed (void) -{ - while (!(tsc2000_read(TSC2000_REG_ADC) & TC_PSM)); -} - -#else -static int touch_check_pressed (void) -{ - return (tsc2000_read(TSC2000_REG_ADC) & TC_PSM); -} -#endif /* CONFIG_TOUCH_WAIT_PRESSED */ - -static int touch_write_clibration_values (int calib_point, int x, int y) -{ -#if defined(CONFIG_CMD_I2C) - int x_verify = 0; - int y_verify = 0; - - tsc2000_reg_init (); - - if (calib_point == CALIB_TL) { - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X0, 1, - (unsigned char *)&x, 2)) { - return 1; - } - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y0, 1, - (unsigned char *)&y, 2)) { - return 1; - } - - /* verify written values */ - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X0, 1, - (unsigned char *)&x_verify, 2)) { - return 1; - } - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y0, 1, - (unsigned char *)&y_verify, 2)) { - return 1; - } - if ((y != y_verify) || (x != x_verify)) { - print_identifier (); - printf ("error: verify error\n"); - return 1; - } - return 0; /* no error */ - } - else if (calib_point == CALIB_DR) { - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X1, 1, - (unsigned char *)&x, 2)) { - return 1; - } - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y1, 1, - (unsigned char *)&y, 2)) { - return 1; - } - - /* verify written values */ - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X1, 1, - (unsigned char *)&x_verify, 2)) { - return 1; - } - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y1, 1, - (unsigned char *)&y_verify, 2)) { - return 1; - } - if ((y != y_verify) || (x != x_verify)) { - print_identifier (); - printf ("error: verify error\n"); - return 1; - } - return 0; - } - return 1; -#else - printf ("No I2C support enabled (CONFIG_CMD_I2C), could not write " - "to EEPROM\n"); - return (1); -#endif -} - - -static void touch_read_x_y (int *px, int *py) -{ - tsc2000_write(TSC2000_REG_ADC, DEFAULT_ADC | TC_AD0 | TC_AD1); - adc_wait_conversion_done(); - *px = tsc2000_read(TSC2000_REG_X); - - tsc2000_write(TSC2000_REG_ADC, DEFAULT_ADC | TC_AD2); - adc_wait_conversion_done(); - *py = tsc2000_read(TSC2000_REG_Y); -} - - -int do_rs485 (char * const *argv) -{ - int timeout; - char data[RS485_MAX_RECEIVE_BUF_LEN]; - - if (strcmp (argv[2], "send") == 0) { - return (rs485_send_line (argv[3])); - } - else if (strcmp (argv[2], "receive") == 0) { - timeout = simple_strtoul(argv[3], NULL, 10); - if (rs485_receive_chars (data, timeout) != 0) { - print_identifier (); - printf ("## nothing received\n"); - return (1); - } - else { - print_identifier (); - printf ("%s\n", data); - return (0); - } - } - printf ("%s: unknown command %s\n", __FUNCTION__, argv[2]); - return (1); /* unknown command, return error */ -} - - -static int rs485_send_line (const char *data) -{ - rs485_init (); - trab_rs485_enable_tx (); - rs485_puts (data); - rs485_putc ('\n'); - - return (0); -} - - -static int rs485_receive_chars (char *data, int timeout) -{ - int i; - int receive_count = 0; - - rs485_init (); - trab_rs485_enable_rx (); - - /* test every 1 ms for received characters to avoid a receive FIFO - * overrun (@ 38.400 Baud) */ - for (i = 0; i < (timeout * 1000); i++) { - while (rs485_tstc ()) { - if (receive_count >= RS485_MAX_RECEIVE_BUF_LEN-1) - break; - *data++ = rs485_getc (); - receive_count++; - } - udelay (1000); /* pause 1 ms */ - } - *data = '\0'; /* terminate string */ - - if (receive_count == 0) - return (1); - else - return (0); -} - - -int do_serial_number (char * const *argv) -{ -#if defined(CONFIG_CMD_I2C) - unsigned int serial_number; - - if (strcmp (argv[2], "read") == 0) { - if (i2c_read (I2C_EEPROM_DEV_ADDR, SERIAL_NUMBER, 1, - (unsigned char *)&serial_number, 4)) { - printf ("could not read from eeprom\n"); - return (1); - } - print_identifier (); - printf ("%08d\n", serial_number); - return (0); - } - else if (strcmp (argv[2], "write") == 0) { - serial_number = simple_strtoul(argv[3], NULL, 10); - if (i2c_write (I2C_EEPROM_DEV_ADDR, SERIAL_NUMBER, 1, - (unsigned char *)&serial_number, 4)) { - printf ("could not write to eeprom\n"); - return (1); - } - return (0); - } - printf ("%s: unknown command %s\n", __FUNCTION__, argv[2]); - return (1); /* unknown command, return error */ -#else - printf ("No I2C support enabled (CONFIG_CMD_I2C), could not write " - "to EEPROM\n"); - return (1); -#endif -} - - -int do_crc16 (void) -{ -#if defined(CONFIG_CMD_I2C) - int crc; - unsigned char buf[EEPROM_MAX_CRC_BUF]; - - if (i2c_read (I2C_EEPROM_DEV_ADDR, 0, 1, buf, 60)) { - printf ("could not read from eeprom\n"); - return (1); - } - crc = 0; /* start value of crc calculation */ - crc = updcrc (crc, buf, 60); - - print_identifier (); - printf ("crc16=%#04x\n", crc); - - if (i2c_write (I2C_EEPROM_DEV_ADDR, CRC16, 1, (unsigned char *)&crc, - sizeof (crc))) { - printf ("could not read from eeprom\n"); - return (1); - } - return (0); -#else - printf ("No I2C support enabled (CONFIG_CMD_I2C), could not write " - "to EEPROM\n"); - return (1); -#endif -} - - -/* - * Calculate, intelligently, the CRC of a dataset incrementally given a - * buffer full at a time. - * Initialize crc to 0 for XMODEM, -1 for CCITT. - * - * Usage: - * newcrc = updcrc( oldcrc, bufadr, buflen ) - * unsigned int oldcrc, buflen; - * char *bufadr; - * - * Compile with -DTEST to generate program that prints CRC of stdin to stdout. - * Compile with -DMAKETAB to print values for crctab to stdout - */ - - /* the CRC polynomial. This is used by XMODEM (almost CCITT). - * If you change P, you must change crctab[]'s initial value to what is - * printed by initcrctab() - */ -#define P 0x1021 - - /* number of bits in CRC: don't change it. */ -#define W 16 - - /* this the number of bits per char: don't change it. */ -#define B 8 - -static unsigned short crctab[1<<B] = { /* as calculated by initcrctab() */ - 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, - 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, - 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, - 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, - 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, - 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, - 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, - 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, - 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, - 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, - 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, - 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, - 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, - 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, - 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, - 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, - 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, - 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, - 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, - 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, - 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, - 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, - 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, - 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, - 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, - 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, - 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, - 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, - 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, - 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, - 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, - 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 - }; - -static unsigned short updcrc(unsigned short icrc, unsigned char *icp, - unsigned int icnt ) -{ - register unsigned short crc = icrc; - register unsigned char *cp = icp; - register unsigned int cnt = icnt; - - while (cnt--) - crc = (crc<<B) ^ crctab[(crc>>(W-B)) ^ *cp++]; - - return (crc); -} - - -int do_gain (char * const *argv) -{ - int range; - - range = simple_strtoul (argv[2], NULL, 10); - if ((range < 1) || (range > 3)) - { - printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); - return 1; - } - - tsc2000_set_range (range); - return (0); -} - - -int do_eeprom (char * const *argv) -{ -#if defined(CONFIG_CMD_I2C) - if (strcmp (argv[2], "read") == 0) { - return (trab_eeprom_read (argv)); - } - - else if (strcmp (argv[2], "write") == 0) { - return (trab_eeprom_write (argv)); - } - - printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); - return (1); -#else - printf ("No I2C support enabled (CONFIG_CMD_I2C), could not write " - "to EEPROM\n"); - return (1); -#endif -} - -#if defined(CONFIG_CMD_I2C) -static int trab_eeprom_read (char * const *argv) -{ - int i; - int len; - unsigned int addr; - long int value = 0; - uchar *buffer; - - buffer = (uchar *) &value; - addr = simple_strtoul (argv[3], NULL, 10); - addr &= 0xfff; - len = simple_strtoul (argv[4], NULL, 10); - if ((len < 1) || (len > 4)) { - printf ("%s: invalid parameter %s\n", __FUNCTION__, - argv[4]); - return (1); - } - for (i = 0; i < len; i++) { - if (i2c_read (I2C_EEPROM_DEV_ADDR, addr+i, 1, buffer+i, 1)) { - printf ("%s: could not read from i2c device %#x" - ", addr %d\n", __FUNCTION__, - I2C_EEPROM_DEV_ADDR, addr); - return (1); - } - } - print_identifier (); - if (strcmp (argv[5], "-") == 0) { - if (len == 1) - printf ("%d\n", (signed char) value); - else if (len == 2) - printf ("%d\n", (signed short int) value); - else - printf ("%ld\n", value); - } - else { - if (len == 1) - printf ("%d\n", (unsigned char) value); - else if (len == 2) - printf ("%d\n", (unsigned short int) value); - else - printf ("%ld\n", (unsigned long int) value); - } - return (0); -} - -static int trab_eeprom_write (char * const *argv) -{ - int i; - int len; - unsigned int addr; - long int value = 0; - uchar *buffer; - - buffer = (uchar *) &value; - addr = simple_strtoul (argv[3], NULL, 10); - addr &= 0xfff; - len = simple_strtoul (argv[4], NULL, 10); - if ((len < 1) || (len > 4)) { - printf ("%s: invalid parameter %s\n", __FUNCTION__, - argv[4]); - return (1); - } - value = simple_strtol (argv[5], NULL, 10); - debug ("value=%ld\n", value); - for (i = 0; i < len; i++) { - if (i2c_write (I2C_EEPROM_DEV_ADDR, addr+i, 1, buffer+i, 1)) { - printf ("%s: could not write to i2c device %d" - ", addr %d\n", __FUNCTION__, - I2C_EEPROM_DEV_ADDR, addr); - return (1); - } -#if 0 - printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i=" - "%#x+%d=%p=%#x \n",I2C_EEPROM_DEV_ADDR_DEV_ADDR , addr, - i, addr+i, 1, buffer, i, buffer+i, *(buffer+i)); -#endif - udelay (30000); /* wait for EEPROM ready */ - } - return (0); -} - -int i2c_write_multiple (uchar chip, uint addr, int alen, - uchar *buffer, int len) -{ - int i; - - if (alen != 1) { - printf ("%s: addr len other than 1 not supported\n", - __FUNCTION__); - return (1); - } - - for (i = 0; i < len; i++) { - if (i2c_write (chip, addr+i, alen, buffer+i, 1)) { - printf ("%s: could not write to i2c device %d" - ", addr %d\n", __FUNCTION__, chip, addr); - return (1); - } -#if 0 - printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i=" - "%#x+%d=%p=\"%.1s\"\n", chip, addr, i, addr+i, - alen, buffer, i, buffer+i, buffer+i); -#endif - - udelay (30000); - } - return (0); -} - -int i2c_read_multiple ( uchar chip, uint addr, int alen, - uchar *buffer, int len) -{ - int i; - - if (alen != 1) { - printf ("%s: addr len other than 1 not supported\n", - __FUNCTION__); - return (1); - } - - for (i = 0; i < len; i++) { - if (i2c_read (chip, addr+i, alen, buffer+i, 1)) { - printf ("%s: could not read from i2c device %#x" - ", addr %d\n", __FUNCTION__, chip, addr); - return (1); - } - } - return (0); -} -#endif diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c deleted file mode 100644 index 426ed9c..0000000 --- a/board/trab/tsc2000.c +++ /dev/null @@ -1,366 +0,0 @@ -/* - * Functions to access the TSC2000 controller on TRAB board (used for scanning - * thermo sensors) - * - * Copyright (C) 2003 Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * Copyright (C) 2002 DENX Software Engineering, Wolfgang Denk, wd@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/s3c24x0_cpu.h> -#include <asm/io.h> -#include <div64.h> -#include "tsc2000.h" - -#include "Pt1000_temp_data.h" - -/* helper function */ -#define abs(value) (((value) < 0) ? ((value)*-1) : (value)) - -/* - * Maximal allowed deviation between two immediate meassurments of an analog - * thermo channel. 1 DIGIT = 0.0276 °C. This is used to filter sporadic - * "jumps" in measurment. - */ -#define MAX_DEVIATION 18 /* unit: DIGITs of adc; 18 DIGIT = 0.5 °C */ - -void tsc2000_spi_init(void) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - struct s3c24x0_spi * const spi = s3c24x0_get_base_spi(); - int i; - - /* Configure I/O ports. */ - gpio->pdcon = (gpio->pdcon & 0xF3FFFF) | 0x040000; - gpio->pgcon = (gpio->pgcon & 0x0F3FFF) | 0x008000; - gpio->pgcon = (gpio->pgcon & 0x0CFFFF) | 0x020000; - gpio->pgcon = (gpio->pgcon & 0x03FFFF) | 0x080000; - - CLR_CS_TOUCH(); - - spi->ch[0].sppre = 0x1F; /* Baud-rate ca. 514kHz */ - spi->ch[0].sppin = 0x01; /* SPI-MOSI holds Level after last bit */ - spi->ch[0].spcon = 0x1A; /* Polling, Prescaler, Master, CPOL=0, - CPHA=1 */ - - /* Dummy byte ensures clock to be low. */ - for (i = 0; i < 10; i++) { - spi->ch[0].sptdat = 0xFF; - } - spi_wait_transmit_done(); -} - - -void spi_wait_transmit_done(void) -{ - struct s3c24x0_spi * const spi = s3c24x0_get_base_spi(); - - while (!(spi->ch[0].spsta & 0x01)) /* wait until transfer is done */ - ; -} - - -void tsc2000_write(unsigned short reg, unsigned short data) -{ - struct s3c24x0_spi * const spi = s3c24x0_get_base_spi(); - unsigned int command; - - SET_CS_TOUCH(); - command = reg; - spi->ch[0].sptdat = (command & 0xFF00) >> 8; - spi_wait_transmit_done(); - spi->ch[0].sptdat = (command & 0x00FF); - spi_wait_transmit_done(); - spi->ch[0].sptdat = (data & 0xFF00) >> 8; - spi_wait_transmit_done(); - spi->ch[0].sptdat = (data & 0x00FF); - spi_wait_transmit_done(); - - CLR_CS_TOUCH(); -} - - -unsigned short tsc2000_read (unsigned short reg) -{ - unsigned short command, data; - struct s3c24x0_spi * const spi = s3c24x0_get_base_spi(); - - SET_CS_TOUCH(); - command = 0x8000 | reg; - - spi->ch[0].sptdat = (command & 0xFF00) >> 8; - spi_wait_transmit_done(); - spi->ch[0].sptdat = (command & 0x00FF); - spi_wait_transmit_done(); - - spi->ch[0].sptdat = 0xFF; - spi_wait_transmit_done(); - data = spi->ch[0].sprdat; - spi->ch[0].sptdat = 0xFF; - spi_wait_transmit_done(); - - CLR_CS_TOUCH(); - return (spi->ch[0].sprdat & 0x0FF) | (data << 8); -} - - -void tsc2000_set_mux (unsigned int channel) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - CLR_MUX1_ENABLE; CLR_MUX2_ENABLE; - CLR_MUX3_ENABLE; CLR_MUX4_ENABLE; - switch (channel) { - case 0: - CLR_MUX0; CLR_MUX1; - SET_MUX1_ENABLE; - break; - case 1: - SET_MUX0; CLR_MUX1; - SET_MUX1_ENABLE; - break; - case 2: - CLR_MUX0; SET_MUX1; - SET_MUX1_ENABLE; - break; - case 3: - SET_MUX0; SET_MUX1; - SET_MUX1_ENABLE; - break; - case 4: - CLR_MUX0; CLR_MUX1; - SET_MUX2_ENABLE; - break; - case 5: - SET_MUX0; CLR_MUX1; - SET_MUX2_ENABLE; - break; - case 6: - CLR_MUX0; SET_MUX1; - SET_MUX2_ENABLE; - break; - case 7: - SET_MUX0; SET_MUX1; - SET_MUX2_ENABLE; - break; - case 8: - CLR_MUX0; CLR_MUX1; - SET_MUX3_ENABLE; - break; - case 9: - SET_MUX0; CLR_MUX1; - SET_MUX3_ENABLE; - break; - case 10: - CLR_MUX0; SET_MUX1; - SET_MUX3_ENABLE; - break; - case 11: - SET_MUX0; SET_MUX1; - SET_MUX3_ENABLE; - break; - case 12: - CLR_MUX0; CLR_MUX1; - SET_MUX4_ENABLE; - break; - case 13: - SET_MUX0; CLR_MUX1; - SET_MUX4_ENABLE; - break; - case 14: - CLR_MUX0; SET_MUX1; - SET_MUX4_ENABLE; - break; - case 15: - SET_MUX0; SET_MUX1; - SET_MUX4_ENABLE; - break; - default: - CLR_MUX0; CLR_MUX1; - } -} - - -void tsc2000_set_range (unsigned int range) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - switch (range) { - case 1: - CLR_SEL_TEMP_V_0; SET_SEL_TEMP_V_1; - CLR_SEL_TEMP_V_2; CLR_SEL_TEMP_V_3; - break; - case 2: - CLR_SEL_TEMP_V_0; CLR_SEL_TEMP_V_1; - CLR_SEL_TEMP_V_2; SET_SEL_TEMP_V_3; - break; - case 3: - SET_SEL_TEMP_V_0; CLR_SEL_TEMP_V_1; - SET_SEL_TEMP_V_2; CLR_SEL_TEMP_V_3; - break; - } -} - - -u16 tsc2000_read_channel (unsigned int channel) -{ - u16 res; - - tsc2000_set_mux(channel); - udelay(20 * TSC2000_DELAY_BASE); - - tsc2000_write(TSC2000_REG_ADC, 0x2036); - adc_wait_conversion_done (); - res = tsc2000_read(TSC2000_REG_AUX1); - return res; -} - - -s32 tsc2000_contact_temp (void) -{ - long adc_pt1000, offset; - long u_pt1000; - long contact_temp; - long temp1, temp2; - - tsc2000_reg_init (); - tsc2000_set_range (3); - - /* - * Because of sporadic "jumps" in the measured adc values every - * channel is read two times. If there is a significant difference - * between the two measurements, then print an error and do a third - * measurement, because it is very unlikely that a successive third - * measurement goes also wrong. - */ - temp1 = tsc2000_read_channel (14); - temp2 = tsc2000_read_channel (14); - if (abs(temp2 - temp1) < MAX_DEVIATION) - adc_pt1000 = temp2; - else { - printf ("%s: read adc value (channel 14) exceeded max allowed " - "deviation: %d * 0.0276 °C\n", - __FUNCTION__, MAX_DEVIATION); - printf ("adc value 1: %ld DIGITs\nadc value 2: %ld DIGITs\n", - temp1, temp2); - adc_pt1000 = tsc2000_read_channel (14); - printf ("use (third read) adc value: adc_pt1000 = " - "%ld DIGITs\n", adc_pt1000); - } - debug ("read channel 14 (pt1000 adc value): %ld\n", adc_pt1000); - - temp1 = tsc2000_read_channel (15); - temp2 = tsc2000_read_channel (15); - if (abs(temp2 - temp1) < MAX_DEVIATION) - offset = temp2; - else { - printf ("%s: read adc value (channel 15) exceeded max allowed " - "deviation: %d * 0.0276 °C\n", - __FUNCTION__, MAX_DEVIATION); - printf ("adc value 1: %ld DIGITs\nadc value 2: %ld DIGITs\n", - temp1, temp2); - offset = tsc2000_read_channel (15); - printf ("use (third read) adc value: offset = %ld DIGITs\n", - offset); - } - debug ("read channel 15 (offset): %ld\n", offset); - - /* - * Formula for calculating voltage drop on PT1000 resistor: u_pt1000 = - * x_range3 * (adc_raw - offset) / 10. Formula to calculate x_range3: - * x_range3 = (2500 * (1000000 + err_vref + err_amp3)) / (4095*6). The - * error correction Values err_vref and err_amp3 are assumed as 0 in - * u-boot, because this could cause only a very small error (< 1%). - */ - u_pt1000 = (101750 * (adc_pt1000 - offset)) / 10; - debug ("u_pt1000: %ld\n", u_pt1000); - - if (tsc2000_interpolate(u_pt1000, Pt1000_temp_table, - &contact_temp) == -1) { - printf ("%s: error interpolating PT1000 vlaue\n", - __FUNCTION__); - return (-1000); - } - debug ("contact_temp: %ld\n", contact_temp); - - return contact_temp; -} - - -void tsc2000_reg_init (void) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - tsc2000_write(TSC2000_REG_ADC, 0x2036); - tsc2000_write(TSC2000_REG_REF, 0x0011); - tsc2000_write(TSC2000_REG_DACCTL, 0x0000); - - CON_MUX0; - CON_MUX1; - - CON_MUX1_ENABLE; - CON_MUX2_ENABLE; - CON_MUX3_ENABLE; - CON_MUX4_ENABLE; - - CON_SEL_TEMP_V_0; - CON_SEL_TEMP_V_1; - CON_SEL_TEMP_V_2; - CON_SEL_TEMP_V_3; - - tsc2000_set_mux(0); - tsc2000_set_range(0); -} - - -int tsc2000_interpolate(long value, long data[][2], long *result) -{ - int i; - unsigned long long val; - - /* the data is sorted and the first element is upper - * limit so we can easily check for out-of-band values - */ - if (data[0][0] < value || data[1][0] > value) - return -1; - - i = 1; - while (data[i][0] < value) - i++; - - /* To prevent overflow we have to store the intermediate - result in 'long long'. - */ - - val = ((unsigned long long)(data[i][1] - data[i-1][1]) - * (unsigned long long)(value - data[i-1][0])); - do_div(val, (data[i][0] - data[i-1][0])); - *result = data[i-1][1] + val; - - return 0; -} - - -void adc_wait_conversion_done(void) -{ - while (!(tsc2000_read(TSC2000_REG_ADC) & (1 << 14))); -} diff --git a/board/trab/tsc2000.h b/board/trab/tsc2000.h deleted file mode 100644 index f3cecb9..0000000 --- a/board/trab/tsc2000.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Functions to access the TSC2000 controller on TRAB board (used for scanning - * thermo sensors) - * - * Copyright (C) 2003 Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * Copyright (C) 2002 DENX Software Engineering, Wolfgang Denk, wd@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TSC2000_H_ -#define _TSC2000_H_ - -/* temperature channel multiplexer definitions */ -#define CON_MUX0 (gpio->pccon = (gpio->pccon & 0x0FFFFFCFF) | 0x00000100) -#define CLR_MUX0 (gpio->pcdat &= 0x0FFEF) -#define SET_MUX0 (gpio->pcdat |= 0x00010) - -#define CON_MUX1 (gpio->pccon = (gpio->pccon & 0x0FFFFF3FF) | 0x00000400) -#define CLR_MUX1 (gpio->pcdat &= 0x0FFDF) -#define SET_MUX1 (gpio->pcdat |= 0x00020) - -#define CON_MUX1_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFFFCFFF) | 0x00001000) -#define CLR_MUX1_ENABLE (gpio->pcdat |= 0x00040) -#define SET_MUX1_ENABLE (gpio->pcdat &= 0x0FFBF) - -#define CON_MUX2_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFFF3FFF) | 0x00004000) -#define CLR_MUX2_ENABLE (gpio->pcdat |= 0x00080) -#define SET_MUX2_ENABLE (gpio->pcdat &= 0x0FF7F) - -#define CON_MUX3_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFFCFFFF) | 0x00010000) -#define CLR_MUX3_ENABLE (gpio->pcdat |= 0x00100) -#define SET_MUX3_ENABLE (gpio->pcdat &= 0x0FEFF) - -#define CON_MUX4_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFF3FFFF) | 0x00040000) -#define CLR_MUX4_ENABLE (gpio->pcdat |= 0x00200) -#define SET_MUX4_ENABLE (gpio->pcdat &= 0x0FDFF) - -#define CON_SEL_TEMP_V_0 (gpio->pccon = (gpio->pccon & 0x0FFCFFFFF) | \ - 0x00100000) -#define CLR_SEL_TEMP_V_0 (gpio->pcdat &= 0x0FBFF) -#define SET_SEL_TEMP_V_0 (gpio->pcdat |= 0x00400) - -#define CON_SEL_TEMP_V_1 (gpio->pccon = (gpio->pccon & 0x0FF3FFFFF) | \ - 0x00400000) -#define CLR_SEL_TEMP_V_1 (gpio->pcdat &= 0x0F7FF) -#define SET_SEL_TEMP_V_1 (gpio->pcdat |= 0x00800) - -#define CON_SEL_TEMP_V_2 (gpio->pccon = (gpio->pccon & 0x0FCFFFFFF) | \ - 0x01000000) -#define CLR_SEL_TEMP_V_2 (gpio->pcdat &= 0x0EFFF) -#define SET_SEL_TEMP_V_2 (gpio->pcdat |= 0x01000) - -#define CON_SEL_TEMP_V_3 (gpio->pccon = (gpio->pccon & 0x0F3FFFFFF) | \ - 0x04000000) -#define CLR_SEL_TEMP_V_3 (gpio->pcdat &= 0x0DFFF) -#define SET_SEL_TEMP_V_3 (gpio->pcdat |= 0x02000) - -/* TSC2000 register definition */ -#define TSC2000_REG_X ((0 << 11) | (0 << 5)) -#define TSC2000_REG_Y ((0 << 11) | (1 << 5)) -#define TSC2000_REG_Z1 ((0 << 11) | (2 << 5)) -#define TSC2000_REG_Z2 ((0 << 11) | (3 << 5)) -#define TSC2000_REG_BAT1 ((0 << 11) | (5 << 5)) -#define TSC2000_REG_BAT2 ((0 << 11) | (6 << 5)) -#define TSC2000_REG_AUX1 ((0 << 11) | (7 << 5)) -#define TSC2000_REG_AUX2 ((0 << 11) | (8 << 5)) -#define TSC2000_REG_TEMP1 ((0 << 11) | (9 << 5)) -#define TSC2000_REG_TEMP2 ((0 << 11) | (0xA << 5)) -#define TSC2000_REG_DAC ((0 << 11) | (0xB << 5)) -#define TSC2000_REG_ZERO ((0 << 11) | (0x10 << 5)) -#define TSC2000_REG_ADC ((1 << 11) | (0 << 5)) -#define TSC2000_REG_DACCTL ((1 << 11) | (2 << 5)) -#define TSC2000_REG_REF ((1 << 11) | (3 << 5)) -#define TSC2000_REG_RESET ((1 << 11) | (4 << 5)) -#define TSC2000_REG_CONFIG ((1 << 11) | (5 << 5)) - -/* bit definition of TSC2000 ADC register */ -#define TC_PSM (1 << 15) -#define TC_STS (1 << 14) -#define TC_AD3 (1 << 13) -#define TC_AD2 (1 << 12) -#define TC_AD1 (1 << 11) -#define TC_AD0 (1 << 10) -#define TC_RS1 (1 << 9) -#define TC_RS0 (1 << 8) -#define TC_AV1 (1 << 7) -#define TC_AV0 (1 << 6) -#define TC_CL1 (1 << 5) -#define TC_CL0 (1 << 4) -#define TC_PV2 (1 << 3) -#define TC_PV1 (1 << 2) -#define TC_PV0 (1 << 1) - -/* default value for TSC2000 ADC register for use with touch functions */ -#define DEFAULT_ADC (TC_PV1 | TC_AV0 | TC_AV1 | TC_RS0) - -#define TSC2000_DELAY_BASE 500 -#define TSC2000_NO_SENSOR -0x10000 - -#define ERROR_BATTERY 220 /* must be adjusted, if R68 is changed on TRAB */ - -void tsc2000_write(unsigned short, unsigned short); -unsigned short tsc2000_read (unsigned short); -u16 tsc2000_read_channel (unsigned int); -void tsc2000_set_mux (unsigned int); -void tsc2000_set_range (unsigned int); -void tsc2000_reg_init (void); -s32 tsc2000_contact_temp (void); -void spi_wait_transmit_done (void); -void tsc2000_spi_init(void); -int tsc2000_interpolate(long value, long data[][2], long *result); -void adc_wait_conversion_done(void); - - -static inline void SET_CS_TOUCH(void) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - gpio->pddat &= 0x5FF; -} - - -static inline void CLR_CS_TOUCH(void) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - gpio->pddat |= 0x200; -} - -#endif /* _TSC2000_H_ */ diff --git a/board/trab/vfd.c b/board/trab/vfd.c deleted file mode 100644 index 9a2b1ba..0000000 --- a/board/trab/vfd.c +++ /dev/null @@ -1,574 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering -- wd@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************/ -/* ** DEBUG SETTINGS */ -/************************************************************************/ - -/* #define DEBUG */ - -/************************************************************************/ -/* ** HEADER FILES */ -/************************************************************************/ - -#include <config.h> -#include <common.h> -#include <version.h> -#include <stdarg.h> -#include <linux/types.h> -#include <stdio_dev.h> -#include <asm/arch/s3c24x0_cpu.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_VFD - -/************************************************************************/ -/* ** CONFIG STUFF -- should be moved to board config file */ -/************************************************************************/ - -/************************************************************************/ - -#ifndef PAGE_SIZE -#define PAGE_SIZE 4096 -#endif - -#define ROT 0x09 -#define BLAU 0x0C -#define VIOLETT 0X0D - -/* MAGIC */ -#define FRAME_BUF_SIZE ((256*4*56)/8) -#define frame_buf_offs 4 - -/* defines for starting Timer3 as CPLD-Clk */ -#define START3 (1 << 16) -#define UPDATE3 (1 << 17) -#define INVERT3 (1 << 18) -#define RELOAD3 (1 << 19) - -/* CPLD-Register for controlling vfd-blank-signal */ -#define VFD_DISABLE (*(volatile uchar *)0x04038000=0x0000) -#define VFD_ENABLE (*(volatile uchar *)0x04038000=0x0001) - -/* Supported VFD Types */ -#define VFD_TYPE_T119C 1 /* Noritake T119C VFD */ -#define VFD_TYPE_MN11236 2 - -/*#define NEW_CPLD_CLK*/ - -int vfd_board_id; - -/* taken from armboot/common/vfd.c */ -unsigned long adr_vfd_table[112][18][2][4][2]; -unsigned char bit_vfd_table[112][18][2][4][2]; - -/* - * initialize the values for the VFD-grid-control in the framebuffer - */ -void init_grid_ctrl(void) -{ - ulong adr, grid_cycle; - unsigned int bit, display; - unsigned char temp, bit_nr; - - /* - * clear frame buffer (logical clear => set to "black") - */ - memset ((void *)(gd->fb_base), 0, FRAME_BUF_SIZE); - - switch (gd->vfd_type) { - case VFD_TYPE_T119C: - for (display=0; display<4; display++) { - for(grid_cycle=0; grid_cycle<56; grid_cycle++) { - bit = grid_cycle * 256 * 4 + - (grid_cycle + 200) * 4 + - frame_buf_offs + display; - /* wrap arround if offset (see manual S3C2400) */ - if (bit>=FRAME_BUF_SIZE*8) - bit = bit - (FRAME_BUF_SIZE * 8); - adr = gd->fb_base + (bit/32) * 4 + (3 - (bit%32) / 8); - bit_nr = bit % 8; - bit_nr = (bit_nr > 3) ? bit_nr-4 : bit_nr+4; - temp=(*(volatile unsigned char*)(adr)); - temp |= (1<<bit_nr); - (*(volatile unsigned char*)(adr))=temp; - - if(grid_cycle<55) - bit = grid_cycle*256*4+(grid_cycle+201)*4+frame_buf_offs+display; - else - bit = grid_cycle*256*4+200*4+frame_buf_offs+display-4; /* grid nr. 0 */ - /* wrap arround if offset (see manual S3C2400) */ - if (bit>=FRAME_BUF_SIZE*8) - bit = bit-(FRAME_BUF_SIZE*8); - adr = gd->fb_base+(bit/32)*4+(3-(bit%32)/8); - bit_nr = bit%8; - bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4; - temp=(*(volatile unsigned char*)(adr)); - temp |= (1<<bit_nr); - (*(volatile unsigned char*)(adr))=temp; - } - } - break; - case VFD_TYPE_MN11236: - for (display=0; display<4; display++) { - for (grid_cycle=0; grid_cycle<38; grid_cycle++) { - bit = grid_cycle * 256 * 4 + - (253 - grid_cycle) * 4 + - frame_buf_offs + display; - /* wrap arround if offset (see manual S3C2400) */ - if (bit>=FRAME_BUF_SIZE*8) - bit = bit - (FRAME_BUF_SIZE * 8); - adr = gd->fb_base + (bit/32) * 4 + (3 - (bit%32) / 8); - bit_nr = bit % 8; - bit_nr = (bit_nr > 3) ? bit_nr-4 : bit_nr+4; - temp=(*(volatile unsigned char*)(adr)); - temp |= (1<<bit_nr); - (*(volatile unsigned char*)(adr))=temp; - - if(grid_cycle<37) - bit = grid_cycle*256*4+(252-grid_cycle)*4+frame_buf_offs+display; - - /* wrap arround if offset (see manual S3C2400) */ - if (bit>=FRAME_BUF_SIZE*8) - bit = bit-(FRAME_BUF_SIZE*8); - adr = gd->fb_base+(bit/32)*4+(3-(bit%32)/8); - bit_nr = bit%8; - bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4; - temp=(*(volatile unsigned char*)(adr)); - temp |= (1<<bit_nr); - (*(volatile unsigned char*)(adr))=temp; - } - } - break; - default: - printf ("Warning: unknown display type\n"); - break; - } -} - -/* - *create translation table for getting easy the right position in the - *physical framebuffer for some x/y-coordinates of the VFDs - */ -void create_vfd_table(void) -{ - unsigned long vfd_table[112][18][2][4][2]; - unsigned int x, y, color, display, entry, pixel; - unsigned int x_abcdef = 0; - - switch (gd->vfd_type) { - case VFD_TYPE_T119C: - for(y=0; y<=17; y++) { /* Line */ - for(x=0; x<=111; x++) { /* Column */ - for(display=0; display <=3; display++) { - - /* Display 0 blue pixels */ - vfd_table[x][y][0][display][0] = - (x==0) ? y*16+display - : (x%4)*4+y*16+((x-1)/2)*1024+display; - /* Display 0 red pixels */ - vfd_table[x][y][1][display][0] = - (x==0) ? y*16+512+display - : (x%4)*4+y*16+((x-1)/2)*1024+512+display; - } - } - } - break; - case VFD_TYPE_MN11236: - for(y=0; y<=17; y++) { /* Line */ - for(x=0; x<=111; x++) { /* Column */ - for(display=0; display <=3; display++) { - - vfd_table[x][y][0][display][0]=0; - vfd_table[x][y][0][display][1]=0; - vfd_table[x][y][1][display][0]=0; - vfd_table[x][y][1][display][1]=0; - - switch (x%6) { - case 0: x_abcdef=0; break; /* a -> a */ - case 1: x_abcdef=2; break; /* b -> c */ - case 2: x_abcdef=4; break; /* c -> e */ - case 3: x_abcdef=5; break; /* d -> f */ - case 4: x_abcdef=3; break; /* e -> d */ - case 5: x_abcdef=1; break; /* f -> b */ - } - - /* blue pixels */ - vfd_table[x][y][0][display][0] = - (x>1) ? x_abcdef*4+((x-1)/3)*1024+y*48+display - : x_abcdef*4+ 0+y*48+display; - /* blue pixels */ - if (x>1 && (x-1)%3) - vfd_table[x][y][0][display][1] = x_abcdef*4+((x-1)/3+1)*1024+y*48+display; - - /* red pixels */ - vfd_table[x][y][1][display][0] = - (x>1) ? x_abcdef*4+24+((x-1)/3)*1024+y*48+display - : x_abcdef*4+24+ 0+y*48+display; - /* red pixels */ - if (x>1 && (x-1)%3) - vfd_table[x][y][1][display][1] = x_abcdef*4+24+((x-1)/3+1)*1024+y*48+display; - } - } - } - break; - default: - /* do nothing */ - return; - } - - /* - * Create table with entries for physical byte adresses and - * bit-number within the byte - * from table with bit-numbers within the total framebuffer - */ - for(y=0;y<18;y++) { - for(x=0;x<112;x++) { - for(color=0;color<2;color++) { - for(display=0;display<4;display++) { - for(entry=0;entry<2;entry++) { - unsigned long adr = gd->fb_base; - unsigned int bit_nr = 0; - - pixel = vfd_table[x][y][color][display][entry] + frame_buf_offs; - /* - * wrap arround if offset - * (see manual S3C2400) - */ - if (pixel>=FRAME_BUF_SIZE*8) - pixel = pixel-(FRAME_BUF_SIZE*8); - adr = gd->fb_base+(pixel/32)*4+(3-(pixel%32)/8); - bit_nr = pixel%8; - bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4; - - adr_vfd_table[x][y][color][display][entry] = adr; - bit_vfd_table[x][y][color][display][entry] = bit_nr; - } - } - } - } - } -} - -/* - * Set/clear pixel of the VFDs - */ -void set_vfd_pixel(unsigned char x, unsigned char y, - unsigned char color, unsigned char display, - unsigned char value) -{ - ulong adr; - unsigned char bit_nr, temp; - - if (! gd->vfd_type) { - /* Unknown type. */ - return; - } - - /* Pixel-Eintrag Nr. 1 */ - adr = adr_vfd_table[x][y][color][display][0]; - /* Pixel-Eintrag Nr. 1 */ - bit_nr = bit_vfd_table[x][y][color][display][0]; - temp=(*(volatile unsigned char*)(adr)); - - if (value) - temp |= (1<<bit_nr); - else - temp &= ~(1<<bit_nr); - - (*(volatile unsigned char*)(adr))=temp; -} - -/* - * transfer image from BMP-File - */ -void transfer_pic(int display, unsigned char *adr, int height, int width) -{ - int x, y; - unsigned char temp; - - for (; height > 0; height -= 18) - { - if (height > 18) - y = 18; - else - y = height; - for (; y > 0; y--) - { - for (x = 0; x < width; x += 2) - { - temp = *adr++; - set_vfd_pixel(x, y-1, 0, display, 0); - set_vfd_pixel(x, y-1, 1, display, 0); - if ((temp >> 4) == BLAU) - set_vfd_pixel(x, y-1, 0, display, 1); - else if ((temp >> 4) == ROT) - set_vfd_pixel(x, y-1, 1, display, 1); - else if ((temp >> 4) == VIOLETT) - { - set_vfd_pixel(x, y-1, 0, display, 1); - set_vfd_pixel(x, y-1, 1, display, 1); - } - set_vfd_pixel(x+1, y-1, 0, display, 0); - set_vfd_pixel(x+1, y-1, 1, display, 0); - if ((temp & 0x0F) == BLAU) - set_vfd_pixel(x+1, y-1, 0, display, 1); - else if ((temp & 0x0F) == ROT) - set_vfd_pixel(x+1, y-1, 1, display, 1); - else if ((temp & 0x0F) == VIOLETT) - { - set_vfd_pixel(x+1, y-1, 0, display, 1); - set_vfd_pixel(x+1, y-1, 1, display, 1); - } - } - } - if (display > 0) - display--; - else - display = 3; - } -} - -/* - * This function initializes VFD clock that is needed for the CPLD that - * manages the keyboard. - */ -int vfd_init_clocks (void) -{ - int i; - - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - struct s3c24x0_timers * const timers = s3c24x0_get_base_timers(); - struct s3c24x0_lcd * const lcd = s3c24x0_get_base_lcd(); - - /* try to determine display type from the value - * defined by pull-ups - */ - gpio->pcup = (gpio->pcup & 0xFFF0); /* activate GPC0...GPC3 pullups */ - gpio->pccon = (gpio->pccon & 0xFFFFFF00); /* cfg GPC0...GPC3 inputs */ - /* allow signals to settle */ - for (i=0; i<10000; i++) /* udelay isn't working yet at this point! */ - __asm__("NOP"); - vfd_board_id = (~gpio->pcdat) & 0x000F; /* read GPC0...GPC3 port pins */ - - VFD_DISABLE; /* activate blank for the vfd */ - -#define NEW_CPLD_CLK - -#ifdef NEW_CPLD_CLK - if (vfd_board_id) { - /* If new board revision, then use PWM 3 as cpld-clock */ - /* Enable 500 Hz timer for fill level sensor to operate properly */ - /* Configure TOUT3 as functional pin, disable pull-up */ - gpio->pdcon &= ~0x30000; - gpio->pdcon |= 0x20000; - gpio->pdup |= (1 << 8); - - /* Configure the prescaler */ - timers->tcfg0 &= ~0xff00; - timers->tcfg0 |= 0x0f00; - - /* Select MUX input (divider) for timer3 (1/16) */ - timers->tcfg1 &= ~0xf000; - timers->tcfg1 |= 0x3000; - - /* Enable autoreload and set the counter and compare - * registers to values for the 500 Hz clock - * (for a given prescaler (15) and divider (16)): - * counter = (66000000 / 500) >> 9; - */ - timers->ch[3].tcntb = 0x101; - timers->ch[3].tcmpb = 0x101 / 2; - - /* Start timer */ - timers->tcon = (timers->tcon | UPDATE3 | RELOAD3) & ~INVERT3; - timers->tcon = (timers->tcon | START3) & ~UPDATE3; - } -#endif - /* If old board revision, then use vm-signal as cpld-clock */ - lcd->lcdcon2 = 0x00FFC000; - lcd->lcdcon3 = 0x0007FF00; - lcd->lcdcon4 = 0x00000000; - lcd->lcdcon5 = 0x00000400; - lcd->lcdcon1 = 0x00000B75; - /* VM (GPD1) is used as clock for the CPLD */ - gpio->pdcon = (gpio->pdcon & 0xFFFFFFF3) | 0x00000008; - - return 0; -} - -/* - * initialize LCD-Controller of the S3C2400 for using VFDs - * - * VFD detection depends on the board revision: - * starting from Rev. 200 a type code can be read from the data pins, - * driven by some pull-up resistors; all earlier systems must be - * manually configured. The type is set in the "vfd_type" environment - * variable. - */ -int drv_vfd_init(void) -{ - struct s3c24x0_lcd * const lcd = s3c24x0_get_base_lcd(); - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - char *tmp; - ulong palette; - static int vfd_init_done = 0; - int vfd_inv_data = 0; - - if (vfd_init_done != 0) - return (0); - vfd_init_done = 1; - - debug("Detecting Revison of WA4-VFD: ID=0x%X\n", vfd_board_id); - - switch (vfd_board_id) { - case 0: /* board revision < Rev.200 */ - if ((tmp = getenv ("vfd_type")) == NULL) { - break; - } - if (strcmp(tmp, "T119C") == 0) { - gd->vfd_type = VFD_TYPE_T119C; - } else if (strcmp(tmp, "MN11236") == 0) { - gd->vfd_type = VFD_TYPE_MN11236; - } else { - /* cannot use printf for a warning here */ - gd->vfd_type = 0; /* unknown */ - } - - break; - default: /* default to MN11236, data inverted */ - gd->vfd_type = VFD_TYPE_MN11236; - vfd_inv_data = 1; - setenv ("vfd_type", "MN11236"); - } - debug ("VFD type: %s%s\n", - (gd->vfd_type == VFD_TYPE_T119C) ? "T119C" : - (gd->vfd_type == VFD_TYPE_MN11236) ? "MN11236" : - "unknown", - vfd_inv_data ? ", inverted data" : ""); - - gd->fb_base = gd->fb_base; - create_vfd_table(); - init_grid_ctrl(); - - for (palette=0; palette < 16; palette++) - (*(volatile unsigned int*)(PALETTE+(palette*4)))=palette; - for (palette=16; palette < 256; palette++) - (*(volatile unsigned int*)(PALETTE+(palette*4)))=0x00; - - /* - * Hinweis: Der Framebuffer ist um genau ein Nibble verschoben - * Das erste angezeigte Pixel wird aus dem zweiten Nibble geholt - * das letzte angezeigte Pixel wird aus dem ersten Nibble geholt - * (wrap around) - * see manual S3C2400 - */ - /* Stopp LCD-Controller */ - lcd->lcdcon1 = 0x00000000; - /* frame buffer startadr */ - lcd->lcdsaddr1 = gd->fb_base >> 1; - /* frame buffer endadr */ - lcd->lcdsaddr2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1; - lcd->lcdsaddr3 = ((256/4)); - lcd->lcdcon2 = 0x000DC000; - if(gd->vfd_type == VFD_TYPE_MN11236) - lcd->lcdcon2 = 37 << 14; /* MN11236: 38 lines */ - else - lcd->lcdcon2 = 55 << 14; /* T119C: 56 lines */ - lcd->lcdcon3 = 0x0051000A; - lcd->lcdcon4 = 0x00000001; - if (gd->vfd_type && vfd_inv_data) - lcd->lcdcon5 = 0x000004C0; - else - lcd->lcdcon5 = 0x00000440; - - /* Port pins as LCD output */ - gpio->pccon = (gpio->pccon & 0xFFFFFF00) | 0x000000AA; - gpio->pdcon = (gpio->pdcon & 0xFFFFFF03) | 0x000000A8; - - /* Synchronize VFD enable with LCD controller to avoid flicker */ - lcd->lcdcon1 = 0x00000B75; /* Start LCD-Controller */ - while ((lcd->lcdcon5 & 0x180000) != 0x100000) /* Wait for VSYNC end */ - ; - while ((lcd->lcdcon5 & 0x060000) != 0x040000) /* Wait for next HSYNC */ - ; - while ((lcd->lcdcon5 & 0x060000) == 0x040000) - ; - while ((lcd->lcdcon5 & 0x060000) != 0x000000) - ; - if(gd->vfd_type) - VFD_ENABLE; - - debug("LCDSADDR1: %lX\n", lcd->lcdsaddr1); - debug("LCDSADDR2: %lX\n", lcd->lcdsaddr2); - debug("LCDSADDR3: %lX\n", lcd->lcdsaddr3); - - return 0; -} - -/* - * Disable VFD: should be run before resetting the system: - * disable VM, enable pull-up - */ -void disable_vfd (void) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - VFD_DISABLE; - gpio->pdcon &= ~0xC; - gpio->pdup &= ~0x2; -} - -/************************************************************************/ -/* ** ROM capable initialization part - needed to reserve FB memory */ -/************************************************************************/ - -/* - * This is called early in the system initialization to grab memory - * for the VFD controller. - * - * Note that this is running from ROM, so no write access to global data. - */ -ulong vfd_setmem (ulong addr) -{ - ulong size; - - /* Round up to nearest full page */ - size = (FRAME_BUF_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); - - debug ("Reserving %ldk for VFD Framebuffer at: %08lx\n", size>>10, addr); - - return (size); -} - -/* - * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb, - * descriptors and palette areas. - */ -ulong calc_fbsize (void) -{ - return FRAME_BUF_SIZE; -} - -#endif /* CONFIG_VFD */ diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c index 8e6ad74..565c4d0 100644 --- a/board/ttcontrol/vision2/vision2.c +++ b/board/ttcontrol/vision2/vision2.c @@ -169,11 +169,11 @@ static void setup_weim(void) { struct weim *pweim = (struct weim *)WEIM_BASE_ADDR; - pweim->csgcr1 = 0x004100b9; - pweim->csgcr2 = 0x00000001; - pweim->csrcr1 = 0x0a018000; - pweim->csrcr2 = 0; - pweim->cswcr1 = 0x0704a240; + pweim->cs0gcr1 = 0x004100b9; + pweim->cs0gcr2 = 0x00000001; + pweim->cs0rcr1 = 0x0a018000; + pweim->cs0rcr2 = 0; + pweim->cs0wcr1 = 0x0704a240; } static void setup_uart(void) diff --git a/board/xaeniax/flash.c b/board/xaeniax/flash.c index b051c89..6cb0aca 100644 --- a/board/xaeniax/flash.c +++ b/board/xaeniax/flash.c @@ -221,7 +221,7 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) int flash_erase (flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -254,9 +254,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - start = get_timer (0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -269,14 +266,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); *addr = (FPW) 0x00500050; /* clear status register */ *addr = (FPW) 0x00200020; /* erase setup */ *addr = (FPW) 0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -393,6 +390,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) FPWV *addr = (FPWV *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -406,11 +404,11 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c index 3b6e08b..8031a34 100644 --- a/board/xes/xpedite550x/ddr.c +++ b/board/xes/xpedite550x/ddr.c @@ -125,10 +125,16 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->clk_adjust = pbsp->clk_adjust; popts->cpo_override = pbsp->cpo; popts->twoT_en = 0; + break; } pbsp++; } + if (i == num_params) { + printf("Warning: board specific timing not found " + "for data rate %lu MT/s!\n", ddr_freq); + } + /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed diff --git a/board/xm250/flash.c b/board/xm250/flash.c index b02149c..e825aba 100644 --- a/board/xm250/flash.c +++ b/board/xm250/flash.c @@ -250,7 +250,7 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) int flash_erase (flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -283,9 +283,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - start = get_timer (0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -298,14 +295,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); *addr = (FPW) 0x00500050; /* clear status register */ *addr = (FPW) 0x00200020; /* erase setup */ *addr = (FPW) 0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -422,6 +419,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) FPWV *addr = (FPWV *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -435,11 +433,11 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } @@ -470,6 +468,7 @@ int flash_real_protect(flash_info_t *info, long sector, int prot) int rc = 0; vu_long *addr = (vu_long *)(info->start[sector]); int flag = disable_interrupts(); + ulong start; *addr = INTEL_CLEAR; /* Clear status register */ if (prot) { /* Set sector lock bit */ @@ -481,10 +480,10 @@ int flash_real_protect(flash_info_t *info, long sector, int prot) *addr = INTEL_CONFIRM; /* clear */ } - reset_timer_masked (); + start = get_timer(0); while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) { printf("Flash lock bit operation timed out\n"); rc = 1; break; @@ -510,13 +509,13 @@ int flash_real_protect(flash_info_t *info, long sector, int prot) { if (info->protect[i]) { - reset_timer_masked (); + start = get_timer(0); addr = (vu_long *)(info->start[i]); *addr = INTEL_LOCKBIT; /* Sector lock bit */ *addr = INTEL_PROTECT; /* set */ while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) { printf("Flash lock bit operation timed out\n"); rc = 1; diff --git a/board/zylonite/flash.c b/board/zylonite/flash.c index 5ba84c6..3ee0ab8 100644 --- a/board/zylonite/flash.c +++ b/board/zylonite/flash.c @@ -224,7 +224,7 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) int flash_erase (flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -257,9 +257,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - start = get_timer (0); - last = start; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -272,14 +269,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("Erasing sector %2d ... ", sect); /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); *addr = (FPW) 0x00500050; /* clear status register */ *addr = (FPW) 0x00200020; /* erase setup */ *addr = (FPW) 0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -396,6 +393,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) FPWV *addr = (FPWV *) dest; ulong status; int flag; + ulong start; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -409,11 +407,11 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) *addr = data; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); + start = get_timer(0); /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } @@ -71,9 +71,34 @@ smdk2410 arm arm920t - samsung netstar arm arm925t voiceblue arm arm925t omap1510inn arm arm925t - ti +versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU +versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB +versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB aspenite arm arm926ejs - Marvell armada100 afeb9260 arm arm926ejs - - at91 at91cap9adk arm arm926ejs - atmel at91 +at91sam9260ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH +at91sam9260ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0 +at91sam9260ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1 +at91sam9261ek_nandflash arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9261,SYS_USE_NANDFLASH +at91sam9261ek_dataflash_cs0 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS0 +at91sam9261ek_dataflash_cs3 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS3 +at91sam9263ek_nandflash arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_NANDFLASH +at91sam9263ek_dataflash_cs0 arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH +at91sam9263ek_dataflash arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH +at91sam9263ek_norflash arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_NORFLASH +at91sam9263ek_norflash_boot arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_BOOT_NORFLASH +at91sam9g10ek_nandflash arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9G10,SYS_USE_NANDFLASH +at91sam9g10ek_dataflash_cs0 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS0 +at91sam9g10ek_dataflash_cs3 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS3 +at91sam9g20ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH +at91sam9g20ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0 +at91sam9g20ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1 +at91sam9rlek_nandflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH +at91sam9rlek_dataflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH +at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH +at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0 +at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260 snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20 cpu9260 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260 @@ -106,9 +131,13 @@ davinci_dvevm arm arm926ejs dvevm davinci davinci_schmoogie arm arm926ejs schmoogie davinci davinci davinci_sffsdr arm arm926ejs sffsdr davinci davinci davinci_sonata arm arm926ejs sonata davinci davinci -suen3 arm arm926ejs km_arm keymile kirkwood -suen8 arm arm926ejs km_arm keymile kirkwood +km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_DISABLE_PCI +km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood mgcoge3un arm arm926ejs km_arm keymile kirkwood +portl2 arm arm926ejs km_arm keymile kirkwood +inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood netspace_v2:INETSPACE_V2 +netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood netspace_v2:NETSPACE_V2 +netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood netspace_v2:NETSPACE_MAX_V2 guruplug arm arm926ejs - Marvell kirkwood mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood openrd_base arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE @@ -118,6 +147,7 @@ rd6281a arm arm926ejs - Marvell sheevaplug arm arm926ejs - Marvell kirkwood dockstar arm arm926ejs - Seagate kirkwood jadecpu arm arm926ejs jadecpu syteco mb86r0x +zmx25 arm arm926ejs zmx25 syteco mx25 imx27lite arm arm926ejs imx27lite logicpd mx27 magnesium arm arm926ejs imx27lite logicpd mx27 nhk8815 arm arm926ejs nhk8815 st nomadik @@ -126,8 +156,9 @@ omap5912osk arm arm926ejs - ti edminiv2 arm arm926ejs - LaCie orion5x dkb arm arm926ejs - Marvell pantheon ca9x4_ct_vxp arm armv7 vexpress armltd -efikamx arm armv7 efikamx - mx5 mx51evk:IMX_CONFIG=board/efikamx/imximage.cfg +efikamx arm armv7 efikamx - mx5 efikamx:IMX_CONFIG=board/efikamx/imximage.cfg mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg +mx53ard arm armv7 mx53ard freescale mx5 mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg mx53loco arm armv7 mx53loco freescale mx5 mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg mx53smd arm armv7 mx53smd freescale mx5 mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg @@ -155,12 +186,16 @@ smdkv310 arm armv7 smdkv310 samsung s5pc2xx harmony arm armv7 harmony nvidia tegra2 seaboard arm armv7 seaboard nvidia tegra2 u8500_href arm armv7 u8500 st-ericsson u8500 -actux1 arm ixp +actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 +actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 +actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB +actux1_8_32 arm ixp actux1 - - actux1:FLASH1X8,RAM_32MB actux2 arm ixp actux3 arm ixp actux4 arm ixp +dvlhost arm ixp ixdp425 arm ixp -ixdpg425 arm ixp +ixdpg425 arm ixp ixdp425 lpd7a400 arm lh7a40x lpd7a40x lpd7a404 arm lh7a40x lpd7a40x balloon3 arm pxa @@ -196,6 +231,7 @@ atstk1003 avr32 at32ap atstk1000 atmel atstk1004 avr32 at32ap atstk1000 atmel at32ap700x atstk1006 avr32 at32ap atstk1000 atmel at32ap700x favr-32-ezkit avr32 at32ap - earthlcd at32ap700x +grasshopper avr32 at32ap - in-circuit at32ap700x mimc200 avr32 at32ap - mimc at32ap700x hammerhead avr32 at32ap - miromico at32ap700x bct-brettl2 blackfin blackfin @@ -270,6 +306,7 @@ vct_platinumavc mips mips32 vct microna vct_platinumavc_small mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND vct_platinumavc_onenand_small mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE +nios2-generic nios2 nios2 nios2-generic altera PCI5441 nios2 nios2 pci5441 psyent PK1C20 nios2 nios2 pk1c20 psyent EVB64260 powerpc 74xx_7xx evb64260 - - EVB64260 @@ -298,10 +335,10 @@ a4m072 powerpc mpc5xxx a4m072 BC3450 powerpc mpc5xxx bc3450 canmb powerpc mpc5xxx cm5200 powerpc mpc5xxx -digsy_mtc powerpc mpc5xxx digsy_mtc -digsy_mtc_RAMBOOT powerpc mpc5xxx digsy_mtc - - digsy_mtc:SYS_TEXT_BASE=0x00100000 -digsy_mtc_rev5 powerpc mpc5xxx digsy_mtc - - digsy_mtc:DIGSY_REV5 -digsy_mtc_rev5_RAMBOOT powerpc mpc5xxx digsy_mtc - - digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5 +digsy_mtc powerpc mpc5xxx digsy_mtc intercontrol +digsy_mtc_RAMBOOT powerpc mpc5xxx digsy_mtc intercontrol - digsy_mtc:SYS_TEXT_BASE=0x00100000 +digsy_mtc_rev5 powerpc mpc5xxx digsy_mtc intercontrol - digsy_mtc:DIGSY_REV5 +digsy_mtc_rev5_RAMBOOT powerpc mpc5xxx digsy_mtc intercontrol - digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5 galaxy5200 powerpc mpc5xxx galaxy5200 - - galaxy5200:galaxy5200 galaxy5200_LOWBOOT powerpc mpc5xxx galaxy5200 - - galaxy5200:galaxy5200_LOWBOOT icecube_5200 powerpc mpc5xxx icecube - - IceCube @@ -499,6 +536,7 @@ MPC837XEMDS powerpc mpc83xx mpc837xemds freesca MPC837XEMDS_HOST powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS:PCI MPC837XERDB powerpc mpc83xx mpc837xerdb freescale kmeter1 powerpc mpc83xx km83xx keymile +MERGERBOX powerpc mpc83xx mergerbox matrix_vision MVBLM7 powerpc mpc83xx mvblm7 matrix_vision SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP @@ -556,6 +594,8 @@ P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freesca P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SPIFLASH P1022DS powerpc mpc85xx p1022ds freescale P1022DS_36BIT powerpc mpc85xx p1022ds freescale - P1022DS:36BIT +P1023RDS powerpc mpc85xx p1023rds freescale - P1023RDS +P1023RDS_NAND powerpc mpc85xx p1023rds freescale - P1023RDS:NAND P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB P2010RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT P2010RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SDCARD @@ -575,13 +615,18 @@ P2020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freesca P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,NAND P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH +P2041RDB powerpc mpc85xx p2041rdb freescale +P2041RDB_SDCARD powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 +P2041RDB_SPIFLASH powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P3041DS powerpc mpc85xx corenet_ds freescale +P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P4080DS powerpc mpc85xx corenet_ds freescale P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P5020DS powerpc mpc85xx corenet_ds freescale +P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 mpq101 powerpc mpc85xx mpq101 mercury - mpq101 @@ -810,9 +855,6 @@ icon powerpc ppc4xx - mosaixt MIP405 powerpc ppc4xx mip405 mpl MIP405T powerpc ppc4xx mip405 mpl - MIP405:MIP405T PIP405 powerpc ppc4xx pip405 mpl -hcu4 powerpc ppc4xx hcu4 netstal -hcu5 powerpc ppc4xx hcu5 netstal -mcu25 powerpc ppc4xx mcu25 netstal alpr powerpc ppc4xx - prodrive p3p440 powerpc ppc4xx - prodrive KAREF powerpc ppc4xx karef sandburst diff --git a/common/Makefile b/common/Makefile index f81cff9..d662468 100644 --- a/common/Makefile +++ b/common/Makefile @@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk LIB = $(obj)libcommon.o # core +ifndef CONFIG_SPL_BUILD COBJS-y += main.o -COBJS-y += console.o COBJS-y += command.o COBJS-y += dlmalloc.o COBJS-y += exports.o COBJS-$(CONFIG_SYS_HUSH_PARSER) += hush.o COBJS-y += image.o -COBJS-y += memsize.o COBJS-y += s_record.o COBJS-$(CONFIG_SERIAL_MULTI) += serial.o -COBJS-y += stdio.o COBJS-y += xyzModem.o # core command @@ -94,6 +92,7 @@ COBJS-$(CONFIG_CMD_FAT) += cmd_fat.o COBJS-$(CONFIG_CMD_FDC)$(CONFIG_CMD_FDOS) += cmd_fdc.o COBJS-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o COBJS-$(CONFIG_CMD_FDOS) += cmd_fdos.o +COBJS-$(CONFIG_CMD_FITUPD) += cmd_fitupd.o COBJS-$(CONFIG_CMD_FLASH) += cmd_flash.o ifdef CONFIG_FPGA COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o @@ -160,7 +159,6 @@ COBJS-$(CONFIG_USB_STORAGE) += usb_storage.o endif COBJS-$(CONFIG_CMD_XIMG) += cmd_ximg.o COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o -COBJS-$(CONFIG_VFD) += cmd_vfd.o # others COBJS-$(CONFIG_DDR_SPD) += ddr_spd.o @@ -174,6 +172,11 @@ COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o COBJS-$(CONFIG_MODEM_SUPPORT) += modem.o COBJS-$(CONFIG_UPDATE_TFTP) += update.o COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o +endif + +COBJS-y += console.o +COBJS-y += memsize.o +COBJS-y += stdio.o COBJS := $(sort $(COBJS-y)) diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 75924f8..6051120 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -345,7 +345,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("ip_addr = %pI4\n", &bd->bi_ip_addr); #endif printf("baudrate = %d bps\n", bd->bi_baudrate); -#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) print_num("TLB addr", gd->tlb_addr); #endif print_num("relocaddr", gd->relocaddr); diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 1966da4..272d879 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -708,6 +708,21 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; } +int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd) +{ + const char *ep = getenv("autostart"); + + if (ep && !strcmp(ep, "yes")) { + char *local_args[2]; + local_args[0] = (char *)cmd; + local_args[1] = NULL; + printf("Automatic boot of image at addr 0x%08lX ...\n", load_addr); + return do_bootm(cmdtp, 0, 1, local_args); + } + + return 0; +} + /** * image_get_kernel - verify legacy format kernel image * @img_addr: in RAM address of the legacy format image to be verified diff --git a/common/cmd_cache.c b/common/cmd_cache.c index 5cdd834..9778d3b 100644 --- a/common/cmd_cache.c +++ b/common/cmd_cache.c @@ -26,18 +26,27 @@ */ #include <common.h> #include <command.h> +#include <linux/compiler.h> -static int on_off (const char *); +static int parse_argv(const char *); + +void __weak flush_icache(void) +{ + /* please define arch specific flush_icache */ + puts("No arch specific flush_icache available!\n"); +} int do_icache ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { switch (argc) { case 2: /* on / off */ - switch (on_off(argv[1])) { + switch (parse_argv(argv[1])) { case 0: icache_disable(); break; case 1: icache_enable (); break; + case 2: flush_icache(); + break; } /* FALL TROUGH */ case 1: /* get status */ @@ -50,15 +59,23 @@ int do_icache ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +void __weak flush_dcache(void) +{ + puts("No arch specific flush_dcache available!\n"); + /* please define arch specific flush_dcache */ +} + int do_dcache ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { switch (argc) { case 2: /* on / off */ - switch (on_off(argv[1])) { + switch (parse_argv(argv[1])) { case 0: dcache_disable(); break; case 1: dcache_enable (); break; + case 2: flush_dcache(); + break; } /* FALL TROUGH */ case 1: /* get status */ @@ -72,9 +89,11 @@ int do_dcache ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } -static int on_off (const char *s) +static int parse_argv(const char *s) { - if (strcmp(s, "on") == 0) { + if (strcmp(s, "flush") == 0) { + return (2); + } else if (strcmp(s, "on") == 0) { return (1); } else if (strcmp(s, "off") == 0) { return (0); @@ -86,13 +105,13 @@ static int on_off (const char *s) U_BOOT_CMD( icache, 2, 1, do_icache, "enable or disable instruction cache", - "[on, off]\n" - " - enable or disable instruction cache" + "[on, off, flush]\n" + " - enable, disable, or flush instruction cache" ); U_BOOT_CMD( dcache, 2, 1, do_dcache, "enable or disable data cache", - "[on, off]\n" - " - enable or disable data (writethrough) cache" + "[on, off, flush]\n" + " - enable, disable, or flush data (writethrough) cache" ); diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c index 9f4b22c..e911377 100644 --- a/common/cmd_eeprom.c +++ b/common/cmd_eeprom.c @@ -250,7 +250,7 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn /* * For a FRAM device there is no limit on the number of the - * bytes that can be ccessed with the single read or write + * bytes that can be accessed with the single read or write * operation. */ #if !defined(CONFIG_SYS_I2C_FRAM) diff --git a/common/cmd_fdc.c b/common/cmd_fdc.c index cdb050c..40d12f6 100644 --- a/common/cmd_fdc.c +++ b/common/cmd_fdc.c @@ -721,8 +721,6 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) image_header_t *hdr; /* used for fdc boot */ unsigned char boot_drive; int i,nrofblk; - char *ep; - int rcode = 0; #if defined(CONFIG_FIT) const void *fit_hdr = NULL; #endif @@ -823,19 +821,7 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* Loading ok, update default load address */ load_addr = addr; - /* Check if we should attempt an auto-start */ - if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { - char *local_args[2]; - - local_args[0] = argv[0]; - local_args[1] = NULL; - - printf ("Automatic boot of image at addr 0x%08lX ...\n", addr); - - do_bootm (cmdtp, 0, 1, local_args); - rcode ++; - } - return rcode; + return bootm_maybe_autostart(cmdtp, argv[0]); } U_BOOT_CMD( diff --git a/common/cmd_fdos.c b/common/cmd_fdos.c index 2af4ca0..d714af8 100644 --- a/common/cmd_fdos.c +++ b/common/cmd_fdos.c @@ -40,7 +40,6 @@ int do_fdosboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char *name; char *ep; int size; - int rcode = 0; char buf [12]; int drive = CONFIG_SYS_FDC_DRIVE_NUMBER; @@ -98,15 +97,7 @@ int do_fdosboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("Floppy DOS load complete: %d bytes loaded to 0x%lx\n", size, load_addr); - /* Check if we should attempt an auto-start */ - if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { - char *local_args[2]; - local_args[0] = argv[0]; - local_args[1] = NULL; - printf ("Automatic boot of image at addr 0x%08lX ...\n", load_addr); - rcode = do_bootm (cmdtp, 0, 1, local_args); - } - return rcode; + return bootm_maybe_autostart(cmdtp, argv[0]); } /*----------------------------------------------------------------------------- diff --git a/common/cmd_fitupd.c b/common/cmd_fitupd.c new file mode 100644 index 0000000..4d1192b --- /dev/null +++ b/common/cmd_fitupd.c @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2011 + * Andreas Pretzsch, carpe noctem engineering, apr@cn-eng.de + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#include <common.h> +#include <command.h> + +#if !defined(CONFIG_UPDATE_TFTP) +#error "CONFIG_UPDATE_TFTP required" +#endif + +extern int update_tftp(ulong addr); + +static int do_fitupd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ulong addr = 0UL; + + if (argc > 2) + return cmd_usage(cmdtp); + + if (argc == 2) + addr = simple_strtoul(argv[1], NULL, 16); + + return update_tftp(addr); +} + +U_BOOT_CMD(fitupd, 2, 0, do_fitupd, + "update from FIT image", + "[addr]\n" + "\t- run update from FIT image at addr\n" + "\t or from tftp 'updatefile'" +); diff --git a/common/cmd_flash.c b/common/cmd_flash.c index bd49b79..5508d73 100644 --- a/common/cmd_flash.c +++ b/common/cmd_flash.c @@ -139,7 +139,7 @@ int flash_sect_roundb (ulong *addr) } /* bank */ } if (!found) { - /* error, addres not in flash */ + /* error, address not in flash */ printf("Error: end address (0x%08lx) not in flash!\n", *addr); return 1; } diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index 0ad310f..8946345 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -289,7 +289,7 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { const void *fit_hdr = (const void *)fpga_data; int noffset; - void *fit_data; + const void *fit_data; if (fit_uname == NULL) { puts ("No FIT subimage unit name\n"); diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index d913e13..3ea75f7 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -1397,8 +1397,8 @@ static int i2c_mux_get_busid (void) return tmp; } -/* Analyses a Muxstring and sends immediately the - Commands to the Muxes. Runs from Flash. +/* Analyses a Muxstring and immediately sends the + commands to the muxes. Runs from flash. */ int i2c_mux_ident_muxstring_f (uchar *buf) { diff --git a/common/cmd_ide.c b/common/cmd_ide.c index 21fe1ea..2e8c6e0 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -356,7 +356,6 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) ulong addr, cnt; disk_partition_t info; image_header_t *hdr; - int rcode = 0; #if defined(CONFIG_FIT) const void *fit_hdr = NULL; #endif @@ -495,19 +494,7 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) load_addr = addr; - /* Check if we should attempt an auto-start */ - if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { - char *local_args[2]; - - local_args[0] = argv[0]; - local_args[1] = NULL; - - printf ("Automatic boot of image at addr 0x%08lX ...\n", addr); - - do_bootm (cmdtp, 0, 1, local_args); - rcode = 1; - } - return rcode; + return bootm_maybe_autostart(cmdtp, argv[0]); } /* ------------------------------------------------------------------------- */ @@ -732,10 +719,12 @@ void ide_init (void) /* ------------------------------------------------------------------------- */ +#ifdef CONFIG_PARTITIONS block_dev_desc_t * ide_get_dev(int dev) { return (dev < CONFIG_SYS_IDE_MAXDEVICE) ? &ide_dev_desc[dev] : NULL; } +#endif #ifdef CONFIG_IDE_8xx_DIRECT diff --git a/common/cmd_mac.c b/common/cmd_mac.c index 1884c2a..fcc2867 100644 --- a/common/cmd_mac.c +++ b/common/cmd_mac.c @@ -30,8 +30,8 @@ U_BOOT_CMD( mac, 3, 1, do_mac, "display and program the system ID and MAC addresses in EEPROM", "[read|save|id|num|errata|date|ports|0|1|2|3|4|5|6|7]\n" - "read\n" - " - show content of EEPROM\n" + "mac read\n" + " - read EEPROM content into memory\n" "mac save\n" " - save to the EEPROM\n" "mac id\n" diff --git a/common/cmd_md5sum.c b/common/cmd_md5sum.c index d6ebb80..629a74d 100644 --- a/common/cmd_md5sum.c +++ b/common/cmd_md5sum.c @@ -37,7 +37,7 @@ static int do_md5sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) addr = simple_strtoul(argv[1], NULL, 16); len = simple_strtoul(argv[2], NULL, 16); - md5((unsigned char *) addr, len, output); + md5_wd((unsigned char *) addr, len, output, CHUNKSZ_MD5); printf("md5 for %08lx ... %08lx ==> ", addr, addr + len - 1); for (i = 0; i < 16; i++) printf("%02x", output[i]); diff --git a/common/cmd_mem.c b/common/cmd_mem.c index a5576aa..4daa1b3 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -1092,7 +1092,7 @@ int do_mem_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) length = simple_strtoul (argv[2], NULL, 16); - crc = crc32 (0, (const uchar *) addr, length); + crc = crc32_wd (0, (const uchar *) addr, length, CHUNKSZ_CRC32); printf ("CRC32 for %08lx ... %08lx ==> %08lx\n", addr, addr + length - 1, crc); @@ -1137,7 +1137,7 @@ usage: addr += base_address; length = simple_strtoul(*av++, NULL, 16); - crc = crc32(0, (const uchar *) addr, length); + crc = crc32_wd (0, (const uchar *) addr, length, CHUNKSZ_CRC32); if (!verify) { printf ("CRC32 for %08lx ... %08lx ==> %08lx\n", diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 176646d..8f13c22 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -87,6 +87,12 @@ U_BOOT_CMD( ); #else /* !CONFIG_GENERIC_MMC */ +enum mmc_state { + MMC_INVALID, + MMC_READ, + MMC_WRITE, + MMC_ERASE, +}; static void print_mmcinfo(struct mmc *mmc) { printf("Device: %s\n", mmc->name); @@ -144,6 +150,8 @@ U_BOOT_CMD( int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + enum mmc_state state; + if (argc < 2) return cmd_usage(cmdtp); @@ -165,9 +173,11 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } mmc->has_init = 0; - mmc_init(mmc); - return 0; + if (mmc_init(mmc)) + return 1; + else + return 0; } else if (strncmp(argv[1], "part", 4) == 0) { block_dev_desc_t *mmc_dev; struct mmc *mmc = find_mmc_device(curr_device); @@ -239,53 +249,61 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) curr_device, mmc->part_num); return 0; - } else if (strcmp(argv[1], "read") == 0) { - void *addr = (void *)simple_strtoul(argv[2], NULL, 16); - u32 cnt = simple_strtoul(argv[4], NULL, 16); - u32 n; - u32 blk = simple_strtoul(argv[3], NULL, 16); - struct mmc *mmc = find_mmc_device(curr_device); - - if (!mmc) { - printf("no mmc device at slot %x\n", curr_device); - return 1; - } - - printf("\nMMC read: dev # %d, block # %d, count %d ... ", - curr_device, blk, cnt); - - mmc_init(mmc); - - n = mmc->block_dev.block_read(curr_device, blk, cnt, addr); + } - /* flush cache after read */ - flush_cache((ulong)addr, cnt * 512); /* FIXME */ + if (strcmp(argv[1], "read") == 0) + state = MMC_READ; + else if (strcmp(argv[1], "write") == 0) + state = MMC_WRITE; + else if (strcmp(argv[1], "erase") == 0) + state = MMC_ERASE; + else + state = MMC_INVALID; - printf("%d blocks read: %s\n", - n, (n==cnt) ? "OK" : "ERROR"); - return (n == cnt) ? 0 : 1; - } else if (strcmp(argv[1], "write") == 0) { - void *addr = (void *)simple_strtoul(argv[2], NULL, 16); - u32 cnt = simple_strtoul(argv[4], NULL, 16); - u32 n; + if (state != MMC_INVALID) { struct mmc *mmc = find_mmc_device(curr_device); + int idx = 2; + u32 blk, cnt, n; + void *addr; - int blk = simple_strtoul(argv[3], NULL, 16); + if (state != MMC_ERASE) { + addr = (void *)simple_strtoul(argv[idx], NULL, 16); + ++idx; + } else + addr = 0; + blk = simple_strtoul(argv[idx], NULL, 16); + cnt = simple_strtoul(argv[idx + 1], NULL, 16); if (!mmc) { printf("no mmc device at slot %x\n", curr_device); return 1; } - printf("\nMMC write: dev # %d, block # %d, count %d ... ", - curr_device, blk, cnt); + printf("\nMMC %s: dev # %d, block # %d, count %d ... ", + argv[1], curr_device, blk, cnt); mmc_init(mmc); - n = mmc->block_dev.block_write(curr_device, blk, cnt, addr); + switch (state) { + case MMC_READ: + n = mmc->block_dev.block_read(curr_device, blk, + cnt, addr); + /* flush cache after read */ + flush_cache((ulong)addr, cnt * 512); /* FIXME */ + break; + case MMC_WRITE: + n = mmc->block_dev.block_write(curr_device, blk, + cnt, addr); + break; + case MMC_ERASE: + n = mmc->block_dev.block_erase(curr_device, blk, cnt); + break; + default: + BUG(); + } - printf("%d blocks written: %s\n", - n, (n == cnt) ? "OK" : "ERROR"); + printf("%d blocks %s: %s\n", + n, argv[1], (n == cnt) ? "OK" : "ERROR"); return (n == cnt) ? 0 : 1; } @@ -297,6 +315,7 @@ U_BOOT_CMD( "MMC sub system", "read addr blk# cnt\n" "mmc write addr blk# cnt\n" + "mmc erase blk# cnt\n" "mmc rescan\n" "mmc part - lists available partition on current mmc device\n" "mmc dev [dev] [part] - show or set current mmc device [partition]\n" diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 44c4d1f..66e06a5 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -575,13 +575,24 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) else ret = nand_write_skip_bad(nand, off, &rwsize, (u_char *)addr, 0); +#ifdef CONFIG_CMD_NAND_TRIMFFS + } else if (!strcmp(s, ".trimffs")) { + if (read) { + printf("Unknown nand command suffix '%s'\n", s); + return 1; + } + ret = nand_write_skip_bad(nand, off, &rwsize, + (u_char *)addr, + WITH_DROP_FFS); +#endif #ifdef CONFIG_CMD_NAND_YAFFS } else if (!strcmp(s, ".yaffs")) { if (read) { printf("Unknown nand command suffix '%s'.\n", s); return 1; } - ret = nand_write_skip_bad(nand, off, &rwsize, (u_char *)addr, 1); + ret = nand_write_skip_bad(nand, off, &rwsize, + (u_char *)addr, WITH_YAFFS_OOB); #endif } else if (!strcmp(s, ".oob")) { /* out-of-band data */ @@ -688,6 +699,12 @@ U_BOOT_CMD( "nand write - addr off|partition size\n" " read/write 'size' bytes starting at offset 'off'\n" " to/from memory address 'addr', skipping bad blocks.\n" +#ifdef CONFIG_CMD_NAND_TRIMFFS + "nand write.trimffs - addr off|partition size\n" + " write 'size' bytes starting at offset 'off' from memory address\n" + " 'addr', skipping bad blocks and dropping any pages at the end\n" + " of eraseblocks that contain only 0xFF\n" +#endif #ifdef CONFIG_CMD_NAND_YAFFS "nand write.yaffs - addr off|partition size\n" " write 'size' bytes starting at offset 'off' with yaffs format\n" @@ -724,7 +741,7 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, ulong offset, ulong addr, char *cmd) { int r; - char *ep, *s; + char *s; size_t cnt; image_header_t *hdr; #if defined(CONFIG_FIT) @@ -799,19 +816,7 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, load_addr = addr; - /* Check if we should attempt an auto-start */ - if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) { - char *local_args[2]; - - local_args[0] = cmd; - local_args[1] = NULL; - - printf("Automatic boot of image at addr 0x%08lx ...\n", addr); - - do_bootm(cmdtp, 0, 1, local_args); - return 1; - } - return 0; + return bootm_maybe_autostart(cmdtp, cmd); } int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) diff --git a/common/cmd_net.c b/common/cmd_net.c index 75ba1c3..872f4a6 100644 --- a/common/cmd_net.c +++ b/common/cmd_net.c @@ -227,17 +227,8 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char * const argv[]) /* flush cache */ flush_cache(load_addr, size); - /* Loading ok, check if we should attempt an auto-start */ - if (((s = getenv("autostart")) != NULL) && (strcmp(s,"yes") == 0)) { - char *local_args[2]; - local_args[0] = argv[0]; - local_args[1] = NULL; - - printf ("Automatic boot of image at addr 0x%08lX ...\n", - load_addr); - show_boot_progress (82); - rcode = do_bootm (cmdtp, 0, 1, local_args); - } + show_boot_progress(82); + rcode = bootm_maybe_autostart(cmdtp, argv[0]); if (rcode < 0) show_boot_progress (-83); diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index b2c88ba..e8b116d 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -367,13 +367,14 @@ int _do_env_set (int flag, int argc, char * const argv[]) return 0; } -int setenv(char *varname, char *varvalue) +int setenv(const char *varname, const char *varvalue) { - char * const argv[4] = { "setenv", varname, varvalue, NULL }; + const char * const argv[4] = { "setenv", varname, varvalue, NULL }; + if ((varvalue == NULL) || (varvalue[0] == '\0')) - return _do_env_set(0, 2, argv); + return _do_env_set(0, 2, (char * const *)argv); else - return _do_env_set(0, 3, argv); + return _do_env_set(0, 3, (char * const *)argv); } int do_env_set(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -482,7 +483,7 @@ int do_env_edit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * return address of storage for that variable, * or NULL if not found */ -char *getenv(char *name) +char *getenv(const char *name) { if (gd->flags & GD_FLG_ENV_READY) { /* after import into hashtable */ ENTRY e, *ep; @@ -507,7 +508,7 @@ char *getenv(char *name) /* * Look up variable from environment for restricted C runtime env. */ -int getenv_f(char *name, char *buf, unsigned len) +int getenv_f(const char *name, char *buf, unsigned len) { int i, nxt; diff --git a/common/cmd_sata.c b/common/cmd_sata.c index 7efa859..f62c0cb 100644 --- a/common/cmd_sata.c +++ b/common/cmd_sata.c @@ -57,10 +57,12 @@ int __sata_initialize(void) } int sata_initialize(void) __attribute__((weak,alias("__sata_initialize"))); +#ifdef CONFIG_PARTITIONS block_dev_desc_t *sata_get_dev(int dev) { return (dev < CONFIG_SYS_SATA_MAX_DEVICE) ? &sata_dev_desc[dev] : NULL; } +#endif int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index be4fe74..fa10751 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -46,7 +46,7 @@ #define SCSI_VEND_ID 0x10b9 #define SCSI_DEV_ID 0x5288 -#else +#elif !defined(CONFIG_SCSI_AHCI_PLAT) #error no scsi device defined #endif @@ -174,7 +174,7 @@ removable: scsi_curr_dev = -1; } - +#ifdef CONFIG_PCI void scsi_init(void) { int busdevfunc; @@ -192,12 +192,14 @@ void scsi_init(void) scsi_low_level_init(busdevfunc); scsi_scan(1); } +#endif +#ifdef CONFIG_PARTITIONS block_dev_desc_t * scsi_get_dev(int dev) { return (dev < CONFIG_SYS_SCSI_MAX_DEVICE) ? &scsi_dev_desc[dev] : NULL; } - +#endif /****************************************************************************** * scsi boot command intepreter. Derived from diskboot @@ -210,7 +212,6 @@ int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) ulong addr, cnt; disk_partition_t info; image_header_t *hdr; - int rcode = 0; #if defined(CONFIG_FIT) const void *fit_hdr = NULL; #endif @@ -326,15 +327,7 @@ int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) flush_cache (addr, (cnt+1)*info.blksz); - /* Check if we should attempt an auto-start */ - if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { - char *local_args[2]; - local_args[0] = argv[0]; - local_args[1] = NULL; - printf ("Automatic boot of image at addr 0x%08lX ...\n", addr); - rcode = do_bootm (cmdtp, 0, 1, local_args); - } - return rcode; + return bootm_maybe_autostart(cmdtp, argv[0]); } /********************************************************************************* diff --git a/common/cmd_sha1sum.c b/common/cmd_sha1sum.c index bb3cff0..2b2dd8b 100644 --- a/common/cmd_sha1sum.c +++ b/common/cmd_sha1sum.c @@ -37,7 +37,7 @@ static int do_sha1sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) addr = simple_strtoul(argv[1], NULL, 16); len = simple_strtoul(argv[2], NULL, 16); - sha1_csum((unsigned char *) addr, len, output); + sha1_csum_wd((unsigned char *) addr, len, output, CHUNKSZ_SHA1); printf("SHA1 for %08lx ... %08lx ==> ", addr, addr + len - 1); for (i = 0; i < 20; i++) printf("%02x", output[i]); diff --git a/common/cmd_usb.c b/common/cmd_usb.c index 3ba6fff..cd4d417 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -356,7 +356,7 @@ int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char *boot_device = NULL; char *ep; - int dev, part = 1, rcode; + int dev, part = 1; ulong addr, cnt; disk_partition_t info; image_header_t *hdr; @@ -490,16 +490,7 @@ int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) flush_cache(addr, (cnt+1)*info.blksz); - /* Check if we should attempt an auto-start */ - if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) { - char *local_args[2]; - local_args[0] = argv[0]; - local_args[1] = NULL; - printf("Automatic boot of image at addr 0x%08lX ...\n", addr); - rcode = do_bootm(cmdtp, 0, 1, local_args); - return rcode; - } - return 0; + return bootm_maybe_autostart(cmdtp, argv[0]); } #endif /* CONFIG_USB_STORAGE */ diff --git a/common/cmd_version.c b/common/cmd_version.c index 83cb11c..e4b2ac1 100644 --- a/common/cmd_version.c +++ b/common/cmd_version.c @@ -24,8 +24,9 @@ #include <common.h> #include <command.h> #include <version.h> +#include <linux/compiler.h> -extern char version_string[]; +const char __weak version_string[] = U_BOOT_VERSION_STRING; int do_version(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/common/cmd_vfd.c b/common/cmd_vfd.c deleted file mode 100644 index 18c14d1..0000000 --- a/common/cmd_vfd.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Command to load a splash screen to the VFDs. - * NOTE that this will be controlled by a key combination when - * the keyboard stuff works. For now the user has to enter a - * bitmap number (only VFD_TEST_LOGO is supported now - 16.10.2002). - * Added VFD_REMOTE_LOGO (same as VFD_TEST_LOGO but a different color) - * on 20.10.2002. - * - * This rather crudely requires that each bitmap be included as a - * header file. - */ -#include <common.h> -#include <command.h> - -#if defined(CONFIG_CMD_VFD) - -#include <vfd_logo.h> -#define VFD_TEST_LOGO_BMPNR 0 -#define VFD_REMOTE_LOGO_BMPNR 1 - -extern int transfer_pic(unsigned char, unsigned char *, int, int); - -int trab_vfd (ulong bitmap); - -int do_vfd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong bitmap; - - if (argc != 2) - return cmd_usage(cmdtp); - - if (argv[1][0] == '/') { /* select bitmap by number */ - bitmap = simple_strtoul(argv[1]+1, NULL, 10); - return (trab_vfd(bitmap)); - } - - /* display bitmap at given address */ - bitmap = simple_strtoul(argv[1], NULL, 16); - transfer_pic(3, (uchar *)bitmap, VFD_LOGO_HEIGHT, VFD_LOGO_WIDTH); - return 0; -} - -U_BOOT_CMD( - vfd, 2, 0, do_vfd, - "load a bitmap to the VFDs on TRAB", - "/N\n" - " - load bitmap N to the VFDs (N is _decimal_ !!!)\n" - "vfd ADDR\n" - " - load bitmap at address ADDR" -); -#endif - -int trab_vfd (ulong bitmap) -{ - uchar *addr; - char *s; - - switch (bitmap) { - case VFD_TEST_LOGO_BMPNR: - if ((s = getenv ("bitmap0")) != NULL) { - addr = (uchar *)simple_strtoul (s, NULL, 16); - } else { - addr = &vfd_test_logo_bitmap[0]; - } - break; - case VFD_REMOTE_LOGO_BMPNR: - if ((s = getenv ("bitmap1")) != NULL) { - addr = (uchar *)simple_strtoul (s, NULL, 16); - } else { - addr = &vfd_remote_logo_bitmap[0]; - } - break; - default: - printf("Unknown bitmap %ld\n", bitmap); - return 1; - } - transfer_pic(3, addr, VFD_LOGO_HEIGHT, VFD_LOGO_WIDTH); - return 0; -} diff --git a/common/cmd_ximg.c b/common/cmd_ximg.c index dceb975..850188e 100644 --- a/common/cmd_ximg.c +++ b/common/cmd_ximg.c @@ -215,6 +215,7 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) memmove ((char *) dest, (char *)data, len); #endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ break; +#ifdef CONFIG_GZIP case IH_COMP_GZIP: printf (" Uncompressing part %d ... ", part); if (gunzip ((void *) dest, unc_len, @@ -223,6 +224,7 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) return 1; } break; +#endif #if defined(CONFIG_BZIP2) case IH_COMP_BZIP2: { diff --git a/common/command.c b/common/command.c index b3ec510..ddaed68 100644 --- a/common/command.c +++ b/common/command.c @@ -140,7 +140,7 @@ cmd_tbl_t *find_cmd (const char *cmd) return find_cmd_tbl(cmd, &__u_boot_cmd_start, len); } -int cmd_usage(cmd_tbl_t *cmdtp) +int cmd_usage(const cmd_tbl_t *cmdtp) { printf("%s - %s\n\n", cmdtp->name, cmdtp->usage); diff --git a/common/env_common.c b/common/env_common.c index c3e6388..19149b5 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -47,7 +47,7 @@ static uchar env_get_char_init (int index); #define XMK_STR(x) #x #define MK_STR(x) XMK_STR(x) -uchar default_environment[] = { +const uchar default_environment[] = { #ifdef CONFIG_BOOTARGS "bootargs=" CONFIG_BOOTARGS "\0" #endif @@ -162,7 +162,7 @@ uchar env_get_char (int index) return (c); } -uchar *env_get_addr (int index) +const uchar *env_get_addr (int index) { if (gd->env_valid) return (uchar *)(gd->env_addr + index); diff --git a/common/env_embedded.c b/common/env_embedded.c index ae6cac4..e438575 100644 --- a/common/env_embedded.c +++ b/common/env_embedded.c @@ -44,7 +44,7 @@ * Generate embedded environment table * inside U-Boot image, if needed. */ -#if defined(ENV_IS_EMBEDDED) +#if defined(ENV_IS_EMBEDDED) || defined(CONFIG_BUILD_ENVCRC) /* * Only put the environment in it's own section when we are building * U-Boot proper. The host based program "tools/envcrc" does not need diff --git a/common/env_flash.c b/common/env_flash.c index 456f2e8..50ca4ffa 100644 --- a/common/env_flash.c +++ b/common/env_flash.c @@ -74,7 +74,7 @@ static env_t *flash_addr_new = (env_t *)CONFIG_ENV_ADDR_REDUND; static ulong end_addr_new = CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1; #endif /* CONFIG_ENV_ADDR_REDUND */ -extern uchar default_environment[]; +extern const uchar default_environment[]; uchar env_get_char_spec(int index) diff --git a/common/fdt_support.c b/common/fdt_support.c index 496040b..19b2ef6 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -1195,6 +1195,46 @@ int fdt_alloc_phandle(void *blob) return phandle + 1; } +/* + * fdt_create_phandle: Create a phandle property for the given node + * + * @fdt: ptr to device tree + * @nodeoffset: node to update + * @phandle: phandle value to set (must be unique) +*/ +int fdt_create_phandle(void *fdt, int nodeoffset, uint32_t phandle) +{ + int ret; + +#ifdef DEBUG + int off = fdt_node_offset_by_phandle(fdt, phandle); + + if ((off >= 0) && (off != nodeoffset)) { + char buf[64]; + + fdt_get_path(fdt, nodeoffset, buf, sizeof(buf)); + printf("Trying to update node %s with phandle %u ", + buf, phandle); + + fdt_get_path(fdt, off, buf, sizeof(buf)); + printf("that already exists in node %s.\n", buf); + return -FDT_ERR_BADPHANDLE; + } +#endif + + ret = fdt_setprop_cell(fdt, nodeoffset, "phandle", phandle); + if (ret < 0) + return ret; + + /* + * For now, also set the deprecated "linux,phandle" property, so that we + * don't break older kernels. + */ + ret = fdt_setprop_cell(fdt, nodeoffset, "linux,phandle", phandle); + + return ret; +} + #if defined(CONFIG_VIDEO) int fdt_add_edid(void *blob, const char *compat, unsigned char *edid_buf) { @@ -1223,3 +1263,70 @@ err_size: return ret; } #endif + +/* + * Verify the physical address of device tree node for a given alias + * + * This function locates the device tree node of a given alias, and then + * verifies that the physical address of that device matches the given + * parameter. It displays a message if there is a mismatch. + * + * Returns 1 on success, 0 on failure + */ +int fdt_verify_alias_address(void *fdt, int anode, const char *alias, u64 addr) +{ + const char *path; + const u32 *reg; + int node, len; + u64 dt_addr; + + path = fdt_getprop(fdt, anode, alias, NULL); + if (!path) { + /* If there's no such alias, then it's not a failure */ + return 1; + } + + node = fdt_path_offset(fdt, path); + if (node < 0) { + printf("Warning: device tree alias '%s' points to invalid " + "node %s.\n", alias, path); + return 0; + } + + reg = fdt_getprop(fdt, node, "reg", &len); + if (!reg) { + printf("Warning: device tree node '%s' has no address.\n", + path); + return 0; + } + + dt_addr = fdt_translate_address(fdt, node, reg); + if (addr != dt_addr) { + printf("Warning: U-Boot configured device %s at address %llx,\n" + " but the device tree has it address %llx.\n", + alias, addr, dt_addr); + return 0; + } + + return 1; +} + +/* + * Returns the base address of an SOC or PCI node + */ +u64 fdt_get_base_address(void *fdt, int node) +{ + int size; + u32 naddr; + const u32 *prop; + + prop = fdt_getprop(fdt, node, "#address-cells", &size); + if (prop && size == 4) + naddr = *prop; + else + naddr = 2; + + prop = fdt_getprop(fdt, node, "ranges", &size); + + return prop ? fdt_translate_address(fdt, node, prop + naddr) : 0; +} diff --git a/common/image.c b/common/image.c index e542a57..5eea2a1 100644 --- a/common/image.c +++ b/common/image.c @@ -130,17 +130,22 @@ static const table_entry_t uimage_os[] = { }; static const table_entry_t uimage_type[] = { - { IH_TYPE_INVALID, NULL, "Invalid Image", }, { IH_TYPE_FILESYSTEM, "filesystem", "Filesystem Image", }, { IH_TYPE_FIRMWARE, "firmware", "Firmware", }, + { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", }, + { IH_TYPE_INVALID, NULL, "Invalid Image", }, + { IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot Image",}, { IH_TYPE_KERNEL, "kernel", "Kernel Image", }, + { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, { IH_TYPE_MULTI, "multi", "Multi-File Image", }, + { IH_TYPE_OMAPIMAGE, "omapimage", "TI OMAP SPL With GP CH",}, { IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", }, { IH_TYPE_SCRIPT, "script", "Script", }, { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", }, { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, { IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot Image",}, + { IH_TYPE_UBLIMAGE, "ublimage", "Davinci UBL image",}, { -1, "", "", }, }; @@ -1234,8 +1239,10 @@ int boot_relocate_fdt (struct lmb *lmb, char **of_flat_tree, ulong *of_size) { void *fdt_blob = *of_flat_tree; void *of_start = 0; + char *fdt_high; ulong of_len = 0; int err; + int disable_relocation = 0; /* nothing to do */ if (*of_size == 0) @@ -1249,26 +1256,62 @@ int boot_relocate_fdt (struct lmb *lmb, char **of_flat_tree, ulong *of_size) /* position on a 4K boundary before the alloc_current */ /* Pad the FDT by a specified amount */ of_len = *of_size + CONFIG_SYS_FDT_PAD; - of_start = (void *)(unsigned long)lmb_alloc_base(lmb, of_len, 0x1000, - getenv_bootm_mapsize() + getenv_bootm_low()); + + /* If fdt_high is set use it to select the relocation address */ + fdt_high = getenv("fdt_high"); + if (fdt_high) { + void *desired_addr = (void *)simple_strtoul(fdt_high, NULL, 16); + + if (((ulong) desired_addr) == ~0UL) { + /* All ones means use fdt in place */ + desired_addr = fdt_blob; + disable_relocation = 1; + } + if (desired_addr) { + of_start = + (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000, + ((ulong) + desired_addr) + + of_len); + if (desired_addr && of_start != desired_addr) { + puts("Failed using fdt_high value for Device Tree"); + goto error; + } + } else { + of_start = + (void *)(ulong) lmb_alloc(lmb, of_len, 0x1000); + } + } else { + of_start = + (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000, + getenv_bootm_mapsize() + + getenv_bootm_low()); + } if (of_start == 0) { puts("device tree - allocation error\n"); goto error; } - debug ("## device tree at %p ... %p (len=%ld [0x%lX])\n", - fdt_blob, fdt_blob + *of_size - 1, of_len, of_len); + if (disable_relocation) { + /* We assume there is space after the existing fdt to use for padding */ + fdt_set_totalsize(of_start, of_len); + printf(" Using Device Tree in place at %p, end %p\n", + of_start, of_start + of_len - 1); + } else { + debug ("## device tree at %p ... %p (len=%ld [0x%lX])\n", + fdt_blob, fdt_blob + *of_size - 1, of_len, of_len); - printf (" Loading Device Tree to %p, end %p ... ", - of_start, of_start + of_len - 1); + printf (" Loading Device Tree to %p, end %p ... ", + of_start, of_start + of_len - 1); - err = fdt_open_into (fdt_blob, of_start, of_len); - if (err != 0) { - fdt_error ("fdt move failed"); - goto error; + err = fdt_open_into (fdt_blob, of_start, of_len); + if (err != 0) { + fdt_error ("fdt move failed"); + goto error; + } + puts ("OK\n"); } - puts ("OK\n"); *of_flat_tree = of_start; *of_size = of_len; diff --git a/common/main.c b/common/main.c index dcbacc9..3324d9d 100644 --- a/common/main.c +++ b/common/main.c @@ -30,6 +30,7 @@ #include <common.h> #include <watchdog.h> #include <command.h> +#include <version.h> #ifdef CONFIG_MODEM_SUPPORT #include <malloc.h> /* for free() prototype */ #endif @@ -51,15 +52,11 @@ void inline __show_boot_progress (int val) {} void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress"))); #if defined(CONFIG_UPDATE_TFTP) -void update_tftp (void); +int update_tftp (ulong addr); #endif /* CONFIG_UPDATE_TFTP */ #define MAX_DELAY_STOP_STR 32 -#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) -static int abortboot(int); -#endif - #undef DEBUG_PARSER char console_buffer[CONFIG_SYS_CBSIZE + 1]; /* console I/O buffer */ @@ -91,7 +88,7 @@ extern void mdm_init(void); /* defined in board.c */ */ #if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) # if defined(CONFIG_AUTOBOOT_KEYED) -static __inline__ int abortboot(int bootdelay) +static inline int abortboot(int bootdelay) { int abort = 0; uint64_t etime = endtick(bootdelay); @@ -205,7 +202,7 @@ static __inline__ int abortboot(int bootdelay) static int menukey = 0; #endif -static __inline__ int abortboot(int bootdelay) +static inline int abortboot(int bootdelay) { int abort = 0; @@ -288,17 +285,6 @@ void main_loop (void) char bcs_set[16]; #endif /* CONFIG_BOOTCOUNT_LIMIT */ -#if defined(CONFIG_VFD) && defined(VFD_TEST_LOGO) - ulong bmp = 0; /* default bitmap */ - extern int trab_vfd (ulong bitmap); - -#ifdef CONFIG_MODEM_SUPPORT - if (do_mdm_init) - bmp = 1; /* alternate bitmap */ -#endif - trab_vfd (bmp); -#endif /* CONFIG_VFD && VFD_TEST_LOGO */ - #ifdef CONFIG_BOOTCOUNT_LIMIT bootcount = bootcount_load(); bootcount++; @@ -322,8 +308,6 @@ void main_loop (void) #ifdef CONFIG_VERSION_VARIABLE { - extern char version_string[]; - setenv ("ver", version_string); /* set version variable */ } #endif /* CONFIG_VERSION_VARIABLE */ @@ -356,7 +340,7 @@ void main_loop (void) #endif /* CONFIG_PREBOOT */ #if defined(CONFIG_UPDATE_TFTP) - update_tftp (); + update_tftp (0UL); #endif /* CONFIG_UPDATE_TFTP */ #if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) @@ -406,15 +390,15 @@ void main_loop (void) # ifdef CONFIG_MENUKEY if (menukey == CONFIG_MENUKEY) { - s = getenv("menucmd"); - if (s) { + s = getenv("menucmd"); + if (s) { # ifndef CONFIG_SYS_HUSH_PARSER - run_command (s, 0); + run_command(s, 0); # else - parse_string_outer(s, FLAG_PARSE_SEMICOLON | - FLAG_EXIT_FROM_LOOP); + parse_string_outer(s, FLAG_PARSE_SEMICOLON | + FLAG_EXIT_FROM_LOOP); # endif - } + } } #endif /* CONFIG_MENUKEY */ #endif /* CONFIG_BOOTDELAY */ diff --git a/common/memsize.c b/common/memsize.c index 6c275c9..963e4f3 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -37,7 +37,7 @@ * the actually available RAM size between addresses `base' and * `base + maxsize'. */ -long get_ram_size(volatile long *base, long maxsize) +long get_ram_size(long *base, long maxsize) { volatile long *addr; long save[32]; diff --git a/common/miiphyutil.c b/common/miiphyutil.c index bcab74e..35ad357 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -111,7 +111,8 @@ void miiphy_register(const char *name, { struct mii_dev *new_dev; struct legacy_mii_dev *ldev; - unsigned int name_len; + + BUG_ON(strlen(name) >= MDIO_NAME_LEN); /* check if we have unique name */ new_dev = miiphy_get_dev_by_name(name); @@ -121,14 +122,6 @@ void miiphy_register(const char *name, } /* allocate memory */ - name_len = strlen(name); - if (name_len > MDIO_NAME_LEN - 1) { - /* Hopefully this won't happen, but if it does, we'll know */ - printf("miiphy_register: MDIO name was longer than %d\n", - MDIO_NAME_LEN); - return; - } - new_dev = mdio_alloc(); ldev = malloc(sizeof(*ldev)); @@ -141,7 +134,8 @@ void miiphy_register(const char *name, /* initalize mii_dev struct fields */ new_dev->read = legacy_miiphy_read; new_dev->write = legacy_miiphy_write; - sprintf(new_dev->name, name); + strncpy(new_dev->name, name, MDIO_NAME_LEN); + new_dev->name[MDIO_NAME_LEN - 1] = 0; ldev->read = read; ldev->write = write; new_dev->priv = ldev; diff --git a/common/serial.c b/common/serial.c index 8ebf9a5..995d268 100644 --- a/common/serial.c +++ b/common/serial.c @@ -24,81 +24,15 @@ #include <common.h> #include <serial.h> #include <stdio_dev.h> +#include <post.h> +#include <linux/compiler.h> DECLARE_GLOBAL_DATA_PTR; static struct serial_device *serial_devices = NULL; static struct serial_device *serial_current = NULL; -#if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA250) && !defined(CONFIG_PXA27X) -struct serial_device *__default_serial_console (void) -{ -#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) - return &serial_smc_device; -#elif defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \ - || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) - return &serial_scc_device; -#elif defined(CONFIG_4xx) \ - || defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) \ - || defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) \ - || defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) \ - || defined(CONFIG_TEGRA2) -#if defined(CONFIG_CONS_INDEX) && defined(CONFIG_SYS_NS16550_SERIAL) -#if (CONFIG_CONS_INDEX==1) - return &eserial1_device; -#elif (CONFIG_CONS_INDEX==2) - return &eserial2_device; -#elif (CONFIG_CONS_INDEX==3) - return &eserial3_device; -#elif (CONFIG_CONS_INDEX==4) - return &eserial4_device; -#else -#error "Bad CONFIG_CONS_INDEX." -#endif -#else - return &serial0_device; -#endif -#elif defined(CONFIG_MPC512X) -#if (CONFIG_PSC_CONSOLE == 3) - return &serial3_device; -#elif (CONFIG_PSC_CONSOLE == 6) - return &serial6_device; -#else -#error "Bad CONFIG_PSC_CONSOLE." -#endif -#elif defined(CONFIG_S3C2410) -#if defined(CONFIG_SERIAL1) - return &s3c24xx_serial0_device; -#elif defined(CONFIG_SERIAL2) - return &s3c24xx_serial1_device; -#elif defined(CONFIG_SERIAL3) - return &s3c24xx_serial2_device; -#else -#error "CONFIG_SERIAL? missing." -#endif -#elif defined(CONFIG_S5P) -#if defined(CONFIG_SERIAL0) - return &s5p_serial0_device; -#elif defined(CONFIG_SERIAL1) - return &s5p_serial1_device; -#elif defined(CONFIG_SERIAL2) - return &s5p_serial2_device; -#elif defined(CONFIG_SERIAL3) - return &s5p_serial3_device; -#else -#error "CONFIG_SERIAL? missing." -#endif -#elif defined(CONFIG_OMAP3_ZOOM2) - return ZOOM2_DEFAULT_SERIAL_DEVICE; -#else -#error No default console -#endif -} - -struct serial_device *default_serial_console(void) __attribute__((weak, alias("__default_serial_console"))); -#endif - -int serial_register (struct serial_device *dev) +void serial_register(struct serial_device *dev) { #ifdef CONFIG_NEEDS_MANUAL_RELOC dev->init += gd->reloc_off; @@ -111,8 +45,6 @@ int serial_register (struct serial_device *dev) dev->next = serial_devices; serial_devices = dev; - - return 0; } void serial_initialize (void) @@ -173,6 +105,9 @@ void serial_initialize (void) serial_register(&serial6_device); #endif #endif +#if defined(CONFIG_SYS_BFIN_UART) + serial_register_bfin_uart(); +#endif serial_assign (default_serial_console ()->name); } @@ -291,3 +226,91 @@ void serial_puts (const char *s) serial_current->puts (s); } + +#if CONFIG_POST & CONFIG_SYS_POST_UART +static const int bauds[] = CONFIG_SYS_BAUDRATE_TABLE; + +/* Mark weak until post/cpu/.../uart.c migrate over */ +__weak +int uart_post_test(int flags) +{ + unsigned char c; + int ret, saved_baud, b; + struct serial_device *saved_dev, *s; + bd_t *bd = gd->bd; + + /* Save current serial state */ + ret = 0; + saved_dev = serial_current; + saved_baud = bd->bi_baudrate; + + for (s = serial_devices; s; s = s->next) { + /* If this driver doesn't support loop back, skip it */ + if (!s->loop) + continue; + + /* Test the next device */ + serial_current = s; + + ret = serial_init(); + if (ret) + goto done; + + /* Consume anything that happens to be queued */ + while (serial_tstc()) + serial_getc(); + + /* Enable loop back */ + s->loop(1); + + /* Test every available baud rate */ + for (b = 0; b < ARRAY_SIZE(bauds); ++b) { + bd->bi_baudrate = bauds[b]; + serial_setbrg(); + + /* + * Stick to printable chars to avoid issues: + * - terminal corruption + * - serial program reacting to sequences and sending + * back random extra data + * - most serial drivers add in extra chars (like \r\n) + */ + for (c = 0x20; c < 0x7f; ++c) { + /* Send it out */ + serial_putc(c); + + /* Make sure it's the same one */ + ret = (c != serial_getc()); + if (ret) { + s->loop(0); + goto done; + } + + /* Clean up the output in case it was sent */ + serial_putc('\b'); + ret = ('\b' != serial_getc()); + if (ret) { + s->loop(0); + goto done; + } + } + } + + /* Disable loop back */ + s->loop(0); + + /* XXX: There is no serial_uninit() !? */ + if (s->uninit) + s->uninit(); + } + + done: + /* Restore previous serial state */ + serial_current = saved_dev; + bd->bi_baudrate = saved_baud; + serial_reinit_all(); + serial_setbrg(); + + return ret; +} +#endif diff --git a/common/update.c b/common/update.c index 7528474..a19f136 100644 --- a/common/update.c +++ b/common/update.c @@ -238,13 +238,17 @@ static int update_fit_getparams(const void *fit, int noffset, ulong *addr, return 0; } -void update_tftp(void) +int update_tftp(ulong addr) { char *filename, *env_addr; int images_noffset, ndepth, noffset; ulong update_addr, update_fladdr, update_size; - ulong addr; void *fit; + int ret = 0; + + /* use already present image */ + if (addr) + goto got_update_file; printf("Auto-update from TFTP: "); @@ -253,7 +257,7 @@ void update_tftp(void) if (filename == NULL) { printf("failed, env. variable '%s' not found\n", UPDATE_FILE_ENV); - return; + return 1; } printf("trying update file '%s'\n", filename); @@ -268,15 +272,16 @@ void update_tftp(void) if (update_load(filename, CONFIG_UPDATE_TFTP_MSEC_MAX, CONFIG_UPDATE_TFTP_CNT_MAX, addr)) { printf("Can't load update file, aborting auto-update\n"); - return; + return 1; } +got_update_file: fit = (void *)addr; if (!fit_check_format((void *)fit)) { printf("Bad FIT format of the update file, aborting " "auto-update\n"); - return; + return 1; } /* process updates */ @@ -293,6 +298,7 @@ void update_tftp(void) if (!fit_image_check_hashes(fit, noffset)) { printf("Error: invalid update hash, aborting\n"); + ret = 1; goto next_node; } @@ -301,15 +307,17 @@ void update_tftp(void) &update_fladdr, &update_size)) { printf("Error: can't get update parameteres, " "aborting\n"); + ret = 1; goto next_node; } if (update_flash(update_addr, update_fladdr, update_size)) { printf("Error: can't flash update, aborting\n"); + ret = 1; goto next_node; } next_node: noffset = fdt_next_node(fit, noffset, &ndepth); } - return; + return ret; } diff --git a/common/usb_storage.c b/common/usb_storage.c index 9ecf165..16667f3 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -173,11 +173,12 @@ unsigned long usb_stor_write(int device, unsigned long blknr, struct usb_device * usb_get_dev_index(int index); void uhci_show_temp_int_td(void); +#ifdef CONFIG_PARTITIONS block_dev_desc_t *usb_stor_get_dev(int index) { return (index < usb_max_devs) ? &usb_dev_desc[index] : NULL; } - +#endif void usb_show_progress(void) { diff --git a/common/xyzModem.c b/common/xyzModem.c index 7a46805..a1f955b 100644 --- a/common/xyzModem.c +++ b/common/xyzModem.c @@ -786,7 +786,7 @@ xyzModem_stream_terminate (bool abort, int (*getc) (void)) ZM_DEBUG (zm_dprintf ("Engaging cleanup mode...\n")); /* * Consume any trailing crap left in the inbuffer from - * previous recieved blocks. Since very few files are an exact multiple + * previous received blocks. Since very few files are an exact multiple * of the transfer block size, there will almost always be some gunk here. * If we don't eat it now, RedBoot will think the user typed it. */ @@ -23,19 +23,31 @@ ######################################################################### -ifneq ($(OBJTREE),$(SRCTREE)) ifeq ($(CURDIR),$(SRCTREE)) dir := else dir := $(subst $(SRCTREE)/,,$(CURDIR)) endif +ifneq ($(OBJTREE),$(SRCTREE)) +# Create object files for SPL in a separate directory +ifeq ($(CONFIG_SPL_BUILD),y) +obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/) +else obj := $(if $(dir),$(OBJTREE)/$(dir)/,$(OBJTREE)/) +endif src := $(if $(dir),$(SRCTREE)/$(dir)/,$(SRCTREE)/) $(shell mkdir -p $(obj)) else +# Create object files for SPL in a separate directory +ifeq ($(CONFIG_SPL_BUILD),y) +obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/) + +$(shell mkdir -p $(obj)) +else obj := +endif src := endif @@ -154,46 +166,31 @@ RELFLAGS= $(PLATFORM_RELFLAGS) DBGFLAGS= -g # -DDEBUG OPTFLAGS= -Os #-fomit-frame-pointer -# If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use -# that (or fail if absent). Otherwise, search for a linker script in a -# standard location. - -ifndef LDSCRIPT - #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug - ifdef CONFIG_SYS_LDSCRIPT - # need to strip off double quotes - LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT)) - endif -endif - -ifndef LDSCRIPT - ifeq ($(CONFIG_NAND_U_BOOT),y) - LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds - ifeq ($(wildcard $(LDSCRIPT)),) - LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds - endif - endif - ifeq ($(wildcard $(LDSCRIPT)),) - LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds - endif - ifeq ($(wildcard $(LDSCRIPT)),) - LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot.lds - endif - ifeq ($(wildcard $(LDSCRIPT)),) -$(error could not find linker script) - endif -endif - OBJCFLAGS += --gap-fill=0xff gccincdir := $(shell $(CC) -print-file-name=include) CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ -D__KERNEL__ + +# Enable garbage collection of un-used sections for SPL +ifeq ($(CONFIG_SPL_BUILD),y) +CPPFLAGS += -ffunction-sections -fdata-sections +LDFLAGS_FINAL += --gc-sections +endif + ifneq ($(CONFIG_SYS_TEXT_BASE),) CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) endif +ifneq ($(CONFIG_SPL_TEXT_BASE),) +CPPFLAGS += -DCONFIG_SPL_TEXT_BASE=$(CONFIG_SPL_TEXT_BASE) +endif + +ifeq ($(CONFIG_SPL_BUILD),y) +CPPFLAGS += -DCONFIG_SPL_BUILD +endif + ifneq ($(RESET_VECTOR_ADDRESS),) CPPFLAGS += -DRESET_VECTOR_ADDRESS=$(RESET_VECTOR_ADDRESS) endif @@ -214,6 +211,10 @@ CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes endif CFLAGS += $(call cc-option,-fno-stack-protector) +# Some toolchains enable security related warning flags by default, +# but they don't make much sense in the u-boot world, so disable them. +CFLAGS += $(call cc-option,-Wno-format-nonliteral) +CFLAGS += $(call cc-option,-Wno-format-security) # $(CPPFLAGS) sets -g, which causes gcc to pass a suitable -g<format> # option to the assembler. @@ -236,6 +237,11 @@ ifneq ($(CONFIG_SYS_TEXT_BASE),) LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE) endif +LDFLAGS_u-boot-spl += -T $(obj)u-boot-spl.lds $(LDFLAGS_FINAL) +ifneq ($(CONFIG_SPL_TEXT_BASE),) +LDFLAGS_u-boot-spl += -Ttext $(CONFIG_SPL_TEXT_BASE) +endif + # Location of a usable BFD library, where we define "usable" as # "built for ${HOST}, supports ${TARGET}". Sensible values are # - When cross-compiling: the root of the cross-environment diff --git a/disk/Makefile b/disk/Makefile index 17266a2..5affe34 100644 --- a/disk/Makefile +++ b/disk/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libdisk.o -COBJS-y += part.o +COBJS-$(CONFIG_PARTITIONS) += part.o COBJS-$(CONFIG_MAC_PARTITION) += part_mac.o COBJS-$(CONFIG_DOS_PARTITION) += part_dos.o COBJS-$(CONFIG_ISO_PARTITION) += part_iso.o diff --git a/disk/part_dos.c b/disk/part_dos.c index 2de1bb8..b5bcb37 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -87,7 +87,7 @@ static int test_block_type(unsigned char *buffer) int test_part_dos (block_dev_desc_t *dev_desc) { - unsigned char buffer[DEFAULT_SECTOR_SIZE]; + unsigned char buffer[dev_desc->blksz]; if ((dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) buffer) != 1) || (buffer[DOS_PART_MAGIC_OFFSET + 0] != 0x55) || @@ -102,7 +102,7 @@ int test_part_dos (block_dev_desc_t *dev_desc) static void print_partition_extended (block_dev_desc_t *dev_desc, int ext_part_sector, int relative, int part_num) { - unsigned char buffer[DEFAULT_SECTOR_SIZE]; + unsigned char buffer[dev_desc->blksz]; dos_partition_t *pt; int i; @@ -166,7 +166,7 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part int relative, int part_num, int which_part, disk_partition_t *info) { - unsigned char buffer[DEFAULT_SECTOR_SIZE]; + unsigned char buffer[dev_desc->blksz]; dos_partition_t *pt; int i; diff --git a/disk/part_dos.h b/disk/part_dos.h index 195a32c..de75542 100644 --- a/disk/part_dos.h +++ b/disk/part_dos.h @@ -25,13 +25,6 @@ #define _DISK_PART_DOS_H -#ifdef CONFIG_ISO_PARTITION -/* Make the buffers bigger if ISO partition support is enabled -- CD-ROMS - have 2048 byte blocks */ -#define DEFAULT_SECTOR_SIZE 2048 -#else -#define DEFAULT_SECTOR_SIZE 512 -#endif #define DOS_PART_TBL_OFFSET 0x1be #define DOS_PART_MAGIC_OFFSET 0x1fe #define DOS_PBR_FSTYPE_OFFSET 0x36 diff --git a/doc/README.SPL b/doc/README.SPL new file mode 100644 index 0000000..ce8e19f --- /dev/null +++ b/doc/README.SPL @@ -0,0 +1,62 @@ +Generic SPL framework +===================== + +Overview +-------- + +To unify all existing implementations for a secondary program loader (SPL) +and to allow simply adding of new implementations this generic SPL framework +has been created. With this framework almost all source files for a board +can be reused. No code duplication or symlinking is necessary anymore. + + +How it works +------------ + +There is a new directory TOPDIR/spl which contains only a Makefile. +The object files are built separately for SPL and placed in this directory. +The final binaries which are generated are u-boot-spl, u-boot-spl.bin and +u-boot-spl.map. + +During the SPL build a variable named CONFIG_SPL_BUILD is exported +in the make environment and also appended to CPPFLAGS with -DCONFIG_SPL_BUILD. +Source files can therefore be compiled for SPL with different settings. +ARM-based boards have previously used the option CONFIG_PRELOADER for it. + +For example: + +ifeq ($(CONFIG_SPL_BUILD),y) +COBJS-y += board_spl.o +else +COBJS-y += board.o +endif + +COBJS-$(CONFIG_SPL_BUILD) += foo.o + +#ifdef CONFIG_SPL_BUILD + foo(); +#endif + + +The building of SPL images can be with: + +#define CONFIG_SPL + +Because SPL images normally have a different text base, one have to be +configured by defining CONFIG_SPL_TEXT_BASE. The linker script have to be +defined with CONFIG_SPL_LDSCRIPT. + +To support generic U-Boot libraries and drivers in the SPL binary one can +optionally define CONFIG_SPL_XXX_SUPPORT. Currently following options +are supported: + +CONFIG_SPL_LIBCOMMON_SUPPORT (common/libcommon.o) +CONFIG_SPL_LIBDISK_SUPPORT (disk/libdisk.o) +CONFIG_SPL_I2C_SUPPORT (drivers/i2c/libi2c.o) +CONFIG_SPL_GPIO_SUPPORT (drivers/gpio/libgpio.o) +CONFIG_SPL_MMC_SUPPORT (drivers/mmc/libmmc.o) +CONFIG_SPL_SERIAL_SUPPORT (drivers/serial/libserial.o) +CONFIG_SPL_SPI_FLASH_SUPPORT (drivers/mtd/spi/libspi_flash.o) +CONFIG_SPL_SPI_SUPPORT (drivers/spi/libspi.o) +CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o) +CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o) diff --git a/doc/README.at91-soc b/doc/README.at91-soc index 425fc58..ed6e76a 100644 --- a/doc/README.at91-soc +++ b/doc/README.at91-soc @@ -40,25 +40,3 @@ The method for updating 4. Convert arch, driver and boards file to new SoC 5. remove legacy code, if all boards and drives are ready - Join AT91 and AT91RM9200 SoC -============================== - -Approximately 95 percent of AT91 and AT91RM9200 SoC parts are the same. -So, we should use the chance, to join both archs togetter. - -To do this follow step needed: - -1. change Makefile - @$(MKCONFIG) $(@:_config=) arm arm920t board vendor at91rm9200 - to - @$(MKCONFIG) $(@:_config=) arm arm920t board vendor at91 -2. remove CONFIG_AT91_LEGACY in board config -3. convert boards file to new SoC access -4. convert or change drivers - -To support the joining process, a new SoC dir (at91) has been adding to -arm920t arch directory. This directory contains files like at91rm9200 dir, but -uses the new c structure Soc access. The advantage of this is, we don't merge -old Soc access code and new code while the board are not converted. -Finally we can delete the whole at91rm9200 dir, if all board support the -new AT91-SoC access. diff --git a/doc/README.fsl-hwconfig b/doc/README.fsl-hwconfig index 03fea74..e752505 100644 --- a/doc/README.fsl-hwconfig +++ b/doc/README.fsl-hwconfig @@ -19,3 +19,28 @@ audclk 'audclk:12' Select the 12.288MHz clock + +usb + Specific to boards have USB controller + + This option specifies the following for a USB controller: + + - which controller mode to use + - which USB PHY to use + + This is used by generic USB device-tree fixup function to update + modified values of phy type and controller mode. + + Also used for configuring multiple USB controllers such that + 'usbN' (where N is 1, 2, etc. refers to controller no.) + + 'phy_type' + Select USB phy type: 'utmi' OR 'ulpi' + + 'dr_mode' + Select USB controller mode: 'host', 'peripheral' OR 'otg' + + Examples: + usb1:dr_mode=host;usb2:dr_mode=peripheral' + + usb1:dr_mode=host,phy_type=utmi;usb2:dr_mode=host' diff --git a/doc/README.m68k b/doc/README.m68k index 3766b33..c85febc 100644 --- a/doc/README.m68k +++ b/doc/README.m68k @@ -111,7 +111,7 @@ CONFIG_SYS_MBAR -- defines the base address of the MCF5272 configuration registe CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5272 internal SRAM CONFIG_SYS_ENET_BD_BASE - -- defines the base addres of the FEC buffer descriptors + -- defines the base address of the FEC buffer descriptors CONFIG_SYS_SCR -- defines the contents of the System Configuration Register CONFIG_SYS_SPR -- defines the contents of the System Protection Register @@ -138,7 +138,7 @@ CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_INT_FLASH_BASE -- defines the base address of the MCF5282 internal Flash memory CONFIG_SYS_ENET_BD_BASE - -- defines the base addres of the FEC buffer descriptors + -- defines the base address of the FEC buffer descriptors CONFIG_SYS_MFD -- defines the PLL Multiplication Factor Devider diff --git a/doc/README.mergerbox b/doc/README.mergerbox new file mode 100644 index 0000000..1994b65 --- /dev/null +++ b/doc/README.mergerbox @@ -0,0 +1,59 @@ +Matrix Vision MergerBox +----------------------- + +1. Board Description + + The MergerBox is a 120x160mm single board computing platform + for 3D Full-HD digital video processing. + + Power Supply is 10-32VDC. + +2 System Components + +2.1 CPU + Freescale MPC8377 CPU running at 800MHz core and 333MHz csb. + 256 MByte DDR-II memory @ 333MHz data rate. + 64 MByte Nor Flash on local bus. + 1 GByte Nand Flash on FCM. + 1 Vitesse VSC8601 RGMII ethernet Phys. + 1 USB host controller over ULPI I/F with 4-Port hub. + 2 serial ports. Console running on ttyS0 @ 115200 8N1. + 1 mPCIe expansion slot (PCIe x1 + USB) used for Wifi/Bt. + 2 PCIe x1 busses on local mPCIe and cutom expansion connector. + 2 SATA host ports. + System configuration (HRCW) is taken from I2C EEPROM. + +2.2 Graphics + SM107 emebedded video controller driving a 5" 800x480 TFT panel. + Connected over 32-Bit/66MHz PCI utilizing 4 MByte embedded memory. + +2.3 FPGA + Altera Cyclone-IV EP4C115 with several PCI DMA engines. + Connects to 7x Gennum 3G-SDI transceivers as video interconnect + as well as a HDMI v1.4 compliant output for 3D monitoring. + Utilizes two more DDR-II controllers providing 256MB memory. + +2.4 I2C + Bus1: + AD7418 @ 0x50 for voltage/temp. monitoring. + SX8650 @ 0x90 touch controller for HMI. + EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. + Bus2: + mPCIe SMBus + SiI9022A @ 0x72/0xC0 HDMI transmitter. + TCA6416A @ 0x40 + 0x42 16-Bit I/O expander. + LMH1983 @ 0xCA video PLL. + DS1338C @ 0xD0 real-time clock with embedded crystal. + 9FG104 @ 0xDC 4x 100MHz LVDS SerDes reference clock. + +3 Flash layout. + + reset vector is 0x00000100, i.e. low boot. + + 00000000 u-boot binary. + 00100000 FPGA raw bit file. + 00300000 FIT image holding kernel, dtb and rescue squashfs. + 03d00000 u-boot environment. + 03e00000 splash image + + mtd partitions are propagated to linux kernel via device tree blob. diff --git a/doc/README.nand b/doc/README.nand index 8eedb6c..751b693 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -78,6 +78,16 @@ Commands: should work well, but loading an image copied from another flash is going to be trouble if there are any bad blocks. + nand write.trimffs addr ofs|partition size + Enabled by the CONFIG_CMD_NAND_TRIMFFS macro. This command will write to + the NAND flash in a manner identical to the 'nand write' command + described above -- with the additional check that all pages at the end + of eraseblocks which contain only 0xff data will not be written to the + NAND flash. This behaviour is required when flashing UBI images + containing UBIFS volumes as per the UBI FAQ[1]. + + [1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo + nand write.oob addr ofs|partition size Write `size' bytes from `addr' to the out-of-band data area corresponding to `ofs' in NAND flash. This is limited to the 16 bytes diff --git a/doc/README.p1023rds b/doc/README.p1023rds new file mode 100644 index 0000000..685f5da --- /dev/null +++ b/doc/README.p1023rds @@ -0,0 +1,101 @@ +Overview +-------- +The P1023 process includes a performance optimized implementation of the +QorIQ data Path Acceleration Architecture (DPAA). This architecture +provides the infrastructure to support simplified sharing of networking +interfaces and accelerators by multiple CPU cores. P1023 is an e500 based +dual core SOC. + +P1023RDS board is a Low End Dual core platform supporting the P1023 +processor of QorIQ series. + +Building U-boot +--------------- +To build the u-boot for P1023RDS: +Configure to NOR boot: + make P1023RDS_config +Configure to NAND boot: + make P1023RDS_NAND_config +Build: + make + +Board Switches +-------------- +Most switches on the board should not be changed. The most frequent +user-settable switches on the board are used to configure +the flash banks. + +J4: all open + +Default NOR flash boot switch setting: + Sw3[1:8]: off on on off on on off off + Sw4[1:8]: off off off on off off off off + Sw6[1:8]: off on off on off on on off + Sw7[1:8]: off on off off on off off off + Sw8[1:8]: on off off off off off off off + +For NAND flash boot,set +Sw4[1:4]: off on on on + +The default native ethernet setting is for RGMII mode. +To use SGMII mode, set +SW8[1:2]: OFF OFF +SW7[6:7]: ON ON + +Memory Map +---------- +0x0000_0000 0x7fff_ffff DDR 2G Cacheable +0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable +0xc000_0000 0xdfff_ffff PCI 512M non-cacheable +0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable + +0xe000_0000 0xe003_ffff BCSR 256K BCSR +0xee00_0000 0xefff_ffff NOR flash 32M NOR flash +0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M +0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable +0xffa0_0000 0xffaf_ffff NAND FLASH 1M non-cacheable +0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + +Flashing u-boot Images +--------------- +To program the image in the boot flash bank: +NOR flash boot: + => tftp 1000000 u-boot.bin + => protect off all + => erase eff80000 efffffff + => cp.b 1000000 eff80000 80000 + +NAND flash boot: + => tftp 1000000 u-boot-nand.bin + => nand erase 0 80000 + => nand write 1000000 0 80000 + +Firmware ucode location +--------------------------------- +Microcode(ucode) to FMAN's IRAM is needed to make FMAN Ethernet work. +u-boot loads ucode FLASH. The location for ucode: +NOR Flash: 0xfe000000 +NAND Flash: 0x1f00000 + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb p1023rds.dts > p1023rds.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/p1023rds.dts +or + make p1023rds.dtb ARCH=powerpc +in linux-2.6 directory. + +Booting Linux +------------- +Place a linux uImage in the TFTP disk area. + + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp c00000 p1023rds.dtb + bootm 1000000 2000000 c00000 diff --git a/doc/README.p2041rdb b/doc/README.p2041rdb new file mode 100644 index 0000000..292d0d3 --- /dev/null +++ b/doc/README.p2041rdb @@ -0,0 +1,123 @@ +Overview +========= +The P2041 Processor combines four Power Architecture processor cores +with high-performance datapath acceleration architecture(DPAA), CoreNet +fabric infrastructure, as well as network and peripheral bus interfaces +required for networking, telecom/datacom, wireless infrastructure, and +military/aerospace applications. + +P2041RDB board is a quad core platform supporting the P2041 processor +of QorIQ DPAA series. + +Boot from NOR flash +=================== +1. Build image + make P2041RDB_config + make all + +2. Program image + => tftp 1000000 u-boot.bin + => protect off all + => erase eff80000 efffffff + => cp.b 1000000 eff80000 80000 + +3. Program RCW + => tftp 1000000 rcw.bin + => protect off all + => erase e8000000 e801ffff + => cp.b 1000000 e8000000 50 + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => protect off all + => erase ef000000 ef0fffff + => cp.b 1000000 ef000000 2000 + +5. Change DIP-switch + SW1[1-5] = 10110 + Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SDCard +=================== +1. Build image + make P2041RDB_SDCARD_config + make all + +2. Generate PBL imge + Use PE tool to produce a image used to be programed to + SDCard which contains RCW and U-Boot image. + +3. Program the PBL image to SDCard + => tftp 1000000 pbl_sd.bin + => mmcinfo + => mmc write 1000000 8 441 + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => mmc write 1000000 46a 10 + +5. Change DIP-switch + SW1[1-5] = 01100 + Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SPI flash +=================== +1. Build image + make P2041RDB_SPIFLASH_config + make all + +2. Generate PBL imge + Use PE tool to produce a image used to be programed to + SPI flash which contains RCW and U-Boot image. + +3. Program the PBL image to SPI flash + => tftp 1000000 pbl_spi.bin + => spi probe 0 + => sf erase 0 100000 + => sf write 1000000 0 $filesize + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => sf erase 110000 10000 + => sf write 1000000 110000 $filesize + +5. Change DIP-switch + SW1[1-5] = 10100 + Note: 1 stands for 'on', 0 stands for 'off' + +CPLD command +============ +The CPLD is used to control the power sequence and some serdes lane +mux function. + +cpld reset - hard reset to default bank +cpld reset altbank - reset to alternate bank +cpld lane_mux <lane> <mux_value> - set multiplexed lane pin + lane 6: 0 -> slot1 (Default) + 1 -> SGMII + lane a: 0 -> slot2 (Default) + 1 -> AURORA + lane c: 0 -> slot2 (Default) + 1 -> SATA0 + lane d: 0 -> slot2 (Default) + 1 -> SATA1 + +Using the Device Tree Source File +================================= +To create the DTB (Device Tree Binary) image file, use a command +similar to this: + dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb + +Or use the following command: + {linux-2.6}/make p2041rdb.dtb ARCH=powerpc + +then the dtb file will be generated under the following directory: + {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb + +Booting Linux +============= +Place a linux uImage in the TFTP disk area. + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp 3000000 p2041rdb.dtb + bootm 1000000 2000000 3000000 diff --git a/doc/README.qemu_mips b/doc/README.qemu_mips index 3985264..e6a3855 100644 --- a/doc/README.qemu_mips +++ b/doc/README.qemu_mips @@ -24,7 +24,7 @@ you can downland #config to build the kernel qemu_mips_defconfig -#patch to fix mips interupt init on 2.6.24.y kernel +#patch to fix mips interrupt init on 2.6.24.y kernel qemu_mips_kernel.patch initrd.gz vmlinux diff --git a/doc/README.scrapyard b/doc/README.scrapyard index d7bf9a7..4cb727f 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,11 +11,12 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +trab arm S3C2400 - 2011-05-01 Gary Jennejohn <garyj@denx.de> xsengine ARM PXA2xx 4262a7c 2010-10-20 wepep250 ARM PXA2xx 7369478 2010-10-20 Peter Figuli <peposh@etc.sk> delta ARM PXA2xx 75e2035 2010-10-20 mp2usb ARM AT91RM2900 ee986e2 2011-01-25 Eric Bénard <eric@eukrea.com> -barco powerpc MPC8245 - 2010-11-23 Marc Leeman <marc.leeman@barco.com> +barco powerpc MPC8245 afaa27b 2010-11-23 Marc Leeman <marc.leeman@barco.com> ERIC powerpc 405GP d9ba451 2010-11-21 Swen Anderson <sand@peppercon.de> VoVPN-GW_100MHz powerpc MPC8260 26fe3d2 2010-10-24 Juergen Selent <j.selent@elmeg.de> NC650 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk <wd@denx.de> diff --git a/doc/README.ublimage b/doc/README.ublimage new file mode 100644 index 0000000..add24d6 --- /dev/null +++ b/doc/README.ublimage @@ -0,0 +1,141 @@ +--------------------------------------------- +UBL image Boot Image generation using mkimage +--------------------------------------------- + +This document describes how to set up an U-Boot image that can be directly +booted by a DaVinci processor via NAND boot mode, using an UBL header, +but without need for UBL. + +For more details see section 11.2 "ARM ROM Boot Modes" of +http://focus.ti.com/lit/ug/sprufg5a/sprufg5a.pdf + +Command syntax: +-------------- +./tools/mkimage -l <u-boot_file> + to list the UBL image file details + +./tools/mkimage -T ublimage \ + -n <board specific configuration file> \ + -d <u-boot binary> <output image file> + +For example, for the davinci dm365evm board: +./tools/mkimage -n ./board/davinci/dm365evm/ublimage.cfg \ + -T ublimage \ + -d u-boot-nand.bin u-boot.ubl + +You can generate the image directly when you compile u-boot with: + +$ make u-boot.ubl + +The output image can be flashed into the NAND. + +Please check the DaVinci documentation for further details. + +Board specific configuration file specifications: +------------------------------------------------- +1. This file must present in the $(BOARDDIR) and the name should be + ublimage.cfg (since this is used in Makefile). +2. This file can have empty lines and lines starting with "#" as first + character to put comments. +3. This file can have configuration command lines as mentioned below, + any other information in this file is treated as invalid. + +Configuration command line syntax: +--------------------------------- +1. Each command line must have two strings, first one command or address + and second one data string +2. Following are the valid command strings and associated data strings:- + Command string data string + -------------- ----------- + MODE UBL special mode, on of: + safe + Example: + MODE safe + + ENTRY Entry point address for the user + bootloader (absolute address) = TEXT_BASE + nand_spl loader. + Example: + ENTRY 0x00000020 + + PAGES Number of pages (size of user bootloader + in number of pages) + Example: + PAGES 27 + + START_BLOCK Block number where user bootloader is present + Example: + START_BLOCK 5 + + START_PAGE Page number where user bootloader is present + (for RBL always 0) + Example: + START_PAGE 0 + +------------------------------------------------ + +Structure of the u-boot.ubl binary: + +compile steps: + +1) nand_spl code compile, with pad_to = (TEXT_BASE + + (CONFIG_SYS_NROF_PAGES_NAND_SPL * pagesize)) + Example: cam_enc_4xx pad_to = 0x20 + (6 * 0x800) = 0x3020 = 12320 + -> u-boot-spl-16k.bin + + !! TEXT_BASE = 0x20, as the RBL starts at 0x20 + +2) compile u-boot.bin ("normal" u-boot) + -> u-boot.bin + +3) create u-boot-nand.bin = u-boot-spl-16k.bin + u-boot.bin + +4) create u-boot.ubl, size = 1 page size NAND + create UBL header and paste it before u-boot.bin + +This steps are done automagically if you do a "make all" + +-> You get an u-boot.ubl binary, which you can flash + into your NAND. + +Structure of this binary (Example for the cam_enc_4xx board with a NAND +page size = 0x800): + +offset : 0x00000 | 0x800 | 0x3800 +content: UBL | nand_spl | u-boot code + Header | code | + +The NAND layout looks for example like this: + +(Example for the cam_enc_4xx board with a NAND page size = 0x800, block +size = 0x20000 and CONFIG_SYS_NROF_UBL_HEADER 5): + +offset : 0x80000 | 0xa0000 | 0xa3000 +content: UBL | nand_spl | u-boot code + Header | code | + ^ ^ + ^ 0xa0000 = CONFIG_SYS_NROF_UBL_HEADER * 0x20000 + ^ + 0x80000 = Block 4 * 0x20000 + +If the cpu starts in NAND boot mode, it checks the UBL descriptor +starting with block 1 (page 0). When a valid UBL signature is found, +the corresponding block number (from 1 to 24) is written to the last 32 +bits of ARM internal memory (0x7ffc-0x8000). This feature is provided +as a basic debug mechanism. If not found, it continues with block 2 +... last possible block is 24 + +If a valid UBL descriptor is found, the UBL descriptor is read and +processed. The descriptor gives the information required for loading +and control transfer to the nand_spl code. The nand_spl code is then +read and processed. + +Once the user-specified start-up conditions are set, the RBL copies the +nand_spl into ARM internal RAM, starting at address 0x0000: 0020. + ^^^^ + +The nand_spl code itself now does necessary intializations, and at least, +copies the u-boot code from NAND into RAM, and jumps to it ... + +------------------------------------------------ +Author: Heiko Schocher <hs@denx.de> diff --git a/doc/README.update b/doc/README.update index 48f03b7..a7f4d9e 100644 --- a/doc/README.update +++ b/doc/README.update @@ -51,6 +51,11 @@ the mkimage tool. dtc tool with support for binary includes, e.g. in version to be prepared. Refer to the doc/uImage.FIT/ directory for more details on FIT images. +This mechanism can be also triggered by the commmand "fitupd". +If an optional, non-zero address is provided as argument, the TFTP transfer +is skipped and the image at this address is used. +The fitupd command is enabled by CONFIG_CMD_FITUPD. + Example .its files ------------------ diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index a3ca2dc..64f52bb 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -78,13 +78,15 @@ static int waiting_for_cmd_completed(volatile u8 *offset, static int ahci_host_init(struct ahci_probe_ent *probe_ent) { +#ifndef CONFIG_SCSI_AHCI_PLAT pci_dev_t pdev = probe_ent->dev; + u16 tmp16; + unsigned short vendor; +#endif volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; u32 tmp, cap_save; - u16 tmp16; int i, j; volatile u8 *port_mmio; - unsigned short vendor; cap_save = readl(mmio + HOST_CAP); cap_save &= ((1 << 28) | (1 << 17)); @@ -110,6 +112,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) writel(cap_save, mmio + HOST_CAP); writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); +#ifndef CONFIG_SCSI_AHCI_PLAT pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); if (vendor == PCI_VENDOR_ID_INTEL) { @@ -118,7 +121,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) tmp16 |= 0xf; pci_write_config_word(pdev, 0x92, tmp16); } - +#endif probe_ent->cap = readl(mmio + HOST_CAP); probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; @@ -183,22 +186,24 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); tmp = readl(mmio + HOST_CTL); debug("HOST_CTL 0x%x\n", tmp); - +#ifndef CONFIG_SCSI_AHCI_PLAT pci_read_config_word(pdev, PCI_COMMAND, &tmp16); tmp |= PCI_COMMAND_MASTER; pci_write_config_word(pdev, PCI_COMMAND, tmp16); - +#endif return 0; } static void ahci_print_info(struct ahci_probe_ent *probe_ent) { +#ifndef CONFIG_SCSI_AHCI_PLAT pci_dev_t pdev = probe_ent->dev; + u16 cc; +#endif volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; u32 vers, cap, impl, speed; const char *speed_s; - u16 cc; const char *scc_s; vers = readl(mmio + HOST_VERSION); @@ -213,6 +218,9 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) else speed_s = "?"; +#ifdef CONFIG_SCSI_AHCI_PLAT + scc_s = "SATA"; +#else pci_read_config_word(pdev, 0x0a, &cc); if (cc == 0x0101) scc_s = "IDE"; @@ -222,7 +230,7 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) scc_s = "RAID"; else scc_s = "unknown"; - +#endif printf("AHCI %02x%02x.%02x%02x " "%u slots %u ports %s Gbps 0x%x impl %s mode\n", (vers >> 24) & 0xff, @@ -249,6 +257,7 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) cap & (1 << 13) ? "part " : ""); } +#ifndef CONFIG_SCSI_AHCI_PLAT static int ahci_init_one(pci_dev_t pdev) { u16 vendor; @@ -291,7 +300,7 @@ static int ahci_init_one(pci_dev_t pdev) err_out: return rc; } - +#endif #define MAX_DATA_BYTE_COUNT (4*1024*1024) @@ -468,7 +477,7 @@ static char *ata_id_strcpy(u16 *target, u16 *src, int len) { int i; for (i = 0; i < len / 2; i++) - target[i] = le16_to_cpu(src[i]); + target[i] = swab16(src[i]); return (char *)target; } @@ -667,7 +676,9 @@ void scsi_low_level_init(int busdevfunc) int i; u32 linkmap; +#ifndef CONFIG_SCSI_AHCI_PLAT ahci_init_one(busdevfunc); +#endif linkmap = probe_ent->link_port_map; @@ -682,6 +693,49 @@ void scsi_low_level_init(int busdevfunc) } } +#ifdef CONFIG_SCSI_AHCI_PLAT +int ahci_init(u32 base) +{ + int i, rc = 0; + u32 linkmap; + + memset(ataid, 0, sizeof(ataid)); + + probe_ent = malloc(sizeof(struct ahci_probe_ent)); + memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); + + probe_ent->host_flags = ATA_FLAG_SATA + | ATA_FLAG_NO_LEGACY + | ATA_FLAG_MMIO + | ATA_FLAG_PIO_DMA + | ATA_FLAG_NO_ATAPI; + probe_ent->pio_mask = 0x1f; + probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ + + probe_ent->mmio_base = base; + + /* initialize adapter */ + rc = ahci_host_init(probe_ent); + if (rc) + goto err_out; + + ahci_print_info(probe_ent); + + linkmap = probe_ent->link_port_map; + + for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { + if (((linkmap >> i) & 0x01)) { + if (ahci_port_start((u8) i)) { + printf("Can not start port %d\n", i); + continue; + } + ahci_set_feature((u8) i); + } + } +err_out: + return rc; +} +#endif void scsi_bus_reset(void) { diff --git a/drivers/block/mg_disk.c b/drivers/block/mg_disk.c index b74307a..4407006 100644 --- a/drivers/block/mg_disk.c +++ b/drivers/block/mg_disk.c @@ -91,7 +91,9 @@ static unsigned int mg_wait (u32 expect, u32 msec) u32 from, cur, err; err = MG_ERR_NONE; +#ifdef CONFIG_SYS_LOW_RES_TIMER reset_timer(); +#endif from = get_timer(0); status = readb(mg_base() + MG_REG_STATUS); @@ -522,10 +524,12 @@ mg_write_exit: return err; } +#ifdef CONFIG_PARTITIONS block_dev_desc_t *mg_disk_get_dev(int dev) { return ((block_dev_desc_t *) & mg_disk_dev); } +#endif /* must override this function */ struct mg_drv_data * __attribute__((weak)) mg_get_drv_data (void) diff --git a/drivers/block/systemace.c b/drivers/block/systemace.c index e8dff0a..58402b9 100644 --- a/drivers/block/systemace.c +++ b/drivers/block/systemace.c @@ -104,6 +104,7 @@ static void release_cf_lock(void) ace_writew((val & 0xffff), 0x18); } +#ifdef CONFIG_PARTITIONS block_dev_desc_t *systemace_get_dev(int dev) { /* The first time through this, the systemace_dev object is @@ -128,6 +129,7 @@ block_dev_desc_t *systemace_get_dev(int dev) return &systemace_dev; } +#endif /* * This function is called (by dereferencing the block_read pointer in diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c index 09c18c1..30785ec 100644 --- a/drivers/dma/fsl_dma.c +++ b/drivers/dma/fsl_dma.c @@ -116,10 +116,12 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) { out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF)); out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF)); +#if !defined(CONFIG_MPC83xx) out_dma32(&dma->satr, in_dma32(&dma->satr) | (u32)((u64)src >> 32)); out_dma32(&dma->datr, in_dma32(&dma->datr) | (u32)((u64)dest >> 32)); +#endif out_dma32(&dma->bcr, xfer_size); dma_sync(); diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c index 06b4247..4703fc1 100644 --- a/drivers/fpga/ACEX1K.c +++ b/drivers/fpga/ACEX1K.c @@ -48,13 +48,13 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ #endif -static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize ); -static int ACEX1K_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); -/* static int ACEX1K_ps_info( Altera_desc *desc ); */ +static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize); +static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize); +/* static int ACEX1K_ps_info(Altera_desc *desc); */ /* ------------------------------------------------------------------------- */ /* ACEX1K Generic Implementation */ -int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize) +int ACEX1K_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -74,7 +74,7 @@ int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize) return ret_val; } -int ACEX1K_dump (Altera_desc * desc, void *buf, size_t bsize) +int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -103,7 +103,7 @@ int ACEX1K_info( Altera_desc *desc ) /* ------------------------------------------------------------------------- */ /* ACEX1K Passive Serial Generic Implementation */ -static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize) +static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns; @@ -256,7 +256,7 @@ static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize) return ret_val; } -static int ACEX1K_ps_dump (Altera_desc * desc, void *buf, size_t bsize) +static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 650f2ec..f087d01 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -45,7 +45,7 @@ static int altera_validate (Altera_desc * desc, const char *fn); /* ------------------------------------------------------------------------- */ -int altera_load( Altera_desc *desc, void *buf, size_t bsize ) +int altera_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ @@ -60,7 +60,7 @@ int altera_load( Altera_desc *desc, void *buf, size_t bsize ) __FUNCTION__); ret_val = ACEX1K_load (desc, buf, bsize); #elif defined(CONFIG_FPGA_CYCLON2) - PRINTF ("%s: Launching the CYCLON II Loader...\n", + PRINTF ("%s: Launching the CYCLONE II Loader...\n", __FUNCTION__); ret_val = CYC2_load (desc, buf, bsize); #else @@ -85,7 +85,7 @@ int altera_load( Altera_desc *desc, void *buf, size_t bsize ) return ret_val; } -int altera_dump( Altera_desc *desc, void *buf, size_t bsize ) +int altera_dump(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index 4622b4e..26494a3 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -47,13 +47,13 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ #endif -static int CYC2_ps_load( Altera_desc *desc, void *buf, size_t bsize ); -static int CYC2_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); +static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize); +static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize); /* static int CYC2_ps_info( Altera_desc *desc ); */ /* ------------------------------------------------------------------------- */ /* CYCLON2 Generic Implementation */ -int CYC2_load (Altera_desc * desc, void *buf, size_t bsize) +int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -63,6 +63,16 @@ int CYC2_load (Altera_desc * desc, void *buf, size_t bsize) ret_val = CYC2_ps_load (desc, buf, bsize); break; + case fast_passive_parallel: + /* Fast Passive Parallel (FPP) and PS only differ in what is + * done in the write() callback. Use the existing PS load + * function for FPP, too. + */ + PRINTF ("%s: Launching Fast Passive Parallel Loader\n", + __FUNCTION__); + ret_val = CYC2_ps_load(desc, buf, bsize); + break; + /* Add new interface types here */ default: @@ -73,7 +83,7 @@ int CYC2_load (Altera_desc * desc, void *buf, size_t bsize) return ret_val; } -int CYC2_dump (Altera_desc * desc, void *buf, size_t bsize) +int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -100,7 +110,7 @@ int CYC2_info( Altera_desc *desc ) /* ------------------------------------------------------------------------- */ /* CYCLON2 Passive Serial Generic Implementation */ -static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize) +static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns; @@ -200,7 +210,7 @@ static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize) return ret_val; } -static int CYC2_ps_dump (Altera_desc * desc, void *buf, size_t bsize) +static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index a669039..26d2443 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -52,7 +52,7 @@ static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES]; /* Local static functions */ static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum ); -static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate( int devnum, void *buf, +static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf, size_t bsize, char *fn ); static int fpga_dev_info( int devnum ); @@ -94,7 +94,7 @@ static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_ge /* fpga_validate * generic parameter checking code */ -static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate( int devnum, void *buf, +static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf, size_t bsize, char *fn ) { fpga_desc * desc = fpga_get_desc( devnum ); @@ -212,7 +212,7 @@ int fpga_add( fpga_type devtype, void *desc ) /* * Generic multiplexing code */ -int fpga_load( int devnum, void *buf, size_t bsize ) +int fpga_load(int devnum, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume failure */ fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ ); @@ -252,7 +252,7 @@ int fpga_load( int devnum, void *buf, size_t bsize ) /* fpga_dump * generic multiplexing code */ -int fpga_dump( int devnum, void *buf, size_t bsize ) +int fpga_dump(int devnum, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume failure */ fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ ); diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index cd16a9c..4bc7070 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -48,17 +48,17 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int Spartan2_sp_load( Xilinx_desc *desc, void *buf, size_t bsize ); -static int Spartan2_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -/* static int Spartan2_sp_info( Xilinx_desc *desc ); */ +static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int Spartan2_sp_info(Xilinx_desc *desc ); */ -static int Spartan2_ss_load( Xilinx_desc *desc, void *buf, size_t bsize ); -static int Spartan2_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -/* static int Spartan2_ss_info( Xilinx_desc *desc ); */ +static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int Spartan2_ss_info(Xilinx_desc *desc ); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int Spartan2_load (Xilinx_desc * desc, void *buf, size_t bsize) +int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -81,7 +81,7 @@ int Spartan2_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -int Spartan2_dump (Xilinx_desc * desc, void *buf, size_t bsize) +int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -113,7 +113,7 @@ int Spartan2_info( Xilinx_desc *desc ) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int Spartan2_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; @@ -265,7 +265,7 @@ static int Spartan2_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -static int Spartan2_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; @@ -313,7 +313,7 @@ static int Spartan2_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns; @@ -456,7 +456,7 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 1dd6f26..9207391 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -53,17 +53,17 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int Spartan3_sp_load( Xilinx_desc *desc, void *buf, size_t bsize ); -static int Spartan3_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -/* static int Spartan3_sp_info( Xilinx_desc *desc ); */ +static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int Spartan3_sp_info(Xilinx_desc *desc ); */ -static int Spartan3_ss_load( Xilinx_desc *desc, void *buf, size_t bsize ); -static int Spartan3_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -/* static int Spartan3_ss_info( Xilinx_desc *desc ); */ +static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int Spartan3_ss_info(Xilinx_desc *desc); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize) +int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -86,7 +86,7 @@ int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -int Spartan3_dump (Xilinx_desc * desc, void *buf, size_t bsize) +int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -118,7 +118,7 @@ int Spartan3_info( Xilinx_desc *desc ) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; @@ -272,7 +272,7 @@ static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; @@ -320,7 +320,7 @@ static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns; @@ -475,7 +475,7 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -static int Spartan3_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index d1b4d15..b26d231 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -101,13 +101,13 @@ #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */ #endif -static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize); -static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize); +static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize); -static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize); +static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize) +int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -129,7 +129,7 @@ int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -int Virtex2_dump (Xilinx_desc * desc, void *buf, size_t bsize) +int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -170,7 +170,7 @@ int Virtex2_info (Xilinx_desc * desc) * INIT_B and DONE lines. If both are high, configuration has * succeeded. Congratulations! */ -static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize) +static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; @@ -369,7 +369,7 @@ static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize) /* * Read the FPGA configuration data */ -static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize) +static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; @@ -421,13 +421,13 @@ static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) +static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); return FPGA_FAIL; } -static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) +static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); return FPGA_FAIL; diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 08dfdec..4072cb4 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -48,7 +48,7 @@ static int xilinx_validate (Xilinx_desc * desc, char *fn); /* ------------------------------------------------------------------------- */ -int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize) +int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ @@ -95,7 +95,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize) +int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index a5fa2b5..62ec97d 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -31,6 +31,8 @@ COBJS-$(CONFIG_MARVELL_MFP) += mvmfp.o COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o COBJS-$(CONFIG_S5P) += s5p_gpio.o +COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o +COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/gpio/da8xx_gpio.c b/drivers/gpio/da8xx_gpio.c new file mode 100644 index 0000000..0308223 --- /dev/null +++ b/drivers/gpio/da8xx_gpio.c @@ -0,0 +1,281 @@ +/* + * GPIO driver for TI DaVinci DA8xx SOCs. + * + * (C) Copyright 2011 Guralp Systems Ltd. + * Laurence Withers <lwithers@guralp.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/gpio.h> +#include <asm/arch/hardware.h> +#include <asm/arch/davinci_misc.h> + + +static struct gpio_registry { + int is_registered; + char name[GPIO_NAME_SIZE]; +} gpio_registry[MAX_NUM_GPIOS]; + + +#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) + +static const struct pinmux_config gpio_pinmux[] = { + { pinmux(1), 8, 7 }, /* GP0[0] */ + { pinmux(1), 8, 6 }, + { pinmux(1), 8, 5 }, + { pinmux(1), 8, 4 }, + { pinmux(1), 8, 3 }, + { pinmux(1), 8, 2 }, + { pinmux(1), 8, 1 }, + { pinmux(1), 8, 0 }, + { pinmux(0), 8, 7 }, + { pinmux(0), 8, 6 }, + { pinmux(0), 8, 5 }, + { pinmux(0), 8, 4 }, + { pinmux(0), 8, 3 }, + { pinmux(0), 8, 2 }, + { pinmux(0), 8, 1 }, + { pinmux(0), 8, 0 }, + { pinmux(4), 8, 7 }, /* GP1[0] */ + { pinmux(4), 8, 6 }, + { pinmux(4), 8, 5 }, + { pinmux(4), 8, 4 }, + { pinmux(4), 8, 3 }, + { pinmux(4), 8, 2 }, + { pinmux(4), 4, 1 }, + { pinmux(4), 4, 0 }, + { pinmux(3), 4, 0 }, + { pinmux(2), 4, 6 }, + { pinmux(2), 4, 5 }, + { pinmux(2), 4, 4 }, + { pinmux(2), 4, 3 }, + { pinmux(2), 4, 2 }, + { pinmux(2), 4, 1 }, + { pinmux(2), 8, 0 }, + { pinmux(6), 8, 7 }, /* GP2[0] */ + { pinmux(6), 8, 6 }, + { pinmux(6), 8, 5 }, + { pinmux(6), 8, 4 }, + { pinmux(6), 8, 3 }, + { pinmux(6), 8, 2 }, + { pinmux(6), 8, 1 }, + { pinmux(6), 8, 0 }, + { pinmux(5), 8, 7 }, + { pinmux(5), 8, 6 }, + { pinmux(5), 8, 5 }, + { pinmux(5), 8, 4 }, + { pinmux(5), 8, 3 }, + { pinmux(5), 8, 2 }, + { pinmux(5), 8, 1 }, + { pinmux(5), 8, 0 }, + { pinmux(8), 8, 7 }, /* GP3[0] */ + { pinmux(8), 8, 6 }, + { pinmux(8), 8, 5 }, + { pinmux(8), 8, 4 }, + { pinmux(8), 8, 3 }, + { pinmux(8), 8, 2 }, + { pinmux(8), 8, 1 }, + { pinmux(8), 8, 0 }, + { pinmux(7), 8, 7 }, + { pinmux(7), 8, 6 }, + { pinmux(7), 8, 5 }, + { pinmux(7), 8, 4 }, + { pinmux(7), 8, 3 }, + { pinmux(7), 8, 2 }, + { pinmux(7), 8, 1 }, + { pinmux(7), 8, 0 }, + { pinmux(10), 8, 7 }, /* GP4[0] */ + { pinmux(10), 8, 6 }, + { pinmux(10), 8, 5 }, + { pinmux(10), 8, 4 }, + { pinmux(10), 8, 3 }, + { pinmux(10), 8, 2 }, + { pinmux(10), 8, 1 }, + { pinmux(10), 8, 0 }, + { pinmux(9), 8, 7 }, + { pinmux(9), 8, 6 }, + { pinmux(9), 8, 5 }, + { pinmux(9), 8, 4 }, + { pinmux(9), 8, 3 }, + { pinmux(9), 8, 2 }, + { pinmux(9), 8, 1 }, + { pinmux(9), 8, 0 }, + { pinmux(12), 8, 7 }, /* GP5[0] */ + { pinmux(12), 8, 6 }, + { pinmux(12), 8, 5 }, + { pinmux(12), 8, 4 }, + { pinmux(12), 8, 3 }, + { pinmux(12), 8, 2 }, + { pinmux(12), 8, 1 }, + { pinmux(12), 8, 0 }, + { pinmux(11), 8, 7 }, + { pinmux(11), 8, 6 }, + { pinmux(11), 8, 5 }, + { pinmux(11), 8, 4 }, + { pinmux(11), 8, 3 }, + { pinmux(11), 8, 2 }, + { pinmux(11), 8, 1 }, + { pinmux(11), 8, 0 }, + { pinmux(19), 8, 6 }, /* GP6[0] */ + { pinmux(19), 8, 5 }, + { pinmux(19), 8, 4 }, + { pinmux(19), 8, 3 }, + { pinmux(19), 8, 2 }, + { pinmux(16), 8, 1 }, + { pinmux(14), 8, 1 }, + { pinmux(14), 8, 0 }, + { pinmux(13), 8, 7 }, + { pinmux(13), 8, 6 }, + { pinmux(13), 8, 5 }, + { pinmux(13), 8, 4 }, + { pinmux(13), 8, 3 }, + { pinmux(13), 8, 2 }, + { pinmux(13), 8, 1 }, + { pinmux(13), 8, 0 }, + { pinmux(18), 8, 1 }, /* GP7[0] */ + { pinmux(18), 8, 0 }, + { pinmux(17), 8, 7 }, + { pinmux(17), 8, 6 }, + { pinmux(17), 8, 5 }, + { pinmux(17), 8, 4 }, + { pinmux(17), 8, 3 }, + { pinmux(17), 8, 2 }, + { pinmux(17), 8, 1 }, + { pinmux(17), 8, 0 }, + { pinmux(16), 8, 7 }, + { pinmux(16), 8, 6 }, + { pinmux(16), 8, 5 }, + { pinmux(16), 8, 4 }, + { pinmux(16), 8, 3 }, + { pinmux(16), 8, 2 }, + { pinmux(19), 8, 0 }, /* GP8[0] */ + { pinmux(3), 4, 7 }, + { pinmux(3), 4, 6 }, + { pinmux(3), 4, 5 }, + { pinmux(3), 4, 4 }, + { pinmux(3), 4, 3 }, + { pinmux(3), 4, 2 }, + { pinmux(2), 4, 7 }, + { pinmux(19), 8, 1 }, + { pinmux(19), 8, 0 }, + { pinmux(18), 8, 7 }, + { pinmux(18), 8, 6 }, + { pinmux(18), 8, 5 }, + { pinmux(18), 8, 4 }, + { pinmux(18), 8, 3 }, + { pinmux(18), 8, 2 }, +}; + + + +int gpio_request(int gp, const char *label) +{ + if (gp >= MAX_NUM_GPIOS) + return -1; + + if (gpio_registry[gp].is_registered) + return -1; + + gpio_registry[gp].is_registered = 1; + strncpy(gpio_registry[gp].name, label, GPIO_NAME_SIZE); + gpio_registry[gp].name[GPIO_NAME_SIZE - 1] = 0; + + davinci_configure_pin_mux(&gpio_pinmux[gp], 1); + + return 0; +} + + +void gpio_free(int gp) +{ + gpio_registry[gp].is_registered = 0; +} + + +void gpio_toggle_value(int gp) +{ + struct davinci_gpio *bank; + + bank = GPIO_BANK(gp); + gpio_set_value(gp, !gpio_get_value(gp)); +} + + +int gpio_direction_input(int gp) +{ + struct davinci_gpio *bank; + + bank = GPIO_BANK(gp); + setbits_le32(&bank->dir, 1U << GPIO_BIT(gp)); + return 0; +} + + +int gpio_direction_output(int gp, int value) +{ + struct davinci_gpio *bank; + + bank = GPIO_BANK(gp); + clrbits_le32(&bank->dir, 1U << GPIO_BIT(gp)); + gpio_set_value(gp, value); + return 0; +} + + +int gpio_get_value(int gp) +{ + struct davinci_gpio *bank; + unsigned int ip; + + bank = GPIO_BANK(gp); + ip = in_le32(&bank->in_data) & (1U << GPIO_BIT(gp)); + return ip ? 1 : 0; +} + + +void gpio_set_value(int gp, int value) +{ + struct davinci_gpio *bank; + + bank = GPIO_BANK(gp); + + if (value) + bank->set_data = 1U << GPIO_BIT(gp); + else + bank->clr_data = 1U << GPIO_BIT(gp); +} + + +void gpio_info(void) +{ + int gp, dir, val; + struct davinci_gpio *bank; + + for (gp = 0; gp < MAX_NUM_GPIOS; ++gp) { + bank = GPIO_BANK(gp); + dir = in_le32(&bank->dir) & (1U << GPIO_BIT(gp)); + val = gpio_get_value(gp); + + printf("% 4d: %s: %d [%c] %s\n", + gp, dir ? " in" : "out", val, + gpio_registry[gp].is_registered ? 'x' : ' ', + gpio_registry[gp].name); + } +} diff --git a/drivers/gpio/tegra2_gpio.c b/drivers/gpio/tegra2_gpio.c new file mode 100644 index 0000000..f686e80 --- /dev/null +++ b/drivers/gpio/tegra2_gpio.c @@ -0,0 +1,255 @@ +/* + * NVIDIA Tegra2 GPIO handling. + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver. + * Tom Warren (twarren@nvidia.com) + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/bitops.h> +#include <asm/arch/tegra2.h> +#include <asm/gpio.h> + +enum { + TEGRA2_CMD_INFO, + TEGRA2_CMD_PORT, + TEGRA2_CMD_OUTPUT, + TEGRA2_CMD_INPUT, +}; + +static struct gpio_names { + char name[GPIO_NAME_SIZE]; +} gpio_names[MAX_NUM_GPIOS]; + +static char *get_name(int i) +{ + return *gpio_names[i].name ? gpio_names[i].name : "UNKNOWN"; +} + +/* Return config of pin 'gp' as GPIO (1) or SFPIO (0) */ +static int get_config(int gp) +{ + struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + u32 u; + int type; + + u = readl(&bank->gpio_config[GPIO_PORT(gp)]); + type = (u >> GPIO_BIT(gp)) & 1; + + debug("get_config: port = %d, bit = %d is %s\n", + GPIO_FULLPORT(gp), GPIO_BIT(gp), type ? "GPIO" : "SFPIO"); + + return type; +} + +/* Config pin 'gp' as GPIO or SFPIO, based on 'type' */ +static void set_config(int gp, int type) +{ + struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + u32 u; + + debug("set_config: port = %d, bit = %d, %s\n", + GPIO_FULLPORT(gp), GPIO_BIT(gp), type ? "GPIO" : "SFPIO"); + + u = readl(&bank->gpio_config[GPIO_PORT(gp)]); + if (type) /* GPIO */ + u |= 1 << GPIO_BIT(gp); + else + u &= ~(1 << GPIO_BIT(gp)); + writel(u, &bank->gpio_config[GPIO_PORT(gp)]); +} + +/* Return GPIO pin 'gp' direction - 0 = input or 1 = output */ +static int get_direction(int gp) +{ + struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + u32 u; + int dir; + + u = readl(&bank->gpio_dir_out[GPIO_PORT(gp)]); + dir = (u >> GPIO_BIT(gp)) & 1; + + debug("get_direction: port = %d, bit = %d, %s\n", + GPIO_FULLPORT(gp), GPIO_BIT(gp), dir ? "OUT" : "IN"); + + return dir; +} + +/* Config GPIO pin 'gp' as input or output (OE) as per 'output' */ +static void set_direction(int gp, int output) +{ + struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + u32 u; + + debug("set_direction: port = %d, bit = %d, %s\n", + GPIO_FULLPORT(gp), GPIO_BIT(gp), output ? "OUT" : "IN"); + + u = readl(&bank->gpio_dir_out[GPIO_PORT(gp)]); + if (output) + u |= 1 << GPIO_BIT(gp); + else + u &= ~(1 << GPIO_BIT(gp)); + writel(u, &bank->gpio_dir_out[GPIO_PORT(gp)]); +} + +/* set GPIO pin 'gp' output bit as 0 or 1 as per 'high' */ +static void set_level(int gp, int high) +{ + struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + u32 u; + + debug("set_level: port = %d, bit %d == %d\n", + GPIO_FULLPORT(gp), GPIO_BIT(gp), high); + + u = readl(&bank->gpio_out[GPIO_PORT(gp)]); + if (high) + u |= 1 << GPIO_BIT(gp); + else + u &= ~(1 << GPIO_BIT(gp)); + writel(u, &bank->gpio_out[GPIO_PORT(gp)]); +} + +/* + * Generic_GPIO primitives. + */ + +int gpio_request(int gp, const char *label) +{ + if (gp >= MAX_NUM_GPIOS) + return -1; + + strncpy(gpio_names[gp].name, label, GPIO_NAME_SIZE); + gpio_names[gp].name[GPIO_NAME_SIZE - 1] = '\0'; + + /* Configure as a GPIO */ + set_config(gp, 1); + + return 0; +} + +void gpio_free(int gp) +{ +} + +/* read GPIO OUT value of pin 'gp' */ +static int gpio_get_output_value(int gp) +{ + struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + int val; + + debug("gpio_get_output_value: pin = %d (port %d:bit %d)\n", + gp, GPIO_FULLPORT(gp), GPIO_BIT(gp)); + + val = readl(&bank->gpio_out[GPIO_PORT(gp)]); + + return (val >> GPIO_BIT(gp)) & 1; +} + +void gpio_toggle_value(int gp) +{ + gpio_set_value(gp, !gpio_get_output_value(gp)); +} + +/* set GPIO pin 'gp' as an input */ +int gpio_direction_input(int gp) +{ + debug("gpio_direction_input: pin = %d (port %d:bit %d)\n", + gp, GPIO_FULLPORT(gp), GPIO_BIT(gp)); + + /* Configure GPIO direction as input. */ + set_direction(gp, 0); + + return 0; +} + +/* set GPIO pin 'gp' as an output, with polarity 'value' */ +int gpio_direction_output(int gp, int value) +{ + debug("gpio_direction_output: pin = %d (port %d:bit %d) = %s\n", + gp, GPIO_FULLPORT(gp), GPIO_BIT(gp), value ? "HIGH" : "LOW"); + + /* Configure GPIO output value. */ + set_level(gp, value); + + /* Configure GPIO direction as output. */ + set_direction(gp, 1); + + return 0; +} + +/* read GPIO IN value of pin 'gp' */ +int gpio_get_value(int gp) +{ + struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + int val; + + debug("gpio_get_value: pin = %d (port %d:bit %d)\n", + gp, GPIO_FULLPORT(gp), GPIO_BIT(gp)); + + val = readl(&bank->gpio_in[GPIO_PORT(gp)]); + + return (val >> GPIO_BIT(gp)) & 1; +} + +/* write GPIO OUT value to pin 'gp' */ +void gpio_set_value(int gp, int value) +{ + debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n", + gp, GPIO_FULLPORT(gp), GPIO_BIT(gp), value); + + /* Configure GPIO output value. */ + set_level(gp, value); +} + +/* + * Display Tegra GPIO information + */ +void gpio_info(void) +{ + int c, type; + + for (c = 0; c < MAX_NUM_GPIOS; c++) { + type = get_config(c); /* GPIO, not SFPIO */ + if (type) { + printf("GPIO_%d:\t%s is an %s, ", c, + get_name(c), + get_direction(c) ? "OUTPUT" : "INPUT"); + if (get_direction(c)) + printf("value = %d", gpio_get_output_value(c)); + else + printf("value = %d", gpio_get_value(c)); + printf("\n"); + } else + continue; + } +} diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 71251d8..966ffc4 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -399,7 +399,7 @@ static void wait_for_bb (void) int timeout = I2C_TIMEOUT; u16 stat; - writew(0xFFFF, &i2c_base->stat); /* clear current interruts...*/ + writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/ while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) { writew (stat, &i2c_base->stat); udelay(1000); diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index a8fe17a..3968c14 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -33,11 +33,15 @@ COBJS-$(CONFIG_GENERIC_MMC) += mmc.o COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o COBJS-$(CONFIG_MMC_SPI) += mmc_spi.o COBJS-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o +COBJS-$(CONFIG_MV_SDHCI) += mv_sdhci.o COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o COBJS-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o COBJS-$(CONFIG_S5P_MMC) += s5p_mmc.o +COBJS-$(CONFIG_SDHCI) += sdhci.o +COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o +COBJS-$(CONFIG_TEGRA2_MMC) += tegra2_mmc.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 21aedba..7e703c0 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -174,6 +174,88 @@ struct mmc *find_mmc_device(int dev_num) return NULL; } +static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt) +{ + struct mmc_cmd cmd; + ulong end; + int err, start_cmd, end_cmd; + + if (mmc->high_capacity) + end = start + blkcnt - 1; + else { + end = (start + blkcnt - 1) * mmc->write_bl_len; + start *= mmc->write_bl_len; + } + + if (IS_SD(mmc)) { + start_cmd = SD_CMD_ERASE_WR_BLK_START; + end_cmd = SD_CMD_ERASE_WR_BLK_END; + } else { + start_cmd = MMC_CMD_ERASE_GROUP_START; + end_cmd = MMC_CMD_ERASE_GROUP_END; + } + + cmd.cmdidx = start_cmd; + cmd.cmdarg = start; + cmd.resp_type = MMC_RSP_R1; + cmd.flags = 0; + + err = mmc_send_cmd(mmc, &cmd, NULL); + if (err) + goto err_out; + + cmd.cmdidx = end_cmd; + cmd.cmdarg = end; + + err = mmc_send_cmd(mmc, &cmd, NULL); + if (err) + goto err_out; + + cmd.cmdidx = MMC_CMD_ERASE; + cmd.cmdarg = SECURE_ERASE; + cmd.resp_type = MMC_RSP_R1b; + + err = mmc_send_cmd(mmc, &cmd, NULL); + if (err) + goto err_out; + + return 0; + +err_out: + puts("mmc erase failed\n"); + return err; +} + +static unsigned long +mmc_berase(int dev_num, unsigned long start, lbaint_t blkcnt) +{ + int err = 0; + struct mmc *mmc = find_mmc_device(dev_num); + lbaint_t blk = 0, blk_r = 0; + + if (!mmc) + return -1; + + if ((start % mmc->erase_grp_size) || (blkcnt % mmc->erase_grp_size)) + printf("\n\nCaution! Your devices Erase group is 0x%x\n" + "The erase range would be change to 0x%lx~0x%lx\n\n", + mmc->erase_grp_size, start & ~(mmc->erase_grp_size - 1), + ((start + blkcnt + mmc->erase_grp_size) + & ~(mmc->erase_grp_size - 1)) - 1); + + while (blk < blkcnt) { + blk_r = ((blkcnt - blk) > mmc->erase_grp_size) ? + mmc->erase_grp_size : (blkcnt - blk); + err = mmc_erase_t(mmc, start + blk, blk_r); + if (err) + break; + + blk += blk_r; + } + + return blk; +} + static ulong mmc_write_blocks(struct mmc *mmc, ulong start, lbaint_t blkcnt, const void*src) { @@ -449,6 +531,10 @@ int mmc_send_op_cond(struct mmc *mmc) (mmc->voltages & (cmd.response[0] & OCR_VOLTAGE_MASK)) | (cmd.response[0] & OCR_ACCESS_MODE)); + + if (mmc->host_caps & MMC_MODE_HC) + cmd.cmdarg |= OCR_HCS; + cmd.flags = 0; err = mmc_send_cmd(mmc, &cmd, NULL); @@ -771,7 +857,7 @@ int mmc_startup(struct mmc *mmc) { int err; uint mult, freq; - u64 cmult, csize; + u64 cmult, csize, capacity; struct mmc_cmd cmd; char ext_csd[512]; int timeout = 1000; @@ -911,14 +997,40 @@ int mmc_startup(struct mmc *mmc) return err; } + /* + * For SD, its erase group is always one sector + */ + mmc->erase_grp_size = 1; mmc->part_config = MMCPART_NOAVAILABLE; if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { /* check ext_csd version and capacity */ err = mmc_send_ext_csd(mmc, ext_csd); if (!err & (ext_csd[192] >= 2)) { - mmc->capacity = ext_csd[212] << 0 | ext_csd[213] << 8 | - ext_csd[214] << 16 | ext_csd[215] << 24; - mmc->capacity *= 512; + /* + * According to the JEDEC Standard, the value of + * ext_csd's capacity is valid if the value is more + * than 2GB + */ + capacity = ext_csd[212] << 0 | ext_csd[213] << 8 | + ext_csd[214] << 16 | ext_csd[215] << 24; + capacity *= 512; + if ((capacity >> 20) > 2 * 1024) + mmc->capacity = capacity; + } + + /* + * Check whether GROUP_DEF is set, if yes, read out + * group size from ext_csd directly, or calculate + * the group size from the csd value. + */ + if (ext_csd[175]) + mmc->erase_grp_size = ext_csd[224] * 512 * 1024; + else { + int erase_gsz, erase_gmul; + erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; + erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; + mmc->erase_grp_size = (erase_gsz + 1) + * (erase_gmul + 1); } /* store the partition info of emmc */ @@ -1044,6 +1156,7 @@ int mmc_register(struct mmc *mmc) mmc->block_dev.removable = 1; mmc->block_dev.block_read = mmc_bread; mmc->block_dev.block_write = mmc_bwrite; + mmc->block_dev.block_erase = mmc_berase; if (!mmc->b_max) mmc->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; @@ -1054,12 +1167,14 @@ int mmc_register(struct mmc *mmc) return 0; } +#ifdef CONFIG_PARTITIONS block_dev_desc_t *mmc_get_dev(int dev) { struct mmc *mmc = find_mmc_device(dev); return mmc ? &mmc->block_dev : NULL; } +#endif int mmc_init(struct mmc *mmc) { diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c new file mode 100644 index 0000000..9e59951 --- /dev/null +++ b/drivers/mmc/mv_sdhci.c @@ -0,0 +1,21 @@ +#include <common.h> +#include <malloc.h> +#include <sdhci.h> + +static char *MVSDH_NAME = "mv_sdh"; +int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks) +{ + struct sdhci_host *host = NULL; + host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); + if (!host) { + printf("sdh_host malloc fail!\n"); + return 1; + } + + host->name = MVSDH_NAME; + host->ioaddr = (void *)regbase; + host->quirks = quirks; + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + add_sdhci(host, max_clk, min_clk); + return 0; +} diff --git a/drivers/mmc/s5p_mmc.c b/drivers/mmc/s5p_mmc.c index 280738f..f136813 100644 --- a/drivers/mmc/s5p_mmc.c +++ b/drivers/mmc/s5p_mmc.c @@ -462,7 +462,7 @@ static int s5p_mmc_initialize(int dev_index, int bus_width) mmc->host_caps = MMC_MODE_8BIT; else mmc->host_caps = MMC_MODE_4BIT; - mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; + mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC; mmc->f_min = 400000; mmc->f_max = 52000000; diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c new file mode 100644 index 0000000..9ebd33d --- /dev/null +++ b/drivers/mmc/sdhci.c @@ -0,0 +1,433 @@ +/* + * Copyright 2011, Marvell Semiconductor Inc. + * Lei Wen <leiwen@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Back ported to the 8xx platform (from the 8260 platform) by + * Murray.Jensen@cmst.csiro.au, 27-Jan-01. + */ + +#include <common.h> +#include <malloc.h> +#include <mmc.h> +#include <sdhci.h> + +void *aligned_buffer; + +static void sdhci_reset(struct sdhci_host *host, u8 mask) +{ + unsigned long timeout; + + /* Wait max 100 ms */ + timeout = 100; + sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); + while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { + if (timeout == 0) { + printf("Reset 0x%x never completed.\n", (int)mask); + return; + } + timeout--; + udelay(1000); + } +} + +static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd) +{ + int i; + if (cmd->resp_type & MMC_RSP_136) { + /* CRC is stripped so we need to do some shifting. */ + for (i = 0; i < 4; i++) { + cmd->response[i] = sdhci_readl(host, + SDHCI_RESPONSE + (3-i)*4) << 8; + if (i != 3) + cmd->response[i] |= sdhci_readb(host, + SDHCI_RESPONSE + (3-i)*4-1); + } + } else { + cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); + } +} + +static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) +{ + int i; + char *offs; + for (i = 0; i < data->blocksize; i += 4) { + offs = data->dest + i; + if (data->flags == MMC_DATA_READ) + *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); + else + sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); + } +} + +static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, + unsigned int start_addr) +{ + unsigned int stat, rdy, mask, block = 0; + + rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; + mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; + do { + stat = sdhci_readl(host, SDHCI_INT_STATUS); + if (stat & SDHCI_INT_ERROR) { + printf("Error detected in status(0x%X)!\n", stat); + return -1; + } + if (stat & rdy) { + if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) + continue; + sdhci_writel(host, rdy, SDHCI_INT_STATUS); + sdhci_transfer_pio(host, data); + data->dest += data->blocksize; + if (++block >= data->blocks) + break; + } +#ifdef CONFIG_MMC_SDMA + if (stat & SDHCI_INT_DMA_END) { + sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); + start_addr &= SDHCI_DEFAULT_BOUNDARY_SIZE - 1; + start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; + sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); + } +#endif + } while (!(stat & SDHCI_INT_DATA_END)); + return 0; +} + +int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct sdhci_host *host = (struct sdhci_host *)mmc->priv; + unsigned int stat = 0; + int ret = 0; + int trans_bytes = 0, is_aligned = 1; + u32 mask, flags, mode; + unsigned int timeout, start_addr = 0; + + /* Wait max 10 ms */ + timeout = 10; + + sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); + mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT; + + /* We shouldn't wait for data inihibit for stop commands, even + though they might use busy signaling */ + if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) + mask &= ~SDHCI_DATA_INHIBIT; + + while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { + if (timeout == 0) { + printf("Controller never released inhibit bit(s).\n"); + return COMM_ERR; + } + timeout--; + udelay(1000); + } + + mask = SDHCI_INT_RESPONSE; + if (!(cmd->resp_type & MMC_RSP_PRESENT)) + flags = SDHCI_CMD_RESP_NONE; + else if (cmd->resp_type & MMC_RSP_136) + flags = SDHCI_CMD_RESP_LONG; + else if (cmd->resp_type & MMC_RSP_BUSY) { + flags = SDHCI_CMD_RESP_SHORT_BUSY; + mask |= SDHCI_INT_DATA_END; + } else + flags = SDHCI_CMD_RESP_SHORT; + + if (cmd->resp_type & MMC_RSP_CRC) + flags |= SDHCI_CMD_CRC; + if (cmd->resp_type & MMC_RSP_OPCODE) + flags |= SDHCI_CMD_INDEX; + if (data) + flags |= SDHCI_CMD_DATA; + + /*Set Transfer mode regarding to data flag*/ + if (data != 0) { + sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); + mode = SDHCI_TRNS_BLK_CNT_EN; + trans_bytes = data->blocks * data->blocksize; + if (data->blocks > 1) + mode |= SDHCI_TRNS_MULTI; + + if (data->flags == MMC_DATA_READ) + mode |= SDHCI_TRNS_READ; + +#ifdef CONFIG_MMC_SDMA + if (data->flags == MMC_DATA_READ) + start_addr = (unsigned int)data->dest; + else + start_addr = (unsigned int)data->src; + if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && + (start_addr & 0x7) != 0x0) { + is_aligned = 0; + start_addr = (unsigned int)aligned_buffer; + if (data->flags != MMC_DATA_READ) + memcpy(aligned_buffer, data->src, trans_bytes); + } + + sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); + mode |= SDHCI_TRNS_DMA; +#endif + sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, + data->blocksize), + SDHCI_BLOCK_SIZE); + sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); + } + + sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); +#ifdef CONFIG_MMC_SDMA + flush_cache(0, ~0); +#endif + sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); + do { + stat = sdhci_readl(host, SDHCI_INT_STATUS); + if (stat & SDHCI_INT_ERROR) + break; + } while ((stat & mask) != mask); + + if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { + sdhci_cmd_done(host, cmd); + sdhci_writel(host, mask, SDHCI_INT_STATUS); + } else + ret = -1; + + if (!ret && data) + ret = sdhci_transfer_data(host, data, start_addr); + + stat = sdhci_readl(host, SDHCI_INT_STATUS); + sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); + if (!ret) { + if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && + !is_aligned && (data->flags == MMC_DATA_READ)) + memcpy(data->dest, aligned_buffer, trans_bytes); + return 0; + } + + sdhci_reset(host, SDHCI_RESET_CMD); + sdhci_reset(host, SDHCI_RESET_DATA); + if (stat & SDHCI_INT_TIMEOUT) + return TIMEOUT; + else + return COMM_ERR; +} + +static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) +{ + struct sdhci_host *host = (struct sdhci_host *)mmc->priv; + unsigned int div, clk, timeout; + + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + + if (clock == 0) + return 0; + + if (host->version >= SDHCI_SPEC_300) { + /* Version 3.00 divisors must be a multiple of 2. */ + if (mmc->f_max <= clock) + div = 1; + else { + for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { + if ((mmc->f_max / div) <= clock) + break; + } + } + } else { + /* Version 2.00 divisors must be a power of 2. */ + for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { + if ((mmc->f_max / div) <= clock) + break; + } + } + div >>= 1; + + clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; + clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) + << SDHCI_DIVIDER_HI_SHIFT; + clk |= SDHCI_CLOCK_INT_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + /* Wait max 20 ms */ + timeout = 20; + while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) + & SDHCI_CLOCK_INT_STABLE)) { + if (timeout == 0) { + printf("Internal clock never stabilised.\n"); + return -1; + } + timeout--; + udelay(1000); + } + + clk |= SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + return 0; +} + +static void sdhci_set_power(struct sdhci_host *host, unsigned short power) +{ + u8 pwr = 0; + + if (power != (unsigned short)-1) { + switch (1 << power) { + case MMC_VDD_165_195: + pwr = SDHCI_POWER_180; + break; + case MMC_VDD_29_30: + case MMC_VDD_30_31: + pwr = SDHCI_POWER_300; + break; + case MMC_VDD_32_33: + case MMC_VDD_33_34: + pwr = SDHCI_POWER_330; + break; + } + } + + if (pwr == 0) { + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + return; + } + + pwr |= SDHCI_POWER_ON; + + sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); +} + +void sdhci_set_ios(struct mmc *mmc) +{ + u32 ctrl; + struct sdhci_host *host = (struct sdhci_host *)mmc->priv; + + if (mmc->clock != host->clock) + sdhci_set_clock(mmc, mmc->clock); + + /* Set bus width */ + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + if (mmc->bus_width == 8) { + ctrl &= ~SDHCI_CTRL_4BITBUS; + if (host->version >= SDHCI_SPEC_300) + ctrl |= SDHCI_CTRL_8BITBUS; + } else { + if (host->version >= SDHCI_SPEC_300) + ctrl &= ~SDHCI_CTRL_8BITBUS; + if (mmc->bus_width == 4) + ctrl |= SDHCI_CTRL_4BITBUS; + else + ctrl &= ~SDHCI_CTRL_4BITBUS; + } + + if (mmc->clock > 26000000) + ctrl |= SDHCI_CTRL_HISPD; + else + ctrl &= ~SDHCI_CTRL_HISPD; + + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); +} + +int sdhci_init(struct mmc *mmc) +{ + struct sdhci_host *host = (struct sdhci_host *)mmc->priv; + + if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { + aligned_buffer = memalign(8, 512*1024); + if (!aligned_buffer) { + printf("Aligned buffer alloc failed!!!"); + return -1; + } + } + + /* Eable all state */ + sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_ENABLE); + sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_SIGNAL_ENABLE); + + sdhci_set_power(host, fls(mmc->voltages) - 1); + + return 0; +} + +int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) +{ + struct mmc *mmc; + unsigned int caps; + + mmc = malloc(sizeof(struct mmc)); + if (!mmc) { + printf("mmc malloc fail!\n"); + return -1; + } + + mmc->priv = host; + + sprintf(mmc->name, "%s", host->name); + mmc->send_cmd = sdhci_send_command; + mmc->set_ios = sdhci_set_ios; + mmc->init = sdhci_init; + + caps = sdhci_readl(host, SDHCI_CAPABILITIES); +#ifdef CONFIG_MMC_SDMA + if (!(caps & SDHCI_CAN_DO_SDMA)) { + printf("Your controller don't support sdma!!\n"); + return -1; + } +#endif + + if (max_clk) + mmc->f_max = max_clk; + else { + if (host->version >= SDHCI_SPEC_300) + mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) + >> SDHCI_CLOCK_BASE_SHIFT; + else + mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK) + >> SDHCI_CLOCK_BASE_SHIFT; + mmc->f_max *= 1000000; + } + if (mmc->f_max == 0) { + printf("Hardware doesn't specify base clock frequency\n"); + return -1; + } + if (min_clk) + mmc->f_min = min_clk; + else { + if (host->version >= SDHCI_SPEC_300) + mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300; + else + mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200; + } + + mmc->voltages = 0; + if (caps & SDHCI_CAN_VDD_330) + mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; + if (caps & SDHCI_CAN_VDD_300) + mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; + if (caps & SDHCI_CAN_VDD_180) + mmc->voltages |= MMC_VDD_165_195; + mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; + if (caps & SDHCI_CAN_DO_8BIT) + mmc->host_caps |= MMC_MODE_8BIT; + + sdhci_reset(host, SDHCI_RESET_ALL); + mmc_register(mmc); + + return 0; +} diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c new file mode 100644 index 0000000..567e2cb --- /dev/null +++ b/drivers/mmc/sh_mmcif.c @@ -0,0 +1,608 @@ +/* + * MMCIF driver. + * + * Copyright (C) 2011 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + */ + +#include <config.h> +#include <common.h> +#include <watchdog.h> +#include <command.h> +#include <mmc.h> +#include <malloc.h> +#include <asm/errno.h> +#include <asm/io.h> +#include "sh_mmcif.h" + +#define DRIVER_NAME "sh_mmcif" + +static void *mmc_priv(struct mmc *mmc) +{ + return (void *)mmc->priv; +} + +static int sh_mmcif_intr(void *dev_id) +{ + struct sh_mmcif_host *host = dev_id; + u32 state = 0; + + state = sh_mmcif_read(&host->regs->ce_int); + state &= sh_mmcif_read(&host->regs->ce_int_mask); + + if (state & INT_RBSYE) { + sh_mmcif_write(~(INT_RBSYE | INT_CRSPE), &host->regs->ce_int); + sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask); + goto end; + } else if (state & INT_CRSPE) { + sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int); + sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask); + /* one more interrupt (INT_RBSYE) */ + if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY) + return -EAGAIN; + goto end; + } else if (state & INT_BUFREN) { + sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int); + sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask); + goto end; + } else if (state & INT_BUFWEN) { + sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int); + sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask); + goto end; + } else if (state & INT_CMD12DRE) { + sh_mmcif_write(~(INT_CMD12DRE | INT_CMD12RBE | INT_CMD12CRE | + INT_BUFRE), &host->regs->ce_int); + sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask); + goto end; + } else if (state & INT_BUFRE) { + sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int); + sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask); + goto end; + } else if (state & INT_DTRANE) { + sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int); + sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask); + goto end; + } else if (state & INT_CMD12RBE) { + sh_mmcif_write(~(INT_CMD12RBE | INT_CMD12CRE), + &host->regs->ce_int); + sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask); + goto end; + } else if (state & INT_ERR_STS) { + /* err interrupts */ + sh_mmcif_write(~state, &host->regs->ce_int); + sh_mmcif_bitclr(state, &host->regs->ce_int_mask); + goto err; + } else + return -EAGAIN; + +err: + host->sd_error = 1; + debug("%s: int err state = %08x\n", DRIVER_NAME, state); +end: + host->wait_int = 1; + return 0; +} + +static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host) +{ + int timeout = 10000000; + + while (1) { + timeout--; + if (timeout < 0) { + printf("timeout\n"); + return 0; + } + + if (!sh_mmcif_intr(host)) + break; + + udelay(1); /* 1 usec */ + } + + return 1; /* Return value: NOT 0 = complete waiting */ +} + +static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) +{ + int i; + + sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); + sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); + + if (!clk) + return; + if (clk == CLKDEV_EMMC_DATA) { + sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); + } else { + for (i = 1; (unsigned int)host->clk / (1 << i) >= clk; i++) + ; + sh_mmcif_bitset((i - 1) << 16, &host->regs->ce_clk_ctrl); + } + sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); +} + +static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) +{ + u32 tmp; + + tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | + CLK_CLEAR); + + sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version); + sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version); + sh_mmcif_bitset(tmp | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29, + &host->regs->ce_clk_ctrl); + /* byte swap on */ + sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc); +} + +static int sh_mmcif_error_manage(struct sh_mmcif_host *host) +{ + u32 state1, state2; + int ret, timeout = 10000000; + + host->sd_error = 0; + host->wait_int = 0; + + state1 = sh_mmcif_read(&host->regs->ce_host_sts1); + state2 = sh_mmcif_read(&host->regs->ce_host_sts2); + debug("%s: ERR HOST_STS1 = %08x\n", \ + DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1)); + debug("%s: ERR HOST_STS2 = %08x\n", \ + DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2)); + + if (state1 & STS1_CMDSEQ) { + debug("%s: Forced end of command sequence\n", DRIVER_NAME); + sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl); + sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl); + while (1) { + timeout--; + if (timeout < 0) { + printf(DRIVER_NAME": Forceed end of " \ + "command sequence timeout err\n"); + return -EILSEQ; + } + if (!(sh_mmcif_read(&host->regs->ce_host_sts1) + & STS1_CMDSEQ)) + break; + } + sh_mmcif_sync_reset(host); + return -EILSEQ; + } + + if (state2 & STS2_CRC_ERR) + ret = -EILSEQ; + else if (state2 & STS2_TIMEOUT_ERR) + ret = TIMEOUT; + else + ret = -EILSEQ; + return ret; +} + +static int sh_mmcif_single_read(struct sh_mmcif_host *host, + struct mmc_data *data) +{ + long time; + u32 blocksize, i; + unsigned long *p = (unsigned long *)data->dest; + + if ((unsigned long)p & 0x00000001) { + printf("%s: The data pointer is unaligned.", __func__); + return -EIO; + } + + host->wait_int = 0; + + /* buf read enable */ + sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask); + time = mmcif_wait_interrupt_flag(host); + if (time == 0 || host->sd_error != 0) + return sh_mmcif_error_manage(host); + + host->wait_int = 0; + blocksize = (BLOCK_SIZE_MASK & + sh_mmcif_read(&host->regs->ce_block_set)) + 3; + for (i = 0; i < blocksize / 4; i++) + *p++ = sh_mmcif_read(&host->regs->ce_data); + + /* buffer read end */ + sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask); + time = mmcif_wait_interrupt_flag(host); + if (time == 0 || host->sd_error != 0) + return sh_mmcif_error_manage(host); + + host->wait_int = 0; + return 0; +} + +static int sh_mmcif_multi_read(struct sh_mmcif_host *host, + struct mmc_data *data) +{ + long time; + u32 blocksize, i, j; + unsigned long *p = (unsigned long *)data->dest; + + if ((unsigned long)p & 0x00000001) { + printf("%s: The data pointer is unaligned.", __func__); + return -EIO; + } + + host->wait_int = 0; + blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set); + for (j = 0; j < data->blocks; j++) { + sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask); + time = mmcif_wait_interrupt_flag(host); + if (time == 0 || host->sd_error != 0) + return sh_mmcif_error_manage(host); + + host->wait_int = 0; + for (i = 0; i < blocksize / 4; i++) + *p++ = sh_mmcif_read(&host->regs->ce_data); + + WATCHDOG_RESET(); + } + return 0; +} + +static int sh_mmcif_single_write(struct sh_mmcif_host *host, + struct mmc_data *data) +{ + long time; + u32 blocksize, i; + const unsigned long *p = (unsigned long *)data->dest; + + if ((unsigned long)p & 0x00000001) { + printf("%s: The data pointer is unaligned.", __func__); + return -EIO; + } + + host->wait_int = 0; + sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask); + + time = mmcif_wait_interrupt_flag(host); + if (time == 0 || host->sd_error != 0) + return sh_mmcif_error_manage(host); + + host->wait_int = 0; + blocksize = (BLOCK_SIZE_MASK & + sh_mmcif_read(&host->regs->ce_block_set)) + 3; + for (i = 0; i < blocksize / 4; i++) + sh_mmcif_write(*p++, &host->regs->ce_data); + + /* buffer write end */ + sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask); + + time = mmcif_wait_interrupt_flag(host); + if (time == 0 || host->sd_error != 0) + return sh_mmcif_error_manage(host); + + host->wait_int = 0; + return 0; +} + +static int sh_mmcif_multi_write(struct sh_mmcif_host *host, + struct mmc_data *data) +{ + long time; + u32 i, j, blocksize; + const unsigned long *p = (unsigned long *)data->dest; + + if ((unsigned long)p & 0x00000001) { + printf("%s: The data pointer is unaligned.", __func__); + return -EIO; + } + + host->wait_int = 0; + blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set); + for (j = 0; j < data->blocks; j++) { + sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask); + + time = mmcif_wait_interrupt_flag(host); + + if (time == 0 || host->sd_error != 0) + return sh_mmcif_error_manage(host); + + host->wait_int = 0; + for (i = 0; i < blocksize / 4; i++) + sh_mmcif_write(*p++, &host->regs->ce_data); + + WATCHDOG_RESET(); + } + return 0; +} + +static void sh_mmcif_get_response(struct sh_mmcif_host *host, + struct mmc_cmd *cmd) +{ + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3); + cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2); + cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1); + cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0); + debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0], + cmd->response[1], cmd->response[2], cmd->response[3]); + } else { + cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0); + } +} + +static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, + struct mmc_cmd *cmd) +{ + cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12); +} + +static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, + struct mmc_data *data, struct mmc_cmd *cmd) +{ + u32 tmp = 0; + u32 opc = cmd->cmdidx; + + /* Response Type check */ + switch (cmd->resp_type) { + case MMC_RSP_NONE: + tmp |= CMD_SET_RTYP_NO; + break; + case MMC_RSP_R1: + case MMC_RSP_R1b: + case MMC_RSP_R3: + tmp |= CMD_SET_RTYP_6B; + break; + case MMC_RSP_R2: + tmp |= CMD_SET_RTYP_17B; + break; + default: + printf(DRIVER_NAME": Not support type response.\n"); + break; + } + + /* RBSY */ + if (opc == MMC_CMD_SWITCH) + tmp |= CMD_SET_RBSY; + + /* WDAT / DATW */ + if (host->data) { + tmp |= CMD_SET_WDAT; + switch (host->bus_width) { + case MMC_BUS_WIDTH_1: + tmp |= CMD_SET_DATW_1; + break; + case MMC_BUS_WIDTH_4: + tmp |= CMD_SET_DATW_4; + break; + case MMC_BUS_WIDTH_8: + tmp |= CMD_SET_DATW_8; + break; + default: + printf(DRIVER_NAME": Not support bus width.\n"); + break; + } + } + /* DWEN */ + if (opc == MMC_CMD_WRITE_SINGLE_BLOCK || + opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) + tmp |= CMD_SET_DWEN; + /* CMLTE/CMD12EN */ + if (opc == MMC_CMD_READ_MULTIPLE_BLOCK || + opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) { + tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; + sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set); + } + /* RIDXC[1:0] check bits */ + if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID || + opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID) + tmp |= CMD_SET_RIDXC_BITS; + /* RCRC7C[1:0] check bits */ + if (opc == MMC_CMD_SEND_OP_COND) + tmp |= CMD_SET_CRC7C_BITS; + /* RCRC7C[1:0] internal CRC7 */ + if (opc == MMC_CMD_ALL_SEND_CID || + opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID) + tmp |= CMD_SET_CRC7C_INTERNAL; + + return opc = ((opc << 24) | tmp); +} + +static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host, + struct mmc_data *data, u16 opc) +{ + u32 ret; + + switch (opc) { + case MMC_CMD_READ_MULTIPLE_BLOCK: + ret = sh_mmcif_multi_read(host, data); + break; + case MMC_CMD_WRITE_MULTIPLE_BLOCK: + ret = sh_mmcif_multi_write(host, data); + break; + case MMC_CMD_WRITE_SINGLE_BLOCK: + ret = sh_mmcif_single_write(host, data); + break; + case MMC_CMD_READ_SINGLE_BLOCK: + case MMC_CMD_SEND_EXT_CSD: + ret = sh_mmcif_single_read(host, data); + break; + default: + printf(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc); + ret = -EINVAL; + break; + } + return ret; +} + +static int sh_mmcif_start_cmd(struct sh_mmcif_host *host, + struct mmc_data *data, struct mmc_cmd *cmd) +{ + long time; + int ret = 0, mask = 0; + u32 opc = cmd->cmdidx; + + if (opc == MMC_CMD_STOP_TRANSMISSION) { + /* MMCIF sends the STOP command automatically */ + if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK) + sh_mmcif_bitset(MASK_MCMD12DRE, + &host->regs->ce_int_mask); + else + sh_mmcif_bitset(MASK_MCMD12RBE, + &host->regs->ce_int_mask); + + time = mmcif_wait_interrupt_flag(host); + if (time == 0 || host->sd_error != 0) + return sh_mmcif_error_manage(host); + + sh_mmcif_get_cmd12response(host, cmd); + return 0; + } + if (opc == MMC_CMD_SWITCH) + mask = MASK_MRBSYE; + else + mask = MASK_MCRSPE; + + mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | + MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | + MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | + MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO; + + if (host->data) { + sh_mmcif_write(0, &host->regs->ce_block_set); + sh_mmcif_write(data->blocksize, &host->regs->ce_block_set); + } + opc = sh_mmcif_set_cmd(host, data, cmd); + + sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int); + sh_mmcif_write(mask, &host->regs->ce_int_mask); + + debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg); + /* set arg */ + sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg); + host->wait_int = 0; + /* set cmd */ + sh_mmcif_write(opc, &host->regs->ce_cmd_set); + + time = mmcif_wait_interrupt_flag(host); + if (time == 0) + return sh_mmcif_error_manage(host); + + if (host->sd_error) { + switch (cmd->cmdidx) { + case MMC_CMD_ALL_SEND_CID: + case MMC_CMD_SELECT_CARD: + case MMC_CMD_APP_CMD: + ret = TIMEOUT; + break; + default: + printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx); + ret = sh_mmcif_error_manage(host); + break; + } + host->sd_error = 0; + host->wait_int = 0; + return ret; + } + + /* if no response */ + if (!(opc & 0x00C00000)) + return 0; + + if (host->wait_int == 1) { + sh_mmcif_get_response(host, cmd); + host->wait_int = 0; + } + if (host->data) + ret = sh_mmcif_data_trans(host, data, cmd->cmdidx); + host->last_cmd = cmd->cmdidx; + + return ret; +} + +static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct sh_mmcif_host *host = mmc_priv(mmc); + int ret; + + WATCHDOG_RESET(); + + switch (cmd->cmdidx) { + case MMC_CMD_APP_CMD: + return TIMEOUT; + case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ + if (data) + /* ext_csd */ + break; + else + /* send_if_cond cmd (not support) */ + return TIMEOUT; + default: + break; + } + host->sd_error = 0; + host->data = data; + ret = sh_mmcif_start_cmd(host, data, cmd); + host->data = NULL; + + return ret; +} + +static void sh_mmcif_set_ios(struct mmc *mmc) +{ + struct sh_mmcif_host *host = mmc_priv(mmc); + + if (mmc->clock) + sh_mmcif_clock_control(host, mmc->clock); + + if (mmc->bus_width == 8) + host->bus_width = MMC_BUS_WIDTH_8; + else if (mmc->bus_width == 4) + host->bus_width = MMC_BUS_WIDTH_4; + else + host->bus_width = MMC_BUS_WIDTH_1; + + debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width); +} + +static int sh_mmcif_init(struct mmc *mmc) +{ + struct sh_mmcif_host *host = mmc_priv(mmc); + + sh_mmcif_sync_reset(host); + sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask); + return 0; +} + +int mmcif_mmc_init(void) +{ + int ret = 0; + struct mmc *mmc; + struct sh_mmcif_host *host = NULL; + + mmc = malloc(sizeof(struct mmc)); + if (!mmc) + ret = -ENOMEM; + memset(mmc, 0, sizeof(*mmc)); + host = malloc(sizeof(struct sh_mmcif_host)); + if (!host) + ret = -ENOMEM; + memset(host, 0, sizeof(*host)); + + mmc->f_min = CLKDEV_MMC_INIT; + mmc->f_max = CLKDEV_EMMC_DATA; + mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT | + MMC_MODE_8BIT; + memcpy(mmc->name, DRIVER_NAME, sizeof(DRIVER_NAME)); + mmc->send_cmd = sh_mmcif_request; + mmc->set_ios = sh_mmcif_set_ios; + mmc->init = sh_mmcif_init; + host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR; + host->clk = CONFIG_SH_MMCIF_CLK; + mmc->priv = host; + + mmc_register(mmc); + + return ret; +} diff --git a/drivers/mmc/sh_mmcif.h b/drivers/mmc/sh_mmcif.h new file mode 100644 index 0000000..bd6fbf7 --- /dev/null +++ b/drivers/mmc/sh_mmcif.h @@ -0,0 +1,238 @@ +/* + * MMCIF driver. + * + * Copyright (C) 2011 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + */ + +#ifndef _SH_MMCIF_H_ +#define _SH_MMCIF_H_ + +struct sh_mmcif_regs { + unsigned long ce_cmd_set; + unsigned long reserved; + unsigned long ce_arg; + unsigned long ce_arg_cmd12; + unsigned long ce_cmd_ctrl; + unsigned long ce_block_set; + unsigned long ce_clk_ctrl; + unsigned long ce_buf_acc; + unsigned long ce_resp3; + unsigned long ce_resp2; + unsigned long ce_resp1; + unsigned long ce_resp0; + unsigned long ce_resp_cmd12; + unsigned long ce_data; + unsigned long reserved2[2]; + unsigned long ce_int; + unsigned long ce_int_mask; + unsigned long ce_host_sts1; + unsigned long ce_host_sts2; + unsigned long reserved3[11]; + unsigned long ce_version; +}; + +/* CE_CMD_SET */ +#define CMD_MASK 0x3f000000 +#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) +/* R1/R1b/R3/R4/R5 */ +#define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) +/* R2 */ +#define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) +/* R1b */ +#define CMD_SET_RBSY (1 << 21) +#define CMD_SET_CCSEN (1 << 20) +/* 1: on data, 0: no data */ +#define CMD_SET_WDAT (1 << 19) +/* 1: write to card, 0: read from card */ +#define CMD_SET_DWEN (1 << 18) +/* 1: multi block trans, 0: single */ +#define CMD_SET_CMLTE (1 << 17) +/* 1: CMD12 auto issue */ +#define CMD_SET_CMD12EN (1 << 16) +/* index check */ +#define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) +/* check bits check */ +#define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) +/* no check */ +#define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) +/* 1: CRC7 check*/ +#define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) +/* 1: check bits check*/ +#define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) +/* 1: internal CRC7 check*/ +#define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) +/* 1: CRC16 check*/ +#define CMD_SET_CRC16C (1 << 10) +/* 1: not receive CRC status */ +#define CMD_SET_CRCSTE (1 << 8) +/* 1: tran mission bit "Low" */ +#define CMD_SET_TBIT (1 << 7) +/* 1: open/drain */ +#define CMD_SET_OPDM (1 << 6) +#define CMD_SET_CCSH (1 << 5) +/* 1bit */ +#define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) +/* 4bit */ +#define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) +/* 8bit */ +#define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) + +/* CE_CMD_CTRL */ +#define CMD_CTRL_BREAK (1 << 0) + +/* CE_BLOCK_SET */ +#define BLOCK_SIZE_MASK 0x0000ffff + +/* CE_CLK_CTRL */ +#define CLK_ENABLE (1 << 24) +#define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) +#define CLK_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) +/* respons timeout */ +#define SRSPTO_256 ((1 << 13) | (0 << 12)) +/* respons busy timeout */ +#define SRBSYTO_29 ((1 << 11) | (1 << 10) | (1 << 9) | (1 << 8)) +/* read/write timeout */ +#define SRWDTO_29 ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4)) +/* ccs timeout */ +#define SCCSTO_29 ((1 << 3) | (1 << 2) | (1 << 1) | (1 << 0)) + +/* CE_BUF_ACC */ +#define BUF_ACC_DMAWEN (1 << 25) +#define BUF_ACC_DMAREN (1 << 24) +#define BUF_ACC_BUSW_32 (0 << 17) +#define BUF_ACC_BUSW_16 (1 << 17) +#define BUF_ACC_ATYP (1 << 16) + +/* CE_INT */ +#define INT_CCSDE (1 << 29) +#define INT_CMD12DRE (1 << 26) +#define INT_CMD12RBE (1 << 25) +#define INT_CMD12CRE (1 << 24) +#define INT_DTRANE (1 << 23) +#define INT_BUFRE (1 << 22) +#define INT_BUFWEN (1 << 21) +#define INT_BUFREN (1 << 20) +#define INT_CCSRCV (1 << 19) +#define INT_RBSYE (1 << 17) +#define INT_CRSPE (1 << 16) +#define INT_CMDVIO (1 << 15) +#define INT_BUFVIO (1 << 14) +#define INT_WDATERR (1 << 11) +#define INT_RDATERR (1 << 10) +#define INT_RIDXERR (1 << 9) +#define INT_RSPERR (1 << 8) +#define INT_CCSTO (1 << 5) +#define INT_CRCSTO (1 << 4) +#define INT_WDATTO (1 << 3) +#define INT_RDATTO (1 << 2) +#define INT_RBSYTO (1 << 1) +#define INT_RSPTO (1 << 0) +#define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ + INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ + INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ + INT_RDATTO | INT_RBSYTO | INT_RSPTO) +#define INT_START_MAGIC 0xD80430C0 + +/* CE_INT_MASK */ +#define MASK_ALL 0x00000000 +#define MASK_MCCSDE (1 << 29) +#define MASK_MCMD12DRE (1 << 26) +#define MASK_MCMD12RBE (1 << 25) +#define MASK_MCMD12CRE (1 << 24) +#define MASK_MDTRANE (1 << 23) +#define MASK_MBUFRE (1 << 22) +#define MASK_MBUFWEN (1 << 21) +#define MASK_MBUFREN (1 << 20) +#define MASK_MCCSRCV (1 << 19) +#define MASK_MRBSYE (1 << 17) +#define MASK_MCRSPE (1 << 16) +#define MASK_MCMDVIO (1 << 15) +#define MASK_MBUFVIO (1 << 14) +#define MASK_MWDATERR (1 << 11) +#define MASK_MRDATERR (1 << 10) +#define MASK_MRIDXERR (1 << 9) +#define MASK_MRSPERR (1 << 8) +#define MASK_MCCSTO (1 << 5) +#define MASK_MCRCSTO (1 << 4) +#define MASK_MWDATTO (1 << 3) +#define MASK_MRDATTO (1 << 2) +#define MASK_MRBSYTO (1 << 1) +#define MASK_MRSPTO (1 << 0) + +/* CE_HOST_STS1 */ +#define STS1_CMDSEQ (1 << 31) + +/* CE_HOST_STS2 */ +#define STS2_CRCSTE (1 << 31) +#define STS2_CRC16E (1 << 30) +#define STS2_AC12CRCE (1 << 29) +#define STS2_RSPCRC7E (1 << 28) +#define STS2_CRCSTEBE (1 << 27) +#define STS2_RDATEBE (1 << 26) +#define STS2_AC12REBE (1 << 25) +#define STS2_RSPEBE (1 << 24) +#define STS2_AC12IDXE (1 << 23) +#define STS2_RSPIDXE (1 << 22) +#define STS2_CCSTO (1 << 15) +#define STS2_RDATTO (1 << 14) +#define STS2_DATBSYTO (1 << 13) +#define STS2_CRCSTTO (1 << 12) +#define STS2_AC12BSYTO (1 << 11) +#define STS2_RSPBSYTO (1 << 10) +#define STS2_AC12RSPTO (1 << 9) +#define STS2_RSPTO (1 << 8) + +#define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ + STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) +#define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ + STS2_DATBSYTO | STS2_CRCSTTO | \ + STS2_AC12BSYTO | STS2_RSPBSYTO | \ + STS2_AC12RSPTO | STS2_RSPTO) + +/* CE_VERSION */ +#define SOFT_RST_ON (1 << 31) +#define SOFT_RST_OFF (0 << 31) + +#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ +#define CLKDEV_MMC_INIT 400000 /* 100 - 400 KHz */ + +#define MMC_BUS_WIDTH_1 0 +#define MMC_BUS_WIDTH_4 2 +#define MMC_BUS_WIDTH_8 3 + +struct sh_mmcif_host { + struct mmc_data *data; + struct sh_mmcif_regs *regs; + unsigned int clk; + int bus_width; + u16 wait_int; + u16 sd_error; + u8 last_cmd; +}; + +static inline u32 sh_mmcif_read(unsigned long *reg) +{ + return readl(reg); +} + +static inline void sh_mmcif_write(u32 val, unsigned long *reg) +{ + writel(val, reg); +} + +static inline void sh_mmcif_bitset(u32 val, unsigned long *reg) +{ + sh_mmcif_write(val | sh_mmcif_read(reg), reg); +} + +static inline void sh_mmcif_bitclr(u32 val, unsigned long *reg) +{ + sh_mmcif_write(~val & sh_mmcif_read(reg), reg); +} + +#endif /* _SH_MMCIF_H_ */ diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc/tegra2_mmc.c new file mode 100644 index 0000000..8b6f829 --- /dev/null +++ b/drivers/mmc/tegra2_mmc.c @@ -0,0 +1,510 @@ +/* + * (C) Copyright 2009 SAMSUNG Electronics + * Minkyu Kang <mk7.kang@samsung.com> + * Jaehoon Chung <jh80.chung@samsung.com> + * Portions Copyright 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <common.h> +#include <mmc.h> +#include <asm/io.h> +#include <asm/arch/clk_rst.h> +#include "tegra2_mmc.h" + +/* support 4 mmc hosts */ +struct mmc mmc_dev[4]; +struct mmc_host mmc_host[4]; + +static inline struct tegra2_mmc *tegra2_get_base_mmc(int dev_index) +{ + unsigned long offset; + debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index); + + switch (dev_index) { + case 0: + offset = TEGRA2_SDMMC4_BASE; + break; + case 1: + offset = TEGRA2_SDMMC3_BASE; + break; + case 2: + offset = TEGRA2_SDMMC2_BASE; + break; + case 3: + offset = TEGRA2_SDMMC1_BASE; + break; + default: + offset = TEGRA2_SDMMC4_BASE; + break; + } + + return (struct tegra2_mmc *)(offset); +} + +static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data) +{ + unsigned char ctrl; + + debug("data->dest: %08X, data->blocks: %u, data->blocksize: %u\n", + (u32)data->dest, data->blocks, data->blocksize); + + writel((u32)data->dest, &host->reg->sysad); + /* + * DMASEL[4:3] + * 00 = Selects SDMA + * 01 = Reserved + * 10 = Selects 32-bit Address ADMA2 + * 11 = Selects 64-bit Address ADMA2 + */ + ctrl = readb(&host->reg->hostctl); + ctrl &= ~(3 << 3); /* SDMA */ + writeb(ctrl, &host->reg->hostctl); + + /* We do not handle DMA boundaries, so set it to max (512 KiB) */ + writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize); + writew(data->blocks, &host->reg->blkcnt); +} + +static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data) +{ + unsigned short mode; + debug(" mmc_set_transfer_mode called\n"); + /* + * TRNMOD + * MUL1SIN0[5] : Multi/Single Block Select + * RD1WT0[4] : Data Transfer Direction Select + * 1 = read + * 0 = write + * ENACMD12[2] : Auto CMD12 Enable + * ENBLKCNT[1] : Block Count Enable + * ENDMA[0] : DMA Enable + */ + mode = (1 << 1) | (1 << 0); + if (data->blocks > 1) + mode |= (1 << 5); + if (data->flags & MMC_DATA_READ) + mode |= (1 << 4); + + writew(mode, &host->reg->trnmod); +} + +static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct mmc_host *host = (struct mmc_host *)mmc->priv; + int flags, i; + unsigned int timeout; + unsigned int mask; + unsigned int retry = 0x100000; + debug(" mmc_send_cmd called\n"); + + /* Wait max 10 ms */ + timeout = 10; + + /* + * PRNSTS + * CMDINHDAT[1] : Command Inhibit (DAT) + * CMDINHCMD[0] : Command Inhibit (CMD) + */ + mask = (1 << 0); + if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY)) + mask |= (1 << 1); + + /* + * We shouldn't wait for data inhibit for stop commands, even + * though they might use busy signaling + */ + if (data) + mask &= ~(1 << 1); + + while (readl(&host->reg->prnsts) & mask) { + if (timeout == 0) { + printf("%s: timeout error\n", __func__); + return -1; + } + timeout--; + udelay(1000); + } + + if (data) + mmc_prepare_data(host, data); + + debug("cmd->arg: %08x\n", cmd->cmdarg); + writel(cmd->cmdarg, &host->reg->argument); + + if (data) + mmc_set_transfer_mode(host, data); + + if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) + return -1; + + /* + * CMDREG + * CMDIDX[13:8] : Command index + * DATAPRNT[5] : Data Present Select + * ENCMDIDX[4] : Command Index Check Enable + * ENCMDCRC[3] : Command CRC Check Enable + * RSPTYP[1:0] + * 00 = No Response + * 01 = Length 136 + * 10 = Length 48 + * 11 = Length 48 Check busy after response + */ + if (!(cmd->resp_type & MMC_RSP_PRESENT)) + flags = 0; + else if (cmd->resp_type & MMC_RSP_136) + flags = (1 << 0); + else if (cmd->resp_type & MMC_RSP_BUSY) + flags = (3 << 0); + else + flags = (2 << 0); + + if (cmd->resp_type & MMC_RSP_CRC) + flags |= (1 << 3); + if (cmd->resp_type & MMC_RSP_OPCODE) + flags |= (1 << 4); + if (data) + flags |= (1 << 5); + + debug("cmd: %d\n", cmd->cmdidx); + + writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg); + + for (i = 0; i < retry; i++) { + mask = readl(&host->reg->norintsts); + /* Command Complete */ + if (mask & (1 << 0)) { + if (!data) + writel(mask, &host->reg->norintsts); + break; + } + } + + if (i == retry) { + printf("%s: waiting for status update\n", __func__); + return TIMEOUT; + } + + if (mask & (1 << 16)) { + /* Timeout Error */ + debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx); + return TIMEOUT; + } else if (mask & (1 << 15)) { + /* Error Interrupt */ + debug("error: %08x cmd %d\n", mask, cmd->cmdidx); + return -1; + } + + if (cmd->resp_type & MMC_RSP_PRESENT) { + if (cmd->resp_type & MMC_RSP_136) { + /* CRC is stripped so we need to do some shifting. */ + for (i = 0; i < 4; i++) { + unsigned int offset = + (unsigned int)(&host->reg->rspreg3 - i); + cmd->response[i] = readl(offset) << 8; + + if (i != 3) { + cmd->response[i] |= + readb(offset - 1); + } + debug("cmd->resp[%d]: %08x\n", + i, cmd->response[i]); + } + } else if (cmd->resp_type & MMC_RSP_BUSY) { + for (i = 0; i < retry; i++) { + /* PRNTDATA[23:20] : DAT[3:0] Line Signal */ + if (readl(&host->reg->prnsts) + & (1 << 20)) /* DAT[0] */ + break; + } + + if (i == retry) { + printf("%s: card is still busy\n", __func__); + return TIMEOUT; + } + + cmd->response[0] = readl(&host->reg->rspreg0); + debug("cmd->resp[0]: %08x\n", cmd->response[0]); + } else { + cmd->response[0] = readl(&host->reg->rspreg0); + debug("cmd->resp[0]: %08x\n", cmd->response[0]); + } + } + + if (data) { + while (1) { + mask = readl(&host->reg->norintsts); + + if (mask & (1 << 15)) { + /* Error Interrupt */ + writel(mask, &host->reg->norintsts); + printf("%s: error during transfer: 0x%08x\n", + __func__, mask); + return -1; + } else if (mask & (1 << 3)) { + /* DMA Interrupt */ + debug("DMA end\n"); + break; + } else if (mask & (1 << 1)) { + /* Transfer Complete */ + debug("r/w is done\n"); + break; + } + } + writel(mask, &host->reg->norintsts); + } + + udelay(1000); + return 0; +} + +static void mmc_change_clock(struct mmc_host *host, uint clock) +{ + int div, hw_div; + unsigned short clk; + unsigned long timeout; + unsigned int reg, hostbase; + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + debug(" mmc_change_clock called\n"); + + /* Change Tegra2 SDMMCx clock divisor here */ + /* Source is 216MHz, PLLP_OUT0 */ + if (clock == 0) + goto out; + + div = 1; + if (clock <= 400000) { + hw_div = ((9-1)<<1); /* Best match is 375KHz */ + div = 64; + } else if (clock <= 20000000) + hw_div = ((11-1)<<1); /* Best match is 19.6MHz */ + else if (clock <= 26000000) + hw_div = ((9-1)<<1); /* Use 24MHz */ + else + hw_div = ((4-1)<<1) + 1; /* 4.5 divisor for 48MHz */ + + debug("mmc_change_clock: hw_div = %d, card clock div = %d\n", + hw_div, div); + + /* Change SDMMCx divisor */ + + hostbase = readl(&host->base); + debug("mmc_change_clock: hostbase = %08X\n", hostbase); + + if (hostbase == TEGRA2_SDMMC1_BASE) { + reg = readl(&clkrst->crc_clk_src_sdmmc1); + reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */ + reg |= hw_div; /* n-1 */ + writel(reg, &clkrst->crc_clk_src_sdmmc1); + } else if (hostbase == TEGRA2_SDMMC2_BASE) { + reg = readl(&clkrst->crc_clk_src_sdmmc2); + reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */ + reg |= hw_div; /* n-1 */ + writel(reg, &clkrst->crc_clk_src_sdmmc2); + } else if (hostbase == TEGRA2_SDMMC3_BASE) { + reg = readl(&clkrst->crc_clk_src_sdmmc3); + reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */ + reg |= hw_div; /* n-1 */ + writel(reg, &clkrst->crc_clk_src_sdmmc3); + } else { + reg = readl(&clkrst->crc_clk_src_sdmmc4); + reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */ + reg |= hw_div; /* n-1 */ + writel(reg, &clkrst->crc_clk_src_sdmmc4); + } + + writew(0, &host->reg->clkcon); + + div >>= 1; + /* + * CLKCON + * SELFREQ[15:8] : base clock divided by value + * ENSDCLK[2] : SD Clock Enable + * STBLINTCLK[1] : Internal Clock Stable + * ENINTCLK[0] : Internal Clock Enable + */ + clk = (div << 8) | (1 << 0); + writew(clk, &host->reg->clkcon); + + /* Wait max 10 ms */ + timeout = 10; + while (!(readw(&host->reg->clkcon) & (1 << 1))) { + if (timeout == 0) { + printf("%s: timeout error\n", __func__); + return; + } + timeout--; + udelay(1000); + } + + clk |= (1 << 2); + writew(clk, &host->reg->clkcon); + + debug("mmc_change_clock: clkcon = %08X\n", clk); + debug("mmc_change_clock: CLK_SOURCE_SDMMCx = %08X\n", reg); + +out: + host->clock = clock; +} + +static void mmc_set_ios(struct mmc *mmc) +{ + struct mmc_host *host = mmc->priv; + unsigned char ctrl; + debug(" mmc_set_ios called\n"); + + debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); + + /* Change clock first */ + + mmc_change_clock(host, mmc->clock); + + ctrl = readb(&host->reg->hostctl); + + /* + * WIDE8[5] + * 0 = Depend on WIDE4 + * 1 = 8-bit mode + * WIDE4[1] + * 1 = 4-bit mode + * 0 = 1-bit mode + */ + if (mmc->bus_width == 8) + ctrl |= (1 << 5); + else if (mmc->bus_width == 4) + ctrl |= (1 << 1); + else + ctrl &= ~(1 << 1); + + writeb(ctrl, &host->reg->hostctl); + debug("mmc_set_ios: hostctl = %08X\n", ctrl); +} + +static void mmc_reset(struct mmc_host *host) +{ + unsigned int timeout; + debug(" mmc_reset called\n"); + + /* + * RSTALL[0] : Software reset for all + * 1 = reset + * 0 = work + */ + writeb((1 << 0), &host->reg->swrst); + + host->clock = 0; + + /* Wait max 100 ms */ + timeout = 100; + + /* hw clears the bit when it's done */ + while (readb(&host->reg->swrst) & (1 << 0)) { + if (timeout == 0) { + printf("%s: timeout error\n", __func__); + return; + } + timeout--; + udelay(1000); + } +} + +static int mmc_core_init(struct mmc *mmc) +{ + struct mmc_host *host = (struct mmc_host *)mmc->priv; + unsigned int mask; + debug(" mmc_core_init called\n"); + + mmc_reset(host); + + host->version = readw(&host->reg->hcver); + debug("host version = %x\n", host->version); + + /* mask all */ + writel(0xffffffff, &host->reg->norintstsen); + writel(0xffffffff, &host->reg->norintsigen); + + writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */ + /* + * NORMAL Interrupt Status Enable Register init + * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable + * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable + * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable + * [0] ENSTACMDCMPLT : Command Complete Status Enable + */ + mask = readl(&host->reg->norintstsen); + mask &= ~(0xffff); + mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0); + writel(mask, &host->reg->norintstsen); + + /* + * NORMAL Interrupt Signal Enable Register init + * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable + */ + mask = readl(&host->reg->norintsigen); + mask &= ~(0xffff); + mask |= (1 << 1); + writel(mask, &host->reg->norintsigen); + + return 0; +} + +static int tegra2_mmc_initialize(int dev_index, int bus_width) +{ + struct mmc *mmc; + + debug(" mmc_initialize called\n"); + + mmc = &mmc_dev[dev_index]; + + sprintf(mmc->name, "Tegra2 SD/MMC"); + mmc->priv = &mmc_host[dev_index]; + mmc->send_cmd = mmc_send_cmd; + mmc->set_ios = mmc_set_ios; + mmc->init = mmc_core_init; + + mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + if (bus_width == 8) + mmc->host_caps = MMC_MODE_8BIT; + else + mmc->host_caps = MMC_MODE_4BIT; + mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; + + /* + * min freq is for card identification, and is the highest + * low-speed SDIO card frequency (actually 400KHz) + * max freq is highest HS eMMC clock as per the SD/MMC spec + * (actually 52MHz) + * Both of these are the closest equivalents w/216MHz source + * clock and Tegra2 SDMMC divisors. + */ + mmc->f_min = 375000; + mmc->f_max = 48000000; + + mmc_host[dev_index].clock = 0; + mmc_host[dev_index].reg = tegra2_get_base_mmc(dev_index); + mmc_host[dev_index].base = (unsigned int)mmc_host[dev_index].reg; + mmc_register(mmc); + + return 0; +} + +int tegra2_mmc_init(int dev_index, int bus_width) +{ + debug(" tegra2_mmc_init: index %d, bus width %d\n", + dev_index, bus_width); + return tegra2_mmc_initialize(dev_index, bus_width); +} diff --git a/drivers/mmc/tegra2_mmc.h b/drivers/mmc/tegra2_mmc.h new file mode 100644 index 0000000..4b80f9f --- /dev/null +++ b/drivers/mmc/tegra2_mmc.h @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2009 SAMSUNG Electronics + * Minkyu Kang <mk7.kang@samsung.com> + * Portions Copyright (C) 2011 NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __TEGRA2_MMC_H_ +#define __TEGRA2_MMC_H_ + +#define TEGRA2_SDMMC1_BASE 0xC8000000 +#define TEGRA2_SDMMC2_BASE 0xC8000200 +#define TEGRA2_SDMMC3_BASE 0xC8000400 +#define TEGRA2_SDMMC4_BASE 0xC8000600 + +#ifndef __ASSEMBLY__ +struct tegra2_mmc { + unsigned int sysad; /* _SYSTEM_ADDRESS_0 */ + unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */ + unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */ + unsigned int argument; /* _ARGUMENT_0 */ + unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */ + unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */ + unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */ + unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */ + unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */ + unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */ + unsigned int bdata; /* _BUFFER_DATA_PORT_0 */ + unsigned int prnsts; /* _PRESENT_STATE_0 */ + unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */ + unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */ + unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */ + unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */ + unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */ + unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */ + unsigned char swrst; /* _SW_RESET_ 31:24 */ + unsigned int norintsts; /* _INTERRUPT_STATUS_0 */ + unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */ + unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */ + unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */ + unsigned char res1[2]; /* _RESERVED 31:16 */ + unsigned int capareg; /* _CAPABILITIES_0 */ + unsigned char res2[4]; /* RESERVED, offset 44h-47h */ + unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */ + unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */ + unsigned short setacmd12err; /* offset 50h */ + unsigned short setinterr; /* offset 52h */ + unsigned char admaerr; /* offset 54h */ + unsigned char res4[3]; /* RESERVED, offset 55h-57h */ + unsigned long admaaddr; /* offset 58h-5Fh */ + unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */ + unsigned short slotintstatus; /* offset FCh */ + unsigned short hcver; /* HOST Version */ + unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */ +}; + +struct mmc_host { + struct tegra2_mmc *reg; + unsigned int version; /* SDHCI spec. version */ + unsigned int clock; /* Current clock (MHz) */ + unsigned int base; /* Base address, SDMMC1/2/3/4 */ +}; + +int tegra2_mmc_init(int dev_index, int bus_width); + +#endif /* __ASSEMBLY__ */ +#endif /* __TEGRA2_MMC_H_ */ diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 6039e1f..ac91dfd 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -573,7 +573,9 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector, #endif /* Wait for command completion */ +#ifdef CONFIG_SYS_LOW_RES_TIMER reset_timer(); +#endif start = get_timer (0); while (flash_is_busy (info, sector)) { if (get_timer (start) > tout) { @@ -662,7 +664,9 @@ static int flash_status_poll(flash_info_t *info, void *src, void *dst, #endif /* Wait for command completion */ +#ifdef CONFIG_SYS_LOW_RES_TIMER reset_timer(); +#endif start = get_timer(0); while (1) { switch (info->portwidth) { @@ -1874,6 +1878,10 @@ static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry) info->device_id == 0x22D7) { /* M29W800DT */ cfi_reverse_geometry(qry); } + } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { + /* CFI >= 1.1, deduct from top/bottom flag */ + /* note: ext_addr is valid since cfi_version > 0 */ + cfi_reverse_geometry(qry); } } } diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 52f8575..1a95a91 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -1950,7 +1950,7 @@ static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, struct nand_chip *chip = mtd->priv; int ret; - /* Do not allow reads past end of device */ + /* Do not allow writes past end of device */ if ((to + len) > mtd->size) return -EINVAL; if (!len) diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index 5a6f7ae..81bf366 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -11,6 +11,9 @@ * nandwrite.c by Steven J. Hill (sjhill@realitydiluted.com) * and Thomas Gleixner (tglx@linutronix.de) * + * Copyright (C) 2008 Nokia Corporation: drop_ffs() function by + * Artem Bityutskiy <dedekind1@gmail.com> from mtd-utils + * * See file CREDITS for list of people who contributed to this * project. * @@ -436,6 +439,29 @@ static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length) return ret; } +#ifdef CONFIG_CMD_NAND_TRIMFFS +static size_t drop_ffs(const nand_info_t *nand, const u_char *buf, + const size_t *len) +{ + size_t i, l = *len; + + for (i = l - 1; i >= 0; i--) + if (buf[i] != 0xFF) + break; + + /* The resulting length must be aligned to the minimum flash I/O size */ + l = i + 1; + l = (l + nand->writesize - 1) / nand->writesize; + l *= nand->writesize; + + /* + * since the input length may be unaligned, prevent access past the end + * of the buffer + */ + return min(l, *len); +} +#endif + /** * nand_write_skip_bad: * @@ -448,11 +474,11 @@ static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length) * @param offset offset in flash * @param length buffer length * @param buffer buffer to read from - * @param withoob whether write with yaffs format + * @param flags flags modifying the behaviour of the write to NAND * @return 0 in case of success */ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, - u_char *buffer, int withoob) + u_char *buffer, int flags) { int rval = 0, blocksize; size_t left_to_write = *length; @@ -460,7 +486,10 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, int need_skip; #ifdef CONFIG_CMD_NAND_YAFFS - if (withoob) { + if (flags & WITH_YAFFS_OOB) { + if (flags & ~WITH_YAFFS_OOB) + return -EINVAL; + int pages; pages = nand->erasesize / nand->writesize; blocksize = (pages * nand->oobsize) + nand->erasesize; @@ -499,7 +528,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, return -EINVAL; } - if (!need_skip) { + if (!need_skip && !(flags & WITH_DROP_FFS)) { rval = nand_write (nand, offset, length, buffer); if (rval == 0) return 0; @@ -512,7 +541,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, while (left_to_write > 0) { size_t block_offset = offset & (nand->erasesize - 1); - size_t write_size; + size_t write_size, truncated_write_size; WATCHDOG_RESET (); @@ -529,7 +558,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, write_size = blocksize - block_offset; #ifdef CONFIG_CMD_NAND_YAFFS - if (withoob) { + if (flags & WITH_YAFFS_OOB) { int page, pages; size_t pagesize = nand->writesize; size_t pagesize_oob = pagesize + nand->oobsize; @@ -558,7 +587,15 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, else #endif { - rval = nand_write (nand, offset, &write_size, p_buffer); + truncated_write_size = write_size; +#ifdef CONFIG_CMD_NAND_TRIMFFS + if (flags & WITH_DROP_FFS) + truncated_write_size = drop_ffs(nand, p_buffer, + &write_size); +#endif + + rval = nand_write(nand, offset, &truncated_write_size, + p_buffer); offset += write_size; p_buffer += write_size; } diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c index 0729e0c..6ebbb5e 100644 --- a/drivers/mtd/nand/ndfc.c +++ b/drivers/mtd/nand/ndfc.c @@ -37,6 +37,13 @@ #include <asm/io.h> #include <asm/ppc4xx.h> +#ifndef CONFIG_SYS_NAND_BCR +#define CONFIG_SYS_NAND_BCR 0x80002222 +#endif +#ifndef CONFIG_SYS_NDFC_EBC0_CFG +#define CONFIG_SYS_NDFC_EBC0_CFG 0xb8400000 +#endif + /* * We need to store the info, which chip-select (CS) is used for the * chip number. For example on Sequoia NAND chip #0 uses @@ -140,12 +147,25 @@ static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len return 0; } -#endif /* #ifndef CONFIG_NAND_SPL */ -#ifndef CONFIG_SYS_NAND_BCR -#define CONFIG_SYS_NAND_BCR 0x80002222 +/* + * Read a byte from the NDFC. + */ +static uint8_t ndfc_read_byte(struct mtd_info *mtd) +{ + + struct nand_chip *chip = mtd->priv; + +#ifdef CONFIG_SYS_NDFC_16BIT + return (uint8_t) readw(chip->IO_ADDR_R); +#else + return readb(chip->IO_ADDR_R); #endif +} + +#endif /* #ifndef CONFIG_NAND_SPL */ + void board_nand_select_device(struct nand_chip *nand, int chip) { /* @@ -198,16 +218,21 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.bytes = 3; nand->select_chip = ndfc_select_chip; +#ifdef CONFIG_SYS_NDFC_16BIT + nand->options |= NAND_BUSWIDTH_16; +#endif + #ifndef CONFIG_NAND_SPL nand->write_buf = ndfc_write_buf; nand->verify_buf = ndfc_verify_buf; + nand->read_byte = ndfc_read_byte; chip++; #else /* * Setup EBC (CS0 only right now) */ - mtebc(EBC0_CFG, 0xb8400000); + mtebc(EBC0_CFG, CONFIG_SYS_NDFC_EBC0_CFG); mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR); mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP); diff --git a/drivers/mtd/spi/eeprom_m95xxx.c b/drivers/mtd/spi/eeprom_m95xxx.c index 632db4e..ef8ed6f 100644 --- a/drivers/mtd/spi/eeprom_m95xxx.c +++ b/drivers/mtd/spi/eeprom_m95xxx.c @@ -75,6 +75,7 @@ ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) { struct spi_slave *slave; char buf[3]; + ulong start; slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000, CONFIG_DEFAULT_SPI_MODE); @@ -102,7 +103,7 @@ ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) if(spi_xfer(slave, len * 8, buffer, NULL, SPI_XFER_END)) return -1; - reset_timer_masked(); + start = get_timer(0); do { buf[0] = SPI_EEPROM_RDSR; buf[1] = 0; @@ -111,7 +112,7 @@ ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) if (!(buf[1] & 1)) break; - } while (get_timer_masked() < CONFIG_SYS_SPI_WRITE_TOUT); + } while (get_timer(start) < CONFIG_SYS_SPI_WRITE_TOUT); if (buf[1] & 1) printf ("*** spi_write: Time out while writing!\n"); diff --git a/drivers/mtd/spi/eon.c b/drivers/mtd/spi/eon.c index e3de3aa..806b44e 100644 --- a/drivers/mtd/spi/eon.c +++ b/drivers/mtd/spi/eon.c @@ -23,8 +23,6 @@ #define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */ #define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */ -#define EON_ID_EN25Q128 0x18 - struct eon_spi_flash_params { u8 idcode1; u16 page_size; @@ -34,20 +32,9 @@ struct eon_spi_flash_params { const char *name; }; -/* spi_flash needs to be first so upper layers can free() it */ -struct eon_spi_flash { - struct spi_flash flash; - const struct eon_spi_flash_params *params; -}; - -static inline struct eon_spi_flash *to_eon_spi_flash(struct spi_flash *flash) -{ - return container_of(flash, struct eon_spi_flash, flash); -} - static const struct eon_spi_flash_params eon_spi_flash_table[] = { { - .idcode1 = EON_ID_EN25Q128, + .idcode1 = 0x18, .page_size = 256, .pages_per_sector = 16, .sectors_per_block = 16, @@ -56,69 +43,6 @@ static const struct eon_spi_flash_params eon_spi_flash_table[] = { }, }; -static int eon_write(struct spi_flash *flash, - u32 offset, size_t len, const void *buf) -{ - struct eon_spi_flash *eon = to_eon_spi_flash(flash); - unsigned long page_addr; - unsigned long byte_addr; - unsigned long page_size; - size_t chunk_len; - size_t actual; - int ret; - u8 cmd[4]; - - page_size = eon->params->page_size; - page_addr = offset / page_size; - byte_addr = offset % page_size; - - ret = spi_claim_bus(flash->spi); - if (ret) { - debug("SF: Unable to claim SPI bus\n"); - return ret; - } - - ret = 0; - for (actual = 0; actual < len; actual += chunk_len) { - chunk_len = min(len - actual, page_size - byte_addr); - - cmd[0] = CMD_EN25Q128_PP; - cmd[1] = page_addr >> 8; - cmd[2] = page_addr; - cmd[3] = byte_addr; - - debug - ("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n", - buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); - - ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0); - if (ret < 0) { - debug("SF: Enabling Write failed\n"); - break; - } - - ret = spi_flash_cmd_write(flash->spi, cmd, 4, - buf + actual, chunk_len); - if (ret < 0) { - debug("SF: EON Page Program failed\n"); - break; - } - - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); - if (ret) - break; - - page_addr++; - byte_addr = 0; - } - - debug("SF: EON: Successfully programmed %u bytes @ 0x%x\n", - len, offset); - - spi_release_bus(flash->spi); - return ret; -} - static int eon_erase(struct spi_flash *flash, u32 offset, size_t len) { return spi_flash_cmd_erase(flash, CMD_EN25Q128_BE, offset, len); @@ -127,7 +51,7 @@ static int eon_erase(struct spi_flash *flash, u32 offset, size_t len) struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) { const struct eon_spi_flash_params *params; - struct eon_spi_flash *eon; + struct spi_flash *flash; unsigned int i; for (i = 0; i < ARRAY_SIZE(eon_spi_flash_table); ++i) { @@ -141,23 +65,23 @@ struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) return NULL; } - eon = malloc(sizeof(*eon)); - if (!eon) { + flash = malloc(sizeof(*flash)); + if (!flash) { debug("SF: Failed to allocate memory\n"); return NULL; } - eon->params = params; - eon->flash.spi = spi; - eon->flash.name = params->name; + flash->spi = spi; + flash->name = params->name; - eon->flash.write = eon_write; - eon->flash.erase = eon_erase; - eon->flash.read = spi_flash_cmd_read_fast; - eon->flash.sector_size = params->page_size * params->pages_per_sector + flash->write = spi_flash_cmd_write_multi; + flash->erase = eon_erase; + flash->read = spi_flash_cmd_read_fast; + flash->page_size = params->page_size; + flash->sector_size = params->page_size * params->pages_per_sector * params->sectors_per_block; - eon->flash.size = params->page_size * params->pages_per_sector + flash->size = params->page_size * params->pages_per_sector * params->nr_sectors; - return &eon->flash; + return flash; } diff --git a/drivers/mtd/spi/macronix.c b/drivers/mtd/spi/macronix.c index ff66f2a..dacbc28 100644 --- a/drivers/mtd/spi/macronix.c +++ b/drivers/mtd/spi/macronix.c @@ -58,19 +58,24 @@ struct macronix_spi_flash_params { const char *name; }; -struct macronix_spi_flash { - struct spi_flash flash; - const struct macronix_spi_flash_params *params; -}; - -static inline struct macronix_spi_flash *to_macronix_spi_flash(struct spi_flash - *flash) -{ - return container_of(flash, struct macronix_spi_flash, flash); -} - static const struct macronix_spi_flash_params macronix_spi_flash_table[] = { { + .idcode = 0x2013, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 8, + .name = "MX25L4005", + }, + { + .idcode = 0x2014, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 16, + .name = "MX25L8005", + }, + { .idcode = 0x2015, .page_size = 256, .pages_per_sector = 16, @@ -112,66 +117,42 @@ static const struct macronix_spi_flash_params macronix_spi_flash_table[] = { }, }; -static int macronix_write(struct spi_flash *flash, - u32 offset, size_t len, const void *buf) +static int macronix_write_status(struct spi_flash *flash, u8 sr) { - struct macronix_spi_flash *mcx = to_macronix_spi_flash(flash); - unsigned long page_addr; - unsigned long byte_addr; - unsigned long page_size; - size_t chunk_len; - size_t actual; + u8 cmd; int ret; - u8 cmd[4]; - page_size = mcx->params->page_size; - page_addr = offset / page_size; - byte_addr = offset % page_size; + ret = spi_flash_cmd_write_enable(flash); + if (ret < 0) { + debug("SF: enabling write failed\n"); + return ret; + } - ret = spi_claim_bus(flash->spi); + cmd = CMD_MX25XX_WRSR; + ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &sr, 1); if (ret) { - debug("SF: Unable to claim SPI bus\n"); + debug("SF: fail to write status register\n"); return ret; } - ret = 0; - for (actual = 0; actual < len; actual += chunk_len) { - chunk_len = min(len - actual, page_size - byte_addr); - - cmd[0] = CMD_MX25XX_PP; - cmd[1] = page_addr >> 8; - cmd[2] = page_addr; - cmd[3] = byte_addr; - - debug - ("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n", - buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); - - ret = spi_flash_cmd(flash->spi, CMD_MX25XX_WREN, NULL, 0); - if (ret < 0) { - debug("SF: Enabling Write failed\n"); - break; - } - - ret = spi_flash_cmd_write(flash->spi, cmd, 4, - buf + actual, chunk_len); - if (ret < 0) { - debug("SF: Macronix Page Program failed\n"); - break; - } + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret < 0) { + debug("SF: write status register timed out\n"); + return ret; + } - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); - if (ret) - break; + return 0; +} - page_addr++; - byte_addr = 0; - } +static int macronix_unlock(struct spi_flash *flash) +{ + int ret; - debug("SF: Macronix: Successfully programmed %u bytes @ 0x%x\n", - len, offset); + /* Enable status register writing and clear BP# bits */ + ret = macronix_write_status(flash, 0); + if (ret) + debug("SF: fail to disable write protection\n"); - spi_release_bus(flash->spi); return ret; } @@ -183,7 +164,7 @@ static int macronix_erase(struct spi_flash *flash, u32 offset, size_t len) struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode) { const struct macronix_spi_flash_params *params; - struct macronix_spi_flash *mcx; + struct spi_flash *flash; unsigned int i; u16 id = idcode[2] | idcode[1] << 8; @@ -198,22 +179,25 @@ struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode) return NULL; } - mcx = malloc(sizeof(*mcx)); - if (!mcx) { + flash = malloc(sizeof(*flash)); + if (!flash) { debug("SF: Failed to allocate memory\n"); return NULL; } - mcx->params = params; - mcx->flash.spi = spi; - mcx->flash.name = params->name; + flash->spi = spi; + flash->name = params->name; - mcx->flash.write = macronix_write; - mcx->flash.erase = macronix_erase; - mcx->flash.read = spi_flash_cmd_read_fast; - mcx->flash.sector_size = params->page_size * params->pages_per_sector + flash->write = spi_flash_cmd_write_multi; + flash->erase = macronix_erase; + flash->read = spi_flash_cmd_read_fast; + flash->page_size = params->page_size; + flash->sector_size = params->page_size * params->pages_per_sector * params->sectors_per_block; - mcx->flash.size = mcx->flash.sector_size * params->nr_blocks; + flash->size = flash->sector_size * params->nr_blocks; + + /* Clear BP# bits for read-only flash */ + macronix_unlock(flash); - return &mcx->flash; + return flash; } diff --git a/drivers/mtd/spi/ramtron.c b/drivers/mtd/spi/ramtron.c index 078d16c..27d4039 100644 --- a/drivers/mtd/spi/ramtron.c +++ b/drivers/mtd/spi/ramtron.c @@ -198,7 +198,7 @@ static int ramtron_common(struct spi_flash *flash, if (command == CMD_RAMTRON_WRITE) { /* send WREN */ - ret = spi_flash_cmd(flash->spi, CMD_RAMTRON_WREN, NULL, 0); + ret = spi_flash_cmd_write_enable(flash); if (ret < 0) { debug("SF: Enabling Write failed\n"); goto releasebus; diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c index a3401b3..6301d87 100644 --- a/drivers/mtd/spi/spansion.c +++ b/drivers/mtd/spi/spansion.c @@ -53,6 +53,7 @@ #define SPSN_EXT_ID_S25FL128P_256KB 0x0300 #define SPSN_EXT_ID_S25FL128P_64KB 0x0301 #define SPSN_EXT_ID_S25FL032P 0x4d00 +#define SPSN_EXT_ID_S25FL129P 0x4d01 struct spansion_spi_flash_params { u16 idcode1; @@ -63,17 +64,6 @@ struct spansion_spi_flash_params { const char *name; }; -struct spansion_spi_flash { - struct spi_flash flash; - const struct spansion_spi_flash_params *params; -}; - -static inline struct spansion_spi_flash *to_spansion_spi_flash(struct spi_flash - *flash) -{ - return container_of(flash, struct spansion_spi_flash, flash); -} - static const struct spansion_spi_flash_params spansion_spi_flash_table[] = { { .idcode1 = SPSN_ID_S25FL008A, @@ -131,71 +121,16 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = { .nr_sectors = 64, .name = "S25FL032P", }, + { + .idcode1 = SPSN_ID_S25FL128P, + .idcode2 = SPSN_EXT_ID_S25FL129P, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 256, + .name = "S25FL129P_64K", + }, }; -static int spansion_write(struct spi_flash *flash, - u32 offset, size_t len, const void *buf) -{ - struct spansion_spi_flash *spsn = to_spansion_spi_flash(flash); - unsigned long page_addr; - unsigned long byte_addr; - unsigned long page_size; - size_t chunk_len; - size_t actual; - int ret; - u8 cmd[4]; - - page_size = spsn->params->page_size; - page_addr = offset / page_size; - byte_addr = offset % page_size; - - ret = spi_claim_bus(flash->spi); - if (ret) { - debug("SF: Unable to claim SPI bus\n"); - return ret; - } - - ret = 0; - for (actual = 0; actual < len; actual += chunk_len) { - chunk_len = min(len - actual, page_size - byte_addr); - - cmd[0] = CMD_S25FLXX_PP; - cmd[1] = page_addr >> 8; - cmd[2] = page_addr; - cmd[3] = byte_addr; - - debug - ("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n", - buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); - - ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0); - if (ret < 0) { - debug("SF: Enabling Write failed\n"); - break; - } - - ret = spi_flash_cmd_write(flash->spi, cmd, 4, - buf + actual, chunk_len); - if (ret < 0) { - debug("SF: SPANSION Page Program failed\n"); - break; - } - - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); - if (ret) - break; - - page_addr++; - byte_addr = 0; - } - - debug("SF: SPANSION: Successfully programmed %u bytes @ 0x%x\n", - len, offset); - - spi_release_bus(flash->spi); - return ret; -} - static int spansion_erase(struct spi_flash *flash, u32 offset, size_t len) { return spi_flash_cmd_erase(flash, CMD_S25FLXX_SE, offset, len); @@ -204,7 +139,7 @@ static int spansion_erase(struct spi_flash *flash, u32 offset, size_t len) struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) { const struct spansion_spi_flash_params *params; - struct spansion_spi_flash *spsn; + struct spi_flash *flash; unsigned int i; unsigned short jedec, ext_jedec; @@ -224,21 +159,21 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) return NULL; } - spsn = malloc(sizeof(struct spansion_spi_flash)); - if (!spsn) { + flash = malloc(sizeof(*flash)); + if (!flash) { debug("SF: Failed to allocate memory\n"); return NULL; } - spsn->params = params; - spsn->flash.spi = spi; - spsn->flash.name = params->name; + flash->spi = spi; + flash->name = params->name; - spsn->flash.write = spansion_write; - spsn->flash.erase = spansion_erase; - spsn->flash.read = spi_flash_cmd_read_fast; - spsn->flash.sector_size = params->page_size * params->pages_per_sector; - spsn->flash.size = spsn->flash.sector_size * params->nr_sectors; + flash->write = spi_flash_cmd_write_multi; + flash->erase = spansion_erase; + flash->read = spi_flash_cmd_read_fast; + flash->page_size = params->page_size; + flash->sector_size = params->page_size * params->pages_per_sector; + flash->size = flash->sector_size * params->nr_sectors; - return &spsn->flash; + return flash; } diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 016b586..730c009 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -65,6 +65,63 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len); } +int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, + size_t len, const void *buf) +{ + unsigned long page_addr, byte_addr, page_size; + size_t chunk_len, actual; + int ret; + u8 cmd[4]; + + page_size = flash->page_size; + page_addr = offset / page_size; + byte_addr = offset % page_size; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: unable to claim SPI bus\n"); + return ret; + } + + cmd[0] = CMD_PAGE_PROGRAM; + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[1] = page_addr >> 8; + cmd[2] = page_addr; + cmd[3] = byte_addr; + + debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", + buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + + ret = spi_flash_cmd_write_enable(flash); + if (ret < 0) { + debug("SF: enabling write failed\n"); + break; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + debug("SF: write failed\n"); + break; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + break; + + page_addr++; + byte_addr = 0; + } + + debug("SF: program %s %zu bytes @ %#x\n", + ret ? "failure" : "success", len, offset); + + spi_release_bus(flash->spi); + return ret; +} + int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, size_t cmd_len, void *data, size_t data_len) { @@ -163,7 +220,7 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd, debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], cmd[2], cmd[3], offset); - ret = spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); + ret = spi_flash_cmd_write_enable(flash); if (ret) goto out; diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index fc109ce..91e036a 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -19,6 +19,8 @@ #define CMD_READ_ARRAY_FAST 0x0b #define CMD_READ_ARRAY_LEGACY 0xe8 +#define CMD_PAGE_PROGRAM 0x02 +#define CMD_WRITE_DISABLE 0x04 #define CMD_READ_STATUS 0x05 #define CMD_WRITE_ENABLE 0x06 @@ -46,6 +48,29 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, const void *data, size_t data_len); /* + * Write the requested data out breaking it up into multiple write + * commands as needed per the write size. + */ +int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, + size_t len, const void *buf); + +/* + * Enable writing on the SPI flash. + */ +static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) +{ + return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); +} + +/* + * Disable writing on the SPI flash. + */ +static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) +{ + return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); +} + +/* * Same as spi_flash_cmd_read() except it also claims/releases the SPI * bus. Used as common part of the ->read() operation. */ diff --git a/drivers/mtd/spi/sst.c b/drivers/mtd/spi/sst.c index 4dc2db2..9559c80 100644 --- a/drivers/mtd/spi/sst.c +++ b/drivers/mtd/spi/sst.c @@ -36,8 +36,12 @@ #define SST_SR_AAI (1 << 6) /* Addressing mode */ #define SST_SR_BPL (1 << 7) /* BP bits lock */ +#define SST_FEAT_WP (1 << 0) /* Supports AAI word program */ +#define SST_FEAT_MBP (1 << 1) /* Supports multibyte program */ + struct sst_spi_flash_params { u8 idcode1; + u8 flags; u16 nr_sectors; const char *name; }; @@ -53,41 +57,51 @@ static inline struct sst_spi_flash *to_sst_spi_flash(struct spi_flash *flash) } #define SST_SECTOR_SIZE (4 * 1024) +#define SST_PAGE_SIZE 256 static const struct sst_spi_flash_params sst_spi_flash_table[] = { { .idcode1 = 0x8d, + .flags = SST_FEAT_WP, .nr_sectors = 128, .name = "SST25VF040B", },{ .idcode1 = 0x8e, + .flags = SST_FEAT_WP, .nr_sectors = 256, .name = "SST25VF080B", },{ .idcode1 = 0x41, + .flags = SST_FEAT_WP, .nr_sectors = 512, .name = "SST25VF016B", },{ .idcode1 = 0x4a, + .flags = SST_FEAT_WP, .nr_sectors = 1024, .name = "SST25VF032B", },{ .idcode1 = 0x4b, + .flags = SST_FEAT_MBP, .nr_sectors = 2048, .name = "SST25VF064C", },{ .idcode1 = 0x01, + .flags = SST_FEAT_WP, .nr_sectors = 16, .name = "SST25WF512", },{ .idcode1 = 0x02, + .flags = SST_FEAT_WP, .nr_sectors = 32, .name = "SST25WF010", },{ .idcode1 = 0x03, + .flags = SST_FEAT_WP, .nr_sectors = 64, .name = "SST25WF020", },{ .idcode1 = 0x04, + .flags = SST_FEAT_WP, .nr_sectors = 128, .name = "SST25WF040", }, @@ -96,7 +110,7 @@ static const struct sst_spi_flash_params sst_spi_flash_table[] = { static int sst_enable_writing(struct spi_flash *flash) { - int ret = spi_flash_cmd(flash->spi, CMD_SST_WREN, NULL, 0); + int ret = spi_flash_cmd_write_enable(flash); if (ret) debug("SF: Enabling Write failed\n"); return ret; @@ -105,7 +119,7 @@ sst_enable_writing(struct spi_flash *flash) static int sst_disable_writing(struct spi_flash *flash) { - int ret = spi_flash_cmd(flash->spi, CMD_SST_WRDI, NULL, 0); + int ret = spi_flash_cmd_write_disable(flash); if (ret) debug("SF: Disabling Write failed\n"); return ret; @@ -137,7 +151,7 @@ sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) } static int -sst_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf) +sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf) { size_t actual, cmd_len; int ret; @@ -257,9 +271,13 @@ spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode) stm->flash.spi = spi; stm->flash.name = params->name; - stm->flash.write = sst_write; + if (stm->params->flags & SST_FEAT_WP) + stm->flash.write = sst_write_wp; + else + stm->flash.write = spi_flash_cmd_write_multi; stm->flash.erase = sst_erase; stm->flash.read = spi_flash_cmd_read_fast; + stm->flash.page_size = SST_PAGE_SIZE; stm->flash.sector_size = SST_SECTOR_SIZE; stm->flash.size = stm->flash.sector_size * params->nr_sectors; diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c index a1959ca..a9b33cf 100644 --- a/drivers/mtd/spi/stmicro.c +++ b/drivers/mtd/spi/stmicro.c @@ -46,15 +46,6 @@ #define CMD_M25PXX_DP 0xb9 /* Deep Power-down */ #define CMD_M25PXX_RES 0xab /* Release from DP, and Read Signature */ -#define STM_ID_M25P10 0x11 -#define STM_ID_M25P16 0x15 -#define STM_ID_M25P20 0x12 -#define STM_ID_M25P32 0x16 -#define STM_ID_M25P40 0x13 -#define STM_ID_M25P64 0x17 -#define STM_ID_M25P80 0x14 -#define STM_ID_M25P128 0x18 - struct stmicro_spi_flash_params { u8 idcode1; u16 page_size; @@ -63,70 +54,58 @@ struct stmicro_spi_flash_params { const char *name; }; -/* spi_flash needs to be first so upper layers can free() it */ -struct stmicro_spi_flash { - struct spi_flash flash; - const struct stmicro_spi_flash_params *params; -}; - -static inline struct stmicro_spi_flash *to_stmicro_spi_flash(struct spi_flash - *flash) -{ - return container_of(flash, struct stmicro_spi_flash, flash); -} - static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = { { - .idcode1 = STM_ID_M25P10, + .idcode1 = 0x11, .page_size = 256, .pages_per_sector = 128, .nr_sectors = 4, .name = "M25P10", }, { - .idcode1 = STM_ID_M25P16, + .idcode1 = 0x15, .page_size = 256, .pages_per_sector = 256, .nr_sectors = 32, .name = "M25P16", }, { - .idcode1 = STM_ID_M25P20, + .idcode1 = 0x12, .page_size = 256, .pages_per_sector = 256, .nr_sectors = 4, .name = "M25P20", }, { - .idcode1 = STM_ID_M25P32, + .idcode1 = 0x16, .page_size = 256, .pages_per_sector = 256, .nr_sectors = 64, .name = "M25P32", }, { - .idcode1 = STM_ID_M25P40, + .idcode1 = 0x13, .page_size = 256, .pages_per_sector = 256, .nr_sectors = 8, .name = "M25P40", }, { - .idcode1 = STM_ID_M25P64, + .idcode1 = 0x17, .page_size = 256, .pages_per_sector = 256, .nr_sectors = 128, .name = "M25P64", }, { - .idcode1 = STM_ID_M25P80, + .idcode1 = 0x14, .page_size = 256, .pages_per_sector = 256, .nr_sectors = 16, .name = "M25P80", }, { - .idcode1 = STM_ID_M25P128, + .idcode1 = 0x18, .page_size = 256, .pages_per_sector = 1024, .nr_sectors = 64, @@ -134,69 +113,6 @@ static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = { }, }; -static int stmicro_write(struct spi_flash *flash, - u32 offset, size_t len, const void *buf) -{ - struct stmicro_spi_flash *stm = to_stmicro_spi_flash(flash); - unsigned long page_addr; - unsigned long byte_addr; - unsigned long page_size; - size_t chunk_len; - size_t actual; - int ret; - u8 cmd[4]; - - page_size = stm->params->page_size; - page_addr = offset / page_size; - byte_addr = offset % page_size; - - ret = spi_claim_bus(flash->spi); - if (ret) { - debug("SF: Unable to claim SPI bus\n"); - return ret; - } - - ret = 0; - for (actual = 0; actual < len; actual += chunk_len) { - chunk_len = min(len - actual, page_size - byte_addr); - - cmd[0] = CMD_M25PXX_PP; - cmd[1] = page_addr >> 8; - cmd[2] = page_addr; - cmd[3] = byte_addr; - - debug - ("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n", - buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); - - ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0); - if (ret < 0) { - debug("SF: Enabling Write failed\n"); - break; - } - - ret = spi_flash_cmd_write(flash->spi, cmd, 4, - buf + actual, chunk_len); - if (ret < 0) { - debug("SF: STMicro Page Program failed\n"); - break; - } - - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); - if (ret) - break; - - page_addr++; - byte_addr = 0; - } - - debug("SF: STMicro: Successfully programmed %u bytes @ 0x%x\n", - len, offset); - - spi_release_bus(flash->spi); - return ret; -} - static int stmicro_erase(struct spi_flash *flash, u32 offset, size_t len) { return spi_flash_cmd_erase(flash, CMD_M25PXX_SE, offset, len); @@ -205,7 +121,7 @@ static int stmicro_erase(struct spi_flash *flash, u32 offset, size_t len) struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode) { const struct stmicro_spi_flash_params *params; - struct stmicro_spi_flash *stm; + struct spi_flash *flash; unsigned int i; if (idcode[0] == 0xff) { @@ -233,21 +149,21 @@ struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode) return NULL; } - stm = malloc(sizeof(struct stmicro_spi_flash)); - if (!stm) { + flash = malloc(sizeof(*flash)); + if (!flash) { debug("SF: Failed to allocate memory\n"); return NULL; } - stm->params = params; - stm->flash.spi = spi; - stm->flash.name = params->name; + flash->spi = spi; + flash->name = params->name; - stm->flash.write = stmicro_write; - stm->flash.erase = stmicro_erase; - stm->flash.read = spi_flash_cmd_read_fast; - stm->flash.sector_size = params->page_size * params->pages_per_sector; - stm->flash.size = stm->flash.sector_size * params->nr_sectors; + flash->write = spi_flash_cmd_write_multi; + flash->erase = stmicro_erase; + flash->read = spi_flash_cmd_read_fast; + flash->page_size = params->page_size; + flash->sector_size = params->page_size * params->pages_per_sector; + flash->size = flash->sector_size * params->nr_sectors; - return &stm->flash; + return flash; } diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c index e8d30ae..45bd146 100644 --- a/drivers/mtd/spi/winbond.c +++ b/drivers/mtd/spi/winbond.c @@ -34,18 +34,6 @@ struct winbond_spi_flash_params { const char *name; }; -/* spi_flash needs to be first so upper layers can free() it */ -struct winbond_spi_flash { - struct spi_flash flash; - const struct winbond_spi_flash_params *params; -}; - -static inline struct winbond_spi_flash * -to_winbond_spi_flash(struct spi_flash *flash) -{ - return container_of(flash, struct winbond_spi_flash, flash); -} - static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { { .id = 0x3015, @@ -105,71 +93,6 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { }, }; -static int winbond_write(struct spi_flash *flash, - u32 offset, size_t len, const void *buf) -{ - struct winbond_spi_flash *stm = to_winbond_spi_flash(flash); - unsigned long page_addr; - unsigned long byte_addr; - unsigned long page_size; - unsigned int page_shift; - size_t chunk_len; - size_t actual; - int ret; - u8 cmd[4]; - - page_shift = stm->params->l2_page_size; - page_size = (1 << page_shift); - page_addr = offset / page_size; - byte_addr = offset % page_size; - - ret = spi_claim_bus(flash->spi); - if (ret) { - debug("SF: Unable to claim SPI bus\n"); - return ret; - } - - for (actual = 0; actual < len; actual += chunk_len) { - chunk_len = min(len - actual, page_size - byte_addr); - - cmd[0] = CMD_W25_PP; - cmd[1] = page_addr >> (16 - page_shift); - cmd[2] = page_addr << (page_shift - 8) | (byte_addr >> 8); - cmd[3] = byte_addr; - debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n", - buf + actual, - cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); - - ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0); - if (ret < 0) { - debug("SF: Enabling Write failed\n"); - goto out; - } - - ret = spi_flash_cmd_write(flash->spi, cmd, 4, - buf + actual, chunk_len); - if (ret < 0) { - debug("SF: Winbond Page Program failed\n"); - goto out; - } - - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); - if (ret) - goto out; - - page_addr++; - byte_addr = 0; - } - - debug("SF: Winbond: Successfully programmed %u bytes @ 0x%x\n", - len, offset); - ret = 0; - -out: - spi_release_bus(flash->spi); - return ret; -} - static int winbond_erase(struct spi_flash *flash, u32 offset, size_t len) { return spi_flash_cmd_erase(flash, CMD_W25_SE, offset, len); @@ -178,9 +101,9 @@ static int winbond_erase(struct spi_flash *flash, u32 offset, size_t len) struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode) { const struct winbond_spi_flash_params *params; - unsigned page_size; - struct winbond_spi_flash *stm; + struct spi_flash *flash; unsigned int i; + unsigned page_size; for (i = 0; i < ARRAY_SIZE(winbond_spi_flash_table); i++) { params = &winbond_spi_flash_table[i]; @@ -194,27 +117,26 @@ struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode) return NULL; } - stm = malloc(sizeof(struct winbond_spi_flash)); - if (!stm) { + flash = malloc(sizeof(*flash)); + if (!flash) { debug("SF: Failed to allocate memory\n"); return NULL; } - stm->params = params; - stm->flash.spi = spi; - stm->flash.name = params->name; + flash->spi = spi; + flash->name = params->name; /* Assuming power-of-two page size initially. */ page_size = 1 << params->l2_page_size; - stm->flash.write = winbond_write; - stm->flash.erase = winbond_erase; - stm->flash.read = spi_flash_cmd_read_fast; - stm->flash.sector_size = (1 << stm->params->l2_page_size) * - stm->params->pages_per_sector; - stm->flash.size = page_size * params->pages_per_sector + flash->write = spi_flash_cmd_write_multi; + flash->erase = winbond_erase; + flash->read = spi_flash_cmd_read_fast; + flash->page_size = page_size; + flash->sector_size = page_size * params->pages_per_sector; + flash->size = page_size * params->pages_per_sector * params->sectors_per_block * params->nr_blocks; - return &stm->flash; + return flash; } diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index b1763b1..07170f6 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -1704,7 +1704,7 @@ int enetInt (struct eth_device *dev) rc = 0; } - /* handle MAL RX EOB interupt from a receive */ + /* handle MAL RX EOB interrupt from a receive */ /* check for EOB on valid channels */ if (uic_mal & UIC_MAL_RXEOB) { mal_eob = mfdcr(MAL0_RXEOBISR); @@ -2035,6 +2035,13 @@ int ppc_4xx_eth_initialize (bd_t * bis) dev->send = ppc_4xx_eth_send; dev->recv = ppc_4xx_eth_rx; + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, + emac4xx_miiphy_read, emac4xx_miiphy_write); +#endif + if (0 == virgin) { /* set the MAL IER ??? names may change with new spec ??? */ #if defined(CONFIG_440SPE) || \ @@ -2072,13 +2079,6 @@ int ppc_4xx_eth_initialize (bd_t * bis) dev); virgin = 1; } - - eth_register (dev); - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register (dev->name, - emac4xx_miiphy_read, emac4xx_miiphy_write); -#endif } /* end for each supported device */ return 0; diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c index 90eb515..97d2739 100644 --- a/drivers/net/at91_emac.c +++ b/drivers/net/at91_emac.c @@ -342,34 +342,34 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd) u32 value; emac_device *dev; at91_emac_t *emac; - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; emac = (at91_emac_t *) netdev->iobase; dev = (emac_device *) netdev->priv; /* PIO Disable Register */ - value = AT91_PMX_AA_EMDIO | AT91_PMX_AA_EMDC | - AT91_PMX_AA_ERXER | AT91_PMX_AA_ERX1 | - AT91_PMX_AA_ERX0 | AT91_PMX_AA_ECRS | - AT91_PMX_AA_ETX1 | AT91_PMX_AA_ETX0 | - AT91_PMX_AA_ETXEN | AT91_PMX_AA_EREFCK; + value = ATMEL_PMX_AA_EMDIO | ATMEL_PMX_AA_EMDC | + ATMEL_PMX_AA_ERXER | ATMEL_PMX_AA_ERX1 | + ATMEL_PMX_AA_ERX0 | ATMEL_PMX_AA_ECRS | + ATMEL_PMX_AA_ETX1 | ATMEL_PMX_AA_ETX0 | + ATMEL_PMX_AA_ETXEN | ATMEL_PMX_AA_EREFCK; writel(value, &pio->pioa.pdr); writel(value, &pio->pioa.asr); #ifdef CONFIG_RMII - value = AT91_PMX_BA_ERXCK; + value = ATMEL_PMX_BA_ERXCK; #else - value = AT91_PMX_BA_ERXCK | AT91_PMX_BA_ECOL | - AT91_PMX_BA_ERXDV | AT91_PMX_BA_ERX3 | - AT91_PMX_BA_ERX2 | AT91_PMX_BA_ETXER | - AT91_PMX_BA_ETX3 | AT91_PMX_BA_ETX2; + value = ATMEL_PMX_BA_ERXCK | ATMEL_PMX_BA_ECOL | + ATMEL_PMX_BA_ERXDV | ATMEL_PMX_BA_ERX3 | + ATMEL_PMX_BA_ERX2 | ATMEL_PMX_BA_ETXER | + ATMEL_PMX_BA_ETX3 | ATMEL_PMX_BA_ETX2; #endif writel(value, &pio->piob.pdr); writel(value, &pio->piob.bsr); - writel(1 << AT91_ID_EMAC, &pmc->pcer); + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl); /* Init Ethernet buffers */ @@ -476,16 +476,18 @@ static int at91emac_write_hwaddr(struct eth_device *netdev) { emac_device *dev; at91_emac_t *emac; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; emac = (at91_emac_t *) netdev->iobase; dev = (emac_device *) netdev->priv; - writel(1 << AT91_ID_EMAC, &pmc->pcer); - DEBUG_AT91EMAC("init MAC-ADDR %x%x \n", - cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), - cpu_to_le32(*((u32 *)netdev->enetaddr))); - writel(cpu_to_le32(*((u32 *)netdev->enetaddr)), &emac->sa2l); - writel(cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), &emac->sa2h); + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + DEBUG_AT91EMAC("init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n", + netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3], + netdev->enetaddr[2], netdev->enetaddr[1], netdev->enetaddr[0]); + writel( (netdev->enetaddr[0] | netdev->enetaddr[1] << 8 | + netdev->enetaddr[2] << 16 | netdev->enetaddr[3] << 24), + &emac->sa2l); + writel((netdev->enetaddr[4] | netdev->enetaddr[5] << 8), &emac->sa2h); DEBUG_AT91EMAC("init MAC-ADDR %x%x \n", readl(&emac->sa2h), readl(&emac->sa2l)); return 0; @@ -498,7 +500,7 @@ int at91emac_register(bd_t *bis, unsigned long iobase) struct eth_device *dev; if (iobase == 0) - iobase = AT91_EMAC_BASE; + iobase = ATMEL_BASE_EMAC; emac = malloc(sizeof(*emac)+512); if (emac == NULL) return -1; diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 3f5eeb7..bfa4384 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -368,11 +368,13 @@ static int configure_phy(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; int phy_addr; - u16 bmcr, ctrl; + u16 bmcr; #if defined(CONFIG_DW_AUTONEG) u16 bmsr; u32 timeout; u16 anlpar, btsr; +#else + u16 ctrl; #endif #if defined(CONFIG_DW_SEARCH_PHY) @@ -381,6 +383,8 @@ static int configure_phy(struct eth_device *dev) priv->address = phy_addr; else return -1; +#else + phy_addr = priv->address; #endif if (dw_reset_phy(dev) < 0) return -1; diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 4e4cd27..ab90afa 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -86,7 +86,7 @@ static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr, /* * wait for the related interrupt */ - start = get_timer_masked(); + start = get_timer(0); while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) { if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { printf("Read MDIO failed...\n"); @@ -138,7 +138,7 @@ static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr, /* * wait for the MII interrupt */ - start = get_timer_masked(); + start = get_timer(0); while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) { if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { printf("Write MDIO failed...\n"); @@ -189,7 +189,7 @@ static int miiphy_wait_aneg(struct eth_device *dev) /* * Wait for AN completion */ - start = get_timer_masked(); + start = get_timer(0); do { if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { printf("%s: Autonegotiation timeout\n", dev->name); diff --git a/drivers/net/greth.c b/drivers/net/greth.c index 6c32226..2aab52f 100644 --- a/drivers/net/greth.c +++ b/drivers/net/greth.c @@ -576,7 +576,7 @@ int greth_recv(struct eth_device *dev) GRETH_REGORIN(®s->control, GRETH_RXEN); } done: - /* return positive length of packet or 0 if non recieved */ + /* return positive length of packet or 0 if non received */ return len; } diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 72ea1fc..c63eea9 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -522,9 +522,10 @@ static int macb_write_hwaddr(struct eth_device *dev) u16 hwaddr_top; /* set hardware address */ - hwaddr_bottom = cpu_to_le32(*((u32 *)dev->enetaddr)); + hwaddr_bottom = dev->enetaddr[0] | dev->enetaddr[1] << 8 | + dev->enetaddr[2] << 16 | dev->enetaddr[3] << 24; macb_writel(macb, SA1B, hwaddr_bottom); - hwaddr_top = cpu_to_le16(*((u16 *)(dev->enetaddr + 4))); + hwaddr_top = dev->enetaddr[4] | dev->enetaddr[5] << 8; macb_writel(macb, SA1T, hwaddr_top); return 0; } diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c index 14b2d35..9386adf 100644 --- a/drivers/net/natsemi.c +++ b/drivers/net/natsemi.c @@ -282,7 +282,7 @@ OUTL(struct eth_device *dev, int command, u_long addr) * ready to send and receive packets. * * Side effects: - * leaves the natsemi initialized, and ready to recieve packets. + * leaves the natsemi initialized, and ready to receive packets. * * Returns: struct eth_device *: pointer to NIC data structure */ diff --git a/drivers/net/netarm_eth.c b/drivers/net/netarm_eth.c index c9e324e..f54817e 100644 --- a/drivers/net/netarm_eth.c +++ b/drivers/net/netarm_eth.c @@ -81,9 +81,10 @@ static unsigned int na_mii_read (int reg) static int na_mii_poll_busy (void) { + ulong start; /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - while (get_timer_masked () < NA_MII_POLL_BUSY_DELAY) { + start = get_timer(0)); + while (get_timer(start) < NA_MII_POLL_BUSY_DELAY) { if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) { return 1; } @@ -164,19 +165,20 @@ static unsigned int na_mii_check_speed (void) static int reset_eth (void) { int pt; + ulong start; na_get_mac_addr (); pt = na_mii_identify_phy (); /* reset the phy */ na_mii_write (MII_PHY_CONTROL, 0x8000); - reset_timer_masked (); - while (get_timer_masked () < NA_MII_NEGOTIATE_DELAY) { + start = get_timer(0); + while (get_timer(start) < NA_MII_NEGOTIATE_DELAY) { if ((na_mii_read (MII_PHY_STATUS) & 0x8000) == 0) { break; } } - if (get_timer_masked () >= NA_MII_NEGOTIATE_DELAY) + if (get_timer(start) >= NA_MII_NEGOTIATE_DELAY) printf ("phy reset timeout\n"); /* set the PCS reg */ diff --git a/drivers/net/ns8382x.c b/drivers/net/ns8382x.c index 45402cc..6dfcd0e 100644 --- a/drivers/net/ns8382x.c +++ b/drivers/net/ns8382x.c @@ -299,7 +299,7 @@ OUTL(struct eth_device *dev, int command, u_long addr) * Description: Retrieves the MAC address of the card, and sets up some * globals required by other routines, and initializes the NIC, making it * ready to send and receive packets. - * Side effects: initializes ns8382xs, ready to recieve packets. + * Side effects: initializes ns8382xs, ready to receive packets. * Returns: int: number of cards found */ diff --git a/drivers/net/phy/generic_10g.c b/drivers/net/phy/generic_10g.c index 60dec45..e4a499d 100644 --- a/drivers/net/phy/generic_10g.c +++ b/drivers/net/phy/generic_10g.c @@ -36,7 +36,7 @@ int gen10g_shutdown(struct phy_device *phydev) int gen10g_startup(struct phy_device *phydev) { int devad, reg; - u32 mmd_mask = phydev->mmds; + u32 mmd_mask = phydev->mmds & MDIO_DEVS_LINK; phydev->link = 1; @@ -44,8 +44,12 @@ int gen10g_startup(struct phy_device *phydev) phydev->speed = SPEED_10000; phydev->duplex = DUPLEX_FULL; + /* + * Go through all the link-reporting devices, and make sure + * they're all up and happy + */ for (devad = 0; mmd_mask; devad++, mmd_mask = mmd_mask >> 1) { - if (!mmd_mask & 1) + if (!(mmd_mask & 1)) continue; /* Read twice because link state is latched and a diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h index 05e007c..8ce08a9 100644 --- a/drivers/net/smc911x.h +++ b/drivers/net/smc911x.h @@ -384,6 +384,7 @@ static inline void smc911x_reg_write(struct eth_device *dev, #define WUCSR_MPEN 0x00000002 /* Chip ID values */ +#define CHIP_89218 0x218a #define CHIP_9115 0x115 #define CHIP_9116 0x116 #define CHIP_9117 0x117 @@ -402,6 +403,7 @@ struct chip_id { }; static const struct chip_id chip_ids[] = { + { CHIP_89218, "LAN89218" }, { CHIP_9115, "LAN9115" }, { CHIP_9116, "LAN9116" }, { CHIP_9117, "LAN9117" }, diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index ab461b4..7f601d4 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -316,7 +316,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) hose->current_busno = hose->first_busno; out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */ - out_be32(&pci->peer, ~0x20140); /* Enable All Error Interupts except + out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except * - Master abort (pci) * - Master PERR (pci) * - ICCA (PCIe) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index cdfc4fb..1a0b14c 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -50,7 +50,6 @@ PCI_HOSE_OP(write, byte, u8) PCI_HOSE_OP(write, word, u16) PCI_HOSE_OP(write, dword, u32) -#ifndef CONFIG_IXP425 #define PCI_OP(rw, size, type, error_code) \ int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \ { \ @@ -71,7 +70,6 @@ PCI_OP(read, dword, u32 *, *value = 0xffffffff) PCI_OP(write, byte, u8, ) PCI_OP(write, word, u16, ) PCI_OP(write, dword, u32, ) -#endif /* CONFIG_IXP425 */ #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \ int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\ @@ -190,7 +188,6 @@ int pci_last_busno(void) return hose->last_busno; } -#ifndef CONFIG_IXP425 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) { struct pci_controller * hose; @@ -246,7 +243,6 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) return (-1); } -#endif /* CONFIG_IXP425 */ pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index) { diff --git a/drivers/pci/pci_indirect.c b/drivers/pci/pci_indirect.c index 2070d01..526a55c 100644 --- a/drivers/pci/pci_indirect.c +++ b/drivers/pci/pci_indirect.c @@ -11,7 +11,7 @@ #include <common.h> -#if (!defined(__I386__) && !defined(CONFIG_IXDP425)) +#if !defined(__I386__) #include <asm/processor.h> #include <asm/io.h> @@ -20,15 +20,6 @@ #define cfg_read(val, addr, type, op) *val = op((type)(addr)) #define cfg_write(val, addr, type, op) op((type *)(addr), (val)) -#ifdef CONFIG_IXP425 -extern unsigned char in_8 (volatile unsigned *addr); -extern unsigned short in_le16 (volatile unsigned *addr); -extern unsigned in_le32 (volatile unsigned *addr); -extern void out_8 (volatile unsigned *addr, char val); -extern void out_le16 (volatile unsigned *addr, unsigned short val); -extern void out_le32 (volatile unsigned *addr, unsigned int val); -#endif /* CONFIG_IXP425 */ - #if defined(CONFIG_MPC8260) #define INDIRECT_PCI_OP(rw, size, type, op, mask) \ static int \ @@ -134,4 +125,4 @@ void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) hose->cfg_data = (unsigned char *) cfg_data; } -#endif /* !__I386__ && !CONFIG_IXDP425 */ +#endif /* !__I386__ */ diff --git a/drivers/pci/pci_ixp.c b/drivers/pci/pci_ixp.c index 3b303b4..5b5c915 100644 --- a/drivers/pci/pci_ixp.c +++ b/drivers/pci/pci_ixp.c @@ -1,5 +1,8 @@ /* * IXP PCI Init + * + * (C) Copyright 2011 + * Michael Schwingen, michael@schwingen.org * (C) Copyright 2004 eslab.whut.edu.cn * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com) * @@ -22,7 +25,6 @@ * MA 02111-1307 USA */ - #include <common.h> #include <asm/processor.h> #include <asm/io.h> @@ -30,542 +32,336 @@ #include <asm/arch/ixp425.h> #include <asm/arch/ixp425pci.h> -static void non_prefetch_read (unsigned int addr, unsigned int cmd, - unsigned int *data); -static void non_prefetch_write (unsigned int addr, unsigned int cmd, - unsigned int data); -static void configure_pins (void); -static void sys_pci_gpio_clock_config (void); -static void pci_bus_scan (void); -static int pci_device_exists (unsigned int deviceNo); -static void sys_pci_bar_info_get (unsigned int devnum, unsigned int bus, - unsigned int dev, unsigned int func); -static void sys_pci_device_bars_write (void); -static void calc_bars (PciBar * Bars[], unsigned int nBars, - unsigned int startAddr); +DECLARE_GLOBAL_DATA_PTR; + +static void non_prefetch_read(unsigned int addr, unsigned int cmd, + unsigned int *data); +static void non_prefetch_write(unsigned int addr, unsigned int cmd, + unsigned int data); + +/*define the sub vendor and subsystem to be used */ +#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000 #define PCI_MEMORY_BUS 0x00000000 -#define PCI_MEMORY_PHY 0x48000000 +#define PCI_MEMORY_PHY 0x00000000 #define PCI_MEMORY_SIZE 0x04000000 -#define PCI_MEM_BUS 0x40000000 +#define PCI_MEM_BUS 0x48000000 #define PCI_MEM_PHY 0x00000000 #define PCI_MEM_SIZE 0x04000000 -#define PCI_IO_BUS 0x40000000 -#define PCI_IO_PHY 0x50000000 -#define PCI_IO_SIZE 0x10000000 +#define PCI_IO_BUS 0x00000000 +#define PCI_IO_PHY 0x00000000 +#define PCI_IO_SIZE 0x00010000 + +/* build address value for config sycle */ +static unsigned int pci_config_addr(pci_dev_t bdf, unsigned int reg) +{ + unsigned int bus = PCI_BUS(bdf); + unsigned int dev = PCI_DEV(bdf); + unsigned int func = PCI_FUNC(bdf); + unsigned int addr; + + if (bus) { /* secondary bus, use type 1 config cycle */ + addr = bdf | (reg & ~3) | 1; + } else { + /* + primary bus, type 0 config cycle. address bits 31:28 + specify the device 10:8 specify the function + */ + addr = BIT((31 - dev)) | (func << 8) | (reg & ~3); + } + + return addr; +} + +static int pci_config_status(void) +{ + unsigned int regval; -struct pci_controller hose; + regval = readl(PCI_CSR_BASE + PCI_ISR_OFFSET); + if ((regval & PCI_ISR_PFE) == 0) + return OK; -unsigned int nDevices; -unsigned int nMBars; -unsigned int nIOBars; -PciBar *memBars[IXP425_PCI_MAX_BAR]; -PciBar *ioBars[IXP425_PCI_MAX_BAR]; -PciDevice devices[IXP425_PCI_MAX_FUNC_ON_BUS]; + /* no device present, make sure that the master abort bit is reset */ + writel(PCI_ISR_PFE, PCI_CSR_BASE + PCI_ISR_OFFSET); + return ERROR; +} -int pci_read_config_dword (pci_dev_t dev, int where, unsigned int *val) +static int pci_ixp_hose_read_config_dword(struct pci_controller *hose, + pci_dev_t bdf, int where, unsigned int *val) { unsigned int retval; unsigned int addr; + int stat; - /*address bits 31:28 specify the device 10:8 specify the function */ + debug("pci_ixp_hose_read_config_dword: bdf %x, reg %x", bdf, where); /*Set the address to be read */ - addr = BIT ((31 - dev)) | (where & ~3); - non_prefetch_read (addr, NP_CMD_CONFIGREAD, &retval); - + addr = pci_config_addr(bdf, where); + non_prefetch_read(addr, NP_CMD_CONFIGREAD, &retval); *val = retval; - return (OK); + stat = pci_config_status(); + if (stat < 0) + *val = -1; + debug("-> val %x, status %x\n", *val, stat); + return stat; } -int pci_read_config_word (pci_dev_t dev, int where, unsigned short *val) +static int pci_ixp_hose_read_config_word(struct pci_controller *hose, + pci_dev_t bdf, int where, unsigned short *val) { unsigned int n; unsigned int retval; unsigned int addr; unsigned int byteEnables; + int stat; + debug("pci_ixp_hose_read_config_word: bdf %x, reg %x", bdf, where); n = where % 4; /*byte enables are 4 bits active low, the position of each bit maps to the byte that it enables */ byteEnables = - (~(BIT (n) | BIT ((n + 1)))) & + (~(BIT(n) | BIT((n + 1)))) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; byteEnables = byteEnables << PCI_NP_CBE_BESL; - /*address bits 31:28 specify the device 10:8 specify the function */ /*Set the address to be read */ - addr = BIT ((31 - dev)) | (where & ~3); - non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval); + addr = pci_config_addr(bdf, where); + non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval); /*Pick out the word we are interested in */ - *val = (retval >> (8 * n)); + *val = retval >> (8 * n); - return (OK); + stat = pci_config_status(); + if (stat < 0) + *val = -1; + debug("-> val %x, status %x\n", *val, stat); + return stat; } -int pci_read_config_byte (pci_dev_t dev, int where, unsigned char *val) +static int pci_ixp_hose_read_config_byte(struct pci_controller *hose, + pci_dev_t bdf, int where, unsigned char *val) { unsigned int retval; unsigned int n; unsigned int byteEnables; unsigned int addr; + int stat; + debug("pci_ixp_hose_read_config_byte: bdf %x, reg %x", bdf, where); n = where % 4; /*byte enables are 4 bits, active low, the position of each bit maps to the byte that it enables */ - byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; + byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; byteEnables = byteEnables << PCI_NP_CBE_BESL; - /*address bits 31:28 specify the device, 10:8 specify the function */ /*Set the address to be read */ - addr = BIT ((31 - dev)) | (where & ~3); - non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval); + addr = pci_config_addr(bdf, where); + non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval); /*Pick out the byte we are interested in */ - *val = (retval >> (8 * n)); + *val = retval >> (8 * n); - return (OK); + stat = pci_config_status(); + if (stat < 0) + *val = -1; + debug("-> val %x, status %x\n", *val, stat); + return stat; } -int pci_write_config_byte (pci_dev_t dev, int where, unsigned char val) +static int pci_ixp_hose_write_config_byte(struct pci_controller *hose, + pci_dev_t bdf, int where, unsigned char val) { unsigned int addr; unsigned int byteEnables; unsigned int n; unsigned int ldata; + int stat; + debug("pci_ixp_hose_write_config_byte: bdf %x, reg %x, val %x", + bdf, where, val); n = where % 4; /*byte enables are 4 bits active low, the position of each bit maps to the byte that it enables */ - byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; + byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; byteEnables = byteEnables << PCI_NP_CBE_BESL; ldata = val << (8 * n); - /*address bits 31:28 specify the device 10:8 specify the function */ /*Set the address to be written */ - addr = BIT ((31 - dev)) | (where & ~3); - non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); + addr = pci_config_addr(bdf, where); + non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); - return (OK); + stat = pci_config_status(); + debug("-> status %x\n", stat); + return stat; } -int pci_write_config_word (pci_dev_t dev, int where, unsigned short val) +static int pci_ixp_hose_write_config_word(struct pci_controller *hose, + pci_dev_t bdf, int where, unsigned short val) { unsigned int addr; unsigned int byteEnables; unsigned int n; unsigned int ldata; + int stat; + debug("pci_ixp_hose_write_config_word: bdf %x, reg %x, val %x", + bdf, where, val); n = where % 4; /*byte enables are 4 bits active low, the position of each bit maps to the byte that it enables */ byteEnables = - (~(BIT (n) | BIT ((n + 1)))) & + (~(BIT(n) | BIT((n + 1)))) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; byteEnables = byteEnables << PCI_NP_CBE_BESL; ldata = val << (8 * n); - /*address bits 31:28 specify the device 10:8 specify the function */ /*Set the address to be written */ - addr = BIT (31 - dev) | (where & ~3); - non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); + addr = pci_config_addr(bdf, where); + non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); - return (OK); + stat = pci_config_status(); + debug("-> status %x\n", stat); + return stat; } -int pci_write_config_dword (pci_dev_t dev, int where, unsigned int val) +static int pci_ixp_hose_write_config_dword(struct pci_controller *hose, + pci_dev_t bdf, int where, unsigned int val) { unsigned int addr; + int stat; - /*address bits 31:28 specify the device 10:8 specify the function */ + debug("pci_ixp_hose_write_config_dword: bdf %x, reg %x, val %x", + bdf, where, val); /*Set the address to be written */ - addr = BIT (31 - dev) | (where & ~3); - non_prefetch_write (addr, NP_CMD_CONFIGWRITE, val); + addr = pci_config_addr(bdf, where); + non_prefetch_write(addr, NP_CMD_CONFIGWRITE, val); - return (OK); + stat = pci_config_status(); + debug("-> status %x\n", stat); + return stat; } -void non_prefetch_read (unsigned int addr, - unsigned int cmd, unsigned int *data) +static void non_prefetch_read(unsigned int addr, + unsigned int cmd, unsigned int *data) { - REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr); + writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET); /*set up and execute the read */ - REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd); + writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET); /*The result of the read is now in np_rdata */ - REG_READ (PCI_CSR_BASE, PCI_NP_RDATA_OFFSET, *data); + *data = readl(PCI_CSR_BASE + PCI_NP_RDATA_OFFSET); return; } -void non_prefetch_write (unsigned int addr, - unsigned int cmd, unsigned int data) +static void non_prefetch_write(unsigned int addr, + unsigned int cmd, unsigned int data) { - REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr); + writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET); /*set up the write */ - REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd); + writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET); /*Execute the write by writing to NP_WDATA */ - REG_WRITE (PCI_CSR_BASE, PCI_NP_WDATA_OFFSET, data); + writel(data, PCI_CSR_BASE + PCI_NP_WDATA_OFFSET); return; } -/* - * PCI controller config registers are accessed through these functions - * i.e. these allow us to set up our own BARs etc. - */ -void crp_read (unsigned int offset, unsigned int *data) +static void crp_write(unsigned int offset, unsigned int data) { - REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, offset); - REG_READ (PCI_CSR_BASE, PCI_CRP_RDATA_OFFSET, *data); -} - -void crp_write (unsigned int offset, unsigned int data) -{ - /*The CRP address register bit 16 indicates that we want to do a write */ - REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, - PCI_CRP_WRITE | offset); - REG_WRITE (PCI_CSR_BASE, PCI_CRP_WDATA_OFFSET, data); -} - -/*struct pci_controller *hose*/ -void pci_ixp_init (struct pci_controller *hose) -{ - unsigned int regval; - - hose->first_busno = 0; - hose->last_busno = 0x00; - - /* System memory space */ - pci_set_region (hose->regions + 0, - PCI_MEMORY_BUS, - PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region (hose->regions + 1, - PCI_MEM_BUS, - PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM); - /* PCI I/O space */ - pci_set_region (hose->regions + 2, - PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO); - - hose->region_count = 3; - - pci_register_hose (hose); - -/* - ========================================================== - Init IXP PCI - ========================================================== -*/ - REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); - regval |= 1 << 2; - REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); - - configure_pins (); - - READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval & (~(1 << 13))); - udelay (533); - sys_pci_gpio_clock_config (); - REG_WRITE (PCI_CSR_BASE, PCI_INTEN_OFFSET, 0); - udelay (100); - READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval | (1 << 13)); - udelay (533); - crp_write (PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_0_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_1, IXP425_PCI_BAR_1_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_2, IXP425_PCI_BAR_2_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_3, IXP425_PCI_BAR_3_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_4, IXP425_PCI_BAR_4_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_5, IXP425_PCI_BAR_5_DEFAULT); - /*Setup PCI-AHB and AHB-PCI address mappings */ - REG_WRITE (PCI_CSR_BASE, PCI_AHBMEMBASE_OFFSET, - IXP425_PCI_AHBMEMBASE_DEFAULT); - - REG_WRITE (PCI_CSR_BASE, PCI_AHBIOBASE_OFFSET, - IXP425_PCI_AHBIOBASE_DEFAULT); - - REG_WRITE (PCI_CSR_BASE, PCI_PCIMEMBASE_OFFSET, - IXP425_PCI_PCIMEMBASE_DEFAULT); - - crp_write (PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM); - - REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); - regval |= PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS; - REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); - crp_write (PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME); - udelay (1000); - - pci_write_config_word (0, PCI_CFG_COMMAND, INITIAL_PCI_CMD); - REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE - | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE); -#ifdef CONFIG_PCI_SCAN_SHOW - printf ("Device bus dev func deviceID vendorID \n"); -#endif - pci_bus_scan (); -} - -void configure_pins (void) -{ - unsigned int regval; - - /* Disable clock on GPIO PIN 14 */ - READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval & (~(1 << 8))); - READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - - READ_GPIO_REG (IXP425_GPIO_GPOER, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPOER, - (((~(3 << 13)) & regval) | (0xf << 8))); - READ_GPIO_REG (IXP425_GPIO_GPOER, regval); - - READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPIT2R, - (regval & - ((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1))); - READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval); - - READ_GPIO_REG (IXP425_GPIO_GPISR, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPISR, (regval | (0xf << 8))); - READ_GPIO_REG (IXP425_GPIO_GPISR, regval); + /* + * The CRP address register bit 16 indicates that we want to do a + * write + */ + writel(PCI_CRP_WRITE | offset, PCI_CSR_BASE + PCI_CRP_AD_CBE_OFFSET); + writel(data, PCI_CSR_BASE + PCI_CRP_WDATA_OFFSET); } -void sys_pci_gpio_clock_config (void) +void pci_ixp_init(struct pci_controller *hose) { - unsigned int regval; - - READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - regval |= 0x1 << 4; - WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - regval |= 0x1 << 8; - WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval); -} + unsigned int csr; -void pci_bus_scan (void) -{ - unsigned int bus = 0, dev, func = 0; - unsigned short data16; - unsigned int data32; - unsigned char intPin; - - /* Assign first device to ourselves */ - devices[0].bus = 0; - devices[0].device = 0; - devices[0].func = 0; - - crp_read (PCI_CFG_VENDOR_ID, &data32); - - devices[0].vendor_id = data32 & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK; - devices[0].device_id = data32 >> 16; - devices[0].error = FALSE; - devices[0].bar[NO_BAR].size = 0; /*dummy - required */ - - nDevices = 1; - - nMBars = 0; - nIOBars = 0; - - for (dev = 0; dev < IXP425_PCI_MAX_DEV; dev++) { - - /*Check whether a device is present */ - if (pci_device_exists (dev) != TRUE) { - - /*Clear error bits in ISR, write 1 to clear */ - REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE - | PCI_ISR_PFE | PCI_ISR_PPE | - PCI_ISR_AHBE); - continue; - } - - /*A device is present, add an entry to the array */ - devices[nDevices].bus = bus; - devices[nDevices].device = dev; - devices[nDevices].func = func; - - pci_read_config_word (dev, PCI_CFG_VENDOR_ID, &data16); - - devices[nDevices].vendor_id = data16; - - pci_read_config_word (dev, PCI_CFG_DEVICE_ID, &data16); - devices[nDevices].device_id = data16; - - /*The device is functioning correctly, set error to FALSE */ - devices[nDevices].error = FALSE; - - /*Figure out what BARs are on this device */ - sys_pci_bar_info_get (nDevices, bus, dev, func); - /*Figure out what INTX# line the card uses */ - pci_read_config_byte (dev, PCI_CFG_DEV_INT_PIN, &intPin); - - /*assign the appropriate irq line */ - if (intPin > PCI_IRQ_LINES) { - devices[nDevices].error = TRUE; - } else if (intPin != 0) { - /*This device uses an interrupt line */ - /*devices[nDevices].irq = ixp425PciIntTranslate[dev][intPin-1]; */ - devices[nDevices].irq = intPin; - } -#ifdef CONFIG_PCI_SCAN_SHOW - printf ("%06d %03d %03d %04d %08d %08x\n", nDevices, - devices[nDevices].vendor_id); + /* + * Specify that the AHB bus is operating in big endian mode. Set up + * byte lane swapping between little-endian PCI and the big-endian + * AHB bus + */ +#ifdef __ARMEB__ + csr = PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS; +#else + csr = PCI_CSR_ABE; #endif - nDevices++; - - } - - calc_bars (memBars, nMBars, IXP425_PCI_BAR_MEM_BASE); - sys_pci_device_bars_write (); - - REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE - | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE); -} - -void sys_pci_bar_info_get (unsigned int devnum, - unsigned int bus, - unsigned int dev, unsigned int func) -{ - unsigned int data32; - unsigned int tmp; - unsigned int size; - - pci_write_config_dword (devnum, - PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_QUERY); - pci_read_config_dword (devnum, PCI_CFG_BASE_ADDRESS_0, &data32); + writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET); - devices[devnum].bar[0].address = (data32 & 1); + writel(0, PCI_CSR_BASE + PCI_INTEN_OFFSET); - if (data32 & 1) { - /* IO space */ - tmp = data32 & ~0x3; - size = ~(tmp - 1); - devices[devnum].bar[0].size = size; - - if (nIOBars < IXP425_PCI_MAX_BAR) { - ioBars[nIOBars++] = &devices[devnum].bar[0]; - } - } else { - /* Mem space */ - tmp = data32 & ~IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - size = ~(tmp - 1); - devices[devnum].bar[0].size = size; - - if (nMBars < IXP425_PCI_MAX_BAR) { - memBars[nMBars++] = &devices[devnum].bar[0]; - } else { - devices[devnum].error = TRUE; - } - - } - - devices[devnum].bar[1].size = 0; -} - -void sortBars (PciBar * Bars[], unsigned int nBars) -{ - unsigned int i, j; - PciBar *tmp; - - if (nBars == 0) { - return; - } - - /* Sort biggest to smallest */ - for (i = 0; i < nBars - 1; i++) { - for (j = i + 1; j < nBars; j++) { - if (Bars[j]->size > Bars[i]->size) { - /* swap them */ - tmp = Bars[i]; - Bars[i] = Bars[j]; - Bars[j] = tmp; - } - } - } -} + /* + * We configure the PCI inbound memory windows to be + * 1:1 mapped to SDRAM + */ + crp_write(PCI_CFG_BASE_ADDRESS_0, 0x00000000); + crp_write(PCI_CFG_BASE_ADDRESS_1, 0x01000000); + crp_write(PCI_CFG_BASE_ADDRESS_2, 0x02000000); + crp_write(PCI_CFG_BASE_ADDRESS_3, 0x03000000); + + /* + * Enable CSR window at 64 MiB to allow PCI masters + * to continue prefetching past 64 MiB boundary. + */ + crp_write(PCI_CFG_BASE_ADDRESS_4, 0x04000000); + /* + * Enable the IO window to be way up high, at 0xfffffc00 + */ + crp_write(PCI_CFG_BASE_ADDRESS_5, 0xfffffc01); -void calc_bars (PciBar * Bars[], unsigned int nBars, unsigned int startAddr) -{ - unsigned int i; + /*Setup PCI-AHB and AHB-PCI address mappings */ + writel(0x00010203, PCI_CSR_BASE + PCI_AHBMEMBASE_OFFSET); - if (nBars == 0) { - return; - } + writel(0x00000000, PCI_CSR_BASE + PCI_AHBIOBASE_OFFSET); - for (i = 0; i < nBars; i++) { - Bars[i]->address |= startAddr; - startAddr += Bars[i]->size; - } -} + writel(0x48494a4b, PCI_CSR_BASE + PCI_PCIMEMBASE_OFFSET); -void sys_pci_device_bars_write (void) -{ - unsigned int i; - int addr; - - for (i = 1; i < nDevices; i++) { - if (devices[i].error) { - continue; - } - - pci_write_config_dword (devices[i].device, - PCI_CFG_BASE_ADDRESS_0, - devices[i].bar[0].address); - addr = BIT (31 - devices[i].device) | - (0 << PCI_NP_AD_FUNCSL) | - (PCI_CFG_BASE_ADDRESS_0 & ~3); - pci_write_config_dword (devices[i].device, - PCI_CFG_DEV_INT_LINE, devices[i].irq); - - pci_write_config_word (devices[i].device, - PCI_CFG_COMMAND, INITIAL_PCI_CMD); + crp_write(PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM); - } -} + crp_write(PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME); + udelay(1000); + /* clear error bits in status register */ + writel(PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE, + PCI_CSR_BASE + PCI_ISR_OFFSET); -int pci_device_exists (unsigned int deviceNo) -{ - unsigned int vendorId; - unsigned int regval; - - pci_read_config_dword (deviceNo, PCI_CFG_VENDOR_ID, &vendorId); - - /* There are two ways to find out an empty device. - * 1. check Master Abort bit after the access. - * 2. check whether the vendor id read back is 0x0. + /* + * Set Initialize Complete in PCI Control Register: allow IXP4XX to + * respond to PCI configuration cycles. */ - REG_READ (PCI_CSR_BASE, PCI_ISR_OFFSET, regval); - if ((vendorId != 0x0) && ((regval & PCI_ISR_PFE) == 0)) { - return TRUE; - } - /*no device present, make sure that the master abort bit is reset */ + csr |= PCI_CSR_IC; + writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET); - REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PFE); - return FALSE; -} + hose->first_busno = 0; + hose->last_busno = 0; -pci_dev_t pci_find_devices (struct pci_device_id * ids, int devNo) -{ - unsigned int i; - unsigned int devdidvid; - unsigned int didvid; - unsigned int vendorId, deviceId; + /* System memory space */ + pci_set_region(hose->regions + 0, + PCI_MEMORY_BUS, + PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY); - vendorId = ids->vendor; - deviceId = ids->device; - didvid = ((deviceId << 16) & IXP425_PCI_TOP_WORD_OF_LONG_MASK) | - (vendorId & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK); + /* PCI memory space */ + pci_set_region(hose->regions + 1, + PCI_MEM_BUS, + PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM); + /* PCI I/O space */ + pci_set_region(hose->regions + 2, + PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO); - for (i = devNo + 1; i < nDevices; i++) { + hose->region_count = 3; - pci_read_config_dword (devices[i].device, PCI_CFG_VENDOR_ID, - &devdidvid); + pci_set_ops(hose, + pci_ixp_hose_read_config_byte, + pci_ixp_hose_read_config_word, + pci_ixp_hose_read_config_dword, + pci_ixp_hose_write_config_byte, + pci_ixp_hose_write_config_word, + pci_ixp_hose_write_config_dword); - if (devdidvid == didvid) { - return devices[i].device; - } - } - return -1; + pci_register_hose(hose); + hose->last_busno = pci_hose_scan(hose); } diff --git a/drivers/rtc/mpc5xxx.c b/drivers/rtc/mpc5xxx.c index ec0b0ef..6b3d5e6 100644 --- a/drivers/rtc/mpc5xxx.c +++ b/drivers/rtc/mpc5xxx.c @@ -44,7 +44,7 @@ typedef struct rtc5200 { volatile ulong aier; /* MBAR+0x80C: alarm and interrupt enable register */ volatile ulong ctr; /* MBAR+0x810: current time register */ volatile ulong cdr; /* MBAR+0x814: current data register */ - volatile ulong asir; /* MBAR+0x818: alarm and stopwatch interupt register */ + volatile ulong asir; /* MBAR+0x818: alarm and stopwatch interrupt register */ volatile ulong piber; /* MBAR+0x81C: periodic interrupt and bus error register */ volatile ulong trdr; /* MBAR+0x820: test register/divides register */ } RTC5200; diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 5a6011e..1dcc1c7 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -28,7 +28,6 @@ LIB := $(obj)libserial.o COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o COBJS-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o -COBJS-$(CONFIG_AT91RM9200_USART) += at91rm9200_usart.o COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o COBJS-$(CONFIG_MCFUART) += mcfuart.o COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o @@ -56,7 +55,10 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o COBJS-$(CONFIG_TEGRA2) += serial_tegra2.o + +ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_USB_TTY) += usbtty.o +endif COBJS := $(sort $(COBJS-y)) SRCS := $(COBJS:.o=.c) diff --git a/drivers/serial/at91rm9200_usart.c b/drivers/serial/at91rm9200_usart.c deleted file mode 100644 index 05ebbc3..0000000 --- a/drivers/serial/at91rm9200_usart.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2002 - * Lineo, Inc <www.lineo.com> - * Bernhard Kuhn <bkuhn@lineo.com> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include <common.h> - -#ifndef CONFIG_AT91_LEGACY -#include <asm/io.h> -#include <asm/arch/hardware.h> -#define CONFIG_AT91_LEGACY -#include <asm/arch-at91rm9200/AT91RM9200.h> -#warning Please update to use C structur SoC access ! -#else -#include <asm/arch/AT91RM9200.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1) -#error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1 -#endif - -/* ggi thunder */ -#ifdef CONFIG_DBGU -AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU; -#endif -#ifdef CONFIG_USART0 -AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US0; -#endif -#ifdef CONFIG_USART1 -AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US1; -#endif - -void serial_setbrg (void) -{ - int baudrate; - - if ((baudrate = gd->baudrate) <= 0) - baudrate = CONFIG_BAUDRATE; - /* MASTER_CLOCK/(16 * baudrate) */ - us->US_BRGR = (AT91C_MASTER_CLOCK >> 4) / (unsigned)baudrate; -} - -int serial_init (void) -{ - /* make any port initializations specific to this port */ -#ifdef CONFIG_DBGU - *AT91C_PIOA_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; /* PA 31 & 30 */ - *AT91C_PMC_PCER = 1 << AT91C_ID_SYS; /* enable clock */ -#endif -#ifdef CONFIG_USART0 - *AT91C_PIOA_PDR = AT91C_PA17_TXD0 | AT91C_PA18_RXD0; - *AT91C_PMC_PCER |= 1 << AT91C_ID_USART0; /* enable clock */ -#endif -#ifdef CONFIG_USART1 - *AT91C_PIOB_PDR = AT91C_PB21_TXD1 | AT91C_PB20_RXD1; - *AT91C_PMC_PCER |= 1 << AT91C_ID_USART1; /* enable clock */ -#endif - serial_setbrg (); - - us->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX; - us->US_CR = AT91C_US_RXEN | AT91C_US_TXEN; - us->US_MR = - (AT91C_US_CLKS_CLOCK | AT91C_US_CHRL_8_BITS | - AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT); - us->US_IMR = ~0ul; - return (0); -} - -void serial_exit (void) -{ - us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX); -} - -void serial_putc (const char c) -{ - if (c == '\n') - serial_putc ('\r'); - while ((us->US_CSR & AT91C_US_TXRDY) == 0); - us->US_THR = c; -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int serial_getc (void) -{ - while ((us->US_CSR & AT91C_US_RXRDY) == 0); - return us->US_RHR; -} - -int serial_tstc (void) -{ - return ((us->US_CSR & AT91C_US_RXRDY) == AT91C_US_RXRDY); -} diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 4032dfd..0d56e78 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -22,6 +22,7 @@ */ #include <common.h> +#include <linux/compiler.h> #include <ns16550.h> #ifdef CONFIG_NS87308 @@ -117,9 +118,8 @@ static NS16550_t serial_ports[4] = { serial_puts_dev(port, s);} /* Serial device descriptor */ -#define INIT_ESERIAL_STRUCTURE(port,name,bus) {\ +#define INIT_ESERIAL_STRUCTURE(port, name) {\ name,\ - bus,\ eserial##port##_init,\ NULL,\ eserial##port##_setbrg,\ @@ -325,14 +325,30 @@ serial_setbrg(void) DECLARE_ESERIAL_FUNCTIONS(1); struct serial_device eserial1_device = - INIT_ESERIAL_STRUCTURE(1,"eserial0","EUART1"); + INIT_ESERIAL_STRUCTURE(1, "eserial0"); DECLARE_ESERIAL_FUNCTIONS(2); struct serial_device eserial2_device = - INIT_ESERIAL_STRUCTURE(2,"eserial1","EUART2"); + INIT_ESERIAL_STRUCTURE(2, "eserial1"); DECLARE_ESERIAL_FUNCTIONS(3); struct serial_device eserial3_device = - INIT_ESERIAL_STRUCTURE(3,"eserial2","EUART3"); + INIT_ESERIAL_STRUCTURE(3, "eserial2"); DECLARE_ESERIAL_FUNCTIONS(4); struct serial_device eserial4_device = - INIT_ESERIAL_STRUCTURE(4,"eserial3","EUART4"); + INIT_ESERIAL_STRUCTURE(4, "eserial3"); + +__weak struct serial_device *default_serial_console(void) +{ +#if CONFIG_CONS_INDEX == 1 + return &eserial1_device; +#elif CONFIG_CONS_INDEX == 2 + return &eserial2_device; +#elif CONFIG_CONS_INDEX == 3 + return &eserial3_device; +#elif CONFIG_CONS_INDEX == 4 + return &eserial4_device; +#else +#error "Bad CONFIG_CONS_INDEX." +#endif +} + #endif /* CONFIG_SERIAL_MULTI */ diff --git a/drivers/serial/serial_ixp.c b/drivers/serial/serial_ixp.c index dd26af4..a9acd47 100644 --- a/drivers/serial/serial_ixp.c +++ b/drivers/serial/serial_ixp.c @@ -30,6 +30,7 @@ #include <common.h> #include <asm/arch/ixp425.h> +#include <watchdog.h> /* * 14.7456 MHz @@ -85,7 +86,8 @@ int serial_init (void) void serial_putc (const char c) { /* wait for room in the tx FIFO on UART */ - while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0); + while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0) + WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */ THR(CONFIG_SYS_IXP425_CONSOLE) = c; @@ -111,7 +113,8 @@ int serial_tstc (void) */ int serial_getc (void) { - while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR)); + while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR)) + WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */ return (char) RBR(CONFIG_SYS_IXP425_CONSOLE) & 0xff; } diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c index e457980..68469a4 100644 --- a/drivers/serial/serial_pxa.c +++ b/drivers/serial/serial_pxa.c @@ -268,7 +268,6 @@ static int ffuart_tstc(void) struct serial_device serial_ffuart_device = { "serial_ffuart", - "PXA", ffuart_init, NULL, ffuart_setbrg, @@ -313,7 +312,6 @@ static int btuart_tstc(void) struct serial_device serial_btuart_device = { "serial_btuart", - "PXA", btuart_init, NULL, btuart_setbrg, @@ -358,7 +356,6 @@ static int stuart_tstc(void) struct serial_device serial_stuart_device = { "serial_stuart", - "PXA", stuart_init, NULL, stuart_setbrg, diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c index f42b15e..12bcdd3 100644 --- a/drivers/serial/serial_s3c24x0.c +++ b/drivers/serial/serial_s3c24x0.c @@ -19,6 +19,7 @@ */ #include <common.h> +#include <linux/compiler.h> #include <asm/arch/s3c24x0_cpu.h> DECLARE_GLOBAL_DATA_PTR; @@ -27,15 +28,9 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_NR S3C24X0_UART0 #elif defined(CONFIG_SERIAL2) -# if defined(CONFIG_TRAB) -# error "TRAB supports only CONFIG_SERIAL1" -# endif #define UART_NR S3C24X0_UART1 #elif defined(CONFIG_SERIAL3) -# if defined(CONFIG_TRAB) -# error "TRAB supports only CONFIG_SERIAL1" -# endif #define UART_NR S3C24X0_UART2 #else @@ -74,9 +69,8 @@ DECLARE_GLOBAL_DATA_PTR; serial_puts_dev(port, s); \ } -#define INIT_S3C_SERIAL_STRUCTURE(port, name, bus) { \ +#define INIT_S3C_SERIAL_STRUCTURE(port, name) { \ name, \ - bus, \ s3serial##port##_init, \ NULL,\ s3serial##port##_setbrg, \ @@ -309,11 +303,24 @@ void serial_puts(const char *s) #if defined(CONFIG_SERIAL_MULTI) DECLARE_S3C_SERIAL_FUNCTIONS(0); struct serial_device s3c24xx_serial0_device = -INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0", "S3UART1"); +INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0"); DECLARE_S3C_SERIAL_FUNCTIONS(1); struct serial_device s3c24xx_serial1_device = -INIT_S3C_SERIAL_STRUCTURE(1, "s3ser1", "S3UART2"); +INIT_S3C_SERIAL_STRUCTURE(1, "s3ser1"); DECLARE_S3C_SERIAL_FUNCTIONS(2); struct serial_device s3c24xx_serial2_device = -INIT_S3C_SERIAL_STRUCTURE(2, "s3ser2", "S3UART3"); +INIT_S3C_SERIAL_STRUCTURE(2, "s3ser2"); + +__weak struct serial_device *default_serial_console(void) +{ +#if defined(CONFIG_SERIAL1) + return &s3c24xx_serial0_device; +#elif defined(CONFIG_SERIAL2) + return &s3c24xx_serial1_device; +#elif defined(CONFIG_SERIAL3) + return &s3c24xx_serial2_device; +#else +#error "CONFIG_SERIAL? missing." +#endif +} #endif /* CONFIG_SERIAL_MULTI */ diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index f1ffa29..6819bb0 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -22,6 +22,7 @@ */ #include <common.h> +#include <linux/compiler.h> #include <asm/io.h> #include <asm/arch/uart.h> #include <asm/arch/clk.h> @@ -182,9 +183,8 @@ int s5p_serial##port##_tstc(void) { return serial_tstc_dev(port); } \ void s5p_serial##port##_putc(const char c) { serial_putc_dev(c, port); } \ void s5p_serial##port##_puts(const char *s) { serial_puts_dev(s, port); } -#define INIT_S5P_SERIAL_STRUCTURE(port, name, bus) { \ +#define INIT_S5P_SERIAL_STRUCTURE(port, name) { \ name, \ - bus, \ s5p_serial##port##_init, \ NULL, \ s5p_serial##port##_setbrg, \ @@ -195,13 +195,28 @@ void s5p_serial##port##_puts(const char *s) { serial_puts_dev(s, port); } DECLARE_S5P_SERIAL_FUNCTIONS(0); struct serial_device s5p_serial0_device = - INIT_S5P_SERIAL_STRUCTURE(0, "s5pser0", "S5PUART0"); + INIT_S5P_SERIAL_STRUCTURE(0, "s5pser0"); DECLARE_S5P_SERIAL_FUNCTIONS(1); struct serial_device s5p_serial1_device = - INIT_S5P_SERIAL_STRUCTURE(1, "s5pser1", "S5PUART1"); + INIT_S5P_SERIAL_STRUCTURE(1, "s5pser1"); DECLARE_S5P_SERIAL_FUNCTIONS(2); struct serial_device s5p_serial2_device = - INIT_S5P_SERIAL_STRUCTURE(2, "s5pser2", "S5PUART2"); + INIT_S5P_SERIAL_STRUCTURE(2, "s5pser2"); DECLARE_S5P_SERIAL_FUNCTIONS(3); struct serial_device s5p_serial3_device = - INIT_S5P_SERIAL_STRUCTURE(3, "s5pser3", "S5PUART3"); + INIT_S5P_SERIAL_STRUCTURE(3, "s5pser3"); + +__weak struct serial_device *default_serial_console(void) +{ +#if defined(CONFIG_SERIAL0) + return &s5p_serial0_device; +#elif defined(CONFIG_SERIAL1) + return &s5p_serial1_device; +#elif defined(CONFIG_SERIAL2) + return &s5p_serial2_device; +#elif defined(CONFIG_SERIAL3) + return &s5p_serial3_device; +#else +#error "CONFIG_SERIAL? missing." +#endif +} diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index a9b1ca4..96c9642 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libspi.o COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o +COBJS-$(CONFIG_ANDES_SPI) += andes_spi.o COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o diff --git a/drivers/spi/andes_spi.c b/drivers/spi/andes_spi.c new file mode 100644 index 0000000..fdde139 --- /dev/null +++ b/drivers/spi/andes_spi.c @@ -0,0 +1,302 @@ +/* + * Driver of Andes SPI Controller + * + * (C) Copyright 2011 Andes Technology + * Macpaul Lin <macpaul@andestech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> + +#include <asm/io.h> +#include "andes_spi.h" + +void spi_init(void) +{ + /* do nothing */ +} + +static void andes_spi_spit_en(struct andes_spi_slave *ds) +{ + unsigned int dcr = readl(&ds->regs->dcr); + + debug("%s: dcr: %x, write value: %x\n", + __func__, dcr, (dcr | ANDES_SPI_DCR_SPIT)); + + writel((dcr | ANDES_SPI_DCR_SPIT), &ds->regs->dcr); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct andes_spi_slave *ds; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ds = malloc(sizeof(*ds)); + if (!ds) + return NULL; + + ds->slave.bus = bus; + ds->slave.cs = cs; + ds->regs = (struct andes_spi_regs *)CONFIG_SYS_SPI_BASE; + + /* + * The hardware of andes_spi will set its frequency according + * to APB/AHB bus clock. Hence the hardware doesn't allow changing of + * requency and so the user requested speed is always ignored. + */ + ds->freq = max_hz; + + return &ds->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct andes_spi_slave *ds = to_andes_spi(slave); + + free(ds); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct andes_spi_slave *ds = to_andes_spi(slave); + unsigned int apb; + unsigned int baud; + + /* Enable the SPI hardware */ + writel(ANDES_SPI_CR_SPIRST, &ds->regs->cr); + udelay(1000); + + /* setup format */ + baud = ((CONFIG_SYS_CLK_FREQ / CONFIG_SYS_SPI_CLK / 2) - 1) & 0xFF; + + /* + * SPI_CLK = AHB bus clock / ((BAUD + 1)*2) + * BAUD = AHB bus clock / SPI_CLK / 2) - 1 + */ + apb = (readl(&ds->regs->apb) & 0xffffff00) | baud; + writel(apb, &ds->regs->apb); + + /* no interrupts */ + writel(0, &ds->regs->ie); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct andes_spi_slave *ds = to_andes_spi(slave); + + /* Disable the SPI hardware */ + writel(ANDES_SPI_CR_SPIRST, &ds->regs->cr); +} + +static int andes_spi_read(struct spi_slave *slave, unsigned int len, + u8 *rxp, unsigned long flags) +{ + struct andes_spi_slave *ds = to_andes_spi(slave); + unsigned int i, left; + unsigned int data; + + debug("%s: slave: %x, len: %d, rxp: %x, flags: %d\n", + __func__, slave, len, rxp, flags); + + debug("%s: data: ", __func__); + while (len > 0) { + left = min(len, 4); + data = readl(&ds->regs->data); + + debug(" "); + for (i = 0; i < left; i++) { + debug("%02x ", data & 0xff); + *rxp++ = data; + data >>= 8; + len--; + } + } + debug("\n"); + + return 0; +} + +static int andes_spi_write(struct spi_slave *slave, unsigned int wlen, + unsigned int rlen, const u8 *txp, unsigned long flags) +{ + struct andes_spi_slave *ds = to_andes_spi(slave); + unsigned int data; + unsigned int i, left; + unsigned int spit_enabled = 0; + + debug("%s: slave: %x, wlen: %d, rlen: %d, txp: %x, flags: %x\n", + __func__, slave, wlen, rlen, txp, flags); + + /* The value of wlen and rlen wrote to register must minus 1 */ + if (rlen == 0) /* write only */ + writel(ANDES_SPI_DCR_MODE_WO | ANDES_SPI_DCR_WCNT(wlen-1) | + ANDES_SPI_DCR_RCNT(0), &ds->regs->dcr); + else /* write then read */ + writel(ANDES_SPI_DCR_MODE_WR | ANDES_SPI_DCR_WCNT(wlen-1) | + ANDES_SPI_DCR_RCNT(rlen-1), &ds->regs->dcr); + + /* wait till SPIBSY is cleared */ + while (readl(&ds->regs->st) & ANDES_SPI_ST_SPIBSY) + ; + + /* data write process */ + debug("%s: txp: ", __func__); + while (wlen > 0) { + /* clear the data */ + data = 0; + + /* data are usually be read 32bits once a time */ + left = min(wlen, 4); + + for (i = 0; i < left; i++) { + debug("%x ", *txp); + data |= *txp++ << (i * 8); + wlen--; + } + debug("\n"); + + debug("data: %08x\n", data); + debug("streg before write: %08x\n", readl(&ds->regs->st)); + /* wait till TXFULL is deasserted */ + while (readl(&ds->regs->st) & ANDES_SPI_ST_TXFEL) + ; + writel(data, &ds->regs->data); + debug("streg after write: %08x\n", readl(&ds->regs->st)); + + + if (spit_enabled == 0) { + /* enable SPIT bit - trigger the tx and rx progress */ + andes_spi_spit_en(ds); + spit_enabled = 1; + } + + } + debug("\n"); + + return 0; +} + +/* + * spi_xfer: + * Since andes_spi doesn't support independent command transaction, + * that is, write and than read must be operated in continuous + * execution, there is no need to set dcr and trigger spit again in + * RX process. + */ +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + unsigned int len; + static int op_nextime; + static u8 tmp_cmd[5]; + static int tmp_wlen; + unsigned int i; + + if (bitlen == 0) + /* Finish any previously submitted transfers */ + goto out; + + if (bitlen % 8) { + /* Errors always terminate an ongoing transfer */ + flags |= SPI_XFER_END; + goto out; + } + + len = bitlen / 8; + + debug("%s: slave: %08x, bitlen: %d, dout: " + "%08x, din: %08x, flags: %d, len: %d\n", + __func__, slave, bitlen, dout, din, flags, len); + + /* + * Important: + * andes_spi's hardware doesn't support 2 data channel. The read + * and write cmd/data share the same register (data register). + * + * If a command has write and read transaction, you cannot do write + * this time and then do read on next time. + * + * A command writes first with a read response must indicating + * the read length in write operation. Hence the write action must + * be stored temporary and wait until the next read action has been + * arrived. Then we flush the write and read action out together. + */ + if (!dout) { + if (op_nextime == 1) { + /* flags should be SPI_XFER_END, value is 2 */ + op_nextime = 0; + andes_spi_write(slave, tmp_wlen, len, tmp_cmd, flags); + } + return andes_spi_read(slave, len, din, flags); + } else if (!din) { + if (flags == SPI_XFER_BEGIN) { + /* store the write command and do operation next time */ + op_nextime = 1; + memset(tmp_cmd, 0, sizeof(tmp_cmd)); + memcpy(tmp_cmd, dout, len); + + debug("%s: tmp_cmd: ", __func__); + for (i = 0; i < len; i++) + debug("%x ", *(tmp_cmd + i)); + debug("\n"); + + tmp_wlen = len; + } else { + /* + * flags should be (SPI_XFER_BEGIN | SPI_XFER_END), + * the value is 3. + */ + if (op_nextime == 1) { + /* flags should be SPI_XFER_END, value is 2 */ + op_nextime = 0; + /* flags 3 implies write only */ + andes_spi_write(slave, tmp_wlen, 0, tmp_cmd, 3); + } + + debug("flags: %x\n", flags); + return andes_spi_write(slave, len, 0, dout, flags); + } + } + +out: + return 0; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* do nothing */ +} diff --git a/drivers/spi/andes_spi.h b/drivers/spi/andes_spi.h new file mode 100644 index 0000000..844bdba --- /dev/null +++ b/drivers/spi/andes_spi.h @@ -0,0 +1,128 @@ +/* + * Register definitions for the Andes SPI Controller + * + * (C) Copyright 2011 Andes Technology + * Macpaul Lin <macpaul@andestech.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ANDES_SPI_H +#define __ANDES_SPI_H + +struct andes_spi_regs { + unsigned int apb; /* 0x00 - APB SPI interface setting */ + unsigned int pio; /* 0x04 - PIO reg */ + unsigned int cr; /* 0x08 - SPI Control reg */ + unsigned int st; /* 0x0c - SPI Status reg */ + unsigned int ie; /* 0x10 - Interrupt Enable reg */ + unsigned int ist; /* 0x14 - Interrupt Status reg */ + unsigned int dcr; /* 0x18 - data control reg */ + unsigned int data; /* 0x1c - data register */ + unsigned int ahb; /* 0x20 - AHB SPI interface setting */ + unsigned int ver; /* 0x3c - SPI version reg */ +}; + +#define BIT(x) (1 << (x)) + +/* 0x00 - APB SPI interface setting register */ +#define ANDES_SPI_APB_BAUD(x) (((x) & 0xff) < 0) +#define ANDES_SPI_APB_CSHT(x) (((x) & 0xf) < 16) +#define ANDES_SPI_APB_SPNTS BIT(20) /* 0: normal, 1: delay */ +#define ANDES_SPI_APB_CPHA BIT(24) /* 0: Sampling at odd edges */ +#define ANDES_SPI_APB_CPOL BIT(25) /* 0: SCK low, 1: SCK high */ +#define ANDES_SPI_APB_MSSL BIT(26) /* 0: SPI Master, 1: slave */ + +/* 0x04 - PIO register */ +#define ANDES_SPI_PIO_MISO BIT(0) /* input value of pin MISO */ +#define ANDES_SPI_PIO_MOSI BIT(1) /* I/O value of pin MOSI */ +#define ANDES_SPI_PIO_SCK BIT(2) /* I/O value of pin SCK */ +#define ANDES_SPI_PIO_CS BIT(3) /* I/O value of pin CS */ +#define ANDES_SPI_PIO_PIOE BIT(4) /* Programming IO Enable */ + +/* 0x08 - SPI Control register */ +#define ANDES_SPI_CR_SPIRST BIT(0) /* SPI mode reset */ +#define ANDES_SPI_CR_RXFRST BIT(1) /* RxFIFO reset */ +#define ANDES_SPI_CR_TXFRST BIT(2) /* TxFIFO reset */ +#define ANDES_SPI_CR_RXFTH(x) (((x) & 0x1f) << 10) /* RxFIFO Threshold */ +#define ANDES_SPI_CR_TXFTH(x) (((x) & 0x1f) << 18) /* TxFIFO Threshold */ + +/* 0x0c - SPI Status register */ +#define ANDES_SPI_ST_SPIBSY BIT(0) /* SPI Transfer is active */ +#define ANDES_SPI_ST_RXFEM BIT(8) /* RxFIFO Empty Flag */ +#define ANDES_SPI_ST_RXFEL BIT(9) /* RxFIFO Full Flag */ +#define ANDES_SPI_ST_RXFVE(x) (((x) >> 10) & 0x1f) +#define ANDES_SPI_ST_TXFEM BIT(16) /* TxFIFO Empty Flag */ +#define ANDES_SPI_ST_TXFEL BIT(7) /* TxFIFO Full Flag */ +#define ANDES_SPI_ST_TXFVE(x) (((x) >> 18) & 0x1f) + +/* 0x10 - Interrupt Enable register */ +#define ANDES_SPI_IE_RXFORIE BIT(0) /* RxFIFO overrun intr */ +#define ANDES_SPI_IE_TXFURIE BIT(1) /* TxFOFO underrun intr */ +#define ANDES_SPI_IE_RXFTHIE BIT(2) /* RxFIFO threshold intr */ +#define ANDES_SPI_IE_TXFTHIE BIT(3) /* TxFIFO threshold intr */ +#define ANDES_SPI_IE_SPIEIE BIT(4) /* SPI transmit END intr */ +#define ANDES_SPI_IE_SPCFIE BIT(5) /* AHB/APB TxReq conflict */ + +/* 0x14 - Interrupt Status Register */ +#define ANDES_SPI_IST_RXFORI BIT(0) /* has RxFIFO overrun */ +#define ANDES_SPI_IST_TXFURI BIT(1) /* has TxFOFO underrun */ +#define ANDES_SPI_IST_RXFTHI BIT(2) /* has RxFIFO threshold */ +#define ANDES_SPI_IST_TXFTHI BIT(3) /* has TxFIFO threshold */ +#define ANDES_SPI_IST_SPIEI BIT(4) /* has SPI transmit END */ +#define ANDES_SPI_IST_SPCFI BIT(5) /* has AHB/APB TxReq conflict */ + +/* 0x18 - Data Control Register */ +#define ANDES_SPI_DCR_RCNT(x) (((x) & 0x3ff) << 0) +#define ANDES_SPI_DCR_DYCNT(x) (((x) & 0x7) << 12) +#define ANDES_SPI_DCR_WCNT(x) (((x) & 0x3ff) << 16) +#define ANDES_SPI_DCR_TRAMODE(x) (((x) & 0x7) << 28) +#define ANDES_SPI_DCR_SPIT BIT(31) /* SPI bus trigger */ + +#define ANDES_SPI_DCR_MODE_WRCON ANDES_SPI_DCR_TRAMODE(0) /* w/r at the same time */ +#define ANDES_SPI_DCR_MODE_WO ANDES_SPI_DCR_TRAMODE(1) /* write only */ +#define ANDES_SPI_DCR_MODE_RO ANDES_SPI_DCR_TRAMODE(2) /* read only */ +#define ANDES_SPI_DCR_MODE_WR ANDES_SPI_DCR_TRAMODE(3) /* write, read */ +#define ANDES_SPI_DCR_MODE_RW ANDES_SPI_DCR_TRAMODE(4) /* read, write */ +#define ANDES_SPI_DCR_MODE_WDR ANDES_SPI_DCR_TRAMODE(5) /* write, dummy, read */ +#define ANDES_SPI_DCR_MODE_RDW ANDES_SPI_DCR_TRAMODE(6) /* read, dummy, write */ +#define ANDES_SPI_DCR_MODE_RECEIVE ANDES_SPI_DCR_TRAMODE(7) /* receive */ + +/* 0x20 - AHB SPI interface setting register */ +#define ANDES_SPI_AHB_BAUD(x) (((x) & 0xff) < 0) +#define ANDES_SPI_AHB_CSHT(x) (((x) & 0xf) < 16) +#define ANDES_SPI_AHB_SPNTS BIT(20) /* 0: normal, 1: delay */ +#define ANDES_SPI_AHB_CPHA BIT(24) /* 0: Sampling at odd edges */ +#define ANDES_SPI_AHB_CPOL BIT(25) /* 0: SCK low, 1: SCK high */ +#define ANDES_SPI_AHB_MSSL BIT(26) /* only Master mode */ + +/* 0x3c - Version Register - (Year V.MAJOR.MINOR) */ +#define ANDES_SPI_VER_MINOR(x) (((x) >> 0) & 0xf) +#define ANDES_SPI_VER_MAJOR(x) (((x) >> 8) & 0xf) +#define ANDES_SPI_VER_YEAR(x) (((x) >> 16) & 0xf) + +struct andes_spi_slave { + struct spi_slave slave; + struct andes_spi_regs *regs; + unsigned int freq; +}; + +static inline struct andes_spi_slave *to_andes_spi(struct spi_slave *slave) +{ + return container_of(slave, struct andes_spi_slave, slave); +} + +#endif /* __ANDES_SPI_H */ diff --git a/drivers/spi/atmel_dataflash_spi.c b/drivers/spi/atmel_dataflash_spi.c index 9c991e8..363e07a 100644 --- a/drivers/spi/atmel_dataflash_spi.c +++ b/drivers/spi/atmel_dataflash_spi.c @@ -19,12 +19,21 @@ * */ +/* + * This driver desperately needs rework: + * + * - use structure SoC access + * - get rid of including asm/arch/at91_spi.h + * - remove asm/arch/at91_spi.h + * - get rid of all CONFIG_ATMEL_LEGACY defines and uses + * + * 02-Aug-2010 Reinhard Meyer <uboot@emk-elektronik.de> + */ + #include <common.h> -#ifndef CONFIG_AT91_LEGACY +#ifndef CONFIG_ATMEL_LEGACY # define CONFIG_ATMEL_LEGACY -# warning Please update to use C structure SoC access ! #endif -#include <common.h> #include <spi.h> #include <malloc.h> diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index f909e07..81381d9 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -31,7 +31,7 @@ /* i.MX27 has a completely wrong register layout and register definitions in the * datasheet, the correct one is in the Freescale's Linux driver */ -#error "i.MX27 CSPI not supported due to drastic differences in register definisions" \ +#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \ "See linux mxc_spi driver from Freescale for details." #elif defined(CONFIG_MX31) @@ -60,8 +60,6 @@ static unsigned long spi_bases[] = { 0x53f84000, }; -#define mxc_get_clock(x) mx31_get_ipg_clk() - #elif defined(CONFIG_MX51) #define MXC_CSPICTRL_EN (1 << 0) diff --git a/drivers/usb/eth/Makefile b/drivers/usb/eth/Makefile index 6a5f25a..a8e9eff 100644 --- a/drivers/usb/eth/Makefile +++ b/drivers/usb/eth/Makefile @@ -21,7 +21,7 @@ include $(TOPDIR)/config.mk -LIB := $(obj)libusb_eth.a +LIB := $(obj)libusb_eth.o # new USB host ethernet layer dependencies COBJS-$(CONFIG_USB_HOST_ETHER) += usb_ether.o @@ -36,7 +36,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) all: $(LIB) $(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index 6af35ab..a0cfbb7 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -29,6 +29,14 @@ #define USBCTRL_OTGBASE_OFFSET 0x600 +#ifdef CONFIG_MX25 +#define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6) +#define MX25_USB_CTRL_HSTD_BIT (1<<5) +#define MX25_USB_CTRL_USBTE_BIT (1<<4) +#define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3) +#endif + +#ifdef CONFIG_MX31 #define MX31_OTG_SIC_SHIFT 29 #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) #define MX31_OTG_PM_BIT (1 << 24) @@ -42,12 +50,19 @@ #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) #define MX31_H1_PM_BIT (1 << 8) #define MX31_H1_DT_BIT (1 << 4) +#endif static int mxc_set_usbcontrol(int port, unsigned int flags) { unsigned int v; + +#ifdef CONFIG_MX25 + v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT | + MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT; +#endif + #ifdef CONFIG_MX31 - v = readl(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET); + v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); switch (port) { case 0: /* OTG port */ @@ -85,36 +100,38 @@ static int mxc_set_usbcontrol(int port, unsigned int flags) default: return -EINVAL; } - - writel(v, MX31_OTG_BASE_ADDR + - USBCTRL_OTGBASE_OFFSET); #endif - return 0; + + writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); + return 0; } int ehci_hcd_init(void) { - u32 tmp; struct usb_ehci *ehci; +#ifdef CONFIG_MX31 + u32 tmp; struct clock_control_regs *sc_regs = (struct clock_control_regs *)CCM_BASE; tmp = __raw_readl(&sc_regs->ccmr); __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ; +#endif udelay(80); /* Take USB2 */ - ehci = (struct usb_ehci *)(MX31_OTG_BASE_ADDR + + ehci = (struct usb_ehci *)(IMX_USB_BASE + (0x200 * CONFIG_MXC_USB_PORT)); hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); setbits_le32(&ehci->usbmode, CM_HOST); +#ifdef CONFIG_MX31 setbits_le32(&ehci->control, USB_EN); __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); - +#endif mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); udelay(10000); diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index 4abe5e3..020ab11 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -42,7 +42,6 @@ static struct pci_device_id ehci_pci_ids[] = { int ehci_hcd_init(void) { pci_dev_t pdev; - uint32_t addr; pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVICE); if (pdev == -1) { @@ -50,8 +49,8 @@ int ehci_hcd_init(void) return -1; } - pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &addr); - hccr = (struct ehci_hccr *)addr; + hccr = (struct ehci_hccr *)pci_map_bar(pdev, + PCI_BASE_ADDRESS_0, PCI_REGION_MEM); hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); diff --git a/drivers/usb/musb/da8xx.h b/drivers/usb/musb/da8xx.h index b9660ba..be1cdaf 100644 --- a/drivers/usb/musb/da8xx.h +++ b/drivers/usb/musb/da8xx.h @@ -25,7 +25,7 @@ #define __DA8XX_MUSB_H__ #include <asm/arch/hardware.h> -#include <asm/arch/gpio_defs.h> +#include <asm/arch/gpio.h> #include "musb_core.h" /* Base address of da8xx usb0 wrapper */ diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c index 8b0c61d..974bb31 100644 --- a/drivers/usb/musb/musb_hcd.c +++ b/drivers/usb/musb/musb_hcd.c @@ -853,8 +853,11 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, #ifdef MUSB_NO_MULTIPOINT /* Control message is for the HUB? */ - if (devnum == rh_devnum) - return musb_submit_rh_msg(dev, pipe, buffer, len, setup); + if (devnum == rh_devnum) { + int stat = musb_submit_rh_msg(dev, pipe, buffer, len, setup); + if (stat) + return stat; + } #endif /* select control endpoint */ diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index b427c84..3a93b64 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -29,75 +29,83 @@ * At the moment only the 8x16 font is tested and the font fore- and * background color is limited to black/white/gray colors. The Linux * logo can be placed in the upper left corner and additional board - * information strings (that normaly goes to serial port) can be drawed. + * information strings (that normally goes to serial port) can be drawn. * * The console driver can use the standard PC keyboard interface (i8042) * for character input. Character output goes to a memory mapped video * framebuffer with little or big-endian organisation. * With environment setting 'console=serial' the console i/o can be * forced to serial port. - - The driver uses graphic specific defines/parameters/functions: - - (for SMI LynxE graphic chip) - - CONFIG_VIDEO_SMI_LYNXEM - use graphic driver for SMI 710,712,810 - VIDEO_FB_LITTLE_ENDIAN - framebuffer organisation default: big endian - VIDEO_HW_RECTFILL - graphic driver supports hardware rectangle fill - VIDEO_HW_BITBLT - graphic driver supports hardware bit blt - - Console Parameters are set by graphic drivers global struct: - - VIDEO_VISIBLE_COLS - x resolution - VIDEO_VISIBLE_ROWS - y resolution - VIDEO_PIXEL_SIZE - storage size in byte per pixel - VIDEO_DATA_FORMAT - graphical data format GDF - VIDEO_FB_ADRS - start of video memory - - CONFIG_I8042_KBD - AT Keyboard driver for i8042 - VIDEO_KBD_INIT_FCT - init function for keyboard - VIDEO_TSTC_FCT - keyboard_tstc function - VIDEO_GETC_FCT - keyboard_getc function - - CONFIG_CONSOLE_CURSOR - on/off drawing cursor is done with delay - loop in VIDEO_TSTC_FCT (i8042) - CONFIG_SYS_CONSOLE_BLINK_COUNT - value for delay loop - blink rate - CONFIG_CONSOLE_TIME - display time/date in upper right corner, - needs CONFIG_CMD_DATE and CONFIG_CONSOLE_CURSOR - CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner - CONFIG_VIDEO_BMP_LOGO - use bmp_logo instead of linux_logo - CONFIG_CONSOLE_EXTRA_INFO - display additional board information strings - that normaly goes to serial port. This define - requires a board specific function: - video_drawstring (VIDEO_INFO_X, - VIDEO_INFO_Y + i*VIDEO_FONT_HEIGHT, - info); - that fills a info buffer at i=row. - s.a: board/eltec/bab7xx. -CONFIG_VGA_AS_SINGLE_DEVICE - If set the framebuffer device will be initialised - as an output only device. The Keyboard driver - will not be set-up. This may be used, if you - have none or more than one Keyboard devices - (USB Keyboard, AT Keyboard). - -CONFIG_VIDEO_SW_CURSOR: - Draws a cursor after the last character. No - blinking is provided. Uses the macros CURSOR_SET - and CURSOR_OFF. -CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the - graphic chip. Uses the macro CURSOR_SET. - ATTENTION: If booting an OS, the display driver - must disable the hardware register of the graphic - chip. Otherwise a blinking field is displayed -*/ + * + * The driver uses graphic specific defines/parameters/functions: + * + * (for SMI LynxE graphic chip) + * + * CONFIG_VIDEO_SMI_LYNXEM - use graphic driver for SMI 710,712,810 + * VIDEO_FB_LITTLE_ENDIAN - framebuffer organisation default: big endian + * VIDEO_HW_RECTFILL - graphic driver supports hardware rectangle fill + * VIDEO_HW_BITBLT - graphic driver supports hardware bit blt + * + * Console Parameters are set by graphic drivers global struct: + * + * VIDEO_VISIBLE_COLS - x resolution + * VIDEO_VISIBLE_ROWS - y resolution + * VIDEO_PIXEL_SIZE - storage size in byte per pixel + * VIDEO_DATA_FORMAT - graphical data format GDF + * VIDEO_FB_ADRS - start of video memory + * + * CONFIG_I8042_KBD - AT Keyboard driver for i8042 + * VIDEO_KBD_INIT_FCT - init function for keyboard + * VIDEO_TSTC_FCT - keyboard_tstc function + * VIDEO_GETC_FCT - keyboard_getc function + * + * CONFIG_CONSOLE_CURSOR - on/off drawing cursor is done with + * delay loop in VIDEO_TSTC_FCT (i8042) + * + * CONFIG_SYS_CONSOLE_BLINK_COUNT - value for delay loop - blink rate + * CONFIG_CONSOLE_TIME - display time/date in upper right + * corner, needs CONFIG_CMD_DATE and + * CONFIG_CONSOLE_CURSOR + * CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner + * CONFIG_VIDEO_BMP_LOGO - use bmp_logo instead of linux_logo + * CONFIG_CONSOLE_EXTRA_INFO - display additional board information + * strings that normaly goes to serial + * port. This define requires a board + * specific function: + * video_drawstring (VIDEO_INFO_X, + * VIDEO_INFO_Y + i*VIDEO_FONT_HEIGHT, + * info); + * that fills a info buffer at i=row. + * s.a: board/eltec/bab7xx. + * CONFIG_VGA_AS_SINGLE_DEVICE - If set the framebuffer device will be + * initialized as an output only device. + * The Keyboard driver will not be + * set-up. This may be used, if you have + * no or more than one Keyboard devices + * (USB Keyboard, AT Keyboard). + * + * CONFIG_VIDEO_SW_CURSOR: - Draws a cursor after the last + * character. No blinking is provided. + * Uses the macros CURSOR_SET and + * CURSOR_OFF. + * + * CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability + * of the graphic chip. Uses the macro + * CURSOR_SET. ATTENTION: If booting an + * OS, the display driver must disable + * the hardware register of the graphic + * chip. Otherwise a blinking field is + * displayed. + */ #include <common.h> - +#include <version.h> #include <malloc.h> -/*****************************************************************************/ -/* Console device defines with SMI graphic */ -/* Any other graphic must change this section */ -/*****************************************************************************/ +/* + * Console device defines with SMI graphic + * Any other graphic must change this section + */ #ifdef CONFIG_VIDEO_SMI_LYNXEM @@ -106,9 +114,9 @@ CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the #define VIDEO_HW_BITBLT #endif -/*****************************************************************************/ -/* Defines for the CT69000 driver */ -/*****************************************************************************/ +/* + * Defines for the CT69000 driver + */ #ifdef CONFIG_VIDEO_CT69000 #define VIDEO_FB_LITTLE_ENDIAN @@ -116,9 +124,9 @@ CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the #define VIDEO_HW_BITBLT #endif -/*****************************************************************************/ -/* Defines for the SED13806 driver */ -/*****************************************************************************/ +/* + * Defines for the SED13806 driver + */ #ifdef CONFIG_VIDEO_SED13806 #ifndef CONFIG_TOTAL5200 @@ -128,9 +136,9 @@ CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the #define VIDEO_HW_BITBLT #endif -/*****************************************************************************/ -/* Defines for the SED13806 driver */ -/*****************************************************************************/ +/* + * Defines for the SED13806 driver + */ #ifdef CONFIG_VIDEO_SM501 #ifdef CONFIG_HH405 @@ -138,9 +146,9 @@ CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the #endif #endif -/*****************************************************************************/ -/* Defines for the MB862xx driver */ -/*****************************************************************************/ +/* + * Defines for the MB862xx driver + */ #ifdef CONFIG_VIDEO_MB862xx #ifdef CONFIG_VIDEO_CORALP @@ -152,24 +160,24 @@ CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the #endif #endif -/*****************************************************************************/ -/* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc */ -/*****************************************************************************/ +/* + * Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc. + */ #include <video_fb.h> -/*****************************************************************************/ -/* some Macros */ -/*****************************************************************************/ +/* + * some Macros + */ #define VIDEO_VISIBLE_COLS (pGD->winSizeX) #define VIDEO_VISIBLE_ROWS (pGD->winSizeY) #define VIDEO_PIXEL_SIZE (pGD->gdfBytesPP) #define VIDEO_DATA_FORMAT (pGD->gdfIndex) #define VIDEO_FB_ADRS (pGD->frameAdrs) -/*****************************************************************************/ -/* Console device defines with i8042 keyboard controller */ -/* Any other keyboard controller must change this section */ -/*****************************************************************************/ +/* + * Console device defines with i8042 keyboard controller + * Any other keyboard controller must change this section + */ #ifdef CONFIG_I8042_KBD #include <i8042.h> @@ -179,9 +187,9 @@ CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the #define VIDEO_GETC_FCT i8042_getc #endif -/*****************************************************************************/ -/* Console device */ -/*****************************************************************************/ +/* + * Console device + */ #include <version.h> #include <linux/types.h> @@ -202,20 +210,20 @@ CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the #endif -/*****************************************************************************/ -/* Cursor definition: */ -/* CONFIG_CONSOLE_CURSOR: Uses a timer function (see drivers/input/i8042.c) */ -/* to let the cursor blink. Uses the macros */ -/* CURSOR_OFF and CURSOR_ON. */ -/* CONFIG_VIDEO_SW_CURSOR: Draws a cursor after the last character. No */ -/* blinking is provided. Uses the macros CURSOR_SET */ -/* and CURSOR_OFF. */ -/* CONFIG_VIDEO_HW_CURSOR: Uses the hardware cursor capability of the */ -/* graphic chip. Uses the macro CURSOR_SET. */ -/* ATTENTION: If booting an OS, the display driver */ -/* must disable the hardware register of the graphic */ -/* chip. Otherwise a blinking field is displayed */ -/*****************************************************************************/ +/* + * Cursor definition: + * CONFIG_CONSOLE_CURSOR: Uses a timer function (see drivers/input/i8042.c) + * to let the cursor blink. Uses the macros + * CURSOR_OFF and CURSOR_ON. + * CONFIG_VIDEO_SW_CURSOR: Draws a cursor after the last character. No + * blinking is provided. Uses the macros CURSOR_SET + * and CURSOR_OFF. + * CONFIG_VIDEO_HW_CURSOR: Uses the hardware cursor capability of the + * graphic chip. Uses the macro CURSOR_SET. + * ATTENTION: If booting an OS, the display driver + * must disable the hardware register of the graphic + * chip. Otherwise a blinking field is displayed + */ #if !defined(CONFIG_CONSOLE_CURSOR) && \ !defined(CONFIG_VIDEO_SW_CURSOR) && \ !defined(CONFIG_VIDEO_HW_CURSOR) @@ -227,9 +235,11 @@ CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the #ifdef CONFIG_CONSOLE_CURSOR #ifdef CURSOR_ON -#error only one of CONFIG_CONSOLE_CURSOR,CONFIG_VIDEO_SW_CURSOR,CONFIG_VIDEO_HW_CURSOR can be defined +#error only one of CONFIG_CONSOLE_CURSOR, CONFIG_VIDEO_SW_CURSOR, \ + or CONFIG_VIDEO_HW_CURSOR can be defined #endif -void console_cursor (int state); +void console_cursor(int state); + #define CURSOR_ON console_cursor(1) #define CURSOR_OFF console_cursor(0) #define CURSOR_SET @@ -244,7 +254,8 @@ void console_cursor (int state); #ifdef CONFIG_VIDEO_SW_CURSOR #ifdef CURSOR_ON -#error only one of CONFIG_CONSOLE_CURSOR,CONFIG_VIDEO_SW_CURSOR,CONFIG_VIDEO_HW_CURSOR can be defined +#error only one of CONFIG_CONSOLE_CURSOR, CONFIG_VIDEO_SW_CURSOR, \ + or CONFIG_VIDEO_HW_CURSOR can be defined #endif #define CURSOR_ON #define CURSOR_OFF video_putchar(console_col * VIDEO_FONT_WIDTH,\ @@ -255,13 +266,14 @@ void console_cursor (int state); #ifdef CONFIG_VIDEO_HW_CURSOR #ifdef CURSOR_ON -#error only one of CONFIG_CONSOLE_CURSOR,CONFIG_VIDEO_SW_CURSOR,CONFIG_VIDEO_HW_CURSOR can be defined +#error only one of CONFIG_CONSOLE_CURSOR, CONFIG_VIDEO_SW_CURSOR, \ + or CONFIG_VIDEO_HW_CURSOR can be defined #endif #define CURSOR_ON #define CURSOR_OFF #define CURSOR_SET video_set_hw_cursor(console_col * VIDEO_FONT_WIDTH, \ (console_row * VIDEO_FONT_HEIGHT) + video_logo_height) -#endif /* CONFIG_VIDEO_HW_CURSOR */ +#endif /* CONFIG_VIDEO_HW_CURSOR */ #ifdef CONFIG_VIDEO_LOGO #ifdef CONFIG_VIDEO_BMP_LOGO @@ -271,7 +283,7 @@ void console_cursor (int state); #define VIDEO_LOGO_LUT_OFFSET BMP_LOGO_OFFSET #define VIDEO_LOGO_COLORS BMP_LOGO_COLORS -#else /* CONFIG_VIDEO_BMP_LOGO */ +#else /* CONFIG_VIDEO_BMP_LOGO */ #define LINUX_LOGO_WIDTH 80 #define LINUX_LOGO_HEIGHT 80 #define LINUX_LOGO_COLORS 214 @@ -282,13 +294,13 @@ void console_cursor (int state); #define VIDEO_LOGO_HEIGHT LINUX_LOGO_HEIGHT #define VIDEO_LOGO_LUT_OFFSET LINUX_LOGO_LUT_OFFSET #define VIDEO_LOGO_COLORS LINUX_LOGO_COLORS -#endif /* CONFIG_VIDEO_BMP_LOGO */ +#endif /* CONFIG_VIDEO_BMP_LOGO */ #define VIDEO_INFO_X (VIDEO_LOGO_WIDTH) #define VIDEO_INFO_Y (VIDEO_FONT_HEIGHT/2) -#else /* CONFIG_VIDEO_LOGO */ +#else /* CONFIG_VIDEO_LOGO */ #define VIDEO_LOGO_WIDTH 0 #define VIDEO_LOGO_HEIGHT 0 -#endif /* CONFIG_VIDEO_LOGO */ +#endif /* CONFIG_VIDEO_LOGO */ #define VIDEO_COLS VIDEO_VISIBLE_COLS #define VIDEO_ROWS VIDEO_VISIBLE_ROWS @@ -313,101 +325,107 @@ void console_cursor (int state); /* Macros */ #ifdef VIDEO_FB_LITTLE_ENDIAN -#define SWAP16(x) ((((x) & 0x00ff) << 8) | ( (x) >> 8)) -#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\ - (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) ) -#define SHORTSWAP32(x) ((((x) & 0x000000ff) << 8) | (((x) & 0x0000ff00) >> 8)|\ - (((x) & 0x00ff0000) << 8) | (((x) & 0xff000000) >> 8) ) +#define SWAP16(x) ((((x) & 0x00ff) << 8) | \ + ((x) >> 8) \ + ) +#define SWAP32(x) ((((x) & 0x000000ff) << 24) | \ + (((x) & 0x0000ff00) << 8) | \ + (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0xff000000) >> 24) \ + ) +#define SHORTSWAP32(x) ((((x) & 0x000000ff) << 8) | \ + (((x) & 0x0000ff00) >> 8) | \ + (((x) & 0x00ff0000) << 8) | \ + (((x) & 0xff000000) >> 8) \ + ) #else -#define SWAP16(x) (x) -#define SWAP32(x) (x) +#define SWAP16(x) (x) +#define SWAP32(x) (x) #if defined(VIDEO_FB_16BPP_WORD_SWAP) -#define SHORTSWAP32(x) ( ((x) >> 16) | ((x) << 16) ) +#define SHORTSWAP32(x) (((x) >> 16) | ((x) << 16)) #else -#define SHORTSWAP32(x) (x) -#endif +#define SHORTSWAP32(x) (x) #endif - -#if defined(DEBUG) || defined(DEBUG_CFB_CONSOLE) -#define PRINTD(x) printf(x) -#else -#define PRINTD(x) #endif - #ifdef CONFIG_CONSOLE_EXTRA_INFO -extern void video_get_info_str ( /* setup a board string: type, speed, etc. */ - int line_number, /* location to place info string beside logo */ - char *info /* buffer for info string */ - ); - +/* + * setup a board string: type, speed, etc. + * + * line_number: location to place info string beside logo + * info: buffer for info string + */ +extern void video_get_info_str(int line_number, char *info); #endif /* Locals */ static GraphicDevice *pGD; /* Pointer to Graphic array */ -static void *video_fb_address; /* frame buffer address */ +static void *video_fb_address; /* frame buffer address */ static void *video_console_address; /* console buffer start address */ static int video_logo_height = VIDEO_LOGO_HEIGHT; -static int console_col = 0; /* cursor col */ -static int console_row = 0; /* cursor row */ +static int console_col; /* cursor col */ +static int console_row; /* cursor row */ -static u32 eorx, fgx, bgx; /* color pats */ +static u32 eorx, fgx, bgx; /* color pats */ static const int video_font_draw_table8[] = { - 0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff, - 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff, - 0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff, - 0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff }; + 0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff, + 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff, + 0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff, + 0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff +}; static const int video_font_draw_table15[] = { - 0x00000000, 0x00007fff, 0x7fff0000, 0x7fff7fff }; + 0x00000000, 0x00007fff, 0x7fff0000, 0x7fff7fff +}; static const int video_font_draw_table16[] = { - 0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff }; + 0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff +}; static const int video_font_draw_table24[16][3] = { - { 0x00000000, 0x00000000, 0x00000000 }, - { 0x00000000, 0x00000000, 0x00ffffff }, - { 0x00000000, 0x0000ffff, 0xff000000 }, - { 0x00000000, 0x0000ffff, 0xffffffff }, - { 0x000000ff, 0xffff0000, 0x00000000 }, - { 0x000000ff, 0xffff0000, 0x00ffffff }, - { 0x000000ff, 0xffffffff, 0xff000000 }, - { 0x000000ff, 0xffffffff, 0xffffffff }, - { 0xffffff00, 0x00000000, 0x00000000 }, - { 0xffffff00, 0x00000000, 0x00ffffff }, - { 0xffffff00, 0x0000ffff, 0xff000000 }, - { 0xffffff00, 0x0000ffff, 0xffffffff }, - { 0xffffffff, 0xffff0000, 0x00000000 }, - { 0xffffffff, 0xffff0000, 0x00ffffff }, - { 0xffffffff, 0xffffffff, 0xff000000 }, - { 0xffffffff, 0xffffffff, 0xffffffff } }; + {0x00000000, 0x00000000, 0x00000000}, + {0x00000000, 0x00000000, 0x00ffffff}, + {0x00000000, 0x0000ffff, 0xff000000}, + {0x00000000, 0x0000ffff, 0xffffffff}, + {0x000000ff, 0xffff0000, 0x00000000}, + {0x000000ff, 0xffff0000, 0x00ffffff}, + {0x000000ff, 0xffffffff, 0xff000000}, + {0x000000ff, 0xffffffff, 0xffffffff}, + {0xffffff00, 0x00000000, 0x00000000}, + {0xffffff00, 0x00000000, 0x00ffffff}, + {0xffffff00, 0x0000ffff, 0xff000000}, + {0xffffff00, 0x0000ffff, 0xffffffff}, + {0xffffffff, 0xffff0000, 0x00000000}, + {0xffffffff, 0xffff0000, 0x00ffffff}, + {0xffffffff, 0xffffffff, 0xff000000}, + {0xffffffff, 0xffffffff, 0xffffffff} +}; static const int video_font_draw_table32[16][4] = { - { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, - { 0x00000000, 0x00000000, 0x00000000, 0x00ffffff }, - { 0x00000000, 0x00000000, 0x00ffffff, 0x00000000 }, - { 0x00000000, 0x00000000, 0x00ffffff, 0x00ffffff }, - { 0x00000000, 0x00ffffff, 0x00000000, 0x00000000 }, - { 0x00000000, 0x00ffffff, 0x00000000, 0x00ffffff }, - { 0x00000000, 0x00ffffff, 0x00ffffff, 0x00000000 }, - { 0x00000000, 0x00ffffff, 0x00ffffff, 0x00ffffff }, - { 0x00ffffff, 0x00000000, 0x00000000, 0x00000000 }, - { 0x00ffffff, 0x00000000, 0x00000000, 0x00ffffff }, - { 0x00ffffff, 0x00000000, 0x00ffffff, 0x00000000 }, - { 0x00ffffff, 0x00000000, 0x00ffffff, 0x00ffffff }, - { 0x00ffffff, 0x00ffffff, 0x00000000, 0x00000000 }, - { 0x00ffffff, 0x00ffffff, 0x00000000, 0x00ffffff }, - { 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00000000 }, - { 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff } }; - - -/******************************************************************************/ - -static void video_drawchars (int xx, int yy, unsigned char *s, int count) + {0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x00000000, 0x00000000, 0x00000000, 0x00ffffff}, + {0x00000000, 0x00000000, 0x00ffffff, 0x00000000}, + {0x00000000, 0x00000000, 0x00ffffff, 0x00ffffff}, + {0x00000000, 0x00ffffff, 0x00000000, 0x00000000}, + {0x00000000, 0x00ffffff, 0x00000000, 0x00ffffff}, + {0x00000000, 0x00ffffff, 0x00ffffff, 0x00000000}, + {0x00000000, 0x00ffffff, 0x00ffffff, 0x00ffffff}, + {0x00ffffff, 0x00000000, 0x00000000, 0x00000000}, + {0x00ffffff, 0x00000000, 0x00000000, 0x00ffffff}, + {0x00ffffff, 0x00000000, 0x00ffffff, 0x00000000}, + {0x00ffffff, 0x00000000, 0x00ffffff, 0x00ffffff}, + {0x00ffffff, 0x00ffffff, 0x00000000, 0x00000000}, + {0x00ffffff, 0x00ffffff, 0x00000000, 0x00ffffff}, + {0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00000000}, + {0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff} +}; + + +static void video_drawchars(int xx, int yy, unsigned char *s, int count) { u8 *cdat, *dest, *dest0; int rows, offset, c; @@ -422,12 +440,15 @@ static void video_drawchars (int xx, int yy, unsigned char *s, int count) c = *s; cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; for (rows = VIDEO_FONT_HEIGHT, dest = dest0; - rows--; - dest += VIDEO_LINE_LEN) { + rows--; dest += VIDEO_LINE_LEN) { u8 bits = *cdat++; - ((u32 *) dest)[0] = (video_font_draw_table8[bits >> 4] & eorx) ^ bgx; - ((u32 *) dest)[1] = (video_font_draw_table8[bits & 15] & eorx) ^ bgx; + ((u32 *) dest)[0] = + (video_font_draw_table8[bits >> 4] & + eorx) ^ bgx; + ((u32 *) dest)[1] = + (video_font_draw_table8[bits & 15] & + eorx) ^ bgx; } dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; s++; @@ -439,14 +460,25 @@ static void video_drawchars (int xx, int yy, unsigned char *s, int count) c = *s; cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; for (rows = VIDEO_FONT_HEIGHT, dest = dest0; - rows--; - dest += VIDEO_LINE_LEN) { + rows--; dest += VIDEO_LINE_LEN) { u8 bits = *cdat++; - ((u32 *) dest)[0] = SHORTSWAP32 ((video_font_draw_table15 [bits >> 6] & eorx) ^ bgx); - ((u32 *) dest)[1] = SHORTSWAP32 ((video_font_draw_table15 [bits >> 4 & 3] & eorx) ^ bgx); - ((u32 *) dest)[2] = SHORTSWAP32 ((video_font_draw_table15 [bits >> 2 & 3] & eorx) ^ bgx); - ((u32 *) dest)[3] = SHORTSWAP32 ((video_font_draw_table15 [bits & 3] & eorx) ^ bgx); + ((u32 *) dest)[0] = + SHORTSWAP32((video_font_draw_table15 + [bits >> 6] & eorx) ^ + bgx); + ((u32 *) dest)[1] = + SHORTSWAP32((video_font_draw_table15 + [bits >> 4 & 3] & eorx) ^ + bgx); + ((u32 *) dest)[2] = + SHORTSWAP32((video_font_draw_table15 + [bits >> 2 & 3] & eorx) ^ + bgx); + ((u32 *) dest)[3] = + SHORTSWAP32((video_font_draw_table15 + [bits & 3] & eorx) ^ + bgx); } dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; s++; @@ -458,14 +490,25 @@ static void video_drawchars (int xx, int yy, unsigned char *s, int count) c = *s; cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; for (rows = VIDEO_FONT_HEIGHT, dest = dest0; - rows--; - dest += VIDEO_LINE_LEN) { + rows--; dest += VIDEO_LINE_LEN) { u8 bits = *cdat++; - ((u32 *) dest)[0] = SHORTSWAP32 ((video_font_draw_table16 [bits >> 6] & eorx) ^ bgx); - ((u32 *) dest)[1] = SHORTSWAP32 ((video_font_draw_table16 [bits >> 4 & 3] & eorx) ^ bgx); - ((u32 *) dest)[2] = SHORTSWAP32 ((video_font_draw_table16 [bits >> 2 & 3] & eorx) ^ bgx); - ((u32 *) dest)[3] = SHORTSWAP32 ((video_font_draw_table16 [bits & 3] & eorx) ^ bgx); + ((u32 *) dest)[0] = + SHORTSWAP32((video_font_draw_table16 + [bits >> 6] & eorx) ^ + bgx); + ((u32 *) dest)[1] = + SHORTSWAP32((video_font_draw_table16 + [bits >> 4 & 3] & eorx) ^ + bgx); + ((u32 *) dest)[2] = + SHORTSWAP32((video_font_draw_table16 + [bits >> 2 & 3] & eorx) ^ + bgx); + ((u32 *) dest)[3] = + SHORTSWAP32((video_font_draw_table16 + [bits & 3] & eorx) ^ + bgx); } dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; s++; @@ -477,18 +520,33 @@ static void video_drawchars (int xx, int yy, unsigned char *s, int count) c = *s; cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; for (rows = VIDEO_FONT_HEIGHT, dest = dest0; - rows--; - dest += VIDEO_LINE_LEN) { + rows--; dest += VIDEO_LINE_LEN) { u8 bits = *cdat++; - ((u32 *) dest)[0] = SWAP32 ((video_font_draw_table32 [bits >> 4][0] & eorx) ^ bgx); - ((u32 *) dest)[1] = SWAP32 ((video_font_draw_table32 [bits >> 4][1] & eorx) ^ bgx); - ((u32 *) dest)[2] = SWAP32 ((video_font_draw_table32 [bits >> 4][2] & eorx) ^ bgx); - ((u32 *) dest)[3] = SWAP32 ((video_font_draw_table32 [bits >> 4][3] & eorx) ^ bgx); - ((u32 *) dest)[4] = SWAP32 ((video_font_draw_table32 [bits & 15][0] & eorx) ^ bgx); - ((u32 *) dest)[5] = SWAP32 ((video_font_draw_table32 [bits & 15][1] & eorx) ^ bgx); - ((u32 *) dest)[6] = SWAP32 ((video_font_draw_table32 [bits & 15][2] & eorx) ^ bgx); - ((u32 *) dest)[7] = SWAP32 ((video_font_draw_table32 [bits & 15][3] & eorx) ^ bgx); + ((u32 *) dest)[0] = + SWAP32((video_font_draw_table32 + [bits >> 4][0] & eorx) ^ bgx); + ((u32 *) dest)[1] = + SWAP32((video_font_draw_table32 + [bits >> 4][1] & eorx) ^ bgx); + ((u32 *) dest)[2] = + SWAP32((video_font_draw_table32 + [bits >> 4][2] & eorx) ^ bgx); + ((u32 *) dest)[3] = + SWAP32((video_font_draw_table32 + [bits >> 4][3] & eorx) ^ bgx); + ((u32 *) dest)[4] = + SWAP32((video_font_draw_table32 + [bits & 15][0] & eorx) ^ bgx); + ((u32 *) dest)[5] = + SWAP32((video_font_draw_table32 + [bits & 15][1] & eorx) ^ bgx); + ((u32 *) dest)[6] = + SWAP32((video_font_draw_table32 + [bits & 15][2] & eorx) ^ bgx); + ((u32 *) dest)[7] = + SWAP32((video_font_draw_table32 + [bits & 15][3] & eorx) ^ bgx); } dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; s++; @@ -500,16 +558,27 @@ static void video_drawchars (int xx, int yy, unsigned char *s, int count) c = *s; cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; for (rows = VIDEO_FONT_HEIGHT, dest = dest0; - rows--; - dest += VIDEO_LINE_LEN) { + rows--; dest += VIDEO_LINE_LEN) { u8 bits = *cdat++; - ((u32 *) dest)[0] = (video_font_draw_table24[bits >> 4][0] & eorx) ^ bgx; - ((u32 *) dest)[1] = (video_font_draw_table24[bits >> 4][1] & eorx) ^ bgx; - ((u32 *) dest)[2] = (video_font_draw_table24[bits >> 4][2] & eorx) ^ bgx; - ((u32 *) dest)[3] = (video_font_draw_table24[bits & 15][0] & eorx) ^ bgx; - ((u32 *) dest)[4] = (video_font_draw_table24[bits & 15][1] & eorx) ^ bgx; - ((u32 *) dest)[5] = (video_font_draw_table24[bits & 15][2] & eorx) ^ bgx; + ((u32 *) dest)[0] = + (video_font_draw_table24[bits >> 4][0] + & eorx) ^ bgx; + ((u32 *) dest)[1] = + (video_font_draw_table24[bits >> 4][1] + & eorx) ^ bgx; + ((u32 *) dest)[2] = + (video_font_draw_table24[bits >> 4][2] + & eorx) ^ bgx; + ((u32 *) dest)[3] = + (video_font_draw_table24[bits & 15][0] + & eorx) ^ bgx; + ((u32 *) dest)[4] = + (video_font_draw_table24[bits & 15][1] + & eorx) ^ bgx; + ((u32 *) dest)[5] = + (video_font_draw_table24[bits & 15][2] + & eorx) ^ bgx; } dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; s++; @@ -518,23 +587,18 @@ static void video_drawchars (int xx, int yy, unsigned char *s, int count) } } -/*****************************************************************************/ - -static inline void video_drawstring (int xx, int yy, unsigned char *s) +static inline void video_drawstring(int xx, int yy, unsigned char *s) { - video_drawchars (xx, yy, s, strlen ((char *)s)); + video_drawchars(xx, yy, s, strlen((char *) s)); } -/*****************************************************************************/ - -static void video_putchar (int xx, int yy, unsigned char c) +static void video_putchar(int xx, int yy, unsigned char c) { - video_drawchars (xx, yy + video_logo_height, &c, 1); + video_drawchars(xx, yy + video_logo_height, &c, 1); } -/*****************************************************************************/ #if defined(CONFIG_CONSOLE_CURSOR) || defined(CONFIG_VIDEO_SW_CURSOR) -static void video_set_cursor (void) +static void video_set_cursor(void) { /* swap drawing colors */ eorx = fgx; @@ -542,9 +606,8 @@ static void video_set_cursor (void) bgx = eorx; eorx = fgx ^ bgx; /* draw cursor */ - video_putchar (console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, - ' '); + video_putchar(console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, ' '); /* restore drawing colors */ eorx = fgx; fgx = bgx; @@ -552,9 +615,9 @@ static void video_set_cursor (void) eorx = fgx ^ bgx; } #endif -/*****************************************************************************/ + #ifdef CONFIG_CONSOLE_CURSOR -void console_cursor (int state) +void console_cursor(int state) { static int last_state = 0; @@ -564,92 +627,88 @@ void console_cursor (int state) /* time update only if cursor is on (faster scroll) */ if (state) { - rtc_get (&tm); - - sprintf (info, " %02d:%02d:%02d ", tm.tm_hour, tm.tm_min, - tm.tm_sec); - video_drawstring (VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH, - VIDEO_INFO_Y, (uchar *)info); - - sprintf (info, "%02d.%02d.%04d", tm.tm_mday, tm.tm_mon, - tm.tm_year); - video_drawstring (VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH, - VIDEO_INFO_Y + 1 * VIDEO_FONT_HEIGHT, (uchar *)info); + rtc_get(&tm); + + sprintf(info, " %02d:%02d:%02d ", tm.tm_hour, tm.tm_min, + tm.tm_sec); + video_drawstring(VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH, + VIDEO_INFO_Y, (uchar *) info); + + sprintf(info, "%02d.%02d.%04d", tm.tm_mday, tm.tm_mon, + tm.tm_year); + video_drawstring(VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH, + VIDEO_INFO_Y + 1 * VIDEO_FONT_HEIGHT, + (uchar *) info); } #endif if (state && (last_state != state)) { - video_set_cursor (); + video_set_cursor(); } if (!state && (last_state != state)) { /* clear cursor */ - video_putchar (console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, - ' '); + video_putchar(console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, ' '); } last_state = state; } #endif -/*****************************************************************************/ - #ifndef VIDEO_HW_RECTFILL -static void memsetl (int *p, int c, int v) +static void memsetl(int *p, int c, int v) { while (c--) *(p++) = v; } #endif -/*****************************************************************************/ - #ifndef VIDEO_HW_BITBLT -static void memcpyl (int *d, int *s, int c) +static void memcpyl(int *d, int *s, int c) { while (c--) *(d++) = *(s++); } #endif -/*****************************************************************************/ - -static void console_scrollup (void) +static void console_scrollup(void) { /* copy up rows ignoring the first one */ #ifdef VIDEO_HW_BITBLT - video_hw_bitblt (VIDEO_PIXEL_SIZE, /* bytes per pixel */ - 0, /* source pos x */ - video_logo_height + VIDEO_FONT_HEIGHT, /* source pos y */ - 0, /* dest pos x */ - video_logo_height, /* dest pos y */ - VIDEO_VISIBLE_COLS, /* frame width */ - VIDEO_VISIBLE_ROWS - video_logo_height - VIDEO_FONT_HEIGHT /* frame height */ + video_hw_bitblt(VIDEO_PIXEL_SIZE, /* bytes per pixel */ + 0, /* source pos x */ + video_logo_height + + VIDEO_FONT_HEIGHT, /* source pos y */ + 0, /* dest pos x */ + video_logo_height, /* dest pos y */ + VIDEO_VISIBLE_COLS, /* frame width */ + VIDEO_VISIBLE_ROWS + - video_logo_height + - VIDEO_FONT_HEIGHT /* frame height */ ); #else - memcpyl (CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, - CONSOLE_SCROLL_SIZE >> 2); + memcpyl(CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, + CONSOLE_SCROLL_SIZE >> 2); #endif /* clear the last one */ #ifdef VIDEO_HW_RECTFILL - video_hw_rectfill (VIDEO_PIXEL_SIZE, /* bytes per pixel */ - 0, /* dest pos x */ - VIDEO_VISIBLE_ROWS - VIDEO_FONT_HEIGHT, /* dest pos y */ - VIDEO_VISIBLE_COLS, /* frame width */ - VIDEO_FONT_HEIGHT, /* frame height */ - CONSOLE_BG_COL /* fill color */ + video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */ + 0, /* dest pos x */ + VIDEO_VISIBLE_ROWS + - VIDEO_FONT_HEIGHT, /* dest pos y */ + VIDEO_VISIBLE_COLS, /* frame width */ + VIDEO_FONT_HEIGHT, /* frame height */ + CONSOLE_BG_COL /* fill color */ ); #else - memsetl (CONSOLE_ROW_LAST, CONSOLE_ROW_SIZE >> 2, CONSOLE_BG_COL); + memsetl(CONSOLE_ROW_LAST, CONSOLE_ROW_SIZE >> 2, CONSOLE_BG_COL); #endif } -/*****************************************************************************/ - -static void console_back (void) +static void console_back(void) { CURSOR_OFF; console_col--; @@ -660,14 +719,11 @@ static void console_back (void) if (console_row < 0) console_row = 0; } - video_putchar (console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, - ' '); + video_putchar(console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, ' '); } -/*****************************************************************************/ - -static void console_newline (void) +static void console_newline(void) { /* Check if last character in the line was just drawn. If so, cursor was overwriten and need not to be cleared. Cursor clearing without this @@ -682,33 +738,31 @@ static void console_newline (void) /* Check if we need to scroll the terminal */ if (console_row >= CONSOLE_ROWS) { /* Scroll everything up */ - console_scrollup (); + console_scrollup(); /* Decrement row number */ console_row--; } } -static void console_cr (void) +static void console_cr(void) { CURSOR_OFF; console_col = 0; } -/*****************************************************************************/ - -void video_putc (const char c) +void video_putc(const char c) { static int nl = 1; switch (c) { case 13: /* back to first column */ - console_cr (); + console_cr(); break; case '\n': /* next line */ if (console_col || (!console_col && nl)) - console_newline (); + console_newline(); nl = 1; break; @@ -718,52 +772,47 @@ void video_putc (const char c) console_col &= ~0x0007; if (console_col >= CONSOLE_COLS) - console_newline (); + console_newline(); break; case 8: /* backspace */ - console_back (); + console_back(); break; default: /* draw the char */ - video_putchar (console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, - c); + video_putchar(console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, c); console_col++; /* check for newline */ if (console_col >= CONSOLE_COLS) { - console_newline (); + console_newline(); nl = 0; } } CURSOR_SET; } - -/*****************************************************************************/ - -void video_puts (const char *s) +void video_puts(const char *s) { - int count = strlen (s); + int count = strlen(s); while (count--) - video_putc (*s++); + video_putc(*s++); } -/*****************************************************************************/ - /* * Do not enforce drivers (or board code) to provide empty * video_set_lut() if they do not support 8 bpp format. * Implement weak default function instead. */ -void __video_set_lut (unsigned int index, unsigned char r, - unsigned char g, unsigned char b) +void __video_set_lut(unsigned int index, unsigned char r, + unsigned char g, unsigned char b) { } -void video_set_lut (unsigned int, unsigned char, unsigned char, unsigned char) - __attribute__((weak, alias("__video_set_lut"))); + +void video_set_lut(unsigned int, unsigned char, unsigned char, unsigned char) + __attribute__ ((weak, alias("__video_set_lut"))); #if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) @@ -773,17 +822,26 @@ void video_set_lut (unsigned int, unsigned char, unsigned char, unsigned char) } #define FILL_15BIT_555RGB(r,g,b) { \ - *(unsigned short *)fb = SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3))); \ + *(unsigned short *)fb = \ + SWAP16((unsigned short)(((r>>3)<<10) | \ + ((g>>3)<<5) | \ + (b>>3))); \ fb += 2; \ } #define FILL_16BIT_565RGB(r,g,b) { \ - *(unsigned short *)fb = SWAP16((unsigned short)((((r)>>3)<<11) | (((g)>>2)<<5) | ((b)>>3))); \ + *(unsigned short *)fb = \ + SWAP16((unsigned short)((((r)>>3)<<11)| \ + (((g)>>2)<<5) | \ + ((b)>>3))); \ fb += 2; \ } #define FILL_32BIT_X888RGB(r,g,b) { \ - *(unsigned long *)fb = SWAP32((unsigned long)(((r<<16) | (g<<8) | b))); \ + *(unsigned long *)fb = \ + SWAP32((unsigned long)(((r<<16) | \ + (g<<8) | \ + b))); \ fb += 4; \ } @@ -804,13 +862,12 @@ void video_set_lut (unsigned int, unsigned char, unsigned char, unsigned char) #endif #if defined(VIDEO_FB_16BPP_PIXEL_SWAP) -static void inline fill_555rgb_pswap(uchar *fb, int x, - u8 r, u8 g, u8 b) +static inline void fill_555rgb_pswap(uchar *fb, int x, u8 r, u8 g, u8 b) { - ushort *dst = (ushort *)fb; - ushort color = (ushort)(((r >> 3) << 10) | - ((g >> 3) << 5) | - (b >> 3)); + ushort *dst = (ushort *) fb; + ushort color = (ushort) (((r >> 3) << 10) | + ((g >> 3) << 5) | + (b >> 3)); if (x & 1) *(--dst) = color; else @@ -826,18 +883,18 @@ static void inline fill_555rgb_pswap(uchar *fb, int x, /* Pre-calculated color table entry */ struct palette { union { - unsigned short w; /* word */ - unsigned int dw; /* double word */ - } ce; /* color entry */ + unsigned short w; /* word */ + unsigned int dw; /* double word */ + } ce; /* color entry */ }; /* * Helper to draw encoded/unencoded run. */ -static void draw_bitmap (uchar **fb, uchar *bm, struct palette *p, - int cnt, int enc) +static void draw_bitmap(uchar **fb, uchar *bm, struct palette *p, + int cnt, int enc) { - ulong addr = (ulong)*fb; + ulong addr = (ulong) *fb; int *off; int enc_off = 1; int i; @@ -851,28 +908,28 @@ static void draw_bitmap (uchar **fb, uchar *bm, struct palette *p, switch (VIDEO_DATA_FORMAT) { case GDF__8BIT_INDEX: for (i = 0; i < cnt; i++) - *(unsigned char *)addr++ = bm[*off]; + *(unsigned char *) addr++ = bm[*off]; break; case GDF_15BIT_555RGB: case GDF_16BIT_565RGB: /* differences handled while pre-calculating palette */ for (i = 0; i < cnt; i++) { - *(unsigned short *)addr = p[bm[*off]].ce.w; + *(unsigned short *) addr = p[bm[*off]].ce.w; addr += 2; } break; case GDF_32BIT_X888RGB: for (i = 0; i < cnt; i++) { - *(unsigned long *)addr = p[bm[*off]].ce.dw; + *(unsigned long *) addr = p[bm[*off]].ce.dw; addr += 4; } break; } - *fb = (uchar *)addr; /* return modified address */ + *fb = (uchar *) addr; /* return modified address */ } -static int display_rle8_bitmap (bmp_image_t *img, int xoff, int yoff, - int width, int height) +static int display_rle8_bitmap(bmp_image_t *img, int xoff, int yoff, + int width, int height) { unsigned char *bm; unsigned char *fbp; @@ -889,17 +946,17 @@ static int display_rle8_bitmap (bmp_image_t *img, int xoff, int yoff, y = __le32_to_cpu(img->header.height) - 1; ncolors = __le32_to_cpu(img->header.colors_used); bpp = VIDEO_PIXEL_SIZE; - fbp = (unsigned char *)((unsigned int)video_fb_address + - (((y + yoff) * VIDEO_COLS) + xoff) * bpp); + fbp = (unsigned char *) ((unsigned int) video_fb_address + + (((y + yoff) * VIDEO_COLS) + xoff) * bpp); - bm = (uchar *)img + __le32_to_cpu(img->header.data_offset); + bm = (uchar *) img + __le32_to_cpu(img->header.data_offset); /* pre-calculate and setup palette */ switch (VIDEO_DATA_FORMAT) { case GDF__8BIT_INDEX: for (i = 0; i < ncolors; i++) { cte = img->color_table[i]; - video_set_lut (i, cte.red, cte.green, cte.blue); + video_set_lut(i, cte.red, cte.green, cte.blue); } break; case GDF_15BIT_555RGB: @@ -922,13 +979,14 @@ static int display_rle8_bitmap (bmp_image_t *img, int xoff, int yoff, case GDF_32BIT_X888RGB: for (i = 0; i < ncolors; i++) { cte = img->color_table[i]; - p[i].ce.dw = SWAP32((cte.red << 16) | (cte.green << 8) | + p[i].ce.dw = SWAP32((cte.red << 16) | + (cte.green << 8) | cte.blue); } break; default: printf("RLE Bitmap unsupported in video mode 0x%x\n", - VIDEO_DATA_FORMAT); + VIDEO_DATA_FORMAT); return -1; } @@ -942,7 +1000,7 @@ static int display_rle8_bitmap (bmp_image_t *img, int xoff, int yoff, x = 0; y--; fbp = (unsigned char *) - ((unsigned int)video_fb_address + + ((unsigned int) video_fb_address + (((y + yoff) * VIDEO_COLS) + xoff) * bpp); continue; @@ -955,7 +1013,7 @@ static int display_rle8_bitmap (bmp_image_t *img, int xoff, int yoff, x += bm[2]; y -= bm[3]; fbp = (unsigned char *) - ((unsigned int)video_fb_address + + ((unsigned int) video_fb_address + (((y + yoff) * VIDEO_COLS) + x + xoff) * bpp); bm += 4; @@ -976,13 +1034,13 @@ static int display_rle8_bitmap (bmp_image_t *img, int xoff, int yoff, } if (x + runlen > width) cnt = width - x; - draw_bitmap (&fbp, bm, p, cnt, 0); + draw_bitmap(&fbp, bm, p, cnt, 0); x += runlen; } next_run: bm += runlen; if (runlen & 1) - bm++; /* 0 padding if length is odd */ + bm++; /* 0 padding if length is odd */ } break; default: @@ -993,7 +1051,7 @@ next_run: if (pixels > limit) goto error; - if (y < height) { /* only draw into visible area */ + if (y < height) { /* only draw into visible area */ if (x >= width) { x += runlen; bm += 2; @@ -1001,7 +1059,7 @@ next_run: } if (x + runlen > width) cnt = width - x; - draw_bitmap (&fbp, bm, p, cnt, 1); + draw_bitmap(&fbp, bm, p, cnt, 1); x += runlen; } bm += 2; @@ -1018,7 +1076,7 @@ error: /* * Display the BMP file located at address bmp_image. */ -int video_display_bitmap (ulong bmp_image, int x, int y) +int video_display_bitmap(ulong bmp_image, int x, int y) { ushort xcount, ycount; uchar *fb; @@ -1029,12 +1087,13 @@ int video_display_bitmap (ulong bmp_image, int x, int y) unsigned colors; unsigned long compression; bmp_color_table_entry_t cte; + #ifdef CONFIG_VIDEO_BMP_GZIP unsigned char *dst = NULL; ulong len; #endif - WATCHDOG_RESET (); + WATCHDOG_RESET(); if (!((bmp->header.signature[0] == 'B') && (bmp->header.signature[1] == 'M'))) { @@ -1047,50 +1106,55 @@ int video_display_bitmap (ulong bmp_image, int x, int y) dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE); if (dst == NULL) { printf("Error: malloc in gunzip failed!\n"); - return(1); + return 1; } - if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE, (uchar *)bmp_image, &len) != 0) { - printf ("Error: no valid bmp or bmp.gz image at %lx\n", bmp_image); + if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE, + (uchar *) bmp_image, + &len) != 0) { + printf("Error: no valid bmp or bmp.gz image at %lx\n", + bmp_image); free(dst); return 1; } if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) { - printf("Image could be truncated (increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n"); + printf("Image could be truncated " + "(increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n"); } /* * Set addr to decompressed image */ - bmp = (bmp_image_t *)dst; + bmp = (bmp_image_t *) dst; if (!((bmp->header.signature[0] == 'B') && (bmp->header.signature[1] == 'M'))) { - printf ("Error: no valid bmp.gz image at %lx\n", bmp_image); + printf("Error: no valid bmp.gz image at %lx\n", + bmp_image); free(dst); return 1; } #else - printf ("Error: no valid bmp image at %lx\n", bmp_image); + printf("Error: no valid bmp image at %lx\n", bmp_image); return 1; #endif /* CONFIG_VIDEO_BMP_GZIP */ } - width = le32_to_cpu (bmp->header.width); - height = le32_to_cpu (bmp->header.height); - bpp = le16_to_cpu (bmp->header.bit_count); - colors = le32_to_cpu (bmp->header.colors_used); - compression = le32_to_cpu (bmp->header.compression); + width = le32_to_cpu(bmp->header.width); + height = le32_to_cpu(bmp->header.height); + bpp = le16_to_cpu(bmp->header.bit_count); + colors = le32_to_cpu(bmp->header.colors_used); + compression = le32_to_cpu(bmp->header.compression); - debug ("Display-bmp: %d x %d with %d colors\n", - width, height, colors); + debug("Display-bmp: %d x %d with %d colors\n", + width, height, colors); if (compression != BMP_BI_RGB #ifdef CONFIG_VIDEO_BMP_RLE8 && compression != BMP_BI_RLE8 #endif - ) { - printf ("Error: compression type %ld not supported\n", - compression); + ) { + printf("Error: compression type %ld not supported\n", + compression); #ifdef CONFIG_VIDEO_BMP_GZIP if (dst) free(dst); @@ -1117,20 +1181,19 @@ int video_display_bitmap (ulong bmp_image, int x, int y) if ((y + height) > VIDEO_VISIBLE_ROWS) height = VIDEO_VISIBLE_ROWS - y; - bmap = (uchar *) bmp + le32_to_cpu (bmp->header.data_offset); + bmap = (uchar *) bmp + le32_to_cpu(bmp->header.data_offset); fb = (uchar *) (video_fb_address + ((y + height - 1) * VIDEO_COLS * VIDEO_PIXEL_SIZE) + x * VIDEO_PIXEL_SIZE); #ifdef CONFIG_VIDEO_BMP_RLE8 if (compression == BMP_BI_RLE8) { - return display_rle8_bitmap(bmp, - x, y, width, height); + return display_rle8_bitmap(bmp, x, y, width, height); } #endif /* We handle only 4, 8, or 24 bpp bitmaps */ - switch (le16_to_cpu (bmp->header.bit_count)) { + switch (le16_to_cpu(bmp->header.bit_count)) { case 4: padded_line -= width / 2; ycount = height; @@ -1138,7 +1201,7 @@ int video_display_bitmap (ulong bmp_image, int x, int y) switch (VIDEO_DATA_FORMAT) { case GDF_32BIT_X888RGB: while (ycount--) { - WATCHDOG_RESET (); + WATCHDOG_RESET(); /* * Don't assume that 'width' is an * even number @@ -1157,7 +1220,7 @@ int video_display_bitmap (ulong bmp_image, int x, int y) } bmap += padded_line; fb -= (VIDEO_VISIBLE_COLS + width) * - VIDEO_PIXEL_SIZE; + VIDEO_PIXEL_SIZE; } break; default: @@ -1173,32 +1236,36 @@ int video_display_bitmap (ulong bmp_image, int x, int y) /* Copy colormap */ for (xcount = 0; xcount < colors; ++xcount) { cte = bmp->color_table[xcount]; - video_set_lut (xcount, cte.red, cte.green, cte.blue); + video_set_lut(xcount, cte.red, cte.green, + cte.blue); } } ycount = height; switch (VIDEO_DATA_FORMAT) { case GDF__8BIT_INDEX: while (ycount--) { - WATCHDOG_RESET (); + WATCHDOG_RESET(); xcount = width; while (xcount--) { *fb++ = *bmap++; } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; } break; case GDF__8BIT_332RGB: while (ycount--) { - WATCHDOG_RESET (); + WATCHDOG_RESET(); xcount = width; while (xcount--) { cte = bmp->color_table[*bmap++]; - FILL_8BIT_332RGB (cte.red, cte.green, cte.blue); + FILL_8BIT_332RGB(cte.red, cte.green, + cte.blue); } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; } break; case GDF_15BIT_555RGB: @@ -1206,56 +1273,65 @@ int video_display_bitmap (ulong bmp_image, int x, int y) #if defined(VIDEO_FB_16BPP_PIXEL_SWAP) int xpos = x; #endif - WATCHDOG_RESET (); + WATCHDOG_RESET(); xcount = width; while (xcount--) { cte = bmp->color_table[*bmap++]; #if defined(VIDEO_FB_16BPP_PIXEL_SWAP) - fill_555rgb_pswap (fb, xpos++, cte.red, - cte.green, cte.blue); + fill_555rgb_pswap(fb, xpos++, cte.red, + cte.green, + cte.blue); fb += 2; #else - FILL_15BIT_555RGB (cte.red, cte.green, cte.blue); + FILL_15BIT_555RGB(cte.red, cte.green, + cte.blue); #endif } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; } break; case GDF_16BIT_565RGB: while (ycount--) { - WATCHDOG_RESET (); + WATCHDOG_RESET(); xcount = width; while (xcount--) { cte = bmp->color_table[*bmap++]; - FILL_16BIT_565RGB (cte.red, cte.green, cte.blue); + FILL_16BIT_565RGB(cte.red, cte.green, + cte.blue); } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; } break; case GDF_32BIT_X888RGB: while (ycount--) { - WATCHDOG_RESET (); + WATCHDOG_RESET(); xcount = width; while (xcount--) { cte = bmp->color_table[*bmap++]; - FILL_32BIT_X888RGB (cte.red, cte.green, cte.blue); + FILL_32BIT_X888RGB(cte.red, cte.green, + cte.blue); } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; } break; case GDF_24BIT_888RGB: while (ycount--) { - WATCHDOG_RESET (); + WATCHDOG_RESET(); xcount = width; while (xcount--) { cte = bmp->color_table[*bmap++]; - FILL_24BIT_888RGB (cte.red, cte.green, cte.blue); + FILL_24BIT_888RGB(cte.red, cte.green, + cte.blue); } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; } break; } @@ -1266,14 +1342,16 @@ int video_display_bitmap (ulong bmp_image, int x, int y) switch (VIDEO_DATA_FORMAT) { case GDF__8BIT_332RGB: while (ycount--) { - WATCHDOG_RESET (); + WATCHDOG_RESET(); xcount = width; while (xcount--) { - FILL_8BIT_332RGB (bmap[2], bmap[1], bmap[0]); + FILL_8BIT_332RGB(bmap[2], bmap[1], + bmap[0]); bmap += 3; } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; } break; case GDF_15BIT_555RGB: @@ -1281,66 +1359,75 @@ int video_display_bitmap (ulong bmp_image, int x, int y) #if defined(VIDEO_FB_16BPP_PIXEL_SWAP) int xpos = x; #endif - WATCHDOG_RESET (); + WATCHDOG_RESET(); xcount = width; while (xcount--) { #if defined(VIDEO_FB_16BPP_PIXEL_SWAP) - fill_555rgb_pswap (fb, xpos++, bmap[2], - bmap[1], bmap[0]); + fill_555rgb_pswap(fb, xpos++, bmap[2], + bmap[1], bmap[0]); fb += 2; #else - FILL_15BIT_555RGB (bmap[2], bmap[1], bmap[0]); + FILL_15BIT_555RGB(bmap[2], bmap[1], + bmap[0]); #endif bmap += 3; } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; } break; case GDF_16BIT_565RGB: while (ycount--) { - WATCHDOG_RESET (); + WATCHDOG_RESET(); xcount = width; while (xcount--) { - FILL_16BIT_565RGB (bmap[2], bmap[1], bmap[0]); + FILL_16BIT_565RGB(bmap[2], bmap[1], + bmap[0]); bmap += 3; } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; } break; case GDF_32BIT_X888RGB: while (ycount--) { - WATCHDOG_RESET (); + WATCHDOG_RESET(); xcount = width; while (xcount--) { - FILL_32BIT_X888RGB (bmap[2], bmap[1], bmap[0]); + FILL_32BIT_X888RGB(bmap[2], bmap[1], + bmap[0]); bmap += 3; } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; } break; case GDF_24BIT_888RGB: while (ycount--) { - WATCHDOG_RESET (); + WATCHDOG_RESET(); xcount = width; while (xcount--) { - FILL_24BIT_888RGB (bmap[2], bmap[1], bmap[0]); + FILL_24BIT_888RGB(bmap[2], bmap[1], + bmap[0]); bmap += 3; } bmap += padded_line; - fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; } break; default: - printf ("Error: 24 bits/pixel bitmap incompatible with current video mode\n"); + printf("Error: 24 bits/pixel bitmap incompatible " + "with current video mode\n"); break; } break; default: - printf ("Error: %d bit/pixel bitmaps not supported by U-Boot\n", - le16_to_cpu (bmp->header.bit_count)); + printf("Error: %d bit/pixel bitmaps not supported by U-Boot\n", + le16_to_cpu(bmp->header.bit_count)); break; } @@ -1354,28 +1441,26 @@ int video_display_bitmap (ulong bmp_image, int x, int y) } #endif -/*****************************************************************************/ #ifdef CONFIG_VIDEO_LOGO -void logo_plot (void *screen, int width, int x, int y) +void logo_plot(void *screen, int width, int x, int y) { int xcount, i; - int skip = (width - VIDEO_LOGO_WIDTH) * VIDEO_PIXEL_SIZE; + int skip = (width - VIDEO_LOGO_WIDTH) * VIDEO_PIXEL_SIZE; int ycount = video_logo_height; unsigned char r, g, b, *logo_red, *logo_blue, *logo_green; unsigned char *source; - unsigned char *dest = (unsigned char *)screen + - ((y * width * VIDEO_PIXEL_SIZE) + - x * VIDEO_PIXEL_SIZE); + unsigned char *dest = (unsigned char *) screen + + ((y * width * VIDEO_PIXEL_SIZE) + x * VIDEO_PIXEL_SIZE); #ifdef CONFIG_VIDEO_BMP_LOGO source = bmp_logo_bitmap; /* Allocate temporary space for computing colormap */ - logo_red = malloc (BMP_LOGO_COLORS); - logo_green = malloc (BMP_LOGO_COLORS); - logo_blue = malloc (BMP_LOGO_COLORS); + logo_red = malloc(BMP_LOGO_COLORS); + logo_green = malloc(BMP_LOGO_COLORS); + logo_blue = malloc(BMP_LOGO_COLORS); /* Compute color map */ for (i = 0; i < VIDEO_LOGO_COLORS; i++) { logo_red[i] = (bmp_logo_palette[i] & 0x0f00) >> 4; @@ -1391,8 +1476,9 @@ void logo_plot (void *screen, int width, int x, int y) if (VIDEO_DATA_FORMAT == GDF__8BIT_INDEX) { for (i = 0; i < VIDEO_LOGO_COLORS; i++) { - video_set_lut (i + VIDEO_LOGO_LUT_OFFSET, - logo_red[i], logo_green[i], logo_blue[i]); + video_set_lut(i + VIDEO_LOGO_LUT_OFFSET, + logo_red[i], logo_green[i], + logo_blue[i]); } } @@ -1411,23 +1497,34 @@ void logo_plot (void *screen, int width, int x, int y) *dest = *source; break; case GDF__8BIT_332RGB: - *dest = ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6); + *dest = ((r >> 5) << 5) | + ((g >> 5) << 2) | + (b >> 6); break; case GDF_15BIT_555RGB: #if defined(VIDEO_FB_16BPP_PIXEL_SWAP) - fill_555rgb_pswap (dest, xpos++, r, g, b); + fill_555rgb_pswap(dest, xpos++, r, g, b); #else *(unsigned short *) dest = - SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3))); + SWAP16((unsigned short) ( + ((r >> 3) << 10) | + ((g >> 3) << 5) | + (b >> 3))); #endif break; case GDF_16BIT_565RGB: *(unsigned short *) dest = - SWAP16 ((unsigned short) (((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3))); + SWAP16((unsigned short) ( + ((r >> 3) << 11) | + ((g >> 2) << 5) | + (b >> 3))); break; case GDF_32BIT_X888RGB: *(unsigned long *) dest = - SWAP32 ((unsigned long) ((r << 16) | (g << 8) | b)); + SWAP32((unsigned long) ( + (r << 16) | + (g << 8) | + b)); break; case GDF_24BIT_888RGB: #ifdef VIDEO_FB_LITTLE_ENDIAN @@ -1447,94 +1544,100 @@ void logo_plot (void *screen, int width, int x, int y) dest += skip; } #ifdef CONFIG_VIDEO_BMP_LOGO - free (logo_red); - free (logo_green); - free (logo_blue); + free(logo_red); + free(logo_green); + free(logo_blue); #endif } -/*****************************************************************************/ - -static void *video_logo (void) +static void *video_logo(void) { char info[128]; - extern char version_string; int space, len, y_off = 0; #ifdef CONFIG_SPLASH_SCREEN char *s; ulong addr; - if ((s = getenv ("splashimage")) != NULL) { + s = getenv("splashimage"); + if (s != NULL) { int x = 0, y = 0; - addr = simple_strtoul (s, NULL, 16); + addr = simple_strtoul(s, NULL, 16); #ifdef CONFIG_SPLASH_SCREEN_ALIGN - if ((s = getenv ("splashpos")) != NULL) { + s = getenv("splashpos"); + if (s != NULL) { if (s[0] == 'm') x = BMP_ALIGN_CENTER; else - x = simple_strtol (s, NULL, 0); + x = simple_strtol(s, NULL, 0); - if ((s = strchr (s + 1, ',')) != NULL) { + s = strchr(s + 1, ','); + if (s != NULL) { if (s[1] == 'm') y = BMP_ALIGN_CENTER; else - y = simple_strtol (s + 1, NULL, 0); + y = simple_strtol(s + 1, NULL, 0); } } #endif /* CONFIG_SPLASH_SCREEN_ALIGN */ - if (video_display_bitmap (addr, x, y) == 0) { + if (video_display_bitmap(addr, x, y) == 0) { video_logo_height = 0; return ((void *) (video_fb_address)); } } #endif /* CONFIG_SPLASH_SCREEN */ - logo_plot (video_fb_address, VIDEO_COLS, 0, 0); + logo_plot(video_fb_address, VIDEO_COLS, 0, 0); - sprintf (info, " %s", &version_string); + sprintf(info, " %s", version_string); space = (VIDEO_LINE_LEN / 2 - VIDEO_INFO_X) / VIDEO_FONT_WIDTH; len = strlen(info); if (len > space) { - video_drawchars (VIDEO_INFO_X, VIDEO_INFO_Y, - (uchar *)info, space); - video_drawchars (VIDEO_INFO_X + VIDEO_FONT_WIDTH, - VIDEO_INFO_Y + VIDEO_FONT_HEIGHT, - (uchar *)info + space, len - space); + video_drawchars(VIDEO_INFO_X, VIDEO_INFO_Y, + (uchar *) info, space); + video_drawchars(VIDEO_INFO_X + VIDEO_FONT_WIDTH, + VIDEO_INFO_Y + VIDEO_FONT_HEIGHT, + (uchar *) info + space, len - space); y_off = 1; } else - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, (uchar *)info); + video_drawstring(VIDEO_INFO_X, VIDEO_INFO_Y, (uchar *) info); #ifdef CONFIG_CONSOLE_EXTRA_INFO { - int i, n = ((video_logo_height - VIDEO_FONT_HEIGHT) / VIDEO_FONT_HEIGHT); + int i, n = + ((video_logo_height - + VIDEO_FONT_HEIGHT) / VIDEO_FONT_HEIGHT); for (i = 1; i < n; i++) { - video_get_info_str (i, info); + video_get_info_str(i, info); if (!*info) continue; len = strlen(info); if (len > space) { - video_drawchars (VIDEO_INFO_X, - VIDEO_INFO_Y + - (i + y_off) * VIDEO_FONT_HEIGHT, - (uchar *)info, space); + video_drawchars(VIDEO_INFO_X, + VIDEO_INFO_Y + + (i + y_off) * + VIDEO_FONT_HEIGHT, + (uchar *) info, space); y_off++; - video_drawchars (VIDEO_INFO_X + VIDEO_FONT_WIDTH, - VIDEO_INFO_Y + - (i + y_off) * VIDEO_FONT_HEIGHT, - (uchar *)info + space, - len - space); + video_drawchars(VIDEO_INFO_X + + VIDEO_FONT_WIDTH, + VIDEO_INFO_Y + + (i + y_off) * + VIDEO_FONT_HEIGHT, + (uchar *) info + space, + len - space); } else { - video_drawstring (VIDEO_INFO_X, - VIDEO_INFO_Y + - (i + y_off) * VIDEO_FONT_HEIGHT, - (uchar *)info); + video_drawstring(VIDEO_INFO_X, + VIDEO_INFO_Y + + (i + y_off) * + VIDEO_FONT_HEIGHT, + (uchar *) info); } } } @@ -1544,74 +1647,94 @@ static void *video_logo (void) } #endif - -/*****************************************************************************/ - -static int video_init (void) +static int video_init(void) { unsigned char color8; - if ((pGD = video_hw_init ()) == NULL) + pGD = video_hw_init(); + if (pGD == NULL) return -1; video_fb_address = (void *) VIDEO_FB_ADRS; #ifdef CONFIG_VIDEO_HW_CURSOR - video_init_hw_cursor (VIDEO_FONT_WIDTH, VIDEO_FONT_HEIGHT); + video_init_hw_cursor(VIDEO_FONT_WIDTH, VIDEO_FONT_HEIGHT); #endif /* Init drawing pats */ switch (VIDEO_DATA_FORMAT) { case GDF__8BIT_INDEX: - video_set_lut (0x01, CONSOLE_FG_COL, CONSOLE_FG_COL, CONSOLE_FG_COL); - video_set_lut (0x00, CONSOLE_BG_COL, CONSOLE_BG_COL, CONSOLE_BG_COL); + video_set_lut(0x01, CONSOLE_FG_COL, CONSOLE_FG_COL, + CONSOLE_FG_COL); + video_set_lut(0x00, CONSOLE_BG_COL, CONSOLE_BG_COL, + CONSOLE_BG_COL); fgx = 0x01010101; bgx = 0x00000000; break; case GDF__8BIT_332RGB: color8 = ((CONSOLE_FG_COL & 0xe0) | - ((CONSOLE_FG_COL >> 3) & 0x1c) | CONSOLE_FG_COL >> 6); - fgx = (color8 << 24) | (color8 << 16) | (color8 << 8) | color8; + ((CONSOLE_FG_COL >> 3) & 0x1c) | + CONSOLE_FG_COL >> 6); + fgx = (color8 << 24) | (color8 << 16) | (color8 << 8) | + color8; color8 = ((CONSOLE_BG_COL & 0xe0) | - ((CONSOLE_BG_COL >> 3) & 0x1c) | CONSOLE_BG_COL >> 6); - bgx = (color8 << 24) | (color8 << 16) | (color8 << 8) | color8; + ((CONSOLE_BG_COL >> 3) & 0x1c) | + CONSOLE_BG_COL >> 6); + bgx = (color8 << 24) | (color8 << 16) | (color8 << 8) | + color8; break; case GDF_15BIT_555RGB: fgx = (((CONSOLE_FG_COL >> 3) << 26) | - ((CONSOLE_FG_COL >> 3) << 21) | ((CONSOLE_FG_COL >> 3) << 16) | - ((CONSOLE_FG_COL >> 3) << 10) | ((CONSOLE_FG_COL >> 3) << 5) | - (CONSOLE_FG_COL >> 3)); + ((CONSOLE_FG_COL >> 3) << 21) | + ((CONSOLE_FG_COL >> 3) << 16) | + ((CONSOLE_FG_COL >> 3) << 10) | + ((CONSOLE_FG_COL >> 3) << 5) | + (CONSOLE_FG_COL >> 3)); bgx = (((CONSOLE_BG_COL >> 3) << 26) | - ((CONSOLE_BG_COL >> 3) << 21) | ((CONSOLE_BG_COL >> 3) << 16) | - ((CONSOLE_BG_COL >> 3) << 10) | ((CONSOLE_BG_COL >> 3) << 5) | - (CONSOLE_BG_COL >> 3)); + ((CONSOLE_BG_COL >> 3) << 21) | + ((CONSOLE_BG_COL >> 3) << 16) | + ((CONSOLE_BG_COL >> 3) << 10) | + ((CONSOLE_BG_COL >> 3) << 5) | + (CONSOLE_BG_COL >> 3)); break; case GDF_16BIT_565RGB: fgx = (((CONSOLE_FG_COL >> 3) << 27) | - ((CONSOLE_FG_COL >> 2) << 21) | ((CONSOLE_FG_COL >> 3) << 16) | - ((CONSOLE_FG_COL >> 3) << 11) | ((CONSOLE_FG_COL >> 2) << 5) | - (CONSOLE_FG_COL >> 3)); + ((CONSOLE_FG_COL >> 2) << 21) | + ((CONSOLE_FG_COL >> 3) << 16) | + ((CONSOLE_FG_COL >> 3) << 11) | + ((CONSOLE_FG_COL >> 2) << 5) | + (CONSOLE_FG_COL >> 3)); bgx = (((CONSOLE_BG_COL >> 3) << 27) | - ((CONSOLE_BG_COL >> 2) << 21) | ((CONSOLE_BG_COL >> 3) << 16) | - ((CONSOLE_BG_COL >> 3) << 11) | ((CONSOLE_BG_COL >> 2) << 5) | - (CONSOLE_BG_COL >> 3)); + ((CONSOLE_BG_COL >> 2) << 21) | + ((CONSOLE_BG_COL >> 3) << 16) | + ((CONSOLE_BG_COL >> 3) << 11) | + ((CONSOLE_BG_COL >> 2) << 5) | + (CONSOLE_BG_COL >> 3)); break; case GDF_32BIT_X888RGB: - fgx = (CONSOLE_FG_COL << 16) | (CONSOLE_FG_COL << 8) | CONSOLE_FG_COL; - bgx = (CONSOLE_BG_COL << 16) | (CONSOLE_BG_COL << 8) | CONSOLE_BG_COL; + fgx = (CONSOLE_FG_COL << 16) | + (CONSOLE_FG_COL << 8) | + CONSOLE_FG_COL; + bgx = (CONSOLE_BG_COL << 16) | + (CONSOLE_BG_COL << 8) | + CONSOLE_BG_COL; break; case GDF_24BIT_888RGB: - fgx = (CONSOLE_FG_COL << 24) | (CONSOLE_FG_COL << 16) | - (CONSOLE_FG_COL << 8) | CONSOLE_FG_COL; - bgx = (CONSOLE_BG_COL << 24) | (CONSOLE_BG_COL << 16) | - (CONSOLE_BG_COL << 8) | CONSOLE_BG_COL; + fgx = (CONSOLE_FG_COL << 24) | + (CONSOLE_FG_COL << 16) | + (CONSOLE_FG_COL << 8) | + CONSOLE_FG_COL; + bgx = (CONSOLE_BG_COL << 24) | + (CONSOLE_BG_COL << 16) | + (CONSOLE_BG_COL << 8) | + CONSOLE_BG_COL; break; } eorx = fgx ^ bgx; #ifdef CONFIG_VIDEO_LOGO /* Plot the logo and get start point of console */ - PRINTD ("Video: Drawing the logo ...\n"); - video_console_address = video_logo (); + debug("Video: Drawing the logo ...\n"); + video_console_address = video_logo(); #else video_console_address = video_fb_address; #endif @@ -1623,9 +1746,6 @@ static int video_init (void) return 0; } - -/*****************************************************************************/ - /* * Implement a weak default function for boards that optionally * need to skip the video initialization. @@ -1635,9 +1755,11 @@ int __board_video_skip(void) /* As default, don't skip test */ return 0; } -int board_video_skip(void) __attribute__((weak, alias("__board_video_skip"))); -int drv_video_init (void) +int board_video_skip(void) + __attribute__ ((weak, alias("__board_video_skip"))); + +int drv_video_init(void) { int skip_dev_init; struct stdio_dev console_dev; @@ -1647,10 +1769,10 @@ int drv_video_init (void) return 0; /* Init video chip - returns with framebuffer cleared */ - skip_dev_init = (video_init () == -1); + skip_dev_init = (video_init() == -1); #if !defined(CONFIG_VGA_AS_SINGLE_DEVICE) - PRINTD ("KBD: Keyboard init ...\n"); + debug("KBD: Keyboard init ...\n"); skip_dev_init |= (VIDEO_KBD_INIT_FCT == -1); #endif @@ -1658,8 +1780,8 @@ int drv_video_init (void) return 0; /* Init vga device */ - memset (&console_dev, 0, sizeof (console_dev)); - strcpy (console_dev.name, "vga"); + memset(&console_dev, 0, sizeof(console_dev)); + strcpy(console_dev.name, "vga"); console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */ console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM; console_dev.putc = video_putc; /* 'putc' function */ @@ -1674,7 +1796,7 @@ int drv_video_init (void) console_dev.getc = VIDEO_GETC_FCT; /* 'getc' function */ #endif /* CONFIG_VGA_AS_SINGLE_DEVICE */ - if (stdio_register (&console_dev) != 0) + if (stdio_register(&console_dev) != 0) return 0; /* Return success */ diff --git a/fs/ext2/dev.c b/fs/ext2/dev.c index 3b49650..78851d0 100644 --- a/fs/ext2/dev.c +++ b/fs/ext2/dev.c @@ -31,7 +31,7 @@ static block_dev_desc_t *ext2fs_block_dev_desc; static disk_partition_t part_info; -int ext2fs_set_blk_dev (block_dev_desc_t * rbdd, int part) +int ext2fs_set_blk_dev(block_dev_desc_t *rbdd, int part) { ext2fs_block_dev_desc = rbdd; @@ -46,94 +46,86 @@ int ext2fs_set_blk_dev (block_dev_desc_t * rbdd, int part) return 0; } } - return (part_info.size); + return part_info.size; } -int ext2fs_devread (int sector, int byte_offset, int byte_len, char *buf) { +int ext2fs_devread(int sector, int byte_offset, int byte_len, char *buf) +{ char sec_buf[SECTOR_SIZE]; - unsigned block_len; + unsigned sectors; -/* - * Check partition boundaries - */ - if ((sector < 0) - || ((sector + ((byte_offset + byte_len - 1) >> SECTOR_BITS)) >= + /* + * Check partition boundaries + */ + if ((sector < 0) || + ((sector + ((byte_offset + byte_len - 1) >> SECTOR_BITS)) >= part_info.size)) { - /* errnum = ERR_OUTSIDE_PART; */ - printf (" ** ext2fs_devread() read outside partition sector %d\n", sector); - return (0); + /* errnum = ERR_OUTSIDE_PART; */ + printf(" ** %s read outside partition sector %d\n", + __func__, + sector); + return 0; } -/* - * Get the read to the beginning of a partition. - */ + /* + * Get the read to the beginning of a partition. + */ sector += byte_offset >> SECTOR_BITS; byte_offset &= SECTOR_SIZE - 1; - debug (" <%d, %d, %d>\n", sector, byte_offset, byte_len); + debug(" <%d, %d, %d>\n", sector, byte_offset, byte_len); if (ext2fs_block_dev_desc == NULL) { - printf ("** Invalid Block Device Descriptor (NULL)\n"); - return (0); + printf(" ** %s Invalid Block Device Descriptor (NULL)\n", + __func__); + return 0; } if (byte_offset != 0) { /* read first part which isn't aligned with start of sector */ if (ext2fs_block_dev_desc-> - block_read (ext2fs_block_dev_desc->dev, - part_info.start + sector, 1, - (unsigned long *) sec_buf) != 1) { - printf (" ** ext2fs_devread() read error **\n"); - return (0); + block_read(ext2fs_block_dev_desc->dev, + part_info.start + sector, 1, + (unsigned long *) sec_buf) != 1) { + printf(" ** %s read error **\n", __func__); + return 0; } - memcpy (buf, sec_buf + byte_offset, - min (SECTOR_SIZE - byte_offset, byte_len)); - buf += min (SECTOR_SIZE - byte_offset, byte_len); - byte_len -= min (SECTOR_SIZE - byte_offset, byte_len); + memcpy(buf, sec_buf + byte_offset, + min(SECTOR_SIZE - byte_offset, byte_len)); + buf += min(SECTOR_SIZE - byte_offset, byte_len); + byte_len -= min(SECTOR_SIZE - byte_offset, byte_len); sector++; } - if (byte_len == 0) - return 1; - /* read sector aligned part */ - block_len = byte_len & ~(SECTOR_SIZE - 1); - - if (block_len == 0) { - u8 p[SECTOR_SIZE]; - - block_len = SECTOR_SIZE; - ext2fs_block_dev_desc->block_read(ext2fs_block_dev_desc->dev, - part_info.start + sector, - 1, (unsigned long *)p); - memcpy(buf, p, byte_len); - return 1; - } + sectors = byte_len / SECTOR_SIZE; + + if (sectors > 0) { + if (ext2fs_block_dev_desc->block_read( + ext2fs_block_dev_desc->dev, + part_info.start + sector, + sectors, + (unsigned long *) buf) != sectors) { + printf(" ** %s read error - block\n", __func__); + return 0; + } - if (ext2fs_block_dev_desc->block_read (ext2fs_block_dev_desc->dev, - part_info.start + sector, - block_len / SECTOR_SIZE, - (unsigned long *) buf) != - block_len / SECTOR_SIZE) { - printf (" ** ext2fs_devread() read error - block\n"); - return (0); + buf += sectors * SECTOR_SIZE; + byte_len -= sectors * SECTOR_SIZE; + sector += sectors; } - block_len = byte_len & ~(SECTOR_SIZE - 1); - buf += block_len; - byte_len -= block_len; - sector += block_len / SECTOR_SIZE; if (byte_len != 0) { /* read rest of data which are not in whole sector */ if (ext2fs_block_dev_desc-> - block_read (ext2fs_block_dev_desc->dev, - part_info.start + sector, 1, - (unsigned long *) sec_buf) != 1) { - printf (" ** ext2fs_devread() read error - last part\n"); - return (0); + block_read(ext2fs_block_dev_desc->dev, + part_info.start + sector, 1, + (unsigned long *) sec_buf) != 1) { + printf(" ** %s read error - last part\n", __func__); + return 0; } - memcpy (buf, sec_buf, byte_len); + memcpy(buf, sec_buf, byte_len); } - return (1); + return 1; } diff --git a/fs/fat/Makefile b/fs/fat/Makefile index bc45966..93b6f07 100644 --- a/fs/fat/Makefile +++ b/fs/fat/Makefile @@ -24,7 +24,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)libfat.o AOBJS = -COBJS-$(CONFIG_CMD_FAT) := fat.o file.o +COBJS-$(CONFIG_CMD_FAT) := fat.o + +ifndef CONFIG_SPL_BUILD +COBJS-$(CONFIG_CMD_FAT) += file.o +endif SRCS := $(AOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS-y)) diff --git a/include/ACEX1K.h b/include/ACEX1K.h index ae20164..e2e96d2 100644 --- a/include/ACEX1K.h +++ b/include/ACEX1K.h @@ -30,13 +30,13 @@ #include <altera.h> -extern int ACEX1K_load( Altera_desc *desc, void *image, size_t size ); -extern int ACEX1K_dump( Altera_desc *desc, void *buf, size_t bsize ); -extern int ACEX1K_info( Altera_desc *desc ); +extern int ACEX1K_load(Altera_desc *desc, const void *image, size_t size); +extern int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize); +extern int ACEX1K_info(Altera_desc *desc); -extern int CYC2_load( Altera_desc *desc, void *image, size_t size ); -extern int CYC2_dump( Altera_desc *desc, void *buf, size_t bsize ); -extern int CYC2_info( Altera_desc *desc ); +extern int CYC2_load(Altera_desc *desc, const void *image, size_t size); +extern int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize); +extern int CYC2_info(Altera_desc *desc); /* Slave Serial Implementation function table */ typedef struct { @@ -76,6 +76,7 @@ typedef struct { #define Altera_EP2C8_SIZE 247942 #define Altera_EP2C20_SIZE 586562 #define Altera_EP2C35_SIZE 883905 +#define Altera_EP3C5_SIZE 368011 /* .rbf size in bytes */ /* Descriptor Macros *********************************************************************/ diff --git a/include/ahci.h b/include/ahci.h index 0c6bbbd..465ea7f 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -25,6 +25,8 @@ #ifndef _AHCI_H_ #define _AHCI_H_ +#include <pci.h> + #define AHCI_PCI_BAR 0x24 #define AHCI_MAX_SG 56 /* hardware max is 64K */ #define AHCI_CMD_SLOT_SZ 32 @@ -187,4 +189,6 @@ struct ahci_probe_ent { u32 link_port_map; /*linkup port map*/ }; +int ahci_init(u32 base); + #endif diff --git a/include/altera.h b/include/altera.h index bc21ddf..7a2bece 100644 --- a/include/altera.h +++ b/include/altera.h @@ -51,18 +51,18 @@ typedef enum { /* typedef Altera_iface */ passive_parallel_asynchronous, /* parallel data */ passive_serial_asynchronous, /* serial data w/ internal clock (not used) */ altera_jtag_mode, /* jtag/tap serial (not used ) */ - fast_passive_parallel, /* fast passive parallel (FPP) */ + fast_passive_parallel, /* fast passive parallel (FPP) */ fast_passive_parallel_security, /* fast passive parallel with security (FPPS) */ max_altera_iface_type /* insert all new types before this */ } Altera_iface; /* end, typedef Altera_iface */ typedef enum { /* typedef Altera_Family */ - min_altera_type, /* insert all new types after this */ - Altera_ACEX1K, /* ACEX1K Family */ - Altera_CYC2, /* CYCLONII Family */ + min_altera_type, /* insert all new types after this */ + Altera_ACEX1K, /* ACEX1K Family */ + Altera_CYC2, /* CYCLONII Family */ Altera_StratixII, /* StratixII Familiy */ /* Add new models here */ - max_altera_type /* insert all new types before this */ + max_altera_type /* insert all new types before this */ } Altera_Family; /* end, typedef Altera_Family */ typedef struct { /* typedef Altera_desc */ @@ -76,9 +76,9 @@ typedef struct { /* typedef Altera_desc */ /* Generic Altera Functions *********************************************************************/ -extern int altera_load( Altera_desc *desc, void *image, size_t size ); -extern int altera_dump( Altera_desc *desc, void *buf, size_t bsize ); -extern int altera_info( Altera_desc *desc ); +extern int altera_load(Altera_desc *desc, const void *image, size_t size); +extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize); +extern int altera_info(Altera_desc *desc); /* Board specific implementation specific function types *********************************************************************/ @@ -88,7 +88,7 @@ typedef int (*Altera_status_fn)( int cookie ); typedef int (*Altera_done_fn)( int cookie ); typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie ); typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie ); -typedef int (*Altera_write_fn)(void *buf, size_t len, int flush, int cookie); +typedef int(*Altera_write_fn)(const void *buf, size_t len, int flush, int cookie); typedef int (*Altera_abort_fn)( int cookie ); typedef int (*Altera_post_fn)( int cookie ); diff --git a/include/command.h b/include/command.h index 8310fe5..f1accd0 100644 --- a/include/command.h +++ b/include/command.h @@ -71,7 +71,7 @@ int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int cmd_tbl_t *find_cmd(const char *cmd); cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len); -extern int cmd_usage(cmd_tbl_t *cmdtp); +extern int cmd_usage(const cmd_tbl_t *cmdtp); #ifdef CONFIG_AUTO_COMPLETE extern int var_complete(int argc, char * const argv[], char last_char, int maxv, char *cmdv[]); @@ -98,7 +98,15 @@ extern int cmd_get_data_size(char* arg, int default_size); #ifdef CONFIG_CMD_BOOTD extern int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); #endif +#ifdef CONFIG_CMD_BOOTM extern int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +extern int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd); +#else +static inline int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd) +{ + return 0; +} +#endif extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); #endif /* __ASSEMBLY__ */ diff --git a/include/common.h b/include/common.h index 1e4a6a5..12a1074 100644 --- a/include/common.h +++ b/include/common.h @@ -137,6 +137,9 @@ typedef volatile unsigned char vu_char; #define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0) #endif /* BUG */ +/* Force a compilation error if condition is true */ +#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)])) + typedef void (interrupt_handler_t)(void *); #include <asm/u-boot.h> /* boot information for Linux kernel */ @@ -219,6 +222,9 @@ typedef void (interrupt_handler_t)(void *); void hang (void) __attribute__ ((noreturn)); +int timer_init(void); +int cpu_init(void); + /* */ phys_size_t initdram (int); int display_options (void); @@ -259,13 +265,13 @@ void doc_probe(unsigned long physadr); int env_init (void); void env_relocate (void); int envmatch (uchar *, int); -char *getenv (char *); -int getenv_f (char *name, char *buf, unsigned len); +char *getenv (const char *); +int getenv_f (const char *name, char *buf, unsigned len); int saveenv (void); #ifdef CONFIG_PPC /* ARM version to be fixed! */ -int inline setenv (char *, char *); +int inline setenv (const char *, const char *); #else -int setenv (char *, char *); +int setenv (const char *, const char *); #endif /* CONFIG_PPC */ #ifdef CONFIG_ARM # include <asm/mach-types.h> @@ -317,7 +323,7 @@ const char *symbol_lookup(unsigned long addr, unsigned long *caddr); void api_init (void); /* common/memsize.c */ -long get_ram_size (volatile long *, long); +long get_ram_size (long *, long); /* $(BOARD)/$(BOARD).c */ void reset_phy (void); @@ -413,6 +419,7 @@ void icache_disable(void); int dcache_status (void); void dcache_enable (void); void dcache_disable(void); +void mmu_disable(void); void relocate_code (ulong, gd_t *, ulong) __attribute__ ((noreturn)); ulong get_endaddr (void); void trap_init (ulong); @@ -586,7 +593,6 @@ void irq_install_handler(int, interrupt_handler_t *, void *); void irq_free_handler (int); void reset_timer (void); ulong get_timer (ulong base); -void set_timer (ulong t); void enable_interrupts (void); int disable_interrupts (void); @@ -606,17 +612,16 @@ void mii_init (void); /* $(CPU)/.../lcd.c */ ulong lcd_setmem (ulong); -/* $(CPU)/.../vfd.c */ -ulong vfd_setmem (ulong); - /* $(CPU)/.../video.c */ ulong video_setmem (ulong); /* arch/$(ARCH)/lib/cache.c */ void flush_cache (unsigned long, unsigned long); +void flush_dcache_all(void); void flush_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_range(unsigned long start, unsigned long stop); - +void invalidate_dcache_all(void); +void invalidate_icache_all(void); /* arch/$(ARCH)/lib/ticks.S */ unsigned long long get_ticks(void); @@ -654,7 +659,7 @@ int strict_strtoul(const char *cp, unsigned int base, unsigned long *res); unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base); long simple_strtol(const char *cp,char **endp,unsigned int base); void panic(const char *fmt, ...) - __attribute__ ((format (__printf__, 1, 2))); + __attribute__ ((format (__printf__, 1, 2), noreturn)); int sprintf(char * buf, const char *fmt, ...) __attribute__ ((format (__printf__, 2, 3))); int vsprintf(char *buf, const char *fmt, va_list args); @@ -762,4 +767,9 @@ int cpu_release(int nr, int argc, char * const argv[]); #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) +/* Pull in stuff for the build system */ +#ifdef DO_DEPS_ONLY +# include <environment.h> +#endif + #endif /* __COMMON_H_ */ diff --git a/include/commproc.h b/include/commproc.h index a69a809..8b8cc45 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -108,7 +108,7 @@ typedef struct cpm_buf_desc { uint cbd_bufaddr; /* Buffer address in host memory */ } cbd_t; -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ diff --git a/include/compiler.h b/include/compiler.h index 91dbe56..4e047c7 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -44,7 +44,7 @@ #ifdef __linux__ # include <endian.h> # include <byteswap.h> -#elif defined(__MACH__) +#elif defined(__MACH__) || defined(__FreeBSD__) # include <machine/endian.h> typedef unsigned long ulong; #endif diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index cdc5ff1..9716f9c 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -87,7 +87,6 @@ #define CONFIG_CMD_UNIVERSE /* Tundra Universe Support */ #define CONFIG_CMD_UNZIP /* unzip from memory to memory */ #define CONFIG_CMD_USB /* USB Support */ -#define CONFIG_CMD_VFD /* VFD support (TRAB) */ #define CONFIG_CMD_XIMG /* Load part of Multi Image */ #endif /* _CONFIG_CMD_ALL_H */ diff --git a/include/config_defaults.h b/include/config_defaults.h index 0337163..d023c63 100644 --- a/include/config_defaults.h +++ b/include/config_defaults.h @@ -16,5 +16,6 @@ #define CONFIG_GZIP 1 #define CONFIG_ZLIB 1 +#define CONFIG_PARTITIONS 1 #endif diff --git a/include/configs/B2.h b/include/configs/B2.h index 7846a92..e181fa8 100644 --- a/include/configs/B2.h +++ b/include/configs/B2.h @@ -38,7 +38,8 @@ #define CONFIG_B2 1 /* on an B2 Board */ #define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */ #undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ -#define CONFIG_SYS_NO_CP15_CACHE +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF #define CONFIG_ARCH_CPU_INIT #define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/ diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h new file mode 100644 index 0000000..f9681cd --- /dev/null +++ b/include/configs/MERGERBOX.h @@ -0,0 +1,619 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * Copyright (C) 2011 Matrix Vision GmbH + * Andre Schwarz <andre.schwarz@matrix-vision.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <version.h> + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 +#define CONFIG_MPC83xx 1 +#define CONFIG_MPC837x 1 +#define CONFIG_MPC8377 1 + +#define CONFIG_SYS_TEXT_BASE 0xFC000000 + +#define CONFIG_PCI 1 + +#define CONFIG_MASK_AER_AO +#define CONFIG_DISPLAY_AER_FULL + +#define CONFIG_MISC_INIT_R + +/* + * On-board devices + */ +#define CONFIG_TSEC_ENET + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ +#define CONFIG_PCIE +#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +/* + * Hardware Reset Configuration Word stored in EEPROM. + */ +#define CONFIG_SYS_HRCW_LOW 0 +#define CONFIG_SYS_HRCW_HIGH 0 + +/* Arbiter Configuration Register */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 +#define CONFIG_SYS_ACR_RPTCNT 3 + +/* System Priority Control Regsiter */ +#define CONFIG_SYS_SPCR_TSECEP 3 + +/* System Clock Configuration Register */ +#define CONFIG_SYS_SCCR_TSEC1CM 3 +#define CONFIG_SYS_SCCR_TSEC2CM 0 +#define CONFIG_SYS_SCCR_SDHCCM 3 +#define CONFIG_SYS_SCCR_ENCCM 3 /* also clock for I2C-1 */ +#define CONFIG_SYS_SCCR_USBDRCM CONFIG_SYS_SCCR_ENCCM /* must match */ +#define CONFIG_SYS_SCCR_PCIEXP1CM 3 +#define CONFIG_SYS_SCCR_PCIEXP2CM 3 +#define CONFIG_SYS_SCCR_PCICM 1 +#define CONFIG_SYS_SCCR_SATACM 0xFF + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH 0x087c0000 +#define CONFIG_SYS_SICRL 0x40000000 + +/* + * Output Buffer Impedance + */ +#define CONFIG_SYS_OBIR 0x30000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_83XX_DDR_USES_CS0 + +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN | DDRCDR_PZ_HIZ |\ + DDRCDR_NZ_HIZ | DDRCDR_ODT |\ + DDRCDR_Q_DRN) + +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + +#define CONFIG_SYS_DDR_MODE_WEAK +#define CONFIG_SYS_DDR_WRITE_DATA_DELAY 2 +#define CONFIG_SYS_DDR_CPO 0x1f + +/* SPD table located at offset 0x20 in extended adressing ROM + * used for HRCW fetch after power-on reset + */ +#define CONFIG_SPD_EEPROM +#define SPD_EEPROM_ADDRESS 0x50 +#define SPD_EEPROM_OFFSET 0x20 +#define SPD_EEPROM_ADDR_LEN 2 + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (512*1024) +#define CONFIG_SYS_MALLOC_LEN (512*1024) + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\ + CONFIG_SYS_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 +#define CONFIG_SYS_LBC_LBCR 0x00000000 +#define CONFIG_FSL_ELBC 1 + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_FLASH_SIZE 64 + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\ + OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX |\ + OR_GPCM_EHTR | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* + * NAND Flash on the Local Bus + */ +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_NAND_FSL_ELBC 1 + +#define CONFIG_SYS_NAND_BASE 0xE0600000 +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | (2<<BR_DECC_SHIFT) |\ + BR_PS_8 | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 | OR_FCM_BCTLD | OR_FCM_CST |\ + OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\ + OR_FCM_TRLX | OR_FCM_EHTR) + +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +#define CONFIG_CONSOLE ttyS0 +#define CONFIG_BAUDRATE 115200 + +/* SERDES */ +#define CONFIG_FSL_SERDES +#define CONFIG_FSL_SERDES1 0xe3000 +#define CONFIG_FSL_SERDES2 0xe3100 + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* I2C */ +#define CONFIG_HARD_I2C +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_SPEED 120000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE +#define CONFIG_SYS_PCI_MEM_SIZE (256 << 20) +#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE +#define CONFIG_SYS_PCI_MMIO_SIZE (256 << 20) +#define CONFIG_SYS_PCI_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 +#define CONFIG_SYS_PCI_IO_SIZE (1 << 20) + +#ifdef CONFIG_PCIE +#define CONFIG_SYS_PCIE1_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_CFG_SIZE (128 << 20) +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE (256 << 20) +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 +#define CONFIG_SYS_PCIE1_IO_SIZE (8 << 20) + +#define CONFIG_SYS_PCIE2_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_CFG_SIZE (128 << 20) +#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE (256 << 20) +#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 +#define CONFIG_SYS_PCIE2_IO_SIZE (8 << 20) +#endif + +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +/* + * TSEC + */ +#define CONFIG_NET_MULTI +#define CONFIG_GMII /* MII PHY management */ +#define CONFIG_SYS_VSC8601_SKEWFIX +#define CONFIG_SYS_VSC8601_SKEW_TX 3 +#define CONFIG_SYS_VSC8601_SKEW_RX 3 + +#define CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define TSEC1_PHY_ADDR 0x10 +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC1_PHYIDX 0 + +#define CONFIG_ETHPRIME "TSEC0" +#define CONFIG_HAS_ETH0 + +/* + * SATA + */ +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1_OFFSET 0x18000 +#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2_OFFSET 0x19000 +#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_VENDOREX +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_NTPSERVER +#define CONFIG_BOOTP_RANDOM_DELAY +#define CONFIG_BOOTP_SEND_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PCI +#define CONFIG_CMD_USB +#define CONFIG_CMD_SPI +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_SATA + +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 + +#define CONFIG_RBTREE +#define CONFIG_LZO + +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS + +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=NOR,nand0=NAND" +#define MTDPARTS_DEFAULT "mtdparts=NOR:1M(u-boot),2M(FPGA);NAND:-(root)" + +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE 1 + +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_LOAD_ADDR 0x2000000 +#define CONFIG_LOADADDR 0x4000000 +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 256 + +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_LOADS_ECHO 1 +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 + +#define CONFIG_SYS_MEMTEST_START (60<<20) +#define CONFIG_SYS_MEMTEST_END (70<<20) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ +#define CONFIG_HIGH_BATS 1 + +/* DDR: cache cacheable */ +#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE + +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_10 |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* unused */ +#define CONFIG_SYS_IBAT1L (0) +#define CONFIG_SYS_IBAT1U (0) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 |\ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* unused */ +#define CONFIG_SYS_IBAT3L (0) +#define CONFIG_SYS_IBAT3U (0) +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +/* PCI MEM space: cacheable */ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U + +/* PCI MMIO space: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +/* + * I2C EEPROM settings + */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_SIZE 0x4000 + +/* + * Environment Configuration + */ +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR 0xFFD00000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +/* + * Video + */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_SM501_PCI +#define VIDEO_FB_LITTLE_ENDIAN +#define CONFIG_CMD_BMP +#define CONFIG_VIDEO_SM501 +#define CONFIG_VIDEO_SM501_32BPP +#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) + +/* + * SPI + */ +#define CONFIG_MPC8XXX_SPI + +/* + * USB + */ +#define CONFIG_SYS_USB_HOST +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_HAS_FSL_DR_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +#define CONFIG_USB_STORAGE +#define CONFIG_USB_KEYBOARD +/* + * + */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR "s" +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_RESET_TO_RETRY 1000 + +#define MV_CI MergerBox +#define MV_VCI MergerBox +#define MV_FPGA_DATA 0xfc100000 +#define MV_FPGA_SIZE 0x00200000 + +#define CONFIG_SHOW_BOOT_PROGRESS 1 + +#define MV_KERNEL_ADDR_RAM 0x02800000 +#define MV_DTB_ADDR_RAM 0x00600000 +#define MV_INITRD_ADDR_RAM 0x01000000 +#define MV_FITADDR 0xfc300000 +#define MV_SPLAH_ADDR 0xffe00000 + +#define CONFIG_BOOTCOMMAND "run i2c_init;if test ${boot_sqfs} -eq 1;"\ + "then; run fitboot;else;run ubiboot;fi;" +#define CONFIG_BOOTARGS "console=ttyS0,115200n8" + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console_nr=0\0"\ + "stdin=serial\0"\ + "stdout=serial\0"\ + "stderr=serial\0"\ + "boot_sqfs=1\0"\ + "usb_dr_mode=host\0"\ + "bootfile=MergerBox.fit\0"\ + "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0"\ + "fpga=0\0"\ + "fpgadata=" MK_STR(MV_FPGA_DATA) "\0"\ + "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0"\ + "mv_kernel_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0"\ + "mv_initrd_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0"\ + "mv_dtb_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0"\ + "uboota=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0"\ + "fitaddr=" MK_STR(MV_FITADDR) "\0"\ + "mv_version=" U_BOOT_VERSION "\0"\ + "mtdids=" MTDIDS_DEFAULT "\0"\ + "mtdparts=" MTDPARTS_DEFAULT "\0"\ + "dhcp_client_id=" MK_STR(MV_CI) "\0"\ + "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0"\ + "upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\ + "protect off all;erase $uboota +0xC0000;"\ + "cp.b $loadaddr $uboota $filesize\0"\ + "upd_fpga=dhcp;tftp MergerBox.rbf;erase $fpgadata +$fpgadatasize;"\ + "cp.b $loadaddr $fpgadata $filesize\0"\ + "upd_fit=dhcp;tftp MergerBox.fit;erase $fitaddr +0x1000000;"\ + "cp.b $loadaddr $fitaddr $filesize\0"\ + "addsqshrfs=set bootargs $bootargs root=/dev/ram ro "\ + "rootfstype=squashfs\0"\ + "addubirfs=set bootargs $bootargs ubi.mtd=9 root=ubi0:rootfs rw "\ + "rootfstype=ubifs\0"\ + "addusbrfs=set bootargs $bootargs root=/dev/sda1 rw "\ + "rootfstype=ext3 usb-storage.delay_use=1 rootdelay=3\0"\ + "netusbboot=bootp;run fpganetload fitnetload addusbrfs doboot\0"\ + "netubiboot= bootp;run fpganetload fitnetload addubirfs doboot\0"\ + "ubiboot=run fitprep addubirfs;set mv_initrd_ram -;run doboot\0"\ + "doboot=bootm $mv_kernel_ram $mv_initrd_ram $mv_dtb_ram\0"\ + "fitprep=imxtract $fitaddr kernel $mv_kernel_ram;"\ + "imxtract $fitaddr ramdisk $mv_initrd_ram;"\ + "imxtract $fitaddr fdt $mv_dtb_ram\0"\ + "fdtprep=fdt addr $mv_dtb_ram;fdt boardsetup\0"\ + "fitboot=run fitprep fdtprep addsqshrfs doboot\0"\ + "i2c_init=run i2c_speed init_sdi_tx i2c_init_pll\0"\ + "i2c_init_pll=i2c mw 65 9 2;i2c mw 65 9 0;i2c mw 65 5 2b;"\ + "i2c mw 65 7 f;i2c mw 65 8 f;i2c mw 65 11 40;i2c mw 65 12 40;"\ + "i2c mw 65 13 40; i2c mw 65 14 40; i2c mw 65 a 0\0"\ + "i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\ + "init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\ + "i2c mw 21 2 ff;i2c mw 21 3 3c\0"\ + "splashimage=" MK_STR(MV_SPLAH_ADDR) "\0"\ + "" + +#undef MK_STR +#undef XMK_STR + +/* + * FPGA + */ +#define CONFIG_FPGA_COUNT 1 +#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2 +#define CONFIG_FPGA_ALTERA +#define CONFIG_FPGA_CYCLON2 + +#endif diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index e25d5ac..4d4c758 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -59,8 +59,6 @@ */ #define CONFIG_SYS_SICRL 0x00000000 -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ - /* * IMMR new address */ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index a4f42cf..851872a 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -72,7 +72,6 @@ #define CONFIG_SYS_SICRH 0x00000000 #define CONFIG_SYS_SICRL 0x40000000 -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ #define CONFIG_BOARD_EARLY_INIT_R /* diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 7f7ff9f..783ed51 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -262,6 +262,7 @@ #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_HWCONFIG /* enable hwconfig */ #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ #ifdef CONFIG_PHYS_64BIT @@ -782,7 +783,7 @@ "fdtaddr=c00000\0" \ "fdtfile=8536ds/mpc8536ds.dtb\0" \ "bdev=sda3\0" \ - "usb_phy_type=ulpi\0" + "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" #define CONFIG_HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 0c0ae02..c9a0f60 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -91,7 +91,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h index bdc93b6..92b7d6a 100644 --- a/include/configs/NETTA.h +++ b/include/configs/NETTA.h @@ -589,7 +589,7 @@ +------+----------------+------------------------------------------------------------ | # | Name | Comment +------+----------------+------------------------------------------------------------ - | IRQ1 | UINTER_3V | S interupt chips interrupt (common) + | IRQ1 | UINTER_3V | S interrupt chips interrupt (common) | IRQ3 | IRQ_DSP | DSP interrupt | IRQ4 | IRQ_DSP1 | Extra DSP interrupt +------+----------------+------------------------------------------------------------ diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h new file mode 100644 index 0000000..95f3a2c --- /dev/null +++ b/include/configs/P1023RDS.h @@ -0,0 +1,562 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * Authors: Roy Zang <tie-fei.zang@freescale.com> + * Chunhe Lan <b25806@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * p1023rds board configuration file + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_NAND +#define CONFIG_NAND_U_BOOT +#define CONFIG_RAMBOOT_NAND +#endif + +#ifdef CONFIG_NAND_U_BOOT +#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 +#define CONFIG_SYS_TEXT_BASE 0x11001000 + +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ +#else +#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif /* CONFIG_NAND_SPL */ +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE /* BOOKE */ +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_MPC85xx +#define CONFIG_P1023 +#define CONFIG_P1023RDS +#define CONFIG_MP /* support multiple processors */ + +#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#ifndef __ASSEMBLY__ +extern unsigned long get_clock_freq(void); +#endif + +#define CONFIG_SYS_CLK_FREQ 66666666 +#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_HWCONFIG + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x1fffffff /* fix me, only 1G */ +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +#define CONFIG_SYS_LBC_LBCR 0x00000000 /* Implement conversion of + addresses in the LBC */ +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xff600000 /* relocated CCSRBAR */ +/* physical addr of CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ + +/* DDR Setup */ +#define CONFIG_VERY_BIG_RAM + +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 + +/* These are used when DDR doesn't use SPD. */ +#define CONFIG_SYS_SDRAM_SIZE 2048u /* DDR is 2GB */ + +/* Default settings for "stable" mode */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F +#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 +#define CONFIG_SYS_DDR_TIMING_3 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0 0x40110104 +#define CONFIG_SYS_DDR_TIMING_1 0x5C59E544 +#define CONFIG_SYS_DDR_TIMING_2 0x0fA888CA +#define CONFIG_SYS_DDR_MODE_1 0x00441210 +#define CONFIG_SYS_DDR_MODE_2 0x00000000 +#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL 0x0A280100 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_CLK_CTRL 0x01800000 +#define CONFIG_SYS_DDR_TIMING_4 0x00000001 +#define CONFIG_SYS_DDR_TIMING_5 0x01401400 +#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F605 +#define CONFIG_SYS_DDR_CONTROL 0xC70C0008 /* Type = DDR3: No Interleaving */ +#define CONFIG_SYS_DDR_CONTROL2 0x24401010 +#define CONFIG_SYS_DDR_CDR1 0x00000000 +#define CONFIG_SYS_DDR_CDR2 0x00000000 + +#define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 +#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 +#define CONFIG_SYS_DDR_SBE 0x00000000 + +/* Settings that differ for "performance" mode */ +#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */ +#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */ +#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014302 +#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5C58E544 +#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0FA888CA +/* Type = DDR3: cs0-cs1 interleaving */ +#define CONFIG_SYS_DDR_CONTROL_PERF 0xC70C4008 +#define CONFIG_SYS_DDR_CDR_1 0x00000000 +#define CONFIG_SYS_DDR_CDR_2 0x00000000 + + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable + * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable + * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable + * + * Localbus non-cacheable + * 0xe000_0000 0xe003_ffff BCSR 256K BCSR + * 0xee00_0000 0xefff_ffff NOR flash 32M NOR flash + * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M + * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable + * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + */ + +/* + * Local Bus Definitions + */ +#define CONFIG_SYS_BCSR_BASE 0xe0000000 /* start of on board FPGA */ +#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE + +#ifndef CONFIG_NAND +#define CONFIG_SYS_FLASH_BASE 0xee000000 /* start of FLASH 32M */ + +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ + | BR_PS_16 | BR_V) +#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#else +#define CONFIG_SYS_NO_FLASH +#endif + +#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */ +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ + +#ifndef CONFIG_NAND_SPL +#define CONFIG_SYS_NAND_BASE 0xffa00000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#else +#define CONFIG_SYS_NAND_BASE 0xfff00000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif + +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) + +/* NAND boot: 4K NAND loader config */ +#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) + +/* NAND flash config */ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) + +#ifdef CONFIG_RAMBOOT_NAND +/* NAND Base Address */ +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ +/* chip select 1 - BCSR */ +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \ + | BR_MS_GPCM | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \ + | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \ + | OR_GPCM_EAD) +#else +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +/* chip select 1 - BCSR */ +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \ + | BR_MS_GPCM | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \ + | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \ + | OR_GPCM_EAD) +#endif + +/* Serial Port + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +#define CONFIG_SYS_64BIT_VSPRINTF +#define CONFIG_SYS_64BIT_STRTOUL + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* + * I2C2 EEPROM + */ +#define CONFIG_ID_EEPROM +#ifdef CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#endif +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_BUS_NUM 0 + +#define CONFIG_CMD_I2C + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL + +#define CONFIG_HARD_SPI +#define CONFIG_FSL_ESPI + +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 3, Slot 1, tgtid 3, Base address b000 */ +#define CONFIG_SYS_PCIE3_NAME "Slot 3" +#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, direct to uli, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_NAME "Slot 2" +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 1, Slot 2, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "Slot 1" +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +#if defined(CONFIG_PCI) +#define CONFIG_E1000 /* Defind e1000 pci Ethernet card */ +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#endif /* CONFIG_PCI */ + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI +#endif + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x4000) +#define CONFIG_ENV_SIZE 0x2000 +#endif +#else +#define CONFIG_ENV_IS_IN_FLASH +#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 +#define CONFIG_ENV_ADDR 0xfff80000 +#else +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#endif +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_CMD_ELF +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* + * USB + */ +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ + +#define CONFIG_BAUDRATE 115200 + +/* Qman/Bman */ +#define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */ +#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000 +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000 +#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 + +/* For FM */ +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#endif + +#define CONFIG_SYS_FMAN_FW +#ifndef CONFIG_NAND +/* Default address of microcode for the Linux Fman driver */ +/* QE microcode/firmware address */ +#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 +#else +#define CONFIG_SYS_QE_FW_IN_NAND 0x1f00000 +#endif +#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH) + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 +#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x7 + +#define CONFIG_SYS_TBIPA_VALUE 8 +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" + +#endif /* __CONFIG_H */ diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 59f9755..df88b79 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -601,6 +601,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL #define CONFIG_USB_STORAGE +#define CONFIG_HAS_FSL_DR_USB #endif #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) @@ -688,7 +689,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "nandfdtaddr=80000\0" \ "nandimgsize=400000\0" \ "nandfdtsize=80000\0" \ - "usb_phy_type=ulpi\0" \ + "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ "vscfw_addr=ef000000\0" \ "othbootargs=ramdisk_size=600000\0" \ "usbfatboot=setenv bootargs root=/dev/ram rw " \ diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index b5db0b3..90fe7c4 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -752,7 +752,8 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "perf_mode=performance\0" \ - "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=ulpi\0" \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h new file mode 100644 index 0000000..638dbe7 --- /dev/null +++ b/include/configs/P2041RDB.h @@ -0,0 +1,646 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * P2041 RDB board configuration file + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_P2041RDB +#define CONFIG_PHYS_64BIT +#define CONFIG_PPC_P2041 + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_MP /* support multiple processors */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#else +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#endif + +#if defined(CONFIG_SPIFLASH) + #define CONFIG_SYS_EXTRA_ENV_RELOC + #define CONFIG_ENV_IS_IN_SPI_FLASH + #define CONFIG_ENV_SPI_BUS 0 + #define CONFIG_ENV_SPI_CS 0 + #define CONFIG_ENV_SPI_MAX_HZ 10000000 + #define CONFIG_ENV_SPI_MODE 0 + #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ + #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ + #define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) + #define CONFIG_SYS_EXTRA_ENV_RELOC + #define CONFIG_ENV_IS_IN_MMC + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_ENV_SIZE 0x2000 + #define CONFIG_ENV_OFFSET (512 * 1097) +#else + #define CONFIG_ENV_IS_IN_FLASH + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ + - CONFIG_ENV_SECT_SIZE) + #define CONFIG_ENV_SIZE 0x2000 + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_SYS_CLK_FREQ 66666666 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ +#endif + +#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ + CONFIG_RAMBOOT_TEXT_BASE) +#else +#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR +#endif +#define CONFIG_SYS_L3_SIZE (1024 << 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull +#else +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#endif +/* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD +#define CONFIG_FSL_DDR3 + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x52 +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * Local Bus Definitions + */ + +/* Set the local bus clock 1/8 of platform clock */ +#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 + +#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* Start of PromJet */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_SYS_BR0_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ + | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) + +#define CONFIG_FSL_CPLD +#define CPLD_BASE 0xffdf0000 /* CPLD registers */ +#ifdef CONFIG_PHYS_64BIT +#define CPLD_BASE_PHYS 0xfffdf0000ull +#else +#define CPLD_BASE_PHYS CPLD_BASE +#endif + +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ + +#define PIXIS_LBMAP_SWITCH 7 +#define PIXIS_LBMAP_MASK 0xf0 +#define PIXIS_LBMAP_SHIFT 4 +#define PIXIS_LBMAP_ALTBANK 0x40 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x118000 +#define CONFIG_SYS_I2C2_OFFSET 0x118100 + +/* + * RapidIO + */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ + +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#else +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 +#endif +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 +#endif +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 +#endif +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 +#endif +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 +#endif +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* Qman/Bman */ +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#else +#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#endif +#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull +#else +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#endif +#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +/* Default address of microcode for the Linux Fman driver */ +#define CONFIG_SYS_FMAN_FW +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 545KB (1089 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + */ +#define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 +#endif +#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH) + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#endif + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* SATA */ +#define CONFIG_FSL_SATA_V2 +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 +#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 +#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 +#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 +#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 + +#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c +#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d +#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e +#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f + +#define CONFIG_SYS_TBIPA_VALUE 8 +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* +* USB +*/ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 + +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_HZ 1000 /* decrementer freq 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ + +#define CONFIG_BAUDRATE 115200 + +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ + "bank_intlv=cs0_cs1\0" \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "usb_phy_type=" MK_STR(__USB_PHY_TYPE) "\0" \ + "usb_dr_mode=host\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=p2041rdb/p2041rdb.dtb\0" \ + "bdev=sda3\0" \ + "c=ffe\0" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT + +#ifdef CONFIG_SECURE_BOOT +#include <asm/fsl_secure_boot.h> +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h index 70775e7..ae5bc2e 100644 --- a/include/configs/PCI5441.h +++ b/include/configs/PCI5441.h @@ -118,6 +118,7 @@ * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ #define CONFIG_SYS_HZ 1000 /* Always 1000 */ +#define CONFIG_SYS_LOW_RES_TIMER #define CONFIG_SYS_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */ #define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ #define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h index b466c4b..95c30cc 100644 --- a/include/configs/PK1C20.h +++ b/include/configs/PK1C20.h @@ -128,6 +128,7 @@ * TMRMS represents the desired mecs per tick (msecs per interrupt). *----------------------------------------------------------------------*/ #define CONFIG_SYS_HZ 1000 /* Always 1000 */ +#define CONFIG_SYS_LOW_RES_TIMER #define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ #define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ #define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 7c9dd79..5cd517d 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -39,7 +39,7 @@ #define CONFIG_SYS_TEXT_BASE 0x80000000 -/* IMMR Base Addres Register, use Freescale default: 0xff400000 */ +/* IMMR Base Address Register, use Freescale default: 0xff400000 */ #define CONFIG_SYS_IMMR 0xff400000 /* System clock. Primary input clock when in PCI host mode */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 79a958d..b336723 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -147,10 +147,16 @@ * DDR Setup */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ + #if defined(CONFIG_TQM_BIGFLASH) || \ (!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE)) #define CONFIG_SYS_PPC_DDR_WIMGE (MAS2_I | MAS2_G) +#define CONFIG_SYS_DDR_EARLY_SIZE_MB (512) +#else +#define CONFIG_SYS_PPC_DDR_WIMGE (0) +#define CONFIG_SYS_DDR_EARLY_SIZE_MB (2 * 1024) #endif + #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #ifdef CONFIG_TQM8548_AG #define CONFIG_VERY_BIG_RAM diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 3cd1bc3..740cb75 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -33,21 +33,23 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ -#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ -#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ +#define CONFIG_ARM920T /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ +#define CONFIG_VCMA9 /* on a MPL VCMA9 Board */ -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */ +#define CONFIG_SYS_TEXT_BASE 0x0 -#define USE_920T_MMU 1 -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +/* input clock of PLL (VCMA9 has 12MHz input clock) */ +#define CONFIG_SYS_CLK_FREQ 12000000 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG /* * BOOTP options @@ -57,7 +59,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ @@ -68,188 +69,198 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_USB #define CONFIG_CMD_REGINFO -#define CONFIG_CMD_FAT #define CONFIG_CMD_DATE #define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_BSP +#define CONFIG_CMD_NAND +#define BOARD_LATE_INIT #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -/*********************************************************** +#define CONFIG_CMDLINE_EDITING + +/* * I2C stuff: * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at * address 0x50 with 16bit addressing - ***********************************************************/ -#define CONFIG_HARD_I2C /* I2C with hardware support */ + */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */ +/* we use the built-in I2C controller */ +#define CONFIG_DRIVER_S3C24X0_I2C + #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at offset 0 */ -#define CONFIG_ENV_SIZE 0x800 /* 2KB should be more than enough */ +/* use EEPROM for environment vars */ +#define CONFIG_ENV_IS_IN_EEPROM 1 +/* environment starts at offset 0 */ +#define CONFIG_ENV_OFFSET 0x000 +/* 2KB should be more than enough */ +#define CONFIG_ENV_SIZE 0x800 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes page write mode on 24C256 */ +/* 64 bytes page write mode on 24C256 */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* - * Size of malloc() pool - */ -/*#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)*/ - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */ - -/* * Hardware drivers */ #define CONFIG_NET_MULTI -#define CONFIG_CS8900 /* we have a CS8900 on-board */ -#define CONFIG_CS8900_BASE 0x20000300 -#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ - -#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ +#define CONFIG_CS8900 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x20000300 +#define CONFIG_CS8900_BUS16 /* * select serial console configuration */ #define CONFIG_S3C24X0_SERIAL -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ -/************************************************************ - * USB support - ************************************************************/ -#define CONFIG_USB_OHCI 1 -#define CONFIG_USB_KEYBOARD 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_DOS_PARTITION 1 +/* USB support (currently only works with D-cache off) */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_KEYBOARD +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION /* Enable needed helper functions */ -#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ +#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ -/************************************************************ - * RTC - ************************************************************/ -#define CONFIG_RTC_S3C24X0 1 +/* RTC */ +#define CONFIG_RTC_S3C24X0 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 9600 +#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 5 -/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ -/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_RESET_TO_RETRY +#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 10.0.0.110 -#define CONFIG_SERVERIP 10.0.0.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 10.0.0.110 +#define CONFIG_SERVERIP 10.0.0.1 #if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* speed to run kgdb serial port */ +#define CONFIG_KGDB_BAUDRATE 115200 /* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "VCMA9 # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "VCMA9 # " +#define CONFIG_SYS_CBSIZE 256 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x30F80000 /* 15.5 MB in DRAM */ +/* to be activated as soon as s3c24x0 has print_cpuinfo support */ +/*#define CONFIG_DISPLAY_CPUINFO*/ /* Display cpu info */ +#define CONFIG_DISPLAY_BOARDINFO /* Display board info */ + +#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */ #define CONFIG_SYS_ALT_MEMTEST -#define CONFIG_SYS_LOAD_ADDR 0x30800000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x30800000 -/* we configure PWM Timer 4 to 1us ~ 1MHz */ -/*#define CONFIG_SYS_HZ 1000000 */ -#define CONFIG_SYS_HZ 1562500 +/* we configure PWM Timer 4 to 1ms 1000Hz */ +#define CONFIG_SYS_HZ 1000 /* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -/* support BZIP2 compression */ -#define CONFIG_BZIP2 1 +/* support additional compression methods */ +#define CONFIG_BZIP2 +#define CONFIG_LZO +#define CONFIG_LZMA -/************************************************************ - * Ident - ************************************************************/ +/* Ident */ /*#define VERSION_TAG "released"*/ #define VERSION_TAG "unstable" -#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG +#define CONFIG_IDENT_STRING "\n(c) 2003 - 2011 by MPL AG Switzerland, " \ + "MEV-10080-001 " VERSION_TAG -/*----------------------------------------------------------------------- +/* * Stack sizes - * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ #endif -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ -#if 0 -#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ -#endif +/* FLASH and environment organization */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx16 +#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#ifdef CONFIG_AMD_LV800 -#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */ -#endif -#ifdef CONFIG_AMD_LV400 -#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ -#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */ -#endif - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_SECT (19) -#if 0 -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +/* + * Size of malloc() pool + * BZIP2 / LZO / LZMA need a lot of RAM + */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +/* NAND configuration */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_S3C2410 +#define CONFIG_SYS_S3C2410_NAND_HWECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0x4E000000 +#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING +#define CONFIG_S3C24XX_TACLS 1 +#define CONFIG_S3C24XX_TWRPH0 5 +#define CONFIG_S3C24XX_TWRPH1 3 #endif +#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 +/* File system */ +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_JFFS2 +#define CONFIG_YAFFS2 +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ GENERATED_GBL_DATA_SIZE) +#define CONFIG_BOARD_EARLY_INIT_F -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h index dfab0f4..62913b5 100644 --- a/include/configs/a320evb.h +++ b/include/configs/a320evb.h @@ -24,29 +24,35 @@ #include <asm/arch/a320.h> -/*----------------------------------------------------------------------- +/* + * Linux kernel tagged list + */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +/* * CPU and Board Configuration Options */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #undef CONFIG_SKIP_LOWLEVEL_INIT -/*----------------------------------------------------------------------- +/* * Power Management Unit */ #define CONFIG_FTPMU010_POWER -/*----------------------------------------------------------------------- +/* * Timer */ #define CONFIG_SYS_HZ 1000 /* timer ticks per second */ -/*----------------------------------------------------------------------- +/* * Real Time Clock */ #define CONFIG_RTC_FTRTC010 -/*----------------------------------------------------------------------- +/* * Serial console configuration */ @@ -62,7 +68,7 @@ /* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -/*----------------------------------------------------------------------- +/* * Ethernet */ #define CONFIG_NET_MULTI @@ -70,7 +76,7 @@ #define CONFIG_BOOTDELAY 3 -/*----------------------------------------------------------------------- +/* * Command line configuration. */ #include <config_cmd_default.h> @@ -79,7 +85,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_PING -/*----------------------------------------------------------------------- +/* * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ @@ -96,7 +102,7 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/*----------------------------------------------------------------------- +/* * Stack sizes * * The stack sizes are set up in start.S using the settings below @@ -107,12 +113,12 @@ #define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ #endif -/*----------------------------------------------------------------------- +/* * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) -/*----------------------------------------------------------------------- +/* * SDRAM controller configuration */ #define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \ @@ -132,7 +138,7 @@ FTSDMC020_BANK_MBW_32 | \ FTSDMC020_BANK_SIZE_64M) -/*----------------------------------------------------------------------- +/* * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ @@ -155,7 +161,7 @@ #define CONFIG_SYS_TEXT_BASE 0 -/*----------------------------------------------------------------------- +/* * Static memory controller configuration */ @@ -194,7 +200,7 @@ { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ } -/*----------------------------------------------------------------------- +/* * FLASH and environment organization */ diff --git a/include/configs/actux1.h b/include/configs/actux1.h index 8121b27..2717aba 100644 --- a/include/configs/actux1.h +++ b/include/configs/actux1.h @@ -26,13 +26,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* 1: modified board with 32MB DRAM */ -#define CONFIG_ACTUX1_32MB 0 -/* 1: 2*2MB FLASH (standard) */ -#define CONFIG_ACTUX1_FLASH2X2 1 -/* 1: 1*8MB FLASH (upgraded boards) */ -#define CONFIG_ACTUX1_FLASH1X8 0 - #define CONFIG_IXP425 1 #define CONFIG_ACTUX1 1 @@ -44,12 +37,12 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_SYS_LDSCRIPT "board/actux1/u-boot.lds" /*************************************************************** * U-boot generic defines start here. ***************************************************************/ -#undef CONFIG_USE_IRQ - /* * Size of malloc() pool */ @@ -62,8 +55,13 @@ #include <config_cmd_default.h> #define CONFIG_CMD_ELF -#undef CONFIG_CMD_PCI -#undef CONFIG_PCI +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_PCI_PNP +#define CONFIG_IXP_PCI +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI_ENUM +#endif #define CONFIG_BOOTCOMMAND "run boot_flash" /* enable passing of ATAGs */ @@ -93,8 +91,9 @@ #define CONFIG_SYS_MEMTEST_START 0x00400000 #define CONFIG_SYS_MEMTEST_END 0x00800000 -/* spec says 66.666 MHz, but it appears to be 33 */ -#define CONFIG_SYS_HZ 3333333 +/* timer clock - 2* OSC_IN system clock */ +#define CONFIG_IXP425_TIMER_CLK 66666666 +#define CONFIG_SYS_HZ 1000 /* default load address */ #define CONFIG_SYS_LOAD_ADDR 0x00010000 @@ -109,10 +108,6 @@ * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -# define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -# define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif /* Expansion bus settings */ #define CONFIG_SYS_EXP_CS0 0xbd113842 @@ -120,9 +115,9 @@ /* SDRAM settings */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_DRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#if CONFIG_ACTUX1_32MB +#ifdef CONFIG_RAM_32MB # define CONFIG_SYS_SDR_CONFIG 0x18 # define PHYS_SDRAM_1_SIZE 0x02000000 # define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a @@ -137,7 +132,8 @@ #endif /* FLASH organization */ -#if CONFIG_ACTUX1_FLASH2X2 +#define CONFIG_SYS_TEXT_BASE 0x50000000 +#ifdef CONFIG_FLASH2X2 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of sectors on one chip */ # define CONFIG_SYS_MAX_FLASH_SECT 40 @@ -145,7 +141,7 @@ # define PHYS_FLASH_2 0x50200000 # define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } #endif -#if CONFIG_ACTUX1_FLASH1X8 +#ifdef CONFIG_FLASH1X8 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of sectors on one chip */ # define CONFIG_SYS_MAX_FLASH_SECT 140 @@ -156,6 +152,7 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_LEN (256 << 10) +#define CONFIG_BOARD_SIZE_LIMIT 262144 /* Use common CFI driver */ #define CONFIG_SYS_FLASH_CFI @@ -172,12 +169,16 @@ #define CONFIG_NET_MULTI 1 /* NPE0 PHY address */ #define CONFIG_PHY_ADDR 0 +/* NPE1 PHY address (HW Release E only) */ +#define CONFIG_PHY1_ADDR 1 /* MII PHY management */ #define CONFIG_MII 1 /* Number of ethernet rx buffers & descriptors */ #define CONFIG_SYS_RX_ETH_BUFFER 16 #define CONFIG_RESET_PHY_R 1 +#define CONFIG_HAS_ETH1 1 + #define CONFIG_CMD_DHCP #define CONFIG_CMD_NET #define CONFIG_CMD_MII @@ -202,17 +203,19 @@ #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) #define CONFIG_SYS_USE_PPCENV 1 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CONFIG_EXTRA_ENV_SETTINGS \ "npe_ucode=50040000\0" \ "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ "kerneladdr=50050000\0" \ + "kernelfile=actux1/uImage\0" \ + "rootfile=actux1/rootfs\0" \ "rootaddr=50170000\0" \ "loadaddr=10000\0" \ "updateboot_ser=mw.b 10000 ff 40000;" \ " loady ${loadaddr};" \ " run eraseboot writeboot\0" \ "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} u-boot.bin;" \ + " tftp ${loadaddr} actux1/u-boot.bin;" \ " run eraseboot writeboot\0" \ "eraseboot=protect off 50000000 50003fff;" \ " protect off 50006000 5003ffff;" \ @@ -220,8 +223,9 @@ " erase 50006000 5003ffff\0" \ "writeboot=cp.b 10000 50000000 4000;" \ " cp.b 16000 50006000 3a000\0" \ - "eraseenv=protect off 50004000 50005fff;" \ - " erase 50004000 50005fff\0" \ + "updateucode=loady;" \ + " era ${npe_ucode} +${filesize};" \ + " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ "updateroot=tftp ${loadaddr} ${rootfile};" \ " era ${rootaddr} +${filesize};" \ " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ @@ -232,7 +236,7 @@ " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \ "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ "boot_flash=run flashargs addtty addeth;" \ " bootm ${kerneladdr}\0" \ @@ -240,4 +244,8 @@ " tftpboot ${loadaddr} ${kernelfile};" \ " bootm\0" +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + #endif /* __CONFIG_H */ diff --git a/include/configs/actux2.h b/include/configs/actux2.h index 8ab3b19..eca814b 100644 --- a/include/configs/actux2.h +++ b/include/configs/actux2.h @@ -37,12 +37,12 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 5 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_SYS_LDSCRIPT "board/actux2/u-boot.lds" /*************************************************************** * U-boot generic defines start here. ***************************************************************/ -#undef CONFIG_USE_IRQ - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) @@ -84,8 +84,9 @@ #define CONFIG_SYS_MEMTEST_START 0x00400000 #define CONFIG_SYS_MEMTEST_END 0x00800000 -/* spec says 66.666 MHz, but it appears to be 33 */ -#define CONFIG_SYS_HZ 3333333 +/* timer clock - 2* OSC_IN system clock */ +#define CONFIG_IXP425_TIMER_CLK 66666666 +#define CONFIG_SYS_HZ 1000 /* default load address */ #define CONFIG_SYS_LOAD_ADDR 0x00010000 @@ -100,10 +101,6 @@ * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -# define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -# define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif /* Expansion bus settings */ #define CONFIG_SYS_EXP_CS0 0xbd113042 @@ -111,7 +108,7 @@ /* SDRAM settings */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_DRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* 16MB SDRAM */ #define CONFIG_SYS_SDR_CONFIG 0x3A @@ -121,6 +118,7 @@ #define CONFIG_SYS_DRAM_SIZE 0x01000000 /* FLASH organization */ +#define CONFIG_SYS_TEXT_BASE 0x50000000 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of sectors on one chip */ #define CONFIG_SYS_MAX_FLASH_SECT 140 @@ -130,6 +128,7 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_LEN (256 << 10) +#define CONFIG_BOARD_SIZE_LIMIT 262144 /* Use common CFI driver */ #define CONFIG_SYS_FLASH_CFI @@ -149,6 +148,11 @@ #define CONFIG_PHY_ADDR 0x00 /* MII PHY management */ #define CONFIG_MII 1 +/* fixed-speed switch without standard PHY registers on MII */ +#define CONFIG_MII_NPE0_FIXEDLINK 1 +#define CONFIG_MII_NPE0_SPEED 100 +#define CONFIG_MII_NPE0_FULLDUPLEX 1 + /* Number of ethernet rx buffers & descriptors */ #define CONFIG_SYS_RX_ETH_BUFFER 16 #define CONFIG_RESET_PHY_R 1 @@ -183,13 +187,15 @@ "npe_ucode=50040000\0" \ "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ "kerneladdr=50050000\0" \ + "kernelfile=actux2/uImage\0" \ + "rootfile=actux2/rootfs\0" \ "rootaddr=50170000\0" \ "loadaddr=10000\0" \ "updateboot_ser=mw.b 10000 ff 40000;" \ " loady ${loadaddr};" \ " run eraseboot writeboot\0" \ "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} u-boot.bin;" \ + " tftp ${loadaddr} actux2/u-boot.bin;" \ " run eraseboot writeboot\0" \ "eraseboot=protect off 50000000 50003fff;" \ " protect off 50006000 5003ffff;" \ @@ -197,8 +203,9 @@ " erase 50006000 5003ffff\0" \ "writeboot=cp.b 10000 50000000 4000;" \ " cp.b 16000 50006000 3a000\0" \ - "eraseenv=protect off 50004000 50005fff;" \ - " erase 50004000 50005fff\0" \ + "updateucode=loady;" \ + " era ${npe_ucode} +${filesize};" \ + " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ "updateroot=tftp ${loadaddr} ${rootfile};" \ " era ${rootaddr} +${filesize};" \ " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ @@ -217,4 +224,8 @@ " tftpboot ${loadaddr} ${kernelfile};" \ " bootm\0" +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + #endif /* __CONFIG_H */ diff --git a/include/configs/actux3.h b/include/configs/actux3.h index 91987cb..c103312 100644 --- a/include/configs/actux3.h +++ b/include/configs/actux3.h @@ -37,12 +37,12 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_SYS_LDSCRIPT "board/actux3/u-boot.lds" /*************************************************************** * U-boot generic defines start here. ***************************************************************/ -#undef CONFIG_USE_IRQ - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) @@ -82,8 +82,9 @@ #define CONFIG_SYS_MEMTEST_START 0x00400000 #define CONFIG_SYS_MEMTEST_END 0x00800000 -/* spec says 66.666 MHz, but it appears to be 33 */ -#define CONFIG_SYS_HZ 3333333 +/* timer clock - 2* OSC_IN system clock */ +#define CONFIG_IXP425_TIMER_CLK 66666666 +#define CONFIG_SYS_HZ 1000 /* default load address */ #define CONFIG_SYS_LOAD_ADDR 0x00010000 @@ -99,10 +100,6 @@ * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -# define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -# define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif /* Expansion bus settings */ #define CONFIG_SYS_EXP_CS0 0xbd113442 @@ -110,7 +107,7 @@ /* SDRAM settings */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_DRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* 16MB SDRAM */ #define CONFIG_SYS_SDR_CONFIG 0x3A @@ -120,6 +117,7 @@ #define CONFIG_SYS_DRAM_SIZE 0x01000000 /* FLASH organization */ +#define CONFIG_SYS_TEXT_BASE 0x50000000 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of sectors on one chip */ #define CONFIG_SYS_MAX_FLASH_SECT 140 @@ -129,6 +127,7 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_LEN (256 << 10) +#define CONFIG_BOARD_SIZE_LIMIT 262144 /* Use common CFI driver */ #define CONFIG_SYS_FLASH_CFI @@ -149,6 +148,11 @@ #define CONFIG_PHY_ADDR 0x10 /* MII PHY management */ #define CONFIG_MII 1 +/* fixed-speed switch without standard PHY registers on MII */ +#define CONFIG_MII_NPE0_FIXEDLINK 1 +#define CONFIG_MII_NPE0_SPEED 100 +#define CONFIG_MII_NPE0_FULLDUPLEX 1 + /* Number of ethernet rx buffers & descriptors */ #define CONFIG_SYS_RX_ETH_BUFFER 16 #define CONFIG_RESET_PHY_R 1 @@ -183,13 +187,15 @@ "npe_ucode=50040000\0" \ "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ "kerneladdr=50050000\0" \ + "kernelfile=actux3/uImage\0" \ + "rootfile=actux3/rootfs\0" \ "rootaddr=50170000\0" \ "loadaddr=10000\0" \ "updateboot_ser=mw.b 10000 ff 40000;" \ " loady ${loadaddr};" \ " run eraseboot writeboot\0" \ "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} u-boot.bin;" \ + " tftp ${loadaddr} actux3/u-boot.bin;" \ " run eraseboot writeboot\0" \ "eraseboot=protect off 50000000 50003fff;" \ " protect off 50006000 5003ffff;" \ @@ -197,8 +203,9 @@ " erase 50006000 5003ffff\0" \ "writeboot=cp.b 10000 50000000 4000;" \ " cp.b 16000 50006000 3a000\0" \ - "eraseenv=protect off 50004000 50005fff;" \ - " erase 50004000 50005fff\0" \ + "updateucode=loady;" \ + " era ${npe_ucode} +${filesize};" \ + " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ "updateroot=tftp ${loadaddr} ${rootfile};" \ " era ${rootaddr} +${filesize};" \ " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ @@ -209,7 +216,7 @@ " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \ "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ "boot_flash=run flashargs addtty addeth;" \ " bootm ${kerneladdr}\0" \ @@ -217,4 +224,8 @@ " tftpboot ${loadaddr} ${kernelfile};" \ " bootm\0" +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + #endif /* __CONFIG_H */ diff --git a/include/configs/actux4.h b/include/configs/actux4.h index 6718921..190de5a 100644 --- a/include/configs/actux4.h +++ b/include/configs/actux4.h @@ -37,12 +37,11 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /*************************************************************** * U-boot generic defines start here. ***************************************************************/ -#undef CONFIG_USE_IRQ - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) @@ -54,6 +53,15 @@ #define CONFIG_CMD_ELF +#define CONFIG_PCI +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_PCI_PNP +#define CONFIG_IXP_PCI +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI_ENUM +#endif + #define CONFIG_BOOTCOMMAND "run boot_flash" /* enable passing of ATAGs */ #define CONFIG_CMDLINE_TAG 1 @@ -81,8 +89,9 @@ #define CONFIG_SYS_MEMTEST_START 0x00400000 #define CONFIG_SYS_MEMTEST_END 0x00800000 -/* spec says 66.666 MHz, but it appears to be 33 */ -#define CONFIG_SYS_HZ 3333333 +/* timer clock - 2* OSC_IN system clock */ +#define CONFIG_IXP425_TIMER_CLK 66000000 +#define CONFIG_SYS_HZ 1000 /* default load address */ #define CONFIG_SYS_LOAD_ADDR 0x00010000 @@ -97,10 +106,6 @@ * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -# define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -# define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif /* Expansion bus settings */ #define CONFIG_SYS_EXP_CS0 0xbd113003 @@ -108,7 +113,7 @@ /* SDRAM settings */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_DRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* 32MB SDRAM */ #define CONFIG_SYS_SDR_CONFIG 0x18 @@ -118,6 +123,7 @@ #define CONFIG_SYS_DRAM_SIZE 0x02000000 /* FLASH organization */ +#define CONFIG_SYS_TEXT_BASE 0x50000000 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max # of sectors per chip */ #define CONFIG_SYS_MAX_FLASH_SECT 70 @@ -128,6 +134,7 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_LEN (252 << 10) +#define CONFIG_BOARD_SIZE_LIMIT 258048 /* Use common CFI driver */ #define CONFIG_SYS_FLASH_CFI @@ -152,6 +159,7 @@ #define CONFIG_PHY_ADDR 0x1C /* MII PHY management */ #define CONFIG_MII 1 + /* Number of ethernet rx buffers & descriptors */ #define CONFIG_SYS_RX_ETH_BUFFER 16 @@ -180,19 +188,22 @@ "mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);" \ "IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0" \ "kerneladdr=51020000\0" \ + "kernelfile=actux4/uImage\0" \ + "rootfile=actux4/rootfs\0" \ "rootaddr=51160000\0" \ "loadaddr=10000\0" \ "updateboot_ser=mw.b 10000 ff 40000;" \ " loady ${loadaddr};" \ " run eraseboot writeboot\0" \ "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} u-boot.bin;" \ + " tftp ${loadaddr} actux4/u-boot.bin;" \ " run eraseboot writeboot\0" \ "eraseboot=protect off 50000000 5003efff;" \ " erase 50000000 +${filesize}\0" \ "writeboot=cp.b 10000 50000000 ${filesize}\0" \ - "eraseenv=protect off 5003f000 5003ffff;" \ - " erase 5003f000 5003ffff\0" \ + "updateucode=loady;" \ + " era ${npe_ucode} +${filesize};" \ + " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ "updateroot=tftp ${loadaddr} ${rootfile};" \ " era ${rootaddr} +${filesize};" \ " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ @@ -211,4 +222,8 @@ " tftpboot ${loadaddr} ${kernelfile};" \ " bootm\0" +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + #endif /* __CONFIG_H */ diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index 36a2a46..2c2c077 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -25,17 +25,21 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91SAM9260 /* Atmel AT91SAM9260 SoC*/ +#include <asm/arch/hardware.h> -#define CONFIG_AT91_LEGACY +#define CONFIG_SYS_TEXT_BASE 0x21f00000 /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */ -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_HZ 1000 -#define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/ -#define CONFIG_AFEB9260 1 /* on an AFEB9260 Board */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_AFEB9260 /* AFEB9260 Board */ #define CONFIG_ARCH_CPU_INIT -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 @@ -46,12 +50,14 @@ /* * Hardware drivers */ -#define CONFIG_AT91_GPIO 1 -#define CONFIG_ATMEL_USART 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define CONFIG_ATMEL_LEGACY +#define CONFIG_AT91_GPIO +#define CONFIG_AT91_PULLUP 1 + +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_USART3 /* USART 3 is DBGU */ #define CONFIG_BOOTDELAY 3 @@ -74,20 +80,20 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_SOURCE -#define CONFIG_CMD_PING 1 -#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NAND 1 -#define CONFIG_CMD_USB 1 +#define CONFIG_CMD_NAND +#define CONFIG_CMD_USB /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI -#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_HAS_DATAFLASH #define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ @@ -100,8 +106,8 @@ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ @@ -112,37 +118,36 @@ #endif /* NOR flash - no real flash on this board */ -#define CONFIG_SYS_NO_FLASH 1 +#define CONFIG_SYS_NO_FLASH /* Ethernet */ -#define CONFIG_MACB 1 -#undef CONFIG_RMII /* We have full MII there */ -#define CONFIG_RESET_PHY_R 1 +#define CONFIG_MACB +#define CONFIG_RESET_PHY_R -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI #define CONFIG_NET_RETRY_COUNT 20 /* USB */ #define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#define CONFIG_USB_STORAGE 1 +#define CONFIG_USB_STORAGE #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END 0x21e00000 -#undef CONFIG_SYS_USE_DATAFLASH_CS0 -#define CONFIG_SYS_USE_DATAFLASH_CS1 1 -#undef CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SYS_USE_DATAFLASH_CS1 +#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 -\ + GENERATED_GBL_DATA_SIZE) /* bootstrap + u-boot + env + linux in dataflash on CS1 */ -#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_ENV_IS_IN_DATAFLASH #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400) #define CONFIG_ENV_OFFSET 0x4200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET) @@ -159,8 +164,8 @@ #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING /* * Size of malloc() pool @@ -172,5 +177,4 @@ #ifdef CONFIG_USE_IRQ #error CONFIG_USE_IRQ not supported #endif - #endif diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 09cb951..743768e 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -28,7 +28,6 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 80ad342..6c5728d 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -28,7 +28,6 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ @@ -190,7 +189,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ - "console=ttyS2,115200n8\0" \ + "console=ttyO2,115200n8\0" \ "mmcargs=setenv bootargs console=${console} " \ "root=/dev/mmcblk0p2 rw " \ "rootfstype=ext3 rootwait\0" \ diff --git a/include/configs/apollon.h b/include/configs/apollon.h index 3364ec0..1f959fc 100644 --- a/include/configs/apollon.h +++ b/include/configs/apollon.h @@ -266,4 +266,8 @@ "-(ubifs)" #endif +#define PHYS_SRAM 0x4020F800 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM + #endif /* __CONFIG_H */ diff --git a/include/configs/assabet.h b/include/configs/assabet.h index 5cd1836..dc9bd88 100644 --- a/include/configs/assabet.h +++ b/include/configs/assabet.h @@ -38,7 +38,7 @@ #undef CONFIG_USE_IRQ /* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE +#define CONFIG_SYS_DCACHE_OFF #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index d2bf4b7..b847798 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -55,23 +55,25 @@ * CONFIG_SYS_HZ is the tick rate for timer tc0 */ #define AT91C_XTAL_CLOCK 18432000 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39) #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 ) #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) #define CONFIG_SYS_HZ 1000 /* CPU configuration */ -#define CONFIG_ARM920T #define CONFIG_AT91RM9200 #define CONFIG_AT91RM9200EK #define CONFIG_CPUAT91 #define USE_920T_MMU +#include <asm/hardware.h> /* needed for port definitions */ + #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -#define CONFIG_AT91FAMILY +#define CONFIG_BOARD_EARLY_INIT_F /* * Memory Configuration @@ -123,8 +125,9 @@ * CONFIG_DBGU is DBGU unit on J10 * CONFIG_USART1 is USART1 on J14 */ -#define CONFIG_AT91RM9200_USART -#define CONFIG_DBGU +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID 0/* ignored in arm */ #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } #define CONFIG_BAUDRATE 115200 @@ -172,7 +175,7 @@ #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_USB_HOST_BASE #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 5e7dee5..88578c6 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -27,38 +27,53 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_AT91_LEGACY +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include <asm/hardware.h> -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ -#define CONFIG_SYS_HZ 1000 +/* + * Warning: changing CONFIG_SYS_TEXT_BASE requires + * adapting the initial boot program. + * Since the linker has to swallow that define, we must use a pure + * hex number here! + */ +#define CONFIG_SYS_TEXT_BASE 0x21f00000 -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ +#define CONFIG_SYS_HZ 1000 -#ifdef CONFIG_AT91SAM9G20EK -#define CONFIG_AT91SAM9G20 1 /* It's an Atmel AT91SAM9G20 SoC*/ +/* Define actual evaluation board type from used processor type */ +#ifdef CONFIG_AT91SAM9G20 +# define CONFIG_AT91SAM9G20EK /* It's an Atmel AT91SAM9G20 EK */ #else -#define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/ +# define CONFIG_AT91SAM9260EK /* It's an Atmel AT91SAM9260 EK */ #endif +/* Misc CPU related */ #define CONFIG_ARCH_CPU_INIT -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Hardware drivers - */ -#define CONFIG_AT91_GPIO 1 -#define CONFIG_ATMEL_USART 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +#define CONFIG_AT91_GPIO +#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } /* LED */ #define CONFIG_AT91_LED @@ -91,10 +106,26 @@ #define CONFIG_CMD_NAND 1 #define CONFIG_CMD_USB 1 -/* SDRAM */ +/* + * SDRAM: 1 bank, min 32, max 128 MB + * Initialized before u-boot gets started. + */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 + +/* + * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, + * leaving the correct space for initial global data structure above + * that address while providing maximum stack area below. + */ +#ifdef CONFIG_AT91SAM9XE +# define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE) +#else +# define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) +#endif /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI @@ -115,16 +146,13 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_ATMEL -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 - +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 #endif /* NOR flash - no real flash on this board */ @@ -150,7 +178,7 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END 0x23e00000 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 @@ -198,9 +226,6 @@ #endif -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } - #define CONFIG_SYS_PROMPT "U-Boot> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 401478b..126907f 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -27,52 +27,62 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_AT91_LEGACY - /* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ 1000 -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#ifdef CONFIG_AT91SAM9G10EK -#define CONFIG_AT91SAM9G10 1 /* It's an Atmel AT91SAM9G10 SoC*/ +#ifdef CONFIG_AT91SAM9G10 +#define CONFIG_AT91SAM9G10EK /* It's an Atmel AT91SAM9G10 EK*/ #else -#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/ +#define CONFIG_AT91SAM9261EK /* It's an Atmel AT91SAM9261 EK*/ #endif + +#include <asm/hardware.h> + #define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_ATMEL_LEGACY +#define CONFIG_SYS_TEXT_BASE 0x21f00000 + /* * Hardware drivers */ -#define CONFIG_AT91_GPIO 1 -#define CONFIG_ATMEL_USART 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +/* gpio */ +#define CONFIG_AT91_GPIO +#define CONFIG_AT91_GPIO_PULLUP 1 + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200, 57600, 38400, 19200, 9600} /* LCD */ -#define CONFIG_LCD 1 +#define CONFIG_LCD #define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO 1 +#define CONFIG_LCD_LOGO #undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO 1 -#define CONFIG_LCD_INFO_BELOW_LOGO 1 -#define CONFIG_SYS_WHITE_ON_BLACK 1 -#define CONFIG_ATMEL_LCD 1 +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_ATMEL_LCD #ifdef CONFIG_AT91SAM9261EK -#define CONFIG_ATMEL_LCD_BGR555 1 -#else -#define CONFIG_AT91SAM9G10_LCD_BASE 0x23E00000 /* LCD is no more in SRAM */ +#define CONFIG_ATMEL_LCD_BGR555 #endif -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* LED */ #define CONFIG_AT91_LED @@ -85,10 +95,10 @@ /* * BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 -#define CONFIG_BOOTP_BOOTPATH 1 -#define CONFIG_BOOTP_GATEWAY 1 -#define CONFIG_BOOTP_HOSTNAME 1 +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME /* * Command line configuration. @@ -101,33 +111,35 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_SOURCE -#define CONFIG_CMD_PING 1 -#define CONFIG_CMD_DHCP 1 -#define CONFIG_CMD_NAND 1 -#define CONFIG_CMD_USB 1 +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND +#define CONFIG_CMD_USB /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE) /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI -#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_HAS_DATAFLASH #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */ -#define AT91_SPI_CLK 15000000 -#define DATAFLASH_TCSS (0x1a << 16) -#define DATAFLASH_TCHS (0x1 << 24) +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD22 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) /* our CLE is AD21 */ @@ -138,24 +150,24 @@ #endif /* NOR flash - no real flash on this board */ -#define CONFIG_SYS_NO_FLASH 1 +#define CONFIG_SYS_NO_FLASH /* Ethernet */ -#define CONFIG_NET_MULTI 1 -#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_NET_MULTI +#define CONFIG_DRIVER_DM9000 #define CONFIG_DM9000_BASE 0x30000000 #define DM9000_IO CONFIG_DM9000_BASE #define DM9000_DATA (CONFIG_DM9000_BASE + 4) -#define CONFIG_DM9000_USE_16BIT 1 -#define CONFIG_DM9000_NO_SROM 1 +#define CONFIG_DM9000_USE_16BIT +#define CONFIG_DM9000_NO_SROM #define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R 1 +#define CONFIG_RESET_PHY_R /* USB */ #define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ #ifdef CONFIG_AT91SAM9G10EK #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10" @@ -163,18 +175,18 @@ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" #endif #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_CMD_FAT 1 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_FAT #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END 0x23e00000 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ -#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_ENV_IS_IN_DATAFLASH #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) #define CONFIG_ENV_OFFSET 0x4200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) @@ -188,7 +200,7 @@ #elif CONFIG_SYS_USE_DATAFLASH_CS3 /* bootstrap + u-boot + env + linux in dataflash on CS3 */ -#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_ENV_IS_IN_DATAFLASH #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + 0x8400) #define CONFIG_ENV_OFFSET 0x4200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET) @@ -202,7 +214,7 @@ #else /* CONFIG_SYS_USE_NANDFLASH */ /* bootstrap + u-boot + env + linux in nandflash */ -#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x60000 #define CONFIG_ENV_OFFSET_REDUND 0x80000 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ @@ -216,22 +228,19 @@ #endif -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } - #define CONFIG_SYS_PROMPT "U-Boot> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING /* * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) -#define CONFIG_STACKSIZE (32*1024) /* regular stack */ +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ #ifdef CONFIG_USE_IRQ #error CONFIG_USE_IRQ not supported diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index f6cb406..d817423 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -27,13 +27,21 @@ #ifndef __CONFIG_H #define __CONFIG_H +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include <asm/hardware.h> + +#define CONFIG_SYS_TEXT_BASE 0x21F00000 + /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */ -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ -#define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */ #define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ @@ -43,17 +51,27 @@ #ifndef CONFIG_SYS_USE_BOOT_NORFLASH #define CONFIG_SKIP_LOWLEVEL_INIT +#else +#define CONFIG_SYS_USE_NORFLASH #endif +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_DISPLAY_CPUINFO + /* * Hardware drivers */ -#define CONFIG_AT91_GPIO 1 -#define CONFIG_ATMEL_USART 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define CONFIG_ATMEL_LEGACY +#define CONFIG_AT91_GPIO 1 +#define CONFIG_AT91_GPIO_PULLUP 1 + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600} /* LCD */ #define CONFIG_LCD 1 @@ -62,16 +80,16 @@ #undef LCD_TEST_PATTERN #define CONFIG_LCD_INFO 1 #define CONFIG_LCD_INFO_BELOW_LOGO 1 -#define CONFIG_SYS_WHITE_ON_BLACK 1 +#define CONFIG_SYS_WHITE_ON_BLACK 1 #define CONFIG_ATMEL_LCD 1 #define CONFIG_ATMEL_LCD_BGR555 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 /* LED */ #define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIO_PORTB, 7 /* the power led */ -#define CONFIG_GREEN_LED AT91_PIO_PORTB, 8 /* the user1 led */ -#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 29 /* the user2 led */ +#define CONFIG_RED_LED AT91_PIN_PB7 /* the power led */ +#define CONFIG_GREEN_LED AT91_PIN_PB8 /* the user1 led */ +#define CONFIG_YELLOW_LED AT91_PIN_PC29 /* the user2 led */ #define CONFIG_BOOTDELAY 3 @@ -101,8 +119,11 @@ /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI @@ -254,19 +275,14 @@ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22 -/* -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 -*/ - +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif @@ -291,7 +307,7 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END 0x23e00000 #ifdef CONFIG_SYS_USE_DATAFLASH @@ -311,7 +327,7 @@ #elif CONFIG_SYS_USE_NANDFLASH /* bootstrap + u-boot + env + linux in nandflash */ -#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_OFFSET 0x60000 #define CONFIG_ENV_OFFSET_REDUND 0x80000 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ @@ -323,15 +339,12 @@ #endif -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } - #define CONFIG_SYS_PROMPT "U-Boot> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_CMDLINE_EDITING 1 #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " @@ -339,12 +352,10 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) #define CONFIG_STACKSIZE (32*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif +#undef CONFIG_USE_IRQ #endif diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 8dbd082..3ca09e1 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -27,33 +27,42 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_AT91_LEGACY +#include <asm/hardware.h> + +#define CONFIG_SYS_TEXT_BASE 0x21F00000 /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_AT91SAM9RLEK 1 /* It's an AT91SAM9RLEK Board */ -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#define CONFIG_AT91SAM9RL 1 /* It's an Atmel AT91SAM9RL SoC*/ -#define CONFIG_AT91SAM9RLEK 1 /* on an AT91SAM9RLEK Board */ #define CONFIG_ARCH_CPU_INIT -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_ATMEL_LEGACY +#define CONFIG_AT91_GPIO 1 +#define CONFIG_AT91_GPIO_PULLUP 1 /* * Hardware drivers */ -#define CONFIG_AT91_GPIO 1 -#define CONFIG_ATMEL_USART 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600} /* LCD */ #define CONFIG_LCD 1 @@ -62,10 +71,13 @@ #undef LCD_TEST_PATTERN #define CONFIG_LCD_INFO 1 #define CONFIG_LCD_INFO_BELOW_LOGO 1 -#define CONFIG_SYS_WHITE_ON_BLACK 1 +#define CONFIG_SYS_WHITE_ON_BLACK 1 #define CONFIG_ATMEL_LCD 1 #define CONFIG_ATMEL_LCD_RGB565 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 +/* Let board_init_f handle the framebuffer allocation */ +#undef CONFIG_FB_ADDR +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + /* LED */ #define CONFIG_AT91_LED @@ -85,25 +97,29 @@ #undef CONFIG_CMD_IMLS #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS #undef CONFIG_CMD_SOURCE #undef CONFIG_CMD_USB -#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_NAND 1 /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE) /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI -#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_HAS_DATAFLASH 1 #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ -#define AT91_SPI_CLK 15000000 -#define DATAFLASH_TCSS (0x1a << 16) -#define DATAFLASH_TCHS (0x1 << 24) +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) /* NOR flash - not present */ #define CONFIG_SYS_NO_FLASH 1 @@ -112,7 +128,7 @@ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) @@ -129,7 +145,7 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END 0x23e00000 #ifdef CONFIG_SYS_USE_DATAFLASH @@ -149,7 +165,7 @@ #else /* CONFIG_SYS_USE_NANDFLASH */ /* bootstrap + u-boot + env + linux in nandflash */ -#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_OFFSET 0x60000 #define CONFIG_ENV_OFFSET_REDUND 0x80000 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ @@ -161,25 +177,20 @@ #endif -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } - #define CONFIG_SYS_PROMPT "U-Boot> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_CMDLINE_EDITING 1 /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) #define CONFIG_STACKSIZE (32*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif +#undef CONFIG_USE_IRQ #endif diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index c17d107..f24452b 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -32,8 +32,6 @@ #define CONFIG_ATSTK1002 #define CONFIG_ATSTK1000 -#define CONFIG_ATSTK1000_EXT_FLASH - /* * Timer clock frequency. We're using the CPU-internal COUNT register * for this, so this is equivalent to the CPU core clock frequency @@ -161,11 +159,8 @@ #define CONFIG_NR_DRAM_BANKS 1 -/* External flash on STK1000 */ -#if 0 -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#endif +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_BASE 0x00000000 #define CONFIG_SYS_FLASH_SIZE 0x800000 diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h index a77d52e..c5e357f 100644 --- a/include/configs/atstk1003.h +++ b/include/configs/atstk1003.h @@ -32,8 +32,6 @@ #define CONFIG_ATSTK1003 #define CONFIG_ATSTK1000 -#define CONFIG_ATSTK1000_EXT_FLASH - /* * Timer clock frequency. We're using the CPU-internal COUNT register * for this, so this is equivalent to the CPU core clock frequency @@ -144,11 +142,8 @@ #define CONFIG_NR_DRAM_BANKS 1 -/* External flash on STK1000 */ -#if 0 -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#endif +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_BASE 0x00000000 #define CONFIG_SYS_FLASH_SIZE 0x800000 diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h index cc00a0a..3814732 100644 --- a/include/configs/atstk1004.h +++ b/include/configs/atstk1004.h @@ -32,8 +32,6 @@ #define CONFIG_ATSTK1004 #define CONFIG_ATSTK1000 -#define CONFIG_ATSTK1000_EXT_FLASH - /* * Timer clock frequency. We're using the CPU-internal COUNT register * for this, so this is equivalent to the CPU core clock frequency @@ -144,11 +142,8 @@ #define CONFIG_NR_DRAM_BANKS 1 -/* External flash on STK1000 */ -#if 0 -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#endif +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_BASE 0x00000000 #define CONFIG_SYS_FLASH_SIZE 0x800000 diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h index 2cff140..26c08e2 100644 --- a/include/configs/atstk1006.h +++ b/include/configs/atstk1006.h @@ -32,8 +32,6 @@ #define CONFIG_ATSTK1006 #define CONFIG_ATSTK1000 -#define CONFIG_ATSTK1000_EXT_FLASH - /* * Timer clock frequency. We're using the CPU-internal COUNT register * for this, so this is equivalent to the CPU core clock frequency @@ -161,11 +159,8 @@ #define CONFIG_NR_DRAM_BANKS 1 -/* External flash on STK1000 */ -#if 0 -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#endif +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_BASE 0x00000000 #define CONFIG_SYS_FLASH_SIZE 0x800000 diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index c31e914..da14a4f 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -260,7 +260,6 @@ #define FLASH_START_POST_BLOCK 11 /* Should > = 11 */ #define FLASH_END_POST_BLOCK 71 /* Should < = 71 */ #endif -#define CONFIG_SYS_POST_WORD_ADDR 0xFF903FFC /* These are for board tests */ #if 0 diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 3312681..57d9b97 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -112,6 +112,10 @@ #ifndef CONFIG_BAUDRATE # define CONFIG_BAUDRATE 57600 #endif +#ifndef CONFIG_DEBUG_EARLY_SERIAL +# define CONFIG_SERIAL_MULTI +# define CONFIG_SYS_BFIN_UART +#endif /* * Debug Settings @@ -200,7 +204,8 @@ "nc=" \ "set ncip ${serverip};" \ "set stdin nc;" \ - "set stdout nc" \ + "set stdout nc;" \ + "set stderr nc" \ "\0" # else # define NETCONSOLE_ENV @@ -273,6 +278,11 @@ #endif /* + * Flash Settings + */ +#define CONFIG_FLASH_SHOW_PROGRESS 45 + +/* * SPI Settings */ #ifdef CONFIG_SPI_FLASH_ALL diff --git a/include/configs/ca9x4_ct_vxp.h b/include/configs/ca9x4_ct_vxp.h index 7f83249..8c57eab 100644 --- a/include/configs/ca9x4_ct_vxp.h +++ b/include/configs/ca9x4_ct_vxp.h @@ -32,16 +32,13 @@ #define CONFIG_REVISION_TAG 1 #define CONFIG_SYS_TEXT_BASE 0x60800000 -/* High Level Configuration Options */ -#define CONFIG_ARMV7 1 - #define CONFIG_SYS_MEMTEST_START 0x60000000 #define CONFIG_SYS_MEMTEST_END 0x20000000 #define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_L2_OFF 1 +#define CONFIG_SYS_L2CACHE_OFF 1 #define CONFIG_INITRD_TAG 1 #define CONFIG_OF_LIBFDT 1 diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h index 9696487..7e179be 100644 --- a/include/configs/cerf250.h +++ b/include/configs/cerf250.h @@ -43,7 +43,7 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE +#define CONFIG_SYS_DCACHE_OFF /* * Size of malloc() pool diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h index 04bca6c..9649e18 100644 --- a/include/configs/cm-bf537e.h +++ b/include/configs/cm-bf537e.h @@ -55,7 +55,7 @@ #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) @@ -65,6 +65,9 @@ #ifndef __ADSPBF534__ #define ADI_CMDS_NETWORK 1 #define CONFIG_BFIN_MAC +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_BASE 0x20308000 +#define CONFIG_SMC911X_16_BIT #define CONFIG_NETCONSOLE 1 #define CONFIG_NET_MULTI 1 #endif @@ -86,6 +89,13 @@ /* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 + + +/* * Env Storage Settings */ #define CONFIG_ENV_IS_IN_FLASH 1 @@ -118,6 +128,14 @@ /* + * SPI_MMC Settings + */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SPI + + +/* * Misc Settings */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h index af2fe89..84846ef 100644 --- a/include/configs/cm-bf537u.h +++ b/include/configs/cm-bf537u.h @@ -54,7 +54,7 @@ #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) @@ -63,11 +63,11 @@ */ #ifndef __ADSPBF534__ #define ADI_CMDS_NETWORK 1 -#define CONFIG_NET_MULTI -/* The next 3 lines are for use with SMSC on EXT-BF5xx-USB-ETH2 */ -#define CONFIG_SMC911X 1 -#define CONFIG_SMC911X_BASE 0x24000000 +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_BASE 0x20308000 #define CONFIG_SMC911X_16_BIT +#define CONFIG_NETCONSOLE 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_HOSTNAME cm-bf537u /* Uncomment next line to use fixed MAC address */ @@ -87,6 +87,13 @@ /* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 + + +/* * Env Storage Settings */ #define CONFIG_ENV_IS_IN_FLASH 1 @@ -119,6 +126,13 @@ /* + * SPI_MMC Settings + */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SPI + +/* * Misc Settings */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 93a1b26..16a5f5b 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -36,7 +36,6 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 9ba032b..adf9906 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -73,6 +73,7 @@ #else #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #endif #if defined(CONFIG_SPIFLASH) @@ -91,6 +92,11 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (512 * 1097) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) @@ -196,10 +202,10 @@ #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_BR0_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ - BR_PS_16 | BR_V) -#define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ +#define CONFIG_SYS_FLASH_BR_PRELIM \ + (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ + | BR_PS_16 | BR_V) +#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_BR1_PRELIM \ @@ -268,9 +274,21 @@ | OR_FCM_TRLX \ | OR_FCM_EHTR) -#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ +#ifdef CONFIG_NAND +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ +#else +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ +#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ +#endif #endif /* CONFIG_NAND_FSL_ELBC */ +#else +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ #endif #define CONFIG_SYS_FLASH_EMPTY_INFO @@ -469,12 +487,27 @@ #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME /* Default address of microcode for the Linux Fman driver */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FMAN_FW_ADDR_PHYS 0xFEF000000ULL +#define CONFIG_SYS_FMAN_FW +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 545KB (1089 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + */ +#define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE) #else -#define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR +#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 #endif +#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH) #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET @@ -562,6 +595,7 @@ #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_CMD_EXT2 +#define CONFIG_HAS_FSL_DR_USB #define CONFIG_MMC @@ -621,9 +655,16 @@ #define CONFIG_BAUDRATE 115200 +#if defined(CONFIG_P4080DS) +#define __USB_PHY_TYPE ulpi +#else +#define __USB_PHY_TYPE utmi +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ - "bank_intlv=cs0_cs1\0" \ + "bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=" MK_STR(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ @@ -639,8 +680,7 @@ "fdtaddr=c00000\0" \ "fdtfile=p4080ds/p4080ds.dtb\0" \ "bdev=sda3\0" \ - "c=ffe\0" \ - "fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0" + "c=ffe\0" #define CONFIG_HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h index a8ada2d..ba9f797 100644 --- a/include/configs/cpu9260.h +++ b/include/configs/cpu9260.h @@ -37,8 +37,7 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 #define CONFIG_SYS_HZ 1000 - -#define CONFIG_ARM926EJS +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #if defined(CONFIG_CPU9G20) #define CONFIG_AT91SAM9G20 @@ -48,6 +47,8 @@ #error "Unknown board" #endif +#include <asm/arch/hardware.h> + #define CONFIG_AT91FAMILY #define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ @@ -251,10 +252,8 @@ #define CONFIG_AT91SAM9_WATCHDOG #define CONFIG_AT91_GPIO #define CONFIG_ATMEL_USART -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS #define CONFIG_BOOTDELAY 3 diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h index cfaef15..75b881c 100644 --- a/include/configs/cpuat91.h +++ b/include/configs/cpuat91.h @@ -37,6 +37,7 @@ #endif #define AT91C_XTAL_CLOCK 18432000 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39) #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3) #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) @@ -45,14 +46,15 @@ #define CONFIG_ARM920T #define CONFIG_AT91RM9200 #define CONFIG_CPUAT91 -#define CONFIG_AT91FAMILY - #undef CONFIG_USE_IRQ #define USE_920T_MMU +#include <asm/hardware.h> /* needed for port definitions */ + #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG +#define CONFIG_BOARD_EARLY_INIT_F #ifndef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR @@ -86,9 +88,9 @@ #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -/* define one of these to choose the DBGU, USART0 or USART1 as console */ -#define CONFIG_AT91RM9200_USART -#define CONFIG_DBGU +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID 0/* ignored in arm */ #undef CONFIG_HARD_I2C #undef CONFIG_SOFT_I2C diff --git a/include/configs/cradle.h b/include/configs/cradle.h index c21af38..21a8e64 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -38,7 +38,7 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE +#define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_TEXT_BASE 0x0 /* * Size of malloc() pool diff --git a/include/configs/csb226.h b/include/configs/csb226.h index 505740c..dcfbc6e 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -44,7 +44,7 @@ /* for timer/console/ethernet */ /* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE +#define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_TEXT_BASE 0x0 /* * Hardware drivers diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 125c690..cf77606 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -32,7 +32,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ diff --git a/include/configs/dig297.h b/include/configs/dig297.h index 7aeb24e..b68f073 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -35,7 +35,6 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP3430 /* which is in a 3430 */ diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h index c738b3a..ec5223c 100644 --- a/include/configs/digsy_mtc.h +++ b/include/configs/digsy_mtc.h @@ -86,10 +86,38 @@ #define CONFIG_BZIP2 /* + * Video + */ +#define CONFIG_VIDEO + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MB862xx +#define CONFIG_VIDEO_MB862xx_ACCEL +#define CONFIG_VIDEO_CORALP +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SPLASH_SCREEN +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ + +/* Coral-PA clock frequency, geo and other both 133MHz */ +#define CONFIG_SYS_MB862xx_CCF 0x00050000 +/* Video SDRAM parameters */ +#define CONFIG_SYS_MB862xx_MMR 0x11d7fa72 +#endif + +/* * Command line configuration. */ #include <config_cmd_default.h> +#ifdef CONFIG_VIDEO +#define CONFIG_CMD_BMP +#endif #define CONFIG_CMD_DFL #define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h index 69c6420..7d79d57 100644 --- a/include/configs/dnp1110.h +++ b/include/configs/dnp1110.h @@ -42,7 +42,7 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE +#define CONFIG_SYS_DCACHE_OFF /* * Size of malloc() pool diff --git a/include/configs/dvlhost.h b/include/configs/dvlhost.h new file mode 100644 index 0000000..bccd416 --- /dev/null +++ b/include/configs/dvlhost.h @@ -0,0 +1,248 @@ +/* + * (C) Copyright 2009 + * Michael Schwingen, michael@schwingen.org + * + * Configuration settings for the + * dLAN200 AV Wireless G ("dvlhost") board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_IXP425 1 +#define CONFIG_DVLHOST 1 + +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +#define CONFIG_IXP_SERIAL +#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_SYS_LDSCRIPT "board/dvlhost/u-boot.lds" + +/*************************************************************** + * U-boot generic defines start here. + ***************************************************************/ +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Command line configuration. */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ELF +#define CONFIG_PCI +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_PCI_PNP +#define CONFIG_IXP_PCI +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI_ENUM +#endif + +#define CONFIG_BOOTCOMMAND "run boot_flash" +/* enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#if defined(CONFIG_CMD_KGDB) +# define CONFIG_KGDB_BAUDRATE 230400 +/* which serial port to use */ +# define CONFIG_KGDB_SER_INDEX 1 +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END 0x01D80000 + +/* timer clock - 2* OSC_IN system clock */ +#define CONFIG_IXP425_TIMER_CLK 66666666 +#define CONFIG_SYS_HZ 1000 + +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x00010000 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200, 230400 } +#define CONFIG_SERIAL_RTS_ACTIVE 1 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +/* Expansion bus settings */ +#define CONFIG_SYS_EXP_CS0 0xbd113442 + +/* SDRAM settings */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +/* 32MB SDRAM: 2* 8Mx16, CL3 */ +#define CONFIG_SYS_SDR_CONFIG 0x18 +#define PHYS_SDRAM_1_SIZE 0x02000000 +#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x800 +#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 +#define CONFIG_SYS_DRAM_SIZE PHYS_SDRAM_1_SIZE + +/* FLASH organization: one Spansion S29AL032D-04 Flash */ +#define CONFIG_SYS_TEXT_BASE 0x50000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 140 +#define PHYS_FLASH_1 0x50000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } + +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +#define CONFIG_BOARD_SIZE_LIMIT 262144 + +/* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +/* no byte writes on IXP4xx */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +/* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_EMPTY_INFO + +/* Ethernet */ + +/* include IXP4xx NPE support */ +#define CONFIG_IXP4XX_NPE 1 + +#define CONFIG_NET_MULTI 1 +/* NPE0 PHY: MII dLAN200 AVmodule, 100BaseT-FDX fixed */ +#define CONFIG_PHY_ADDR 0x18 +/* NPE1 PHY: MII IP175 switch, port 5 is host port */ +#define CONFIG_PHY1_ADDR 0x05 +/* MII PHY management */ +#define CONFIG_MII 1 +/* fixed-speed powerline modem without standard PHY registers on MII */ +#define CONFIG_MII_NPE0_FIXEDLINK 1 +#define CONFIG_MII_NPE0_SPEED 100 +#define CONFIG_MII_NPE0_FULLDUPLEX 1 +/* fixed-speed switch without standard PHY registers on MII */ +#define CONFIG_MII_NPE1_FIXEDLINK 1 +#define CONFIG_MII_NPE1_SPEED 100 +#define CONFIG_MII_NPE1_FULLDUPLEX 1 + +/* Number of ethernet rx buffers & descriptors */ +#define CONFIG_SYS_RX_ETH_BUFFER 16 +#define CONFIG_RESET_PHY_R 1 +/* ethernet switch connected to MII port */ +#define CONFIG_MII_ETHSWITCH 1 +#define CONFIG_HAS_ETH1 1 + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#undef CONFIG_CMD_NFS + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* + * environment organization: + * one flash sector, embedded in uboot area (bottom bootblock flash) + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) +#define CONFIG_SYS_USE_PPCENV 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "npe_ucode=50040000\0" \ + "ethprime=NPE1\0" \ + "ethrotate=no\0" \ + "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root),\0" \ + "kerneladdr=50050000\0" \ + "kernelfile=dvlhost/uImage\0" \ + "rootfile=dvlhost/rootfs\0" \ + "rootaddr=50170000\0" \ + "loadaddr=10000\0" \ + "updateboot_ser=mw.b 10000 ff 40000;" \ + " loady ${loadaddr};" \ + " run eraseboot writeboot\0" \ + "updateboot_net=mw.b 10000 ff 40000;" \ + " tftp ${loadaddr} dvlhost/u-boot.bin;" \ + " run eraseboot writeboot\0" \ + "eraseboot=protect off 50000000 50003fff;" \ + " protect off 50006000 5003ffff;" \ + " erase 50000000 50003fff;" \ + " erase 50006000 5003ffff\0" \ + "writeboot=cp.b 10000 50000000 4000;" \ + " cp.b 16000 50006000 3a000\0" \ + "updateucode=loady;" \ + " era ${npe_ucode} +${filesize};" \ + " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ + "updateroot=tftp ${loadaddr} ${rootfile};" \ + " era ${rootaddr} +${filesize};" \ + " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ + "updatekern=tftp ${loadaddr} ${kernelfile};" \ + " era ${kerneladdr} +${filesize};" \ + " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ + "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ + " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ + " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ + "boot_flash=run flashargs addtty addeth;" \ + " bootm ${kerneladdr}\0" \ + "boot_net=run netargs addtty addeth;" \ + " tftpboot ${loadaddr} ${kernelfile};" \ + " bootm\0" + +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#endif /* __CONFIG_H */ diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h index 754fc8b..c4b1e65 100644 --- a/include/configs/eb_cpux9k2.h +++ b/include/configs/eb_cpux9k2.h @@ -29,17 +29,17 @@ /*--------------------------------------------------------------------------*/ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -#define CONFIG_EB_CPUX9K2 1 /* on an EP+CPUX9K2 Board */ -#define USE_920T_MMU 1 +#define CONFIG_AT91RM9200 /* It's an Atmel AT91RM9200 SoC */ +#define CONFIG_EB_CPUX9K2 /* on an EP+CPUX9K2 Board */ +#define USE_920T_MMU -#define CONFIG_VERSION_VARIABLE 1 +#define CONFIG_VERSION_VARIABLE #define CONFIG_IDENT_STRING " on EB+CPUx9K2" -#include <asm/arch/hardware.h> /* needed for port definitions */ +#include <asm/hardware.h> /* needed for port definitions */ #define CONFIG_MISC_INIT_R +#define CONFIG_BOARD_EARLY_INIT_F /*--------------------------------------------------------------------------*/ #define CONFIG_SYS_TEXT_BASE 0x00000000 @@ -70,7 +70,7 @@ #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) -#define AT91_SLOW_CLOCK 32768 /* slow clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */ #define CONFIG_CMDLINE_TAG 1 #define CONFIG_SETUP_MEMORY_TAGS 1 @@ -175,8 +175,9 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 } #define CONFIG_BAUDRATE 115200 -#define CONFIG_AT91RM9200_USART -#define CONFIG_DBGU /* define DBGU as console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID 0/* ignored in arm */ /* * network @@ -217,19 +218,19 @@ #define CONFIG_SYS_I2C_INIT_BOARD #define I2C_INIT i2c_init_board(); -#define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr); -#define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder); -#define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0) +#define I2C_ACTIVE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr); +#define I2C_TRISTATE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder); +#define I2C_READ ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0) #define I2C_SDA(bit) \ if (bit) \ - writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \ + writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr); \ else \ - writel(AT91_PMX_AA_TWD, &pio->pioa.codr); + writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr); #define I2C_SCL(bit) \ if (bit) \ - writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \ + writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr); \ else \ - writel(AT91_PMX_AA_TWCK, &pio->pioa.codr); + writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr); #define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED) diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h index 571c3cb..7d3363a 100644 --- a/include/configs/efikamx.h +++ b/include/configs/efikamx.h @@ -38,7 +38,9 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_L2_OFF +#define CONFIG_SYS_TEXT_BASE 0x97800000 + +#define CONFIG_SYS_L2CACHE_OFF /* * Bootloader Components Configuration @@ -47,6 +49,7 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_MMC #define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #undef CONFIG_CMD_IMLS diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h index fb05727..23a2efa 100644 --- a/include/configs/evb4510.h +++ b/include/configs/evb4510.h @@ -43,7 +43,8 @@ #define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */ #define CONFIG_S3C4510B 1 /* it's a S3C4510B chip */ #define CONFIG_EVB4510 1 /* on an EVB4510 Board */ -#define CONFIG_SYS_NO_CP15_CACHE +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF #define CONFIG_USE_IRQ #define CONFIG_STACKSIZE_IRQ (4*1024) diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h index fd39ab4..9412daa 100644 --- a/include/configs/gcplus.h +++ b/include/configs/gcplus.h @@ -49,7 +49,7 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE +#define CONFIG_SYS_DCACHE_OFF #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h new file mode 100644 index 0000000..9779449 --- /dev/null +++ b/include/configs/grasshopper.h @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2011 + * Corscience GmbH & Co.KG, Andreas Bießmann <biessmann@corscience.de> + * + * Configuration settings for the grasshopper (ICnova AP7000) board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __GRASSHOPPER_CONFIG_H +#define __GRASSHOPPER_CONFIG_H + +#include <asm/arch/hardware.h> + +#define CONFIG_AVR32 +#define CONFIG_AT32AP +#define CONFIG_AT32AP7000 + +/* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency + */ +#define CONFIG_SYS_HZ 1000 + +/* + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the + * PLL frequency. + * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz + */ +#define CONFIG_PLL +#define CONFIG_SYS_POWER_MANAGER +#define CONFIG_SYS_OSC0_HZ 20000000 +#define CONFIG_SYS_PLL0_DIV 1 +#define CONFIG_SYS_PLL0_MUL 7 +#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 +/* + * Set the CPU running at: + * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz + */ +#define CONFIG_SYS_CLKDIV_CPU 0 +/* + * Set the HSB running at: + * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz + */ +#define CONFIG_SYS_CLKDIV_HSB 1 +/* + * Set the PBA running at: + * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz + */ +#define CONFIG_SYS_CLKDIV_PBA 2 +/* + * Set the PBB running at: + * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz + */ +#define CONFIG_SYS_CLKDIV_PBB 1 + +/* Reserve VM regions for SDRAM and NOR flash */ +#define CONFIG_SYS_NR_VM_REGIONS 2 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CONFIG_SYS_PLL0_OPT 0x04 + +#define CONFIG_USART_BASE ATMEL_BASE_USART1 +#define CONFIG_USART_ID 1 + +/* User serviceable stuff */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 + +/* + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d" \ + " seconds\n", bootdelay +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * After booting the board for the first time, new ethernet addresses + * should be generated and assigned to the environment variables + * "ethaddr". This is normally done during production. + */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_NET_MULTI + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +/* remove unneeded commands */ +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR + +/* add useful commands */ +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_PROMPT_HUSH_PS2 "~> " +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_ATMEL_USART +#define CONFIG_MACB +#define CONFIG_PORTMUX_PIO +#define CONFIG_SYS_NR_PIOS 5 +#define CONFIG_SYS_HSDRAMC + +#define CONFIG_SYS_DCACHE_LINESZ 32 +#define CONFIG_SYS_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER + +#define CONFIG_SYS_FLASH_BASE 0x00000000 +#define CONFIG_SYS_FLASH_SIZE 0x800000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 135 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_TEXT_BASE 0x00000000 + +#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE +#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE + +#define CONFIG_ENV_IS_IN_FLASH +/* place u-boot env in flash sector after u-boot */ +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_ADDR 0x20000 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + \ + CONFIG_SYS_INTRAM_SIZE) + +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#define CONFIG_SYS_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) +#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP + +#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) +#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __GRASSHOPPER_CONFIG_H */ +/* vim: set ts=8 noet: */ diff --git a/include/configs/harmony.h b/include/configs/harmony.h index 34bd899..89e4911 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -47,4 +47,15 @@ #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ #define CONFIG_BOARD_EARLY_INIT_F + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA2_MMC +#define CONFIG_CMD_MMC + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT #endif /* __CONFIG_H */ diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h deleted file mode 100644 index c56efde..0000000 --- a/include/configs/hcu4.h +++ /dev/null @@ -1,275 +0,0 @@ -/* - *(C) Copyright 2005-2008 Netstal Maschinen AG - * Niklaus Giger (Niklaus.Giger@netstal.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * hcu4.h - configuration for HCU4 board (similar to hcu5.h) - ***********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_HCU4 1 /* Board is HCU4 */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_405GP 1 -#define CONFIG_4xx 1 -#define CONFIG_HOSTNAME hcu4 - -#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 - -/* - * Include common defines/options for all boards produced by Netstal Maschinen - */ -#include "netstal-common.h" - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) -*----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -/* ... with on-chip memory here (4KBytes) */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x00001000 -/* Do not set up locked dcache as init ram. */ -#undef CONFIG_SYS_INIT_DCACHE_CS - -/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* OCM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -/* - * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. - * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. - * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. - * The Linux BASE_BAUD define should match this configuration. - * baseBaud = cpuClock/(uartDivisor*16) - * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, - * set Linux BASE_BAUD to 403200. - */ -#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* Set console baudrate to 9600 */ -#define CONFIG_BAUDRATE 9600 - -/*----------------------------------------------------------------------- - * Flash - *----------------------------------------------------------------------*/ - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* board provides its own flash_init code */ -#define CONFIG_FLASH_CFI_LEGACY 1 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CONFIG_SYS_FLASH_LEGACY_512Kx8 1 - -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ - -#undef CONFIG_ENV_IS_IN_NVRAM -#define CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_ENV_IS_NOWHERE - -#ifdef CONFIG_ENV_IS_IN_EEPROM -/* Put the environment after the SDRAM configuration */ -#define PROM_SIZE 2048 -#define CONFIG_ENV_OFFSET 512 -#define CONFIG_ENV_SIZE (PROM_SIZE-CONFIG_ENV_OFFSET) -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH -/* Put the environment in Flash */ -#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif - -/*----------------------------------------------------------------------- - * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the - * the first internal I2C controller of the PPC440EPx - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SPD_BUS_NUM 0 - -#define CONFIG_IPADDR 172.25.1.14 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_NETSTAL_DEF_ENV \ - CONFIG_NETSTAL_DEF_ENV_POWERPC \ - "" - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SDRAM - -/* SPD EEPROM (sdram speed config) disabled */ -#define CONFIG_SPD_EEPROM 1 -#define SPD_EEPROM_ADDRESS 0x50 - -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_UART | \ - CONFIG_SYS_POST_I2C | \ - CONFIG_SYS_POST_CACHE | \ - CONFIG_SYS_POST_ETHER | \ - CONFIG_SYS_POST_SPR) - -#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 } -#undef CONFIG_LOGBUFFER -#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -#define CONFIG_SYS_EBC_CFG 0x98400000 - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x02005400 -#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ - -#define CONFIG_SYS_EBC_PB1AP 0x03041200 -#define CONFIG_SYS_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */ - -#define CONFIG_SYS_EBC_PB2AP 0x02054500 -#define CONFIG_SYS_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */ - -#define CONFIG_SYS_EBC_PB3AP 0x01840300 -#define CONFIG_SYS_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */ - -#define CONFIG_SYS_EBC_PB4AP 0x01800300 -#define CONFIG_SYS_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */ - -#define CONFIG_SYS_GPIO0_OR 0xF27FFFFF /* GPIO value */ -#define CONFIG_SYS_GPIO0_TCR 0x7FFE0000 /* GPIO value */ -#define CONFIG_SYS_GPIO0_ODR 0x00E897FC /* GPIO value */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */ - -/* Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - - -/* Configuration Port location */ -#define CONFIG_PORT_ADDR 0xF0000500 - -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h deleted file mode 100644 index 0c8fdf5..0000000 --- a/include/configs/hcu5.h +++ /dev/null @@ -1,325 +0,0 @@ -/* - * (C) Copyright 2007-2008 Netstal Maschinen AG - * Niklaus Giger (Niklaus.Giger@netstal.com) - * - * (C) Copyright 2006-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2006 - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * hcu5.h - configuration for HCU5 board (derived from sequoia.h) - ***********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_HCU5 1 /* Board is HCU5 */ -#define CONFIG_440EPX 1 /* Specific PPC440EPx */ -#define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_HOSTNAME hcu5 - -#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 - -/* - * Include common defines/options for all boards produced by Netstal Maschinen - */ -#include "netstal-common.h" - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -#define CONFIG_SYS_TLB_FOR_BOOT_FLASH 3 -#define CONFIG_SYS_BOOT_BASE_ADDR 0xfff00000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ -#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE -#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 -#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 -#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 - -#define CONFIG_SYS_USB2D0_BASE 0xe0000100 -#define CONFIG_SYS_USB_DEVICE 0xe0000000 -#define CONFIG_SYS_USB_HOST 0xe0000400 - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer - *----------------------------------------------------------------------*/ -/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ - -#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ -#define CONFIG_BAUDRATE 115200 - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ - -#undef CONFIG_ENV_IS_IN_NVRAM -#define CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_ENV_IS_IN_EEPROM -#undef CONFIG_ENV_IS_NOWHERE - -#ifdef CONFIG_ENV_IS_IN_EEPROM -/* Put the environment after the SDRAM and bootstrap configuration */ -#define PROM_SIZE 2048 -#define CONFIG_SYS_BOOSTRAP_OPTION_OFFSET 512 -#define CONFIG_ENV_OFFSET (CONFIG_SYS_BOOSTRAP_OPTION_OFFSET + 0x10) -#define CONFIG_ENV_SIZE (PROM_SIZE-CONFIG_ENV_OFFSET) -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH -/* Put the environment in Flash */ -#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#endif - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MBYTES_SDRAM (128) /* 128 MB or 256 MB */ -#define CONFIG_SYS_DDR_CACHED_ADDR 0x50000000 /* setup 2nd TLB cached here */ -#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */ -#define CONFIG_DDR_ECC 1 /* enable ECC */ - -/* Following two definitions must be kept in sync with config.h of vxWorks */ -#define USER_RESERVED_MEM ( 0) /* in kB */ -#define PM_RESERVED_MEM ( 64) /* in kB: pmLib reserved area size */ -#define CONFIG_PRAM ( USER_RESERVED_MEM + PM_RESERVED_MEM ) - -#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ - /* 440EPx errata CHIP 11 */ - -/*----------------------------------------------------------------------- - * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the - * the second internal I2C controller of the PPC440EPx - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SPD_BUS_NUM 1 - -/* Setup some board specific values for the default environment variables */ -#define CONFIG_IPADDR 172.25.1.15 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_NETSTAL_DEF_ENV \ - CONFIG_NETSTAL_DEF_ENV_POWERPC \ - "" - -#define CONFIG_M88E1111_PHY 1 -#define CONFIG_IBM_EMAC4_V4 1 - -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ -#define CONFIG_PHY1_ADDR 2 - -/* USB */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE - -/* Comment this out to enable USB 1.1 device */ -#define USB_2_0_DEVICE - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_USB - -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_UART | \ - CONFIG_SYS_POST_I2C | \ - CONFIG_SYS_POST_CACHE | \ - CONFIG_SYS_POST_FPU | \ - CONFIG_SYS_POST_ETHER | \ - CONFIG_SYS_POST_SPR) - -#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 } -#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ - -#define CONFIG_SUPPORT_VFAT - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------*/ -/* General PCI */ -#define CONFIG_PCI 1 /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr map to CONFIG_SYS_PCI_MEMBASE*/ - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT -#define CONFIG_SYS_PCI_MASTER_INIT - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Flash - *----------------------------------------------------------------------*/ - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* board provides its own flash_init code */ -#define CONFIG_FLASH_CFI_LEGACY 1 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CONFIG_SYS_FLASH_LEGACY_512Kx8 1 - -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS_1 0xC8000000 /* CAN */ -#define CONFIG_SYS_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */ -#define CONFIG_SYS_CPLD CONFIG_SYS_CS_2 -#define CONFIG_SYS_CS_3 0xCE000000 /* CPLD and IMC-Bus Fast */ - -#define CONFIG_SYS_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */ -#define CONFIG_SYS_EBC_PB0AP 0x02005400 -#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* (CONFIG_SYS_FLASH | 0xda000) */ -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ - -/* Memory Bank 1 CAN-Chips initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x02054500 -#define CONFIG_SYS_EBC_PB1CR 0xC8018000 - -/* Memory Bank 2 CPLD/IMC-Bus standard initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x01840300 -#define CONFIG_SYS_EBC_PB2CR 0xCC0BA000 - -/* Memory Bank 3 IMC-Bus fast mode initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x01800300 -#define CONFIG_SYS_EBC_PB3CR 0xCE0BA000 - -/* Memory Bank 4 (not used) initialization */ -#undef CONFIG_SYS_EBC_PB4AP -#undef CONFIG_SYS_EBC_PB4CR - -/* Memory Bank 5 (not used) initialization */ -#undef CONFIG_SYS_EBC_PB5AP -#undef CONFIG_SYS_EBC_PB5CR - -#define HCU_CPLD_VERSION_REGISTER ( CONFIG_SYS_CPLD + 0x0F00000 ) -#define HCU_HW_VERSION_REGISTER ( CONFIG_SYS_CPLD + 0x1400000 ) - -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#ifdef CONFIG_SYS_HUSH_PARSER - #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/igep0020.h b/include/configs/igep0020.h index 5af9bec..b6534e4 100644 --- a/include/configs/igep0020.h +++ b/include/configs/igep0020.h @@ -25,7 +25,6 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ diff --git a/include/configs/igep0030.h b/include/configs/igep0030.h index 92144af..d85e5ae 100644 --- a/include/configs/igep0030.h +++ b/include/configs/igep0030.h @@ -25,7 +25,6 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 4d11f97..a0c0f1b 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -28,6 +28,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <asm/arch/imx-regs.h> + /* High Level Configuration Options */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ #define CONFIG_MX31 1 /* in a mx31 */ @@ -143,6 +145,16 @@ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SYS_TEXT_BASE 0xA0000000 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_GBL_DATA_OFFSET) /*----------------------------------------------------------------------- * FLASH and environment organization diff --git a/include/configs/incaip.h b/include/configs/incaip.h index f2950e8..0e5ad2b 100644 --- a/include/configs/incaip.h +++ b/include/configs/incaip.h @@ -31,6 +31,8 @@ #define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */ #define CONFIG_INCA_IP 1 /* on a INCA-IP Board */ +#define CONFIG_XWAY_SWAP_BYTES + /* * Clock for the MIPS core (MHz) * allowed values: 100000000, 133000000, and 150000000 (default) @@ -39,7 +41,7 @@ #define CONFIG_CPU_CLOCK_RATE 150000000 #endif -#define INFINEON_EBU_BOOTCFG 0x40C4 /* CMULT = 8 */ +#define CONFIG_SYS_XWAY_EBU_BOOTCFG 0x40C4 /* CMULT = 8 */ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 744d65c..2e4b346 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -43,7 +43,7 @@ #define CONFIG_SYS_TEXT_BASE 0x0 /* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE +#define CONFIG_SYS_DCACHE_OFF /* * Hardware drivers diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h index 28d41e2..d6ef3b3 100644 --- a/include/configs/ixdp425.h +++ b/include/configs/ixdp425.h @@ -36,12 +36,19 @@ #define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ #define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ +/* + * select serial console configuration + */ +#define CONFIG_IXP_SERIAL +#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOARD_EARLY_INIT_F 1 + /*************************************************************** * U-boot generic defines start here. ***************************************************************/ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - /* * Size of malloc() pool */ @@ -50,9 +57,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 - - /* * BOOTP options */ @@ -61,38 +65,33 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ +/* Command line configuration. */ #include <config_cmd_default.h> #define CONFIG_CMD_ELF -#define CONFIG_CMD_PCI - #define CONFIG_PCI +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_PCI_PNP #define CONFIG_IXP_PCI -#define CONFIG_NET_MULTI +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI_ENUM #define CONFIG_EEPRO100 +#endif -#define CONFIG_BOOTDELAY 3 -/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b*/ -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.0.21 -#define CONFIG_SERVERIP 192.168.0.148 -#define CONFIG_BOOTCOMMAND "bootm 50040000" -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" -#define CONFIG_CMDLINE_TAG +#define CONFIG_BOOTCOMMAND "run boot_flash" +/* enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif -/* - * Miscellaneous configurable options - */ +/* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ @@ -103,10 +102,13 @@ #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */ +/* timer clock - 2* OSC_IN system clock */ +#define CONFIG_IXP425_TIMER_CLK 66666666 +#define CONFIG_SYS_HZ 1000 + +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x00010000 -#define CONFIG_SYS_HZ 3333333 /* spec says 66.666 MHz, but it appears to be 33 */ - /* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* @@ -115,10 +117,6 @@ * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif /*************************************************************** * Platform/Board specific defines start here. @@ -128,72 +126,143 @@ * Hardware drivers */ - -/* - * select serial console configuration - */ -#define CONFIG_IXP_SERIAL -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ - /* * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ +#define CONFIG_SYS_TEXT_BASE 0x50000000 #define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ #define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ #define PHYS_FLASH_BANK_SIZE 0x00800000 /* 8 MB Banks */ #define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ -#define CONFIG_SYS_DRAM_BASE 0x00000000 -#define CONFIG_SYS_DRAM_SIZE 0x01000000 - #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CONFIG_BOARD_SIZE_LIMIT 262144 -/* - * Expansion bus settings - */ -#define CONFIG_SYS_EXP_CS0 0xbcd23c42 +/* Expansion bus settings */ +#define CONFIG_SYS_EXP_CS0 0xbcd23c42 + +/* SDRAM settings */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* - * SDRAM settings - */ #define CONFIG_SYS_SDR_CONFIG 0xd #define CONFIG_SYS_SDR_MODE_CONFIG 0x1 #define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a /* - * GPIO settings - */ - -/* - * FLASH and environment organization - */ -/* * FLASH and environment organization */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ - #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ +/* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +/* no byte writes on IXP4xx */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +/* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_EMPTY_INFO + +/* Ethernet */ + +/* include IXP4xx NPE support */ +#define CONFIG_IXP4XX_NPE 1 +#define CONFIG_NET_MULTI 1 +/* NPE0 PHY address */ +#define CONFIG_PHY_ADDR 0 +/* NPE1 PHY address (HW Release E only) */ +#define CONFIG_PHY1_ADDR 1 +/* MII PHY management */ +#define CONFIG_MII 1 +/* Number of ethernet rx buffers & descriptors */ +#define CONFIG_SYS_RX_ETH_BUFFER 16 + +#define CONFIG_HAS_ETH1 1 + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#undef CONFIG_CMD_NFS + +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "npe_ucode=50060000\0" \ + "mtd=IXP4XX-Flash.0:256k(uboot),128k(env),128k(ucode),2048k(linux),-(root)\0" \ + "kerneladdr=50080000\0" \ + "kernelfile=ixdp425/uImage\0" \ + "rootfile=ixdp425/rootfs\0" \ + "rootaddr=50280000\0" \ + "loadaddr=10000\0" \ + "updateboot_ser=mw.b 10000 ff 40000;" \ + " loady ${loadaddr};" \ + " run eraseboot writeboot\0" \ + "updateboot_net=mw.b 10000 ff 40000;" \ + " tftp ${loadaddr} ixdp425/u-boot.bin;" \ + " run eraseboot writeboot\0" \ + "eraseboot=protect off 50000000 5003ffff;" \ + " erase 50000000 5003ffff\0" \ + "writeboot=cp.b 10000 50000000 ${filesize}\0" \ + "updateucode=loady;" \ + " era ${npe_ucode} +${filesize};" \ + " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ + "updateroot=tftp ${loadaddr} ${rootfile};" \ + " era ${rootaddr} +${filesize};" \ + " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ + "updatekern=tftp ${loadaddr} ${kernelfile};" \ + " era ${kerneladdr} +${filesize};" \ + " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ + "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \ + " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \ + " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ + "boot_flash=run flashargs addtty addeth;" \ + " bootm ${kerneladdr}\0" \ + "boot_net=run netargs addtty addeth;" \ + " tftpboot ${loadaddr} ${kernelfile};" \ + " bootm\0" + +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +/* + * GPIO settings + */ +#define CONFIG_SYS_GPIO_UTOPIA_GPIO1 0 +#define CONFIG_SYS_GPIO_UTOPIA_IRQ_N 1 +#define CONFIG_SYS_GPIO_HSS1_IRQ_N 2 +#define CONFIG_SYS_GPIO_HSS0_IRQ_N 3 +#define CONFIG_SYS_GPIO_ETH0_IRQ_N 4 +#define CONFIG_SYS_GPIO_ETH1_IRQ_N 5 +#define CONFIG_SYS_GPIO_I2C_SCL 6 +#define CONFIG_SYS_GPIO_I2C_SDA 7 +#define CONFIG_SYS_GPIO_PCI_INTD_N 8 +#define CONFIG_SYS_GPIO_PCI_INTC_N 9 +#define CONFIG_SYS_GPIO_PCI_INTB_N 10 +#define CONFIG_SYS_GPIO_PCI_INTA_N 11 +#define CONFIG_SYS_GPIO_UTOPIA_GPIO0 12 +#define CONFIG_SYS_GPIO_PCI_RESET_N 13 +#define CONFIG_SYS_GPIO_PCI_CLK 14 +#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 + #endif /* __CONFIG_H */ diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h index 637fd7d..3de0013 100644 --- a/include/configs/ixdpg425.h +++ b/include/configs/ixdpg425.h @@ -53,9 +53,6 @@ /* * Misc configuration options */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */ -#define CONFIG_TIMER_IRQ #define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */ #define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */ @@ -115,6 +112,7 @@ #define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ #define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */ +#define CONFIG_IXP425_TIMER_CLK 66666666 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ /* valid baudrates */ @@ -179,6 +177,8 @@ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ +#define CONFIG_SYS_TEXT_BASE 0x50000000 + #define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ #define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ @@ -248,4 +248,9 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 32 +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + #endif /* __CONFIG_H */ diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h index c119392..0375732 100644 --- a/include/configs/jadecpu.h +++ b/include/configs/jadecpu.h @@ -29,17 +29,21 @@ #define CONFIG_MB86R0x #define CONFIG_MB86R0x_IOCLK get_bus_freq(0) #define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_TEXT_BASE 0x10000000 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define CONFIG_USE_ARCH_MEMCPY +#define CONFIG_USE_ARCH_MEMSET + /* * Environment settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "gs_fast_boot=setenv bootdelay 5\0" \ "gs_slow_boot=setenv bootdelay 10\0" \ - "bootcmd=mw.l 0x40000000 0 1024; usb start;" \ + "bootcmd=dcache off; mw.l 0x40000000 0 1024; usb start;" \ "fatls usb 0; fatload usb 0 0x40000000 jadecpu-init.bin;" \ "bootelf 0x40000000\0" \ "" @@ -122,13 +126,14 @@ #undef CONFIG_CMD_NFS #undef CONFIG_CMD_XIMG -#define CONFIG_CMD_BMP 1 -#define CONFIG_CMD_CAN 1 -#define CONFIG_CMD_DHCP 1 -#define CONFIG_CMD_ELF 1 -#define CONFIG_CMD_FAT 1 -#define CONFIG_CMD_PING 1 -#define CONFIG_CMD_USB 1 +#define CONFIG_CMD_BMP +#define CONFIG_CMD_CAN +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_CACHE #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " @@ -196,7 +201,8 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000) +#define CONFIG_SYS_MALLOC_LEN (10 << 20) +#define CONFIG_SYS_MEM_TOP_HIDE (4 << 20) #define CONFIG_STACKSIZE (32*1024) /* regular stack */ diff --git a/include/configs/jornada.h b/include/configs/jornada.h index 41b09aa..84ad2d8 100644 --- a/include/configs/jornada.h +++ b/include/configs/jornada.h @@ -32,7 +32,7 @@ #define CONFIG_SYS_TEXT_BASE 0xC1F00000 /* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE +#define CONFIG_SYS_DCACHE_OFF #undef CONFIG_USE_IRQ /* Console setting */ diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 70c9dad..bc1edaf 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -83,27 +83,11 @@ #define CONFIG_SYS_LOADS_BAUD_CHANGE #define CONFIG_SYS_BOARD_DRAM_INIT /* Used board specific dram_init */ -/* - * How to get access to the slot ID. Put this here to make it easy - * to modify in a centralized location. This is used in the HDLC - * driver to set the MAC. -*/ -#define CONFIG_CHECK_ETHERNET_PRESENT -#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ -#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ - #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_MAX_I2C_BUS 1 #define CONFIG_SYS_I2C_INIT_BOARD #define CONFIG_I2C_MUX -/* EEprom support */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - /* Support the IVM EEprom */ #define CONFIG_SYS_IVM_EEPROM_ADR 0x50 #define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400 @@ -128,11 +112,12 @@ #define CONFIG_MTD_DEVICE #define CONFIG_MTD_CONCAT -/* common powerpc specific env settings */ +#define CONFIG_CMD_CRAMFS +#define CONFIG_CRAMFS_CMDLINE + #ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS #define CONFIG_KM_DEF_ENV_BOOTPARAMS \ - "bootparams=empty\0" \ - "initial_boot_bank=0\0" + "actual_bank=0\0" #endif #ifndef CONFIG_KM_DEF_NETDEV @@ -151,98 +136,49 @@ #define str(s) #s /* - * bootrunner - * - run all commands in 'subbootcmds' - * - on error, stop running the remaing commands - */ -#define CONFIG_KM_DEF_ENV_BOOTRUNNER \ - "bootrunner=" \ - "break=0; " \ - "for subbootcmd in ${subbootcmds}; do " \ - "if test ${break} -eq 0; then; " \ - "print ${subbootcmd}; " \ - "run ${subbootcmd} || break=1; " \ - "fi; " \ - "done\0" \ - "" - -/* * boottargets - * - set 'subbootcmds' for the bootrunner + * - set 'subbootcmds' * - set 'bootcmd' and 'altbootcmd' * available targets: * - 'release': for a standalone system kernel/rootfs from flash - * - * - 'commonargs': bootargs common to all targets */ #define CONFIG_KM_DEF_ENV_BOOTTARGETS \ - "commonargs=" \ - "addip " \ - "addtty " \ - "addmem " \ - "addinit " \ - "addvar " \ - "addmtdparts " \ - "addbootcount " \ - "\0" \ - "release=" \ - "setenv actual_bank ${initial_boot_bank} && " \ - "setenv subbootcmds \"" \ - "checkboardid " \ - "ubiattach ubicopy " \ - "cramfsloadfdt cramfsloadkernel " \ - "flashargs ${commonargs} " \ - "addpanic boot " \ - "\" && " \ - "setenv bootcmd \'" \ - "run actual bootrunner; reset" \ - "\' && " \ - "setenv altbootcmd \'" \ - "run backup bootrunner; reset" \ - "\' && " \ - "saveenv && saveenv && " \ - "reset\0" \ - "debug_env=" \ - "tftp 200000 " CONFIG_KM_ARCH_DBG_FILE " && " \ + "subbootcmds=ubiattach ubicopy cramfsloadfdt cramfsloadkernel " \ + "flashargs add_default addpanic boot\0" \ + "develop=" \ + "tftp 200000 scripts/develop-${arch}.txt && " \ "env import -t 200000 ${filesize} && " \ - "run debug_env_common\0" \ + "run setup_debug_env\0" \ + "ramfs=" \ + "tftp 200000 scripts/ramfs-${arch}.txt && " \ + "env import -t 200000 ${filesize} && " \ + "run setup_debug_env\0" \ "" /* * bootargs * - modify 'bootargs' * - * - 'addip': add ip configuration - * - 'addmem': limit kernel memory mem= + * - 'add_default': default bootargs common for all arm/ppc boards * - 'addpanic': add kernel panic options - * - 'addtty': add console=... - * - 'addvar': add phram device for /var * - 'flashargs': defaults arguments for flash base boot * - * processor specific settings - * - 'addbootcount': add boot counter - * - 'addmtdparts': add mtd partition information */ #define CONFIG_KM_DEF_ENV_BOOTARGS \ - "addinit=" \ - "setenv bootargs ${bootargs} init=${init}\0" \ - "addip=" \ + "add_default=" \ "setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off\0" \ - "addmem=" \ - "setenv bootargs ${bootargs} mem=${pnvramaddr}\0" \ + ":${hostname}:${netdev}:off3" \ + " console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}" \ + " mem=${pnvramaddr} init=${init}" \ + " phram.phram=phvar,${varaddr}," xstr(CONFIG_KM_PHRAM) \ + " ubi.mtd=" CONFIG_KM_UBI_LINUX_MTD_NAME " " \ + CONFIG_KM_DEF_BOOT_ARGS_CPU \ + "\0" \ "addpanic=" \ "setenv bootargs ${bootargs} panic=1 panic_on_oops=1\0" \ - "addtty=" \ - "setenv bootargs ${bootargs}" \ - " console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}\0" \ - "addvar=" \ - "setenv bootargs ${bootargs} phram.phram=phvar," \ - "${varaddr}," xstr(CONFIG_KM_PHRAM) "\0" \ "flashargs=" \ "setenv bootargs " \ - "ubi.mtd=" CONFIG_KM_UBI_LINUX_MTD_NAME " " \ "root=mtdblock:rootfs${boot_bank} " \ "rootfstype=squashfs ro\0" \ "" @@ -261,9 +197,7 @@ */ #define CONFIG_KM_DEF_ENV_FLASH_BOOT \ "cramfsaddr=" xstr(CONFIG_KM_CRAMFS_ADDR) "\0" \ - "cramfsloadkernel=" \ - "cramfsload ${kernel_addr_r} uImage && " \ - "setenv actual_kernel_addr ${kernel_addr_r}\0" \ + "cramfsloadkernel=cramfsload ${load_addr_r} uImage\0" \ "ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME "\0" \ "ubicopy=ubi read "xstr(CONFIG_KM_CRAMFS_ADDR) \ " bootfs${boot_bank}\0" \ @@ -276,15 +210,11 @@ * - 'default': setup default environment */ #define CONFIG_KM_DEF_ENV_CONSTANTS \ - "actual=setenv boot_bank ${actual_bank}\0" \ - "backup=setenv boot_bank ${backup_bank}\0" \ - "actual_bank=${initial_boot_bank}\0" \ "backup_bank=0\0" \ - "default=" \ - "setenv default 'run newenv; reset' && " \ - "run release && saveenv; reset\0" \ - "checkboardid=km_checkbidhwk\0" \ + "release=run newenv; reset\0" \ "pnvramsize=" xstr(CONFIG_KM_PNVRAM) "\0" \ + "testbootcmd=setenv boot_bank ${test_bank}; " \ + "run ${subbootcmds}; reset\0" \ "" #ifndef CONFIG_KM_DEF_ENV @@ -292,24 +222,26 @@ CONFIG_KM_DEF_ENV_BOOTPARAMS \ CONFIG_KM_DEF_NETDEV \ CONFIG_KM_DEF_ENV_CPU \ - CONFIG_KM_DEF_ENV_BOOTRUNNER \ CONFIG_KM_DEF_ENV_BOOTTARGETS \ CONFIG_KM_DEF_ENV_BOOTARGS \ CONFIG_KM_DEF_ENV_FLASH_BOOT \ CONFIG_KM_DEF_ENV_CONSTANTS \ "altbootcmd=run bootcmd\0" \ - "bootcmd=run default\0" \ + "bootcmd=km_checkbidhwk && " \ + " setenv bootcmd \'setenv boot_bank ${actual_bank}; " \ + "run ${subbootcmds}; reset\' && " \ + "setenv altbootcmd \'setenv boot_bank ${backup_bank}; " \ + "run ${subbootcmds}; reset\' && " \ + "saveenv && saveenv && boot\0" \ "bootlimit=2\0" \ "init=/sbin/init-overlay.sh\0" \ - "kernel_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \ - "load=tftpboot ${u-boot_addr_r} ${u-boot}\0" \ + "load_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \ + "load=tftpboot ${load_addr_r} ${u-boot}\0" \ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ "stderr=serial\0" \ "stdin=serial\0" \ "stdout=serial\0" \ - "u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ - "u-boot_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \ "" #endif /* CONFIG_KM_DEF_ENV */ diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index d6db8d7..506755b 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -29,6 +29,12 @@ #define CONFIG_CMD_DTT #define CONFIG_JFFS2_CMDLINE +/* EEprom support 24C08, 24C16, 24C64 */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 Byte write page */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + #define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */ #define CONFIG_FLASH_CFI_MTD @@ -66,23 +72,22 @@ #define CONFIG_KM_KERNEL_ADDR 0x400000 /* 3968Kbytes */ #define CONFIG_KM_FDT_ADDR 0x7E0000 /* 128Kbytes */ +/* architecture specific default bootargs */ +#define CONFIG_KM_DEF_BOOT_ARGS_CPU "" + #define CONFIG_KM_DEF_ENV_CPU \ - "addbootcount=true\0" \ - "addmtdparts=true\0" \ - "boot=bootm ${actual_kernel_addr} - ${actual_fdt_addr}\0" \ + "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ "cramfsloadfdt=" \ "cramfsload ${fdt_addr_r} " \ - "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb && " \ - "setenv actual_fdt_addr ${fdt_addr_r}\0" \ + "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ "fdt_addr_r=" xstr(CONFIG_KM_FDT_ADDR) "\0" \ + "u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ "update=" \ "protect off " xstr(BOOTFLASH_START) " +${filesize} && "\ "erase " xstr(BOOTFLASH_START) " +${filesize} && " \ - "cp.b ${u-boot_addr_r} " xstr(BOOTFLASH_START) \ + "cp.b ${load_addr_r} " xstr(BOOTFLASH_START) \ " ${filesize} && " \ "protect on " xstr(BOOTFLASH_START) " +${filesize}\0" \ "" -#define CONFIG_KM_ARCH_DBG_FILE "scripts/debug-ppc-env.txt" - #endif /* __CONFIG_KEYMILE_POWERPC_H */ diff --git a/include/configs/km/km82xx-common.h b/include/configs/km/km82xx-common.h index 446c1d0..0360cd3 100644 --- a/include/configs/km/km82xx-common.h +++ b/include/configs/km/km82xx-common.h @@ -87,7 +87,7 @@ "newenv=" \ "prot off 0xFE0C0000 +0x40000 && " \ "era 0xFE0C0000 +0x40000\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ + "arch=ppc_82xx\0" \ "" #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE @@ -139,6 +139,13 @@ } while (0) #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#ifndef __ASSEMBLY__ +void set_sda(int state); +void set_scl(int state); +int get_sda(void); +int get_scl(void); +#endif + /* I2C SYSMON (LM75, AD7414 is almost compatible) */ #define CONFIG_DTT_LM75 /* ON Semi's LM75 */ #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ diff --git a/include/configs/km/km8321-common.h b/include/configs/km/km8321-common.h index 6fab45e..902ae26 100644 --- a/include/configs/km/km8321-common.h +++ b/include/configs/km/km8321-common.h @@ -33,8 +33,7 @@ #define CONFIG_MPC832x /* MPC832x CPU specific */ #define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ -#define CONFIG_KM_DEF_ROOTPATH \ - "rootpath=/opt/eldk/ppc_8xx\0" +#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" /* include common defines/options for all 83xx Keymile boards */ #include "km83xx-common.h" diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h index 85b6ed2..2b1a84a 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km/km83xx-common.h @@ -302,14 +302,13 @@ #define CONFIG_KM_DEF_ENV "km-common=empty\0" #endif -#ifndef CONFIG_KM_DEF_ROOTPATH -#define CONFIG_KM_DEF_ROOTPATH \ - "rootpath=/opt/eldk/ppc_82xx\0" +#ifndef CONFIG_KM_DEF_ARCH +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ROOTPATH \ + CONFIG_KM_DEF_ARCH \ "dtt_bus=pca9547:70:a\0" \ "EEprom_ivm=pca9547:70:9\0" \ "newenv=" \ diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 20ee6ea..2e3b182 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -40,7 +40,6 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_MARVELL -#define CONFIG_ARM926EJS /* Basic Architecture */ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ #define CONFIG_KIRKWOOD /* SOC Family Name */ #define CONFIG_KW88F6281 /* SOC Name */ @@ -49,8 +48,13 @@ /* include common defines/options for all Keymile boards */ #include "keymile-common.h" +#define CONFIG_CMD_NAND +#define CONFIG_CMD_SF +#define CONFIG_SOFT_I2C /* I2C bit-banged */ + +#include "asm/arch/config.h" + #define CONFIG_SYS_TEXT_BASE 0x04000000 /* code address after reloc */ -#define CONFIG_ENV_SIZE (128 << 10) /* NAND chip block size */ #define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ #define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ @@ -63,24 +67,18 @@ #define CONFIG_KM_CRAMFS_ADDR 0x2400000 #define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 4096KBytes */ +/* architecture specific default bootargs */ +#define CONFIG_KM_DEF_BOOT_ARGS_CPU \ + "bootcountaddr=${bootcountaddr} ${mtdparts}" + #define CONFIG_KM_DEF_ENV_CPU \ - "addbootcount=" \ - "setenv bootargs ${bootargs} " \ - "bootcountaddr=${bootcountaddr}\0" \ - "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "boot=bootm ${actual_kernel_addr} - -\0" \ + "boot=bootm ${load_addr_r} - -\0" \ "cramfsloadfdt=true\0" \ + "u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.kwb\0" \ CONFIG_KM_DEF_ENV_UPDATE \ "" -#define CONFIG_KM_ARCH_DBG_FILE "scripts/debug-arm-env.txt" - -#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#undef CONFIG_KIRKWOOD_PCIE_INIT /* Disable PCIE Port0 for kernel */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ - #define CONFIG_MISC_INIT_R /* @@ -116,7 +114,6 @@ */ #define CONFIG_CMD_ELF #define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_NAND #define CONFIG_CMD_NFS /* @@ -131,8 +128,6 @@ */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 -#define CONFIG_NAND_KIRKWOOD -#define CONFIG_SYS_NAND_BASE 0xd8000000 #define BOOTFLASH_START 0x0 @@ -175,8 +170,6 @@ /* * I2C related stuff */ -#define CONFIG_SOFT_I2C /* I2C bit-banged */ - #define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */ #if defined(CONFIG_SOFT_I2C) #ifndef __ASSEMBLY__ @@ -200,10 +193,14 @@ int get_scl(void); #define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */ #define I2C_SOFT_DECLARATIONS -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 #endif +/* EEprom support 24C128, 24C256 valid for environment eeprom */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 Byte write page */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 @@ -215,24 +212,16 @@ int get_scl(void); #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_EEPROM_WREN #define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ -#undef CONFIG_ENV_SIZE #define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) -#define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0" +#define CONFIG_I2C_ENV_EEPROM_BUS KM_ENV_BUS "\0" /* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#define CONFIG_CMD_SF - #define CONFIG_SPI_FLASH -#define CONFIG_HARD_SPI -#define CONFIG_KIRKWOOD_SPI #define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50Mhz */ #define FLASH_GPIO_PIN 0x00010000 @@ -245,7 +234,7 @@ int get_scl(void); #define CONFIG_KM_DEF_ENV_UPDATE \ "update=" \ "spi on;sf probe 0;sf erase 0 50000;" \ - "sf write ${u-boot_addr_r} 0 ${filesize};" \ + "sf write ${load_addr_r} 0 ${filesize};" \ "spi off\0" /* @@ -259,7 +248,7 @@ int get_scl(void); " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ - "rootpath=/opt/eldk/arm\0" \ + "arch=arm\0" \ "EEprom_ivm=" KM_IVM_BUS "\0" \ "" @@ -272,8 +261,6 @@ int get_scl(void); /* additions for new relocation code, must be added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* Kirkwood has 2k of Security SRAM, use it for SP */ -#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 /* Do early setups now in board_init_f() */ #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/suen3.h b/include/configs/km_kirkwood.h index 0f1b11e..e51b270 100644 --- a/include/configs/suen3.h +++ b/include/configs/km_kirkwood.h @@ -6,6 +6,9 @@ * (C) Copyright 2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * + * (C) Copyright 2011 + * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.de + * * See file CREDITS for list of people who contributed to this * project. * @@ -30,8 +33,8 @@ * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ -#ifndef _CONFIG_SUEN3_H -#define _CONFIG_SUEN3_H +#ifndef _CONFIG_KM_KIRKWOOD_H +#define _CONFIG_KM_KIRKWOOD_H /* include common defines/options for all arm based Keymile boards */ #include "km/km_arm.h" @@ -39,11 +42,16 @@ /* * Version number information */ -#define CONFIG_IDENT_STRING "\nKeymile SUEN3" +#ifdef CONFIG_KM_DISABLE_PCI +#define CONFIG_IDENT_STRING "\nKeymile Kirkwood" +#undef CONFIG_KIRKWOOD_PCIE_INIT +#else +#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" +#endif -#define CONFIG_HOSTNAME suen3 +#define CONFIG_HOSTNAME km_kirkwood #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ #define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ -#endif /* _CONFIG_SUEN3_H */ +#endif /* _CONFIG_KM_KIRKWOOD */ diff --git a/include/configs/lart.h b/include/configs/lart.h index 795cf34..7316b23 100644 --- a/include/configs/lart.h +++ b/include/configs/lart.h @@ -36,7 +36,7 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE +#define CONFIG_SYS_DCACHE_OFF /* * Size of malloc() pool diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index b7d53b6..b6ee919 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -47,7 +47,7 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE +#define CONFIG_SYS_DCACHE_OFF /* * Size of malloc() pool diff --git a/include/configs/mcu25.h b/include/configs/mcu25.h deleted file mode 100644 index a162291..0000000 --- a/include/configs/mcu25.h +++ /dev/null @@ -1,281 +0,0 @@ -/* - *(C) Copyright 2005-2007 Netstal Maschinen AG - * Niklaus Giger (Niklaus.Giger@netstal.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * mcu25.h - configuration for MCU25 board (similar to hcu4.h) - ***********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_MCU25 1 /* Board is MCU25 */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_405GP 1 -#define CONFIG_4xx 1 -#define CONFIG_HOSTNAME mcu25 - -#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 - -/* - * Include common defines/options for all boards produced by Netstal Maschinen - */ -#include "netstal-common.h" - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) -*----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -/* ... with on-chip memory here (4KBytes) */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x00001000 -/* Do not set up locked dcache as init ram. */ -#undef CONFIG_SYS_INIT_DCACHE_CS - -/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* OCM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -/* - * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. - * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. - * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. - * The Linux BASE_BAUD define should match this configuration. - * baseBaud = cpuClock/(uartDivisor*16) - * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, - * set Linux BASE_BAUD to 403200. - */ -#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* Set console baudrate to 9600 */ -#define CONFIG_BAUDRATE 9600 - -/*----------------------------------------------------------------------- - * Flash - *----------------------------------------------------------------------*/ - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* board provides its own flash_init code */ -#define CONFIG_FLASH_CFI_LEGACY 1 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CONFIG_SYS_FLASH_LEGACY_512Kx8 1 - -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ - -#undef CONFIG_ENV_IS_IN_NVRAM -#define CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_ENV_IS_NOWHERE - -#ifdef CONFIG_ENV_IS_IN_EEPROM -/* Put the environment after the SDRAM configuration */ -#define PROM_SIZE 2048 -#define CONFIG_ENV_OFFSET 512 -#define CONFIG_ENV_SIZE (PROM_SIZE-CONFIG_ENV_OFFSET) -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH -/* Put the environment in Flash */ -#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif - -/*----------------------------------------------------------------------- - * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the - * the first internal I2C controller of the PPC440EPx - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SPD_BUS_NUM 0 - -/* Setup some board specific values for the default environment variables */ -#define CONFIG_IPADDR 172.25.1.25 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_NETSTAL_DEF_ENV \ - CONFIG_NETSTAL_DEF_ENV_POWERPC \ - "" - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SDRAM - -/* SPD EEPROM (sdram speed config) disabled */ -#define CONFIG_SPD_EEPROM 1 -#define SPD_EEPROM_ADDRESS 0x50 - -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_UART | \ - CONFIG_SYS_POST_I2C | \ - CONFIG_SYS_POST_CACHE | \ - CONFIG_SYS_POST_ETHER | \ - CONFIG_SYS_POST_SPR) - -#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 } -#undef CONFIG_LOGBUFFER -#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -#define CONFIG_SYS_EBC_CFG 0x98400000 - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x02005400 -#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit*/ - -#define CONFIG_SYS_EBC_PB1AP 0x03041200 -#define CONFIG_SYS_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */ - -#define CONFIG_SYS_EBC_PB2AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */ -#define CONFIG_SYS_EBC_PB2CR 0x7A09A000u - -#define CONFIG_SYS_EBC_PB3AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */ -#define CONFIG_SYS_EBC_PB3CR 0x7B09A000u - -#define CONFIG_SYS_EBC_PB4AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */ -#define CONFIG_SYS_EBC_PB4CR 0x7C09A000u - -#define CONFIG_SYS_EBC_PB5AP 0x00800200u -#define CONFIG_SYS_EBC_PB5CR 0x7D81A000u - -#define CONFIG_SYS_EBC_PB6AP 0x01040200u -#define CONFIG_SYS_EBC_PB6CR 0x7D91A000u - -#define CONFIG_SYS_GPIO0_OR 0x087FFFFF /* GPIO value */ -#define CONFIG_SYS_GPIO0_TCR 0x7FFF8000 /* GPIO value */ -#define CONFIG_SYS_GPIO0_ODR 0xFFFF0000 /* GPIO value */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - - -/* Configuration Port location */ -#define CONFIG_PORT_ADDR 0xF0000500 - -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/mgcoge3un.h b/include/configs/mgcoge3un.h index 6d56d7d..ac01a31 100644 --- a/include/configs/mgcoge3un.h +++ b/include/configs/mgcoge3un.h @@ -48,6 +48,7 @@ #define KM_ENV_BUS "pca9547:70:d" /* I2C2 (Mux-Port 5)*/ /* we use a new RAM type on mgcoge3un board */ +#undef CONFIG_SYS_KWD_CONFIG #define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg /* @@ -75,4 +76,9 @@ MVGBE_SET_GMII_SPEED_TO_10_100 |\ MVGBE_SET_MII_SPEED_TO_100) +/* + * PCIe port not used on mgcoge3un + */ +#undef CONFIG_KIRKWOOD_PCIE_INIT + #endif /* _CONFIG_MGCOGE3UN_H */ diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h index 166da6c..7b68ec5 100644 --- a/include/configs/mx1ads.h +++ b/include/configs/mx1ads.h @@ -156,6 +156,16 @@ #define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */ #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define CONFIG_SYS_TEXT_BASE 0x10000000 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x000FFFFF +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_GBL_DATA_OFFSET) + #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */ #define CONFIG_SYS_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */ #define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h index 1632ce8..ddbc65a 100644 --- a/include/configs/mx1fs2.h +++ b/include/configs/mx1fs2.h @@ -88,7 +88,6 @@ #define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ #define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ #define CONFIG_INITRD_TAG 1 /* send initrd params */ -#undef CONFIG_VFD /* do not send framebuffer setup */ /* * Malloc pool need to host env + 128 Kb reserve for other allocations. diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index ba1e187..35ceacd 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -88,6 +88,7 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP #define CONFIG_CMD_SPI #define CONFIG_CMD_DATE #define CONFIG_CMD_NAND @@ -161,8 +162,10 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_GBL_DATA_OFFSET) /*----------------------------------------------------------------------- * FLASH and environment organization diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 207b20c..fd42afc 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -35,7 +35,7 @@ #define CONFIG_SYS_TEXT_BASE 0x97800000 -#define CONFIG_L2_OFF +#define CONFIG_SYS_L2CACHE_OFF #include <asm/arch/imx-regs.h> /* diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h new file mode 100644 index 0000000..c872510 --- /dev/null +++ b/include/configs/mx53ard.h @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX53ARD Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MX53 + +#define CONFIG_SYS_MX5_HCLK 24000000 +#define CONFIG_SYS_MX5_CLK32 32768 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_L2_OFF + +#include <asm/arch/imx-regs.h> + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX53_UART1 + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_MX53_PORT2 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 2 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* Eth Configs */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI +#define CONFIG_MII +#define CONFIG_MII_GASKET +#define CONFIG_DISCOVER_PHY + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/* Command definition */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "smc911x" + +/*Support LAN9217*/ +#define CONFIG_SMC911X +#define CONFIG_SMC911X_16_BIT +#define CONFIG_SMC911X_BASE CS1_BASE_ADDR + +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ +#define CONFIG_SYS_TEXT_BASE 0x77800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p3 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm\0" \ + "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "dhcp ${uimage}; bootm\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "MX53ARD U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x70000000 +#define CONFIG_SYS_MEMTEST_END 0x70010000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_CMDLINE_EDITING + +/* Stack sizes */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) +#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_OF_LIBFDT + +#define MX53ARD_CS1GCR1 (CSEN | DSZ(2)) +#define MX53ARD_CS1RCR1 (RCSN(2) | OEN (1) | RWSC(22)) +#define MX53ARD_CS1RCR2 RBEN(2) +#define MX53ARD_CS1WCR1 (WCSN(2) | WEN(2) | WBEN(2) | WWSC(22)) + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 78122a7..5f54035 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -29,7 +29,7 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_L2_OFF +#define CONFIG_SYS_L2CACHE_OFF #include <asm/arch/imx-regs.h> diff --git a/include/configs/netspace_v2.h b/include/configs/netspace_v2.h new file mode 100644 index 0000000..82a1233 --- /dev/null +++ b/include/configs/netspace_v2.h @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CONFIG_NETSPACE_V2_H +#define _CONFIG_NETSPACE_V2_H + +/* + * Machine number definition + */ +#if defined(CONFIG_INETSPACE_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_INETSPACE_V2 +#define CONFIG_IDENT_STRING " IS v2" +#elif defined(CONFIG_NETSPACE_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2 +#define CONFIG_IDENT_STRING " NS v2" +#elif defined(CONFIG_NETSPACE_MAX_V2) +#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2 +#define CONFIG_IDENT_STRING " NS Max v2" +#else +#error "Unknown board" +#endif + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SOC Family Name */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include <config_cmd_default.h> +#define CONFIG_CMD_ENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_SF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_USB + +/* + * Core clock definition. + */ +#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#define CONFIG_NR_DRAM_BANKS 2 +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ +#undef CONFIG_RBTREE +#undef CONFIG_ENV_SPI_MAX_HZ +#undef CONFIG_SYS_IDE_MAXBUS +#undef CONFIG_SYS_IDE_MAXDEVICE +#undef CONFIG_SYS_PROMPT +#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */ +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 +#define CONFIG_SYS_PROMPT "ns2> " + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_NETCONSOLE +#endif + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +/* Network Space Max v2 use 2 SATA ports */ +#ifdef CONFIG_NETSPACE_MAX_V2 +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif +#endif + +/* + * Enable GPI0 support + */ +#define CONFIG_KIRKWOOD_GPIO + +/* + * File systems support + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Console configuration + */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* + * Enable device tree support + */ +#define CONFIG_OF_LIBFDT + +/* + * Environment variables configurations + */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64KB */ +#define CONFIG_ENV_SIZE 0x1000 /* 4KB */ +#define CONFIG_ENV_ADDR 0x70000 +#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTARGS "console=ttyS0,115200" + +#define CONFIG_BOOTCOMMAND \ + "dhcp && run netconsole; " \ + "if run usbload || run diskload; then bootm; fi" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "bootfile=uImage\0" \ + "loadaddr=0x800000\0" \ + "autoload=no\0" \ + "netconsole=" \ + "set stdin $stdin,nc; " \ + "set stdout $stdout,nc; " \ + "set stderr $stderr,nc;\0" \ + "diskload=ide reset && " \ + "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \ + "usbload=usb start && " \ + "fatload usb 0:1 $loadaddr /boot/$bootfile\0" + +#endif /* _CONFIG_NETSPACE_V2_H */ diff --git a/include/configs/netstal-common.h b/include/configs/netstal-common.h deleted file mode 100644 index 122f139..0000000 --- a/include/configs/netstal-common.h +++ /dev/null @@ -1,261 +0,0 @@ -/* - * (C) Copyright 2008 - * Niklaus Giger, Netstal Maschinen AG, niklaus.giger@netstal.com - * adapted from amcc-common.h by - * (C) Copyright 2008 - * * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Common configuration options for all Netstal boards - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __NETSTAL_COMMON_H -#define __NETSTAL_COMMON_H - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */ -#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/* - * UART - */ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SERIAL_MULTI -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -/* - * I2C - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* This is the 7bit address of the device, not including P. */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE - -/* - * Ethernet/EMAC/PHY - */ -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address */ -#define CONFIG_NET_MULTI 1 -#if defined(CONFIG_440) -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_SYS_RX_ETH_BUFFER 32 /* number of eth rx buffers */ -#else -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* number of eth rx buffers */ -#endif -#define CONFIG_HAS_ETH0 - -/* - * Commands - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#if defined(CONFIG_440) -#define CONFIG_CMD_CACHE -#endif -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_BOOT_RETRY_TIME 30 -#define CONFIG_RESET_TO_RETRY -/* - * Miscellaneous configurable options - */ -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO /* To use extended board_into (bd_t) */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_CMDLINE_EDITING /* add command line history */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -#define CONFIG_LOOPW /* enable loopw command */ -#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE /* include version env variable */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ - -#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_SUBNETMASK - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Internal Definitions - */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Pass open firmware flat tree - */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP - -/* - * Booting and default environment - */ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run net_nfs\" to mount root filesystem over NFS;" \ - "echo" -#define CONFIG_BOOTCOMMAND "run vx" - -/* - * Only very few boards have default console not on ttyS0 (like Taishan) - */ -#if !defined(CONFIG_USE_TTY) -#define CONFIG_USE_TTY ttyS0 -#endif - -/* - * Only some 4xx PPC's are equipped with an FPU - */ -#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define CONFIG_NETSTAL_DEF_ENV_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" -#else -#define CONFIG_NETSTAL_DEF_ENV_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0" -#endif - -/* - * Only some boards need to extend the bootargs by some additional - * parameters (like Makalu) - */ -#if !defined(CONFIG_ADDMISC) -#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs}\0" -#endif - -#define xstr(s) str(s) -#define str(s) #s - -/* Setup some values for the default environment variables */ -#define CONFIG_SERVERIP 172.25.1.1 -#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -#define CONFIG_SYS_TFTP_LOADADDR 0x01000000 -#define CONFIG_SYS_VXWORKS_ADD_PARAMS "u=dpu pw=netstal8752" -#define CONFIG_SYS_VXWORKS_SERVERNAME "c" -/* - * General common environment variables shared by all boards produced by Netstal Maschinen - */ -#define CONFIG_NETSTAL_DEF_ENV \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=" xstr(CONFIG_USE_TTY) ",${baudrate}\0" \ - CONFIG_ADDMISC \ - "initrd_high=30000000\0" \ - "kernel_addr_r=400000\0" \ - "fdt_addr_r=800000\0" \ - "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ - "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ - "uload=tftp " xstr(CONFIG_SYS_TFTP_LOADADDR) " " \ - xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ - "vx_rom=" xstr(CONFIG_HOSTNAME) "/" \ - xstr(CONFIG_HOSTNAME) "_vx_rom\0" \ - "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;"\ - "era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \ - "cp.b ${fileaddr} "xstr(CONFIG_SYS_MONITOR_BASE) \ - " ${filesize}; setenv filesize\0" \ - "upd=run uload update\0" \ - "vx=setenv bootfile ${vx_rom}; tftp " \ - xstr(CONFIG_SYS_TFTP_LOADADDR) "; bootvx\0" \ - CONFIG_NETSTAL_DEF_ENV_ROOTPATH - -/* - * Default environment for arch/powerpc booting - * for boards that are ported to arch/powerpc - */ -#define CONFIG_NETSTAL_DEF_ENV_POWERPC \ - "flash_self=run ramargs addip addtty addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmisc;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addtty addmisc;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" - -#endif /* __NETSTAL_COMMON_H */ diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h index 53f2084..d57d53c 100644 --- a/include/configs/nios2-generic.h +++ b/include/configs/nios2-generic.h @@ -52,6 +52,7 @@ /* * TIMER */ +#define CONFIG_SYS_LOW_RES_TIMER #define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_TIMER_BASE #define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_TIMER_IRQ #define CONFIG_SYS_HZ 1000 /* Always 1000 */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 9fd80ed..d7cbc2f 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -31,7 +31,6 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 13a4fbf..afa18aa 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -36,7 +36,6 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 242b317..d6e0a06 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -23,7 +23,6 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 39c87a8..bd55abc 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -26,7 +26,6 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index 55bbcd4..e1d8c78 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -36,7 +36,6 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 9183849..aeac7c7 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -32,7 +32,6 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index 3573edf..2a56182 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -33,7 +33,6 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index b4e7f41..e313231 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -30,7 +30,6 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP44XX 1 /* which is a 44XX */ #define CONFIG_OMAP4430 1 /* which is in a 4430 */ @@ -45,9 +44,6 @@ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 -/* Keep L2 Cache Disabled */ -#define CONFIG_L2_OFF 1 - /* Clock Defines */ #define V_OSCK 38400000 /* Clock output from T2 */ #define V_SCLK V_OSCK @@ -235,4 +231,46 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 1 +#define CONFIG_SYS_PL310_BASE 0x48242000 +#endif + +/* Defines for SDRAM init */ +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +#endif + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_TEXT_BASE 0x40304350 +#define CONFIG_SPL_MAX_SIZE 0x8000 /* 32 K */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds" + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 + #endif /* __CONFIG_H */ diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index 584a52b..5b3110c 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -31,7 +31,6 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP44XX 1 /* which is a 44XX */ #define CONFIG_OMAP4430 1 /* which is in a 4430 */ @@ -46,9 +45,6 @@ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 -/* Keep L2 Cache Disabled */ -#define CONFIG_L2_OFF 1 - /* Clock Defines */ #define V_OSCK 38400000 /* Clock output from T2 */ #define V_SCLK V_OSCK @@ -241,4 +237,46 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 1 +#define CONFIG_SYS_PL310_BASE 0x48242000 +#endif + +/* Defines for SDRAM init */ +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +#endif + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_TEXT_BASE 0x40304350 +#define CONFIG_SPL_MAX_SIZE 0x8000 /* 32 K */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds" + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 + #endif /* __CONFIG_H */ diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index 33fa6ee..7fe9e5b 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -50,9 +50,6 @@ /* * Misc configuration options */ -#define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */ -#define CONFIG_TIMER_IRQ - #define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */ #define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */ @@ -117,6 +114,7 @@ #define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ #define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */ +#define CONFIG_IXP425_TIMER_CLK 66666666 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ /* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } @@ -188,6 +186,7 @@ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ +#define CONFIG_SYS_TEXT_BASE 0x50000000 #define CONFIG_SYS_FLASH_BASE 0x50000000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #if defined(CONFIG_SCPU) @@ -345,4 +344,9 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 32 +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + #endif /* __CONFIG_H */ diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h index 9dbb406..ad82213 100644 --- a/include/configs/pleb2.h +++ b/include/configs/pleb2.h @@ -44,7 +44,7 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE +#define CONFIG_SYS_DCACHE_OFF /* * Size of malloc() pool diff --git a/include/configs/suen8.h b/include/configs/portl2.h index 78cee75..a8543a5 100644 --- a/include/configs/suen8.h +++ b/include/configs/portl2.h @@ -8,6 +8,7 @@ * * (C) Copyright 2010-2011 * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com. + * Valentin Longchamp, Keymile AG Bern, valentin.longchamp@keymile.com * * See file CREDITS for list of people who contributed to this * project. @@ -31,8 +32,8 @@ /* for linking errors see * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ -#ifndef _CONFIG_SUEN8_H -#define _CONFIG_SUEN8_H +#ifndef _CONFIG_PORTL2_H +#define _CONFIG_PORTL2_H /* include common defines/options for all arm based Keymile boards */ #include "km/km_arm.h" @@ -40,11 +41,41 @@ /* * Version number information */ -#define CONFIG_IDENT_STRING "\nKeymile SUEN8" - -#define CONFIG_HOSTNAME suen8 +#define CONFIG_IDENT_STRING "\nKeymile Port-L2" +#define CONFIG_HOSTNAME portl2 +#define CONFIG_PORTL2 #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ -#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ +#define KM_ENV_BUS "pca9544a:70:a" /* I2C2 (Mux-Port 2)*/ + +/* + * portl2 has a fixed link to the XMPP backplane + * with 100MB full duplex and autoneg off, for this + * reason we have to change the default settings + */ +#define PORT_SERIAL_CONTROL_VALUE ( \ + MVGBE_FORCE_LINK_PASS | \ + MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ + MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ + MVGBE_ADV_NO_FLOW_CTRL | \ + MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + MVGBE_FORCE_BP_MODE_NO_JAM | \ + (1 << 9) /* Reserved bit has to be 1 */ | \ + MVGBE_DO_NOT_FORCE_LINK_FAIL | \ + MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ + MVGBE_DTE_ADV_0 | \ + MVGBE_MIIPHY_MAC_MODE | \ + MVGBE_AUTO_NEG_NO_CHANGE | \ + MVGBE_MAX_RX_PACKET_1552BYTE | \ + MVGBE_CLR_EXT_LOOPBACK | \ + MVGBE_SET_FULL_DUPLEX_MODE | \ + MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ + MVGBE_SET_GMII_SPEED_TO_10_100 |\ + MVGBE_SET_MII_SPEED_TO_100) + +/* + * portl2 does use the PCIe Port0 + */ +#define CONFIG_KIRKWOOD_PCIE_INIT -#endif /* _CONFIG_SUEN8_H */ +#endif /* _CONFIG_PORTL2_H */ diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index c1c7f80..e591d87 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -69,7 +69,7 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE +#define CONFIG_SYS_DCACHE_OFF /* * Size of malloc() pool diff --git a/include/configs/qong.h b/include/configs/qong.h index 405c438..78b3701 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -24,7 +24,7 @@ #include <asm/arch/imx-regs.h> - /* High Level Configuration Options */ +/* High Level Configuration Options */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ #define CONFIG_MX31 1 /* in a mx31 */ #define CONFIG_QONG 1 @@ -34,6 +34,8 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_TEXT_BASE 0xa0000000 + #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index d648ce8..a5aa859 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -28,7 +28,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ #define CONFIG_S5P 1 /* which is in a S5P Family */ #define CONFIG_S5PC110 1 /* which is in a S5PC110 */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 5915984..4031016 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -30,7 +30,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ #define CONFIG_S5P 1 /* which is in a S5P Family */ #define CONFIG_S5PC210 1 /* which is in a S5PC210 */ @@ -43,7 +42,7 @@ #define CONFIG_DISPLAY_BOARDINFO /* Keep L2 Cache Disabled */ -#define CONFIG_L2_OFF 1 +#define CONFIG_SYS_L2CACHE_OFF 1 #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_TEXT_BASE 0x44800000 diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h index 3da214e..1b5d931 100644 --- a/include/configs/scb9328.h +++ b/include/configs/scb9328.h @@ -95,7 +95,6 @@ #define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ #define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ #define CONFIG_INITRD_TAG 1 /* send initrd params */ -#undef CONFIG_VFD /* do not send framebuffer setup */ /* * Malloc pool need to host env + 128 Kb reserve for other allocations. @@ -127,6 +126,11 @@ #define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */ #define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */ +#define CONFIG_SYS_TEXT_BASE 0x10000000 + +#define CONFIG_SYS_SDRAM_BASE SCB9328_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (SCB9328_SDRAM_1 + 0xf00000) + /* * Configuration for FLASH memory for the Synertronixx board */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 06ce3e2..7d29144 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -41,4 +41,15 @@ #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ #define CONFIG_BOARD_EARLY_INIT_F + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA2_MMC +#define CONFIG_CMD_MMC + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT #endif /* __CONFIG_H */ diff --git a/include/configs/shannon.h b/include/configs/shannon.h index c0e6643..fce4121 100644 --- a/include/configs/shannon.h +++ b/include/configs/shannon.h @@ -44,7 +44,7 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE +#define CONFIG_SYS_DCACHE_OFF /* * Size of malloc() pool diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 70e23b5..19dde1b 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -32,7 +32,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ #define CONFIG_S5P 1 /* which is in a S5P Family */ #define CONFIG_S5PC100 1 /* which is in a S5PC100 */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index a7f5850..2f97bea 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -26,7 +26,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_ARMV7 1 /*This is an ARM V7 CPU core */ #define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ #define CONFIG_S5P 1 /* S5P Family */ #define CONFIG_S5PC210 1 /* which is in a S5PC210 SoC */ @@ -166,4 +165,7 @@ #define CONFIG_SMC911X_16_BIT #define CONFIG_ENV_SROM_BANK 1 #endif /*CONFIG_CMD_NET*/ + +/* Enable devicetree support */ +#define CONFIG_OF_LIBFDT #endif /* __CONFIG_H */ diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h new file mode 100644 index 0000000..7def16f --- /dev/null +++ b/include/configs/snapper9260.h @@ -0,0 +1,191 @@ +/* + * Bluewater Systems Snapper 9260 and 9G20 modules + * + * (C) Copyright 2011 Bluewater Systems + * Author: Andre Renaud <andre@bluewatersys.com> + * Author: Ryan Mallon <ryan@bluewatersys.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* SoC type is defined in boards.cfg */ +#include <asm/hardware.h> +#include <asm/sizes.h> + +#define CONFIG_SYS_TEXT_BASE 0x20000000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_HZ 1000 + +/* CPU */ +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_USE_IRQ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_FIT + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */ +#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) + +/* Mem test settings */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024)) + +/* NAND Flash */ +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_MULTI +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R +#define CONFIG_TFTP_PORT +#define CONFIG_TFTP_TSIZE + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE + +/* GPIOs and IO expander */ +#define CONFIG_AT91_LEGACY +#define CONFIG_ATMEL_LEGACY +#define CONFIG_AT91_GPIO +#define CONFIG_AT91_GPIO_PULLUP 1 +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR 0x28 +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} } + +/* UARTs/Serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } +#define CONFIG_SYS_PROMPT "Snapper> " + +/* I2C - Bit-bashed */ +#define CONFIG_SOFT_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SOFT_I2C_READ_REPEATED_START +#define CONFIG_I2C_MULTI_BUS +#define I2C_INIT do { \ + at91_set_gpio_output(AT91_PIN_PA23, 1); \ + at91_set_gpio_output(AT91_PIN_PA24, 1); \ + at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ + at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ + } while (0) +#define I2C_SOFT_DECLARATIONS +#define I2C_ACTIVE +#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1); +#define I2C_READ at91_get_gpio_value(AT91_PIN_PA23); +#define I2C_SDA(bit) do { \ + if (bit) { \ + at91_set_gpio_input(AT91_PIN_PA23, 1); \ + } else { \ + at91_set_gpio_output(AT91_PIN_PA23, 1); \ + at91_set_gpio_value(AT91_PIN_PA23, bit); \ + } \ + } while (0) +#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) +#define I2C_DELAY udelay(2) + +/* Boot options */ +#define CONFIG_SYS_LOAD_ADDR 0x23000000 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Environment settings */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (512 << 10) +#define CONFIG_ENV_SIZE (256 << 10) +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BOOTARGS "console=ttyS0,115200 ip=any" + +/* Console settings */ +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_EXTBDINFO +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* U-Boot memory settings */ +#define CONFIG_SYS_MALLOC_LEN (1 << 20) +#define CONFIG_STACKSIZE (256 << 10) + +/* Command line configuration */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_SOURCE + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#undef CONFIG_CMD_GPIO +#define CONFIG_CMD_USB +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO + +#endif /* __CONFIG_H */ diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 4e5bdea..55d19b5 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -86,6 +86,8 @@ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* NAND FLASH Configuration */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS #define CONFIG_NAND_SPEAR 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 @@ -209,4 +211,14 @@ #define PHYS_SDRAM_1 0x00000000 #define PHYS_SDRAM_1_MAXSIZE 0x40000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + #endif diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index d5dd94f..141da26 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -43,7 +43,7 @@ #define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/ #define CONFIG_MPC8560 1 -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 +#define CONFIG_SYS_TEXT_BASE 0xFFF80000 #define CONFIG_PCI /* PCI ethernet support */ #define CONFIG_TSEC_ENET /* tsec ethernet support*/ @@ -194,6 +194,11 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + /* * I2C */ diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h index 9a6100e..2375fc5 100644 --- a/include/configs/tcm-bf537.h +++ b/include/configs/tcm-bf537.h @@ -55,17 +55,19 @@ #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* * Network Settings */ -/* TCM-BF537E has no PHY on it, but EXT-BF5xx-USB/Ethernet board has */ #ifndef __ADSPBF534__ #define ADI_CMDS_NETWORK 1 #define CONFIG_BFIN_MAC +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_BASE 0x20308000 +#define CONFIG_SMC911X_16_BIT #define CONFIG_NETCONSOLE 1 #define CONFIG_NET_MULTI 1 #endif @@ -87,6 +89,13 @@ /* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 + + +/* * Env Storage Settings */ #define CONFIG_ENV_IS_IN_FLASH 1 @@ -119,6 +128,13 @@ /* + * SPI_MMC Settings + */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SPI + +/* * Misc Settings */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index febce35..73e0f05 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -31,7 +31,7 @@ #define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */ #define CONFIG_TEGRA2 /* in a NVidia Tegra2 core */ #define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */ -#define CONFIG_L2_OFF /* No L2 cache */ +#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ #define CONFIG_ENABLE_CORTEXA9 /* enable CPU (A9 complex) */ @@ -160,4 +160,6 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) +#define CONFIG_TEGRA2_GPIO +#define CONFIG_CMD_GPIO #endif /* __TEGRA2_COMMON_H */ diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h index 3627ce7..4bced0c 100644 --- a/include/configs/tnetv107x_evm.h +++ b/include/configs/tnetv107x_evm.h @@ -57,6 +57,12 @@ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_STACKSIZE (256*1024) +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + /* Serial Driver Info */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL diff --git a/include/configs/top9000.h b/include/configs/top9000.h index 5f0160d..5bca6e1 100644 --- a/include/configs/top9000.h +++ b/include/configs/top9000.h @@ -38,6 +38,10 @@ #ifndef __CONFIG_H #define __CONFIG_H +/* SoC must be defined first, before hardware.h is included */ +#define CONFIG_AT91SAM9XE +#include <asm/hardware.h> + /* * Warning: changing CONFIG_SYS_TEXT_BASE requires * adapting the initial boot program. @@ -61,17 +65,11 @@ #define CONFIG_CMD_CACHE /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz xtal */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ #define CONFIG_SYS_HZ 1000 -/* SoC */ -#define CONFIG_ARM926EJS /* ARM926EJS Core */ -#define CONFIG_AT91FAMILY /* it's a member of AT91 */ -#define CONFIG_AT91SAM9260 /* Atmel AT91SAM9260 based SoC */ -#define CONFIG_AT91SAM9XE - /* Misc CPU related */ -#define CONFIG_AT91_LEGACY #define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ @@ -83,12 +81,14 @@ #define CONFIG_AT91RESET_EXTRST /* assert external reset */ /* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ /* serial console */ #define CONFIG_ATMEL_USART -#define CONFIG_USART3 /* USART 3 is DBGU !!! */ +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } @@ -123,7 +123,7 @@ * with u-boot commands */ # define CONFIG_AT91_EFLASH -# define CONFIG_SYS_FLASH_BASE 0x200000 +# define CONFIG_SYS_FLASH_BASE ATMEL_BASE_FLASH # define CONFIG_SYS_MAX_FLASH_SECT 32 # define CONFIG_SYS_MAX_FLASH_BANKS 1 # define CONFIG_SYS_FLASH_PROTECTION @@ -159,10 +159,10 @@ * Initialized before u-boot gets started. */ #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x21e00000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01e00000) #define CONFIG_SYS_LOAD_ADDR \ (CONFIG_SYS_SDRAM_BASE + 0x01000000) /* @@ -171,7 +171,7 @@ * that address while providing maximum stack area below. */ #define CONFIG_SYS_INIT_SP_ADDR \ - (0x00300000 + 0x4000 - GENERATED_GBL_DATA_SIZE) + (ATMEL_BASE_SRAM + 0x4000 - GENERATED_GBL_DATA_SIZE) /* * NAND flash: 256 MB (optional) @@ -184,7 +184,7 @@ */ #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) @@ -197,7 +197,7 @@ #define CONFIG_USB_OHCI_NEW #define CONFIG_DOS_PARTITION #define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE #define CONFIG_SYS_USB_OHCI_SLOT_NAME "top9000" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE diff --git a/include/configs/trab.h b/include/configs/trab.h deleted file mode 100644 index d5736a2..0000000 --- a/include/configs/trab.h +++ /dev/null @@ -1,419 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Gary Jennejohn <garyj@denx.de> - * - * Configuation settings for the TRAB board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Default configuration is with 8 MB Flash, 32 MB RAM - */ -#if (!defined(CONFIG_FLASH_8MB)) && (!defined(CONFIG_FLASH_16MB)) -# define CONFIG_FLASH_8MB /* 8 MB Flash */ -#endif -#if (!defined(CONFIG_RAM_16MB)) && (!defined(CONFIG_RAM_32MB)) -# define CONFIG_RAM_32MB /* 32 MB SDRAM */ -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM920T 1 /* This is an arm920t CPU */ -#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ -#define CONFIG_S3C2400 1 /* specifically a SAMSUNG S3C2400 SoC */ -#define CONFIG_TRAB 1 /* on a TRAB Board */ -#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */ - -/* automatic software updates (see board/trab/auto_update.c) */ -#define CONFIG_AUTO_UPDATE 1 - -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000 /* TRAB has 12 MHz input clock */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enble null device */ -#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*********************************************************** - * I2C stuff: - * the TRAB is equipped with an ATMEL 24C04 EEPROM at - * address 0x54 with 8bit addressing - ***********************************************************/ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ -#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM address */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 1 address byte */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 bytes page write mode on 24C04 */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* USB stuff */ -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_DOS_PARTITION 1 - -#undef CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 - -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x14200000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "s3c2400" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -#define CONFIG_NET_MULTI -#define CONFIG_CS8900 /* we have a CS8900 on-board */ -#define CONFIG_CS8900_BASE 0x07000300 /* agrees with WIN CE PA */ -#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ - -#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ - -#define CONFIG_VFD 1 /* VFD linear frame buffer driver */ -#define VFD_TEST_LOGO 1 /* output a test logo to the VFDs */ - -/* - * select serial console configuration - */ -#define CONFIG_S3C24X0_SERIAL -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on TRAB */ - -#define CONFIG_HWFLOW /* include RTS/CTS flow control support */ - -#define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */ - -#define CONFIG_MODEM_KEY_MAGIC "23" /* hold down these keys to enable modem */ - -/* - * The following enables modem debugging stuff. The dbg() and - * 'char screen[1024]' are used for debug printfs. Unfortunately, - * it is usable only from BDI - */ -#undef CONFIG_MODEM_SUPPORT_DEBUG - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ - -/* Use s3c2400's RTC */ -#define CONFIG_RTC_S3C24X0 1 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_FAT -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_USB - -#ifdef CONFIG_HWFLOW - #define CONFIG_CMD_HWFLOW -#endif - -#ifdef CONFIG_VFD - #define CONFIG_CMD_VFD -#endif - -#ifdef CONFIG_DRIVER_S3C24X0_I2C - #define CONFIG_CMD_EEPROM - #define CONFIG_CMD_I2C -#endif - -#ifndef USE_920T_MMU - #undef CONFIG_CMD_CACHE -#endif - - -/* moved up */ -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */ -#define CONFIG_PREBOOT "echo;echo *** booting ***;echo" -#define CONFIG_BOOTARGS "console=ttyS0" -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_IPADDR 192.168.3.68 -#define CONFIG_HOSTNAME trab -#define CONFIG_SERVERIP 192.168.3.1 -#define CONFIG_BOOTCOMMAND "burn_in" - -#ifndef CONFIG_FLASH_8MB /* current config: 16 MB flash */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfs_args=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath\0" \ - "rootpath=/opt/eldk/arm_920TDI\0" \ - "ram_args=setenv bootargs root=/dev/ram rw\0" \ - "add_net=setenv bootargs $bootargs ethaddr=$ethaddr " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ - "add_misc=setenv bootargs $bootargs console=ttyS0 panic=1\0" \ - "u-boot=/tftpboot/TRAB/u-boot.bin\0" \ - "load=tftp C100000 ${u-boot}\0" \ - "update=protect off 0 5FFFF;era 0 5FFFF;" \ - "cp.b C100000 0 $filesize\0" \ - "loadfile=/tftpboot/TRAB/uImage\0" \ - "loadaddr=c400000\0" \ - "net_load=tftpboot $loadaddr $loadfile\0" \ - "net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \ - "kernel_addr=00060000\0" \ - "flash_nfs=run nfs_args add_net add_misc;bootm $kernel_addr\0" \ - "mdm_init1=ATZ\0" \ - "mdm_init2=ATS0=1\0" \ - "mdm_flow_control=rts/cts\0" -#else /* !CONFIG_SYS_HUSH_PARSER */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfs_args=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "rootpath=/opt/eldk/arm_920TDI\0" \ - "ram_args=setenv bootargs root=/dev/ram rw\0" \ - "add_net=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ - "add_misc=setenv bootargs ${bootargs} console=ttyS0 panic=1\0" \ - "u-boot=/tftpboot/TRAB/u-boot.bin\0" \ - "load=tftp C100000 ${u-boot}\0" \ - "update=protect off 0 5FFFF;era 0 5FFFF;" \ - "cp.b C100000 0 ${filesize}\0" \ - "loadfile=/tftpboot/TRAB/uImage\0" \ - "loadaddr=c400000\0" \ - "net_load=tftpboot ${loadaddr} ${loadfile}\0" \ - "net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \ - "kernel_addr=000C0000\0" \ - "flash_nfs=run nfs_args add_net add_misc;bootm ${kernel_addr}\0" \ - "mdm_init1=ATZ\0" \ - "mdm_init2=ATS0=1\0" \ - "mdm_flow_control=rts/cts\0" -#endif /* CONFIG_SYS_HUSH_PARSER */ -#else /* CONFIG_FLASH_8MB => 8 MB flash */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfs_args=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath\0" \ - "rootpath=/opt/eldk/arm_920TDI\0" \ - "ram_args=setenv bootargs root=/dev/ram rw\0" \ - "add_net=setenv bootargs $bootargs ethaddr=$ethaddr " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ - "add_misc=setenv bootargs $bootargs console=ttyS0 panic=1\0" \ - "u-boot=/tftpboot/TRAB/u-boot.bin\0" \ - "load=tftp C100000 ${u-boot}\0" \ - "update=protect off 0 3FFFF;era 0 3FFFF;" \ - "cp.b C100000 0 $filesize;" \ - "setenv filesize;saveenv\0" \ - "loadfile=/tftpboot/TRAB/uImage\0" \ - "loadaddr=C400000\0" \ - "net_load=tftpboot $loadaddr $loadfile\0" \ - "net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \ - "kernel_addr=000C0000\0" \ - "flash_nfs=run nfs_args add_net add_misc;bootm $kernel_addr\0" \ - "mdm_init1=ATZ\0" \ - "mdm_init2=ATS0=1\0" \ - "mdm_flow_control=rts/cts\0" -#else /* !CONFIG_SYS_HUSH_PARSER */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfs_args=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "rootpath=/opt/eldk/arm_920TDI\0" \ - "ram_args=setenv bootargs root=/dev/ram rw\0" \ - "add_net=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ - "add_misc=setenv bootargs ${bootargs} console=ttyS0 panic=1\0" \ - "u-boot=/tftpboot/TRAB/u-boot.bin\0" \ - "load=tftp C100000 ${u-boot}\0" \ - "update=protect off 0 3FFFF;era 0 3FFFF;" \ - "cp.b C100000 0 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "loadfile=/tftpboot/TRAB/uImage\0" \ - "loadaddr=C400000\0" \ - "net_load=tftpboot ${loadaddr} ${loadfile}\0" \ - "net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \ - "kernel_addr=000C0000\0" \ - "flash_nfs=run nfs_args add_net add_misc;bootm ${kernel_addr}\0" \ - "mdm_init1=ATZ\0" \ - "mdm_init2=ATS0=1\0" \ - "mdm_flow_control=rts/cts\0" -#endif /* CONFIG_SYS_HUSH_PARSER */ -#endif /* CONFIG_FLASH_8MB */ - -#if 1 /* feel free to disable for development */ -#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT \ - "\nEnter password - autoboot in %d sec...\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "R" /* 1st "password" */ -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "TRAB # " /* Monitor Command Prompt */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif - -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0C000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0D000000 /* 16 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x0CF00000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ - -/*----------------------------------------------------------------------- - * burn-in test stuff. - * - * BURN_IN_CYCLE_DELAY defines the seconds to wait between each burn-in cycle - * Because the burn-in test itself causes also an delay of about 4 seconds, - * this time must be subtracted from the desired overall burn-in cycle time. - */ -#define BURN_IN_CYCLE_DELAY 296 /* seconds between burn-in cycles */ - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x0C000000 /* SDRAM Bank #1 */ -#ifndef CONFIG_RAM_16MB -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ -#else -#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ -#endif - -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* Flash Bank #1 */ - -/* The following #defines are needed to get flash environment right */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) - -/* Dynamic MTD partition support */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=0" - -/* production flash layout */ -#define MTDPARTS_DEFAULT "mtdparts=0:16k(Firmware1)ro," \ - "16k(Env1)," \ - "16k(Env2)," \ - "336k(Firmware2)ro," \ - "896k(Kernel)," \ - "5376k(Root-FS)," \ - "1408k(JFFS2)," \ - "-(VFD)" - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#ifndef CONFIG_FLASH_8MB -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#else -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#endif - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (15*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#ifndef CONFIG_FLASH_8MB -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_ENV_SECT_SIZE 0x4000 -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/* Initial value of the on-board touch screen brightness */ -#define CONFIG_SYS_BRIGHTNESS 0x20 - -#endif /* __CONFIG_H */ diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index 2512f93..ec052c4 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -49,7 +49,7 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE +#define CONFIG_SYS_DCACHE_OFF #define RTC diff --git a/include/configs/versatile.h b/include/configs/versatile.h index db68965..32cee82 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -74,6 +74,7 @@ /* * Size of malloc() pool */ +#define CONFIG_ENV_SIZE 8192 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) /* @@ -168,9 +169,26 @@ #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ #define PHYS_FLASH_SIZE 0x04000000 /* 64MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x00800000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x000FFFFF +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_GBL_DATA_OFFSET) + +#define CONFIG_BOARD_EARLY_INIT_F + /*----------------------------------------------------------------------- * FLASH and environment organization */ +#ifdef CONFIG_ARCH_VERSATILE_QEMU +#define CONFIG_SYS_TEXT_BASE 0x10000 +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#else +#define CONFIG_SYS_TEXT_BASE 0x01000000 /* * Use the CFI flash driver for ease of use */ @@ -222,7 +240,6 @@ /* The ARM Boot Monitor is shipped in the lowest sector of flash */ #define FLASH_TOP (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE) -#define CONFIG_ENV_SIZE 8192 #define CONFIG_ENV_ADDR (FLASH_TOP - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) #define CONFIG_SYS_MONITOR_BASE (CONFIG_ENV_ADDR - CONFIG_SYS_MONITOR_LEN) @@ -230,4 +247,6 @@ #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/vision2.h b/include/configs/vision2.h index 66795b5..50c920d 100644 --- a/include/configs/vision2.h +++ b/include/configs/vision2.h @@ -26,7 +26,7 @@ #define CONFIG_MX51 /* in a mx51 */ -#define CONFIG_L2_OFF +#define CONFIG_SYS_L2CACHE_OFF #define CONFIG_SYS_TEXT_BASE 0x97800000 #include <asm/arch/imx-regs.h> diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h index a75c426..205e86c 100644 --- a/include/configs/xaeniax.h +++ b/include/configs/xaeniax.h @@ -51,7 +51,7 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE +#define CONFIG_SYS_DCACHE_OFF /* * select serial console configuration diff --git a/include/configs/xm250.h b/include/configs/xm250.h index 232baf3..32544fe 100644 --- a/include/configs/xm250.h +++ b/include/configs/xm250.h @@ -38,7 +38,7 @@ #define CONFIG_SYS_TEXT_BASE 0x0 /* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE +#define CONFIG_SYS_DCACHE_OFF /* * Size of malloc() pool; this lives below the uppermost 128 KiB which are @@ -139,7 +139,6 @@ #define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ #define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ #define CONFIG_INITRD_TAG 1 /* do not send initrd params */ -#undef CONFIG_VFD /* do not send framebuffer setup */ /* * Stack sizes diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h new file mode 100644 index 0000000..374c88a --- /dev/null +++ b/include/configs/zmx25.h @@ -0,0 +1,180 @@ +/* + * (c) 2011 Graf-Syteco, Matthias Weisser + * <weisserm@arcor.de> + * + * Configuation settings for the zmx25 board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_MX25 +#define CONFIG_MX25_CLK32 32768 /* OSC32K frequency */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_TEXT_BASE 0xA0000000 + +/* + * Environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "gs_fast_boot=setenv bootdelay 5\0" \ + "gs_slow_boot=setenv bootdelay 10\0" \ + "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \ + "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \ + "bootm 0x81000000; bootelf 0x81000000\0" + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define BOARD_LATE_INIT + +/* + * Compressions + */ +#define CONFIG_LZO + +/* + * Hardware drivers + */ + +/* + * GPIO + */ +#define CONFIG_MXC_GPIO + +/* + * Serial + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX25_UART2 +#define CONFIG_CONS_INDEX 1 /* use UART2 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Ethernet + */ +#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_PHYADDR 0x00 +#define CONFIG_MII +#define CONFIG_NET_MULTI + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#define CONFIG_CMD_NET +#define CONFIG_CMD_CACHE + +#define CONFIG_SYS_64BIT_VSPRINTF + +/* + * Additional command + */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_USB + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_MXC +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORT 2 +#define CONFIG_MXC_USB_PORTSC 0xC0000000 +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT +#endif /* CONFIG_CMD_USB */ + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */ +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */ + +/* + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE 0xA0000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 + +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE (128 * 1024) + +/* + * CFI FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* ~10x faster */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024)) +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE) + +#define CONFIG_SYS_PROMPT "zmx25> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_PREBOOT "" + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay +#define CONFIG_AUTOBOOT_DELAY_STR "delaygs" +#define CONFIG_AUTOBOOT_STOP_STR "stopgs" + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000) +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index 1e03b01..5f153e3 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -48,7 +48,7 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE +#define CONFIG_SYS_DCACHE_OFF /* * Size of malloc() pool diff --git a/include/ddr_spd.h b/include/ddr_spd.h index e895d61..40a0463 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -219,7 +219,9 @@ typedef struct ddr3_spd_eeprom_s { Delay Time*/ unsigned char opt_features; /* 30 SDRAM Optional Features */ unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */ - unsigned char res_32_59[28]; /* 32-59 Reserved, General Section */ + unsigned char therm_sensor; /* 32 Module Thermal Sensor */ + unsigned char device_type; /* 33 SDRAM device type */ + unsigned char res_34_59[26]; /* 34-59 Reserved, General Section */ /* Module-Specific Section: Bytes 60-116 */ union { diff --git a/include/environment.h b/include/environment.h index 53d92df..6394a96 100644 --- a/include/environment.h +++ b/include/environment.h @@ -124,7 +124,9 @@ extern unsigned long nand_env_oob_offset; /* The build system likes to know if the env is embedded */ #ifdef DO_DEPS_ONLY # ifdef ENV_IS_EMBEDDED -# define CONFIG_ENV_IS_EMBEDDED +# ifndef CONFIG_ENV_IS_EMBEDDED +# define CONFIG_ENV_IS_EMBEDDED +# endif # endif #endif @@ -160,7 +162,7 @@ extern struct hsearch_data env_htab; unsigned char env_get_char (int); /* Function that returns a pointer to a value from the environment */ -unsigned char *env_get_addr(int); +const unsigned char *env_get_addr(int); unsigned char env_get_char_memory (int index); /* Function that updates CRC of the enironment */ diff --git a/include/exports.h b/include/exports.h index e14d727..9492566 100644 --- a/include/exports.h +++ b/include/exports.h @@ -21,8 +21,8 @@ unsigned long get_timer(unsigned long); int vprintf(const char *, va_list); unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base); int strict_strtoul(const char *cp, unsigned int base, unsigned long *res); -char *getenv (char *name); -int setenv (char *varname, char *varvalue); +char *getenv (const char *name); +int setenv (const char *varname, const char *varvalue); long simple_strtol(const char *cp,char **endp,unsigned int base); int strcmp(const char * cs,const char * ct); int ustrtoul(const char *cp, char **endp, unsigned int base); diff --git a/include/fdt_support.h b/include/fdt_support.h index ce6817b..863024f 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -79,6 +79,7 @@ void ft_pci_setup(void *blob, bd_t *bd); void set_working_fdt_addr(void *addr); int fdt_resize(void *blob); +int fdt_increase_size(void *fdt, int add_len); int fdt_fixup_nor_flash_size(void *blob); @@ -88,7 +89,12 @@ u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr); int fdt_node_offset_by_compat_reg(void *blob, const char *compat, phys_addr_t compat_off); int fdt_alloc_phandle(void *blob); +int fdt_create_phandle(void *fdt, int nodeoffset, uint32_t phandle); int fdt_add_edid(void *blob, const char *compat, unsigned char *buf); +int fdt_verify_alias_address(void *fdt, int anode, const char *alias, + u64 addr); +u64 fdt_get_base_address(void *fdt, int node); + #endif /* ifdef CONFIG_OF_LIBFDT */ #endif /* ifndef __FDT_SUPPORT_H */ diff --git a/include/fpga.h b/include/fpga.h index ac24f2b..e0b1fe7 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -72,11 +72,11 @@ typedef struct { /* typedef fpga_desc */ /* root function definitions */ -extern void fpga_init( void ); -extern int fpga_add( fpga_type devtype, void *desc ); -extern int fpga_count( void ); -extern int fpga_load( int devnum, void *buf, size_t bsize ); -extern int fpga_dump( int devnum, void *buf, size_t bsize ); -extern int fpga_info( int devnum ); +extern void fpga_init(void); +extern int fpga_add(fpga_type devtype, void *desc); +extern int fpga_count(void); +extern int fpga_load(int devnum, const void *buf, size_t bsize); +extern int fpga_dump(int devnum, const void *buf, size_t bsize); +extern int fpga_info(int devnum); #endif /* _FPGA_H_ */ diff --git a/include/galileo/gt64260R.h b/include/galileo/gt64260R.h index c2cfb06..b55da9d 100644 --- a/include/galileo/gt64260R.h +++ b/include/galileo/gt64260R.h @@ -1182,7 +1182,7 @@ #define CHANNEL2_REGISTER10 0x9070 #define CHANNEL2_REGISTER11 0x9074 -/* MPSCs Interupts */ +/* MPSCs Interrupts */ #define MPSC0_CAUSE 0xb824 #define MPSC0_MASK 0xb8a4 diff --git a/include/image.h b/include/image.h index c31e862..352e4a0 100644 --- a/include/image.h +++ b/include/image.h @@ -157,6 +157,8 @@ #define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ #define IH_TYPE_KWBIMAGE 9 /* Kirkwood Boot Image */ #define IH_TYPE_IMXIMAGE 10 /* Freescale IMXBoot Image */ +#define IH_TYPE_UBLIMAGE 11 /* Davinci UBL Image */ +#define IH_TYPE_OMAPIMAGE 12 /* TI OMAP Config Header Image */ /* * Compression Types diff --git a/include/libfdt.h b/include/libfdt.h index d23d40e..de82ed5 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -343,6 +343,75 @@ int fdt_path_offset(const void *fdt, const char *path); const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp); /** + * fdt_first_property_offset - find the offset of a node's first property + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * + * fdt_first_property_offset() finds the first property of the node at + * the given structure block offset. + * + * returns: + * structure block offset of the property (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested node has no properties + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_first_property_offset(const void *fdt, int nodeoffset); + +/** + * fdt_next_property_offset - step through a node's properties + * @fdt: pointer to the device tree blob + * @offset: structure block offset of a property + * + * fdt_next_property_offset() finds the property immediately after the + * one at the given structure block offset. This will be a property + * of the same node as the given property. + * + * returns: + * structure block offset of the next property (>=0), on success + * -FDT_ERR_NOTFOUND, if the given property is the last in its node + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_next_property_offset(const void *fdt, int offset); + +/** + * fdt_get_property_by_offset - retrieve the property at a given offset + * @fdt: pointer to the device tree blob + * @offset: offset of the property to retrieve + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property_by_offset() retrieves a pointer to the + * fdt_property structure within the device tree blob at the given + * offset. If lenp is non-NULL, the length of the property value is + * also returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property_by_offset(const void *fdt, + int offset, + int *lenp); + +/** * fdt_get_property_namelen - find a property based on substring * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node whose property to find @@ -396,6 +465,40 @@ static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset, } /** + * fdt_getprop_by_offset - retrieve the value of a property at a given offset + * @fdt: pointer to the device tree blob + * @ffset: offset of the property to read + * @namep: pointer to a string variable (will be overwritten) or NULL + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop_by_offset() retrieves a pointer to the value of the + * property at structure block offset 'offset' (this will be a pointer + * to within the device blob itself, not a copy of the value). If + * lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. If namep is non-NULL, + * the property's namne will also be returned in the char * pointed to + * by namep (this will be a pointer to within the device tree's string + * block, not a new copy of the name). + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * if namep is non-NULL *namep contiains a pointer to the property + * name. + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_getprop_by_offset(const void *fdt, int offset, + const char **namep, int *lenp); + +/** * fdt_getprop_namelen - get property value based on substring * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node whose property to find diff --git a/include/linux/mdio.h b/include/linux/mdio.h index 022d772..be80f91 100644 --- a/include/linux/mdio.h +++ b/include/linux/mdio.h @@ -120,6 +120,14 @@ #define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1) #define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2) +#define MDIO_DEVS_LINK (MDIO_DEVS_PMAPMD | \ + MDIO_DEVS_WIS | \ + MDIO_DEVS_PCS | \ + MDIO_DEVS_PHYXS | \ + MDIO_DEVS_DTEXS | \ + MDIO_DEVS_AN) + + /* Control register 2. */ #define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */ diff --git a/include/mmc.h b/include/mmc.h index aeacdee..53aff9b 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -45,6 +45,7 @@ #define MMC_MODE_4BIT 0x100 #define MMC_MODE_8BIT 0x200 #define MMC_MODE_SPI 0x400 +#define MMC_MODE_HC 0x800 #define SD_DATA_4BIT 0x00040000 @@ -75,6 +76,9 @@ #define MMC_CMD_READ_MULTIPLE_BLOCK 18 #define MMC_CMD_WRITE_SINGLE_BLOCK 24 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 +#define MMC_CMD_ERASE_GROUP_START 35 +#define MMC_CMD_ERASE_GROUP_END 36 +#define MMC_CMD_ERASE 38 #define MMC_CMD_APP_CMD 55 #define MMC_CMD_SPI_READ_OCR 58 #define MMC_CMD_SPI_CRC_ON_OFF 59 @@ -84,6 +88,8 @@ #define SD_CMD_SEND_IF_COND 8 #define SD_CMD_APP_SET_BUS_WIDTH 6 +#define SD_CMD_ERASE_WR_BLK_START 32 +#define SD_CMD_ERASE_WR_BLK_END 33 #define SD_CMD_APP_SEND_OP_COND 41 #define SD_CMD_APP_SEND_SCR 51 @@ -99,6 +105,8 @@ #define OCR_VOLTAGE_MASK 0x007FFF80 #define OCR_ACCESS_MODE 0x60000000 +#define SECURE_ERASE 0x80000000 + #define MMC_STATUS_MASK (~0x0206BF7F) #define MMC_STATUS_RDY_FOR_DATA (1 << 8) #define MMC_STATUS_CURR_STATE (0xf << 9) @@ -285,6 +293,7 @@ struct mmc { uint tran_speed; uint read_bl_len; uint write_bl_len; + uint erase_grp_size; u64 capacity; block_dev_desc_t block_dev; int (*send_cmd)(struct mmc *mmc, diff --git a/include/mpc5xxx_sdma.h b/include/mpc5xxx_sdma.h index 8b740e4..821ac0a 100644 --- a/include/mpc5xxx_sdma.h +++ b/include/mpc5xxx_sdma.h @@ -82,11 +82,11 @@ ALL PARAMETERS ARE ALL LONGWORDS (FOUR BYTES EACH). sdma->IntPend = (1 << tasknum); \ } -/* get interupt pending bit of a task */ +/* get interrupt pending bit of a task */ #define SDMA_GET_PENDINGBIT(tasknum) \ ((*(vu_long *)(MPC5XXX_SDMA + 0x14)) & (1<<(tasknum))) -/* get interupt mask bit of a task */ +/* get interrupt mask bit of a task */ #define SDMA_GET_MASKBIT(tasknum) \ ((*(vu_long *)(MPC5XXX_SDMA + 0x18)) & (1<<(tasknum))) diff --git a/include/mpc824x.h b/include/mpc824x.h index fca9371..cb84458 100644 --- a/include/mpc824x.h +++ b/include/mpc824x.h @@ -258,7 +258,7 @@ #define PLTR 0x8000000d /* PCI Latancy Timer Register */ #define PHTR 0x8000000e /* PCI Header Type Register */ #define BISTCTRL 0x8000000f /* BIST Control */ -#define LMBAR 0x80000010 /* Local Base Addres Register */ +#define LMBAR 0x80000010 /* Local Base Address Register */ #define PCSRBAR 0x80000014 /* PCSR Base Address Register */ #define ILR 0x8000003c /* PCI Interrupt Line Register */ #define IPR 0x8000003d /* Interrupt Pin Register */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index ea137c7..8292018 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -1000,6 +1000,7 @@ #define SDRAM_CFG_8_BE 0x00040000 #define SDRAM_CFG_NCAP 0x00020000 #define SDRAM_CFG_2T_EN 0x00008000 +#define SDRAM_CFG_HSE 0x00000008 #define SDRAM_CFG_BI 0x00000001 /* DDR_SDRAM_MODE - DDR SDRAM Mode Register diff --git a/include/mxc_gpio.h b/include/mxc_gpio.h index 002ba61..f673dce 100644 --- a/include/mxc_gpio.h +++ b/include/mxc_gpio.h @@ -24,6 +24,11 @@ #ifndef __MXC_GPIO_H #define __MXC_GPIO_H +/* Converts a GPIO port number and the internal bit position + * to the GPIO number + */ +#define MXC_GPIO_PORT_TO_NUM(port, bit) (((port - 1) << 5) + (bit & 0x1f)) + enum mxc_gpio_direction { MXC_GPIO_DIRECTION_IN, MXC_GPIO_DIRECTION_OUT, diff --git a/include/nand.h b/include/nand.h index 7459bd0..8d94b5c 100644 --- a/include/nand.h +++ b/include/nand.h @@ -114,8 +114,14 @@ typedef struct nand_erase_options nand_erase_options_t; int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, u_char *buffer); + +#define WITH_YAFFS_OOB (1 << 0) /* whether write with yaffs format. This flag + * is a 'mode' meaning it cannot be mixed with + * other flags */ +#define WITH_DROP_FFS (1 << 1) /* drop trailing all-0xff pages */ + int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, - u_char *buffer, int withoob); + u_char *buffer, int flags); int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts); #define NAND_LOCK_STATUS_TIGHT 0x01 diff --git a/include/part.h b/include/part.h index 3cdae02..1827767 100644 --- a/include/part.h +++ b/include/part.h @@ -49,6 +49,9 @@ typedef struct block_dev_desc { unsigned long start, lbaint_t blkcnt, const void *buffer); + unsigned long (*block_erase)(int dev, + unsigned long start, + lbaint_t blkcnt); void *priv; /* driver private struct pointer */ }block_dev_desc_t; @@ -93,6 +96,7 @@ typedef struct disk_partition { } disk_partition_t; /* Misc _get_dev functions */ +#ifdef CONFIG_PARTITIONS block_dev_desc_t* get_dev(char* ifname, int dev); block_dev_desc_t* ide_get_dev(int dev); block_dev_desc_t* sata_get_dev(int dev); @@ -107,7 +111,22 @@ int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t void print_part (block_dev_desc_t *dev_desc); void init_part (block_dev_desc_t *dev_desc); void dev_print(block_dev_desc_t *dev_desc); - +#else +static inline block_dev_desc_t* get_dev(char* ifname, int dev) { return NULL; } +static inline block_dev_desc_t* ide_get_dev(int dev) { return NULL; } +static inline block_dev_desc_t* sata_get_dev(int dev) { return NULL; } +static inline block_dev_desc_t* scsi_get_dev(int dev) { return NULL; } +static inline block_dev_desc_t* usb_stor_get_dev(int dev) { return NULL; } +static inline block_dev_desc_t* mmc_get_dev(int dev) { return NULL; } +static inline block_dev_desc_t* systemace_get_dev(int dev) { return NULL; } +static inline block_dev_desc_t* mg_disk_get_dev(int dev) { return NULL; } + +static inline int get_partition_info (block_dev_desc_t * dev_desc, int part, + disk_partition_t *info) { return -1; } +static inline void print_part (block_dev_desc_t *dev_desc) {} +static inline void init_part (block_dev_desc_t *dev_desc) {} +static inline void dev_print(block_dev_desc_t *dev_desc) {} +#endif #ifdef CONFIG_MAC_PARTITION /* disk/part_mac.c */ diff --git a/include/post.h b/include/post.h index 519cef1..3d23d22 100644 --- a/include/post.h +++ b/include/post.h @@ -147,6 +147,7 @@ unsigned long post_time_ms (unsigned long base); extern struct post_test post_list[]; extern unsigned int post_list_size; extern int post_hotkeys_pressed(void); +extern int memory_post_test(int flags); /* * If GCC is configured to use a version of GAS that supports @@ -186,6 +187,7 @@ extern int post_hotkeys_pressed(void); #define CONFIG_SYS_POST_BSPEC5 0x00100000 #define CONFIG_SYS_POST_CODEC 0x00200000 #define CONFIG_SYS_POST_COPROC 0x00400000 +#define CONFIG_SYS_POST_FLASH 0x00800000 #endif /* CONFIG_POST */ diff --git a/include/scsi.h b/include/scsi.h index aaafc9c..c52759c 100644 --- a/include/scsi.h +++ b/include/scsi.h @@ -185,6 +185,7 @@ void scsi_low_level_init(int busdevfunc); * functions residing inside cmd_scsi.c */ void scsi_init(void); +void scsi_scan(int mode); #define SCSI_IDENTIFY 0xC0 /* not used */ diff --git a/include/sdhci.h b/include/sdhci.h new file mode 100644 index 0000000..6d52ce9 --- /dev/null +++ b/include/sdhci.h @@ -0,0 +1,325 @@ +/* + * Copyright 2011, Marvell Semiconductor Inc. + * Lei Wen <leiwen@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Back ported to the 8xx platform (from the 8260 platform) by + * Murray.Jensen@cmst.csiro.au, 27-Jan-01. + */ +#ifndef __SDHCI_HW_H +#define __SDHCI_HW_H + +#include <asm/io.h> +/* + * Controller registers + */ + +#define SDHCI_DMA_ADDRESS 0x00 + +#define SDHCI_BLOCK_SIZE 0x04 +#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) + +#define SDHCI_BLOCK_COUNT 0x06 + +#define SDHCI_ARGUMENT 0x08 + +#define SDHCI_TRANSFER_MODE 0x0C +#define SDHCI_TRNS_DMA 0x01 +#define SDHCI_TRNS_BLK_CNT_EN 0x02 +#define SDHCI_TRNS_ACMD12 0x04 +#define SDHCI_TRNS_READ 0x10 +#define SDHCI_TRNS_MULTI 0x20 + +#define SDHCI_COMMAND 0x0E +#define SDHCI_CMD_RESP_MASK 0x03 +#define SDHCI_CMD_CRC 0x08 +#define SDHCI_CMD_INDEX 0x10 +#define SDHCI_CMD_DATA 0x20 +#define SDHCI_CMD_ABORTCMD 0xC0 + +#define SDHCI_CMD_RESP_NONE 0x00 +#define SDHCI_CMD_RESP_LONG 0x01 +#define SDHCI_CMD_RESP_SHORT 0x02 +#define SDHCI_CMD_RESP_SHORT_BUSY 0x03 + +#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) +#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) + +#define SDHCI_RESPONSE 0x10 + +#define SDHCI_BUFFER 0x20 + +#define SDHCI_PRESENT_STATE 0x24 +#define SDHCI_CMD_INHIBIT 0x00000001 +#define SDHCI_DATA_INHIBIT 0x00000002 +#define SDHCI_DOING_WRITE 0x00000100 +#define SDHCI_DOING_READ 0x00000200 +#define SDHCI_SPACE_AVAILABLE 0x00000400 +#define SDHCI_DATA_AVAILABLE 0x00000800 +#define SDHCI_CARD_PRESENT 0x00010000 +#define SDHCI_WRITE_PROTECT 0x00080000 + +#define SDHCI_HOST_CONTROL 0x28 +#define SDHCI_CTRL_LED 0x01 +#define SDHCI_CTRL_4BITBUS 0x02 +#define SDHCI_CTRL_HISPD 0x04 +#define SDHCI_CTRL_DMA_MASK 0x18 +#define SDHCI_CTRL_SDMA 0x00 +#define SDHCI_CTRL_ADMA1 0x08 +#define SDHCI_CTRL_ADMA32 0x10 +#define SDHCI_CTRL_ADMA64 0x18 +#define SDHCI_CTRL_8BITBUS 0x20 + +#define SDHCI_POWER_CONTROL 0x29 +#define SDHCI_POWER_ON 0x01 +#define SDHCI_POWER_180 0x0A +#define SDHCI_POWER_300 0x0C +#define SDHCI_POWER_330 0x0E + +#define SDHCI_BLOCK_GAP_CONTROL 0x2A + +#define SDHCI_WAKE_UP_CONTROL 0x2B +#define SDHCI_WAKE_ON_INT 0x01 +#define SDHCI_WAKE_ON_INSERT 0x02 +#define SDHCI_WAKE_ON_REMOVE 0x04 + +#define SDHCI_CLOCK_CONTROL 0x2C +#define SDHCI_DIVIDER_SHIFT 8 +#define SDHCI_DIVIDER_HI_SHIFT 6 +#define SDHCI_DIV_MASK 0xFF +#define SDHCI_DIV_MASK_LEN 8 +#define SDHCI_DIV_HI_MASK 0x300 +#define SDHCI_CLOCK_CARD_EN 0x0004 +#define SDHCI_CLOCK_INT_STABLE 0x0002 +#define SDHCI_CLOCK_INT_EN 0x0001 + +#define SDHCI_TIMEOUT_CONTROL 0x2E + +#define SDHCI_SOFTWARE_RESET 0x2F +#define SDHCI_RESET_ALL 0x01 +#define SDHCI_RESET_CMD 0x02 +#define SDHCI_RESET_DATA 0x04 + +#define SDHCI_INT_STATUS 0x30 +#define SDHCI_INT_ENABLE 0x34 +#define SDHCI_SIGNAL_ENABLE 0x38 +#define SDHCI_INT_RESPONSE 0x00000001 +#define SDHCI_INT_DATA_END 0x00000002 +#define SDHCI_INT_DMA_END 0x00000008 +#define SDHCI_INT_SPACE_AVAIL 0x00000010 +#define SDHCI_INT_DATA_AVAIL 0x00000020 +#define SDHCI_INT_CARD_INSERT 0x00000040 +#define SDHCI_INT_CARD_REMOVE 0x00000080 +#define SDHCI_INT_CARD_INT 0x00000100 +#define SDHCI_INT_ERROR 0x00008000 +#define SDHCI_INT_TIMEOUT 0x00010000 +#define SDHCI_INT_CRC 0x00020000 +#define SDHCI_INT_END_BIT 0x00040000 +#define SDHCI_INT_INDEX 0x00080000 +#define SDHCI_INT_DATA_TIMEOUT 0x00100000 +#define SDHCI_INT_DATA_CRC 0x00200000 +#define SDHCI_INT_DATA_END_BIT 0x00400000 +#define SDHCI_INT_BUS_POWER 0x00800000 +#define SDHCI_INT_ACMD12ERR 0x01000000 +#define SDHCI_INT_ADMA_ERROR 0x02000000 + +#define SDHCI_INT_NORMAL_MASK 0x00007FFF +#define SDHCI_INT_ERROR_MASK 0xFFFF8000 + +#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ + SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) +#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ + SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ + SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ + SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR) +#define SDHCI_INT_ALL_MASK ((unsigned int)-1) + +#define SDHCI_ACMD12_ERR 0x3C + +/* 3E-3F reserved */ + +#define SDHCI_CAPABILITIES 0x40 +#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F +#define SDHCI_TIMEOUT_CLK_SHIFT 0 +#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 +#define SDHCI_CLOCK_BASE_MASK 0x00003F00 +#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 +#define SDHCI_CLOCK_BASE_SHIFT 8 +#define SDHCI_MAX_BLOCK_MASK 0x00030000 +#define SDHCI_MAX_BLOCK_SHIFT 16 +#define SDHCI_CAN_DO_8BIT 0x00040000 +#define SDHCI_CAN_DO_ADMA2 0x00080000 +#define SDHCI_CAN_DO_ADMA1 0x00100000 +#define SDHCI_CAN_DO_HISPD 0x00200000 +#define SDHCI_CAN_DO_SDMA 0x00400000 +#define SDHCI_CAN_VDD_330 0x01000000 +#define SDHCI_CAN_VDD_300 0x02000000 +#define SDHCI_CAN_VDD_180 0x04000000 +#define SDHCI_CAN_64BIT 0x10000000 + +#define SDHCI_CAPABILITIES_1 0x44 + +#define SDHCI_MAX_CURRENT 0x48 + +/* 4C-4F reserved for more max current */ + +#define SDHCI_SET_ACMD12_ERROR 0x50 +#define SDHCI_SET_INT_ERROR 0x52 + +#define SDHCI_ADMA_ERROR 0x54 + +/* 55-57 reserved */ + +#define SDHCI_ADMA_ADDRESS 0x58 + +/* 60-FB reserved */ + +#define SDHCI_SLOT_INT_STATUS 0xFC + +#define SDHCI_HOST_VERSION 0xFE +#define SDHCI_VENDOR_VER_MASK 0xFF00 +#define SDHCI_VENDOR_VER_SHIFT 8 +#define SDHCI_SPEC_VER_MASK 0x00FF +#define SDHCI_SPEC_VER_SHIFT 0 +#define SDHCI_SPEC_100 0 +#define SDHCI_SPEC_200 1 +#define SDHCI_SPEC_300 2 + +/* + * End of controller registers. + */ + +#define SDHCI_MAX_DIV_SPEC_200 256 +#define SDHCI_MAX_DIV_SPEC_300 2046 + +/* + * quirks + */ +#define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0) + +/* + * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. + */ +#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) +#define SDHCI_DEFAULT_BOUNDARY_ARG (7) +struct sdhci_ops { +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS + u32 (*read_l)(struct sdhci_host *host, int reg); + u16 (*read_w)(struct sdhci_host *host, int reg); + u8 (*read_b)(struct sdhci_host *host, int reg); + void (*write_l)(struct sdhci_host *host, u32 val, int reg); + void (*write_w)(struct sdhci_host *host, u16 val, int reg); + void (*write_b)(struct sdhci_host *host, u8 val, int reg); +#endif +}; + +struct sdhci_host { + char *name; + void *ioaddr; + unsigned int quirks; + unsigned int version; + unsigned int clock; + const struct sdhci_ops *ops; +}; + +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS + +static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) +{ + if (unlikely(host->ops->write_l)) + host->ops->write_l(host, val, reg); + else + writel(val, host->ioaddr + reg); +} + +static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) +{ + if (unlikely(host->ops->write_w)) + host->ops->write_w(host, val, reg); + else + writew(val, host->ioaddr + reg); +} + +static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) +{ + if (unlikely(host->ops->write_b)) + host->ops->write_b(host, val, reg); + else + writeb(val, host->ioaddr + reg); +} + +static inline u32 sdhci_readl(struct sdhci_host *host, int reg) +{ + if (unlikely(host->ops->read_l)) + return host->ops->read_l(host, reg); + else + return readl(host->ioaddr + reg); +} + +static inline u16 sdhci_readw(struct sdhci_host *host, int reg) +{ + if (unlikely(host->ops->read_w)) + return host->ops->read_w(host, reg); + else + return readw(host->ioaddr + reg); +} + +static inline u8 sdhci_readb(struct sdhci_host *host, int reg) +{ + if (unlikely(host->ops->read_b)) + return host->ops->read_b(host, reg); + else + return readb(host->ioaddr + reg); +} + +#else + +static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) +{ + writel(val, host->ioaddr + reg); +} + +static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) +{ + writew(val, host->ioaddr + reg); +} + +static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) +{ + writeb(val, host->ioaddr + reg); +} +static inline u32 sdhci_readl(struct sdhci_host *host, int reg) +{ + return readl(host->ioaddr + reg); +} + +static inline u16 sdhci_readw(struct sdhci_host *host, int reg) +{ + return readw(host->ioaddr + reg); +} + +static inline u8 sdhci_readb(struct sdhci_host *host, int reg) +{ + return readb(host->ioaddr + reg); +} +#endif + +int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk); +#endif /* __SDHCI_HW_H */ diff --git a/include/search.h b/include/search.h index c827d4d..b4edd43 100644 --- a/include/search.h +++ b/include/search.h @@ -39,7 +39,7 @@ typedef enum { } ACTION; typedef struct entry { - char *key; + const char *key; char *data; } ENTRY; diff --git a/include/serial.h b/include/serial.h index f21d961..ff1ce99 100644 --- a/include/serial.h +++ b/include/serial.h @@ -1,12 +1,12 @@ #ifndef __SERIAL_H__ #define __SERIAL_H__ +#include <post.h> + #define NAMESIZE 16 -#define CTLRSIZE 8 struct serial_device { char name[NAMESIZE]; - char ctlr[CTLRSIZE]; int (*init) (void); int (*uninit) (void); @@ -15,6 +15,9 @@ struct serial_device { int (*tstc) (void); void (*putc) (const char c); void (*puts) (const char *s); +#if CONFIG_POST & CONFIG_SYS_POST_UART + void (*loop) (int); +#endif struct serial_device *next; }; @@ -71,6 +74,15 @@ extern struct serial_device serial_ffuart_device; extern struct serial_device serial_btuart_device; extern struct serial_device serial_stuart_device; +#if defined(CONFIG_SYS_BFIN_UART) +extern void serial_register_bfin_uart(void); +extern struct serial_device bfin_serial0_device; +extern struct serial_device bfin_serial1_device; +extern struct serial_device bfin_serial2_device; +extern struct serial_device bfin_serial3_device; +#endif + +extern void serial_register(struct serial_device *); extern void serial_initialize(void); extern void serial_stdio_init(void); extern int serial_assign(char * name); diff --git a/include/spartan2.h b/include/spartan2.h index 8959f90..e257a67 100644 --- a/include/spartan2.h +++ b/include/spartan2.h @@ -27,9 +27,9 @@ #include <xilinx.h> -extern int Spartan2_load( Xilinx_desc *desc, void *image, size_t size ); -extern int Spartan2_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -extern int Spartan2_info( Xilinx_desc *desc ); +extern int Spartan2_load(Xilinx_desc *desc, const void *image, size_t size); +extern int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +extern int Spartan2_info(Xilinx_desc *desc); /* Slave Parallel Implementation function table */ typedef struct { diff --git a/include/spartan3.h b/include/spartan3.h index 0f0b400..67ede4b 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -27,9 +27,9 @@ #include <xilinx.h> -extern int Spartan3_load( Xilinx_desc *desc, void *image, size_t size ); -extern int Spartan3_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -extern int Spartan3_info( Xilinx_desc *desc ); +extern int Spartan3_load(Xilinx_desc *desc, const void *image, size_t size); +extern int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +extern int Spartan3_info(Xilinx_desc *desc); /* Slave Parallel Implementation function table */ typedef struct { diff --git a/include/spi_flash.h b/include/spi_flash.h index a384071..2671ab5 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -31,8 +31,11 @@ struct spi_flash { const char *name; + /* Total flash size */ u32 size; - + /* Write (page) size */ + u32 page_size; + /* Erase (sector) size */ u32 sector_size; int (*read)(struct spi_flash *flash, u32 offset, diff --git a/include/stdio_dev.h b/include/stdio_dev.h index 82ad463..23e0ee1 100644 --- a/include/stdio_dev.h +++ b/include/stdio_dev.h @@ -105,9 +105,6 @@ int drv_arm_dcc_init(void); #ifdef CONFIG_LCD int drv_lcd_init (void); #endif -#ifdef CONFIG_VFD -int drv_vfd_init (void); -#endif #if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) int drv_video_init (void); #endif diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h index d2c90a6..69006e2 100644 --- a/include/ubi_uboot.h +++ b/include/ubi_uboot.h @@ -191,9 +191,6 @@ static inline long IS_ERR(const void *ptr) return IS_ERR_VALUE((unsigned long)ptr); } -/* Force a compilation error if condition is true */ -#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)])) - /* module */ #define THIS_MODULE 0 #define try_module_get(...) 1 diff --git a/include/version.h b/include/version.h index a34291a..129acef 100644 --- a/include/version.h +++ b/include/version.h @@ -24,8 +24,20 @@ #ifndef __VERSION_H__ #define __VERSION_H__ +#include <timestamp.h> + #ifndef DO_DEPS_ONLY #include "version_autogenerated.h" #endif +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \ + U_BOOT_TIME ")" CONFIG_IDENT_STRING + +#ifndef __ASSEMBLY__ +extern const char version_string[]; +#endif /* __ASSEMBLY__ */ #endif /* __VERSION_H__ */ diff --git a/include/vfd_logo.h b/include/vfd_logo.h deleted file mode 100644 index c41867a..0000000 --- a/include/vfd_logo.h +++ /dev/null @@ -1,1032 +0,0 @@ -/* - * Automatically generated by "tools/bmp_logo" - * - * DO NOT EDIT - * - */ - - -#ifndef __VFD_LOGO_H__ -#define __VFD_LOGO_H__ - -#define VFD_LOGO_WIDTH 112 -#define VFD_LOGO_HEIGHT 72 -#define VFD_LOGO_COLORS 0 -#define VFD_LOGO_OFFSET 0 - - -unsigned char vfd_test_logo_bitmap[] = { - 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, - 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, - 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, - 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFD, - 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, - 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, - 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, - 0xDF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, - 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, - 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD, - 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, - 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, - 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, - 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, - 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD, - 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, - 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, - 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, - 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, - 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD, - 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, - 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, - 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, - 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, - 0xFD, 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFD, 0xDF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFD, - 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, - 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, - 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, - 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFD, - 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, - 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, - 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, - 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFD, 0xDD, 0xDF, 0xDD, 0xDD, 0xFF, 0xFD, - 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, - 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFD, - 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, - 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDF, 0xFD, - 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, - 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, - 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, - 0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDF, 0xFD, - 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, - 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, - 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, - 0xFD, 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFD, 0xDF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xDD, 0xDD, 0xDF, 0xFD, 0xDD, 0xDF, 0xFD, - 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, - 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, - 0xDD, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFF, - 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, - 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, - 0xFD, 0xDD, 0xDD, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, - 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, - 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, - 0xDD, 0xDF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, - 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, - 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, - 0xFD, 0xDD, 0xDD, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD, - 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, - 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, - 0xDD, 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF, - 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, - 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, - 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 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0x99, 0x9F, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF, - 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99, - 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, - 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF, - 0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9, - 0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, - 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, - 0x99, 0x99, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF, - 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99, - 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, - 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, - 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, - 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99, - 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99, - 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, - 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, - 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xF9, - 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, - 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, - 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, - 0x9F, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, - 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, - 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9, - 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, - 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, - 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, - 0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, - 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, - 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF, - 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9, - 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, - 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, - 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, - 0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, - 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9, - 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, - 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, - 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, - 0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, - 0xF9, 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x9F, 0xFF, - 0xFF, 0xFF, 0xFF, 0xF9, 0x9F, 0xFF, 0xFF, 0xFF, - 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xF9, - 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, - 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, - 0x99, 0x9F, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, - 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xF9, - 0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, - 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, - 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F, - 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xF9, 0x99, 0x9F, 0x99, 0x99, 0xFF, 0xF9, - 0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, - 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xF9, - 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F, - 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x9F, 0xF9, - 0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, - 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xF9, - 0x99, 0x99, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F, - 0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x9F, 0xF9, - 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, - 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xF9, - 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, - 0xF9, 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x9F, 0xFF, - 0xFF, 0xFF, 0xFF, 0xF9, 0x9F, 0xFF, 0xFF, 0xFF, - 0xFF, 0x99, 0x99, 0x9F, 0xF9, 0x99, 0x9F, 0xF9, - 0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, - 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, - 0x99, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xFF, - 0x99, 0x99, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, - 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, - 0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9, - 0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, - 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, - 0x99, 0x9F, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF, - 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99, - 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, - 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF, - 0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9, - 0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, - 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, - 0x99, 0x99, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF, - 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99, - 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, - 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, - 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99, - 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99, -}; - -#endif /* __VFD_LOGO_H__ */ diff --git a/include/virtex2.h b/include/virtex2.h index 89d7d76..4717e0c 100644 --- a/include/virtex2.h +++ b/include/virtex2.h @@ -28,9 +28,9 @@ #include <xilinx.h> -extern int Virtex2_load( Xilinx_desc *desc, void *image, size_t size ); -extern int Virtex2_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -extern int Virtex2_info( Xilinx_desc *desc ); +extern int Virtex2_load(Xilinx_desc *desc, const void *image, size_t size); +extern int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +extern int Virtex2_info(Xilinx_desc *desc); /* * Slave SelectMap Implementation function table. diff --git a/include/xilinx.h b/include/xilinx.h index 2cb2e5b..5f25b7a 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -81,9 +81,9 @@ typedef struct { /* typedef Xilinx_desc */ /* Generic Xilinx Functions *********************************************************************/ -extern int xilinx_load( Xilinx_desc *desc, void *image, size_t size ); -extern int xilinx_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -extern int xilinx_info( Xilinx_desc *desc ); +extern int xilinx_load(Xilinx_desc *desc, const void *image, size_t size); +extern int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +extern int xilinx_info(Xilinx_desc *desc); /* Board specific implementation specific function types *********************************************************************/ diff --git a/lib/Makefile b/lib/Makefile index afa6914..884f64c 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libgeneric.o +ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_ADDR_MAP) += addr_map.o COBJS-$(CONFIG_BZIP2) += bzlib.o COBJS-$(CONFIG_BZIP2) += bzlib_crctable.o @@ -35,9 +36,7 @@ COBJS-$(CONFIG_USB_TTY) += circbuf.o COBJS-y += crc7.o COBJS-y += crc16.o COBJS-y += crc32.o -COBJS-y += ctype.o COBJS-y += display_options.o -COBJS-y += div64.o COBJS-y += errno.o COBJS-$(CONFIG_GZIP) += gunzip.o COBJS-y += hashtable.o @@ -48,11 +47,15 @@ COBJS-y += net_utils.o COBJS-y += qsort.o COBJS-$(CONFIG_SHA1) += sha1.o COBJS-$(CONFIG_SHA256) += sha256.o -COBJS-y += string.o COBJS-y += strmhz.o +COBJS-$(CONFIG_RBTREE) += rbtree.o +endif + +COBJS-y += ctype.o +COBJS-y += div64.o +COBJS-y += string.o COBJS-y += time.o COBJS-y += vsprintf.o -COBJS-$(CONFIG_RBTREE) += rbtree.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/lib/display_options.c b/lib/display_options.c index d0480f5..694d2f2 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -23,13 +23,12 @@ #include <config.h> #include <common.h> +#include <version.h> #include <linux/ctype.h> #include <asm/io.h> int display_options (void) { - extern char version_string[]; - #if defined(BUILD_TAG) printf ("\n\n%s, Build: %s\n\n", version_string, BUILD_TAG); #else diff --git a/lib/hashtable.c b/lib/hashtable.c index 19d5b15..026dbca 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -155,7 +155,7 @@ void hdestroy_r(struct hsearch_data *htab) if (htab->table[i].used > 0) { ENTRY *ep = &htab->table[i].entry; - free(ep->key); + free((void *)ep->key); free(ep->data); } } @@ -416,7 +416,7 @@ int hdelete_r(const char *key, struct hsearch_data *htab) /* free used ENTRY */ debug("hdelete: DELETING key \"%s\"\n", key); - free(ep->key); + free((void *)ep->key); free(ep->data); htab->table[idx].used = -1; @@ -564,7 +564,7 @@ ssize_t hexport_r(struct hsearch_data *htab, const char sep, * export sorted list of result data */ for (i = 0, p = res; i < n; ++i) { - char *s; + const char *s; s = list[i]->key; while (*s) diff --git a/lib/libfdt/fdt.c b/lib/libfdt/fdt.c index b09ea6f..4157b21 100644 --- a/lib/libfdt/fdt.c +++ b/lib/libfdt/fdt.c @@ -153,6 +153,15 @@ int _fdt_check_node_offset(const void *fdt, int offset) return offset; } +int _fdt_check_prop_offset(const void *fdt, int offset) +{ + if ((offset < 0) || (offset % FDT_TAGSIZE) + || (fdt_next_tag(fdt, offset, &offset) != FDT_PROP)) + return -FDT_ERR_BADOFFSET; + + return offset; +} + int fdt_next_node(const void *fdt, int offset, int *depth) { int nextoffset = 0; diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c index 1e1e322..1933010 100644 --- a/lib/libfdt/fdt_ro.c +++ b/lib/libfdt/fdt_ro.c @@ -109,6 +109,30 @@ int fdt_num_mem_rsv(const void *fdt) return i; } +static int _nextprop(const void *fdt, int offset) +{ + uint32_t tag; + int nextoffset; + + do { + tag = fdt_next_tag(fdt, offset, &nextoffset); + + switch (tag) { + case FDT_END: + if (nextoffset >= 0) + return -FDT_ERR_BADSTRUCTURE; + else + return nextoffset; + + case FDT_PROP: + return offset; + } + offset = nextoffset; + } while (tag == FDT_NOP); + + return -FDT_ERR_NOTFOUND; +} + int fdt_subnode_offset_namelen(const void *fdt, int offset, const char *name, int namelen) { @@ -198,52 +222,66 @@ const char *fdt_get_name(const void *fdt, int nodeoffset, int *len) return NULL; } -const struct fdt_property *fdt_get_property_namelen(const void *fdt, - int nodeoffset, - const char *name, - int namelen, int *lenp) +int fdt_first_property_offset(const void *fdt, int nodeoffset) +{ + int offset; + + if ((offset = _fdt_check_node_offset(fdt, nodeoffset)) < 0) + return offset; + + return _nextprop(fdt, offset); +} + +int fdt_next_property_offset(const void *fdt, int offset) +{ + if ((offset = _fdt_check_prop_offset(fdt, offset)) < 0) + return offset; + + return _nextprop(fdt, offset); +} + +const struct fdt_property *fdt_get_property_by_offset(const void *fdt, + int offset, + int *lenp) { - uint32_t tag; - const struct fdt_property *prop; - int offset, nextoffset; int err; + const struct fdt_property *prop; - if (((err = fdt_check_header(fdt)) != 0) - || ((err = _fdt_check_node_offset(fdt, nodeoffset)) < 0)) - goto fail; + if ((err = _fdt_check_prop_offset(fdt, offset)) < 0) { + if (lenp) + *lenp = err; + return NULL; + } - nextoffset = err; - do { - offset = nextoffset; + prop = _fdt_offset_ptr(fdt, offset); - tag = fdt_next_tag(fdt, offset, &nextoffset); - switch (tag) { - case FDT_END: - if (nextoffset < 0) - err = nextoffset; - else - /* FDT_END tag with unclosed nodes */ - err = -FDT_ERR_BADSTRUCTURE; - goto fail; + if (lenp) + *lenp = fdt32_to_cpu(prop->len); - case FDT_PROP: - prop = _fdt_offset_ptr(fdt, offset); - if (_fdt_string_eq(fdt, fdt32_to_cpu(prop->nameoff), - name, namelen)) { - /* Found it! */ - if (lenp) - *lenp = fdt32_to_cpu(prop->len); - - return prop; - } + return prop; +} + +const struct fdt_property *fdt_get_property_namelen(const void *fdt, + int offset, + const char *name, + int namelen, int *lenp) +{ + for (offset = fdt_first_property_offset(fdt, offset); + (offset >= 0); + (offset = fdt_next_property_offset(fdt, offset))) { + const struct fdt_property *prop; + + if (!(prop = fdt_get_property_by_offset(fdt, offset, lenp))) { + offset = -FDT_ERR_INTERNAL; break; } - } while ((tag != FDT_BEGIN_NODE) && (tag != FDT_END_NODE)); + if (_fdt_string_eq(fdt, fdt32_to_cpu(prop->nameoff), + name, namelen)) + return prop; + } - err = -FDT_ERR_NOTFOUND; - fail: if (lenp) - *lenp = err; + *lenp = offset; return NULL; } @@ -267,6 +305,19 @@ const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, return prop->data; } +const void *fdt_getprop_by_offset(const void *fdt, int offset, + const char **namep, int *lenp) +{ + const struct fdt_property *prop; + + prop = fdt_get_property_by_offset(fdt, offset, lenp); + if (!prop) + return NULL; + if (namep) + *namep = fdt_string(fdt, fdt32_to_cpu(prop->nameoff)); + return prop->data; +} + const void *fdt_getprop(const void *fdt, int nodeoffset, const char *name, int *lenp) { @@ -278,9 +329,14 @@ uint32_t fdt_get_phandle(const void *fdt, int nodeoffset) const uint32_t *php; int len; - php = fdt_getprop(fdt, nodeoffset, "linux,phandle", &len); - if (!php || (len != sizeof(*php))) - return 0; + /* FIXME: This is a bit sub-optimal, since we potentially scan + * over all the properties twice. */ + php = fdt_getprop(fdt, nodeoffset, "phandle", &len); + if (!php || (len != sizeof(*php))) { + php = fdt_getprop(fdt, nodeoffset, "linux,phandle", &len); + if (!php || (len != sizeof(*php))) + return 0; + } return fdt32_to_cpu(*php); } @@ -440,11 +496,27 @@ int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle) { + int offset; + if ((phandle == 0) || (phandle == -1)) return -FDT_ERR_BADPHANDLE; - phandle = cpu_to_fdt32(phandle); - return fdt_node_offset_by_prop_value(fdt, -1, "linux,phandle", - &phandle, sizeof(phandle)); + + FDT_CHECK_HEADER(fdt); + + /* FIXME: The algorithm here is pretty horrible: we + * potentially scan each property of a node in + * fdt_get_phandle(), then if that didn't find what + * we want, we scan over them again making our way to the next + * node. Still it's the easiest to implement approach; + * performance can come later. */ + for (offset = fdt_next_node(fdt, -1, NULL); + offset >= 0; + offset = fdt_next_node(fdt, offset, NULL)) { + if (fdt_get_phandle(fdt, offset) == phandle) + return offset; + } + + return offset; /* error from fdt_next_node() */ } static int _fdt_stringlist_contains(const char *strlist, int listlen, diff --git a/lib/libfdt/libfdt_internal.h b/lib/libfdt/libfdt_internal.h index d2dcbd6..381133b 100644 --- a/lib/libfdt/libfdt_internal.h +++ b/lib/libfdt/libfdt_internal.h @@ -63,6 +63,7 @@ } int _fdt_check_node_offset(const void *fdt, int offset); +int _fdt_check_prop_offset(const void *fdt, int offset); const char *_fdt_find_string(const char *strtab, int tabsize, const char *s); int _fdt_node_end_offset(void *fdt, int nodeoffset); diff --git a/lib/string.c b/lib/string.c index b375b81..2c4f0ec 100644 --- a/lib/string.c +++ b/lib/string.c @@ -467,6 +467,9 @@ void * memcpy(void *dest, const void *src, size_t count) unsigned long *dl = (unsigned long *)dest, *sl = (unsigned long *)src; char *d8, *s8; + if (src == dest) + return dest; + /* while all data is aligned (common case), copy a word at a time */ if ( (((ulong)dest | (ulong)src) & (sizeof(*dl) - 1)) == 0) { while (count >= sizeof(*dl)) { @@ -497,6 +500,9 @@ void * memmove(void * dest,const void *src,size_t count) { char *tmp, *s; + if (src == dest) + return dest; + if (dest <= src) { tmp = (char *) dest; s = (char *) src; diff --git a/lib/vsprintf.c b/lib/vsprintf.c index 3b924ec..c029fbb 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -727,4 +727,6 @@ void panic(const char *fmt, ...) udelay (100000); /* allow messages to go out */ do_reset (NULL, 0, 0, NULL); #endif + while (1) + ; } @@ -148,7 +148,7 @@ fi echo "/* Automatically generated - do not edit */" >>config.h for i in ${TARGETS} ; do - i="`echo ${i} | sed '/=/ {s/=/\t/;q } ; { s/$/\t1/ }'`" + i="`echo ${i} | sed '/=/ {s/=/ /;q; } ; { s/$/ 1/; }'`" echo "#define CONFIG_${i}" >>config.h ; done diff --git a/mmc_spl/board/samsung/smdkv310/Makefile b/mmc_spl/board/samsung/smdkv310/Makefile index f1ce066..fdfd015 100644 --- a/mmc_spl/board/samsung/smdkv310/Makefile +++ b/mmc_spl/board/samsung/smdkv310/Makefile @@ -35,12 +35,12 @@ LDSCRIPT= $(TOPDIR)/mmc_spl/board/$(BOARDDIR)/u-boot.lds LDFLAGS = -Bstatic -T $(mmcobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS) AFLAGS += -DCONFIG_MMC_SPL CFLAGS += -DCONFIG_MMC_SPL -CFLAGS += -DCONFIG_PRELOADER +CFLAGS += -DCONFIG_SPL_BUILD SOBJS = start.o mem_setup.o lowlevel_init.o COBJS = mmc_boot.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(OBJTREE)/mmc_spl/board/$(BOARDDIR) @@ -76,25 +76,25 @@ $(mmcobj)u-boot.lds: $(LDSCRIPT) # create symbolic links for common files # from cpu directory -$(obj)start.S: +start.S: @rm -f $@ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/start.S $@ # from board directory -$(obj)mem_setup.S: +mem_setup.S: @rm -f $@ @ln -s $(TOPDIR)/board/samsung/smdkv310/mem_setup.S $@ -$(obj)lowlevel_init.S: +lowlevel_init.S: @rm -f $@ @ln -s $(TOPDIR)/board/samsung/smdkv310/lowlevel_init.S $@ ######################################################################### -$(obj)%.o: $(obj)%.S +$(obj)%.o: %.S $(CC) $(AFLAGS) -c -o $@ $< -$(obj)%.o: $(obj)%.c +$(obj)%.o: %.c $(CC) $(CFLAGS) -c -o $@ $< # defines $(obj).depend target diff --git a/nand_spl/board/davinci/da8xxevm/Makefile b/nand_spl/board/davinci/da8xxevm/Makefile index c3cb1bb..b3f4bd6 100644 --- a/nand_spl/board/davinci/da8xxevm/Makefile +++ b/nand_spl/board/davinci/da8xxevm/Makefile @@ -33,8 +33,8 @@ nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL +AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL SOBJS = start.o _udivsi3.o _divsi3.o COBJS = cpu.o davinci_nand.o ns16550.o div0.o davinci_pinmux.o psc.o \ diff --git a/nand_spl/board/freescale/mx31pdk/Makefile b/nand_spl/board/freescale/mx31pdk/Makefile index 984f959..e6ec10a 100644 --- a/nand_spl/board/freescale/mx31pdk/Makefile +++ b/nand_spl/board/freescale/mx31pdk/Makefile @@ -8,8 +8,8 @@ nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL +AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL SOBJS = start.o lowlevel_init.o COBJS = nand_boot_fsl_nfc.o diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile new file mode 100644 index 0000000..168e868 --- /dev/null +++ b/nand_spl/board/freescale/p1023rds/Makefile @@ -0,0 +1,132 @@ +# +# Copyright 2010-2011 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +NAND_SPL := y +PAD_TO := 0xfff01000 + +include $(TOPDIR)/config.mk + +nandobj := $(OBJTREE)/nand_spl/ + +LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ + $(LDFLAGS) $(LDFLAGS_FINAL) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o resetvec.o +COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(nandobj)board/$(BOARDDIR) + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + +# create symbolic links for common files + +$(obj)cache.c: + @rm -f $(obj)cache.c + ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c + +$(obj)cpu_init_early.c: + @rm -f $(obj)cpu_init_early.c + ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c + +$(obj)cpu_init_nand.c: + @rm -f $(obj)cpu_init_nand.c + ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c + +$(obj)fsl_law.c: + @rm -f $(obj)fsl_law.c + ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c + +$(obj)law.c: + @rm -f $(obj)law.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c + +$(obj)nand_boot_fsl_elbc.c: + @rm -f $(obj)nand_boot_fsl_elbc.c + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ + $(obj)nand_boot_fsl_elbc.c + +$(obj)ns16550.c: + @rm -f $(obj)ns16550.c + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + +$(obj)resetvec.S: + @rm -f $(obj)resetvec.S + ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S + +$(obj)fixed_ivor.S: + @rm -f $(obj)fixed_ivor.S + ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S + +$(obj)start.S: $(obj)fixed_ivor.S + @rm -f $(obj)start.S + ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S + +$(obj)tlb.c: + @rm -f $(obj)tlb.c + ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c + +$(obj)tlb_table.c: + @rm -f $(obj)tlb_table.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c + +ifneq ($(OBJTREE), $(SRCTREE)) +$(obj)nand_boot.c: + @rm -f $(obj)nand_boot.c + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +endif + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c new file mode 100644 index 0000000..0065c87 --- /dev/null +++ b/nand_spl/board/freescale/p1023rds/nand_boot.c @@ -0,0 +1,99 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Roy Zang <tie-fei.zang@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ns16550.h> +#include <asm/io.h> +#include <nand.h> +#include <asm/fsl_law.h> + +/* Fixed sdram init -- doesn't use serial presence detect. */ +void sdram_init(void) +{ + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + + set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); + + out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); + out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); + out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); + out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); + out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); + out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); + out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2); + out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); + out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); + out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); + out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); + out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); + out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); + out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); + out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); + out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); + out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1); + out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2); + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, bus_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + /* Initialize the DDR3 */ + sdram_init(); + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} diff --git a/nand_spl/board/karo/tx25/Makefile b/nand_spl/board/karo/tx25/Makefile index 8bc54d1..0336346 100644 --- a/nand_spl/board/karo/tx25/Makefile +++ b/nand_spl/board/karo/tx25/Makefile @@ -29,8 +29,8 @@ nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL +AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL SOBJS = start.o lowlevel_init.o COBJS = nand_boot_fsl_nfc.o diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c index 9545a9a..4683c7c 100644 --- a/nand_spl/nand_boot.c +++ b/nand_spl/nand_boot.c @@ -122,10 +122,15 @@ static int nand_is_bad_block(struct mtd_info *mtd, int block) nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB); /* - * Read one byte + * Read one byte (or two if it's a 16 bit chip). */ - if (readb(this->IO_ADDR_R) != 0xff) - return 1; + if (this->options & NAND_BUSWIDTH_16) { + if (readw(this->IO_ADDR_R) != 0xffff) + return 1; + } else { + if (readb(this->IO_ADDR_R) != 0xff) + return 1; + } return 0; } diff --git a/net/bootp.c b/net/bootp.c index 4db63cb..45eaab1 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -228,6 +228,11 @@ static void BootpVendorFieldProcess (u8 * ext) NetOurNISDomain[size] = 0; } break; +#if defined(CONFIG_CMD_SNTP) && defined(CONFIG_BOOTP_NTPSERVER) + case 42: /* NTP server IP */ + NetCopyIP(&NetNtpServerIP, (IPaddr_t *) (ext + 2)); + break; +#endif /* Application layer fields */ case 43: /* Vendor specific info - Not yet supported */ /* @@ -278,6 +283,11 @@ static void BootpVendorProcess (u8 * ext, int size) if (NetBootFileSize) debug("NetBootFileSize: %d\n", NetBootFileSize); + +#if defined(CONFIG_CMD_SNTP) && defined(CONFIG_BOOTP_NTPSERVER) + if (NetNtpServerIP) + debug("NetNtpServerIP : %pI4\n", &NetNtpServerIP); +#endif } /* * Handle a BOOTP received packet. @@ -538,6 +548,11 @@ static int BootpExtended (u8 * e) *e++ = 32; e += 32; #endif +#if defined(CONFIG_BOOTP_NTPSERVER) + *e++ = 42; + *e++ = 4; + e += 4; +#endif *e++ = 255; /* End of the list */ @@ -521,7 +521,6 @@ char *eth_get_name (void) #warning Ethernet driver is deprecated. Please update to use CONFIG_NET_MULTI -extern int at91rm9200_miiphy_initialize(bd_t *bis); extern int mcf52x2_miiphy_initialize(bd_t *bis); extern int ns7520_miiphy_initialize(bd_t *bis); @@ -532,9 +531,6 @@ int eth_initialize(bd_t *bis) miiphy_init(); #endif -#if defined(CONFIG_AT91RM9200) - at91rm9200_miiphy_initialize(bis); -#endif #if defined(CONFIG_MCF52x2) mcf52x2_miiphy_initialize(bis); #endif diff --git a/onenand_ipl/board/apollon/Makefile b/onenand_ipl/board/apollon/Makefile index 5397186..3bc9920 100644 --- a/onenand_ipl/board/apollon/Makefile +++ b/onenand_ipl/board/apollon/Makefile @@ -4,8 +4,8 @@ include $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/config.mk LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS) -AFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL -CFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL +AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_ONENAND_IPL +CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_ONENAND_IPL OBJCFLAGS += --gap-fill=0x00 SOBJS := low_levelinit.o diff --git a/onenand_ipl/board/vpac270/Makefile b/onenand_ipl/board/vpac270/Makefile index 7300692..f850ddd 100644 --- a/onenand_ipl/board/vpac270/Makefile +++ b/onenand_ipl/board/vpac270/Makefile @@ -4,8 +4,8 @@ include $(TOPDIR)/board/$(BOARDDIR)/config.mk LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS) -AFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL -CFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL +AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_ONENAND_IPL +CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_ONENAND_IPL OBJCFLAGS += --gap-fill=0x00 SOBJS += start.o diff --git a/post/board/lwmon/sysmon.c b/post/board/lwmon/sysmon.c index fc828b2..72224c6 100644 --- a/post/board/lwmon/sysmon.c +++ b/post/board/lwmon/sysmon.c @@ -133,7 +133,7 @@ static sysmon_table_t sysmon_table[] = {"+ 5 V standby", "V", &sysmon_pic, NULL, NULL, 100, 1000, 0, 6040, 0xFF, 0xC8, 0xDE, 0, 0xC8, 0xDE, 0, 0x7C}, }; -static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]); +static int sysmon_table_size = ARRAY_SIZE(sysmon_table); static int conversion_done = 0; diff --git a/post/cpu/mpc8xx/ether.c b/post/cpu/mpc8xx/ether.c index 43ea817..fcbb300 100644 --- a/post/cpu/mpc8xx/ether.c +++ b/post/cpu/mpc8xx/ether.c @@ -67,8 +67,6 @@ static int ctlr_list[][2] = { {CTLR_SCC, 1} }; static int ctlr_list[][2] = { }; #endif -#define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0])) - static struct { void (*init) (int index); void (*halt) (int index); @@ -618,7 +616,7 @@ int ether_post_test (int flags) ctlr_proc[CTLR_SCC].send = scc_send; ctlr_proc[CTLR_SCC].recv = scc_recv; - for (i = 0; i < CTRL_LIST_SIZE; i++) { + for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) { if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) { res = -1; } diff --git a/post/cpu/mpc8xx/spr.c b/post/cpu/mpc8xx/spr.c index db84dbe..4c1e2af 100644 --- a/post/cpu/mpc8xx/spr.c +++ b/post/cpu/mpc8xx/spr.c @@ -108,8 +108,7 @@ static struct {826, "MD_DBRAM1", 0x00000000, 0x00000000}, }; -static int spr_test_list_size = - sizeof (spr_test_list) / sizeof (spr_test_list[0]); +static int spr_test_list_size = ARRAY_SIZE(spr_test_list); int spr_post_test (int flags) { diff --git a/post/cpu/mpc8xx/uart.c b/post/cpu/mpc8xx/uart.c index f351ac0..7a7a62a 100644 --- a/post/cpu/mpc8xx/uart.c +++ b/post/cpu/mpc8xx/uart.c @@ -61,8 +61,6 @@ static int ctlr_list[][2] = static int ctlr_list[][2] = { }; #endif -#define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0])) - static struct { void (*init) (int index); void (*halt) (int index); @@ -540,7 +538,7 @@ int uart_post_test (int flags) ctlr_proc[CTLR_SCC].putc = scc_putc; ctlr_proc[CTLR_SCC].getc = scc_getc; - for (i = 0; i < CTRL_LIST_SIZE; i++) { + for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) { if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) { res = -1; } diff --git a/post/cpu/ppc4xx/spr.c b/post/cpu/ppc4xx/spr.c index cb18b64..3f5e965 100644 --- a/post/cpu/ppc4xx/spr.c +++ b/post/cpu/ppc4xx/spr.c @@ -156,8 +156,7 @@ static struct { {0x3f3, "DBDR", 0x00000000, 0x00000000}, }; -static int spr_test_list_size = - sizeof (spr_test_list) / sizeof (spr_test_list[0]); +static int spr_test_list_size = ARRAY_SIZE(spr_test_list); int spr_post_test (int flags) { diff --git a/post/drivers/Makefile b/post/drivers/Makefile index 0d87ae0..85d6c03 100644 --- a/post/drivers/Makefile +++ b/post/drivers/Makefile @@ -24,6 +24,6 @@ include $(TOPDIR)/config.mk LIB = libpostdrivers.o -COBJS-$(CONFIG_HAS_POST) += i2c.o memory.o rtc.o +COBJS-$(CONFIG_HAS_POST) += flash.o i2c.o memory.o rtc.o include $(TOPDIR)/post/rules.mk diff --git a/post/drivers/flash.c b/post/drivers/flash.c new file mode 100644 index 0000000..07eab33 --- /dev/null +++ b/post/drivers/flash.c @@ -0,0 +1,107 @@ +/* + * Parallel NOR Flash tests + * + * Copyright (c) 2005-2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <malloc.h> +#include <post.h> +#include <flash.h> + +#if CONFIG_POST & CONFIG_SYS_POST_FLASH + +/* + * This code will walk over the declared sectors erasing them, + * then programming them, then verifying the written contents. + * Possible future work: + * - verify sectors before/after are not erased/written + * - verify partial writes (e.g. programming only middle of sector) + * - verify the contents of the erased sector + * - better seed pattern than 0x00..0xff + */ + +#ifndef CONFIG_SYS_POST_FLASH_NUM +# define CONFIG_SYS_POST_FLASH_NUM 0 +#endif +#if CONFIG_SYS_POST_FLASH_START >= CONFIG_SYS_POST_FLASH_END +# error "invalid flash block start/end" +#endif + +extern flash_info_t flash_info[]; + +static void *seed_src_data(void *ptr, ulong *old_len, ulong new_len) +{ + unsigned char *p; + ulong i; + + p = ptr = realloc(ptr, new_len); + if (!ptr) + return ptr; + + for (i = *old_len; i < new_len; ++i) + p[i] = i; + + *old_len = new_len; + + return ptr; +} + +int flash_post_test(int flags) +{ + ulong len; + void *src; + int ret, n, n_start, n_end; + flash_info_t *info; + + /* the output from the common flash layers needs help */ + puts("\n"); + + len = 0; + src = NULL; + info = &flash_info[CONFIG_SYS_POST_FLASH_NUM]; + n_start = CONFIG_SYS_POST_FLASH_START; + n_end = CONFIG_SYS_POST_FLASH_END; + + for (n = n_start; n < n_end; ++n) { + ulong s_start, s_len, s_off; + + s_start = info->start[n]; + s_len = flash_sector_size(info, n); + s_off = s_start - info->start[0]; + + src = seed_src_data(src, &len, s_len); + if (!src) { + printf("malloc(%#lx) failed\n", s_len); + return 1; + } + + printf("\tsector %i: %#lx +%#lx", n, s_start, s_len); + + ret = flash_erase(info, n, n + 1); + if (ret) { + flash_perror(ret); + break; + } + + ret = write_buff(info, src, s_start, s_len); + if (ret) { + flash_perror(ret); + break; + } + + ret = memcmp(src, (void *)s_start, s_len); + if (ret) { + printf(" verify failed with %i\n", ret); + break; + } + } + + free(src); + + return ret; +} + +#endif diff --git a/post/drivers/memory.c b/post/drivers/memory.c index 3f47449..c2b711e 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -225,7 +225,7 @@ const unsigned long long otherpattern = 0x0123456789abcdefULL; static int memory_post_dataline(unsigned long long * pmem) { unsigned long long temp64 = 0; - int num_patterns = sizeof(pattern)/ sizeof(pattern[0]); + int num_patterns = ARRAY_SIZE(pattern); int i; unsigned int hi, lo, pathi, patlo; int ret = 0; @@ -452,13 +452,17 @@ static int memory_post_tests (unsigned long start, unsigned long size) return ret; } +/* + * !! this is only valid, if you have contiguous memory banks !! + */ __attribute__((weak)) int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { bd_t *bd = gd->bd; + *vstart = CONFIG_SYS_SDRAM_BASE; - *size = (bd->bi_memsize >= 256 << 20 ? - 256 << 20 : bd->bi_memsize) - (1 << 20); + *size = (gd->ram_size >= 256 << 20 ? + 256 << 20 : gd->ram_size) - (1 << 20); /* Limit area to be tested with the board info struct */ if ((*vstart) + (*size) > (ulong)bd) @@ -500,9 +504,10 @@ int memory_post_test(int flags) unsigned long i; for (i = 0; i < (memsize >> 20) && ret == 0; i++) { if (ret == 0) - ret = memory_post_tests(i << 20, 0x800); + ret = memory_post_tests(vstart + + (i << 20), 0x800); if (ret == 0) - ret = memory_post_tests( + ret = memory_post_tests(vstart + (i << 20) + 0xff800, 0x800); } } diff --git a/post/lib_powerpc/andi.c b/post/lib_powerpc/andi.c index 52ec7c4..2791cd7 100644 --- a/post/lib_powerpc/andi.c +++ b/post/lib_powerpc/andi.c @@ -61,8 +61,7 @@ static struct cpu_post_andi_s 0x80000000 }, }; -static unsigned int cpu_post_andi_size = - sizeof (cpu_post_andi_table) / sizeof (struct cpu_post_andi_s); +static unsigned int cpu_post_andi_size = ARRAY_SIZE(cpu_post_andi_table); int cpu_post_test_andi (void) { diff --git a/post/lib_powerpc/cmp.c b/post/lib_powerpc/cmp.c index 5f6a3b9..ae5b72b 100644 --- a/post/lib_powerpc/cmp.c +++ b/post/lib_powerpc/cmp.c @@ -95,8 +95,7 @@ static struct cpu_post_cmp_s 0x04 }, }; -static unsigned int cpu_post_cmp_size = - sizeof (cpu_post_cmp_table) / sizeof (struct cpu_post_cmp_s); +static unsigned int cpu_post_cmp_size = ARRAY_SIZE(cpu_post_cmp_table); int cpu_post_test_cmp (void) { diff --git a/post/lib_powerpc/cmpi.c b/post/lib_powerpc/cmpi.c index 1a2fc3d..4160a2a 100644 --- a/post/lib_powerpc/cmpi.c +++ b/post/lib_powerpc/cmpi.c @@ -95,8 +95,7 @@ static struct cpu_post_cmpi_s 0x04 }, }; -static unsigned int cpu_post_cmpi_size = - sizeof (cpu_post_cmpi_table) / sizeof (struct cpu_post_cmpi_s); +static unsigned int cpu_post_cmpi_size = ARRAY_SIZE(cpu_post_cmpi_table); int cpu_post_test_cmpi (void) { diff --git a/post/lib_powerpc/cr.c b/post/lib_powerpc/cr.c index fbee6d5..ada7c7a 100644 --- a/post/lib_powerpc/cr.c +++ b/post/lib_powerpc/cr.c @@ -59,8 +59,7 @@ static ulong cpu_post_cr_table1[] = 0xaaaaaaaa, 0x55555555, }; -static unsigned int cpu_post_cr_size1 = - sizeof (cpu_post_cr_table1) / sizeof (ulong); +static unsigned int cpu_post_cr_size1 = ARRAY_SIZE(cpu_post_cr_table1); static struct cpu_post_cr_s2 { ulong xer; @@ -76,8 +75,7 @@ static struct cpu_post_cr_s2 { 5 }, }; -static unsigned int cpu_post_cr_size2 = - sizeof (cpu_post_cr_table2) / sizeof (struct cpu_post_cr_s2); +static unsigned int cpu_post_cr_size2 = ARRAY_SIZE(cpu_post_cr_table2); static struct cpu_post_cr_s3 { ulong cr; @@ -99,8 +97,7 @@ static struct cpu_post_cr_s3 { 0x71234567 }, }; -static unsigned int cpu_post_cr_size3 = - sizeof (cpu_post_cr_table3) / sizeof (struct cpu_post_cr_s3); +static unsigned int cpu_post_cr_size3 = ARRAY_SIZE(cpu_post_cr_table3); static struct cpu_post_cr_s4 { ulong cmd; @@ -240,8 +237,7 @@ static struct cpu_post_cr_s4 { 0x0000ffff }, }; -static unsigned int cpu_post_cr_size4 = - sizeof (cpu_post_cr_table4) / sizeof (struct cpu_post_cr_s4); +static unsigned int cpu_post_cr_size4 = ARRAY_SIZE(cpu_post_cr_table4); int cpu_post_test_cr (void) { diff --git a/post/lib_powerpc/fpu/mul-subnormal-single-1.c b/post/lib_powerpc/fpu/mul-subnormal-single-1.c index 23a3f30..b3f8deb 100644 --- a/post/lib_powerpc/fpu/mul-subnormal-single-1.c +++ b/post/lib_powerpc/fpu/mul-subnormal-single-1.c @@ -86,7 +86,7 @@ int fpu_post_test_math7 (void) { unsigned int i; - for (i = 0; i < sizeof (expected) / sizeof (expected[0]); i++) + for (i = 0; i < ARRAY_SIZE(expected); i++) { tstmul (expected[i].p1, expected[i].p2, expected[i].res); tstmul (expected[i].p2, expected[i].p1, expected[i].res); diff --git a/post/lib_powerpc/load.c b/post/lib_powerpc/load.c index 98d4373..49924f2 100644 --- a/post/lib_powerpc/load.c +++ b/post/lib_powerpc/load.c @@ -171,8 +171,7 @@ static struct cpu_post_load_s 1 }, }; -static unsigned int cpu_post_load_size = - sizeof (cpu_post_load_table) / sizeof (struct cpu_post_load_s); +static unsigned int cpu_post_load_size = ARRAY_SIZE(cpu_post_load_table); int cpu_post_test_load (void) { diff --git a/post/lib_powerpc/multi.c b/post/lib_powerpc/multi.c index e42a7c0..5845616 100644 --- a/post/lib_powerpc/multi.c +++ b/post/lib_powerpc/multi.c @@ -57,7 +57,7 @@ int cpu_post_test_multi (void) ASM_BLR, }; - for (i = 0; i < sizeof(src) / sizeof(src[0]); i ++) + for (i = 0; i < ARRAY_SIZE(src); ++i) { src[i] = i; dst[i] = 0; diff --git a/post/lib_powerpc/rlwimi.c b/post/lib_powerpc/rlwimi.c index fd628b3..15d96ac 100644 --- a/post/lib_powerpc/rlwimi.c +++ b/post/lib_powerpc/rlwimi.c @@ -62,8 +62,7 @@ static struct cpu_post_rlwimi_s 0xffaaffff }, }; -static unsigned int cpu_post_rlwimi_size = - sizeof (cpu_post_rlwimi_table) / sizeof (struct cpu_post_rlwimi_s); +static unsigned int cpu_post_rlwimi_size = ARRAY_SIZE(cpu_post_rlwimi_table); int cpu_post_test_rlwimi (void) { diff --git a/post/lib_powerpc/rlwinm.c b/post/lib_powerpc/rlwinm.c index 88a28c6..a04ec52 100644 --- a/post/lib_powerpc/rlwinm.c +++ b/post/lib_powerpc/rlwinm.c @@ -59,8 +59,7 @@ static struct cpu_post_rlwinm_s 0x0000ff00 }, }; -static unsigned int cpu_post_rlwinm_size = - sizeof (cpu_post_rlwinm_table) / sizeof (struct cpu_post_rlwinm_s); +static unsigned int cpu_post_rlwinm_size = ARRAY_SIZE(cpu_post_rlwinm_table); int cpu_post_test_rlwinm (void) { diff --git a/post/lib_powerpc/rlwnm.c b/post/lib_powerpc/rlwnm.c index 60bcb6d..764fe0c 100644 --- a/post/lib_powerpc/rlwnm.c +++ b/post/lib_powerpc/rlwnm.c @@ -60,8 +60,7 @@ static struct cpu_post_rlwnm_s 0x0000ff00 }, }; -static unsigned int cpu_post_rlwnm_size = - sizeof (cpu_post_rlwnm_table) / sizeof (struct cpu_post_rlwnm_s); +static unsigned int cpu_post_rlwnm_size = ARRAY_SIZE(cpu_post_rlwnm_table); int cpu_post_test_rlwnm (void) { diff --git a/post/lib_powerpc/srawi.c b/post/lib_powerpc/srawi.c index be153ad..90a1e4d 100644 --- a/post/lib_powerpc/srawi.c +++ b/post/lib_powerpc/srawi.c @@ -61,8 +61,7 @@ static struct cpu_post_srawi_s 0xf0000000 }, }; -static unsigned int cpu_post_srawi_size = - sizeof (cpu_post_srawi_table) / sizeof (struct cpu_post_srawi_s); +static unsigned int cpu_post_srawi_size = ARRAY_SIZE(cpu_post_srawi_table); int cpu_post_test_srawi (void) { diff --git a/post/lib_powerpc/store.c b/post/lib_powerpc/store.c index 1956f6b..441389c 100644 --- a/post/lib_powerpc/store.c +++ b/post/lib_powerpc/store.c @@ -156,8 +156,7 @@ static struct cpu_post_store_s 0xff }, }; -static unsigned int cpu_post_store_size = - sizeof (cpu_post_store_table) / sizeof (struct cpu_post_store_s); +static unsigned int cpu_post_store_size = ARRAY_SIZE(cpu_post_store_table); int cpu_post_test_store (void) { diff --git a/post/lib_powerpc/three.c b/post/lib_powerpc/three.c index 7f8c1e2..4391386 100644 --- a/post/lib_powerpc/three.c +++ b/post/lib_powerpc/three.c @@ -155,8 +155,7 @@ static struct cpu_post_three_s 0x40 }, }; -static unsigned int cpu_post_three_size = - sizeof (cpu_post_three_table) / sizeof (struct cpu_post_three_s); +static unsigned int cpu_post_three_size = ARRAY_SIZE(cpu_post_three_table); int cpu_post_test_three (void) { diff --git a/post/lib_powerpc/threei.c b/post/lib_powerpc/threei.c index 31953f9..95b6322 100644 --- a/post/lib_powerpc/threei.c +++ b/post/lib_powerpc/threei.c @@ -75,8 +75,7 @@ static struct cpu_post_threei_s 0xffff8000 }, }; -static unsigned int cpu_post_threei_size = - sizeof (cpu_post_threei_table) / sizeof (struct cpu_post_threei_s); +static unsigned int cpu_post_threei_size = ARRAY_SIZE(cpu_post_threei_table); int cpu_post_test_threei (void) { diff --git a/post/lib_powerpc/threex.c b/post/lib_powerpc/threex.c index 350a12a..7769218 100644 --- a/post/lib_powerpc/threex.c +++ b/post/lib_powerpc/threex.c @@ -125,8 +125,7 @@ static struct cpu_post_threex_s 0x1000 }, }; -static unsigned int cpu_post_threex_size = - sizeof (cpu_post_threex_table) / sizeof (struct cpu_post_threex_s); +static unsigned int cpu_post_threex_size = ARRAY_SIZE(cpu_post_threex_table); int cpu_post_test_threex (void) { diff --git a/post/lib_powerpc/two.c b/post/lib_powerpc/two.c index 2b11147..7f08880 100644 --- a/post/lib_powerpc/two.c +++ b/post/lib_powerpc/two.c @@ -81,8 +81,7 @@ static struct cpu_post_two_s ~5 }, }; -static unsigned int cpu_post_two_size = - sizeof (cpu_post_two_table) / sizeof (struct cpu_post_two_s); +static unsigned int cpu_post_two_size = ARRAY_SIZE(cpu_post_two_table); int cpu_post_test_two (void) { diff --git a/post/lib_powerpc/twox.c b/post/lib_powerpc/twox.c index d6714f9..88140bf 100644 --- a/post/lib_powerpc/twox.c +++ b/post/lib_powerpc/twox.c @@ -81,8 +81,7 @@ static struct cpu_post_twox_s 12 }, }; -static unsigned int cpu_post_twox_size = - sizeof (cpu_post_twox_table) / sizeof (struct cpu_post_twox_s); +static unsigned int cpu_post_twox_size = ARRAY_SIZE(cpu_post_twox_table); int cpu_post_test_twox (void) { diff --git a/post/post.c b/post/post.c index 1b7f2aa..852d6a5 100644 --- a/post/post.c +++ b/post/post.c @@ -26,6 +26,10 @@ #include <watchdog.h> #include <post.h> +#ifdef CONFIG_SYS_POST_HOTKEYS_GPIO +#include <asm/gpio.h> +#endif + #ifdef CONFIG_LOGBUFFER #include <logbuff.h> #endif @@ -68,6 +72,23 @@ int post_init_f (void) */ int __post_hotkeys_pressed(void) { +#ifdef CONFIG_SYS_POST_HOTKEYS_GPIO + int ret; + unsigned gpio = CONFIG_SYS_POST_HOTKEYS_GPIO; + + ret = gpio_request(gpio, "hotkeys"); + if (ret) { + printf("POST: gpio hotkey request failed\n"); + return 0; + } + + gpio_direction_input(gpio); + ret = gpio_get_value(gpio); + gpio_free(gpio); + + return ret; +#endif + return 0; /* No hotkeys supported */ } int post_hotkeys_pressed(void) @@ -175,7 +196,7 @@ static void post_get_flags (int *test_flags) POST_CRITICAL }; char *var[] = { "post_poweron", "post_normal", "post_slowtest", "post_critical" }; - int varnum = sizeof (var) / sizeof (var[0]); + int varnum = ARRAY_SIZE(var); char list[128]; /* long enough for POST list */ char *name; char *s; @@ -272,18 +293,18 @@ static int post_run_single (struct post_test *test, gd->flags |= GD_FLG_POSTSTOP; } } else { - if ((*test->test) (flags) != 0) { - post_log ("FAILED\n"); - show_boot_progress (-32); - show_post_progress(i, POST_AFTER, POST_FAILED); - if (test_flags & POST_CRITICAL) - gd->flags |= GD_FLG_POSTFAIL; - if (test_flags & POST_STOP) - gd->flags |= GD_FLG_POSTSTOP; - } - else - post_log ("PASSED\n"); - show_post_progress(i, POST_AFTER, POST_PASSED); + if ((*test->test)(flags) != 0) { + post_log("FAILED\n"); + show_boot_progress(-32); + show_post_progress(i, POST_AFTER, POST_FAILED); + if (test_flags & POST_CRITICAL) + gd->flags |= GD_FLG_POSTFAIL; + if (test_flags & POST_STOP) + gd->flags |= GD_FLG_POSTSTOP; + } else { + post_log("PASSED\n"); + show_post_progress(i, POST_AFTER, POST_PASSED); + } } if ((test_flags & POST_REBOOT) && !(flags & POST_MANUAL)) { diff --git a/post/tests.c b/post/tests.c index 5f59fbb..bfb9cb5 100644 --- a/post/tests.c +++ b/post/tests.c @@ -46,6 +46,7 @@ extern int sysmon_post_test (int flags); extern int dsp_post_test (int flags); extern int codec_post_test (int flags); extern int ecc_post_test (int flags); +extern int flash_post_test(int flags); extern int dspic_init_post_test (int flags); extern int dspic_post_test (int flags); @@ -301,8 +302,20 @@ struct post_test post_list[] = NULL, NULL, CONFIG_SYS_POST_COPROC - } + }, +#endif +#if CONFIG_POST & CONFIG_SYS_POST_FLASH + { + "Parallel NOR flash test", + "flash", + "This test verifies parallel flash operations.", + POST_RAM | POST_SLOWTEST | POST_MANUAL, + &flash_post_test, + NULL, + NULL, + CONFIG_SYS_POST_FLASH + }, #endif }; -unsigned int post_list_size = sizeof (post_list) / sizeof (struct post_test); +unsigned int post_list_size = ARRAY_SIZE(post_list); @@ -29,11 +29,11 @@ $(obj).depend: $(src)Makefile $(TOPDIR)/config.mk $(SRCS) $(HOSTSRCS) @rm -f $@ @touch $@ @for f in $(SRCS); do \ - g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \ + g=`basename $$f | sed -e 's/\(.*\)\.[[:alnum:]_]/\1.o/'`; \ $(CC) -M $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \ done @for f in $(HOSTSRCS); do \ - g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \ + g=`basename $$f | sed -e 's/\(.*\)\.[[:alnum:]_]/\1.o/'`; \ $(HOSTCC) -M $(HOSTCPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \ done @@ -42,4 +42,14 @@ $(HOSTOBJS): $(obj)%.o: %.c $(NOPEDOBJS): $(obj)%.o: %.c $(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTCFLAGS_$(@F)) $(HOSTCFLAGS_$(BCURDIR)) -o $@ $< -c +$(TOPDIR)/include/asm/arch/asm-offsets.h: $(TOPDIR)/include/autoconf.mk.dep \ + $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.s + @echo Generating $@ + $(TOPDIR)/tools/scripts/make-asm-offsets $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.s $@ + +$(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.s: $(TOPDIR)/include/autoconf.mk.dep \ + $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.c + $(CC) -DDO_DEPS_ONLY \ + $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \ + -o $@ $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.c -c -S ######################################################################### diff --git a/spl/.gitignore b/spl/.gitignore new file mode 100644 index 0000000..7c88147 --- /dev/null +++ b/spl/.gitignore @@ -0,0 +1,4 @@ +u-boot-spl +u-boot-spl.bin +u-boot-spl.lds +u-boot-spl.map diff --git a/spl/Makefile b/spl/Makefile new file mode 100644 index 0000000..87f13f6 --- /dev/null +++ b/spl/Makefile @@ -0,0 +1,124 @@ +# +# (C) Copyright 2000-2011 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2011 +# Daniel Schwierzeck, daniel.schwierzeck@googlemail.com. +# +# (C) Copyright 2011 +# Texas Instruments Incorporated - http://www.ti.com/ +# Aneesh V <aneesh@ti.com> +# +# This file is released under the terms of GPL v2 and any later version. +# See the file COPYING in the root directory of the source tree for details. +# +# Based on top-level Makefile. +# + +CONFIG_SPL_BUILD := y +export CONFIG_SPL_BUILD + +include $(TOPDIR)/config.mk + +# We want the final binaries in this directory +obj := $(OBJTREE)/spl/ + +HAVE_VENDOR_COMMON_LIB := $(shell [ -f $(SRCTREE)/board/$(VENDOR)/common/Makefile ] \ + && echo y || echo n) + +START := $(CPUDIR)/start.o + +LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o +LIBS-y += $(CPUDIR)/lib$(CPU).o +ifdef SOC +LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o +endif +LIBS-y += board/$(BOARDDIR)/lib$(BOARD).o +LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/lib$(VENDOR).o + +LIBS-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/libcommon.o +LIBS-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/libdisk.o +LIBS-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/libi2c.o +LIBS-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/libgpio.o +LIBS-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/libmmc.o +LIBS-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/libserial.o +LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/libspi_flash.o +LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/libspi.o +LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/libfat.o +LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o + +ifeq ($(SOC),omap3) +LIBS-y += $(CPUDIR)/omap-common/libomap-common.o +endif +ifeq ($(SOC),omap4) +LIBS-y += $(CPUDIR)/omap-common/libomap-common.o +endif + +START := $(addprefix $(SPLTREE)/,$(START)) +LIBS := $(addprefix $(SPLTREE)/,$(sort $(LIBS-y))) + +__START := $(subst $(obj),,$(START)) +__LIBS := $(subst $(obj),,$(LIBS)) + +# Linker Script +ifdef CONFIG_SPL_LDSCRIPT +# need to strip off double quotes +LDSCRIPT := $(addprefix $(SRCTREE)/,$(subst ",,$(CONFIG_SPL_LDSCRIPT))) +endif + +ifeq ($(wildcard $(LDSCRIPT)),) + LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-spl.lds +endif +ifeq ($(wildcard $(LDSCRIPT)),) + LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-spl.lds +endif +ifeq ($(wildcard $(LDSCRIPT)),) +$(error could not find linker script) +endif + +# Special flags for CPP when processing the linker script. +# Pass the version down so we can handle backwards compatibility +# on the fly. +LDPPFLAGS += \ + -include $(TOPDIR)/include/u-boot/u-boot.lds.h \ + -include $(OBJTREE)/include/config.h \ + $(shell $(LD) --version | \ + sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') + +ifdef CONFIG_OMAP +$(OBJTREE)/MLO: $(obj)u-boot-spl.bin + $(OBJTREE)/tools/mkimage -T omapimage \ + -a $(CONFIG_SPL_TEXT_BASE) -d $< $@ +endif + +ALL-y += $(obj)u-boot-spl.bin + +all: $(ALL-y) + +$(obj)u-boot-spl.bin: $(obj)u-boot-spl + $(OBJCOPY) $(OBJCFLAGS) -O binary $< $@ + +GEN_UBOOT = \ + UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) | \ + sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ + cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $$UNDEF_SYM $(__START) \ + --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ + -Map u-boot-spl.map -o u-boot-spl + +$(obj)u-boot-spl: depend $(START) $(LIBS) $(obj)u-boot-spl.lds + $(GEN_UBOOT) + +$(START): depend + $(MAKE) -C $(SRCTREE)/$(CPUDIR) $@ + +$(LIBS): depend + $(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)) + +$(obj)u-boot-spl.lds: $(LDSCRIPT) depend + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - < $< > $@ + +depend: $(obj).depend +.PHONY: depend + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk diff --git a/tools/Makefile b/tools/Makefile index 623f908..fc741d3 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -43,31 +43,35 @@ ifneq ($(HOST_TOOLS_ALL),) CONFIG_LCD_LOGO = y CONFIG_CMD_LOADS = y CONFIG_CMD_NET = y -CONFIG_INCA_IP = y +CONFIG_XWAY_SWAP_BYTES = y CONFIG_NETCONSOLE = y CONFIG_SHA1_CHECK_UB_IMG = y endif +# Merge all the different vars for envcrc into one +ENVCRC-$(CONFIG_ENV_IS_EMBEDDED) = y +ENVCRC-$(CONFIG_ENV_IS_IN_DATAFLASH) = y +ENVCRC-$(CONFIG_ENV_IS_IN_EEPROM) = y +ENVCRC-$(CONFIG_ENV_IS_IN_FLASH) = y +ENVCRC-$(CONFIG_ENV_IS_IN_ONENAND) = y +ENVCRC-$(CONFIG_ENV_IS_IN_NAND) = y +ENVCRC-$(CONFIG_ENV_IS_IN_NVRAM) = y +ENVCRC-$(CONFIG_ENV_IS_IN_SPI_FLASH) = y +CONFIG_BUILD_ENVCRC ?= $(ENVCRC-y) + # Generated executable files BIN_FILES-$(CONFIG_LCD_LOGO) += bmp_logo$(SFX) BIN_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo$(SFX) -BIN_FILES-$(CONFIG_ENV_IS_EMBEDDED) += envcrc$(SFX) -BIN_FILES-$(CONFIG_ENV_IS_IN_DATAFLASH) += envcrc$(SFX) -BIN_FILES-$(CONFIG_ENV_IS_IN_EEPROM) += envcrc$(SFX) -BIN_FILES-$(CONFIG_ENV_IS_IN_FLASH) += envcrc$(SFX) -BIN_FILES-$(CONFIG_ENV_IS_IN_ONENAND) += envcrc$(SFX) -BIN_FILES-$(CONFIG_ENV_IS_IN_NAND) += envcrc$(SFX) -BIN_FILES-$(CONFIG_ENV_IS_IN_NVRAM) += envcrc$(SFX) -BIN_FILES-$(CONFIG_ENV_IS_IN_SPI_FLASH) += envcrc$(SFX) +BIN_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc$(SFX) BIN_FILES-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX) BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX) -BIN_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes$(SFX) +BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX) BIN_FILES-y += mkimage$(SFX) BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX) BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX) # Source files which exist outside the tools directory -EXT_OBJ_FILES-y += common/env_embedded.o +EXT_OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += common/env_embedded.o EXT_OBJ_FILES-y += common/image.o EXT_OBJ_FILES-y += lib/crc32.o EXT_OBJ_FILES-y += lib/md5.o @@ -77,17 +81,19 @@ EXT_OBJ_FILES-y += lib/sha1.o OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o NOPED_OBJ_FILES-y += default_image.o -OBJ_FILES-y += envcrc.o +OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o NOPED_OBJ_FILES-y += fit_image.o OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o -OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o +OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o NOPED_OBJ_FILES-y += kwbimage.o NOPED_OBJ_FILES-y += imximage.o +NOPED_OBJ_FILES-y += omapimage.o NOPED_OBJ_FILES-y += mkimage.o OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o NOPED_OBJ_FILES-y += os_support.o OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o +NOPED_OBJ_FILES-y += ublimage.o # Don't build by default #ifeq ($(ARCH),ppc) @@ -125,6 +131,9 @@ endif ifeq ($(VENDOR),syteco) LOGO_BMP= logos/syteco.bmp endif +ifeq ($(VENDOR),intercontrol) +LOGO_BMP= logos/intercontrol.bmp +endif # now $(obj) is defined HOSTSRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c)) @@ -171,7 +180,7 @@ $(obj)img2srec$(SFX): $(obj)img2srec.o $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTSTRIP) $@ -$(obj)inca-swap-bytes$(SFX): $(obj)inca-swap-bytes.o +$(obj)xway-swap-bytes$(SFX): $(obj)xway-swap-bytes.o $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTSTRIP) $@ @@ -184,7 +193,9 @@ $(obj)mkimage$(SFX): $(obj)crc32.o \ $(obj)md5.o \ $(obj)mkimage.o \ $(obj)os_support.o \ + $(obj)omapimage.o \ $(obj)sha1.o \ + $(obj)ublimage.o \ $(LIBFDT_OBJS) $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTSTRIP) $@ diff --git a/tools/env/README b/tools/env/README index d5f228f..3f0d77e 100644 --- a/tools/env/README +++ b/tools/env/README @@ -34,9 +34,6 @@ following lines are relevant: #define DEVICE2_ESIZE 0x4000 #define DEVICE2_ENVSECTORS 2 -Current configuration matches the environment layout of the TRAB -board. - Un-define HAVE_REDUND, if you want to use the utlities on a system that does not have support for redundant environment enabled. If HAVE_REDUND is undefined, DEVICE2_NAME is ignored, diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h index c83d608..9258c79 100644 --- a/tools/env/fw_env.h +++ b/tools/env/fw_env.h @@ -24,7 +24,7 @@ /* * To build the utility with the run-time configuration * uncomment the next line. - * See included "fw_env.config" sample file (TRAB board) + * See included "fw_env.config" sample file * for notes on configuration. */ #define CONFIG_FILE "/etc/fw_env.config" diff --git a/tools/envcrc.c b/tools/envcrc.c index c8c50d7..feebbab 100644 --- a/tools/envcrc.c +++ b/tools/envcrc.c @@ -60,6 +60,10 @@ # endif #endif /* CONFIG_ENV_IS_IN_FLASH */ +#if defined(ENV_IS_EMBEDDED) && !defined(CONFIG_BUILD_ENVCRC) +# define CONFIG_BUILD_ENVCRC 1 +#endif + #ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT # define ENV_HEADER_SIZE (sizeof(uint32_t) + 1) #else @@ -71,14 +75,14 @@ extern uint32_t crc32 (uint32_t, const unsigned char *, unsigned int); -#ifdef ENV_IS_EMBEDDED +#ifdef CONFIG_BUILD_ENVCRC extern unsigned int env_size; extern unsigned char environment; -#endif /* ENV_IS_EMBEDDED */ +#endif /* CONFIG_BUILD_ENVCRC */ int main (int argc, char **argv) { -#ifdef ENV_IS_EMBEDDED +#ifdef CONFIG_BUILD_ENVCRC unsigned char pad = 0x00; uint32_t crc; unsigned char *envptr = &environment, diff --git a/tools/logos/intercontrol.bmp b/tools/logos/intercontrol.bmp Binary files differnew file mode 100644 index 0000000..cf2a884 --- /dev/null +++ b/tools/logos/intercontrol.bmp diff --git a/tools/mkimage.c b/tools/mkimage.c index 60f7263..2f33101 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -156,8 +156,12 @@ main (int argc, char **argv) init_imx_image_type (); /* Init FIT image generation/list support */ init_fit_image_type (); + /* Init TI OMAP Boot image generation/list support */ + init_omap_image_type(); /* Init Default image generation/list support */ init_default_image_type (); + /* Init Davinci UBL support */ + init_ubl_image_type(); params.cmdname = *argv; params.addr = params.ep = 0; diff --git a/tools/mkimage.h b/tools/mkimage.h index 9033a7d..e59a919 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -143,5 +143,7 @@ void init_kwb_image_type (void); void init_imx_image_type (void); void init_default_image_type (void); void init_fit_image_type (void); +void init_ubl_image_type(void); +void init_omap_image_type(void); #endif /* _MKIIMAGE_H_ */ diff --git a/tools/omap/clocks_get_m_n.c b/tools/omap/clocks_get_m_n.c new file mode 100644 index 0000000..cfc1760 --- /dev/null +++ b/tools/omap/clocks_get_m_n.c @@ -0,0 +1,197 @@ +/* + * Program for finding M & N values for DPLLs + * To be run on Host PC + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <stdlib.h> +#include <stdio.h> +typedef unsigned int u32; +#define MAX_N 127 + +/* + * get_m_n_optimized() - Finds optimal DPLL multiplier(M) and divider(N) + * values based on the reference frequency, required output frequency, + * maximum tolerance for output frequency etc. + * + * target_freq_khz - output frequency required in KHz + * ref_freq_khz - reference(input) frequency in KHz + * m - pointer to computed M value + * n - pointer to computed N value + * tolerance_khz - tolerance for the output frequency. When the algorithm + * succeeds in finding vialble M and N values the corresponding output + * frequency will be in the range: + * [target_freq_khz - tolerance_khz, target_freq_khz] + * + * Formula: + * Fdpll = (2 * M * Fref) / (N + 1) + * + * Considerations for lock-time: + * - Smaller the N, better lock-time, especially lock-time will be + * - For acceptable lock-times: + * Fref / (M + 1) >= 1 MHz + * + * Considerations for power: + * - The difference in power for different N values giving the same + * output is negligible. So, we optimize for lock-time + * + * Hard-constraints: + * - N can not be greater than 127(7 bit field for representing N) + * + * Usage: + * $ gcc clocks_get_m_n.c + * $ ./a.out + */ +int get_m_n_optimized(u32 target_freq_khz, u32 ref_freq_khz, u32 *m, u32 *n, + u32 tolerance_khz) +{ + u32 min_freq = target_freq_khz - tolerance_khz; + u32 max_freq = target_freq_khz; + u32 freq, freq_old; + *n = 1; + while (1) { + *m = min_freq / ref_freq_khz / 2 * (*n) ; + freq_old = 0; + while (1) { + freq = ref_freq_khz * 2 * (*m) / (*n); + if (abs(target_freq_khz - freq_old) <= + abs(target_freq_khz - freq)) { + freq = freq_old; + (*m)--; + break; + } + (*m)++; + freq_old = freq; + } + if (freq >= min_freq && freq <= max_freq) + break; + (*n)++; + if ((*n) > MAX_N + 1) { + printf("ref %d m %d n %d target %d : ", + ref_freq_khz, *m, *n, target_freq_khz); + printf("can not find m & n - please consider" + " increasing tolerance\n"); + return -1; + } + } + (*n)--; + printf("ref %d m %d n %d target %d locked %d\n", + ref_freq_khz, *m, *n, target_freq_khz, freq); + if ((ref_freq_khz / (*n + 1)) < 1000) { + printf("\tREFCLK - CLKINP/(N+1) is less than 1 MHz - less than" + " ideal, locking time will be high!\n"); + } + return 0; +} + +void main(void) +{ + u32 m, n; + printf("\nMPU - 2000000\n"); + get_m_n_optimized(2000000, 12000, &m, &n, 0); + get_m_n_optimized(2000000, 13000, &m, &n, 0); + get_m_n_optimized(2000000, 16800, &m, &n, 800); + get_m_n_optimized(2000000, 19200, &m, &n, 0); + get_m_n_optimized(2000000, 26000, &m, &n, 0); + get_m_n_optimized(2000000, 27000, &m, &n, 0); + get_m_n_optimized(2000000, 38400, &m, &n, 0); + + printf("\nMPU - 1200000\n"); + get_m_n_optimized(1200000, 12000, &m, &n, 0); + get_m_n_optimized(1200000, 13000, &m, &n, 0); + get_m_n_optimized(1200000, 16800, &m, &n, 800); + get_m_n_optimized(1200000, 19200, &m, &n, 0); + get_m_n_optimized(1200000, 26000, &m, &n, 0); + get_m_n_optimized(1200000, 27000, &m, &n, 0); + get_m_n_optimized(1200000, 38400, &m, &n, 0); + + printf("\nMPU - 1584000\n"); + get_m_n_optimized(1584000, 12000, &m, &n, 0); + get_m_n_optimized(1584000, 13000, &m, &n, 0); + get_m_n_optimized(1584000, 16800, &m, &n, 400); + get_m_n_optimized(1584000, 19200, &m, &n, 0); + get_m_n_optimized(1584000, 26000, &m, &n, 0); + get_m_n_optimized(1584000, 27000, &m, &n, 0); + get_m_n_optimized(1584000, 38400, &m, &n, 0); + + printf("\nCore 1600000\n"); + get_m_n_optimized(1600000, 12000, &m, &n, 0); + get_m_n_optimized(1600000, 13000, &m, &n, 0); + get_m_n_optimized(1600000, 16800, &m, &n, 200); + get_m_n_optimized(1600000, 19200, &m, &n, 0); + get_m_n_optimized(1600000, 26000, &m, &n, 0); + get_m_n_optimized(1600000, 27000, &m, &n, 0); + get_m_n_optimized(1600000, 38400, &m, &n, 0); + + printf("\nPER 1536000\n"); + get_m_n_optimized(1536000, 12000, &m, &n, 0); + get_m_n_optimized(1536000, 13000, &m, &n, 0); + get_m_n_optimized(1536000, 16800, &m, &n, 0); + get_m_n_optimized(1536000, 19200, &m, &n, 0); + get_m_n_optimized(1536000, 26000, &m, &n, 0); + get_m_n_optimized(1536000, 27000, &m, &n, 0); + get_m_n_optimized(1536000, 38400, &m, &n, 0); + + printf("\nIVA 1862000\n"); + get_m_n_optimized(1862000, 12000, &m, &n, 0); + get_m_n_optimized(1862000, 13000, &m, &n, 0); + get_m_n_optimized(1862000, 16800, &m, &n, 0); + get_m_n_optimized(1862000, 19200, &m, &n, 900); + get_m_n_optimized(1862000, 26000, &m, &n, 0); + get_m_n_optimized(1862000, 27000, &m, &n, 0); + get_m_n_optimized(1862000, 38400, &m, &n, 800); + + printf("\nABE 196608 sys clk\n"); + get_m_n_optimized(196608, 12000, &m, &n, 700); + get_m_n_optimized(196608, 13000, &m, &n, 200); + get_m_n_optimized(196608, 16800, &m, &n, 700); + get_m_n_optimized(196608, 19200, &m, &n, 400); + get_m_n_optimized(196608, 26000, &m, &n, 200); + get_m_n_optimized(196608, 27000, &m, &n, 900); + get_m_n_optimized(196608, 38400, &m, &n, 0); + + printf("\nABE 196608 32K\n"); + get_m_n_optimized(196608000/4, 32768, &m, &n, 0); + + printf("\nUSB 1920000\n"); + get_m_n_optimized(1920000, 12000, &m, &n, 0); + get_m_n_optimized(1920000, 13000, &m, &n, 0); + get_m_n_optimized(1920000, 16800, &m, &n, 0); + get_m_n_optimized(1920000, 19200, &m, &n, 0); + get_m_n_optimized(1920000, 26000, &m, &n, 0); + get_m_n_optimized(1920000, 27000, &m, &n, 0); + get_m_n_optimized(1920000, 38400, &m, &n, 0); + + printf("\nCore ES1 1523712\n"); + get_m_n_optimized(1524000, 12000, &m, &n, 100); + get_m_n_optimized(1524000, 13000, &m, &n, 0); + get_m_n_optimized(1524000, 16800, &m, &n, 0); + get_m_n_optimized(1524000, 19200, &m, &n, 0); + get_m_n_optimized(1524000, 26000, &m, &n, 0); + get_m_n_optimized(1524000, 27000, &m, &n, 0); + + /* exact recommendation for SDPs */ + get_m_n_optimized(1523712, 38400, &m, &n, 0); + +} diff --git a/tools/omapimage.c b/tools/omapimage.c new file mode 100644 index 0000000..29d91cc --- /dev/null +++ b/tools/omapimage.c @@ -0,0 +1,224 @@ +/* + * (C) Copyright 2010 + * Linaro LTD, www.linaro.org + * Author: John Rigby <john.rigby@linaro.org> + * Based on TI's signGP.c + * + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2008 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Required to obtain the getline prototype from stdio.h */ +#define _GNU_SOURCE + +#include "mkimage.h" +#include <image.h> +#include "omapimage.h" + +/* Header size is CH header rounded up to 512 bytes plus GP header */ +#define OMAP_CH_HDR_SIZE 512 +#define OMAP_GP_HDR_SIZE (sizeof(struct gp_header)) +#define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE+OMAP_GP_HDR_SIZE) + +static uint8_t omapimage_header[OMAP_FILE_HDR_SIZE]; + +static int omapimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_OMAPIMAGE) + return EXIT_SUCCESS; + else { + fprintf(stderr, "Unknown OMAP image type - %x", type); + return EXIT_FAILURE; + } +} + +/* + * Only the simplest image type is currently supported: + * TOC pointing to CHSETTINGS + * TOC terminator + * CHSETTINGS + * + * padding to OMAP_CH_HDR_SIZE bytes + * + * gp header + * size + * load_addr + */ +static int valid_gph_size(uint32_t size) +{ + return size; +} + +static int valid_gph_load_addr(uint32_t load_addr) +{ + return load_addr; +} + +static int omapimage_verify_header(unsigned char *ptr, int image_size, + struct mkimage_params *params) +{ + struct ch_toc *toc = (struct ch_toc *)ptr; + struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE); + uint32_t offset, size; + + while (toc->section_offset != 0xffffffff + && toc->section_size != 0xffffffff) { + offset = toc->section_offset; + size = toc->section_size; + if (!offset || !size) + return -1; + if (offset >= OMAP_CH_HDR_SIZE || + offset+size >= OMAP_CH_HDR_SIZE) + return -1; + toc++; + } + if (!valid_gph_size(gph->size)) + return -1; + if (!valid_gph_load_addr(gph->load_addr)) + return -1; + + return 0; +} + +static void omapimage_print_section(struct ch_settings *chs) +{ + const char *section_name; + + if (chs->section_key) + section_name = "CHSETTINGS"; + else + section_name = "UNKNOWNKEY"; + + printf("%s (%x) " + "valid:%x " + "version:%x " + "reserved:%x " + "flags:%x\n", + section_name, + chs->section_key, + chs->valid, + chs->version, + chs->reserved, + chs->flags); +} + +static void omapimage_print_header(const void *ptr) +{ + const struct ch_toc *toc = (struct ch_toc *)ptr; + const struct gp_header *gph = + (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE); + uint32_t offset, size; + + while (toc->section_offset != 0xffffffff + && toc->section_size != 0xffffffff) { + offset = toc->section_offset; + size = toc->section_size; + + if (offset >= OMAP_CH_HDR_SIZE || + offset+size >= OMAP_CH_HDR_SIZE) + exit(EXIT_FAILURE); + + printf("Section %s offset %x length %x\n", + toc->section_name, + toc->section_offset, + toc->section_size); + + omapimage_print_section((struct ch_settings *)(ptr+offset)); + toc++; + } + + if (!valid_gph_size(gph->size)) { + fprintf(stderr, + "Error: invalid image size %x\n", + gph->size); + exit(EXIT_FAILURE); + } + + if (!valid_gph_load_addr(gph->load_addr)) { + fprintf(stderr, + "Error: invalid image load address %x\n", + gph->size); + exit(EXIT_FAILURE); + } + + printf("GP Header: Size %x LoadAddr %x\n", + gph->size, gph->load_addr); +} + +static int toc_offset(void *hdr, void *member) +{ + return member - hdr; +} + +static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct mkimage_params *params) +{ + struct ch_toc *toc = (struct ch_toc *)ptr; + struct ch_settings *chs = (struct ch_settings *) + (ptr + 2 * sizeof(*toc)); + struct gp_header *gph = (struct gp_header *)(ptr + OMAP_CH_HDR_SIZE); + + toc->section_offset = toc_offset(ptr, chs); + toc->section_size = sizeof(struct ch_settings); + strcpy((char *)toc->section_name, "CHSETTINGS"); + + chs->section_key = KEY_CHSETTINGS; + chs->valid = 0; + chs->version = 1; + chs->reserved = 0; + chs->flags = 0; + + toc++; + memset(toc, 0xff, sizeof(*toc)); + + gph->size = sbuf->st_size - OMAP_FILE_HDR_SIZE; + gph->load_addr = params->addr; +} + +int omapimage_check_params(struct mkimage_params *params) +{ + return (params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag)); +} + +/* + * omapimage parameters + */ +static struct image_type_params omapimage_params = { + .name = "TI OMAP CH/GP Boot Image support", + .header_size = OMAP_FILE_HDR_SIZE, + .hdr = (void *)&omapimage_header, + .check_image_type = omapimage_check_image_types, + .verify_header = omapimage_verify_header, + .print_header = omapimage_print_header, + .set_header = omapimage_set_header, + .check_params = omapimage_check_params, +}; + +void init_omap_image_type(void) +{ + mkimage_register(&omapimage_params); +} diff --git a/tools/omapimage.h b/tools/omapimage.h new file mode 100644 index 0000000..719db00 --- /dev/null +++ b/tools/omapimage.h @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2010 + * Linaro LTD, www.linaro.org + * Author John Rigby <john.rigby@linaro.org> + * Based on TI's signGP.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAPIMAGE_H_ +#define _OMAPIMAGE_H_ + +struct ch_toc { + uint32_t section_offset; + uint32_t section_size; + uint8_t unused[12]; + uint8_t section_name[12]; +}; + +struct ch_settings { + uint32_t section_key; + uint8_t valid; + uint8_t version; + uint16_t reserved; + uint32_t flags; +}; + +struct gp_header { + uint32_t size; + uint32_t load_addr; +}; + +#define KEY_CHSETTINGS 0xC0C0C0C1 +#endif /* _OMAPIMAGE_H_ */ diff --git a/tools/ublimage.c b/tools/ublimage.c new file mode 100644 index 0000000..9987462 --- /dev/null +++ b/tools/ublimage.c @@ -0,0 +1,275 @@ +/* + * (C) Copyright 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2008 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Required to obtain the getline prototype from stdio.h */ +#define _GNU_SOURCE + +#include "mkimage.h" +#include <image.h> +#include "ublimage.h" + +/* + * Supported commands for configuration file + */ +static table_entry_t ublimage_cmds[] = { + {CMD_BOOT_MODE, "MODE", "UBL special modes", }, + {CMD_ENTRY, "ENTRY", "Entry point addr for bootloader", }, + {CMD_PAGE, "PAGES", + "number of pages (size of bootloader)", }, + {CMD_ST_BLOCK, "START_BLOCK", + "block number where bootloader is present", }, + {CMD_ST_PAGE, "START_PAGE", + "page number where bootloader is present", }, + {CMD_LD_ADDR, "LD_ADDR", + "load addr", }, + {-1, "", "", }, +}; + +/* + * Supported Boot options for configuration file + * this is needed to set the correct flash offset + */ +static table_entry_t ublimage_bootops[] = { + {UBL_MAGIC_SAFE, "safe", "Safe boot mode", }, + {-1, "", "Invalid", }, +}; + +static struct ubl_header ublimage_header; + +static uint32_t get_cfg_value(char *token, char *name, int linenr) +{ + char *endptr; + uint32_t value; + + errno = 0; + value = strtoul(token, &endptr, 16); + if (errno || (token == endptr)) { + fprintf(stderr, "Error: %s[%d] - Invalid hex data(%s)\n", + name, linenr, token); + exit(EXIT_FAILURE); + } + return value; +} + +static void print_hdr(struct ubl_header *ubl_hdr) +{ + printf("Image Type : Davinci UBL Boot Image\n"); + printf("UBL magic : %08x\n", ubl_hdr->magic); + printf("Entry Point: %08x\n", ubl_hdr->entry); + printf("nr of pages: %08x\n", ubl_hdr->pages); + printf("start block: %08x\n", ubl_hdr->block); + printf("start page : %08x\n", ubl_hdr->page); +} + +static void parse_cfg_cmd(struct ubl_header *ublhdr, int32_t cmd, char *token, + char *name, int lineno, int fld, int dcd_len) +{ + static int cmd_ver_first = ~0; + + switch (cmd) { + case CMD_BOOT_MODE: + ublhdr->magic = get_table_entry_id(ublimage_bootops, + "ublimage special boot mode", token); + if (ublhdr->magic == -1) { + fprintf(stderr, "Error: %s[%d] -Invalid boot mode" + "(%s)\n", name, lineno, token); + exit(EXIT_FAILURE); + } + ublhdr->magic += UBL_MAGIC_BASE; + if (unlikely(cmd_ver_first != 1)) + cmd_ver_first = 0; + break; + case CMD_ENTRY: + ublhdr->entry = get_cfg_value(token, name, lineno); + break; + case CMD_PAGE: + ublhdr->pages = get_cfg_value(token, name, lineno); + break; + case CMD_ST_BLOCK: + ublhdr->block = get_cfg_value(token, name, lineno); + break; + case CMD_ST_PAGE: + ublhdr->page = get_cfg_value(token, name, lineno); + break; + case CMD_LD_ADDR: + ublhdr->pll_m = get_cfg_value(token, name, lineno); + break; + } +} + +static void parse_cfg_fld(struct ubl_header *ublhdr, int32_t *cmd, + char *token, char *name, int lineno, int fld, int *dcd_len) +{ + + switch (fld) { + case CFG_COMMAND: + *cmd = get_table_entry_id(ublimage_cmds, + "ublimage commands", token); + if (*cmd < 0) { + fprintf(stderr, "Error: %s[%d] - Invalid command" + "(%s)\n", name, lineno, token); + exit(EXIT_FAILURE); + } + break; + case CFG_REG_VALUE: + parse_cfg_cmd(ublhdr, *cmd, token, name, lineno, fld, *dcd_len); + break; + default: + break; + } +} +static uint32_t parse_cfg_file(struct ubl_header *ublhdr, char *name) +{ + FILE *fd = NULL; + char *line = NULL; + char *token, *saveptr1, *saveptr2; + int lineno = 0; + int i; + char *ptr = (char *)ublhdr; + int fld; + size_t len; + int dcd_len = 0; + int32_t cmd; + int ublhdrlen = sizeof(struct ubl_header); + + fd = fopen(name, "r"); + if (fd == 0) { + fprintf(stderr, "Error: %s - Can't open DCD file\n", name); + exit(EXIT_FAILURE); + } + + /* Fill header with 0xff */ + for (i = 0; i < ublhdrlen; i++) { + *ptr = 0xff; + ptr++; + } + + /* + * Very simple parsing, line starting with # are comments + * and are dropped + */ + while ((getline(&line, &len, fd)) > 0) { + lineno++; + + token = strtok_r(line, "\r\n", &saveptr1); + if (token == NULL) + continue; + + /* Check inside the single line */ + for (fld = CFG_COMMAND, cmd = CMD_INVALID, + line = token; ; line = NULL, fld++) { + token = strtok_r(line, " \t", &saveptr2); + if (token == NULL) + break; + + /* Drop all text starting with '#' as comments */ + if (token[0] == '#') + break; + + parse_cfg_fld(ublhdr, &cmd, token, name, + lineno, fld, &dcd_len); + } + } + fclose(fd); + + return dcd_len; +} + +static int ublimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_UBLIMAGE) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +static int ublimage_verify_header(unsigned char *ptr, int image_size, + struct mkimage_params *params) +{ + return 0; +} + +static void ublimage_print_header(const void *ptr) +{ + struct ubl_header *ubl_hdr = (struct ubl_header *) ptr; + + print_hdr(ubl_hdr); +} + +static void ublimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct mkimage_params *params) +{ + struct ubl_header *ublhdr = (struct ubl_header *)ptr; + + /* Parse configuration file */ + parse_cfg_file(ublhdr, params->imagename); +} + +int ublimage_check_params(struct mkimage_params *params) +{ + if (!params) + return CFG_INVALID; + if (!strlen(params->imagename)) { + fprintf(stderr, "Error: %s - Configuration file not" + "specified, it is needed for ublimage generation\n", + params->cmdname); + return CFG_INVALID; + } + /* + * Check parameters: + * XIP is not allowed and verify that incompatible + * parameters are not sent at the same time + * For example, if list is required a data image must not be provided + */ + return (params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag)) || + (params->xflag) || !(strlen(params->imagename)); +} + +/* + * ublimage parameters + */ +static struct image_type_params ublimage_params = { + .name = "Davinci UBL boot support", + .header_size = sizeof(struct ubl_header), + .hdr = (void *)&ublimage_header, + .check_image_type = ublimage_check_image_types, + .verify_header = ublimage_verify_header, + .print_header = ublimage_print_header, + .set_header = ublimage_set_header, + .check_params = ublimage_check_params, +}; + +void init_ubl_image_type(void) +{ + mkimage_register(&ublimage_params); +} diff --git a/tools/ublimage.h b/tools/ublimage.h new file mode 100644 index 0000000..c926689 --- /dev/null +++ b/tools/ublimage.h @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Vased on: + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _UBLIMAGE_H_ +#define _UBLIMAGE_H_ + +#include <config.h> + +#if !defined(CONFIG_SYS_UBL_BLOCK) +#define CONFIG_SYS_UBL_BLOCK 512 +#endif + +enum ublimage_cmd { + CMD_INVALID, + CMD_BOOT_MODE, + CMD_ENTRY, + CMD_PAGE, + CMD_ST_BLOCK, + CMD_ST_PAGE, + CMD_LD_ADDR +}; + +enum ublimage_fld_types { + CFG_INVALID = -1, + CFG_COMMAND, + CFG_REG_VALUE +}; + +/* + * from sprufg5a.pdf Table 110 + * Used by RBL when doing NAND boot + */ +#define UBL_MAGIC_BASE (0xA1ACED00) +/* Safe boot mode */ +#define UBL_MAGIC_SAFE (0x00) +/* DMA boot mode */ +#define UBL_MAGIC_DMA (0x11) +/* I Cache boot mode */ +#define UBL_MAGIC_IC (0x22) +/* Fast EMIF boot mode */ +#define UBL_MAGIC_FAST (0x33) +/* DMA + ICache boot mode */ +#define UBL_MAGIC_DMA_IC (0x44) +/* DMA + ICache + Fast EMIF boot mode */ +#define UBL_MAGIC_DMA_IC_FAST (0x55) + +/* Define max UBL image size */ +#define UBL_IMAGE_SIZE (0x00003800u) + +/* from sprufg5a.pdf Table 109 */ +struct ubl_header { + uint32_t magic; /* Magic Number, see UBL_* defines */ + uint32_t entry; /* entry point address for bootloader */ + uint32_t pages; /* number of pages (size of bootloader) */ + uint32_t block; /* + * blocknumber where user bootloader is + * present + */ + uint32_t page; /* + * page number where user bootloader is + * present. + */ + uint32_t pll_m; /* + * PLL setting -Multiplier (only valid if + * Magic Number indicates PLL enable). + */ + uint32_t pll_n; /* + * PLL setting -Divider (only valid if + * Magic Number indicates PLL enable). + */ + uint32_t emif; /* + * fast EMIF setting (only valid if + * Magic Number indicates fast EMIF boot). + */ + /* to fit in one nand block */ + unsigned char res[CONFIG_SYS_UBL_BLOCK - 8 * 4]; +}; + +#endif /* _UBLIMAGE_H_ */ diff --git a/tools/inca-swap-bytes.c b/tools/xway-swap-bytes.c index 3a6d82d..3a6d82d 100644 --- a/tools/inca-swap-bytes.c +++ b/tools/xway-swap-bytes.c |
