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-rw-r--r--drivers/net/fm/memac_phy.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
index 140e59b..2f4bc11 100644
--- a/drivers/net/fm/memac_phy.c
+++ b/drivers/net/fm/memac_phy.c
@@ -133,5 +133,17 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
bus->priv = info->regs;
+ /*
+ * On some platforms like B4860, default value of MDIO_CLK_DIV bits
+ * in mdio_stat(mdio_cfg) register generates MDIO clock too high
+ * (much higher than 2.5MHz), violating the IEEE specs.
+ * On other platforms like T1040, default value of MDIO_CLK_DIV bits
+ * is zero, so MDIO clock is disabled.
+ * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
+ * be properly initialized.
+ */
+ setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat,
+ MDIO_STAT_CLKDIV(258));
+
return mdio_register(bus);
}