24 files changed, 378 insertions, 198 deletions

diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
index 89c47f3..9d50e24 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -20,7 +20,7 @@ extern void zynq_ddrc_init(void);
 extern unsigned int zynq_get_silicon_version(void);
 
 /* Driver extern functions */
-extern int zynq_sdhci_init(u32 regbase);
+extern int zynq_sdhci_init(phys_addr_t regbase);
 extern int zynq_sdhci_of_init(const void *blob);
 
 extern void ps7_init(void);
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 1757bbf..84c29e5 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -23,11 +23,15 @@ _start:
 
 	mts	rmsr, r0	/* disable cache */
 
+	addi	r8, r0, __end
+	mts	rslr, r8
 #if defined(CONFIG_SPL_BUILD)
 	addi	r1, r0, CONFIG_SPL_STACK_ADDR
+	mts	rshr, r1
 	addi	r1, r1, -4	/* Decrement SP to top of memory */
 #else
 	addi	r1, r0, CONFIG_SYS_INIT_SP_OFFSET
+	mts	rshr, r1
 	addi	r1, r1, -4	/* Decrement SP to top of memory */
 
 	/* Find-out if u-boot is running on BIG/LITTLE endian platform
@@ -130,7 +134,7 @@ flush:	bralid r15, flush_cache
 
 	/* enable instruction and data cache */
 	mfs	r12, rmsr
-	ori	r12, r12, 0xa0
+	ori	r12, r12, 0x1a0
 	mts	rmsr, r12
 
 clear_bss:
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 4991da2..ef78929 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -29,6 +29,7 @@ config TARGET_MALTA
 	select SUPPORTS_LITTLE_ENDIAN
 	select SUPPORTS_CPU_MIPS32_R1
 	select SUPPORTS_CPU_MIPS32_R2
+	select SWAP_IO_SPACE
 
 config TARGET_VCT
 	bool "Support vct"
@@ -116,6 +117,39 @@ config CPU_MIPS64_R2
 
 endchoice
 
+menu "OS boot interface"
+
+config MIPS_BOOT_CMDLINE_LEGACY
+	bool "Hand over legacy command line to Linux kernel"
+	default y
+	help
+	  Enable this option if you want U-Boot to hand over the Yamon-style
+	  command line to the kernel. All bootargs will be prepared as argc/argv
+	  compatible list. The argument count (argc) is stored in register $a0.
+	  The address of the argument list (argv) is stored in register $a1.
+
+config MIPS_BOOT_ENV_LEGACY
+	bool "Hand over legacy environment to Linux kernel"
+	default y
+	help
+	  Enable this option if you want U-Boot to hand over the Yamon-style
+	  environment to the kernel. Information like memory size, initrd
+	  address and size will be prepared as zero-terminated key/value list.
+	  The address of the enviroment is stored in register $a2.
+
+config MIPS_BOOT_FDT
+	bool "Hand over a flattened device tree to Linux kernel (INCOMPLETE)"
+	default n
+	help
+	  Enable this option if you want U-Boot to hand over a flattened
+	  device tree to the kernel.
+
+	  Note: the final hand over to the kernel is not yet implemented. After
+	        the community agreed on the MIPS boot interface for device trees,
+	        the corresponding code will be added.
+
+endmenu
+
 config SUPPORTS_BIG_ENDIAN
 	bool
 
@@ -134,12 +168,23 @@ config SUPPORTS_CPU_MIPS64_R1
 config SUPPORTS_CPU_MIPS64_R2
 	bool
 
+config CPU_MIPS32
+	bool
+	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2
+
+config CPU_MIPS64
+	bool
+	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
+
 config 32BIT
 	bool
 
 config 64BIT
 	bool
 
+config SWAP_IO_SPACE
+	bool
+
 endif
 
 endmenu
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 1907b57..0a9e7e6 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -2,7 +2,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-head-y := arch/mips/cpu/$(CPU)/start.o
+head-$(CONFIG_CPU_MIPS32) := arch/mips/cpu/mips32/start.o
+head-$(CONFIG_CPU_MIPS64) := arch/mips/cpu/mips64/start.o
 
-libs-y += arch/mips/cpu/$(CPU)/
+libs-$(CONFIG_CPU_MIPS32) += arch/mips/cpu/mips32/
+libs-$(CONFIG_CPU_MIPS64) += arch/mips/cpu/mips64/
 libs-y += arch/mips/lib/
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 384ea26..36b92cc 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -15,6 +15,11 @@
 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
 #endif
 
+#ifndef CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + \
+				CONFIG_SYS_INIT_SP_OFFSET)
+#endif
+
 	/*
 	 * For the moment disable interrupts, mark the kernel mode and
 	 * set ST0_KX so that the CPU does not spit fire when using
@@ -135,9 +140,31 @@ reset:
 #endif
 
 	/* Set up temporary stack */
-	li	sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+	li	t0, -16
+	li	t1, CONFIG_SYS_INIT_SP_ADDR
+	and	sp, t1, t0		# force 16 byte alignment
+	sub	sp, sp, GD_SIZE		# reserve space for gd
+	and	sp, sp, t0		# force 16 byte alignment
+	move	k0, sp			# save gd pointer
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	li	t2, CONFIG_SYS_MALLOC_F_LEN
+	sub	sp, sp, t2		# reserve space for early malloc
+	and	sp, sp, t0		# force 16 byte alignment
+#endif
 	move	fp, sp
 
+	/* Clear gd */
+	move	t0, k0
+1:
+	sw	zero, 0(t0)
+	blt	t0, t1, 1b
+	 addi	t0, 4
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	addu	t0, k0, GD_MALLOC_BASE	# gd->malloc_base offset
+	sw	sp, 0(t0)
+#endif
+
 	la	t9, board_init_f
 	jr	t9
 	 move	ra, zero
diff --git a/arch/mips/cpu/mips32/time.c b/arch/mips/cpu/mips32/time.c
index 386f45a..553da5f 100644
--- a/arch/mips/cpu/mips32/time.c
+++ b/arch/mips/cpu/mips32/time.c
@@ -8,63 +8,12 @@
 #include <common.h>
 #include <asm/mipsregs.h>
 
-static unsigned long timestamp;
-
-/* how many counter cycles in a jiffy */
-#define CYCLES_PER_JIFFY	\
-	(CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
-
-/*
- * timer without interrupts
- */
-
-int timer_init(void)
-{
-	/* Set up the timer for the first expiration. */
-	write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
-
-	return 0;
-}
-
-ulong get_timer(ulong base)
-{
-	unsigned int count;
-	unsigned int expirelo = read_c0_compare();
-
-	/* Check to see if we have missed any timestamps. */
-	count = read_c0_count();
-	while ((count - expirelo) < 0x7fffffff) {
-		expirelo += CYCLES_PER_JIFFY;
-		timestamp++;
-	}
-	write_c0_compare(expirelo);
-
-	return timestamp - base;
-}
-
-void __udelay(unsigned long usec)
+unsigned long notrace timer_read_counter(void)
 {
-	unsigned int tmo;
-
-	tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
-	while ((tmo - read_c0_count()) < 0x7fffffff)
-		/*NOP*/;
+	return read_c0_count();
 }
 
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On MIPS it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On MIPS it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
+ulong notrace get_tbclk(void)
 {
-	return CONFIG_SYS_HZ;
+	return CONFIG_SYS_MIPS_TIMER_FREQ;
 }
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
index 6ff714e..471bc1e 100644
--- a/arch/mips/cpu/mips64/start.S
+++ b/arch/mips/cpu/mips64/start.S
@@ -15,6 +15,11 @@
 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
 #endif
 
+#ifndef CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + \
+				CONFIG_SYS_INIT_SP_OFFSET)
+#endif
+
 #ifdef CONFIG_SYS_LITTLE_ENDIAN
 #define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
 	(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
@@ -129,9 +134,31 @@ reset:
 #endif
 
 	/* Set up temporary stack */
-	dli	sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+	dli	t0, -16
+	dli	t1, CONFIG_SYS_INIT_SP_ADDR
+	and	sp, t1, t0		# force 16 byte alignment
+	dsub	sp, sp, GD_SIZE		# reserve space for gd
+	and	sp, sp, t0		# force 16 byte alignment
+	move	k0, sp			# save gd pointer
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	dli	t2, CONFIG_SYS_MALLOC_F_LEN
+	dsub	sp, sp, t2		# reserve space for early malloc
+	and	sp, sp, t0		# force 16 byte alignment
+#endif
 	move	fp, sp
 
+	/* Clear gd */
+	move	t0, k0
+1:
+	sw	zero, 0(t0)
+	blt	t0, t1, 1b
+	 daddi	t0, 4
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+	daddu	t0, k0, GD_MALLOC_BASE	# gd->malloc_base offset
+	sw	sp, 0(t0)
+#endif
+
 	dla	t9, board_init_f
 	jr	t9
 	 move	ra, zero
diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c
index 0497acf..553da5f 100644
--- a/arch/mips/cpu/mips64/time.c
+++ b/arch/mips/cpu/mips64/time.c
@@ -8,63 +8,12 @@
 #include <common.h>
 #include <asm/mipsregs.h>
 
-static unsigned long timestamp;
-
-/* how many counter cycles in a jiffy */
-#define CYCLES_PER_JIFFY	 \
-	(CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
-
-/*
- * timer without interrupts
- */
-
-int timer_init(void)
-{
-	/* Set up the timer for the first expiration. */
-	write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
-
-	return 0;
-}
-
-ulong get_timer(ulong base)
-{
-	unsigned int count;
-	unsigned int expirelo = read_c0_compare();
-
-	/* Check to see if we have missed any timestamps. */
-	count = read_c0_count();
-	while ((count - expirelo) < 0x7fffffff) {
-		expirelo += CYCLES_PER_JIFFY;
-		timestamp++;
-	}
-	write_c0_compare(expirelo);
-
-	return timestamp - base;
-}
-
-void __udelay(unsigned long usec)
+unsigned long notrace timer_read_counter(void)
 {
-	unsigned int tmo;
-
-	tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
-	while ((tmo - read_c0_count()) < 0x7fffffff)
-		/*NOP*/;
+	return read_c0_count();
 }
 
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On MIPS it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On MIPS it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
+ulong notrace get_tbclk(void)
 {
-	return CONFIG_SYS_HZ;
+	return CONFIG_SYS_MIPS_TIMER_FREQ;
 }
diff --git a/arch/mips/include/asm/config.h b/arch/mips/include/asm/config.h
index 1c8a42b..3a891ba 100644
--- a/arch/mips/include/asm/config.h
+++ b/arch/mips/include/asm/config.h
@@ -7,8 +7,6 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
-
 #define CONFIG_LMB
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
 
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index e0722d2..d9d8396 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -7,6 +7,7 @@
 
 #include <common.h>
 #include <image.h>
+#include <fdt_support.h>
 #include <asm/addrspace.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -20,6 +21,18 @@ DECLARE_GLOBAL_DATA_PTR;
 #define mips_boot_malta		0
 #endif
 
+#if defined(CONFIG_MIPS_BOOT_CMDLINE_LEGACY)
+#define mips_boot_cmdline_legacy	1
+#else
+#define mips_boot_cmdline_legacy	0
+#endif
+
+#if defined(CONFIG_MIPS_BOOT_ENV_LEGACY)
+#define mips_boot_env_legacy	1
+#else
+#define mips_boot_env_legacy	0
+#endif
+
 static int linux_argc;
 static char **linux_argv;
 static char *linux_argp;
@@ -60,9 +73,39 @@ static int boot_setup_linux(bootm_headers_t *images)
 	if (ret)
 		return ret;
 
+#if defined(CONFIG_MIPS_BOOT_FDT) && defined(CONFIG_OF_LIBFDT)
+	if (images->ft_len) {
+		boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr);
+
+		ret = boot_relocate_fdt(&images->lmb, &images->ft_addr,
+			&images->ft_len);
+		if (ret)
+			return ret;
+	}
+#endif
+
 	return 0;
 }
 
+static void boot_setup_fdt(bootm_headers_t *images)
+{
+#if defined(CONFIG_MIPS_BOOT_FDT) && defined(CONFIG_OF_LIBFDT)
+	u64 mem_start = 0;
+	u64 mem_size = gd->ram_size;
+
+	debug("## setup FDT\n");
+
+	fdt_chosen(images->ft_addr, 1);
+	fdt_fixup_memory_banks(images->ft_addr, &mem_start, &mem_size, 1);
+	fdt_fixup_ethernet(images->ft_addr);
+	fdt_initrd(images->ft_addr, images->initrd_start, images->initrd_end, 1);
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+	ft_board_setup(images->ft_addr, gd->bd);
+#endif
+#endif
+}
+
 static void linux_cmdline_init(void)
 {
 	linux_argc = 1;
@@ -92,7 +135,7 @@ static void linux_cmdline_dump(void)
 		debug("   arg %03d: %s\n", i, linux_argv[i]);
 }
 
-static void boot_cmdline_linux(bootm_headers_t *images)
+static void linux_cmdline_legacy(bootm_headers_t *images)
 {
 	const char *bootargs, *next, *quote;
 
@@ -130,8 +173,40 @@ static void boot_cmdline_linux(bootm_headers_t *images)
 
 		bootargs = next;
 	}
+}
 
-	linux_cmdline_dump();
+static void linux_cmdline_append(bootm_headers_t *images)
+{
+	char buf[24];
+	ulong mem, rd_start, rd_size;
+
+	/* append mem */
+	mem = gd->ram_size >> 20;
+	sprintf(buf, "mem=%luM", mem);
+	linux_cmdline_set(buf, strlen(buf));
+
+	/* append rd_start and rd_size */
+	rd_start = images->initrd_start;
+	rd_size = images->initrd_end - images->initrd_start;
+
+	if (rd_size) {
+		sprintf(buf, "rd_start=0x%08lX", rd_start);
+		linux_cmdline_set(buf, strlen(buf));
+		sprintf(buf, "rd_size=0x%lX", rd_size);
+		linux_cmdline_set(buf, strlen(buf));
+	}
+}
+
+static void boot_cmdline_linux(bootm_headers_t *images)
+{
+	if (mips_boot_cmdline_legacy && !images->ft_len) {
+		linux_cmdline_legacy(images);
+
+		if (!mips_boot_env_legacy)
+			linux_cmdline_append(images);
+
+		linux_cmdline_dump();
+	}
 }
 
 static void linux_env_init(void)
@@ -165,7 +240,7 @@ static void linux_env_set(const char *env_name, const char *env_val)
 	}
 }
 
-static void boot_prep_linux(bootm_headers_t *images)
+static void linux_env_legacy(bootm_headers_t *images)
 {
 	char env_buf[12];
 	const char *cp;
@@ -213,6 +288,15 @@ static void boot_prep_linux(bootm_headers_t *images)
 	}
 }
 
+static void boot_prep_linux(bootm_headers_t *images)
+{
+	if (mips_boot_env_legacy && !images->ft_len)
+		linux_env_legacy(images);
+
+	if (images->ft_len)
+		boot_setup_fdt(images);
+}
+
 static void boot_jump_linux(bootm_headers_t *images)
 {
 	typedef void __noreturn (*kernel_entry_t)(int, ulong, ulong, ulong);
@@ -226,8 +310,12 @@ static void boot_jump_linux(bootm_headers_t *images)
 	if (mips_boot_malta)
 		linux_extra = gd->ram_size;
 
-	/* we assume that the kernel is in place */
-	printf("\nStarting kernel ...\n\n");
+#ifdef CONFIG_BOOTSTAGE_FDT
+	bootstage_fdt_add_report();
+#endif
+#ifdef CONFIG_BOOTSTAGE_REPORT
+	bootstage_report();
+#endif
 
 	kernel(linux_argc, (ulong)linux_argv, (ulong)linux_env, linux_extra);
 }
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 258632e..3a2198f 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -24,6 +24,7 @@ static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
 static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
 static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
 static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
+static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
 static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
 static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
 #endif
@@ -49,6 +50,9 @@ int board_init(void)
 	case XILINX_ZYNQ_7030:
 		fpga = fpga030;
 		break;
+	case XILINX_ZYNQ_7035:
+		fpga = fpga035;
+		break;
 	case XILINX_ZYNQ_7045:
 		fpga = fpga045;
 		break;
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c
index 8c5bf44..484a6c6 100644
--- a/common/cmd_fpga.c
+++ b/common/cmd_fpga.c
@@ -211,6 +211,7 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 
 				comp = image_get_comp(hdr);
 				if (comp == IH_COMP_GZIP) {
+#if defined(CONFIG_GZIP)
 					ulong image_buf = image_get_data(hdr);
 					data = image_get_load(hdr);
 					ulong image_size = ~0UL;
@@ -222,6 +223,10 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 						return 1;
 					}
 					data_size = image_size;
+#else
+					puts("Gunzip image is not supported\n");
+					return 1;
+#endif
 				} else {
 					data = (ulong)image_get_data(hdr);
 					data_size = image_get_data_size(hdr);
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 37946d5..d94eb5c 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -38,7 +38,7 @@ static void fpga_no_sup(char *fn, char *msg)
 /* fpga_get_desc
  *	map a device number to a descriptor
  */
-static const fpga_desc *const fpga_get_desc(int devnum)
+const fpga_desc *const fpga_get_desc(int devnum)
 {
 	fpga_desc *desc = (fpga_desc *)NULL;
 
diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index adb4b8c..c765a74 100644
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
@@ -139,6 +139,11 @@ int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
 		return FPGA_FAIL;
 	}
 
+	if (!desc->operations || !desc->operations->load) {
+		printf("%s: Missing load operation\n", __func__);
+		return FPGA_FAIL;
+	}
+
 	return desc->operations->load(desc, buf, bsize, bstype);
 }
 
@@ -151,8 +156,10 @@ int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
 		return FPGA_FAIL;
 	}
 
-	if (!desc->operations->loadfs)
+	if (!desc->operations || !desc->operations->loadfs) {
+		printf("%s: Missing loadfs operation\n", __func__);
 		return FPGA_FAIL;
+	}
 
 	return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
 }
@@ -165,6 +172,11 @@ int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 		return FPGA_FAIL;
 	}
 
+	if (!desc->operations || !desc->operations->dump) {
+		printf("%s: Missing dump operation\n", __func__);
+		return FPGA_FAIL;
+	}
+
 	return desc->operations->dump(desc, buf, bsize);
 }
 
@@ -226,12 +238,14 @@ int xilinx_info(xilinx_desc *desc)
 		if (desc->name)
 			printf("Device name:   \t%s\n", desc->name);
 
-		if (desc->iface_fns) {
+		if (desc->iface_fns)
 			printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
-			desc->operations->info(desc);
-		} else
+		else
 			printf ("No Device Function Table.\n");
 
+		if (desc->operations && desc->operations->info)
+			desc->operations->info(desc);
+
 		ret_val = FPGA_SUCCESS;
 	} else {
 		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index fdce2c2..7887f11 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -13,7 +13,7 @@
 #include <sdhci.h>
 #include <asm/arch/sys_proto.h>
 
-int zynq_sdhci_init(u32 regbase)
+int zynq_sdhci_init(phys_addr_t regbase)
 {
 	struct sdhci_host *host = NULL;
 
@@ -40,7 +40,7 @@ int zynq_sdhci_of_init(const void *blob)
 {
 	int offset = 0;
 	u32 ret = 0;
-	u32 reg;
+	phys_addr_t reg;
 
 	debug("ZYNQ SDHCI: Initialization\n");
 
diff --git a/drivers/net/xilinx_ll_temac.c b/drivers/net/xilinx_ll_temac.c
index dab78d0..7cc8657 100644
--- a/drivers/net/xilinx_ll_temac.c
+++ b/drivers/net/xilinx_ll_temac.c
@@ -231,7 +231,7 @@ static int ll_temac_init(struct eth_device *dev, bd_t *bis)
 	struct ll_temac *ll_temac = dev->priv;
 	int ret;
 
-	printf("%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08X.\n",
+	printf("%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08lx.\n",
 		dev->name, dev->index, dev->iobase);
 
 	if (!ll_temac_setup_ctrl(dev))
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 3cadd23..430e228 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -489,7 +489,8 @@ static int zynq_gem_miiphy_write(const char *devname, uchar addr,
 	return phywrite(dev, addr, reg, val);
 }
 
-int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio)
+int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
+			int phy_addr, u32 emio)
 {
 	struct eth_device *dev;
 	struct zynq_gem_priv *priv;
@@ -521,7 +522,7 @@ int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio)
 	priv->phyaddr = phy_addr;
 	priv->emio = emio;
 
-	sprintf(dev->name, "Gem.%x", base_addr);
+	sprintf(dev->name, "Gem.%lx", base_addr);
 
 	dev->iobase = base_addr;
 
diff --git a/include/configs/malta.h b/include/configs/malta.h
index a29b86b..684d249 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -38,8 +38,6 @@
 #define CONFIG_SYS_MHZ			250	/* arbitrary value */
 #define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
 
-#define CONFIG_SWAP_IO_SPACE
-
 /*
  * Memory map
  */
diff --git a/include/fpga.h b/include/fpga.h
index 914024c..e0d1298 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -49,18 +49,19 @@ typedef enum {
 } bitstream_type;
 
 /* root function definitions */
-extern void fpga_init(void);
-extern int fpga_add(fpga_type devtype, void *desc);
-extern int fpga_count(void);
-extern int fpga_load(int devnum, const void *buf, size_t bsize,
-		     bitstream_type bstype);
-extern int fpga_fsload(int devnum, const void *buf, size_t size,
-		       fpga_fs_info *fpga_fsinfo);
-extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
-			      bitstream_type bstype);
-extern int fpga_dump(int devnum, const void *buf, size_t bsize);
-extern int fpga_info(int devnum);
-extern const fpga_desc *const fpga_validate(int devnum, const void *buf,
-					    size_t bsize, char *fn);
+void fpga_init(void);
+int fpga_add(fpga_type devtype, void *desc);
+int fpga_count(void);
+const fpga_desc *const fpga_get_desc(int devnum);
+int fpga_load(int devnum, const void *buf, size_t bsize,
+	      bitstream_type bstype);
+int fpga_fsload(int devnum, const void *buf, size_t size,
+		fpga_fs_info *fpga_fsinfo);
+int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
+		       bitstream_type bstype);
+int fpga_dump(int devnum, const void *buf, size_t bsize);
+int fpga_info(int devnum);
+const fpga_desc *const fpga_validate(int devnum, const void *buf,
+				     size_t bsize, char *fn);
 
 #endif	/* _FPGA_H_ */
diff --git a/include/netdev.h b/include/netdev.h
index 34651ab..daffc12 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -93,7 +93,8 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
 int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
 						unsigned long ctrl_addr);
 int zynq_gem_of_init(const void *blob);
-int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio);
+int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
+			int phy_addr, u32 emio);
 /*
  * As long as the Xilinx xps_ll_temac ethernet driver has not its own interface
  * exported by a public hader file, we need a global definition at this point.
diff --git a/include/spartan2.h b/include/spartan2.h
index 2aca954..14606c3 100644
--- a/include/spartan2.h
+++ b/include/spartan2.h
@@ -38,7 +38,12 @@ typedef struct {
 	xilinx_post_fn	post;
 } xilinx_spartan2_slave_serial_fns;
 
+#if defined(CONFIG_FPGA_SPARTAN2)
 extern struct xilinx_fpga_op spartan2_op;
+# define FPGA_SPARTAN2_OPS	&spartan2_op
+#else
+# define FPGA_SPARTAN2_OPS	NULL
+#endif
 
 /* Device Image Sizes
  *********************************************************************/
@@ -61,36 +66,47 @@ extern struct xilinx_fpga_op spartan2_op;
  *********************************************************************/
 /* Spartan-II devices */
 #define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
 
 #define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
 
 #endif /* _SPARTAN2_H_ */
diff --git a/include/spartan3.h b/include/spartan3.h
index d6d67a6..fcb27b0 100644
--- a/include/spartan3.h
+++ b/include/spartan3.h
@@ -40,7 +40,12 @@ typedef struct {
 	xilinx_abort_fn abort;
 } xilinx_spartan3_slave_serial_fns;
 
+#if defined(CONFIG_FPGA_SPARTAN3)
 extern struct xilinx_fpga_op spartan3_op;
+# define FPGA_SPARTAN3_OPS	&spartan3_op
+#else
+# define FPGA_SPARTAN3_OPS	NULL
+#endif
 
 /* Device Image Sizes
  *********************************************************************/
@@ -71,48 +76,60 @@ extern struct xilinx_fpga_op spartan3_op;
  *********************************************************************/
 /* Spartan-III devices */
 #define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
 
 #define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
 
 #define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
 
 #define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
 
 #define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
 
 #define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
 
 #define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
 
 #define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
 
 /* Spartan-3E devices */
 #define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
 
 #define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
 
 #define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
 
 #define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
 { xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \
-	&spartan3_op }
+	FPGA_SPARTAN3_OPS }
 
 #define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
 { xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \
-	&spartan3_op }
+	FPGA_SPARTAN3_OPS }
 
 #define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
 
 #endif /* _SPARTAN3_H_ */
diff --git a/include/virtex2.h b/include/virtex2.h
index 7b7825f..503df9a 100644
--- a/include/virtex2.h
+++ b/include/virtex2.h
@@ -11,8 +11,6 @@
 
 #include <xilinx.h>
 
-extern struct xilinx_fpga_op virtex2_op;
-
 /*
  * Slave SelectMap Implementation function table.
  */
@@ -40,12 +38,19 @@ typedef struct {
 	xilinx_wdata_fn	wdata;
 } xilinx_virtex2_slave_serial_fns;
 
+#if defined(CONFIG_FPGA_VIRTEX2)
+extern struct xilinx_fpga_op virtex2_op;
+# define FPGA_VIRTEX2_OPS	&virtex2_op
+#else
+# define FPGA_VIRTEX2_OPS	NULL
+#endif
+
 /* Device Image Sizes (in bytes)
  *********************************************************************/
-#define XILINX_XC2V40_SIZE		(338208 / 8)
-#define XILINX_XC2V80_SIZE		(597408 / 8)
-#define XILINX_XC2V250_SIZE		(1591584 / 8)
-#define XILINX_XC2V500_SIZE		(2557857 / 8)
+#define XILINX_XC2V40_SIZE	(338208 / 8)
+#define XILINX_XC2V80_SIZE	(597408 / 8)
+#define XILINX_XC2V250_SIZE	(1591584 / 8)
+#define XILINX_XC2V500_SIZE	(2557857 / 8)
 #define XILINX_XC2V1000_SIZE	(3749408 / 8)
 #define XILINX_XC2V1500_SIZE	(5166240 / 8)
 #define XILINX_XC2V2000_SIZE	(6808352 / 8)
@@ -58,39 +63,51 @@ typedef struct {
 /* Descriptor Macros
  *********************************************************************/
 #define XILINX_XC2V40_DESC(iface, fn_table, cookie)	\
-{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #endif /* _VIRTEX2_H_ */
diff --git a/include/zynqpl.h b/include/zynqpl.h
index 8a9ec32..1d37a51 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -12,12 +12,18 @@
 
 #include <xilinx.h>
 
+#if defined(CONFIG_FPGA_ZYNQPL)
 extern struct xilinx_fpga_op zynq_op;
+# define FPGA_ZYNQPL_OPS	&zynq_op
+#else
+# define FPGA_ZYNQPL_OPS	NULL
+#endif
 
 #define XILINX_ZYNQ_7010	0x2
 #define XILINX_ZYNQ_7015	0x1b
 #define XILINX_ZYNQ_7020	0x7
 #define XILINX_ZYNQ_7030	0xc
+#define XILINX_ZYNQ_7035	0x12
 #define XILINX_ZYNQ_7045	0x11
 #define XILINX_ZYNQ_7100	0x16
 
@@ -26,26 +32,37 @@ extern struct xilinx_fpga_op zynq_op;
 #define XILINX_XC7Z015_SIZE	28085344/8
 #define XILINX_XC7Z020_SIZE	32364512/8
 #define XILINX_XC7Z030_SIZE	47839328/8
+#define XILINX_XC7Z035_SIZE	106571232/8
 #define XILINX_XC7Z045_SIZE	106571232/8
 #define XILINX_XC7Z100_SIZE	139330784/8
 
 /* Descriptor Macros */
 #define XILINX_XC7Z010_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, &zynq_op, "7z010" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+	"7z010" }
 
 #define XILINX_XC7Z015_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, &zynq_op, "7z015" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+	"7z015" }
 
 #define XILINX_XC7Z020_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, &zynq_op, "7z020" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+	"7z020" }
 
 #define XILINX_XC7Z030_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, &zynq_op, "7z030" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+	"7z030" }
+
+#define XILINX_XC7Z035_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+	"7z035" }
 
 #define XILINX_XC7Z045_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, &zynq_op, "7z045" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+	"7z045" }
 
 #define XILINX_XC7Z100_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, &zynq_op, "7z100" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+	"7z100" }
 
 #endif /* _ZYNQPL_H_ */