diff options
63 files changed, 1529 insertions, 926 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 1e40af2..46f63a0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -594,10 +594,6 @@ Enric Balletbo i Serra <eballetbo@iseebcn.com> igep0020 ARM ARMV7 (OMAP3xx SoC) igep0030 ARM ARMV7 (OMAP3xx SoC) -Dirk Behme <dirk.behme@gmail.com> - - omap3_beagle ARM ARMV7 (OMAP3530 SoC) - Eric Benard <eric@eukrea.com> cpuat91 ARM920T @@ -767,10 +763,6 @@ Nagendra T S <nagendra@mistralsolutions.com> am3517_crane ARM ARMV7 (AM35x SoC) -Chandan Nath <chandan.nath@ti.com> - - am335x_evm ARM ARMV7 (AM33xx Soc) - Kyungmin Park <kyungmin.park@samsung.com> apollon ARM1136EJS @@ -813,6 +805,8 @@ Manfred Rudigier <manfred.rudigier@omicron.at> Tom Rini <trini@ti.com> + am335x_evm ARM ARMV7 (AM33xx Soc) + omap3_beagle ARM ARMV7 (OMAP3xx SoC) omap3_evm ARM ARMV7 (OMAP3xx SoC) Tom Rix <Tom.Rix@windriver.com> @@ -3665,6 +3665,14 @@ List of environment variables (most likely not complete): fdt_high - if set this restricts the maximum address that the flattened device tree will be copied into upon boot. + For example, if you have a system with 1 GB memory + at physical address 0x10000000, while Linux kernel + only recognizes the first 704 MB as low memory, you + may need to set fdt_high as 0x3C000000 to have the + device tree blob be copied to the maximum address + of the 704 MB low memory, so that Linux kernel can + access it during the boot procedure. + If this is set to the special value 0xFFFFFFFF then the fdt will not be copied at all on boot. For this to work it must reside in writable memory, have diff --git a/arch/arm/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c index f494440..72081a8 100644 --- a/arch/arm/cpu/arm1136/mx31/timer.c +++ b/arch/arm/cpu/arm1136/mx31/timer.c @@ -153,6 +153,15 @@ void __udelay(unsigned long usec) /*NOP*/; } +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_MX31_CLK32; +} + void reset_cpu(ulong addr) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE; diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index d41613e..986b1f9 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -422,6 +422,7 @@ U_BOOT_CMD( "" ); +#if defined(CONFIG_DISPLAY_CPUINFO) static char *get_reset_cause(void) { /* read RCSR register from CCM module */ @@ -444,7 +445,6 @@ static char *get_reset_cause(void) } } -#if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { u32 srev = get_cpu_rev(); diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c index 80c0675..04937a1 100644 --- a/arch/arm/cpu/arm1136/mx35/timer.c +++ b/arch/arm/cpu/arm1136/mx35/timer.c @@ -25,7 +25,14 @@ #include <common.h> #include <asm/io.h> +#include <div64.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define timestamp (gd->tbl) +#define lastinc (gd->lastinc) /* General purpose timers bitfields */ #define GPTCR_SWR (1<<15) /* Software reset */ @@ -33,7 +40,24 @@ #define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */ #define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */ #define GPTCR_TEN (1) /* Timer enable */ -#define GPTPR_VAL (66) + +#define TIMER_FREQ_HZ mxc_get_clock(MXC_IPG_CLK) + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, TIMER_FREQ_HZ); + + return tick; +} + +static inline unsigned long long us_to_tick(unsigned long long usec) +{ + usec *= TIMER_FREQ_HZ; + do_div(usec, 1000000); + + return usec; +} int timer_init(void) { @@ -45,7 +69,7 @@ int timer_init(void) for (i = 0; i < 100; i++) writel(0, &gpt->ctrl); /* We have no udelay by now */ - writel(GPTPR_VAL, &gpt->pre); + writel(0, &gpt->pre); /* Freerun Mode, PERCLK1 input */ writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_IPG | GPTCR_TEN, @@ -54,58 +78,59 @@ int timer_init(void) return 0; } -void reset_timer_masked(void) +unsigned long long get_ticks(void) { struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; - - writel(0, &gpt->ctrl); - /* Freerun Mode, PERCLK1 input */ - writel(GPTCR_CLKSOURCE_IPG | GPTCR_TEN, - &gpt->ctrl); + ulong now = readl(&gpt->counter); /* current tick value */ + + if (now >= lastinc) { + /* + * normal mode (non roll) + * move stamp forward with absolut diff ticks + */ + timestamp += (now - lastinc); + } else { + /* we have rollover of incrementer */ + timestamp += (0xFFFFFFFF - lastinc) + now; + } + lastinc = now; + return timestamp; } -inline ulong get_timer_masked(void) +ulong get_timer_masked(void) { - - struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; - ulong val = readl(&gpt->counter); - - return val; + /* + * get_ticks() returns a long long (64 bit), it wraps in + * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in + * 5 * 10^6 days - long enough. + */ + return tick_to_time(get_ticks()); } ulong get_timer(ulong base) { - ulong tmp; + return get_timer_masked() - base; +} - tmp = get_timer_masked(); +/* delay x useconds AND preserve advance timstamp value */ +void __udelay(unsigned long usec) +{ + unsigned long long tmp; + ulong tmo; - if (tmp <= (base * 1000)) { - /* Overflow */ - tmp += (0xffffffff - base); - } + tmo = us_to_tick(usec); + tmp = get_ticks() + tmo; /* get current timestamp */ - return (tmp / 1000) - base; + while (get_ticks() < tmp) /* loop till event */ + /*NOP*/; } /* - * delay x useconds AND preserve advance timstamp value - * GPTCNT is now supposed to tick 1 by 1 us. + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. */ -void __udelay(unsigned long usec) +ulong get_tbclk(void) { - ulong tmp; - - tmp = get_timer_masked(); /* get current timestamp */ - - /* if setting this forward will roll time stamp */ - if ((usec + tmp + 1) < tmp) { - /* reset "advancing" timestamp to 0, set lastinc value */ - reset_timer_masked(); - } else { - /* else, set advancing stamp wake up time */ - tmp += usec; - } - - while (get_timer_masked() < tmp) /* loop till event */ - /*NOP*/; + return TIMER_FREQ_HZ; } diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index b3c9fb7..6cb857a 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -156,7 +156,7 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div) { volatile void *pllbase = (volatile void *) pll_addr; #ifdef CONFIG_SOC_DM646X - unsigned base = CFG_REFCLK_FREQ / 1000; + unsigned base = CONFIG_REFCLK_FREQ / 1000; #else unsigned base = CONFIG_SYS_HZ_CLOCK / 1000; #endif diff --git a/arch/arm/cpu/arm926ejs/davinci/misc.c b/arch/arm/cpu/arm926ejs/davinci/misc.c index 5f510b6..c310c69 100644 --- a/arch/arm/cpu/arm926ejs/davinci/misc.c +++ b/arch/arm/cpu/arm926ejs/davinci/misc.c @@ -101,9 +101,10 @@ void davinci_emac_mii_mode_sel(int mode_sel) void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) { uint8_t env_enetaddr[6]; + int ret; - eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr); - if (!memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) { + ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr); + if (ret) { /* * There is no MAC address in the environment, so we * initialize it from the value in the EEPROM. @@ -111,8 +112,10 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) debug("### Setting environment from EEPROM MAC address = " "\"%pM\"\n", env_enetaddr); - eth_setenv_enetaddr("ethaddr", rom_enetaddr); + ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr); } + if (!ret) + printf("Failed to set mac address from EEPROM\n"); } #endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/arch/arm/cpu/arm926ejs/mx27/timer.c b/arch/arm/cpu/arm926ejs/mx27/timer.c index 5af9359..a5dd684 100644 --- a/arch/arm/cpu/arm926ejs/mx27/timer.c +++ b/arch/arm/cpu/arm926ejs/mx27/timer.c @@ -171,3 +171,8 @@ void __udelay(unsigned long usec) while (get_ticks() < tmp) /* loop till event */ /*NOP*/; } + +ulong get_tbclk(void) +{ + return CONFIG_MX27_CLK32; +} diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c index 380b120..271da8d 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c @@ -726,7 +726,9 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout) clrsetbits_le32(&power_regs->hw_power_vddioctrl, POWER_VDDIOCTRL_TRG_MASK, diff); - if (powered_by_linreg) + if (powered_by_linreg || + (readl(&power_regs->hw_power_sts) & + POWER_STS_VDD5V_GT_VDDIO)) early_delay(1500); else { while (!(readl(&power_regs->hw_power_sts) & @@ -761,7 +763,9 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout) clrsetbits_le32(&power_regs->hw_power_vddioctrl, POWER_VDDIOCTRL_TRG_MASK, diff); - if (powered_by_linreg) + if (powered_by_linreg || + (readl(&power_regs->hw_power_sts) & + POWER_STS_VDD5V_GT_VDDIO)) early_delay(1500); else { while (!(readl(&power_regs->hw_power_sts) & @@ -819,7 +823,9 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) clrsetbits_le32(&power_regs->hw_power_vdddctrl, POWER_VDDDCTRL_TRG_MASK, diff); - if (powered_by_linreg) + if (powered_by_linreg || + (readl(&power_regs->hw_power_sts) & + POWER_STS_VDD5V_GT_VDDIO)) early_delay(1500); else { while (!(readl(&power_regs->hw_power_sts) & @@ -854,7 +860,9 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) clrsetbits_le32(&power_regs->hw_power_vdddctrl, POWER_VDDDCTRL_TRG_MASK, diff); - if (powered_by_linreg) + if (powered_by_linreg || + (readl(&power_regs->hw_power_sts) & + POWER_STS_VDD5V_GT_VDDIO)) early_delay(1500); else { while (!(readl(&power_regs->hw_power_sts) & diff --git a/arch/arm/cpu/arm926ejs/mx28/start.S b/arch/arm/cpu/arm926ejs/mx28/start.S index 2cd4d73..e572b78 100644 --- a/arch/arm/cpu/arm926ejs/mx28/start.S +++ b/arch/arm/cpu/arm926ejs/mx28/start.S @@ -167,10 +167,15 @@ _reset: */ push {r0-r12,r14} + /* save control register c1 */ + mrc p15, 0, r0, c1, c0, 0 + push {r0} + /* - * set the cpu to SVC32 mode + * set the cpu to SVC32 mode and store old CPSR register content */ mrs r0,cpsr + push {r0} bic r0,r0,#0x1f orr r0,r0,#0xd3 msr cpsr,r0 @@ -185,6 +190,20 @@ _reset: bl board_init_ll + /* + * restore bootrom's cpu mode (especially FIQ) + */ + pop {r0} + msr cpsr,r0 + + /* + * restore c1 register + * (especially set exception vector location back to + * bootrom space which is required by bootrom for USB boot) + */ + pop {r0} + mcr p15, 0, r0, c1, c0, 0 + pop {r0-r12,r14} bx lr diff --git a/arch/arm/cpu/arm926ejs/mx28/timer.c b/arch/arm/cpu/arm926ejs/mx28/timer.c index dbc904d..5b73f4a 100644 --- a/arch/arm/cpu/arm926ejs/mx28/timer.c +++ b/arch/arm/cpu/arm926ejs/mx28/timer.c @@ -82,7 +82,7 @@ int timer_init(void) return 0; } -ulong get_timer(ulong base) +unsigned long long get_ticks(void) { struct mx28_timrot_regs *timrot_regs = (struct mx28_timrot_regs *)MXS_TIMROT_BASE; @@ -103,7 +103,17 @@ ulong get_timer(ulong base) } lastdec = now; - return tick_to_time(timestamp) - base; + return timestamp; +} + +ulong get_timer_masked(void) +{ + return tick_to_time(get_ticks()); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; } /* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */ @@ -139,3 +149,8 @@ void __udelay(unsigned long usec) old = new; } } + +ulong get_tbclk(void) +{ + return MX28_INCREMENTER_HZ; +} diff --git a/arch/arm/cpu/armv7/imx-common/timer.c b/arch/arm/cpu/armv7/imx-common/timer.c index 98e9f4a..1645ff8 100755 --- a/arch/arm/cpu/armv7/imx-common/timer.c +++ b/arch/arm/cpu/armv7/imx-common/timer.c @@ -25,6 +25,7 @@ #include <common.h> #include <asm/io.h> +#include <div64.h> #include <asm/arch/imx-regs.h> /* General purpose timers registers */ @@ -50,6 +51,22 @@ DECLARE_GLOBAL_DATA_PTR; #define timestamp (gd->tbl) #define lastinc (gd->lastinc) +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, CLK_32KHZ); + + return tick; +} + +static inline unsigned long long us_to_tick(unsigned long long usec) +{ + usec *= CLK_32KHZ; + do_div(usec, 1000000); + + return usec; +} + int timer_init(void) { int i; @@ -75,36 +92,58 @@ int timer_init(void) return 0; } -ulong get_timer_masked(void) +unsigned long long get_ticks(void) { - ulong val = __raw_readl(&cur_gpt->counter); - val /= (CLK_32KHZ / CONFIG_SYS_HZ); - if (val >= lastinc) - timestamp += (val - lastinc); - else - timestamp += ((0xFFFFFFFF / (CLK_32KHZ / CONFIG_SYS_HZ)) - - lastinc) + val; - lastinc = val; + ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */ + + if (now >= lastinc) { + /* + * normal mode (non roll) + * move stamp forward with absolut diff ticks + */ + timestamp += (now - lastinc); + } else { + /* we have rollover of incrementer */ + timestamp += (0xFFFFFFFF - lastinc) + now; + } + lastinc = now; return timestamp; } +ulong get_timer_masked(void) +{ + /* + * get_ticks() returns a long long (64 bit), it wraps in + * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in + * 5 * 10^6 days - long enough. + */ + return tick_to_time(get_ticks()); +} + ulong get_timer(ulong base) { return get_timer_masked() - base; } -/* delay x useconds AND preserve advance timestamp value */ +/* delay x useconds AND preserve advance timstamp value */ void __udelay(unsigned long usec) { - unsigned long now, start, tmo; - tmo = usec * (CLK_32KHZ / 1000) / 1000; - - if (!tmo) - tmo = 1; + unsigned long long tmp; + ulong tmo; - now = start = readl(&cur_gpt->counter); + tmo = us_to_tick(usec); + tmp = get_ticks() + tmo; /* get current timestamp */ - while ((now - start) < tmo) - now = readl(&cur_gpt->counter); + while (get_ticks() < tmp) /* loop till event */ + /*NOP*/; +} +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CLK_32KHZ; } diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 637ab7b..aabc651 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -430,7 +430,7 @@ void v7_outer_cache_enable(void) omap3_update_aux_cr(0x2, 0); } -void v7_outer_cache_disable(void) +void omap3_outer_cache_disable(void) { /* Clear L2EN */ omap3_update_aux_cr_secure(0, 0x2); diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index ba6b59b..388336f 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -36,7 +36,7 @@ #define CMD_FORCE 0x00 #define CMD_DELAY 0x00 -#define EMIF_READ_LATENCY 0x04 +#define EMIF_READ_LATENCY 0x05 #define EMIF_TIM1 0x0666B3D6 #define EMIF_TIM2 0x143731DA #define EMIF_TIM3 0x00000347 diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 798cc74..6454acb 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -901,4 +901,31 @@ struct esdc_regs { #define MXC_EHCI_IPPUE_DOWN (1 << 8) #define MXC_EHCI_IPPUE_UP (1 << 9) +/* + * CSPI register definitions + */ +#define MXC_CSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_SMC (1 << 3) +#define MXC_CSPICTRL_POL (1 << 4) +#define MXC_CSPICTRL_PHA (1 << 5) +#define MXC_CSPICTRL_SSCTL (1 << 6) +#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) +#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) +#define MXC_CSPICTRL_TC (1 << 8) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_MAXBITS 0x1f + +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 4 + +#define MXC_SPI_BASE_ADDRESSES \ + 0x43fa4000, \ + 0x50010000, \ + 0x53f84000, + #endif /* __ASM_ARCH_MX31_IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-mx31/sys_proto.h b/arch/arm/include/asm/arch-mx31/sys_proto.h index ded481c..f3fa04d 100644 --- a/arch/arm/include/asm/arch-mx31/sys_proto.h +++ b/arch/arm/include/asm/arch-mx31/sys_proto.h @@ -32,4 +32,5 @@ struct mxc_weimcs { void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs); int mxc_mmc_init(bd_t *bis); +u32 get_cpu_rev(void); #endif diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h index df74508..e570ad1 100644 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -179,6 +179,31 @@ #define IPU_CONF_IC_EN (1<<1) #define IPU_CONF_SCI_EN (1<<0) +/* + * CSPI register definitions + */ +#define MXC_CSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_SMC (1 << 3) +#define MXC_CSPICTRL_POL (1 << 4) +#define MXC_CSPICTRL_PHA (1 << 5) +#define MXC_CSPICTRL_SSCTL (1 << 6) +#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 4 + +#define MXC_SPI_BASE_ADDRESSES \ + 0x43fa4000, \ + 0x50010000, + #define GPIO_PORT_NUM 3 #define GPIO_NUM_PIN 32 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 0ee88d2..4fa6658 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -223,6 +223,36 @@ #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 /* + * CSPI register definitions + */ +#define MXC_ECSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) +#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) +#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 32 + +/* Bit position inside CTRL register to be associated with SS */ +#define MXC_CSPICTRL_CHAN 18 + +/* Bit position inside CON register to be associated with SS */ +#define MXC_CSPICON_POL 4 +#define MXC_CSPICON_PHA 0 +#define MXC_CSPICON_SSPOL 12 +#define MXC_SPI_BASE_ADDRESSES \ + CSPI1_BASE_ADDR, \ + CSPI2_BASE_ADDR, \ + CSPI3_BASE_ADDR, + +/* * Number of GPIO pins per port */ #define GPIO_NUM_PIN 32 diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5227b44..6b7589b 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -163,6 +163,11 @@ #define CHIP_REV_1_0 0x10 #define IRAM_SIZE 0x00040000 #define IMX_IIM_BASE OCOTP_BASE_ADDR +#define FEC_QUIRK_ENET_MAC + +#define GPIO_NUMBER(port, index) ((((port)-1)*32)+((index)&31)) +#define GPIO_TO_PORT(number) (((number)/32)+1) +#define GPIO_TO_INDEX(number) ((number)&31) #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> @@ -190,6 +195,50 @@ struct src { u32 gpr10; }; +/* ECSPI registers */ +struct cspi_regs { + u32 rxdata; + u32 txdata; + u32 ctrl; + u32 cfg; + u32 intr; + u32 dma; + u32 stat; + u32 period; +}; + +/* + * CSPI register definitions + */ +#define MXC_ECSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) +#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) +#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 32 + +/* Bit position inside CTRL register to be associated with SS */ +#define MXC_CSPICTRL_CHAN 18 + +/* Bit position inside CON register to be associated with SS */ +#define MXC_CSPICON_POL 4 +#define MXC_CSPICON_PHA 0 +#define MXC_CSPICON_SSPOL 12 +#define MXC_SPI_BASE_ADDRESSES \ + ECSPI1_BASE_ADDR, \ + ECSPI2_BASE_ADDR, \ + ECSPI3_BASE_ADDR, \ + ECSPI4_BASE_ADDR, \ + ECSPI5_BASE_ADDR + struct iim_regs { u32 ctrl; u32 ctrl_set; diff --git a/arch/nds32/cpu/n1213/ag101/watchdog.S b/arch/nds32/cpu/n1213/ag101/watchdog.S index fc39f3f..18f0b66 100644 --- a/arch/nds32/cpu/n1213/ag101/watchdog.S +++ b/arch/nds32/cpu/n1213/ag101/watchdog.S @@ -22,12 +22,12 @@ */ #include <asm/arch-ag101/ag101.h> +#include <linux/linkage.h> .text #ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG -.globl turnoff_watchdog -turnoff_watchdog: +ENTRY(turnoff_watchdog) #define WD_CR 0xC #define WD_ENABLE 0x1 @@ -45,4 +45,5 @@ turnoff_watchdog: ret +ENDPROC(turnoff_watchdog) #endif diff --git a/arch/nds32/include/asm/linkage.h b/arch/nds32/include/asm/linkage.h new file mode 100644 index 0000000..6d4493a --- /dev/null +++ b/arch/nds32/include/asm/linkage.h @@ -0,0 +1,28 @@ +/* + * U-boot - linkage.h + * + * Copyright (c) 2005-2007 Analog Devices Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __ASM_LINKAGE_H +#define __ASM_LINKAGE_H + +#endif diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c index 66e4537..074aabf 100644 --- a/arch/nds32/lib/board.c +++ b/arch/nds32/lib/board.c @@ -365,6 +365,7 @@ void board_init_r(gd_t *id, ulong dest_addr) env_relocate(); #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) + puts("PCI: "); nds32_pci_init(); #endif diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index a507c09..4658ac1 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -115,9 +115,6 @@ extern void cm_remap(void); int misc_init_r (void) { -#ifdef CONFIG_PCI - pci_init(); -#endif setenv("verify", "n"); return (0); } diff --git a/board/armltd/integrator/pci.c b/board/armltd/integrator/pci.c index 6ee2a85..f040450 100644 --- a/board/armltd/integrator/pci.c +++ b/board/armltd/integrator/pci.c @@ -14,6 +14,10 @@ * ARM Ltd. * Philippe Robin, <philippe.robin@arm.com> * + * (C) Copyright 2011 + * Linaro + * Linus Walleij <linus.walleij@linaro.org> + * * See file CREDITS for list of people who contributed to this * project. * @@ -32,15 +36,53 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ - #include <common.h> #include <pci.h> +#include <asm/io.h> +#include "integrator-sc.h" +#include "pci_v3.h" + +#define INTEGRATOR_BOOT_ROM_BASE 0x20000000 +#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 + +/* + * These are in the physical addresses on the CPU side, i.e. + * where we read and write stuff - you don't want to try to + * move these around + */ +#define PHYS_PCI_MEM_BASE 0x40000000 +#define PHYS_PCI_IO_BASE 0x60000000 /* PCI I/O space base */ +#define PHYS_PCI_CONFIG_BASE 0x61000000 +#define PHYS_PCI_V3_BASE 0x62000000 /* V360EPC registers */ +#define SZ_256M 0x10000000 + +/* + * These are in the PCI BUS address space + * Set to 0x00000000 in the Linux kernel, 0x40000000 in Boot monitor + * we follow the example of the kernel, because that is the address + * range that devices actually use - what would they be doing at + * 0x40000000? + */ +#define PCI_BUS_NONMEM_START 0x00000000 +#define PCI_BUS_NONMEM_SIZE SZ_256M + +#define PCI_BUS_PREMEM_START (PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE) +#define PCI_BUS_PREMEM_SIZE SZ_256M + +#if PCI_BUS_NONMEM_START & 0x000fffff +#error PCI_BUS_NONMEM_START must be megabyte aligned +#endif +#if PCI_BUS_PREMEM_START & 0x000fffff +#error PCI_BUS_PREMEM_START must be megabyte aligned +#endif /* * Initialize PCI Devices, report devices found. */ #ifndef CONFIG_PCI_PNP +#define PCI_ENET0_IOADDR 0x60000000 /* First card in PCI I/O space */ +#define PCI_ENET0_MEMADDR 0x40000000 /* First card in PCI memory space */ static struct pci_config_table pci_integrator_config_table[] = { { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, @@ -51,163 +93,187 @@ static struct pci_config_table pci_integrator_config_table[] = { #endif /* CONFIG_PCI_PNP */ /* V3 access routines */ -#define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v)) -#define _V3Read16(o) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o))) - -#define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v)) -#define _V3Read32(o) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o))) - -/* Compute address necessary to access PCI config space for the given */ -/* bus and device. */ -#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) ({ \ - unsigned int __address, __devicebit; \ - unsigned short __mapaddress; \ - unsigned int __dev = PCI_DEV (__devfn); /* FIXME to check!! (slot?) */ \ - \ - if (__bus == 0) { \ - /* local bus segment so need a type 0 config cycle */ \ - /* build the PCI configuration "address" with one-hot in A31-A11 */ \ - __address = PCI_CONFIG_BASE; \ - __address |= ((__devfn & 0x07) << 8); \ - __address |= __offset & 0xFF; \ - __mapaddress = 0x000A; /* 101=>config cycle, 0=>A1=A0=0 */ \ - __devicebit = (1 << (__dev + 11)); \ - \ - if ((__devicebit & 0xFF000000) != 0) { \ - /* high order bits are handled by the MAP register */ \ - __mapaddress |= (__devicebit >> 16); \ - } else { \ - /* low order bits handled directly in the address */ \ - __address |= __devicebit; \ - } \ - } else { /* bus !=0 */ \ - /* not the local bus segment so need a type 1 config cycle */ \ - /* A31-A24 are don't care (so clear to 0) */ \ - __mapaddress = 0x000B; /* 101=>config cycle, 1=>A1&A0 from PCI_CFG */ \ - __address = PCI_CONFIG_BASE; \ - __address |= ((__bus & 0xFF) << 16); /* bits 23..16 = bus number */ \ - __address |= ((__dev & 0x1F) << 11); /* bits 15..11 = device number */ \ - __address |= ((__devfn & 0x07) << 8); /* bits 10..8 = function number */ \ - __address |= __offset & 0xFF; /* bits 7..0 = register number */ \ - } \ - _V3Write16 (V3_LB_MAP1, __mapaddress); \ - __address; \ -}) - -/* _V3OpenConfigWindow - open V3 configuration window */ -#define _V3OpenConfigWindow() { \ - /* Set up base0 to see all 512Mbytes of memory space (not */ \ - /* prefetchable), this frees up base1 for re-use by configuration*/ \ - /* memory */ \ - \ - _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \ - 0x90 | V3_LB_BASE_M_ENABLE)); \ - /* Set up base1 to point into configuration space, note that MAP1 */ \ - /* register is set up by pciMakeConfigAddress(). */ \ - \ - _V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) | \ - 0x40 | V3_LB_BASE_M_ENABLE)); \ +#define v3_writeb(o, v) __raw_writeb(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) +#define v3_readb(o) (__raw_readb(PHYS_PCI_V3_BASE + (unsigned int)(o))) + +#define v3_writew(o, v) __raw_writew(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) +#define v3_readw(o) (__raw_readw(PHYS_PCI_V3_BASE + (unsigned int)(o))) + +#define v3_writel(o, v) __raw_writel(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) +#define v3_readl(o) (__raw_readl(PHYS_PCI_V3_BASE + (unsigned int)(o))) + +static unsigned long v3_open_config_window(pci_dev_t bdf, int offset) +{ + unsigned int address, mapaddress; + unsigned int busnr = PCI_BUS(bdf); + unsigned int devfn = PCI_FUNC(bdf); + + /* + * Trap out illegal values + */ + if (offset > 255) + BUG(); + if (busnr > 255) + BUG(); + if (devfn > 255) + BUG(); + + if (busnr == 0) { + /* + * Linux calls the thing U-Boot calls "DEV" "SLOT" + * instead, but it's the same 5 bits + */ + int slot = PCI_DEV(bdf); + + /* + * local bus segment so need a type 0 config cycle + * + * build the PCI configuration "address" with one-hot in + * A31-A11 + * + * mapaddress: + * 3:1 = config cycle (101) + * 0 = PCI A1 & A0 are 0 (0) + */ + address = PCI_FUNC(bdf) << 8; + mapaddress = V3_LB_MAP_TYPE_CONFIG; + + if (slot > 12) + /* + * high order bits are handled by the MAP register + */ + mapaddress |= 1 << (slot - 5); + else + /* + * low order bits handled directly in the address + */ + address |= 1 << (slot + 11); + } else { + /* + * not the local bus segment so need a type 1 config cycle + * + * address: + * 23:16 = bus number + * 15:11 = slot number (7:3 of devfn) + * 10:8 = func number (2:0 of devfn) + * + * mapaddress: + * 3:1 = config cycle (101) + * 0 = PCI A1 & A0 from host bus (1) + */ + mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN; + address = (busnr << 16) | (devfn << 8); + } + + /* + * Set up base0 to see all 512Mbytes of memory space (not + * prefetchable), this frees up base1 for re-use by + * configuration memory + */ + v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | + V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE); + + /* + * Set up base1/map1 to point into configuration space. + */ + v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) | + V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE); + v3_writew(V3_LB_MAP1, mapaddress); + + return PHYS_PCI_CONFIG_BASE + address + offset; } -/* _V3CloseConfigWindow - close V3 configuration window */ -#define _V3CloseConfigWindow() { \ - /* Reassign base1 for use by prefetchable PCI memory */ \ - _V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) \ - | 0x84 | V3_LB_BASE_M_ENABLE)); \ - _V3Write16 (V3_LB_MAP1, \ - (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006); \ - \ - /* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */ \ - \ - _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \ - 0x80 | V3_LB_BASE_M_ENABLE)); \ +static void v3_close_config_window(void) +{ + /* + * Reassign base1 for use by prefetchable PCI memory + */ + v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | + V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | + V3_LB_BASE_ENABLE); + v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | + V3_LB_MAP_TYPE_MEM_MULTIPLE); + + /* + * And shrink base0 back to a 256M window (NOTE: MAP0 already correct) + */ + v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | + V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); } -static int pci_integrator_read_byte (struct pci_controller *hose, pci_dev_t dev, - int offset, unsigned char *val) +static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t bdf, + int offset, unsigned char *val) { - _V3OpenConfigWindow (); - *val = *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - offset); - _V3CloseConfigWindow (); + unsigned long addr; + addr = v3_open_config_window(bdf, offset); + *val = __raw_readb(addr); + v3_close_config_window(); return 0; } -static int pci_integrator_read__word (struct pci_controller *hose, - pci_dev_t dev, int offset, - unsigned short *val) +static int pci_integrator_read__word(struct pci_controller *hose, + pci_dev_t bdf, int offset, + unsigned short *val) { - _V3OpenConfigWindow (); - *val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - offset); - _V3CloseConfigWindow (); + unsigned long addr; + addr = v3_open_config_window(bdf, offset); + *val = __raw_readw(addr); + v3_close_config_window(); return 0; } -static int pci_integrator_read_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, - unsigned int *val) +static int pci_integrator_read_dword(struct pci_controller *hose, + pci_dev_t bdf, int offset, + unsigned int *val) { - _V3OpenConfigWindow (); - *val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - offset); - *val |= (*(volatile unsigned int *) - PCI_CONFIG_ADDRESS (PCI_BUS (dev), PCI_FUNC (dev), - (offset + 2))) << 16; - _V3CloseConfigWindow (); + unsigned long addr; + addr = v3_open_config_window(bdf, offset); + *val = __raw_readl(addr); + v3_close_config_window(); return 0; } -static int pci_integrator_write_byte (struct pci_controller *hose, - pci_dev_t dev, int offset, - unsigned char val) +static int pci_integrator_write_byte(struct pci_controller *hose, + pci_dev_t bdf, int offset, + unsigned char val) { - _V3OpenConfigWindow (); - *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - offset) = val; - _V3CloseConfigWindow (); + unsigned long addr; + addr = v3_open_config_window(bdf, offset); + __raw_writeb((u8)val, addr); + __raw_readb(addr); + v3_close_config_window(); return 0; } -static int pci_integrator_write_word (struct pci_controller *hose, - pci_dev_t dev, int offset, - unsigned short val) +static int pci_integrator_write_word(struct pci_controller *hose, + pci_dev_t bdf, int offset, + unsigned short val) { - _V3OpenConfigWindow (); - *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - offset) = val; - _V3CloseConfigWindow (); + unsigned long addr; + addr = v3_open_config_window(bdf, offset); + __raw_writew((u8)val, addr); + __raw_readw(addr); + v3_close_config_window(); return 0; } -static int pci_integrator_write_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, - unsigned int val) +static int pci_integrator_write_dword(struct pci_controller *hose, + pci_dev_t bdf, int offset, + unsigned int val) { - _V3OpenConfigWindow (); - *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - offset) = (val & 0xFFFF); - *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - (offset + 2)) = ((val >> 16) & 0xFFFF); - _V3CloseConfigWindow (); + unsigned long addr; + addr = v3_open_config_window(bdf, offset); + __raw_writel((u8)val, addr); + __raw_readl(addr); + v3_close_config_window(); return 0; } -/****************************** - * PCI initialisation - ******************************/ struct pci_controller integrator_hose = { #ifndef CONFIG_PCI_PNP @@ -215,182 +281,198 @@ struct pci_controller integrator_hose = { #endif }; -void pci_init_board (void) +void pci_init_board(void) { volatile int i, j; struct pci_controller *hose = &integrator_hose; + u16 val; /* setting this register will take the V3 out of reset */ - - *(volatile unsigned int *) (INTEGRATOR_SC_PCIENABLE) = 1; + __raw_writel(SC_PCI_PCIEN, SC_PCI); /* wait a few usecs to settle the device and the PCI bus */ for (i = 0; i < 100; i++) j = i + 1; - /* Now write the Base I/O Address Word to V3_BASE + 0x6C */ - - *(volatile unsigned short *) (V3_BASE + V3_LB_IO_BASE) = - (unsigned short) (V3_BASE >> 16); + /* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */ + v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16)); + /* Wait for the mailbox to settle */ do { - *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) = 0xAA; - *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + 4) = - 0x55; - } while (*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) != 0xAA - || *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + - 4) != 0x55); + v3_writeb(V3_MAIL_DATA, 0xAA); + v3_writeb(V3_MAIL_DATA + 4, 0x55); + } while (v3_readb(V3_MAIL_DATA) != 0xAA || + v3_readb(V3_MAIL_DATA + 4) != 0x55); /* Make sure that V3 register access is not locked, if it is, unlock it */ + if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK) + v3_writew(V3_SYSTEM, 0xA05F); - if ((*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) & - V3_SYSTEM_M_LOCK) - == V3_SYSTEM_M_LOCK) - *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = 0xA05F; - - /* Ensure that the slave accesses from PCI are disabled while we */ - /* setup windows */ - - *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) &= - ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN); + /* + * Ensure that the slave accesses from PCI are disabled while we + * setup memory windows + */ + val = v3_readw(V3_PCI_CMD); + val &= ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN); + v3_writew(V3_PCI_CMD, val); /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */ - - *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &= - ~V3_SYSTEM_M_RST_OUT; + val = v3_readw(V3_SYSTEM); + val &= ~V3_SYSTEM_M_RST_OUT; + v3_writew(V3_SYSTEM, val); /* Make all accesses from PCI space retry until we're ready for them */ + val = v3_readw(V3_PCI_CFG); + val |= V3_PCI_CFG_M_RETRY_EN; + v3_writew(V3_PCI_CFG, val); - *(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) |= - V3_PCI_CFG_M_RETRY_EN; - - /* Set up any V3 PCI Configuration Registers that we absolutely have to */ - /* LB_CFG controls Local Bus protocol. */ - /* Enable LocalBus byte strobes for READ accesses too. */ - /* set bit 7 BE_IMODE and bit 6 BE_OMODE */ - - *(volatile unsigned short *) (V3_BASE + V3_LB_CFG) |= 0x0C0; - - /* PCI_CMD controls overall PCI operation. */ - /* Enable PCI bus master. */ - - *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) |= 0x04; + /* + * Set up any V3 PCI Configuration Registers that we absolutely have to. + * LB_CFG controls Local Bus protocol. + * Enable LocalBus byte strobes for READ accesses too. + * set bit 7 BE_IMODE and bit 6 BE_OMODE + */ + val = v3_readw(V3_LB_CFG); + val |= 0x0C0; + v3_writew(V3_LB_CFG, val); - /* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus */ + /* PCI_CMD controls overall PCI operation. Enable PCI bus master. */ + val = v3_readw(V3_PCI_CMD); + val |= V3_COMMAND_M_MASTER_EN; + v3_writew(V3_PCI_CMD, val); - *(volatile unsigned int *) (V3_BASE + V3_PCI_MAP0) = - (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512M | - V3_PCI_MAP_M_REG_EN | - V3_PCI_MAP_M_ENABLE); + /* + * PCI_MAP0 controls where the PCI to CPU memory window is on + * Local Bus + */ + v3_writel(V3_PCI_MAP0, + (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512MB | + V3_PCI_MAP_M_REG_EN | + V3_PCI_MAP_M_ENABLE)); /* PCI_BASE0 is the PCI address of the start of the window */ - - *(volatile unsigned int *) (V3_BASE + V3_PCI_BASE0) = - INTEGRATOR_BOOT_ROM_BASE; + v3_writel(V3_PCI_BASE0, INTEGRATOR_BOOT_ROM_BASE); /* PCI_MAP1 is LOCAL address of the start of the window */ - - *(volatile unsigned int *) (V3_BASE + V3_PCI_MAP1) = - (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1024M | - V3_PCI_MAP_M_REG_EN | - V3_PCI_MAP_M_ENABLE); + v3_writel(V3_PCI_MAP1, + (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1GB | + V3_PCI_MAP_M_REG_EN | + V3_PCI_MAP_M_ENABLE)); /* PCI_BASE1 is the PCI address of the start of the window */ + v3_writel(V3_PCI_BASE1, INTEGRATOR_HDR0_SDRAM_BASE); - *(volatile unsigned int *) (V3_BASE + V3_PCI_BASE1) = - INTEGRATOR_HDR0_SDRAM_BASE; - - /* Set up the windows from local bus memory into PCI configuration, */ - /* I/O and Memory. */ - /* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */ - - *(volatile unsigned short *) (V3_BASE + V3_LB_BASE2) = - ((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE; - *(volatile unsigned short *) (V3_BASE + V3_LB_MAP2) = 0; + /* + * Set up memory the windows from local bus memory into PCI + * configuration, I/O and Memory regions. + * PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. + */ + v3_writew(V3_LB_BASE2, + v3_addr_to_lb_map(PHYS_PCI_IO_BASE) | V3_LB_BASE_ENABLE); + v3_writew(V3_LB_MAP2, 0); /* PCI Configuration, use LB_BASE1/LB_MAP1. */ - /* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */ - /* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */ - /* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */ - - *(volatile unsigned int *) (V3_BASE + V3_LB_BASE0) = - INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE); - - *(volatile unsigned short *) (V3_BASE + V3_LB_MAP0) = - ((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006; + /* + * PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 + * Map first 256Mbytes as non-prefetchable via BASE0/MAP0 + */ + v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | + V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); + v3_writew(V3_LB_MAP0, + v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | V3_LB_MAP_TYPE_MEM); /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */ + v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | + V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | + V3_LB_BASE_ENABLE); + v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | + V3_LB_MAP_TYPE_MEM_MULTIPLE); + + /* Dump PCI to local address space mappings */ + debug("LB_BASE0 = %08x\n", v3_readl(V3_LB_BASE0)); + debug("LB_MAP0 = %04x\n", v3_readw(V3_LB_MAP0)); + debug("LB_BASE1 = %08x\n", v3_readl(V3_LB_BASE1)); + debug("LB_MAP1 = %04x\n", v3_readw(V3_LB_MAP1)); + debug("LB_BASE2 = %04x\n", v3_readw(V3_LB_BASE2)); + debug("LB_MAP2 = %04x\n", v3_readw(V3_LB_MAP2)); + debug("LB_IO_BASE = %04x\n", v3_readw(V3_LB_IO_BASE)); - *(volatile unsigned int *) (V3_BASE + V3_LB_BASE1) = - INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE); - - *(volatile unsigned short *) (V3_BASE + V3_LB_MAP1) = - (((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006; - - /* Allow accesses to PCI Configuration space */ - /* and set up A1, A0 for type 1 config cycles */ - - *(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) = - ((*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG)) & - ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1)) | - V3_PCI_CFG_M_AD_LOW0; - - /* now we can allow in PCI MEMORY accesses */ - - *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) = - (*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD)) | - V3_COMMAND_M_MEM_EN; + /* + * Allow accesses to PCI Configuration space and set up A1, A0 for + * type 1 config cycles + */ + val = v3_readw(V3_PCI_CFG); + val &= ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1); + val |= V3_PCI_CFG_M_AD_LOW0; + v3_writew(V3_PCI_CFG, val); - /* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */ - /* initialise and lock the V3 system register so that no one else */ - /* can play with it */ + /* now we can allow incoming PCI MEMORY accesses */ + val = v3_readw(V3_PCI_CMD); + val |= V3_COMMAND_M_MEM_EN; + v3_writew(V3_PCI_CMD, val); - *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = - (*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) | - V3_SYSTEM_M_RST_OUT; + /* + * Set RST_OUT to take the PCI bus is out of reset, PCI devices can + * now initialise. + */ + val = v3_readw(V3_SYSTEM); + val |= V3_SYSTEM_M_RST_OUT; + v3_writew(V3_SYSTEM, val); - *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = - (*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) | - V3_SYSTEM_M_LOCK; + /* Lock the V3 system register so that no one else can play with it */ + val = v3_readw(V3_SYSTEM); + val |= V3_SYSTEM_M_LOCK; + v3_writew(V3_SYSTEM, val); /* - * Register the hose + * Configure and register the PCI hose */ hose->first_busno = 0; hose->last_busno = 0xff; - /* System memory space */ - pci_set_region (hose->regions + 0, - 0x00000000, 0x40000000, 0x01000000, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + /* System memory space, window 0 256 MB non-prefetchable */ + pci_set_region(hose->regions + 0, + PCI_BUS_NONMEM_START, PHYS_PCI_MEM_BASE, + SZ_256M, + PCI_REGION_MEM); - /* PCI Memory - config space */ - pci_set_region (hose->regions + 1, - 0x00000000, 0x62000000, 0x01000000, PCI_REGION_MEM); - - /* PCI V3 regs */ - pci_set_region (hose->regions + 2, - 0x00000000, 0x61000000, 0x00080000, PCI_REGION_MEM); + /* System memory space, window 1 256 MB prefetchable */ + pci_set_region(hose->regions + 1, + PCI_BUS_PREMEM_START, PHYS_PCI_MEM_BASE + SZ_256M, + SZ_256M, + PCI_REGION_MEM | + PCI_REGION_PREFETCH); /* PCI I/O space */ - pci_set_region (hose->regions + 3, - 0x00000000, 0x60000000, 0x00010000, PCI_REGION_IO); + pci_set_region(hose->regions + 2, + 0x00000000, PHYS_PCI_IO_BASE, 0x01000000, + PCI_REGION_IO); + + /* PCI Memory - config space */ + pci_set_region(hose->regions + 3, + 0x00000000, PHYS_PCI_CONFIG_BASE, 0x01000000, + PCI_REGION_MEM); + /* PCI V3 regs */ + pci_set_region(hose->regions + 4, + 0x00000000, PHYS_PCI_V3_BASE, 0x01000000, + PCI_REGION_MEM); - pci_set_ops (hose, - pci_integrator_read_byte, - pci_integrator_read__word, - pci_integrator_read_dword, - pci_integrator_write_byte, - pci_integrator_write_word, pci_integrator_write_dword); + hose->region_count = 5; - hose->region_count = 4; + pci_set_ops(hose, + pci_integrator_read_byte, + pci_integrator_read__word, + pci_integrator_read_dword, + pci_integrator_write_byte, + pci_integrator_write_word, + pci_integrator_write_dword); - pci_register_hose (hose); + pci_register_hose(hose); - pciauto_config_init (hose); - pciauto_config_device (hose, 0); + pciauto_config_init(hose); + pciauto_config_device(hose, 0); - hose->last_busno = pci_hose_scan (hose); + hose->last_busno = pci_hose_scan(hose); } diff --git a/board/armltd/integrator/pci_v3.h b/board/armltd/integrator/pci_v3.h new file mode 100644 index 0000000..39a0c41 --- /dev/null +++ b/board/armltd/integrator/pci_v3.h @@ -0,0 +1,200 @@ +/* + * arch/arm/include/asm/hardware/pci_v3.h + * + * Internal header file PCI V3 chip + * + * Copyright (C) ARM Limited + * Copyright (C) 2000-2001 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef ASM_ARM_HARDWARE_PCI_V3_H +#define ASM_ARM_HARDWARE_PCI_V3_H + +/* ------------------------------------------------------------------------------- + * V3 Local Bus to PCI Bridge definitions + * ------------------------------------------------------------------------------- + * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04 + * All V3 register names are prefaced by V3_ to avoid clashing with any other + * PCI definitions. Their names match the user's manual. + * + * I'm assuming that I20 is disabled. + * + */ +#define V3_PCI_VENDOR 0x00000000 +#define V3_PCI_DEVICE 0x00000002 +#define V3_PCI_CMD 0x00000004 +#define V3_PCI_STAT 0x00000006 +#define V3_PCI_CC_REV 0x00000008 +#define V3_PCI_HDR_CFG 0x0000000C +#define V3_PCI_IO_BASE 0x00000010 +#define V3_PCI_BASE0 0x00000014 +#define V3_PCI_BASE1 0x00000018 +#define V3_PCI_SUB_VENDOR 0x0000002C +#define V3_PCI_SUB_ID 0x0000002E +#define V3_PCI_ROM 0x00000030 +#define V3_PCI_BPARAM 0x0000003C +#define V3_PCI_MAP0 0x00000040 +#define V3_PCI_MAP1 0x00000044 +#define V3_PCI_INT_STAT 0x00000048 +#define V3_PCI_INT_CFG 0x0000004C +#define V3_LB_BASE0 0x00000054 +#define V3_LB_BASE1 0x00000058 +#define V3_LB_MAP0 0x0000005E +#define V3_LB_MAP1 0x00000062 +#define V3_LB_BASE2 0x00000064 +#define V3_LB_MAP2 0x00000066 +#define V3_LB_SIZE 0x00000068 +#define V3_LB_IO_BASE 0x0000006E +#define V3_FIFO_CFG 0x00000070 +#define V3_FIFO_PRIORITY 0x00000072 +#define V3_FIFO_STAT 0x00000074 +#define V3_LB_ISTAT 0x00000076 +#define V3_LB_IMASK 0x00000077 +#define V3_SYSTEM 0x00000078 +#define V3_LB_CFG 0x0000007A +#define V3_PCI_CFG 0x0000007C +#define V3_DMA_PCI_ADR0 0x00000080 +#define V3_DMA_PCI_ADR1 0x00000090 +#define V3_DMA_LOCAL_ADR0 0x00000084 +#define V3_DMA_LOCAL_ADR1 0x00000094 +#define V3_DMA_LENGTH0 0x00000088 +#define V3_DMA_LENGTH1 0x00000098 +#define V3_DMA_CSR0 0x0000008B +#define V3_DMA_CSR1 0x0000009B +#define V3_DMA_CTLB_ADR0 0x0000008C +#define V3_DMA_CTLB_ADR1 0x0000009C +#define V3_DMA_DELAY 0x000000E0 +#define V3_MAIL_DATA 0x000000C0 +#define V3_PCI_MAIL_IEWR 0x000000D0 +#define V3_PCI_MAIL_IERD 0x000000D2 +#define V3_LB_MAIL_IEWR 0x000000D4 +#define V3_LB_MAIL_IERD 0x000000D6 +#define V3_MAIL_WR_STAT 0x000000D8 +#define V3_MAIL_RD_STAT 0x000000DA +#define V3_QBA_MAP 0x000000DC + +/* PCI COMMAND REGISTER bits + */ +#define V3_COMMAND_M_FBB_EN (1 << 9) +#define V3_COMMAND_M_SERR_EN (1 << 8) +#define V3_COMMAND_M_PAR_EN (1 << 6) +#define V3_COMMAND_M_MASTER_EN (1 << 2) +#define V3_COMMAND_M_MEM_EN (1 << 1) +#define V3_COMMAND_M_IO_EN (1 << 0) + +/* SYSTEM REGISTER bits + */ +#define V3_SYSTEM_M_RST_OUT (1 << 15) +#define V3_SYSTEM_M_LOCK (1 << 14) + +/* PCI_CFG bits + */ +#define V3_PCI_CFG_M_I2O_EN (1 << 15) +#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) +#define V3_PCI_CFG_M_IO_DIS (1 << 13) +#define V3_PCI_CFG_M_EN3V (1 << 12) +#define V3_PCI_CFG_M_RETRY_EN (1 << 10) +#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) +#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) + +/* PCI_BASE register bits (PCI -> Local Bus) + */ +#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 +#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 +#define V3_PCI_BASE_M_PREFETCH (1 << 3) +#define V3_PCI_BASE_M_TYPE (3 << 1) +#define V3_PCI_BASE_M_IO (1 << 0) + +/* PCI MAP register bits (PCI -> Local bus) + */ +#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 +#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) +#define V3_PCI_MAP_M_ROM_SIZE (3 << 10) +#define V3_PCI_MAP_M_SWAP (3 << 8) +#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 +#define V3_PCI_MAP_M_REG_EN (1 << 1) +#define V3_PCI_MAP_M_ENABLE (1 << 0) + +#define V3_PCI_MAP_M_ADR_SIZE_1MB (0 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_2MB (1 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_4MB (2 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_8MB (3 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_16MB (4 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_32MB (5 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_64MB (6 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_128MB (7 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_256MB (8 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_512MB (9 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_1GB (10 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_2GB (11 << 4) + +/* + * LB_BASE0,1 register bits (Local bus -> PCI) + */ +#define V3_LB_BASE_ADR_BASE 0xfff00000 +#define V3_LB_BASE_SWAP (3 << 8) +#define V3_LB_BASE_ADR_SIZE (15 << 4) +#define V3_LB_BASE_PREFETCH (1 << 3) +#define V3_LB_BASE_ENABLE (1 << 0) + +#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) +#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) +#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) +#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) +#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) +#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) +#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) +#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) +#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) +#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) +#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) +#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) + +#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) + +/* + * LB_MAP0,1 register bits (Local bus -> PCI) + */ +#define V3_LB_MAP_MAP_ADR 0xfff0 +#define V3_LB_MAP_TYPE (7 << 1) +#define V3_LB_MAP_AD_LOW_EN (1 << 0) + +#define V3_LB_MAP_TYPE_IACK (0 << 1) +#define V3_LB_MAP_TYPE_IO (1 << 1) +#define V3_LB_MAP_TYPE_MEM (3 << 1) +#define V3_LB_MAP_TYPE_CONFIG (5 << 1) +#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) + +/* PCI MAP register bits (PCI -> Local bus) */ +#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) + +/* + * LB_BASE2 register bits (Local bus -> PCI IO) + */ +#define V3_LB_BASE2_ADR_BASE 0xff00 +#define V3_LB_BASE2_SWAP (3 << 6) +#define V3_LB_BASE2_ENABLE (1 << 0) + +#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) + +/* + * LB_MAP2 register bits (Local bus -> PCI IO) + */ +#define V3_LB_MAP2_MAP_ADR 0xff00 + +#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) + +#endif diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 34ef53d..004d5ad 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -25,12 +25,15 @@ #include <i2c.h> #include <net.h> #include <netdev.h> +#include <spi.h> +#include <spi_flash.h> #include <asm/arch/hardware.h> #include <asm/arch/emif_defs.h> #include <asm/arch/emac_defs.h> #include <asm/arch/pinmux_defs.h> #include <asm/io.h> #include <asm/arch/davinci_misc.h> +#include <asm/errno.h> #include <hwconfig.h> DECLARE_GLOBAL_DATA_PTR; @@ -43,6 +46,36 @@ DECLARE_GLOBAL_DATA_PTR; #endif #endif /* CONFIG_DRIVER_TI_EMAC */ +#define CFG_MAC_ADDR_SPI_BUS 0 +#define CFG_MAC_ADDR_SPI_CS 0 +#define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3 + +#define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K) + +#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH +static int get_mac_addr(u8 *addr) +{ + struct spi_flash *flash; + int ret; + + flash = spi_flash_probe(CFG_MAC_ADDR_SPI_BUS, CFG_MAC_ADDR_SPI_CS, + CFG_MAC_ADDR_SPI_MAX_HZ, CFG_MAC_ADDR_SPI_MODE); + if (!flash) { + printf("Error - unable to probe SPI flash.\n"); + return -1; + } + + ret = spi_flash_read(flash, CFG_MAC_ADDR_OFFSET, 6, addr); + if (ret) { + printf("Error - unable to read MAC address from SPI flash.\n"); + return -1; + } + + return ret; +} +#endif + void dsp_lpsc_on(unsigned domain, unsigned int id) { dv_reg_p mdstat, mdctl, ptstat, ptcmd; @@ -98,6 +131,76 @@ static void dspwake(void) int misc_init_r(void) { dspwake(); + +#if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) || defined(CONFIG_MAC_ADDR_IN_EEPROM) + + uchar env_enetaddr[6]; + int enetaddr_found; + + enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr); + +#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH + int spi_mac_read; + uchar buff[6]; + + spi_mac_read = get_mac_addr(buff); + + /* + * MAC address not present in the environment + * try and read the MAC address from SPI flash + * and set it. + */ + if (!enetaddr_found) { + if (!spi_mac_read) { + if (is_valid_ether_addr(buff)) { + if (eth_setenv_enetaddr("ethaddr", buff)) { + printf("Warning: Failed to " + "set MAC address from SPI flash\n"); + } + } else { + printf("Warning: Invalid " + "MAC address read from SPI flash\n"); + } + } + } else { + /* + * MAC address present in environment compare it with + * the MAC address in SPI flash and warn on mismatch + */ + if (!spi_mac_read && is_valid_ether_addr(buff) && + memcmp(env_enetaddr, buff, 6)) + printf("Warning: MAC address in SPI flash don't match " + "with the MAC address in the environment\n"); + printf("Default using MAC address from environment\n"); + } +#endif + uint8_t enetaddr[8]; + int eeprom_mac_read; + + /* Read Ethernet MAC address from EEPROM */ + eeprom_mac_read = dvevm_read_mac_address(enetaddr); + + /* + * MAC address not present in the environment + * try and read the MAC address from EEPROM flash + * and set it. + */ + if (!enetaddr_found) { + if (eeprom_mac_read) + /* Set Ethernet MAC address from EEPROM */ + davinci_sync_env_enetaddr(enetaddr); + } else { + /* + * MAC address present in environment compare it with + * the MAC address in EEPROM and warn on mismatch + */ + if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6)) + printf("Warning: MAC address in EEPROM don't match " + "with the MAC address in the environment\n"); + printf("Default using MAC address from environment\n"); + } + +#endif return 0; } diff --git a/board/davinci/dm6467evm/dm6467evm.c b/board/davinci/dm6467evm/dm6467evm.c index ac82d5c..e2e4d1a 100644 --- a/board/davinci/dm6467evm/dm6467evm.c +++ b/board/davinci/dm6467evm/dm6467evm.c @@ -36,7 +36,7 @@ DECLARE_GLOBAL_DATA_PTR; u32 get_board_rev(void) { -#ifdef DAVINCI_DM6467TEVM +#ifdef CONFIG_DAVINCI_DM6467TEVM return REV_DM6467TEVM; #else return REV_DM6467EVM; diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c index e42e91e..fd021a3 100644 --- a/board/egnite/ethernut5/ethernut5.c +++ b/board/egnite/ethernut5/ethernut5.c @@ -235,10 +235,9 @@ int board_mmc_init(bd_t *bd) return atmel_mci_init((void *)ATMEL_BASE_MCI); } -int board_mmc_getcd(u8 *cd, struct mmc *mmc) +int board_mmc_getcd(struct mmc *mmc) { - *cd = at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN) ? 1 : 0; - return 0; + return !at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN); } #endif diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 4882ffc..9dd4375 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -73,20 +73,20 @@ static void meesc_nand_hw_init(void) writel(csa, &matrix->csa[0]); /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2), &smc->cs[3].setup); writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6), &smc->cs[3].cycle); writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | AT91_SMC_MODE_EXNW_DISABLE | AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(3), + AT91_SMC_MODE_TDF_CYCLE(12), &smc->cs[3].mode); /* Configure RDY/BSY */ diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c index 5dded41..0c12b66 100644 --- a/board/esd/otc570/otc570.c +++ b/board/esd/otc570/otc570.c @@ -81,20 +81,20 @@ static void otc570_nand_hw_init(void) writel(csa, &matrix->csa[0]); /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2), &smc->cs[3].setup); writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6), &smc->cs[3].cycle); writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | AT91_SMC_MODE_EXNW_DISABLE | AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(3), + AT91_SMC_MODE_TDF_CYCLE(12), &smc->cs[3].mode); /* Configure RDY/BSY */ diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index 1f00c14..b87b092 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -96,6 +96,8 @@ struct mii_dev *mii_dev_for_muxval(u32 muxval) #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS) int board_phy_config(struct phy_device *phydev) { + if (phydev->drv->config) + phydev->drv->config(phydev); if (phydev->drv->uid == PHY_UID_TN2020) { unsigned long timeout = 1 * 1000; /* 1 seconds */ enum srds_prtcl device; diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 6fe8d39..24a1715 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -261,6 +261,8 @@ int board_phy_config(struct phy_device *phydev) uint phyid; struct mii_dev *bus = phydev->bus; + if (phydev->drv->config) + phydev->drv->config(phydev); if (do_once) return 0; diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c index 904e3f3..396761b 100644 --- a/board/freescale/mx28evk/iomux.c +++ b/board/freescale/mx28evk/iomux.c @@ -28,6 +28,7 @@ #define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) #define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) #define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) const iomux_cfg_t iomux_setup[] = { /* DUART */ @@ -130,6 +131,13 @@ const iomux_cfg_t iomux_setup[] = { MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + + /* SPI2 (for SPI flash) */ + MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_SS0__SSP2_D3 | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), }; void board_init_ll(void) diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c index 0d04d44..1bc83e9 100644 --- a/board/freescale/mx28evk/mx28evk.c +++ b/board/freescale/mx28evk/mx28evk.c @@ -52,6 +52,13 @@ int board_early_init_f(void) /* SSP2 clock at 96MHz */ mx28_set_sspclk(MXC_SSPCLK2, 96000, 0); +#ifdef CONFIG_CMD_USB + mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); + mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 | + MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL); + gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1); +#endif + return 0; } diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index a5b51a0..cce7123 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -263,10 +263,6 @@ int board_late_init(void) int checkboard(void) { - struct ccm_regs *ccm = - (struct ccm_regs *)IMX_CCM_BASE; - u32 cpu_rev = get_cpu_rev(); - /* * Be sure that I2C is initialized to check * the board revision @@ -274,28 +270,7 @@ int checkboard(void) i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* Print board revision */ - printf("Board: MX35 PDK %d.0 ", ((get_board_rev() >> 8) + 1) & 0x0F); - - /* Print CPU revision */ - printf("i.MX35 %d.%d [", (cpu_rev & 0xF0) >> 4, cpu_rev & 0x0F); - - switch (readl(&ccm->rcsr) & 0x0F) { - case 0x0000: - puts("POR"); - break; - case 0x0002: - puts("JTAG"); - break; - case 0x0004: - puts("RST"); - break; - case 0x0008: - puts("WDT"); - break; - default: - puts("unknown"); - } - puts("]\n"); + printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F); return 0; } diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 8d1f6a3..b505a71 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -327,7 +327,9 @@ int board_mmc_getcd(struct mmc *mmc) int ret; mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1); + gpio_direction_input(0); mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0); + gpio_direction_input(6); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) ret = !gpio_get_value(0); diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index 40b5c19..e90e39e 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -89,7 +89,9 @@ int board_mmc_getcd(struct mmc *mmc) int ret; mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1); + gpio_direction_input(1); mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1); + gpio_direction_input(4); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) ret = !gpio_get_value(1); /* GPIO1_1 */ diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index e976ae1..8a6e31d 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -214,7 +214,9 @@ int board_mmc_getcd(struct mmc *mmc) int ret; mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); + gpio_direction_input(75); mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); + gpio_direction_input(77); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) ret = !gpio_get_value(77); /* GPIO3_13 */ diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index e6345e7..d736141 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -153,7 +153,9 @@ int board_mmc_getcd(struct mmc *mmc) int ret; mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); + gpio_direction_input(75); mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); + gpio_direction_input(77); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) ret = !gpio_get_value(77); /* GPIO3_13 */ diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c index e273192..c237980 100644 --- a/board/freescale/mx53smd/mx53smd.c +++ b/board/freescale/mx53smd/mx53smd.c @@ -135,6 +135,7 @@ struct fsl_esdhc_cfg esdhc_cfg[1] = { int board_mmc_getcd(struct mmc *mmc) { mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); + gpio_direction_input(77); return !gpio_get_value(77); /* GPIO3_13 */ } diff --git a/board/freescale/mx6qsabrelite/imximage.cfg b/board/freescale/mx6qsabrelite/imximage.cfg index 83dee6f..c389427 100644 --- a/board/freescale/mx6qsabrelite/imximage.cfg +++ b/board/freescale/mx6qsabrelite/imximage.cfg @@ -156,7 +156,7 @@ DATA 4 0x021b0404 0x00011006 # set the default clock gate to save power DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC00 +DATA 4 0x020c406c 0x0030FC03 DATA 4 0x020c4070 0x0FFFC000 DATA 4 0x020c4074 0x3FF00000 DATA 4 0x020c4078 0x00FFF300 diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index a53b01f..f884bb5 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -29,9 +29,9 @@ #include <asm/gpio.h> #include <mmc.h> #include <fsl_esdhc.h> +#include <micrel.h> #include <miiphy.h> #include <netdev.h> - DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ @@ -46,6 +46,10 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -193,51 +197,53 @@ int board_mmc_init(bd_t *bis) } #endif -#define MII_1000BASET_CTRL 0x9 -#define MII_EXTENDED_CTRL 0xb -#define MII_EXTENDED_DATAW 0xc +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t ecspi1_pads[] = { + /* SS1 */ + MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), +}; -int fecmxc_mii_postcall(int phy) +void setup_spi(void) { - /* prefer master mode */ - miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x0f00); + gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1); + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); +} +#endif +int board_phy_config(struct phy_device *phydev) +{ /* min rx data delay */ - miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8105); - miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000); - - /* max rx/tx clock delay, min rx/tx control delay */ - miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8104); - miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0xf0f0); - miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x104); - + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); + /* min tx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); + /* max rx/tx clock delay, min rx/tx control */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; } int board_eth_init(bd_t *bis) { - struct eth_device *dev; int ret; setup_iomux_enet(); ret = cpu_eth_init(bis); - if (ret) { + if (ret) printf("FEC MXC: %s:failed\n", __func__); - return ret; - } - - dev = eth_get_dev_by_name("FEC"); - if (!dev) { - printf("FEC MXC: Unable to get FEC device entry\n"); - return -EINVAL; - } - - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - printf("FEC MXC: Unable to register FEC mii postcall\n"); - return ret; - } + +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif return 0; } diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c index ed3fa6e..02e75ed 100644 --- a/board/hale/tt01/tt01.c +++ b/board/hale/tt01/tt01.c @@ -228,3 +228,24 @@ int board_eth_init(bd_t *bis) #endif return rc; } + +#ifdef CONFIG_CONSOLE_EXTRA_INFO +void video_get_info_str(int line_number, char *info) +{ + u32 srev = get_cpu_rev(); + + switch (line_number) { + case 2: + sprintf(info, " CPU : Freescale i.MX31 rev %d.%d%s at %d MHz", + (srev & 0xF0) >> 4, (srev & 0x0F), + ((srev & 0x8000) ? " unknown" : ""), + mxc_get_clock(MXC_ARM_CLK) / 1000000); + break; + case 3: + strcpy(info, " " BOARD_STRING); + break; + default: + info[0] = 0; + } +} +#endif diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 8757876..c09c833 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -252,6 +252,38 @@ void beagle_display_init(void) } /* + * Enable DVI power + */ +static void beagle_dvi_pup() { + uchar val; + + switch (get_board_revision()) { + case REVISION_AXBX: + case REVISION_CX: + case REVISION_C4: + case REVISION_XM_A: + gpio_request(170, ""); + gpio_direction_output(170, 0); + gpio_set_value(170, 1); + break; + case REVISION_XM_B: + case REVISION_XM_C: + default: + #define GPIODATADIR1 (TWL4030_BASEADD_GPIO+3) + #define GPIODATAOUT1 (TWL4030_BASEADD_GPIO+6) + + i2c_read(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1); + val |= 4; + i2c_write(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1); + + i2c_read(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1); + val |= 4; + i2c_write(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1); + break; + } +} + +/* * Routine: misc_init_r * Description: Configure board specific parts */ @@ -422,6 +454,8 @@ int misc_init_r(void) GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); dieid_num_r(); + + beagle_dvi_pup(); beagle_display_init(); omap3_dss_enable(); @@ -120,13 +120,13 @@ pm9263 arm arm926ejs pm9263 ronetix pm9g45 arm arm926ejs pm9g45 ronetix at91 pm9g45:AT91SAM9G45 cam_enc_4xx arm arm926ejs cam_enc_4xx ait davinci cam_enc_4xx da830evm arm arm926ejs da8xxevm davinci davinci -da850_am18xxevm arm arm926ejs da8xxevm davinci davinci da850evm:DA850_AM18X_EVM -da850evm arm arm926ejs da8xxevm davinci davinci +da850_am18xxevm arm arm926ejs da8xxevm davinci davinci da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50 +da850evm arm arm926ejs da8xxevm davinci davinci da850evm:MAC_ADDR_IN_SPIFLASH davinci_dm355evm arm arm926ejs dm355evm davinci davinci davinci_dm355leopard arm arm926ejs dm355leopard davinci davinci davinci_dm365evm arm arm926ejs dm365evm davinci davinci -davinci_dm6467evm arm arm926ejs dm6467evm davinci davinci -davinci_dm6467Tevm arm arm926ejs dm6467evm davinci davinci +davinci_dm6467evm arm arm926ejs dm6467evm davinci davinci davinci_dm6467evm:REFCLK_FREQ=27000000 +davinci_dm6467Tevm arm arm926ejs dm6467evm davinci davinci davinci_dm6467evm:DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000 davinci_dvevm arm arm926ejs dvevm davinci davinci davinci_schmoogie arm arm926ejs schmoogie davinci davinci davinci_sffsdr arm arm926ejs sffsdr davinci davinci diff --git a/common/image.c b/common/image.c index 202c8a1..fbdc40a 100644 --- a/common/image.c +++ b/common/image.c @@ -1289,16 +1289,14 @@ int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size) if (((ulong) desired_addr) == ~0UL) { /* All ones means use fdt in place */ - desired_addr = fdt_blob; + of_start = fdt_blob; + lmb_reserve(lmb, (ulong)of_start, of_len); disable_relocation = 1; - } - if (desired_addr) { + } else if (desired_addr) { of_start = (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000, - ((ulong) - desired_addr) - + of_len); - if (desired_addr && of_start != desired_addr) { + (ulong)desired_addr); + if (of_start == 0) { puts("Failed using fdt_high value for Device Tree"); goto error; } diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index ed73353..1fdd071 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -70,34 +70,15 @@ static void swap_packet(uint32_t *packet, int length) #endif /* - * The i.MX28 has two ethernet interfaces, but they are not equal. - * Only the first one can access the MDIO bus. - */ -#ifdef CONFIG_MX28 -static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec) -{ - return (struct ethernet_regs *)MXS_ENET0_BASE; -} -#else -static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec) -{ - return fec->eth; -} -#endif - -/* * MII-interface related functions */ -static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr, - uint16_t *retVal) +static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, + uint8_t regAddr) { - struct eth_device *edev = eth_get_dev_by_name(dev); - struct fec_priv *fec = (struct fec_priv *)edev->priv; - struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec); - uint32_t reg; /* convenient holder for the PHY register */ uint32_t phy; /* convenient holder for the PHY */ uint32_t start; + int val; /* * reading from any PHY's register is done by properly @@ -129,10 +110,10 @@ static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr, /* * it's now safe to read the PHY's register */ - *retVal = readl(ð->mii_data); - debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr, - regAddr, *retVal); - return 0; + val = (unsigned short)readl(ð->mii_data); + debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, + regAddr, val); + return val; } static void fec_mii_setspeed(struct fec_priv *fec) @@ -143,16 +124,12 @@ static void fec_mii_setspeed(struct fec_priv *fec) */ writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, &fec->eth->mii_speed); - debug("fec_init: mii_speed %08x\n", - readl(&fec->eth->mii_speed)); + debug("%s: mii_speed %08x\n", __func__, readl(&fec->eth->mii_speed)); } -static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr, - uint16_t data) -{ - struct eth_device *edev = eth_get_dev_by_name(dev); - struct fec_priv *fec = (struct fec_priv *)edev->priv; - struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec); +static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, + uint8_t regAddr, uint16_t data) +{ uint32_t reg; /* convenient holder for the PHY register */ uint32_t phy; /* convenient holder for the PHY */ uint32_t start; @@ -178,15 +155,28 @@ static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr, * clear MII interrupt bit */ writel(FEC_IEVENT_MII, ð->ievent); - debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr, + debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, regAddr, data); return 0; } +int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr) +{ + return fec_mdio_read(bus->priv, phyAddr, regAddr); +} + +int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr, + u16 data) +{ + return fec_mdio_write(bus->priv, phyAddr, regAddr, data); +} + +#ifndef CONFIG_PHYLIB static int miiphy_restart_aneg(struct eth_device *dev) { struct fec_priv *fec = (struct fec_priv *)dev->priv; + struct ethernet_regs *eth = fec->bus->priv; int ret = 0; /* @@ -194,19 +184,18 @@ static int miiphy_restart_aneg(struct eth_device *dev) * Reset PHY, then delay 300ns */ #ifdef CONFIG_MX27 - miiphy_write(dev->name, fec->phy_id, MII_DCOUNTER, 0x00FF); + fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); #endif - miiphy_write(dev->name, fec->phy_id, MII_BMCR, - BMCR_RESET); + fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); udelay(1000); /* * Set the auto-negotiation advertisement register bits */ - miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE, + fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, LPA_100FULL | LPA_100HALF | LPA_10FULL | LPA_10HALF | PHY_ANLPAR_PSB_802_3); - miiphy_write(dev->name, fec->phy_id, MII_BMCR, + fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); if (fec->mii_postcall) @@ -218,8 +207,9 @@ static int miiphy_restart_aneg(struct eth_device *dev) static int miiphy_wait_aneg(struct eth_device *dev) { uint32_t start; - uint16_t status; + int status; struct fec_priv *fec = (struct fec_priv *)dev->priv; + struct ethernet_regs *eth = fec->bus->priv; /* * Wait for AN completion @@ -231,9 +221,9 @@ static int miiphy_wait_aneg(struct eth_device *dev) return -1; } - if (miiphy_read(dev->name, fec->phy_id, - MII_BMSR, &status)) { - printf("%s: Autonegotiation failed. status: 0x%04x\n", + status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); + if (status < 0) { + printf("%s: Autonegotiation failed. status: %d\n", dev->name, status); return -1; } @@ -241,6 +231,8 @@ static int miiphy_wait_aneg(struct eth_device *dev) return 0; } +#endif + static int fec_rx_task_enable(struct fec_priv *fec) { writel(1 << 24, &fec->eth->r_des_active); @@ -372,6 +364,21 @@ static int fec_set_hwaddr(struct eth_device *dev) return 0; } +static void fec_eth_phy_config(struct eth_device *dev) +{ +#ifdef CONFIG_PHYLIB + struct fec_priv *fec = (struct fec_priv *)dev->priv; + struct phy_device *phydev; + + phydev = phy_connect(fec->bus, fec->phy_id, dev, + PHY_INTERFACE_MODE_RGMII); + if (phydev) { + fec->phydev = phydev; + phy_config(phydev); + } +#endif +} + /** * Start the FEC engine * @param[in] dev Our device to handle @@ -379,13 +386,14 @@ static int fec_set_hwaddr(struct eth_device *dev) static int fec_open(struct eth_device *edev) { struct fec_priv *fec = (struct fec_priv *)edev->priv; + int speed; debug("fec_open: fec_open(dev)\n"); /* full-duplex, heartbeat disabled */ writel(1 << 2, &fec->eth->x_cntrl); fec->rbd_index = 0; -#if defined(CONFIG_MX6Q) +#ifdef FEC_QUIRK_ENET_MAC /* Enable ENET HW endian SWAP */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, &fec->eth->ecntrl); @@ -427,9 +435,37 @@ static int fec_open(struct eth_device *edev) } #endif +#ifdef CONFIG_PHYLIB + if (!fec->phydev) + fec_eth_phy_config(edev); + if (fec->phydev) { + /* Start up the PHY */ + phy_startup(fec->phydev); + speed = fec->phydev->speed; + } else { + speed = _100BASET; + } +#else miiphy_wait_aneg(edev); - miiphy_speed(edev->name, fec->phy_id); + speed = miiphy_speed(edev->name, fec->phy_id); miiphy_duplex(edev->name, fec->phy_id); +#endif + +#ifdef FEC_QUIRK_ENET_MAC + { + u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; + u32 rcr = (readl(&fec->eth->r_cntrl) & + ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) | + FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE; + if (speed == _1000BASET) + ecr |= FEC_ECNTRL_SPEED; + else if (speed != _100BASET) + rcr |= FEC_RCNTRL_RMII_10T; + writel(ecr, &fec->eth->ecntrl); + writel(rcr, &fec->eth->r_cntrl); + } +#endif + debug("%s:Speed=%i\n", __func__, speed); /* * Enable SmartDMA receive task @@ -541,9 +577,10 @@ static int fec_init(struct eth_device *dev, bd_t* bd) fec_tbd_init(fec); +#ifndef CONFIG_PHYLIB if (fec->xcv_type != SEVENWIRE) miiphy_restart_aneg(dev); - +#endif fec_open(dev); return 0; } @@ -745,6 +782,7 @@ static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr) { struct eth_device *edev; struct fec_priv *fec; + struct mii_dev *bus; unsigned char ethaddr[6]; uint32_t start; int ret = 0; @@ -819,15 +857,40 @@ static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr) } fec->phy_id = phy_id; - miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write); - + bus = mdio_alloc(); + if (!bus) { + printf("mdio_alloc failed\n"); + ret = -ENOMEM; + goto err3; + } + bus->read = fec_phy_read; + bus->write = fec_phy_write; + sprintf(bus->name, edev->name); +#ifdef CONFIG_MX28 + /* + * The i.MX28 has two ethernet interfaces, but they are not equal. + * Only the first one can access the MDIO bus. + */ + bus->priv = (struct ethernet_regs *)MXS_ENET0_BASE; +#else + bus->priv = fec->eth; +#endif + ret = mdio_register(bus); + if (ret) { + printf("mdio_register failed\n"); + free(bus); + ret = -ENOMEM; + goto err3; + } + fec->bus = bus; eth_register(edev); if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); memcpy(edev->enetaddr, ethaddr, 6); } - + /* Configure phy */ + fec_eth_phy_config(edev); return ret; err3: @@ -860,9 +923,11 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) return lout; } +#ifndef CONFIG_PHYLIB int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) { struct fec_priv *fec = (struct fec_priv *)dev->priv; fec->mii_postcall = cb; return 0; } +#endif diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 9825eab..2eb7803 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -198,6 +198,7 @@ struct ethernet_regs { #define FEC_RCNTRL_FCE 0x00000020 #define FEC_RCNTRL_RGMII 0x00000040 #define FEC_RCNTRL_RMII 0x00000100 +#define FEC_RCNTRL_RMII_10T 0x00000200 #define FEC_TCNTRL_GTS 0x00000001 #define FEC_TCNTRL_HBC 0x00000002 @@ -207,6 +208,7 @@ struct ethernet_regs { #define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */ #define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */ +#define FEC_ECNTRL_SPEED 0x00000020 #define FEC_ECNTRL_DBSWAP 0x00000100 #define FEC_X_WMRK_STRFWD 0x00000100 @@ -284,7 +286,12 @@ struct fec_priv { void *base_ptr; int dev_id; int phy_id; + struct mii_dev *bus; +#ifdef CONFIG_PHYLIB + struct phy_device *phydev; +#else int (*mii_postcall)(int); +#endif }; /** diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index d4e64f2..e3043df 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -20,6 +20,9 @@ * author Andy Fleming * */ +#include <config.h> +#include <common.h> +#include <micrel.h> #include <phy.h> static struct phy_driver KSZ804_driver = { @@ -42,10 +45,94 @@ static struct phy_driver KS8721_driver = { .shutdown = &genphy_shutdown, }; +/* ksz9021 PHY Registers */ +#define MII_KSZ9021_EXTENDED_CTRL 0x0b +#define MII_KSZ9021_EXTENDED_DATAW 0x0c +#define MII_KSZ9021_EXTENDED_DATAR 0x0d +#define MII_KSZ9021_PHY_CTL 0x1f +#define MIIM_KSZ9021_PHYCTL_1000 (1 << 6) +#define MIIM_KSZ9021_PHYCTL_100 (1 << 5) +#define MIIM_KSZ9021_PHYCTL_10 (1 << 4) +#define MIIM_KSZ9021_PHYCTL_DUPLEX (1 << 3) + +#define CTRL1000_PREFER_MASTER (1 << 10) +#define CTRL1000_CONFIG_MASTER (1 << 11) +#define CTRL1000_MANUAL_CONFIG (1 << 12) + +int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val) +{ + /* extended registers */ + phy_write(phydev, MDIO_DEVAD_NONE, + MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000); + return phy_write(phydev, MDIO_DEVAD_NONE, + MII_KSZ9021_EXTENDED_DATAW, val); +} + +int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum) +{ + /* extended registers */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum); + return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR); +} + +/* Micrel ksz9021 */ +static int ksz9021_config(struct phy_device *phydev) +{ + unsigned ctrl1000 = 0; + const unsigned master = CTRL1000_PREFER_MASTER | + CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG; + unsigned features = phydev->drv->features; + + if (getenv("disable_giga")) + features &= ~(SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full); + /* force master mode for 1000BaseT due to chip errata */ + if (features & SUPPORTED_1000baseT_Half) + ctrl1000 |= ADVERTISE_1000HALF | master; + if (features & SUPPORTED_1000baseT_Full) + ctrl1000 |= ADVERTISE_1000FULL | master; + phydev->advertising = phydev->supported = features; + phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000); + genphy_config_aneg(phydev); + genphy_restart_aneg(phydev); + return 0; +} + +static int ksz9021_startup(struct phy_device *phydev) +{ + unsigned phy_ctl; + genphy_update_link(phydev); + phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_PHY_CTL); + + if (phy_ctl & MIIM_KSZ9021_PHYCTL_DUPLEX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + if (phy_ctl & MIIM_KSZ9021_PHYCTL_1000) + phydev->speed = SPEED_1000; + else if (phy_ctl & MIIM_KSZ9021_PHYCTL_100) + phydev->speed = SPEED_100; + else if (phy_ctl & MIIM_KSZ9021_PHYCTL_10) + phydev->speed = SPEED_10; + return 0; +} + +static struct phy_driver ksz9021_driver = { + .name = "Micrel ksz9021", + .uid = 0x221610, + .mask = 0xfffff0, + .features = PHY_GBIT_FEATURES, + .config = &ksz9021_config, + .startup = &ksz9021_startup, + .shutdown = &genphy_shutdown, +}; + int phy_micrel_init(void) { phy_register(&KSZ804_driver); phy_register(&KS8721_driver); + phy_register(&ksz9021_driver); return 0; } diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index eb55180..7d327f7 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -733,6 +733,8 @@ int phy_startup(struct phy_device *phydev) static int __board_phy_config(struct phy_device *phydev) { + if (phydev->drv->config) + return phydev->drv->config(phydev); return 0; } @@ -741,9 +743,6 @@ int board_phy_config(struct phy_device *phydev) int phy_config(struct phy_device *phydev) { - if (phydev->drv->config) - phydev->drv->config(phydev); - /* Invoke an optional board-specific helper */ board_phy_config(phydev); diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 2fa7486..2e15318 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -33,93 +33,12 @@ #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \ "See linux mxc_spi driver from Freescale for details." - -#elif defined(CONFIG_MX31) - -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_SMC (1 << 3) -#define MXC_CSPICTRL_POL (1 << 4) -#define MXC_CSPICTRL_PHA (1 << 5) -#define MXC_CSPICTRL_SSCTL (1 << 6) -#define MXC_CSPICTRL_SSPOL (1 << 7) -#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) -#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) -#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) -#define MXC_CSPICTRL_TC (1 << 8) -#define MXC_CSPICTRL_RXOVF (1 << 6) -#define MXC_CSPICTRL_MAXBITS 0x1f - -#define MXC_CSPIPERIOD_32KHZ (1 << 15) -#define MAX_SPI_BYTES 4 - -static unsigned long spi_bases[] = { - 0x43fa4000, - 0x50010000, - 0x53f84000, -}; - -#elif defined(CONFIG_MX51) - -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) -#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) -#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) -#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) -#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) -#define MXC_CSPICTRL_MAXBITS 0xfff -#define MXC_CSPICTRL_TC (1 << 7) -#define MXC_CSPICTRL_RXOVF (1 << 6) - -#define MXC_CSPIPERIOD_32KHZ (1 << 15) -#define MAX_SPI_BYTES 32 - -/* Bit position inside CTRL register to be associated with SS */ -#define MXC_CSPICTRL_CHAN 18 - -/* Bit position inside CON register to be associated with SS */ -#define MXC_CSPICON_POL 4 -#define MXC_CSPICON_PHA 0 -#define MXC_CSPICON_SSPOL 12 - -static unsigned long spi_bases[] = { - CSPI1_BASE_ADDR, - CSPI2_BASE_ADDR, - CSPI3_BASE_ADDR, -}; - -#elif defined(CONFIG_MX35) - -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_SMC (1 << 3) -#define MXC_CSPICTRL_POL (1 << 4) -#define MXC_CSPICTRL_PHA (1 << 5) -#define MXC_CSPICTRL_SSCTL (1 << 6) -#define MXC_CSPICTRL_SSPOL (1 << 7) -#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) -#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) -#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) -#define MXC_CSPICTRL_TC (1 << 7) -#define MXC_CSPICTRL_RXOVF (1 << 6) -#define MXC_CSPICTRL_MAXBITS 0xfff - -#define MXC_CSPIPERIOD_32KHZ (1 << 15) -#define MAX_SPI_BYTES 4 +#endif static unsigned long spi_bases[] = { - 0x43fa4000, - 0x50010000, + MXC_SPI_BASE_ADDRESSES }; -#else -#error "Unsupported architecture" -#endif - #define OUT MXC_GPIO_DIRECTION_OUT #define reg_read readl @@ -129,7 +48,7 @@ struct mxc_spi_slave { struct spi_slave slave; unsigned long base; u32 ctrl_reg; -#if defined(CONFIG_MX51) +#if defined(MXC_ECSPI) u32 cfg_reg; #endif int gpio; @@ -167,7 +86,7 @@ u32 get_cspi_div(u32 div) return i; } -#if defined(CONFIG_MX31) || defined(CONFIG_MX35) +#ifdef MXC_CSPI static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, unsigned int max_hz, unsigned int mode) { @@ -204,7 +123,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, } #endif -#if defined(CONFIG_MX51) +#ifdef MXC_ECSPI static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, unsigned int max_hz, unsigned int mode) { @@ -316,7 +235,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, MXC_CSPICTRL_BITCOUNT(bitlen - 1); reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); -#ifdef CONFIG_MX51 +#ifdef MXC_ECSPI reg_write(®s->cfg, mxcs->cfg_reg); #endif diff --git a/include/configs/davinci_dm6467Tevm.h b/include/configs/davinci_dm6467Tevm.h deleted file mode 100644 index 0cbdec8..0000000 --- a/include/configs/davinci_dm6467Tevm.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Spectrum Digital TMS320DM6467T EVM board */ -#define DAVINCI_DM6467EVM -#define DAVINCI_DM6467TEVM -#define CONFIG_SYS_USE_NAND -#define CONFIG_SYS_NAND_SMALLPAGE - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* SoC Configuration */ -#define CONFIG_ARM926EJS /* arm926ejs CPU */ - -/* Clock rates detection */ -#ifndef __ASSEMBLY__ -extern unsigned int davinci_arm_clk_get(void); -#endif - -#define CFG_REFCLK_FREQ 33000000 -/* Arm Clock frequency */ -#define CONFIG_SYS_CLK_FREQ davinci_arm_clk_get() -/* Timer Input clock freq */ -#define CONFIG_SYS_HZ_CLOCK (CONFIG_SYS_CLK_FREQ/2) -#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SOC_DM646X - -/* EEPROM definitions for EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* Memory Info */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ -#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ -#define PHYS_SDRAM_1_SIZE (256 << 20) /* DDR size 256MB */ - -/* Linux interfacing */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_SYS_BARGSIZE 1024 /* Bootarg Size */ -#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */ -#define CONFIG_REVISION_TAG - -/* Serial Driver info */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 4 -#define CONFIG_SYS_NS16550_COM1 0x01c20000 -#define CONFIG_SYS_NS16550_CLK 24000000 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* I2C Configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 80000 -#define CONFIG_SYS_I2C_SLAVE 10 - -/* Network & Ethernet Configuration */ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_EMAC_MDIO_PHY_NUM 1 -#define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_CMD_NET - -/* Flash & Environment */ -#define CONFIG_SYS_NO_FLASH -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_CS 2 -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ -#define CONFIG_SYS_NAND_BASE_LIST {0x42000000, } -#define CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_ENV_OFFSET 0 -#else -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE (4 << 10) /* 4 KiB */ -#endif - -/* U-Boot general configuration */ -#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_PROMPT "DM6467 EVM > " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC -#define CONFIG_BOOTCOMMAND "source 0x82080000; dhcp; bootm" -#define CONFIG_BOOTARGS \ - "mem=120M console=ttyS0,115200n8 " \ - "root=/dev/hda1 rw noinitrd ip=dhcp" - -/* U-Boot commands */ -#include <config_cmd_default.h> -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_SETGETDCR -#ifdef CONFIG_SYS_USE_NAND -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_IMLS -#define CONFIG_CMD_NAND -#endif - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h index e0fe6b5..4f14e04 100644 --- a/include/configs/davinci_dm6467evm.h +++ b/include/configs/davinci_dm6467evm.h @@ -35,7 +35,6 @@ extern unsigned int davinci_arm_clk_get(void); #endif -#define CFG_REFCLK_FREQ 27000000 /* Arm Clock frequency */ #define CONFIG_SYS_CLK_FREQ davinci_arm_clk_get() /* Timer Input clock freq */ diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index a1fdbb8..0a704cb 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -82,17 +82,7 @@ /* * Command line configuration. */ - - -#define CONFIG_CMD_IMI -#define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMLS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_LOADS - +#include <config_cmd_default.h> #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyAM0 console=tty" @@ -157,142 +147,16 @@ * PCI definitions */ -#ifdef CONFIG_PCI /* pci support */ -#undef CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#define DEBUG +#define CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_PCI_PNP +#define CONFIG_NET_MULTI +#define CONFIG_TULIP #define CONFIG_EEPRO100 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define INTEGRATOR_BOOT_ROM_BASE 0x20000000 -#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 - -/* PCI Base area */ -#define INTEGRATOR_PCI_BASE 0x40000000 -#define INTEGRATOR_PCI_SIZE 0x3FFFFFFF - -/* memory map as seen by the CPU on the local bus */ -#define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */ -#define CPU_PCI_IO_SIZE 0x10000 - -#define CPU_PCI_CNFG_ADRS 0x61000000 /* PCI config space */ -#define CPU_PCI_CNFG_SIZE 0x1000000 - -#define PCI_MEM_BASE 0x40000000 /* 512M to xxx */ -/* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */ -#define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */ -/* unused (128-16)M from B1000000-B7FFFFFF */ -#define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */ -/* unused ((128-16)M - 64K) from XXX */ - -#define PCI_V3_BASE 0x62000000 - -/* V3 PCI bridge controller */ -#define V3_BASE 0x62000000 /* V360EPC registers */ - -#define PCI_ENET0_IOADDR (CPU_PCI_IO_ADRS) -#define PCI_ENET0_MEMADDR (PCI_MEM_BASE) - - -#define V3_PCI_VENDOR 0x00000000 -#define V3_PCI_DEVICE 0x00000002 -#define V3_PCI_CMD 0x00000004 -#define V3_PCI_STAT 0x00000006 -#define V3_PCI_CC_REV 0x00000008 -#define V3_PCI_HDR_CF 0x0000000C -#define V3_PCI_IO_BASE 0x00000010 -#define V3_PCI_BASE0 0x00000014 -#define V3_PCI_BASE1 0x00000018 -#define V3_PCI_SUB_VENDOR 0x0000002C -#define V3_PCI_SUB_ID 0x0000002E -#define V3_PCI_ROM 0x00000030 -#define V3_PCI_BPARAM 0x0000003C -#define V3_PCI_MAP0 0x00000040 -#define V3_PCI_MAP1 0x00000044 -#define V3_PCI_INT_STAT 0x00000048 -#define V3_PCI_INT_CFG 0x0000004C -#define V3_LB_BASE0 0x00000054 -#define V3_LB_BASE1 0x00000058 -#define V3_LB_MAP0 0x0000005E -#define V3_LB_MAP1 0x00000062 -#define V3_LB_BASE2 0x00000064 -#define V3_LB_MAP2 0x00000066 -#define V3_LB_SIZE 0x00000068 -#define V3_LB_IO_BASE 0x0000006E -#define V3_FIFO_CFG 0x00000070 -#define V3_FIFO_PRIORITY 0x00000072 -#define V3_FIFO_STAT 0x00000074 -#define V3_LB_ISTAT 0x00000076 -#define V3_LB_IMASK 0x00000077 -#define V3_SYSTEM 0x00000078 -#define V3_LB_CFG 0x0000007A -#define V3_PCI_CFG 0x0000007C -#define V3_DMA_PCI_ADR0 0x00000080 -#define V3_DMA_PCI_ADR1 0x00000090 -#define V3_DMA_LOCAL_ADR0 0x00000084 -#define V3_DMA_LOCAL_ADR1 0x00000094 -#define V3_DMA_LENGTH0 0x00000088 -#define V3_DMA_LENGTH1 0x00000098 -#define V3_DMA_CSR0 0x0000008B -#define V3_DMA_CSR1 0x0000009B -#define V3_DMA_CTLB_ADR0 0x0000008C -#define V3_DMA_CTLB_ADR1 0x0000009C -#define V3_DMA_DELAY 0x000000E0 -#define V3_MAIL_DATA 0x000000C0 -#define V3_PCI_MAIL_IEWR 0x000000D0 -#define V3_PCI_MAIL_IERD 0x000000D2 -#define V3_LB_MAIL_IEWR 0x000000D4 -#define V3_LB_MAIL_IERD 0x000000D6 -#define V3_MAIL_WR_STAT 0x000000D8 -#define V3_MAIL_RD_STAT 0x000000DA -#define V3_QBA_MAP 0x000000DC - -/* SYSTEM register bits */ -#define V3_SYSTEM_M_RST_OUT (1 << 15) -#define V3_SYSTEM_M_LOCK (1 << 14) - -/* PCI_CFG bits */ -#define V3_PCI_CFG_M_RETRY_EN (1 << 10) -#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) -#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) - -/* PCI MAP register bits (PCI -> Local bus) */ -#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 -#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) -#define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10) -#define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8) -#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 -#define V3_PCI_MAP_M_REG_EN (1 << 1) -#define V3_PCI_MAP_M_ENABLE (1 << 0) - -/* 9 => 512M window size */ -#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090 - -/* A => 1024M window size */ -#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0 - -/* LB_BASE register bits (Local bus -> PCI) */ -#define V3_LB_BASE_M_MAP_ADR 0xFFF00000 -#define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9) -#define V3_LB_BASE_M_ADR_SIZE 0x000000F0 -#define V3_LB_BASE_M_PREFETCH (1 << 3) -#define V3_LB_BASE_M_ENABLE (1 << 0) - -/* PCI COMMAND REGISTER bits */ -#define V3_COMMAND_M_FBB_EN (1 << 9) -#define V3_COMMAND_M_SERR_EN (1 << 8) -#define V3_COMMAND_M_PAR_EN (1 << 6) -#define V3_COMMAND_M_MASTER_EN (1 << 2) -#define V3_COMMAND_M_MEM_EN (1 << 1) -#define V3_COMMAND_M_IO_EN (1 << 0) - -#define INTEGRATOR_SC_BASE 0x11000000 -#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18 -#define INTEGRATOR_SC_PCIENABLE \ - (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) -#endif /* CONFIG_PCI */ /*----------------------------------------------------------------------- * There are various dependencies on the core module (CM) fitted * Users should refer to their CM user guide diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index ccbdf44..57610a6 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -31,8 +31,13 @@ #ifndef __CONFIG_H #define __CONFIG_H +/* Integrator-specific configuration */ #define CONFIG_INTEGRATOR -#define CONFIG_ARCH_INTEGRATOR +#define CONFIG_ARCH_CINTEGRATOR +#define CONFIG_CM_INIT +#define CONFIG_CM_REMAP +#define CONFIG_CM_SPD_DETECT + /* * High Level Configuration Options * (easy to change) @@ -47,6 +52,7 @@ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ + /* * Size of malloc() pool */ @@ -85,32 +91,14 @@ /* * Command line configuration. */ -#define CONFIG_CMD_BDI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING - +#include <config_cmd_default.h> -#if 0 #define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS "root=/dev/nfs nfsroot=<IP address>:/<exported rootfs> mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" -#define CONFIG_BOOTCOMMAND "bootp ; bootm" -#endif -/* The kernel command line & boot command below are for a platform flashed with afu.axf - -Image 666 Block 0 End Block 0 address 0x24000000 exec 0x24000000- name u-boot -Image 667 Block 1 End Block 13 address 0x24040000 exec 0x24040000- name u-linux -Image 668 Block 14 End Block 33 address 0x24380000 exec 0x24380000- name rootfs -SIB at Block62 End Block62 address 0x24f80000 - -*/ -#define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0 console=ttyAMA0" -#define CONFIG_BOOTCOMMAND "cp 0x24080000 0x7fc0 0x100000; bootm" +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" +#define CONFIG_BOOTCOMMAND "tftpboot ; bootm" +#define CONFIG_SERVERIP 192.168.1.100 +#define CONFIG_IPADDR 192.168.1.104 +#define CONFIG_BOOTFILE "uImage" /* * Miscellaneous configurable options @@ -201,15 +189,6 @@ SIB at Block62 End Block62 address 0x24f80000 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ #define CONFIG_ENV_SIZE 8192 /* 8KB */ -/*----------------------------------------------------------------------- - * CP control registers - */ -#define CPCR_BASE 0xCB000000 /* CP Registers*/ -#define OS_FLASHPROG 0x00000004 /* Flash register*/ -#define CPMASK_EXTRABANK 0x8 -#define CPMASK_FLASHSIZE 0x4 -#define CPMASK_FLWREN 0x2 -#define CPMASK_FLVPPEN 0x1 /* * The ARM boot monitor initializes the board. diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 0940e86..1315c3c 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -219,6 +219,8 @@ "else run nandboot; fi" #define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING + /* * Miscellaneous configurable options */ @@ -351,11 +353,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 256 #define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ - CONFIG_SYS_NAND_ECCSIZE) -#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ - CONFIG_SYS_NAND_ECCSTEPS) - #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index bea46e7..04967d7 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -56,6 +56,7 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_GPIO #define CONFIG_CMD_MII @@ -63,6 +64,9 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_NFS #define CONFIG_CMD_PING +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_USB /* * Memory configurations @@ -125,9 +129,11 @@ * MMC Driver */ #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET (256 * 1024) -#define CONFIG_ENV_SIZE (16 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 +#ifdef CONFIG_ENV_IS_IN_MMC + #define CONFIG_ENV_OFFSET (256 * 1024) + #define CONFIG_ENV_SIZE (16 * 1024) + #define CONFIG_SYS_MMC_ENV_DEV 0 +#endif #define CONFIG_CMD_SAVEENV #ifdef CONFIG_CMD_MMC #define CONFIG_MMC @@ -150,6 +156,58 @@ #endif /* + * RTC + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MXS +#endif + +/* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MXS +#define CONFIG_EHCI_MXS_PORT 1 +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#endif + +/* + * SPI + */ +#ifdef CONFIG_CMD_SPI +#define CONFIG_HARD_SPI +#define CONFIG_MXS_SPI +#define CONFIG_SPI_HALF_DUPLEX +#define CONFIG_DEFAULT_SPI_BUS 2 +#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 + +/* SPI Flash */ +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +/* this may vary and depends on the installed chip */ +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 + +/* (redundant) environemnt in SPI flash */ +#undef CONFIG_ENV_IS_IN_SPI_FLASH +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SIZE 0x1000 /* 4KB */ +#define CONFIG_ENV_OFFSET 0x40000 /* 256K */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_BUS 2 +#define CONFIG_ENV_SPI_MAX_HZ 24000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 +#endif +#endif +#endif + +/* * Boot Linux */ #define CONFIG_CMDLINE_TAG diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index d650ee3..982f03f 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -44,6 +44,17 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SST +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS (0|(GPIO_NUMBER(3, 19)<<8)) +#define CONFIG_SF_DEFAULT_SPEED 25000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#endif + /* MMC Configs */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC @@ -66,6 +77,8 @@ #define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 6 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -163,10 +176,22 @@ /* FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) + #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 +/* #define CONFIG_ENV_IS_IN_SPI_FLASH */ + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_SECT_SIZE (8 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif #define CONFIG_OF_LIBFDT diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index bfd4570..64adc74 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -339,10 +339,6 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ - CONFIG_SYS_NAND_ECCSIZE) -#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ - CONFIG_SYS_NAND_ECCSTEPS) #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index f87696b..ba8847b 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -160,6 +160,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyO2,115200n8\0" \ + "mmcdev=0\0" \ "vram=12M\0" \ "lcdmode=800x600\0" \ "defaultdisplay=lcd\0" \ @@ -182,10 +183,10 @@ "root=ubi0:rootfs " \ "rootfstype=ubifs " \ "${kernelopts}\0" \ - "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ - "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ @@ -194,7 +195,7 @@ "run nandargs; " \ "nand read ${loadaddr} 280000 400000; " \ "bootm ${loadaddr}\0" \ - "autoboot=if mmc init 0; then " \ + "autoboot=if mmc rescan ${mmcdev}; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ @@ -304,11 +305,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ - CONFIG_SYS_NAND_ECCSIZE) -#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ - CONFIG_SYS_NAND_ECCSTEPS) - #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 diff --git a/include/configs/tt01.h b/include/configs/tt01.h index 35d2bd8..2623dbc 100644 --- a/include/configs/tt01.h +++ b/include/configs/tt01.h @@ -131,7 +131,7 @@ #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) /* smaller for faster access */ +#define CONFIG_ENV_SIZE (128 * 1024) /* Address and size of Redundant Environment Sector */ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) @@ -185,6 +185,28 @@ #define CONFIG_GENERIC_MMC #define CONFIG_MXC_MMC #define CONFIG_MXC_MCI_REGS_BASE SDHC1_BASE_ADDR + +/* video support */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_MX3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +/* splash image won't work with NAND boot, use preboot script */ +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_CONSOLE_EXTRA_INFO /* display additional board info */ +#define CONFIG_VGA_AS_SINGLE_DEVICE /* display is an output only device */ + +/* allow stdin, stdout and stderr variables to redirect output */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SILENT_CONSOLE /* UARTs used externally (release) */ +#define CONFIG_SYS_DEVICE_NULLDEV /* allow console to be turned off */ +#define CONFIG_PREBOOT + +/* allow decompressing max. 4MB */ +#define CONFIG_VIDEO_BMP_GZIP +/* this is not only used by cfb_console.c for the logo, but also in cmd_bmp.c */ +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4*1024*1024) + /* * Command definition */ @@ -201,6 +223,7 @@ * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports * a software locking scheme. */ +#define CONFIG_CMD_BMP #define CONFIG_BOOTDELAY 3 @@ -208,16 +231,25 @@ * currently a default setting for booting via script is implemented * set user to login name and serverip to tftp host, define your * boot behaviour in bootscript.loginname + * + * TT-01 board specific TFT setup (used by drivers/video/mx3fb.c) + * + * This set-up is for the L5F30947T04 by Epson, which is + * 800x480, 33MHz pixel clock, 60Hz vsync, 31.6kHz hsync + * sync must be set to: DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "bootcmd=dhcp bootscript.$(user); source\0" +"videomode=epson\0" \ +"epson=video=ctfb:x:800,y:480,depth:16,mode:0,pclk:30076," \ + "le:215,ri:1,up:32,lo:13,hs:7,vs:10,sync:100663296,vmode:0\0" \ +"bootcmd=dhcp bootscript.${user}; source\0" #define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */ #define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */ /* Miscellaneous configurable options */ -#define CONFIG_HUSH_PARSER -#define CONFIG_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_PROMPT "TT01> " diff --git a/include/micrel.h b/include/micrel.h new file mode 100644 index 0000000..25e8a46 --- /dev/null +++ b/include/micrel.h @@ -0,0 +1,16 @@ +#ifndef _MICREL_H + +#define MII_KSZ9021_EXT_COMMON_CTRL 0x100 +#define MII_KSZ9021_EXT_STRAP_STATUS 0x101 +#define MII_KSZ9021_EXT_OP_STRAP_OVERRIDE 0x102 +#define MII_KSZ9021_EXT_OP_STRAP_STATUS 0x103 +#define MII_KSZ9021_EXT_RGMII_CLOCK_SKEW 0x104 +#define MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW 0x105 +#define MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW 0x106 +#define MII_KSZ9021_EXT_ANALOG_TEST 0x107 + +struct phy_device; +int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val); +int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum); + +#endif diff --git a/include/phy.h b/include/phy.h index bc522d5..3c30f11 100644 --- a/include/phy.h +++ b/include/phy.h @@ -207,6 +207,7 @@ int phy_config(struct phy_device *phydev); int phy_shutdown(struct phy_device *phydev); int phy_register(struct phy_driver *drv); int genphy_config_aneg(struct phy_device *phydev); +int genphy_restart_aneg(struct phy_device *phydev); int genphy_update_link(struct phy_device *phydev); int genphy_config(struct phy_device *phydev); int genphy_startup(struct phy_device *phydev); |