diff options
33 files changed, 2039 insertions, 751 deletions
@@ -777,6 +777,7 @@ LIST_coldfire=" \ EB+MCF-EV123 \ EB+MCF-EV123_internal \ idmr \ + M5208EVBE \ M52277EVB \ M5235EVB \ M5249EVB \ @@ -1993,6 +1993,9 @@ ZPC1900_config: unconfig ## Coldfire ######################################################################### +M5208EVBE_config : unconfig + @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5208evbe freescale + M52277EVB_config \ M52277EVB_spansion_config \ M52277EVB_stmicro_config : unconfig @@ -2097,18 +2100,15 @@ M5373EVB_config : unconfig @$(MKCONFIG) -a M5373EVB m68k mcf532x m5373evb freescale M54451EVB_config \ -M54451EVB_spansion_config \ M54451EVB_stmicro_config : unconfig @case "$@" in \ - M54451EVB_config) FLASH=SPANSION;; \ - M54451EVB_spansion_config) FLASH=SPANSION;; \ + M54451EVB_config) FLASH=NOR;; \ M54451EVB_stmicro_config) FLASH=STMICRO;; \ esac; \ - if [ "$${FLASH}" = "SPANSION" ] ; then \ - echo "#define CONFIG_SYS_SPANSION_BOOT" >> $(obj)include/config.h ; \ + if [ "$${FLASH}" = "NOR" ] ; then \ echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54451evb/config.tmp ; \ cp $(obj)board/freescale/m54451evb/u-boot.spa $(obj)board/freescale/m54451evb/u-boot.lds ; \ - $(XECHO) "... with SPANSION boot..." ; \ + $(XECHO) "... with NOR boot..." ; \ fi; \ if [ "$${FLASH}" = "STMICRO" ] ; then \ echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \ diff --git a/board/freescale/m5208evbe/Makefile b/board/freescale/m5208evbe/Makefile new file mode 100644 index 0000000..981763d --- /dev/null +++ b/board/freescale/m5208evbe/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m5208evbe/config.mk b/board/freescale/m5208evbe/config.mk new file mode 100644 index 0000000..ce014ed --- /dev/null +++ b/board/freescale/m5208evbe/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0 diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c new file mode 100644 index 0000000..5f99e2f --- /dev/null +++ b/board/freescale/m5208evbe/m5208evbe.c @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale M5208EVBe\n"); + return 0; +}; + +phys_size_t initdram(int board_type) +{ + volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + u32 dramsize, i; + + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i); +#ifdef CONFIG_SYS_SDRAM_BASE1 + sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i); +#endif + sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; + sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; + + udelay(500); + + /* Issue PALL */ + sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + asm("nop"); + + /* Perform two refresh cycles */ + sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + asm("nop"); + + /* Issue LEMR */ + sdram->mode = CONFIG_SYS_SDRAM_MODE; + asm("nop"); + sdram->mode = CONFIG_SYS_SDRAM_EMOD; + asm("nop"); + + sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + asm("nop"); + + sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00; + asm("nop"); + + udelay(100); + + return dramsize; +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/freescale/m5208evbe/u-boot.lds b/board/freescale/m5208evbe/u-boot.lds new file mode 100644 index 0000000..bc9d5cd --- /dev/null +++ b/board/freescale/m5208evbe/u-boot.lds @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + cpu/mcf52x2/libmcf52x2.a (.text) + lib_m68k/libm68k.a (.text) + common/dlmalloc.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/freescale/m54451evb/u-boot.spa b/board/freescale/m54451evb/u-boot.spa index 08e184c..d8caefa 100644 --- a/board/freescale/m54451evb/u-boot.spa +++ b/board/freescale/m54451evb/u-boot.spa @@ -56,10 +56,13 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/mcf5445x/start.o (.text) - lib_m68k/traps.o (.text) - lib_m68k/interrupts.o (.text) + cpu/mcf5445x/libmcf5445x.a (.text) + lib_m68k/libm68k.a (.text) + common/cmd_flash.o (.text) common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) + common/main.o (.text) + common/image.o (.text) + lib_generic/libgeneric.a (.text) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text) diff --git a/common/cmd_sf.c b/common/cmd_sf.c index 2d463a8..d571f60 100644 --- a/common/cmd_sf.c +++ b/common/cmd_sf.c @@ -48,7 +48,7 @@ static int do_spi_flash_probe(int argc, char *argv[]) goto usage; } if (argc >= 4) { - mode = simple_strtoul(argv[3], &endp, 0); + mode = simple_strtoul(argv[3], &endp, 16); if (*argv[3] == 0 || *endp != 0) goto usage; } diff --git a/cpu/mcf5227x/Makefile b/cpu/mcf5227x/Makefile index 44f9385..d0e9b45 100644 --- a/cpu/mcf5227x/Makefile +++ b/cpu/mcf5227x/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = lib$(CPU).a START = start.o -COBJS = cpu.o speed.o cpu_init.o interrupts.o dspi.o +COBJS = cpu.o speed.o cpu_init.o interrupts.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c index 8945ef3..d8bcf37 100644 --- a/cpu/mcf5227x/cpu_init.c +++ b/cpu/mcf5227x/cpu_init.c @@ -152,3 +152,56 @@ void uart_port_conf(void) break; } } + +#ifdef CONFIG_CF_DSPI +void cfspi_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + gpio->par_dspi = + GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | + GPIO_PAR_DSPI_SCK_SCK; +} + +int cfspi_claim_bus(uint bus, uint cs) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) + return -1; + + /* Clear FIFO and resume transfer */ + dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); + + switch (cs) { + case 0: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_MASK; + gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0; + break; + case 2: + gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK; + gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2; + break; + } + + return 0; +} + +void cfspi_release_bus(uint bus, uint cs) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */ + + switch (cs) { + case 0: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; + break; + case 2: + gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK; + break; + } +} +#endif diff --git a/cpu/mcf5227x/dspi.c b/cpu/mcf5227x/dspi.c deleted file mode 100644 index 7f48f91..0000000 --- a/cpu/mcf5227x/dspi.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <spi.h> -#include <malloc.h> - -#if defined(CONFIG_CF_DSPI) -#include <asm/immap.h> - -void dspi_init(void) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - - gpio->par_dspi = - GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | - GPIO_PAR_DSPI_SCK_SCK; - - dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 | - DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 | - DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 | - DSPI_DMCR_CRXF | DSPI_DMCR_CTXF; - -#ifdef CONFIG_SYS_DSPI_DCTAR0 - dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0; -#endif -#ifdef CONFIG_SYS_DSPI_DCTAR1 - dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1; -#endif -#ifdef CONFIG_SYS_DSPI_DCTAR2 - dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2; -#endif -#ifdef CONFIG_SYS_DSPI_DCTAR3 - dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3; -#endif -#ifdef CONFIG_SYS_DSPI_DCTAR4 - dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4; -#endif -#ifdef CONFIG_SYS_DSPI_DCTAR5 - dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5; -#endif -#ifdef CONFIG_SYS_DSPI_DCTAR6 - dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6; -#endif -#ifdef CONFIG_SYS_DSPI_DCTAR7 - dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7; -#endif -} - -void dspi_tx(int chipsel, u8 attrib, u16 data) -{ - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - - while ((dspi->dsr & 0x0000F000) >= 4) ; - - dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data; -} - -u16 dspi_rx(void) -{ - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - - while ((dspi->dsr & 0x000000F0) == 0) ; - - return (dspi->drfr & 0xFFFF); -} - -#if defined(CONFIG_CMD_SPI) -void spi_init_f(void) -{ -} - -void spi_init_r(void) -{ -} - -void spi_init(void) -{ - dspi_init(); -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - struct spi_slave *slave; - - slave = malloc(sizeof(struct spi_slave)); - if (!slave) - return NULL; - - switch (cs) { - case 0: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; - gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0; - break; - case 2: - gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK; - gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2; - break; - } - - slave->bus = bus; - slave->cs = cs; - - return slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - switch (slave->cs) { - case 0: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; - break; - case 2: - gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK; - break; - } - - free(slave); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) -{ - static int bWrite = 0; - u8 *spi_rd, *spi_wr; - int len = bitlen >> 3; - - spi_rd = (u8 *) din; - spi_wr = (u8 *) dout; - - /* command handling */ - if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) { - switch (*spi_wr) { - case 0x02: /* Page Prog */ - bWrite = 1; - dspi_tx(slave->cs, 0x80, spi_wr[0]); - dspi_rx(); - dspi_tx(slave->cs, 0x80, spi_wr[1]); - dspi_rx(); - dspi_tx(slave->cs, 0x80, spi_wr[2]); - dspi_rx(); - dspi_tx(slave->cs, 0x80, spi_wr[3]); - dspi_rx(); - return 0; - case 0x05: /* Read Status */ - if (len == 4) - if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF) - && (spi_wr[3] == 0xFF)) { - dspi_tx(slave->cs, 0x80, *spi_wr); - dspi_rx(); - } - return 0; - case 0x06: /* WREN */ - dspi_tx(slave->cs, 0x00, *spi_wr); - dspi_rx(); - return 0; - case 0x0B: /* Fast read */ - if ((len == 5) && (spi_wr[4] == 0)) { - dspi_tx(slave->cs, 0x80, spi_wr[0]); - dspi_rx(); - dspi_tx(slave->cs, 0x80, spi_wr[1]); - dspi_rx(); - dspi_tx(slave->cs, 0x80, spi_wr[2]); - dspi_rx(); - dspi_tx(slave->cs, 0x80, spi_wr[3]); - dspi_rx(); - dspi_tx(slave->cs, 0x80, spi_wr[4]); - dspi_rx(); - } - return 0; - case 0x9F: /* RDID */ - dspi_tx(slave->cs, 0x80, *spi_wr); - dspi_rx(); - return 0; - case 0xD8: /* Sector erase */ - if (len == 4) - if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) { - dspi_tx(slave->cs, 0x80, spi_wr[0]); - dspi_rx(); - dspi_tx(slave->cs, 0x80, spi_wr[1]); - dspi_rx(); - dspi_tx(slave->cs, 0x80, spi_wr[2]); - dspi_rx(); - dspi_tx(slave->cs, 0x00, spi_wr[3]); - dspi_rx(); - } - return 0; - } - } - - if (bWrite) - len--; - - while (len--) { - if (dout != NULL) { - dspi_tx(slave->cs, 0x80, *spi_wr); - dspi_rx(); - spi_wr++; - } - - if (din != NULL) { - dspi_tx(slave->cs, 0x80, 0); - *spi_rd = dspi_rx(); - spi_rd++; - } - } - - if (flags == SPI_XFER_END) { - if (bWrite) { - dspi_tx(slave->cs, 0x00, *spi_wr); - dspi_rx(); - bWrite = 0; - } else { - dspi_tx(slave->cs, 0x00, 0); - dspi_rx(); - } - } - - return 0; -} -#endif /* CONFIG_CMD_SPI */ - -#endif /* CONFIG_CF_DSPI */ diff --git a/cpu/mcf52x2/config.mk b/cpu/mcf52x2/config.mk index 8292736..52751be 100644 --- a/cpu/mcf52x2/config.mk +++ b/cpu/mcf52x2/config.mk @@ -26,6 +26,7 @@ PLATFORM_RELFLAGS += -ffixed-d7 -msep-data cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') +is5208:=$(shell grep CONFIG_M5208 $(TOPDIR)/include/$(cfg)) is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg)) is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg)) is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg)) @@ -36,6 +37,9 @@ is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg)) ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1) +ifneq (,$(findstring CONFIG_M5208,$(is5208))) +PLATFORM_CPPFLAGS += -mcpu=5208 +endif ifneq (,$(findstring CONFIG_M5249,$(is5249))) PLATFORM_CPPFLAGS += -mcpu=5249 endif diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c index 32d6c40..2cfe631 100644 --- a/cpu/mcf52x2/cpu.c +++ b/cpu/mcf52x2/cpu.c @@ -34,6 +34,72 @@ #include <asm/immap.h> #include <netdev.h> +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_M5208 +int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM); + + udelay(1000); + + rcm->rcr = RCM_RCR_SOFTRST; + + /* we don't return! */ + return 0; +}; + +int checkcpu(void) +{ + char buf1[32], buf2[32]; + + printf("CPU: Freescale Coldfire MCF5208\n" + " CPU CLK %s MHz BUS CLK %s MHz\n", + strmhz(buf1, gd->cpu_clk), + strmhz(buf2, gd->bus_clk)); + return 0; +}; + +#if defined(CONFIG_WATCHDOG) +/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{ + volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + wdt->sr = 0x5555; + wdt->sr = 0xAAAA; +} + +int watchdog_disable(void) +{ + volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + + wdt->sr = 0x5555; /* reset watchdog counteDECLARE_GLOBAL_DATA_PTR; +r */ + wdt->sr = 0xAAAA; + wdt->cr = 0; /* disable watchdog timer */ + + puts("WATCHDOG:disabled\n"); + return (0); +} + +int watchdog_init(void) +{ + volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + + wdt->cr = 0; /* disable watchdog */ + + /* set timeout and enable watchdog */ + wdt->mr = + ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1; + wdt->sr = 0x5555; /* reset watchdog counter */ + wdt->sr = 0xAAAA; + + puts("WATCHDOG:enabled\n"); + return (0); +} +#endif /* #ifdef CONFIG_WATCHDOG */ +#endif /* #ifdef CONFIG_M5208 */ + #ifdef CONFIG_M5271 /* * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 11f70b0..7cea655 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -101,6 +101,95 @@ void init_fbcs(void) } #endif +#if defined(CONFIG_M5208) +void cpu_init_f(void) +{ + volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + +#ifndef CONFIG_WATCHDOG + volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG; + + /* Disable the watchdog if we aren't using it */ + wdg->cr = 0; +#endif + + scm1->mpr = 0x77777777; + scm1->pacra = 0; + scm1->pacrb = 0; + scm1->pacrc = 0; + scm1->pacrd = 0; + scm1->pacre = 0; + scm1->pacrf = 0; + + /* FlexBus Chipselect */ + init_fbcs(); + + icache_enable(); +} + +/* initialize higher level parts of CPU like timers */ +int cpu_init_r(void) +{ + return (0); +} + +void uart_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (CONFIG_SYS_UART_PORT) { + case 0: + gpio->par_uart &= GPIO_PAR_UART0_MASK; + gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); + break; + case 1: + gpio->par_uart &= GPIO_PAR_UART0_MASK; + gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD); + break; + case 2: +#ifdef CONFIG_SYS_UART2_PRI_GPIO + gpio->par_timer &= + (GPIO_PAR_TMR_TIN0_MASK | GPIO_PAR_TMR_TIN1_MASK); + gpio->par_timer |= + (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD); +#endif +#ifdef CONFIG_SYS_UART2_ALT1_GPIO + gpio->par_feci2c &= + (GPIO_PAR_FECI2C_MDC_MASK | GPIO_PAR_FECI2C_MDIO_MASK); + gpio->par_feci2c |= + (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD); +#endif +#ifdef CONFIG_SYS_UART2_ALT1_GPIO + gpio->par_feci2c &= + (GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK); + gpio->par_feci2c |= + (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); +#endif + break; + } +} + +#if defined(CONFIG_CMD_NET) +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->par_fec |= + GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; + gpio->par_feci2c |= + GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO; + } else { + gpio->par_fec &= + (GPIO_PAR_FEC_7W_MASK & GPIO_PAR_FEC_MII_MASK); + gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_MASK; + } + return 0; +} +#endif /* CONFIG_CMD_NET */ +#endif /* CONFIG_M5208 */ + #if defined(CONFIG_M5253) /* * Breath some life into the CPU... diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c index 0181e4b..dff8c6a 100644 --- a/cpu/mcf52x2/interrupts.c +++ b/cpu/mcf52x2/interrupts.c @@ -59,13 +59,19 @@ void dtimer_intr_setup(void) #endif /* CONFIG_MCFTMR */ #endif /* CONFIG_M5272 */ -#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275) +#if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \ + defined(CONFIG_M5271) || defined(CONFIG_M5275) int interrupt_init(void) { volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ +#if defined(CONFIG_M5208) + intp->imrl0 = 0xFFFFFFFF; + intp->imrh0 = 0xFFFFFFFF; +#else intp->imrl0 |= 0x1; +#endif enable_interrupts(); return 0; diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c index c93a518..b485e1c 100644 --- a/cpu/mcf52x2/speed.c +++ b/cpu/mcf52x2/speed.c @@ -30,11 +30,16 @@ DECLARE_GLOBAL_DATA_PTR; -/* - * get_clocks() fills in gd->cpu_clock and gd->bus_clk - */ +/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ int get_clocks (void) { +#if defined(CONFIG_M5208) + volatile pll_t *pll = (pll_t *) MMAP_PLL; + + pll->odr = CONFIG_SYS_PLL_ODR; + pll->fdr = CONFIG_SYS_PLL_FDR; +#endif + #if defined(CONFIG_M5249) || defined(CONFIG_M5253) volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); unsigned long pllcr; @@ -77,7 +82,7 @@ int get_clocks (void) #endif gd->cpu_clk = CONFIG_SYS_CLK; -#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \ +#if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \ defined(CONFIG_M5271) || defined(CONFIG_M5275) gd->bus_clk = gd->cpu_clk / 2; #else diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index ba6b884..0dd4de5 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -120,6 +120,12 @@ _start: nop move.w #0x2700,%sr +#if defined(CONFIG_M5208) + /* Initialize RAMBAR: locate SRAM and validate it */ + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR1 +#endif + #if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253) move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set MBAR address + valid flag */ move.c %d0, %MBAR @@ -195,15 +201,6 @@ _after_flashbar_copy: movec %d0, %RAMBAR1 #endif -#if 0 - /* invalidate and disable cache */ - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0, %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 -#endif - /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- @@ -340,6 +337,24 @@ _int_handler: /*------------------------------------------------------------------------------*/ /* cache functions */ +#ifdef CONFIG_M5208 + .globl icache_enable +icache_enable: + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0 /* Setup cache mask */ + movec %d0, %ACR0 /* Enable cache */ + + move.l #0x80000200, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + nop + + move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts +#endif + #ifdef CONFIG_M5271 .globl icache_enable icache_enable: diff --git a/cpu/mcf5445x/Makefile b/cpu/mcf5445x/Makefile index a549fdd..26ec298 100644 --- a/cpu/mcf5445x/Makefile +++ b/cpu/mcf5445x/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = lib$(CPU).a START = start.o -COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o +COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c index 7e04e32..48b37df 100644 --- a/cpu/mcf5445x/cpu_init.c +++ b/cpu/mcf5445x/cpu_init.c @@ -171,3 +171,69 @@ int fecpin_setclear(struct eth_device *dev, int setclear) return 0; } #endif + +#ifdef CONFIG_CF_DSPI +void cfspi_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | + GPIO_PAR_DSPI_SCK_SCK; +} + +int cfspi_claim_bus(uint bus, uint cs) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) + return -1; + + /* Clear FIFO and resume transfer */ + dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); + + switch (cs) { + case 0: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; + gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0; + break; + case 1: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1; + gpio->par_dspi |= GPIO_PAR_DSPI_PCS1_PCS1; + break; + case 2: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2; + gpio->par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2; + break; + case 5: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5; + gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5; + break; + } + + return 0; +} + +void cfspi_release_bus(uint bus, uint cs) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */ + + switch (cs) { + case 0: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; + break; + case 1: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1; + break; + case 2: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2; + break; + case 5: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5; + break; + } +} +#endif diff --git a/cpu/mcf5445x/dspi.c b/cpu/mcf5445x/dspi.c deleted file mode 100644 index 6d3ebab..0000000 --- a/cpu/mcf5445x/dspi.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - * - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <spi.h> -#include <malloc.h> - -#if defined(CONFIG_CF_DSPI) -#include <asm/immap.h> - -void dspi_init(void) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - - gpio->par_dspi = GPIO_PAR_DSPI_PCS5_PCS5 | GPIO_PAR_DSPI_PCS2_PCS2 | - GPIO_PAR_DSPI_PCS1_PCS1 | GPIO_PAR_DSPI_PCS0_PCS0 | - GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | - GPIO_PAR_DSPI_SCK_SCK; - - dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 | - DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 | - DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 | - DSPI_DMCR_CRXF | DSPI_DMCR_CTXF; - -#ifdef CONFIG_SYS_DSPI_DCTAR0 - dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0; -#endif -#ifdef CONFIG_SYS_DSPI_DCTAR1 - dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1; -#endif -#ifdef CONFIG_SYS_DSPI_DCTAR2 - dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2; -#endif -#ifdef CONFIG_SYS_DSPI_DCTAR3 - dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3; -#endif -#ifdef CONFIG_SYS_DSPI_DCTAR4 - dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4; -#endif -#ifdef CONFIG_SYS_DSPI_DCTAR5 - dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5; -#endif -#ifdef CONFIG_SYS_DSPI_DCTAR6 - dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6; -#endif -#ifdef CONFIG_SYS_DSPI_DCTAR7 - dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7; -#endif -} - -void dspi_tx(int chipsel, u8 attrib, u16 data) -{ - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - - while ((dspi->dsr & 0x0000F000) >= 4) ; - - dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data; -} - -u16 dspi_rx(void) -{ - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - - while ((dspi->dsr & 0x000000F0) == 0) ; - - return (dspi->drfr & 0xFFFF); -} - -#if defined(CONFIG_CMD_SPI) -void spi_init_f(void) -{ -} - -void spi_init_r(void) -{ -} - -void spi_init(void) -{ - dspi_init(); -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct spi_slave *slave; - - slave = malloc(sizeof(struct spi_slave)); - if (!slave) - return NULL; - - slave->bus = bus; - slave->cs = cs; - - return slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - free(slave); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) -{ - static int bWrite = 0; - u8 *spi_rd, *spi_wr; - int len = bitlen >> 3; - - spi_rd = (u8 *) din; - spi_wr = (u8 *) dout; - - /* command handling */ - if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) { - switch (*spi_wr) { - case 0x02: /* Page Prog */ - bWrite = 1; - dspi_tx(slave->cs, 0x80, spi_wr[0]); - dspi_rx(); - dspi_tx(slave->cs, 0x80, spi_wr[1]); - dspi_rx(); - dspi_tx(slave->cs, 0x80, spi_wr[2]); - dspi_rx(); - dspi_tx(slave->cs, 0x80, spi_wr[3]); - dspi_rx(); - return 0; - case 0x05: /* Read Status */ - if (len == 4) - if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF) - && (spi_wr[3] == 0xFF)) { - dspi_tx(slave->cs, 0x80, *spi_wr); - dspi_rx(); - } - return 0; - case 0x06: /* WREN */ - dspi_tx(slave->cs, 0x00, *spi_wr); - dspi_rx(); - return 0; - case 0x0B: /* Fast read */ - if ((len == 5) && (spi_wr[4] == 0)) { - dspi_tx(slave->cs, 0x80, spi_wr[0]); - dspi_rx(); - dspi_tx(slave->cs, 0x80, spi_wr[1]); - dspi_rx(); - dspi_tx(slave->cs, 0x80, spi_wr[2]); - dspi_rx(); - dspi_tx(slave->cs, 0x80, spi_wr[3]); - dspi_rx(); - dspi_tx(slave->cs, 0x80, spi_wr[4]); - dspi_rx(); - } - return 0; - case 0x9F: /* RDID */ - dspi_tx(slave->cs, 0x80, *spi_wr); - dspi_rx(); - return 0; - case 0xD8: /* Sector erase */ - if (len == 4) - if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) { - dspi_tx(slave->cs, 0x80, spi_wr[0]); - dspi_rx(); - dspi_tx(slave->cs, 0x80, spi_wr[1]); - dspi_rx(); - dspi_tx(slave->cs, 0x80, spi_wr[2]); - dspi_rx(); - dspi_tx(slave->cs, 0x00, spi_wr[3]); - dspi_rx(); - } - return 0; - } - } - - if (bWrite) - len--; - - while (len--) { - if (dout != NULL) { - dspi_tx(slave->cs, 0x80, *spi_wr); - dspi_rx(); - spi_wr++; - } - - if (din != NULL) { - dspi_tx(slave->cs, 0x80, 0); - *spi_rd = dspi_rx(); - spi_rd++; - } - } - - if (flags == SPI_XFER_END) { - if (bWrite) { - dspi_tx(slave->cs, 0x00, *spi_wr); - dspi_rx(); - bWrite = 0; - } else { - dspi_tx(slave->cs, 0x00, 0); - dspi_rx(); - } - } - - return 0; -} -#endif /* CONFIG_CMD_SPI */ - -#endif /* CONFIG_CF_DSPI */ diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S index 26fb2ce..c156bab 100644 --- a/cpu/mcf5445x/start.S +++ b/cpu/mcf5445x/start.S @@ -149,9 +149,35 @@ asm_sbf_img_hdr: .long 0x00030000 /* image length */ .long TEXT_BASE /* image to be relocated at */ + + asm_dram_init: + move.w #0x2700,%sr /* Mask off Interrupt */ + + move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0 + movec %d0, %VBR + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 - movec %d0, %RAMBAR1 /* init Rambar */ + movec %d0, %RAMBAR1 + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(CACR_STATUS), %a1 /* CACR */ + move.l #(ICACHE_STATUS), %a2 /* icache */ + move.l #(DCACHE_STATUS), %a3 /* dcache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + move.l %d0, (%a3) + + /* invalidate and disable cache */ + move.l #0x01004100, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + movec %d0, %ACR2 + movec %d0, %ACR3 + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- @@ -163,10 +189,7 @@ asm_dram_init: move.l #0xFC008004, %a1 move.l #(CONFIG_SYS_CS0_MASK), (%a1) - /* - * Dram Initialization - * a1, a2, and d0 - */ + /* Dram Initialization a1, a2, and d0 */ /* mscr sdram */ move.l #0xFC0A4074, %a1 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1) @@ -209,24 +232,21 @@ dramsz_loop: move.l #0xFC0B8000, %a1 /* Mode */ move.l #0xFC0B8004, %a2 /* Ctrl */ -#ifdef CONFIG_M54455EVB /* Issue PALL */ move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) nop +#ifdef CONFIG_M54455EVB /* Issue LEMR */ move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1) nop move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1) nop - - move.l #1000, %d0 -wait1000: - nop - subq.l #1, %d0 - bne wait1000 #endif + move.l #1000, %d1 + jsr asm_delay + /* Issue PALL */ move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) nop @@ -246,25 +266,24 @@ wait1000: move.l #(CONFIG_SYS_SDRAM_MODE), (%a1) nop move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1) - nop #endif - move.l #500, %d0 -wait500: - nop - subq.l #1, %d0 - bne wait500 + move.l #500, %d1 + jsr asm_delay - move.l #(CONFIG_SYS_SDRAM_CTRL), %d0 - and.l #0x7FFFFFFF, %d0 + move.l #(CONFIG_SYS_SDRAM_CTRL), %d1 + and.l #0x7FFFFFFF, %d1 #ifdef CONFIG_M54455EVB - or.l #0x10000c00, %d0 + or.l #0x10000C00, %d1 #elif defined(CONFIG_M54451EVB) - or.l #0x10000000, %d0 + or.l #0x10000C00, %d1 #endif - move.l %d0, (%a2) + move.l %d1, (%a2) nop + move.l #2000, %d1 + jsr asm_delay + /* * DSPI Initialization * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h @@ -274,6 +293,7 @@ wait500: * a4 - Dst addr */ /* Enable pins for DSPI mode - chip-selects are enabled later */ +asm_dspi_init: move.l #0xFC0A4063, %a0 move.b #0x7F, (%a0) @@ -367,27 +387,29 @@ asm_dspi_rd_status: move.b (%a3), %d1 rts + +asm_delay: + nop + subq.l #1, %d1 + bne asm_delay + rts #endif /* CONFIG_CF_SBF */ .text . = 0x400 .globl _start _start: +#if !defined(CONFIG_CF_SBF) nop nop move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ -#if defined(CONFIG_CF_SBF) - move.l #TEXT_BASE, %d0 - movec %d0, %VBR -#else move.l #CONFIG_SYS_FLASH_BASE, %d0 movec %d0, %VBR move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 -#endif /* initialize general use internal ram */ move.l #0, %d0 @@ -411,6 +433,7 @@ _start: the first c-code */ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- +#endif move.l #__got_start, %a5 /* put relocation table address to a5 */ @@ -532,7 +555,7 @@ icache_enable: move.l #0x00040100, %d0 /* Invalidate icache */ movec %d0, %CACR - move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 /* Setup icache */ + move.l #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0 /* Setup icache */ movec %d0, %ACR2 move.l #0x04088020, %d0 /* Enable bcache and icache */ diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index a9f67a0..824d8e7 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -28,6 +28,7 @@ LIB := $(obj)libspi.a COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o +COBJS-$(CONFIG_CF_SPI) += cf_spi.o COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c new file mode 100644 index 0000000..722aafc --- /dev/null +++ b/drivers/spi/cf_spi.c @@ -0,0 +1,357 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <spi.h> +#include <malloc.h> +#include <asm/immap.h> + +struct cf_spi_slave { + struct spi_slave slave; + uint baudrate; + int charbit; +}; + +int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, + void *din, ulong flags); +struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode); +void cfspi_init(void); +void cfspi_tx(u32 ctrl, u16 data); +u16 cfspi_rx(void); + +extern void cfspi_port_conf(void); +extern int cfspi_claim_bus(uint bus, uint cs); +extern void cfspi_release_bus(uint bus, uint cs); + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CF_DSPI) +/* DSPI specific mode */ +#define SPI_MODE_MOD 0x00200000 +#define SPI_DBLRATE 0x00100000 + +void cfspi_init(void) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + + cfspi_port_conf(); /* port configuration */ + + dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 | + DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 | + DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 | + DSPI_MCR_CRXF | DSPI_MCR_CTXF; + + /* Default setting in platform configuration */ +#ifdef CONFIG_SYS_DSPI_CTAR0 + dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0; +#endif +#ifdef CONFIG_SYS_DSPI_CTAR1 + dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1; +#endif +#ifdef CONFIG_SYS_DSPI_CTAR2 + dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2; +#endif +#ifdef CONFIG_SYS_DSPI_CTAR3 + dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3; +#endif +#ifdef CONFIG_SYS_DSPI_CTAR4 + dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4; +#endif +#ifdef CONFIG_SYS_DSPI_CTAR5 + dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5; +#endif +#ifdef CONFIG_SYS_DSPI_CTAR6 + dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6; +#endif +#ifdef CONFIG_SYS_DSPI_CTAR7 + dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7; +#endif +} + +void cfspi_tx(u32 ctrl, u16 data) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + + while ((dspi->sr & 0x0000F000) >= 4) ; + + dspi->tfr = (ctrl | data); +} + +u16 cfspi_rx(void) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + + while ((dspi->sr & 0x000000F0) == 0) ; + + return (dspi->rfr & 0xFFFF); +} + +int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, + void *din, ulong flags) +{ + struct cf_spi_slave *cfslave = (struct cf_spi_slave *)slave; + u16 *spi_rd16 = NULL, *spi_wr16 = NULL; + u8 *spi_rd = NULL, *spi_wr = NULL; + static u32 ctrl = 0; + uint len = bitlen >> 3; + + if (cfslave->charbit == 16) { + bitlen >>= 1; + spi_wr16 = (u16 *) dout; + spi_rd16 = (u16 *) din; + } else { + spi_wr = (u8 *) dout; + spi_rd = (u8 *) din; + } + + if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN) + ctrl |= DSPI_TFR_CONT; + + ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16); + + if (len > 1) { + int tmp_len = len - 1; + while (tmp_len--) { + if (dout != NULL) { + if (cfslave->charbit == 16) + cfspi_tx(ctrl, *spi_wr16++); + else + cfspi_tx(ctrl, *spi_wr++); + cfspi_rx(); + } + + if (din != NULL) { + cfspi_tx(ctrl, 0); + if (cfslave->charbit == 16) + *spi_rd16++ = cfspi_rx(); + else + *spi_rd++ = cfspi_rx(); + } + } + + len = 1; /* remaining byte */ + } + + if ((flags & SPI_XFER_END) == SPI_XFER_END) + ctrl &= ~DSPI_TFR_CONT; + + if (len) { + if (dout != NULL) { + if (cfslave->charbit == 16) + cfspi_tx(ctrl, *spi_wr16); + else + cfspi_tx(ctrl, *spi_wr); + cfspi_rx(); + } + + if (din != NULL) { + cfspi_tx(ctrl, 0); + if (cfslave->charbit == 16) + *spi_rd16 = cfspi_rx(); + else + *spi_rd = cfspi_rx(); + } + } else { + /* dummy read */ + cfspi_tx(ctrl, 0); + cfspi_rx(); + } + + return 0; +} + +struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode) +{ + /* + * bit definition for mode: + * bit 31 - 28: Transfer size 3 to 16 bits + * 27 - 26: PCS to SCK delay prescaler + * 25 - 24: After SCK delay prescaler + * 23 - 22: Delay after transfer prescaler + * 21 : Allow overwrite for bit 31-22 and bit 20-8 + * 20 : Double baud rate + * 19 - 16: PCS to SCK delay scaler + * 15 - 12: After SCK delay scaler + * 11 - 8: Delay after transfer scaler + * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST + */ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + int prescaler[] = { 2, 3, 5, 7 }; + int scaler[] = { + 2, 4, 6, 8, + 16, 32, 64, 128, + 256, 512, 1024, 2048, + 4096, 8192, 16384, 32768 + }; + int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0; + int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed; + u32 bus_setup = 0; + + tmp = (prescaler[3] * scaler[15]); + /* Maximum and minimum baudrate it can handle */ + if ((cfslave->baudrate > (gd->bus_clk >> 1)) || + (cfslave->baudrate < (gd->bus_clk / tmp))) { + printf("Exceed baudrate limitation: Max %d - Min %d\n", + (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp)); + return NULL; + } + + /* Activate Double Baud when it exceed 1/4 the bus clk */ + if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) || + (cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) { + bus_setup |= DSPI_CTAR_DBR; + dbr = 1; + } + + if (mode & SPI_CPOL) + bus_setup |= DSPI_CTAR_CPOL; + if (mode & SPI_CPHA) + bus_setup |= DSPI_CTAR_CPHA; + if (mode & SPI_LSB_FIRST) + bus_setup |= DSPI_CTAR_LSBFE; + + /* Overwrite default value set in platform configuration file */ + if (mode & SPI_MODE_MOD) { + + if ((mode & 0xF0000000) == 0) + bus_setup |= + dspi->ctar[cfslave->slave.bus] & 0x78000000; + else + bus_setup |= ((mode & 0xF0000000) >> 1); + + /* + * Check to see if it is enabled by default in platform + * config, or manual setting passed by mode parameter + */ + if (mode & SPI_DBLRATE) { + bus_setup |= DSPI_CTAR_DBR; + dbr = 1; + } + bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */ + bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */ + } else + bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0); + + cfslave->charbit = + ((dspi->ctar[cfslave->slave.bus] & 0x78000000) == + 0x78000000) ? 16 : 8; + + pbrcnt = sizeof(prescaler) / sizeof(int); + brcnt = sizeof(scaler) / sizeof(int); + + /* baudrate calculation - to closer value, may not be exact match */ + for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) { + baud_speed = gd->bus_clk / prescaler[i]; + for (j = 0; j < brcnt; j++) { + tmp = (baud_speed / scaler[j]) * (1 + dbr); + + if (tmp > cfslave->baudrate) + diff = tmp - cfslave->baudrate; + else + diff = cfslave->baudrate - tmp; + + if (diff < bestmatch) { + bestmatch = diff; + best_i = i; + best_j = j; + } + } + } + bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j)); + dspi->ctar[cfslave->slave.bus] = bus_setup; + + return &cfslave->slave; +} +#endif /* CONFIG_CF_DSPI */ + +#ifdef CONFIG_CF_QSPI +/* 52xx, 53xx */ +#endif /* CONFIG_CF_QSPI */ + +#ifdef CONFIG_CMD_SPI +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8))) + return 1; + else + return 0; +} + +void spi_init_f(void) +{ +} + +void spi_init_r(void) +{ +} + +void spi_init(void) +{ + cfspi_init(); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct cf_spi_slave *cfslave; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + cfslave = malloc(sizeof(struct cf_spi_slave)); + if (!cfslave) + return NULL; + + cfslave->slave.bus = bus; + cfslave->slave.cs = cs; + cfslave->baudrate = max_hz; + + /* specific setup */ + return cfspi_setup_slave(cfslave, mode); +} + +void spi_free_slave(struct spi_slave *slave) +{ + free(slave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return cfspi_claim_bus(slave->bus, slave->cs); +} + +void spi_release_bus(struct spi_slave *slave) +{ + cfspi_release_bus(slave->bus, slave->cs); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + return cfspi_xfer(slave, bitlen, dout, din, flags); +} +#endif /* CONFIG_CMD_SPI */ diff --git a/include/asm-m68k/coldfire/dspi.h b/include/asm-m68k/coldfire/dspi.h index 4b7d61e..02d1409 100644 --- a/include/asm-m68k/coldfire/dspi.h +++ b/include/asm-m68k/coldfire/dspi.h @@ -26,140 +26,133 @@ #ifndef __DSPI_H__ #define __DSPI_H__ -/********************************************************************* -* DMA Serial Peripheral Interface (DSPI) -*********************************************************************/ - +/* DMA Serial Peripheral Interface (DSPI) */ typedef struct dspi { - u32 dmcr; - u8 resv0[0x4]; - u32 dtcr; - u32 dctar0; - u32 dctar1; - u32 dctar2; - u32 dctar3; - u32 dctar4; - u32 dctar5; - u32 dctar6; - u32 dctar7; - u32 dsr; - u32 dirsr; - u32 dtfr; - u32 drfr; + u32 mcr; /* 0x00 */ + u32 resv0; /* 0x04 */ + u32 tcr; /* 0x08 */ + u32 ctar[8]; /* 0x0C - 0x28 */ + u32 sr; /* 0x2C */ + u32 irsr; /* 0x30 */ + u32 tfr; /* 0x34 - PUSHR */ + u16 resv1; /* 0x38 */ + u16 rfr; /* 0x3A - POPR */ #ifdef CONFIG_MCF547x_8x - u32 dtfdr[4]; - u8 resv1[0x30]; - u32 drfdr[4]; + u32 tfdr[4]; /* 0x3C */ + u8 resv2[0x30]; /* 0x40 */ + u32 rfdr[4]; /* 0x7C */ #else - u32 dtfdr[16]; - u32 drfdr[16]; + u32 tfdr[16]; /* 0x3C */ + u32 rfdr[16]; /* 0x7C */ #endif } dspi_t; -/* Bit definitions and macros for DMCR */ -#define DSPI_DMCR_HALT (0x00000001) -#define DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8) -#define DSPI_DMCR_CRXF (0x00000400) -#define DSPI_DMCR_CTXF (0x00000800) -#define DSPI_DMCR_DRXF (0x00001000) -#define DSPI_DMCR_DTXF (0x00002000) -#define DSPI_DMCR_MDIS (0x00004000) -#define DSPI_DMCR_CSIS0 (0x00010000) -#define DSPI_DMCR_CSIS1 (0x00020000) -#define DSPI_DMCR_CSIS2 (0x00040000) -#define DSPI_DMCR_CSIS3 (0x00080000) -#define DSPI_DMCR_CSIS4 (0x00100000) -#define DSPI_DMCR_CSIS5 (0x00200000) -#define DSPI_DMCR_CSIS6 (0x00400000) -#define DSPI_DMCR_CSIS7 (0x00800000) -#define DSPI_DMCR_ROOE (0x01000000) -#define DSPI_DMCR_PCSSE (0x02000000) -#define DSPI_DMCR_MTFE (0x04000000) -#define DSPI_DMCR_FRZ (0x08000000) -#define DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) -#define DSPI_DMCR_CSCK (0x40000000) -#define DSPI_DMCR_MSTR (0x80000000) +/* Module configuration */ +#define DSPI_MCR_MSTR (0x80000000) +#define DSPI_MCR_CSCK (0x40000000) +#define DSPI_MCR_DCONF(x) (((x)&0x03)<<28) +#define DSPI_MCR_FRZ (0x08000000) +#define DSPI_MCR_MTFE (0x04000000) +#define DSPI_MCR_PCSSE (0x02000000) +#define DSPI_MCR_ROOE (0x01000000) +#define DSPI_MCR_CSIS7 (0x00800000) +#define DSPI_MCR_CSIS6 (0x00400000) +#define DSPI_MCR_CSIS5 (0x00200000) +#define DSPI_MCR_CSIS4 (0x00100000) +#define DSPI_MCR_CSIS3 (0x00080000) +#define DSPI_MCR_CSIS2 (0x00040000) +#define DSPI_MCR_CSIS1 (0x00020000) +#define DSPI_MCR_CSIS0 (0x00010000) +#define DSPI_MCR_MDIS (0x00004000) +#define DSPI_MCR_DTXF (0x00002000) +#define DSPI_MCR_DRXF (0x00001000) +#define DSPI_MCR_CTXF (0x00000800) +#define DSPI_MCR_CRXF (0x00000400) +#define DSPI_MCR_SMPL_PT(x) (((x)&0x03)<<8) +#define DSPI_MCR_HALT (0x00000001) + +/* Transfer count */ +#define DSPI_TCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) -/* Bit definitions and macros for DTCR */ -#define DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) +/* Clock and transfer attributes */ +#define DSPI_CTAR_DBR (0x80000000) +#define DSPI_CTAR_TRSZ(x) (((x)&0x0F)<<27) +#define DSPI_CTAR_CPOL (0x04000000) +#define DSPI_CTAR_CPHA (0x02000000) +#define DSPI_CTAR_LSBFE (0x01000000) +#define DSPI_CTAR_PCSSCK(x) (((x)&0x03)<<22) +#define DSPI_CTAR_PCSSCK_7CLK (0x00A00000) +#define DSPI_CTAR_PCSSCK_5CLK (0x00800000) +#define DSPI_CTAR_PCSSCK_3CLK (0x00400000) +#define DSPI_CTAR_PCSSCK_1CLK (0x00000000) +#define DSPI_CTAR_PASC(x) (((x)&0x03)<<20) +#define DSPI_CTAR_PASC_7CLK (0x00300000) +#define DSPI_CTAR_PASC_5CLK (0x00200000) +#define DSPI_CTAR_PASC_3CLK (0x00100000) +#define DSPI_CTAR_PASC_1CLK (0x00000000) +#define DSPI_CTAR_PDT(x) (((x)&0x03)<<18) +#define DSPI_CTAR_PDT_7CLK (0x000A0000) +#define DSPI_CTAR_PDT_5CLK (0x00080000) +#define DSPI_CTAR_PDT_3CLK (0x00040000) +#define DSPI_CTAR_PDT_1CLK (0x00000000) +#define DSPI_CTAR_PBR(x) (((x)&0x03)<<16) +#define DSPI_CTAR_PBR_7CLK (0x00030000) +#define DSPI_CTAR_PBR_5CLK (0x00020000) +#define DSPI_CTAR_PBR_3CLK (0x00010000) +#define DSPI_CTAR_PBR_1CLK (0x00000000) +#define DSPI_CTAR_CSSCK(x) (((x)&0x0F)<<12) +#define DSPI_CTAR_ASC(x) (((x)&0x0F)<<8) +#define DSPI_CTAR_DT(x) (((x)&0x0F)<<4) +#define DSPI_CTAR_BR(x) (((x)&0x0F)) -/* Bit definitions and macros for DCTAR group */ -#define DSPI_DCTAR_BR(x) (((x)&0x0000000F)) -#define DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4) -#define DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8) -#define DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12) -#define DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16) -#define DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18) -#define DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20) -#define DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22) -#define DSPI_DCTAR_LSBFE (0x01000000) -#define DSPI_DCTAR_CPHA (0x02000000) -#define DSPI_DCTAR_CPOL (0x04000000) -#define DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27) -#define DSPI_DCTAR_DBR (0x80000000) -#define DSPI_DCTAR_PCSSCK_1CLK (0x00000000) -#define DSPI_DCTAR_PCSSCK_3CLK (0x00400000) -#define DSPI_DCTAR_PCSSCK_5CLK (0x00800000) -#define DSPI_DCTAR_PCSSCK_7CLK (0x00A00000) -#define DSPI_DCTAR_PASC_1CLK (0x00000000) -#define DSPI_DCTAR_PASC_3CLK (0x00100000) -#define DSPI_DCTAR_PASC_5CLK (0x00200000) -#define DSPI_DCTAR_PASC_7CLK (0x00300000) -#define DSPI_DCTAR_PDT_1CLK (0x00000000) -#define DSPI_DCTAR_PDT_3CLK (0x00040000) -#define DSPI_DCTAR_PDT_5CLK (0x00080000) -#define DSPI_DCTAR_PDT_7CLK (0x000A0000) -#define DSPI_DCTAR_PBR_1CLK (0x00000000) -#define DSPI_DCTAR_PBR_3CLK (0x00010000) -#define DSPI_DCTAR_PBR_5CLK (0x00020000) -#define DSPI_DCTAR_PBR_7CLK (0x00030000) +/* Status */ +#define DSPI_SR_TCF (0x80000000) +#define DSPI_SR_TXRXS (0x40000000) +#define DSPI_SR_EOQF (0x10000000) +#define DSPI_SR_TFUF (0x08000000) +#define DSPI_SR_TFFF (0x02000000) +#define DSPI_SR_RFOF (0x00080000) +#define DSPI_SR_RFDF (0x00020000) +#define DSPI_SR_TXCTR(x) (((x)&0x0F)<<12) +#define DSPI_SR_TXPTR(x) (((x)&0x0F)<<8) +#define DSPI_SR_RXCTR(x) (((x)&0x0F)<<4) +#define DSPI_SR_RXPTR(x) (((x)&0x0F)) -/* Bit definitions and macros for DSR */ -#define DSPI_DSR_RXPTR(x) (((x)&0x0000000F)) -#define DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) -#define DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) -#define DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) -#define DSPI_DSR_RFDF (0x00020000) -#define DSPI_DSR_RFOF (0x00080000) -#define DSPI_DSR_TFFF (0x02000000) -#define DSPI_DSR_TFUF (0x08000000) -#define DSPI_DSR_EOQF (0x10000000) -#define DSPI_DSR_TXRXS (0x40000000) -#define DSPI_DSR_TCF (0x80000000) +/* DMA/interrupt request selct and enable */ +#define DSPI_IRSR_TCFE (0x80000000) +#define DSPI_IRSR_EOQFE (0x10000000) +#define DSPI_IRSR_TFUFE (0x08000000) +#define DSPI_IRSR_TFFFE (0x02000000) +#define DSPI_IRSR_TFFFS (0x01000000) +#define DSPI_IRSR_RFOFE (0x00080000) +#define DSPI_IRSR_RFDFE (0x00020000) +#define DSPI_IRSR_RFDFS (0x00010000) -/* Bit definitions and macros for DIRSR */ -#define DSPI_DIRSR_RFDFS (0x00010000) -#define DSPI_DIRSR_RFDFE (0x00020000) -#define DSPI_DIRSR_RFOFE (0x00080000) -#define DSPI_DIRSR_TFFFS (0x01000000) -#define DSPI_DIRSR_TFFFE (0x02000000) -#define DSPI_DIRSR_TFUFE (0x08000000) -#define DSPI_DIRSR_EOQFE (0x10000000) -#define DSPI_DIRSR_TCFE (0x80000000) +/* Transfer control - 32-bit access */ +#define DSPI_TFR_CONT (0x80000000) +#define DSPI_TFR_CTAS(x) (((x)&0x07)<<12) +#define DSPI_TFR_EOQ (0x08000000) +#define DSPI_TFR_CTCNT (0x04000000) +#define DSPI_TFR_CS7 (0x00800000) +#define DSPI_TFR_CS6 (0x00400000) +#define DSPI_TFR_CS5 (0x00200000) +#define DSPI_TFR_CS4 (0x00100000) +#define DSPI_TFR_CS3 (0x00080000) +#define DSPI_TFR_CS2 (0x00040000) +#define DSPI_TFR_CS1 (0x00020000) +#define DSPI_TFR_CS0 (0x00010000) -/* Bit definitions and macros for DTFR */ -#define DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)) -#define DSPI_DTFR_CS0 (0x00010000) -#define DSPI_DTFR_CS2 (0x00040000) -#define DSPI_DTFR_CS3 (0x00080000) -#define DSPI_DTFR_CS5 (0x00200000) -#define DSPI_DTFR_CTCNT (0x04000000) -#define DSPI_DTFR_EOQ (0x08000000) -#define DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) -#define DSPI_DTFR_CONT (0x80000000) +/* Transfer Fifo */ +#define DSPI_TFR_TXDATA(x) (((x)&0xFFFF)) /* Bit definitions and macros for DRFR */ -#define DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)) +#define DSPI_RFR_RXDATA(x) (((x)&0xFFFF)) /* Bit definitions and macros for DTFDR group */ -#define DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF)) -#define DSPI_DTFDR_TXCMD(x) (((x)&0x0000FFFF)<<16) +#define DSPI_TFDR_TXDATA(x) (((x)&0x0000FFFF)) +#define DSPI_TFDR_TXCMD(x) (((x)&0x0000FFFF)<<16) /* Bit definitions and macros for DRFDR group */ -#define DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF)) - -void dspi_init(void); -void dspi_tx(int chipsel, u8 attrib, u16 data); -u16 dspi_rx(void); +#define DSPI_RFDR_RXDATA(x) (((x)&0x0000FFFF)) #endif /* __DSPI_H__ */ diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h index 6a3ef03..e83ce08 100644 --- a/include/asm-m68k/immap.h +++ b/include/asm-m68k/immap.h @@ -26,6 +26,35 @@ #ifndef __IMMAP_H #define __IMMAP_H +#if defined(CONFIG_MCF520x) +#include <asm/immap_520x.h> +#include <asm/m520x.h> + +#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) +#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) +#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) +#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) +#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) +#define CONFIG_SYS_TMRINTR_PRI (6) +#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif + +#ifdef CONFIG_MCFPIT +#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) +#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) +#define CONFIG_SYS_PIT_PRESCALE (6) +#endif + +#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) +#define CONFIG_SYS_NUM_IRQS (128) +#endif /* CONFIG_M520x */ + #ifdef CONFIG_M52277 #include <asm/immap_5227x.h> #include <asm/m5227x.h> diff --git a/include/asm-m68k/immap_520x.h b/include/asm-m68k/immap_520x.h new file mode 100644 index 0000000..08bc109 --- /dev/null +++ b/include/asm-m68k/immap_520x.h @@ -0,0 +1,212 @@ +/* + * MCF520x Internal Memory Map + * + * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_520X__ +#define __IMMAP_520X__ + +#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) +#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) +#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) +#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000) +#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000) +#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) +#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) +#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000) +#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) +#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x0005C000) +#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) +#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) +#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) +#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) +#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) +#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) +#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) +#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) +#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) +#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00088000) +#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x0008C000) +#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00090000) +#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) +#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) +#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) +#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000A8000) + +#include <asm/coldfire/crossbar.h> +#include <asm/coldfire/edma.h> +#include <asm/coldfire/eport.h> +#include <asm/coldfire/flexbus.h> +#include <asm/coldfire/intctrl.h> +#include <asm/coldfire/qspi.h> + +/* System Controller Module */ +typedef struct scm1 { + u32 mpr; /* 0x00 Master Privilege */ + u32 rsvd1[7]; + u32 pacra; /* 0x20 Peripheral Access Ctrl A */ + u32 pacrb; /* 0x24 Peripheral Access Ctrl B */ + u32 pacrc; /* 0x28 Peripheral Access Ctrl C */ + u32 pacrd; /* 0x2C Peripheral Access Ctrl D */ + u32 rsvd2[4]; + u32 pacre; /* 0x40 Peripheral Access Ctrl E */ + u32 pacrf; /* 0x44 Peripheral Access Ctrl F */ + u32 rsvd3[3]; + u32 bmt; /* 0x50 bus monitor */ +} scm1_t; + +typedef struct scm2 { + u8 rsvd1[19]; /* 0x00 - 0x12 */ + u8 wcr; /* 0x13 */ + u16 rsvd2; /* 0x14 - 0x15 */ + u16 cwcr; /* 0x16 */ + u8 rsvd3[3]; /* 0x18 - 0x1A */ + u8 cwsr; /* 0x1B */ + u8 rsvd4[3]; /* 0x1C - 0x1E */ + u8 scmisr; /* 0x1F */ + u8 rsvd5[79]; /* 0x20 - 0x6F */ + u32 cfadr; /* 0x70 */ + u8 rsvd7; /* 0x74 */ + u8 cfier; /* 0x75 */ + u8 cfloc; /* 0x76 */ + u8 cfatr; /* 0x77 */ + u32 rsvd8; /* 0x78 - 0x7B */ + u32 cfdtr; /* 0x7C */ +} scm2_t; + +/* Chip configuration module */ +typedef struct rcm { + u8 rcr; + u8 rsr; +} rcm_t; + +typedef struct ccm_ctrl { + u16 ccr; /* 0x00 Chip Cfg */ + u16 res1; /* 0x02 */ + u16 rcon; /* 0x04 Reset Cfg */ + u16 cir; /* 0x06 Chip ID */ +} ccm_t; + +/* GPIO port */ +typedef struct gpio_ctrl { + /* Port Output Data */ + u8 podr_busctl; /* 0x00 */ + u8 podr_be; /* 0x01 */ + u8 podr_cs; /* 0x02 */ + u8 podr_feci2c; /* 0x03 */ + u8 podr_qspi; /* 0x04 */ + u8 podr_timer; /* 0x05 */ + u8 podr_uart; /* 0x06 */ + u8 podr_fech; /* 0x07 */ + u8 podr_fecl; /* 0x08 */ + u8 res01[3]; /* 0x9 - 0x0B */ + + /* Port Data Direction */ + u8 pddr_busctl; /* 0x0C */ + u8 pddr_be; /* 0x0D */ + u8 pddr_cs; /* 0x0E */ + u8 pddr_feci2c; /* 0x0F */ + u8 pddr_qspi; /* 0x10*/ + u8 pddr_timer; /* 0x11 */ + u8 pddr_uart; /* 0x12 */ + u8 pddr_fech; /* 0x13 */ + u8 pddr_fecl; /* 0x14 */ + u8 res02[5]; /* 0x15 - 0x19 */ + + /* Port Data Direction */ + u8 ppdr_cs; /* 0x1A */ + u8 ppdr_feci2c; /* 0x1B */ + u8 ppdr_qspi; /* 0x1C */ + u8 ppdr_timer; /* 0x1D */ + u8 ppdr_uart; /* 0x1E */ + u8 ppdr_fech; /* 0x1F */ + u8 ppdr_fecl; /* 0x20 */ + u8 res03[3]; /* 0x21 - 0x23 */ + + /* Port Clear Output Data */ + u8 pclrr_busctl; /* 0x24 */ + u8 pclrr_be; /* 0x25 */ + u8 pclrr_cs; /* 0x26 */ + u8 pclrr_feci2c; /* 0x27 */ + u8 pclrr_qspi; /* 0x28 */ + u8 pclrr_timer; /* 0x29 */ + u8 pclrr_uart; /* 0x2A */ + u8 pclrr_fech; /* 0x2B */ + u8 pclrr_fecl; /* 0x2C */ + u8 res04[3]; /* 0x2D - 0x2F */ + + /* Pin Assignment */ + u8 par_busctl; /* 0x30 */ + u8 par_be; /* 0x31 */ + u8 par_cs; /* 0x32 */ + u8 par_feci2c; /* 0x33 */ + u8 par_qspi; /* 0x34 */ + u8 par_timer; /* 0x35 */ + u16 par_uart; /* 0x36 */ + u8 par_fec; /* 0x38 */ + u8 par_irq; /* 0x39 */ + + /* Mode Select Control */ + /* Drive Strength Control */ + u8 mscr_fb; /* 0x3A */ + u8 mscr_sdram; /* 0x3B */ + + u8 dscr_i2c; /* 0x3C */ + u8 dscr_misc; /* 0x3D */ + u8 dscr_fec; /* 0x3E */ + u8 dscr_uart; /* 0x3F */ + u8 dscr_qspi; /* 0x40 */ +} gpio_t; + +/* SDRAM controller */ +typedef struct sdram_ctrl { + u32 mode; /* 0x00 Mode/Extended Mode */ + u32 ctrl; /* 0x04 Ctrl */ + u32 cfg1; /* 0x08 Cfg 1 */ + u32 cfg2; /* 0x0C Cfg 2 */ + u32 res1[64]; /* 0x10 - 0x10F */ + u32 cs0; /* 0x110 Chip Select 0 Cfg */ + u32 cs1; /* 0x114 Chip Select 1 Cfg */ +} sdram_t; + +/* Clock Module */ +typedef struct pll_ctrl { + u8 odr; /* 0x00 Output divider */ + u8 rsvd1; + u8 cr; /* 0x02 Control */ + u8 rsvd2; + u8 mdr; /* 0x04 Modulation Divider */ + u8 rsvd3; + u8 fdr; /* 0x06 Feedback Divider */ + u8 rsvd4; +} pll_t; + +/* Watchdog registers */ +typedef struct wdog_ctrl { + u16 cr; /* 0x00 Control */ + u16 mr; /* 0x02 Modulus */ + u16 cntr; /* 0x04 Count */ + u16 sr; /* 0x06 Service */ +} wdog_t; + +#endif /* __IMMAP_520X__ */ diff --git a/include/asm-m68k/m520x.h b/include/asm-m68k/m520x.h new file mode 100644 index 0000000..267bfd9 --- /dev/null +++ b/include/asm-m68k/m520x.h @@ -0,0 +1,358 @@ +/* + * m520x.h -- Definitions for Freescale Coldfire 520x + * + * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __M520X__ +#define __M520X__ + +/* *** System Control Module (SCM) *** */ +#define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28) +#define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24) +#define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20) +#define MPROT_MTR 4 +#define MPROT_MTW 2 +#define MPROT_MPL 1 + +#define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28) +#define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24) +#define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20) + +#define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12) + +#define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28) +#define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24) +#define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20) +#define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8) +#define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4) +#define SCM_PACRC_PACR23(x) ((x) & 0x0F) + +#define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28) +#define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24) +#define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20) +#define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12) +#define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8) +#define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4) +#define SCM_PACRD_PACR31(x) ((x) & 0x0F) + +#define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28) +#define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24) +#define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20) +#define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16) +#define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12) + +#define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28) +#define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24) +#define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20) + +#define PACR_SP 4 +#define PACR_WP 2 +#define PACR_TP 1 + +#define SCM_BMT_BME (0x00000008) +#define SCM_BMT_BMT_MASK (0x07) +#define SCM_BMT_BMT(x) ((x) & 0x07) +#define SCM_BMT_BMT1024 (0x0000) +#define SCM_BMT_BMT512 (0x0001) +#define SCM_BMT_BMT256 (0x0002) +#define SCM_BMT_BMT128 (0x0003) +#define SCM_BMT_BMT64 (0x0004) +#define SCM_BMT_BMT32 (0x0005) +#define SCM_BMT_BMT16 (0x0006) +#define SCM_BMT_BMT8 (0x0007) + +#define SCM_CWCR_RO (0x8000) +#define SCM_CWCR_CWR_WH (0x0100) +#define SCM_CWCR_CWE (0x0080) +#define SCM_CWRI_WINDOW (0x0060) +#define SCM_CWRI_RESET (0x0040) +#define SCM_CWRI_INT_RESET (0x0020) +#define SCM_CWRI_INT (0x0000) +#define SCM_CWCR_CWT(x) (((x) & 0x001F)) + +#define SCM_ISR_CFEI (0x02) +#define SCM_ISR_CWIC (0x01) + +#define SCM_CFIER_ECFEI (0x01) + +#define SCM_CFLOC_LOC (0x80) + +#define SCM_CFATR_WRITE (0x80) +#define SCM_CFATR_SZ32 (0x20) +#define SCM_CFATR_SZ16 (0x10) +#define SCM_CFATR_SZ08 (0x00) +#define SCM_CFATR_CACHE (0x08) +#define SCM_CFATR_MODE (0x02) +#define SCM_CFATR_TYPE (0x01) + +/* *** Interrupt Controller (INTC) *** */ +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT_F1 (1) +#define INT0_LO_EPORT_F4 (2) +#define INT0_LO_EPORT_F7 (3) +#define INT1_LO_PIT0 (4) +#define INT1_LO_PIT1 (5) +/* 6 - 7 rsvd */ +#define INT0_LO_EDMA_00 (8) +#define INT0_LO_EDMA_01 (9) +#define INT0_LO_EDMA_02 (10) +#define INT0_LO_EDMA_03 (11) +#define INT0_LO_EDMA_04 (12) +#define INT0_LO_EDMA_05 (13) +#define INT0_LO_EDMA_06 (14) +#define INT0_LO_EDMA_07 (15) +#define INT0_LO_EDMA_08 (16) +#define INT0_LO_EDMA_09 (17) +#define INT0_LO_EDMA_10 (18) +#define INT0_LO_EDMA_11 (19) +#define INT0_LO_EDMA_12 (20) +#define INT0_LO_EDMA_13 (21) +#define INT0_LO_EDMA_14 (22) +#define INT0_LO_EDMA_15 (23) +#define INT0_LO_EDMA_ERR (24) +#define INT0_LO_SCM_CWIC (25) +#define INT0_LO_UART0 (26) +#define INT0_LO_UART1 (27) +#define INT0_LO_UART2 (28) +/* 29 rsvd */ +#define INT0_LO_I2C (30) +#define INT0_LO_QSPI (31) + +#define INT0_HI_DTMR0 (32) +#define INT0_HI_DTMR1 (33) +#define INT0_HI_DTMR2 (34) +#define INT0_HI_DTMR3 (35) +#define INT0_HI_FEC0_TXF (36) +#define INT0_HI_FEC0_TXB (37) +#define INT0_HI_FEC0_UN (38) +#define INT0_HI_FEC0_RL (39) +#define INT0_HI_FEC0_RXF (40) +#define INT0_HI_FEC0_RXB (41) +#define INT0_HI_FEC0_MII (42) +#define INT0_HI_FEC0_LC (43) +#define INT0_HI_FEC0_HBERR (44) +#define INT0_HI_FEC0_GRA (45) +#define INT0_HI_FEC0_EBERR (46) +#define INT0_HI_FEC0_BABT (47) +#define INT0_HI_FEC0_BABR (48) +/* 49 - 61 rsvd */ +#define INT0_HI_SCMISR_CFEI (62) + +/* *** Reset Controller Module (RCM) *** */ +#define RCM_RCR_SOFTRST (0x80) +#define RCM_RCR_FRCRSTOUT (0x40) + +#define RCM_RSR_SOFT (0x20) +#define RCM_RSR_WDOG (0x10) +#define RCM_RSR_POR (0x08) +#define RCM_RSR_EXT (0x04) +#define RCM_RSR_WDR_CORE (0x02) +#define RCM_RSR_LOL (0x01) + +/* *** Chip Configuration Module (CCM) *** */ +#define CCM_CCR_CSC (0x0200) +#define CCM_CCR_OSCFREQ (0x0080) +#define CCM_CCR_LIMP (0x0040) +#define CCM_CCR_LOAD (0x0020) +#define CCM_CCR_BOOTPS(x) (((x) & 0x0003) << 3) +#define CCM_CCR_OSC_MODE (0x0004) +#define CCM_CCR_PLL_MODE (0x0002) +#define CCM_CCR_RESERVED (0x0001) + +#define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6) +#define CCM_CIR_PRN(x) ((x) & 0x003F) + +/* *** General Purpose I/O (GPIO) *** */ +#define GPIO_PDR_BUSCTL(x) ((x) & 0x0F) +#define GPIO_PDR_BE(x) ((x) & 0x0F) +#define GPIO_PDR_CS(x) (((x) & 0x07) << 1) +#define GPIO_PDR_FECI2C(x) ((x) & 0x0F) +#define GPIO_PDR_QSPI(x) ((x) & 0x0F) +#define GPIO_PDR_TIMER(x) ((x) & 0x0F) +#define GPIO_PDR_UART(x) ((x) & 0xFF) +#define GPIO_PDR_FECH(x) ((x) & 0xFF) +#define GPIO_PDR_FECL(x) ((x) & 0xFF) + +#define GPIO_PAR_FBCTL_OE (0x10) +#define GPIO_PAR_FBCTL_TA (0x08) +#define GPIO_PAR_FBCTL_RWB (0x04) +#define GPIO_PAR_FBCTL_TS_MASK (0xFC) +#define GPIO_PAR_FBCTL_TS_TS (0x03) +#define GPIO_PAR_FBCTL_TS_DMA (0x02) + +#define GPIO_PAR_BE3 (0x08) +#define GPIO_PAR_BE2 (0x04) +#define GPIO_PAR_BE1 (0x02) +#define GPIO_PAR_BE0 (0x01) + +#define GPIO_PAR_CS3 (0x08) +#define GPIO_PAR_CS2 (0x04) +#define GPIO_PAR_CS1_MASK (0xFC) +#define GPIO_PAR_CS1_CS1 (0x03) +#define GPIO_PAR_CS1_SDCS1 (0x02) + +#define GPIO_PAR_FECI2C_RMII_MASK (0x0F) +#define GPIO_PAR_FECI2C_MDC_MASK (0x3F) +#define GPIO_PAR_FECI2C_MDC_MDC (0xC0) +#define GPIO_PAR_FECI2C_MDC_SCL (0x80) +#define GPIO_PAR_FECI2C_MDC_U2TXD (0x40) +#define GPIO_PAR_FECI2C_MDIO_MASK (0xCF) +#define GPIO_PAR_FECI2C_MDIO_MDIO (0x30) +#define GPIO_PAR_FECI2C_MDIO_SDA (0x20) +#define GPIO_PAR_FECI2C_MDIO_U2RXD (0x10) +#define GPIO_PAR_FECI2C_I2C_MASK (0xF0) +#define GPIO_PAR_FECI2C_SCL_MASK (0xF3) +#define GPIO_PAR_FECI2C_SCL_SCL (0x0C) +#define GPIO_PAR_FECI2C_SCL_U2RXD (0x04) +#define GPIO_PAR_FECI2C_SDA_MASK (0xFC) +#define GPIO_PAR_FECI2C_SDA_SDA (0x03) +#define GPIO_PAR_FECI2C_SDA_U2TXD (0x01) + +#define GPIO_PAR_QSPI_PCS2_MASK (0x3F) +#define GPIO_PAR_QSPI_PCS2_PCS2 (0xC0) +#define GPIO_PAR_QSPI_PCS2_DACK0 (0x80) +#define GPIO_PAR_QSPI_PCS2_U2RTS (0x40) +#define GPIO_PAR_QSPI_DIN_MASK (0xCF) +#define GPIO_PAR_QSPI_DIN_DIN (0x30) +#define GPIO_PAR_QSPI_DIN_DREQ0 (0x20) +#define GPIO_PAR_QSPI_DIN_U2CTS (0x10) +#define GPIO_PAR_QSPI_DOUT_MASK (0xF3) +#define GPIO_PAR_QSPI_DOUT_DOUT (0x0C) +#define GPIO_PAR_QSPI_DOUT_SDA (0x08) +#define GPIO_PAR_QSPI_SCK_MASK (0xFC) +#define GPIO_PAR_QSPI_SCK_SCK (0x03) +#define GPIO_PAR_QSPI_SCK_SCL (0x02) + +#define GPIO_PAR_TMR_TIN3(x) (((x) & 0x03) << 6) +#define GPIO_PAR_TMR_TIN2(x) (((x) & 0x03) << 4) +#define GPIO_PAR_TMR_TIN1(x) (((x) & 0x03) << 2) +#define GPIO_PAR_TMR_TIN0(x) ((x) & 0x03) +#define GPIO_PAR_TMR_TIN3_MASK (0x3F) +#define GPIO_PAR_TMR_TIN3_TIN3 (0xC0) +#define GPIO_PAR_TMR_TIN3_TOUT3 (0x80) +#define GPIO_PAR_TMR_TIN3_U2CTS (0x40) +#define GPIO_PAR_TMR_TIN2_MASK (0xCF) +#define GPIO_PAR_TMR_TIN2_TIN2 (0x30) +#define GPIO_PAR_TMR_TIN2_TOUT2 (0x20) +#define GPIO_PAR_TMR_TIN2_U2RTS (0x10) +#define GPIO_PAR_TMR_TIN1_MASK (0xF3) +#define GPIO_PAR_TMR_TIN1_TIN1 (0x0C) +#define GPIO_PAR_TMR_TIN1_TOUT1 (0x08) +#define GPIO_PAR_TMR_TIN1_U2RXD (0x04) +#define GPIO_PAR_TMR_TIN0_MASK (0xFC) +#define GPIO_PAR_TMR_TIN0_TIN0 (0x03) +#define GPIO_PAR_TMR_TIN0_TOUT0 (0x02) +#define GPIO_PAR_TMR_TIN0_U2TXD (0x01) + +#define GPIO_PAR_UART1_MASK (0xF03F) +#define GPIO_PAR_UART0_MASK (0xFFC0) +#define GPIO_PAR_UART_U1CTS_MASK (0xF3FF) +#define GPIO_PAR_UART_U1CTS_U1CTS (0x0C00) +#define GPIO_PAR_UART_U1CTS_TIN1 (0x0800) +#define GPIO_PAR_UART_U1CTS_PCS1 (0x0400) +#define GPIO_PAR_UART_U1RTS_MASK (0xFCFF) +#define GPIO_PAR_UART_U1RTS_U1RTS (0x0300) +#define GPIO_PAR_UART_U1RTS_TOUT1 (0x0200) +#define GPIO_PAR_UART_U1RTS_PCS1 (0x0100) +#define GPIO_PAR_UART_U1TXD (0x0080) +#define GPIO_PAR_UART_U1RXD (0x0040) +#define GPIO_PAR_UART_U0CTS_MASK (0xFFCF) +#define GPIO_PAR_UART_U0CTS_U0CTS (0x0030) +#define GPIO_PAR_UART_U0CTS_TIN0 (0x0020) +#define GPIO_PAR_UART_U0CTS_PCS0 (0x0010) +#define GPIO_PAR_UART_U0RTS_MASK (0xFFF3) +#define GPIO_PAR_UART_U0RTS_U0RTS (0x000C) +#define GPIO_PAR_UART_U0RTS_TOUT0 (0x0008) +#define GPIO_PAR_UART_U0RTS_PCS0 (0x0004) +#define GPIO_PAR_UART_U0TXD (0x0002) +#define GPIO_PAR_UART_U0RXD (0x0001) + +#define GPIO_PAR_FEC_7W_MASK (0xF3) +#define GPIO_PAR_FEC_7W_FEC (0x0C) +#define GPIO_PAR_FEC_7W_U1RTS (0x04) +#define GPIO_PAR_FEC_MII_MASK (0xFC) +#define GPIO_PAR_FEC_MII_FEC (0x03) +#define GPIO_PAR_FEC_MII_UnCTS (0x01) + +#define GPIO_PAR_IRQ_IRQ4 (0x01) + +#define GPIO_MSCR_FB_FBCLK(x) (((x) & 0x03) << 6) +#define GPIO_MSCR_FB_DUP(x) (((x) & 0x03) << 4) +#define GPIO_MSCR_FB_DLO(x) (((x) & 0x03) << 2) +#define GPIO_MSCR_FB_ADRCTL(x) ((x) & 0x03) +#define GPIO_MSCR_FB_FBCLK_MASK (0x3F) +#define GPIO_MSCR_FB_DUP_MASK (0xCF) +#define GPIO_MSCR_FB_DLO_MASK (0xF3) +#define GPIO_MSCR_FB_ADRCTL_MASK (0xFC) + +#define GPIO_MSCR_SDR_SDCLKB(x) (((x) & 0x03) << 4) +#define GPIO_MSCR_SDR_SDCLK(x) (((x) & 0x03) << 2) +#define GPIO_MSCR_SDR_SDRAM(x) ((x) & 0x03) +#define GPIO_MSCR_SDR_SDCLKB_MASK (0xCF) +#define GPIO_MSCR_SDR_SDCLK_MASK (0xF3) +#define GPIO_MSCR_SDR_SDRAM_MASK (0xFC) + +#define MSCR_25VDDR (0x03) +#define MSCR_18VDDR_FULL (0x02) +#define MSCR_OPENDRAIN (0x01) +#define MSCR_18VDDR_HALF (0x00) + +#define GPIO_DSCR_I2C(x) ((x) & 0x03) +#define GPIO_DSCR_I2C_MASK (0xFC) + +#define GPIO_DSCR_MISC_DBG(x) (((x) & 0x03) << 4) +#define GPIO_DSCR_MISC_DBG_MASK (0xCF) +#define GPIO_DSCR_MISC_RSTOUT(x) (((x) & 0x03) << 2) +#define GPIO_DSCR_MISC_RSTOUT_MASK (0xF3) +#define GPIO_DSCR_MISC_TIMER(x) ((x) & 0x03) +#define GPIO_DSCR_MISC_TIMER_MASK (0xFC) + +#define GPIO_DSCR_FEC(x) ((x) & 0x03) +#define GPIO_DSCR_FEC_MASK (0xFC) + +#define GPIO_DSCR_UART_UART1(x) (((x) & 0x03) << 4) +#define GPIO_DSCR_UART_UART1_MASK (0xCF) +#define GPIO_DSCR_UART_UART0(x) (((x) & 0x03) << 2) +#define GPIO_DSCR_UART_UART0_MASK (0xF3) +#define GPIO_DSCR_UART_IRQ(x) ((x) & 0x03) +#define GPIO_DSCR_UART_IRQ_MASK (0xFC) + +#define GPIO_DSCR_QSPI(x) ((x) & 0x03) +#define GPIO_DSCR_QSPI_MASK (0xFC) + +#define DSCR_50PF (0x03) +#define DSCR_30PF (0x02) +#define DSCR_20PF (0x01) +#define DSCR_10PF (0x00) + +/* *** Phase Locked Loop (PLL) *** */ +#define PLL_PODR_CPUDIV(x) (((x) & 0x0F) << 4) +#define PLL_PODR_CPUDIV_MASK (0x0F) +#define PLL_PODR_BUSDIV(x) ((x) & 0x0F) +#define PLL_PODR_BUSDIV_MASK (0xF0) + +#define PLL_PCR_DITHEN (0x80) +#define PLL_PCR_DITHDEV(x) ((x) & 0x07) +#define PLL_PCR_DITHDEV_MASK (0xF8) + +#endif /* __M520X__ */ diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h new file mode 100644 index 0000000..32123d2 --- /dev/null +++ b/include/configs/M5208EVBE.h @@ -0,0 +1,223 @@ +/* + * Configuation settings for the Freescale MCF5208EVBe. + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _M5208EVBE_H +#define _M5208EVBE_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF520x /* define processor family */ +#define CONFIG_M5208 /* define processor type */ + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 5000 + +/* Command line configuration */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#undef CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CONFIG_MII_INIT 1 +# define CONFIG_SYS_DISCOVER_PHY +# define CONFIG_SYS_RX_ETH_BUFFER 8 +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_HAS_ETH1 + +# define CONFIG_SYS_FEC0_PINMUX 0 +# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CONFIG_SYS_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SPEED 80000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#define CONFIG_UDP_CHECKSUM + +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* CONFIG_MCFFEC */ + +#define CONFIG_HOSTNAME M5208EVBe +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 3ffff;" \ + "era 0 3ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ +#define CONFIG_SYS_PROMPT "-> " +#define CONFIG_SYS_LONGHELP /* undef to save memory */ + +#ifdef CONFIG_CMD_KGDB +# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ +#define CONFIG_SYS_LOAD_ADDR 0x40010000 + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ +#define CONFIG_SYS_PLL_ODR 0x36 +#define CONFIG_SYS_PLL_FDR 0x7D + +#define CONFIG_SYS_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/* Definitions for initial stack pointer and data area (in DPRAM) */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ +#define CONFIG_SYS_SDRAM_CFG1 0x43711630 +#define CONFIG_SYS_SDRAM_CFG2 0x56670000 +#define CONFIG_SYS_SDRAM_CTRL 0xE1002000 +#define CONFIG_SYS_SDRAM_EMOD 0x80010000 +#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 +#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) + +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) + +/* FLASH organization */ +#define CONFIG_SYS_FLASH_CFI +#ifdef CONFIG_SYS_FLASH_CFI +# define CONFIG_FLASH_CFI_DRIVER 1 +# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */ +# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +#endif + +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE + +/* + * Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#define CONFIG_ENV_OFFSET 0x2000 +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_SECT_SIZE 0x2000 +#define CONFIG_ENV_IS_IN_FLASH 1 + +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +/* Chipselect bank definitions */ +/* + * CS0 - NOR Flash + * CS1 - Available + * CS2 - Available + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ +#define CONFIG_SYS_CS0_BASE 0 +#define CONFIG_SYS_CS0_MASK 0x007F0001 +#define CONFIG_SYS_CS0_CTRL 0x00001FA0 + +#endif /* _M5208EVBE_H */ diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index 053a914..e7db0cc 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -154,26 +154,22 @@ #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR /* DSPI and Serial Flash */ +#define CONFIG_CF_SPI #define CONFIG_CF_DSPI #define CONFIG_HARD_SPI -#define CONFIG_SYS_SER_FLASH_BASE 0x01000000 #define CONFIG_SYS_SBFHDR_SIZE 0x7 #ifdef CONFIG_CMD_SPI # define CONFIG_SYS_DSPI_CS2 # define CONFIG_SPI_FLASH # define CONFIG_SPI_FLASH_STMICRO -# define CONFIG_SYS_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ - DSPI_DCTAR_CPOL | \ - DSPI_DCTAR_CPHA | \ - DSPI_DCTAR_PCSSCK_1CLK | \ - DSPI_DCTAR_PASC(0) | \ - DSPI_DCTAR_PDT(0) | \ - DSPI_DCTAR_CSSCK(0) | \ - DSPI_DCTAR_ASC(0) | \ - DSPI_DCTAR_PBR(0) | \ - DSPI_DCTAR_DT(1) | \ - DSPI_DCTAR_BR(1)) +# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ + DSPI_CTAR_PCSSCK_1CLK | \ + DSPI_CTAR_PASC(0) | \ + DSPI_CTAR_PDT(0) | \ + DSPI_CTAR_CSSCK(0) | \ + DSPI_CTAR_ASC(0) | \ + DSPI_CTAR_DT(1)) #endif /* Input, PCI, Flexbus, and VCO */ @@ -265,9 +261,7 @@ * FLASH organization */ #ifdef CONFIG_SYS_STMICRO_BOOT -# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SER_FLASH_BASE -# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_SER_FLASH_BASE -# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS0_BASE +# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE # define CONFIG_ENV_OFFSET 0x30000 # define CONFIG_ENV_SIZE 0x1000 # define CONFIG_ENV_SECT_SIZE 0x10000 @@ -283,6 +277,8 @@ #define CONFIG_SYS_FLASH_CFI #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_FLASH_CFI_DRIVER 1 +# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +# define CONFIG_FLASH_SPANSION_S29WS_N 1 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 07c85c4..30855bd 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -77,6 +77,9 @@ # define CONFIG_SYS_FEC1_PINMUX 0 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE # define MCFFEC_TOUT_LOOP 50000 + +# define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2" + /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ # ifndef CONFIG_SYS_DISCOVER_PHY # define FECDUPLEX FULL @@ -204,7 +207,9 @@ #define CONFIG_SYS_FLASH_CFI #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_FLASH_CFI_DRIVER 1 -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +# define CONFIG_FLASH_SPANSION_S29WS_N 1 +# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index 45f7016..fa444c3 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -70,6 +70,7 @@ #define CONFIG_CMD_MISC #define CONFIG_CMD_MII #define CONFIG_CMD_NET +#define CONFIG_CMD_NFS #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SPI @@ -93,7 +94,7 @@ # define MCFFEC_TOUT_LOOP 50000 # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ -# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" +# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)" # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 # define CONFIG_ETHPRIME "FEC0" # define CONFIG_IPADDR 192.162.1.2 @@ -163,35 +164,33 @@ #define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_OFFSET 0x58000 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR /* DSPI and Serial Flash */ +#define CONFIG_CF_SPI #define CONFIG_CF_DSPI #define CONFIG_SERIAL_FLASH #define CONFIG_HARD_SPI -#define CONFIG_SYS_SER_FLASH_BASE 0x01000000 #define CONFIG_SYS_SBFHDR_SIZE 0x7 #ifdef CONFIG_CMD_SPI # define CONFIG_SPI_FLASH # define CONFIG_SPI_FLASH_STMICRO -# define CONFIG_SYS_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ - DSPI_DCTAR_CPOL | \ - DSPI_DCTAR_CPHA | \ - DSPI_DCTAR_PCSSCK_1CLK | \ - DSPI_DCTAR_PASC(0) | \ - DSPI_DCTAR_PDT(0) | \ - DSPI_DCTAR_CSSCK(0) | \ - DSPI_DCTAR_ASC(0) | \ - DSPI_DCTAR_PBR(0) | \ - DSPI_DCTAR_DT(1) | \ - DSPI_DCTAR_BR(1)) +# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ + DSPI_CTAR_PCSSCK_1CLK | \ + DSPI_CTAR_PASC(0) | \ + DSPI_CTAR_PDT(0) | \ + DSPI_CTAR_CSSCK(0) | \ + DSPI_CTAR_ASC(0) | \ + DSPI_CTAR_DT(1)) +# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) +# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) #endif /* Input, PCI, Flexbus, and VCO */ #define CONFIG_EXTRA_CLOCK -#define CONFIG_PRAM 2048 /* 2048 KB */ +#define CONFIG_PRAM 2048 /* 2048 KB */ #define CONFIG_SYS_PROMPT "-> " #define CONFIG_SYS_LONGHELP /* undef to save memory */ @@ -209,7 +208,7 @@ #define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_MBAR 0xFC000000 +#define CONFIG_SYS_MBAR 0xFC000000 /* * Low Level Configuration Settings @@ -265,7 +264,7 @@ /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash */ -#if defined(CONFIG_CF_SBF) +#if defined(CONFIG_SYS_STMICRO_BOOT) # define CONFIG_ENV_IS_IN_SPI_FLASH 1 # define CONFIG_ENV_SPI_CS 1 # define CONFIG_ENV_OFFSET 0x20000 @@ -273,30 +272,21 @@ # define CONFIG_ENV_SECT_SIZE 0x10000 #else # define CONFIG_ENV_IS_IN_FLASH 1 -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) -# define CONFIG_ENV_SECT_SIZE 0x2000 +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000) +# define CONFIG_ENV_SIZE 0x2000 +# define CONFIG_ENV_SECT_SIZE 0x8000 #endif #undef CONFIG_ENV_OVERWRITE #undef CONFIG_ENV_IS_EMBEDDED -/*----------------------------------------------------------------------- - * FLASH organization - */ -#ifdef CONFIG_SYS_STMICRO_BOOT -# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SER_FLASH_BASE -# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_SER_FLASH_BASE -# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS0_BASE -#endif -#ifdef CONFIG_SYS_SPANSION_BOOT -# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_SER_FLASH_BASE -#endif +/* FLASH organization */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE #define CONFIG_SYS_FLASH_CFI #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_FLASH_CFI_DRIVER 1 +# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ @@ -311,27 +301,20 @@ * This is setting for JFFS2 support in u-boot. * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. */ -#ifdef CONFIG_SYS_SPANSION_BOOT -# define CONFIG_JFFS2_DEV "nor0" -# define CONFIG_JFFS2_PART_SIZE 0x01000000 -# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) -#endif -#ifdef CONFIG_SYS_STMICRO_BOOT +#ifdef CONFIG_CMD_JFFS2 # define CONFIG_JFFS2_DEV "nor0" # define CONFIG_JFFS2_PART_SIZE 0x01000000 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) #endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ +/* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 /*----------------------------------------------------------------------- * Memory bank definitions */ /* - * CS0 - NOR Flash 8MB + * CS0 - NOR Flash 16MB * CS1 - Available * CS2 - Available * CS3 - Available @@ -339,10 +322,10 @@ * CS5 - Available */ - /* SPANSION Flash */ + /* Flash */ #define CONFIG_SYS_CS0_BASE 0x00000000 -#define CONFIG_SYS_CS0_MASK 0x007F0001 -#define CONFIG_SYS_CS0_CTRL 0x00001180 +#define CONFIG_SYS_CS0_MASK 0x00FF0001 +#define CONFIG_SYS_CS0_CTRL 0x00004D80 #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 87f3a73..14d98d6 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -200,25 +200,21 @@ #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR /* DSPI and Serial Flash */ +#define CONFIG_CF_SPI #define CONFIG_CF_DSPI #define CONFIG_HARD_SPI -#define CONFIG_SYS_SER_FLASH_BASE 0x01000000 #define CONFIG_SYS_SBFHDR_SIZE 0x13 #ifdef CONFIG_CMD_SPI # define CONFIG_SPI_FLASH # define CONFIG_SPI_FLASH_STMICRO -# define CONFIG_SYS_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ - DSPI_DCTAR_CPOL | \ - DSPI_DCTAR_CPHA | \ - DSPI_DCTAR_PCSSCK_1CLK | \ - DSPI_DCTAR_PASC(0) | \ - DSPI_DCTAR_PDT(0) | \ - DSPI_DCTAR_CSSCK(0) | \ - DSPI_DCTAR_ASC(0) | \ - DSPI_DCTAR_PBR(0) | \ - DSPI_DCTAR_DT(1) | \ - DSPI_DCTAR_BR(1)) +# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ + DSPI_CTAR_PCSSCK_1CLK | \ + DSPI_CTAR_PASC(0) | \ + DSPI_CTAR_PDT(0) | \ + DSPI_CTAR_CSSCK(0) | \ + DSPI_CTAR_ASC(0) | \ + DSPI_CTAR_DT(1)) #endif /* PCI */ @@ -342,10 +338,8 @@ * FLASH organization */ #ifdef CONFIG_SYS_STMICRO_BOOT -# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SER_FLASH_BASE -# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_SER_FLASH_BASE -# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH2_BASE CONFIG_SYS_CS1_BASE +# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE # define CONFIG_ENV_OFFSET 0x30000 # define CONFIG_ENV_SIZE 0x2000 # define CONFIG_ENV_SECT_SIZE 0x10000 @@ -370,6 +364,7 @@ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_FLASH_CFI_DRIVER 1 +# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ diff --git a/lib_m68k/board.c b/lib_m68k/board.c index f73a46c..483c9b6 100644 --- a/lib_m68k/board.c +++ b/lib_m68k/board.c @@ -535,7 +535,7 @@ void board_init_r (gd_t *id, ulong dest_addr) */ s = getenv ("flashchecksum"); if (s && (*s == 'y')) { - printf (" CRC: %08lX", + printf (" CRC: %08X", crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size) |