diff options
| -rw-r--r-- | arch/powerpc/cpu/mpc8xx/cpu_init.c | 1 | ||||
| -rw-r--r-- | board/spc1920/Makefile | 8 | ||||
| -rw-r--r-- | board/spc1920/hpi.c | 596 | ||||
| -rw-r--r-- | board/spc1920/hpi.h | 12 | ||||
| -rw-r--r-- | board/spc1920/pld.h | 14 | ||||
| -rw-r--r-- | board/spc1920/spc1920.c | 248 | ||||
| -rw-r--r-- | board/spc1920/u-boot.lds | 82 | ||||
| -rw-r--r-- | boards.cfg | 1 | ||||
| -rw-r--r-- | doc/README.scrapyard | 1 | ||||
| -rw-r--r-- | include/configs/spc1920.h | 405 |
10 files changed, 1 insertions, 1367 deletions
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index b4001de..e51fec7 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -138,7 +138,6 @@ void cpu_init_f (volatile immap_t * immr) defined(CONFIG_MHPC) || \ defined(CONFIG_R360MPI) || \ defined(CONFIG_RMU) || \ - defined(CONFIG_SPC1920) || \ defined(CONFIG_SPD823TS) memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM; diff --git a/board/spc1920/Makefile b/board/spc1920/Makefile deleted file mode 100644 index c0c9a32..0000000 --- a/board/spc1920/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = spc1920.o hpi.o diff --git a/board/spc1920/hpi.c b/board/spc1920/hpi.c deleted file mode 100644 index c593837..0000000 --- a/board/spc1920/hpi.c +++ /dev/null @@ -1,596 +0,0 @@ -/* - * (C) Copyright 2006 - * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Host Port Interface (HPI) - */ - -/* debug levels: - * 0 : errors - * 1 : usefull info - * 2 : lots of info - * 3 : noisy - */ - -#define DEBUG 0 - -#include <config.h> -#include <common.h> -#include <mpc8xx.h> - -#include "pld.h" -#include "hpi.h" - -#define _NOT_USED_ 0xFFFFFFFF - -/* original table: - * - inserted loops to achieve long CS low and high Periods (~217ns) - * - move cs high 2/4 to the right - */ -const uint dsp_table_slow[] = -{ - /* single read (offset 0x00 in upm ram) */ - 0x8fffdc04, 0x0fffdc84, 0x0fffdc84, 0x0fffdc00, - 0x3fffdc04, 0xffffdc84, 0xffffdc84, 0xffffdc05, - - /* burst read (offset 0x08 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* single write (offset 0x18 in upm ram) */ - 0x8fffd004, 0x0fffd084, 0x0fffd084, 0x3fffd000, - 0xffffd084, 0xffffd084, 0xffffd005, _NOT_USED_, - - /* burst write (offset 0x20 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* refresh (offset 0x30 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* exception (offset 0x3C in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* dsp hpi upm ram table - * works fine for noninc access, failes on incremental. - * - removed first word - */ -const uint dsp_table_fast[] = -{ - /* single read (offset 0x00 in upm ram) */ - 0x8fffdc04, 0x0fffdc04, 0x0fffdc00, 0x3fffdc04, - 0xffffdc05, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* burst read (offset 0x08 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* single write (offset 0x18 in upm ram) */ - 0x8fffd004, 0x0fffd004, 0x3fffd000, 0xffffd005, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* burst write (offset 0x20 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* refresh (offset 0x30 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* exception (offset 0x3C in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - - -#ifdef CONFIG_SPC1920_HPI_TEST -#undef HPI_TEST_OSZI - -#define HPI_TEST_CHUNKSIZE 0x1000 -#define HPI_TEST_PATTERN 0x00000000 -#define HPI_TEST_START 0x0 -#define HPI_TEST_END 0x30000 - -#define TINY_AUTOINC_DATA_SIZE 16 /* 32bit words */ -#define TINY_AUTOINC_BASE_ADDR 0x0 - -static int hpi_activate(void); -#if 0 -static void hpi_inactivate(void); -#endif -static void dsp_reset(void); - -static int hpi_write_inc(u32 addr, u32 *data, u32 count); -static int hpi_read_inc(u32 addr, u32 *buf, u32 count); -static int hpi_write_noinc(u32 addr, u32 data); -static u32 hpi_read_noinc(u32 addr); - -int hpi_test(void); -static int hpi_write_addr_test(u32 addr); -static int hpi_read_write_test(u32 addr, u32 data); -#ifdef DO_TINY_TEST -static int hpi_tiny_autoinc_test(void); -#endif /* DO_TINY_TEST */ -#endif /* CONFIG_SPC1920_HPI_TEST */ - - -/* init the host port interface on UPMA */ -int hpi_init(void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; - - upmconfig(UPMA, (uint *)dsp_table_slow, sizeof(dsp_table_slow)/sizeof(uint)); - udelay(100); - - memctl->memc_mamr = CONFIG_SYS_MAMR; - memctl->memc_or3 = CONFIG_SYS_OR3; - memctl->memc_br3 = CONFIG_SYS_BR3; - - /* reset dsp */ - dsp_reset(); - - /* activate hpi switch*/ - pld->dsp_hpi_on = 0x1; - - udelay(100); - - return 0; -} - -#ifdef CONFIG_SPC1920_HPI_TEST -/* activate the Host Port interface */ -static int hpi_activate(void) -{ - volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; - - /* turn on hpi */ - pld->dsp_hpi_on = 0x1; - - udelay(5); - - /* turn on the power EN_DSP_POWER high*/ - /* currently always on TBD */ - - /* setup hpi control register */ - HPI_HPIC_1 = (u16) 0x0008; - HPI_HPIC_2 = (u16) 0x0008; - - udelay(100); - - return 0; -} - -#if 0 -/* turn off the host port interface */ -static void hpi_inactivate(void) -{ - volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; - - /* deactivate hpi */ - pld->dsp_hpi_on = 0x0; - - /* reset the dsp */ - /* pld->dsp_reset = 0x0; */ - - /* turn off the power EN_DSP_POWER# high*/ - /* currently always on TBD */ - -} -#endif - -/* reset the DSP */ -static void dsp_reset(void) -{ - volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; - pld->dsp_reset = 0x1; - pld->dsp_hpi_on = 0x0; - - udelay(300000); - - pld->dsp_reset = 0x0; - pld->dsp_hpi_on = 0x1; -} - - -/* write using autoinc (count is number of 32bit words) */ -static int hpi_write_inc(u32 addr, u32 *data, u32 count) -{ - int i; - u16 addr1, addr2; - - addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */ - addr2 = (u16) (addr & 0xffff); - - /* write address */ - HPI_HPIA_1 = addr1; - HPI_HPIA_2 = addr2; - - debug("writing from data=0x%lx to 0x%lx\n", - (ulong)data, (ulong)(data+count)); - - for(i=0; i<count; i++) { - HPI_HPID_INC_1 = (u16) ((data[i] >> 16) & 0xffff); - HPI_HPID_INC_2 = (u16) (data[i] & 0xffff); - debug("hpi_write_inc: data1=0x%x, data2=0x%x\n", - (u16) ((data[i] >> 16) & 0xffff), - (u16) (data[i] & 0xffff)); - } -#if 0 - while(data_ptr < (u16*) (data + count)) { - HPI_HPID_INC_1 = *(data_ptr++); - HPI_HPID_INC_2 = *(data_ptr++); - } -#endif - - /* return number of bytes written */ - return count; -} - -/* - * read using autoinc (count is number of 32bit words) - */ -static int hpi_read_inc(u32 addr, u32 *buf, u32 count) -{ - int i; - u16 addr1, addr2, data1, data2; - - addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */ - addr2 = (u16) (addr & 0xffff); - - /* write address */ - HPI_HPIA_1 = addr1; - HPI_HPIA_2 = addr2; - - for(i=0; i<count; i++) { - data1 = HPI_HPID_INC_1; - data2 = HPI_HPID_INC_2; - debug("hpi_read_inc: data1=0x%x, data2=0x%x\n", data1, data2); - buf[i] = (((u32) data1) << 16) | (data2 & 0xffff); - } - -#if 0 - while(buf_ptr < (u16*) (buf + count)) { - *(buf_ptr++) = HPI_HPID_INC_1; - *(buf_ptr++) = HPI_HPID_INC_2; - } -#endif - - /* return number of bytes read */ - return count; -} - - -/* write to non- auto inc regs */ -static int hpi_write_noinc(u32 addr, u32 data) -{ - - u16 addr1, addr2, data1, data2; - - addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */ - addr2 = (u16) (addr & 0xffff); - - /* printf("hpi_write_noinc: addr1=0x%x, addr2=0x%x\n", addr1, addr2); */ - - HPI_HPIA_1 = addr1; - HPI_HPIA_2 = addr2; - - data1 = (u16) ((data >> 16) & 0xffff); - data2 = (u16) (data & 0xffff); - - /* printf("hpi_write_noinc: data1=0x%x, data2=0x%x\n", data1, data2); */ - - HPI_HPID_NOINC_1 = data1; - HPI_HPID_NOINC_2 = data2; - - return 0; -} - -/* read from non- auto inc regs */ -static u32 hpi_read_noinc(u32 addr) -{ - u16 addr1, addr2, data1, data2; - u32 ret; - - addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */ - addr2 = (u16) (addr & 0xffff); - - HPI_HPIA_1 = addr1; - HPI_HPIA_2 = addr2; - - /* printf("hpi_read_noinc: addr1=0x%x, addr2=0x%x\n", addr1, addr2); */ - - data1 = HPI_HPID_NOINC_1; - data2 = HPI_HPID_NOINC_2; - - /* printf("hpi_read_noinc: data1=0x%x, data2=0x%x\n", data1, data2); */ - - ret = (((u32) data1) << 16) | (data2 & 0xffff); - return ret; - -} - -/* - * Host Port Interface Tests - */ - -#ifndef HPI_TEST_OSZI -/* main test function */ -int hpi_test(void) -{ - int err = 0; - u32 i, ii, pattern, tmp; - - pattern = HPI_TEST_PATTERN; - - u32 test_data[HPI_TEST_CHUNKSIZE]; - u32 read_data[HPI_TEST_CHUNKSIZE]; - - debug("hpi_test: activating hpi..."); - hpi_activate(); - debug("OK.\n"); - -#if 0 - /* Dump the first 1024 bytes - * - */ - for(i=0; i<1024; i+=4) { - if(i%16==0) - printf("\n0x%08x: ", i); - printf("0x%08x ", hpi_read_noinc(i)); - } -#endif - - /* HPIA read-write test - * - */ - debug("hpi_test: starting HPIA read-write tests...\n"); - err |= hpi_write_addr_test(0xdeadc0de); - err |= hpi_write_addr_test(0xbeefd00d); - err |= hpi_write_addr_test(0xabcd1234); - err |= hpi_write_addr_test(0xaaaaaaaa); - if(err) { - debug("hpi_test: HPIA read-write tests: *** FAILED ***\n"); - return -1; - } - debug("hpi_test: HPIA read-write tests: OK\n"); - - - /* read write test using nonincremental data regs - * - */ - debug("hpi_test: starting nonincremental tests...\n"); - for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) { - err |= hpi_read_write_test(i, pattern); - - /* stolen from cmd_mem.c */ - if(pattern & 0x80000000) { - pattern = -pattern; /* complement & increment */ - } else { - pattern = ~pattern; - } - err |= hpi_read_write_test(i, pattern); - - if(err) { - debug("hpi_test: nonincremental tests *** FAILED ***\n"); - return -1; - } - } - debug("hpi_test: nonincremental test OK\n"); - - /* read write a chunk of data using nonincremental data regs - * - */ - debug("hpi_test: starting nonincremental chunk tests...\n"); - pattern = HPI_TEST_PATTERN; - for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) { - hpi_write_noinc(i, pattern); - - /* stolen from cmd_mem.c */ - if(pattern & 0x80000000) { - pattern = -pattern; /* complement & increment */ - } else { - pattern = ~pattern; - } - } - pattern = HPI_TEST_PATTERN; - for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) { - tmp = hpi_read_noinc(i); - - if(tmp != pattern) { - debug("hpi_test: noninc chunk test *** FAILED *** @ 0x%x, written=0x%x, read=0x%x\n", i, pattern, tmp); - err = -1; - } - /* stolen from cmd_mem.c */ - if(pattern & 0x80000000) { - pattern = -pattern; /* complement & increment */ - } else { - pattern = ~pattern; - } - } - if(err) - return -1; - debug("hpi_test: nonincremental chunk test OK\n"); - - -#ifdef DO_TINY_TEST - /* small verbose test using autoinc and nonautoinc to compare - * - */ - debug("hpi_test: tiny_autoinc_test...\n"); - hpi_tiny_autoinc_test(); - debug("hpi_test: tiny_autoinc_test done\n"); -#endif /* DO_TINY_TEST */ - - - /* $%& write a chunk of data using the autoincremental regs - * - */ - debug("hpi_test: starting autoinc test %d chunks with 0x%x bytes...\n", - ((HPI_TEST_END - HPI_TEST_START) / HPI_TEST_CHUNKSIZE), - HPI_TEST_CHUNKSIZE); - - for(i=HPI_TEST_START; - i < ((HPI_TEST_END - HPI_TEST_START) / HPI_TEST_CHUNKSIZE); - i++) { - /* generate the pattern data */ - debug("generating pattern data: "); - for(ii = 0; ii < HPI_TEST_CHUNKSIZE; ii++) { - debug("0x%x ", pattern); - - test_data[ii] = pattern; - read_data[ii] = 0x0; /* zero to be sure */ - - /* stolen from cmd_mem.c */ - if(pattern & 0x80000000) { - pattern = -pattern; /* complement & increment */ - } else { - pattern = ~pattern; - } - } - debug("done\n"); - - debug("Writing autoinc data @ 0x%x\n", i); - hpi_write_inc(i, test_data, HPI_TEST_CHUNKSIZE); - - debug("Reading autoinc data @ 0x%x\n", i); - hpi_read_inc(i, read_data, HPI_TEST_CHUNKSIZE); - - /* compare */ - for(ii = 0; ii < HPI_TEST_CHUNKSIZE; ii++) { - debug("hpi_test_autoinc: @ 0x%x, written=0x%x, read=0x%x", i+ii, test_data[ii], read_data[ii]); - if(read_data[ii] != test_data[ii]) { - debug("hpi_test: autoinc test @ 0x%x, written=0x%x, read=0x%x *** FAILED ***\n", i+ii, test_data[ii], read_data[ii]); - return -1; - } - } - } - debug("hpi_test: autoinc test OK\n"); - - return 0; -} -#else /* HPI_TEST_OSZI */ -int hpi_test(void) -{ - int i; - u32 read_data[TINY_AUTOINC_DATA_SIZE]; - - unsigned int dummy_data[TINY_AUTOINC_DATA_SIZE] = { - 0x11112222, 0x33334444, 0x55556666, 0x77778888, - 0x9999aaaa, 0xbbbbcccc, 0xddddeeee, 0xffff1111, - 0x00010002, 0x00030004, 0x00050006, 0x00070008, - 0x0009000a, 0x000b000c, 0x000d000e, 0x000f0001 - }; - - debug("hpi_test: activating hpi..."); - hpi_activate(); - debug("OK.\n"); - - while(1) { - led9(1); - debug(" writing to autoinc...\n"); - hpi_write_inc(TINY_AUTOINC_BASE_ADDR, - dummy_data, TINY_AUTOINC_DATA_SIZE); - - debug(" reading from autoinc...\n"); - hpi_read_inc(TINY_AUTOINC_BASE_ADDR, - read_data, TINY_AUTOINC_DATA_SIZE); - - for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) { - debug(" written=0x%x, read(inc)=0x%x\n", - dummy_data[i], read_data[i]); - } - led9(0); - udelay(2000000); - } - return 0; -} -#endif - -/* test if Host Port Address Register can be written correctly */ -static int hpi_write_addr_test(u32 addr) -{ - u32 read_back; - /* write address */ - HPI_HPIA_1 = ((u16) (addr >> 16)); /* First HW is most significant */ - HPI_HPIA_2 = ((u16) addr); - - read_back = (((u32) HPI_HPIA_1)<<16) | ((u32) HPI_HPIA_2); - - if(read_back == addr) { - debug(" hpi_write_addr_test OK: written=0x%x, read=0x%x\n", - addr, read_back); - return 0; - } else { - debug(" hpi_write_addr_test *** FAILED ***: written=0x%x, read=0x%x\n", - addr, read_back); - return -1; - } - - return 0; -} - -/* test if a simple read/write sequence succeeds */ -static int hpi_read_write_test(u32 addr, u32 data) -{ - u32 read_back; - - hpi_write_noinc(addr, data); - read_back = hpi_read_noinc(addr); - - if(read_back == data) { - debug(" hpi_read_write_test: OK, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back); - return 0; - } else { - debug(" hpi_read_write_test: *** FAILED ***, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back); - return -1; - } - - return 0; -} - -#ifdef DO_TINY_TEST -static int hpi_tiny_autoinc_test(void) -{ - int i; - u32 read_data[TINY_AUTOINC_DATA_SIZE]; - u32 read_data_noinc[TINY_AUTOINC_DATA_SIZE]; - - unsigned int dummy_data[TINY_AUTOINC_DATA_SIZE] = { - 0x11112222, 0x33334444, 0x55556666, 0x77778888, - 0x9999aaaa, 0xbbbbcccc, 0xddddeeee, 0xffff1111, - 0x00010002, 0x00030004, 0x00050006, 0x00070008, - 0x0009000a, 0x000b000c, 0x000d000e, 0x000f0001 - }; - - printf(" writing to autoinc...\n"); - hpi_write_inc(TINY_AUTOINC_BASE_ADDR, dummy_data, TINY_AUTOINC_DATA_SIZE); - - printf(" reading from autoinc...\n"); - hpi_read_inc(TINY_AUTOINC_BASE_ADDR, read_data, TINY_AUTOINC_DATA_SIZE); - - printf(" reading from noinc for comparison...\n"); - for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) - read_data_noinc[i] = hpi_read_noinc(TINY_AUTOINC_BASE_ADDR+i*4); - - for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) { - printf(" written=0x%x, read(inc)=0x%x, read(noinc)=0x%x\n", - dummy_data[i], read_data[i], read_data_noinc[i]); - } - return 0; -} -#endif /* DO_TINY_TEST */ - -#endif /* CONFIG_SPC1920_HPI_TEST */ diff --git a/board/spc1920/hpi.h b/board/spc1920/hpi.h deleted file mode 100644 index db67672..0000000 --- a/board/spc1920/hpi.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2006 - * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -int hpi_init(void); - -#ifdef CONFIG_SPC1920_HPI_TEST -int hpi_test(void); -#endif diff --git a/board/spc1920/pld.h b/board/spc1920/pld.h deleted file mode 100644 index 5beb71b..0000000 --- a/board/spc1920/pld.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef __PLD_H__ -#define __PLD_H__ - -typedef struct spc1920_pld { - uchar com1_en; - uchar dsp_reset; - uchar dsp_hpi_on; - uchar superv_mode; - uchar codec_dsp_power_en; - uchar clk3_select; - uchar clk4_select; -} spc1920_pld_t; - -#endif /* __PLD_H__ */ diff --git a/board/spc1920/spc1920.c b/board/spc1920/spc1920.c deleted file mode 100644 index 1775433..0000000 --- a/board/spc1920/spc1920.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <mpc8xx.h> -#include "pld.h" -#include "hpi.h" - -#define _NOT_USED_ 0xFFFFFFFF - -static long int dram_size (long int, long int *, long int); - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMB RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMB RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMB RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMB RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMB RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMB RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMB RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - /* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; */ - - long int size_b0; - long int size8, size9; - int i; - - /* - * Configure UPMB for SDRAM - */ - upmconfig (UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - udelay(100); - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - /* burst length=4, burst type=sequential, CAS latency=2 */ - memctl->memc_mar = CONFIG_SYS_MAR; - - /* - * Map controller bank 1 to the SDRAM bank at preliminary address. - */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - /* initialize memory address register */ - memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */ - - /* mode initialization (offset 5) */ - udelay (200); /* 0x80006105 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x05); - - /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ - udelay (1); /* 0x80006130 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30); - udelay (1); /* 0x80006130 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30); - udelay (1); /* 0x80006106 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x06); - - memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */ - - udelay (200); - - /* Need at least 10 DRAM accesses to stabilize */ - for (i = 0; i < 10; ++i) { - volatile unsigned long *addr = - (volatile unsigned long *) CONFIG_SYS_SDRAM_BASE; - unsigned long val; - - val = *(addr + i); - *(addr + i) = val; - } - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MBMR_8COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MBMR_9COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; - memctl->memc_mbmr = CONFIG_SYS_MBMR_9COL | MBMR_PTBE; - udelay (500); - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE; - udelay (500); - } - - /* - * Final mapping: - */ - - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | - OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING; - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V; - udelay (1000); - - /* initalize the DSP Host Port Interface */ - hpi_init(); - - /* FRAM Setup */ - memctl->memc_or4 = CONFIG_SYS_OR4; - memctl->memc_br4 = CONFIG_SYS_BR4; - udelay(1000); - - return (size_b0); -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -static long int dram_size (long int mbmr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mbmr = mbmr_value; - - return (get_ram_size (base, maxsize)); -} - - -/************* other stuff ******************/ - - -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - /* Set Go/NoGo led (PA15) to color red */ - immap->im_ioport.iop_papar &= ~0x1; - immap->im_ioport.iop_paodr &= ~0x1; - immap->im_ioport.iop_padir |= 0x1; - immap->im_ioport.iop_padat |= 0x1; - -#if 0 - /* Turn on LED PD9 */ - immap->im_ioport.iop_pdpar &= ~(0x0040); - immap->im_ioport.iop_pddir |= 0x0040; - immap->im_ioport.iop_pddat |= 0x0040; -#endif - - /* - * Enable console on SMC1. This requires turning on - * the com2_en signal and SMC1_DISABLE - */ - - /* SMC1_DISABLE: PB17 */ - immap->im_cpm.cp_pbodr &= ~0x4000; - immap->im_cpm.cp_pbpar &= ~0x4000; - immap->im_cpm.cp_pbdir |= 0x4000; - immap->im_cpm.cp_pbdat &= ~0x4000; - - /* COM2_EN: PD10 */ - immap->im_ioport.iop_pdpar &= ~0x0020; - immap->im_ioport.iop_pddir &= ~0x4000; - immap->im_ioport.iop_pddir |= 0x0020; - immap->im_ioport.iop_pddat |= 0x0020; - - -#ifdef CONFIG_SYS_SMC1_PLD_CLK4 /* SMC1 uses CLK4 from PLD */ - immap->im_cpm.cp_simode |= 0x7000; - immap->im_cpm.cp_simode &= ~(0x8000); -#endif - - return 0; -} - -int last_stage_init(void) -{ -#ifdef CONFIG_SPC1920_HPI_TEST - printf("CMB1920 Host Port Interface Test: %s\n", - hpi_test() ? "Failed!" : "OK"); -#endif - return 0; -} - -int checkboard (void) -{ - puts("Board: SPC1920\n"); - return 0; -} diff --git a/board/spc1920/u-boot.lds b/board/spc1920/u-boot.lds deleted file mode 100644 index 0eb2fba..0000000 --- a/board/spc1920/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} @@ -978,7 +978,6 @@ Active powerpc mpc86xx - xes - Active powerpc mpc8xx - - - hermes - Wolfgang Denk <wd@denx.de> Active powerpc mpc8xx - - - lwmon - Wolfgang Denk <wd@denx.de> Active powerpc mpc8xx - - - RRvision - Wolfgang Denk <wd@denx.de> -Active powerpc mpc8xx - - - spc1920 - - Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen <Murray.Jensen@csiro.au> Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark <clark@esteem.com> Active powerpc mpc8xx - - icu862 ICU862 - Wolfgang Denk <wd@denx.de> diff --git a/doc/README.scrapyard b/doc/README.scrapyard index d8678af..6a1d2a5 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +spc1920 powerpc mpc8xx - - v37 powerpc mpc8xx - - fads powerpc mpc8xx - - netphone powerpc mpc8xx - - diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h deleted file mode 100644 index 127de00..0000000 --- a/include/configs/spc1920.h +++ /dev/null @@ -1,405 +0,0 @@ -/* - * (C) Copyright 2006 - * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de - * - * Configuation settings for the SPC1920 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __H -#define __CONFIG_H - -#define CONFIG_SPC1920 1 /* SPC1920 board */ -#define CONFIG_MPC885 1 /* MPC885 CPU */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_MII -#define CONFIG_MII_INIT 1 -#undef CONFIG_ETHER_ON_FEC1 -#define CONFIG_ETHER_ON_FEC2 -#define FEC_ENET -#define CONFIG_FEC2_PHY 1 - -#define CONFIG_BAUDRATE 19200 - -/* use PLD CLK4 instead of brg */ -#define CONFIG_SYS_SPC1920_SMC1_CLK4 - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 -#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000 -#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xC0000000 - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_LAST_STAGE_INIT - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_NFSBOOTCOMMAND \ - "dhcp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ - "bootm" - -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ - "bootm fe080000" - -#undef CONFIG_BOOTARGS - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -#define CONFIG_SYS_BAUDRATE_TABLE { 2400, 4800, 9600, 19200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */ - -#ifdef CONFIG_BZIP2 -#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ -#else -#define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -#define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */ - -/* - * Flash - */ -/*----------------------------------------------------------------------- - * Flash organisation - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max num of sects on one chip */ - -/* Environment is in flash */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -#define CONFIG_ENV_OVERWRITE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ - -#ifdef CONFIG_CMD_DATE -# define CONFIG_RTC_DS3231 -# define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#endif - -/*----------------------------------------------------------------------- - * I2C configuration - */ -#if defined(CONFIG_CMD_I2C) -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_FRC) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -/* #define CONFIG_SYS_SCCR SCCR_TBS */ -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * DER - Debug Enable Register - *----------------------------------------------------------------------- - * Set to zero to prevent the processor from entering debug mode - */ -#define CONFIG_SYS_DER 0 - - -/* Because of the way the 860 starts up and assigns CS0 the entire - * address space, we have to set the memory controller differently. - * Normally, you write the option register first, and then enable the - * chip select by writing the base register. For CS0, you must write - * the base register first, followed by the option register. - */ - - -/* - * Init Memory Controller: - */ - -/* BR0 and OR0 (FLASH) */ -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ - - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_6_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - - -/* - * SDRAM CS1 UPMB - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE_PRELIM CONFIG_SYS_SDRAM_BASE -#define SDRAM_MAX_SIZE 0x4000000 /* max 64 MB */ - -#define CONFIG_SYS_PRELIM_OR1_AM 0xF0000000 -/* #define CONFIG_SYS_OR1_TIMING OR_CSNT_SAM/\* | OR_G5LS /\\* *\\/ *\/ */ -#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ - -#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING) -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V) - -/* #define CONFIG_SYS_OR1_FINAL ((CONFIG_SYS_OR1_AM & OR_AM_MSK) | CONFIG_SYS_OR1_TIMING) */ -/* #define CONFIG_SYS_BR1_FINAL ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */ - -#define CONFIG_SYS_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64)) -#define CONFIG_SYS_PTA_PER_CLK 195 -#define CONFIG_SYS_MBMR_PTB 195 -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV16 -#define CONFIG_SYS_MAR 0x88 - -#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_0 | \ - MBMR_G0CLB_A10 | \ - MBMR_DSB_1_CYCL | \ - MBMR_RLFB_1X | \ - MBMR_WLFB_1X | \ - MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */ - -#define CONFIG_SYS_MBMR_9COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_1 | \ - MBMR_G0CLB_A10 | \ - MBMR_DSB_1_CYCL | \ - MBMR_RLFB_1X | \ - MBMR_WLFB_1X | \ - MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */ - - -/* - * DSP Host Port Interface CS3 - */ -#define CONFIG_SYS_SPC1920_HPI_BASE 0x90000000 -#define CONFIG_SYS_PRELIM_OR3_AM 0xF8000000 - -#define CONFIG_SYS_OR3 (CONFIG_SYS_PRELIM_OR3_AM | \ - OR_G5LS | \ - OR_SCY_0_CLK | \ - OR_BI) - -#define CONFIG_SYS_BR3 ((CONFIG_SYS_SPC1920_HPI_BASE & BR_BA_MSK) | \ - BR_MS_UPMA | \ - BR_PS_16 | \ - BR_V) - -#define CONFIG_SYS_MAMR (MAMR_GPL_A4DIS | \ - MAMR_RLFA_5X | \ - MAMR_WLFA_5X) - -#define CONFIG_SPC1920_HPI_TEST - -#ifdef CONFIG_SPC1920_HPI_TEST -#define HPI_REG(x) (*((volatile u16 *) (CONFIG_SYS_SPC1920_HPI_BASE + x))) -#define HPI_HPIC_1 HPI_REG(0) -#define HPI_HPIC_2 HPI_REG(2) -#define HPI_HPIA_1 HPI_REG(0x2000008) -#define HPI_HPIA_2 HPI_REG(0x2000008 + 2) -#define HPI_HPID_INC_1 HPI_REG(0x1000004) -#define HPI_HPID_INC_2 HPI_REG(0x1000004 + 2) -#define HPI_HPID_NOINC_1 HPI_REG(0x300000c) -#define HPI_HPID_NOINC_2 HPI_REG(0x300000c + 2) -#endif /* CONFIG_SPC1920_HPI_TEST */ - -/* - * Ramtron FM18L08 FRAM 32KB on CS4 - */ -#define CONFIG_SYS_SPC1920_FRAM_BASE 0x80100000 -#define CONFIG_SYS_PRELIM_OR4_AM 0xffff8000 -#define CONFIG_SYS_OR4 (CONFIG_SYS_PRELIM_OR4_AM | \ - OR_ACS_DIV2 | \ - OR_BI | \ - OR_SCY_4_CLK | \ - OR_TRLX) - -#define CONFIG_SYS_BR4 ((CONFIG_SYS_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) - -/* - * PLD CS5 - */ -#define CONFIG_SYS_SPC1920_PLD_BASE 0x80000000 -#define CONFIG_SYS_PRELIM_OR5_AM 0xffff8000 - -#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PRELIM_OR5_AM | \ - OR_CSNT_SAM | \ - OR_ACS_DIV1 | \ - OR_BI | \ - OR_SCY_0_CLK | \ - OR_TRLX) - -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) - -#endif /* __CONFIG_H */ |