diff options
36 files changed, 1190 insertions, 208 deletions
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/soc.c b/arch/arm/cpu/arm_cortexa8/mx51/soc.c index 2a139b2..f22ebe9 100644 --- a/arch/arm/cpu/arm_cortexa8/mx51/soc.c +++ b/arch/arm/cpu/arm_cortexa8/mx51/soc.c @@ -67,7 +67,7 @@ int print_cpuinfo(void) u32 cpurev; cpurev = get_cpu_rev(); - printf("CPU: Freescale i.MX51 family %d.%dV at %d MHz\n", + printf("CPU: Freescale i.MX51 family rev%d.%d at %d MHz\n", (cpurev & 0xF0) >> 4, (cpurev & 0x0F) >> 4, mxc_get_clock(MXC_ARM_CLK) / 1000000); diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index a7c8079..1b3d618 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -739,6 +739,7 @@ setup_bats: * Note: requires that all cache bits in * HID0 are in the low half word. */ +#ifndef CONFIG_NAND_SPL .globl icache_enable icache_enable: mfspr r3, HID0 @@ -767,6 +768,7 @@ icache_status: mfspr r3, HID0 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 blr +#endif /* !CONFIG_NAND_SPL */ .globl dcache_enable dcache_enable: diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index e578b29..99431dc 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2003 Motorola Inc. * Modified by Xianghua Xiao, X.Xiao@motorola.com @@ -30,9 +30,11 @@ #include <watchdog.h> #include <asm/processor.h> #include <ioports.h> +#include <sata.h> #include <asm/io.h> #include <asm/mmu.h> #include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> #include "mp.h" DECLARE_GLOBAL_DATA_PTR; @@ -418,3 +420,13 @@ void arch_preboot_os(void) setup_ivors(); } + +#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) +int sata_initialize(void) +{ + if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) + return __sata_initialize(); + + return 1; +} +#endif diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c index cb6a6f0..7e72f5f 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c @@ -1,17 +1,31 @@ /* - * Copyright (C) 2008 Freescale Semicondutor, Inc. + * Copyright 2008,2010 Freescale Semiconductor, Inc. * Dave Liu <daveliu@freescale.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #include <config.h> #include <common.h> #include <asm/io.h> #include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> /* PORDEVSR register */ #define GUTS_PORDEVSR_OFFS 0xc @@ -52,6 +66,61 @@ #define FSL_SRDSCR3_LANEE_SGMII 0x00000000 #define FSL_SRDSCR3_LANEE_SATA 0x00150005 + +#define SRDS1_MAX_LANES 8 +#define SRDS2_MAX_LANES 2 + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE}, + [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}, + [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, + [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3}, +}; + +static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x1] = {SATA1, SATA2}, + [0x3] = {SATA1, NONE}, + [0x4] = {SGMII_TSEC1, SGMII_TSEC3}, + [0x6] = {SGMII_TSEC1, NONE}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + int i; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + + u32 srds2_cfg = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> + GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT; + + debug("%s: dev = %d\n", __FUNCTION__, device); + debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg); + debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_cfg); + + if (srds1_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg); + return 0; + } + + if (srds2_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_cfg); + return 0; + } + + for (i = 0; i < SRDS1_MAX_LANES; i++) { + if (serdes1_cfg_tbl[srds1_cfg][i] == device) + return 1; + } + for (i = 0; i < SRDS2_MAX_LANES; i++) { + if (serdes2_cfg_tbl[srds2_cfg][i] == device) + return 1; + } + + return 0; +} + void fsl_serdes_init(void) { void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c index d9d0fa7..dcb37ce 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c @@ -175,8 +175,8 @@ determine_refresh_rate_ps(const unsigned int spd_refresh) * ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3 * Not certain if any good value exists for CL=2 */ - /* CL2 CL3 CL4 CL5 CL6 */ -unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500 }; + /* CL2 CL3 CL4 CL5 CL6 CL7*/ +unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500, 1875 }; unsigned int compute_derated_DDR2_CAS_latency(unsigned int mclk_ps) diff --git a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c index 85995ca..186936f 100644 --- a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c +++ b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c @@ -56,18 +56,6 @@ static struct pci_info pci_config_info[] = #elif defined(CONFIG_MPC8536) static struct pci_info pci_config_info[] = { - [LAW_TRGT_IF_PCI] = { - .cfg = 0, - }, - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 5) | (1 << 7), - }, - [LAW_TRGT_IF_PCIE_3] = { - .cfg = (1 << 7), - }, }; #elif defined(CONFIG_MPC8544) static struct pci_info pci_config_info[] = diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 6da4b6f..d4839f4 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -1,21 +1,48 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + #ifndef __FSL_SERDES_H #define __FSL_SERDES_H #include <config.h> -#define FSL_SERDES_CLK_100 (0 << 28) -#define FSL_SERDES_CLK_125 (1 << 28) -#define FSL_SERDES_CLK_150 (3 << 28) -#define FSL_SERDES_PROTO_SATA 0 -#define FSL_SERDES_PROTO_PEX 1 -#define FSL_SERDES_PROTO_PEX_X2 2 -#define FSL_SERDES_PROTO_SGMII 3 -#define FSL_SERDES_VDD_1V 1 +enum srds_prtcl { + NONE = 0, + PCIE1, + PCIE2, + PCIE3, + PCIE4, + SATA1, + SATA2, + SRIO1, + SRIO2, + SGMII_FM1, + SGMII_FM2, + SGMII_TSEC1, + SGMII_TSEC2, + SGMII_TSEC3, + SGMII_TSEC4, + XAUI_FM1, + XAUI_FM2, + AURORA, +}; -#ifdef CONFIG_FSL_SERDES -extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd); -#else -static void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) {} -#endif /* CONFIG_FSL_SERDES */ +int is_serdes_configured(enum srds_prtcl device); #endif /* __FSL_SERDES_H */ diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index eb9218e..781333b 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -26,6 +26,7 @@ #include <asm/arch/mx31.h> #include <asm/arch/mx31-regs.h> #include <nand.h> +#include <fsl_pmic.h> #include "qong_fpga.h" DECLARE_GLOBAL_DATA_PTR; @@ -128,6 +129,13 @@ int board_init (void) mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); + /* setup pins for SPI (pmic) */ + mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); + mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); + mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); + mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); + mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); + /* board id for linux */ gd->bd->bi_arch_number = MACH_TYPE_QONG; gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ @@ -135,6 +143,18 @@ int board_init (void) return 0; } +int board_late_init(void) +{ + u32 val; + + /* Enable RTC battery */ + val = pmic_reg_read(REG_POWER_CTL0); + pmic_reg_write(REG_POWER_CTL0, val | COINCHEN); + pmic_reg_write(REG_INT_STATUS1, RTCRSTI); + + return 0; +} + int checkboard (void) { printf("Board: DAVE/DENX Qong\n"); diff --git a/board/esd/plu405/config.mk b/board/esd/plu405/config.mk index 0fb4efa..0a4dbaa 100644 --- a/board/esd/plu405/config.mk +++ b/board/esd/plu405/config.mk @@ -25,4 +25,4 @@ # esd PLU405 boards # -TEXT_BASE = 0xFFFA0000 +TEXT_BASE = 0xFFF80000 diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c index cbee8fe..e740ad8 100644 --- a/board/freescale/common/fsl_diu_fb.c +++ b/board/freescale/common/fsl_diu_fb.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007, 2010 Freescale Semiconductor, Inc. * York Sun <yorksun@freescale.com> * * FSL DIU Framebuffer driver @@ -26,6 +26,7 @@ #include <common.h> #include <i2c.h> #include <malloc.h> +#include <asm/io.h> #include "fsl_diu_fb.h" @@ -267,9 +268,9 @@ int fsl_diu_init(int xres, memset(info->screen_base, 0, info->smem_len); - dr.diu_reg->desc[0] = (unsigned int) &dummy_ad; - dr.diu_reg->desc[1] = (unsigned int) &dummy_ad; - dr.diu_reg->desc[2] = (unsigned int) &dummy_ad; + out_be32(&dr.diu_reg->desc[0], (int)&dummy_ad); + out_be32(&dr.diu_reg->desc[1], (int)&dummy_ad); + out_be32(&dr.diu_reg->desc[2], (int)&dummy_ad); debug("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]); debug("dummy desc[0] = 0x%x\n", hw->desc[0]); @@ -331,26 +332,26 @@ int fsl_diu_init(int xres, /* Program DIU registers */ - hw->gamma = (unsigned int) gamma.paddr; - hw->cursor= (unsigned int) cursor.paddr; - hw->bgnd = 0x007F7F7F; /* BGND */ - hw->bgnd_wb = 0; /* BGND_WB */ - hw->disp_size = var->yres << 16 | var->xres; /* DISP SIZE */ - hw->wb_size = 0; /* WB SIZE */ - hw->wb_mem_addr = 0; /* WB MEM ADDR */ - hw->hsyn_para = var->left_margin << 22 | /* BP_H */ + out_be32(&hw->gamma, (int)gamma.paddr); + out_be32(&hw->cursor, (int)cursor.paddr); + out_be32(&hw->bgnd, 0x007F7F7F); + out_be32(&hw->bgnd_wb, 0); /* BGND_WB */ + out_be32(&hw->disp_size, var->yres << 16 | var->xres); /* DISP SIZE */ + out_be32(&hw->wb_size, 0); /* WB SIZE */ + out_be32(&hw->wb_mem_addr, 0); /* WB MEM ADDR */ + out_be32(&hw->hsyn_para, var->left_margin << 22 | /* BP_H */ var->hsync_len << 11 | /* PW_H */ - var->right_margin; /* FP_H */ - hw->vsyn_para = var->upper_margin << 22 | /* BP_V */ - var->vsync_len << 11 | /* PW_V */ - var->lower_margin; /* FP_V */ + var->right_margin); /* FP_H */ - hw->syn_pol = 0; /* SYNC SIGNALS POLARITY */ - hw->thresholds = 0x00037800; /* The Thresholds */ - hw->int_status = 0; /* INTERRUPT STATUS */ - hw->int_mask = 0; /* INT MASK */ - hw->plut = 0x01F5F666; + out_be32(&hw->vsyn_para, var->upper_margin << 22 | /* BP_V */ + var->vsync_len << 11 | /* PW_V */ + var->lower_margin); /* FP_V */ + out_be32(&hw->syn_pol, 0); /* SYNC SIGNALS POLARITY */ + out_be32(&hw->thresholds, 0x00037800); /* The Thresholds */ + out_be32(&hw->int_status, 0); /* INTERRUPT STATUS */ + out_be32(&hw->int_mask, 0); /* INT MASK */ + out_be32(&hw->plut, 0x01F5F666); /* Pixel Clock configuration */ debug("DIU pixclock in ps - %d\n", var->pixclock); diu_set_pixel_clock(var->pixclock); @@ -390,8 +391,8 @@ static int fsl_diu_enable_panel(struct fb_info *info) struct diu_ad *ad = &fsl_diu_fb_ad; debug("Entered: enable_panel\n"); - if (hw->desc[0] != (unsigned int)ad) - hw->desc[0] = (unsigned int)ad; + if (in_be32(&hw->desc[0]) != (unsigned)ad) + out_be32(&hw->desc[0], (unsigned)ad); debug("desc[0] = 0x%x\n", hw->desc[0]); return 0; } @@ -401,8 +402,8 @@ static int fsl_diu_disable_panel(struct fb_info *info) struct diu *hw = dr.diu_reg; debug("Entered: disable_panel\n"); - if (hw->desc[0] != (unsigned int)&dummy_ad) - hw->desc[0] = (unsigned int)&dummy_ad; + if (in_be32(&hw->desc[0]) != (unsigned)&dummy_ad) + out_be32(&hw->desc[0], (unsigned)&dummy_ad); return 0; } @@ -443,7 +444,7 @@ static void enable_lcdc(void) debug("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled); if (!fb_enabled) { - hw->diu_mode = dr.mode; + out_be32(&hw->diu_mode, dr.mode); fb_enabled++; } debug("diu_mode = %d\n", hw->diu_mode); @@ -455,7 +456,7 @@ static void disable_lcdc(void) debug("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled); if (fb_enabled) { - hw->diu_mode = 0; + out_be32(&hw->diu_mode, 0); fb_enabled = 0; } } diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c index 1f11563..61b7454 100644 --- a/board/freescale/mpc8536ds/law.c +++ b/board/freescale/mpc8536ds/law.c @@ -28,15 +28,7 @@ #include <asm/mmu.h> struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3), - SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 253ed18..1968106 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -30,6 +30,7 @@ #include <asm/fsl_pci.h> #include <asm/fsl_ddr_sdram.h> #include <asm/io.h> +#include <asm/fsl_serdes.h> #include <spd.h> #include <miiphy.h> #include <libfdt.h> @@ -219,9 +220,13 @@ void pci_init_board(void) puts("\n"); #ifdef CONFIG_PCIE3 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); + pcie_configured = is_serdes_configured(PCIE3); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ + set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, + LAW_TRGT_IF_PCIE_3); + set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCIE_3); SET_STD_PCIE_INFO(pci_info[num], 3); pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n", @@ -239,9 +244,13 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, + LAW_TRGT_IF_PCIE_1); + set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCIE_1); SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n", @@ -259,9 +268,13 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE2 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + pcie_configured = is_serdes_configured(PCIE2); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ + set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, + LAW_TRGT_IF_PCIE_2); + set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCIE_2); SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n", @@ -285,6 +298,10 @@ void pci_init_board(void) pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, + LAW_TRGT_IF_PCI); + set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCI); SET_STD_PCI_INFO(pci_info[num], 1); pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", @@ -481,17 +498,6 @@ get_board_ddr_clk(ulong dummy) } #endif -int sata_initialize(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint sdrs2_io_sel = - (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; - if (sdrs2_io_sel & 0x04) - return 1; - - return __sata_initialize(); -} - int board_eth_init(bd_t *bis) { #ifdef CONFIG_TSEC_ENET @@ -540,15 +546,23 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_PCI1 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); +#else + ft_fsl_pci_setup(blob, "pci0", NULL); #endif #ifdef CONFIG_PCIE2 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); +#else + ft_fsl_pci_setup(blob, "pci1", NULL); #endif #ifdef CONFIG_PCIE2 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); +#else + ft_fsl_pci_setup(blob, "pci2", NULL); #endif #ifdef CONFIG_PCIE1 ft_fsl_pci_setup(blob, "pci3", &pcie3_hose); +#else + ft_fsl_pci_setup(blob, "pci3", NULL); #endif #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index f0b7abc..75d642b 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -27,9 +27,12 @@ #include <asm/arch/iomux.h> #include <asm/errno.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> #include <i2c.h> #include <mmc.h> #include <fsl_esdhc.h> +#include <fsl_pmic.h> +#include <mc13892.h> #include "mx51evk.h" DECLARE_GLOBAL_DATA_PTR; @@ -39,8 +42,8 @@ struct io_board_ctrl *mx51_io_board; #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC1_BASE_ADDR, 1, 1}, - {MMC_SDHC2_BASE_ADDR, 1, 1}, + {MMC_SDHC1_BASE_ADDR, 1}, + {MMC_SDHC2_BASE_ADDR, 1}, }; #endif @@ -147,6 +150,130 @@ static void setup_iomux_fec(void) mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180); } +#ifdef CONFIG_MXC_SPI +static void setup_iomux_spi(void) +{ + /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ + mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105); + + /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105); + + /* de-select SS1 of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85); + + /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */ + mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185); + + /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180); + + /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105); +} +#endif + +static void power_init(void) +{ + unsigned int val; + unsigned int reg; + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; + + /* Write needed to Power Gate 2 register */ + val = pmic_reg_read(REG_POWER_MISC); + val &= ~PWGT2SPIEN; + pmic_reg_write(REG_POWER_MISC, val); + + /* Write needed to update Charger 0 */ + pmic_reg_write(REG_CHARGE, VCHRG0 | VCHRG1 | VCHRG2 | + ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | ICHRGTR0 | + OVCTRL1 | UCHEN | CHRGLEDEN | CYCLB); + + /* power up the system first */ + pmic_reg_write(REG_POWER_MISC, PWUP); + + /* Set core voltage to 1.1V */ + val = pmic_reg_read(REG_SW_0); + val = (val & (~0x1F)) | 0x14; + pmic_reg_write(REG_SW_0, val); + + /* Setup VCC (SW2) to 1.25 */ + val = pmic_reg_read(REG_SW_1); + val = (val & (~0x1F)) | 0x1A; + pmic_reg_write(REG_SW_1, val); + + /* Setup 1V2_DIG1 (SW3) to 1.25 */ + val = pmic_reg_read(REG_SW_2); + val = (val & (~0x1F)) | 0x1A; + pmic_reg_write(REG_SW_2, val); + udelay(50); + + /* Raise the core frequency to 800MHz */ + writel(0x0, &mxc_ccm->cacrr); + + /* Set switchers in Auto in NORMAL mode & STANDBY mode */ + /* Setup the switcher mode for SW1 & SW2*/ + val = pmic_reg_read(REG_SW_4); + val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | + (SWMODE_MASK << SWMODE2_SHIFT))); + val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | + (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); + pmic_reg_write(REG_SW_4, val); + + /* Setup the switcher mode for SW3 & SW4 */ + val = pmic_reg_read(REG_SW_5); + val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) | + (SWMODE_MASK << SWMODE4_SHIFT))); + val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) | + (SWMODE_AUTO_AUTO << SWMODE4_SHIFT); + pmic_reg_write(REG_SW_5, val); + + /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */ + val = pmic_reg_read(REG_SETTING_0); + val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); + val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6; + pmic_reg_write(REG_SETTING_0, val); + + /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ + val = pmic_reg_read(REG_SETTING_1); + val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); + val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775; + pmic_reg_write(REG_SETTING_1, val); + + /* Configure VGEN3 and VCAM regulators to use external PNP */ + val = VGEN3CONFIG | VCAMCONFIG; + pmic_reg_write(REG_MODE_1, val); + udelay(200); + + reg = readl(GPIO2_BASE_ADDR + 0x0); + reg &= ~0x4000; /* Lower reset line */ + writel(reg, GPIO2_BASE_ADDR + 0x0); + + reg = readl(GPIO2_BASE_ADDR + 0x4); + reg |= 0x4000; /* configure GPIO lines as output */ + writel(reg, GPIO2_BASE_ADDR + 0x4); + + /* Reset the ethernet controller over GPIO */ + writel(0x1, IOMUXC_BASE_ADDR + 0x0AC); + + /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ + val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | + VVIDEOEN | VAUDIOEN | VSDEN; + pmic_reg_write(REG_MODE_1, val); + + udelay(500); + + reg = readl(GPIO2_BASE_ADDR + 0x0); + reg |= 0x4000; + writel(reg, GPIO2_BASE_ADDR + 0x0); +} + #ifdef CONFIG_FSL_ESDHC int board_mmc_getcd(u8 *cd, struct mmc *mmc) { @@ -284,9 +411,21 @@ int board_init(void) setup_iomux_uart(); setup_iomux_fec(); + return 0; } +#ifdef BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_MXC_SPI + setup_iomux_spi(); + power_init(); +#endif + return 0; +} +#endif + int checkboard(void) { puts("Board: MX51EVK "); diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c index 4d6a96d..2608698 100644 --- a/board/karo/tx25/tx25.c +++ b/board/karo/tx25/tx25.c @@ -145,6 +145,9 @@ int board_init() mx25_uart_init_pins(); #endif + /* board id for linux */ + gd->bd->bi_arch_number = MACH_TYPE_TX25; + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; return 0; } diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c index 0235545..cb30b48 100644 --- a/board/sheldon/simpc8313/simpc8313.c +++ b/board/sheldon/simpc8313/simpc8313.c @@ -33,13 +33,13 @@ DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_NAND_SPL int checkboard(void) { puts("Board: Sheldon Instruments SIMPC8313\n"); return 0; } -#ifndef CONFIG_NAND_SPL static struct pci_region pci_regions[] = { { bus_start: CONFIG_SYS_PCI1_MEM_BASE, diff --git a/common/cmd_flash.c b/common/cmd_flash.c index 3773412..6361c4e 100644 --- a/common/cmd_flash.c +++ b/common/cmd_flash.c @@ -34,7 +34,7 @@ #if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_CMD_MTDPARTS) #include <jffs2/jffs2.h> -/* parition handling routines */ +/* partition handling routines */ int mtdparts_init(void); int mtd_id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num); int find_dev_and_part(const char *id, struct mtd_device **dev, @@ -368,7 +368,7 @@ int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) addr_first = part->offset + info->start[0]; addr_last = addr_first + part->size - 1; - printf ("Erase Flash Parition %s, " + printf ("Erase Flash Partition %s, " "bank %ld, 0x%08lx - 0x%08lx ", argv[1], bank, addr_first, addr_last); @@ -576,7 +576,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) addr_first = part->offset + info->start[0]; addr_last = addr_first + part->size - 1; - printf ("%sProtect Flash Parition %s, " + printf ("%sProtect Flash Partition %s, " "bank %ld, 0x%08lx - 0x%08lx\n", p ? "" : "Un", argv[1], bank, addr_first, addr_last); diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 9b0c930..f611fd7 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -19,7 +19,7 @@ #if defined(CONFIG_CMD_MTDPARTS) -/* parition handling routines */ +/* partition handling routines */ int mtdparts_init(void); int id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num); int find_dev_and_part(const char *id, struct mtd_device **dev, diff --git a/common/ddr_spd.c b/common/ddr_spd.c index c058e4f..a7a30de 100644 --- a/common/ddr_spd.c +++ b/common/ddr_spd.c @@ -20,11 +20,15 @@ spd_check(const u8 *buf, u8 spd_rev, u8 spd_cksum) * Check SPD revision supported * Rev 1.2 or less supported by this code */ - if (spd_rev > 0x12) { + if (spd_rev >= 0x20) { printf("SPD revision %02X not supported by this code\n", spd_rev); return 1; } + if (spd_rev > 0x13) { + printf("SPD revision %02X not verified by this code\n", + spd_rev); + } /* * Calculate checksum diff --git a/doc/README.JFFS2_NAND b/doc/README.JFFS2_NAND index 2b3326b..5018ae8 100644 --- a/doc/README.JFFS2_NAND +++ b/doc/README.JFFS2_NAND @@ -5,7 +5,7 @@ To ebable, use the following #define in the board configuration file: #define CONFIG_JFFS2_NAND 1 Configuration of partitions is similar to how this is done in U-Boot -for JFFS2 on top NOR flash. If a single parition is used, it can be +for JFFS2 on top NOR flash. If a single partition is used, it can be configured using the following #defines in the configuration file: #define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */ diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index 8878560..4b97a0e 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2008 Freescale Semiconductor, Inc. + * Copyright (C) 2008,2010 Freescale Semiconductor, Inc. * Dave Liu <daveliu@freescale.com> * * This program is free software; you can redistribute it and/or @@ -22,6 +22,7 @@ #include <command.h> #include <asm/io.h> #include <asm/processor.h> +#include <asm/fsl_serdes.h> #include <malloc.h> #include <libata.h> #include <fis.h> @@ -129,6 +130,17 @@ int init_sata(int dev) return -1; } +#ifdef CONFIG_MPC85xx + if ((dev == 0) && (!is_serdes_configured(SATA1))) { + printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev); + return -1; + } + if ((dev == 1) && (!is_serdes_configured(SATA2))) { + printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev); + return -1; + } +#endif + /* Allocate SATA device driver struct */ sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t)); if (!sata) { diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index f6df60f..96aa331 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -31,6 +31,7 @@ COBJS-$(CONFIG_FSL_LAW) += fsl_law.o COBJS-$(CONFIG_NS87308) += ns87308.o COBJS-$(CONFIG_STATUS_LED) += status_led.o COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o +COBJS-$(CONFIG_FSL_PMIC) += fsl_pmic.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/misc/fsl_pmic.c b/drivers/misc/fsl_pmic.c new file mode 100644 index 0000000..87f0aed --- /dev/null +++ b/drivers/misc/fsl_pmic.c @@ -0,0 +1,200 @@ +/* + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <spi.h> +#include <asm/errno.h> +#include <linux/types.h> +#include <fsl_pmic.h> + +static struct spi_slave *slave; + +struct spi_slave *pmic_spi_probe(void) +{ + return spi_setup_slave(CONFIG_FSL_PMIC_BUS, + CONFIG_FSL_PMIC_CS, + CONFIG_FSL_PMIC_CLK, + CONFIG_FSL_PMIC_MODE); +} + +void pmic_spi_free(struct spi_slave *slave) +{ + if (slave) + spi_free_slave(slave); +} + +u32 pmic_reg(u32 reg, u32 val, u32 write) +{ + u32 pmic_tx, pmic_rx; + + if (!slave) { + slave = pmic_spi_probe(); + + if (!slave) + return -1; + } + + if (reg > 63 || write > 1) { + printf("<reg num> = %d is invalid. Should be less then 63\n", + reg); + return -1; + } + + if (spi_claim_bus(slave)) + return -1; + + pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FFFFFF); + + if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx, + SPI_XFER_BEGIN | SPI_XFER_END)) { + spi_release_bus(slave); + return -1; + } + + if (write) { + pmic_tx &= ~(1 << 31); + if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx, + SPI_XFER_BEGIN | SPI_XFER_END)) { + spi_release_bus(slave); + return -1; + } + } + + spi_release_bus(slave); + return pmic_rx; +} + +void pmic_reg_write(u32 reg, u32 value) +{ + pmic_reg(reg, value, 1); +} + +u32 pmic_reg_read(u32 reg) +{ + return pmic_reg(reg, 0, 0); +} + +void pmic_show_pmic_info(void) +{ + u32 rev_id; + + rev_id = pmic_reg_read(REG_IDENTIFICATION); + printf("PMIC ID: 0x%08x [Rev: ", rev_id); + switch (rev_id & 0x1F) { + case 0x1: + puts("1.0"); + break; + case 0x9: + puts("1.1"); + break; + case 0xA: + puts("1.2"); + break; + case 0x10: + puts("2.0"); + break; + case 0x11: + puts("2.1"); + break; + case 0x18: + puts("3.0"); + break; + case 0x19: + puts("3.1"); + break; + case 0x1A: + puts("3.2"); + break; + case 0x2: + puts("3.2A"); + break; + case 0x1B: + puts("3.3"); + break; + case 0x1D: + puts("3.5"); + break; + default: + puts("unknown"); + break; + } + puts("]\n"); +} + +static void pmic_dump(int numregs) +{ + u32 val; + int i; + + pmic_show_pmic_info(); + for (i = 0; i < numregs; i++) { + val = pmic_reg_read(i); + if (!(i % 8)) + printf ("\n0x%02x: ", i); + printf("%08x ", val); + } + puts("\n"); +} + +int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *cmd; + int nregs; + u32 val; + + /* at least two arguments please */ + if (argc < 2) { + cmd_usage(cmdtp); + return 1; + } + + cmd = argv[1]; + if (strcmp(cmd, "dump") == 0) { + if (argc < 3) { + cmd_usage(cmdtp); + return 1; + } + nregs = simple_strtoul(argv[2], NULL, 16); + pmic_dump(nregs); + return 0; + } + if (strcmp(cmd, "write") == 0) { + if (argc < 4) { + cmd_usage(cmdtp); + return 1; + } + nregs = simple_strtoul(argv[2], NULL, 16); + val = simple_strtoul(argv[3], NULL, 16); + pmic_reg_write(nregs, val); + return 0; + } + /* No subcommand found */ + return 1; +} + +U_BOOT_CMD( + pmic, CONFIG_SYS_MAXARGS, 1, do_pmic, + "Freescale PMIC (Atlas)", + "dump [numregs] dump registers\n" + "pmic write <reg> <value> - write register" +); diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c index 90e4002..810079f 100644 --- a/drivers/net/lan91c96.c +++ b/drivers/net/lan91c96.c @@ -795,7 +795,6 @@ int lan91c96_initialize(u8 dev_num, int base_addr) dev = malloc(sizeof(*dev)); if (!dev) { - free(dev); return 0; } memset(dev, 0, sizeof(*dev)); diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index f2fc88b..3da4c35 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -242,7 +242,6 @@ int smc911x_initialize(u8 dev_num, int base_addr) dev = malloc(sizeof(*dev)); if (!dev) { - free(dev); return -1; } memset(dev, 0, sizeof(*dev)); diff --git a/drivers/rtc/mc13783-rtc.c b/drivers/rtc/mc13783-rtc.c index 416f50d..4e18f80 100644 --- a/drivers/rtc/mc13783-rtc.c +++ b/drivers/rtc/mc13783-rtc.c @@ -23,53 +23,30 @@ #include <common.h> #include <rtc.h> #include <spi.h> - -static struct spi_slave *slave; +#include <fsl_pmic.h> int rtc_get(struct rtc_time *rtc) { u32 day1, day2, time; - u32 reg; - int err, tim, i = 0; - - if (!slave) { - /* FIXME: Verify the max SCK rate */ - slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS, - CONFIG_MC13783_SPI_CS, 1000000, - SPI_MODE_2 | SPI_CS_HIGH); - if (!slave) - return -1; - } - - if (spi_claim_bus(slave)) - return -1; + int tim, i = 0; do { - reg = 0x2c000000; - err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&day1, - SPI_XFER_BEGIN | SPI_XFER_END); - - if (err) - return err; - - reg = 0x28000000; - err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&time, - SPI_XFER_BEGIN | SPI_XFER_END); + day1 = pmic_reg_read(REG_RTC_DAY); + if (day1 < 0) + return -1; - if (err) - return err; + time = pmic_reg_read(REG_RTC_TIME); + if (time < 0) + return -1; - reg = 0x2c000000; - err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&day2, - SPI_XFER_BEGIN | SPI_XFER_END); + day2 = pmic_reg_read(REG_RTC_DAY); + if (day2 < 0) + return -1; - if (err) - return err; } while (day1 != day2 && i++ < 3); - spi_release_bus(slave); - tim = day1 * 86400 + time; + to_tm(tim, rtc); rtc->tm_yday = 0; @@ -80,34 +57,15 @@ int rtc_get(struct rtc_time *rtc) int rtc_set(struct rtc_time *rtc) { - u32 time, day, reg; - - if (!slave) { - /* FIXME: Verify the max SCK rate */ - slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS, - CONFIG_MC13783_SPI_CS, 1000000, - SPI_MODE_2 | SPI_CS_HIGH); - if (!slave) - return -1; - } + u32 time, day; time = mktime(rtc->tm_year, rtc->tm_mon, rtc->tm_mday, rtc->tm_hour, rtc->tm_min, rtc->tm_sec); day = time / 86400; time %= 86400; - if (spi_claim_bus(slave)) - return -1; - - reg = 0x2c000000 | day | 0x80000000; - spi_xfer(slave, 32, (uchar *)®, (uchar *)&day, - SPI_XFER_BEGIN | SPI_XFER_END); - - reg = 0x28000000 | time | 0x80000000; - spi_xfer(slave, 32, (uchar *)®, (uchar *)&time, - SPI_XFER_BEGIN | SPI_XFER_END); - - spi_release_bus(slave); + pmic_reg_write(REG_RTC_DAY, day); + pmic_reg_write(REG_RTC_TIME, time); return 0; } diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 3a45200..e15a63c 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -31,7 +31,7 @@ #error "i.MX27 CSPI not supported due to drastic differences in register definisions" \ "See linux mxc_spi driver from Freescale for details." -#else +#elif defined(CONFIG_MX31) #include <asm/arch/mx31.h> @@ -56,6 +56,9 @@ #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) +#define MXC_CSPICTRL_TC (1 << 8) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_MAXBITS 0x1f #define MXC_CSPIPERIOD_32KHZ (1 << 15) @@ -65,12 +68,63 @@ static unsigned long spi_bases[] = { 0x53f84000, }; +#define OUT MX31_GPIO_DIRECTION_OUT +#define mxc_gpio_direction mx31_gpio_direction +#define mxc_gpio_set mx31_gpio_set +#elif defined(CONFIG_MX51) +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> + +#define MXC_CSPIRXDATA 0x00 +#define MXC_CSPITXDATA 0x04 +#define MXC_CSPICTRL 0x08 +#define MXC_CSPICON 0x0C +#define MXC_CSPIINT 0x10 +#define MXC_CSPIDMA 0x14 +#define MXC_CSPISTAT 0x18 +#define MXC_CSPIPERIOD 0x1C +#define MXC_CSPIRESET 0x00 +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) +#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) +#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) + +#define MXC_CSPIPERIOD_32KHZ (1 << 15) + +/* Bit position inside CTRL register to be associated with SS */ +#define MXC_CSPICTRL_CHAN 18 + +/* Bit position inside CON register to be associated with SS */ +#define MXC_CSPICON_POL 4 +#define MXC_CSPICON_PHA 0 +#define MXC_CSPICON_SSPOL 12 + +static unsigned long spi_bases[] = { + CSPI1_BASE_ADDR, + CSPI2_BASE_ADDR, + CSPI3_BASE_ADDR, +}; +#define mxc_gpio_direction(gpio, dir) (0) +#define mxc_gpio_set(gpio, value) {} +#define OUT 1 +#else +#error "Unsupported architecture" #endif struct mxc_spi_slave { struct spi_slave slave; unsigned long base; u32 ctrl_reg; +#if defined(CONFIG_MX51) + u32 cfg_reg; +#endif int gpio; }; @@ -89,34 +143,161 @@ static inline void reg_write(unsigned long addr, u32 val) *(volatile unsigned long*)addr = val; } +void spi_cs_activate(struct spi_slave *slave) +{ + struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); + if (mxcs->gpio > 0) + mxc_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); + if (mxcs->gpio > 0) + mxc_gpio_set(mxcs->gpio, + !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL)); +} + +#ifdef CONFIG_MX51 +static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); + s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config; + u32 ss_pol = 0, sclkpol = 0, sclkpha = 0; + + if (max_hz == 0) { + printf("Error: desired clock is 0\n"); + return -1; + } + + reg_ctrl = reg_read(mxcs->base + MXC_CSPICTRL); + + /* Reset spi */ + reg_write(mxcs->base + MXC_CSPICTRL, 0); + reg_write(mxcs->base + MXC_CSPICTRL, (reg_ctrl | 0x1)); + + /* + * The following computation is taken directly from Freescale's code. + */ + if (clk_src > max_hz) { + pre_div = clk_src / max_hz; + if (pre_div > 16) { + post_div = pre_div / 16; + pre_div = 15; + } + if (post_div != 0) { + for (i = 0; i < 16; i++) { + if ((1 << i) >= post_div) + break; + } + if (i == 16) { + printf("Error: no divider for the freq: %d\n", + max_hz); + return -1; + } + post_div = i; + } + } + + debug("pre_div = %d, post_div=%d\n", pre_div, post_div); + reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | + MXC_CSPICTRL_SELCHAN(cs); + reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | + MXC_CSPICTRL_PREDIV(pre_div); + reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | + MXC_CSPICTRL_POSTDIV(post_div); + + /* always set to master mode */ + reg_ctrl |= 1 << (cs + 4); + + /* We need to disable SPI before changing registers */ + reg_ctrl &= ~MXC_CSPICTRL_EN; + + if (mode & SPI_CS_HIGH) + ss_pol = 1; + + if (!(mode & SPI_CPOL)) + sclkpol = 1; + + if (mode & SPI_CPHA) + sclkpha = 1; + + reg_config = reg_read(mxcs->base + MXC_CSPICON); + + /* + * Configuration register setup + * The MX51 has support different setup for each SS + */ + reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | + (ss_pol << (cs + MXC_CSPICON_SSPOL)); + reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | + (sclkpol << (cs + MXC_CSPICON_POL)); + reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | + (sclkpha << (cs + MXC_CSPICON_PHA)); + + debug("reg_ctrl = 0x%x\n", reg_ctrl); + reg_write(mxcs->base + MXC_CSPICTRL, reg_ctrl); + debug("reg_config = 0x%x\n", reg_config); + reg_write(mxcs->base + MXC_CSPICON, reg_config); + + /* save config register and control register */ + mxcs->ctrl_reg = reg_ctrl; + mxcs->cfg_reg = reg_config; + + /* clear interrupt reg */ + reg_write(mxcs->base + MXC_CSPIINT, 0); + reg_write(mxcs->base + MXC_CSPISTAT, + MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); + + return 0; +} +#endif + static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen, unsigned long flags) { struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); - unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL); - mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(31)) | + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + mxcs->ctrl_reg = (mxcs->ctrl_reg & + ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | MXC_CSPICTRL_BITCOUNT(bitlen - 1); - if (cfg_reg != mxcs->ctrl_reg) - reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg); + reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_EN); +#ifdef CONFIG_MX51 + reg_write(mxcs->base + MXC_CSPICON, mxcs->cfg_reg); +#endif - if (mxcs->gpio > 0 && (flags & SPI_XFER_BEGIN)) - mx31_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL); + /* Clear interrupt register */ + reg_write(mxcs->base + MXC_CSPISTAT, + MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); + debug("Sending SPI 0x%x\n", data); reg_write(mxcs->base + MXC_CSPITXDATA, data); - reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_XCH); + /* FIFO is written, now starts the transfer setting the XCH bit */ + reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | + MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); - while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH) + /* Wait until the TC (Transfer completed) bit is set */ + while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0) ; - if (mxcs->gpio > 0 && (flags & SPI_XFER_END)) { - mx31_gpio_set(mxcs->gpio, - !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL)); - } + /* Transfer completed, clear any pending request */ + reg_write(mxcs->base + MXC_CSPISTAT, + MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); + + data = reg_read(mxcs->base + MXC_CSPIRXDATA); + debug("SPI Rx: 0x%x\n", data); + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return data; - return reg_read(mxcs->base + MXC_CSPIRXDATA); } int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, @@ -176,7 +357,7 @@ static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) if (cs > 3) { mxcs->gpio = cs >> 8; cs &= 3; - ret = mx31_gpio_direction(mxcs->gpio, MX31_GPIO_DIRECTION_OUT); + ret = mxc_gpio_direction(mxcs->gpio, OUT); if (ret) { printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); return -EINVAL; @@ -210,6 +391,20 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, cs = ret; + mxcs->slave.bus = bus; + mxcs->slave.cs = cs; + mxcs->base = spi_bases[bus]; + +#ifdef CONFIG_MX51 + /* Can be used for i.MX31 too ? */ + ctrl_reg = 0; + ret = spi_cfg(mxcs, cs, max_hz, mode); + if (ret) { + printf("mxc_spi: cannot setup SPI controller\n"); + free(mxcs); + return NULL; + } +#else ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | MXC_CSPICTRL_BITCOUNT(31) | MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */ @@ -222,12 +417,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, ctrl_reg |= MXC_CSPICTRL_POL; if (mode & SPI_CS_HIGH) ctrl_reg |= MXC_CSPICTRL_SSPOL; - - mxcs->slave.bus = bus; - mxcs->slave.cs = cs; - mxcs->base = spi_bases[bus]; mxcs->ctrl_reg = ctrl_reg; - +#endif return &mxcs->slave; } diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c index 99a595e..7f04b49 100644 --- a/drivers/video/mx3fb.c +++ b/drivers/video/mx3fb.c @@ -56,22 +56,7 @@ void lcd_panel_disable(void) #define msleep(a) udelay(a * 1000) -#ifndef CONFIG_DISPLAY_VBEST_VGG322403 -#define XRES 240 -#define YRES 320 -#define PANEL_TYPE IPU_PANEL_TFT -#define PIXEL_CLK 185925 -#define PIXEL_FMT IPU_PIX_FMT_RGB666 -#define H_START_WIDTH 9 /* left_margin */ -#define H_SYNC_WIDTH 1 /* hsync_len */ -#define H_END_WIDTH (16 + 1) /* right_margin + hsync_len */ -#define V_START_WIDTH 7 /* upper_margin */ -#define V_SYNC_WIDTH 1 /* vsync_len */ -#define V_END_WIDTH (9 + 1) /* lower_margin + vsync_len */ -#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) -#define IF_CONF 0 -#define IF_CLK_DIV 0x175 -#else /* Display Vbest VGG322403 */ +#if defined(CONFIG_DISPLAY_VBEST_VGG322403) #define XRES 320 #define YRES 240 #define PANEL_TYPE IPU_PANEL_TFT @@ -86,6 +71,36 @@ void lcd_panel_disable(void) #define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) #define IF_CONF 0 #define IF_CLK_DIV 0x175 +#elif defined(CONFIG_DISPLAY_COM57H5M10XRC) +#define XRES 640 +#define YRES 480 +#define PANEL_TYPE IPU_PANEL_TFT +#define PIXEL_CLK 40000 +#define PIXEL_FMT IPU_PIX_FMT_RGB666 +#define H_START_WIDTH 120 /* left_margin */ +#define H_SYNC_WIDTH 30 /* hsync_len */ +#define H_END_WIDTH (10 + 30) /* right_margin + hsync_len */ +#define V_START_WIDTH 35 /* upper_margin */ +#define V_SYNC_WIDTH 3 /* vsync_len */ +#define V_END_WIDTH (7 + 3) /* lower_margin + vsync_len */ +#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) +#define IF_CONF 0 +#define IF_CLK_DIV 0x175 +#else +#define XRES 240 +#define YRES 320 +#define PANEL_TYPE IPU_PANEL_TFT +#define PIXEL_CLK 185925 +#define PIXEL_FMT IPU_PIX_FMT_RGB666 +#define H_START_WIDTH 9 /* left_margin */ +#define H_SYNC_WIDTH 1 /* hsync_len */ +#define H_END_WIDTH (16 + 1) /* right_margin + hsync_len */ +#define V_START_WIDTH 7 /* upper_margin */ +#define V_SYNC_WIDTH 1 /* vsync_len */ +#define V_END_WIDTH (9 + 1) /* lower_margin + vsync_len */ +#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL) +#define IF_CONF 0 +#define IF_CLK_DIV 0x175 #endif #define LCD_COLOR_IPU LCD_COLOR16 diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 1a17323..9104f1a 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -418,7 +418,8 @@ | SICRH_ETSEC2_G \ | SICRH_TSOBI1 \ | SICRH_TSOBI2 ) -#define CONFIG_SYS_SICRL (SICRL_USBDR \ +#define CONFIG_SYS_SICRL ( SICRL_LBC \ + | SICRL_USBDR \ | SICRL_ETSEC2_A ) #define CONFIG_SYS_HID0_INIT 0x000000000 diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 6131008..4904856 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -68,10 +68,13 @@ #define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 1 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 1000000 +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) + #define CONFIG_RTC_MC13783 1 -/* MC13783 connected to CSPI2 and SS0 */ -#define CONFIG_MC13783_SPI_BUS 1 -#define CONFIG_MC13783_SPI_CS 0 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -89,6 +92,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_SPI #define CONFIG_CMD_DATE +#define CONFIG_CMD_NAND #define CONFIG_BOOTDELAY 3 @@ -174,4 +178,13 @@ #undef CONFIG_CMD_MTDPARTS #define CONFIG_JFFS2_DEV "nor0" +/* + * NAND flash + */ +#define CONFIG_NAND_MXC +#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR +#define CONFIG_MXC_NAND_HWECC + #endif /* __CONFIG_H */ diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index ec1c905..dedecd7 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -65,10 +65,12 @@ #define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 1 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 1000000 +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 -/* MC13783 connected to CSPI2 and SS0 */ -#define CONFIG_MC13783_SPI_BUS 1 -#define CONFIG_MC13783_SPI_CS 0 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index bee2f45..0414cc3 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -69,12 +69,13 @@ #define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 1 +#define CONFIG_FSL_PMIC_CS 2 +#define CONFIG_FSL_PMIC_CLK 1000000 +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 -/* MC13783 connected to CSPI2 and SS2 */ -#define CONFIG_MC13783_SPI_BUS 1 -#define CONFIG_MC13783_SPI_CS 2 - /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 3626df7..86a4731 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -54,6 +54,8 @@ /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_SIZE 128 +#define BOARD_LATE_INIT + /* * Hardware drivers */ @@ -61,6 +63,19 @@ #define CONFIG_SYS_MX51_UART1 /* + * SPI Configs + * */ +#define CONFIG_CMD_SPI + +#define CONFIG_MXC_SPI + +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 0 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 2500000 +#define CONFIG_FSL_PMIC_MODE (SPI_CPOL | SPI_CS_HIGH) + +/* * MMC Configs * */ #define CONFIG_FSL_ESDHC diff --git a/include/configs/qong.h b/include/configs/qong.h index 1d63b33..100fa3f 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -54,6 +54,17 @@ #define CONFIG_MX31_GPIO +#define CONFIG_MXC_SPI +#define CONFIG_DEFAULT_SPI_BUS 1 +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_RTC_MC13783 + +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 1 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 100000 +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) + /* FPGA */ #define CONFIG_QONG_FPGA 1 #define CONFIG_FPGA_BASE (CS1_BASE) @@ -73,7 +84,7 @@ #define CONFIG_SPLASH_SCREEN #define CONFIG_CMD_BMP #define CONFIG_BMP_16BPP -#define CONFIG_DISPLAY_VBEST_VGG322403 +#define CONFIG_DISPLAY_COM57H5M10XRC /* * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the @@ -98,6 +109,9 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_MII #define CONFIG_CMD_NAND +#define CONFIG_CMD_SPI +#define CONFIG_CMD_DATE +#define BOARD_LATE_INIT /* * You can compile in a MAC address and your custom net settings by using diff --git a/include/fsl_pmic.h b/include/fsl_pmic.h new file mode 100644 index 0000000..e3abde6 --- /dev/null +++ b/include/fsl_pmic.h @@ -0,0 +1,128 @@ +/* + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FSL_PMIC_H__ +#define __FSL_PMIC_H__ + +/* + * The registers of different PMIC has the same meaning + * but the bit positions of the fields can differ or + * some fields has a meaning only on some devices. + * You have to check with the internal SPI bitmap + * (see Freescale Documentation) to set the registers + * for the device you are using + */ +enum { + REG_INT_STATUS0 = 0, + REG_INT_MASK0, + REG_INT_SENSE0, + REG_INT_STATUS1, + REG_INT_MASK1, + REG_INT_SENSE1, + REG_PU_MODE_S, + REG_IDENTIFICATION, + REG_UNUSED0, + REG_ACC0, + REG_ACC1, /*10 */ + REG_UNUSED1, + REG_UNUSED2, + REG_POWER_CTL0, + REG_POWER_CTL1, + REG_POWER_CTL2, + REG_REGEN_ASSIGN, + REG_UNUSED3, + REG_MEM_A, + REG_MEM_B, + REG_RTC_TIME, /*20 */ + REG_RTC_ALARM, + REG_RTC_DAY, + REG_RTC_DAY_ALARM, + REG_SW_0, + REG_SW_1, + REG_SW_2, + REG_SW_3, + REG_SW_4, + REG_SW_5, + REG_SETTING_0, /*30 */ + REG_SETTING_1, + REG_MODE_0, + REG_MODE_1, + REG_POWER_MISC, + REG_UNUSED4, + REG_UNUSED5, + REG_UNUSED6, + REG_UNUSED7, + REG_UNUSED8, + REG_UNUSED9, /*40 */ + REG_UNUSED10, + REG_UNUSED11, + REG_ADC0, + REG_ADC1, + REG_ADC2, + REG_ADC3, + REG_ADC4, + REG_CHARGE, + REG_USB0, + REG_USB1, /*50 */ + REG_LED_CTL0, + REG_LED_CTL1, + REG_LED_CTL2, + REG_LED_CTL3, + REG_UNUSED12, + REG_UNUSED13, + REG_TRIM0, + REG_TRIM1, + REG_TEST0, + REG_TEST1, /*60 */ + REG_TEST2, + REG_TEST3, + REG_TEST4, +}; + +/* REG_POWER_MISC */ +#define GPO1EN (1 << 6) +#define GPO1STBY (1 << 7) +#define GPO2EN (1 << 8) +#define GPO2STBY (1 << 9) +#define GPO3EN (1 << 10) +#define GPO3STBY (1 << 11) +#define GPO4EN (1 << 12) +#define GPO4STBY (1 << 13) +#define PWGT1SPIEN (1 << 15) +#define PWGT2SPIEN (1 << 16) +#define PWUP (1 << 21) + +/* Power Control 0 */ +#define COINCHEN (1 << 23) +#define BATTDETEN (1 << 19) + +/* Interrupt status 1 */ +#define RTCRSTI (1 << 7) + +void pmic_show_pmic_info(void); +void pmic_reg_write(u32 reg, u32 value); +u32 pmic_reg_read(u32 reg); + +#endif diff --git a/include/mc13892.h b/include/mc13892.h new file mode 100644 index 0000000..b291757 --- /dev/null +++ b/include/mc13892.h @@ -0,0 +1,160 @@ +/* + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __MC13892_H__ +#define __MC13892_H__ + +/* REG_CHARGE */ + +#define VCHRG0 0 +#define VCHRG1 (1 << 1) +#define VCHRG2 (1 << 2) +#define ICHRG0 (1 << 3) +#define ICHRG1 (1 << 4) +#define ICHRG2 (1 << 5) +#define ICHRG3 (1 << 6) +#define ICHRGTR0 (1 << 7) +#define ICHRGTR1 (1 << 8) +#define ICHRGTR2 (1 << 9) +#define FETOVRD (1 << 10) +#define FETCTRL (1 << 11) +#define RVRSMODE (1 << 13) +#define OVCTRL0 (1 << 15) +#define OVCTRL1 (1 << 16) +#define UCHEN (1 << 17) +#define CHRGLEDEN (1 << 18) +#define CHRGRAWPDEN (1 << 19) +#define CHGRESTART (1 << 20) +#define CHGAUTOB (1 << 21) +#define CYCLB (1 << 22) +#define CHGAUTOVIB (1 << 23) + +/* REG_SETTING_0/1 */ +#define VO_1_20V 0 +#define VO_1_30V 1 +#define VO_1_50V 2 +#define VO_1_80V 3 +#define VO_1_10V 4 +#define VO_2_00V 5 +#define VO_2_77V 6 +#define VO_2_40V 7 + +#define VIOL 2 +#define VDIG 4 +#define VGEN 6 + +/* SWxMode for Normal/Standby Mode */ +#define SWMODE_OFF_OFF 0 +#define SWMODE_PWM_OFF 1 +#define SWMODE_PWMPS_OFF 2 +#define SWMODE_PFM_OFF 3 +#define SWMODE_AUTO_OFF 4 +#define SWMODE_PWM_PWM 5 +#define SWMODE_PWM_AUTO 6 +#define SWMODE_AUTO_AUTO 8 +#define SWMODE_PWM_PWMPS 9 +#define SWMODE_PWMS_PWMPS 10 +#define SWMODE_PWMS_AUTO 11 +#define SWMODE_AUTO_PFM 12 +#define SWMODE_PWM_PFM 13 +#define SWMODE_PWMS_PFM 14 +#define SWMODE_PFM_PFM 15 +#define SWMODE_MASK 0x0F + +#define SWMODE1_SHIFT 0 +#define SWMODE2_SHIFT 10 +#define SWMODE3_SHIFT 0 +#define SWMODE4_SHIFT 8 + +/* Fields in REG_SETTING_1 */ +#define VVIDEO_2_7 (0 << 2) +#define VVIDEO_2_775 (1 << 2) +#define VVIDEO_2_5 (2 << 2) +#define VVIDEO_2_6 (3 << 2) +#define VVIDEO_MASK (3 << 2) +#define VAUDIO_2_3 (0 << 4) +#define VAUDIO_2_5 (1 << 4) +#define VAUDIO_2_775 (2 << 4) +#define VAUDIO_3_0 (3 << 4) +#define VAUDIO_MASK (3 << 4) +#define VSD_1_8 (0 << 6) +#define VSD_2_0 (1 << 6) +#define VSD_2_6 (2 << 6) +#define VSD_2_7 (3 << 6) +#define VSD_2_8 (4 << 6) +#define VSD_2_9 (5 << 6) +#define VSD_3_0 (6 << 6) +#define VSD_3_15 (7 << 6) +#define VSD_MASK (7 << 6) +#define VGEN1_1_2 0 +#define VGEN1_1_5 1 +#define VGEN1_2_775 2 +#define VGEN1_3_15 3 +#define VGEN1_MASK 3 +#define VGEN2_1_2 (0 << 6) +#define VGEN2_1_5 (1 << 6) +#define VGEN2_1_6 (2 << 6) +#define VGEN2_1_8 (3 << 6) +#define VGEN2_2_7 (4 << 6) +#define VGEN2_2_8 (5 << 6) +#define VGEN2_3_0 (6 << 6) +#define VGEN2_3_15 (7 << 6) +#define VGEN2_MASK (7 << 6) + +/* Fields in REG_SETTING_1 */ +#define VGEN3_1_8 (0 << 14) +#define VGEN3_2_9 (1 << 14) +#define VGEN3_MASK (1 << 14) +#define VDIG_1_05 (0 << 4) +#define VDIG_1_25 (1 << 4) +#define VDIG_1_65 (2 << 4) +#define VDIG_1_8 (3 << 4) +#define VDIG_MASK (3 << 4) +#define VCAM_2_5 (0 << 16) +#define VCAM_2_6 (1 << 16) +#define VCAM_2_75 (2 << 16) +#define VCAM_3_0 (3 << 16) +#define VCAM_MASK (3 << 16) + +/* Reg Mode 1 */ +#define VGEN3EN (1 << 0) +#define VGEN3STBY (1 << 1) +#define VGEN3MODE (1 << 2) +#define VGEN3CONFIG (1 << 3) +#define VCAMEN (1 << 6) +#define VCAMSTBY (1 << 7) +#define VCAMMODE (1 << 8) +#define VCAMCONFIG (1 << 9) +#define VVIDEOEN (1 << 12) +#define VIDEOSTBY (1 << 13) +#define VVIDEOMODE (1 << 14) +#define VAUDIOEN (1 << 15) +#define VAUDIOSTBY (1 << 16) +#define VSDEN (1 << 18) +#define VSDSTBY (1 << 19) +#define VSDMODE (1 << 20) + +#endif diff --git a/lib/display_options.c b/lib/display_options.c index 86df05d..a711425 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -46,13 +46,14 @@ int display_options (void) void print_size(unsigned long long size, const char *s) { unsigned long m = 0, n; + unsigned long long f; static const char names[] = {'E', 'P', 'T', 'G', 'M', 'K'}; - unsigned long long d = 1ULL << (10 * ARRAY_SIZE(names)); + unsigned long d = 10 * ARRAY_SIZE(names); char c = 0; unsigned int i; - for (i = 0; i < ARRAY_SIZE(names); i++, d >>= 10) { - if (size >= d) { + for (i = 0; i < ARRAY_SIZE(names); i++, d -= 10) { + if (size >> d) { c = names[i]; break; } @@ -63,11 +64,12 @@ void print_size(unsigned long long size, const char *s) return; } - n = size / d; + n = size >> d; + f = size & ((1ULL << d) - 1); /* If there's a remainder, deal with it */ - if(size % d) { - m = (10 * (size - (n * d)) + (d / 2) ) / d; + if (f) { + m = (10ULL * f + (1ULL << (d - 1))) >> d; if (m >= 10) { m -= 10; |