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-rw-r--r--board/ads5121/ads5121.c4
-rw-r--r--include/configs/ads5121.h1
-rw-r--r--include/mpc512x.h1
3 files changed, 6 insertions, 0 deletions
diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c
index ba3d7d2..deaa292 100644
--- a/board/ads5121/ads5121.c
+++ b/board/ads5121/ads5121.c
@@ -25,6 +25,7 @@
#include <mpc512x.h>
#include <asm/bitops.h>
#include <command.h>
+#include <asm/processor.h>
#include <fdt_support.h>
#ifdef CONFIG_MISC_INIT_R
#include <i2c.h>
@@ -92,6 +93,9 @@ int board_early_init_f (void)
* Configure Flash Speed
*/
*((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG;
+ if (SVR_MJREV (im->sysconf.spridr) >= 2) {
+ *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CFG_CS_ALETIMING;
+ }
/*
* Enable clocks
*/
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index 5f74afb..f516c46 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -210,6 +210,7 @@
#define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
#define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
+#define CFG_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */
/* Use SRAM for initial stack */
#define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */
diff --git a/include/mpc512x.h b/include/mpc512x.h
index a76b1ca..cb418d1 100644
--- a/include/mpc512x.h
+++ b/include/mpc512x.h
@@ -58,6 +58,7 @@
#define CS5_CONFIG 0x00014
#define CS6_CONFIG 0x00018
#define CS7_CONFIG 0x0001C
+#define CS_ALE_TIMING_CONFIG 0x00034
#define CS_CTRL 0x00020
#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */