diff options
69 files changed, 3848 insertions, 1465 deletions
@@ -151,50 +151,10 @@ ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk)) include $(obj)include/config.mk export ARCH CPU BOARD VENDOR SOC -ifndef CROSS_COMPILE +# set default to nothing for native builds ifeq ($(HOSTARCH),$(ARCH)) -CROSS_COMPILE = -else -ifeq ($(ARCH),ppc) -CROSS_COMPILE = ppc_8xx- -endif -ifeq ($(ARCH),arm) -CROSS_COMPILE = arm-linux- -endif -ifeq ($(ARCH),i386) -CROSS_COMPILE = i386-linux- -endif -ifeq ($(ARCH),mips) -CROSS_COMPILE = mips_4KC- -endif -ifeq ($(ARCH),nios) -CROSS_COMPILE = nios-elf- -endif -ifeq ($(ARCH),nios2) -CROSS_COMPILE = nios2-elf- +CROSS_COMPILE ?= endif -ifeq ($(ARCH),m68k) -CROSS_COMPILE = m68k-elf- -endif -ifeq ($(ARCH),microblaze) -CROSS_COMPILE = mb- -endif -ifeq ($(ARCH),blackfin) -CROSS_COMPILE = bfin-uclinux- -endif -ifeq ($(ARCH),avr32) -CROSS_COMPILE = avr32-linux- -endif -ifeq ($(ARCH),sh) -CROSS_COMPILE = sh4-linux- -endif -ifeq ($(ARCH),sparc) -CROSS_COMPILE = sparc-elf- -endif # sparc -endif # HOSTARCH,ARCH -endif # CROSS_COMPILE - -export CROSS_COMPILE # load other configuration include $(TOPDIR)/config.mk @@ -696,6 +656,7 @@ o2dnt_config: unconfig pcm030_config \ pcm030_LOWBOOT_config: unconfig + @mkdir -p $(obj)include $(obj)board/phytec/pcm030 @ >$(obj)include/config.h @[ -z "$(findstring LOWBOOT_,$@)" ] || \ { echo "TEXT_BASE = 0xFF000000" >$(obj)board/phytec/pcm030/config.tmp ; \ diff --git a/arm_config.mk b/arm_config.mk index c4cf99d..a13603e 100644 --- a/arm_config.mk +++ b/arm_config.mk @@ -21,6 +21,8 @@ # MA 02111-1307 USA # +CROSS_COMPILE ?= arm-linux- + PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ LDSCRIPT := $(SRCTREE)/cpu/$(CPU)/u-boot.lds diff --git a/avr32_config.mk b/avr32_config.mk index 441caa4..c258b4b 100644 --- a/avr32_config.mk +++ b/avr32_config.mk @@ -21,5 +21,7 @@ # MA 02111-1307 USA # +CROSS_COMPILE ?= avr32-linux- + PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax PLATFORM_LDFLAGS += --relax diff --git a/blackfin_config.mk b/blackfin_config.mk index 821f082..0dd2ac6 100644 --- a/blackfin_config.mk +++ b/blackfin_config.mk @@ -21,6 +21,8 @@ # MA 02111-1307 USA # +CROSS_COMPILE ?= bfin-uclinux- + CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU))) CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE))) CONFIG_ENV_OFFSET := $(strip $(subst ",,$(CONFIG_ENV_OFFSET))) diff --git a/board/bmw/bmw.c b/board/bmw/bmw.c index 870011e..4039145 100644 --- a/board/bmw/bmw.c +++ b/board/bmw/bmw.c @@ -117,6 +117,7 @@ sys_led_msg(char* msg) LED_REG(3) = msg[0]; } +#ifdef CONFIG_CMD_DOC /* * Map onboard TSOP-16MB DOC FLASH chip. */ @@ -124,6 +125,7 @@ void doc_init (void) { doc_probe(DOC_BASE_ADDR); } +#endif #define NV_ADDR ((volatile unsigned char *) CONFIG_ENV_ADDR) diff --git a/board/freescale/mpc832xemds/Makefile b/board/freescale/mpc832xemds/Makefile index a97116c..c34905c 100644 --- a/board/freescale/mpc832xemds/Makefile +++ b/board/freescale/mpc832xemds/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c index 212fb52..e1dd757 100644 --- a/board/freescale/mpc832xemds/pci.c +++ b/board/freescale/mpc832xemds/pci.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -16,62 +16,78 @@ #include <asm/mmu.h> #include <asm/io.h> #include <common.h> +#include <mpc83xx.h> #include <pci.h> #include <i2c.h> -#if defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#include <fdt_support.h> -#endif - #include <asm/fsl_i2c.h> +#include "../common/pq-mds-pib.h" DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_PCI) -#define PCI_FUNCTION_CONFIG 0x44 -#define PCI_FUNCTION_CFG_LOCK 0x20 +static struct pci_region pci1_regions[] = { + { + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, + flags: PCI_REGION_IO + }, + { + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, +}; -/* - * Initialize PCI Devices, report devices found - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc83xxemds_config_table[] = { +#ifdef CONFIG_MPC83XX_PCI2 +static struct pci_region pci2_regions[] = { { - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - pci_cfgfunc_config_device, - {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} + bus_start: CONFIG_SYS_PCI2_MEM_BASE, + phys_start: CONFIG_SYS_PCI2_MEM_PHYS, + size: CONFIG_SYS_PCI2_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH }, - {} -} -#endif -static struct pci_controller hose[] = { { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc83xxemds_config_table, -#endif + bus_start: CONFIG_SYS_PCI2_IO_BASE, + phys_start: CONFIG_SYS_PCI2_IO_PHYS, + size: CONFIG_SYS_PCI2_IO_SIZE, + flags: PCI_REGION_IO + }, + { + bus_start: CONFIG_SYS_PCI2_MMIO_BASE, + phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, + size: CONFIG_SYS_PCI2_MMIO_SIZE, + flags: PCI_REGION_MEM }, }; +#endif + +DECLARE_GLOBAL_DATA_PTR; + -/********************************************************************** - * pci_init_board() - *********************************************************************/ void pci_init_board(void) #ifdef CONFIG_PCISLAVE { - u16 reg16; - volatile immap_t *immr; - volatile law83xx_t *pci_law; - volatile pot83xx_t *pci_pot; - volatile pcictrl83xx_t *pci_ctrl; - volatile pciconf83xx_t *pci_conf; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0]; + struct pci_region *reg[] = { pci1_regions }; + + /* Configure PCI Local Access Windows */ + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; + + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; + + mpc83xx_pci_init(1, reg, 0); - immr = (immap_t *) CONFIG_SYS_IMMR; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; /* * Configure PCI Inbound Translation Windows */ @@ -90,61 +106,24 @@ void pci_init_board(void) pci_ctrl[0].piebar2 = 0x0; pci_ctrl[0].piwar2 &= ~PIWAR_EN; - hose[0].first_busno = 0; - hose[0].last_busno = 0xff; - pci_setup_indirect(&hose[0], - (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304)); - reg16 = 0xff; - - pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_STATUS, 0xffff); - pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), - PCI_LATENCY_TIMER, 0x80); - - /* - * Unlock configuration lock in PCI function configuration register. - */ - pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_FUNCTION_CONFIG, ®16); - reg16 &= ~(PCI_FUNCTION_CFG_LOCK); - pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_FUNCTION_CONFIG, reg16); - - printf("Enabled PCI 32bit Agent Mode\n"); + /* Unlock the configuration bit */ + mpc83xx_pcislave_unlock(0); + printf("PCI: Agent mode enabled\n"); } #else { - volatile immap_t *immr; - volatile clk83xx_t *clk; - volatile law83xx_t *pci_law; - volatile pot83xx_t *pci_pot; - volatile pcictrl83xx_t *pci_ctrl; - volatile pciconf83xx_t *pci_conf; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; +#ifndef CONFIG_MPC83XX_PCI2 + struct pci_region *reg[] = { pci1_regions }; +#else + struct pci_region *reg[] = { pci1_regions, pci2_regions }; +#endif - u16 reg16; - u32 val32; - u32 dev; + /* initialize the PCA9555PW IO expander on the PIB board */ + pib_init(); - immr = (immap_t *) CONFIG_SYS_IMMR; - clk = (clk83xx_t *) & immr->clk; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; - /* - * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode - */ - val32 = clk->occr; - udelay(2000); #if defined(PCI_66M) clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; printf("PCI clock is 66MHz\n"); @@ -158,129 +137,19 @@ void pci_init_board(void) #endif udelay(2000); - /* - * Configure PCI Local Access Windows - */ - pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; + /* Configure PCI Local Access Windows */ + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI mem space - prefetch */ - pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[0].pocmr = - POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI mmio - non-prefetch mem space */ - pci_pot[1].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI IO space */ - pci_pot[2].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - pci_ctrl[0].pitar1 = (CONFIG_SYS_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; - pci_ctrl[0].pibar1 = (CONFIG_SYS_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 = - PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | - PIWAR_IWS_2G; - - /* - * Release PCI RST Output signal - */ udelay(2000); - pci_ctrl[0].gcr = 1; - udelay(2000); - - hose[0].first_busno = 0; - hose[0].last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose[0].regions + 0, - CONFIG_SYS_PCI_MEM_BASE, - CONFIG_SYS_PCI_MEM_PHYS, - CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose[0].regions + 1, - CONFIG_SYS_PCI_MMIO_BASE, - CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose[0].regions + 2, - CONFIG_SYS_PCI_IO_BASE, - CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose[0].regions + 3, - CONFIG_SYS_PCI_SLV_MEM_LOCAL, - CONFIG_SYS_PCI_SLV_MEM_BUS, - CONFIG_SYS_PCI_SLV_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - hose[0].region_count = 4; - - pci_setup_indirect(&hose[0], - (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304)); - - pci_register_hose(hose); - - /* - * Write command register - */ - reg16 = 0xff; - dev = PCI_BDF(0, 0, 0); - pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); - - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); +#ifndef CONFIG_MPC83XX_PCI2 + mpc83xx_pci_init(1, reg, 0); +#else + mpc83xx_pci_init(2, reg, 0); +#endif } #endif /* CONFIG_PCISLAVE */ - -#if defined(CONFIG_OF_LIBFDT) -void ft_pci_setup(void *blob, bd_t *bd) -{ - int nodeoffset; - int tmp[2]; - const char *path; - - nodeoffset = fdt_path_offset(blob, "/aliases"); - if (nodeoffset >= 0) { - path = fdt_getprop(blob, nodeoffset, "pci0", NULL); - if (path) { - tmp[0] = cpu_to_be32(hose[0].first_busno); - tmp[1] = cpu_to_be32(hose[0].last_busno); - do_fixup_by_path(blob, path, "bus-range", - &tmp, sizeof(tmp), 1); - - tmp[0] = cpu_to_be32(gd->pci_clk); - do_fixup_by_path(blob, path, "clock-frequency", - &tmp, sizeof(tmp[0]), 1); - } - } -} -#endif /* CONFIG_OF_LIBFDT */ -#endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile index a97116c..c34905c 100644 --- a/board/freescale/mpc8349emds/Makefile +++ b/board/freescale/mpc8349emds/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c index af0b1da..9293f70 100644 --- a/board/freescale/mpc8349emds/pci.c +++ b/board/freescale/mpc8349emds/pci.c @@ -1,4 +1,6 @@ /* + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. + * * See file CREDITS for list of people who contributed to this * project. * @@ -29,8 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_PCI - static struct pci_region pci1_regions[] = { { bus_start: CONFIG_SYS_PCI1_MEM_BASE, @@ -207,5 +207,3 @@ void pci_init_board(void) printf("PCI: Agent mode enabled\n"); } #endif /* CONFIG_PCISLAVE */ - -#endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc8349itx/Makefile b/board/freescale/mpc8349itx/Makefile index c81ba66..2fed9f0 100644 --- a/board/freescale/mpc8349itx/Makefile +++ b/board/freescale/mpc8349itx/Makefile @@ -24,8 +24,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c index 8da7117..38baff3 100644 --- a/board/freescale/mpc8349itx/pci.c +++ b/board/freescale/mpc8349itx/pci.c @@ -1,5 +1,5 @@ /* - * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -22,91 +22,70 @@ #include <common.h> -#ifdef CONFIG_PCI - #include <asm/mmu.h> -#include <asm/global_data.h> +#include <asm/io.h> +#include <mpc83xx.h> #include <pci.h> -#include <asm/mpc8349_pci.h> #include <i2c.h> -#if defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#include <fdt_support.h> -#endif +#include <asm/fsl_i2c.h> DECLARE_GLOBAL_DATA_PTR; -/* System RAM mapped to PCI space */ -#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc8349itx_config_table[] = { +static struct pci_region pci1_regions[] = { + { + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, + flags: PCI_REGION_IO + }, { - PCI_ANY_ID, - PCI_ANY_ID, - PCI_ANY_ID, - PCI_ANY_ID, - PCI_IDSEL_NUMBER, - PCI_ANY_ID, - pci_cfgfunc_config_device, - { - PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} - }, - {} + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, }; -#endif -static struct pci_controller pci_hose[] = { +#ifdef CONFIG_MPC83XX_PCI2 +static struct pci_region pci2_regions[] = { { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc8349itx_config_table, -#endif - }, + bus_start: CONFIG_SYS_PCI2_MEM_BASE, + phys_start: CONFIG_SYS_PCI2_MEM_PHYS, + size: CONFIG_SYS_PCI2_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc8349itx_config_table, -#endif - } + bus_start: CONFIG_SYS_PCI2_IO_BASE, + phys_start: CONFIG_SYS_PCI2_IO_PHYS, + size: CONFIG_SYS_PCI2_IO_SIZE, + flags: PCI_REGION_IO + }, + { + bus_start: CONFIG_SYS_PCI2_MMIO_BASE, + phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, + size: CONFIG_SYS_PCI2_MMIO_SIZE, + flags: PCI_REGION_MEM + }, }; +#endif -/************************************************************************** - * pci_init_board() - * - * NOTICE: PCI2 is not currently supported - * - */ void pci_init_board(void) { - volatile immap_t *immr; - volatile clk83xx_t *clk; - volatile law83xx_t *pci_law; - volatile pot83xx_t *pci_pot; - volatile pcictrl83xx_t *pci_ctrl; - volatile pciconf83xx_t *pci_conf; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; +#ifndef CONFIG_MPC83XX_PCI2 + struct pci_region *reg[] = { pci1_regions }; +#else + struct pci_region *reg[] = { pci1_regions, pci2_regions }; +#endif u8 reg8; - u16 reg16; - u32 reg32; - u32 dev; - struct pci_controller *hose; - - immr = (immap_t *) CONFIG_SYS_IMMR; - clk = (clk83xx_t *) & immr->clk; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; - - hose = &pci_hose[0]; - - /* - * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode - */ - - reg32 = clk->occr; - udelay(2000); #ifdef CONFIG_HARD_I2C i2c_set_bus_num(1); @@ -123,250 +102,20 @@ void pci_init_board(void) #else clk->occr = 0xff000000; /* 66 MHz PCI */ #endif - - udelay(2000); - - /* - * Release PCI RST Output signal - */ - pci_ctrl[0].gcr = 0; - udelay(2000); - pci_ctrl[0].gcr = 1; - -#ifdef CONFIG_MPC83XX_PCI2 - pci_ctrl[1].gcr = 0; udelay(2000); - pci_ctrl[1].gcr = 1; -#endif - - /* We need to wait at least a 1sec based on PCI specs */ - { - int i; - for (i = 0; i < 1000; i++) - udelay(1000); - } - - /* - * Configure PCI Local Access Windows - */ + /* Configure PCI Local Access Windows */ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M; - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI1 mem space - prefetch */ - pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M; - - /* PCI1 IO space */ - pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M; - - /* PCI1 mmio - non-prefetch mem space */ - pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M; - - /* - * Configure PCI Inbound Translation Windows - */ - - /* we need RAM mapped to PCI space for the devices to - * access main memory */ - pci_ctrl[0].pitar1 = 0x0; - pci_ctrl[0].pibar1 = 0x0; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | - PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); - - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose->regions + 0, - CONFIG_SYS_PCI1_MEM_BASE, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CONFIG_SYS_PCI1_MMIO_BASE, - CONFIG_SYS_PCI1_MMIO_PHYS, CONFIG_SYS_PCI1_MMIO_SIZE, PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CONFIG_SYS_PCI1_IO_BASE, - CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose->regions + 3, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose->region_count = 4; - - pci_setup_indirect(hose, - (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304)); - - pci_register_hose(hose); - - /* - * Write to Command register - */ - reg16 = 0xff; - dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); - -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); - -#ifdef CONFIG_MPC83XX_PCI2 - hose = &pci_hose[1]; - - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI2 mem space - prefetch */ - pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M; - - /* PCI2 IO space */ - pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M; - - /* PCI2 mmio - non-prefetch mem space */ - pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M; - - /* - * Configure PCI Inbound Translation Windows - */ - - /* we need RAM mapped to PCI space for the devices to - * access main memory */ - pci_ctrl[1].pitar1 = 0x0; - pci_ctrl[1].pibar1 = 0x0; - pci_ctrl[1].piebar1 = 0x0; - pci_ctrl[1].piwar1 = - PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | - (__ilog2(gd->ram_size) - 1); - - hose->first_busno = pci_hose[0].last_busno + 1; - hose->last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose->regions + 0, - CONFIG_SYS_PCI2_MEM_BASE, - CONFIG_SYS_PCI2_MEM_PHYS, - CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CONFIG_SYS_PCI2_MMIO_BASE, - CONFIG_SYS_PCI2_MMIO_PHYS, CONFIG_SYS_PCI2_MMIO_SIZE, PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CONFIG_SYS_PCI2_IO_BASE, - CONFIG_SYS_PCI2_IO_PHYS, CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose->regions + 3, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose->region_count = 4; - - pci_setup_indirect(hose, - (CONFIG_SYS_IMMR + 0x8380), (CONFIG_SYS_IMMR + 0x8384)); - - pci_register_hose(hose); - - /* - * Write to Command register - */ - reg16 = 0xff; - dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); - - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); -#endif -} - -#if defined(CONFIG_OF_LIBFDT) -void ft_pci_setup(void *blob, bd_t *bd) -{ - int nodeoffset; - int tmp[2]; - const char *path; - - nodeoffset = fdt_path_offset(blob, "/aliases"); - if (nodeoffset >= 0) { - path = fdt_getprop(blob, nodeoffset, "pci0", NULL); - if (path) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - do_fixup_by_path(blob, path, "bus-range", - &tmp, sizeof(tmp), 1); - - tmp[0] = cpu_to_be32(gd->pci_clk); - do_fixup_by_path(blob, path, "clock-frequency", - &tmp, sizeof(tmp[0]), 1); - } -#ifdef CONFIG_MPC83XX_PCI2 - path = fdt_getprop(blob, nodeoffset, "pci1", NULL); - if (path) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - do_fixup_by_path(blob, path, "bus-range", - &tmp, sizeof(tmp), 1); + udelay(2000); - tmp[0] = cpu_to_be32(gd->pci_clk); - do_fixup_by_path(blob, path, "clock-frequency", - &tmp, sizeof(tmp[0]), 1); - } +#ifndef CONFIG_MPC83XX_PCI2 + mpc83xx_pci_init(1, reg, 0); +#else + mpc83xx_pci_init(2, reg, 0); #endif - } } -#endif /* CONFIG_OF_LIBFDT */ -#endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc8360emds/Makefile b/board/freescale/mpc8360emds/Makefile index a97116c..c34905c 100644 --- a/board/freescale/mpc8360emds/Makefile +++ b/board/freescale/mpc8360emds/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c index 7ac35dc..04a802b 100644 --- a/board/freescale/mpc8360emds/pci.c +++ b/board/freescale/mpc8360emds/pci.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -13,65 +13,79 @@ /* * PCI Configuration space access support for MPC83xx PCI Bridge */ + #include <asm/mmu.h> #include <asm/io.h> #include <common.h> +#include <mpc83xx.h> #include <pci.h> #include <i2c.h> -#if defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#include <fdt_support.h> -#endif - #include <asm/fsl_i2c.h> +#include "../common/pq-mds-pib.h" DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_PCI) -#define PCI_FUNCTION_CONFIG 0x44 -#define PCI_FUNCTION_CFG_LOCK 0x20 +static struct pci_region pci1_regions[] = { + { + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, + flags: PCI_REGION_IO + }, + { + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, +}; -/* - * Initialize PCI Devices, report devices found - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc83xxemds_config_table[] = { +#ifdef CONFIG_MPC83XX_PCI2 +static struct pci_region pci2_regions[] = { { - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - pci_cfgfunc_config_device, - {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} - }, - {} -} -#endif -static struct pci_controller hose[] = { + bus_start: CONFIG_SYS_PCI2_MEM_BASE, + phys_start: CONFIG_SYS_PCI2_MEM_PHYS, + size: CONFIG_SYS_PCI2_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc83xxemds_config_table, -#endif - }, + bus_start: CONFIG_SYS_PCI2_IO_BASE, + phys_start: CONFIG_SYS_PCI2_IO_PHYS, + size: CONFIG_SYS_PCI2_IO_SIZE, + flags: PCI_REGION_IO + }, + { + bus_start: CONFIG_SYS_PCI2_MMIO_BASE, + phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, + size: CONFIG_SYS_PCI2_MMIO_SIZE, + flags: PCI_REGION_MEM + }, }; +#endif -/********************************************************************** - * pci_init_board() - *********************************************************************/ void pci_init_board(void) #ifdef CONFIG_PCISLAVE { - u16 reg16; - volatile immap_t *immr; - volatile law83xx_t *pci_law; - volatile pot83xx_t *pci_pot; - volatile pcictrl83xx_t *pci_ctrl; - volatile pciconf83xx_t *pci_conf; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0]; + struct pci_region *reg[] = { pci1_regions }; + + /* Configure PCI Local Access Windows */ + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; + + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; + + mpc83xx_pci_init(1, reg, 0); - immr = (immap_t *) CONFIG_SYS_IMMR; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; /* * Configure PCI Inbound Translation Windows */ @@ -90,61 +104,24 @@ void pci_init_board(void) pci_ctrl[0].piebar2 = 0x0; pci_ctrl[0].piwar2 &= ~PIWAR_EN; - hose[0].first_busno = 0; - hose[0].last_busno = 0xff; - pci_setup_indirect(&hose[0], - (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304)); - reg16 = 0xff; - - pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_STATUS, 0xffff); - pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), - PCI_LATENCY_TIMER, 0x80); - - /* - * Unlock configuration lock in PCI function configuration register. - */ - pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_FUNCTION_CONFIG, ®16); - reg16 &= ~(PCI_FUNCTION_CFG_LOCK); - pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_FUNCTION_CONFIG, reg16); - - printf("Enabled PCI 32bit Agent Mode\n"); + /* Unlock the configuration bit */ + mpc83xx_pcislave_unlock(0); + printf("PCI: Agent mode enabled\n"); } #else { - volatile immap_t *immr; - volatile clk83xx_t *clk; - volatile law83xx_t *pci_law; - volatile pot83xx_t *pci_pot; - volatile pcictrl83xx_t *pci_ctrl; - volatile pciconf83xx_t *pci_conf; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; +#ifndef CONFIG_MPC83XX_PCI2 + struct pci_region *reg[] = { pci1_regions }; +#else + struct pci_region *reg[] = { pci1_regions, pci2_regions }; +#endif - u16 reg16; - u32 val32; - u32 dev; + /* initialize the PCA9555PW IO expander on the PIB board */ + pib_init(); - immr = (immap_t *) CONFIG_SYS_IMMR; - clk = (clk83xx_t *) & immr->clk; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; - /* - * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode - */ - val32 = clk->occr; - udelay(2000); #if defined(PCI_66M) clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; printf("PCI clock is 66MHz\n"); @@ -158,129 +135,19 @@ void pci_init_board(void) #endif udelay(2000); - /* - * Configure PCI Local Access Windows - */ - pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; + /* Configure PCI Local Access Windows */ + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI mem space - prefetch */ - pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[0].pocmr = - POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI mmio - non-prefetch mem space */ - pci_pot[1].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI IO space */ - pci_pot[2].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - pci_ctrl[0].pitar1 = (CONFIG_SYS_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; - pci_ctrl[0].pibar1 = (CONFIG_SYS_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 = - PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | - PIWAR_IWS_2G; - - /* - * Release PCI RST Output signal - */ - udelay(2000); - pci_ctrl[0].gcr = 1; udelay(2000); - hose[0].first_busno = 0; - hose[0].last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose[0].regions + 0, - CONFIG_SYS_PCI_MEM_BASE, - CONFIG_SYS_PCI_MEM_PHYS, - CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose[0].regions + 1, - CONFIG_SYS_PCI_MMIO_BASE, - CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose[0].regions + 2, - CONFIG_SYS_PCI_IO_BASE, - CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose[0].regions + 3, - CONFIG_SYS_PCI_SLV_MEM_LOCAL, - CONFIG_SYS_PCI_SLV_MEM_BUS, - CONFIG_SYS_PCI_SLV_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose[0].region_count = 4; - - pci_setup_indirect(&hose[0], - (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304)); - - pci_register_hose(hose); - - /* - * Write command register - */ - reg16 = 0xff; - dev = PCI_BDF(0, 0, 0); - pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); - - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); +#ifndef CONFIG_MPC83XX_PCI2 + mpc83xx_pci_init(1, reg, 0); +#else + mpc83xx_pci_init(2, reg, 0); +#endif } #endif /* CONFIG_PCISLAVE */ - -#if defined(CONFIG_OF_LIBFDT) -void ft_pci_setup(void *blob, bd_t *bd) -{ - int nodeoffset; - int tmp[2]; - const char *path; - - nodeoffset = fdt_path_offset(blob, "/aliases"); - if (nodeoffset >= 0) { - path = fdt_getprop(blob, nodeoffset, "pci0", NULL); - if (path) { - tmp[0] = cpu_to_be32(hose[0].first_busno); - tmp[1] = cpu_to_be32(hose[0].last_busno); - do_fixup_by_path(blob, path, "bus-range", - &tmp, sizeof(tmp), 1); - - tmp[0] = cpu_to_be32(gd->pci_clk); - do_fixup_by_path(blob, path, "clock-frequency", - &tmp, sizeof(tmp[0]), 1); - } - } -} -#endif /* CONFIG_OF_LIBFDT */ -#endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc837xemds/Makefile b/board/freescale/mpc837xemds/Makefile index a97116c..c34905c 100644 --- a/board/freescale/mpc837xemds/Makefile +++ b/board/freescale/mpc837xemds/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c index 29de2e7..6b7b8b2 100644 --- a/board/freescale/mpc837xemds/pci.c +++ b/board/freescale/mpc837xemds/pci.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -20,7 +20,6 @@ #include <asm/fsl_i2c.h> #include <asm/fsl_serdes.h> -#if defined(CONFIG_PCI) static struct pci_region pci_regions[] = { { bus_start: CONFIG_SYS_PCI_MEM_BASE, @@ -152,4 +151,3 @@ void ft_pcie_fixup(void *blob, bd_t *bd) do_fixup_by_path(blob, "pci2", "status", status, strlen(status) + 1, 1); } -#endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc837xerdb/Makefile b/board/freescale/mpc837xerdb/Makefile index a97116c..c34905c 100644 --- a/board/freescale/mpc837xerdb/Makefile +++ b/board/freescale/mpc837xerdb/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc837xerdb/pci.c b/board/freescale/mpc837xerdb/pci.c index 83e89cf..97ad227 100644 --- a/board/freescale/mpc837xerdb/pci.c +++ b/board/freescale/mpc837xerdb/pci.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -15,7 +15,6 @@ #include <pci.h> #include <asm/io.h> -#if defined(CONFIG_PCI) static struct pci_region pci_regions[] = { { bus_start: CONFIG_SYS_PCI_MEM_BASE, @@ -113,4 +112,3 @@ void pci_init_board(void) mpc83xx_pcie_init(2, pcie_reg, 0); } -#endif /* CONFIG_PCI */ diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c index 7985f7d..6ee44d6 100644 --- a/board/pcippc2/pcippc2.c +++ b/board/pcippc2/pcippc2.c @@ -147,10 +147,12 @@ void pci_init_board (void) cpc710_pci_enable_timeout (); } +#ifdef CONFIG_CMD_DOC void doc_init (void) { doc_probe (pcippc2_fpga1_phys + HW_FPGA1_DOC); } +#endif void pcippc2_cpci3264_init (void) { diff --git a/board/rbc823/rbc823.c b/board/rbc823/rbc823.c index b294906..e10d9f9 100644 --- a/board/rbc823/rbc823.c +++ b/board/rbc823/rbc823.c @@ -256,6 +256,7 @@ static long int dram_size (long int mamr_value, long int *base, return (get_ram_size (base, maxsize)); } +#ifdef CONFIG_CMD_DOC void doc_init (void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; @@ -267,3 +268,4 @@ void doc_init (void) doc_probe (FLASH_BASE1_PRELIM); } +#endif diff --git a/board/sbc8349/Makefile b/board/sbc8349/Makefile index fd6bb2d..454c226 100644 --- a/board/sbc8349/Makefile +++ b/board/sbc8349/Makefile @@ -24,8 +24,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/sbc8349/pci.c b/board/sbc8349/pci.c index ac5f30b..ca53356 100644 --- a/board/sbc8349/pci.c +++ b/board/sbc8349/pci.c @@ -1,6 +1,7 @@ /* * pci.c -- WindRiver SBC8349 PCI board support. * Copyright (c) 2006 Wind River Systems, Inc. + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. * * Based on MPC8349 PCI support but w/o PIB related code. * @@ -25,51 +26,37 @@ */ #include <asm/mmu.h> +#include <asm/io.h> #include <common.h> -#include <asm/global_data.h> +#include <mpc83xx.h> #include <pci.h> -#include <asm/mpc8349_pci.h> #include <i2c.h> -#if defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#include <fdt_support.h> -#endif +#include <asm/fsl_i2c.h> DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_PCI - -/* System RAM mapped to PCI space */ -#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc8349emds_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } +static struct pci_region pci1_regions[] = { + { + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, + flags: PCI_REGION_IO + }, + { + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM }, - {} -}; -#endif - -static struct pci_controller pci_hose[] = { - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc8349emds_config_table, -#endif - }, - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc8349emds_config_table, -#endif - } }; -/************************************************************************** +/* * pci_init_board() * * NOTICE: PCI2 is not supported. There is only one @@ -79,288 +66,23 @@ static struct pci_controller pci_hose[] = { void pci_init_board(void) { - volatile immap_t * immr; - volatile clk83xx_t * clk; - volatile law83xx_t * pci_law; - volatile pot83xx_t * pci_pot; - volatile pcictrl83xx_t * pci_ctrl; - volatile pciconf83xx_t * pci_conf; - u16 reg16; - u32 reg32; - u32 dev; - struct pci_controller * hose; - - immr = (immap_t *)CONFIG_SYS_IMMR; - clk = (clk83xx_t *)&immr->clk; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; - - hose = &pci_hose[0]; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + struct pci_region *reg[] = { pci1_regions }; - /* - * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode - */ - - reg32 = clk->occr; - udelay(2000); + /* Enable all 8 PCI_CLK_OUTPUTS */ clk->occr = 0xff000000; udelay(2000); - /* - * Release PCI RST Output signal - */ - pci_ctrl[0].gcr = 0; - udelay(2000); - pci_ctrl[0].gcr = 1; - -#ifdef CONFIG_MPC83XX_PCI2 - pci_ctrl[1].gcr = 0; - udelay(2000); - pci_ctrl[1].gcr = 1; -#endif - - /* We need to wait at least a 1sec based on PCI specs */ - { - int i; - - for (i = 0; i < 1000; ++i) - udelay (1000); - } - - /* - * Configure PCI Local Access Windows - */ + /* Configure PCI Local Access Windows */ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI1 mem space - prefetch */ - pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI1 IO space */ - pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); - - /* PCI1 mmio - non-prefetch mem space */ - pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - - /* we need RAM mapped to PCI space for the devices to - * access main memory */ - pci_ctrl[0].pitar1 = 0x0; - pci_ctrl[0].pibar1 = 0x0; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); - - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose->regions + 0, - CONFIG_SYS_PCI1_MEM_BASE, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM|PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CONFIG_SYS_PCI1_MMIO_BASE, - CONFIG_SYS_PCI1_MMIO_PHYS, - CONFIG_SYS_PCI1_MMIO_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CONFIG_SYS_PCI1_IO_BASE, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose->regions + 3, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - gd->ram_size, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose->region_count = 4; - - pci_setup_indirect(hose, - (CONFIG_SYS_IMMR+0x8300), - (CONFIG_SYS_IMMR+0x8304)); - - pci_register_hose(hose); - - /* - * Write to Command register - */ - reg16 = 0xff; - dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); - -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); - -#ifdef CONFIG_MPC83XX_PCI2 - hose = &pci_hose[1]; - - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI2 mem space - prefetch */ - pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI2 IO space */ - pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); - - /* PCI2 mmio - non-prefetch mem space */ - pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - - /* we need RAM mapped to PCI space for the devices to - * access main memory */ - pci_ctrl[1].pitar1 = 0x0; - pci_ctrl[1].pibar1 = 0x0; - pci_ctrl[1].piebar1 = 0x0; - pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); - - hose->first_busno = pci_hose[0].last_busno + 1; - hose->last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose->regions + 0, - CONFIG_SYS_PCI2_MEM_BASE, - CONFIG_SYS_PCI2_MEM_PHYS, - CONFIG_SYS_PCI2_MEM_SIZE, - PCI_REGION_MEM|PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CONFIG_SYS_PCI2_MMIO_BASE, - CONFIG_SYS_PCI2_MMIO_PHYS, - CONFIG_SYS_PCI2_MMIO_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CONFIG_SYS_PCI2_IO_BASE, - CONFIG_SYS_PCI2_IO_PHYS, - CONFIG_SYS_PCI2_IO_SIZE, - PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose->regions + 3, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - gd->ram_size, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose->region_count = 4; - - pci_setup_indirect(hose, - (CONFIG_SYS_IMMR+0x8380), - (CONFIG_SYS_IMMR+0x8384)); - - pci_register_hose(hose); - - /* - * Write to Command register - */ - reg16 = 0xff; - dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); - - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); -#endif - -} - -#if defined(CONFIG_OF_LIBFDT) -void ft_pci_setup(void *blob, bd_t *bd) -{ - int nodeoffset; - int tmp[2]; - const char *path; - - nodeoffset = fdt_path_offset(blob, "/aliases"); - if (nodeoffset >= 0) { - path = fdt_getprop(blob, nodeoffset, "pci0", NULL); - if (path) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - do_fixup_by_path(blob, path, "bus-range", - &tmp, sizeof(tmp), 1); - - tmp[0] = cpu_to_be32(gd->pci_clk); - do_fixup_by_path(blob, path, "clock-frequency", - &tmp, sizeof(tmp[0]), 1); - } -#ifdef CONFIG_MPC83XX_PCI2 - path = fdt_getprop(blob, nodeoffset, "pci1", NULL); - if (path) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - do_fixup_by_path(blob, path, "bus-range", - &tmp, sizeof(tmp), 1); + udelay(2000); - tmp[0] = cpu_to_be32(gd->pci_clk); - do_fixup_by_path(blob, path, "clock-frequency", - &tmp, sizeof(tmp[0]), 1); - } -#endif - } + mpc83xx_pci_init(1, reg, 0); } -#endif /* CONFIG_OF_LIBFDT */ -#endif /* CONFIG_PCI */ diff --git a/board/tqc/tqm834x/Makefile b/board/tqc/tqm834x/Makefile index 8889726..011e631 100644 --- a/board/tqc/tqm834x/Makefile +++ b/board/tqc/tqm834x/Makefile @@ -27,8 +27,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o pci.o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c index 6c113e3..fcf4379 100644 --- a/board/tqc/tqm834x/pci.c +++ b/board/tqc/tqm834x/pci.c @@ -1,6 +1,7 @@ /* * (C) Copyright 2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -23,45 +24,37 @@ */ #include <asm/mmu.h> +#include <asm/io.h> #include <common.h> -#include <asm/global_data.h> +#include <mpc83xx.h> #include <pci.h> -#include <asm/mpc8349_pci.h> -#if defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#include <fdt_support.h> -#endif +#include <i2c.h> +#include <asm/fsl_i2c.h> DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_PCI - -/* System RAM mapped to PCI space */ -#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_tqm834x_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } +static struct pci_region pci1_regions[] = { + { + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, + flags: PCI_REGION_IO + }, + { + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM }, - {} -}; -#endif - -static struct pci_controller pci1_hose = { -#ifndef CONFIG_PCI_PNP - config_table:pci_tqm834x_config_table, -#endif }; - -/************************************************************************** +/* * pci_init_board() * * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since @@ -76,30 +69,15 @@ static struct pci_controller pci1_hose = { void pci_init_board(void) { - volatile immap_t * immr; - volatile clk83xx_t * clk; - volatile law83xx_t * pci_law; - volatile pot83xx_t * pci_pot; - volatile pcictrl83xx_t * pci_ctrl; - volatile pciconf83xx_t * pci_conf; - u16 reg16; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + struct pci_region *reg[] = { pci1_regions }; u32 reg32; - struct pci_controller * hose; - - immr = (immap_t *)CONFIG_SYS_IMMR; - clk = (clk83xx_t *)&immr->clk; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; - - hose = &pci1_hose; /* * Configure PCI controller and PCI_CLK_OUTPUT - */ - - /* + * * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one * line actually used for clocking all external PCI devices in TQM83xx. * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for @@ -125,141 +103,14 @@ pci_init_board(void) clk->occr = reg32; udelay(2000); - /* - * Release PCI RST Output signal - */ - pci_ctrl[0].gcr = 0; - udelay(2000); - pci_ctrl[0].gcr = 1; - udelay(2000); - - /* - * Configure PCI Local Access Windows - */ + /* Configure PCI Local Access Windows */ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI1 mem space */ - pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK); - - /* PCI1 IO space */ - pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - - /* we need RAM mapped to PCI space for the devices to - * access main memory */ - pci_ctrl[0].pitar1 = 0x0; - pci_ctrl[0].pibar1 = 0x0; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_256M; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* PCI memory space */ - pci_set_region(hose->regions + 0, - CONFIG_SYS_PCI1_MEM_BASE, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 1, - CONFIG_SYS_PCI1_IO_BASE, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose->regions + 2, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - CONFIG_PCI_SYS_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose->region_count = 3; - - pci_setup_indirect(hose, - (CONFIG_SYS_IMMR+0x8300), - (CONFIG_SYS_IMMR+0x8304)); - - pci_register_hose(hose); - - /* - * Write to Command register - */ - reg16 = 0xff; - pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND, - ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, - reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS, - 0xffff); - pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, - 0x80); - -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); -} - -#if defined(CONFIG_OF_LIBFDT) -void ft_pci_setup(void *blob, bd_t *bd) -{ - int nodeoffset; - int tmp[2]; - const char *path; - - nodeoffset = fdt_path_offset(blob, "/aliases"); - if (nodeoffset >= 0) { - path = fdt_getprop(blob, nodeoffset, "pci0", NULL); - if (path) { - tmp[0] = cpu_to_be32(pci1_hose.first_busno); - tmp[1] = cpu_to_be32(pci1_hose.last_busno); - do_fixup_by_path(blob, path, "bus-range", - &tmp, sizeof(tmp), 1); - - tmp[0] = cpu_to_be32(gd->pci_clk); - do_fixup_by_path(blob, path, "clock-frequency", - &tmp, sizeof(tmp[0]), 1); - } -#ifdef CONFIG_MPC83XX_PCI2 - path = fdt_getprop(blob, nodeoffset, "pci1", NULL); - if (path) { - tmp[0] = cpu_to_be32(pci2_hose.first_busno); - tmp[1] = cpu_to_be32(pci2_hose.last_busno); - do_fixup_by_path(blob, path, "bus-range", - &tmp, sizeof(tmp), 1); + udelay(2000); - tmp[0] = cpu_to_be32(gd->pci_clk); - do_fixup_by_path(blob, path, "clock-frequency", - &tmp, sizeof(tmp[0]), 1); - } -#endif - } + mpc83xx_pci_init(1, reg, 0); } -#endif /* CONFIG_OF_LIBFDT */ -#endif /* CONFIG_PCI */ diff --git a/common/Makefile b/common/Makefile index 89f1c88..3781738 100644 --- a/common/Makefile +++ b/common/Makefile @@ -135,6 +135,7 @@ COBJS-$(CONFIG_CMD_SPI) += cmd_spi.o COBJS-$(CONFIG_CMD_SPIBOOTLDR) += cmd_spibootldr.o COBJS-$(CONFIG_CMD_STRINGS) += cmd_strings.o COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o +COBJS-$(CONFIG_CMD_TSI148) += cmd_tsi148.o COBJS-$(CONFIG_CMD_UBI) += cmd_ubi.o COBJS-$(CONFIG_CMD_UBIFS) += cmd_ubifs.o COBJS-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o diff --git a/common/cmd_flash.c b/common/cmd_flash.c index bc651fa..3773412 100644 --- a/common/cmd_flash.c +++ b/common/cmd_flash.c @@ -467,8 +467,10 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) flash_info_t *info; ulong bank; int i, n, sect_first, sect_last; - ulong addr_first, addr_last; #endif /* CONFIG_SYS_NO_FLASH */ +#if !defined(CONFIG_SYS_NO_FLASH) || defined(CONFIG_HAS_DATAFLASH) + ulong addr_first, addr_last; +#endif #if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_CMD_MTDPARTS) struct mtd_device *dev; struct part_info *part; diff --git a/common/cmd_tsi148.c b/common/cmd_tsi148.c new file mode 100644 index 0000000..222938c --- /dev/null +++ b/common/cmd_tsi148.c @@ -0,0 +1,488 @@ +/* + * (C) Copyright 2009 Reinhard Arlt, reinhard.arlt@esd-electronics.com + * + * base on universe.h by + * + * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define DEBUG + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <asm/io.h> +#include <pci.h> + +#include <tsi148.h> + +#define PCI_VENDOR PCI_VENDOR_ID_TUNDRA +#define PCI_DEVICE PCI_DEVICE_ID_TUNDRA_TSI148 + +typedef struct _TSI148_DEV TSI148_DEV; + +struct _TSI148_DEV { + int bus; + pci_dev_t busdevfn; + TSI148 *uregs; + unsigned int pci_bs; +}; + +static TSI148_DEV *dev; + +/* + * Most of the TSI148 register are BIGENDIAN + * This is the reason for the __raw_writel(htonl(x), x) usage! + */ + +int tsi148_init(void) +{ + int j, result, lastError = 0; + pci_dev_t busdevfn; + unsigned int val; + + busdevfn = pci_find_device(PCI_VENDOR, PCI_DEVICE, 0); + if (busdevfn == -1) { + puts("Tsi148: No Tundra Tsi148 found!\n"); + return -1; + } + + /* Lets turn Latency off */ + pci_write_config_dword(busdevfn, 0x0c, 0); + + dev = malloc(sizeof(*dev)); + if (NULL == dev) { + puts("Tsi148: No memory!\n"); + result = -1; + goto break_20; + } + + memset(dev, 0, sizeof(*dev)); + dev->busdevfn = busdevfn; + + pci_read_config_dword(busdevfn, PCI_BASE_ADDRESS_0, &val); + val &= ~0xf; + dev->uregs = (TSI148 *)val; + + debug("Tsi148: Base : %p\n", dev->uregs); + + /* check mapping */ + debug("Tsi148: Read via mapping, PCI_ID = %08X\n", readl(&dev->uregs->pci_id)); + if (((PCI_DEVICE << 16) | PCI_VENDOR) != readl(&dev->uregs->pci_id)) { + printf("Tsi148: Cannot read PCI-ID via Mapping: %08x\n", + readl(&dev->uregs->pci_id)); + result = -1; + goto break_30; + } + + debug("Tsi148: PCI_BS = %08X\n", readl(&dev->uregs->pci_mbarl)); + + dev->pci_bs = readl(&dev->uregs->pci_mbarl); + + /* turn off windows */ + for (j = 0; j < 8; j++) { + __raw_writel(htonl(0x00000000), &dev->uregs->outbound[j].otat); + __raw_writel(htonl(0x00000000), &dev->uregs->inbound[j].itat); + } + + /* Tsi148 VME timeout etc */ + __raw_writel(htonl(0x00000084), &dev->uregs->vctrl); + + if ((__raw_readl(&dev->uregs->vstat) & 0x00000100) != 0) + debug("Tsi148: System Controller!\n"); + else + debug("Tsi148: Not System Controller!\n"); + + /* + * Lets turn off interrupts + */ + /* Disable interrupts in Tsi148 first */ + __raw_writel(htonl(0x00000000), &dev->uregs->inten); + /* Disable interrupt out */ + __raw_writel(htonl(0x00000000), &dev->uregs->inteo); + eieio(); + /* Reset all IRQ's */ + __raw_writel(htonl(0x03ff3f00), &dev->uregs->intc); + /* Map all ints to 0 */ + __raw_writel(htonl(0x00000000), &dev->uregs->intm1); + __raw_writel(htonl(0x00000000), &dev->uregs->intm2); + eieio(); + + val = __raw_readl(&dev->uregs->vstat); + val &= ~(0x00004000); + __raw_writel(val, &dev->uregs->vstat); + eieio(); + + debug("Tsi148: register struct size %08x\n", sizeof(TSI148)); + + return 0; + + break_30: + free(dev); + dev = NULL; + break_20: + lastError = result; + + return result; +} + +/* + * Create pci slave window (access: pci -> vme) + */ +int tsi148_pci_slave_window(unsigned int pciAddr, unsigned int vmeAddr, int size, int vam, int vdw) +{ + int result, i; + unsigned int ctl = 0; + + if (NULL == dev) { + result = -1; + goto exit_10; + } + + for (i = 0; i < 8; i++) { + if (0x00000000 == readl(&dev->uregs->outbound[i].otat)) + break; + } + + if (i > 7) { + printf("Tsi148: No Image available\n"); + result = -1; + goto exit_10; + } + + debug("Tsi148: Using image %d\n", i); + + printf("Tsi148: Pci addr %08x\n", pciAddr); + + + __raw_writel(htonl(pciAddr) , &dev->uregs->outbound[i].otsal); + __raw_writel(0x00000000 , &dev->uregs->outbound[i].otsau); + __raw_writel(htonl(pciAddr + size), &dev->uregs->outbound[i].oteal); + __raw_writel(0x00000000 , &dev->uregs->outbound[i].oteau); + __raw_writel(htonl(vmeAddr - pciAddr), &dev->uregs->outbound[i].otofl); + __raw_writel(0x00000000 , &dev->uregs->outbound[i].otofu); + + switch (vam & VME_AM_Axx) { + case VME_AM_A16: + ctl = 0x00000000; + break; + case VME_AM_A24: + ctl = 0x00000001; + break; + case VME_AM_A32: + ctl = 0x00000002; + break; + } + + switch (vam & VME_AM_Mxx) { + case VME_AM_DATA: + ctl |= 0x00000000; + break; + case VME_AM_PROG: + ctl |= 0x00000010; + break; + } + + if (vam & VME_AM_SUP) + ctl |= 0x00000020; + + switch (vdw & VME_FLAG_Dxx) { + case VME_FLAG_D16: + ctl |= 0x00000000; + break; + case VME_FLAG_D32: + ctl |= 0x00000040; + break; + } + + ctl |= 0x80040000; /* enable, no prefetch */ + + __raw_writel(htonl(ctl), &dev->uregs->outbound[i].otat); + + debug("Tsi148: window-addr =%p\n", + &dev->uregs->outbound[i].otsau); + debug("Tsi148: pci slave window[%d] attr =%08x\n", + i, ntohl(__raw_readl(&dev->uregs->outbound[i].otat))); + debug("Tsi148: pci slave window[%d] start =%08x\n", + i, ntohl(__raw_readl(&dev->uregs->outbound[i].otsal))); + debug("Tsi148: pci slave window[%d] end =%08x\n", + i, ntohl(__raw_readl(&dev->uregs->outbound[i].oteal))); + debug("Tsi148: pci slave window[%d] offset=%08x\n", + i, ntohl(__raw_readl(&dev->uregs->outbound[i].otofl))); + + return 0; + + exit_10: + return -result; +} + +unsigned int tsi148_eval_vam(int vam) +{ + unsigned int ctl = 0; + + switch (vam & VME_AM_Axx) { + case VME_AM_A16: + ctl = 0x00000000; + break; + case VME_AM_A24: + ctl = 0x00000010; + break; + case VME_AM_A32: + ctl = 0x00000020; + break; + } + switch (vam & VME_AM_Mxx) { + case VME_AM_DATA: + ctl |= 0x00000001; + break; + case VME_AM_PROG: + ctl |= 0x00000002; + break; + case (VME_AM_PROG | VME_AM_DATA): + ctl |= 0x00000003; + break; + } + + if (vam & VME_AM_SUP) + ctl |= 0x00000008; + if (vam & VME_AM_USR) + ctl |= 0x00000004; + + return ctl; +} + +/* + * Create vme slave window (access: vme -> pci) + */ +int tsi148_vme_slave_window(unsigned int vmeAddr, unsigned int pciAddr, int size, int vam) +{ + int result, i; + unsigned int ctl = 0; + + if (NULL == dev) { + result = -1; + goto exit_10; + } + + for (i = 0; i < 8; i++) { + if (0x00000000 == readl(&dev->uregs->inbound[i].itat)) + break; + } + + if (i > 7) { + printf("Tsi148: No Image available\n"); + result = -1; + goto exit_10; + } + + debug("Tsi148: Using image %d\n", i); + + __raw_writel(htonl(vmeAddr), &dev->uregs->inbound[i].itsal); + __raw_writel(0x00000000, &dev->uregs->inbound[i].itsau); + __raw_writel(htonl(vmeAddr + size), &dev->uregs->inbound[i].iteal); + __raw_writel(0x00000000, &dev->uregs->inbound[i].iteau); + __raw_writel(htonl(pciAddr - vmeAddr), &dev->uregs->inbound[i].itofl); + if (vmeAddr > pciAddr) + __raw_writel(0xffffffff, &dev->uregs->inbound[i].itofu); + else + __raw_writel(0x00000000, &dev->uregs->inbound[i].itofu); + + ctl = tsi148_eval_vam(vam); + ctl |= 0x80000000; /* enable */ + __raw_writel(htonl(ctl), &dev->uregs->inbound[i].itat); + + debug("Tsi148: window-addr =%p\n", + &dev->uregs->inbound[i].itsau); + debug("Tsi148: vme slave window[%d] attr =%08x\n", + i, ntohl(__raw_readl(&dev->uregs->inbound[i].itat))) ; + debug("Tsi148: vme slave window[%d] start =%08x\n", + i, ntohl(__raw_readl(&dev->uregs->inbound[i].itsal))); + debug("Tsi148: vme slave window[%d] end =%08x\n", + i, ntohl(__raw_readl(&dev->uregs->inbound[i].iteal))); + debug("Tsi148: vme slave window[%d] offset=%08x\n", + i, ntohl(__raw_readl(&dev->uregs->inbound[i].itofl))); + + return 0; + + exit_10: + return -result; +} + +/* + * Create vme slave window (access: vme -> gcsr) + */ +int tsi148_vme_gcsr_window(unsigned int vmeAddr, int vam) +{ + int result; + unsigned int ctl; + + result = 0; + + if (NULL == dev) { + result = 1; + } else { + __raw_writel(htonl(vmeAddr), &dev->uregs->gbal); + __raw_writel(0x00000000, &dev->uregs->gbau); + + ctl = tsi148_eval_vam(vam); + ctl |= 0x00000080; /* enable */ + __raw_writel(htonl(ctl), &dev->uregs->gcsrat); + } + + return result; +} + +/* + * Create vme slave window (access: vme -> crcsr) + */ +int tsi148_vme_crcsr_window(unsigned int vmeAddr) +{ + int result; + unsigned int ctl; + + result = 0; + + if (NULL == dev) { + result = 1; + } else { + __raw_writel(htonl(vmeAddr), &dev->uregs->crol); + __raw_writel(0x00000000, &dev->uregs->crou); + + ctl = 0x00000080; /* enable */ + __raw_writel(htonl(ctl), &dev->uregs->crat); + } + + return result; +} + + +/* + * Create vme slave window (access: vme -> crg) + */ +int tsi148_vme_crg_window(unsigned int vmeAddr, int vam) +{ + int result; + unsigned int ctl; + + result = 0; + + if (NULL == dev) { + result = 1; + } else { + __raw_writel(htonl(vmeAddr), &dev->uregs->cbal); + __raw_writel(0x00000000, &dev->uregs->cbau); + + ctl = tsi148_eval_vam(vam); + ctl |= 0x00000080; /* enable */ + __raw_writel(htonl(ctl), &dev->uregs->crgat); + } + + return result; +} + +/* + * Tundra Tsi148 configuration + */ +int do_tsi148(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr1 = 0, addr2 = 0, size = 0, vam = 0, vdw = 0; + char cmd = 'x'; + + /* get parameter */ + if (argc > 1) + cmd = argv[1][0]; + if (argc > 2) + addr1 = simple_strtoul(argv[2], NULL, 16); + if (argc > 3) + addr2 = simple_strtoul(argv[3], NULL, 16); + if (argc > 4) + size = simple_strtoul(argv[4], NULL, 16); + if (argc > 5) + vam = simple_strtoul(argv[5], NULL, 16); + if (argc > 6) + vdw = simple_strtoul(argv[7], NULL, 16); + + switch (cmd) { + case 'c': + if (strcmp(argv[1], "crg") == 0) { + vam = addr2; + printf("Tsi148: Configuring VME CRG Window (VME->CRG):\n"); + printf(" vme=%08lx vam=%02lx\n", addr1, vam); + tsi148_vme_crg_window(addr1, vam); + } else { + printf("Tsi148: Configuring VME CR/CSR Window (VME->CR/CSR):\n"); + printf(" pci=%08lx\n", addr1); + tsi148_vme_crcsr_window(addr1); + } + break; + case 'i': /* init */ + tsi148_init(); + break; + case 'g': + vam = addr2; + printf("Tsi148: Configuring VME GCSR Window (VME->GCSR):\n"); + printf(" vme=%08lx vam=%02lx\n", addr1, vam); + tsi148_vme_gcsr_window(addr1, vam); + break; + case 'v': /* vme */ + printf("Tsi148: Configuring VME Slave Window (VME->PCI):\n"); + printf(" vme=%08lx pci=%08lx size=%08lx vam=%02lx\n", + addr1, addr2, size, vam); + tsi148_vme_slave_window(addr1, addr2, size, vam); + break; + case 'p': /* pci */ + printf("Tsi148: Configuring PCI Slave Window (PCI->VME):\n"); + printf(" pci=%08lx vme=%08lx size=%08lx vam=%02lx vdw=%02lx\n", + addr1, addr2, size, vam, vdw); + tsi148_pci_slave_window(addr1, addr2, size, vam, vdw); + break; + default: + printf("Tsi148: Command %s not supported!\n", argv[1]); + } + + return 0; +} + +U_BOOT_CMD( + tsi148, 8, 1, do_tsi148, + "tsi148 - initialize and configure Turndra Tsi148\n", + "init\n" + " - initialize tsi148\n" + "tsi148 vme [vme_addr] [pci_addr] [size] [vam]\n" + " - create vme slave window (access: vme->pci)\n" + "tsi148 pci [pci_addr] [vme_addr] [size] [vam] [vdw]\n" + " - create pci slave window (access: pci->vme)\n" + "tsi148 crg [vme_addr] [vam]\n" + " - create vme slave window: (access vme->CRG\n" + "tsi148 crcsr [pci_addr]\n" + " - create vme slave window: (access vme->CR/CSR\n" + "tsi148 gcsr [vme_addr] [vam]\n" + " - create vme slave window: (access vme->GCSR\n" + " [vam] = VMEbus Address-Modifier: 01 -> A16 Address Space\n" + " 02 -> A24 Address Space\n" + " 03 -> A32 Address Space\n" + " 04 -> Usr AM Code\n" + " 08 -> Supervisor AM Code\n" + " 10 -> Data AM Code\n" + " 20 -> Program AM Code\n" + " [vdw] = VMEbus Maximum Datawidth: 02 -> D16 Data Width\n" + " 03 -> D32 Data Width\n" +); diff --git a/common/xyzModem.c b/common/xyzModem.c index a209dfa..7a46805 100644 --- a/common/xyzModem.c +++ b/common/xyzModem.c @@ -544,7 +544,7 @@ xyzModem_stream_open (connection_info_t * info, int *err) xyzModem_CHAR_TIMEOUT); #else /* TODO: CHECK ! */ - int dummy; + int dummy = 0; xyz.__chan = &dummy; #endif xyz.len = 0; @@ -196,7 +196,7 @@ endif ######################################################################### -export HPATH HOSTCC HOSTCFLAGS CROSS_COMPILE \ +export HOSTCC HOSTCFLAGS CROSS_COMPILE \ AS LD CC CPP AR NM STRIP OBJCOPY OBJDUMP MAKE export TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS diff --git a/drivers/block/Makefile b/drivers/block/Makefile index eccefc1..3f6ad5c 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -31,6 +31,7 @@ COBJS-$(CONFIG_FSL_SATA) += fsl_sata.o COBJS-$(CONFIG_IDE_SIL680) += sil680.o COBJS-$(CONFIG_LIBATA) += libata.o COBJS-$(CONFIG_PATA_BFIN) += pata_bfin.o +COBJS-$(CONFIG_SATA_DWC) += sata_dwc.o COBJS-$(CONFIG_SATA_SIL3114) += sata_sil3114.o COBJS-$(CONFIG_SCSI_AHCI) += ahci.o COBJS-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o diff --git a/drivers/block/sata_dwc.c b/drivers/block/sata_dwc.c new file mode 100644 index 0000000..b2b3804 --- /dev/null +++ b/drivers/block/sata_dwc.c @@ -0,0 +1,2110 @@ +/* + * sata_dwc.c + * + * Synopsys DesignWare Cores (DWC) SATA host driver + * + * Author: Mark Miesfeld <mmiesfeld@amcc.com> + * + * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de> + * Copyright 2008 DENX Software Engineering + * + * Based on versions provided by AMCC and Synopsys which are: + * Copyright 2006 Applied Micro Circuits Corporation + * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED + * + * This program is free software; you can redistribute + * it and/or modify it under the terms of the GNU + * General Public License as published by the + * Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. + * + */ +/* + * SATA support based on the chip canyonlands. + * + * 04-17-2009 + * The local version of this driver for the canyonlands board + * does not use interrupts but polls the chip instead. + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <malloc.h> +#include <ata.h> +#include <linux/ctype.h> + +#include "sata_dwc.h" + +#define DMA_NUM_CHANS 1 +#define DMA_NUM_CHAN_REGS 8 + +#define AHB_DMA_BRST_DFLT 16 + +struct dmareg { + u32 low; + u32 high; +}; + +struct dma_chan_regs { + struct dmareg sar; + struct dmareg dar; + struct dmareg llp; + struct dmareg ctl; + struct dmareg sstat; + struct dmareg dstat; + struct dmareg sstatar; + struct dmareg dstatar; + struct dmareg cfg; + struct dmareg sgr; + struct dmareg dsr; +}; + +struct dma_interrupt_regs { + struct dmareg tfr; + struct dmareg block; + struct dmareg srctran; + struct dmareg dsttran; + struct dmareg error; +}; + +struct ahb_dma_regs { + struct dma_chan_regs chan_regs[DMA_NUM_CHAN_REGS]; + struct dma_interrupt_regs interrupt_raw; + struct dma_interrupt_regs interrupt_status; + struct dma_interrupt_regs interrupt_mask; + struct dma_interrupt_regs interrupt_clear; + struct dmareg statusInt; + struct dmareg rq_srcreg; + struct dmareg rq_dstreg; + struct dmareg rq_sgl_srcreg; + struct dmareg rq_sgl_dstreg; + struct dmareg rq_lst_srcreg; + struct dmareg rq_lst_dstreg; + struct dmareg dma_cfg; + struct dmareg dma_chan_en; + struct dmareg dma_id; + struct dmareg dma_test; + struct dmareg res1; + struct dmareg res2; + /* DMA Comp Params + * Param 6 = dma_param[0], Param 5 = dma_param[1], + * Param 4 = dma_param[2] ... + */ + struct dmareg dma_params[6]; +}; + +#define DMA_EN 0x00000001 +#define DMA_DI 0x00000000 +#define DMA_CHANNEL(ch) (0x00000001 << (ch)) +#define DMA_ENABLE_CHAN(ch) ((0x00000001 << (ch)) | \ + ((0x000000001 << (ch)) << 8)) +#define DMA_DISABLE_CHAN(ch) (0x00000000 | \ + ((0x000000001 << (ch)) << 8)) + +#define SATA_DWC_MAX_PORTS 1 +#define SATA_DWC_SCR_OFFSET 0x24 +#define SATA_DWC_REG_OFFSET 0x64 + +struct sata_dwc_regs { + u32 fptagr; + u32 fpbor; + u32 fptcr; + u32 dmacr; + u32 dbtsr; + u32 intpr; + u32 intmr; + u32 errmr; + u32 llcr; + u32 phycr; + u32 physr; + u32 rxbistpd; + u32 rxbistpd1; + u32 rxbistpd2; + u32 txbistpd; + u32 txbistpd1; + u32 txbistpd2; + u32 bistcr; + u32 bistfctr; + u32 bistsr; + u32 bistdecr; + u32 res[15]; + u32 testr; + u32 versionr; + u32 idr; + u32 unimpl[192]; + u32 dmadr[256]; +}; + +#define SATA_DWC_TXFIFO_DEPTH 0x01FF +#define SATA_DWC_RXFIFO_DEPTH 0x01FF + +#define SATA_DWC_DBTSR_MWR(size) ((size / 4) & SATA_DWC_TXFIFO_DEPTH) +#define SATA_DWC_DBTSR_MRD(size) (((size / 4) & \ + SATA_DWC_RXFIFO_DEPTH) << 16) +#define SATA_DWC_INTPR_DMAT 0x00000001 +#define SATA_DWC_INTPR_NEWFP 0x00000002 +#define SATA_DWC_INTPR_PMABRT 0x00000004 +#define SATA_DWC_INTPR_ERR 0x00000008 +#define SATA_DWC_INTPR_NEWBIST 0x00000010 +#define SATA_DWC_INTPR_IPF 0x10000000 +#define SATA_DWC_INTMR_DMATM 0x00000001 +#define SATA_DWC_INTMR_NEWFPM 0x00000002 +#define SATA_DWC_INTMR_PMABRTM 0x00000004 +#define SATA_DWC_INTMR_ERRM 0x00000008 +#define SATA_DWC_INTMR_NEWBISTM 0x00000010 + +#define SATA_DWC_DMACR_TMOD_TXCHEN 0x00000004 +#define SATA_DWC_DMACR_TXRXCH_CLEAR SATA_DWC_DMACR_TMOD_TXCHEN + +#define SATA_DWC_QCMD_MAX 32 + +#define SATA_DWC_SERROR_ERR_BITS 0x0FFF0F03 + +#define HSDEVP_FROM_AP(ap) (struct sata_dwc_device_port*) \ + (ap)->private_data + +struct sata_dwc_device { + struct device *dev; + struct ata_probe_ent *pe; + struct ata_host *host; + u8 *reg_base; + struct sata_dwc_regs *sata_dwc_regs; + int irq_dma; +}; + +struct sata_dwc_device_port { + struct sata_dwc_device *hsdev; + int cmd_issued[SATA_DWC_QCMD_MAX]; + u32 dma_chan[SATA_DWC_QCMD_MAX]; + int dma_pending[SATA_DWC_QCMD_MAX]; +}; + +enum { + SATA_DWC_CMD_ISSUED_NOT = 0, + SATA_DWC_CMD_ISSUED_PEND = 1, + SATA_DWC_CMD_ISSUED_EXEC = 2, + SATA_DWC_CMD_ISSUED_NODATA = 3, + + SATA_DWC_DMA_PENDING_NONE = 0, + SATA_DWC_DMA_PENDING_TX = 1, + SATA_DWC_DMA_PENDING_RX = 2, +}; + +#define msleep(a) udelay(a * 1000) +#define ssleep(a) msleep(a * 1000) + +static int ata_probe_timeout = (ATA_TMOUT_INTERNAL / 100); + +enum sata_dev_state { + SATA_INIT = 0, + SATA_READY = 1, + SATA_NODEVICE = 2, + SATA_ERROR = 3, +}; +enum sata_dev_state dev_state = SATA_INIT; + +static struct ahb_dma_regs *sata_dma_regs = 0; +static struct ata_host *phost; +static struct ata_port ap; +static struct ata_port *pap = ≈ +static struct ata_device ata_device; +static struct sata_dwc_device_port dwc_devp; + +static void *scr_addr_sstatus; +static u32 temp_n_block = 0; + +static unsigned ata_exec_internal(struct ata_device *dev, + struct ata_taskfile *tf, const u8 *cdb, + int dma_dir, unsigned int buflen, + unsigned long timeout); +static unsigned int ata_dev_set_feature(struct ata_device *dev, + u8 enable,u8 feature); +static unsigned int ata_dev_init_params(struct ata_device *dev, + u16 heads, u16 sectors); +static u8 ata_irq_on(struct ata_port *ap); +static struct ata_queued_cmd *__ata_qc_from_tag(struct ata_port *ap, + unsigned int tag); +static int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc, + u8 status, int in_wq); +static void ata_tf_to_host(struct ata_port *ap, + const struct ata_taskfile *tf); +static void ata_exec_command(struct ata_port *ap, + const struct ata_taskfile *tf); +static unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc); +static u8 ata_check_altstatus(struct ata_port *ap); +static u8 ata_check_status(struct ata_port *ap); +static void ata_dev_select(struct ata_port *ap, unsigned int device, + unsigned int wait, unsigned int can_sleep); +static void ata_qc_issue(struct ata_queued_cmd *qc); +static void ata_tf_load(struct ata_port *ap, + const struct ata_taskfile *tf); +static int ata_dev_read_sectors(unsigned char* pdata, + unsigned long datalen, u32 block, u32 n_block); +static int ata_dev_write_sectors(unsigned char* pdata, + unsigned long datalen , u32 block, u32 n_block); +static void ata_std_dev_select(struct ata_port *ap, unsigned int device); +static void ata_qc_complete(struct ata_queued_cmd *qc); +static void __ata_qc_complete(struct ata_queued_cmd *qc); +static void fill_result_tf(struct ata_queued_cmd *qc); +static void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf); +static void ata_mmio_data_xfer(struct ata_device *dev, + unsigned char *buf, + unsigned int buflen,int do_write); +static void ata_pio_task(struct ata_port *arg_ap); +static void __ata_port_freeze(struct ata_port *ap); +static int ata_port_freeze(struct ata_port *ap); +static void ata_qc_free(struct ata_queued_cmd *qc); +static void ata_pio_sectors(struct ata_queued_cmd *qc); +static void ata_pio_sector(struct ata_queued_cmd *qc); +static void ata_pio_queue_task(struct ata_port *ap, + void *data,unsigned long delay); +static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq); +static int sata_dwc_softreset(struct ata_port *ap); +static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class, + unsigned int flags, u16 *id); +static int check_sata_dev_state(void); + +extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; + +static const struct ata_port_info sata_dwc_port_info[] = { + { + .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | + ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING | + ATA_FLAG_SRST | ATA_FLAG_NCQ, + .pio_mask = 0x1f, + .mwdma_mask = 0x07, + .udma_mask = 0x7f, + }, +}; + +int init_sata(int dev) +{ + struct sata_dwc_device hsdev; + struct ata_host host; + struct ata_port_info pi = sata_dwc_port_info[0]; + struct ata_link *link; + struct sata_dwc_device_port hsdevp = dwc_devp; + u8 *base = 0; + u8 *sata_dma_regs_addr = 0; + u8 status; + unsigned long base_addr = 0; + int chan = 0; + int rc; + int i; + + phost = &host; + + base = (u8*)SATA_BASE_ADDR; + + hsdev.sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET); + + host.n_ports = SATA_DWC_MAX_PORTS; + + for (i = 0; i < SATA_DWC_MAX_PORTS; i++) { + ap.pflags |= ATA_PFLAG_INITIALIZING; + ap.flags = ATA_FLAG_DISABLED; + ap.print_id = -1; + ap.ctl = ATA_DEVCTL_OBS; + ap.host = &host; + ap.last_ctl = 0xFF; + + link = &ap.link; + link->ap = ≈ + link->pmp = 0; + link->active_tag = ATA_TAG_POISON; + link->hw_sata_spd_limit = 0; + + ap.port_no = i; + host.ports[i] = ≈ + } + + ap.pio_mask = pi.pio_mask; + ap.mwdma_mask = pi.mwdma_mask; + ap.udma_mask = pi.udma_mask; + ap.flags |= pi.flags; + ap.link.flags |= pi.link_flags; + + host.ports[0]->ioaddr.cmd_addr = base; + host.ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET; + scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET; + + base_addr = (unsigned long)base; + + host.ports[0]->ioaddr.cmd_addr = (void *)base_addr + 0x00; + host.ports[0]->ioaddr.data_addr = (void *)base_addr + 0x00; + + host.ports[0]->ioaddr.error_addr = (void *)base_addr + 0x04; + host.ports[0]->ioaddr.feature_addr = (void *)base_addr + 0x04; + + host.ports[0]->ioaddr.nsect_addr = (void *)base_addr + 0x08; + + host.ports[0]->ioaddr.lbal_addr = (void *)base_addr + 0x0c; + host.ports[0]->ioaddr.lbam_addr = (void *)base_addr + 0x10; + host.ports[0]->ioaddr.lbah_addr = (void *)base_addr + 0x14; + + host.ports[0]->ioaddr.device_addr = (void *)base_addr + 0x18; + host.ports[0]->ioaddr.command_addr = (void *)base_addr + 0x1c; + host.ports[0]->ioaddr.status_addr = (void *)base_addr + 0x1c; + + host.ports[0]->ioaddr.altstatus_addr = (void *)base_addr + 0x20; + host.ports[0]->ioaddr.ctl_addr = (void *)base_addr + 0x20; + + sata_dma_regs_addr = (u8*)SATA_DMA_REG_ADDR; + sata_dma_regs = (void *__iomem)sata_dma_regs_addr; + + status = ata_check_altstatus(&ap); + + if (status == 0x7f) { + printf("Hard Disk not found.\n"); + dev_state = SATA_NODEVICE; + rc = FALSE; + return rc; + } + + printf("Waiting for device..."); + i = 0; + while (1) { + udelay(10000); + + status = ata_check_altstatus(&ap); + + if ((status & ATA_BUSY) == 0) { + printf("\n"); + break; + } + + i++; + if (i > (ATA_RESET_TIME * 100)) { + printf("** TimeOUT **\n"); + + dev_state = SATA_NODEVICE; + rc = FALSE; + return rc; + } + if ((i >= 100) && ((i % 100) == 0)) + printf("."); + } + + rc = sata_dwc_softreset(&ap); + + if (rc) { + printf("sata_dwc : error. soft reset failed\n"); + return rc; + } + + for (chan = 0; chan < DMA_NUM_CHANS; chan++) { + out_le32(&(sata_dma_regs->interrupt_mask.error.low), + DMA_DISABLE_CHAN(chan)); + + out_le32(&(sata_dma_regs->interrupt_mask.tfr.low), + DMA_DISABLE_CHAN(chan)); + } + + out_le32(&(sata_dma_regs->dma_cfg.low), DMA_DI); + + out_le32(&hsdev.sata_dwc_regs->intmr, + SATA_DWC_INTMR_ERRM | + SATA_DWC_INTMR_PMABRTM); + + /* Unmask the error bits that should trigger + * an error interrupt by setting the error mask register. + */ + out_le32(&hsdev.sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS); + + hsdev.host = ap.host; + memset(&hsdevp, 0, sizeof(hsdevp)); + hsdevp.hsdev = &hsdev; + + for (i = 0; i < SATA_DWC_QCMD_MAX; i++) + hsdevp.cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT; + + out_le32((void __iomem *)scr_addr_sstatus + 4, + in_le32((void __iomem *)scr_addr_sstatus + 4)); + + rc = 0; + return rc; +} + +static u8 ata_check_altstatus(struct ata_port *ap) +{ + u8 val = 0; + val = readb(ap->ioaddr.altstatus_addr); + return val; +} + +static int sata_dwc_softreset(struct ata_port *ap) +{ + u8 nsect,lbal = 0; + u8 tmp = 0; + u32 serror = 0; + u8 status = 0; + struct ata_ioports *ioaddr = &ap->ioaddr; + + serror = in_le32((void *)ap->ioaddr.scr_addr + (SCR_ERROR * 4)); + + writeb(0x55, ioaddr->nsect_addr); + writeb(0xaa, ioaddr->lbal_addr); + writeb(0xaa, ioaddr->nsect_addr); + writeb(0x55, ioaddr->lbal_addr); + writeb(0x55, ioaddr->nsect_addr); + writeb(0xaa, ioaddr->lbal_addr); + + nsect = readb(ioaddr->nsect_addr); + lbal = readb(ioaddr->lbal_addr); + + if ((nsect == 0x55) && (lbal == 0xaa)) { + printf("Device found\n"); + } else { + printf("No device found\n"); + dev_state = SATA_NODEVICE; + return FALSE; + } + + tmp = ATA_DEVICE_OBS; + writeb(tmp, ioaddr->device_addr); + writeb(ap->ctl, ioaddr->ctl_addr); + + udelay(200); + + writeb(ap->ctl | ATA_SRST, ioaddr->ctl_addr); + + udelay(200); + writeb(ap->ctl, ioaddr->ctl_addr); + + msleep(150); + status = ata_check_status(ap); + + msleep(50); + ata_check_status(ap); + + while (1) { + u8 status = ata_check_status(ap); + + if (!(status & ATA_BUSY)) + break; + + printf("Hard Disk status is BUSY.\n"); + msleep(50); + } + + tmp = ATA_DEVICE_OBS; + writeb(tmp, ioaddr->device_addr); + + nsect = readb(ioaddr->nsect_addr); + lbal = readb(ioaddr->lbal_addr); + + return 0; +} + +static u8 ata_check_status(struct ata_port *ap) +{ + u8 val = 0; + val = readb(ap->ioaddr.status_addr); + return val; +} + +static int ata_id_has_hipm(const u16 *id) +{ + u16 val = id[76]; + + if (val == 0 || val == 0xffff) + return -1; + + return val & (1 << 9); +} + +static int ata_id_has_dipm(const u16 *id) +{ + u16 val = id[78]; + + if (val == 0 || val == 0xffff) + return -1; + + return val & (1 << 3); +} + +int scan_sata(int dev) +{ + int i; + int rc; + u8 status; + const u16 *id; + struct ata_device *ata_dev = &ata_device; + unsigned long pio_mask, mwdma_mask, udma_mask; + unsigned long xfer_mask; + char revbuf[7]; + u16 iobuf[ATA_SECTOR_WORDS]; + + memset(iobuf, 0, sizeof(iobuf)); + + if (dev_state == SATA_NODEVICE) + return 1; + + printf("Waiting for device..."); + i = 0; + while (1) { + udelay(10000); + + status = ata_check_altstatus(&ap); + + if ((status & ATA_BUSY) == 0) { + printf("\n"); + break; + } + + i++; + if (i > (ATA_RESET_TIME * 100)) { + printf("** TimeOUT **\n"); + + dev_state = SATA_NODEVICE; + return 1; + } + if ((i >= 100) && ((i % 100) == 0)) + printf("."); + } + + udelay(1000); + + rc = ata_dev_read_id(ata_dev, &ata_dev->class, + ATA_READID_POSTRESET,ata_dev->id); + if (rc) { + printf("sata_dwc : error. failed sata scan\n"); + return 1; + } + + /* SATA drives indicate we have a bridge. We don't know which + * end of the link the bridge is which is a problem + */ + if (ata_id_is_sata(ata_dev->id)) + ap.cbl = ATA_CBL_SATA; + + id = ata_dev->id; + + ata_dev->flags &= ~ATA_DFLAG_CFG_MASK; + ata_dev->max_sectors = 0; + ata_dev->cdb_len = 0; + ata_dev->n_sectors = 0; + ata_dev->cylinders = 0; + ata_dev->heads = 0; + ata_dev->sectors = 0; + + if (id[ATA_ID_FIELD_VALID] & (1 << 1)) { + pio_mask = id[ATA_ID_PIO_MODES] & 0x03; + pio_mask <<= 3; + pio_mask |= 0x7; + } else { + /* If word 64 isn't valid then Word 51 high byte holds + * the PIO timing number for the maximum. Turn it into + * a mask. + */ + u8 mode = (id[ATA_ID_OLD_PIO_MODES] >> 8) & 0xFF; + if (mode < 5) { + pio_mask = (2 << mode) - 1; + } else { + pio_mask = 1; + } + } + + mwdma_mask = id[ATA_ID_MWDMA_MODES] & 0x07; + + if (ata_id_is_cfa(id)) { + int pio = id[163] & 0x7; + int dma = (id[163] >> 3) & 7; + + if (pio) + pio_mask |= (1 << 5); + if (pio > 1) + pio_mask |= (1 << 6); + if (dma) + mwdma_mask |= (1 << 3); + if (dma > 1) + mwdma_mask |= (1 << 4); + } + + udma_mask = 0; + if (id[ATA_ID_FIELD_VALID] & (1 << 2)) + udma_mask = id[ATA_ID_UDMA_MODES] & 0xff; + + xfer_mask = ((pio_mask << ATA_SHIFT_PIO) & ATA_MASK_PIO) | + ((mwdma_mask << ATA_SHIFT_MWDMA) & ATA_MASK_MWDMA) | + ((udma_mask << ATA_SHIFT_UDMA) & ATA_MASK_UDMA); + + if (ata_dev->class == ATA_DEV_ATA) { + if (ata_id_is_cfa(id)) { + if (id[162] & 1) + printf("supports DRM functions and may " + "not be fully accessable.\n"); + sprintf(revbuf, "%s", "CFA"); + } else { + if (ata_id_has_tpm(id)) + printf("supports DRM functions and may " + "not be fully accessable.\n"); + } + + ata_dev->n_sectors = ata_id_n_sectors((u16*)id); + + if (ata_dev->id[59] & 0x100) + ata_dev->multi_count = ata_dev->id[59] & 0xff; + + if (ata_id_has_lba(id)) { + const char *lba_desc; + char ncq_desc[20]; + + lba_desc = "LBA"; + ata_dev->flags |= ATA_DFLAG_LBA; + if (ata_id_has_lba48(id)) { + ata_dev->flags |= ATA_DFLAG_LBA48; + lba_desc = "LBA48"; + + if (ata_dev->n_sectors >= (1UL << 28) && + ata_id_has_flush_ext(id)) + ata_dev->flags |= ATA_DFLAG_FLUSH_EXT; + } + if (!ata_id_has_ncq(ata_dev->id)) + ncq_desc[0] = '\0'; + + if (ata_dev->horkage & ATA_HORKAGE_NONCQ) + sprintf(ncq_desc, "%s", "NCQ (not used)"); + + if (ap.flags & ATA_FLAG_NCQ) + ata_dev->flags |= ATA_DFLAG_NCQ; + } + ata_dev->cdb_len = 16; + } + ata_dev->max_sectors = ATA_MAX_SECTORS; + if (ata_dev->flags & ATA_DFLAG_LBA48) + ata_dev->max_sectors = ATA_MAX_SECTORS_LBA48; + + if (!(ata_dev->horkage & ATA_HORKAGE_IPM)) { + if (ata_id_has_hipm(ata_dev->id)) + ata_dev->flags |= ATA_DFLAG_HIPM; + if (ata_id_has_dipm(ata_dev->id)) + ata_dev->flags |= ATA_DFLAG_DIPM; + } + + if ((ap.cbl == ATA_CBL_SATA) && (!ata_id_is_sata(ata_dev->id))) { + ata_dev->udma_mask &= ATA_UDMA5; + ata_dev->max_sectors = ATA_MAX_SECTORS; + } + + if (ata_dev->horkage & ATA_HORKAGE_DIAGNOSTIC) { + printf("Drive reports diagnostics failure." + "This may indicate a drive\n"); + printf("fault or invalid emulation." + "Contact drive vendor for information.\n"); + } + + rc = check_sata_dev_state(); + + ata_id_c_string(ata_dev->id, + (unsigned char *)sata_dev_desc[dev].revision, + ATA_ID_FW_REV, sizeof(sata_dev_desc[dev].revision)); + ata_id_c_string(ata_dev->id, + (unsigned char *)sata_dev_desc[dev].vendor, + ATA_ID_PROD, sizeof(sata_dev_desc[dev].vendor)); + ata_id_c_string(ata_dev->id, + (unsigned char *)sata_dev_desc[dev].product, + ATA_ID_SERNO, sizeof(sata_dev_desc[dev].product)); + + sata_dev_desc[dev].lba = (u32) ata_dev->n_sectors; + +#ifdef CONFIG_LBA48 + if (ata_dev->id[83] & (1 << 10)) { + sata_dev_desc[dev].lba48 = 1; + } else { + sata_dev_desc[dev].lba48 = 0; + } +#endif + + return 0; +} + +static u8 ata_busy_wait(struct ata_port *ap, + unsigned int bits,unsigned int max) +{ + u8 status; + + do { + udelay(10); + status = ata_check_status(ap); + max--; + } while (status != 0xff && (status & bits) && (max > 0)); + + return status; +} + +static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class, + unsigned int flags, u16 *id) +{ + struct ata_port *ap = pap; + unsigned int class = *p_class; + struct ata_taskfile tf; + unsigned int err_mask = 0; + const char *reason; + int may_fallback = 1, tried_spinup = 0; + u8 status; + int rc; + + status = ata_busy_wait(ap, ATA_BUSY, 30000); + if (status & ATA_BUSY) { + printf("BSY = 0 check. timeout.\n"); + rc = FALSE; + return rc; + } + + ata_dev_select(ap, dev->devno, 1, 1); + +retry: + memset(&tf, 0, sizeof(tf)); + ap->print_id = 1; + ap->flags &= ~ATA_FLAG_DISABLED; + tf.ctl = ap->ctl; + tf.device = ATA_DEVICE_OBS; + tf.command = ATA_CMD_ID_ATA; + tf.protocol = ATA_PROT_PIO; + + /* Some devices choke if TF registers contain garbage. Make + * sure those are properly initialized. + */ + tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE; + + /* Device presence detection is unreliable on some + * controllers. Always poll IDENTIFY if available. + */ + tf.flags |= ATA_TFLAG_POLLING; + + temp_n_block = 1; + + err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE, + sizeof(id[0]) * ATA_ID_WORDS, 0); + + if (err_mask) { + if (err_mask & AC_ERR_NODEV_HINT) { + printf("NODEV after polling detection\n"); + return -ENOENT; + } + + if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) { + /* Device or controller might have reported + * the wrong device class. Give a shot at the + * other IDENTIFY if the current one is + * aborted by the device. + */ + if (may_fallback) { + may_fallback = 0; + + if (class == ATA_DEV_ATA) { + class = ATA_DEV_ATAPI; + } else { + class = ATA_DEV_ATA; + } + goto retry; + } + /* Control reaches here iff the device aborted + * both flavors of IDENTIFYs which happens + * sometimes with phantom devices. + */ + printf("both IDENTIFYs aborted, assuming NODEV\n"); + return -ENOENT; + } + rc = -EIO; + reason = "I/O error"; + goto err_out; + } + + /* Falling back doesn't make sense if ID data was read + * successfully at least once. + */ + may_fallback = 0; + + unsigned int id_cnt; + + for (id_cnt = 0; id_cnt < ATA_ID_WORDS; id_cnt++) + id[id_cnt] = le16_to_cpu(id[id_cnt]); + + + rc = -EINVAL; + reason = "device reports invalid type"; + + if (class == ATA_DEV_ATA) { + if (!ata_id_is_ata(id) && !ata_id_is_cfa(id)) + goto err_out; + } else { + if (ata_id_is_ata(id)) + goto err_out; + } + if (!tried_spinup && (id[2] == 0x37c8 || id[2] == 0x738c)) { + tried_spinup = 1; + /* + * Drive powered-up in standby mode, and requires a specific + * SET_FEATURES spin-up subcommand before it will accept + * anything other than the original IDENTIFY command. + */ + err_mask = ata_dev_set_feature(dev, SETFEATURES_SPINUP, 0); + if (err_mask && id[2] != 0x738c) { + rc = -EIO; + reason = "SPINUP failed"; + goto err_out; + } + /* + * If the drive initially returned incomplete IDENTIFY info, + * we now must reissue the IDENTIFY command. + */ + if (id[2] == 0x37c8) + goto retry; + } + + if ((flags & ATA_READID_POSTRESET) && class == ATA_DEV_ATA) { + /* + * The exact sequence expected by certain pre-ATA4 drives is: + * SRST RESET + * IDENTIFY (optional in early ATA) + * INITIALIZE DEVICE PARAMETERS (later IDE and ATA) + * anything else.. + * Some drives were very specific about that exact sequence. + * + * Note that ATA4 says lba is mandatory so the second check + * shoud never trigger. + */ + if (ata_id_major_version(id) < 4 || !ata_id_has_lba(id)) { + err_mask = ata_dev_init_params(dev, id[3], id[6]); + if (err_mask) { + rc = -EIO; + reason = "INIT_DEV_PARAMS failed"; + goto err_out; + } + + /* current CHS translation info (id[53-58]) might be + * changed. reread the identify device info. + */ + flags &= ~ATA_READID_POSTRESET; + goto retry; + } + } + + *p_class = class; + return 0; + +err_out: + return rc; +} + +static u8 ata_wait_idle(struct ata_port *ap) +{ + u8 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); + return status; +} + +static void ata_dev_select(struct ata_port *ap, unsigned int device, + unsigned int wait, unsigned int can_sleep) +{ + if (wait) + ata_wait_idle(ap); + + ata_std_dev_select(ap, device); + + if (wait) + ata_wait_idle(ap); +} + +static void ata_std_dev_select(struct ata_port *ap, unsigned int device) +{ + u8 tmp; + + if (device == 0) { + tmp = ATA_DEVICE_OBS; + } else { + tmp = ATA_DEVICE_OBS | ATA_DEV1; + } + + writeb(tmp, ap->ioaddr.device_addr); + + readb(ap->ioaddr.altstatus_addr); + + udelay(1); +} + +static int waiting_for_reg_state(volatile u8 *offset, + int timeout_msec, + u32 sign) +{ + int i; + u32 status; + + for (i = 0; i < timeout_msec; i++) { + status = readl(offset); + if ((status & sign) != 0) + break; + msleep(1); + } + + return (i < timeout_msec) ? 0 : -1; +} + +static void ata_qc_reinit(struct ata_queued_cmd *qc) +{ + qc->dma_dir = DMA_NONE; + qc->flags = 0; + qc->nbytes = qc->extrabytes = qc->curbytes = 0; + qc->n_elem = 0; + qc->err_mask = 0; + qc->sect_size = ATA_SECT_SIZE; + qc->nbytes = ATA_SECT_SIZE * temp_n_block; + + memset(&qc->tf, 0, sizeof(qc->tf)); + qc->tf.ctl = 0; + qc->tf.device = ATA_DEVICE_OBS; + + qc->result_tf.command = ATA_DRDY; + qc->result_tf.feature = 0; +} + +struct ata_queued_cmd *__ata_qc_from_tag(struct ata_port *ap, + unsigned int tag) +{ + if (tag < ATA_MAX_QUEUE) + return &ap->qcmd[tag]; + return NULL; +} + +static void __ata_port_freeze(struct ata_port *ap) +{ + printf("set port freeze.\n"); + ap->pflags |= ATA_PFLAG_FROZEN; +} + +static int ata_port_freeze(struct ata_port *ap) +{ + __ata_port_freeze(ap); + return 0; +} + +unsigned ata_exec_internal(struct ata_device *dev, + struct ata_taskfile *tf, const u8 *cdb, + int dma_dir, unsigned int buflen, + unsigned long timeout) +{ + struct ata_link *link = dev->link; + struct ata_port *ap = pap; + struct ata_queued_cmd *qc; + unsigned int tag, preempted_tag; + u32 preempted_sactive, preempted_qc_active; + int preempted_nr_active_links; + unsigned int err_mask; + int rc = 0; + u8 status; + + status = ata_busy_wait(ap, ATA_BUSY, 300000); + if (status & ATA_BUSY) { + printf("BSY = 0 check. timeout.\n"); + rc = FALSE; + return rc; + } + + if (ap->pflags & ATA_PFLAG_FROZEN) + return AC_ERR_SYSTEM; + + tag = ATA_TAG_INTERNAL; + + if (test_and_set_bit(tag, &ap->qc_allocated)) { + rc = FALSE; + return rc; + } + + qc = __ata_qc_from_tag(ap, tag); + qc->tag = tag; + qc->ap = ap; + qc->dev = dev; + + ata_qc_reinit(qc); + + preempted_tag = link->active_tag; + preempted_sactive = link->sactive; + preempted_qc_active = ap->qc_active; + preempted_nr_active_links = ap->nr_active_links; + link->active_tag = ATA_TAG_POISON; + link->sactive = 0; + ap->qc_active = 0; + ap->nr_active_links = 0; + + qc->tf = *tf; + if (cdb) + memcpy(qc->cdb, cdb, ATAPI_CDB_LEN); + qc->flags |= ATA_QCFLAG_RESULT_TF; + qc->dma_dir = dma_dir; + qc->private_data = 0; + + ata_qc_issue(qc); + + if (!timeout) + timeout = ata_probe_timeout * 1000 / HZ; + + status = ata_busy_wait(ap, ATA_BUSY, 30000); + if (status & ATA_BUSY) { + printf("BSY = 0 check. timeout.\n"); + printf("altstatus = 0x%x.\n", status); + qc->err_mask |= AC_ERR_OTHER; + return qc->err_mask; + } + + if (waiting_for_reg_state(ap->ioaddr.altstatus_addr, 1000, 0x8)) { + u8 status = 0; + u8 errorStatus = 0; + + status = readb(ap->ioaddr.altstatus_addr); + if ((status & 0x01) != 0) { + errorStatus = readb(ap->ioaddr.feature_addr); + if (errorStatus == 0x04 && + qc->tf.command == ATA_CMD_PIO_READ_EXT){ + printf("Hard Disk doesn't support LBA48\n"); + dev_state = SATA_ERROR; + qc->err_mask |= AC_ERR_OTHER; + return qc->err_mask; + } + } + qc->err_mask |= AC_ERR_OTHER; + return qc->err_mask; + } + + status = ata_busy_wait(ap, ATA_BUSY, 10); + if (status & ATA_BUSY) { + printf("BSY = 0 check. timeout.\n"); + qc->err_mask |= AC_ERR_OTHER; + return qc->err_mask; + } + + ata_pio_task(ap); + + if (!rc) { + if (qc->flags & ATA_QCFLAG_ACTIVE) { + qc->err_mask |= AC_ERR_TIMEOUT; + ata_port_freeze(ap); + } + } + + if (qc->flags & ATA_QCFLAG_FAILED) { + if (qc->result_tf.command & (ATA_ERR | ATA_DF)) + qc->err_mask |= AC_ERR_DEV; + + if (!qc->err_mask) + qc->err_mask |= AC_ERR_OTHER; + + if (qc->err_mask & ~AC_ERR_OTHER) + qc->err_mask &= ~AC_ERR_OTHER; + } + + *tf = qc->result_tf; + err_mask = qc->err_mask; + ata_qc_free(qc); + link->active_tag = preempted_tag; + link->sactive = preempted_sactive; + ap->qc_active = preempted_qc_active; + ap->nr_active_links = preempted_nr_active_links; + + if (ap->flags & ATA_FLAG_DISABLED) { + err_mask |= AC_ERR_SYSTEM; + ap->flags &= ~ATA_FLAG_DISABLED; + } + + return err_mask; +} + +static void ata_qc_issue(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + struct ata_link *link = qc->dev->link; + u8 prot = qc->tf.protocol; + + if (ata_is_ncq(prot)) { + if (!link->sactive) + ap->nr_active_links++; + link->sactive |= 1 << qc->tag; + } else { + ap->nr_active_links++; + link->active_tag = qc->tag; + } + + qc->flags |= ATA_QCFLAG_ACTIVE; + ap->qc_active |= 1 << qc->tag; + + if (qc->dev->flags & ATA_DFLAG_SLEEPING) { + msleep(1); + return; + } + + qc->err_mask |= ata_qc_issue_prot(qc); + if (qc->err_mask) + goto err; + + return; +err: + ata_qc_complete(qc); +} + +static unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + + if (ap->flags & ATA_FLAG_PIO_POLLING) { + switch (qc->tf.protocol) { + case ATA_PROT_PIO: + case ATA_PROT_NODATA: + case ATAPI_PROT_PIO: + case ATAPI_PROT_NODATA: + qc->tf.flags |= ATA_TFLAG_POLLING; + break; + default: + break; + } + } + + ata_dev_select(ap, qc->dev->devno, 1, 0); + + switch (qc->tf.protocol) { + case ATA_PROT_PIO: + if (qc->tf.flags & ATA_TFLAG_POLLING) + qc->tf.ctl |= ATA_NIEN; + + ata_tf_to_host(ap, &qc->tf); + + ap->hsm_task_state = HSM_ST; + + if (qc->tf.flags & ATA_TFLAG_POLLING) + ata_pio_queue_task(ap, qc, 0); + + break; + + default: + return AC_ERR_SYSTEM; + } + + return 0; +} + +static void ata_tf_to_host(struct ata_port *ap, + const struct ata_taskfile *tf) +{ + ata_tf_load(ap, tf); + ata_exec_command(ap, tf); +} + +static void ata_tf_load(struct ata_port *ap, + const struct ata_taskfile *tf) +{ + struct ata_ioports *ioaddr = &ap->ioaddr; + unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; + + if (tf->ctl != ap->last_ctl) { + if (ioaddr->ctl_addr) + writeb(tf->ctl, ioaddr->ctl_addr); + ap->last_ctl = tf->ctl; + ata_wait_idle(ap); + } + + if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { + writeb(tf->hob_feature, ioaddr->feature_addr); + writeb(tf->hob_nsect, ioaddr->nsect_addr); + writeb(tf->hob_lbal, ioaddr->lbal_addr); + writeb(tf->hob_lbam, ioaddr->lbam_addr); + writeb(tf->hob_lbah, ioaddr->lbah_addr); + } + + if (is_addr) { + writeb(tf->feature, ioaddr->feature_addr); + writeb(tf->nsect, ioaddr->nsect_addr); + writeb(tf->lbal, ioaddr->lbal_addr); + writeb(tf->lbam, ioaddr->lbam_addr); + writeb(tf->lbah, ioaddr->lbah_addr); + } + + if (tf->flags & ATA_TFLAG_DEVICE) + writeb(tf->device, ioaddr->device_addr); + + ata_wait_idle(ap); +} + +static void ata_exec_command(struct ata_port *ap, + const struct ata_taskfile *tf) +{ + writeb(tf->command, ap->ioaddr.command_addr); + + readb(ap->ioaddr.altstatus_addr); + + udelay(1); +} + +static void ata_pio_queue_task(struct ata_port *ap, + void *data,unsigned long delay) +{ + ap->port_task_data = data; +} + +static unsigned int ac_err_mask(u8 status) +{ + if (status & (ATA_BUSY | ATA_DRQ)) + return AC_ERR_HSM; + if (status & (ATA_ERR | ATA_DF)) + return AC_ERR_DEV; + return 0; +} + +static unsigned int __ac_err_mask(u8 status) +{ + unsigned int mask = ac_err_mask(status); + if (mask == 0) + return AC_ERR_OTHER; + return mask; +} + +static void ata_pio_task(struct ata_port *arg_ap) +{ + struct ata_port *ap = arg_ap; + struct ata_queued_cmd *qc = ap->port_task_data; + u8 status; + int poll_next; + +fsm_start: + /* + * This is purely heuristic. This is a fast path. + * Sometimes when we enter, BSY will be cleared in + * a chk-status or two. If not, the drive is probably seeking + * or something. Snooze for a couple msecs, then + * chk-status again. If still busy, queue delayed work. + */ + status = ata_busy_wait(ap, ATA_BUSY, 5); + if (status & ATA_BUSY) { + msleep(2); + status = ata_busy_wait(ap, ATA_BUSY, 10); + if (status & ATA_BUSY) { + ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE); + return; + } + } + + poll_next = ata_hsm_move(ap, qc, status, 1); + + /* another command or interrupt handler + * may be running at this point. + */ + if (poll_next) + goto fsm_start; +} + +static int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc, + u8 status, int in_wq) +{ + int poll_next; + +fsm_start: + switch (ap->hsm_task_state) { + case HSM_ST_FIRST: + poll_next = (qc->tf.flags & ATA_TFLAG_POLLING); + + if ((status & ATA_DRQ) == 0) { + if (status & (ATA_ERR | ATA_DF)) { + qc->err_mask |= AC_ERR_DEV; + } else { + qc->err_mask |= AC_ERR_HSM; + } + ap->hsm_task_state = HSM_ST_ERR; + goto fsm_start; + } + + /* Device should not ask for data transfer (DRQ=1) + * when it finds something wrong. + * We ignore DRQ here and stop the HSM by + * changing hsm_task_state to HSM_ST_ERR and + * let the EH abort the command or reset the device. + */ + if (status & (ATA_ERR | ATA_DF)) { + if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) { + printf("DRQ=1 with device error, " + "dev_stat 0x%X\n", status); + qc->err_mask |= AC_ERR_HSM; + ap->hsm_task_state = HSM_ST_ERR; + goto fsm_start; + } + } + + if (qc->tf.protocol == ATA_PROT_PIO) { + /* PIO data out protocol. + * send first data block. + */ + /* ata_pio_sectors() might change the state + * to HSM_ST_LAST. so, the state is changed here + * before ata_pio_sectors(). + */ + ap->hsm_task_state = HSM_ST; + ata_pio_sectors(qc); + } else { + printf("protocol is not ATA_PROT_PIO \n"); + } + break; + + case HSM_ST: + if ((status & ATA_DRQ) == 0) { + if (status & (ATA_ERR | ATA_DF)) { + qc->err_mask |= AC_ERR_DEV; + } else { + /* HSM violation. Let EH handle this. + * Phantom devices also trigger this + * condition. Mark hint. + */ + qc->err_mask |= AC_ERR_HSM | AC_ERR_NODEV_HINT; + } + + ap->hsm_task_state = HSM_ST_ERR; + goto fsm_start; + } + /* For PIO reads, some devices may ask for + * data transfer (DRQ=1) alone with ERR=1. + * We respect DRQ here and transfer one + * block of junk data before changing the + * hsm_task_state to HSM_ST_ERR. + * + * For PIO writes, ERR=1 DRQ=1 doesn't make + * sense since the data block has been + * transferred to the device. + */ + if (status & (ATA_ERR | ATA_DF)) { + qc->err_mask |= AC_ERR_DEV; + + if (!(qc->tf.flags & ATA_TFLAG_WRITE)) { + ata_pio_sectors(qc); + status = ata_wait_idle(ap); + } + + if (status & (ATA_BUSY | ATA_DRQ)) + qc->err_mask |= AC_ERR_HSM; + + /* ata_pio_sectors() might change the + * state to HSM_ST_LAST. so, the state + * is changed after ata_pio_sectors(). + */ + ap->hsm_task_state = HSM_ST_ERR; + goto fsm_start; + } + + ata_pio_sectors(qc); + if (ap->hsm_task_state == HSM_ST_LAST && + (!(qc->tf.flags & ATA_TFLAG_WRITE))) { + status = ata_wait_idle(ap); + goto fsm_start; + } + + poll_next = 1; + break; + + case HSM_ST_LAST: + if (!ata_ok(status)) { + qc->err_mask |= __ac_err_mask(status); + ap->hsm_task_state = HSM_ST_ERR; + goto fsm_start; + } + + ap->hsm_task_state = HSM_ST_IDLE; + + ata_hsm_qc_complete(qc, in_wq); + + poll_next = 0; + break; + + case HSM_ST_ERR: + /* make sure qc->err_mask is available to + * know what's wrong and recover + */ + ap->hsm_task_state = HSM_ST_IDLE; + + ata_hsm_qc_complete(qc, in_wq); + + poll_next = 0; + break; + default: + poll_next = 0; + } + + return poll_next; +} + +static void ata_pio_sectors(struct ata_queued_cmd *qc) +{ + struct ata_port *ap; + ap = pap; + qc->pdata = ap->pdata; + + ata_pio_sector(qc); + + readb(qc->ap->ioaddr.altstatus_addr); + udelay(1); +} + +static void ata_pio_sector(struct ata_queued_cmd *qc) +{ + int do_write = (qc->tf.flags & ATA_TFLAG_WRITE); + struct ata_port *ap = qc->ap; + unsigned int offset; + unsigned char *buf; + char temp_data_buf[512]; + + if (qc->curbytes == qc->nbytes - qc->sect_size) + ap->hsm_task_state = HSM_ST_LAST; + + offset = qc->curbytes; + + switch (qc->tf.command) { + case ATA_CMD_ID_ATA: + buf = (unsigned char *)&ata_device.id[0]; + break; + case ATA_CMD_PIO_READ_EXT: + case ATA_CMD_PIO_READ: + case ATA_CMD_PIO_WRITE_EXT: + case ATA_CMD_PIO_WRITE: + buf = qc->pdata + offset; + break; + default: + buf = (unsigned char *)&temp_data_buf[0]; + } + + ata_mmio_data_xfer(qc->dev, buf, qc->sect_size, do_write); + + qc->curbytes += qc->sect_size; + +} + +static void ata_mmio_data_xfer(struct ata_device *dev, unsigned char *buf, + unsigned int buflen, int do_write) +{ + struct ata_port *ap = pap; + void __iomem *data_addr = ap->ioaddr.data_addr; + unsigned int words = buflen >> 1; + u16 *buf16 = (u16 *)buf; + unsigned int i = 0; + + udelay(100); + if (do_write) { + for (i = 0; i < words; i++) + writew(le16_to_cpu(buf16[i]), data_addr); + } else { + for (i = 0; i < words; i++) + buf16[i] = cpu_to_le16(readw(data_addr)); + } + + if (buflen & 0x01) { + __le16 align_buf[1] = { 0 }; + unsigned char *trailing_buf = buf + buflen - 1; + + if (do_write) { + memcpy(align_buf, trailing_buf, 1); + writew(le16_to_cpu(align_buf[0]), data_addr); + } else { + align_buf[0] = cpu_to_le16(readw(data_addr)); + memcpy(trailing_buf, align_buf, 1); + } + } +} + +static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq) +{ + struct ata_port *ap = qc->ap; + + if (in_wq) { + /* EH might have kicked in while host lock is + * released. + */ + qc = &ap->qcmd[qc->tag]; + if (qc) { + if (!(qc->err_mask & AC_ERR_HSM)) { + ata_irq_on(ap); + ata_qc_complete(qc); + } else { + ata_port_freeze(ap); + } + } + } else { + if (!(qc->err_mask & AC_ERR_HSM)) { + ata_qc_complete(qc); + } else { + ata_port_freeze(ap); + } + } +} + +static u8 ata_irq_on(struct ata_port *ap) +{ + struct ata_ioports *ioaddr = &ap->ioaddr; + u8 tmp; + + ap->ctl &= ~ATA_NIEN; + ap->last_ctl = ap->ctl; + + if (ioaddr->ctl_addr) + writeb(ap->ctl, ioaddr->ctl_addr); + + tmp = ata_wait_idle(ap); + + return tmp; +} + +static unsigned int ata_tag_internal(unsigned int tag) +{ + return tag == ATA_MAX_QUEUE - 1; +} + +static void ata_qc_complete(struct ata_queued_cmd *qc) +{ + struct ata_device *dev = qc->dev; + if (qc->err_mask) + qc->flags |= ATA_QCFLAG_FAILED; + + if (qc->flags & ATA_QCFLAG_FAILED) { + if (!ata_tag_internal(qc->tag)) { + fill_result_tf(qc); + return; + } + } + if (qc->flags & ATA_QCFLAG_RESULT_TF) + fill_result_tf(qc); + + /* Some commands need post-processing after successful + * completion. + */ + switch (qc->tf.command) { + case ATA_CMD_SET_FEATURES: + if (qc->tf.feature != SETFEATURES_WC_ON && + qc->tf.feature != SETFEATURES_WC_OFF) + break; + case ATA_CMD_INIT_DEV_PARAMS: + case ATA_CMD_SET_MULTI: + break; + + case ATA_CMD_SLEEP: + dev->flags |= ATA_DFLAG_SLEEPING; + break; + } + + __ata_qc_complete(qc); +} + +static void fill_result_tf(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + + qc->result_tf.flags = qc->tf.flags; + ata_tf_read(ap, &qc->result_tf); +} + +static void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) +{ + struct ata_ioports *ioaddr = &ap->ioaddr; + + tf->command = ata_check_status(ap); + tf->feature = readb(ioaddr->error_addr); + tf->nsect = readb(ioaddr->nsect_addr); + tf->lbal = readb(ioaddr->lbal_addr); + tf->lbam = readb(ioaddr->lbam_addr); + tf->lbah = readb(ioaddr->lbah_addr); + tf->device = readb(ioaddr->device_addr); + + if (tf->flags & ATA_TFLAG_LBA48) { + if (ioaddr->ctl_addr) { + writeb(tf->ctl | ATA_HOB, ioaddr->ctl_addr); + + tf->hob_feature = readb(ioaddr->error_addr); + tf->hob_nsect = readb(ioaddr->nsect_addr); + tf->hob_lbal = readb(ioaddr->lbal_addr); + tf->hob_lbam = readb(ioaddr->lbam_addr); + tf->hob_lbah = readb(ioaddr->lbah_addr); + + writeb(tf->ctl, ioaddr->ctl_addr); + ap->last_ctl = tf->ctl; + } else { + printf("sata_dwc warnning register read.\n"); + } + } +} + +static void __ata_qc_complete(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + struct ata_link *link = qc->dev->link; + + link->active_tag = ATA_TAG_POISON; + ap->nr_active_links--; + + if (qc->flags & ATA_QCFLAG_CLEAR_EXCL && ap->excl_link == link) + ap->excl_link = NULL; + + qc->flags &= ~ATA_QCFLAG_ACTIVE; + ap->qc_active &= ~(1 << qc->tag); +} + +static void ata_qc_free(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + unsigned int tag; + qc->flags = 0; + tag = qc->tag; + if (tag < ATA_MAX_QUEUE) { + qc->tag = ATA_TAG_POISON; + clear_bit(tag, &ap->qc_allocated); + } +} + +static int check_sata_dev_state(void) +{ + unsigned long datalen; + unsigned char *pdata; + int ret = 0; + int i = 0; + char temp_data_buf[512]; + + while (1) { + udelay(10000); + + pdata = (unsigned char*)&temp_data_buf[0]; + datalen = 512; + + ret = ata_dev_read_sectors(pdata, datalen, 0, 1); + + if (ret == TRUE) + break; + + i++; + if (i > (ATA_RESET_TIME * 100)) { + printf("** TimeOUT **\n"); + dev_state = SATA_NODEVICE; + return FALSE; + } + + if ((i >= 100) && ((i % 100) == 0)) + printf("."); + } + + dev_state = SATA_READY; + + return TRUE; +} + +static unsigned int ata_dev_set_feature(struct ata_device *dev, + u8 enable, u8 feature) +{ + struct ata_taskfile tf; + struct ata_port *ap; + ap = pap; + unsigned int err_mask; + + memset(&tf, 0, sizeof(tf)); + tf.ctl = ap->ctl; + + tf.device = ATA_DEVICE_OBS; + tf.command = ATA_CMD_SET_FEATURES; + tf.feature = enable; + tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE; + tf.protocol = ATA_PROT_NODATA; + tf.nsect = feature; + + err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, 0, 0); + + return err_mask; +} + +static unsigned int ata_dev_init_params(struct ata_device *dev, + u16 heads, u16 sectors) +{ + struct ata_taskfile tf; + struct ata_port *ap; + ap = pap; + unsigned int err_mask; + + if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16) + return AC_ERR_INVALID; + + memset(&tf, 0, sizeof(tf)); + tf.ctl = ap->ctl; + tf.device = ATA_DEVICE_OBS; + tf.command = ATA_CMD_INIT_DEV_PARAMS; + tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE; + tf.protocol = ATA_PROT_NODATA; + tf.nsect = sectors; + tf.device |= (heads - 1) & 0x0f; + + err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, 0, 0); + + if (err_mask == AC_ERR_DEV && (tf.feature & ATA_ABORTED)) + err_mask = 0; + + return err_mask; +} + +#if defined(CONFIG_SATA_DWC) && !defined(CONFIG_LBA48) +#define SATA_MAX_READ_BLK 0xFF +#else +#define SATA_MAX_READ_BLK 0xFFFF +#endif + +ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer) +{ + ulong start,blks, buf_addr; + unsigned short smallblks; + unsigned long datalen; + unsigned char *pdata; + device &= 0xff; + + u32 block = 0; + u32 n_block = 0; + + if (dev_state != SATA_READY) + return 0; + + buf_addr = (unsigned long)buffer; + start = blknr; + blks = blkcnt; + do { + pdata = (unsigned char *)buf_addr; + if (blks > SATA_MAX_READ_BLK) { + datalen = sata_dev_desc[device].blksz * SATA_MAX_READ_BLK; + smallblks = SATA_MAX_READ_BLK; + + block = (u32)start; + n_block = (u32)smallblks; + + start += SATA_MAX_READ_BLK; + blks -= SATA_MAX_READ_BLK; + } else { + datalen = sata_dev_desc[device].blksz * SATA_MAX_READ_BLK; + datalen = sata_dev_desc[device].blksz * blks; + smallblks = (unsigned short)blks; + + block = (u32)start; + n_block = (u32)smallblks; + + start += blks; + blks = 0; + } + + if (ata_dev_read_sectors(pdata, datalen, block, n_block) != TRUE) { + printf("sata_dwc : Hard disk read error.\n"); + blkcnt -= blks; + break; + } + buf_addr += datalen; + } while (blks != 0); + + return (blkcnt); +} + +static int ata_dev_read_sectors(unsigned char *pdata, unsigned long datalen, + u32 block, u32 n_block) +{ + struct ata_port *ap = pap; + struct ata_device *dev = &ata_device; + struct ata_taskfile tf; + unsigned int class = ATA_DEV_ATA; + unsigned int err_mask = 0; + const char *reason; + int may_fallback = 1; + int rc; + + if (dev_state == SATA_ERROR) + return FALSE; + + ata_dev_select(ap, dev->devno, 1, 1); + +retry: + memset(&tf, 0, sizeof(tf)); + tf.ctl = ap->ctl; + ap->print_id = 1; + ap->flags &= ~ATA_FLAG_DISABLED; + + ap->pdata = pdata; + + tf.device = ATA_DEVICE_OBS; + + temp_n_block = n_block; + +#ifdef CONFIG_LBA48 + tf.command = ATA_CMD_PIO_READ_EXT; + tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_LBA48; + + tf.hob_feature = 31; + tf.feature = 31; + tf.hob_nsect = (n_block >> 8) & 0xff; + tf.nsect = n_block & 0xff; + + tf.hob_lbah = 0x0; + tf.hob_lbam = 0x0; + tf.hob_lbal = (block >> 24) & 0xff; + tf.lbah = (block >> 16) & 0xff; + tf.lbam = (block >> 8) & 0xff; + tf.lbal = block & 0xff; + + tf.device = 1 << 6; + if (tf.flags & ATA_TFLAG_FUA) + tf.device |= 1 << 7; +#else + tf.command = ATA_CMD_PIO_READ; + tf.flags |= ATA_TFLAG_LBA ; + + tf.feature = 31; + tf.nsect = n_block & 0xff; + + tf.lbah = (block >> 16) & 0xff; + tf.lbam = (block >> 8) & 0xff; + tf.lbal = block & 0xff; + + tf.device = (block >> 24) & 0xf; + + tf.device |= 1 << 6; + if (tf.flags & ATA_TFLAG_FUA) + tf.device |= 1 << 7; + +#endif + + tf.protocol = ATA_PROT_PIO; + + /* Some devices choke if TF registers contain garbage. Make + * sure those are properly initialized. + */ + tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE; + tf.flags |= ATA_TFLAG_POLLING; + + err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE, 0, 0); + + if (err_mask) { + if (err_mask & AC_ERR_NODEV_HINT) { + printf("READ_SECTORS NODEV after polling detection\n"); + return -ENOENT; + } + + if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) { + /* Device or controller might have reported + * the wrong device class. Give a shot at the + * other IDENTIFY if the current one is + * aborted by the device. + */ + if (may_fallback) { + may_fallback = 0; + + if (class == ATA_DEV_ATA) { + class = ATA_DEV_ATAPI; + } else { + class = ATA_DEV_ATA; + } + goto retry; + } + /* Control reaches here iff the device aborted + * both flavors of IDENTIFYs which happens + * sometimes with phantom devices. + */ + printf("both IDENTIFYs aborted, assuming NODEV\n"); + return -ENOENT; + } + + rc = -EIO; + reason = "I/O error"; + goto err_out; + } + + /* Falling back doesn't make sense if ID data was read + * successfully at least once. + */ + may_fallback = 0; + + rc = -EINVAL; + reason = "device reports invalid type"; + + return TRUE; + +err_out: + printf("failed to READ SECTORS (%s, err_mask=0x%x)\n", reason, err_mask); + return FALSE; +} + +#if defined(CONFIG_SATA_DWC) && !defined(CONFIG_LBA48) +#define SATA_MAX_WRITE_BLK 0xFF +#else +#define SATA_MAX_WRITE_BLK 0xFFFF +#endif + +ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, void *buffer) +{ + ulong start,blks, buf_addr; + unsigned short smallblks; + unsigned long datalen; + unsigned char *pdata; + device &= 0xff; + + + u32 block = 0; + u32 n_block = 0; + + if (dev_state != SATA_READY) + return 0; + + buf_addr = (unsigned long)buffer; + start = blknr; + blks = blkcnt; + do { + pdata = (unsigned char *)buf_addr; + if (blks > SATA_MAX_WRITE_BLK) { + datalen = sata_dev_desc[device].blksz * SATA_MAX_WRITE_BLK; + smallblks = SATA_MAX_WRITE_BLK; + + block = (u32)start; + n_block = (u32)smallblks; + + start += SATA_MAX_WRITE_BLK; + blks -= SATA_MAX_WRITE_BLK; + } else { + datalen = sata_dev_desc[device].blksz * blks; + smallblks = (unsigned short)blks; + + block = (u32)start; + n_block = (u32)smallblks; + + start += blks; + blks = 0; + } + + if (ata_dev_write_sectors(pdata, datalen, block, n_block) != TRUE) { + printf("sata_dwc : Hard disk read error.\n"); + blkcnt -= blks; + break; + } + buf_addr += datalen; + } while (blks != 0); + + return (blkcnt); +} + +static int ata_dev_write_sectors(unsigned char* pdata, unsigned long datalen, + u32 block, u32 n_block) +{ + struct ata_port *ap = pap; + struct ata_device *dev = &ata_device; + struct ata_taskfile tf; + unsigned int class = ATA_DEV_ATA; + unsigned int err_mask = 0; + const char *reason; + int may_fallback = 1; + int rc; + + if (dev_state == SATA_ERROR) + return FALSE; + + ata_dev_select(ap, dev->devno, 1, 1); + +retry: + memset(&tf, 0, sizeof(tf)); + tf.ctl = ap->ctl; + ap->print_id = 1; + ap->flags &= ~ATA_FLAG_DISABLED; + + ap->pdata = pdata; + + tf.device = ATA_DEVICE_OBS; + + temp_n_block = n_block; + + +#ifdef CONFIG_LBA48 + tf.command = ATA_CMD_PIO_WRITE_EXT; + tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_LBA48 | ATA_TFLAG_WRITE; + + tf.hob_feature = 31; + tf.feature = 31; + tf.hob_nsect = (n_block >> 8) & 0xff; + tf.nsect = n_block & 0xff; + + tf.hob_lbah = 0x0; + tf.hob_lbam = 0x0; + tf.hob_lbal = (block >> 24) & 0xff; + tf.lbah = (block >> 16) & 0xff; + tf.lbam = (block >> 8) & 0xff; + tf.lbal = block & 0xff; + + tf.device = 1 << 6; + if (tf.flags & ATA_TFLAG_FUA) + tf.device |= 1 << 7; +#else + tf.command = ATA_CMD_PIO_WRITE; + tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_WRITE; + + tf.feature = 31; + tf.nsect = n_block & 0xff; + + tf.lbah = (block >> 16) & 0xff; + tf.lbam = (block >> 8) & 0xff; + tf.lbal = block & 0xff; + + tf.device = (block >> 24) & 0xf; + + tf.device |= 1 << 6; + if (tf.flags & ATA_TFLAG_FUA) + tf.device |= 1 << 7; + +#endif + + tf.protocol = ATA_PROT_PIO; + + /* Some devices choke if TF registers contain garbage. Make + * sure those are properly initialized. + */ + tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE; + tf.flags |= ATA_TFLAG_POLLING; + + err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE, 0, 0); + + if (err_mask) { + if (err_mask & AC_ERR_NODEV_HINT) { + printf("READ_SECTORS NODEV after polling detection\n"); + return -ENOENT; + } + + if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) { + /* Device or controller might have reported + * the wrong device class. Give a shot at the + * other IDENTIFY if the current one is + * aborted by the device. + */ + if (may_fallback) { + may_fallback = 0; + + if (class == ATA_DEV_ATA) { + class = ATA_DEV_ATAPI; + } else { + class = ATA_DEV_ATA; + } + goto retry; + } + /* Control reaches here iff the device aborted + * both flavors of IDENTIFYs which happens + * sometimes with phantom devices. + */ + printf("both IDENTIFYs aborted, assuming NODEV\n"); + return -ENOENT; + } + + rc = -EIO; + reason = "I/O error"; + goto err_out; + } + + /* Falling back doesn't make sense if ID data was read + * successfully at least once. + */ + may_fallback = 0; + + rc = -EINVAL; + reason = "device reports invalid type"; + + return TRUE; + +err_out: + printf("failed to WRITE SECTORS (%s, err_mask=0x%x)\n", reason, err_mask); + return FALSE; +} diff --git a/drivers/block/sata_dwc.h b/drivers/block/sata_dwc.h new file mode 100644 index 0000000..204d644 --- /dev/null +++ b/drivers/block/sata_dwc.h @@ -0,0 +1,477 @@ +/* + * sata_dwc.h + * + * Synopsys DesignWare Cores (DWC) SATA host driver + * + * Author: Mark Miesfeld <mmiesfeld@amcc.com> + * + * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de> + * Copyright 2008 DENX Software Engineering + * + * Based on versions provided by AMCC and Synopsys which are: + * Copyright 2006 Applied Micro Circuits Corporation + * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED + * + * This program is free software; you can redistribute + * it and/or modify it under the terms of the GNU + * General Public License as published by the + * Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. + * + */ +/* + * SATA support based on the chip canyonlands. + * + * 04-17-2009 + * The local version of this driver for the canyonlands board + * does not use interrupts but polls the chip instead. + */ + + +#ifndef _SATA_DWC_H_ +#define _SATA_DWC_H_ + +#define __U_BOOT__ + +#define HZ 100 +#define READ 0 +#define WRITE 1 + +enum { + ATA_READID_POSTRESET = (1 << 0), + + ATA_DNXFER_PIO = 0, + ATA_DNXFER_DMA = 1, + ATA_DNXFER_40C = 2, + ATA_DNXFER_FORCE_PIO = 3, + ATA_DNXFER_FORCE_PIO0 = 4, + + ATA_DNXFER_QUIET = (1 << 31), +}; + +enum hsm_task_states { + HSM_ST_IDLE, + HSM_ST_FIRST, + HSM_ST, + HSM_ST_LAST, + HSM_ST_ERR, +}; + +#define ATA_SHORT_PAUSE ((HZ >> 6) + 1) + +struct ata_queued_cmd { + struct ata_port *ap; + struct ata_device *dev; + + struct ata_taskfile tf; + u8 cdb[ATAPI_CDB_LEN]; + unsigned long flags; + unsigned int tag; + unsigned int n_elem; + + int dma_dir; + unsigned int sect_size; + + unsigned int nbytes; + unsigned int extrabytes; + unsigned int curbytes; + + unsigned int err_mask; + struct ata_taskfile result_tf; + + void *private_data; +#ifndef __U_BOOT__ + void *lldd_task; +#endif + unsigned char *pdata; +}; + +typedef void (*ata_qc_cb_t) (struct ata_queued_cmd *qc); + +#define ATA_TAG_POISON 0xfafbfcfdU + +enum { + LIBATA_MAX_PRD = ATA_MAX_PRD / 2, + LIBATA_DUMB_MAX_PRD = ATA_MAX_PRD / 4, + ATA_MAX_PORTS = 8, + ATA_DEF_QUEUE = 1, + ATA_MAX_QUEUE = 32, + ATA_TAG_INTERNAL = ATA_MAX_QUEUE - 1, + ATA_MAX_BUS = 2, + ATA_DEF_BUSY_WAIT = 10000, + + ATAPI_MAX_DRAIN = 16 << 10, + + ATA_SHT_EMULATED = 1, + ATA_SHT_CMD_PER_LUN = 1, + ATA_SHT_THIS_ID = -1, + ATA_SHT_USE_CLUSTERING = 1, + + ATA_DFLAG_LBA = (1 << 0), + ATA_DFLAG_LBA48 = (1 << 1), + ATA_DFLAG_CDB_INTR = (1 << 2), + ATA_DFLAG_NCQ = (1 << 3), + ATA_DFLAG_FLUSH_EXT = (1 << 4), + ATA_DFLAG_ACPI_PENDING = (1 << 5), + ATA_DFLAG_ACPI_FAILED = (1 << 6), + ATA_DFLAG_AN = (1 << 7), + ATA_DFLAG_HIPM = (1 << 8), + ATA_DFLAG_DIPM = (1 << 9), + ATA_DFLAG_DMADIR = (1 << 10), + ATA_DFLAG_CFG_MASK = (1 << 12) - 1, + + ATA_DFLAG_PIO = (1 << 12), + ATA_DFLAG_NCQ_OFF = (1 << 13), + ATA_DFLAG_SPUNDOWN = (1 << 14), + ATA_DFLAG_SLEEPING = (1 << 15), + ATA_DFLAG_DUBIOUS_XFER = (1 << 16), + ATA_DFLAG_INIT_MASK = (1 << 24) - 1, + + ATA_DFLAG_DETACH = (1 << 24), + ATA_DFLAG_DETACHED = (1 << 25), + + ATA_LFLAG_HRST_TO_RESUME = (1 << 0), + ATA_LFLAG_SKIP_D2H_BSY = (1 << 1), + ATA_LFLAG_NO_SRST = (1 << 2), + ATA_LFLAG_ASSUME_ATA = (1 << 3), + ATA_LFLAG_ASSUME_SEMB = (1 << 4), + ATA_LFLAG_ASSUME_CLASS = ATA_LFLAG_ASSUME_ATA | ATA_LFLAG_ASSUME_SEMB, + ATA_LFLAG_NO_RETRY = (1 << 5), + ATA_LFLAG_DISABLED = (1 << 6), + + ATA_FLAG_SLAVE_POSS = (1 << 0), + ATA_FLAG_SATA = (1 << 1), + ATA_FLAG_NO_LEGACY = (1 << 2), + ATA_FLAG_MMIO = (1 << 3), + ATA_FLAG_SRST = (1 << 4), + ATA_FLAG_SATA_RESET = (1 << 5), + ATA_FLAG_NO_ATAPI = (1 << 6), + ATA_FLAG_PIO_DMA = (1 << 7), + ATA_FLAG_PIO_LBA48 = (1 << 8), + ATA_FLAG_PIO_POLLING = (1 << 9), + ATA_FLAG_NCQ = (1 << 10), + ATA_FLAG_DEBUGMSG = (1 << 13), + ATA_FLAG_IGN_SIMPLEX = (1 << 15), + ATA_FLAG_NO_IORDY = (1 << 16), + ATA_FLAG_ACPI_SATA = (1 << 17), + ATA_FLAG_AN = (1 << 18), + ATA_FLAG_PMP = (1 << 19), + ATA_FLAG_IPM = (1 << 20), + + ATA_FLAG_DISABLED = (1 << 23), + + ATA_PFLAG_EH_PENDING = (1 << 0), + ATA_PFLAG_EH_IN_PROGRESS = (1 << 1), + ATA_PFLAG_FROZEN = (1 << 2), + ATA_PFLAG_RECOVERED = (1 << 3), + ATA_PFLAG_LOADING = (1 << 4), + ATA_PFLAG_UNLOADING = (1 << 5), + ATA_PFLAG_SCSI_HOTPLUG = (1 << 6), + ATA_PFLAG_INITIALIZING = (1 << 7), + ATA_PFLAG_RESETTING = (1 << 8), + ATA_PFLAG_SUSPENDED = (1 << 17), + ATA_PFLAG_PM_PENDING = (1 << 18), + + ATA_QCFLAG_ACTIVE = (1 << 0), + ATA_QCFLAG_DMAMAP = (1 << 1), + ATA_QCFLAG_IO = (1 << 3), + ATA_QCFLAG_RESULT_TF = (1 << 4), + ATA_QCFLAG_CLEAR_EXCL = (1 << 5), + ATA_QCFLAG_QUIET = (1 << 6), + + ATA_QCFLAG_FAILED = (1 << 16), + ATA_QCFLAG_SENSE_VALID = (1 << 17), + ATA_QCFLAG_EH_SCHEDULED = (1 << 18), + + ATA_HOST_SIMPLEX = (1 << 0), + ATA_HOST_STARTED = (1 << 1), + + ATA_TMOUT_BOOT = 30 * 100, + ATA_TMOUT_BOOT_QUICK = 7 * 100, + ATA_TMOUT_INTERNAL = 30 * 100, + ATA_TMOUT_INTERNAL_QUICK = 5 * 100, + + /* FIXME: GoVault needs 2s but we can't afford that without + * parallel probing. 800ms is enough for iVDR disk + * HHD424020F7SV00. Increase to 2secs when parallel probing + * is in place. + */ + ATA_TMOUT_FF_WAIT = 4 * 100 / 5, + + BUS_UNKNOWN = 0, + BUS_DMA = 1, + BUS_IDLE = 2, + BUS_NOINTR = 3, + BUS_NODATA = 4, + BUS_TIMER = 5, + BUS_PIO = 6, + BUS_EDD = 7, + BUS_IDENTIFY = 8, + BUS_PACKET = 9, + + PORT_UNKNOWN = 0, + PORT_ENABLED = 1, + PORT_DISABLED = 2, + + /* encoding various smaller bitmaps into a single + * unsigned long bitmap + */ + ATA_NR_PIO_MODES = 7, + ATA_NR_MWDMA_MODES = 5, + ATA_NR_UDMA_MODES = 8, + + ATA_SHIFT_PIO = 0, + ATA_SHIFT_MWDMA = ATA_SHIFT_PIO + ATA_NR_PIO_MODES, + ATA_SHIFT_UDMA = ATA_SHIFT_MWDMA + ATA_NR_MWDMA_MODES, + + ATA_DMA_PAD_SZ = 4, + + ATA_ERING_SIZE = 32, + + ATA_DEFER_LINK = 1, + ATA_DEFER_PORT = 2, + + ATA_EH_DESC_LEN = 80, + + ATA_EH_REVALIDATE = (1 << 0), + ATA_EH_SOFTRESET = (1 << 1), + ATA_EH_HARDRESET = (1 << 2), + ATA_EH_ENABLE_LINK = (1 << 3), + ATA_EH_LPM = (1 << 4), + + ATA_EH_RESET_MASK = ATA_EH_SOFTRESET | ATA_EH_HARDRESET, + ATA_EH_PERDEV_MASK = ATA_EH_REVALIDATE, + + ATA_EHI_HOTPLUGGED = (1 << 0), + ATA_EHI_RESUME_LINK = (1 << 1), + ATA_EHI_NO_AUTOPSY = (1 << 2), + ATA_EHI_QUIET = (1 << 3), + + ATA_EHI_DID_SOFTRESET = (1 << 16), + ATA_EHI_DID_HARDRESET = (1 << 17), + ATA_EHI_PRINTINFO = (1 << 18), + ATA_EHI_SETMODE = (1 << 19), + ATA_EHI_POST_SETMODE = (1 << 20), + + ATA_EHI_DID_RESET = ATA_EHI_DID_SOFTRESET | ATA_EHI_DID_HARDRESET, + ATA_EHI_RESET_MODIFIER_MASK = ATA_EHI_RESUME_LINK, + + ATA_EH_MAX_TRIES = 5, + + ATA_PROBE_MAX_TRIES = 3, + ATA_EH_DEV_TRIES = 3, + ATA_EH_PMP_TRIES = 5, + ATA_EH_PMP_LINK_TRIES = 3, + + SATA_PMP_SCR_TIMEOUT = 250, + + /* Horkage types. May be set by libata or controller on drives + (some horkage may be drive/controller pair dependant */ + + ATA_HORKAGE_DIAGNOSTIC = (1 << 0), + ATA_HORKAGE_NODMA = (1 << 1), + ATA_HORKAGE_NONCQ = (1 << 2), + ATA_HORKAGE_MAX_SEC_128 = (1 << 3), + ATA_HORKAGE_BROKEN_HPA = (1 << 4), + ATA_HORKAGE_SKIP_PM = (1 << 5), + ATA_HORKAGE_HPA_SIZE = (1 << 6), + ATA_HORKAGE_IPM = (1 << 7), + ATA_HORKAGE_IVB = (1 << 8), + ATA_HORKAGE_STUCK_ERR = (1 << 9), + + ATA_DMA_MASK_ATA = (1 << 0), + ATA_DMA_MASK_ATAPI = (1 << 1), + ATA_DMA_MASK_CFA = (1 << 2), + + ATAPI_READ = 0, + ATAPI_WRITE = 1, + ATAPI_READ_CD = 2, + ATAPI_PASS_THRU = 3, + ATAPI_MISC = 4, +}; + +enum ata_completion_errors { + AC_ERR_DEV = (1 << 0), + AC_ERR_HSM = (1 << 1), + AC_ERR_TIMEOUT = (1 << 2), + AC_ERR_MEDIA = (1 << 3), + AC_ERR_ATA_BUS = (1 << 4), + AC_ERR_HOST_BUS = (1 << 5), + AC_ERR_SYSTEM = (1 << 6), + AC_ERR_INVALID = (1 << 7), + AC_ERR_OTHER = (1 << 8), + AC_ERR_NODEV_HINT = (1 << 9), + AC_ERR_NCQ = (1 << 10), +}; + +enum ata_xfer_mask { + ATA_MASK_PIO = ((1LU << ATA_NR_PIO_MODES) - 1) << ATA_SHIFT_PIO, + ATA_MASK_MWDMA = ((1LU << ATA_NR_MWDMA_MODES) - 1) << ATA_SHIFT_MWDMA, + ATA_MASK_UDMA = ((1LU << ATA_NR_UDMA_MODES) - 1) << ATA_SHIFT_UDMA, +}; + +struct ata_port_info { +#ifndef __U_BOOT__ + struct scsi_host_template *sht; +#endif + unsigned long flags; + unsigned long link_flags; + unsigned long pio_mask; + unsigned long mwdma_mask; + unsigned long udma_mask; +#ifndef __U_BOOT__ + const struct ata_port_operations *port_ops; + void *private_data; +#endif +}; + +struct ata_ioports { + void __iomem *cmd_addr; + void __iomem *data_addr; + void __iomem *error_addr; + void __iomem *feature_addr; + void __iomem *nsect_addr; + void __iomem *lbal_addr; + void __iomem *lbam_addr; + void __iomem *lbah_addr; + void __iomem *device_addr; + void __iomem *status_addr; + void __iomem *command_addr; + void __iomem *altstatus_addr; + void __iomem *ctl_addr; +#ifndef __U_BOOT__ + void __iomem *bmdma_addr; +#endif + void __iomem *scr_addr; +}; + +struct ata_host { +#ifndef __U_BOOT__ + void __iomem * const *iomap; + void *private_data; + const struct ata_port_operations *ops; + unsigned long flags; + struct ata_port *simplex_claimed; +#endif + unsigned int n_ports; + struct ata_port *ports[0]; +}; + +#ifndef __U_BOOT__ +struct ata_port_stats { + unsigned long unhandled_irq; + unsigned long idle_irq; + unsigned long rw_reqbuf; +}; +#endif + +struct ata_device { + struct ata_link *link; + unsigned int devno; + unsigned long flags; + unsigned int horkage; +#ifndef __U_BOOT__ + struct scsi_device *sdev; +#ifdef CONFIG_ATA_ACPI + acpi_handle acpi_handle; + union acpi_object *gtf_cache; +#endif +#endif + u64 n_sectors; + unsigned int class; + + union { + u16 id[ATA_ID_WORDS]; + u32 gscr[SATA_PMP_GSCR_DWORDS]; + }; +#ifndef __U_BOOT__ + u8 pio_mode; + u8 dma_mode; + u8 xfer_mode; + unsigned int xfer_shift; +#endif + unsigned int multi_count; + unsigned int max_sectors; + unsigned int cdb_len; +#ifndef __U_BOOT__ + unsigned long pio_mask; + unsigned long mwdma_mask; +#endif + unsigned long udma_mask; + u16 cylinders; + u16 heads; + u16 sectors; +#ifndef __U_BOOT__ + int spdn_cnt; +#endif +}; + +enum dma_data_direction { + DMA_BIDIRECTIONAL = 0, + DMA_TO_DEVICE = 1, + DMA_FROM_DEVICE = 2, + DMA_NONE = 3, +}; + +struct ata_link { + struct ata_port *ap; + int pmp; + unsigned int active_tag; + u32 sactive; + unsigned int flags; + unsigned int hw_sata_spd_limit; +#ifndef __U_BOOT__ + unsigned int sata_spd_limit; + unsigned int sata_spd; + struct ata_device device[2]; +#endif +}; + +struct ata_port { + unsigned long flags; + unsigned int pflags; + unsigned int print_id; + unsigned int port_no; + + struct ata_ioports ioaddr; + + u8 ctl; + u8 last_ctl; + unsigned int pio_mask; + unsigned int mwdma_mask; + unsigned int udma_mask; + unsigned int cbl; + + struct ata_queued_cmd qcmd[ATA_MAX_QUEUE]; + unsigned long qc_allocated; + unsigned int qc_active; + int nr_active_links; + + struct ata_link link; +#ifndef __U_BOOT__ + int nr_pmp_links; + struct ata_link *pmp_link; +#endif + struct ata_link *excl_link; + int nr_pmp_links; +#ifndef __U_BOOT__ + struct ata_port_stats stats; + struct device *dev; + u32 msg_enable; +#endif + struct ata_host *host; + void *port_task_data; + + unsigned int hsm_task_state; + void *private_data; + unsigned char *pdata; +}; + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#endif diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 8c736ce..b69ce15 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -859,6 +859,9 @@ int mmc_init(struct mmc *mmc) if (err) return err; + mmc_set_bus_width(mmc, 1); + mmc_set_clock(mmc, 1); + /* Reset the Card */ err = mmc_go_idle(mmc); diff --git a/i386_config.mk b/i386_config.mk index 9e6d37d..5fe36d5 100644 --- a/i386_config.mk +++ b/i386_config.mk @@ -21,4 +21,6 @@ # MA 02111-1307 USA # +CROSS_COMPILE ?= i386-linux- + PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ diff --git a/include/compiler.h b/include/compiler.h new file mode 100644 index 0000000..272fd3c --- /dev/null +++ b/include/compiler.h @@ -0,0 +1,125 @@ +/* + * Keep all the ugly #ifdef for system stuff here + */ + +#ifndef __COMPILER_H__ +#define __COMPILER_H__ + +#include <stddef.h> + +#ifdef USE_HOSTCC + +#if defined(__BEOS__) || \ + defined(__NetBSD__) || \ + defined(__FreeBSD__) || \ + defined(__sun__) || \ + defined(__APPLE__) +# include <inttypes.h> +#elif defined(__linux__) || defined(__WIN32__) || defined(__MINGW32__) +# include <stdint.h> +#endif + +#include <errno.h> +#include <stdlib.h> +#include <stdint.h> +#include <stdio.h> +#include <string.h> + +extern int errno; + +#if !defined(__WIN32__) && !defined(__MINGW32__) +# include <sys/mman.h> +#endif + +/* Not all systems (like Windows) has this define, and yes + * we do replace/emulate mmap() on those systems ... + */ +#ifndef MAP_FAILED +# define MAP_FAILED ((void *)-1) +#endif + +#include <fcntl.h> +#ifndef O_BINARY /* should be define'd on __WIN32__ */ +#define O_BINARY 0 +#endif + +#ifdef __linux__ +# include <endian.h> +# include <byteswap.h> +#elif defined(__MACH__) +# include <machine/endian.h> +typedef unsigned long ulong; +typedef unsigned int uint; +#endif + +typedef uint8_t __u8; +typedef uint16_t __u16; +typedef uint32_t __u32; + +#define uswap_16(x) \ + ((((x) & 0xff00) >> 8) | \ + (((x) & 0x00ff) << 8)) +#define uswap_32(x) \ + ((((x) & 0xff000000) >> 24) | \ + (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0x0000ff00) << 8) | \ + (((x) & 0x000000ff) << 24)) +#define _uswap_64(x, sfx) \ + ((((x) & 0xff00000000000000##sfx) >> 56) | \ + (((x) & 0x00ff000000000000##sfx) >> 40) | \ + (((x) & 0x0000ff0000000000##sfx) >> 24) | \ + (((x) & 0x000000ff00000000##sfx) >> 8) | \ + (((x) & 0x00000000ff000000##sfx) << 8) | \ + (((x) & 0x0000000000ff0000##sfx) << 24) | \ + (((x) & 0x000000000000ff00##sfx) << 40) | \ + (((x) & 0x00000000000000ff##sfx) << 56)) +#if defined(__GNUC__) +# define uswap_64(x) _uswap_64(x, ull) +#else +# define uswap_64(x) _uswap_64(x, ) +#endif + +#if __BYTE_ORDER == __LITTLE_ENDIAN +# define cpu_to_le16(x) (x) +# define cpu_to_le32(x) (x) +# define cpu_to_le64(x) (x) +# define le16_to_cpu(x) (x) +# define le32_to_cpu(x) (x) +# define le64_to_cpu(x) (x) +# define cpu_to_be16(x) uswap_16(x) +# define cpu_to_be32(x) uswap_32(x) +# define cpu_to_be64(x) uswap_64(x) +# define be16_to_cpu(x) uswap_16(x) +# define be32_to_cpu(x) uswap_32(x) +# define be64_to_cpu(x) uswap_64(x) +#else +# define cpu_to_le16(x) uswap_16(x) +# define cpu_to_le32(x) uswap_32(x) +# define cpu_to_le64(x) uswap_64(x) +# define le16_to_cpu(x) uswap_16(x) +# define le32_to_cpu(x) uswap_32(x) +# define le64_to_cpu(x) uswap_64(x) +# define cpu_to_be16(x) (x) +# define cpu_to_be32(x) (x) +# define cpu_to_be64(x) (x) +# define be16_to_cpu(x) (x) +# define be32_to_cpu(x) (x) +# define be64_to_cpu(x) (x) +#endif + +#else /* !USE_HOSTCC */ + +#include <linux/string.h> +#include <linux/types.h> +#include <asm/byteorder.h> + +/* Types for `void *' pointers. */ +#if __WORDSIZE == 64 +typedef unsigned long int uintptr_t; +#else +typedef unsigned int uintptr_t; +#endif + +#endif + +#endif diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index c4acc05..6928981 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -315,15 +315,15 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 @@ -334,6 +334,8 @@ #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_83XX_GENERIC_PCI +#define CONFIG_83XX_PCI_STREAMING #undef CONFIG_EEPRO100 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -500,14 +502,14 @@ #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U #else @@ -536,9 +538,7 @@ /* * Environment Configuration - */ - -#define CONFIG_ENV_OVERWRITE + */ #define CONFIG_ENV_OVERWRITE #if defined(CONFIG_UEC_ETH) #define CONFIG_HAS_ETH0 diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 068df57..037cad5 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -382,6 +382,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_83XX_GENERIC_PCI #ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR 0x00000000 diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 60c9968..028ef8c 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -350,15 +350,15 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 @@ -369,6 +369,8 @@ #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_83XX_GENERIC_PCI +#define CONFIG_83XX_PCI_STREAMING #undef CONFIG_EEPRO100 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -539,14 +541,14 @@ #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U #else diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h index 8a197ad..76ca916 100644 --- a/include/configs/NETPHONE.h +++ b/include/configs/NETPHONE.h @@ -120,7 +120,6 @@ */ #include <config_cmd_default.h> -#define CONFIG_CMD_NAND #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_MII diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h index dda6179..4f9f9fe 100644 --- a/include/configs/NETTA.h +++ b/include/configs/NETTA.h @@ -134,7 +134,6 @@ #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MII -#define CONFIG_CMD_NAND #define CONFIG_CMD_NFS #define CONFIG_CMD_PCMCIA #define CONFIG_CMD_PING diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h index 167285e..d060cb7 100644 --- a/include/configs/NETTA2.h +++ b/include/configs/NETTA2.h @@ -121,7 +121,6 @@ */ #include <config_cmd_default.h> -#define CONFIG_CMD_NAND #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_MII diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h index b9cf621..a18b480 100644 --- a/include/configs/NETVIA.h +++ b/include/configs/NETVIA.h @@ -107,7 +107,7 @@ #define CONFIG_CMD_PING #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 -#define CONFIG_CMD_NAND +/* #define CONFIG_CMD_NAND */ /* disabled */ #endif diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index efade69..541a27b 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -247,12 +247,16 @@ extern int tqm834x_num_flash_banks; #if defined(CONFIG_PCI) #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_83XX_GENERIC_PCI #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ /* PCI1 host bridge */ -#define CONFIG_SYS_PCI1_MEM_BASE 0xc0000000 +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ @@ -418,10 +422,10 @@ extern int tqm834x_num_flash_banks; #ifdef CONFIG_PCI #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE | BATU_BL_16M | BATU_VS | BATU_VP) #else #define CONFIG_SYS_IBAT3L (0) #define CONFIG_SYS_IBAT3U (0) diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index 48c5198..d22d411 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -453,6 +453,7 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_NAND #define CONFIG_CMD_PCI +#define CONFIG_CMD_SATA #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SNTP #define CONFIG_CMD_USB @@ -518,6 +519,19 @@ #endif /* CONFIG_ARCHES */ #endif /* CONFIG_460GT */ +/* + * SATA driver setup + */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_SATA_DWC +#define CONFIG_LIBATA +#define SATA_BASE_ADDR 0xe20d1000 /* PPC460EX SATA Base Address */ +#define SATA_DMA_REG_ADDR 0xe20d0800 /* PPC460EX SATA Base Address */ +#define CONFIG_SYS_SATA_MAX_DEVICE 1 /* SATA MAX DEVICE */ +/* Convert sectorsize to wordsize */ +#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2) +#endif + /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h index 558010f..6ccebfa 100644 --- a/include/configs/digsy_mtc.h +++ b/include/configs/digsy_mtc.h @@ -272,6 +272,7 @@ */ #define CONFIG_SYS_LONGHELP #define CONFIG_AUTO_COMPLETE 1 +#define CONFIG_CMDLINE_EDITING 1 #define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 84a251a..20dcd1c 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -329,6 +329,7 @@ #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_83XX_GENERIC_PCI #undef CONFIG_EEPRO100 #undef CONFIG_TULIP diff --git a/include/elf.h b/include/elf.h index f640388..29f276d 100644 --- a/include/elf.h +++ b/include/elf.h @@ -33,15 +33,7 @@ #ifndef _ELF_H #define _ELF_H -#if defined(__BEOS__) || \ - defined(__NetBSD__) || \ - defined(__FreeBSD__) || \ - defined(__sun__) || \ - defined(__APPLE__) -#include <inttypes.h> -#elif (defined(__linux__) && defined(USE_HOSTCC)) || defined(__WIN32__) -#include <stdint.h> -#endif +#include "compiler.h" /* * This version doesn't work for 64-bit ABIs - Erik. diff --git a/include/environment.h b/include/environment.h index 507e832..5bed32f 100644 --- a/include/environment.h +++ b/include/environment.h @@ -96,11 +96,7 @@ # endif #endif /* CONFIG_ENV_IS_IN_MG_DISK */ -#ifdef USE_HOSTCC -# include <stdint.h> -#else -# include <linux/types.h> -#endif +#include "compiler.h" #ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT # define ENV_HEADER_SIZE (sizeof(uint32_t) + 1) diff --git a/include/image.h b/include/image.h index f183757..beb3a16 100644 --- a/include/image.h +++ b/include/image.h @@ -33,10 +33,9 @@ #ifndef __IMAGE_H__ #define __IMAGE_H__ -#if USE_HOSTCC -#ifndef __MINGW32__ -#include <endian.h> -#endif +#include "compiler.h" + +#ifdef USE_HOSTCC /* new uImage format support enabled on host */ #define CONFIG_FIT 1 @@ -46,9 +45,7 @@ #else #include <lmb.h> -#include <linux/string.h> #include <asm/u-boot.h> -#include <asm/byteorder.h> #endif /* USE_HOSTCC */ @@ -284,8 +281,8 @@ typedef struct bootm_headers { #define CHUNKSZ_SHA1 (64 * 1024) #endif -#define uimage_to_cpu(x) ntohl(x) -#define cpu_to_uimage(x) htonl(x) +#define uimage_to_cpu(x) be32_to_cpu(x) +#define cpu_to_uimage(x) cpu_to_be32(x) const char *genimg_get_os_name (uint8_t os); const char *genimg_get_arch_name (uint8_t arch); diff --git a/include/libfdt_env.h b/include/libfdt_env.h index 1c67015..bf63583 100644 --- a/include/libfdt_env.h +++ b/include/libfdt_env.h @@ -21,56 +21,13 @@ #ifndef _LIBFDT_ENV_H #define _LIBFDT_ENV_H -#ifdef USE_HOSTCC -#include <stdint.h> -#include <string.h> -#ifdef __MINGW32__ -#include <linux/types.h> -#include <linux/byteorder/swab.h> -#else -#include <endian.h> -#include <byteswap.h> -#endif /* __MINGW32__ */ -#else -#include <linux/string.h> -#include <linux/types.h> -#include <asm/byteorder.h> -#endif /* USE_HOSTCC */ +#include "compiler.h" -#include <stddef.h> extern struct fdt_header *working_fdt; /* Pointer to the working fdt */ -#if __BYTE_ORDER == __LITTLE_ENDIAN -#ifdef __MINGW32__ -#define fdt32_to_cpu(x) ___swab32(x) -#define cpu_to_fdt32(x) ___swab32(x) -#define fdt64_to_cpu(x) ___swab64(x) -#define cpu_to_fdt64(x) ___swab64(x) -#else -#define fdt32_to_cpu(x) bswap_32(x) -#define cpu_to_fdt32(x) bswap_32(x) -#define fdt64_to_cpu(x) bswap_64(x) -#define cpu_to_fdt64(x) bswap_64(x) -#endif -#else -#define fdt32_to_cpu(x) (x) -#define cpu_to_fdt32(x) (x) -#define fdt64_to_cpu(x) (x) -#define cpu_to_fdt64(x) (x) -#endif - -#ifndef USE_HOSTCC -/* - * Types for `void *' pointers. - * - * Note: libfdt uses this definition from /usr/include/stdint.h. - * Define it here rather than pulling in all of stdint.h. - */ -#if __WORDSIZE == 64 -typedef unsigned long int uintptr_t; -#else -typedef unsigned int uintptr_t; -#endif -#endif /* not USE_HOSTCC */ +#define fdt32_to_cpu(x) be32_to_cpu(x) +#define cpu_to_fdt32(x) cpu_to_be32(x) +#define fdt64_to_cpu(x) be64_to_cpu(x) +#define cpu_to_fdt64(x) cpu_to_be64(x) #endif /* _LIBFDT_ENV_H */ diff --git a/include/malloc.h b/include/malloc.h index 47154b0..a38464e 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -216,7 +216,8 @@ */ - +#ifndef __MALLOC_H__ +#define __MALLOC_H__ /* Preliminaries */ @@ -940,3 +941,5 @@ struct mallinfo mALLINFo(); #ifdef __cplusplus }; /* end of extern "C" */ #endif + +#endif /* __MALLOC_H__ */ diff --git a/include/tsi148.h b/include/tsi148.h new file mode 100644 index 0000000..8e8e12b --- /dev/null +++ b/include/tsi148.h @@ -0,0 +1,218 @@ +/* + * (C) Copyright 2009 Reinhard Arlt, reinhard.arlt@esd-electronics.com + * + * base on universe.h by + * + * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _tsi148_h +#define _tsi148_h + +#ifndef PCI_DEVICE_ID_TUNDRA_TSI148 +#define PCI_DEVICE_ID_TUNDRA_TSI148 0x0148 +#endif + +typedef struct _TSI148 TSI148; +typedef struct _OUTBOUND OUTBOUND; +typedef struct _INBOUND INBOUND; +typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET; + +struct _OUTBOUND { + unsigned int otsau; /* 0x000 Outbound start upper */ + unsigned int otsal; /* 0x004 Outbouud start lower */ + unsigned int oteau; /* 0x008 Outbound end upper */ + unsigned int oteal; /* 0x00c Outbound end lower */ + unsigned int otofu; /* 0x010 Outbound translation upper */ + unsigned int otofl; /* 0x014 Outbound translation lower */ + unsigned int otbs; /* 0x018 Outbound translation 2eSST */ + unsigned int otat; /* 0x01c Outbound translation attr */ +}; + +struct _INBOUND { + unsigned int itsau; /* 0x000 inbound start upper */ + unsigned int itsal; /* 0x004 inbouud start lower */ + unsigned int iteau; /* 0x008 inbound end upper */ + unsigned int iteal; /* 0x00c inbound end lower */ + unsigned int itofu; /* 0x010 inbound translation upper */ + unsigned int itofl; /* 0x014 inbound translation lower */ + unsigned int itat; /* 0x018 inbound translation attr */ + unsigned int spare; /* 0x01c not used */ +}; + +struct _TSI148 { + unsigned int pci_id; /* 0x000 */ + unsigned int pci_csr; /* 0x004 */ + unsigned int pci_class; /* 0x008 */ + unsigned int pci_misc0; /* 0x00c */ + unsigned int pci_mbarl; /* 0x010 */ + unsigned int pci_mbarh; /* 0x014 */ + unsigned int spare0[(0x03c-0x018)/4]; /* 0x018 */ + unsigned int pci_misc1; /* 0x03c */ + unsigned int pci_pcixcap; /* 0x040 */ + unsigned int pci_pcixstat; /* 0x044 */ + unsigned int spare1[(0x100-0x048)/4]; /* 0x048 */ + OUTBOUND outbound[8]; /* 0x100 */ + unsigned int viack[8]; /* 0x204 */ + unsigned int rmwau; /* 0x220 */ + unsigned int rmwal; /* 0x224 */ + unsigned int rmwen; /* 0x228 */ + unsigned int rmwc; /* 0x22c */ + unsigned int rmws; /* 0x230 */ + unsigned int vmctrl; /* 0x234 */ + unsigned int vctrl; /* 0x238 */ + unsigned int vstat; /* 0x23c */ + unsigned int pcsr; /* 0x240 */ + unsigned int spare2[3]; /* 0x244 - 0x24c */ + unsigned int vmefl; /* 0x250 */ + unsigned int spare3[3]; /* 0x254 - 0x25c */ + unsigned int veau; /* 0x260 */ + unsigned int veal; /* 0x264 */ + unsigned int veat; /* 0x268 */ + unsigned int spare4[1]; /* 0x26c */ + unsigned int edpau; /* 0x270 */ + unsigned int edpal; /* 0x274 */ + unsigned int edpxa; /* 0x278 */ + unsigned int edpxs; /* 0x27c */ + unsigned int edpat; /* 0x280 */ + unsigned int spare5[31]; /* 0x284 - 0x2fc */ + INBOUND inbound[8]; /* 0x100 */ + unsigned int gbau; /* 0x400 */ + unsigned int gbal; /* 0x404 */ + unsigned int gcsrat; /* 0x408 */ + unsigned int cbau; /* 0x40c */ + unsigned int cbal; /* 0x410 */ + unsigned int crgat; /* 0x414 */ + unsigned int crou; /* 0x418 */ + unsigned int crol; /* 0x41c */ + unsigned int crat; /* 0x420 */ + unsigned int lmbau; /* 0x424 */ + unsigned int lmbal; /* 0x428 */ + unsigned int lmat; /* 0x42c */ + unsigned int r64bcu; /* 0x430 */ + unsigned int r64bcl; /* 0x434 */ + unsigned int bpgtr; /* 0x438 */ + unsigned int bpctr; /* 0x43c */ + unsigned int vicr; /* 0x440 */ + unsigned int spare6[1]; /* 0x444 */ + unsigned int inten; /* 0x448 */ + unsigned int inteo; /* 0x44c */ + unsigned int ints; /* 0x450 */ + unsigned int intc; /* 0x454 */ + unsigned int intm1; /* 0x458 */ + unsigned int intm2; /* 0x45c */ + unsigned int spare7[40]; /* 0x460 - 0x4fc */ + unsigned int dctl0; /* 0x500 */ + unsigned int dsta0; /* 0x504 */ + unsigned int dcsau0; /* 0x508 */ + unsigned int dcsal0; /* 0x50c */ + unsigned int dcdau0; /* 0x510 */ + unsigned int dcdal0; /* 0x514 */ + unsigned int dclau0; /* 0x518 */ + unsigned int dclal0; /* 0x51c */ + unsigned int dsau0; /* 0x520 */ + unsigned int dsal0; /* 0x524 */ + unsigned int ddau0; /* 0x528 */ + unsigned int ddal0; /* 0x52c */ + unsigned int dsat0; /* 0x530 */ + unsigned int ddat0; /* 0x534 */ + unsigned int dnlau0; /* 0x538 */ + unsigned int dnlal0; /* 0x53c */ + unsigned int dcnt0; /* 0x540 */ + unsigned int ddbs0; /* 0x544 */ + unsigned int r20[14]; /* 0x548 - 0x57c */ + unsigned int dctl1; /* 0x580 */ + unsigned int dsta1; /* 0x584 */ + unsigned int dcsau1; /* 0x588 */ + unsigned int dcsal1; /* 0x58c */ + unsigned int dcdau1; /* 0x590 */ + unsigned int dcdal1; /* 0x594 */ + unsigned int dclau1; /* 0x598 */ + unsigned int dclal1; /* 0x59c */ + unsigned int dsau1; /* 0x5a0 */ + unsigned int dsal1; /* 0x5a4 */ + unsigned int ddau1; /* 0x5a8 */ + unsigned int ddal1; /* 0x5ac */ + unsigned int dsat1; /* 0x5b0 */ + unsigned int ddat1; /* 0x5b4 */ + unsigned int dnlau1; /* 0x5b8 */ + unsigned int dnlal1; /* 0x5bc */ + unsigned int dcnt1; /* 0x5c0 */ + unsigned int ddbs1; /* 0x5c4 */ + unsigned int r21[14]; /* 0x5c8 - 0x5fc */ + unsigned int devi_veni_2; /* 0x600 */ + unsigned int gctrl_ga_revid; /* 0x604 */ + unsigned int semaphore0_1_2_3; /* 0x608 */ + unsigned int semaphore4_5_6_7; /* 0x60c */ + unsigned int mbox0; /* 0x610 */ + unsigned int mbox1; /* 0x614 */ + unsigned int mbox2; /* 0x618 */ + unsigned int mbox3; /* 0x61c */ + unsigned int r22[629]; /* 0x620 - 0xff0 */ + unsigned int csrbcr; /* 0xff4 */ + unsigned int csrbsr; /* 0xff8 */ + unsigned int cbar; /* 0xffc */ +}; + +#define IRQ_VOWN 0x0001 +#define IRQ_VIRQ1 0x0002 +#define IRQ_VIRQ2 0x0004 +#define IRQ_VIRQ3 0x0008 +#define IRQ_VIRQ4 0x0010 +#define IRQ_VIRQ5 0x0020 +#define IRQ_VIRQ6 0x0040 +#define IRQ_VIRQ7 0x0080 +#define IRQ_DMA 0x0100 +#define IRQ_LERR 0x0200 +#define IRQ_VERR 0x0400 +#define IRQ_res 0x0800 +#define IRQ_IACK 0x1000 +#define IRQ_SWINT 0x2000 +#define IRQ_SYSFAIL 0x4000 +#define IRQ_ACFAIL 0x8000 + +struct _TDMA_CMD_PACKET { + unsigned int dctl; /* DMA Control */ + unsigned int dtbc; /* Transfer Byte Count */ + unsigned int dlv; /* PCI Address */ + unsigned int res1; /* Reserved */ + unsigned int dva; /* Vme Address */ + unsigned int res2; /* Reserved */ + unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */ + unsigned int res3; /* Reserved */ +}; + +#define VME_AM_A16 0x01 +#define VME_AM_A24 0x02 +#define VME_AM_A32 0x03 +#define VME_AM_Axx 0x03 +#define VME_AM_USR 0x04 +#define VME_AM_SUP 0x08 +#define VME_AM_DATA 0x10 +#define VME_AM_PROG 0x20 +#define VME_AM_Mxx (VME_AM_DATA | VME_AM_PROG) + +#define VME_FLAG_D8 0x01 +#define VME_FLAG_D16 0x02 +#define VME_FLAG_D32 0x03 +#define VME_FLAG_Dxx 0x03 + +#endif diff --git a/include/u-boot/md5.h b/include/u-boot/md5.h index 8b44a7f..08924cc 100644 --- a/include/u-boot/md5.h +++ b/include/u-boot/md5.h @@ -6,7 +6,7 @@ #ifndef _MD5_H #define _MD5_H -#include <linux/types.h> +#include "compiler.h" struct MD5Context { __u32 buf[4]; diff --git a/lib_generic/md5.c b/lib_generic/md5.c index 9150510..81a09e3 100644 --- a/lib_generic/md5.c +++ b/lib_generic/md5.c @@ -25,14 +25,12 @@ and to fit the cifs vfs by Steve French sfrench@us.ibm.com */ +#include "compiler.h" + #ifndef USE_HOSTCC #include <common.h> -#include <linux/string.h> -#else -#include <string.h> -#endif /* USE_HOSTCC */ #include <watchdog.h> -#include <linux/types.h> +#endif /* USE_HOSTCC */ #include <u-boot/md5.h> static void diff --git a/m68k_config.mk b/m68k_config.mk index 12bd27c..f41d1b3 100644 --- a/m68k_config.mk +++ b/m68k_config.mk @@ -21,5 +21,7 @@ # MA 02111-1307 USA # +CROSS_COMPILE ?= m68k-elf- + PLATFORM_CPPFLAGS += -DCONFIG_M68K -D__M68K__ PLATFORM_LDFLAGS += -n diff --git a/microblaze_config.mk b/microblaze_config.mk index e44c79e..68e7e21 100644 --- a/microblaze_config.mk +++ b/microblaze_config.mk @@ -24,4 +24,6 @@ # MA 02111-1307 USA # +CROSS_COMPILE ?= mb- + PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__ diff --git a/mips_config.mk b/mips_config.mk index 05eb05d..c785677 100644 --- a/mips_config.mk +++ b/mips_config.mk @@ -21,6 +21,8 @@ # MA 02111-1307 USA # +CROSS_COMPILE ?= mips_4KC- + PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ # diff --git a/nios2_config.mk b/nios2_config.mk index 3f23b56..59931c2 100644 --- a/nios2_config.mk +++ b/nios2_config.mk @@ -22,5 +22,7 @@ # MA 02111-1307 USA # +CROSS_COMPILE ?= nios2-elf- + PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__ PLATFORM_CPPFLAGS += -ffixed-r15 -G0 diff --git a/nios_config.mk b/nios_config.mk index 1cf0f32..3ed7170 100644 --- a/nios_config.mk +++ b/nios_config.mk @@ -22,4 +22,6 @@ # MA 02111-1307 USA # +CROSS_COMPILE ?= nios-elf- + PLATFORM_CPPFLAGS += -m32 -DCONFIG_NIOS -D__NIOS__ -ffixed-g7 -gstabs diff --git a/ppc_config.mk b/ppc_config.mk index c95b3b1..d91ef7f 100644 --- a/ppc_config.mk +++ b/ppc_config.mk @@ -21,6 +21,8 @@ # MA 02111-1307 USA # +CROSS_COMPILE ?= ppc_8xx- + PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ PLATFORM_LDFLAGS += -n diff --git a/sh_config.mk b/sh_config.mk index 407e076..67d7e9e 100644 --- a/sh_config.mk +++ b/sh_config.mk @@ -21,6 +21,8 @@ # MA 02111-1307 USA # +CROSS_COMPILE ?= sh4-linux- + PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__ PLATFORM_LDFLAGS += -e $(TEXT_BASE) --defsym reloc_dst=$(TEXT_BASE) diff --git a/sparc_config.mk b/sparc_config.mk index 87f745f..07b528c 100644 --- a/sparc_config.mk +++ b/sparc_config.mk @@ -21,4 +21,6 @@ # MA 02111-1307 USA # +CROSS_COMPILE ?= sparc-elf- + PLATFORM_CPPFLAGS += -DCONFIG_SPARC -D__sparc__ diff --git a/tools/bmp_logo.c b/tools/bmp_logo.c index e8dd8c8..47228d2 100644 --- a/tools/bmp_logo.c +++ b/tools/bmp_logo.c @@ -1,15 +1,4 @@ -#include <stdio.h> -#include <stdlib.h> - -#if defined(__linux__) -#include <stdint.h> -#else -#ifdef __CYGWIN__ -#include "elf.h" -#else -#include <inttypes.h> -#endif -#endif +#include "compiler.h" typedef struct bitmap_s { /* bitmap description */ uint16_t width; diff --git a/tools/img2srec.c b/tools/img2srec.c index b04abbd..f10379f 100644 --- a/tools/img2srec.c +++ b/tools/img2srec.c @@ -52,6 +52,7 @@ | INCLUDES |*************************************************************************/ +#include "os_support.h" #include <stddef.h> #include <stdio.h> #include <stdlib.h> @@ -61,8 +62,6 @@ #include <unistd.h> #include <errno.h> -extern int errno; - /************************************************************************* | DEFINES |*************************************************************************/ diff --git a/tools/mingw_support.h b/tools/mingw_support.h index 1fb6c93..9e45e64 100644 --- a/tools/mingw_support.h +++ b/tools/mingw_support.h @@ -34,9 +34,6 @@ #define MAP_SHARED 0x01 /* Share changes */ #define MAP_PRIVATE 0x02 /* Changes are private */ -/* Return value of `mmap' in case of an error */ -#define MAP_FAILED ((void *) -1) - /* Windows 64-bit access macros */ #define LODWORD(x) ((DWORD)((DWORDLONG)(x))) #define HIDWORD(x) ((DWORD)(((DWORDLONG)(x) >> 32) & 0xffffffff)) diff --git a/tools/mkimage.c b/tools/mkimage.c index 967fe9a..02cdb95 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -25,12 +25,6 @@ #include "mkimage.h" #include <image.h> -extern int errno; - -#ifndef MAP_FAILED -#define MAP_FAILED (void *)(-1) -#endif - extern unsigned long crc32 (unsigned long crc, const char *buf, unsigned int len); static void copy_file (int, const char *, int); static void usage (void); @@ -502,7 +496,7 @@ image_verify_header (char *ptr, int image_size) */ memcpy (hdr, ptr, sizeof(image_header_t)); - if (ntohl(hdr->ih_magic) != IH_MAGIC) { + if (be32_to_cpu(hdr->ih_magic) != IH_MAGIC) { fprintf (stderr, "%s: Bad Magic Number: \"%s\" is no valid image\n", cmdname, imagefile); @@ -512,8 +506,8 @@ image_verify_header (char *ptr, int image_size) data = (char *)hdr; len = sizeof(image_header_t); - checksum = ntohl(hdr->ih_hcrc); - hdr->ih_hcrc = htonl(0); /* clear for re-calculation */ + checksum = be32_to_cpu(hdr->ih_hcrc); + hdr->ih_hcrc = cpu_to_be32(0); /* clear for re-calculation */ if (crc32 (0, data, len) != checksum) { fprintf (stderr, @@ -525,7 +519,7 @@ image_verify_header (char *ptr, int image_size) data = ptr + sizeof(image_header_t); len = image_size - sizeof(image_header_t) ; - if (crc32 (0, data, len) != ntohl(hdr->ih_dcrc)) { + if (crc32 (0, data, len) != be32_to_cpu(hdr->ih_dcrc)) { fprintf (stderr, "%s: ERROR: \"%s\" has corrupted data!\n", cmdname, imagefile); diff --git a/tools/mkimage.h b/tools/mkimage.h index c8df6e1..70c53ad 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -26,14 +26,6 @@ #include <stdio.h> #include <stdlib.h> #include <string.h> -#ifndef __WIN32__ -#include <netinet/in.h> /* for host / network byte order conversions */ -#endif -#ifdef __MINGW32__ -#include <stdint.h> -#else -#include <sys/mman.h> -#endif #include <sys/stat.h> #include <time.h> #include <unistd.h> @@ -53,28 +45,3 @@ #define MKIMAGE_DEFAULT_DTC_OPTIONS "-I dts -O dtb -p 500" #define MKIMAGE_MAX_DTC_CMDLINE_LEN 512 #define MKIMAGE_DTC "dtc" /* assume dtc is in $PATH */ - -#if defined(__BEOS__) || defined(__NetBSD__) || defined(__APPLE__) -#include <inttypes.h> -#endif - -#ifdef __WIN32__ -typedef unsigned int __u32; - -#define SWAP_LONG(x) \ - ((__u32)( \ - (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \ - (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ - (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ - (((__u32)(x) & (__u32)0xff000000UL) >> 24) )) -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -typedef unsigned int uint32_t; - -#define ntohl(a) SWAP_LONG(a) -#define htonl(a) SWAP_LONG(a) -#endif /* __WIN32__ */ - -#ifndef O_BINARY /* should be define'd on __WIN32__ */ -#define O_BINARY 0 -#endif diff --git a/tools/os_support.c b/tools/os_support.c index 001fe64..5b919aa 100644 --- a/tools/os_support.c +++ b/tools/os_support.c @@ -19,6 +19,7 @@ /* * Include additional files required for supporting different operating systems */ +#include "compiler.h" #ifdef __MINGW32__ #include "mingw_support.c" #endif diff --git a/tools/os_support.h b/tools/os_support.h index f6f86b0..7bf930e 100644 --- a/tools/os_support.h +++ b/tools/os_support.h @@ -19,6 +19,8 @@ #ifndef __OS_SUPPORT_H_ #define __OS_SUPPORT_H_ +#include "compiler.h" + /* * Include additional files required for supporting different operating systems */ diff --git a/tools/ubsha1.c b/tools/ubsha1.c index c4203ed..9774eea 100644 --- a/tools/ubsha1.c +++ b/tools/ubsha1.c @@ -28,9 +28,6 @@ #include <fcntl.h> #include <errno.h> #include <string.h> -#ifndef __MINGW32__ -#include <sys/mman.h> -#endif #include <sys/stat.h> #include "sha1.h" @@ -40,16 +37,6 @@ #include <config.h> #undef __ASSEMBLY__ -#ifndef O_BINARY /* should be define'd on __WIN32__ */ -#define O_BINARY 0 -#endif - -#ifndef MAP_FAILED -#define MAP_FAILED (-1) -#endif - -extern int errno; - extern void sha1_csum (unsigned char *input, int ilen, unsigned char output[20]); int main (int argc, char **argv) |