diff options
| -rw-r--r-- | board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg | 3 | ||||
| -rw-r--r-- | board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg | 3 | ||||
| -rw-r--r-- | board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S | 13 |
3 files changed, 17 insertions, 2 deletions
diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg b/board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg index 3c4ace4..c0da271 100644 --- a/board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg @@ -51,6 +51,9 @@ CSF CONFIG_CSF_SIZE */ DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 DATA 4 0x30391000 0x00000002 DATA 4 0x307a0000 0x03040008 diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg b/board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg index 00a74f7..e38c44c 100644 --- a/board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg @@ -51,6 +51,9 @@ CSF CONFIG_CSF_SIZE */ DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 DATA 4 0x30391000 0x00000002 DATA 4 0x307a0000 0x03040008 diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S b/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S index a097799..aaf65c2 100644 --- a/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S @@ -85,7 +85,7 @@ TUNE_END: /* turn on ddr power */ ldr r7, =(0x1 << 29) - str r7, [r1, #0x380] + str r7, [r1, #0x388] ldr r6, =50 1: @@ -246,8 +246,11 @@ TUNE_END: bic r7, r7, #(1 << 29) str r7, [r11] 2: + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ ldr r7, =(0x1 << 30) - str r7, [r1, #0x380] + str r7, [r1, #0x388] + ldr r7, =(0x1 << 30) + str r7, [r1, #0x384] /* need to delay ~5mS */ ldr r6, =0x100000 @@ -414,6 +417,12 @@ TUNE_END: ldr r1, =0x4f400005 str r1, [r0, #0x4] + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =(0x1 << 30) + str r1, [r0, #0x388] + str r1, [r0, #0x384] + ldr r0, =SRC_BASE_ADDR ldr r1, =0x2 ldr r2, =0x1000 |