diff options
332 files changed, 35532 insertions, 6404 deletions
@@ -5,7 +5,286 @@ Changes since U-Boot 1.1.4: * Added PCI support for MPC8349ADS board Patch by Kumar Gala 11 Jan 2006 -* Add support for 28F256J3A flah (=> 64 MB) on PM520 board +* Enable address translation on MPC83xx + Patch by Kumar Gala, 10 Feb 2006 + +* Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xx + Patch by Kumar Gala, 25 Jan 2006 + +* Fixed defines for MPC83xx SICRL register to match current specs + Patch by Kumar Gala, 23 Jan 2006 + +* Only disable the MPC83xx watchdog if its enabled out of reset. + If its disabled out of reset SW can later enable it if so desired + Patch by Kumar Gala, 11 Jan 2006 + +* Allow config of GPIO direction & data registers at boot on 83xx + Patch by Kumar Gala, 11 Jan 2006 + +* Enable time handling on 83xx + Patch by Kumar Gala, 11 Jan 2006 + +* Make System IO Config Registers board configurable on MPC83xx + Patch by Kumar Gala, 11 Jan 2006 + +* Fixed PCI indirect config ops to handle multiple PCI controllers + We need to adjust the bus number we are trying to access based + on which PCI controller its on + Patch by Kumar Gala, 12 Jan 2006 + +* Report back PCI bus when doing table based device config + Patch by Kumar Gala, 11 Jan 2006 + +* Added support for PCI prefetchable region and BARs + If a host controller sets up a region as prefetchable and + a device's BAR denotes it as prefetchable, allocate the + BAR into the prefetch region. + + If a BAR is prefetchable and no prefetchable region has + been setup by the controller we fall back to allocating + the BAR into the normally memory region. + Patch by Kumar Gala, 11 Jan 2006 + +* Add helper function for generic flat device tree fixups for mpc83xx + Patch by Kumar Gala, 11 Jan 2006 + +* Add support for passing initrd information via flat device tree + Patch by Kumar Gala, 11 Jan 2006 + +* Added OF_STDOUT_PATH and OF_SOC + + OF_STDOUT_PATH specifies the path to the device the kernel can use + for console output + + OF_SOC specifies the proper name of the SOC node if one exists. + Patch by Kumar Gala, 11 Jan 2006 + +* Allow board code to fixup the flat device tree before booting a kernel + Patch by Kumar Gala, 11 Jan 2006 + +* Added CONFIG_ options for bd_t and env in flat dev tree + + CONFIG_OF_HAS_BD_T will put a copy of the bd_t + into the resulting flat device tree. + + CONFIG_OF_HAS_UBOOT_ENV will copy the environment + variables from u-boot into the flat device tree + + Patch by Kumar Gala, 11 Jan 2006 + +* Add support for the DHCP vendor optional bootfile (#67). + Ignores the vendor TFTP server name option (#66). + Patch by Murray Jensen, 30 Jun 2005 + +* Fix a HW timing issue on 8548 CDS for eTSEC 3 in RGMII mode + Patch by Andy Fleming, 14 Jun 2005 + +* Fix bad register definitions for LTX971 PHY on MPC85xx boards. + Patch by Gerhard Jaeger, 21 Jun 2005 + +* Add netconsole and some more commands to RPXlite_DW board + Patch by Sam Song, 19 Jun 2005 + +* Fix bad declaration on pci_cfgfunc_nothing + Patch by Sam Song, 19 Jun 2005 + +* Adjust "echo" as a default command + Patch by Sam Song, 19 Jun 2005 + +* Fix PCIDF calculation in cpu/mpc8260/speed.c for MPC8280EC + Patch by KokHow Teh, 16 Jun 2005 + +* Add crc of data to jffs2 (in jffs2_1pass_build_lists()). + Patch by Rick Bronson, 15 Jun 2005 + +* Coding Style cleanup + +* Avoid dereferencing NULL in find_cmd() if no valid commands were found + Patch by Andrew Dyer, 13 Jun 2005 + +* Add ADI Blackfin support + - add support for Analog Devices Blackfin BF533 CPU + - add support for the ADI BF533 Stamp uClinux board + - add support for the ADI BF533 EZKit board + Patches by Richard Klingler, 11 Jun 2005 + +* Add loads of ntohl() in image header handling + Patch by Steven Scholz, 10 Jun 2005 + +* Switch MPC86xADS and MPC885ADS boards to use cpuclk environment + variable to set clock + Patch by Yuli Barcohen, 05 Jun 2005 + +* RPXlite configuration fixes + - Use correct flash sector size + - Use correct memory test end address + - Add support for bzip2 compression + - Various small fixes + Patch by Yuli Barcohen, 05 Jun 2005 + +* Memory configuration changes for ZPC.1900 board + - Fix SDRAM timing on both local bus and 60x bus + - Add support for second flash bank (SIMM) + - Change boot flash base + Patch by Yuli Barcohen, 05 Jun 2005 + +* Add support for Adder boards with 16MB SDRAM; + add support for second FEC on Adder87x board. + Patch by Yuli Barcohen, 05 Jun 2005 + +* Fix conditional for including ks8695eth driver + Patch by Greg Ungerer, 04 Jun 2005 + +* Fix Makefile: include config.mk only after CROSS_COMPILE is defined + Patch by Friedrich Lobenstock, 02 Jun 2005 + +* Fix comment in common/soft_i2c.c + Patches by Peter Korsgaard/Tolunay Orkun, 26 May 2005 + +* Cleanup compiler warnings. + Patch by Greg Ungerer, 21 May 2005 + +* Word alignment fixes for word aligned NS16550 UART + Patch by Jean-Paul Saman, 01 Mar 2005 + + Fixes bug with UART that only supports word aligned access: removed + "__attribute__ ((packed));" for "(CFG_NS16550_REG_SIZE == 4)" some + (broken!) versions of GCC generate byte accesses when encountering + the packed attribute regardless if the struct is already correctly + aligned for a platform. Peripherals that can only handle word + aligned access won't work properly when accessed with byte access. + The struct NS16550 is already word aligned for REG_SIZE = 4, so + there is no need to packed the struct in that case. + +* Fix behaviour if gatewayip is not set + Patch by Robin Gilks, 23 Dec 2004 + +* Fix cleanup for netstart board. + Remove build results from repository + +* Some code cleanup for GCC 4.x + +* Fixes to support environment in NAND flash; + enable NAND flash based environment for delta board. + +* Add support for Intel Monahans CPU on Zylonite and Delta boards + (This is Work in Progress!) + +* Add support for TQM8260-AI boards. + +* Minor code cleanup + +* Merge the new NAND code (testing-NAND brach); see doc/README.nand + Rewrite of NAND code based on what is in 2.6.12 Linux kernel + Patch by Ladislav Michl, 29 Jun 2005 + +* Add lowboot target to mcc200 board + Patch by Stefan Roese, 4 Mar 2006 + +* Fix problem with flash_get_size() from CFI driver update + Patch by Stefan Roese, 1 Mar 2006 + +* Make CFG_NO_FLASH work on ARM systems + Patch by Markus Klotzbuecher, 27 Feb 2006 + +* Update mcc200 config: Disable PCI and DoC, use 133 MHz IPB clock, + use hush shell. + +* Convert mcc200 to use common CFI flash driver + Patch by Stefan Roese, 28 Feb 2006 + +* Add env-variable "unlock" to handle initial state of sectors + (locked/unlocked). + + Only the U-Boot image and it's environment is protected, + all other sectors are unprotected (unlocked) if flash + hardware protection is used (CFG_FLASH_PROTECTION) and + the environment variable "unlock" is set to "yes". + + Patch by Stefan Roese, 28 Feb 2006 + +* Update drivers/cfi_flash.c: + - find_sector() called in both versions of flash_write_cfiword() + Patch by Peter Pearse, 27th Feb 2006 + +* CFI support for a x8/x16 AMD/Spansion flash configured in x8 mode + Patch by Jose Maria Lopez, 16 Jan 2006 + +* Add support for AMD/Spansion Flashes in flash_write_cfibuffer + Patch by Alex Bastos and Thomas Schaefer, 2005-08-29 + +* Changes/fixes for drivers/cfi_flash.c: + We *should* check if there are any error bits if the previous call + returned ERR_OK (Otherwise we will have output an error message in + flash_status_check() already.) The original code would only check for + error bits if flash_status_check() returns ERR_TIMEOUT. + Patch by Marcus Hall, 23 Aug 2005 + +* Changes/fixes for drivers/cfi_flash.c: + - Add CFG_FLASH_PROTECT_CLEAR on drivers/cfi_flash.c + - Prohibit buffer write when buffer_size is 1 on drivers/cfi_flash.c + Patch by Sangmoon Kim, 19 Aug 2005 + +* Fixes for drivers/cfi_flash.c: + - Fix wrong timeout value usage in flash_status_check() + - Round write_tout up when converting to msec in flash_get_size() + - Remove clearing flash status at the end of flash_write_cfibuffer() + which sets Intel 28F640J3 flash back to command mode on CSB472 + Patch by Tolunay Orkun, 02 July 2005 + +* Add basic support for the SMMACO4 Board from PanDaCom. + Patch by Heiko Schocher, 20 Feb 2006 + +* Add GIT version information (commid ID) to untagged U-Boot versions + + As done in the linux kernel, the U-Boot version (U_BOOT_VERSION) + of all unreleased (untagged) U-Boot images will be automatically + extended upon compiletime with a part of the GIT commit ID and + possibly with "dirty" if uncommited changes are detected. + + Here an example for the resulting version: + "U-Boot 1.1.4-g3457ac18-dirty" + + The version is now maintained in the toplevel Makefile and the + version headers are autogenerated. + + Patch by Stefan Roese, 9 Feb 2006 + +* Update default environment for INKA4x00 board. + +* Convert CPCI750 to use common CFI flash driver + Patch by Reinhard Arlt, 8 Feb 2006 + +* Various changes to esd HH405 board specific files + Patch by Matthias Fuchs, 07 Feb 2006 + +* Cleanup U-Boot boot messages on ARM. + + To match the U-Boot user interface on ARM platforms to the U-Boot + standard (as on PPC platforms), some messages with debug character + are removed from the default U-Boot build. + Enable DEBUG for lib_arm/board.c to enable debug messages. + New CONFIG_DISPLAY_CPUINFO and CONFIG_DISPLAY_BOARDINFO options. + Patch by Stefan Roese, 24 Jan 2006 + +* Fix various compiler warnings on ppc4xx builds (ELDK 4.0) + Patch by Stefan Roese, 18 Jan 2006 + +* Add VGA support (CT69000) to CPCI750 board. + Insert missing __le32_to_cpu() for filesize in ext2fs_read_file(). + Patch by Reinhard Arlt, 30 Dec 2005 + +* PMC405 and CPCI405: Moved configuration of pci resources + into config file. + PMC405 and CPCI2DP: Added firmware download and booting via pci. + Patch by Matthias Fuchs, 20 Dec 2005 + +* Fix 28F256J3A support on PM520 board + (without bank-switching only 32 MB can be accessed) + +* Fix mkimage bug with multifile images created on 64 bit systems. + +* Add support for 28F256J3A flash (=> 64 MB) on PM520 board * Fix compiler problem with at91rm9200dk board. Patch by Eugen Bigz, 19 Dec 2005 @@ -26,8 +26,8 @@ LIST_5xx=" \ LIST_5xxx=" \ cpci5200 icecube_5100 icecube_5200 EVAL5200 \ - pf5200 PM520 Total5100 Total5200 \ - Total5200_Rev2 TQM5200_auto o2dnt \ + mcc200 o2dnt pf5200 PM520 \ + Total5100 Total5200 Total5200_Rev2 TQM5200_auto \ " ######################################################################### @@ -177,10 +177,10 @@ LIST_ARM9=" \ ap920t ap922_XA10 ap926ejs ap946es \ ap966 cp920t cp922_XA10 cp926ejs \ cp946es cp966 lpd7a400 mp2usb \ - mx1ads mx1fs2 omap1510inn omap1610h2 \ - omap1610inn omap730p2 scb9328 smdk2400 \ - smdk2410 trab VCMA9 versatile \ - versatileab versatilepb voiceblue + mx1ads mx1fs2 netstar omap1510inn \ + omap1610h2 omap1610inn omap730p2 scb9328 \ + smdk2400 smdk2410 trab VCMA9 \ + versatile versatileab versatilepb voiceblue " ######################################################################### @@ -203,8 +203,9 @@ LIST_ARM11=" \ LIST_pxa=" \ adsvix cerf250 cradle csb226 \ - innokom lubbock pxa255_idp wepep250 \ - xaeniax xm250 xsengine \ + delta innokom lubbock pxa255_idp \ + wepep250 xaeniax xm250 xsengine \ + zylonite \ " LIST_ixp="ixdp425" @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2005 +# (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -21,6 +21,13 @@ # MA 02111-1307 USA # +VERSION = 1 +PATCHLEVEL = 1 +SUBLEVEL = 4 +EXTRAVERSION = +U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) +VERSION_FILE = include/version_autogenerated.h + HOSTARCH := $(shell uname -m | \ sed -e s/i.86/i386/ \ -e s/sun4u/sparc64/ \ @@ -46,9 +53,6 @@ ifeq (include/config.mk,$(wildcard include/config.mk)) # load ARCH, BOARD, and CPU configuration include include/config.mk export ARCH CPU BOARD VENDOR SOC -# load other configuration -include $(TOPDIR)/config.mk - ifndef CROSS_COMPILE ifeq ($(HOSTARCH),ppc) CROSS_COMPILE = @@ -81,11 +85,18 @@ endif ifeq ($(ARCH),microblaze) CROSS_COMPILE = mb- endif +ifeq ($(ARCH),blackfin) +CROSS_COMPILE = bfin-elf- +endif endif endif export CROSS_COMPILE +# load other configuration +include $(TOPDIR)/config.mk + + ######################################################################### # U-Boot objects....order is important (i.e. start must be first) @@ -103,6 +114,10 @@ endif ifeq ($(CPU),mpc85xx) OBJS += cpu/$(CPU)/resetvec.o endif +ifeq ($(CPU),bf533) +OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o +OBJS += cpu/$(CPU)/cplbhdlr.o cpu/$(CPU)/cplbmgr.o cpu/$(CPU)/flush.o +endif LIBS = lib_generic/libgeneric.a LIBS += board/$(BOARDDIR)/lib$(BOARD).a @@ -121,6 +136,7 @@ LIBS += drivers/libdrivers.a LIBS += drivers/sk98lin/libsk98lin.a LIBS += post/libpost.a post/cpu/libcpu.a LIBS += common/libcommon.a +LIBS += $(BOARDLIBS) .PHONY : $(LIBS) # Add GCC lib @@ -154,14 +170,14 @@ u-boot.bin: u-boot u-boot.img: u-boot.bin ./tools/mkimage -A $(ARCH) -T firmware -C none \ -a $(TEXT_BASE) -e 0 \ - -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' include/version.h | \ + -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \ sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ -d $< $@ u-boot.dis: u-boot $(OBJDUMP) -d $< > $@ -u-boot: depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT) +u-boot: depend version $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT) UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ $(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \ --start-group $(LIBS) --end-group $(PLATFORM_LIBS) \ @@ -173,6 +189,13 @@ $(LIBS): $(SUBDIRS): $(MAKE) -C $@ all +version: + @echo -n "#define U_BOOT_VERSION \"U-Boot " > $(VERSION_FILE); \ + echo -n "$(U_BOOT_VERSION)" >> $(VERSION_FILE); \ + echo -n $(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion \ + $(TOPDIR)) >> $(VERSION_FILE); \ + echo "\"" >> $(VERSION_FILE) + gdbtools: $(MAKE) -C tools/gdb || exit 1 @@ -277,14 +300,23 @@ icecube_5100_config: unconfig } @./mkconfig -a IceCube ppc mpc5xxx icecube -inka4x0_config: unconfig +inka4x0_config: unconfig @./mkconfig inka4x0 ppc mpc5xxx inka4x0 +mcc200_config \ +mcc200_lowboot_config: unconfig + @ >include/config.h + @[ -z "$(findstring lowboot_,$@)" ] || \ + { echo "TEXT_BASE = 0xFE000000" >board/mcc200/config.tmp ; \ + echo "... with lowboot configuration" ; \ + } + @./mkconfig mcc200 ppc mpc5xxx mcc200 + o2dnt_config: - @./mkconfig -a o2dnt ppc mpc5xxx o2dnt + @./mkconfig o2dnt ppc mpc5xxx o2dnt pf5200_config: unconfig - @./mkconfig -a pf5200 ppc mpc5xxx pf5200 esd + @./mkconfig pf5200 ppc mpc5xxx pf5200 esd PM520_config \ PM520_DDR_config \ @@ -301,6 +333,14 @@ PM520_ROMBOOT_DDR_config: unconfig } @./mkconfig -a PM520 ppc mpc5xxx pm520 +smmaco4_config: unconfig + @./mkconfig -a smmaco4 ppc mpc5xxx tqm5200 + +spieval_config: unconfig + echo "#define CONFIG_CS_AUTOCONF">>include/config.h + echo "... with automatic CS configuration" + @./mkconfig -a spieval ppc mpc5xxx tqm5200 + MINI5200_config \ EVAL5200_config \ TOP5200_config: unconfig @@ -366,11 +406,6 @@ MiniFAP_config: unconfig } @./mkconfig -a TQM5200 ppc mpc5xxx tqm5200 -spieval_config: unconfig - echo "#define CONFIG_CS_AUTOCONF">>include/config.h - echo "... with automatic CS configuration" - @./mkconfig -a spieval ppc mpc5xxx tqm5200 - ######################################################################### ## MPC8xx Systems ######################################################################### @@ -1181,18 +1216,20 @@ TQM8260_AE_config \ TQM8260_AF_config \ TQM8260_AG_config \ TQM8260_AH_config \ +TQM8260_AI_config \ TQM8265_AA_config: unconfig @case "$@" in \ - TQM8255_AA_config) CTYPE=MPC8255; CFREQ=300; CACHE=no; BMODE=8260;; \ - TQM8260_AA_config) CTYPE=MPC8260; CFREQ=200; CACHE=no; BMODE=8260;; \ - TQM8260_AB_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;; \ - TQM8260_AC_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;; \ - TQM8260_AD_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=60x;; \ - TQM8260_AE_config) CTYPE=MPC8260; CFREQ=266; CACHE=no; BMODE=8260;; \ - TQM8260_AF_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=60x;; \ - TQM8260_AG_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=8260;; \ - TQM8260_AH_config) CTYPE=MPC8260; CFREQ=300; CACHE=yes; BMODE=60x;; \ - TQM8265_AA_config) CTYPE=MPC8265; CFREQ=300; CACHE=no; BMODE=60x;; \ + TQM8255_AA_config) CTYPE=MPC8255; CFREQ=300; CACHE=no; BMODE=8260;; \ + TQM8260_AA_config) CTYPE=MPC8260; CFREQ=200; CACHE=no; BMODE=8260;; \ + TQM8260_AB_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;; \ + TQM8260_AC_config) CTYPE=MPC8260; CFREQ=200; CACHE=yes; BMODE=60x;; \ + TQM8260_AD_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=60x;; \ + TQM8260_AE_config) CTYPE=MPC8260; CFREQ=266; CACHE=no; BMODE=8260;; \ + TQM8260_AF_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=60x;; \ + TQM8260_AG_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=8260;; \ + TQM8260_AH_config) CTYPE=MPC8260; CFREQ=300; CACHE=yes; BMODE=60x;; \ + TQM8260_AI_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=60x;; \ + TQM8265_AA_config) CTYPE=MPC8265; CFREQ=300; CACHE=no; BMODE=60x;; \ esac; \ >include/config.h ; \ if [ "$${CTYPE}" != "MPC8260" ] ; then \ @@ -1459,6 +1496,17 @@ mx1ads_config : unconfig mx1fs2_config : unconfig @./mkconfig $(@:_config=) arm arm920t mx1fs2 NULL imx +netstar_32_config \ +netstar_config: unconfig + @if [ "$(findstring _32_,$@)" ] ; then \ + echo "... 32MB SDRAM" ; \ + echo "#define PHYS_SDRAM_1_SIZE SZ_32M" >>include/config.h ; \ + else \ + echo "... 64MB SDRAM" ; \ + echo "#define PHYS_SDRAM_1_SIZE SZ_64M" >>include/config.h ; \ + fi + @./mkconfig -a netstar arm arm925t netstar + omap1510inn_config : unconfig @./mkconfig $(@:_config=) arm arm925t omap1510inn @@ -1606,6 +1654,9 @@ cradle_config : unconfig csb226_config : unconfig @./mkconfig $(@:_config=) arm pxa csb226 +delta_config : + @./mkconfig $(@:_config=) arm pxa delta + innokom_config : unconfig @./mkconfig $(@:_config=) arm pxa innokom @@ -1633,6 +1684,9 @@ xm250_config : unconfig xsengine_config : unconfig @./mkconfig $(@:_config=) arm pxa xsengine +zylonite_config : + @./mkconfig $(@:_config=) arm pxa zylonite + ######################################################################### ## ARM1136 Systems ######################################################################### @@ -1813,6 +1867,19 @@ suzaku_config: unconfig @./mkconfig -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno ######################################################################### +## Blackfin +######################################################################### +ezkit533_config : unconfig + @./mkconfig $(@:_config=) blackfin bf533 ezkit533 + +stamp_config : unconfig + @./mkconfig $(@:_config=) blackfin bf533 stamp + +dspstamp_config : unconfig + @./mkconfig $(@:_config=) blackfin bf533 dsp_stamp + +######################################################################### +######################################################################### ######################################################################### clean: @@ -1823,6 +1890,7 @@ clean: rm -f examples/hello_world examples/timer \ examples/eepro100_eeprom examples/sched \ examples/mem_to_mem_idma2intr examples/82559_eeprom \ + examples/smc91111_eeprom \ examples/test_burst rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr rm -f tools/mpc86x_clk tools/ncb @@ -1830,6 +1898,8 @@ clean: rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend rm -f tools/env/fw_printenv tools/env/fw_setenv rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image + rm -f board/netstar/eeprom board/netstar/crcek + rm -f board/netstar/*.srec board/netstar/*.bin rm -f board/trab/trab_fkt board/voiceblue/eeprom rm -f board/integratorap/u-boot.lds board/integratorcp/u-boot.lds @@ -1838,7 +1908,7 @@ clobber: clean -o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \ -print0 \ | xargs -0 rm -f - rm -f $(OBJS) *.bak tags TAGS + rm -f $(OBJS) *.bak tags TAGS include/version_autogenerated.h rm -fr *.*~ rm -f u-boot u-boot.map u-boot.hex $(ALL) rm -f tools/crc32.c tools/environment.c tools/env/crc32.c @@ -411,7 +411,24 @@ The following options need to be configured: The maximum size of the constructed OF tree. OF_CPU - The proper name of the cpus node. + OF_SOC - The proper name of the soc node. OF_TBCLK - The timebase frequency. + OF_STDOUT_PATH - The path to the console device + + CONFIG_OF_HAS_BD_T + + The resulting flat device tree will have a copy of the bd_t. + Space should be pre-allocated in the dts for the bd_t. + + CONFIG_OF_HAS_UBOOT_ENV + + The resulting flat device tree will have a copy of u-boot's + environment variables + + CONFIG_OF_BOARD_SETUP + + Board code has addition modification that it wants to make + to the flat device tree before handing it off to the kernel - Serial Ports: CFG_PL010_SERIAL @@ -606,7 +623,7 @@ The following options need to be configured: CFG_CMD_DIAG * Diagnostics CFG_CMD_DOC * Disk-On-Chip Support CFG_CMD_DTT * Digital Therm and Thermostat - CFG_CMD_ECHO * echo arguments + CFG_CMD_ECHO echo arguments CFG_CMD_EEPROM * EEPROM read/write support CFG_CMD_ELF * bootelf, bootvx CFG_CMD_ENV saveenv diff --git a/blackfin_config.mk b/blackfin_config.mk new file mode 100644 index 0000000..e2747aa --- /dev/null +++ b/blackfin_config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -D__blackfin__ diff --git a/board/adder/adder.c b/board/adder/adder.c index cab6e2f..aa781584 100644 --- a/board/adder/adder.c +++ b/board/adder/adder.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004 Arabella Software Ltd. + * Copyright (C) 2004-2005 Arabella Software Ltd. * Yuli Barcohen <yuli@arabellasw.com> * * Support for Analogue&Micro Adder boards family. @@ -28,7 +28,8 @@ #include <mpc8xx.h> /* - * SDRAM is single Samsung K4S643232F-T70 chip. + * SDRAM is single Samsung K4S643232F-T70 chip (8MB) + * or single Micron MT48LC4M32B2TG-7 chip (16MB). * Minimal CPU frequency is 40MHz. */ static uint sdram_table[] = { @@ -53,7 +54,7 @@ static uint sdram_table[] = { 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, /* Refresh (offset 0x30 in UPM RAM) */ - 0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04, + 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, @@ -63,7 +64,7 @@ static uint sdram_table[] = { long int initdram (int board_type) { - long int msize = CFG_SDRAM_SIZE; + long int msize; volatile immap_t *immap = (volatile immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -72,11 +73,11 @@ long int initdram (int board_type) /* Configure SDRAM refresh */ memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */ - memctl->memc_mamr = (94 << 24) | CFG_MAMR; - memctl->memc_mar = 0x0; + memctl->memc_mamr = (94 << 24) | CFG_MAMR; /* No refresh */ udelay(200); /* Run precharge from location 0x15 */ + memctl->memc_mar = 0x0; memctl->memc_mcr = 0x80002115; udelay(200); @@ -84,13 +85,18 @@ long int initdram (int board_type) memctl->memc_mcr = 0x80002830; udelay(200); - memctl->memc_mar = 0x88; - udelay(200); - /* Run MRS pattern from location 0x16 */ + memctl->memc_mar = 0x88; memctl->memc_mcr = 0x80002116; udelay(200); + memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */ + memctl->memc_or1 = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM; + memctl->memc_br1 = CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V; + + msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE); + memctl->memc_or1 |= ~(msize - 1); + return msize; } diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 803995a..7c98920 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -277,7 +277,7 @@ int board_early_init_f(void) } #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; /*----------------------------------------------------------------------------+ diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk index 35cb655..433429b 100644 --- a/board/amcc/bamboo/config.mk +++ b/board/amcc/bamboo/config.mk @@ -32,3 +32,6 @@ endif ifeq ($(dbcr),1) PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 endif + +# legacy nand support +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/amirix/ap1000/ap1000.c b/board/amirix/ap1000/ap1000.c index dd836ce..7d11b29 100644 --- a/board/amirix/ap1000/ap1000.c +++ b/board/amirix/ap1000/ap1000.c @@ -36,8 +36,8 @@ int board_pre_init (void) /** serial number and platform display at startup */ int checkboard (void) { - unsigned char *s = getenv ("serial#"); - unsigned char *e; + char *s = getenv ("serial#"); + char *e; /* After a loadace command, the SystemAce control register is left in a wonky state. */ /* this code did not work in board_pre_init */ @@ -135,13 +135,13 @@ int checkboard (void) long int initdram (int board_type) { - unsigned char *s = getenv ("dramsize"); + char *s = getenv ("dramsize"); if (s != NULL) { if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) { s += 2; } - return simple_strtoul (s, NULL, 16); + return (long int)simple_strtoul (s, NULL, 16); } else { /* give all 64 MB */ return 64 * 1024 * 1024; @@ -293,7 +293,7 @@ int do_swconfigbyte (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) printf ("Writing to Flash... "); write_result = - flash_write (sector_buffer, SW_BYTE_SECTOR_ADDR, + flash_write ((char *)sector_buffer, SW_BYTE_SECTOR_ADDR, SW_BYTE_SECTOR_SIZE); if (write_result != 0) { flash_perror (write_result); diff --git a/board/at91rm9200dk/at45.c b/board/at91rm9200dk/at45.c index 3c00132..f886fe4 100644 --- a/board/at91rm9200dk/at45.c +++ b/board/at91rm9200dk/at45.c @@ -593,7 +593,7 @@ int AT91F_DataFlashRead( if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) return -1; - if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK) + if (AT91F_DataFlashContinuousRead (pDataFlash, addr, (uchar *)buffer, SizeToRead) != DATAFLASH_OK) return -1; size -= SizeToRead; diff --git a/board/at91rm9200dk/flash.c b/board/at91rm9200dk/flash.c index f6228ef..0513d61 100644 --- a/board/at91rm9200dk/flash.c +++ b/board/at91rm9200dk/flash.c @@ -393,8 +393,7 @@ outahere: * Copy memory to flash */ -volatile static int write_word (flash_info_t * info, ulong dest, - ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { volatile u16 *addr = (volatile u16 *) dest; ulong result; @@ -409,7 +408,6 @@ volatile static int write_word (flash_info_t * info, ulong dest, if ((result & data) != data) return ERR_NOT_ERASED; - /* * Disable interrupts which might cause a timeout * here. Remember that our exception vectors are diff --git a/board/cmc_pu2/load_sernum_ethaddr.c b/board/cmc_pu2/load_sernum_ethaddr.c index 94aa30d..354566c 100644 --- a/board/cmc_pu2/load_sernum_ethaddr.c +++ b/board/cmc_pu2/load_sernum_ethaddr.c @@ -69,8 +69,8 @@ int i2c_read (unsigned char chip, unsigned int addr, int alen, void load_sernum_ethaddr (void) { struct manufacturer_data data; - unsigned char serial [9]; - unsigned char ethaddr[18]; + char ethaddr[18]; + char serial [9]; unsigned short chksum; unsigned char *p; unsigned short i, is, id; diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c index 6f5874a..73cc2f2 100644 --- a/board/cobra5272/flash.c +++ b/board/cobra5272/flash.c @@ -256,8 +256,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) return rc; } - -volatile static int write_word (flash_info_t * info, ulong dest, ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { volatile u16 *addr = (volatile u16 *) dest; ulong result; diff --git a/board/dave/PPChameleonEVB/Makefile b/board/dave/PPChameleonEVB/Makefile index 39d2fec..581a580 100644 --- a/board/dave/PPChameleonEVB/Makefile +++ b/board/dave/PPChameleonEVB/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o nand.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $^ diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c index 5f2c705..52055b8 100644 --- a/board/dave/PPChameleonEVB/PPChameleonEVB.c +++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c @@ -238,33 +238,6 @@ int testdram (void) /* ------------------------------------------------------------------------- */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -extern ulong -nand_probe(ulong physadr); - -void -nand_init(void) -{ - ulong totlen = 0; - -/* - The HI model is equipped with a large block NAND chip not supported yet - by U-Boot - (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) -*/ - -#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) - debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE); - totlen += nand_probe (CFG_NAND0_BASE); -#endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */ - - debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE); - totlen += nand_probe (CFG_NAND1_BASE); - - printf ("%3lu MB\n", totlen >>20); -} -#endif - #ifdef CONFIG_CFB_CONSOLE # ifdef CONFIG_CONSOLE_EXTRA_INFO # include <video_fb.h> diff --git a/board/dave/PPChameleonEVB/config.mk b/board/dave/PPChameleonEVB/config.mk index 5856aec..1dc635f 100644 --- a/board/dave/PPChameleonEVB/config.mk +++ b/board/dave/PPChameleonEVB/config.mk @@ -1,5 +1,5 @@ # -# (C) Copyright 2000 +# (C) Copyright 2000, 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,7 +22,13 @@ # # Reserve 256 kB for Monitor -TEXT_BASE = 0xFFFC0000 +#TEXT_BASE = 0xFFFC0000 # Reserve 320 kB for Monitor -#TEXT_BASE = 0xFFFB0000 +TEXT_BASE = 0xFFFB0000 + +# Compile the new NAND code (CFG_NAND_LEGACY mustn't be defined) +BOARDLIBS = drivers/nand/libnand.a + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +#BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/dave/PPChameleonEVB/nand.c b/board/dave/PPChameleonEVB/nand.c new file mode 100644 index 0000000..40a827c --- /dev/null +++ b/board/dave/PPChameleonEVB/nand.c @@ -0,0 +1,117 @@ +/* + * (C) Copyright 2006 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <nand.h> + +/* + * hardware specific access to control-lines + * function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c) + */ +static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W; + + switch(cmd) { + case NAND_CTL_SETCLE: + MACRO_NAND_CTL_SETCLE((unsigned long)base); + break; + case NAND_CTL_CLRCLE: + MACRO_NAND_CTL_CLRCLE((unsigned long)base); + break; + case NAND_CTL_SETALE: + MACRO_NAND_CTL_SETALE((unsigned long)base); + break; + case NAND_CTL_CLRALE: + MACRO_NAND_CTL_CLRALE((unsigned long)base); + break; + case NAND_CTL_SETNCE: + MACRO_NAND_ENABLE_CE((unsigned long)base); + break; + case NAND_CTL_CLRNCE: + MACRO_NAND_DISABLE_CE((unsigned long)base); + break; + } +} + + +/* + * read device ready pin + * function +/- borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c) + */ +static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo) +{ + struct nand_chip *this = mtdinfo->priv; + ulong rb_gpio_pin; + + /* use the base addr to find out which chip are we dealing with */ + switch((ulong) this->IO_ADDR_W) { + case CFG_NAND0_BASE: + rb_gpio_pin = CFG_NAND0_RDY; + break; + case CFG_NAND1_BASE: + rb_gpio_pin = CFG_NAND1_RDY; + break; + default: /* this should never happen */ + return 0; + break; + } + + if (in32(GPIO0_IR) & rb_gpio_pin) + return 1; + return 0; +} + + +/* + * Board-specific NAND initialization. The following members of the + * argument are board-specific (per include/linux/mtd/nand.h): + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device + * - hwcontrol: hardwarespecific function for accesing control-lines + * - dev_ready: hardwarespecific function for accesing device ready/busy line + * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must + * only be provided if a hardware ECC is available + * - eccmode: mode of ecc, see defines + * - chip_delay: chip dependent delay for transfering data from array to + * read regs (tR) + * - options: various chip options. They can partly be set to inform + * nand_scan about special functionality. See the defines for further + * explanation + * Members with a "?" were not set in the merged testing-NAND branch, + * so they are not set here either. + */ +void board_nand_init(struct nand_chip *nand) +{ + + nand->hwcontrol = ppchameleonevb_hwcontrol; + nand->dev_ready = ppchameleonevb_device_ready; + nand->eccmode = NAND_ECC_SOFT; + nand->chip_delay = NAND_BIG_DELAY_US; + nand->options = NAND_SAMSUNG_LP_OPTIONS; +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ diff --git a/board/delta/Makefile b/board/delta/Makefile new file mode 100644 index 0000000..e744eec --- /dev/null +++ b/board/delta/Makefile @@ -0,0 +1,48 @@ + +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := delta.o nand.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/delta/config.mk b/board/delta/config.mk new file mode 100644 index 0000000..9564625 --- /dev/null +++ b/board/delta/config.mk @@ -0,0 +1,8 @@ +#TEXT_BASE = 0x0 +#TEXT_BASE = 0xa1700000 +#TEXT_BASE = 0xa3080000 +#TEXT_BASE = 0x9ffe0000 +TEXT_BASE = 0xa3008000 + +# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE) +BOARDLIBS = drivers/nand/libnand.a diff --git a/board/delta/delta.c b/board/delta/delta.c new file mode 100644 index 0000000..3ffcc2a --- /dev/null +++ b/board/delta/delta.c @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of Lubbock-Board mk@tbd: fix this! */ + gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int board_late_init(void) +{ + setenv("stdout", "serial"); + setenv("stderr", "serial"); + return 0; +} + + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} diff --git a/board/delta/lowlevel_init.S b/board/delta/lowlevel_init.S new file mode 100644 index 0000000..498cf7f --- /dev/null +++ b/board/delta/lowlevel_init.S @@ -0,0 +1,385 @@ +/* + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> + +DRAM_SIZE: .long CFG_DRAM_SIZE + +/* wait for coprocessor write complete */ +.macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 +.endm + + +.macro wait time + ldr r2, =OSCR + mov r3, #0 + str r3, [r2] +0: + ldr r3, [r2] + cmp r3, \time + bls 0b +.endm + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + /* Set up GPIO pins first ----------------------------------------- */ + mov r10, lr + + /* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */ + ldr r0, =GPIO97 + ldr r1, =0x801 + str r1, [r0] + + ldr r0, =GPIO98 + ldr r1, =0x801 + str r1, [r0] + + /* tebrandt - ASCR, clear the RDH bit */ + ldr r0, =ASCR + ldr r1, [r0] + bic r1, r1, #0x80000000 + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ +; wait #300 + +mem_init: + +#define NEW_SDRAM_INIT 1 +#ifdef NEW_SDRAM_INIT + + /* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */ + ldr r0, =ACCR + ldr r1, [r0] + orr r1, r1, #0x3000 + str r1, [r0] + ldr r1, [r0] + + /* 2. Programm MDCNFG, leaving DMCEN de-asserted */ + ldr r0, =MDCNFG + ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13) + /* ldr r1, =0x80000403 */ + str r1, [r0] + ldr r1, [r0] /* delay until written */ + + /* 3. wait nop power up waiting period (200ms) + * optimization: Steps 4+6 can be done during this + */ + wait #300 + + /* 4. Perform an initial Rcomp-calibration cycle */ + ldr r0, =RCOMP + ldr r1, =0x80000000 + str r1, [r0] + ldr r1, [r0] /* delay until written */ + /* missing: program for automatic rcomp evaluation cycles */ + + /* 5. DDR DRAM strobe delay calibration */ + ldr r0, =DDR_HCAL + ldr r1, =0x88000007 + str r1, [r0] + wait #5 + ldr r1, [r0] /* delay until written */ + + /* Set MDMRS */ + ldr r0, =MDMRS + ldr r1, =0x60000033 + str r1, [r0] + wait #300 + + /* Configure MDREFR */ + ldr r0, =MDREFR + ldr r1, =0x00000006 + str r1, [r0] + ldr r1, [r0] + + /* Enable the dynamic memory controller */ + ldr r0, =MDCNFG + ldr r1, [r0] + orr r1, r1, #MDCNFG_DMCEN + str r1, [r0] + + +#else /* NEW_SDRAM_INIT */ + + /* configure the MEMCLKCFG register */ + ldr r1, =MEMCLKCFG + ldr r2, =0x00010001 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[0] to data flash SRAM mode */ + ldr r1, =CSADRCFG0 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[1] to data flash SRAM mode */ + ldr r1, =CSADRCFG1 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set MSC 0 register for SRAM memory */ + ldr r1, =MSC0 + ldr r2, =0x11191119 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[2] to data flash SRAM mode */ + ldr r1, =CSADRCFG2 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[3] to VLIO mode */ + ldr r1, =CSADRCFG3 + ldr r2, =0x0032080B + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set MSC 1 register for VLIO memory */ + ldr r1, =MSC1 + ldr r2, =0x123C1119 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + +#if 0 + /* This does not work in Zylonite. -SC */ + ldr r0, =0x15fffff0 + ldr r1, =0xb10b + str r1, [r0] + str r1, [r0, #4] +#endif + + /* Configure ACCR Register */ + ldr r0, =ACCR @ ACCR + ldr r1, =0x0180b108 + str r1, [r0] + ldr r1, [r0] + + /* Configure MDCNFG Register */ + ldr r0, =MDCNFG @ MDCNFG + ldr r1, =0x403 + str r1, [r0] + ldr r1, [r0] + + /* Perform Resistive Compensation by configuring RCOMP register */ + ldr r1, =RCOMP @ RCOMP + ldr r2, =0x000000ff + str r2, [r1] + ldr r2, [r1] + + /* Configure MDMRS Register for SDCS0 */ + ldr r1, =MDMRS @ MDMRS + ldr r2, =0x60000023 + ldr r3, [r1] + orr r2, r2, r3 + str r2, [r1] + ldr r2, [r1] + + /* Configure MDMRS Register for SDCS1 */ + ldr r1, =MDMRS @ MDMRS + ldr r2, =0xa0000023 + ldr r3, [r1] + orr r2, r2, r3 + str r2, [r1] + ldr r2, [r1] + + /* Configure MDREFR */ + ldr r1, =MDREFR @ MDREFR + ldr r2, =0x00000006 + str r2, [r1] + ldr r2, [r1] + + /* Configure EMPI */ + ldr r1, =EMPI @ EMPI + ldr r2, =0x80000000 + str r2, [r1] + ldr r2, [r1] + + /* Hardware DDR Read-Strobe Delay Calibration */ + ldr r0, =DDR_HCAL @ DDR_HCAL + ldr r1, =0x803ffc07 @ the offset is correct? -SC + str r1, [r0] + wait #5 + ldr r1, [r0] + + /* Here we assume the hardware calibration alwasy be successful. -SC */ + /* Set DMCEN bit in MDCNFG Register */ + ldr r0, =MDCNFG @ MDCNFG + ldr r1, [r0] + orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access + str r1, [r0] + +#endif /* NEW_SDRAM_INIT */ + +#ifndef CFG_SKIP_DRAM_SCRUB + /* scrub/init SDRAM if enabled/present */ + ldr r8, =CFG_DRAM_BASE /* base address of SDRAM (CFG_DRAM_BASE) */ + ldr r9, =CFG_DRAM_SIZE /* size of memory to scrub (CFG_DRAM_SIZE) */ + mov r0, #0 /* scrub with 0x0000:0000 */ + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov r4, #0 + mov r5, #0 + mov r6, #0 + mov r7, #0 +10: /* fastScrubLoop */ + subs r9, r9, #32 /* 8 words/line */ + stmia r8!, {r0-r7} + beq 15f + b 10b +#endif /* CFG_SKIP_DRAM_SCRUB */ + +15: + /* Mask all interrupts */ + mov r1, #0 + mcr p6, 0, r1, c1, c0, 0 @ ICMR + + /* Disable software and data breakpoints */ + mov r0, #0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /* Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ + +endlowlevel_init: + + mov pc, lr + + +/* +@******************************************************************************** +@ DDR calibration +@ +@ This function is used to calibrate DQS delay lines. +@ Monahans supports three ways to do it. One is software +@ calibration. Two is hardware calibration. Three is hybrid +@ calibration. +@ +@ TBD +@ -SC +ddr_calibration: + + @ Case 1: Write the correct delay value once + @ Configure DDR_SCAL Register + ldr r0, =DDR_SCAL @ DDR_SCAL +q ldr r1, =0xaf2f2f2f + str r1, [r0] + ldr r1, [r0] +*/ +/* @ Case 2: Software Calibration + @ Write test pattern to memory + ldr r5, =0x0faf0faf @ Data Pattern + ldr r4, =0xa0000000 @ DDR ram + str r5, [r4] + + mov r1, =0x0 @ delay count + mov r6, =0x0 + mov r7, =0x0 +ddr_loop1: + add r1, r1, =0x1 + cmp r1, =0xf + ble end_loop + mov r3, r1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + str r3, [r2] + + ldr r2, [r4] + cmp r2, r5 + bne ddr_loop1 + mov r6, r1 +ddr_loop2: + add r1, r1, =0x1 + cmp r1, =0xf + ble end_loop + mov r3, r1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + str r3, [r2] + + ldr r2, [r4] + cmp r2, r5 + be ddr_loop2 + mov r7, r2 + + add r3, r6, r7 + lsr r3, r3, =0x1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + +end_loop: + + @ Case 3: Hardware Calibratoin + ldr r0, =DDR_HCAL @ DDR_HCAL + ldr r1, =0x803ffc07 @ the offset is correct? -SC + str r1, [r0] + wait #5 + ldr r1, [r0] + mov pc, lr +*/ diff --git a/board/delta/nand.c b/board/delta/nand.c new file mode 100644 index 0000000..c4df6e5 --- /dev/null +++ b/board/delta/nand.c @@ -0,0 +1,590 @@ +/* + * (C) Copyright 2006 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#ifdef CONFIG_NEW_NAND_CODE + +#include <nand.h> +#include <asm/arch/pxa-regs.h> + +#ifdef CFG_DFC_DEBUG1 +# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args) +#else +# define DFC_DEBUG1(fmt, args...) +#endif + +#ifdef CFG_DFC_DEBUG2 +# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args) +#else +# define DFC_DEBUG2(fmt, args...) +#endif + +#ifdef CFG_DFC_DEBUG3 +# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args) +#else +# define DFC_DEBUG3(fmt, args...) +#endif + +#define MIN(x, y) ((x < y) ? x : y) + +/* These really don't belong here, as they are specific to the NAND Model */ +static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr delta_bbt_descr = { + .options = 0, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern +}; + +static struct nand_oobinfo delta_oob = { + .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ + .eccbytes = 6, + .eccpos = {2, 3, 4, 5, 6, 7}, + .oobfree = { {8, 2}, {12, 4} } +}; + + +/* + * not required for Monahans DFC + */ +static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + return; +} + +#if 0 +/* read device ready pin */ +static int dfc_device_ready(struct mtd_info *mtdinfo) +{ + if(NDSR & NDSR_RDY) + return 1; + else + return 0; + return 0; +} +#endif + +/* + * Write buf to the DFC Controller Data Buffer + */ +static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + unsigned long bytes_multi = len & 0xfffffffc; + unsigned long rest = len & 0x3; + unsigned long *long_buf; + int i; + + DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf)); + if(bytes_multi) { + for(i=0; i<bytes_multi; i+=4) { + long_buf = (unsigned long*) &buf[i]; + NDDB = *long_buf; + } + } + if(rest) { + printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n"); + } + return; +} + + +/* + * These functions are quite problematic for the DFC. Luckily they are + * not used in the current nand code, except for nand_command, which + * we've defined our own anyway. The problem is, that we always need + * to write 4 bytes to the DFC Data Buffer, but in these functions we + * don't know if to buffer the bytes/half words until we've gathered 4 + * bytes or if to send them straight away. + * + * Solution: Don't use these with Mona's DFC and complain loudly. + */ +static void dfc_write_word(struct mtd_info *mtd, u16 word) +{ + printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n"); +} +static void dfc_write_byte(struct mtd_info *mtd, u_char byte) +{ + printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n"); +} + +/* The original: + * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len) + * + * Shouldn't this be "u_char * const buf" ? + */ +static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len) +{ + int i=0, j; + + /* we have to be carefull not to overflow the buffer if len is + * not a multiple of 4 */ + unsigned long bytes_multi = len & 0xfffffffc; + unsigned long rest = len & 0x3; + unsigned long *long_buf; + + DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len); + /* if there are any, first copy multiple of 4 bytes */ + if(bytes_multi) { + for(i=0; i<bytes_multi; i+=4) { + long_buf = (unsigned long*) &buf[i]; + *long_buf = NDDB; + } + } + + /* ...then the rest */ + if(rest) { + unsigned long rest_data = NDDB; + for(j=0;j<rest; j++) + buf[i+j] = (u_char) ((rest_data>>j) & 0xff); + } + + return; +} + +/* + * read a word. Not implemented as not used in NAND code. + */ +static u16 dfc_read_word(struct mtd_info *mtd) +{ + printf("dfc_write_byte: UNIMPLEMENTED.\n"); + return 0; +} + +/* global var, too bad: mk@tbd: move to ->priv pointer */ +static unsigned long read_buf = 0; +static int bytes_read = -1; + +/* + * read a byte from NDDB Because we can only read 4 bytes from NDDB at + * a time, we buffer the remaining bytes. The buffer is reset when a + * new command is sent to the chip. + * + * WARNING: + * This function is currently only used to read status and id + * bytes. For these commands always 8 bytes need to be read from + * NDDB. So we read and discard these bytes right now. In case this + * function is used for anything else in the future, we must check + * what was the last command issued and read the appropriate amount of + * bytes respectively. + */ +static u_char dfc_read_byte(struct mtd_info *mtd) +{ + unsigned char byte; + unsigned long dummy; + + if(bytes_read < 0) { + read_buf = NDDB; + dummy = NDDB; + bytes_read = 0; + } + byte = (unsigned char) (read_buf>>(8 * bytes_read++)); + if(bytes_read >= 4) + bytes_read = -1; + + DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf); + return byte; +} + +/* calculate delta between OSCR values start and now */ +static unsigned long get_delta(unsigned long start) +{ + unsigned long cur = OSCR; + + if(cur < start) /* OSCR overflowed */ + return (cur + (start^0xffffffff)); + else + return (cur - start); +} + +/* delay function, this doesn't belong here */ +static void wait_us(unsigned long us) +{ + unsigned long start = OSCR; + us *= OSCR_CLK_FREQ; + + while (get_delta(start) < us) { + /* do nothing */ + } +} + +static void dfc_clear_nddb(void) +{ + NDCR &= ~NDCR_ND_RUN; + wait_us(CFG_NAND_OTHER_TO); +} + +/* wait_event with timeout */ +static unsigned long dfc_wait_event(unsigned long event) +{ + unsigned long ndsr, timeout, start = OSCR; + + if(!event) + return 0xff000000; + else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD)) + timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ; + else + timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ; + + while(1) { + ndsr = NDSR; + if(ndsr & event) { + NDSR |= event; + break; + } + if(get_delta(start) > timeout) { + DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event); + return 0xff000000; + } + + } + return ndsr; +} + +/* we don't always wan't to do this */ +static void dfc_new_cmd(void) +{ + int retry = 0; + unsigned long status; + + while(retry++ <= CFG_NAND_SENDCMD_RETRY) { + /* Clear NDSR */ + NDSR = 0xFFF; + + /* set NDCR[NDRUN] */ + if(!(NDCR & NDCR_ND_RUN)) + NDCR |= NDCR_ND_RUN; + + status = dfc_wait_event(NDSR_WRCMDREQ); + + if(status & NDSR_WRCMDREQ) + return; + + DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry); + dfc_clear_nddb(); + } + DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry); +} + +/* this function is called after Programm and Erase Operations to + * check for success or failure */ +static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + unsigned long ndsr=0, event=0; + + /* mk@tbd set appropriate timeouts */ + /* if (state == FL_ERASING) */ + /* timeo = CFG_HZ * 400; */ + /* else */ + /* timeo = CFG_HZ * 20; */ + if(state == FL_WRITING) { + event = NDSR_CS0_CMDD | NDSR_CS0_BBD; + } else if(state == FL_ERASING) { + event = NDSR_CS0_CMDD | NDSR_CS0_BBD; + } + + ndsr = dfc_wait_event(event); + + if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000)) + return(0x1); /* Status Read error */ + return 0; +} + +/* cmdfunc send commands to the DFC */ +static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command, + int column, int page_addr) +{ + /* register struct nand_chip *this = mtd->priv; */ + unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0; + + /* clear the ugly byte read buffer */ + bytes_read = -1; + read_buf = 0; + + switch (command) { + case NAND_CMD_READ0: + DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); + dfc_new_cmd(); + ndcb0 = (NAND_CMD_READ0 | (4<<16)); + column >>= 1; /* adjust for 16 bit bus */ + ndcb1 = (((column>>1) & 0xff) | + ((page_addr<<8) & 0xff00) | + ((page_addr<<8) & 0xff0000) | + ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */ + event = NDSR_RDDREQ; + goto write_cmd; + case NAND_CMD_READ1: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n"); + goto end; + case NAND_CMD_READOOB: + DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n"); + goto end; + case NAND_CMD_READID: + dfc_new_cmd(); + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n"); + ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/ + event = NDSR_RDDREQ; + goto write_cmd; + case NAND_CMD_PAGEPROG: + /* sent as a multicommand in NAND_CMD_SEQIN */ + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n"); + goto end; + case NAND_CMD_ERASE1: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); + dfc_new_cmd(); + ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16)); + ndcb1 = (page_addr & 0x00ffffff); + goto write_cmd; + case NAND_CMD_ERASE2: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n"); + goto end; + case NAND_CMD_SEQIN: + /* send PAGE_PROG command(0x1080) */ + dfc_new_cmd(); + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1)); + ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16)); + column >>= 1; /* adjust for 16 bit bus */ + ndcb1 = (((column>>1) & 0xff) | + ((page_addr<<8) & 0xff00) | + ((page_addr<<8) & 0xff0000) | + ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */ + event = NDSR_WRDREQ; + goto write_cmd; + case NAND_CMD_STATUS: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n"); + dfc_new_cmd(); + ndcb0 = NAND_CMD_STATUS | (4<<21); + event = NDSR_RDDREQ; + goto write_cmd; + case NAND_CMD_RESET: + DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n"); + ndcb0 = NAND_CMD_RESET | (5<<21); + event = NDSR_CS0_CMDD; + goto write_cmd; + default: + printk("dfc_cmdfunc: error, unsupported command.\n"); + goto end; + } + + write_cmd: + NDCB0 = ndcb0; + NDCB0 = ndcb1; + NDCB0 = ndcb2; + + /* wait_event: */ + dfc_wait_event(event); + end: + return; +} + +static void dfc_gpio_init(void) +{ + DFC_DEBUG2("Setting up DFC GPIO's.\n"); + + /* no idea what is done here, see zylonite.c */ + GPIO4 = 0x1; + + DF_ALE_WE1 = 0x00000001; + DF_ALE_WE2 = 0x00000001; + DF_nCS0 = 0x00000001; + DF_nCS1 = 0x00000001; + DF_nWE = 0x00000001; + DF_nRE = 0x00000001; + DF_IO0 = 0x00000001; + DF_IO8 = 0x00000001; + DF_IO1 = 0x00000001; + DF_IO9 = 0x00000001; + DF_IO2 = 0x00000001; + DF_IO10 = 0x00000001; + DF_IO3 = 0x00000001; + DF_IO11 = 0x00000001; + DF_IO4 = 0x00000001; + DF_IO12 = 0x00000001; + DF_IO5 = 0x00000001; + DF_IO13 = 0x00000001; + DF_IO6 = 0x00000001; + DF_IO14 = 0x00000001; + DF_IO7 = 0x00000001; + DF_IO15 = 0x00000001; + + DF_nWE = 0x1901; + DF_nRE = 0x1901; + DF_CLE_NOE = 0x1900; + DF_ALE_WE1 = 0x1901; + DF_INT_RnB = 0x1900; +} + +/* + * Board-specific NAND initialization. The following members of the + * argument are board-specific (per include/linux/mtd/nand_new.h): + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device + * - hwcontrol: hardwarespecific function for accesing control-lines + * - dev_ready: hardwarespecific function for accesing device ready/busy line + * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must + * only be provided if a hardware ECC is available + * - eccmode: mode of ecc, see defines + * - chip_delay: chip dependent delay for transfering data from array to + * read regs (tR) + * - options: various chip options. They can partly be set to inform + * nand_scan about special functionality. See the defines for further + * explanation + * Members with a "?" were not set in the merged testing-NAND branch, + * so they are not set here either. + */ +void board_nand_init(struct nand_chip *nand) +{ + unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR; + + /* set up GPIO Control Registers */ + dfc_gpio_init(); + + /* turn on the NAND Controller Clock (104 MHz @ D0) */ + CKENA |= (CKENA_4_NAND | CKENA_9_SMC); + +#undef CFG_TIMING_TIGHT +#ifndef CFG_TIMING_TIGHT + tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1), + DFC_MAX_tCH); + tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1), + DFC_MAX_tCS); + tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1), + DFC_MAX_tWH); + tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1), + DFC_MAX_tWP); + tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1), + DFC_MAX_tRH); + tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1), + DFC_MAX_tRP); + tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1), + DFC_MAX_tR); + tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1), + DFC_MAX_tWHR); + tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1), + DFC_MAX_tAR); +#else /* this is the tight timing */ + + tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)), + DFC_MAX_tCH); + tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)), + DFC_MAX_tCS); + tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)), + DFC_MAX_tWH); + tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)), + DFC_MAX_tWP); + tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)), + DFC_MAX_tRH); + tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)), + DFC_MAX_tRP); + tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2), + DFC_MAX_tR); + tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2), + DFC_MAX_tWHR); + tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2), + DFC_MAX_tAR); +#endif /* CFG_TIMING_TIGHT */ + + + DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR); + + /* tRP value is split in the register */ + if(tRP & (1 << 4)) { + tRP_high = 1; + tRP &= ~(1 << 4); + } else { + tRP_high = 0; + } + + NDTR0CS0 = (tCH << 19) | + (tCS << 16) | + (tWH << 11) | + (tWP << 8) | + (tRP_high << 6) | + (tRH << 3) | + (tRP << 0); + + NDTR1CS0 = (tR << 16) | + (tWHR << 4) | + (tAR << 0); + + /* If it doesn't work (unlikely) think about: + * - ecc enable + * - chip select don't care + * - read id byte count + * + * Intentionally enabled by not setting bits: + * - dma (DMA_EN) + * - page size = 512 + * - cs don't care, see if we can enable later! + * - row address start position (after second cycle) + * - pages per block = 32 + * - ND_RDY : clears command buffer + */ + /* NDCR_NCSX | /\* Chip select busy don't care *\/ */ + + NDCR = (NDCR_SPARE_EN | /* use the spare area */ + NDCR_DWIDTH_C | /* 16bit DFC data bus width */ + NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */ + (2 << 16) | /* read id count = 7 ???? mk@tbd */ + NDCR_ND_ARB_EN | /* enable bus arbiter */ + NDCR_RDYM | /* flash device ready ir masked */ + NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */ + NDCR_CS1_PAGEDM | + NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */ + NDCR_CS1_CMDDM | + NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */ + NDCR_CS1_BBDM | + NDCR_DBERRM | /* double bit error ir masked */ + NDCR_SBERRM | /* single bit error ir masked */ + NDCR_WRDREQM | /* write data request ir masked */ + NDCR_RDDREQM | /* read data request ir masked */ + NDCR_WRCMDREQM); /* write command request ir masked */ + + + /* wait 10 us due to cmd buffer clear reset */ + /* wait(10); */ + + + nand->hwcontrol = dfc_hwcontrol; +/* nand->dev_ready = dfc_device_ready; */ + nand->eccmode = NAND_ECC_SOFT; + nand->chip_delay = NAND_DELAY_US; + nand->options = NAND_BUSWIDTH_16; + nand->waitfunc = dfc_wait; + nand->read_byte = dfc_read_byte; + nand->write_byte = dfc_write_byte; + nand->read_word = dfc_read_word; + nand->write_word = dfc_write_word; + nand->read_buf = dfc_read_buf; + nand->write_buf = dfc_write_buf; + + nand->cmdfunc = dfc_cmdfunc; + nand->autooob = &delta_oob; + nand->badblock_pattern = &delta_bbt_descr; +} + +#else + #error "U-Boot legacy NAND support not available for Monahans DFC." +#endif +#endif diff --git a/board/delta/u-boot.lds b/board/delta/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/delta/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c index 03ae7fd..84fc3a0 100644 --- a/board/esd/ash405/ash405.c +++ b/board/esd/ash405/ash405.c @@ -239,7 +239,7 @@ int testdram (void) /* ------------------------------------------------------------------------- */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/ash405/config.mk b/board/esd/ash405/config.mk index 1d743a9..3cf5dd8 100644 --- a/board/esd/ash405/config.mk +++ b/board/esd/ash405/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0xFFFC0000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index 649619d..e283a92 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -114,7 +114,7 @@ int misc_init_r (void) int checkboard (void) { - unsigned char str[64]; + char str[64]; int flashcnt; int delay; volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000); @@ -238,7 +238,7 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, /* ------------------------------------------------------------------------- */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/cms700/config.mk b/board/esd/cms700/config.mk index 5c3c01c..0c56c40 100644 --- a/board/esd/cms700/config.mk +++ b/board/esd/cms700/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0xFFFC0000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index d48e972..cad8211 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -23,10 +23,15 @@ */ #include <common.h> + +#ifndef CFG_NAND_LEGACY +#error CFG_NAND_LEGACY not defined in a file using the legacy NAND support! +#endif + #include <command.h> #include <image.h> #include <asm/byteorder.h> -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> #include <fat.h> #include "auto_update.h" @@ -76,9 +81,9 @@ extern block_dev_desc_t *get_dev (char*, int); #define NANDRW_JFFS2 0x02 #define NANDRW_JFFS2_SKIP 0x04 extern struct nand_chip nand_dev_desc[]; -extern int nand_rw(struct nand_chip* nand, int cmd, size_t start, size_t len, +extern int nand_legacy_rw(struct nand_chip* nand, int cmd, size_t start, size_t len, size_t * retlen, u_char * buf); -extern int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); +extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE]; @@ -259,9 +264,9 @@ int au_do_update(int i, long sz) } else { #if (CONFIG_COMMANDS & CFG_CMD_NAND) printf("Updating NAND FLASH with image %s\n", au_image[i].name); - debug ("nand_erase(%lx, %lx);\n", start, end); - rc = nand_erase (nand_dev_desc, start, end - start + 1, 0); - debug ("nand_erase returned %x\n", rc); + debug ("nand_legacy_erase(%lx, %lx);\n", start, end); + rc = nand_legacy_erase (nand_dev_desc, start, end - start + 1, 0); + debug ("nand_legacy_erase returned %x\n", rc); #endif } @@ -283,13 +288,13 @@ int au_do_update(int i, long sz) */ if (au_image[i].type != AU_NAND) { debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes); - rc = flash_write((uchar *)addr, start, nbytes); + rc = flash_write((char *)addr, start, nbytes); } else { #if (CONFIG_COMMANDS & CFG_CMD_NAND) - debug ("nand_rw(%p, %lx %x)\n", addr, start, nbytes); - rc = nand_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, + debug ("nand_legacy_rw(%p, %lx %x)\n", addr, start, nbytes); + rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, start, nbytes, (size_t *)&total, (uchar *)addr); - debug ("nand_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes); + debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes); #endif } if (rc != 0) { @@ -304,7 +309,7 @@ int au_do_update(int i, long sz) rc = crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size)); } else { #if (CONFIG_COMMANDS & CFG_CMD_NAND) - rc = nand_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP, + rc = nand_legacy_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP, start, nbytes, (size_t *)&total, (uchar *)addr); rc = crc32 (0, (uchar *)(addr + off), ntohl(hdr->ih_size)); #endif diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c new file mode 100644 index 0000000..bf796ff --- /dev/null +++ b/board/esd/common/cmd_loadpci.c @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2005 + * Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +extern int do_bootm (cmd_tbl_t *, int, int, char *[]); +extern int do_autoscript (cmd_tbl_t *, int, int, char *[]); + +#define ADDRMASK 0xfffff000 + +/* + * Command loadpci: wait for signal from host and boot image. + */ +int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned int *ptr = 0; + int count = 0; + int count2 = 0; + char addr[16]; + char str[] = "\\|/-"; + char *local_args[2]; + + while(1) { + /* + * Mark sync address + */ + ptr = 0; + memset(ptr, 0, 0x20); + + *ptr = 0xffffffff; + puts("\nWaiting for action from pci host -"); + + /* + * Wait for host to write the start address + */ + while (*ptr == 0xffffffff) { + count++; + if (!(count % 100)) { + count2++; + putc(0x08); /* backspace */ + putc(str[count2 % 4]); + } + + /* Abort if ctrl-c was pressed */ + if (ctrlc()) { + puts("\nAbort\n"); + return 0; + } + + udelay(1000); + } + + printf("\nGot bootcode %08x: ", *ptr); + sprintf(addr, "%08x", *ptr & ADDRMASK); + + switch (*ptr & ~ADDRMASK) { + case 0: + /* + * Boot image via bootm + */ + printf("booting image at addr 0x%s ...\n", addr); + setenv("loadaddr", addr); + + do_bootm (cmdtp, 0, 0, NULL); + break; + + case 1: + /* + * Boot image via autoscr + */ + printf("executing script at addr 0x%s ...\n", addr); + + local_args[0] = addr; + local_args[1] = NULL; + do_autoscript(cmdtp, 0, 1, local_args); + break; + + case 2: + /* + * Call run_cmd + */ + printf("running command at addr 0x%s ...\n", addr); + run_command ((char*)(*ptr & ADDRMASK), 0); + break; + + default: + printf("unhandled boot method\n"); + break; + } + } +} + +U_BOOT_CMD( + loadpci, 1, 1, do_loadpci, + "loadpci - Wait for pci bootcmd and boot it\n", + NULL + ); + +#endif diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c index 0edc083..196171c 100644 --- a/board/esd/common/lcd.c +++ b/board/esd/common/lcd.c @@ -229,6 +229,9 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, /* * Detect epson */ + lcd_reg[0] = 0x00; + lcd_reg[1] = 0x00; + if (lcd_reg[0] == 0x1c) { /* * Big epson detected diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile index a60495a..88b0ae3 100644 --- a/board/esd/cpci2dp/Makefile +++ b/board/esd/cpci2dp/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o ../common/misc.o +OBJS = $(BOARD).o flash.o ../common/misc.o ../common/cmd_loadpci.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index df10c0e..1a27ca0 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -31,17 +31,15 @@ int board_early_init_f (void) unsigned long cntrl0Reg; /* - * Setup GPIO pins (CS4+CS7 as GPIO) + * Setup GPIO pins */ cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00900000); + mtdcr(cntrl0, cntrl0Reg | ((CFG_EEPROM_WP | CFG_PB_LED | CFG_SELF_RST | CFG_INTA_FAKE) << 5)); /* set output pins to high */ - out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED); - /* INTA# is open drain */ - out32(GPIO0_ODR, CFG_INTA_FAKE); - /* setup for output */ - out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP); + out32(GPIO0_OR, CFG_EEPROM_WP); + /* setup for output (LED=off) */ + out32(GPIO0_TCR, CFG_EEPROM_WP | CFG_PB_LED); /* * IRQ 0-15 405GP internally generated; active high; level sensitive @@ -130,16 +128,6 @@ long int initdram (int board_type) /* ------------------------------------------------------------------------- */ -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 64 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - #if defined(CFG_EEPROM_WREN) /* Input: <dev_addr> I2C address of EEPROM device to enable. * <state> -1: deliver current state @@ -207,8 +195,8 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( - eepwren, 2, 0, do_eep_wren, - "eepwren - Enable / disable / query EEPROM write access\n", - NULL - ); + eepwren, 2, 0, do_eep_wren, + "eepwren - Enable / disable / query EEPROM write access\n", + NULL + ); #endif /* #if defined(CFG_EEPROM_WREN) */ diff --git a/board/esd/cpci405/config.mk b/board/esd/cpci405/config.mk index 0be45c7..ceff4c4 100644 --- a/board/esd/cpci405/config.mk +++ b/board/esd/cpci405/config.mk @@ -38,3 +38,6 @@ TEXT_BASE = 0xFFFD0000 endif endif endif + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/cpci750/Makefile b/board/esd/cpci750/Makefile index 0486729..cd38b2d 100644 --- a/board/esd/cpci750/Makefile +++ b/board/esd/cpci750/Makefile @@ -29,7 +29,7 @@ SOBJS = misc.o OBJS = $(BOARD).o serial.o ../../Marvell/common/memory.o pci.o \ mv_eth.o mpsc.o i2c.o \ - sdram_init.o strataflash.o ide.o + sdram_init.o ide.o $(LIB): .depend $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) $(SOBJS) diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index e4b062b..dbed597 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -56,6 +56,7 @@ extern void flush_data_cache (void); extern void invalidate_l1_instruction_cache (void); +extern flash_info_t flash_info[]; /* ------------------------------------------------------------------------- */ @@ -363,6 +364,21 @@ int misc_init_r () /* disable the dcache and MMU */ dcache_lock (); #endif + if (flash_info[3].size < CFG_FLASH_INCREMENT) { + unsigned int flash_offset; + unsigned int l; + + flash_offset = CFG_FLASH_INCREMENT - flash_info[3].size; + for (l = 0; l < CFG_MAX_FLASH_SECT; l++) { + if (flash_info[3].start[l] != 0) { + flash_info[3].start[l] += flash_offset; + } + } + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[3]); + } return 0; } diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c index 3e44fb9..c335ebf 100644 --- a/board/esd/cpci750/pci.c +++ b/board/esd/cpci750/pci.c @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -44,6 +44,14 @@ static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 }, }; +#ifdef CONFIG_USE_CPCIDVI +typedef struct { + unsigned int base; + unsigned int init; +} GT_CPCIDVI_ROM_T; + +static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0}; +#endif #ifdef DEBUG static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE }; @@ -125,20 +133,20 @@ static const unsigned int pci_p2p_configuration[] = { /******************************************************************** * pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. +* - Make sure the GT is configured as a master before writing +* to another device on the PCI. +* - The function takes care of Big/Little endian conversion. * * * Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. +* (or any other PCI device spec) +* pciDevNum: The device number needs to be addressed. * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, @@ -172,20 +180,20 @@ void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, /******************************************************************** * pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. +* - Make sure the GT is configured as a master before reading +* from another device on the PCI. +* - The function takes care of Big/Little endian conversion. * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. +* spec) +* pciDevNum: The device number needs to be addressed. * RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid +* cause register to make sure the data is valid * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, @@ -220,21 +228,21 @@ unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, /******************************************************************** * pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. +* the agent is placed on another Bus. For more +* information read P2P in the PCI spec. * * Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. +* GT spec (or any other PCI device spec). +* unsigned int pciDevNum - The device number needs to be addressed. +* unsigned int busNum - On which bus does the Target agent connect +* to. +* unsigned int data - data to be written. * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * * The configuration Address is configure as type-I (bits[1:0] = '01') due to * PCI spec referring to P2P. @@ -265,23 +273,23 @@ void pciOverBridgeWriteConfigReg (PCI_HOST host, /******************************************************************** * pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. +* the agent target locate on another PCI bus. +* - Make sure the GT is configured as a master +* before reading from another device on the PCI. +* - The function takes care of Big/Little endian +* conversion. * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. +* spec). (configuration register offset.) +* pciDevNum: The device number needs to be addressed. +* busNum: the Bus number where the agent is place. * RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid +* cause register to make sure the data is valid * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, @@ -385,7 +393,7 @@ static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) /******************************************************************** * pciGetBaseAddress - Gets the base address of a PCI. -* - If the PCI size is 0 then this base address has no meaning!!! +* - If the PCI size is 0 then this base address has no meaning!!! * * * INPUT: Bus, Region - The bus and region we ask for its base address. @@ -493,13 +501,13 @@ void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, /******************************************************************** * pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. +* feature bits given as an input. +* - Be advised to check the spec before modifying them. * Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. +* unsigned int features - See file: pci.h there are defintion for those +* region features. +* unsigned int baseAddress - The region base Address. +* unsigned int topAddress - The region top Address. * Returns: false if one of the parameters is erroneous true otherwise. *********************************************************************/ bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, @@ -533,7 +541,7 @@ bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, /******************************************************************** * pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. +* to its low Address and MIN size to its high Address. * * Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. * Returns: N/A. @@ -580,12 +588,12 @@ bool pciArbiterDisable (PCI_HOST host) * pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) * * Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. -* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. -* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. -* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. -* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. -* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. -* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. +* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. +* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. +* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. +* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. +* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. +* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. * Returns: true *********************************************************************/ bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, @@ -611,17 +619,17 @@ bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, /******************************************************************** * pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. +* disable the park on last mechanism for each agent. +* disabling this option for all agents results parking +* on the internal master. * * Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. +* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. +* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. +* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. +* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. +* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. +* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. * Returns: true *********************************************************************/ bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, @@ -647,11 +655,11 @@ bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, /******************************************************************** * pciEnableBrokenAgentDetection - A master is said to be broken if it fails to -* respond to grant assertion within a window specified in -* the input value: 'brokenValue'. +* respond to grant assertion within a window specified in +* the input value: 'brokenValue'. * * Inputs: unsigned char brokenValue - A value which limits the Master to hold the -* grant without asserting frame. +* grant without asserting frame. * Returns: Error for illegal broken value otherwise true. *********************************************************************/ bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) @@ -670,9 +678,9 @@ bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) /******************************************************************** * pciDisableBrokenAgentDetection - This function disable the Broken agent -* Detection mechanism. -* NOTE: This operation may cause a dead lock on the -* pci0 arbitration. +* Detection mechanism. +* NOTE: This operation may cause a dead lock on the +* pci0 arbitration. * * Inputs: N/A * Returns: true. @@ -689,15 +697,15 @@ bool pciDisableBrokenAgentDetection (PCI_HOST host) /******************************************************************** * pciP2PConfig - This function set the PCI_n P2P configurate. -* For more information on the P2P read PCI spec. +* For more information on the P2P read PCI spec. * * Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower -* Boundry. -* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper -* Boundry. -* unsigned int busNum - The CPI bus number to which the PCI interface -* is connected. -* unsigned int devNum - The PCI interface's device number. +* Boundry. +* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper +* Boundry. +* unsigned int busNum - The CPI bus number to which the PCI interface +* is connected. +* unsigned int devNum - The PCI interface's device number. * * Returns: true. *********************************************************************/ @@ -715,15 +723,15 @@ bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, /******************************************************************** * pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. +* supports Cache Coherency in the PCI_n interface. * Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. +* snoopType - There is four optional Types: +* 1. No Snoop. +* 2. Snoop to WT region. +* 3. Snoop to WB region. +* 4. Snoop & Invalidate to WB region. +* baseAddress - Base Address of this region. +* regionLength - Region length. * Returns: false if one of the parameters is wrong otherwise return true. *********************************************************************/ bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, @@ -746,7 +754,7 @@ bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, GT_REG_WRITE (snoopXtopAddress, 0); return true; } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ + baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ data = (baseAddress >> 20) | snoopType << 12; GT_REG_WRITE (snoopXbaseAddress, data); snoopHigh = (snoopHigh & 0xfff00000) >> 20; @@ -800,23 +808,65 @@ static void gt_setup_ide (struct pci_controller *hose, unsigned int offset = (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8; - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - 0x0); - pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - &bar_response); + pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset, + 0x0); + pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset, + &bar_response); pciauto_region_allocate (bar_response & PCI_BASE_ADDRESS_SPACE_IO ? hose-> pci_io : hose->pci_mem, ide_bar[bar], &bar_value); - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - bar_value); + pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4, + bar_value); } } +#ifdef CONFIG_USE_CPCIDVI +static void gt_setup_cpcidvi (struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *entry) +{ + u32 bar_value, pci_response; + + pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response); + pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); + pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response); + pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value); + pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00)); + pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0); + pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value); + pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01); + gt_cpcidvi_rom.base = bar_value & 0xffffff00; + gt_cpcidvi_rom.init = 1; +} + +unsigned char gt_cpcidvi_in8(unsigned int offset) +{ + unsigned char data; + + if (gt_cpcidvi_rom.init == 0) { + return(0); + } + data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base); + return(data); +} + +void gt_cpcidvi_out8(unsigned int offset, unsigned char data) +{ + unsigned int off; -/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ + if (gt_cpcidvi_rom.init == 0) { + return; + } + off = data; + off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base; + in8(off); + return; +} +#endif + +/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ /* and is curently not called *. */ #if 0 static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) @@ -835,9 +885,12 @@ static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) #endif struct pci_config_table gt_config_table[] = { +#ifdef CONFIG_USE_CPCIDVI + {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi}, +#endif {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, - {} }; @@ -857,10 +910,21 @@ void pci_init_board (void) #ifdef CONFIG_PCI_PNP unsigned int bar; #endif - #ifdef DEBUG gt_pci_bus_mode_display (PCI_HOST0); #endif +#ifdef CONFIG_USE_CPCIDVI + gt_cpcidvi_rom.init = 0; + gt_cpcidvi_rom.base = 0; +#endif + + pci0_hose.config_table = gt_config_table; + pci1_hose.config_table = gt_config_table; + +#ifdef CONFIG_USE_CPCIDVI + gt_config_table[0].config_device = gt_setup_cpcidvi; +#endif + gt_config_table[1].config_device = gt_setup_ide; pci0_hose.first_busno = 0; pci0_hose.last_busno = 0xff; diff --git a/board/esd/cpci750/strataflash.c b/board/esd/cpci750/strataflash.c deleted file mode 100644 index c22fe5d..0000000 --- a/board/esd/cpci750/strataflash.c +++ /dev/null @@ -1,763 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/cache.h> - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for U-Boot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - - -#define FLASH_MAN_CFI 0x01000000 - - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -/*----------------------------------------------------------------------- - * Functions - */ - - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CFG_FLASH_BASE; - size = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - size += flash_info[i].size = flash_get_size(address, i); - address += CFG_FLASH_INCREMENT; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i, - flash_info[0].size, flash_info[i].size<<20); - } - } - -#if 0 /* test-only */ - /* Monitor protection ON by default */ -#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n"); - printf (" %08lX%5s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;i<aln; ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - - for(; (i< info->portwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; i<info->portwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; i<info->sector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * - */ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio = 0; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - invalidate_dcache_range(base, base+0x400); - - if(flash_detect_cfi(info)){ - - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); - - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); -#ifdef DEBUG_FLASH - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif -#ifdef DEBUG_FLASH - printf("size=%08x sectors=%08x \n", info->size, info->sector_count); -#endif - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t ctladdr; - cfiptr_t cptr; - int flag; - - ctladdr.cp = flash_make_addr(info, 0, 0); - cptr.cp = (uchar *)dest; - - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/hh405/config.mk b/board/esd/hh405/config.mk index 7129ad5..798a3fa 100644 --- a/board/esd/hh405/config.mk +++ b/board/esd/hh405/config.mk @@ -29,3 +29,6 @@ TEXT_BASE = 0xFFF80000 #TEXT_BASE = 0xFFFC0000 #TEXT_BASE = 0x00FC0000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/hh405/fpgadata.c b/board/esd/hh405/fpgadata.c index 58ee3a8..64bca46 100644 --- a/board/esd/hh405/fpgadata.c +++ b/board/esd/hh405/fpgadata.c @@ -1,2520 +1,2517 @@ - 0x1f,0x8b,0x08,0x08,0x9c,0xc4,0xe8,0x42,0x00,0x03,0x68,0x68,0x34,0x30,0x35,0x5f, - 0x31,0x5f,0x30,0x35,0x2e,0x62,0x69,0x74,0x00,0xec,0xfd,0x0f,0x78,0x14,0xd7,0x91, - 0x2f,0x0c,0x57,0x9f,0x6e,0x89,0xa3,0xe9,0x91,0xa6,0x91,0x84,0x57,0xb6,0x31,0x6e, - 0x8d,0x04,0x1e,0x94,0x91,0x18,0x46,0x58,0xc8,0x42,0x8c,0x5a,0x23,0xd9,0x19,0x1b, - 0x6c,0x26,0x8e,0x93,0x65,0x77,0xfd,0xe5,0x0e,0x84,0x64,0x95,0xbc,0xc4,0x2b,0x3b, - 0xb9,0x7b,0x49,0xd6,0xeb,0x1c,0x8d,0x04,0x8c,0x90,0x0c,0x03,0x28,0x31,0x4e,0x58, - 0x6f,0x23,0x64,0x5b,0x38,0x24,0x3b,0x08,0x0c,0x02,0x1c,0xdc,0xc2,0xb2,0x2d,0xfe, - 0x18,0x2b,0x0e,0xeb,0xe0,0x3f,0x71,0x06,0x47,0x26,0xb2,0x23,0xdb,0x32,0xc6,0x8e, - 0x04,0x02,0xde,0x3a,0x3d,0x92,0xa6,0x47,0x64,0xf7,0xe6,0xbe,0xf7,0xf9,0xde,0x6f, - 0x9f,0xe7,0xbb,0xf2,0xf3,0xec,0x9e,0xb4,0x8e,0x9a,0xee,0xd3,0xe7,0x54,0xfd,0xaa, - 0xea,0x57,0x55,0x90,0xe1,0x18,0x4e,0xfc,0x07,0x20,0xac,0x00,0x47,0x5d,0xdd,0x02, - 0xcf,0xad,0xff,0x6d,0xfe,0x7f,0xf3,0xdc,0x5a,0xf2,0xc0,0xd7,0x57,0xc1,0x4a,0x90, - 0xbd,0xdf,0xbd,0xd5,0xf3,0x8d,0xef,0x3d,0x38,0x7f,0xc1,0x02,0xf8,0x3a,0xfe,0x2f, - 0x8f,0xe7,0xd6,0x79,0x9e,0x85,0xf3,0xbc,0xe5,0xb0,0x0a,0x32,0xe6,0x97,0x56,0x2c, - 0xf0,0x56,0x78,0x3d,0xf0,0x0d,0x10,0x4a,0x3b,0xae,0xe2,0xcf,0x33,0x8f,0x7f,0xe5, - 0x9b,0x1e,0x60,0x02,0x00,0x4c,0xf3,0x08,0x21,0xfe,0xff,0x65,0x8f,0xa0,0x0a,0xc0, - 0xaa,0x8a,0x3d,0x60,0xf0,0xff,0x0d,0xe3,0xbf,0xcf,0xf0,0x80,0x6a,0xfd,0xdf,0x82, - 0x07,0x34,0x08,0x82,0xd6,0xca,0xb2,0xe1,0x2f,0xf8,0xa1,0x12,0x9b,0x18,0xfe,0x45, - 0xf3,0x61,0x72,0xfe,0xd5,0xe3,0xec,0x3f,0x9c,0x94,0xfc,0xa9,0x3a,0xaf,0x8f,0x8f, - 0x18,0xf1,0xfc,0xcf,0xa7,0x0b,0x01,0x98,0xb8,0xeb,0x0f,0xdf,0xfc,0x4b,0xee,0xbf, - 0xf0,0xf3,0x89,0xfb,0xff,0xaf,0xce,0x07,0xe5,0x2f,0x98,0x8e,0xef,0x3b,0x31,0xf8, - 0xa1,0x22,0x68,0xb0,0x1c,0xd2,0x41,0x60,0x10,0x82,0xbc,0xff,0x60,0xb0,0xb0,0x77, - 0x62,0xfe,0xd1,0xb4,0x31,0xef,0x29,0x71,0x61,0x7e,0xd6,0xe7,0x62,0x25,0xbc,0x0a, - 0x0b,0x8c,0xcc,0x11,0xf1,0x0a,0x8c,0x42,0x45,0x9f,0x3d,0x2e,0x8e,0xc1,0xc7,0x50, - 0x05,0x77,0xb3,0x1c,0x0f,0xd4,0x8f,0xcf,0x37,0xf2,0x9e,0x57,0x8e,0xab,0x5e,0x95, - 0x7e,0x4e,0x7e,0x01,0x2d,0xe0,0x8c,0xdb,0xbb,0xc9,0x47,0xd0,0xad,0x16,0xbc,0x69, - 0xef,0xc4,0xc1,0x06,0x56,0xa2,0xd2,0x08,0x89,0x49,0x13,0xab,0xd8,0x27,0xed,0x86, - 0x2d,0xb6,0x39,0xb0,0x61,0x01,0x91,0x60,0xab,0x50,0x62,0xe4,0x79,0xc8,0x49,0x38, - 0x2c,0xbb,0x5e,0xa4,0x1e,0x32,0x04,0x3b,0xc1,0x0d,0x54,0x99,0xe3,0x15,0x26,0xef, - 0x8f,0xf3,0x7f,0x02,0x4e,0x0f,0x8d,0x39,0x77,0x6b,0x3f,0x65,0x45,0xf1,0xbc,0x18, - 0x4e,0x3b,0xbc,0x41,0x35,0x32,0x3a,0xc8,0x50,0xd8,0x46,0x4b,0x08,0xdd,0x8c,0xf7, - 0x0f,0x8d,0xcf,0xaf,0x9e,0x3e,0x04,0xbf,0x82,0x32,0x4f,0x56,0x4c,0x74,0x85,0xdf, - 0x3a,0xeb,0x1b,0x76,0xc7,0x6a,0x86,0x60,0x94,0x55,0xf4,0xb4,0xea,0xe2,0x71,0xe9, - 0x8f,0xbf,0xf2,0x45,0xdd,0x11,0x41,0x91,0x26,0xee,0xaf,0x0b,0xcf,0xc1,0xc7,0xb4, - 0x0a,0x1c,0x9e,0x1b,0xfb,0xc8,0x7b,0xb0,0xd0,0x98,0x36,0x2c,0x8e,0x09,0x97,0x33, - 0x9e,0x37,0xb2,0x7a,0xc4,0x0f,0xe0,0xa2,0xe4,0x63,0x0e,0x2a,0x0e,0xc2,0xc4,0xfd, - 0xfb,0x95,0xdd,0xf4,0x7d,0xcd,0x0b,0xfc,0xfe,0xd2,0x1f,0x7b,0x7c,0x41,0x7b,0xac, - 0x60,0x08,0x2e,0x41,0x99,0x61,0x67,0xe2,0xfb,0xf0,0x47,0xcd,0x13,0xb5,0x47,0x65, - 0x8f,0xa4,0x4e,0xbc,0x6f,0x9a,0x8f,0xb6,0xc4,0x43,0x0b,0xe4,0x61,0xb1,0x4e,0x6a, - 0x31,0xd4,0xb7,0x6d,0x31,0x71,0x37,0xec,0x85,0x02,0x83,0x32,0x32,0xc8,0x36,0x80, - 0x93,0xd1,0x28,0x29,0xc3,0xdd,0x3f,0xf1,0xbe,0xab,0xb5,0xf6,0x3b,0x74,0xdd,0xe6, - 0x21,0x76,0xd8,0xa9,0xba,0xe2,0x19,0x7c,0x7d,0x76,0x42,0xa1,0xe1,0x82,0xf4,0x8d, - 0x64,0x07,0xa8,0x1a,0x55,0xc9,0x08,0x9e,0x95,0xc4,0xcf,0x88,0xf2,0xb5,0x8c,0x8d, - 0xb1,0xfc,0x8e,0x1b,0xbf,0x4f,0xbe,0x46,0xd7,0xeb,0x73,0x87,0xe4,0x35,0xe4,0x09, - 0xa8,0xea,0x56,0xe3,0x74,0x0d,0x79,0x27,0xf3,0x49,0x96,0x1f,0xa2,0xdf,0x82,0x2b, - 0x93,0xf7,0x0f,0xd0,0xa5,0xf0,0x6e,0xbb,0x1a,0xce,0xf2,0x88,0x76,0xf8,0xa3,0x5e, - 0x39,0x96,0xe9,0x11,0x4f,0xc2,0xa7,0xd1,0x05,0x71,0x3b,0x1f,0x9c,0x85,0x98,0xe6, - 0xae,0xa8,0x79,0x8d,0x4c,0xec,0x07,0x2d,0xad,0x55,0xfd,0x47,0xa5,0x8a,0x39,0x86, - 0xc5,0x21,0xed,0x8a,0xb2,0xb0,0x37,0x0b,0xd7,0x07,0x3e,0x85,0xaa,0x97,0x1c,0x31, - 0x1c,0xfc,0x7f,0x94,0xaa,0x5a,0xc7,0x48,0x8e,0x92,0x3e,0xb1,0x3e,0x54,0xfa,0x79, - 0xb8,0x07,0x4f,0x75,0xd6,0x01,0x71,0x35,0x9c,0x80,0x32,0x96,0x19,0x13,0x87,0x70, - 0x7e,0x59,0x9f,0x3d,0x8a,0x83,0x13,0xcc,0x1b,0xb7,0xbb,0xe4,0xa2,0xc9,0xfd,0xd3, - 0x97,0xb7,0x5d,0x5d,0x0f,0x3b,0x80,0x7e,0x57,0x9c,0x49,0x70,0xc0,0xdc,0xf5,0xe4, - 0x6d,0x38,0x00,0xfa,0xc9,0x40,0x30,0xfb,0x6d,0xfc,0x43,0xd5,0xa0,0x21,0x9b,0x77, - 0xf2,0xfb,0xaa,0xb0,0x91,0xb5,0x1a,0x05,0xaa,0xad,0xdc,0xb6,0x0c,0x1e,0x63,0xea, - 0xd9,0xeb,0xf1,0x35,0xe1,0x79,0x96,0x1f,0x2f,0x5f,0xee,0x3f,0x05,0xeb,0x71,0x80, - 0x2f,0xae,0xc2,0xc4,0xfa,0xd7,0x49,0xad,0xb0,0x35,0xa4,0xd6,0xe3,0xee,0xca,0xc4, - 0x8d,0xa4,0x0e,0x2f,0xe7,0xeb,0xb9,0x97,0xdf,0x36,0x37,0xdc,0xab,0xed,0x8d,0xaa, - 0x03,0xb8,0x03,0xb3,0x27,0xf7,0xe7,0xe0,0x8c,0x41,0x38,0x65,0x94,0x36,0x67,0xe9, - 0x05,0x7f,0x0b,0xef,0xb4,0xef,0xed,0xcc,0xd4,0xf1,0xeb,0x7f,0x0e,0x5e,0x66,0xff, - 0x40,0xfc,0x23,0x1c,0x87,0x2e,0xe6,0xd6,0xc5,0x8a,0xc9,0xe7,0x09,0x08,0x02,0x0c, - 0xfa,0x7d,0xd4,0x01,0x62,0x9c,0x0d,0x42,0x05,0xcd,0x62,0x62,0x1c,0x46,0x58,0x05, - 0x38,0x98,0xf8,0x2e,0x0c,0x82,0x0f,0x1c,0x86,0xf8,0x1a,0x4c,0xdc,0x9f,0x2a,0x4f, - 0x91,0x1e,0xf6,0x94,0x96,0x19,0x15,0x3b,0xd2,0x8f,0x41,0xf8,0x76,0x1c,0x0c,0xc0, - 0x28,0xe9,0xd2,0xec,0x8a,0x28,0xc1,0xfb,0xe0,0xd3,0x1c,0x51,0xf1,0xe8,0xe4,0xf3, - 0x30,0x58,0xd5,0xd3,0xdc,0xaf,0x06,0x6d,0xd1,0x9c,0x55,0xb0,0x0b,0xd4,0x3a,0x7b, - 0x94,0x0c,0xc0,0x41,0xcd,0xa9,0x45,0xa2,0xa4,0x10,0x9a,0xa1,0x44,0x93,0xa3,0x24, - 0x3e,0x29,0x16,0xca,0xd3,0x0a,0xd3,0x5a,0xb4,0x5f,0x04,0x68,0x34,0x7d,0x00,0x32, - 0x94,0x6f,0x6b,0xcd,0xe6,0x7c,0x8a,0xdb,0x26,0xea,0x77,0xc3,0xcf,0x61,0x9e,0x26, - 0xf7,0x93,0x97,0x26,0xf7,0x83,0x9a,0x2b,0x09,0x0d,0x9a,0xd3,0xd8,0x90,0x9b,0xbe, - 0x4a,0xd8,0xa1,0xa9,0x5a,0x9e,0x42,0x7a,0xf1,0xfe,0x6a,0xd0,0xa5,0xe0,0x09,0x5d, - 0x0b,0xc5,0x9a,0x1c,0x24,0x47,0x85,0x89,0xfd,0xb0,0x26,0x33,0x04,0x11,0x38,0x02, - 0xb8,0xdb,0x75,0xe8,0x23,0x15,0x42,0xa6,0xf9,0xbe,0xe0,0xc5,0x2b,0xb2,0xaa,0xf0, - 0xf7,0xdd,0x64,0x88,0xa7,0xc4,0x89,0xfd,0xb9,0x2d,0xed,0x3d,0xb8,0xac,0x3d,0xaf, - 0x39,0xda,0x72,0x3e,0x23,0xff,0xee,0xaf,0x0a,0x66,0xe1,0xfb,0x4a,0x97,0xb5,0xac, - 0xe0,0xbc,0xd3,0xe2,0x67,0x30,0xaa,0xf9,0x82,0x8e,0x36,0xf1,0x5c,0xfa,0xc4,0x7e, - 0xc8,0x4b,0xbb,0xc0,0x5e,0xf1,0x2c,0xd2,0xb2,0xda,0xc4,0x42,0xd7,0x2b,0x77,0x2e, - 0x0e,0xdc,0x83,0xf3,0x85,0xcb,0x01,0xaf,0x3f,0x2b,0xda,0xb8,0x4f,0x3d,0xa6,0x96, - 0x6a,0xf6,0xfe,0xc6,0x97,0x26,0xf7,0x4f,0x79,0xde,0x59,0x88,0xa8,0x4e,0x81,0x36, - 0x91,0x1d,0x42,0x04,0xda,0xa3,0x36,0x86,0xab,0xd1,0x0d,0x45,0x0a,0x6d,0x12,0xf1, - 0x57,0xe0,0x04,0xbb,0x4e,0x4e,0x4d,0xae,0x67,0xe0,0xf6,0xb5,0xb6,0x06,0xe3,0x19, - 0xcd,0x76,0x9d,0xbf,0x10,0x1a,0x84,0xc2,0xa0,0x4d,0x21,0xb5,0xb0,0x47,0x55,0xef, - 0xb2,0x29,0xfe,0x01,0x68,0xc0,0x17,0xcf,0x50,0xc8,0x6b,0x93,0xf2,0x67,0x9b,0xd4, - 0x81,0x8b,0x4c,0xb4,0x40,0x74,0x65,0x07,0xc9,0x70,0x91,0x80,0xcd,0x5c,0x4f,0x67, - 0x91,0xa6,0xb6,0x91,0x73,0xa4,0x19,0x9c,0x9a,0x2b,0x4a,0x5e,0x9a,0xdc,0x0f,0xfa, - 0x8c,0x55,0xd0,0x03,0x15,0x81,0xac,0x68,0xce,0x1c,0x68,0xd6,0x66,0x6a,0xfc,0x7d, - 0xe1,0xa0,0xee,0xd5,0xee,0xda,0x7e,0xcb,0x3a,0x38,0x06,0x8c,0x7f,0xfa,0xc1,0x49, - 0xf9,0xd3,0x27,0x74,0xc0,0xa8,0x8d,0x7f,0xf4,0x25,0x03,0x91,0x4f,0xc0,0x17,0xc2, - 0xaf,0x3f,0xa0,0x7c,0x22,0xf9,0xb4,0x7f,0xdb,0x22,0x76,0xc0,0x27,0x82,0xb9,0x1f, - 0x2e,0x4e,0xca,0x1f,0xaa,0xb0,0xea,0xbe,0xe9,0xde,0x0c,0x5c,0x6d,0x5c,0x7f,0xad, - 0x4c,0xb1,0xb3,0x02,0x5c,0xff,0xac,0x32,0xc8,0x62,0x39,0x71,0xa5,0x4f,0xf0,0x82, - 0x9b,0xa1,0xa0,0x9b,0xd8,0xff,0xae,0xb4,0x6e,0x3c,0x31,0xf9,0x51,0x9b,0x4e,0x28, - 0x6c,0x84,0x82,0xb0,0x43,0x27,0x83,0x70,0xc4,0x98,0xc3,0xec,0x7c,0xb0,0x01,0x0a, - 0x18,0x8d,0x93,0xe3,0x93,0xfb,0xc1,0x25,0xdd,0x45,0xdb,0x0d,0x97,0xc7,0x16,0xb3, - 0xa1,0xd8,0x61,0xae,0xec,0x88,0x27,0xfd,0x24,0x6e,0xfa,0x39,0x78,0x0d,0xb7,0x4d, - 0x23,0xb8,0x18,0xca,0x9f,0xe3,0x93,0xf2,0x87,0x29,0x01,0xe9,0x29,0xf8,0x82,0x62, - 0x7b,0x90,0x3c,0x07,0xb7,0x68,0x73,0xe1,0xef,0xcc,0xf3,0x9b,0x51,0xd8,0x27,0xd7, - 0xc3,0xbf,0xc3,0x7a,0x3e,0x3f,0x84,0xff,0xd0,0xc4,0xfd,0x23,0x91,0x7b,0xe1,0x17, - 0x0d,0x07,0xf5,0xac,0x11,0xf9,0x09,0xf8,0x37,0xf6,0x4b,0xd5,0xbe,0x46,0x7c,0x07, - 0x3e,0x67,0xb7,0x9e,0xcf,0x5a,0x23,0xbe,0x44,0x5e,0x60,0x07,0x75,0x7b,0x9d,0xf8, - 0xc1,0xa4,0xfc,0xa1,0x33,0x3a,0xe1,0x6f,0xa5,0x7d,0x80,0xd2,0x66,0x29,0x79,0x0b, - 0x05,0xa5,0x83,0xcb,0x93,0x8b,0xd2,0x23,0x86,0x3d,0x26,0x0e,0x10,0x14,0xbc,0xcc, - 0xa1,0x8b,0x47,0x27,0xe5,0x0f,0x48,0x87,0xb4,0x33,0x4d,0xb7,0xe9,0xf6,0x91,0x69, - 0x8f,0xc0,0x89,0xa8,0x47,0xb5,0x73,0xfd,0x75,0x85,0x79,0xcf,0x9a,0x83,0x8f,0xd9, - 0x62,0xdd,0xbe,0x4b,0x86,0xc9,0xfd,0xb3,0x8b,0xfe,0x04,0xc8,0x51,0x94,0x3f,0x0f, - 0x92,0x59,0x6c,0x67,0x7c,0x97,0xba,0xec,0x41,0x7c,0xfe,0xa1,0xa6,0x5b,0x87,0xe8, - 0x0f,0xe0,0x34,0x3e,0x7f,0x31,0xcb,0xac,0xf3,0x17,0x4d,0x7e,0x5f,0xdc,0x11,0xb0, - 0x8e,0xcc,0x65,0xd4,0x63,0xb3,0x37,0xad,0x57,0xf3,0xc3,0x94,0xbf,0xef,0x7e,0x61, - 0x76,0x5f,0xe7,0x43,0xa6,0xe0,0x2a,0x66,0x74,0xa5,0x4d,0x9b,0x94,0x3f,0xaa,0x14, - 0x21,0x1b,0x22,0xaa,0x3f,0x10,0x43,0x79,0xfe,0x33,0x4d,0x55,0x17,0x71,0xf9,0xa3, - 0xa3,0x3c,0xa7,0x3e,0x72,0x07,0x34,0x6a,0x6e,0x46,0xdd,0x24,0x20,0x4d,0x9c,0xdf, - 0xce,0x19,0x83,0xd2,0x89,0x42,0x17,0xb3,0x0f,0x8b,0x6e,0x38,0xa1,0xe3,0xf3,0x9b, - 0xef,0x1b,0xbc,0xc5,0x68,0xed,0x12,0xcf,0x6d,0xfe,0xa3,0x56,0xc2,0xe8,0xee,0xc6, - 0x6f,0x4f,0x3e,0x0f,0x13,0x9a,0x95,0x0f,0x34,0x9f,0x30,0x2f,0x26,0xfe,0x42,0xba, - 0xb8,0xd2,0x37,0xdd,0x5c,0x9f,0x4b,0xe0,0x33,0x1c,0x1e,0xdc,0x78,0x38,0x60,0xc5, - 0x3a,0x1e,0xd5,0x89,0xfd,0x9f,0xaf,0xec,0x46,0x21,0xb6,0x17,0xef,0x2f,0xcf,0xc4, - 0xf5,0x5f,0xe4,0xc9,0xe4,0xf2,0xfc,0x8a,0x34,0xdf,0xc0,0x81,0x14,0xbe,0x4a,0xab, - 0xd8,0xb2,0xf8,0x0e,0xa3,0x76,0x62,0xfe,0x0e,0xf8,0x87,0x30,0x2a,0x29,0x15,0xd5, - 0x96,0x5b,0x89,0x34,0x39,0xf3,0x32,0xb9,0xfe,0xed,0x82,0x76,0x83,0xc6,0x72,0xbe, - 0x89,0x1a,0xbf,0x04,0x37,0xa2,0x45,0xfe,0xb0,0xb4,0x22,0xd8,0xa0,0x38,0x63,0x34, - 0x46,0xdc,0xf0,0x33,0xb5,0x08,0x32,0xf8,0xfc,0x43,0xe0,0x34,0x70,0x50,0x08,0x3f, - 0x13,0x4a,0x1a,0xcc,0xf9,0x13,0xfb,0x81,0x4a,0xb4,0x21,0x1c,0x72,0x82,0xcd,0x93, - 0x6e,0x77,0xb5,0x53,0xf5,0x8e,0xb9,0x7c,0x7d,0x62,0x45,0xa1,0xa3,0xd4,0xeb,0xac, - 0xc5,0xfd,0xe6,0x66,0x4b,0xf2,0xd3,0x93,0xf2,0x07,0x6e,0x5a,0xad,0x6e,0x70,0xa1, - 0x34,0x8e,0x15,0xb8,0xe1,0x8f,0x50,0x04,0xa6,0x7e,0xb9,0xb8,0xe0,0xc1,0x5e,0x1c, - 0x14,0x12,0xfe,0xbe,0xb8,0x1f,0x8c,0x49,0xf9,0xb3,0xe3,0xa6,0x21,0xe5,0x8a,0x7a, - 0x33,0xa0,0xfe,0xdd,0x0d,0xaf,0xdb,0xaa,0xa8,0x83,0xbf,0xef,0x19,0xa1,0xca,0x70, - 0xec,0x11,0x2e,0x90,0xab,0x04,0x55,0xdb,0xd7,0xc5,0x41,0x32,0x89,0x37,0x66,0xbc, - 0x0b,0xaf,0xb2,0xaa,0x33,0x8e,0x4f,0x76,0x3e,0x04,0x57,0x03,0xa5,0xea,0x46,0x43, - 0xac,0x64,0x57,0x9d,0x8b,0xfa,0xb2,0xce,0x3b,0x71,0xa0,0x96,0x1e,0x77,0xbc,0xdb, - 0x38,0x2c,0x4c,0xca,0xe7,0xbc,0x73,0xa8,0xd4,0x4a,0x7a,0xe5,0xcf,0x89,0x53,0xda, - 0xa4,0x15,0xe5,0xd3,0x7e,0x32,0x4f,0xeb,0xee,0x77,0x0e,0x67,0x3e,0x47,0xfe,0x0d, - 0x0e,0x29,0xde,0x61,0x79,0x37,0xbe,0xef,0xa4,0xfc,0x4f,0x0b,0xc1,0x56,0x70,0xf7, - 0xc9,0x1e,0x12,0x52,0x76,0xaa,0xf8,0xe2,0xc0,0x15,0x3d,0xb8,0xfa,0xe9,0x02,0xbf, - 0x54,0xbb,0x07,0x61,0xb1,0x4d,0x55,0x8f,0x4e,0xde,0xdf,0x10,0x9e,0xa4,0x2d,0xac, - 0xc4,0x90,0x63,0x24,0x84,0xab,0x51,0x04,0x74,0x73,0xd8,0xad,0x76,0x67,0x38,0x8f, - 0xd3,0xae,0x70,0x87,0x56,0x4e,0x09,0xc1,0xf5,0x1c,0x4e,0xee,0xcf,0xdc,0x75,0xf0, - 0xa6,0x81,0x5f,0x3f,0x26,0xd6,0xe0,0xd7,0x47,0x45,0xbc,0x5b,0xfe,0x02,0xc2,0x92, - 0x8a,0xa8,0xad,0xe3,0xaf,0xe6,0xd1,0x4f,0x35,0x67,0x7f,0xd6,0x6e,0xd2,0x3f,0x29, - 0x7f,0xce,0xe2,0x96,0xbd,0x42,0xaa,0x7a,0x1c,0xb1,0x9c,0xbd,0x70,0x15,0xaa,0x6c, - 0x8e,0x6e,0x71,0x90,0x5d,0x14,0x7c,0xfa,0x3f,0x74,0x8a,0x1f,0xd1,0x2b,0x70,0xc8, - 0x70,0xec,0x16,0x47,0x26,0xe5,0x8f,0xa1,0x3c,0xcd,0x2e,0x6a,0x15,0xc6,0x26,0xcf, - 0xb4,0x1d,0xca,0x1f,0x51,0xec,0x3b,0x9a,0xe4,0xb9,0xf0,0x82,0xf6,0x50,0xdb,0xa3, - 0x6e,0xf1,0x1b,0xe4,0x84,0xe1,0x8d,0xda,0x3b,0xc4,0x24,0xfe,0x39,0x2e,0xcd,0x86, - 0x8b,0x30,0xcf,0x90,0x87,0x9d,0x2a,0xe2,0x49,0x27,0xcb,0xda,0x4c,0x70,0x87,0xa8, - 0xdf,0xd3,0x23,0x4f,0x92,0xc2,0x26,0xdc,0x5a,0x11,0xaa,0x8b,0x0f,0x4d,0xee,0x87, - 0x78,0xda,0xed,0x4a,0x97,0xea,0x32,0x70,0x7d,0x22,0xa8,0xa6,0xf5,0xdc,0x1b,0x99, - 0xad,0x57,0x43,0xb1,0xa3,0x05,0x14,0x62,0x13,0x70,0xa1,0x0c,0xaa,0x90,0xf2,0x49, - 0xf9,0xb3,0x42,0xb8,0x2e,0x30,0x27,0xf2,0x9d,0x38,0xc2,0x1e,0x4f,0xf5,0xd6,0x86, - 0xd9,0xd2,0x4f,0x96,0x93,0xd7,0x61,0x6d,0x78,0x6e,0x88,0x2e,0x27,0x37,0xdc,0xb9, - 0x93,0xe3,0x81,0xbf,0x25,0xcb,0x93,0xf8,0x27,0x90,0x5e,0xdb,0xa5,0x95,0xf7,0x39, - 0x3c,0xa4,0x99,0xfd,0x1e,0x3c,0x76,0x07,0x59,0xd2,0x1b,0x7e,0x41,0xed,0xd4,0x5c, - 0xd9,0x32,0x95,0xce,0x42,0x79,0xc0,0x7d,0xa3,0x9c,0x34,0x2a,0xb4,0xeb,0xf7,0xe5, - 0x8d,0x40,0x95,0x31,0xed,0x33,0xf1,0x34,0xfc,0xf1,0xae,0x45,0x14,0xb5,0xf9,0x02, - 0xf8,0x67,0x58,0x58,0x9b,0xd5,0x8f,0xcb,0xf2,0x5b,0x05,0x55,0xdb,0x1b,0x62,0x74, - 0x52,0xfe,0x74,0xa6,0x9d,0xc2,0x77,0x5e,0x18,0xc7,0x63,0xab,0xc2,0xa5,0x6f,0x7a, - 0xd4,0xac,0x0e,0xd1,0x4d,0x4f,0x84,0xbd,0xc6,0xd2,0x98,0x89,0x88,0xbc,0x5c,0x70, - 0x3d,0x93,0xc4,0x3f,0xc2,0x76,0xf8,0x31,0x29,0xe8,0x43,0xfc,0xac,0xd0,0x03,0x90, - 0x8f,0x07,0x21,0x6c,0xcf,0x6b,0x24,0xaa,0x11,0x40,0x04,0x28,0x35,0x72,0xa0,0x52, - 0x9f,0x7e,0x7e,0xf2,0xfb,0x1a,0xa8,0x7b,0x9f,0x60,0xb3,0x07,0x32,0xd6,0x90,0x6c, - 0xd8,0xab,0xef,0x52,0x69,0x1d,0x99,0x35,0x0e,0x7b,0xe6,0xcc,0x22,0xe3,0xf8,0x27, - 0x36,0x29,0x7f,0x02,0xb9,0xa7,0xe8,0x96,0x90,0x6a,0xe0,0xb1,0x4a,0x17,0xf6,0x82, - 0x2b,0x68,0x2b,0x27,0x0e,0xad,0x31,0xaa,0xfe,0x89,0x2e,0x5e,0x97,0xc9,0xb6,0x32, - 0x75,0x80,0xde,0x46,0x5e,0xb3,0xe0,0x9f,0x8b,0x91,0x53,0x2a,0xc2,0x36,0xdd,0x56, - 0xae,0x5e,0x84,0x45,0xdb,0xec,0x1f,0xc8,0x73,0x51,0xde,0xb7,0x47,0xdd,0x1d,0xf8, - 0xa1,0x8f,0xeb,0xb1,0x06,0xc4,0x3f,0x87,0x92,0xf8,0x07,0x76,0x66,0x71,0xa5,0x9f, - 0x05,0xb7,0xa0,0x1a,0x22,0x4f,0x11,0x44,0xcb,0x06,0xe2,0x01,0x1f,0xc7,0x3f,0x0c, - 0x06,0xb5,0x71,0xfc,0x33,0xf1,0x3c,0x34,0xf8,0x1e,0x8c,0xea,0x15,0xda,0xa6,0x68, - 0x4d,0x21,0x9a,0x15,0x5e,0xae,0xdd,0xe6,0x84,0x8e,0x45,0x2b,0x35,0x84,0xcd,0x85, - 0xd0,0xa3,0x78,0x71,0x60,0xc5,0x3f,0xd2,0x37,0x3c,0x7b,0x98,0x13,0x41,0x8e,0xad, - 0x10,0x0e,0x0a,0xd7,0x69,0x72,0x1b,0xe9,0x10,0x10,0xf6,0x84,0x22,0xb9,0x04,0x35, - 0x2c,0xea,0x5f,0xd4,0xa7,0xf1,0x49,0xf9,0x90,0x27,0xe1,0x34,0x28,0xd2,0x6e,0xe4, - 0xe8,0x68,0x0f,0x38,0x87,0x71,0x7e,0x21,0x7d,0x14,0xe6,0x05,0x68,0xff,0x96,0x87, - 0xab,0x1f,0x85,0x82,0x5a,0x3a,0x6c,0xc1,0x3f,0x54,0x92,0xe0,0x20,0x53,0x83,0x37, - 0xe6,0x22,0xda,0xd9,0xe3,0x2f,0xd4,0xe4,0x5c,0x92,0x6b,0xc2,0x1e,0x1a,0x24,0xf7, - 0xa5,0xad,0xf5,0xe7,0x6b,0x19,0x56,0xfc,0xd3,0x0d,0x21,0x65,0x04,0x4c,0x74,0xa7, - 0x9a,0xb0,0xc7,0x81,0xb0,0x07,0x61,0x46,0x09,0xe2,0x9f,0x82,0x10,0xd9,0x80,0xa2, - 0x71,0xa9,0x51,0xf3,0x51,0x12,0xff,0xfc,0xcd,0x05,0xf8,0x0c,0x38,0xc8,0x11,0xbe, - 0x87,0x68,0xa7,0x4a,0x73,0x9c,0x16,0xdf,0x23,0x1c,0xf6,0xcc,0x6b,0x13,0x9f,0x9c, - 0xc0,0x3f,0x4f,0x4d,0xe2,0x9f,0x6d,0x33,0x2e,0xc0,0x6f,0xc1,0x77,0xb7,0xdc,0x26, - 0xd6,0xc2,0x31,0xa5,0x54,0xcb,0x7c,0x4d,0x5c,0x10,0x7e,0x05,0x0e,0xe0,0xa0,0x66, - 0x01,0x7b,0x45,0xad,0xc2,0xf5,0x99,0x36,0x67,0xf2,0xfc,0x96,0x2b,0x71,0xe8,0x83, - 0x12,0xbb,0xdc,0x94,0xa3,0x42,0x67,0x6e,0x11,0xcb,0x24,0x36,0x7c,0x1e,0xb4,0x50, - 0x96,0xad,0x25,0xf9,0xda,0x88,0x5a,0x02,0x94,0x89,0x59,0xe9,0x49,0x2b,0xb6,0x97, - 0x6e,0x06,0xf7,0x9d,0xf2,0x75,0x64,0x55,0x5a,0x03,0x71,0x6a,0xf4,0xba,0x70,0x1a, - 0x87,0x3d,0xbd,0xb2,0xe2,0x97,0xa0,0xa1,0xce,0x1d,0xa4,0xb9,0x4e,0x22,0x24,0xf1, - 0x58,0x07,0xb4,0xe4,0x23,0xc8,0x54,0xd2,0x67,0x23,0xfe,0x2c,0xd2,0x10,0x1d,0x15, - 0x9a,0xcb,0x2e,0x47,0xb3,0x0b,0xb5,0xc3,0x6a,0x96,0x3f,0x10,0xcd,0x4e,0x9f,0x94, - 0x0f,0xed,0xd0,0x01,0x6f,0x08,0xbe,0x6a,0x39,0x2a,0xae,0x52,0x8e,0x81,0xf7,0x76, - 0xfb,0x8f,0xc5,0x42,0x38,0x26,0x78,0xb5,0xbb,0xa3,0xf2,0x1c,0xc4,0x3f,0x3e,0xcd, - 0x1d,0x75,0xb8,0x26,0xe5,0x43,0x27,0x74,0xd0,0x04,0xe8,0xcd,0x41,0x18,0x0c,0x3e, - 0xbf,0xe3,0x71,0xb1,0x17,0x61,0x4f,0x45,0xf5,0x46,0x05,0x07,0xef,0xb3,0xca,0x55, - 0x0e,0x05,0x0d,0xb1,0x89,0xf9,0x45,0xa0,0x6b,0x7c,0x77,0xdd,0xcd,0x61,0xcf,0x19, - 0xf0,0x0a,0x69,0xac,0x11,0x3f,0x04,0x79,0x04,0x5c,0x61,0x51,0xc7,0x4f,0xe3,0x45, - 0x44,0x04,0x16,0xfc,0x23,0xe5,0x29,0x47,0xd8,0x1c,0x86,0x42,0x86,0xc2,0x06,0x21, - 0x9f,0xd1,0x21,0xe2,0x42,0x7d,0xe4,0x63,0x91,0x38,0x0e,0x8e,0x44,0x9c,0x2c,0xa0, - 0x8b,0x1b,0x26,0x57,0xc7,0x35,0xe3,0x9e,0xb4,0xbd,0x03,0xee,0x9e,0xeb,0x3d,0xce, - 0x56,0xf8,0x29,0xc4,0xe3,0xd7,0x2f,0xb6,0x49,0xa8,0x2f,0xdd,0xd5,0xa8,0xf1,0x37, - 0x22,0x10,0x72,0xc5,0xd1,0x94,0x48,0xe2,0x9f,0xfc,0xea,0x99,0xb0,0x90,0xce,0x1e, - 0x44,0x18,0x50,0x09,0x8f,0x29,0x05,0x47,0xf3,0xea,0x71,0xff,0x1c,0xb0,0xcd,0x8d, - 0x07,0xea,0xc9,0xcc,0xc2,0x18,0x9b,0xdb,0x8f,0xbf,0xea,0x4b,0xe2,0x2b,0x3a,0x0b, - 0xfe,0x3b,0xab,0x1a,0xcc,0xbc,0x82,0x66,0xda,0xef,0xc2,0xf3,0xe3,0x99,0x6b,0xc4, - 0x59,0xf0,0x27,0xe6,0x8e,0x23,0x10,0x7a,0x02,0x07,0xdd,0x71,0xf7,0x1a,0xf1,0x78, - 0x12,0xff,0x64,0x76,0x4a,0x97,0x60,0x4e,0x7c,0xda,0x3e,0x54,0x73,0x7f,0xd4,0x1e, - 0xe6,0x82,0x9d,0xab,0xf5,0x12,0xae,0xdf,0xd1,0xb0,0x45,0xc3,0xd3,0x11,0x9b,0x16, - 0x9e,0x94,0x3f,0x5a,0xda,0x3b,0xf0,0x1b,0xb6,0xf0,0xf7,0x8e,0x31,0xd1,0x27,0xfd, - 0xee,0xeb,0xa5,0xfc,0x6e,0xfb,0xe1,0x2d,0x56,0x15,0xbf,0x7b,0x8d,0x30,0x4b,0x3b, - 0x8e,0x03,0xc7,0x88,0xd8,0x3f,0x29,0x7f,0x3a,0xa7,0x6f,0x87,0xf5,0x5b,0xf2,0x7b, - 0xe8,0x83,0xb6,0x99,0xf0,0x1b,0x25,0xbf,0x37,0x33,0xc4,0x9f,0xbf,0xa3,0xd8,0x90, - 0x1f,0x22,0x33,0xa1,0x23,0x5a,0xcc,0x45,0xf1,0x07,0x93,0xe7,0x3d,0x0a,0x33,0xe1, - 0x31,0x98,0x6d,0xd8,0xf0,0x7d,0xd5,0xad,0x0a,0x9a,0xb1,0x71,0xb2,0x1d,0x1e,0x0b, - 0x15,0xf7,0xca,0xf5,0xd7,0xdd,0x2f,0x21,0x5e,0x32,0xe4,0x7a,0xb2,0x6e,0xf2,0x7b, - 0x7d,0x3b,0xf7,0x18,0x34,0x2a,0x6a,0x0f,0x2e,0x9a,0x5d,0xdc,0x0a,0x6a,0x7f,0xc6, - 0x53,0x88,0xb7,0xf7,0x12,0x37,0xbf,0xed,0x52,0x44,0x44,0x38,0x58,0x10,0x3e,0xd3, - 0x34,0xb1,0x3f,0x5d,0xd3,0x7f,0x0e,0x6f,0xb0,0x85,0x86,0x6d,0x18,0xf1,0xc3,0xef, - 0xa0,0x4b,0x41,0x69,0xd0,0x24,0xfd,0x0a,0x66,0xe1,0xfb,0xca,0xab,0xa7,0xb7,0x70, - 0x60,0x73,0x28,0x67,0x43,0x53,0xf2,0x79,0x86,0xa4,0xd1,0x6a,0x9f,0x81,0xf6,0xf8, - 0x90,0x7a,0x49,0xf2,0xf5,0x3a,0xfa,0x11,0x36,0xff,0x13,0xf3,0x19,0xcb,0xa2,0xa8, - 0xf1,0x47,0x43,0xbe,0xc4,0x8a,0x4d,0xdc,0xbf,0x41,0x19,0x73,0x5d,0xe6,0x37,0xa9, - 0x37,0xfd,0x1b,0x39,0x47,0x33,0x4f,0x8b,0x65,0xec,0x77,0x7a,0x69,0xbf,0x63,0x58, - 0xae,0x84,0x53,0x90,0xd3,0x87,0x08,0x21,0xbe,0x6a,0x62,0x7e,0x4f,0xd3,0x4a,0xe5, - 0xa0,0x51,0x82,0xf7,0xb7,0xd9,0xc9,0xcf,0x84,0xca,0xf3,0x68,0xad,0xcf,0x81,0x16, - 0x56,0x14,0x97,0xb7,0xaf,0x74,0x6b,0xdd,0x1a,0x0e,0x62,0x24,0xae,0x25,0xf1,0x4f, - 0x09,0xca,0x93,0x12,0xe3,0x46,0x8e,0x7f,0xb6,0x42,0x49,0x3c,0x23,0x96,0x5e,0x08, - 0x2d,0xc4,0x69,0xc8,0xcf,0xe1,0x95,0xc3,0x4a,0x91,0x61,0x8b,0xa5,0xc7,0x27,0xf7, - 0x0f,0x05,0x3b,0x8a,0x29,0xb7,0x81,0xf6,0xbe,0x1b,0x61,0x40,0x89,0x41,0x55,0xdc, - 0x6f,0x8d,0x54,0x35,0x64,0xc5,0xd9,0x44,0xf7,0x00,0x35,0x5a,0xe6,0x93,0xa3,0x93, - 0xfb,0x93,0xd1,0xd5,0x30,0xea,0x32,0x9f,0xdf,0x8d,0xcf,0x3f,0xcb,0x40,0xfb,0xb4, - 0x90,0x9e,0x50,0xbd,0xfc,0x35,0xdd,0xc2,0x19,0x57,0x05,0x0e,0x0a,0xe2,0x64,0xe2, - 0x79,0xf4,0x8c,0x11,0x17,0xd7,0x5f,0x1b,0x87,0xc5,0xb7,0x51,0xbf,0xdf,0x6a,0x38, - 0xe2,0x22,0xc2,0x1e,0xb8,0xd9,0x58,0x66,0x88,0x0f,0xd3,0x31,0x40,0x89,0x34,0x2c, - 0x0e,0x4e,0xca,0x1f,0x43,0x18,0xa3,0x6f,0x1a,0xa5,0x61,0x7b,0x9f,0xf8,0x9c,0xf6, - 0x2b,0xb5,0xa2,0x0f,0x37,0xd2,0x11,0x78,0x95,0xf8,0x8e,0xda,0x47,0xc5,0x47,0xb4, - 0xab,0xd1,0xaa,0x01,0xc7,0x2e,0x71,0x38,0xe9,0xff,0x51,0x3e,0x63,0x61,0x55,0xfd, - 0x09,0x65,0x5b,0x8b,0x8d,0xf7,0x57,0x38,0xcf,0x2c,0xe9,0x22,0x6e,0xfd,0x67,0x74, - 0x5e,0xbf,0xad,0x8b,0x3b,0x6a,0xf0,0x8d,0xe4,0x76,0xc4,0x27,0x93,0xfe,0x9f,0xb4, - 0x57,0x76,0x77,0x17,0x3e,0x13,0xe9,0x64,0xa4,0x15,0xb6,0xdc,0xe0,0x3a,0x25,0x7b, - 0x49,0x2b,0x6b,0x84,0x39,0x47,0x71,0x87,0x2c,0x6d,0xda,0x9b,0x8f,0xd0,0x48,0x25, - 0xe7,0x93,0xfe,0x9f,0x19,0x4d,0xd0,0xc9,0x8a,0x8c,0x3c,0xdd,0xe9,0x06,0xe6,0x72, - 0x72,0x20,0x64,0xa7,0x3f,0x83,0x07,0x70,0x19,0xc7,0xef,0x2f,0x5a,0xf1,0x8f,0x36, - 0x7d,0x00,0x2e,0xb2,0xf2,0x88,0xbd,0x0d,0xbf,0xfe,0x1b,0x1a,0x5f,0x0d,0x1c,0xc8, - 0xf8,0xc5,0x5b,0xb9,0xfe,0xe5,0xc0,0x58,0xd6,0xc5,0x7e,0xab,0xff,0x47,0x7d,0x07, - 0x16,0xd6,0x39,0x5e,0x13,0x86,0xc0,0xdc,0x18,0x88,0x0f,0xe9,0xd5,0xf1,0x81,0x8a, - 0x88,0x88,0xaf,0xd8,0x90,0x05,0xff,0x74,0x90,0x63,0x50,0x16,0xe5,0xb0,0x53,0x79, - 0x53,0x2b,0xe3,0xda,0x1c,0x37,0x1e,0xf5,0x9a,0x3b,0x10,0x11,0xa9,0xef,0xa8,0x63, - 0x87,0x05,0xff,0x9c,0x49,0x73,0x43,0x03,0x4a,0x4b,0xea,0xc9,0x19,0x93,0x22,0x74, - 0xa1,0x41,0x9f,0xc5,0xc7,0x7e,0x1e,0x16,0xbe,0x6b,0x8b,0x39,0x87,0x38,0x7e,0x36, - 0xe4,0x5d,0x16,0xff,0x4f,0x3c,0xed,0xee,0x6a,0x02,0x85,0xac,0x05,0x70,0x5a,0x43, - 0xd3,0x2a,0xfe,0x9a,0x27,0xb5,0xbd,0x30,0xc7,0x28,0xf2,0xe0,0xf7,0xde,0x09,0xee, - 0x5e,0xb9,0xd0,0x82,0x7f,0x46,0x84,0x74,0x6d,0x1d,0xcb,0x1f,0xc8,0x08,0xf8,0x9f, - 0x10,0x1f,0x8d,0xce,0x1e,0xb4,0xad,0x21,0xef,0xd0,0x03,0x3a,0x0e,0x7e,0x40,0xde, - 0x51,0x9f,0x66,0x99,0x71,0xf9,0xdb,0xa4,0x52,0x99,0xb8,0x7f,0x80,0x66,0x19,0x47, - 0xd9,0x02,0xe6,0x98,0x4d,0x4e,0xc1,0x0b,0xb1,0x7d,0xf1,0x12,0x8f,0x78,0x52,0xbb, - 0xa4,0x2f,0x88,0x67,0x95,0xe3,0xf3,0xff,0x1e,0x2a,0x0d,0x47,0xa7,0x90,0x9d,0xf4, - 0xff,0x64,0xee,0x87,0x2b,0xca,0xcd,0x3d,0x59,0xf1,0x1a,0xee,0xfd,0xf3,0x19,0x77, - 0xe3,0xb2,0x68,0x97,0x94,0xc4,0xfa,0xe0,0x09,0xad,0xea,0xc5,0xf7,0xed,0xb7,0xe0, - 0x9f,0x01,0xf6,0x2e,0x57,0x82,0x2c,0x67,0x08,0xde,0xc0,0x6d,0x79,0x33,0x2e,0x0b, - 0xbd,0x2a,0x78,0xfb,0x33,0x63,0xb2,0x3b,0x61,0x98,0xe8,0x28,0xcf,0x27,0xf1,0xcf, - 0xf4,0xe7,0x6a,0xd7,0x49,0xf9,0x1a,0xd5,0xc8,0x3b,0xd0,0x40,0xf3,0xfb,0x6f,0xe4, - 0xf6,0xd4,0xf3,0xba,0xda,0xeb,0x42,0xf9,0xc9,0xed,0x29,0x43,0x0e,0x39,0x93,0xf8, - 0x87,0xc1,0x75,0xf0,0x73,0xa6,0x72,0xd8,0x73,0x4a,0xe3,0x68,0x47,0xe6,0xfe,0x9f, - 0x03,0xd1,0x7c,0x8e,0x88,0x66,0xc1,0x01,0x56,0x1c,0x97,0xeb,0x10,0x6f,0x4f,0xac, - 0x3f,0xe2,0x1f,0x68,0x94,0xd4,0x6a,0xd7,0x2d,0xe4,0x24,0xe5,0x68,0x4a,0xf6,0xf8, - 0x87,0x10,0x58,0x72,0xfb,0xc5,0x6f,0xc7,0x01,0xca,0x1f,0xd5,0x8a,0x7f,0xa6,0x3f, - 0x13,0x3e,0xa7,0xcd,0xd7,0xed,0x83,0x68,0xb4,0x72,0x6f,0x8f,0x69,0x2f,0x5f,0x04, - 0x2f,0x22,0xa2,0x69,0x2e,0x1c,0xa0,0x7d,0x11,0x17,0x2f,0x5a,0xf0,0x4f,0x7c,0xe6, - 0x88,0xea,0xb3,0xcf,0x63,0x62,0x9c,0x8c,0x08,0x3e,0x58,0x66,0xfa,0x43,0x10,0xf6, - 0xf0,0x2b,0xd2,0x38,0x10,0xb2,0xfa,0x7f,0x7a,0x05,0x54,0x8b,0x1a,0x8a,0x91,0x26, - 0x72,0x8c,0x95,0x85,0x36,0x21,0xfe,0x69,0x3a,0xc6,0x61,0xcf,0xe6,0x2f,0xae,0x32, - 0xf5,0xe3,0x54,0xfc,0x23,0x35,0x57,0xb7,0x7f,0x29,0x33,0x97,0xcc,0x86,0x06,0xc3, - 0xf9,0x60,0x56,0xd4,0x76,0x0b,0x34,0xbf,0xeb,0x0c,0x16,0x6f,0xc7,0x2b,0xcd,0x5a, - 0x89,0x46,0xdb,0x2c,0xf6,0x57,0x5e,0x1a,0xbf,0xe8,0x0c,0xda,0xda,0xd2,0x9f,0x84, - 0xe6,0xe0,0x9c,0xfb,0x50,0x8c,0xcc,0xe6,0x3b,0x30,0x88,0xd3,0xd2,0xf0,0x57,0x6e, - 0xfc,0xa7,0xc3,0x56,0xfc,0x93,0x66,0xce,0x97,0xdb,0xd2,0xd7,0xe2,0x40,0x0d,0xda, - 0x72,0xd3,0xd3,0x12,0x6e,0x90,0x5c,0x5b,0x1a,0x69,0xd0,0xdc,0xc1,0xf2,0x5c,0x0b, - 0xfe,0x29,0xcf,0x0c,0xb5,0x47,0x88,0x17,0x36,0xb2,0x02,0x1d,0x5a,0xa5,0x32,0x81, - 0x03,0x21,0xd4,0x6f,0x5d,0x28,0xc7,0x6a,0x42,0xd0,0x47,0x7c,0xd0,0xca,0xac,0xfe, - 0x9f,0x9b,0x2e,0xe0,0xb1,0xaa,0x0a,0x66,0xf6,0x7f,0xf9,0x1b,0x70,0xb9,0xda,0x17, - 0xcc,0x8a,0x16,0x0c,0x98,0xb0,0x67,0x53,0xc2,0xf1,0x85,0xaa,0xbf,0xdf,0xea,0xff, - 0x11,0x06,0xb4,0x13,0x33,0xbc,0xcb,0xf1,0xfc,0x16,0xb2,0x37,0xa8,0x37,0x88,0x83, - 0xd9,0x70,0x2c,0xe4,0x5b,0x8e,0xcb,0x52,0xa8,0xe1,0xd2,0xf1,0x2b,0x2f,0x25,0xf1, - 0x0f,0xf4,0xf8,0x23,0x6a,0x18,0x5c,0x08,0xc3,0x48,0x24,0xd4,0x4e,0x5d,0x8c,0xe8, - 0x61,0x86,0x08,0xcd,0x15,0xb6,0xe1,0x15,0xb5,0x1d,0x32,0x0d,0xab,0xff,0x67,0xc6, - 0x69,0xb6,0x16,0xf2,0x97,0xd3,0x7b,0xb3,0xbf,0xb2,0x63,0x2d,0xc5,0x8d,0x77,0x2f, - 0xc9,0x65,0x6b,0x57,0x15,0x07,0x69,0x30,0x8c,0x83,0xc4,0x95,0xa4,0xff,0x27,0x6f, - 0x46,0x1b,0x4d,0x5c,0x74,0xe6,0xc2,0x93,0x88,0xa8,0x10,0x16,0xb6,0xc1,0xa3,0x30, - 0xb7,0x9a,0x06,0xb3,0x39,0x50,0x44,0x7c,0xc8,0xfd,0x69,0x13,0xfb,0x41,0x9f,0x31, - 0x00,0xc7,0x34,0x6f,0xc0,0x1e,0xad,0xc1,0xaf,0x99,0xef,0xd5,0xb6,0x47,0x39,0xfe, - 0xc1,0xcf,0xda,0x9a,0x18,0x98,0xf8,0x76,0x70,0x72,0xff,0x0f,0x72,0xff,0x4f,0x0f, - 0x2e,0xc2,0x36,0x71,0x80,0x1e,0xcb,0x47,0xfc,0x63,0x2e,0x0b,0x70,0x84,0x2c,0x8e, - 0x23,0xa2,0x68,0x4e,0xd2,0xff,0xe3,0x52,0x74,0x38,0xa3,0xe1,0x6a,0xb3,0x1a,0x55, - 0xea,0x43,0xfc,0x99,0xc9,0x81,0x68,0x9f,0xe9,0x7f,0xc3,0x41,0x80,0x0f,0x0c,0xd1, - 0x36,0xb9,0xff,0x5d,0x69,0x2e,0xc5,0x74,0x32,0x77,0x38,0x5d,0xb0,0x01,0x05,0x17, - 0xd5,0x89,0x8b,0xbe,0x09,0x65,0xdd,0x36,0x1c,0xe0,0x15,0x67,0x03,0x5e,0xb1,0x25, - 0xf1,0x49,0xda,0x52,0x40,0xa3,0x20,0xbe,0xbc,0x82,0x64,0xa1,0xfe,0x0a,0xf5,0x5c, - 0x5f,0x8e,0x82,0x1a,0x0f,0xce,0x08,0xe5,0x57,0x1a,0x99,0x3a,0x1c,0x28,0xf7,0xdb, - 0xa4,0x89,0xef,0xab,0x0b,0x0b,0xe0,0x31,0x2d,0xbf,0x9f,0x7e,0x8f,0xdc,0x04,0x3f, - 0x42,0x60,0x40,0x57,0x71,0x3c,0xc0,0x66,0x6b,0xb6,0xef,0xf9,0x6f,0x82,0xf5,0xfc, - 0x57,0x0f,0xe3,0x3f,0x34,0x71,0xff,0x4e,0xb8,0x01,0xde,0x61,0x7b,0x75,0xd7,0xa0, - 0xad,0x82,0xbc,0xc6,0x4a,0xf5,0xcc,0x11,0xb9,0x0b,0x7a,0x99,0x47,0x97,0x06,0xe5, - 0x0a,0x72,0x8a,0xed,0x8d,0xbb,0x07,0xe5,0x22,0x8b,0xff,0xa7,0x03,0x3e,0xe0,0x4e, - 0x78,0xbd,0x66,0x10,0x3e,0x48,0x58,0xf7,0xab,0xf9,0xb2,0x00,0x0e,0x86,0xf8,0x79, - 0x34,0x52,0xfd,0x3f,0x69,0x57,0xa0,0x87,0x95,0x86,0xb2,0xce,0x14,0xec,0x67,0x27, - 0x58,0xe9,0x80,0xe3,0x8c,0x78,0x05,0xae,0x46,0x4b,0x07,0xec,0x67,0xc4,0xcf,0xe1, - 0x9f,0x59,0xa9,0x6a,0x5f,0x2e,0x26,0xfd,0x3f,0x9d,0x42,0x13,0x5b,0xdb,0xb1,0x33, - 0x88,0x66,0xbb,0xc4,0x7e,0xbb,0xe5,0xd9,0x38,0x0a,0xa2,0xb7,0xd1,0xb0,0x9a,0x3b, - 0x78,0xd7,0x74,0x1c,0x3c,0x2b,0x7d,0xc1,0xb0,0x2d,0x27,0x16,0xff,0x8f,0xb6,0x4d, - 0x6a,0x55,0x67,0x13,0x5b,0x30,0x1c,0xed,0x4d,0xa7,0xf9,0x7d,0xb6,0x20,0xe9,0x87, - 0x7d,0x90,0x6f,0x64,0xd4,0xe3,0xa0,0x0d,0x66,0x03,0xed,0xf3,0x43,0xd2,0xff,0x93, - 0xfb,0x92,0xc6,0xa4,0xc2,0x72,0x9a,0x87,0xaf,0xd4,0x85,0x62,0x9c,0x82,0xff,0x24, - 0xec,0x91,0x4c,0x0b,0xf7,0x24,0x9a,0x13,0xa8,0xfa,0x81,0xd0,0xc9,0xfd,0xd9,0x39, - 0x63,0x37,0x1a,0x89,0x0b,0xfa,0xb3,0xba,0x51,0x6d,0xb5,0x48,0x5e,0x2d,0x2b,0xe1, - 0xcf,0xf1,0x1a,0x99,0x89,0x81,0xa9,0x71,0x8a,0x2c,0xf2,0xf0,0xa4,0x74,0x29,0x58, - 0xd1,0x6f,0xba,0x7d,0xde,0xa8,0xf6,0x55,0x67,0x71,0xa0,0x78,0x89,0x3c,0x32,0xfe, - 0x87,0x09,0x0d,0x98,0xf4,0x3f,0x08,0xca,0x07,0xf0,0xea,0x96,0xd2,0x7e,0x7b,0x5c, - 0xbc,0x9f,0xeb,0x93,0x26,0xfb,0xe8,0x17,0x87,0xe1,0xa2,0xba,0x98,0x65,0xc5,0x0b, - 0x46,0xf8,0x42,0x19,0x8e,0x41,0x02,0xb5,0x49,0xf9,0xf3,0x40,0xb0,0xd1,0x70,0xc6, - 0x6d,0x9d,0xc4,0x2d,0xfd,0x5a,0x6b,0x67,0xf4,0x39,0xae,0x76,0x59,0x09,0x64,0xea, - 0x7c,0x60,0x94,0xa1,0xfc,0x44,0x8b,0x63,0x12,0xff,0x08,0x6e,0x68,0xb1,0xaf,0x34, - 0xe8,0x7c,0xf2,0x00,0x69,0xa1,0x45,0x9a,0x2d,0x16,0x4e,0xa8,0x69,0xd3,0x71,0x7a, - 0x98,0x3a,0x41,0xde,0x43,0xf4,0xa4,0xfc,0xc9,0xb5,0x67,0xb7,0xa8,0xed,0x88,0x7f, - 0xb2,0x37,0xa1,0x59,0xe1,0x0a,0x16,0x71,0x7f,0xe3,0xde,0x52,0x37,0x37,0xf3,0xb9, - 0xa3,0xbe,0xd0,0x68,0x89,0x85,0xc3,0x49,0xff,0x4f,0xda,0xb7,0xb4,0x13,0x21,0xd3, - 0x88,0xbe,0x7b,0x7a,0x4b,0x7d,0xf9,0x1b,0x59,0x88,0xbe,0xe0,0xa2,0x6b,0xe6,0x19, - 0xdb,0xb3,0xf8,0x9a,0x9f,0x72,0x8b,0xec,0x69,0x91,0x89,0x13,0xd3,0xf5,0x19,0x63, - 0xd2,0xd5,0xf2,0x79,0xc6,0xa6,0x61,0xf1,0xe1,0xd6,0xab,0xa1,0xb2,0x93,0x8f,0x72, - 0xb5,0x75,0x49,0xf5,0xbd,0x29,0x0f,0x0b,0x63,0x60,0xea,0x77,0x5d,0xac,0x9b,0x36, - 0x89,0x37,0xd2,0x2e,0xe2,0xfe,0x59,0xa8,0xdb,0x8f,0xe5,0x94,0xd1,0xab,0x4a,0x29, - 0xd8,0x07,0x39,0x50,0x64,0x55,0x47,0xed,0x7d,0x05,0x5e,0x18,0xa3,0x0b,0xa3,0xf6, - 0x11,0x71,0x78,0x52,0xfe,0x30,0xe5,0x23,0x44,0x83,0x4e,0x9d,0x12,0x34,0x8b,0x9e, - 0xd7,0x9c,0x40,0x55,0x34,0x04,0x5a,0xd8,0xbc,0xe1,0x00,0x02,0x21,0xb5,0xbb,0xda, - 0x19,0x40,0x20,0x14,0x9f,0xfc,0xbe,0x34,0xcd,0x80,0x06,0xa9,0xd0,0xd8,0x60,0x9b, - 0x53,0x0b,0x3b,0x57,0xaa,0x52,0x86,0x8a,0x66,0xbe,0x88,0x78,0xd8,0x16,0xdb,0x92, - 0x05,0xb1,0xce,0x42,0x83,0x7a,0xc3,0x47,0x2d,0xf8,0xe7,0xdf,0x64,0xbc,0x7f,0xbb, - 0x8d,0xda,0x56,0xe3,0x6a,0x38,0xdf,0xcd,0xc0,0x0f,0x61,0xc2,0x06,0x1b,0x47,0x98, - 0x5d,0x61,0x67,0xfc,0x86,0x58,0x0a,0xfe,0x39,0x01,0x2f,0xf4,0x2e,0xd0,0x4b,0xb6, - 0x89,0xdf,0xd4,0x2e,0x11,0x6f,0x7d,0x66,0xa7,0xec,0x26,0x27,0xf0,0x98,0x64,0xed, - 0x6b,0x2c,0xd1,0x2e,0xb2,0x32,0xc0,0xa5,0x4b,0xe2,0xff,0xb8,0xf0,0x1c,0x2e,0xc2, - 0xcd,0x2c,0xb3,0x3f,0x67,0x1f,0xa2,0x9d,0x5f,0x6a,0x25,0x3c,0xcc,0xc7,0x97,0x25, - 0xd3,0xcf,0x1d,0x83,0xb0,0x98,0xe3,0x43,0xab,0xff,0xa7,0x13,0xfe,0x18,0xf4,0x32, - 0x94,0x36,0x73,0xe0,0x8f,0xa4,0x82,0x1f,0x43,0x37,0xf0,0xfb,0x3b,0x8e,0xa0,0xfc, - 0xb9,0xa8,0x54,0xc4,0x37,0x76,0x21,0x3e,0x9c,0xd8,0xff,0x7d,0x69,0xc5,0xd0,0x12, - 0x46,0xf9,0xc3,0xc4,0xbf,0x87,0x4d,0xe0,0xac,0x96,0x75,0x5c,0x9f,0x13,0x50,0x7c, - 0xb4,0x31,0x46,0x8a,0x43,0x87,0xc1,0x19,0xca,0x3a,0x42,0xce,0x5b,0xf0,0xcf,0xd2, - 0x17,0xf6,0xc6,0x75,0x9d,0xaa,0xd9,0xb7,0xc3,0x4e,0xe2,0xe2,0xde,0x42,0x0e,0xa4, - 0xdd,0x71,0xdb,0x02,0x94,0x3f,0x7b,0xfb,0x5c,0x11,0xdb,0x82,0xec,0x64,0xfc,0x2b, - 0x24,0xcc,0x62,0xff,0x1a,0xcd,0xd7,0x5d,0xdf,0x22,0x5f,0x85,0xc6,0x68,0x7e,0x08, - 0xb5,0xff,0x2c,0x04,0x06,0x08,0x03,0xd6,0x64,0x67,0xc3,0xb3,0xd1,0x15,0x67,0x11, - 0x11,0x9d,0xb1,0xc4,0xbf,0xec,0xf0,0x69,0xdc,0xb3,0x2e,0xe0,0x91,0x43,0x88,0x76, - 0xca,0x99,0x63,0x8e,0xec,0xf6,0x6f,0x8d,0x55,0xf6,0xa1,0x22,0xb3,0xc3,0x25,0xbd, - 0xdb,0xc8,0xf2,0x88,0x96,0xf8,0xd7,0x4d,0xdb,0xa3,0x1f,0xc3,0xe2,0x06,0x5c,0x84, - 0x0b,0xf0,0xb1,0xe6,0xe3,0x68,0x70,0x4c,0x33,0xb7,0xcd,0xf0,0xf8,0x42,0xe1,0xf9, - 0xb2,0xe2,0x9f,0x21,0x78,0x81,0x3b,0xa5,0x63,0xd3,0xe6,0xc0,0x5b,0xda,0x42,0xd5, - 0xae,0x8b,0x1f,0x86,0x70,0x7d,0x5e,0xb2,0x77,0x8b,0x6e,0xd2,0x22,0xa0,0x61,0x1e, - 0x2b,0xb0,0xe2,0x9f,0xed,0xb0,0x0e,0x76,0x80,0x1c,0x14,0x17,0xc0,0xfa,0xc2,0xb9, - 0x9a,0xbd,0x1e,0xb7,0xfd,0x7a,0x14,0x0b,0xa6,0x45,0xb9,0x11,0x0d,0x4c,0xb9,0xde, - 0x69,0xf5,0xff,0xfc,0x2b,0x97,0xae,0xba,0x7c,0x86,0xfc,0x58,0xda,0xba,0x65,0xb6, - 0x27,0xa3,0x2e,0xfd,0x1d,0xc0,0xf7,0x7d,0x9f,0xae,0xb1,0xcd,0x82,0xf5,0x47,0x9f, - 0x54,0x11,0x11,0x0d,0xa7,0xe0,0x9f,0xad,0x2b,0xd4,0x98,0x1c,0x25,0x12,0x6e,0x1b, - 0x57,0xd0,0xf5,0xb8,0xf3,0x24,0x77,0xab,0x1a,0x79,0x92,0xd3,0xa9,0xb5,0x18,0x73, - 0x1e,0x42,0x44,0x6d,0xf5,0xff,0x1c,0x22,0xaf,0xc3,0xc2,0xe8,0xa6,0xb8,0xd8,0x0d, - 0x6f,0xc2,0x42,0x3d,0x73,0x40,0x1c,0x44,0x7b,0xd7,0xd7,0x30,0xb3,0x53,0x74,0xa1, - 0x7d,0xb4,0x70,0xd7,0x32,0x3d,0x05,0xff,0x9c,0xe5,0x41,0xae,0xeb,0x36,0x45,0x96, - 0xb4,0x73,0xb7,0x0f,0xcd,0x62,0x8d,0xdc,0xff,0xf3,0x30,0xcc,0x5b,0xdb,0xf8,0x7b, - 0x09,0xb5,0x86,0xe2,0x68,0x4a,0xc1,0x3f,0x03,0xa8,0xc4,0x2b,0x42,0x59,0x51,0xf1, - 0x9b,0xe3,0xfe,0x9f,0x82,0x42,0x44,0xd4,0xbe,0x6f,0x65,0x6e,0x17,0xcf,0x71,0xfd, - 0x18,0xb2,0xff,0x44,0x24,0x96,0xf8,0xd7,0x1d,0xe1,0x66,0x41,0x7d,0x88,0x46,0x71, - 0xff,0x1c,0x24,0xdc,0xed,0x30,0x1e,0xf6,0xa2,0x4f,0x90,0x3f,0xf0,0xf8,0x4b,0x2d, - 0xdd,0x46,0x54,0x0b,0xfe,0x29,0x14,0x9a,0xd5,0xa2,0x5a,0x5b,0xd4,0xe6,0xae,0xdd, - 0x05,0xe3,0x8e,0x23,0x3e,0x3f,0xa3,0x3f,0xfb,0x82,0xd6,0xcc,0x10,0xf8,0x45,0x49, - 0xba,0xd5,0xff,0x23,0x70,0x6f,0x06,0xcd,0x25,0x5f,0x84,0x3d,0x9a,0x1e,0x94,0x73, - 0x11,0x26,0x35,0x00,0xc2,0xa4,0xfb,0xc8,0x6f,0xa1,0xa1,0x5a,0x0d,0xe2,0xaf,0x88, - 0x15,0xff,0xa0,0xb6,0xad,0x80,0x7b,0x10,0x6f,0xd0,0x41,0xc1,0x03,0x9b,0x12,0xfa, - 0xd7,0x07,0x8f,0x32,0xdc,0xf6,0x7d,0xe9,0x5e,0xe6,0xd6,0xe5,0x2c,0x0b,0xfe,0x39, - 0x0d,0xbf,0x44,0xc1,0x30,0x2d,0x88,0xfb,0x67,0x54,0xab,0x0a,0x6e,0xea,0x17,0xdf, - 0xe3,0xfa,0x2b,0x38,0x4f,0x41,0xfd,0x7e,0x19,0xaf,0xa0,0xc6,0xb7,0xc6,0xbf,0x4e, - 0xc3,0xcb,0x68,0x94,0x2d,0xdb,0x57,0x50,0x09,0x6f,0x40,0x59,0x70,0xbb,0x82,0xf3, - 0x8f,0xe1,0x15,0x7b,0xbf,0x78,0x41,0xfb,0x65,0x60,0x6f,0x00,0x07,0xe9,0xc9,0xf8, - 0x97,0x12,0x87,0x88,0x50,0x02,0x32,0x23,0x21,0x36,0xa8,0x3a,0x21,0x2f,0x4c,0xce, - 0x9a,0xfe,0xa8,0x48,0x18,0x05,0x63,0x2c,0xdf,0x69,0xa3,0x61,0x92,0x65,0x91,0x3f, - 0x27,0xcd,0xb7,0x6b,0xc9,0x26,0xb5,0xae,0x3d,0x81,0xc2,0x60,0x44,0x09,0xbf,0xc8, - 0xf0,0x4a,0x90,0x2a,0x5b,0x7a,0xd9,0x1e,0x15,0xdf,0x57,0x69,0xb7,0xf8,0x7f,0x66, - 0xf0,0xf8,0x57,0x49,0x00,0x97,0x65,0x95,0xb2,0x8b,0x38,0xfd,0x94,0x8b,0x71,0xbe, - 0x9e,0x45,0x6d,0xe4,0x43,0x5c,0x31,0x04,0x96,0x31,0x92,0x6e,0x89,0x7f,0xbd,0x04, - 0xc7,0x54,0xdf,0xf2,0x65,0xdb,0xe4,0x39,0x4d,0x6f,0x90,0xb2,0x7a,0x8a,0xc0,0x86, - 0x1c,0x9b,0xe6,0xab,0xb6,0x6f,0xc3,0xef,0x3b,0xca,0xbc,0x41,0x77,0x54,0x74,0x49, - 0x49,0xfd,0xdb,0xe1,0x1f,0xe5,0xfe,0x9f,0x9f,0x14,0x3c,0x0d,0x67,0xa5,0xca,0xc0, - 0xbc,0x36,0xb1,0x17,0xd7,0xa7,0x52,0xcb,0x7c,0x3c,0x67,0x80,0x8d,0x2a,0xbe,0x7a, - 0x47,0x54,0xfe,0xc0,0x82,0x7f,0x54,0xc4,0x3f,0xb8,0xa9,0x98,0xac,0x33,0xbe,0xec, - 0x1c,0x08,0xf1,0xf5,0x97,0x32,0xd7,0xf3,0x88,0xa4,0x56,0x01,0xf6,0x70,0x4a,0xfc, - 0xeb,0x36,0x65,0x63,0x4f,0x41,0x58,0xd6,0xb3,0x2b,0x60,0x43,0x5a,0x09,0x77,0x04, - 0xd5,0x21,0xec,0x29,0xd1,0xe9,0x00,0xa9,0x70,0x6e,0x84,0x82,0x68,0x60,0xc0,0x1a, - 0xff,0x4a,0x5b,0xaa,0x6e,0xd5,0x5d,0x2b,0x51,0x3b,0x6f,0x32,0x8f,0x09,0x9a,0xa5, - 0x1c,0xff,0xb8,0x43,0x19,0xe5,0xdc,0x50,0x65,0x45,0xaf,0xb8,0xf6,0x58,0xfc,0x3f, - 0xba,0x50,0x09,0x9b,0x8c,0x7c,0x43,0x7e,0x30,0x6b,0x96,0xfa,0xb4,0x9a,0xd9,0x47, - 0x2f,0x92,0x93,0x8c,0x9f,0xdf,0xc8,0xf2,0xec,0x1b,0x10,0xff,0xac,0x60,0x78,0x90, - 0x93,0xf1,0xaf,0x4e,0x3a,0x0b,0x7e,0xc3,0xe6,0xaa,0xcb,0x2e,0xca,0x47,0xc8,0xcb, - 0xd1,0xaa,0x61,0xfb,0xc3,0xe2,0xbf,0x92,0x97,0xd9,0xe2,0x78,0xda,0x08,0x1a,0xda, - 0x2f,0xb3,0xc3,0xdc,0x11,0x64,0x89,0x7f,0xdd,0xb4,0x7b,0x3a,0x1a,0x4d,0x82,0x63, - 0x3f,0xee,0x9f,0xb7,0x34,0xdf,0xd1,0x79,0xfb,0xc5,0xef,0xe8,0xdc,0x8c,0x5a,0x16, - 0x35,0x15,0x3d,0x22,0xa2,0x98,0x15,0xff,0xcc,0xf8,0x48,0x7b,0x99,0xc3,0xaa,0xb1, - 0x02,0x1f,0x5c,0x8d,0x94,0xc6,0xed,0x63,0xa2,0x0f,0x4e,0x44,0xab,0xe2,0x68,0xbf, - 0xe3,0x15,0x56,0x1a,0x9f,0x36,0x6a,0xc5,0x3f,0xd3,0x9f,0xd0,0xd6,0x43,0x3e,0x3e, - 0x64,0x58,0x41,0xb3,0x34,0x9f,0x8b,0x9d,0x99,0x08,0xf3,0x8a,0x0d,0xd7,0x77,0x49, - 0x1e,0xec,0xc9,0xcb,0x8f,0xc8,0x67,0xc9,0x33,0x96,0xf8,0xd7,0x76,0xb6,0x5e,0xd9, - 0xc9,0x10,0xed,0xe4,0xa9,0x07,0x60,0x47,0x2f,0x7d,0x30,0x3c,0x13,0xd6,0xab,0xc5, - 0xbd,0xb6,0x7a,0xa2,0xa0,0xbd,0xb6,0x83,0x2d,0xd1,0x88,0x05,0xff,0x48,0x27,0xa5, - 0x46,0xaa,0xea,0xb8,0x8c,0x22,0xd7,0x5f,0x7c,0x3d,0xed,0xe6,0xc2,0xda,0x2a,0x89, - 0x8c,0xf8,0x41,0xcd,0xe5,0xc0,0x3d,0x89,0x7f,0xd2,0x4a,0x5a,0x99,0xd3,0x5b,0x9e, - 0x39,0x2c,0x17,0xa2,0x74,0x2d,0x7d,0xcd,0x35,0x22,0x57,0x9a,0xfa,0xcb,0x76,0xb0, - 0xb1,0x58,0xbd,0xa4,0x74,0xf5,0x2f,0xd3,0x6b,0x2c,0xf8,0x47,0x8b,0xab,0xb8,0x1a, - 0xca,0xb2,0x58,0xcd,0x7b,0x0c,0x07,0x7d,0x8e,0x2e,0x93,0x8f,0x51,0x69,0xdc,0xd9, - 0x26,0x7e,0x88,0xe6,0xb1,0x2f,0xb2,0x6c,0x9f,0x15,0xff,0xc0,0x15,0xed,0x14,0x1c, - 0x76,0x2e,0x1b,0x46,0x79,0x8b,0xf7,0x37,0xec,0xc3,0xa8,0xdf,0xd1,0xde,0xef,0xc5, - 0x63,0x35,0xa6,0x5e,0x62,0xa5,0x5c,0xb0,0x27,0xe3,0x5f,0x0d,0xb9,0xcb,0x48,0x4b, - 0x1c,0x41,0x4b,0x8c,0xdc,0x82,0x30,0xc6,0x7c,0x7e,0xb7,0x89,0x67,0x02,0xdb,0xc8, - 0x47,0xb0,0xed,0x8c,0x53,0x97,0x9f,0x4b,0xf1,0xff,0xb8,0xd5,0x16,0x56,0xd4,0xb6, - 0xc4,0x73,0x97,0xb3,0xd0,0x7c,0x5f,0x54,0xd3,0x94,0xcf,0x47,0xe0,0xf4,0x01,0xfe, - 0x61,0xbb,0x53,0xee,0x4c,0x89,0x7f,0xd9,0xa1,0x45,0x41,0xeb,0xc5,0x83,0x8b,0x56, - 0x0a,0x3a,0x9f,0x6f,0xa7,0xdc,0x2c,0x75,0x79,0x88,0xa1,0x44,0xa7,0xab,0x20,0x83, - 0xc5,0xfe,0x82,0xcc,0xd5,0x4d,0x27,0x48,0x05,0x73,0xd4,0xa3,0xd8,0xb9,0x0a,0xf3, - 0x7b,0x66,0xd6,0x8b,0x33,0x11,0xe6,0xf9,0x0c,0x34,0x2b,0xe2,0xf8,0xe2,0x68,0xb1, - 0x32,0x4b,0xfc,0x4b,0xcf,0x7c,0xbb,0xfa,0x6a,0xfe,0xad,0xcc,0x31,0x9c,0x33,0x0c, - 0x49,0xb5,0x55,0x5e,0xd5,0xe3,0xd0,0x50,0x5e,0xbd,0xad,0x3e,0xcf,0xfd,0xf3,0x16, - 0xff,0x4f,0xda,0x79,0x38,0xc1,0x6e,0x0d,0xe1,0xc5,0x4a,0xe8,0x5f,0x7b,0xeb,0x8a, - 0xcc,0x11,0xf1,0x7b,0x26,0xfe,0xc9,0x1c,0x15,0x3d,0x70,0x12,0x72,0x00,0x17,0x2a, - 0xc9,0xff,0xe1,0xf8,0xe7,0x04,0xf7,0xcf,0x47,0xc8,0x1c,0xf2,0x06,0x6b,0x0f,0xd1, - 0x6e,0x7f,0x09,0x69,0x69,0x9a,0x37,0x8c,0x2f,0xe2,0x24,0x11,0xe6,0x54,0xb9,0x7c, - 0x4e,0xca,0x9f,0xdb,0xe3,0xb4,0x05,0x0a,0xf9,0x4b,0xb9,0x21,0x06,0x85,0x5a,0x86, - 0x87,0xac,0x36,0xf7,0x43,0x86,0x17,0xc1,0x13,0xc3,0x8d,0x83,0xc0,0x2f,0x29,0x7f, - 0x8c,0xe9,0xee,0xd0,0x4f,0x5b,0x9d,0xa1,0x25,0x08,0x03,0xa4,0x6d,0xac,0x48,0x0b, - 0xc4,0x48,0x91,0x8a,0xf8,0xa7,0x87,0x7a,0x6c,0x3a,0x44,0x5c,0x4e,0xe2,0x8a,0x12, - 0x8f,0x25,0xfe,0xd5,0x00,0xc7,0x8e,0x96,0x3d,0x34,0x6d,0x83,0xec,0x66,0x67,0xf4, - 0x32,0x2d,0xd3,0x23,0xfe,0x03,0x2c,0x01,0x5f,0x4f,0x66,0x6c,0x5a,0xa1,0x76,0x02, - 0xba,0xfa,0xdd,0xcf,0xb6,0x80,0x25,0xfe,0xb5,0x0f,0xc5,0xd8,0x0f,0x35,0xc7,0x9d, - 0xe2,0x80,0x76,0x19,0x16,0x6a,0x49,0xb5,0x3e,0x2c,0x7e,0x93,0x5e,0x0a,0xfb,0x06, - 0x70,0xa9,0xad,0xf8,0xa7,0x1d,0xde,0xf7,0x57,0x2c,0xb5,0xb3,0x9c,0x0f,0xc9,0x19, - 0xa1,0x4c,0x2b,0x8e,0xd5,0x7c,0x68,0xee,0x37,0x3c,0x86,0x2f,0xc2,0xaf,0x35,0x4f, - 0x7f,0xeb,0x9e,0x69,0xb1,0x24,0xff,0x47,0x9a,0x8d,0x68,0xdf,0x19,0x72,0x3d,0x49, - 0x5e,0x86,0xfe,0x7e,0xd5,0xa0,0xdd,0xe1,0x93,0xf0,0x53,0xf8,0x87,0x1e,0x04,0xae, - 0x1f,0xa9,0x2d,0x41,0xbe,0x43,0x6a,0xba,0x92,0xf8,0x47,0xd2,0xd4,0x1d,0x50,0x57, - 0x6f,0x13,0xc8,0x29,0x95,0xb1,0xc2,0x6a,0xdc,0x6f,0x27,0x25,0xd3,0x4d,0xe1,0x21, - 0x7d,0x84,0xe1,0xd2,0xa1,0x29,0xd1,0x6d,0xc1,0x3f,0x37,0x48,0xbf,0xd4,0xf3,0x07, - 0x6c,0x01,0xff,0xeb,0x6a,0x2b,0xcb,0xff,0xbf,0x38,0xed,0x07,0x1e,0xd3,0x8b,0xe3, - 0x08,0x7b,0xde,0xd4,0x9a,0xd8,0x6c,0x95,0x7e,0x2d,0x7d,0x9b,0xc5,0xff,0x53,0xab, - 0xbd,0xaf,0x97,0x1b,0x25,0xa2,0x78,0x92,0xb0,0xd6,0x05,0x2a,0xe7,0xff,0x68,0x9f, - 0x32,0x77,0xdc,0x31,0x5f,0x3c,0x06,0xdc,0x94,0x71,0xdf,0xf0,0xe5,0x2d,0x16,0xfc, - 0xf3,0x1c,0x8c,0x28,0x55,0xc6,0xdd,0x67,0xff,0x6a,0x8c,0xeb,0x77,0xcd,0xf1,0x09, - 0xe2,0x9f,0x1f,0x22,0x9e,0x19,0x5f,0xa8,0x45,0xbd,0x38,0xb0,0xe0,0x9f,0x19,0x83, - 0x3a,0x5a,0xaf,0x3d,0x25,0x86,0x70,0x92,0xfb,0xe7,0xb5,0xcc,0x98,0x60,0xc6,0xa3, - 0x2f,0xba,0xb9,0x3d,0xf2,0x16,0x74,0x71,0xe8,0x6e,0xc5,0x3f,0xdb,0xe0,0x59,0xa1, - 0xc0,0xa0,0x21,0xe7,0x69,0xe9,0x25,0x72,0xab,0x46,0xeb,0xfd,0x6f,0xdb,0x0f,0x40, - 0x71,0x1f,0x0a,0xa2,0x33,0x74,0x1d,0x17,0x4d,0x41,0x2b,0xfe,0xd1,0x9e,0xa8,0xfd, - 0x25,0x9b,0xfb,0xc9,0x92,0xa5,0x2b,0xdf,0x44,0x51,0x34,0x57,0xc5,0xf7,0xfd,0x1d, - 0x1c,0x58,0xe7,0xe6,0x61,0xaf,0x97,0xa1,0x81,0xa9,0x21,0x3a,0x05,0xff,0xd0,0x3d, - 0x7b,0xd4,0xe1,0xb9,0xbe,0xec,0x93,0x8c,0x35,0xb9,0x07,0xf0,0x58,0x9d,0x32,0xdd, - 0x3e,0x7c,0x61,0x49,0x63,0x54,0x1d,0x70,0xe5,0xaf,0xb3,0xe0,0x9f,0xb4,0x67,0xd8, - 0xe7,0x64,0x11,0xbb,0x79,0xb5,0x78,0x89,0x7d,0x4d,0xff,0x27,0xdd,0xae,0x4f,0xbb, - 0x64,0xba,0x7d,0xec,0x3a,0x19,0x85,0x53,0x5a,0x69,0xd4,0x3e,0x64,0xc5,0x3f,0x42, - 0xc2,0xc9,0x53,0x92,0xa0,0xc1,0xfc,0xa3,0xf2,0x00,0x0e,0xca,0xc7,0xdd,0x3e,0x06, - 0x0c,0x52,0x1f,0x49,0xf5,0xff,0x00,0xda,0xfb,0x30,0x67,0xa5,0x1a,0x9d,0x56,0x08, - 0x19,0x1d,0x5e,0x04,0x42,0x66,0xe0,0xe3,0x11,0x1e,0x08,0x2b,0x54,0x7b,0xc0,0x33, - 0xc5,0xff,0x03,0xab,0xe1,0x60,0x9a,0xaa,0xd1,0xcd,0xe2,0x1d,0x91,0x06,0xc3,0xb5, - 0x26,0xd0,0xc6,0xf9,0x27,0x68,0xdf,0x21,0x10,0x9a,0x8d,0xf8,0xa7,0x3d,0xe8,0x6a, - 0x43,0xc5,0x37,0x89,0x7f,0xa4,0x0e,0xe1,0x20,0x94,0x20,0xfe,0x21,0x85,0xe1,0x5d, - 0x9a,0xb3,0xd7,0xd6,0xe6,0xc4,0xf9,0xa8,0xaf,0x97,0x28,0xa4,0x30,0x1f,0xa1,0x8e, - 0x7f,0x8a,0xff,0x27,0x3d,0xe3,0x20,0xc2,0xc2,0x1b,0xa2,0x36,0x09,0x76,0x91,0x22, - 0x6d,0x39,0xe7,0xff,0xec,0x01,0x97,0x26,0xe7,0xda,0x24,0xa1,0x81,0xf3,0xcd,0x14, - 0x92,0xb4,0xbf,0xca,0x33,0xe2,0x0a,0x7f,0xbb,0x8d,0x3a,0x82,0xae,0x41,0xe0,0x8e, - 0x20,0x31,0x4e,0x47,0x10,0x6f,0x2c,0x4b,0x28,0x62,0xd3,0x11,0x61,0x89,0x7f,0xdd, - 0x34,0x20,0x7d,0x86,0xc7,0xea,0xee,0xd3,0xe2,0x67,0xe4,0xdf,0xc9,0x62,0xee,0xd6, - 0xf8,0xcc,0xc4,0x3f,0x0e,0x3e,0xb8,0xec,0x47,0xfc,0x73,0xda,0x12,0xff,0xca,0x9b, - 0xce,0x57,0xe3,0xb6,0xa0,0xfd,0x35,0x71,0x01,0xfb,0x90,0x7b,0xa7,0xfb,0x4d,0x37, - 0xc8,0x0f,0xee,0xb2,0x73,0x7f,0xc8,0xb1,0x0c,0xaf,0xdf,0xb1,0xa5,0xe6,0x5c,0x12, - 0xff,0x00,0x67,0xfb,0x38,0x23,0xae,0x26,0x51,0xa5,0x9d,0x60,0x02,0x21,0x7e,0xa5, - 0x44,0xb1,0x11,0x72,0xf6,0xde,0x08,0x38,0x15,0x79,0xc0,0x7f,0x6a,0x72,0xfd,0x21, - 0xad,0x17,0x57,0xc3,0x15,0xa0,0xd7,0x93,0x6f,0xd0,0x7c,0x04,0x42,0x37,0x2a,0xe4, - 0x45,0xee,0x81,0xd7,0x6e,0x50,0x8e,0xbe,0x2e,0xac,0x65,0xf9,0xa1,0x96,0x2f,0xa5, - 0x27,0xed,0xaf,0xbc,0xe9,0x1d,0x26,0xdb,0x8a,0x6e,0xc9,0xfe,0x7b,0xd8,0x95,0x5f, - 0x72,0x47,0x0b,0xe2,0x9f,0xd0,0x41,0xa1,0x44,0xb3,0x45,0xfd,0xe7,0x10,0xf4,0xed, - 0xd4,0x10,0x8a,0x5b,0xf8,0x3f,0x52,0x87,0x7a,0x10,0x2a,0x78,0x34,0xf3,0xef,0x61, - 0xae,0x6a,0xb2,0x77,0xfe,0xc0,0xdf,0x57,0xdb,0x18,0xe5,0x40,0xae,0xd6,0x1b,0x74, - 0x6c,0x9f,0x96,0xe4,0xff,0x3c,0x63,0xee,0x07,0x1f,0x0f,0x72,0x75,0x28,0xa3,0x09, - 0xf6,0xd7,0x39,0x73,0xfe,0xcd,0x51,0xb1,0x97,0xe2,0xe0,0x4e,0x47,0x34,0xe7,0x03, - 0x65,0xe2,0xfe,0x2e,0xd8,0x69,0x7a,0x17,0xed,0x0d,0x35,0x3a,0x19,0x01,0xef,0xf4, - 0x4c,0x96,0x73,0x16,0x46,0xd0,0x54,0xb8,0x99,0x89,0x21,0x34,0x0f,0xbc,0xd0,0xda, - 0x2b,0xdb,0x2c,0xf1,0x2f,0x17,0xbc,0x0b,0xf3,0xba,0xe9,0x80,0xff,0x4d,0xf6,0x0e, - 0x2c,0x8c,0x51,0xee,0xd8,0x3c,0x24,0x94,0x34,0x88,0xfa,0xdf,0xba,0xc8,0x06,0x70, - 0xea,0x7d,0x29,0xfe,0x9f,0xb5,0x4b,0xf1,0x74,0x94,0xbc,0x46,0xf3,0xc2,0x11,0x12, - 0x95,0x0a,0x5f,0xcb,0x80,0x30,0x37,0xc3,0xeb,0x78,0x84,0x62,0x29,0x6c,0x0d,0xab, - 0x67,0xf3,0x5c,0xe4,0xae,0x64,0xfc,0x4b,0x98,0x09,0x4f,0xc3,0x77,0xb4,0xbc,0x20, - 0x9e,0xa6,0x1f,0x47,0x66,0x0f,0x67,0x68,0xeb,0xde,0x4e,0xb8,0x6d,0x7f,0x40,0x72, - 0xe1,0xc7,0xfe,0xd0,0xbb,0x2e,0x37,0xa9,0x4b,0xde,0x1f,0x66,0xa9,0x7f,0x42,0xb4, - 0xe3,0x5e,0x9e,0xf3,0x04,0x39,0xcd,0x6e,0x8d,0x67,0x06,0x84,0x77,0x80,0x5f,0xf9, - 0xe2,0xc3,0xe2,0x5d,0xf0,0x6b,0xb6,0x47,0xb7,0xaf,0x91,0xbf,0x3d,0xf1,0xb5,0x80, - 0x5e,0xbf,0x0b,0xd5,0xfa,0x2c,0x1e,0xe4,0x1a,0x22,0xfd,0x28,0x66,0xb3,0xd8,0x04, - 0xbf,0x65,0x7f,0x63,0x3c,0xe1,0x11,0x8a,0x89,0xe1,0xeb,0x26,0xd6,0x47,0x4b,0xfb, - 0x40,0xbb,0x1a,0x5d,0xc4,0x41,0xd4,0x5d,0x5a,0xdb,0x8f,0x0e,0x7e,0x68,0x5f,0x9e, - 0xe3,0xd3,0x5e,0x65,0xf3,0x06,0x1c,0xdd,0xe2,0x15,0x78,0x85,0x55,0x85,0x96,0x06, - 0x44,0xc5,0x8a,0x7f,0xd8,0x81,0x1d,0xf9,0xbd,0x9d,0x0f,0x6e,0x98,0xc5,0x3a,0x3a, - 0xf4,0xa1,0xcc,0x20,0x99,0xa9,0x35,0x42,0xf9,0x80,0x7c,0x49,0xb8,0x4f,0x6b,0xe2, - 0x81,0x60,0x4a,0xac,0xfe,0x96,0x6d,0xc6,0xf3,0xca,0x3c,0xd3,0x3a,0xd3,0x3a,0xc4, - 0x2f,0x18,0x11,0x8d,0xdc,0x6f,0x5b,0x0f,0xc5,0x27,0x5b,0x1e,0x42,0x33,0x66,0x6d, - 0xd0,0x0d,0xf4,0x4c,0x76,0xad,0x32,0xb1,0xfe,0xa1,0xdc,0x63,0xb0,0xb7,0x7a,0xce, - 0x99,0x3b,0xdd,0x68,0xbd,0xea,0x01,0xbd,0x3f,0x03,0xfc,0xcb,0xd8,0x56,0xc1,0xc5, - 0x03,0x19,0x1a,0xde,0x0e,0xe7,0xcf,0xc8,0xfe,0xdb,0x49,0xfe,0x8f,0x6b,0xc6,0x6e, - 0xf8,0xd4,0xef,0x1b,0xc1,0xdd,0xee,0x56,0x77,0xb1,0xf2,0x38,0xca,0x9f,0xbb,0xd9, - 0x09,0x62,0xfa,0xdb,0x51,0xd5,0x36,0xf8,0xe2,0xbb,0x3b,0xe5,0xbb,0x2c,0xcf,0x73, - 0x4e,0xbd,0xa4,0x56,0x44,0xd1,0x9e,0xda,0xed,0x1c,0x0c,0x96,0xf5,0x3a,0xd8,0xb4, - 0xdd,0x3c,0x0c,0x61,0x6c,0x8a,0xc9,0x4f,0x91,0xf3,0xac,0xf2,0x5d,0xb4,0xd0,0x3b, - 0x92,0xf8,0x27,0x38,0x26,0x5d,0x85,0x85,0x3d,0xf6,0x60,0x63,0x25,0x6c,0x97,0x16, - 0xbe,0x90,0x19,0x17,0x87,0xe8,0xab,0x09,0x7d,0x97,0x07,0xbf,0x83,0x52,0x84,0x82, - 0x8d,0x49,0x7d,0xdd,0x83,0xff,0x12,0xc2,0x9e,0x6e,0x54,0xe2,0xd3,0xc0,0x68,0x2f, - 0x8b,0x67,0x36,0x91,0xf1,0xb0,0x45,0x0c,0x25,0xc0,0x06,0x68,0x67,0x9d,0x31,0xbf, - 0x9a,0xc4,0x3f,0x28,0x39,0x0e,0xc3,0x9c,0x38,0xed,0x26,0x25,0xea,0xc1,0x86,0x39, - 0xef,0xd2,0x86,0x75,0x13,0xf3,0x9d,0xee,0xf4,0x66,0xc1,0xa9,0x6d,0x60,0xf8,0x87, - 0x13,0xfb,0x81,0xd6,0x4a,0x70,0xd8,0xc5,0xe3,0x83,0x15,0xf6,0xb9,0x9d,0x50,0x78, - 0x26,0x03,0xc8,0x50,0xc6,0x4e,0x6d,0xf5,0xb1,0x46,0x2f,0x48,0x78,0x3b,0x55,0xbb, - 0x8b,0x84,0x93,0xf6,0x17,0xd0,0x3a,0x38,0x1c,0xe2,0x4e,0xb0,0x02,0x37,0x1b,0xf1, - 0x96,0x6d,0x73,0x33,0xc4,0x7b,0xa6,0xff,0xe1,0x7c,0x83,0x8b,0xbe,0x41,0xbc,0x90, - 0xf5,0x98,0xa8,0x26,0xf1,0xcf,0xf5,0x7b,0xe0,0x53,0xf7,0x4d,0x46,0xa6,0x21,0x8e, - 0x91,0xbe,0x90,0x4f,0x5a,0x66,0xd4,0x8c,0xc1,0xef,0x54,0xdf,0xaf,0xef,0x1e,0x46, - 0xfc,0x33,0x06,0x55,0xf0,0xe8,0x96,0xaf,0xa7,0xe0,0x1f,0xf2,0x62,0xf8,0x56,0xdd, - 0x7e,0x52,0x2c,0xaf,0x3d,0xe9,0x2c,0xa5,0x76,0x43,0xac,0x8f,0xbe,0x0a,0x0b,0x25, - 0x77,0xbf,0x58,0x0f,0xbf,0x25,0x0b,0xb9,0xff,0xc4,0xc2,0x7f,0x46,0xfc,0x13,0x69, - 0x72,0xee,0xb0,0x83,0xdf,0x05,0xcd,0x01,0xe7,0xbd,0xf6,0xa6,0xc6,0xc2,0xd0,0xa6, - 0x7e,0x67,0x1e,0xdd,0x4e,0x0a,0xa4,0x66,0xad,0x88,0x04,0xba,0x1a,0xeb,0x27,0xe3, - 0xef,0x7d,0x69,0x71,0xd8,0x05,0x85,0x46,0xc6,0x16,0xe2,0x62,0x7a,0xa8,0xee,0xfa, - 0x8c,0x1c,0xc2,0x58,0xa3,0x34,0x67,0x39,0x9a,0x99,0x19,0xb0,0xa3,0xb2,0x30,0xc3, - 0xe5,0x22,0x16,0xfe,0xf3,0x8c,0xdd,0x0d,0xbb,0x98,0x53,0x77,0x75,0xa3,0x19,0xbb, - 0x8b,0xb5,0xeb,0x78,0xdb,0x12,0x4e,0xb4,0x0e,0xd1,0x6d,0xd9,0x2e,0x75,0x57,0xa4, - 0x48,0xdf,0xd6,0x45,0xea,0x93,0xf8,0x04,0xe5,0xe7,0xd9,0x9e,0x32,0x3d,0xd3,0xde, - 0xe8,0x0a,0x0f,0xc6,0x2b,0xe6,0x66,0xb6,0xd6,0x38,0xd5,0x17,0xa0,0x2c,0x2e,0xc5, - 0xc4,0x02,0xff,0x1f,0x59,0x59,0x97,0x3d,0x96,0x93,0xc2,0x7f,0xce,0x7d,0x47,0xa8, - 0x62,0x0e,0x5c,0x16,0xed,0x1d,0x5c,0x0d,0x47,0x50,0xee,0x57,0x2f,0x49,0x55,0x3c, - 0xbe,0x3c,0x02,0xbf,0xe1,0x57,0xce,0x58,0xf8,0xcf,0xbd,0xca,0x6e,0xb4,0xdf,0x39, - 0xda,0x24,0x2e,0x78,0x5f,0xf3,0x49,0x8e,0x1d,0xe2,0x7b,0xc2,0x25,0xa5,0xcc,0xc8, - 0xda,0x23,0x7e,0x41,0xba,0x74,0xaf,0x97,0x65,0x4d,0xaf,0xb9,0x60,0x89,0x7f,0x49, - 0xd0,0x3c,0xac,0x6e,0x41,0xfb,0xfd,0x1e,0xd6,0x3c,0x5c,0xb2,0x40,0xde,0x4e,0xde, - 0x6b,0x78,0x9e,0xd3,0x5a,0xb6,0x39,0x25,0x7a,0x88,0x38,0xf5,0xcc,0xc7,0x53,0xfc, - 0x3f,0xda,0xf4,0xe9,0xcc,0x15,0xa6,0x4a,0xb6,0x1d,0x8f,0x5d,0x3a,0x5b,0xe2,0xcc, - 0x3e,0xc6,0xdd,0x80,0x70,0xd7,0x0d,0xd9,0x12,0x6e,0x63,0x27,0x95,0x15,0x9c,0x3f, - 0xb1,0xdf,0x86,0x85,0xeb,0xa4,0xc7,0x58,0xc1,0x6e,0xfa,0x37,0xe4,0x6b,0xb0,0x8e, - 0x15,0x87,0x96,0x2c,0x27,0x6f,0xc2,0x01,0x3d,0x5f,0xb5,0x2d,0x9f,0x73,0x1d,0xdd, - 0xcf,0x0a,0x5c,0x19,0x75,0x64,0x6c,0xf2,0x7c,0xdd,0x49,0x89,0xf6,0x2b,0x28,0x5f, - 0x6a,0x9f,0x8e,0xf8,0xf0,0x2c,0x87,0x6d,0x2a,0xda,0x9b,0x7b,0x59,0x99,0x96,0xa5, - 0xc8,0x76,0x38,0xaf,0x2a,0x61,0x87,0x4b,0x7c,0x6d,0x32,0x7e,0xaa,0xdd,0xd4,0xa6, - 0x7d,0x0c,0x8b,0x5a,0x6f,0xf9,0xa4,0xe6,0x39,0xe9,0xb2,0x80,0xdb,0xac,0x9f,0xfb, - 0x0f,0xf1,0xbc,0xa4,0xf1,0x40,0xd8,0x79,0xb2,0xb8,0x79,0x1e,0x8f,0x27,0x4e,0xac, - 0x4f,0x67,0xda,0x00,0x7c,0x02,0x1e,0x66,0xe7,0xd1,0xe7,0xb7,0x61,0xaf,0x66,0x47, - 0xe0,0x06,0x27,0x3c,0x0b,0xcc,0x40,0x21,0x3d,0x0e,0xa4,0x1a,0xf5,0x23,0x49,0xe2, - 0x9f,0xcd,0x6d,0x70,0x80,0xd3,0x12,0x34,0x14,0xe1,0xeb,0xa0,0xa0,0x7a,0x77,0xbf, - 0xdf,0x03,0xeb,0x5d,0xf9,0x08,0x84,0xc8,0x49,0x58,0x27,0x7c,0xab,0x9a,0x6a,0x36, - 0xef,0x24,0xbe,0x62,0xf0,0x18,0x7d,0xb6,0x21,0xff,0xdd,0xc0,0x9a,0xf4,0xaf,0xc1, - 0xe6,0x9e,0xfc,0xfa,0xeb,0xeb,0xc8,0x75,0xf0,0x18,0xbb,0x85,0xe3,0x9f,0xd7,0x60, - 0xa7,0xa1,0xc7,0x07,0x03,0xce,0x3c,0x0b,0xfe,0x79,0x59,0xd8,0xcb,0x54,0xd6,0x77, - 0x6b,0xf8,0x1f,0x58,0x33,0x02,0x75,0xd4,0xe6,0xb7,0x10,0x93,0x56,0x74,0x1b,0x9a, - 0x9d,0xcf,0xf4,0x15,0x0d,0xd2,0xd6,0xf0,0x0d,0x93,0xf2,0x61,0x70,0xc6,0x61,0xf8, - 0x3c,0x52,0xaa,0x2f,0x1d,0x32,0x03,0x6b,0x68,0x48,0xc6,0x1b,0xcb,0xb5,0xd7,0x60, - 0xe1,0x2f,0xed,0xba,0x78,0x29,0xfc,0x91,0x56,0xda,0x69,0xff,0x88,0x54,0x4c,0xee, - 0x9f,0x00,0xc4,0x23,0x23,0x70,0x04,0xe6,0x31,0x61,0x87,0x36,0x12,0xf0,0x65,0x67, - 0x35,0x35,0xc6,0xb5,0x89,0xf8,0x17,0x6c,0xe3,0xa6,0x19,0xc7,0x3f,0x13,0xcf,0x4f, - 0x95,0x73,0xd1,0x63,0xaa,0x57,0x5b,0x1d,0x15,0xe7,0x90,0x63,0xcc,0x5b,0x6f,0xbf, - 0x81,0x0f,0x78,0x58,0x24,0x4f,0x94,0xe0,0x18,0x74,0xad,0x5a,0xfa,0xb8,0x48,0x26, - 0xf7,0x0f,0x93,0xee,0x80,0x66,0x40,0x50,0x17,0x25,0xb7,0x34,0x35,0x1b,0xed,0xf5, - 0xee,0x36,0xe7,0x6c,0x68,0x7e,0xad,0x4c,0xa3,0xdb,0x6d,0x85,0x0a,0xca,0x93,0x20, - 0xdd,0x92,0xea,0xff,0x81,0x16,0xea,0x0c,0x05,0x94,0xf4,0x42,0xad,0xf9,0x7a,0xa7, - 0x7f,0x5b,0x34,0x5c,0x58,0xdf,0xcc,0x61,0xcc,0x8f,0xc6,0xf9,0x42,0x78,0xab,0xac, - 0xc9,0xfd,0x06,0x68,0x7f,0x35,0x73,0x33,0x2d,0xd7,0x96,0x08,0x7b,0xe5,0x71,0xff, - 0x4f,0x23,0x14,0x9a,0xfc,0x67,0xd2,0xd0,0xa3,0x06,0x5d,0xb9,0x04,0x7f,0x37,0xfe, - 0x53,0x9e,0x19,0x22,0x11,0xe8,0x12,0xec,0x90,0x3d,0x81,0x76,0x72,0x54,0x25,0x31, - 0xf8,0xae,0x39,0x60,0x76,0x66,0xf1,0xff,0x9c,0xb9,0xe9,0x02,0x2c,0xc6,0xdd,0xb2, - 0xac,0x3f,0xe7,0x33,0xee,0xed,0xe9,0xcf,0x3a,0x2d,0x5f,0x86,0x4f,0xb4,0xaa,0xa0, - 0x8c,0x88,0x48,0x32,0xf1,0xcf,0x7d,0xe2,0xb9,0xc9,0xf5,0xcc,0x9b,0x71,0x01,0x5e, - 0x81,0xf9,0xda,0xd2,0xb6,0x9c,0x05,0xfa,0x2b,0x5a,0xd5,0xf2,0x99,0xfd,0xe2,0xad, - 0xf0,0x8a,0x0b,0xd7,0x27,0xd8,0xb8,0x80,0x7d,0x16,0x2a,0xd5,0xdc,0xaf,0x59,0xe2, - 0x5f,0x6b,0x94,0xb8,0x14,0x81,0x76,0x81,0x02,0xd9,0xc5,0x22,0x5a,0x49,0x5e,0x20, - 0xfc,0x55,0xce,0xff,0x29,0xa2,0x9d,0xcc,0x96,0x0f,0xdd,0xab,0x9e,0xb9,0x81,0xae, - 0x0b,0x9f,0x9a,0x5c,0x4f,0x9a,0x36,0x04,0x3f,0x13,0x70,0x35,0xb2,0xb3,0x9b,0xd4, - 0x06,0x6d,0x75,0x90,0xe6,0x6e,0xe0,0xfe,0x2e,0xd7,0x43,0x36,0x4f,0x7a,0x1a,0xec, - 0x35,0x42,0x41,0x3a,0x9d,0xbc,0x26,0x4c,0xcc,0xcf,0x4b,0xdb,0xcd,0x61,0x64,0xb5, - 0x6b,0x73,0x78,0xb7,0xd4,0xc2,0xa3,0x8d,0xd1,0xb0,0xbb,0xba,0x19,0x8a,0x34,0xdb, - 0x16,0x52,0x18,0x39,0xd8,0x54,0x14,0xa0,0x9c,0xff,0x3c,0x31,0x5f,0x17,0x5e,0x82, - 0xf7,0xb9,0x13,0x6f,0x9b,0xfc,0x94,0xff,0x18,0xf3,0x69,0xae,0xed,0x68,0x38,0x9b, - 0x1e,0xbf,0x6d,0x62,0x21,0x1b,0xc5,0x0f,0x61,0xff,0xb1,0x85,0xff,0xcc,0xe3,0x5f, - 0x6f,0xd4,0x1e,0x79,0x28,0x11,0xf6,0xca,0xab,0xac,0x73,0x64,0x8b,0x2f,0x21,0xd0, - 0xae,0x0c,0x64,0xe6,0x15,0xe0,0x51,0xb2,0xfb,0xaa,0x1d,0x5b,0xb6,0x9e,0x4f,0xfa, - 0x7f,0x40,0xe7,0xb4,0x2b,0xc9,0xde,0x24,0xe6,0x43,0xdf,0xbd,0x9c,0xed,0x93,0x93, - 0xcf,0x06,0x55,0x84,0x3d,0x9c,0x08,0xd4,0x27,0xf9,0xa8,0xbd,0x49,0x26,0x16,0xff, - 0x4f,0x39,0xec,0x87,0x7c,0x9d,0xea,0xc2,0xf7,0xfd,0x1b,0xd9,0xce,0x36,0x3a,0x40, - 0xca,0x61,0x9d,0x46,0x58,0x20,0x6e,0x73,0xc1,0x46,0xad,0x20,0xe2,0x1a,0xb0,0xe2, - 0x9f,0x19,0x01,0x61,0x6f,0xc8,0x34,0xc3,0x67,0x6b,0x9b,0xb5,0xc2,0x55,0x08,0x84, - 0xd2,0x61,0xab,0xa6,0x1a,0x19,0x2a,0xb9,0x83,0x36,0x6a,0xae,0x7e,0x5a,0xee,0xb4, - 0x59,0xfc,0x3f,0x79,0xf0,0xbc,0x90,0x6f,0xb8,0x1e,0x24,0xf7,0x41,0x1b,0x43,0xeb, - 0xec,0x7b,0x64,0x06,0x3c,0x06,0x6a,0x5f,0x46,0x3d,0x59,0x26,0xad,0xe7,0x1e,0x95, - 0x87,0xd1,0xfe,0x9d,0xb8,0x7f,0x67,0x84,0xb3,0x7d,0xe6,0xc7,0x97,0xfe,0x93,0xec, - 0x85,0xdf,0x22,0xfe,0x71,0x9f,0x91,0x2b,0xc8,0xa7,0x4d,0xf3,0x07,0x33,0xd7,0x88, - 0x5f,0xc3,0x13,0xb9,0x48,0xb7,0x8f,0xc8,0x4e,0xab,0xff,0x07,0xa5,0x9f,0xcf,0x58, - 0xb6,0x2f,0x27,0x0e,0x43,0xb0,0x88,0x13,0x59,0x47,0x78,0x9a,0xc0,0x0b,0xdf,0x46, - 0x09,0x43,0x2e,0x41,0x85,0xc9,0x7f,0x4e,0xda,0xbf,0x69,0xaf,0x69,0x7d,0xd1,0x2a, - 0x1d,0xcd,0xf6,0x32,0xe3,0x55,0x56,0xba,0xc2,0x0c,0x7b,0xbd,0x1c,0x9d,0xff,0xae, - 0x7d,0xcd,0xd7,0x7d,0xf0,0x6a,0xdb,0xfc,0xb3,0xf6,0x41,0x31,0xe9,0x9f,0x79,0x66, - 0x7a,0x44,0x5b,0x1f,0x2d,0x66,0xae,0x87,0x48,0xae,0xf6,0xba,0x92,0x9f,0xeb,0x0a, - 0x92,0xd3,0x6a,0x63,0x14,0x1f,0xfb,0x21,0x32,0x53,0x5a,0xaf,0xcf,0xcd,0xa1,0xab, - 0x6c,0x45,0xe9,0x13,0xf3,0x01,0xb6,0x2b,0xeb,0x55,0x8e,0x7f,0x9c,0x79,0xec,0x49, - 0x98,0x6b,0xd0,0x2f,0x91,0x7e,0x6d,0x3d,0x14,0xf0,0xf8,0xd7,0xfd,0xda,0xd3,0x3c, - 0xb1,0x25,0x68,0xf5,0xff,0x28,0x27,0xb5,0x46,0xbb,0x7b,0x55,0xe4,0x39,0x92,0x8f, - 0xd2,0xd0,0xa5,0x23,0x48,0x7f,0xc5,0xd6,0x00,0xce,0x81,0x8c,0x3c,0xb2,0x74,0xf6, - 0x4e,0x6d,0x50,0x75,0xd9,0x09,0x9d,0x9c,0xdf,0x39,0xa3,0x13,0x5e,0x60,0xbe,0x17, - 0x33,0x47,0xe4,0xd9,0xf0,0x7e,0xfc,0xd0,0x1a,0xca,0x1a,0xff,0xa0,0xbc,0x00,0x7b, - 0xcf,0x66,0x6e,0x6b,0x7c,0x80,0xfd,0xb1,0x57,0x8f,0xdb,0xbb,0xc3,0x56,0x3c,0xf6, - 0xbe,0xf3,0xd2,0x51,0x5f,0xbf,0x63,0x0f,0xc2,0xec,0xe5,0xa1,0xeb,0x72,0x1c,0xfa, - 0xde,0x81,0x28,0xf7,0x87,0x94,0xb4,0x89,0xad,0xca,0xdf,0x31,0x5f,0xc3,0xbc,0x8e, - 0x94,0xf8,0xd7,0x45,0x8d,0x07,0xb9,0xdc,0xc3,0x8d,0x2a,0x5a,0x5b,0x5e,0xc3,0x61, - 0x88,0xae,0xb4,0x2b,0x7a,0xa9,0x61,0xef,0xe7,0xf9,0x29,0x74,0x6f,0xbf,0x7d,0x4f, - 0x63,0x5f,0xd2,0xff,0x23,0x7d,0x1b,0x0e,0x37,0x78,0xe2,0x91,0x98,0xed,0x0b,0x10, - 0xe9,0x71,0x86,0x50,0x7f,0x39,0xe1,0x50,0xdc,0xd9,0x83,0xfb,0xff,0xa3,0xda,0xc6, - 0xbe,0xb2,0xcd,0x0e,0x46,0x06,0x2d,0xfe,0x1f,0x17,0x3d,0x4c,0x9d,0xf5,0x34,0xe6, - 0x77,0xf2,0xc0,0xd0,0x0a,0xb9,0xd5,0x36,0x47,0xe1,0x8e,0xa3,0xbc,0x6e,0x32,0x44, - 0x5a,0x1a,0x4c,0x8f,0x50,0x0a,0xff,0xb9,0xf6,0xb0,0xaa,0x02,0xf5,0x38,0x41,0xe1, - 0xde,0x0f,0x19,0x70,0xf5,0xf6,0x52,0xbd,0xc7,0xe6,0xf1,0x9f,0x84,0x86,0xfc,0x39, - 0x3c,0xb0,0x7d,0x74,0xed,0xe4,0xf2,0x67,0x7e,0x0b,0x2e,0x49,0x5e,0x6d,0x66,0x7d, - 0x8e,0x8b,0x70,0xb1,0x73,0x33,0x47,0x53,0x87,0xb9,0x23,0x0b,0xf5,0x0b,0x39,0xce, - 0x05,0xe9,0xb3,0xa2,0xd1,0x38,0xb9,0x3f,0x1f,0x1d,0x61,0x57,0x95,0xdb,0xb4,0x7f, - 0xe3,0xdb,0x66,0x0c,0xb8,0xb7,0x27,0x67,0x18,0x2e,0xd1,0x2a,0x43,0x46,0x45,0x26, - 0x8d,0x64,0x57,0x99,0xfe,0x9f,0xc2,0x24,0xde,0x18,0x82,0x57,0x61,0x11,0x5b,0x6a, - 0x14,0x94,0xc0,0x18,0x5b,0xbc,0x6a,0xda,0x88,0xe8,0x51,0x4e,0xa8,0xa5,0x27,0x37, - 0xc6,0xc4,0x59,0xd0,0xcb,0x4a,0x43,0x3c,0xfe,0x65,0xf1,0xff,0x0c,0xc1,0x26,0xa9, - 0x8b,0x45,0x80,0x94,0x48,0xdd,0x0d,0x25,0xd5,0x72,0x37,0x71,0x29,0xbf,0x33,0x76, - 0x9c,0x79,0xf4,0xb2,0x19,0xa8,0x42,0xa0,0xd2,0x9d,0x12,0xff,0x3a,0x39,0xbd,0x11, - 0x8a,0x18,0x55,0x6d,0x76,0x29,0x06,0xee,0x80,0xec,0xb1,0xb5,0xe6,0x35,0x2a,0xea, - 0x19,0x9b,0xc7,0x69,0x4f,0xc8,0x67,0x0f,0xb1,0xc4,0xbf,0xd2,0x76,0x43,0xa3,0x32, - 0x27,0x8a,0xeb,0xef,0x86,0x83,0x4d,0x25,0x5a,0x4b,0x8c,0xb4,0xaa,0x3f,0x35,0xf9, - 0xe4,0x78,0xa5,0x85,0xa9,0x2b,0x68,0x4a,0xfc,0x2b,0x6d,0x88,0x1e,0x63,0x15,0x51, - 0x57,0xb3,0xec,0x86,0x91,0x88,0x2f,0x24,0x7b,0x48,0xa7,0x49,0xbb,0xcd,0x8a,0x89, - 0x59,0x5a,0x4f,0x5f,0xf6,0x79,0x7b,0xcc,0xc2,0x7f,0x8e,0x0b,0xbb,0x61,0x74,0xc3, - 0xa2,0xfe,0x4d,0x88,0x0f,0x39,0x1a,0x0c,0x38,0x86,0xbf,0xb8,0x26,0x35,0xbe,0x33, - 0x2f,0x25,0xfe,0x05,0xbb,0xb9,0x92,0x6a,0xb3,0xb7,0xf3,0xfb,0xa3,0xa1,0x97,0xd9, - 0x8d,0xe8,0xe8,0x04,0x02,0x09,0xfb,0x7c,0xdc,0x3f,0xa8,0xd1,0x02,0x8e,0x2e,0x71, - 0xd8,0x92,0xff,0x55,0x39,0xbd,0x79,0x85,0x7a,0x7a,0x03,0x8f,0xd6,0x1d,0x7c,0xc3, - 0xa9,0x65,0xc5,0x50,0x86,0x3d,0xad,0xce,0xeb,0xa1,0x23,0xe4,0xa3,0x26,0xdc,0x0f, - 0x23,0xf2,0x7e,0x2b,0xfe,0x99,0xf1,0x80,0x7d,0xb3,0xa1,0x2b,0x94,0xdd,0x61,0x87, - 0x58,0xa3,0x4b,0x63,0x5e,0x88,0xd8,0x1b,0x99,0xdb,0x68,0xf6,0x38,0x4f,0x91,0x46, - 0xda,0xd9,0x2f,0x2f,0x20,0x29,0xf1,0x2f,0xf5,0x47,0xd1,0x5b,0x3a,0x6d,0x81,0xd7, - 0x67,0x49,0x47,0xf4,0x82,0xd5,0xb6,0x35,0x70,0x03,0x3c,0xad,0x17,0x0f,0xf2,0xc4, - 0x28,0x65,0x13,0x9b,0x1b,0x47,0x43,0xcc,0x1a,0xff,0xca,0xd2,0x36,0xb7,0x21,0x3e, - 0x71,0x8a,0x59,0x30,0xa2,0x97,0x0f,0xd8,0x3d,0xc2,0xa0,0xf6,0x02,0xab,0x1c,0xcc, - 0xbc,0x4d,0x3c,0x09,0x2f,0x40,0xb9,0xe6,0xa8,0xc8,0xb1,0xc6,0xbf,0x9e,0x53,0x3e, - 0x64,0xb7,0xf5,0x39,0x86,0x73,0xc6,0xe8,0x45,0xbe,0x2c,0x0f,0x8a,0x23,0x0a,0x5f, - 0x96,0x92,0xf3,0x35,0x68,0x4a,0x28,0x0b,0xa7,0xfa,0x7f,0xd0,0x3a,0x0b,0x39,0x39, - 0x2d,0x61,0x35,0x2c,0x17,0x66,0x69,0x88,0x36,0x07,0xe1,0x92,0xe1,0xed,0xcf,0xda, - 0xb7,0xd5,0x0d,0x7f,0x14,0xbc,0xf1,0x54,0xff,0x8f,0xf0,0x2f,0xb0,0x57,0x31,0xf9, - 0x3f,0x33,0xe1,0xc7,0x50,0x5c,0x9d,0x59,0x4f,0xce,0x28,0x07,0x82,0xae,0x5e,0xee, - 0x88,0x26,0xeb,0x13,0x1e,0xe9,0xf3,0x16,0xff,0x1b,0xda,0x6b,0x4c,0xd7,0x33,0x02, - 0xe9,0x5f,0x13,0xda,0xd8,0xbc,0x50,0xde,0x1a,0xc4,0x7b,0x7b,0xb9,0x07,0xec,0x36, - 0xff,0x2c,0xe1,0x69,0x76,0x8b,0xe9,0xff,0x99,0x5c,0xff,0x80,0x34,0xc4,0xf1,0xcf, - 0x49,0x1a,0x4b,0x5f,0x0a,0x51,0x28,0x09,0x65,0x70,0xf6,0xe6,0x5e,0x70,0x19,0x38, - 0x98,0x03,0x8d,0xce,0xc2,0xee,0x3b,0x3d,0xd6,0xf8,0x57,0x5a,0x27,0x5c,0xd4,0xe7, - 0xb3,0xe2,0x77,0xc5,0x3a,0x78,0x47,0xf5,0xe9,0x54,0x15,0x2f,0x32,0xce,0xff,0xc9, - 0xd2,0x0b,0x8a,0xe0,0x1c,0xec,0xdd,0xe2,0x4e,0x8d,0x7f,0xc5,0x61,0x18,0xf1,0x8f, - 0x83,0xe7,0x43,0xe5,0x41,0x96,0x64,0xa6,0x7d,0x25,0x3c,0x42,0x32,0x07,0x42,0x15, - 0x90,0x95,0xea,0xff,0x39,0xb7,0xf9,0x58,0x13,0x1e,0xd2,0xc7,0x6b,0x0a,0xe9,0x68, - 0xa1,0xaf,0x7a,0xe9,0xb6,0xea,0x5a,0x93,0x1f,0x72,0xb7,0x22,0xae,0x82,0x37,0x70, - 0xff,0x3b,0x7e,0x22,0x58,0xf9,0x3f,0xdf,0xe4,0xf1,0xa9,0xa0,0x2d,0xea,0x2f,0x84, - 0x83,0xd5,0x25,0x5a,0xe6,0xf6,0xf0,0x78,0xfc,0x0b,0x11,0x11,0x34,0xe7,0x3b,0xb5, - 0x25,0xdb,0xac,0xfc,0x9f,0x19,0x85,0x52,0xb3,0x82,0x87,0x2e,0x9a,0x5e,0x28,0x71, - 0xb7,0x0f,0xa2,0xa3,0x01,0x68,0x26,0x6e,0x2d,0x63,0x1b,0x59,0xc5,0x1e,0x57,0xbf, - 0x7d,0x87,0x1c,0x4d,0x4f,0xe1,0x3f,0x6b,0x8d,0xb5,0xce,0x7e,0x5b,0xee,0x1d,0x52, - 0xde,0x1e,0x70,0xf3,0xec,0xa7,0xb5,0x3c,0x42,0xc4,0xf1,0xcf,0x34,0x68,0xae,0x1d, - 0xd4,0x7e,0x9a,0x67,0xe5,0xff,0xa4,0xad,0x68,0x8f,0xb8,0xba,0x12,0x6c,0x93,0x8b, - 0xf8,0x9a,0xf7,0xb3,0x9c,0xb8,0x19,0xff,0xca,0x64,0x35,0x21,0xe9,0x0c,0x31,0xa9, - 0xd1,0xa7,0x84,0x49,0xff,0xcf,0x8c,0x81,0xe8,0x65,0xe9,0x66,0x04,0x39,0xf2,0x00, - 0x5c,0x86,0xc5,0xda,0x9c,0xa8,0xf8,0xdf,0xc9,0xa8,0x9f,0xd3,0x9e,0xe5,0xd3,0xf0, - 0x19,0xdc,0x6a,0x7a,0x3c,0x92,0xf8,0x27,0xed,0x02,0xfc,0xb3,0x56,0x1a,0x4c,0x3f, - 0x5d,0x54,0xc8,0x89,0xd3,0x08,0x7b,0xc4,0xc2,0xd0,0x2b,0x70,0x83,0x96,0xd5,0x2f, - 0xe6,0xc2,0x8b,0x28,0xdf,0x96,0x45,0x45,0x4b,0xfe,0x97,0x72,0x56,0x8b,0x05,0x9d, - 0xd1,0x48,0x07,0x8a,0xc1,0x43,0x84,0xd3,0xb0,0xc5,0x15,0x24,0x12,0x2c,0x23,0x8e, - 0x06,0xa2,0xb6,0x6f,0x28,0x74,0x82,0x6c,0xe5,0xff,0xd0,0xb4,0x5e,0x7d,0xaf,0xaa, - 0x2f,0x97,0xaf,0xf3,0x4b,0x12,0xbe,0xef,0x5d,0xf8,0xbe,0xab,0xc2,0x0d,0x52,0xbc, - 0xf6,0x2e,0xc4,0x7b,0xac,0x01,0x81,0xb7,0x99,0xef,0x66,0x89,0x7f,0xd1,0x83,0xf0, - 0xae,0x96,0x11,0xcd,0xc2,0xf5,0x57,0xdd,0x5a,0x5e,0x94,0xac,0x82,0x66,0xe9,0x9b, - 0x78,0x65,0x56,0x21,0x6b,0x86,0x9d,0x66,0x3e,0x9d,0x25,0xfe,0xc5,0xbd,0x55,0xde, - 0x6a,0x7c,0xbb,0xc2,0xbc,0x51,0x98,0xa5,0x15,0x23,0xd0,0x65,0x88,0x6f,0xab,0x67, - 0x45,0x73,0x38,0xff,0x27,0x7b,0xe5,0x32,0x9e,0xff,0x35,0xb1,0x3e,0x9d,0x9c,0xff, - 0x43,0x2b,0xeb,0xb3,0x6e,0xe0,0xf8,0x47,0xf2,0x05,0x38,0x10,0x62,0x9c,0xff,0xf3, - 0x35,0x13,0x11,0xd9,0xf9,0x95,0x46,0x6b,0xfc,0x6b,0x9c,0xe4,0xdc,0x84,0xeb,0x3f, - 0xa8,0x75,0x09,0x8e,0x86,0xaf,0xe7,0xd3,0x38,0xad,0xe0,0xb4,0x2b,0x13,0x7f,0x52, - 0x47,0x6a,0xfe,0x97,0x4b,0x3d,0x42,0x76,0x86,0x5d,0x71,0x14,0xcb,0x47,0x98,0xb3, - 0x61,0xc9,0x6a,0x12,0xc9,0xbc,0x42,0x4a,0x18,0x75,0x85,0xbb,0xd9,0xc6,0x90,0x33, - 0x9c,0xd5,0xee,0x4d,0x89,0x7f,0xc1,0x21,0xad,0x70,0x1b,0xbd,0x35,0x6c,0x87,0x1d, - 0x50,0x67,0xdc,0x78,0x5d,0xba,0x9d,0xb6,0x43,0x91,0x81,0x16,0xd9,0x37,0xc9,0xcf, - 0x7a,0x5d,0xf3,0x51,0x43,0x59,0xe3,0x5f,0x33,0x61,0x1f,0x14,0x32,0x54,0xfa,0xf7, - 0xc3,0xfe,0xc8,0x5c,0xe3,0xa7,0x9a,0xff,0x39,0x6d,0x9f,0x50,0x6c,0xb8,0xea,0xc9, - 0xe9,0xec,0x7f,0x83,0x5d,0x86,0xad,0x1e,0xac,0xf1,0xaf,0xeb,0x78,0xb6,0x57,0x3e, - 0x7d,0x43,0x9c,0x35,0xf3,0x5c,0xd3,0x6d,0x03,0xff,0x6d,0x79,0xce,0x2c,0xfd,0x29, - 0xb6,0xe8,0xbc,0xbd,0x5c,0xfc,0x1a,0xfc,0x81,0xdd,0x16,0x77,0xa4,0xc4,0xbf,0x32, - 0x3b,0xe0,0xa2,0x7a,0x88,0x6d,0x6a,0x93,0x77,0x4b,0x17,0xa1,0xec,0xe4,0xcd,0x51, - 0x72,0x92,0xe1,0xf9,0x3a,0x63,0x12,0x3b,0xdf,0x82,0x32,0x8d,0xc7,0xbf,0xc8,0xc4, - 0xfa,0x70,0xfe,0xcf,0x58,0x7f,0x69,0x68,0x69,0x9d,0xf8,0x08,0x7c,0xc6,0x2a,0x06, - 0xb2,0xce,0xa0,0xda,0xfa,0xbb,0xa8,0x6f,0x20,0x0b,0x11,0x11,0x5c,0x6e,0x28,0x1d, - 0x70,0x1c,0x14,0x0d,0x8b,0xff,0xa7,0x0d,0xf6,0x34,0x14,0x28,0x81,0x95,0xe2,0xfd, - 0xda,0x70,0x54,0x1d,0x94,0x83,0x05,0xf7,0xc3,0xbf,0xc7,0x2b,0xe3,0x99,0xf5,0xe2, - 0xfd,0xf0,0x4b,0x98,0xcb,0xe4,0x22,0x0b,0xff,0x19,0xa0,0x0d,0xf6,0xa9,0xf9,0xd2, - 0x5c,0x03,0xdf,0x77,0x1f,0x9d,0x6b,0xfc,0xe4,0x4b,0x68,0xb8,0xad,0x87,0xef,0x70, - 0xff,0xfc,0xcc,0xd0,0x01,0xc8,0x3f,0xfa,0x77,0x41,0xa7,0x61,0xe1,0xff,0x9c,0x84, - 0x18,0x38,0x21,0x20,0xa0,0xfc,0xd1,0x1b,0x38,0xad,0xd7,0xb6,0x14,0x36,0xc3,0x6a, - 0x43,0xf0,0x90,0x3b,0x60,0xaf,0xdf,0x75,0x9e,0x3b,0xf6,0x53,0xf8,0x3f,0x28,0x6d, - 0x9a,0x32,0xbb,0xe5,0xd5,0x52,0x77,0x74,0x91,0x91,0xa5,0x88,0x95,0xd2,0x31,0xf8, - 0xa1,0xc9,0xef,0xe5,0x82,0x74,0x18,0x07,0x1f,0x58,0xf0,0xcf,0x10,0x5c,0xd4,0x8e, - 0xb4,0x6d,0xd2,0xe5,0x21,0x18,0xa9,0x46,0xfb,0xb4,0x4d,0xdc,0xad,0x8d,0xc2,0x0d, - 0x9c,0x2f,0xfd,0x73,0x18,0xed,0x7b,0x84,0x5f,0xb1,0xe2,0x9f,0x0b,0xf4,0x0a,0x7c, - 0x97,0x2d,0x5d,0xde,0xf8,0x30,0x8c,0xe9,0x0b,0x8d,0xcc,0x33,0x39,0x0f,0xe3,0xc1, - 0xf4,0x18,0xad,0x9f,0x88,0xf5,0xf0,0x3b,0xd8,0xa9,0x6f,0x8a,0x5b,0xe3,0x5f,0xb5, - 0xab,0xe0,0x50,0x9f,0x53,0xa7,0x0d,0x3c,0x5e,0x43,0x55,0xc3,0xd6,0x86,0x82,0x7d, - 0xb3,0x51,0xc4,0x61,0x0c,0x91,0x1a,0x7a,0x9c,0xe7,0x97,0x1c,0x4e,0x8d,0x7f,0x41, - 0x8c,0x07,0x7d,0xf4,0x0d,0x6e,0xe8,0x86,0x39,0x46,0xde,0x8f,0xc9,0x6a,0x3c,0x38, - 0x26,0xec,0xf9,0x07,0x68,0x6e,0x2e,0x0a,0xc8,0xa9,0xf8,0x27,0x0d,0x62,0xf9,0x2a, - 0xa7,0xcd,0xd8,0xa1,0x5b,0x72,0xf6,0xd9,0x38,0xed,0x67,0x73,0xa8,0xae,0x9f,0x7a, - 0xb2,0x39,0x1e,0x70,0x19,0x3f,0x2d,0xb5,0xe6,0x7f,0x65,0x7e,0x03,0x2e,0xdc,0xeb, - 0x84,0x56,0x43,0x2c,0xae,0x1d,0xa9,0x5f,0x78,0x06,0xb5,0xc9,0xc3,0x30,0xaa,0x95, - 0x22,0x6c,0x13,0x43,0xf4,0x2d,0x9e,0xaf,0x14,0x6b,0xb4,0xc4,0xbf,0x6e,0x1a,0x63, - 0x23,0x65,0x26,0xc8,0x19,0x8b,0x8e,0x84,0xaa,0x4e,0x39,0x82,0xfc,0x7d,0x3d,0x55, - 0x27,0x51,0xad,0x0f,0xdb,0xc6,0x60,0x21,0x38,0x8e,0xe6,0x58,0xfd,0x3f,0x9f,0x23, - 0xc8,0xa9,0xea,0xc8,0x8c,0xdb,0xbe,0x07,0x57,0x6b,0x4b,0xf3,0xc5,0x9e,0xcd,0x0f, - 0x29,0x7d,0xec,0x0b,0x24,0x73,0x58,0xf4,0xb0,0x33,0x50,0x1a,0x72,0xbc,0x9f,0x82, - 0x7f,0xce,0x41,0x04,0x61,0x0f,0xd5,0xc9,0x93,0x06,0xc2,0x3c,0x95,0xae,0x23,0x73, - 0x68,0xc4,0xe5,0xf4,0x44,0x3a,0x49,0xc1,0xbd,0xcd,0xd1,0x22,0x4d,0xd6,0x9d,0x56, - 0xfc,0xd3,0x8b,0xdf,0xac,0x24,0xd2,0xec,0x7c,0xc9,0xf0,0xec,0x74,0x3a,0xc1,0x46, - 0x08,0xcf,0x1f,0x71,0x41,0x27,0x07,0x7e,0xdc,0xdf,0x85,0xe8,0xdf,0xca,0xff,0xe9, - 0x20,0x91,0x48,0xc9,0x51,0xbc,0xbf,0x8e,0x30,0xb2,0x5d,0xa3,0xdb,0x88,0x9b,0x20, - 0xac,0x92,0xe8,0x76,0xa2,0xb2,0x96,0x9e,0x6f,0x57,0xcb,0x7a,0xba,0x05,0xff,0xcc, - 0x78,0x09,0xfa,0xc2,0xbe,0x68,0x66,0x2c,0x67,0x95,0x72,0x09,0x3c,0xab,0x1c,0xad, - 0xe2,0x9d,0xf4,0x58,0x9b,0xcd,0x93,0x59,0x2e,0xbb,0xd8,0x31,0xc3,0x6b,0xbc,0xaa, - 0x17,0x58,0xf1,0xcf,0x01,0x4e,0x02,0xef,0xdd,0x74,0xa8,0xe6,0x7f,0xb8,0x50,0xad, - 0xb3,0x65,0xc1,0x1b,0xc7,0xa4,0x31,0xf0,0xa9,0x8e,0xb8,0x78,0x1c,0x86,0xa5,0xaa, - 0x55,0x38,0xb0,0xc6,0xbf,0x3a,0x58,0x5f,0xa0,0x22,0x9a,0xb5,0x0f,0xf5,0xe3,0x25, - 0xc5,0xa7,0x2d,0xd3,0x6b,0x7e,0x8f,0x12,0xaf,0x5e,0x29,0x66,0xa2,0x0b,0x8e,0x85, - 0xb2,0x8d,0x4d,0xba,0x68,0xcd,0x7f,0x2f,0x84,0x48,0x44,0x35,0x68,0x14,0x4f,0xd2, - 0xf3,0xdc,0x0d,0xd8,0x46,0x3e,0x0c,0xee,0x0d,0xae,0x7c,0x1b,0x11,0xf2,0x6e,0xd8, - 0xc0,0x9c,0x75,0x4b,0x7e,0x2e,0x7a,0xad,0xf9,0x5f,0xc0,0x7a,0x71,0x9b,0xe9,0x24, - 0x13,0x0e,0x6f,0x70,0x77,0xc9,0xb7,0x86,0x0d,0xe8,0x52,0x5c,0x3c,0x5e,0x23,0x81, - 0xae,0x15,0x6a,0xb2,0xcb,0xbf,0xc6,0x8a,0x7f,0x48,0x93,0x9e,0xdf,0x19,0xf9,0x96, - 0x6d,0x96,0x74,0x60,0x73,0x71,0x41,0xcb,0x72,0xf2,0x1a,0xec,0xdf,0x31,0x37,0x8e, - 0xf8,0xea,0xc7,0xca,0x93,0xbb,0x66,0xbf,0x27,0x0f,0xa2,0x62,0x9e,0xb8,0x7f,0x80, - 0x4a,0xaa,0xa1,0x57,0x18,0x25,0xb9,0xa2,0xbd,0xef,0x53,0xa9,0x92,0x39,0x0a,0xc5, - 0x17,0x11,0x08,0x75,0xf6,0xda,0x55,0x51,0x22,0x67,0xf5,0x7d,0xda,0x32,0xb5,0xe5, - 0x5e,0x0b,0xfe,0x69,0x85,0xb1,0xe9,0xcf,0x47,0x1c,0x46,0xcd,0x73,0x1c,0x16,0x6a, - 0x8e,0x5f,0x15,0x5c,0x56,0x2f,0x09,0x0b,0x0d,0x12,0x32,0xf9,0xcf,0x8b,0x0c,0x47, - 0x28,0x95,0xff,0xcc,0x49,0xb0,0x3d,0x3c,0x1b,0x91,0xd3,0xf6,0xfa,0x32,0x8d,0xfa, - 0x5d,0xd1,0x4b,0x19,0x5e,0x63,0x99,0x9a,0xe3,0x86,0x6f,0x41,0xb6,0x61,0x4f,0xe5, - 0x3f,0x6f,0xe7,0xd9,0x46,0x3c,0x49,0x36,0x17,0x0e,0xc0,0xdc,0xed,0xa8,0x4d,0xf2, - 0xe8,0x11,0xc8,0x67,0x72,0xa8,0x60,0x39,0xac,0xe3,0xf8,0x27,0x44,0xac,0xfc,0x9f, - 0x1f,0xc3,0x5a,0xf6,0x9d,0xf8,0xae,0xe5,0xf7,0xdc,0x0c,0x7b,0xa3,0xf9,0x9c,0xed, - 0x7c,0x9d,0xfd,0x59,0x36,0xbb,0xbe,0x65,0xec,0xde,0x3b,0xa6,0x37,0xb0,0x82,0x78, - 0x46,0x5d,0x4a,0xfc,0xeb,0x24,0x69,0x84,0x92,0x0e,0x6a,0x4f,0xcf,0xa2,0x87,0xc1, - 0xd5,0x2f,0x2b,0x78,0xd0,0x0e,0x6b,0x9c,0x08,0x4d,0xee,0x79,0xa9,0x31,0xbd,0xbd, - 0x77,0xae,0x9e,0xc2,0xff,0x89,0xc0,0x29,0xad,0x8a,0x15,0x0f,0x8a,0x15,0x5c,0x10, - 0x75,0x3e,0xfa,0x81,0xec,0x82,0x8b,0xca,0x01,0xe6,0xf8,0x96,0xf8,0x7d,0xf8,0x48, - 0xf3,0xb2,0xcc,0x29,0xfc,0x67,0x18,0x09,0xf8,0xc0,0xd1,0x50,0x9a,0xa0,0x3d,0x3b, - 0xd6,0xe5,0xc4,0x4d,0x22,0x90,0xa3,0x89,0x27,0x82,0xe1,0xaf,0x52,0xf1,0x8f,0x32, - 0xa0,0xbd,0xaf,0xfa,0xb4,0xac,0x68,0xe3,0x53,0x81,0x63,0xba,0xd7,0xef,0x50,0xf8, - 0x42,0xa9,0x1e,0x4d,0x8a,0x8a,0x3c,0x75,0xda,0x5b,0x67,0x7f,0xdc,0xca,0xff,0x91, - 0xfe,0x7e,0x02,0xed,0x14,0xa2,0x2e,0x71,0xf2,0xfd,0xe3,0xa6,0x07,0xb5,0x2e,0xad, - 0xae,0x8d,0xc7,0xbf,0xb4,0x76,0x2d,0x33,0x6a,0xb3,0xfa,0x7f,0x66,0xd3,0x5d,0x38, - 0x1f,0xc5,0x48,0xab,0x62,0xa6,0x29,0x6d,0xc6,0x3f,0x3c,0xa8,0x15,0x19,0xb6,0x68, - 0xfa,0x2a,0x75,0xdc,0xff,0x93,0x9e,0xe2,0x7f,0x6e,0x14,0x78,0xd2,0x93,0x3f,0x13, - 0x78,0xfe,0x7b,0x22,0x11,0xac,0xda,0xa5,0xd9,0x38,0x63,0xaa,0x01,0x20,0xf8,0x78, - 0xae,0x35,0xfe,0x95,0x19,0x42,0x6d,0x56,0x09,0x59,0x40,0x74,0xce,0x0f,0x07,0x87, - 0x2e,0xab,0x28,0xe8,0x7e,0x00,0x59,0x3a,0xe2,0x1f,0x7e,0x05,0xbf,0x6f,0x2a,0xff, - 0xe7,0x32,0x54,0x55,0x4f,0x1b,0xcf,0x76,0xe7,0xf9,0x5f,0x1c,0x21,0x94,0x7e,0x29, - 0x93,0x5f,0xb9,0xac,0x2d,0xe6,0xf8,0xe7,0x9b,0xd6,0xfc,0x77,0xf8,0x13,0x54,0xd6, - 0xde,0xbd,0xe5,0xaf,0xbe,0xa7,0xde,0x9d,0xe3,0xad,0x16,0x5f,0x63,0x6e,0xbc,0x03, - 0xd1,0xd2,0xa3,0x62,0x47,0xe4,0x8f,0xae,0xd2,0x5a,0xc7,0xaf,0x52,0xf0,0x0f,0xae, - 0xb6,0x50,0x02,0x34,0x1c,0xce,0x97,0xce,0x78,0x8a,0x40,0x6e,0xe7,0x40,0x08,0x35, - 0x0e,0x4a,0x6c,0x15,0x5a,0xa1,0x88,0xca,0x0c,0x52,0xf0,0x8f,0x19,0xed,0xca,0xc8, - 0x49,0x6f,0x42,0x75,0x84,0xdb,0x20,0x7b,0x43,0x3a,0x1c,0xa4,0x2b,0x56,0x05,0x86, - 0xc9,0x8f,0xb5,0xb5,0xa0,0x06,0xe4,0xec,0x3b,0xac,0xf8,0x67,0xf7,0xf4,0x5d,0x86, - 0x3b,0x90,0xa7,0x84,0x9f,0x84,0xc7,0xa1,0xc8,0xdf,0x82,0x1f,0x22,0x78,0x10,0xda, - 0x43,0xb4,0x3f,0xbc,0x0f,0x1e,0xd5,0x6c,0x9a,0x18,0xd5,0x52,0xf1,0xcf,0x41,0xc3, - 0x17,0xca,0xdc,0x9e,0xc3,0x89,0x5e,0x5e,0x4d,0xde,0x26,0xce,0x81,0xd1,0xa8,0x37, - 0xe8,0x6e,0x13,0x9f,0x24,0x28,0x7f,0xf8,0xfb,0x0e,0x5a,0xf9,0x3f,0x85,0xa3,0x3c, - 0xc9,0x7d,0x8b,0xbc,0x0a,0x3e,0x11,0x71,0x90,0xdd,0x78,0xae,0xdc,0x0c,0x84,0x6d, - 0x17,0x57,0xb1,0x5f,0xe9,0x66,0x44,0x2c,0x05,0xff,0x08,0x23,0x81,0x32,0xc8,0x6c, - 0xaa,0xd6,0xd4,0x3e,0x27,0x47,0x3b,0x5f,0x57,0x61,0xc4,0x56,0x29,0xd8,0x59,0x8d, - 0x06,0x27,0xcd,0x8c,0x3c,0x71,0x43,0x8a,0xff,0xe7,0x08,0x38,0x59,0x9d,0x4e,0x2b, - 0x3c,0xbf,0x30,0xda,0xa3,0x59,0x43,0x68,0xc8,0xef,0xd7,0x1e,0x61,0x2e,0x15,0x5c, - 0x74,0x03,0x94,0xe9,0x4b,0x06,0x44,0x2b,0xff,0xf9,0x6e,0x6d,0x6f,0xb4,0x90,0x4b, - 0x9b,0x2c,0xa1,0x01,0x8f,0xc9,0x8d,0x78,0x5e,0xe8,0x9e,0x2f,0xf1,0x78,0x31,0xdc, - 0x93,0x16,0x26,0x9d,0xc6,0x8d,0x3e,0x4b,0xfc,0x4b,0x17,0x72,0xe1,0x39,0x56,0x60, - 0x44,0x86,0xd3,0x73,0xe1,0x49,0x5b,0xbe,0x76,0xc3,0x7d,0xd9,0x8a,0xba,0x0f,0xe5, - 0x79,0xde,0x30,0xb9,0x09,0xc2,0x50,0xdc,0x2f,0xaf,0xce,0x76,0xa5,0xe0,0x9f,0x67, - 0xc3,0xb7,0xbe,0x6b,0x7f,0x24,0xec,0x83,0x93,0x6c,0x7e,0xdc,0x31,0x48,0x78,0x44, - 0xac,0x38,0x6e,0xaf,0x13,0xef,0x22,0x2f,0xb3,0xdb,0xce,0x3a,0x46,0xe4,0x6f,0x5b, - 0xfc,0x3f,0x1d,0x02,0x47,0x3b,0xd4,0x3b,0x4d,0x47,0xfb,0xd4,0x77,0x2f,0x2a,0xb2, - 0xb3,0x74,0x0c,0x81,0xae,0xa8,0xa2,0x60,0xbb,0x04,0xfb,0xab,0x11,0x0f,0xf8,0x2d, - 0xfc,0xe7,0xd7,0xb5,0xa1,0x68,0xd5,0xbb,0x99,0xa3,0xe4,0x07,0x81,0x57,0xd9,0xcd, - 0x3b,0x38,0xff,0x99,0x5e,0x66,0xf3,0xe2,0xee,0xe5,0x05,0x65,0xf4,0x25,0x56,0x1a, - 0x77,0x74,0xa7,0xf0,0x7f,0x7e,0xac,0xb3,0xfa,0x79,0x7d,0x91,0xef,0x92,0xbc,0xde, - 0xdf,0x40,0x31,0x20,0xfa,0xfd,0x6d,0xee,0xbe,0xee,0x62,0x4a,0x83,0xfe,0x5c,0x05, - 0xe5,0x4f,0xaf,0xfc,0x81,0x95,0xff,0x0c,0x6d,0x0d,0x1d,0xda,0x77,0x8c,0xeb,0xeb, - 0xb3,0xee,0x83,0x26,0x14,0x5c,0x72,0xc8,0x4c,0x7b,0x77,0x1b,0x19,0x1a,0x89,0xc2, - 0x01,0x86,0xf8,0xd9,0x6f,0xf5,0xff,0xe4,0xf6,0x52,0x16,0x2d,0xe9,0xa7,0xcf,0xe2, - 0xc5,0xad,0xe0,0xa6,0xb2,0xce,0x69,0xbd,0xcc,0x9d,0x97,0x61,0x27,0x8c,0x6d,0xd5, - 0xf4,0x5a,0x59,0x4d,0xe1,0x3f,0x77,0xc0,0xfb,0xa4,0xca,0x78,0x74,0x04,0x61,0xc6, - 0x31,0xce,0xe7,0x89,0x36,0x7e,0x84,0xfb,0xc7,0x17,0xcf,0xdc,0x2f,0xfe,0x1b,0x4a, - 0x18,0x6f,0xdc,0x91,0xca,0x7f,0x1e,0xe0,0x49,0xa6,0x2f,0x99,0x49,0x5e,0xa3,0x3c, - 0x1a,0xd8,0xd6,0x78,0x56,0x1b,0xa9,0xae,0x54,0xef,0x89,0x89,0xf7,0xc0,0xa0,0xfe, - 0x48,0xcf,0x14,0xfe,0xf3,0x05,0xdc,0x24,0xdc,0x5b,0xd2,0xe0,0xc6,0x3f,0x2d,0xed, - 0xcb,0x8a,0x8b,0x8f,0xe8,0x57,0xa5,0x2a,0xc3,0x1e,0x6a,0x74,0xc1,0x8b,0x6c,0x21, - 0x67,0x04,0x59,0xf0,0x0f,0xa0,0x3e,0x62,0x4e,0x23,0x10,0x13,0x43,0xca,0x60,0xbb, - 0x33,0xd2,0xb2,0x6d,0xa5,0x4a,0xbb,0xe3,0x25,0x50,0xa7,0x93,0x4e,0xa5,0x99,0xa8, - 0x9a,0x6b,0x9b,0xa8,0x27,0xf1,0x8f,0x30,0x07,0x22,0x2a,0xcf,0x2e,0x21,0x9d,0xd2, - 0x61,0x4e,0x8c,0xd9,0xb6,0x4e,0x85,0xc7,0xd9,0x03,0x86,0x29,0xc1,0x22,0x0a,0x02, - 0xa1,0xce,0xb0,0x15,0xff,0x14,0xb2,0x08,0x84,0x38,0xdb,0xa7,0x0f,0x74,0xfc,0x4f, - 0x86,0xbb,0x00,0x62,0xda,0x6a,0x4e,0x83,0x69,0x4a,0x63,0x1a,0xce,0x57,0x2d,0xf2, - 0x07,0x32,0x57,0xb1,0x3e,0x8d,0xd3,0x96,0xe4,0x0e,0x1e,0x7f,0xd7,0xee,0x61,0x39, - 0x6a,0xee,0x88,0x56,0xd2,0x63,0x67,0x05,0x2a,0x1c,0xd3,0xca,0x78,0x7c,0xc1,0x8a, - 0x7f,0xe2,0xfe,0x31,0x97,0xe9,0xcd,0xa8,0x47,0xa8,0x68,0x02,0xa1,0x61,0x9c,0x3f, - 0x4f,0xe0,0x03,0xe5,0xb2,0x80,0x1a,0xad,0x57,0xec,0xb4,0xe0,0x9f,0x31,0x36,0x06, - 0xf3,0xe3,0x77,0x9f,0x2f,0xf8,0x5b,0x9e,0x06,0xc5,0xdc,0xc3,0x5f,0xa8,0x84,0x13, - 0x0d,0x15,0x71,0xc7,0xeb,0x39,0x0b,0x22,0x97,0xd5,0x2a,0xdc,0x3f,0x5f,0xb7,0xe2, - 0x9f,0xb7,0x11,0x24,0x3b,0xe3,0x81,0x67,0x49,0x11,0x6c,0x3a,0x5a,0x12,0x8d,0x7c, - 0xd6,0x7e,0x93,0xd6,0x52,0x54,0x12,0x97,0xb7,0x12,0xb7,0x71,0xd0,0xc0,0x41,0xaa, - 0xff,0xe7,0x15,0x8e,0x87,0xb9,0xf5,0xdd,0x89,0x86,0x7f,0x49,0x13,0xf5,0xfa,0x4d, - 0x3e,0x58,0x4f,0x8b,0x27,0x5b,0x52,0xf7,0x2a,0x26,0xd1,0xc5,0x82,0x7f,0xa6,0xef, - 0x86,0x83,0x52,0x7b,0x9c,0xf2,0x68,0x63,0x0b,0x94,0x34,0x45,0x62,0x4e,0x3b,0x1f, - 0xf4,0xdc,0xd8,0x89,0xff,0xe2,0xa1,0x44,0x6a,0xbc,0x95,0xff,0x3c,0xc4,0x61,0xcf, - 0x43,0x77,0xc7,0xe4,0x08,0x27,0x86,0x65,0xdb,0x3d,0x39,0x9c,0xff,0xfc,0x03,0x63, - 0xd9,0x21,0x71,0x1e,0xbd,0xa4,0xf3,0x7c,0xc0,0x69,0x56,0xfc,0xf3,0x1c,0x5c,0xed, - 0xe0,0x24,0xde,0xf9,0xdd,0x0c,0xf5,0xbb,0x2a,0x9a,0x6e,0x1f,0xdc,0x81,0x37,0xc7, - 0x65,0x9e,0x5f,0x60,0x2e,0x9d,0x15,0xff,0xec,0x86,0xdf,0x43,0x85,0xdf,0xbe,0x57, - 0x74,0x69,0x27,0x38,0xcd,0x23,0x26,0x0e,0x85,0xcd,0xf8,0x23,0x47,0x44,0x27,0x88, - 0x99,0x88,0x67,0xf5,0xff,0x2c,0x0e,0xb4,0x04,0x9d,0xfd,0xae,0x0b,0xc2,0x77,0xb4, - 0xdf,0x21,0x86,0x96,0x3f,0x79,0xed,0x2a,0x6b,0x81,0x07,0x0c,0x59,0xcf,0xe6,0xf5, - 0x37,0xcc,0x8c,0xb6,0x14,0xfe,0xb3,0x5f,0x57,0xea,0x0c,0xba,0xcf,0x6f,0xe3,0xcb, - 0xa2,0xc9,0x95,0x78,0x5e,0x1a,0x89,0x8b,0xf3,0xe7,0x7b,0x71,0x3b,0x9a,0x8a,0x3b, - 0xc5,0xff,0x93,0xf1,0x68,0x53,0xc1,0x00,0x5d,0xe3,0xff,0x01,0xa7,0xfd,0x7c,0x43, - 0xfe,0x3e,0x79,0x07,0xd6,0x37,0x15,0x9f,0x95,0x79,0x20,0x6c,0x2d,0xcf,0x90,0xfa, - 0xc1,0x14,0xfe,0x73,0x5c,0x2d,0x37,0xec,0x1e,0x91,0x46,0x5f,0x68,0xaa,0x54,0x1d, - 0x1e,0xf1,0xa4,0xf0,0x02,0xab,0x1c,0x9a,0xa6,0x8a,0xb5,0xe4,0x28,0xc4,0x0c,0x47, - 0x45,0x0a,0xff,0xf9,0xe7,0xda,0xb3,0x7c,0x11,0x3e,0x69,0x1c,0xe4,0xde,0x30,0x69, - 0xd9,0xb0,0x78,0x19,0xae,0x2a,0x78,0x85,0xf3,0x5d,0xc7,0xf8,0xe0,0x13,0xb1,0x7f, - 0xd2,0xfe,0xea,0x4c,0xfb,0x10,0x4e,0xac,0x2a,0xe7,0xd9,0xee,0x7d,0xd2,0x89,0xe8, - 0x21,0xe6,0xde,0x9b,0x53,0x6c,0xf0,0xf5,0xd9,0xa4,0xd7,0x7c,0x80,0x1a,0xd3,0xcc, - 0xc7,0xb4,0xe2,0x9f,0x5f,0xc2,0xa3,0x4a,0xbe,0xf1,0xe8,0x43,0xf8,0x90,0xeb,0x95, - 0x02,0x46,0x1f,0x24,0x33,0xd9,0x6f,0xd0,0x7e,0x94,0x35,0xbc,0xd2,0x94,0xc8,0x27, - 0xb5,0xe2,0x1f,0x9e,0xed,0x3e,0x97,0x47,0xbb,0x2e,0x42,0x23,0xcb,0x7f,0x37,0x83, - 0xa7,0xa5,0x98,0x7c,0xef,0xba,0xf0,0x51,0x75,0x9d,0x49,0xfc,0x4e,0xc1,0x3f,0x43, - 0xd0,0xa8,0xe9,0x7a,0x46,0xcc,0xd9,0xc7,0xc3,0x5e,0xf1,0x0c,0x4f,0x91,0x3b,0x6b, - 0xab,0x84,0xdb,0x2c,0x9d,0xf4,0x00,0x33,0xcc,0xfd,0x66,0xc5,0x3f,0x9d,0xe4,0x94, - 0xb1,0x68,0xeb,0x52,0x3d,0xfb,0x4c,0xe8,0x38,0x2c,0xda,0x77,0xa7,0x8e,0xb0,0xf6, - 0x38,0x17,0x2c,0x83,0xe2,0x45,0x38,0xa5,0x9b,0x19,0x28,0x29,0xf8,0x47,0x19,0x59, - 0xce,0x49,0x3e,0x05,0x67,0x4d,0xb7,0x4f,0x96,0x64,0x12,0x81,0x7c,0x82,0x83,0xd5, - 0xc4,0xe7,0x8c,0xd0,0x6b,0xf2,0xbf,0x06,0xc6,0x93,0x80,0x72,0x0a,0x95,0x3b,0x81, - 0xa7,0xbd,0x8b,0xdc,0x9f,0x63,0xaa,0xc5,0xf1,0x7c,0xa8,0xd4,0xfc,0xaf,0x55,0xc4, - 0x24,0xe1,0x44,0xc9,0x1c,0xb6,0x4b,0x2a,0xd1,0x36,0xfc,0x98,0xe7,0x7f,0xa1,0xd9, - 0x2b,0x47,0xc7,0x89,0x3d,0x29,0xf5,0x7f,0x78,0xfc,0xab,0x99,0xb5,0x6b,0xb6,0xcd, - 0xfe,0x42,0xc6,0x81,0x50,0x24,0xea,0x2c,0xd4,0x77,0x24,0xf2,0xb5,0x87,0x26,0xe6, - 0xa7,0xfa,0x7f,0x1a,0x34,0x67,0xc8,0x86,0xb0,0x47,0xda,0x41,0xdc,0xc1,0x1b,0x78, - 0xfc,0x6b,0x47,0xb5,0x99,0x08,0x9f,0x20,0xc6,0x20,0x62,0xb4,0xe6,0x7f,0xad,0xc0, - 0xd5,0xf0,0xc2,0x3d,0xcc,0xa6,0x9a,0xd5,0x8d,0x78,0xfc,0x8b,0x0c,0x9a,0x6a,0x77, - 0x3a,0x27,0x02,0x99,0xef,0x6b,0xcd,0xff,0x7a,0xaf,0xe9,0xb2,0x56,0xa5,0xfd,0xbc, - 0x6d,0x9c,0xff,0x3c,0xaf,0x4d,0x7c,0x8f,0x67,0xb8,0x73,0x20,0xf4,0x19,0xbd,0xac, - 0x25,0x18,0x2f,0x56,0xfc,0x63,0xfc,0x56,0x2b,0xe5,0xbf,0xbd,0xc0,0x89,0xc4,0x01, - 0xfb,0xeb,0xe2,0x02,0xf6,0x7e,0x62,0x7d,0x0a,0xb5,0x63,0x2e,0x73,0x7e,0x8a,0xff, - 0xc7,0x88,0x68,0x4e,0x68,0x69,0xca,0x8e,0x93,0x08,0x94,0xdc,0x70,0x57,0x18,0x35, - 0x52,0xa7,0xda,0x0e,0x72,0x18,0x37,0x71,0x44,0x33,0x19,0x41,0xa9,0xf8,0x67,0x73, - 0x08,0x8d,0xac,0xeb,0xf8,0x69,0xd2,0xdc,0xb5,0x19,0xd7,0xe1,0xfb,0xee,0xa2,0xaa, - 0xb6,0x64,0xe6,0xd1,0xb4,0x86,0x86,0x89,0xf7,0xb5,0xf2,0x7f,0x9a,0x51,0x9e,0xe3, - 0xa2,0x7d,0x98,0xde,0x9c,0x56,0x12,0x94,0xb9,0xff,0x67,0x17,0xac,0x34,0x89,0xe8, - 0x22,0xcf,0xbf,0xbb,0x31,0x3a,0xc5,0xff,0xf3,0x06,0x78,0xb9,0x1b,0xe7,0x65,0x7f, - 0x33,0xf8,0x82,0x99,0xfc,0xfb,0x9e,0xc5,0xe7,0xdf,0xb4,0x4d,0x2c,0x34,0x8e,0x19, - 0xfc,0xf9,0x0b,0x52,0xf0,0x8f,0x3a,0x1a,0x49,0x2c,0x82,0xca,0x61,0x8f,0xc9,0x07, - 0x7b,0x83,0xf3,0xc1,0xb2,0xe5,0x73,0x30,0x6a,0xe2,0x9f,0x69,0x56,0xfc,0xc3,0xa0, - 0x4f,0xf1,0x65,0x3b,0x58,0xa3,0x2a,0xd5,0x25,0xa2,0xab,0x80,0xaa,0xa3,0x8c,0x2f, - 0x7b,0x3e,0xf4,0x69,0xe6,0xfa,0xa7,0xf0,0x9f,0x61,0x23,0xcc,0x8b,0xca,0x83,0xa4, - 0xbc,0xf0,0x22,0x94,0x34,0xc8,0x71,0x5b,0xb9,0x99,0x11,0x26,0x27,0xf2,0xbf,0x78, - 0xfd,0x96,0x95,0x56,0xff,0xcf,0xed,0xd0,0x62,0xac,0x8e,0xca,0xe5,0x44,0x36,0xf3, - 0x91,0x79,0xbe,0x2d,0x24,0x12,0x27,0xc9,0x6e,0xae,0xc1,0xf9,0xc0,0xea,0xff,0xa1, - 0xbc,0x48,0x4e,0x3f,0x8a,0xa9,0xfb,0x39,0xed,0xa7,0x4f,0x06,0xa2,0x28,0xeb,0x3d, - 0xb3,0x0d,0xb9,0x94,0xf0,0x54,0x71,0x7e,0x7e,0x9d,0xa9,0xfe,0x1f,0xce,0x76,0x76, - 0xf0,0xb4,0xf7,0x3f,0xb0,0xc5,0x67,0x1d,0x75,0xa2,0x0f,0x5e,0x8d,0xdd,0xca,0xaf, - 0x3c,0x11,0xfe,0x4d,0xe2,0x57,0x56,0xfe,0x73,0xa7,0x34,0x9a,0xe6,0x43,0x25,0x3e, - 0xcb,0x9e,0x48,0x7b,0x8f,0x8a,0x71,0x7a,0x49,0xe5,0x66,0xbe,0xfc,0xa1,0x49,0x74, - 0x49,0xe5,0x3f,0xa7,0x7d,0xae,0x1d,0x8b,0xce,0x1f,0xb0,0x8f,0x22,0xec,0x39,0xc1, - 0xbc,0xef,0x3a,0x78,0xd9,0x9f,0x57,0xc3,0xbe,0xf8,0xa6,0x51,0xf1,0xaa,0x7a,0x35, - 0x91,0xff,0x6e,0xe4,0x5a,0xf8,0x3f,0xd0,0xb4,0x23,0xbf,0x37,0xf3,0xeb,0xe2,0x13, - 0xfa,0xce,0xd8,0xdc,0x01,0x14,0x3b,0xfd,0xda,0x7a,0xb5,0x78,0x10,0xc5,0x08,0x07, - 0x36,0x8b,0xb9,0xfc,0xb1,0xfa,0x7f,0x72,0x61,0x2d,0x29,0x30,0xee,0xac,0x27,0xcf, - 0x35,0x35,0x0a,0xf9,0x06,0xee,0x36,0x9e,0xaf,0xf1,0x9d,0x3e,0xf9,0xbb,0xe4,0x6d, - 0xed,0x40,0x42,0x5e,0xa5,0xfa,0x7f,0x1a,0x7a,0xf4,0x5f,0x65,0x00,0xd9,0xc4,0x76, - 0x42,0x9d,0x81,0xbb,0xcb,0x80,0x46,0xc9,0x5c,0xc6,0x93,0x2b,0xf6,0x6a,0x09,0x62, - 0xa7,0xd5,0xff,0x93,0x7e,0x22,0xd2,0x55,0x8f,0xf6,0xe3,0x46,0x38,0x81,0x40,0xc5, - 0xc1,0xf9,0x4e,0xaf,0x02,0xae,0xc0,0x15,0xf1,0xaa,0x49,0xf4,0x75,0xc4,0x6a,0x92, - 0xfb,0x81,0x69,0x08,0x02,0xd5,0x23,0xf5,0xa8,0x7d,0x76,0xc3,0x25,0x09,0xa7,0x75, - 0x98,0x7c,0x54,0x9f,0x71,0x73,0x17,0x27,0x4a,0x29,0xd7,0xe4,0x7f,0x8d,0xa1,0xda, - 0xaa,0xf2,0x37,0x0d,0xcb,0x8b,0x79,0xf6,0xae,0xe1,0xb8,0x4b,0xbc,0x97,0x25,0xf8, - 0x3f,0x05,0x63,0xf0,0x27,0x7b,0x82,0xff,0xac,0x25,0xe3,0x5f,0x75,0xd0,0xc2,0x0a, - 0xeb,0xe9,0x3e,0xe7,0x6c,0xc5,0xa4,0xf1,0xec,0x26,0x3a,0x1b,0xe7,0xff,0x0c,0x99, - 0x8c,0xe8,0x29,0xf9,0xef,0x76,0x94,0x3f,0x25,0xf1,0x1b,0x3c,0xe1,0xd5,0x26,0xed, - 0xe7,0xa7,0xec,0x99,0xd5,0xca,0x35,0xf3,0xad,0xfc,0xe7,0x30,0x53,0x0b,0x8d,0x1b, - 0x3c,0xc4,0xce,0x1a,0x15,0x3b,0xcf,0xc6,0x6d,0x95,0x50,0xf1,0x1d,0xbd,0xd1,0x9b, - 0x9d,0x28,0xd4,0x26,0x7b,0xb2,0x2d,0xfe,0x1f,0xfb,0xd2,0x0e,0x14,0x0b,0x3d,0x1b, - 0x63,0xf2,0x6a,0xe7,0x09,0xd5,0xd7,0x8b,0xeb,0x13,0x82,0x57,0x83,0xbe,0x33,0x8e, - 0x2e,0x93,0x98,0xe1,0xe5,0x8a,0xd8,0x82,0x7f,0xee,0xde,0x0d,0x97,0x95,0x85,0x46, - 0x5a,0xbf,0x78,0x12,0xae,0x86,0xaa,0x7a,0x1d,0x71,0xd1,0x24,0x42,0x1f,0xcf,0xdc, - 0x53,0xc0,0x13,0xbd,0xf1,0xc5,0xcf,0x37,0x5a,0xfc,0x3f,0x33,0xae,0xc0,0xdb,0x6b, - 0xab,0x56,0xed,0x3e,0x2a,0x66,0x73,0x36,0x14,0xc7,0x4b,0x9f,0xc0,0x25,0xb6,0x87, - 0xda,0x5f,0x10,0xab,0xa0,0x55,0x9d,0x1f,0x7f,0x34,0x35,0xfe,0xf5,0x11,0x1c,0x0c, - 0xa3,0x7d,0xda,0x94,0xad,0xb2,0x16,0xa3,0x7d,0xba,0xd8,0x4a,0xf2,0xed,0x97,0xb8, - 0x07,0x2c,0x4c,0x28,0xfb,0x99,0xe1,0xec,0xcb,0x9c,0x12,0xff,0x82,0x28,0xac,0xd6, - 0x68,0x7a,0x58,0x55,0xf7,0x6a,0xae,0x1b,0x64,0x89,0xf4,0xb0,0xc3,0x82,0xaa,0x50, - 0xc1,0xef,0xc2,0xcf,0x59,0x77,0x74,0xee,0xd4,0xf8,0xd7,0x41,0x5e,0xed,0x44,0xd0, - 0x56,0xb0,0x9f,0x81,0x53,0x97,0x3b,0xc9,0x1c,0xbe,0x8c,0x71,0x75,0x1b,0x9e,0xdf, - 0x5d,0x68,0xd8,0x66,0x4c,0x89,0x7f,0xc1,0x1b,0x01,0x5f,0x9d,0xbd,0xb5,0x71,0x0e, - 0x8f,0x0e,0xbb,0x1c,0x33,0xe5,0x3f,0xc0,0xa7,0xa2,0x37,0xd4,0xba,0x5d,0xb4,0xc3, - 0xb1,0xea,0x72,0xa3,0x38,0x26,0xa6,0xe2,0x9f,0xcb,0xd1,0x2a,0x90,0xcf,0x88,0xfb, - 0xe1,0x65,0x2e,0x96,0xf9,0x7e,0xfb,0x98,0xfe,0xb3,0x36,0x2f,0x8a,0xaf,0xf9,0x5d, - 0x58,0x38,0x05,0xff,0xc0,0x6e,0xee,0xdf,0x0e,0xa2,0x91,0xdb,0xc1,0xde,0x02,0xdf, - 0x72,0x7b,0xd3,0xcf,0xd4,0x6a,0xd4,0xef,0x4a,0xd6,0x93,0xdc,0xff,0x43,0x2a,0x78, - 0xa0,0xcd,0x8a,0x7f,0xdc,0x70,0x5b,0xaf,0x93,0xd3,0xb6,0x5f,0x56,0x37,0x71,0x43, - 0x7e,0x23,0xb9,0xe5,0xf6,0xb7,0x50,0x91,0xd1,0x1f,0x21,0x7e,0x7b,0x03,0xc8,0x4b, - 0x99,0x29,0xf8,0x67,0xc6,0x52,0xd8,0xc3,0xe6,0x68,0x54,0xf5,0xf7,0xa0,0xd8,0x59, - 0x3d,0x7c,0x97,0x9a,0x4d,0x51,0x83,0xaf,0xd2,0xb9,0x47,0xc8,0x60,0xe0,0x1e,0xb6, - 0x4d,0xc1,0x3f,0xf0,0x4b,0xe3,0x96,0x55,0xae,0x6f,0x91,0xf3,0x64,0x7d,0x43,0x71, - 0x3b,0xfd,0x3e,0xb9,0x4e,0x5b,0x1f,0x2b,0x5e,0x65,0x5b,0x3e,0xe7,0x06,0xe5,0xc7, - 0x3d,0xb3,0xe3,0x19,0x53,0xf3,0xbf,0x3e,0xc9,0xdb,0x77,0x3b,0x55,0x44,0x83,0xbd, - 0x50,0x58,0x09,0x45,0xb9,0x22,0xf8,0x1b,0xa3,0x0b,0xb6,0x6c,0x54,0x45,0x4a,0x0c, - 0xa5,0xb2,0x6f,0x4a,0xfe,0xd7,0x73,0xf0,0x09,0xdc,0x56,0x3b,0x8d,0x87,0x4d,0x3f, - 0x06,0xb3,0x10,0xe2,0x05,0x33,0x3e,0xf8,0xca,0xaf,0x78,0x44,0x55,0x5a,0x64,0xa4, - 0xc6,0xbf,0xd2,0x78,0x51,0x0e,0x5f,0xc8,0xae,0xcb,0x59,0xfc,0xfc,0x72,0xfe,0x6a, - 0x39,0x1f,0x40,0xa6,0x21,0x0e,0x29,0x23,0xc4,0xc7,0x13,0x39,0x53,0xfd,0x3f,0x5c, - 0x68,0xb8,0x3c,0x62,0x2e,0xac,0x37,0x78,0xf4,0x41,0x7c,0x98,0xac,0x17,0xe6,0xf2, - 0x44,0xe3,0x7e,0xd8,0xaf,0x17,0xf3,0x52,0x1b,0x56,0xfc,0xf3,0x04,0x1c,0x68,0xfa, - 0x87,0x90,0xed,0x61,0xbf,0x8f,0xe3,0x9f,0x90,0x7c,0xbf,0x2d,0x9b,0x67,0x84,0xa9, - 0xcd,0x75,0xe1,0x37,0x61,0x5f,0xac,0x98,0xbf,0x6f,0x8a,0xff,0x07,0xf6,0xf6,0xaf, - 0xee,0xb1,0x3d,0xe7,0xb7,0x35,0xa0,0x18,0x0f,0xca,0x33,0x6d,0x7f,0xaf,0xe1,0xf9, - 0xfa,0x1e,0x7d,0x82,0x1c,0xd7,0x62,0x3c,0x91,0x70,0x0a,0xfe,0x81,0xcf,0xb5,0xaa, - 0xf6,0xac,0x01,0xb1,0x9c,0x07,0xca,0xda,0x51,0x3e,0x97,0xc3,0x6b,0x68,0xd8,0x65, - 0x0e,0x8a,0x23,0xca,0x15,0xcd,0xac,0x27,0x36,0xc5,0xff,0x13,0xca,0xa2,0x99,0xe1, - 0x02,0xb3,0x30,0x4b,0xb6,0x23,0x2c,0x9e,0x65,0x23,0x62,0x45,0x9e,0xc3,0x64,0x44, - 0x87,0xfe,0x0c,0xfe,0x19,0x2f,0xfb,0x53,0x88,0x0b,0x6b,0x0e,0x66,0x4b,0xc7,0xb4, - 0x8a,0x60,0xd6,0xb6,0x82,0x42,0xee,0xff,0xd1,0x4a,0xa6,0xe0,0x1f,0x38,0xa8,0x3b, - 0xb5,0x96,0xe8,0x5d,0x85,0xf4,0x20,0x71,0xd6,0x72,0xb5,0x1b,0x6e,0x66,0x6a,0x90, - 0xf3,0x7f,0x42,0x97,0x13,0xfe,0x9c,0x54,0xfc,0x73,0x50,0x75,0x6a,0x4b,0xb8,0xb5, - 0x75,0x10,0x7f,0x9b,0x11,0x45,0xd0,0x6d,0xf2,0x55,0xf6,0x10,0x89,0x0f,0x42,0xb6, - 0xe8,0xd4,0xfa,0x3f,0x7c,0x59,0x72,0xfd,0x69,0xb0,0x47,0xc0,0x81,0x92,0xcd,0xf9, - 0x3f,0x21,0x8d,0xe6,0x7a,0xd3,0x78,0x05,0xaa,0x20,0x4d,0xc5,0x3f,0xa1,0xf1,0xb2, - 0x3f,0x05,0xbc,0xfe,0x4f,0x17,0x6b,0xe6,0xf5,0x7f,0xfa,0xa0,0x82,0x6d,0xd4,0xc7, - 0x13,0xb1,0x37,0xa6,0xe2,0x9f,0x01,0xb8,0x2c,0xfc,0x12,0xf1,0x4c,0xce,0x18,0xe5, - 0xf8,0x47,0xbc,0x2f,0xe7,0x33,0xf8,0x0c,0x16,0xf7,0x2f,0x3b,0xad,0x5d,0x80,0xcb, - 0xd5,0x95,0x53,0xf1,0x0f,0x0f,0x93,0x79,0xaa,0x1d,0x6d,0xe2,0x02,0xf2,0x8a,0xab, - 0x34,0x68,0xef,0x17,0xf7,0xe9,0x2f,0xe2,0x46,0xb2,0x9f,0x16,0x67,0xc3,0xbf,0xc3, - 0x7c,0x9e,0x3f,0x95,0xea,0xff,0xe9,0xe6,0xa4,0xb8,0xb5,0xd9,0x40,0x39,0x10,0xa2, - 0x4f,0xfa,0xe7,0xea,0x11,0x68,0x57,0xe8,0x3a,0x42,0xcd,0xfa,0x87,0xae,0xa9,0xf8, - 0xe7,0x20,0xb8,0xfc,0x72,0xf6,0xca,0x81,0xce,0xcd,0xc0,0xb3,0xbd,0x48,0x13,0x67, - 0x58,0x05,0x23,0xb9,0xa4,0x29,0xfa,0x53,0x70,0x69,0x54,0x49,0x8d,0x7f,0x29,0x07, - 0xa1,0x28,0x28,0xb7,0x55,0x0c,0xc0,0xe3,0x92,0x33,0x18,0x89,0x66,0x27,0xea,0xff, - 0xd0,0x2d,0xfc,0x0f,0x95,0x22,0x8d,0x4e,0xc5,0x3f,0x9f,0xb0,0x0a,0xcd,0xb1,0x8d, - 0x70,0x18,0xd3,0x55,0x8f,0xf8,0xb6,0x23,0x80,0x9f,0xb5,0x5e,0xfa,0xb1,0xf8,0xa4, - 0xf6,0x06,0x94,0x9b,0xf9,0xef,0x56,0xfc,0x03,0xa3,0x85,0xfb,0x35,0xc7,0xf5,0xe2, - 0x9c,0xd0,0x59,0xa1,0x72,0xd5,0xbc,0x9f,0x88,0xbd,0x64,0x54,0xa8,0x0c,0xcc,0xcb, - 0x93,0x1f,0x80,0xd1,0xd6,0xfd,0xfe,0xa9,0xfe,0x1f,0xbe,0xfe,0xca,0x52,0x26,0xef, - 0x00,0xb3,0xec,0x00,0xe2,0x97,0xda,0x11,0xa5,0x2b,0xdb,0xde,0x94,0x93,0x4f,0xc6, - 0xf9,0xe7,0x29,0xf1,0x2f,0x38,0xc2,0xd9,0x3e,0x3a,0xb9,0x01,0x9e,0x61,0x05,0x51, - 0x1a,0x0a,0x2f,0x82,0x23,0xb0,0x30,0x9a,0x39,0xb0,0xe1,0x0b,0xea,0xe7,0x20,0x32, - 0x97,0x9e,0x9a,0xff,0x05,0x7b,0x07,0x18,0x9e,0x47,0xba,0x09,0xad,0xad,0xc2,0x87, - 0x32,0xca,0xd7,0xad,0x55,0xf7,0x30,0xb5,0xdf,0x96,0x17,0x76,0x34,0x35,0x6a,0xc0, - 0xa8,0xc7,0x99,0x1a,0xff,0xda,0xaf,0x15,0xf0,0xfa,0x3f,0x79,0xea,0x0e,0x3a,0x3b, - 0x78,0x3d,0x4f,0x83,0xda,0x07,0xdf,0xe0,0xc0,0x60,0xa6,0xb2,0x1f,0xf2,0x8d,0xba, - 0xa9,0xf9,0x5f,0x9c,0xff,0xd3,0x7a,0x91,0x3c,0x81,0xd6,0xd9,0xc2,0xf8,0x5c,0xb3, - 0xec,0x4f,0xc3,0xfc,0x78,0xc9,0x99,0x82,0x1b,0xc8,0x4b,0x6c,0xb3,0x3e,0x35,0xff, - 0x0b,0x86,0x39,0xff,0x27,0xf6,0xfb,0x41,0x3c,0x38,0x8b,0x78,0x76,0xea,0x30,0xcf, - 0x37,0xd1,0x50,0x9e,0xbc,0xa7,0x5f,0xe4,0x12,0x3b,0x05,0xff,0x64,0x5e,0x81,0xe7, - 0xf5,0xaa,0x77,0xed,0x17,0x1b,0x3f,0xa7,0xbf,0x63,0xa5,0xab,0xec,0x23,0x37,0x96, - 0xd1,0x57,0xd9,0x7c,0xdd,0xcd,0x03,0x61,0xc6,0xe6,0x52,0xdd,0x3d,0x62,0x8d,0x7f, - 0x09,0xdb,0x61,0xbf,0x31,0x8f,0x47,0xdb,0xc7,0xd8,0x6f,0x60,0xe7,0x3d,0x68,0x7f, - 0x4d,0x57,0xd3,0x61,0x2e,0xb3,0xad,0x20,0x33,0xb5,0x26,0xb6,0x23,0x62,0x4b,0xc5, - 0x3f,0x28,0xaf,0x68,0x31,0x67,0x07,0x9d,0x56,0xd6,0xc3,0x6c,0xad,0x9c,0xd3,0x7e, - 0x70,0xd0,0x8b,0xf2,0xaa,0x1e,0x5a,0x3d,0xb3,0x1b,0xe8,0x14,0xfc,0x23,0x75,0x55, - 0xbb,0x8d,0xf2,0x05,0x47,0x4f,0xa9,0x5b,0x61,0x4e,0x34,0xaf,0x8c,0x7c,0xdb,0x34, - 0x6c,0x6f,0x50,0xfd,0xb7,0xe3,0x77,0x29,0x04,0xdb,0xd4,0xf8,0xd7,0x25,0xb6,0xf8, - 0x35,0x7a,0x81,0xbc,0xe2,0x79,0x01,0xca,0x0a,0x29,0x88,0x7f,0x0f,0x2f,0x40,0xe1, - 0x79,0xf7,0x13,0xf2,0x77,0xe0,0xa8,0x51,0xc6,0xdc,0xd7,0xc4,0xbf,0x42,0x59,0x7d, - 0xb8,0x08,0x83,0xd2,0x25,0x5e,0x98,0xeb,0xd9,0x82,0x1d,0x0c,0x07,0x67,0x36,0xb5, - 0x8b,0xbb,0x43,0x17,0xff,0x0c,0xfe,0x81,0xab,0x7a,0xa9,0xd1,0x3a,0x2c,0x3f,0x07, - 0x27,0xa2,0xa5,0x2c,0xb3,0x41,0x74,0x0b,0xaf,0x36,0x2c,0x1a,0x44,0xa0,0x3e,0x02, - 0xa7,0xa0,0x94,0xb5,0xa6,0xf8,0x7f,0xa4,0xd5,0x10,0x3b,0xca,0xfd,0x3f,0x7e,0x97, - 0xd2,0x22,0xa0,0x5a,0xef,0xb2,0x15,0xc0,0x5b,0xf7,0x3a,0xe3,0x14,0x77,0x78,0xfa, - 0x86,0x06,0x55,0x9b,0x17,0x9b,0x12,0xff,0x3a,0x64,0xa6,0x89,0xd9,0x3a,0xe0,0xa7, - 0xb0,0xd2,0x49,0x63,0x73,0xe6,0x48,0x2d,0xf6,0x6f,0x1f,0xa5,0xdb,0xc2,0xaf,0xd0, - 0x0d,0x86,0xb3,0x61,0x0a,0xff,0xc7,0x0e,0x5d,0xea,0x78,0x5a,0x19,0xca,0x67,0xc1, - 0xc5,0xc3,0x1c,0x26,0x3f,0x13,0x10,0x58,0x86,0xd5,0x10,0xfb,0x82,0xc7,0x9a,0xff, - 0x95,0xb6,0xda,0x04,0x39,0xae,0xe1,0x9c,0x0e,0xf2,0x16,0x74,0x69,0x33,0x79,0xa1, - 0xb9,0x16,0x7c,0x4d,0x37,0xcb,0x89,0x93,0xe3,0xf9,0x5e,0xbe,0x3e,0x16,0xfc,0x33, - 0x63,0xcc,0xcc,0xdf,0xe1,0xfc,0x0d,0x0e,0x7b,0x40,0x1e,0x16,0x86,0xf3,0xfe,0xa4, - 0x56,0x71,0xe2,0xd3,0x30,0x5c,0x51,0x16,0x43,0x6a,0xfd,0x9f,0xaf,0x5c,0x51,0x2e, - 0x85,0x4a,0xcf,0x6e,0x32,0xc4,0x7b,0xe1,0x52,0x83,0x57,0xcd,0xec,0x13,0x2b,0x95, - 0x56,0xe8,0x8a,0xcf,0x1c,0x2d,0xb8,0x4e,0xbb,0x9c,0x5d,0x1a,0xb7,0x8f,0x88,0xb1, - 0x24,0xfe,0x81,0x8f,0xe0,0xf9,0x5a,0x12,0x42,0x23,0xcb,0x29,0xb5,0xa8,0x65,0x21, - 0x79,0x1b,0x79,0x5e,0x3b,0x1e,0x72,0xc6,0xcd,0x0a,0x90,0x87,0x83,0x2b,0xe3,0xb4, - 0x5b,0x4c,0xd6,0x7f,0x36,0xcf,0x97,0x47,0x35,0x96,0x84,0xb7,0xa8,0xf4,0xa7,0x2e, - 0x17,0xb7,0xce,0xec,0x10,0xc9,0xc3,0xf7,0xf5,0x66,0x4b,0x6c,0xb3,0xaa,0xf2,0xa5, - 0xe8,0x4a,0xc1,0x3f,0x87,0x21,0xdc,0x2f,0xb3,0x97,0x9c,0x6a,0x0b,0xcc,0x01,0x79, - 0x1d,0x31,0x2b,0x42,0x1b,0x75,0x31,0x52,0x02,0x87,0x99,0x19,0x58,0x4c,0xd6,0x7f, - 0x06,0xc9,0x2d,0x1d,0x06,0xef,0x30,0x2a,0x1d,0x51,0xf9,0x35,0x54,0xa8,0x99,0x92, - 0xe8,0x46,0xb3,0xc8,0x73,0x9e,0xc6,0xa6,0x95,0xb0,0x4b,0xac,0xdd,0x70,0xc7,0x84, - 0xe8,0xe4,0xf3,0xef,0xd0,0x78,0xfe,0x7b,0xd5,0x17,0x1d,0xc7,0xe4,0x98,0xeb,0x77, - 0x46,0xd5,0xf0,0xa6,0x91,0xc6,0xb7,0x6d,0x1f,0x6d,0xfe,0xe1,0x7b,0x9c,0xff,0xa3, - 0x8c,0xfb,0x7f,0x86,0x2c,0xfa,0x77,0x37,0x47,0xd7,0x31,0x07,0xe7,0x1f,0xbe,0x25, - 0x95,0x69,0x8e,0xa6,0x9a,0x8f,0x38,0xff,0xe1,0xa8,0x3d,0x26,0x7e,0xc8,0x4d,0x63, - 0xbe,0xdf,0x92,0xfc,0xe7,0x3e,0xc9,0x0d,0xcf,0x73,0x23,0x0b,0x88,0xca,0x7e,0x16, - 0x71,0xc6,0xe5,0xce,0xec,0x31,0xa5,0x1d,0xd5,0x6e,0x66,0xcc,0x3f,0x94,0xbb,0x81, - 0xa9,0xf1,0x14,0xff,0x8f,0x91,0x6b,0x87,0xc3,0x68,0x86,0xb7,0xa8,0x44,0xe0,0x34, - 0x8c,0x8e,0xbf,0x2b,0xc6,0x6d,0xd0,0x0e,0x6e,0x5c,0xcf,0xec,0x93,0xd9,0xcd,0x3b, - 0x70,0xbe,0x07,0xf5,0xfb,0xc4,0x4f,0x08,0x66,0xc1,0x81,0x1d,0xc5,0x5a,0xcb,0x08, - 0x79,0x48,0x7b,0x3a,0xd6,0x50,0x67,0xd2,0x76,0x9f,0x8e,0x16,0x7f,0xd0,0xbc,0xc6, - 0x79,0x45,0x49,0x67,0xf9,0xef,0xe2,0x95,0xb1,0xc9,0x7a,0xe0,0x81,0xbc,0x2c,0xed, - 0xd3,0x86,0xca,0xda,0x65,0x20,0xdb,0x58,0x4b,0x7b,0xee,0xee,0xff,0xe6,0x11,0x4f, - 0xda,0xdf,0xf5,0x57,0x0e,0xda,0x17,0xe5,0x9f,0x04,0xc4,0x69,0x9c,0xf8,0x6d,0xc1, - 0x3f,0xf6,0xe7,0xb4,0xab,0x1a,0x2e,0x82,0x26,0x3e,0xc7,0x3e,0x06,0x9f,0xe8,0xf8, - 0xa4,0xf1,0x6d,0xb8,0xc2,0x89,0xd3,0xc3,0xe2,0xc3,0x9a,0x19,0x3a,0xe4,0x78,0x72, - 0xe2,0x7d,0x39,0xbf,0xf4,0x92,0x5a,0x19,0xb7,0xc7,0x45,0x40,0xd8,0x53,0xb2,0x65, - 0x53,0x58,0xfc,0x30,0x74,0x11,0x3c,0xb8,0xec,0x39,0x89,0xc4,0x4c,0x5c,0xa8,0xa3, - 0xc9,0xfa,0x27,0x1c,0xff,0xd4,0x16,0x73,0xb6,0xb3,0x82,0x78,0x7b,0xbe,0xc1,0xcd, - 0x28,0x76,0x00,0x76,0x70,0xd8,0xf3,0x36,0x3d,0x07,0x1c,0xff,0xac,0x4c,0xf2,0x7f, - 0x80,0xe3,0x1f,0xbd,0x38,0x4e,0x29,0xb9,0x41,0x58,0xcf,0xbe,0x35,0x28,0xff,0x2d, - 0xbe,0x6f,0xd7,0xba,0x9d,0x3c,0x11,0x0c,0xf1,0x0f,0xc3,0x5f,0xad,0xf1,0x6f,0x4b, - 0xc5,0x3f,0xe0,0xee,0x8f,0x30,0x42,0x23,0x5b,0x25,0xb5,0x5f,0xbe,0x0d,0xd7,0xb3, - 0x0b,0xd4,0xce,0x1b,0xb8,0x19,0xab,0x07,0x57,0x73,0xfc,0xf3,0x66,0x12,0xff,0x48, - 0x9d,0xdc,0xe9,0xd7,0x84,0xcf,0x5f,0x4e,0x8f,0xef,0xa8,0xe8,0x76,0xe8,0x39,0x83, - 0xf8,0xbe,0xf3,0xb7,0x21,0xe2,0x7d,0x63,0xd5,0x95,0xa6,0x4a,0x86,0x83,0x43,0xc9, - 0xfb,0x9b,0xfa,0xc8,0xa7,0x38,0xd8,0x17,0x78,0x1a,0x0e,0x77,0x04,0xe5,0x18,0xe3, - 0x57,0xa6,0xc5,0x73,0x47,0x68,0x16,0xcc,0x63,0x05,0xaf,0x25,0xd7,0x27,0x58,0xa8, - 0x8c,0x42,0x36,0x2f,0xf3,0x3b,0x47,0x38,0xa6,0x7b,0x6b,0x97,0x6d,0x2b,0x18,0x80, - 0xf7,0xa1,0x6c,0x95,0x99,0xdf,0xd4,0x03,0xe3,0xf5,0x0f,0x27,0xe6,0xb3,0x44,0x3d, - 0xc3,0xfa,0x96,0x28,0x99,0x16,0xdd,0xc1,0x8a,0xb8,0xf5,0xc4,0x15,0xab,0x73,0x4d, - 0xa6,0x99,0x88,0xad,0xb5,0x27,0xf0,0xcf,0xc4,0x4f,0x9e,0xd4,0x01,0x7b,0xa0,0xe8, - 0x3e,0x8e,0x7f,0xb4,0x66,0x84,0xd9,0x4b,0x36,0x93,0x73,0xb8,0x91,0xe6,0x68,0x89, - 0xc4,0xed,0x66,0x13,0x11,0x59,0xf0,0x4f,0xae,0x04,0x7b,0x34,0x33,0xdb,0xab,0x90, - 0xee,0xac,0xa6,0x5a,0x8b,0x92,0xdd,0x2b,0x6c,0xd6,0x70,0x5a,0xae,0xff,0x3d,0x1e, - 0x01,0xd1,0xe6,0xa6,0xe0,0x1f,0xca,0xf1,0x4f,0x05,0x1e,0x5b,0xc4,0x3f,0x94,0x98, - 0xd1,0x96,0xb8,0xd4,0x07,0xfb,0xc1,0x94,0x3f,0x89,0x8a,0x34,0x05,0x1f,0x4d,0x9b, - 0x90,0x3f,0xdd,0xb9,0x88,0xf7,0x6a,0xab,0x34,0xc7,0x85,0x02,0x5e,0x08,0x88,0x7b, - 0x33,0x84,0xf7,0xe0,0xb7,0x7e,0xbc,0x12,0x25,0x63,0xc0,0xfd,0x3f,0x59,0x51,0xf1, - 0xa3,0xc9,0xfa,0xab,0xe5,0x88,0x7f,0x46,0x5d,0xa5,0x46,0x56,0x9b,0xbc,0x00,0xde, - 0x13,0x7c,0xd5,0xf6,0x68,0xce,0xf7,0xd4,0x63,0xb4,0x4a,0xb3,0x6f,0x16,0x07,0xb4, - 0x57,0x5c,0xbc,0xfe,0xa1,0xf8,0xd1,0xe4,0xfe,0xc9,0x83,0x38,0x2d,0xcf,0x47,0xd8, - 0xb3,0x0e,0x9f,0x27,0xe2,0xca,0x62,0x36,0x96,0x1d,0x82,0x33,0x2a,0xe7,0x23,0x89, - 0x71,0x5b,0xc4,0xc9,0xeb,0x1f,0xe2,0xfb,0x4e,0x7c,0x5f,0x0d,0x9a,0x60,0x8f,0x4b, - 0xe5,0xf5,0x9f,0x6b,0xa5,0x1d,0xa4,0x48,0x8b,0xf0,0xfa,0xcf,0x0d,0xb4,0x44,0x63, - 0xf8,0xe2,0xac,0xc1,0xe5,0xe6,0xf8,0x27,0x59,0xaf,0x32,0x2f,0xb7,0x83,0xc3,0xc8, - 0x00,0x8d,0xde,0x30,0xdb,0x0c,0x44,0xda,0xa2,0x6c,0x35,0x02,0xa1,0xa2,0xa0,0x10, - 0xc5,0x3f,0x34,0xeb,0x2f,0x71,0xfc,0x33,0xb1,0x3e,0xbc,0xfe,0xe1,0x41,0xe8,0x5a, - 0x93,0x85,0xbf,0x55,0xde,0x0f,0x3f,0x8c,0xbf,0x15,0x57,0xc1,0xb1,0x90,0xbb,0x9e, - 0x46,0x6f,0xc1,0xf5,0x37,0x78,0xfd,0x43,0xc4,0x03,0x13,0xf7,0x1f,0x54,0x3a,0x10, - 0x06,0xe3,0xb2,0xe4,0x8a,0x7f,0xa0,0xa3,0x01,0xb3,0x10,0x22,0xcf,0x7f,0xf7,0xd5, - 0x39,0xa2,0xd3,0x3a,0x12,0x11,0xc3,0x28,0xe2,0xed,0x89,0xf9,0x45,0xe6,0x7e,0x2b, - 0xe1,0xcb,0x1e,0x4a,0x54,0x97,0x6a,0x12,0xe3,0xea,0x78,0x21,0xa0,0x38,0xf4,0xa9, - 0x53,0xf0,0x0f,0x4d,0xe3,0xd5,0x0e,0x8b,0x9b,0x96,0xe8,0x35,0x87,0x8c,0x23,0xd5, - 0xdc,0xed,0xa3,0x8d,0x48,0x1b,0xe0,0xf7,0xd1,0x16,0x9d,0x0c,0x2a,0x1b,0xf1,0x20, - 0xb8,0x74,0x31,0x3c,0xb9,0x7f,0x68,0xda,0x52,0x05,0xcf,0x4b,0x1b,0x0a,0x19,0x1b, - 0xc4,0x58,0xe1,0xbb,0x72,0x39,0x4f,0x93,0x14,0xd4,0x31,0xb3,0x5e,0x4d,0x34,0xa8, - 0x26,0xf8,0x99,0x13,0xf3,0x79,0xfd,0xc3,0x03,0x85,0xc5,0x70,0xe3,0xa7,0x78,0xe8, - 0xf6,0x19,0xf9,0xfd,0x72,0x7d,0xf8,0xb7,0xb4,0xb1,0x3d,0x9f,0xbb,0x41,0xde,0x16, - 0xd7,0x31,0xce,0xdf,0x4b,0xef,0x4b,0xe2,0xb7,0x3c,0x44,0x3b,0x3b,0xfe,0x79,0x87, - 0xe3,0x07,0x68,0x5f,0x5f,0x60,0xb7,0xbe,0xeb,0xf8,0x1b,0xf1,0x54,0xc6,0xcb,0x46, - 0x7e,0x3c,0xf3,0x91,0xc6,0x2b,0xda,0xdb,0x6c,0x4f,0x88,0xae,0x11,0x8f,0xa7,0x4f, - 0x3e,0x4f,0x26,0xca,0xdb,0x2f,0xf9,0x1a,0x1c,0xe5,0x7f,0x35,0xa8,0xf8,0xe0,0x08, - 0x9a,0xf9,0x5c,0x8c,0xb8,0x7c,0x2c,0xb3,0x2b,0x67,0x75,0xef,0x78,0xe2,0x6d,0x78, - 0xd2,0xff,0x1c,0x92,0x8e,0xc0,0x55,0x63,0x7e,0x87,0xb4,0x46,0xac,0xf0,0x0f,0xb2, - 0x45,0x21,0xc7,0x88,0x78,0x91,0x71,0xb7,0x4f,0xfa,0x88,0xf8,0x0e,0xbc,0xcd,0x16, - 0x73,0xfd,0x75,0x26,0xc9,0x37,0x86,0x56,0x38,0xa0,0xec,0x68,0xcb,0x7c,0x50,0x0c, - 0x68,0xad,0x2c,0x7f,0x75,0xcb,0x83,0x68,0x2d,0x1e,0x40,0x33,0x0a,0x5f,0xf3,0x6d, - 0xf6,0x52,0xa8,0xd8,0xb0,0xaf,0xc9,0xfe,0x20,0x79,0x1e,0x11,0xff,0xec,0xe5,0x45, - 0xb3,0x87,0x49,0xb9,0xf4,0x24,0xcc,0xed,0x97,0x83,0xe4,0x0c,0xca,0xab,0xe2,0x1e, - 0x94,0x57,0x63,0x52,0x87,0xfd,0x3b,0xf8,0xbe,0xfe,0x5e,0x6d,0x62,0xbe,0x96,0xdb, - 0xca,0x9d,0x18,0x2c,0xc3,0x43,0x02,0xb9,0x0d,0xd3,0x55,0x43,0xae,0xc4,0x43,0x72, - 0xf8,0x3e,0x37,0x5f,0xc6,0x93,0xa8,0x7e,0xec,0x46,0x86,0xc7,0xff,0x9a,0x45,0x3f, - 0xee,0x46,0x7d,0xe4,0x35,0x66,0x0e,0x8b,0x9c,0x12,0x52,0x81,0xda,0xa1,0x71,0x00, - 0xae,0x86,0x7d,0x75,0x59,0xc3,0xe2,0x3b,0xec,0x03,0x7c,0x5f,0xd4,0xef,0xa7,0x92, - 0xf5,0xa6,0xa6,0x9b,0xd9,0x70,0x6d,0x8e,0x58,0xe3,0x60,0x04,0xe5,0x4f,0xad,0xa3, - 0x83,0xbb,0x7d,0x54,0x9f,0xc6,0x0b,0xaf,0xc1,0x4f,0x6a,0x79,0x69,0xc4,0x9a,0x41, - 0x29,0x89,0x7f,0x4c,0x7d,0xc7,0xeb,0x4b,0x8f,0xf0,0x40,0xd8,0x31,0xc7,0xf9,0x46, - 0x5e,0xd8,0x6d,0xa1,0x96,0x39,0x7c,0x63,0x25,0x9c,0xb2,0x55,0xf1,0xf8,0x57,0x7c, - 0x12,0xff,0xf4,0x20,0xfe,0x39,0x0c,0x6e,0xdd,0x16,0x23,0xaf,0x12,0x7d,0x03,0x1a, - 0x02,0x3a,0xf9,0x08,0xaf,0x2c,0x58,0xc3,0xf5,0x3b,0x69,0x31,0xe6,0x70,0x45,0x6f, - 0xc1,0x3f,0x92,0x99,0x1d,0xcf,0x2f,0xfe,0x11,0xb6,0x31,0x67,0xa3,0x1c,0x0d,0x7f, - 0x04,0x3f,0x83,0x39,0xa1,0x0c,0x4f,0xb6,0x5b,0x69,0x61,0x25,0x01,0x13,0xff,0x4c, - 0xc8,0x07,0x0a,0x76,0x6d,0xef,0x74,0xd3,0x08,0xed,0x43,0x30,0xda,0x09,0x37,0x02, - 0xcf,0x77,0x2e,0x2c,0xbc,0x2b,0x80,0x88,0x48,0x68,0x84,0x55,0x86,0xcb,0xeb,0x4f, - 0xd6,0x3f,0x84,0xbc,0xef,0xf0,0x6c,0x7d,0x66,0x8f,0x91,0x41,0xed,0xcc,0x97,0xbc, - 0x6d,0x78,0x3a,0x86,0xa4,0x8f,0x49,0x59,0xf0,0xee,0xcf,0x0a,0x2a,0x13,0xf5,0xd3, - 0x10,0xef,0x25,0xeb,0x1f,0x66,0x8e,0x49,0x57,0x55,0xd3,0x6c,0x3f,0x03,0x63,0x5e, - 0x14,0xcb,0x86,0x38,0x26,0x5d,0xd2,0x2a,0xef,0x9a,0xc7,0x11,0xd1,0x65,0xae,0xdf, - 0xf7,0x88,0x83,0x77,0x24,0xfd,0x3f,0x47,0xe0,0x0d,0x75,0xb1,0x6a,0x3f,0xca,0x03, - 0x2f,0x46,0xa9,0xea,0x38,0x9a,0x53,0x59,0x3b,0x96,0x7f,0xa3,0xdd,0xde,0x87,0x78, - 0xe9,0xf2,0x96,0x85,0x67,0x1d,0x29,0xfe,0x1f,0x6a,0xfa,0x7f,0x54,0xfa,0x2f,0xce, - 0x79,0xdc,0xda,0xd2,0xe5,0x46,0xff,0x62,0x56,0xee,0x71,0x2e,0xa5,0x11,0x12,0x37, - 0xd0,0x14,0xed,0xcb,0xe8,0x26,0xc3,0x93,0xf9,0x5f,0x54,0x3a,0x09,0x7b,0x14,0xde, - 0xe4,0xc2,0x6b,0x0f,0x74,0xe6,0xbb,0x42,0x4b,0x94,0x70,0x26,0xdb,0x43,0xeb,0xf0, - 0x64,0xa7,0xf7,0xaa,0x07,0x61,0xd5,0x51,0x3c,0x68,0xe7,0x85,0x89,0xef,0x6b,0x08, - 0xbb,0xe1,0xa0,0xf6,0xc0,0x8a,0xce,0x6d,0x88,0xa6,0x3a,0x59,0x51,0xb5,0x1c,0xf1, - 0xba,0xe1,0x20,0x5b,0xa9,0xda,0xa2,0xe9,0xef,0x66,0x1c,0x4e,0x14,0xd6,0x1e,0x9e, - 0xc4,0x4b,0x30,0x63,0x08,0xde,0x8a,0x96,0xb8,0xec,0x54,0xb0,0x4b,0x71,0x76,0x08, - 0x1c,0x1b,0x38,0x51,0xb9,0xaf,0x62,0x7e,0x96,0x3e,0xed,0xf7,0xf0,0xfd,0xb6,0x32, - 0x1e,0x3f,0x35,0xac,0xf9,0x5f,0xc2,0x0f,0x79,0x58,0x90,0xa7,0x35,0xbd,0x03,0x7f, - 0xc5,0x70,0xdb,0x8c,0xd9,0x47,0x85,0xc5,0x70,0xf7,0x27,0x39,0x71,0x3a,0x46,0xaa, - 0x8e,0x73,0x7c,0x98,0x12,0xff,0xba,0xa4,0xf9,0x94,0xa5,0x6d,0xe2,0x10,0xeb,0x0b, - 0x96,0xb5,0xa2,0xa1,0xea,0x86,0x0f,0xc0,0x1b,0x75,0xe8,0xe2,0xfb,0xe4,0x18,0x1a, - 0x13,0x78,0xff,0x4f,0xac,0xfe,0x1f,0xe1,0x12,0x7e,0x63,0xfa,0x2f,0xfe,0xcb,0x70, - 0xa6,0xdf,0x19,0x73,0xfc,0x2b,0xa9,0xaa,0x45,0xfb,0x51,0x5d,0x12,0x4b,0xff,0xbd, - 0x11,0x56,0xdb,0x5f,0xe3,0xf1,0x3b,0x4b,0xff,0x0b,0xbb,0x14,0x63,0x6e,0x4a,0xd5, - 0xec,0x57,0x01,0x88,0xee,0xc1,0xfd,0x96,0x05,0xcf,0x40,0x61,0x64,0x49,0x3a,0xe9, - 0x53,0xf6,0x34,0xa8,0xc3,0x22,0xc7,0x3f,0x13,0xdf,0x17,0xf1,0x8f,0xd2,0x61,0x14, - 0x17,0xd2,0xbf,0x21,0xef,0x68,0xdb,0xa3,0xf9,0xfa,0x92,0x3b,0x71,0xfe,0x5a,0x36, - 0xfb,0x9b,0x72,0x80,0xbc,0x0e,0xcf,0xb6,0x9b,0x15,0x02,0x93,0xf9,0x5f,0x81,0x3c, - 0xc4,0xdb,0x9d,0x95,0x9a,0xfd,0xd6,0xc6,0x93,0xa1,0x1e,0xed,0x7b,0x9a,0x43,0x90, - 0xed,0x6a,0x1c,0x16,0xbc,0xe8,0xf0,0x90,0x57,0xb4,0xd1,0x98,0x27,0x81,0x7f,0x26, - 0xe6,0x6b,0x79,0xcf,0x21,0x48,0xae,0xd2,0xe6,0xfd,0x4a,0x7c,0x3b,0xf4,0x99,0xf4, - 0x88,0xff,0x54,0x4f,0xce,0x98,0x74,0x19,0x16,0xd5,0x3a,0x86,0xd9,0x05,0x78,0x45, - 0x59,0xd4,0xcb,0xeb,0xff,0x4c,0xe2,0x43,0x8a,0xeb,0x3f,0x2a,0xa0,0x10,0xee,0x96, - 0x4b,0xe0,0xa8,0x54,0xe6,0x77,0x0c,0x0b,0x6e,0x5c,0xd8,0xaa,0x6a,0x7b,0x13,0x8f, - 0x80,0x98,0xfe,0x6a,0xe1,0xa8,0x85,0xff,0xbc,0x1d,0xf5,0x75,0x3e,0x0b,0xd4,0x93, - 0x59,0x84,0xb3,0x7d,0xe4,0x7a,0xff,0x4d,0xda,0x5a,0x82,0x88,0xe8,0xcb,0x68,0x61, - 0xed,0x1b,0x8f,0x7f,0x4d,0xda,0x77,0x2a,0xc7,0x3f,0xac,0x20,0xe4,0x2a,0x27,0x59, - 0xc2,0xa3,0xec,0xc9,0xc1,0x96,0xbc,0xec,0xac,0x86,0x1f,0xb3,0xd5,0xc3,0xb4,0x0e, - 0x81,0xd0,0xb3,0x88,0x7f,0x96,0xac,0x49,0x4f,0xca,0xb7,0x3a,0x8e,0x7f,0x0c,0xd5, - 0x88,0x54,0x1e,0xb5,0x53,0x34,0xf3,0x8f,0xca,0x6d,0x7e,0x77,0x5a,0x83,0xf1,0x40, - 0x28,0xb0,0x00,0x81,0x41,0xb7,0x56,0xc2,0x19,0xf2,0x6f,0x26,0xf3,0xbf,0x72,0x3b, - 0xe1,0xca,0xb6,0xd2,0x76,0xfb,0x47,0x39,0x2e,0x38,0x15,0x29,0x63,0x0e,0xce,0xff, - 0x79,0x47,0xaf,0x8a,0xba,0x75,0x71,0x94,0x5d,0x99,0xee,0xd3,0x37,0x71,0xff,0xcf, - 0xc4,0xf3,0x07,0x78,0x3e,0x4e,0x22,0xe8,0x10,0x97,0x38,0xdb,0x19,0x6d,0xe4,0x38, - 0x8c,0xd8,0x7c,0x39,0x0e,0xd6,0x78,0xb6,0x70,0x84,0x67,0x08,0xa6,0xe6,0x7f,0xa1, - 0xbe,0x63,0xde,0x55,0xee,0xcd,0x39,0x03,0x74,0x34,0x5a,0x66,0xd6,0x7f,0xe6,0xb0, - 0x27,0x98,0xc8,0xef,0x16,0xbc,0xf5,0xad,0x53,0xf0,0x0f,0x3d,0xe8,0x54,0x43,0xb4, - 0x8d,0x0c,0x44,0x0f,0xf2,0x40,0xcc,0x16,0xdb,0x9c,0xf0,0x31,0x70,0x2e,0xcf,0x8b, - 0xf1,0xfa,0x3f,0x6a,0x51,0xf0,0xcf,0xfa,0x7f,0x5c,0x66,0x9a,0x3c,0xbc,0x6b,0xf2, - 0x7f,0x34,0x33,0xc3,0x6b,0x0b,0x19,0xd0,0x33,0x12,0xfe,0xa2,0x53,0x93,0xfa,0x8b, - 0xfb,0x7f,0xf6,0x24,0x92,0xdc,0x7b,0x11,0x08,0x85,0x34,0xd3,0x11,0xc4,0x13,0xc1, - 0x28,0x4f,0x0c,0x6f,0xd0,0x5c,0xf5,0x2e,0x85,0x1c,0x4f,0xe6,0x7f,0xdd,0x14,0x32, - 0xdd,0x3e,0x11,0x56,0x13,0x1f,0x77,0x04,0x99,0xf9,0x5f,0x5d,0xdc,0xcd,0x12,0x9f, - 0xcc,0x7f,0x9f,0xc4,0xcf,0xdd,0xdc,0xff,0xa3,0x2d,0xd6,0x96,0x9d,0xce,0x79,0x0f, - 0xa5,0x0d,0x5a,0xa3,0xa7,0xc5,0xf7,0xe0,0xc3,0x6a,0x5e,0xf6,0xa7,0xe6,0x32,0x6e, - 0xa4,0x2a,0xd3,0xff,0x23,0x58,0xf1,0xcf,0x65,0x17,0x4f,0xf2,0x6a,0xbc,0xe0,0xb9, - 0x0c,0x65,0x46,0xfa,0x69,0xf1,0x56,0x78,0xbf,0xba,0x74,0x39,0x8a,0xb5,0x0b,0xec, - 0xf2,0x1d,0xa5,0xda,0xb2,0x28,0x39,0x67,0xc1,0x3f,0x3a,0x74,0xfb,0x9d,0x10,0x69, - 0x22,0x67,0x81,0xd7,0xff,0xa1,0x3c,0x30,0xd7,0x57,0xeb,0x84,0x2c,0x46,0xce,0xea, - 0xdd,0x50,0x86,0x50,0xcd,0x7f,0x6a,0x52,0xfe,0x2c,0x95,0x10,0xff,0x40,0xa1,0x46, - 0xf3,0x48,0xaf,0x74,0x90,0xce,0xe1,0x61,0xbe,0x34,0xfb,0x8e,0x90,0x6b,0x39,0xbf, - 0x12,0x3c,0xa8,0xd6,0xf1,0xf8,0xd7,0x54,0xfc,0x83,0xe8,0x91,0x57,0x2b,0xdd,0x45, - 0x39,0x7a,0x5c,0x57,0x88,0x03,0xa2,0x7d,0x01,0xf1,0x24,0x3b,0xc8,0xe6,0x04,0xcc, - 0x78,0xe2,0xc4,0x7c,0x5d,0xea,0x50,0x3e,0x81,0x05,0x01,0x7b,0x1b,0x8f,0x66,0x1a, - 0x0b,0xea,0x1d,0xdb,0xc5,0x42,0xfa,0xbe,0xe1,0x7d,0xc8,0xbe,0xad,0x66,0x00,0x1e, - 0x84,0x45,0xa9,0xfc,0x1f,0x8e,0x7f,0x0e,0xf6,0x1c,0xaa,0xd9,0x14,0x75,0xae,0x82, - 0x51,0xd5,0x57,0x9b,0x95,0x2d,0xf6,0x42,0x8f,0x71,0xa4,0xde,0xbe,0xbd,0x31,0x11, - 0x11,0xdb,0x14,0x15,0xcf,0x4f,0xf1,0xff,0xf8,0x14,0x7b,0xb3,0x68,0xd6,0x7f,0x96, - 0xf8,0xfa,0x53,0xce,0x3f,0x77,0x33,0xf1,0x2c,0xf4,0xe5,0x99,0x88,0x34,0xb9,0x7f, - 0xa8,0xe4,0x82,0x23,0x81,0x79,0xba,0x2b,0xee,0xbc,0xa4,0xee,0xd7,0x9c,0x7b,0xe4, - 0x81,0xec,0xdb,0xc0,0x46,0xe6,0xed,0xa3,0x7a,0x41,0x37,0x6c,0x94,0x0a,0x10,0x11, - 0xf9,0x93,0xfe,0x1f,0xca,0xed,0xd3,0x80,0x9b,0x6b,0xff,0x57,0xd9,0x9e,0x38,0x9e, - 0x97,0x1b,0x9c,0x77,0xe4,0x37,0x42,0x49,0x90,0x56,0x92,0x97,0x72,0xdb,0x99,0xf4, - 0x5a,0x8b,0x35,0xfe,0xa5,0x0a,0x66,0x91,0xd2,0x30,0xd5,0xb2,0x4f,0x2b,0xfb,0xb5, - 0x7c,0x4d,0x5e,0x45,0xbe,0x44,0xd7,0xab,0xc5,0x7e,0xba,0x8a,0xfc,0x14,0x9e,0x12, - 0x9e,0xe4,0x8d,0x30,0xe2,0x93,0xf9,0x5f,0xae,0x3c,0xee,0xff,0x59,0xac,0xdb,0xeb, - 0x6a,0xde,0x81,0xcb,0x6c,0xc7,0x80,0xe3,0x8c,0xfc,0x08,0x79,0x99,0x55,0xe9,0xf6, - 0xe5,0xe2,0xe7,0xe4,0xe3,0xf0,0xad,0xf1,0x69,0x6b,0xc4,0x77,0x53,0xfc,0x3f,0x07, - 0x85,0x4a,0xf6,0x0f,0xbc,0xba,0xcb,0x15,0xf0,0x05,0x1c,0x71,0x7c,0xec,0x4b,0xf5, - 0x55,0x4c,0x6e,0x6a,0xec,0x86,0xb7,0x60,0xd1,0x2a,0xee,0xff,0x99,0x5c,0x1f,0x8e, - 0x7f,0xfe,0xc4,0x4a,0x75,0xfb,0xb1,0x9a,0xd7,0xe1,0xc5,0xf0,0xc2,0xb8,0xe3,0x8c, - 0xf0,0x39,0x9c,0xe8,0x2f,0x0d,0xd1,0x51,0xb1,0x0c,0x5e,0xe5,0xfc,0x9f,0x91,0x82, - 0xa4,0xbd,0x16,0x41,0x3c,0xb3,0x5f,0xbb,0x35,0xe2,0xfa,0x12,0x39,0x8d,0xd0,0x78, - 0x47,0xf4,0x84,0x46,0x86,0xc3,0xeb,0xd9,0xad,0x41,0xfa,0xa0,0x5f,0x51,0x9a,0xf3, - 0x6f,0x35,0x96,0xfd,0x80,0x24,0xeb,0x6f,0x9b,0xfe,0x1f,0x25,0x1f,0xf2,0xbe,0xe4, - 0xec,0xd7,0x1e,0xa5,0xb3,0x0d,0xc4,0x3f,0xa7,0xe9,0xfa,0xf2,0x7c,0xa0,0x9f,0x38, - 0xef,0x83,0xf5,0xb0,0xc2,0x90,0x1f,0x4a,0xef,0x9d,0xbc,0xbf,0xa6,0xb4,0x42,0x8c, - 0x14,0x92,0x80,0x40,0x8c,0xec,0x30,0x53,0x75,0x99,0x3b,0xe9,0x1a,0x9b,0x0a,0x63, - 0x75,0x0b,0xc8,0x9d,0x68,0x98,0x7c,0x53,0x43,0xf9,0x93,0x94,0x57,0x1c,0xff,0x5c, - 0x02,0x4f,0x8f,0x7d,0x57,0x41,0x1f,0x1c,0x63,0xfb,0xc3,0x8e,0xc7,0x71,0x23,0xbd, - 0x6a,0x78,0xef,0xb5,0xef,0x93,0xbf,0x41,0x8e,0x7b,0x4d,0xfe,0x8f,0x05,0xff,0x28, - 0xbc,0xc8,0xe1,0x21,0x1d,0x37,0xd5,0x59,0xb8,0xe8,0xf7,0x29,0xcb,0x3a,0xd0,0xfe, - 0x42,0xfc,0x13,0x44,0x7d,0xd4,0x69,0x5c,0x04,0xdc,0x51,0x31,0xfc,0x95,0xd5,0xff, - 0x73,0x25,0x5a,0xc5,0x8b,0xd8,0x8c,0x48,0xaf,0x70,0x7f,0x7e,0xbf,0x49,0xe3,0xf4, - 0x85,0x97,0xbd,0xdd,0xd8,0x0b,0xaf,0x26,0x2a,0x02,0x0d,0x26,0xeb,0x45,0x23,0xfe, - 0xe9,0x66,0xbe,0x7c,0xda,0x4a,0xe2,0xa4,0x39,0x52,0x02,0x2d,0x91,0xf0,0x1f,0x78, - 0xfd,0x19,0x75,0x49,0x84,0x9c,0x93,0x1a,0x79,0x7e,0x13,0x42,0x91,0x60,0xd2,0xff, - 0xb3,0x5a,0x39,0x08,0x25,0xba,0x6b,0x33,0x4a,0x83,0x66,0x56,0xb2,0x42,0xde,0x86, - 0xa7,0xf5,0xa7,0x50,0xc2,0x3d,0x24,0x7f,0x00,0x19,0x9c,0xef,0x72,0xfc,0x33,0xb9, - 0x1f,0xa8,0x66,0x87,0x98,0xe0,0x66,0x14,0x88,0x61,0x56,0x03,0x48,0xc4,0x07,0xa9, - 0x1b,0x96,0x50,0x62,0x10,0x6e,0x7f,0x51,0xaf,0xd5,0xff,0x93,0xb7,0xda,0x94,0xb7, - 0xad,0x26,0xda,0x37,0xe3,0x35,0x5f,0x8e,0xc3,0x6f,0xcc,0x41,0x41,0x1c,0x4e,0xd4, - 0x7a,0x99,0xbd,0xab,0x31,0x9e,0x6f,0xe1,0x3f,0xc3,0x98,0xed,0x36,0xd4,0xef,0x39, - 0x66,0xb6,0xbb,0xe0,0x30,0x6a,0x86,0x39,0xbf,0x05,0xcc,0xfa,0x3f,0x97,0xd5,0xe7, - 0x35,0xd3,0x75,0x36,0x89,0x1f,0x80,0xe0,0x2e,0x00,0x17,0x27,0x50,0xfe,0xc7,0x03, - 0xb0,0xfe,0x48,0x20,0x70,0xbb,0x4a,0xf9,0xcf,0x06,0xd6,0x9f,0x26,0xc0,0xcd,0xa2, - 0xa1,0x86,0xfd,0x4f,0x06,0xff,0x3b,0xf7,0x37,0x6b,0x08,0x8d,0x93,0xa9,0xff,0xa3, - 0x81,0xe5,0xe7,0x3f,0x9f,0x98,0x18,0xfc,0xef,0xdc,0xff,0x7f,0xf5,0xe7,0xbf,0xd8, - 0xfa,0x2b,0xbc,0x97,0xdf,0x49,0xf8,0x2e,0xcc,0x34,0xfe,0x93,0x81,0xf4,0xff,0xf8, - 0xfe,0xff,0x5f,0x5e,0x7f,0x49,0x61,0x7f,0xc1,0x9a,0x0b,0x93,0xf2,0xea,0x7f,0xf5, - 0xa7,0xb2,0xf2,0x2f,0x99,0xe5,0x70,0xfc,0x3f,0xbc,0xfd,0xff,0x0b,0x3f,0x55,0x57, - 0xaf,0x5e,0x35,0xfe,0x27,0x83,0xff,0x7f,0x9e,0xff,0x5f,0xec,0x3c,0xfe,0x1f,0x79, - 0xf8,0x7f,0xe4,0xe1,0xff,0xc6,0xfa,0xff,0x1f,0x79,0xf8,0x3f,0xfb,0xf9,0xaf,0x26, - 0x7f,0xfe,0x6b,0xcd,0xe7,0xfc,0x28,0x5e,0x44,0x54,0x1e,0x11,0x1f,0x86,0x63,0x0d, - 0x8b,0x4e,0x3a,0x46,0x6a,0xc6,0x82,0xaf,0xc2,0x7c,0xf5,0xe6,0xf3,0x8d,0xa5,0xf4, - 0x24,0x2c,0xee,0x70,0xfc,0x7a,0x0a,0x3f,0xea,0x10,0xe3,0xa4,0xaf,0xf0,0x55,0xed, - 0x8d,0xc2,0x82,0xde,0x96,0x6e,0xf2,0x36,0xfb,0xdd,0xb7,0x9c,0xaa,0x5c,0x4b,0x54, - 0x68,0x0e,0x94,0xdc,0x79,0xe2,0x31,0xf2,0x89,0x25,0x3f,0xba,0x35,0xf7,0x10,0xc4, - 0x0d,0xd9,0x4b,0x4e,0x2a,0xcd,0x54,0xed,0x93,0x3d,0xbc,0x5e,0x31,0x5a,0x7d,0x68, - 0x26,0x48,0x91,0xf0,0x02,0x77,0x86,0xe9,0x1f,0x4b,0xfa,0xeb,0x56,0x9b,0xf1,0x56, - 0x99,0xdb,0xa7,0x8f,0x37,0xb4,0xf3,0x36,0x2b,0x27,0xe1,0x46,0xc1,0xa9,0xb6,0xb8, - 0x6c,0x73,0x00,0x11,0x7b,0x9f,0xdc,0x69,0xe1,0x47,0x09,0x12,0xda,0x53,0xf8,0x3c, - 0x0e,0xde,0x0d,0xa4,0x47,0xaf,0x30,0xc4,0x6e,0xb3,0x7e,0x94,0xd7,0x25,0x77,0x8b, - 0x25,0xe4,0x18,0xf3,0x45,0x1d,0xcf,0x15,0xfc,0x2a,0x19,0x1f,0xe4,0xfe,0xd2,0x76, - 0x1e,0x04,0x9c,0xfe,0x36,0xe5,0xfd,0x41,0x5e,0x1d,0x2e,0x18,0x4b,0xbb,0xc4,0x3d, - 0x66,0xc3,0xa5,0x63,0xca,0xa8,0x54,0x15,0x72,0xe8,0x30,0x98,0x8c,0x0f,0x2a,0x66, - 0x7c,0x90,0x93,0x7c,0xc6,0xe0,0x18,0xda,0xef,0xd2,0xbe,0x44,0xdb,0x2f,0x78,0x34, - 0xde,0x38,0x07,0x2e,0xf9,0xbd,0x8a,0x3b,0x66,0xcd,0x8f,0x93,0xdc,0xbc,0xde,0x1a, - 0x0f,0x62,0x5e,0x81,0x66,0xad,0xc0,0x08,0x44,0xc9,0x58,0xfa,0x26,0x68,0x07,0xfa, - 0x0c,0xf9,0x79,0xe0,0xa0,0xee,0x34,0xe8,0xcf,0x53,0xfa,0x83,0x2c,0x35,0xfb,0xc5, - 0xc8,0x66,0xf5,0x42,0x58,0x65,0xdc,0x85,0x03,0xe1,0xb0,0xa4,0x86,0x02,0x1e,0xa7, - 0x4b,0x89,0x31,0xd5,0x08,0xe4,0x59,0x7a,0x16,0x73,0x7e,0xd4,0x7e,0xc6,0xab,0x41, - 0xfa,0xdf,0x51,0x9b,0x8c,0xb3,0x43,0xbc,0x3f,0x88,0x76,0x60,0x8b,0xb8,0x92,0xde, - 0x09,0x3f,0x09,0xee,0x43,0xa3,0x81,0x2e,0x0f,0x2f,0x98,0x9c,0x1f,0xa0,0x76,0xed, - 0x3c,0xf8,0x7a,0x96,0xcd,0x17,0x4f,0xa2,0xfd,0x95,0x3b,0x68,0x2f,0x15,0x97,0xc2, - 0xa7,0xa0,0xb8,0xdd,0xf3,0x6b,0x78,0x7d,0xa4,0x98,0x61,0x77,0xcb,0x37,0x4c,0xfa, - 0xe7,0xb5,0x9b,0x9e,0xbb,0x8f,0x07,0x49,0x33,0x87,0xc5,0xdf,0xaa,0x97,0xa6,0xfb, - 0x4e,0x67,0x7e,0x52,0x30,0x06,0xaf,0x0a,0x3e,0x96,0x75,0xb6,0x66,0xbc,0x90,0xe6, - 0x0b,0x62,0xff,0x64,0xfd,0x10,0x17,0xae,0xff,0x1b,0x2c,0x51,0xcd,0x9e,0xbd,0xc0, - 0xbc,0xef,0x65,0xe9,0xe2,0x87,0xea,0x89,0xba,0x0a,0xcd,0xf1,0x26,0x0f,0xd4,0x0a, - 0x9c,0x28,0x2e,0x92,0x64,0x7f,0x4c,0x85,0xdb,0xd7,0x89,0x68,0x02,0x5b,0x0b,0x05, - 0x46,0x66,0x88,0x5c,0x8e,0xfc,0xba,0x96,0x13,0xa5,0x1a,0xef,0x97,0x9a,0x48,0xb1, - 0xb1,0xc4,0x20,0xde,0x64,0xfe,0x2f,0xf0,0xb6,0x92,0x73,0xe3,0xf2,0x9a,0x95,0xa7, - 0xd8,0xa3,0x0d,0x3b,0x06,0xef,0x5c,0x9d,0xfe,0x0e,0x5d,0xcf,0xe6,0xaa,0x6f,0x05, - 0x9c,0xb3,0xd4,0xc7,0x4c,0xa2,0xf8,0x4a,0x6b,0x7d,0xa4,0x56,0xd8,0xab,0xe9,0xc6, - 0x12,0xbe,0x9e,0x5b,0x55,0xd5,0xc8,0x28,0xc1,0xfd,0xb3,0x95,0xa8,0xaa,0x9c,0x61, - 0x5b,0x0d,0x5b,0x39,0x3f,0xb3,0x95,0x64,0x5b,0xea,0x23,0x75,0xc2,0x3b,0xa1,0x6c, - 0x96,0xa9,0x3b,0x07,0xe1,0x14,0x78,0x99,0x3c,0x90,0xc3,0x1b,0x85,0x2c,0xd2,0x1d, - 0x03,0xf2,0x22,0xfc,0xc7,0x17,0x73,0x8f,0x59,0x45,0xb2,0xfe,0x00,0xe7,0x47,0x51, - 0x9f,0xb0,0x89,0x87,0x05,0x39,0x5f,0x7a,0x1e,0x2f,0x0b,0x39,0x0c,0x3e,0x69,0x5a, - 0xb8,0x26,0x5e,0x31,0x48,0x7d,0xb0,0xa9,0xa9,0xd1,0xd2,0x1f,0x4d,0x19,0xa0,0x89, - 0x6a,0x90,0x69,0x03,0xda,0x9d,0xac,0x2c,0xe4,0xe0,0x8d,0xd2,0x8e,0x41,0x76,0x3d, - 0x8f,0x7f,0x41,0x73,0xbb,0x4f,0xb3,0xb7,0x59,0xeb,0x23,0xd5,0xae,0x1a,0x27,0x75, - 0xa7,0x9f,0x83,0xe6,0x7e,0x34,0x33,0x95,0x82,0x42,0xda,0x2c,0x54,0x86,0x6c,0xdb, - 0x79,0xbc,0xaf,0x87,0x57,0x00,0x90,0x93,0xab,0x93,0xe8,0x8f,0x56,0xa2,0xd5,0x44, - 0x9d,0x03,0x42,0x33,0x9d,0x13,0xe0,0x8d,0xd2,0xa4,0x66,0xa1,0x48,0x0b,0xb4,0xe1, - 0x95,0x5d,0xb4,0x24,0xb5,0x3e,0x36,0x98,0xfe,0x31,0x37,0x2f,0x8b,0xdd,0x4b,0xf2, - 0x6b,0xdc,0x5f,0xaa,0x89,0x66,0xa7,0x49,0x0d,0xfe,0x22,0xcd,0x96,0x4b,0x5e,0x94, - 0x1a,0xb4,0x92,0xa0,0x2b,0xf7,0x5e,0xff,0xa4,0x7d,0xba,0x86,0xaa,0xe3,0xf1,0x29, - 0x32,0x38,0x7d,0x9c,0x96,0xac,0x92,0x3e,0x52,0x04,0xad,0x90,0x13,0x27,0x75,0xb8, - 0x02,0x4b,0x99,0x58,0x32,0x19,0x1f,0xe4,0xfc,0xa8,0xcf,0x24,0x5f,0xb5,0x23,0x9a, - 0xa0,0x85,0x07,0x37,0xf5,0xcb,0x4f,0x4e,0x34,0x4a,0x3b,0x2d,0x5d,0x4e,0x0c,0x7e, - 0x91,0xc2,0x8f,0xe2,0xfc,0xb1,0xcc,0xb6,0x69,0x17,0xd8,0x2b,0x5a,0x55,0xad,0x23, - 0x9a,0xf3,0x1e,0xdb,0x55,0xf8,0x5d,0xcd,0xb1,0xb9,0x71,0x9f,0x76,0xd9,0xe3,0xd5, - 0xec,0xaf,0x8b,0x25,0x93,0xe7,0xb1,0x5c,0x89,0xd3,0x6e,0x70,0xa2,0xe1,0x9d,0x7d, - 0x96,0x46,0x20,0x2b,0x77,0x09,0x23,0x3d,0x91,0x48,0x9d,0x17,0x64,0xb6,0x24,0x4e, - 0x07,0x1f,0x72,0xda,0x32,0x3b,0xfc,0xe9,0xc9,0xf8,0xa0,0xc9,0x8f,0x2a,0xd4,0xc4, - 0x6c,0xd2,0xa4,0x35,0x14,0xba,0xfb,0x6e,0x50,0xd2,0x5f,0x84,0x06,0xa5,0x50,0x93, - 0xb3,0x89,0x9d,0xed,0x95,0xd0,0x1e,0xcf,0x21,0xd9,0xc2,0xc4,0xfa,0x6f,0x9b,0xd1, - 0x01,0x07,0x05,0xce,0x4f,0x23,0x03,0xb6,0xc7,0x55,0x93,0x5d,0x8f,0xcb,0x2e,0x98, - 0xfc,0x70,0xde,0x31,0x4d,0xd7,0xf2,0xb7,0x64,0xa7,0x27,0xeb,0x23,0x71,0x7e,0x54, - 0xfc,0xc7,0xdc,0x09,0xd6,0x0b,0xc7,0x22,0x66,0xf4,0x73,0xc0,0xf6,0x3e,0x7c,0xfe, - 0x2d,0x47,0x74,0x43,0xa1,0x36,0xba,0xc0,0xbb,0x82,0x46,0xe5,0x64,0x7f,0xb4,0x0f, - 0x84,0x42,0xb3,0x5f,0x1e,0xcf,0x0e,0x50,0xdf,0x4f,0xa4,0xc5,0xf5,0xc2,0x1b,0x50, - 0x51,0xeb,0xb8,0x6d,0xeb,0x39,0xba,0x83,0xf1,0x8e,0x2a,0xe2,0xc5,0xc9,0x7a,0x83, - 0x66,0x7c,0x50,0xe3,0x6d,0x68,0x40,0x55,0x46,0x24,0x2f,0xd8,0x78,0x61,0x8a,0x7e, - 0x52,0xa6,0x64,0x31,0x99,0x57,0x68,0xef,0xe2,0x1e,0x5a,0x4b,0x7d,0xc8,0xb5,0x2e, - 0x5e,0x0d,0x92,0xb3,0xc1,0x2b,0xa2,0x47,0x84,0x22,0xb6,0x31,0xd1,0x16,0xd6,0xd9, - 0x49,0x3b,0x48,0x39,0x3d,0xa2,0x39,0x99,0x1c,0x27,0x49,0x84,0xe2,0x92,0xc6,0x9b, - 0xe6,0x78,0xd2,0x97,0x99,0x65,0x34,0xfe,0x96,0x97,0xa9,0xd9,0x0a,0xab,0x42,0x37, - 0x94,0xa7,0xd3,0xe9,0x5d,0x6a,0xc8,0x90,0x23,0x84,0x24,0xeb,0x43,0xc2,0x4c,0x6a, - 0x92,0xa2,0xd7,0xa4,0xcf,0x04,0x1f,0xdb,0x65,0x6c,0xe0,0x07,0xb9,0xd1,0xfb,0xf5, - 0x50,0xf3,0xf7,0xc8,0x4c,0xd8,0x47,0xf2,0xfb,0x64,0x89,0xd0,0x24,0xff,0x2a,0xc2, - 0x9b,0xf8,0x2c,0x8e,0x3b,0xbe,0x2f,0x5e,0x07,0x9f,0x35,0xcd,0x0f,0x65,0xad,0x29, - 0x78,0x42,0xfb,0xcd,0x33,0x0b,0x57,0x64,0x95,0xcb,0x37,0xa0,0xea,0x99,0x3f,0x36, - 0xad,0x4e,0x4e,0xf6,0x37,0xb1,0xcd,0x4c,0xc8,0x5b,0xc7,0x1e,0x79,0x08,0x8f,0xd5, - 0x9c,0xea,0x44,0xff,0x53,0xa1,0xc2,0xc8,0x6a,0x42,0xc1,0xcb,0x25,0xf6,0x32,0xfd, - 0x8b,0x49,0x7e,0x94,0xff,0x47,0x1f,0xc1,0xd5,0xa6,0xaa,0x78,0xd6,0xc8,0xb4,0x0f, - 0xa4,0xab,0xe1,0xaa,0x90,0x7d,0xa4,0xe6,0x8a,0xfa,0x31,0xdb,0x33,0x64,0x7f,0xae, - 0xc6,0x97,0xf0,0x8f,0xf5,0x95,0x9e,0x49,0xf6,0xa7,0xbb,0xfe,0x09,0xe3,0x40,0x6c, - 0x9e,0x41,0x3f,0x21,0xd9,0xec,0x5c,0xcc,0xbd,0x6a,0x6e,0x7d,0xf8,0x6d,0x58,0x0f, - 0xea,0x60,0x66,0x80,0xe4,0x6a,0xff,0xae,0xe4,0x1b,0x8e,0xec,0xec,0xa4,0x7f,0x8c, - 0xc7,0x07,0x0f,0x68,0x26,0x69,0xb3,0x6d,0xdb,0xb3,0xaa,0xdb,0x68,0xe6,0xfd,0x64, - 0x9f,0x86,0xfc,0xa5,0x77,0x1a,0xe4,0x61,0xf8,0x11,0xe4,0x1f,0x95,0x43,0x24,0x19, - 0x1f,0x0c,0x49,0x27,0x4d,0xf9,0x1f,0x40,0xed,0x26,0xe9,0xcc,0x6d,0xdc,0xe8,0x21, - 0x43,0x42,0x23,0x84,0x7a,0x33,0xb2,0xc8,0x37,0xe1,0x71,0x70,0xc6,0xe5,0xdc,0xec, - 0xfe,0xa4,0x7f,0x0c,0xe5,0xe7,0xa7,0x28,0x54,0xd3,0x87,0x79,0xf7,0x93,0x5f,0xf9, - 0x8c,0x48,0x37,0x2a,0x9a,0x7f,0x03,0x67,0xc8,0x1e,0xfb,0xd9,0x4a,0xf6,0xa6,0x81, - 0xaa,0x79,0xb7,0xc5,0x3f,0xc6,0xb8,0x3e,0x62,0x26,0x49,0xfe,0x24,0x7c,0xa0,0xf8, - 0x12,0x65,0xe8,0x2e,0xf1,0x8c,0xcb,0x01,0x71,0xb7,0x34,0xe2,0xf1,0xf5,0x65,0xed, - 0xb0,0xf8,0xbb,0x12,0xf1,0xc1,0x52,0x2e,0xcf,0x87,0xe1,0x77,0x50,0xa0,0xc9,0x9c, - 0x06,0xf3,0x1b,0xb2,0x50,0x73,0x7c,0x4b,0xf6,0x68,0xc7,0x4c,0xff,0x58,0xe3,0xc0, - 0x24,0x3f,0xbc,0xc7,0x8c,0xf7,0x99,0xf9,0x6e,0x75,0x4a,0xbb,0xd1,0xae,0xc9,0x31, - 0x71,0xb7,0xd2,0x22,0x14,0xf5,0xca,0x8c,0xb8,0x95,0x66,0xce,0xcf,0xe9,0x9e,0xc2, - 0x8f,0x1a,0x0f,0x5a,0x75,0xc2,0x86,0xbc,0x6f,0xe3,0x7c,0xb2,0x1b,0x5a,0xa0,0x08, - 0x07,0xe1,0x0e,0x5e,0x31,0xc9,0xcc,0x8f,0x9b,0xac,0x8f,0xc1,0xf9,0x51,0x87,0x13, - 0xa4,0x20,0xbf,0xd2,0x1e,0x72,0x71,0x6f,0x21,0xaf,0xc7,0xee,0xaa,0x96,0x9d,0x5b, - 0x9a,0x78,0x6a,0x8c,0x01,0xd3,0xad,0xf1,0xc1,0xcc,0xd5,0xec,0x12,0xde,0x1f,0x9f, - 0x5f,0x8f,0x9e,0x50,0x2b,0x8e,0xe3,0x8b,0x6f,0x87,0x97,0xa1,0xcc,0xbf,0xa9,0x5d, - 0xec,0x90,0x8e,0xc1,0x5e,0xbe,0x02,0xf1,0xf4,0xc9,0xf8,0xe0,0x4d,0x97,0xe1,0x92, - 0x92,0xc8,0x8f,0xd3,0x2e,0x6a,0x65,0x47,0x1d,0xc3,0x05,0xcf,0xa5,0x5d,0x85,0x47, - 0x8e,0xdf,0xac,0x89,0xf7,0x99,0xf1,0xc1,0x79,0xaf,0x59,0xe2,0x83,0x3d,0x69,0x1c, - 0xff,0x2c,0xcc,0x72,0x1c,0xcd,0x79,0x4d,0x79,0x35,0x5a,0x65,0xb3,0xbf,0xe4,0xf4, - 0xc0,0x49,0x86,0x83,0x37,0xc4,0x7a,0xf6,0xbb,0x68,0x69,0xfc,0xe6,0xee,0x2f,0xc7, - 0x26,0xf9,0x0c,0x47,0xe9,0x47,0xbc,0xe9,0x49,0x9e,0xfc,0x28,0x89,0x43,0x8b,0x5a, - 0x92,0xc7,0x53,0xba,0xd5,0x16,0x56,0x92,0x67,0xef,0xc2,0xbd,0xff,0x33,0xd5,0x17, - 0x47,0xe0,0x11,0x9b,0x5c,0xff,0x3e,0x94,0x93,0x7b,0x55,0x17,0xc8,0xea,0x75,0x11, - 0x68,0x24,0x6e,0x42,0xd1,0x94,0x30,0x98,0xe0,0xf6,0xf7,0x45,0x89,0x56,0xb0,0x15, - 0xdf,0xd7,0x66,0xe5,0x47,0xc5,0x81,0xf3,0xa3,0x8a,0x76,0xe2,0xf9,0xfd,0x80,0xbb, - 0x25,0xe3,0x79,0xdb,0xfc,0x73,0xf0,0x1f,0x7a,0x60,0x47,0xc6,0x1e,0x52,0x24,0x8c, - 0x67,0x70,0x24,0xf9,0x51,0xf9,0x66,0x35,0xe6,0x0a,0xd5,0xd1,0x34,0x6d,0x27,0x9c, - 0x60,0x3e,0x97,0x7d,0x43,0x81,0x93,0xfb,0xcf,0x3d,0xad,0x79,0xe2,0x37,0xd9,0x5b, - 0x09,0xfe,0x52,0x92,0x1f,0xa5,0x4f,0xe7,0xfb,0xe1,0x00,0x98,0x45,0x00,0xae,0x4e, - 0x5f,0x2c,0xcc,0x1b,0x96,0xfb,0xc9,0x65,0xe1,0x61,0xed,0x81,0x61,0x71,0xb2,0xa2, - 0x78,0x12,0xff,0x9c,0x36,0xf1,0x8f,0x57,0xca,0x6a,0x9a,0xb6,0x92,0x67,0x67,0x68, - 0x76,0xb6,0xfe,0x43,0x36,0x12,0x7a,0x64,0x79,0xd6,0x16,0x31,0x0e,0x89,0xfb,0xd7, - 0xa4,0xf2,0xc3,0x0f,0x4b,0xce,0xb8,0xf8,0x64,0xce,0x07,0xda,0x09,0x28,0xa9,0x7d, - 0x3b,0x4a,0xfe,0x1e,0x25,0xf0,0x3f,0xd6,0xd3,0x7d,0xe1,0x38,0x67,0x58,0xe1,0xf3, - 0x8b,0xfb,0x53,0xe2,0x83,0x87,0x01,0x9a,0x37,0x48,0x89,0xb6,0x20,0xc6,0xcf,0x78, - 0x7f,0xb4,0x98,0xb6,0xba,0xe9,0xf1,0x5c,0xf2,0x7e,0xc3,0x78,0xa2,0x4a,0x92,0x1f, - 0x35,0xac,0xcc,0x12,0x0e,0xb0,0x7c,0x5d,0x0e,0x90,0x43,0xb0,0x5e,0xff,0xce,0x53, - 0xb6,0x1f,0x84,0x5f,0xd3,0xf6,0xb3,0x15,0x85,0x19,0xcb,0xc9,0x3b,0xe5,0x8f,0xb1, - 0xd9,0x3c,0x3f,0xee,0xca,0xe4,0xfc,0xba,0x3c,0xdc,0x6f,0xe0,0xa1,0x59,0x2a,0xb1, - 0x87,0x3f,0x55,0x7c,0x9a,0xcc,0x69,0x78,0xc3,0xcc,0xcd,0x8a,0xe7,0xa3,0xfe,0x3d, - 0xa1,0x7a,0xcc,0xfc,0xb8,0xc9,0xf9,0x5a,0x2e,0xae,0x8f,0xf2,0x3c,0x2f,0x02,0x80, - 0x68,0xc7,0xe3,0x33,0xee,0x7e,0xad,0xe6,0x7b,0x70,0x51,0xfb,0x2b,0xb6,0x61,0x78, - 0xbc,0x50,0x24,0x5f,0xcf,0xc9,0xf5,0xe1,0xe7,0xf7,0x12,0x3c,0xd4,0x90,0xb9,0x4e, - 0x1c,0x92,0x96,0x84,0x4b,0x55,0x77,0x5f,0x8e,0x87,0x9e,0x80,0x45,0xd5,0x10,0x15, - 0x2f,0x48,0x66,0xfe,0x42,0xb9,0xe8,0x9f,0x5c,0xff,0x93,0x74,0x3b,0x2f,0xcb,0xcf, - 0x96,0xd4,0x6f,0xdd,0x8e,0x62,0x07,0xcd,0xc5,0xe1,0x6c,0x85,0xae,0x0f,0x2d,0xe2, - 0xfc,0xf0,0xd3,0xe3,0xd0,0xc8,0xe6,0x4d,0xe5,0x47,0xb1,0x7c,0xf5,0xce,0xe5,0xe4, - 0x77,0xf0,0xaf,0x4c,0x5d,0x49,0x03,0x24,0x4b,0x45,0xfc,0x13,0xa2,0x6b,0xfc,0xbf, - 0xe1,0xbf,0xe2,0xf1,0xd0,0x24,0x3f,0x6a,0xa9,0xd4,0xca,0xcf,0xe3,0xaf,0x6f,0xac, - 0xc8,0x3e,0xb5,0x61,0x73,0x9b,0x5a,0x4f,0x73,0xfd,0xb3,0x11,0x6f,0x17,0xd5,0xbb, - 0x3c,0xa4,0x57,0x2d,0x4d,0xac,0xe7,0x54,0x7e,0x54,0x01,0x7b,0xf4,0x19,0x71,0x14, - 0xde,0x84,0xbd,0x31,0xfb,0x39,0xf9,0x36,0x13,0xff,0xd8,0xf5,0x9c,0x51,0x7a,0xd1, - 0xec,0x98,0x56,0x70,0x31,0x85,0x1f,0xd5,0x4d,0x8e,0x28,0x08,0x03,0x76,0xc0,0x20, - 0xf1,0xe5,0x39,0xc2,0x62,0x3c,0x3c,0xd2,0xe3,0x4b,0x77,0xf0,0x78,0x4d,0x22,0x5f, - 0x4c,0xc8,0x4e,0xc6,0x6b,0x94,0x0e,0x18,0x4d,0x2b,0x5b,0x81,0x87,0xf4,0x5c,0xd3, - 0x31,0x98,0x15,0xba,0x39,0x2a,0x9e,0x63,0xc7,0xa2,0xde,0x5a,0x3b,0x6f,0x24,0xf1, - 0x06,0x1c,0x4a,0xe4,0xc7,0x4d,0xcc,0x67,0xd2,0x2a,0x7a,0x10,0x9c,0x4b,0x69,0x34, - 0xfb,0xe5,0x70,0x33,0x31,0xfd,0xed,0x7f,0x80,0xc6,0xb8,0x73,0x25,0xdd,0xec,0x7c, - 0x8f,0x8d,0x22,0xb0,0x91,0xad,0xfc,0xa8,0x72,0x1e,0x1f,0x84,0x74,0x8d,0xc6,0xc2, - 0x66,0x1b,0x8b,0x3b,0xe4,0xcd,0x66,0x3d,0xdb,0x39,0x3d,0x08,0x7b,0x7a,0x85,0xcd, - 0x50,0x94,0x9a,0x1f,0xa7,0x9a,0xfc,0x28,0x95,0x57,0x43,0x7a,0x51,0xe0,0xdd,0xd0, - 0xe4,0x05,0xe4,0x15,0xfc,0xc3,0x50,0x90,0x2e,0x40,0xfc,0x63,0x52,0xa7,0x94,0xeb, - 0x92,0xfe,0xf9,0x35,0x3c,0x3e,0x88,0x78,0x7d,0xe9,0xb8,0x7f,0x5e,0x90,0x71,0x60, - 0xd2,0xa2,0xdc,0x7c,0xd0,0x0f,0x15,0xbc,0x63,0x88,0x85,0x1f,0x65,0xd6,0x0b,0xaa, - 0xe2,0x4d,0x60,0x4f,0x23,0x10,0x32,0xab,0x61,0xff,0x77,0x44,0x80,0x87,0x83,0x8e, - 0x7e,0xb3,0x50,0xb6,0x19,0x21,0xfd,0x68,0x12,0xff,0x94,0x9b,0xf3,0x17,0x2e,0xb5, - 0xf7,0x4f,0xbb,0x00,0xc7,0x94,0xaa,0x40,0xd6,0xeb,0x8d,0xcf,0x32,0xbc,0xc3,0x72, - 0xc7,0xaf,0x44,0x44,0x44,0xd5,0x38,0xbf,0x7f,0xda,0x47,0xa9,0xf1,0x41,0xa7,0x6a, - 0xcf,0x6c,0x4a,0x8f,0xab,0x11,0x28,0xb1,0x89,0x61,0xdc,0x32,0xdd,0x50,0x92,0x2b, - 0x87,0x9d,0x83,0x3a,0x53,0x8b,0x38,0x03,0x33,0xc9,0x8f,0x0a,0xf0,0xf8,0xa0,0xcb, - 0xdd,0x67,0xcb,0x4d,0xe7,0xd9,0xa6,0xee,0xa5,0x37,0x66,0x83,0xc4,0x36,0x4b,0xee, - 0x80,0xcc,0xe3,0xa1,0x3b,0xd4,0xc2,0xd4,0xf8,0xe0,0xb6,0x04,0x3f,0xea,0xec,0xf5, - 0x6d,0xe9,0x43,0x8c,0xf3,0xa3,0x96,0x6c,0x0e,0x17,0x73,0x84,0xe9,0x97,0xf7,0x20, - 0x10,0xda,0x65,0xae,0x67,0xb6,0xa5,0x3e,0x64,0xa2,0xde,0x75,0x20,0x6b,0xbb,0xff, - 0xbd,0x05,0xc7,0x9a,0x7c,0x7f,0xb3,0x2c,0x2a,0x3e,0xc5,0xaf,0xd4,0x3b,0xa2,0xc2, - 0x39,0xf2,0xbe,0xf9,0xbe,0x16,0x7e,0x54,0x1f,0xdf,0x0f,0xa4,0x52,0x73,0x6c,0x11, - 0xcf,0x91,0x51,0xd5,0xf7,0x90,0x23,0xaf,0x85,0xd7,0x47,0x32,0x0b,0x25,0xf5,0xde, - 0xfb,0x06,0x4c,0xe1,0x47,0x51,0x33,0x3e,0x58,0xa6,0xda,0xd7,0x89,0x7a,0xfd,0x88, - 0x59,0x96,0xaa,0x20,0x9f,0x37,0x0a,0x99,0xb9,0x11,0x81,0xa8,0x7a,0x46,0xf1,0xa6, - 0xe6,0xc7,0xf1,0xf8,0xe0,0x21,0xdc,0xcf,0x75,0xef,0xe6,0x1c,0xa4,0x3f,0x21,0xf3, - 0xf4,0xce,0x21,0x7f,0x45,0xf9,0x86,0xf0,0x2d,0xbc,0x51,0xec,0x6d,0xec,0x19,0xc9, - 0x4c,0x94,0xf3,0x4f,0xee,0x1f,0x2a,0x2d,0xc5,0xf3,0x52,0x68,0x64,0xb8,0xc9,0x33, - 0xc2,0x5e,0xde,0x36,0x25,0xcf,0x96,0x06,0x8d,0x51,0x1c,0xcc,0xb2,0x6d,0x24,0x3f, - 0x6d,0x32,0xcf,0xcb,0xd1,0x49,0xfc,0x03,0xca,0xfd,0x70,0x40,0xe5,0xdd,0xc1,0xfc, - 0xdb,0x84,0xc7,0xd4,0xe2,0x98,0x4d,0x8d,0xfd,0x18,0xd2,0x61,0x76,0x9c,0xae,0x09, - 0x6f,0xa7,0x4f,0x13,0x01,0xcf,0x6f,0x7a,0x20,0x19,0x1f,0xdf,0xf6,0x35,0xb8,0xaa, - 0xdf,0x1a,0xca,0x5c,0x23,0x3e,0x21,0xfd,0xa9,0xa3,0x2a,0x34,0x73,0xb9,0x50,0x46, - 0x5e,0x8e,0xfe,0x30,0xe4,0x3e,0x23,0x1e,0x21,0xbf,0x61,0x9b,0xe3,0xcb,0xd6,0x4c, - 0x4b,0xf2,0xa3,0x6c,0x33,0x76,0xd3,0x4b,0xb9,0x3e,0xde,0xed,0x8b,0x57,0x03,0xa8, - 0x02,0x7b,0x5c,0x44,0xf9,0x93,0x3f,0x4d,0x13,0x87,0x79,0xbf,0x4b,0x6d,0x56,0x6a, - 0x7e,0x5c,0x28,0xf7,0x08,0xbc,0xc5,0x16,0x22,0xbe,0x12,0x2a,0xa4,0x57,0x37,0x54, - 0x85,0xb2,0xce,0x7c,0xb9,0x42,0x79,0xa5,0xad,0x2a,0xdf,0x71,0x46,0xf4,0xc1,0x7b, - 0xbf,0x2a,0x3d,0xbb,0xc9,0xca,0x8f,0x7a,0x06,0xf1,0xcc,0xf3,0x2c,0x3f,0xed,0x9e, - 0xff,0x2e,0xae,0xd1,0xd6,0x4f,0x2f,0x8e,0x80,0x41,0xf2,0x24,0x96,0x57,0xbc,0x41, - 0xfe,0x55,0x38,0x57,0xfd,0x8c,0xf1,0xd6,0x27,0x53,0xe3,0x83,0xb0,0x83,0xc9,0x0f, - 0xde,0xa1,0xa8,0x4f,0xd3,0xe2,0x6a,0xe1,0x4b,0x08,0x1e,0xd7,0x4b,0xc5,0x90,0x11, - 0x24,0xcb,0xb5,0xb5,0xea,0x6c,0x6e,0xca,0xf5,0x4e,0xce,0xd7,0x72,0x5b,0x85,0xc3, - 0xa0,0xd2,0x1b,0x6e,0xbd,0x6e,0x25,0x6b,0x69,0x28,0x61,0x19,0xc5,0xc4,0xb5,0xaa, - 0x5d,0x73,0x8f,0xc8,0xba,0x33,0x04,0x7b,0x84,0x42,0xe3,0x84,0x87,0xbc,0xd6,0x34, - 0x31,0xdf,0x35,0x7d,0x88,0xf3,0xa3,0xba,0x6e,0xee,0x16,0xbf,0x40,0x3e,0x66,0xbe, - 0x3a,0x47,0x9b,0x3c,0x87,0xb4,0x30,0x5f,0xc8,0x11,0x91,0x1f,0x90,0xfe,0x48,0x38, - 0xff,0x84,0x9c,0x62,0x13,0xef,0xab,0x0b,0x5c,0xde,0x56,0x44,0x1d,0x1e,0xf1,0x7d, - 0x0e,0x14,0xb7,0x64,0xb5,0xa3,0x18,0x7f,0x2b,0xe0,0xeb,0xe7,0x65,0xb1,0xd5,0x4b, - 0x60,0xf2,0xc3,0x93,0xfc,0xa8,0x7c,0x13,0xff,0x2c,0x42,0xeb,0xbe,0xf1,0x61,0xed, - 0x55,0xce,0xc6,0x0c,0x4e,0x2b,0x84,0x93,0x50,0xac,0xd9,0x0d,0x71,0x31,0x7c,0xac, - 0x6c,0x45,0x7d,0x47,0xf4,0xc9,0xfe,0xb0,0x3b,0x4c,0x7e,0x94,0x53,0x71,0x3c,0xe7, - 0xdc,0x85,0xda,0xcd,0xa7,0x46,0xb6,0x87,0x0b,0xa0,0x2f,0x34,0x47,0xa5,0x11,0x27, - 0x6f,0x73,0xc1,0xf5,0x57,0xba,0x05,0xff,0x08,0x7c,0x7e,0x51,0x2d,0x8a,0x29,0x0e, - 0x7b,0x9c,0x2b,0xf3,0xb6,0x91,0x67,0xe0,0x71,0x56,0xe2,0x41,0xeb,0x64,0xb7,0xba, - 0x13,0x38,0xc3,0x33,0x5b,0x4f,0xf2,0xa3,0x14,0xc4,0xdb,0x6a,0x08,0x6c,0x0a,0x1a, - 0x51,0x5b,0x79,0x5b,0x22,0xb0,0x35,0xc1,0x66,0xa5,0x90,0xfb,0xf5,0x22,0xa4,0x91, - 0xee,0xee,0xa9,0xc1,0xfd,0xd6,0x30,0xb1,0xfa,0x24,0x0f,0x3f,0xba,0xab,0x02,0xe4, - 0xa8,0xd8,0xa1,0x9c,0x30,0xd9,0x08,0x44,0x37,0xeb,0xb3,0xb9,0xa2,0x62,0x44,0xfa, - 0x98,0xd7,0x47,0xda,0x27,0xea,0x4f,0x4d,0xc6,0x07,0x37,0x27,0x68,0xe1,0x8e,0xfe, - 0x9a,0x6e,0x9e,0xdf,0xc4,0xf3,0xdd,0xea,0x51,0x22,0xce,0xe3,0x83,0x87,0x71,0xc5, - 0x16,0x1a,0x8e,0xf3,0x2f,0x0c,0x5a,0xfa,0xa3,0x7d,0x64,0xe2,0x43,0xf7,0x88,0x78, - 0x8e,0x5e,0xf5,0x54,0x49,0xf6,0x41,0xf1,0x3c,0x8c,0xa9,0xa5,0x9c,0xff,0xfc,0x27, - 0x78,0x05,0x4a,0x29,0x5e,0xb1,0xf4,0x87,0xdd,0xf6,0x11,0x7d,0x3e,0xe4,0x24,0xb4, - 0x0b,0x24,0xb6,0xc9,0x53,0xc2,0x68,0xa7,0xf3,0x5d,0xe5,0x70,0x7f,0xd5,0x19,0x3a, - 0xac,0x0d,0x40,0xcb,0x51,0xa7,0x87,0x76,0x5a,0xf2,0xe3,0xfa,0xe0,0xa4,0xb4,0xf7, - 0x4e,0x67,0x5f,0xa7,0xe7,0xa5,0x42,0x7d,0x27,0xb8,0xa9,0x8d,0x77,0x97,0x3c,0x24, - 0xa9,0x47,0xe7,0x7a,0x9c,0xbd,0xac,0x51,0x53,0xa5,0x80,0xea,0x3c,0x3a,0xb9,0x7f, - 0x12,0xfc,0x70,0xe7,0x69,0x1a,0x5b,0xd9,0xc1,0xf3,0x0d,0xd9,0x86,0xa7,0xc8,0xa0, - 0x72,0x38,0xe1,0x51,0x19,0xe0,0x78,0xf2,0x38,0xe5,0xfd,0x61,0x27,0xde,0xb7,0x7a, - 0xfa,0x10,0xfd,0x84,0x75,0xf5,0xdb,0x63,0x59,0xb3,0xe1,0x67,0x60,0x1e,0x9c,0x77, - 0xd3,0x2e,0x1a,0xde,0x9e,0xd6,0x98,0xf8,0x9e,0xff,0x18,0xf3,0x80,0x5b,0x17,0xfb, - 0x6b,0x2d,0xfc,0x28,0x18,0xdd,0xe6,0xe3,0x24,0xf9,0xca,0xd6,0x8f,0xc1,0x37,0x9c, - 0x39,0xd2,0x38,0xfc,0x8d,0xab,0xca,0x34,0xe3,0xe6,0xf1,0x42,0x01,0x3a,0x42,0xa3, - 0x54,0x7e,0xd4,0x28,0x2f,0xfb,0x13,0x13,0x57,0xe0,0x7e,0xa8,0x0c,0xda,0xf7,0xe5, - 0x0c,0xd5,0x5e,0x14,0xbc,0xc6,0xb4,0xd8,0xd7,0x0b,0xb5,0x13,0xcc,0x3b,0xdd,0xbe, - 0x73,0x4a,0x7f,0xd8,0x83,0x14,0xf1,0x6d,0x4c,0xe8,0x85,0x4d,0x69,0x0f,0xf0,0x36, - 0x31,0x1f,0xc3,0xde,0x8e,0x85,0x06,0x02,0xef,0xbf,0x57,0x1a,0x79,0x7f,0xc6,0x4e, - 0x92,0xac,0x8f,0xd4,0x87,0xf2,0x67,0x4f,0x93,0xaa,0x64,0xc4,0xa0,0x97,0xa7,0x51, - 0x00,0xd8,0xb3,0x5f,0x34,0x1b,0xeb,0xc8,0x1e,0x28,0x6c,0x33,0x1d,0xbe,0xaa,0xa5, - 0x3f,0xec,0xb0,0xf2,0x35,0x78,0x96,0xe5,0x77,0xd0,0xef,0x93,0x1f,0xf3,0xb2,0x00, - 0xae,0xc8,0x9a,0x75,0xaf,0xc3,0x81,0xb6,0xd9,0x71,0xf1,0x9f,0xc8,0x57,0xb5,0x4d, - 0x8d,0x3b,0x74,0xfa,0x3e,0xb1,0xd6,0x47,0xba,0x07,0x3e,0x61,0x31,0x23,0xd3,0x43, - 0x5e,0x86,0x5f,0x47,0xdd,0x03,0x6e,0x51,0x34,0xe0,0xfc,0xbd,0x9e,0x41,0xc7,0x21, - 0xd1,0x05,0x46,0xbe,0x47,0x73,0xe7,0x8b,0x96,0xfe,0xb0,0x33,0x9e,0xd3,0xfe,0x39, - 0xca,0x41,0xe0,0x97,0x07,0x4c,0xb4,0x33,0x6d,0x4f,0x4d,0x5c,0xfd,0x34,0xb7,0xea, - 0x25,0x47,0xec,0x85,0xe1,0xec,0x3f,0x91,0xc5,0xbd,0x8e,0x15,0x72,0x32,0x3f,0x8e, - 0x72,0xfc,0xa3,0xa3,0x36,0xec,0x16,0x25,0xf8,0xe3,0x83,0x3e,0xc1,0xd6,0xb0,0x75, - 0x28,0x7a,0x9e,0x75,0x5d,0x5c,0x1a,0x6b,0x29,0x84,0x17,0xc0,0x9b,0xb7,0x54,0xaf, - 0x49,0xda,0x77,0x7d,0x79,0xdb,0x61,0x2f,0xcd,0x67,0x74,0x58,0xcc,0xa5,0x2f,0xdb, - 0x8b,0x05,0xf9,0x21,0xf2,0xb6,0x7e,0x00,0x6e,0x35,0x22,0xf5,0x64,0x01,0x59,0x27, - 0xa8,0x4d,0xae,0x90,0xcd,0x3b,0xb9,0x9e,0x26,0x3f,0xaa,0x29,0x9f,0xd7,0x07,0x28, - 0xe3,0x65,0x30,0xe3,0xb6,0x40,0xf6,0x3b,0x91,0xe7,0x1b,0x42,0xef,0xd3,0x1f,0x90, - 0xeb,0x50,0xf7,0xe6,0x87,0xe8,0xa0,0xa5,0x3e,0x49,0x1d,0xe2,0x9f,0xbd,0x51,0xd3, - 0xbe,0xa8,0x85,0x46,0xa1,0xc4,0x58,0xb2,0x80,0x9c,0x14,0xf6,0x32,0xb3,0x02,0x4c, - 0x3a,0x84,0xdf,0x56,0xcf,0xe0,0x7a,0x26,0xf1,0xc9,0xe0,0x0c,0xde,0x0d,0x76,0x2f, - 0x27,0x81,0xe7,0x19,0x1f,0x90,0xaa,0x1f,0x65,0xe9,0x39,0xef,0xab,0x57,0x88,0x97, - 0x6d,0xd7,0xc5,0xdb,0x94,0x97,0x34,0xef,0x36,0x77,0x48,0x5c,0x64,0xe9,0x0f,0x92, - 0xe0,0xab,0x2c,0x43,0x35,0x82,0x60,0x9d,0xa3,0x9d,0xc6,0x38,0x1b,0x89,0xe2,0x00, - 0xc4,0x78,0x68,0x84,0x3c,0x37,0x35,0x3f,0xce,0xd4,0x8f,0x9c,0xe4,0xdc,0xc1,0x13, - 0xc9,0xb5,0xd6,0x2d,0x78,0x4c,0x8e,0xf5,0xfa,0x12,0x44,0xa9,0x63,0xb8,0x91,0xec, - 0xd1,0x1a,0x31,0x35,0x3f,0x0e,0x61,0xc9,0x78,0x5b,0x2e,0xa7,0x86,0xd6,0xd6,0x49, - 0x68,0xf6,0x9b,0x8e,0x88,0xb4,0xe5,0x68,0x7f,0xf1,0x5f,0x25,0xeb,0x23,0x99,0xf8, - 0x47,0x2b,0xe1,0x6d,0xbc,0x3a,0xd0,0xba,0x6c,0x37,0x5c,0xbc,0x2c,0x40,0x73,0xa2, - 0x2c,0x80,0x9b,0xb4,0xa8,0x66,0x87,0xaf,0x3b,0xa6,0xe0,0x1f,0x5e,0x1f,0x89,0xbc, - 0x37,0x41,0x8b,0x3a,0x47,0x1a,0x25,0xee,0x11,0xba,0x97,0x17,0x22,0x50,0x35,0x84, - 0x46,0x5a,0x12,0xff,0x98,0xf9,0x71,0x95,0x1c,0xed,0xe8,0xf4,0x4c,0x82,0x0d,0x95, - 0xa8,0x0f,0xb9,0x0c,0x6d,0x1a,0x3a,0x9e,0xb1,0xf5,0xb5,0x64,0x7e,0xdc,0x8c,0xf1, - 0x26,0x68,0xfd,0x05,0x17,0xcc,0xfc,0xb8,0x4d,0xbc,0xad,0xd5,0x65,0x8d,0xd7,0x87, - 0x14,0x2f,0x98,0x83,0x4d,0x41,0x6b,0x7f,0x10,0xce,0x8f,0x8a,0x96,0x7e,0xc9,0x1d, - 0x25,0xab,0xe8,0xe3,0xaa,0x37,0xb8,0x94,0x27,0x12,0x5e,0x56,0xbd,0xcb,0xed,0x3f, - 0x26,0xb7,0xe2,0xa0,0x2b,0x60,0x4f,0xc9,0x8f,0xcb,0x8b,0x4b,0xdd,0xfd,0x6c,0x41, - 0x26,0x2f,0x93,0x1b,0x29,0x71,0x52,0x8a,0xf2,0x50,0x3a,0xa4,0x39,0xa9,0x2d,0x4c, - 0x50,0x46,0xdf,0xe7,0x54,0x68,0x4a,0x7f,0x58,0xce,0x0f,0x57,0x55,0x8d,0x6e,0xd9, - 0xd0,0xa1,0xe3,0xfb,0x06,0x02,0xbc,0x0c,0xd4,0x9e,0xe9,0x9d,0xcb,0xe9,0x75,0xa4, - 0x50,0xd9,0x03,0x3b,0x6e,0x47,0xe0,0x9d,0xec,0x0f,0xbb,0x4d,0xea,0xe0,0xf2,0xa7, - 0x3a,0x83,0xe7,0x1b,0x36,0x08,0xed,0xcb,0x23,0x51,0x3f,0xbf,0x52,0xc4,0xeb,0x47, - 0x15,0xba,0xf0,0x8b,0xdc,0x47,0xfb,0xc9,0xb9,0x29,0xf5,0x21,0x63,0x77,0xd8,0x95, - 0xec,0x69,0x21,0x5e,0x08,0xc2,0xad,0x88,0xb3,0x95,0xd1,0x9a,0x22,0x6d,0x69,0x54, - 0x9e,0x03,0xa3,0xd3,0xbd,0xf5,0xae,0xa8,0x90,0xe4,0x63,0xf4,0x09,0x89,0xfd,0xe0, - 0x88,0xc2,0x53,0x88,0x8e,0x2a,0x57,0x70,0x7f,0x97,0xf4,0x89,0x5e,0xa6,0xbd,0xaa, - 0x88,0xdf,0xc8,0xfe,0x84,0x1d,0x31,0xf1,0x8f,0x85,0x5f,0xa7,0xc3,0xb0,0xea,0x55, - 0xdd,0xec,0xcb,0x67,0x79,0x35,0x6c,0xc5,0xcd,0x1b,0xf5,0x8e,0xe0,0xfe,0xa2,0x26, - 0x3f,0x8a,0xc6,0x78,0x7f,0xd8,0xa9,0xf9,0x71,0x05,0x3a,0x35,0xdd,0x3e,0x52,0x49, - 0x03,0xed,0x20,0x7f,0x94,0x8e,0xf4,0x74,0xb1,0x4c,0x3d,0xfb,0x0c,0x6c,0x5c,0xe9, - 0x64,0x54,0xb7,0xd6,0x87,0x44,0xf9,0xb3,0x97,0xe9,0xe3,0xdd,0x73,0xd0,0xfe,0xfa, - 0xc9,0xc2,0xf4,0xd6,0xa6,0xae,0xe5,0x60,0xe4,0x79,0x88,0x41,0x50,0x3e,0x1b,0x54, - 0x0d,0x1f,0x4f,0xf6,0x03,0xe5,0xf8,0x47,0xcb,0x3f,0xca,0xdb,0xfa,0xb0,0xf5,0xc4, - 0xa4,0x49,0xff,0x16,0xf6,0x83,0xd0,0x97,0xf1,0x50,0xf6,0x28,0x4a,0x30,0xb3,0xbe, - 0xd9,0xe0,0xe4,0xfc,0x48,0x04,0xf1,0x0f,0xdb,0x13,0x77,0xaf,0x21,0x57,0xd4,0xf5, - 0x83,0x95,0x1f,0x64,0x2d,0x17,0x9f,0x50,0x3f,0x67,0xa5,0xe7,0xed,0x0f,0x37,0xbe, - 0x06,0x2f,0xb3,0x98,0x6e,0xaf,0x13,0x3f,0x70,0x4e,0xcc,0xa7,0x33,0x4c,0xff,0xcf, - 0x5b,0x8e,0x58,0xe9,0x87,0xec,0x52,0xc8,0x67,0x3c,0x1a,0x23,0xef,0x6f,0xef,0x82, - 0x8a,0x33,0x8e,0xfd,0x62,0x1f,0xda,0x53,0x47,0xd8,0x3c,0x3d,0x27,0x59,0x1f,0x92, - 0x34,0x1d,0x81,0xcb,0xbc,0x2c,0xf6,0x48,0xa3,0x2f,0xf4,0x2a,0xf3,0x9e,0xb3,0x5f, - 0x16,0xce,0x9b,0x11,0x8d,0xda,0x51,0x3c,0x86,0xbf,0x8b,0xed,0x8d,0xb7,0x76,0x5b, - 0xf3,0xe3,0xf2,0xb6,0x6b,0xf8,0xd1,0x35,0xfa,0xa0,0x38,0xd3,0xd8,0xd9,0xae,0x0e, - 0xe2,0xd3,0xfe,0x16,0x9e,0x55,0xd5,0x3e,0xca,0x89,0xe2,0xeb,0x3d,0xf9,0x7d,0x28, - 0x6a,0x3e,0x98,0xec,0x47,0xcf,0xf1,0xcf,0xb3,0x30,0xbb,0x9e,0x0e,0x13,0xde,0x16, - 0x2d,0xbf,0x37,0x23,0x18,0xee,0xd7,0xf6,0x4b,0xb3,0x8d,0xc0,0x83,0xfe,0x61,0xff, - 0x63,0x9e,0x50,0x43,0x60,0x8d,0x35,0x3f,0x0e,0xe5,0x4f,0x0c,0x9e,0xe2,0x6c,0xf0, - 0x12,0xed,0x67,0xa0,0xbe,0x88,0xc0,0xb2,0x8f,0x76,0xf5,0x9b,0x12,0xe9,0x03,0x5e, - 0x78,0x9c,0xd1,0xd4,0xfc,0x38,0xb3,0x09,0x6c,0xc0,0x3e,0x2c,0x2e,0x96,0x36,0x49, - 0x05,0xf1,0x47,0x79,0xfd,0xe1,0x8b,0x3d,0x9f,0x72,0xda,0xd2,0x07,0xec,0xd7,0xc4, - 0x7b,0xdf,0x49,0x26,0x7e,0x90,0xec,0x4f,0x8a,0xf8,0xe7,0x13,0xa8,0xd0,0x1c,0xb1, - 0x25,0xbb,0x55,0xce,0x96,0xcf,0xe2,0x7c,0xf2,0x8b,0xf4,0x11,0x63,0x5e,0xcc,0xff, - 0xa1,0xf2,0x7e,0x5f,0x65,0xc8,0x4c,0xd4,0x9d,0x78,0x7e,0xc4,0x3f,0xca,0x25,0xa5, - 0x54,0x73,0x73,0xed,0xc6,0xeb,0x0f,0xd8,0x2f,0xe4,0x8c,0xa0,0x59,0xb7,0xc8,0x58, - 0xca,0x3b,0x60,0xbe,0x25,0x94,0xe6,0xdb,0xfb,0x44,0xa3,0x76,0xe2,0xf9,0x39,0xfe, - 0x39,0x28,0x39,0x57,0x99,0xdd,0xd8,0xdf,0x32,0xfb,0x9d,0x39,0x7f,0xaf,0xf1,0xb2, - 0x3c,0x99,0x31,0xff,0x47,0xd0,0x6c,0xb4,0xab,0xae,0x88,0xd5,0xff,0x23,0xb8,0xb9, - 0xbd,0x10,0xa6,0x09,0xb7,0x8f,0xd3,0x30,0xd9,0x9b,0x87,0xd6,0xba,0x8d,0x48,0x8c, - 0x7c,0xf0,0x85,0x6d,0x11,0x67,0x80,0x6e,0x99,0x92,0x1f,0xb7,0x17,0xe2,0xcc,0xc5, - 0xd9,0xf2,0x5b,0x51,0x51,0xe6,0x41,0x7a,0x2f,0xed,0x92,0xdc,0x46,0xc6,0x7c,0xbc, - 0x12,0x41,0xf9,0x13,0x50,0xd6,0x59,0xf8,0x51,0x8f,0xae,0xd6,0x46,0x61,0x3e,0x4f, - 0x82,0xfb,0x17,0x65,0x53,0x68,0xfe,0x19,0xb3,0x2d,0xda,0x45,0x58,0xdc,0x6b,0x1f, - 0x2e,0x18,0x82,0x37,0x05,0x54,0x3d,0x5b,0x52,0xea,0x23,0xa1,0x12,0xa7,0x37,0x1b, - 0x8e,0x7a,0x71,0x4c,0xbf,0x34,0xb7,0xea,0xcd,0x79,0x86,0x38,0x4c,0xaf,0x40,0x55, - 0x9f,0xe3,0x7c,0xce,0x18,0x1f,0x70,0x6a,0xb4,0xb5,0x3e,0x24,0xf7,0xff,0xe0,0xc5, - 0x38,0x2a,0xe5,0xcb,0x9e,0xd2,0x01,0x47,0x8f,0xe8,0x85,0x31,0xa9,0x94,0x3a,0x46, - 0x6a,0xae,0xe0,0x41,0x2b,0x1d,0x6e,0xfd,0xf5,0x94,0xfe,0x68,0x87,0xc3,0x9c,0xfd, - 0xb5,0x45,0x65,0x91,0x6a,0x44,0x77,0x6b,0x9d,0x25,0x50,0x5e,0xef,0x54,0xe5,0x6e, - 0x4e,0xa4,0x37,0xd4,0x9e,0xc0,0x56,0x6b,0x7f,0xb4,0x34,0x33,0x5f,0xa9,0x56,0xae, - 0x20,0xb5,0x1e,0xdd,0xa3,0x06,0x96,0x64,0xa3,0x01,0x36,0xdf,0xe5,0x0a,0x9a,0xf9, - 0x17,0x5d,0x9a,0xab,0xcf,0xe6,0x4c,0xe9,0x8f,0xc6,0xf1,0x4f,0x49,0xa8,0x25,0x6a, - 0x5b,0x09,0x8d,0xac,0xa8,0x41,0xee,0x36,0xdc,0xca,0x41,0xa3,0x48,0x1f,0xaf,0xb7, - 0x50,0x64,0x20,0x7e,0xb0,0xf4,0x47,0x33,0xf7,0x8f,0xcf,0xe3,0x38,0x2b,0xae,0xa4, - 0x63,0xbc,0x9a,0x68,0x44,0x54,0xd9,0x88,0x71,0xc8,0x63,0x3a,0x4e,0x47,0xb4,0x0a, - 0x23,0x6b,0x9b,0xa8,0xa4,0xd6,0x47,0x82,0xaa,0x6a,0x44,0x83,0x31,0xb8,0x0d,0x61, - 0x90,0x23,0xf8,0x85,0x8b,0xda,0x9f,0x68,0x19,0x38,0x12,0xfe,0x8d,0xbf,0xe2,0x15, - 0x39,0x52,0xeb,0x23,0x5d,0xe2,0xdd,0x9d,0xba,0x6a,0x4a,0xe0,0x2d,0xcd,0xbb,0xc6, - 0xde,0xd4,0xe8,0x64,0x23,0x9a,0x4f,0x31,0xfb,0x7f,0x9d,0x0f,0x76,0xbd,0x9b,0x1a, - 0xff,0x32,0xfd,0x81,0x25,0xb5,0x72,0x5b,0xb8,0x48,0x3a,0xbe,0xdc,0xb9,0x19,0xda, - 0xc2,0x73,0xb9,0x86,0x5a,0x00,0xe6,0xf3,0x33,0x62,0xd4,0x3e,0x4b,0xbc,0x29,0xf1, - 0x2f,0x5c,0x9f,0x0e,0x79,0x9b,0x2d,0xa4,0x6e,0x61,0x6a,0x3f,0x2d,0xb4,0xf5,0xf0, - 0xa6,0x62,0xba,0x99,0x4f,0x11,0x13,0x9c,0x86,0xb0,0xd6,0x82,0x7f,0x78,0xfc,0xeb, - 0x40,0xb8,0x38,0x24,0x9f,0x21,0x5f,0x85,0xb5,0xac,0x60,0x80,0x2e,0x4f,0x7f,0x1d, - 0x9e,0x8d,0x16,0x0f,0xd0,0x35,0xe9,0xef,0x48,0x07,0x1a,0x10,0x2a,0xd4,0xa5,0xe0, - 0x1f,0x3b,0x7c,0xca,0x2a,0x4f,0x3a,0xbc,0xe2,0x2a,0xf8,0x35,0x8f,0x76,0xed,0x10, - 0x0d,0x2d,0x46,0x2b,0xef,0xb5,0x7b,0xc4,0x93,0x70,0xde,0xf0,0xf4,0x65,0x7a,0x6a, - 0x2c,0xf8,0xe7,0x26,0xee,0xff,0xa9,0xaa,0x9d,0x56,0x2f,0xee,0xe3,0xdd,0x72,0x7b, - 0xe6,0x0d,0x8b,0x0b,0x94,0x51,0xb3,0x62,0x92,0x30,0x06,0xbf,0x13,0x12,0xf5,0x91, - 0x52,0xea,0x03,0x5c,0x82,0x47,0x10,0x5f,0x89,0x2a,0x07,0x8a,0x46,0x89,0x51,0x30, - 0xa4,0x5f,0x81,0xbd,0x21,0x73,0x7d,0xf8,0x15,0xde,0xdf,0xf9,0x9a,0xfa,0x00,0x72, - 0x7d,0x76,0x6e,0xda,0x3e,0x61,0x05,0xaf,0xae,0xff,0xdb,0xe8,0x01,0x30,0xfb,0x83, - 0xbc,0x8d,0x4b,0xb1,0x93,0x17,0xda,0xf5,0xa6,0xd6,0x07,0x60,0xc5,0xa1,0x13,0x23, - 0xd9,0xd7,0xc1,0x7e,0x56,0x80,0xf8,0x27,0xfc,0x0e,0x8b,0x31,0x57,0x3d,0x0f,0xfc, - 0xe1,0xaf,0xe6,0xc6,0x6f,0x28,0x27,0x9e,0xa9,0xf9,0x71,0x5f,0xe5,0xd1,0xd5,0x5a, - 0xee,0x98,0xb5,0xb5,0x91,0x57,0x5e,0x3c,0xb8,0x9c,0x3e,0x64,0xf3,0x98,0xfd,0x97, - 0x8b,0x8c,0x1b,0xca,0x6c,0xd9,0x29,0xf5,0x01,0x2e,0x42,0x55,0x2c,0x33,0x2e,0x57, - 0xc0,0x95,0xf8,0x5e,0x96,0x35,0x24,0xfe,0x11,0xae,0x34,0xdc,0xa8,0x67,0xe9,0x28, - 0x88,0x3e,0x4f,0xab,0x68,0xc0,0x2b,0x15,0xa9,0xf5,0x01,0x78,0x36,0x5c,0x13,0xaf, - 0x06,0x60,0xf7,0x29,0xb7,0xaf,0xe3,0x6e,0x9f,0x9a,0x32,0x25,0x83,0xf1,0xc6,0x61, - 0xac,0x4c,0x49,0x6b,0xb8,0xa6,0x3e,0x80,0x4f,0x5b,0xa6,0x88,0x4f,0xb1,0x51,0xe6, - 0x0c,0xd9,0xb7,0xc8,0x73,0xd8,0x31,0xd5,0x89,0x6a,0xae,0x86,0xd7,0x47,0xf2,0x86, - 0x56,0xe7,0xa5,0xd4,0x87,0x1c,0x8f,0x7f,0x6d,0xb3,0x15,0xb2,0x83,0x7d,0x65,0x2b, - 0x5c,0xdb,0x9d,0x0e,0xde,0xe8,0xe4,0xde,0x8c,0xa8,0xc9,0x00,0x6f,0x0f,0x05,0xb6, - 0x4f,0xe9,0x0f,0x82,0xf3,0x5f,0xba,0x71,0xcb,0x86,0xdd,0xf4,0xb0,0x5a,0xf4,0x12, - 0x8d,0xda,0x0a,0x49,0x73,0xc2,0xed,0x83,0xf3,0x9b,0x9c,0xb5,0xae,0xfd,0xa9,0xfd, - 0x61,0x13,0x45,0x90,0x78,0x59,0x24,0x13,0x08,0x2d,0xe0,0x8a,0x5e,0xeb,0xe4,0x6e, - 0x10,0x5e,0x4a,0x91,0xf7,0x87,0xbd,0x81,0x08,0x13,0xeb,0x99,0xa8,0x0f,0xe0,0xe3, - 0x4e,0x1e,0x54,0xc4,0xe9,0x15,0x89,0xfe,0xa4,0xc7,0xc1,0x2c,0x8b,0x6d,0x32,0xc6, - 0x79,0xeb,0xe4,0x92,0x24,0xfe,0xb9,0x1e,0x5f,0x4a,0xa8,0x0a,0x2e,0x3b,0x2d,0x5e, - 0x90,0x2e,0x6b,0xb7,0x26,0xea,0x43,0x5e,0xd5,0x16,0xf2,0xc2,0x41,0x08,0x75,0xfc, - 0xb3,0xf8,0x95,0x94,0xfa,0x48,0xdc,0xff,0xa3,0x39,0x2e,0xd4,0xe4,0x4a,0x97,0xed, - 0xa5,0x5a,0xd6,0xe9,0x1a,0xc4,0x3f,0x9a,0x99,0x36,0x88,0xf3,0xa9,0x49,0x1d,0x9f, - 0x33,0xa5,0x3e,0x40,0x09,0xb4,0x34,0x11,0x95,0x75,0x6b,0x4e,0x5b,0xa6,0xee,0x54, - 0x39,0x63,0x5c,0xa1,0x2c,0x1b,0x7f,0xc5,0x2b,0x06,0xac,0xb3,0x59,0xfb,0xc3,0xe2, - 0x4b,0x11,0x77,0x70,0xc9,0x75,0x77,0xbd,0xa4,0xee,0x71,0x39,0xf9,0x8b,0x23,0x22, - 0x0a,0x71,0xe0,0x97,0xdd,0x2b,0xe0,0xfb,0xde,0x45,0x95,0x70,0x6a,0x7f,0xd8,0x83, - 0x02,0xca,0xb7,0x68,0xfa,0x00,0xdb,0x23,0x39,0xab,0xef,0x8c,0xda,0x3a,0xe8,0x61, - 0x85,0x24,0x10,0xe9,0x41,0x94,0xcf,0x91,0x1f,0x59,0xfb,0xc3,0xe6,0x22,0x9e,0x11, - 0xca,0xd6,0x6c,0xda,0x92,0x33,0x00,0xdf,0x8f,0x78,0xd6,0x38,0xb6,0x23,0xd0,0x1d, - 0x65,0x5d,0x9a,0xdb,0xac,0x7f,0xa5,0x20,0x22,0xda,0x26,0x26,0xe3,0x5f,0x9d,0xa6, - 0xbf,0xa8,0x44,0x73,0xdc,0x80,0x30,0x6f,0xd4,0x38,0xf2,0xed,0x57,0xb3,0x1b,0x57, - 0xc1,0x68,0x6b,0x65,0xdf,0xb2,0xa8,0x80,0xf3,0x39,0xfe,0xd9,0x26,0x27,0xfd,0x0f, - 0xe3,0xfc,0x70,0xd8,0xd4,0xb4,0x44,0x65,0x7d,0x37,0x78,0x73,0xed,0xe6,0xc6,0xd3, - 0x12,0x89,0x8a,0x30,0x8c,0xa2,0x64,0x53,0x58,0x4c,0xed,0x8f,0x76,0x88,0xcc,0x8b, - 0xca,0x1f,0xe1,0x52,0x6d,0x64,0x05,0xcc,0x35,0x48,0x06,0xe9,0x11,0xe6,0x64,0x4b, - 0x38,0x22,0x3a,0x24,0x15,0xb0,0x25,0x03,0x7e,0xdb,0xc4,0x71,0x07,0x77,0x42,0xfe, - 0xb8,0xe5,0x32,0xdb,0x52,0xde,0x6d,0x27,0x48,0xa7,0x2b,0xa7,0xb4,0x83,0x9a,0x99, - 0x96,0x7b,0x12,0xf6,0x30,0xd5,0x40,0xc1,0x9e,0xec,0x0f,0x32,0xce,0x0f,0x67,0x72, - 0x90,0xfc,0x90,0x87,0x81,0x12,0x65,0x3d,0x9e,0xa5,0xbb,0xfa,0x79,0x44,0x1b,0x4a, - 0xfd,0xf9,0x47,0xe5,0xef,0x59,0xe3,0x5f,0x66,0x7d,0x80,0xc5,0x21,0xc7,0xa0,0xf8, - 0x35,0xdb,0xc7,0x6c,0x6f,0xc8,0x1e,0x10,0x39,0x51,0x7c,0x7e,0xbb,0x63,0x8d,0xc8, - 0x1b,0xa5,0xed,0x89,0x3b,0x46,0x64,0x5b,0x0a,0x3f,0x9c,0xc7,0xbf,0x36,0x31,0x79, - 0x1f,0xea,0xdf,0x1f,0x6a,0x28,0xa8,0x87,0x62,0x97,0xa1,0x6c,0x9b,0x23,0xc6,0x1b, - 0xa1,0xa6,0x9b,0xf5,0xca,0x92,0xfe,0x1f,0x6d,0xc6,0x3b,0xbc,0x9b,0xa7,0x6a,0x1f, - 0x11,0x7d,0xd2,0x55,0x36,0x9f,0x67,0xc3,0x5d,0xe1,0x8c,0x68,0xde,0xd6,0xe1,0x8a, - 0x86,0xaa,0xed,0x3d,0x7b,0xb7,0xb5,0x3f,0xda,0xf5,0xdb,0xe1,0xd7,0xf8,0xfc,0x79, - 0xf7,0xda,0x66,0xd2,0x03,0x4a,0xbe,0x91,0x69,0xe2,0x99,0x48,0xb1,0x96,0xf9,0xa0, - 0x59,0x1f,0xa9,0xb8,0x27,0xf2,0xfd,0x94,0xfa,0x90,0xdc,0x4d,0x5d,0xac,0x65,0x84, - 0xb2,0xb6,0x69,0x07,0xa0,0x40,0x43,0xbc,0x74,0x5a,0xdd,0xa7,0x16,0x03,0x97,0x57, - 0xca,0x01,0xa5,0x58,0x0b,0xd4,0x87,0xd3,0x27,0xbf,0x17,0x8f,0x7f,0x6d,0x05,0x77, - 0xf8,0x7a,0x20,0x11,0xa9,0x5b,0x53,0xbb,0x11,0xff,0xbc,0x04,0x7b,0xf5,0xd5,0x79, - 0x19,0xb8,0x9e,0xca,0x5e,0xa5,0x04,0x28,0xb5,0xe5,0x35,0x4d,0xe6,0xc7,0xcd,0x68, - 0xe5,0xdd,0xbe,0xd4,0x62,0x8f,0xbc,0x1b,0x3f,0x74,0x8c,0xb6,0x46,0xc5,0x8f,0xe1, - 0x60,0xaf,0x6f,0x90,0x07,0xb6,0x32,0xf9,0x52,0xa0,0x69,0x69,0x4b,0xa9,0x0f,0x80, - 0x17,0xf5,0x8d,0x3f,0x22,0xdf,0x52,0x47,0xee,0x45,0x41,0xd4,0x86,0xf6,0xd7,0xa8, - 0x36,0xcb,0x2c,0xdc,0x27,0x7c,0x4a,0x7d,0x86,0x59,0x78,0xcd,0xca,0x0f,0x7f,0x95, - 0x7b,0x17,0x07,0xe5,0x4a,0xe5,0x64,0x5f,0x29,0x64,0x6a,0x62,0x39,0x7c,0x06,0xa5, - 0xe3,0xfd,0x20,0xd4,0x52,0x5e,0x3a,0x4f,0x4d,0xa9,0x0f,0xf0,0x33,0x52,0xa2,0x2c, - 0x89,0xe3,0x27,0x69,0x35,0xca,0xbc,0x74,0xfb,0x96,0xb9,0x4d,0xdd,0x61,0x67,0x7a, - 0x42,0xff,0x32,0x67,0x21,0x8d,0xdc,0xa5,0x86,0x2c,0xfc,0x70,0xee,0xa6,0x20,0x37, - 0xee,0xd9,0xe2,0x56,0x23,0x9a,0x73,0x47,0x46,0x37,0x71,0xc3,0x21,0xb6,0x72,0xb2, - 0x3e,0x52,0x0f,0xed,0x0e,0xab,0xd6,0xfc,0x38,0xd8,0xa9,0xb9,0x61,0x09,0x23,0x94, - 0x84,0xa5,0x39,0xd5,0x14,0x70,0x33,0xc6,0x54,0x15,0xe4,0x84,0x7c,0x56,0x8d,0x08, - 0xb4,0x5b,0x18,0x5e,0x74,0x75,0xde,0x09,0xcd,0x57,0xed,0x50,0x64,0x17,0x4f,0xab, - 0xe1,0x69,0xa1,0xaa,0x30,0x42,0xbc,0x3d,0x89,0xc0,0xa8,0xe6,0x31,0xdc,0x5d,0xa2, - 0x9a,0xcc,0x8f,0xbb,0xde,0x74,0x62,0xc0,0x32,0x43,0x1c,0x91,0xc6,0xc6,0xeb,0x43, - 0xc2,0x48,0xad,0x59,0x16,0x60,0x4c,0xba,0x5a,0xf4,0x3c,0xcc,0x4b,0xc1,0x3f,0x26, - 0xff,0xa7,0xaa,0xdf,0xde,0x23,0xde,0x0f,0x0f,0x33,0xaf,0x9a,0x79,0x4c,0x46,0xfc, - 0xc3,0x7c,0xba,0xfd,0x0c,0x59,0xa0,0x5d,0x51,0x70,0xc7,0x76,0x5b,0xf9,0x3f,0x79, - 0x1f,0xc1,0x25,0x36,0xaf,0x97,0x86,0x49,0x55,0xa0,0x9b,0x15,0xa9,0x32,0x21,0x73, - 0xa0,0x9b,0x95,0xe8,0xae,0x6d,0xe4,0x49,0xe3,0xd0,0xf7,0x9c,0x01,0xdb,0xd4,0xfa, - 0x48,0x78,0xbe,0xfa,0x78,0x3d,0x70,0xa9,0x9b,0x85,0xd4,0xeb,0x19,0x01,0x29,0x0a, - 0xab,0x59,0x5f,0xd4,0x29,0x09,0x5d,0x4c,0x5f,0x19,0xf0,0x58,0xfa,0x33,0xf2,0xfc, - 0xb8,0x9f,0x49,0x25,0xbc,0x5a,0x82,0x1b,0xba,0x55,0x27,0xdc,0x88,0x66,0x1d,0xfc, - 0x14,0x1e,0xd0,0x51,0xfe,0x3c,0x65,0xd6,0x07,0xb0,0x59,0xeb,0x23,0x41,0x1a,0x5f, - 0x64,0x9f,0x61,0xdf,0xf8,0xf5,0xd5,0x10,0x63,0x5d,0x1d,0x99,0xae,0x9c,0x22,0xed, - 0x8d,0xf0,0xc3,0x23,0xf6,0x6d,0xc2,0x2d,0x6c,0x84,0x79,0x57,0xd9,0xad,0xf9,0x71, - 0xe3,0xf8,0xc7,0x70,0xb4,0xca,0x63,0xea,0x65,0x36,0xde,0x16,0xe4,0xf2,0xed,0x38, - 0x78,0x5b,0xbc,0xa0,0xe2,0x8a,0x85,0xae,0xa9,0x8f,0x84,0xfb,0x2d,0x6e,0xdf,0xc7, - 0xd3,0xe2,0x72,0xf1,0xf4,0x35,0x89,0x6e,0x5e,0x18,0xa7,0xdf,0x8e,0x86,0x1b,0x39, - 0x4e,0x51,0x50,0x5f,0x13,0xff,0xc2,0x25,0xc6,0xa7,0xad,0xe2,0xf9,0xf2,0xbc,0xd0, - 0x5c,0x09,0x1c,0xee,0xcb,0x32,0xe8,0x36,0x72,0xae,0x70,0x03,0x73,0xae,0xa4,0x53, - 0xea,0x43,0xc2,0x5e,0xa9,0xe4,0x05,0x34,0xc3,0x97,0x91,0x9d,0x4d,0x66,0xff,0x4a, - 0x22,0x75,0x1d,0x77,0x33,0xba,0x2d,0xfc,0x22,0xfc,0x44,0x6b,0xe7,0x1d,0x63,0x53, - 0xeb,0x23,0x1d,0x60,0xdf,0xe1,0xfe,0x90,0x59,0xe1,0xc7,0xf4,0xe2,0xd0,0x8d,0x7f, - 0x63,0xe3,0xc0,0x60,0xde,0x6e,0xfa,0x77,0xe1,0x77,0x60,0x16,0xdb,0x19,0xa2,0xdf, - 0x4f,0xad,0x8f,0xa4,0x7c,0xca,0xd7,0x47,0x95,0xef,0xd1,0xcf,0x86,0x2b,0x3f,0x76, - 0x54,0x8a,0x36,0x63,0x78,0x73,0xe5,0x2f,0xdc,0x37,0xe2,0x31,0xb9,0x97,0x7a,0x34, - 0x7b,0xc5,0x94,0xfa,0x48,0xb8,0x3e,0xaf,0x4d,0x8b,0xff,0xd5,0x87,0xea,0x87,0xf4, - 0xe6,0x1e,0xc7,0xde,0x9a,0x11,0xb8,0x9a,0xbb,0xd8,0x6c,0x94,0x26,0x9d,0x33,0xeb, - 0x4b,0x4c,0x9b,0x82,0x7f,0xc8,0xac,0x41,0x94,0xf6,0x3e,0xf6,0x41,0xe8,0x91,0x3c, - 0x87,0x5a,0xa0,0x1a,0x97,0xd4,0x4a,0x3c,0x56,0x05,0x2e,0x38,0x2f,0x94,0x69,0x8e, - 0x6e,0xd9,0x8a,0x7f,0x66,0x2a,0x07,0x60,0x5e,0x1f,0x1d,0x9e,0x53,0xc9,0x7e,0xe3, - 0x59,0x5c,0x8b,0x62,0x33,0x57,0x3f,0x90,0x51,0x5c,0x4d,0x79,0x7d,0xfe,0xfd,0xb0, - 0x83,0xfb,0x93,0x93,0xf8,0xa7,0x27,0x81,0x7f,0xf0,0x7d,0x57,0xfa,0xa4,0x75,0x6c, - 0x76,0xc7,0x92,0x41,0x32,0x0b,0xf6,0x45,0x8b,0x79,0x5b,0x90,0x59,0xf0,0x3c,0x9b, - 0x1d,0x92,0xd7,0x5c,0x8b,0x7f,0x8c,0xc8,0x02,0x62,0x87,0xad,0x6a,0xa0,0x1f,0x8f, - 0xa1,0xa3,0x70,0x2f,0x2a,0x7a,0x94,0x3f,0x0f,0x54,0xef,0xd5,0xb8,0x63,0x8d,0x58, - 0xf0,0xcf,0x8f,0x3a,0x13,0xdd,0x60,0xe3,0xa2,0x0b,0x9e,0x81,0x39,0x1d,0xcb,0x86, - 0x6e,0x74,0xa9,0x17,0x95,0xc5,0x4f,0xb9,0x3b,0x6b,0x10,0x11,0xc1,0xff,0xe0,0x89, - 0x90,0xd7,0xe0,0x1f,0xd4,0x3e,0xb2,0x39,0xc8,0x75,0x34,0x8c,0x87,0xbd,0xee,0x59, - 0x6b,0x36,0x0a,0x39,0x42,0xfe,0x4c,0x7d,0x24,0x6e,0xef,0x37,0xce,0x61,0xa3,0xaa, - 0x2f,0xb4,0x29,0x8a,0xfa,0xae,0x59,0xf0,0x85,0xec,0x51,0x5e,0x1f,0xa9,0xe8,0xd0, - 0x94,0xfe,0xb0,0x13,0xf8,0x87,0xd7,0x87,0x44,0x20,0x7d,0x01,0x07,0x99,0x5c,0xc2, - 0x68,0x34,0x37,0x3c,0x5b,0x7a,0x43,0x70,0x86,0x5c,0xd7,0xe4,0xc7,0xf1,0x6c,0x14, - 0x85,0x24,0x88,0x40,0x4b,0xa2,0x37,0xbc,0x07,0xbb,0xe0,0x01,0xde,0xc6,0xab,0x90, - 0x35,0xd3,0x22,0xde,0x6a,0xed,0xa5,0xa9,0xf8,0xa7,0x7e,0x49,0xae,0x5f,0x82,0xf9, - 0x9c,0xf8,0x91,0x4b,0x3a,0xc8,0x4e,0xa1,0x44,0xd3,0xa3,0xb6,0x4c,0xd8,0xac,0x4d, - 0xa9,0x8f,0xd4,0x3d,0x8e,0x7f,0x38,0xed,0xc7,0x1c,0x9c,0xe0,0x6a,0x37,0x51,0x28, - 0x52,0xe4,0xfe,0x9f,0x43,0x2c,0xb5,0x3f,0x6c,0xe6,0x40,0xa2,0x1b,0xec,0x69,0xf9, - 0x3d,0x04,0x06,0x8f,0x68,0x8e,0xfe,0x9a,0x55,0xf0,0x86,0x64,0x36,0x7e,0xe5,0xf5, - 0x21,0x9f,0xd7,0x1c,0x8a,0x05,0xff,0x6c,0x33,0xf9,0x3f,0x8b,0xab,0xed,0x51,0xe1, - 0x02,0xef,0xf7,0x9d,0x28,0x24,0x85,0x57,0x34,0xa9,0x9f,0x7c,0xc6,0xe5,0x73,0xbf, - 0x9b,0x3b,0xca,0xa6,0xe0,0x9f,0x4a,0xfa,0x14,0x39,0x4b,0xbb,0x79,0xfd,0x10,0xb2, - 0x81,0xd7,0xc7,0x36,0xcb,0x02,0xe0,0xaf,0xea,0x79,0xc6,0x9c,0x78,0xcf,0xe4,0x7a, - 0x42,0xa2,0x3e,0xb6,0x1f,0x57,0xaf,0x57,0xdb,0x23,0xad,0xe6,0x30,0x4f,0xe2,0x0c, - 0x0d,0x9e,0x21,0xf8,0x0a,0xec,0xb1,0x3b,0xef,0x44,0x20,0x34,0x05,0xff,0xc0,0x03, - 0xd5,0xd1,0x04,0xda,0x79,0x80,0xcf,0x77,0x4b,0x07,0x95,0x12,0xcd,0x65,0x5e,0xd1, - 0xda,0x39,0x10,0xba,0x63,0x8a,0xff,0xc7,0xa7,0x49,0xdb,0xb3,0xcd,0xc1,0x8a,0x4d, - 0x51,0xf1,0x96,0xc2,0x51,0xb1,0x72,0x25,0xc7,0x6f,0xea,0x28,0xf3,0xd6,0xda,0x15, - 0xc4,0x3f,0x93,0xfa,0x77,0xdc,0xff,0xf3,0x6f,0x5b,0xc4,0x01,0x3a,0xaa,0x97,0x05, - 0x36,0xf1,0x32,0x08,0xa3,0x92,0xd9,0x3f,0x77,0x00,0x3e,0xc1,0x1d,0x32,0xa5,0x3e, - 0x64,0x62,0xd9,0xed,0x4c,0x0e,0xd1,0xbe,0x7c,0x4e,0x04,0x92,0x11,0x11,0x65,0x54, - 0x64,0xbb,0xd1,0x18,0x50,0x47,0x54,0x2f,0x49,0xad,0x0f,0x29,0xf0,0xf8,0x97,0xa3, - 0x2d,0x53,0x27,0x8b,0x60,0x83,0x51,0xd2,0xdc,0xa2,0x17,0xb9,0xe8,0x07,0xd5,0xf3, - 0xa2,0x74,0xc0,0x3b,0xaa,0x98,0x85,0xe8,0xe3,0xd6,0xfa,0x48,0x89,0xfe,0xb0,0xfc, - 0x50,0xd8,0x59,0xa3,0xb6,0x1a,0x61,0x8f,0x6d,0x53,0xef,0x5e,0xbf,0x2b,0x9e,0xb1, - 0x20,0xfc,0x0a,0x4f,0x35,0x7d,0x51,0x56,0xa7,0xf4,0x07,0xe1,0xf6,0x4b,0xcb,0x1a, - 0x72,0x33,0x59,0x9b,0x91,0xa9,0xc9,0xf5,0x08,0x24,0x9e,0x16,0x8a,0x8f,0x66,0xd4, - 0xa3,0xd8,0x89,0x69,0x3b,0x34,0x39,0x94,0x5a,0x1f,0x49,0xe1,0xdd,0x60,0xe5,0xb1, - 0xad,0xb3,0x94,0x97,0x23,0x37,0xbd,0xeb,0x48,0xd4,0x47,0xba,0x2d,0x9e,0xb9,0x46, - 0x7c,0x13,0x2e,0x34,0xcd,0xd7,0x1d,0x75,0x29,0xfd,0x41,0x4c,0x79,0xab,0x35,0xc7, - 0xc4,0x26,0x3e,0xe0,0x6e,0x9f,0x21,0xb8,0x48,0x7c,0xda,0x3d,0x3c,0x22,0x76,0x91, - 0x6b,0x34,0x2b,0xfe,0xe1,0xf6,0xfb,0xa5,0x68,0x15,0xef,0x0f,0xbb,0x1f,0x96,0xfc, - 0xa8,0x64,0x60,0xe9,0x58,0x4b,0x81,0x76,0xb1,0xd7,0x67,0x16,0x0a,0x40,0x7c,0x75, - 0x4b,0x07,0x42,0xaf,0x7e,0x4b,0x7d,0xec,0xed,0xda,0x01,0xbd,0xb8,0x97,0x3e,0x44, - 0xb2,0xb4,0x46,0xbd,0xb8,0x2e,0xb3,0x9c,0xd8,0xb4,0x3d,0x0d,0xff,0x1c,0x92,0xcb, - 0xf1,0xf9,0xf7,0x29,0xbc,0x50,0xff,0xd4,0xfa,0x48,0x8a,0xdb,0xa0,0xc3,0xd9,0x6d, - 0xb0,0x5e,0x99,0x17,0x68,0x46,0xc3,0x2d,0xba,0x5f,0x2a,0xc6,0x17,0x27,0x67,0xb4, - 0x5f,0xc2,0x93,0xbc,0x3e,0x69,0x32,0xfe,0xa5,0x26,0xe4,0x0f,0xd0,0xf9,0x04,0x6c, - 0x8d,0x7c,0xe3,0xe1,0xc2,0x52,0xb4,0xd7,0xb8,0xbd,0xdf,0x27,0xec,0x0d,0xa8,0x31, - 0x5c,0xcf,0x64,0xfc,0xbd,0x2e,0xe1,0xef,0xd2,0xdc,0x23,0xe2,0x6e,0x40,0x45,0xdf, - 0x33,0xf7,0xb3,0x9c,0x62,0x6d,0xf4,0xee,0x07,0xce,0x38,0x18,0xf9,0x18,0x81,0xee, - 0xfe,0xb8,0x43,0x9f,0x76,0x6a,0x2a,0xfe,0xe1,0x49,0x5e,0xaf,0xc0,0x68,0xc8,0x1c, - 0xbc,0x27,0xe1,0x95,0x7e,0x47,0x47,0xcd,0x47,0x08,0x84,0x7c,0x81,0x4d,0xba,0xa5, - 0x3e,0x92,0xc1,0xeb,0x23,0xc1,0xe2,0x7a,0x7b,0xbd,0xb8,0x1a,0x81,0x50,0x15,0x9b, - 0xc6,0xb5,0xdb,0xe5,0x48,0xe9,0x0b,0x8e,0xfe,0x5b,0x66,0xf2,0xf8,0x0e,0x8f,0x30, - 0x26,0xf5,0x75,0x03,0xf0,0x78,0x56,0xc9,0xb0,0x2b,0x26,0x7e,0x83,0x8b,0x9d,0x28, - 0xca,0xcf,0xdf,0x43,0x17,0xb4,0x9f,0x95,0x5d,0x7e,0xb7,0xbf,0x21,0x5f,0x2f,0x74, - 0xe9,0xd7,0xf0,0x7f,0x4a,0x82,0xbc,0xbf,0x1e,0x44,0x5c,0x25,0x47,0x6f,0xe4,0xd5, - 0x03,0xba,0xd5,0x39,0x4e,0xb9,0x95,0xac,0x56,0x9f,0x61,0xce,0x86,0x3c,0x3d,0x3b, - 0xc5,0xff,0x23,0xec,0xcd,0x37,0xab,0x25,0x2c,0x3d,0xca,0xaa,0xdd,0x5a,0xcb,0x82, - 0x70,0x8f,0x7a,0x10,0xe1,0x41,0x4b,0x7e,0xd8,0x4e,0x1b,0x25,0x9d,0xd1,0x42,0x8b, - 0xfc,0x61,0x99,0xab,0xcd,0xea,0x07,0xf6,0x61,0x71,0xb6,0xde,0xc7,0x0d,0xcf,0x7f, - 0xe4,0xf5,0xe8,0xa0,0x6c,0xe6,0xb2,0xb0,0xbc,0x1a,0x8e,0x4b,0x68,0x7f,0x75,0x88, - 0xf1,0x54,0xff,0x4f,0x82,0xff,0x33,0x00,0x63,0xda,0xe2,0xac,0x9b,0x63,0xe2,0xb0, - 0x32,0x66,0x47,0x44,0xd4,0x3e,0xed,0x82,0x74,0x85,0x67,0x08,0xc6,0x2d,0xf8,0xe7, - 0x68,0xda,0x15,0xe5,0xaa,0xa7,0x54,0x47,0x58,0x3e,0xcc,0x4e,0x69,0xa5,0xc3,0x59, - 0xcb,0x45,0x0f,0xbc,0x8a,0x3b,0xca,0xd1,0x23,0xfa,0x60,0x2c,0xba,0x30,0x6e,0x3f, - 0x5a,0x60,0xe9,0x0f,0x8b,0xf8,0xe7,0x70,0xd0,0x19,0x89,0x74,0xa6,0xff,0x1e,0x36, - 0x04,0x9d,0x5a,0xa0,0x9b,0xe4,0x9b,0x44,0x1d,0x79,0x2d,0x2a,0xfa,0x6e,0x70,0xc6, - 0xe9,0x2e,0xe2,0x49,0xf6,0x87,0x05,0xb3,0x5e,0x44,0x63,0x04,0xfc,0x71,0x3f,0x53, - 0x9d,0x7d,0x77,0xc5,0x08,0xf4,0xed,0x54,0x51,0xf0,0x12,0xa7,0x1d,0xba,0x9d,0x85, - 0x46,0x9d,0x27,0x3b,0xd9,0x1f,0x36,0x2e,0x99,0xf1,0xaf,0x1d,0xae,0xdd,0x64,0xd0, - 0x6f,0x56,0x17,0x8f,0x1d,0x77,0x2a,0x3f,0xe3,0x27,0x74,0x3b,0x47,0x44,0x09,0xfe, - 0x55,0xf9,0xa4,0x7c,0xa8,0x9e,0xc1,0xe3,0xa7,0x5d,0xf1,0x93,0x91,0xec,0x4f,0xd9, - 0x29,0xbd,0x6b,0x38,0x4b,0x11,0x6f,0x49,0x94,0x51,0xdd,0x8e,0x88,0x65,0x98,0x95, - 0x71,0x7e,0x6f,0xd2,0xff,0x13,0x43,0xfc,0x73,0x89,0x2f,0x82,0x91,0x33,0x02,0x8b, - 0xd9,0xf3,0xf5,0x8e,0x8b,0xa2,0x41,0x78,0xe1,0xd0,0x69,0x3a,0x07,0x42,0xbc,0x31, - 0x8d,0x6e,0x89,0x7f,0xf5,0x27,0xf8,0x3f,0x51,0xb3,0x1a,0xed,0x31,0xed,0x50,0x3f, - 0xa2,0xa9,0x6f,0x91,0x13,0x8a,0xd9,0x98,0x86,0x77,0x4c,0xf3,0xf1,0x7c,0xf9,0x54, - 0xff,0xcf,0xf3,0xbc,0x1a,0xed,0x16,0x34,0xc2,0x9b,0x41,0x1d,0xac,0x8b,0xf9,0x0b, - 0x02,0x6f,0xf5,0xcf,0xe9,0xe1,0xf1,0x08,0xb3,0xe3,0x12,0xda,0x53,0x65,0x16,0xfe, - 0x0f,0x8f,0xbf,0xe3,0x7c,0x17,0x91,0xd5,0x96,0x15,0x21,0xee,0x1d,0xb5,0x29,0x22, - 0x57,0x4c,0x4f,0xa3,0x06,0x8f,0xc5,0xdd,0xba,0x5c,0x19,0xf6,0x26,0xfb,0xc3,0x2a, - 0x5f,0xb3,0x1f,0x40,0x18,0x20,0xd7,0x91,0x43,0x24,0x1c,0x29,0x18,0xa0,0x23,0xbc, - 0x5f,0x6a,0x74,0x76,0x5c,0x0e,0x90,0x59,0xd2,0xbe,0x2d,0xc5,0x7a,0xcb,0x9a,0x70, - 0x65,0xb2,0x3e,0x00,0xe5,0x6c,0x67,0x0f,0xc8,0xaa,0x08,0x9e,0xa3,0x60,0x16,0xca, - 0xbe,0x3b,0xf4,0x02,0x2f,0x33,0x92,0x33,0xcd,0x0e,0xc3,0x50,0xd9,0xef,0x58,0x20, - 0x67,0x27,0xeb,0x03,0xcc,0xe0,0xeb,0x73,0x98,0x6f,0x92,0x33,0xda,0x15,0x40,0xd8, - 0x13,0xff,0xc2,0x05,0xe9,0x63,0x09,0x97,0xe5,0x57,0xd3,0xc6,0x60,0x8c,0x54,0x99, - 0xfd,0xd1,0xa6,0xf0,0x7f,0x7c,0x7a,0x80,0xd5,0x18,0xca,0x09,0xde,0x28,0xd6,0x23, - 0x2e,0x10,0x4c,0xda,0x4f,0x9c,0xfb,0xdf,0x60,0x41,0x1f,0xae,0x98,0x2d,0x89,0x7f, - 0xf2,0x4c,0x3e,0x21,0xa3,0x5a,0xf6,0xdb,0xd0,0x88,0x68,0x87,0xa2,0x3c,0xc1,0x15, - 0xdb,0x61,0x98,0x85,0xf7,0x9f,0x85,0xfc,0xa3,0x91,0x7a,0xf1,0xa1,0x64,0xfd,0xb7, - 0x44,0x7d,0x24,0x9d,0x06,0xb2,0x5f,0x87,0xf5,0xec,0xeb,0xbc,0x0d,0xca,0x2c,0xe9, - 0xe9,0x75,0xf8,0xbe,0xcb,0xc9,0x3b,0xb0,0x8f,0xcd,0xd6,0x69,0x39,0x3e,0xfd,0xc4, - 0xfa,0xd7,0x99,0xfc,0x1f,0x77,0x98,0x66,0x38,0x4f,0xb1,0x46,0xb4,0x5e,0x5d,0x2a, - 0x99,0x93,0xc6,0x19,0x0e,0x27,0x1e,0x47,0xfb,0xe2,0x70,0x48,0xcd,0xe9,0x2c,0x27, - 0x7f,0x6b,0xe1,0x3f,0x9b,0x42,0x75,0x0b,0x1d,0x12,0x47,0xc2,0xa7,0x02,0xa5,0xcc, - 0x1e,0x2a,0x58,0x84,0x57,0xca,0x98,0x63,0x48,0x1c,0x14,0xae,0xf4,0x2d,0xe8,0xb2, - 0x0f,0x8a,0x96,0xfe,0xb0,0x89,0xf8,0x97,0x30,0xcf,0x34,0xc3,0x03,0x26,0x10,0x3a, - 0x6b,0xf0,0x0a,0x42,0x9c,0x08,0x94,0x70,0x0d,0xad,0x9d,0x52,0x1f,0xc0,0xac,0x0f, - 0xb9,0xb9,0xb1,0x17,0x7a,0xd4,0x2e,0xb3,0x7f,0x16,0x1c,0xd3,0xf1,0xca,0x4f,0x4c, - 0x45,0xef,0x35,0x5a,0x95,0x94,0xfe,0xb0,0xab,0xcc,0x32,0x8f,0xf2,0x13,0xce,0x01, - 0xe9,0x0d,0xcd,0x2c,0x94,0xfd,0x34,0x69,0xd6,0xdb,0x35,0x79,0x5b,0xa2,0x02,0x64, - 0xbd,0xeb,0x27,0x44,0x4f,0xc6,0xbf,0x04,0xde,0x16,0x0d,0xad,0xad,0xa8,0xf3,0x3d, - 0x84,0x55,0xce,0xb3,0x19,0x51,0x9b,0x59,0x1f,0x00,0x11,0x54,0xd8,0x9c,0x5f,0x4b, - 0xb7,0x58,0xfa,0xc3,0xf2,0xf8,0xd7,0x41,0x04,0x39,0xa6,0xb7,0x67,0xb3,0xe6,0xfc, - 0x12,0xde,0xff,0x51,0x68,0x30,0x0b,0x05,0xd8,0x4c,0x6a,0x10,0x07,0x06,0x1b,0x26, - 0xeb,0x03,0x24,0xe2,0x5f,0x1e,0x81,0x7b,0x1b,0x08,0xef,0x06,0xc2,0xed,0x2f,0xa9, - 0x6f,0xbc,0x50,0x00,0x1d,0x86,0x2e,0x8e,0x7f,0xb2,0x52,0xe2,0x5f,0xa3,0x5a,0x55, - 0xcf,0xcd,0xfd,0x05,0x66,0x7f,0x58,0x6d,0x9c,0xf6,0xe3,0xd3,0x96,0x71,0x47,0x90, - 0x59,0x31,0xe9,0x82,0xb5,0x3f,0x1a,0x77,0x7a,0xa8,0x95,0x41,0x47,0x30,0xe7,0x42, - 0xe4,0x95,0xf2,0xf9,0xb5,0x08,0x03,0x9e,0x65,0xaf,0x68,0xb8,0x3e,0xaf,0xc9,0x85, - 0x66,0xa9,0x01,0xfb,0x6b,0x62,0xba,0x35,0xfe,0x05,0xdd,0x7a,0x89,0x20,0x23,0xda, - 0x21,0x2c,0xe4,0xa4,0xf8,0x3c,0xdf,0x0a,0x47,0xd0,0x50,0x92,0x9b,0xb2,0x55,0x94, - 0x27,0x3e,0xa0,0x4d,0x24,0x6b,0x52,0xfe,0x98,0xf1,0xaf,0x3a,0x3c,0x74,0x79,0x9c, - 0xed,0x03,0x2b,0x79,0x18,0xeb,0x45,0x5e,0x76,0x1e,0xdf,0x37,0x6c,0x02,0xa1,0x50, - 0xdd,0x74,0x92,0x9d,0xe4,0xff,0x48,0x1c,0xff,0x94,0x04,0xcc,0x6a,0xe4,0xbb,0xc0, - 0xac,0x2e,0xb5,0x8a,0x36,0x4b,0x44,0x13,0xdb,0xc6,0x11,0x26,0x1a,0x32,0x49,0x7b, - 0x5f,0x9f,0x6e,0xc2,0x9e,0x90,0xa3,0xad,0xe0,0xe5,0xd0,0xfb,0x67,0xbc,0xf7,0x67, - 0xfd,0x44,0x3c,0xc7,0xf9,0xed,0x26,0x90,0x13,0x46,0x99,0x4f,0x9b,0x89,0xa6,0xeb, - 0xd4,0xf8,0x17,0xaf,0x97,0x75,0x0e,0xde,0x60,0x47,0xb4,0x4d,0x5b,0xc4,0x5e,0x36, - 0x0a,0x47,0xaa,0x1d,0xd9,0x8d,0x7c,0xe9,0x2a,0x56,0xdd,0x6c,0xad,0x0f,0x90,0xe0, - 0xff,0xf8,0xa6,0x2f,0x65,0x05,0xf9,0x85,0x7d,0x5a,0x57,0x2e,0xbe,0x6f,0x08,0xce, - 0x24,0x0a,0x25,0x21,0x34,0x62,0x3e,0xd5,0xde,0x2a,0x92,0x94,0xf8,0x17,0xa2,0x41, - 0x46,0xe3,0xe2,0x0f,0x60,0x63,0x60,0x81,0x6e,0x53,0xc9,0x6d,0xb0,0xd1,0x28,0x61, - 0x68,0xd1,0xbb,0xe0,0x88,0x80,0x47,0x2f,0x4e,0x36,0xa4,0xc6,0xbf,0x50,0xda,0x5c, - 0x7f,0x3d,0xae,0x46,0xcb,0xbb,0x85,0xbc,0x91,0xc1,0x17,0xd5,0x66,0x2e,0x9f,0x67, - 0xa2,0xe2,0xe6,0xbf,0xe2,0x12,0x69,0x12,0xff,0x98,0xf1,0x2f,0x98,0x37,0x98,0x77, - 0x26,0xfb,0xbf,0xdb,0xd6,0xc2,0x2d,0x86,0x6d,0x98,0x4c,0x87,0x26,0x5a,0x6c,0xdc, - 0xf8,0x3d,0x32,0x53,0xe2,0xd0,0x88,0xaa,0x61,0x7d,0x32,0x1f,0x9c,0xc7,0xbf,0x10, - 0xff,0x0c,0xba,0x03,0xe2,0x75,0xd2,0xcb,0x4d,0xb7,0x22,0xec,0x29,0x78,0x84,0xfc, - 0x3b,0x67,0x44,0x9f,0x91,0x4d,0x68,0xa4,0xba,0xeb,0x44,0x4b,0x7f,0xd8,0x04,0x1e, - 0x38,0x8a,0xfb,0x8d,0x97,0x8d,0x3a,0xa2,0x99,0x6d,0xbb,0xc7,0xc0,0xec,0x17,0x3f, - 0xc4,0x2b,0x42,0x43,0x6a,0x7f,0xd8,0xb6,0x23,0x14,0xed,0xf7,0x77,0x33,0x97,0xe7, - 0x94,0xd9,0x4e,0xb1,0xd2,0x10,0x02,0x89,0xcf,0xb9,0x47,0x28,0xee,0xe8,0x43,0xfd, - 0x75,0x29,0x3a,0x9f,0xab,0xb6,0x64,0x7c,0xbc,0x53,0x49,0xf8,0x9f,0x69,0x90,0xcc, - 0x64,0x4d,0x5a,0x7e,0x6d,0x66,0x3d,0x5a,0x4f,0x4d,0xc1,0x62,0x43,0xac,0x26,0x33, - 0x11,0x1a,0xdd,0x8a,0xa2,0x49,0xfc,0xb6,0xb5,0x3f,0xac,0x39,0x3f,0x63,0x98,0xe4, - 0xd2,0xb0,0x52,0xa0,0xd1,0x61,0x72,0x9a,0x7b,0x84,0x0c,0x59,0x0b,0x23,0x14,0x0c, - 0x15,0x68,0x29,0xfd,0x61,0x0b,0xcd,0xfa,0x48,0x25,0xfd,0x94,0xb7,0x25,0x0a,0x1b, - 0x2b,0xd7,0xdc,0x59,0x89,0xab,0x17,0xe6,0xf2,0xdc,0x15,0xe6,0x54,0xcc,0x42,0xcd, - 0x05,0x24,0x90,0x7c,0x9e,0x34,0xae,0xbf,0xaa,0xce,0x64,0xe6,0x85,0x25,0xed,0x84, - 0xd1,0xd5,0x67,0x3f,0x20,0x0e,0x84,0x8e,0x99,0xfa,0x4b,0x76,0x73,0xd5,0xc3,0x43, - 0xf3,0x45,0x93,0xeb,0xc9,0xa6,0x8f,0xaf,0x4f,0xb4,0xf1,0x3d,0xed,0x93,0xa0,0x89, - 0x7f,0xce,0xda,0x47,0x6e,0x37,0xfb,0x35,0xe0,0xfa,0x04,0x7d,0x92,0xe3,0x39,0x0b, - 0xfe,0x49,0xf0,0x7f,0xaa,0x8c,0xac,0x3e,0x71,0x4e,0xfa,0xab,0x91,0xd2,0x1e,0xfb, - 0xb0,0x5c,0x99,0x28,0x13,0x14,0xe5,0xfe,0x9f,0x68,0x29,0x38,0x42,0x22,0x9d,0xf4, - 0xff,0xf0,0xf8,0xd7,0xf3,0x30,0xcf,0xa0,0xad,0xed,0xb3,0xa1,0xd5,0x28,0xd0,0x3a, - 0x3d,0xa4,0x5d,0x3d,0xc8,0x4a,0x8c,0x3b,0x23,0xdc,0x9f,0x63,0x94,0x95,0xcb,0x1d, - 0xc4,0x35,0x15,0xff,0x18,0xb6,0x06,0xa2,0x86,0x36,0xa8,0x28,0x6d,0x62,0xbc,0x9e, - 0x33,0x6f,0x63,0x11,0x09,0x0f,0xd1,0x43,0xd4,0xb9,0x03,0x07,0xea,0xe4,0x7e,0xb3, - 0xe5,0x26,0xf8,0xf6,0x68,0xad,0x14,0xe2,0x31,0xd4,0x35,0x1a,0xcb,0x6e,0x82,0x18, - 0xdf,0x81,0xbc,0x50,0xd2,0x1e,0xe0,0x1c,0x23,0x42,0x26,0xfb,0xc3,0x12,0x8e,0x7f, - 0x50,0x0d,0x65,0xb1,0x69,0x85,0x9c,0x76,0xa8,0xd9,0x79,0xe3,0x8c,0x11,0xbe,0x3e, - 0xd1,0x82,0x21,0x38,0x6f,0x0a,0x22,0x19,0x26,0xfb,0xc3,0xb6,0xcf,0x18,0x4f,0xd2, - 0x31,0xc4,0x0b,0xb8,0x6d,0x16,0x6b,0x8e,0x7a,0xd1,0x2c,0x14,0xc0,0xaf,0x8c,0x29, - 0x97,0x95,0x45,0x66,0x7d,0xc8,0x64,0x7f,0x58,0x8e,0x9f,0xd7,0x99,0x45,0xd4,0x87, - 0xef,0x3b,0xd1,0xe4,0x7d,0xc5,0xde,0x27,0x3e,0xdc,0x70,0x92,0x79,0x23,0xad,0xe7, - 0xf2,0xaf,0xc0,0x29,0xb3,0xbe,0xc4,0xd4,0xf8,0x17,0x3c,0x90,0x68,0x02,0xd2,0x02, - 0x3b,0x4f,0xa2,0x34,0xb8,0x29,0xbe,0x81,0x39,0x5b,0x1d,0x7b,0xc9,0x03,0xb0,0x41, - 0x7d,0xa6,0xaf,0xa5,0xcb,0x76,0x4d,0xfc,0x8b,0xdb,0x17,0x06,0x6b,0x14,0xd4,0xbe, - 0xe6,0x08,0xb1,0x2b,0x11,0x41,0x0d,0x47,0x9c,0xa8,0x8f,0x36,0x50,0xf5,0xa8,0xec, - 0x09,0x87,0x2d,0xf9,0x5f,0x66,0xfc,0x8b,0x7b,0xcf,0xce,0x09,0x8d,0xe0,0xec,0x99, - 0x1b,0xb5,0xb9,0xa7,0x6d,0x08,0xa9,0x71,0x5b,0x27,0x59,0x0d,0x1b,0x4c,0x3e,0x95, - 0x85,0xff,0xac,0x99,0xf1,0xaf,0x12,0x4e,0xfa,0x1a,0x20,0xbc,0x2d,0x6c,0xe6,0x2e, - 0x84,0x25,0x4c,0xf0,0xc6,0x68,0xa7,0x78,0x12,0x0c,0xe8,0xe2,0x85,0xe5,0xa3,0xd7, - 0xfa,0x7f,0x86,0x6b,0x06,0x12,0x1b,0x63,0x44,0xdc,0xce,0xcf,0x17,0xaf,0x28,0xf5, - 0x30,0x5c,0x31,0x5b,0xab,0x14,0xac,0x49,0x8d,0x7f,0xe5,0xf1,0x7c,0x04,0x31,0x02, - 0x27,0x60,0x71,0x0f,0xc2,0xa4,0x21,0x68,0xd6,0x38,0xec,0xcc,0x19,0xba,0x6f,0x54, - 0x33,0xf9,0xd5,0xd7,0xc4,0xbf,0x0c,0xb9,0x3b,0x34,0x04,0x2d,0x6c,0x9e,0x21,0xdf, - 0x4a,0xc6,0xa0,0x39,0xd7,0xd9,0x46,0x75,0xf2,0xb1,0x76,0x48,0x2b,0x33,0xe4,0x23, - 0x30,0x25,0xfe,0xc5,0x9b,0x56,0x94,0xe3,0xd7,0x35,0xab,0xf1,0x4b,0xb8,0x2c,0x0d, - 0x4a,0x21,0xe4,0xc1,0x1d,0xa7,0x50,0xbb,0xa8,0x46,0x4b,0x8c,0x4d,0x89,0x7f,0xe9, - 0x66,0x53,0x8c,0x37,0xd9,0x63,0x7a,0xf1,0xd0,0x8d,0xdf,0x26,0xef,0x90,0x4d,0x90, - 0xaf,0xba,0x02,0xce,0x77,0xe0,0x40,0xec,0x49,0xfe,0xab,0x29,0xf1,0x2f,0xbd,0x92, - 0x17,0x41,0xda,0x10,0xfe,0x75,0x67,0xe5,0xa0,0x83,0x92,0x93,0x5a,0x8f,0x1a,0xdb, - 0x6d,0x9f,0x27,0x9e,0x94,0xce,0xbb,0x62,0xbd,0x8e,0x3d,0xb2,0x25,0xfe,0x95,0x39, - 0xb1,0x3e,0x05,0x63,0xda,0xc7,0x50,0x75,0xda,0x11,0x17,0xc6,0x94,0xa7,0x9d,0x55, - 0xec,0xc6,0xa3,0x35,0x63,0xda,0xe7,0xea,0xf3,0xbc,0xf4,0x68,0xaa,0xff,0x87,0x93, - 0xc0,0x33,0x79,0xbf,0x9e,0x13,0x70,0xe8,0xa4,0x7d,0x9b,0xf8,0x1d,0xe3,0x7c,0x38, - 0x1d,0xc2,0x0c,0x3f,0x44,0x17,0xfe,0x6a,0xd3,0xd4,0xfa,0xd8,0xcf,0x9b,0x24,0xe7, - 0xf4,0x5e,0x14,0x23,0x1c,0xff,0xd8,0xee,0x57,0xf7,0xc3,0xad,0x20,0x6b,0x36,0xde, - 0x7a,0x72,0x6e,0xcf,0x35,0xfd,0x41,0x1e,0x33,0xf3,0xbf,0xc8,0x9b,0xb0,0x89,0xcd, - 0x1e,0xcc,0x58,0x4e,0x66,0xb1,0x03,0x46,0xbe,0x2a,0xaf,0xf6,0xce,0xa2,0x4f,0xb0, - 0x1d,0x66,0x7f,0x90,0xc9,0x7c,0x19,0xee,0xff,0x39,0x0c,0x2e,0x43,0xe4,0x7c,0x86, - 0x16,0x98,0x63,0xfc,0x4d,0x05,0x59,0x2d,0xed,0x85,0xc2,0x75,0xb2,0xce,0xf1,0xa4, - 0x5a,0x64,0xb4,0x4c,0xad,0x8f,0xfd,0x66,0xa2,0xe9,0xf6,0x08,0xe3,0x6d,0x41,0x9a, - 0x3f,0x12,0x5d,0x70,0xc5,0x28,0x8d,0x65,0x0d,0xf2,0x42,0x49,0x28,0x7f,0x96,0xe9, - 0x05,0x53,0xea,0x63,0xc3,0x7e,0x48,0xb4,0x85,0xad,0xae,0xc0,0xbf,0x10,0x51,0x43, - 0xa9,0x3c,0x42,0x54,0x73,0x56,0x18,0xb9,0xf7,0x3f,0xa8,0x8f,0x7d,0xf3,0x4f,0x78, - 0x9a,0x0f,0x73,0x6a,0xf6,0x2d,0x05,0x03,0x70,0xa7,0x56,0xa9,0xdd,0x13,0x15,0x57, - 0x49,0xa3,0x66,0xa0,0x87,0x4c,0xf1,0xff,0x68,0x26,0xda,0x19,0x20,0xcd,0x3b,0xda, - 0xb5,0x4c,0xb3,0xf0,0x32,0xab,0xe0,0x6e,0x87,0xd9,0xf6,0x3d,0x5a,0xd9,0x9f,0xa9, - 0x8f,0x44,0x9d,0xe3,0x69,0x4a,0x6a,0x91,0x76,0x3d,0x0e,0x94,0x5d,0x50,0x72,0x3a, - 0x2f,0x4a,0x0a,0x6b,0x0f,0x83,0xe9,0xaf,0x98,0xe2,0xff,0x41,0x90,0x23,0x8f,0x57, - 0x43,0x0a,0x0a,0x4a,0xd9,0x8b,0x30,0x5f,0xa8,0x0b,0x96,0xf3,0x46,0x69,0x07,0xb5, - 0x8e,0x60,0xf9,0x82,0x29,0xf5,0xb1,0xbb,0x71,0xbf,0x2e,0x49,0x54,0x43,0x2a,0x87, - 0x9b,0xf8,0x60,0x30,0xdd,0x07,0x4b,0x81,0x37,0x92,0x33,0xf9,0x3f,0xd6,0xfa,0xd8, - 0x99,0xe3,0x20,0x27,0x2a,0xf2,0xb2,0xd8,0x65,0xc1,0x79,0x41,0xb4,0x4f,0x7f,0x67, - 0x12,0xa1,0x0b,0xc6,0x7f,0xd5,0x6f,0x8d,0x7f,0x99,0xf3,0xbd,0xd5,0x78,0xb1,0xd0, - 0x78,0x51,0xf1,0xde,0x65,0xef,0xc7,0x8d,0xf4,0x0a,0x54,0x69,0x33,0x37,0xcb,0x0b, - 0xf2,0x2e,0xa7,0x7b,0x6b,0xed,0x6d,0x56,0xfc,0x03,0xdc,0xff,0xd3,0x8e,0x47,0x8b, - 0xe4,0x1b,0x11,0xb5,0x3d,0x0f,0x05,0xe9,0x59,0x88,0x40,0x09,0x31,0xfb,0xa3,0x75, - 0xa9,0x4e,0xea,0x32,0xa6,0xc4,0xbf,0x0e,0xbb,0x54,0x9e,0x66,0xd2,0x04,0x28,0x7f, - 0xfc,0x75,0x8a,0xff,0x45,0xb5,0x01,0xdc,0xb5,0x54,0xf1,0xe3,0xfb,0xba,0x76,0x04, - 0x5c,0xaf,0x91,0xa9,0xfe,0x1f,0xbe,0x9e,0x77,0x3c,0xe5,0x6c,0x10,0x54,0x5e,0xe8, - 0x7e,0xc0,0xd6,0x9c,0xb6,0xba,0xd6,0x95,0x4b,0xdc,0xc2,0x41,0xc8,0xd7,0xf2,0xfa, - 0xad,0xf1,0x2f,0x9e,0xff,0x65,0x96,0x3d,0x97,0x9f,0xcc,0xe3,0xfc,0x1f,0x33,0x4c, - 0x76,0x4c,0x7b,0x60,0x65,0x64,0xa2,0x22,0xba,0x5d,0x29,0x98,0xe2,0xff,0x49,0x34, - 0x85,0xc1,0xaf,0x0f,0x3c,0x51,0x8e,0x87,0x41,0x05,0x44,0x44,0x8f,0x8b,0x13,0xae, - 0x42,0x39,0xc5,0xff,0x23,0x8d,0xfb,0xdf,0x76,0xc0,0x08,0xf5,0x0a,0x76,0xd6,0x10, - 0xe7,0x85,0x49,0xf3,0x10,0x7f,0xc6,0xd5,0x41,0xe6,0xe5,0xfc,0x1f,0x4b,0xfc,0xeb, - 0x76,0x04,0x39,0xbc,0x3e,0x2d,0xef,0xe6,0x72,0x04,0xda,0x99,0x6b,0x40,0xec,0x44, - 0x74,0xf5,0x0f,0x51,0x59,0xf7,0x5f,0x84,0x43,0x46,0x3b,0xa3,0x7a,0x4a,0x7f,0xb4, - 0x04,0xfe,0xc1,0xfd,0xb0,0xdb,0x8c,0x3e,0x64,0x94,0x93,0x21,0xda,0x55,0xef,0xe6, - 0x2b,0x76,0x4a,0xdb,0xa1,0xa8,0xf1,0xe6,0xf2,0xf4,0xbb,0xae,0xf1,0xff,0x2c,0xa9, - 0x27,0x6f,0x0b,0xcf,0x83,0xda,0x97,0xc7,0xf3,0xa7,0x0e,0xc0,0x77,0xb4,0x96,0x87, - 0xf0,0xca,0x01,0xd8,0xd1,0x9f,0xf1,0x3d,0x62,0xe9,0x8f,0x06,0x3c,0xfe,0x55,0x6c, - 0x76,0x03,0x89,0xfd,0xa9,0x61,0xfa,0xa0,0x7d,0x79,0xce,0x3b,0xea,0x05,0xf3,0x4a, - 0xc1,0x3b,0x70,0x8e,0x95,0xea,0xc5,0x83,0xd6,0xfe,0x68,0x66,0xbf,0x54,0xde,0x1f, - 0xa4,0x80,0x47,0xcf,0xab,0x5e,0x72,0x44,0x73,0x7e,0x0e,0x97,0x08,0x4a,0xe0,0xfd, - 0x05,0x43,0xa6,0xab,0x36,0x4b,0x4f,0xe9,0x0f,0x72,0x85,0xf3,0x7f,0x50,0x49,0xe5, - 0x5f,0x09,0xed,0x42,0xb3,0x7d,0x69,0x67,0x81,0x2f,0x74,0x2a,0x3a,0x2f,0xe4,0x18, - 0x6b,0xf4,0x69,0x2f,0x23,0x22,0x5a,0x7a,0xa6,0x20,0xb5,0x3e,0xf6,0x78,0xfe,0xe9, - 0x49,0x6d,0x3d,0x2b,0x1e,0xa4,0x5f,0x20,0x33,0xe1,0x29,0xad,0xb8,0x0e,0xdf,0x77, - 0x1b,0x3c,0x0d,0x5f,0xd0,0xe8,0xdf,0x59,0xfd,0x3f,0x0a,0xe7,0xff,0x98,0xf3,0x7f, - 0x0b,0xfb,0x54,0x77,0x1f,0x3d,0xaa,0x2e,0x95,0xd6,0xd1,0xe2,0x3e,0xbc,0x32,0x13, - 0xd6,0xc1,0x6c,0xc8,0x08,0x4c,0xe9,0x0f,0xd2,0x05,0x3a,0xcf,0xa7,0x1b,0x12,0xb6, - 0xe1,0xc2,0x06,0xec,0xca,0x52,0xb4,0x6f,0xed,0x47,0x51,0x6d,0xb5,0xc2,0xce,0xc0, - 0x2f,0x20,0x03,0xa6,0xf6,0x87,0x15,0x78,0x34,0x87,0x8c,0x29,0x87,0x50,0xf0,0x4a, - 0x5e,0xf2,0xb0,0x12,0x66,0x6e,0x45,0x1e,0x41,0x7b,0xe4,0x04,0x94,0x99,0xfd,0x05, - 0x52,0xfc,0x3f,0x23,0x89,0x26,0x29,0x43,0xf0,0x01,0xd7,0x5f,0x4f,0xc9,0x78,0x07, - 0xed,0x91,0xaf,0xa0,0x86,0xfa,0xd0,0xec,0x0f,0x92,0x75,0x4d,0x7d,0x6c,0x28,0x35, - 0x6e,0x1e,0x13,0x79,0x20,0x6c,0xbe,0x61,0x1f,0x43,0x0d,0x78,0x0a,0x4a,0xb5,0x47, - 0x63,0x8d,0x0b,0xe0,0x94,0x52,0x6a,0x64,0xc6,0x65,0x48,0x89,0x7f,0x75,0x2b,0xe3, - 0xf9,0xd7,0x68,0x4f,0x19,0x91,0xdd,0x28,0xc6,0xdf,0x34,0x9c,0x21,0x77,0xcc,0x5f, - 0xa2,0x6c,0x68,0x70,0x1a,0xd4,0x45,0xd4,0xd4,0xfe,0xb0,0x89,0x26,0x20,0xbb,0x79, - 0xbd,0x44,0xc3,0x15,0xb5,0x2d,0xe5,0x6d,0x40,0xbf,0x8e,0x40,0xe8,0x9b,0x68,0xe1, - 0x3a,0xe3,0x79,0x5d,0x24,0x64,0xf5,0xff,0x48,0x3c,0xa9,0xd9,0x8c,0x76,0x85,0x3b, - 0xd4,0xa3,0x14,0xd2,0x97,0xc2,0x16,0x49,0xf5,0xff,0x8d,0xc7,0xc6,0x1b,0xd3,0x84, - 0x78,0xa9,0xc9,0x64,0xfe,0x29,0xaf,0x8f,0xfd,0x09,0x77,0xda,0xc7,0xc4,0x7f,0x91, - 0x22,0xdf,0x2b,0xed,0x6f,0x7d,0x4c,0x7c,0x58,0x39,0x0e,0xde,0x80,0xfd,0x13,0x71, - 0x15,0x3d,0xce,0xf9,0x93,0x7a,0xa3,0x96,0x52,0x1f,0x3b,0xd1,0x1f,0x6d,0xda,0x98, - 0x3e,0xa6,0xcd,0x3a,0xee,0xa8,0x11,0x2b,0xe1,0x08,0xf9,0xc5,0x5d,0xf7,0x9c,0xaf, - 0x39,0x9d,0x50,0x6d,0x7a,0x4a,0x7f,0x34,0x1e,0xff,0xda,0x7b,0xd2,0x7d,0x5e,0xbc, - 0x22,0x5d,0x26,0x0b,0x8d,0xcc,0xfe,0x82,0x61,0x78,0x7b,0x7e,0x29,0xb4,0xf6,0x89, - 0xc3,0xc6,0xab,0x6c,0xef,0x9f,0xc1,0x3f,0xac,0xe0,0x0c,0x1d,0x4b,0xff,0x08,0x1e, - 0x57,0x9d,0x06,0x8a,0xd9,0x8f,0x20,0x52,0x7f,0x28,0x8f,0x46,0xc8,0x59,0xa3,0x85, - 0x39,0x11,0x1a,0x39,0xf5,0x29,0xf8,0x47,0xed,0xa7,0xf3,0xc9,0xc9,0xbc,0x9f,0xd1, - 0x42,0xfd,0x2e,0x05,0xe5,0x67,0x14,0xd4,0x74,0x1b,0x2e,0x56,0x22,0xbf,0x29,0x46, - 0xc8,0xf4,0x54,0xfc,0x63,0x16,0xc1,0x1e,0x82,0x9f,0xe2,0xc6,0x41,0x7b,0x6d,0x08, - 0xad,0x88,0x39,0x2b,0xef,0xea,0x6c,0x3f,0x67,0x32,0xac,0xe4,0x58,0xba,0x05,0xff, - 0x98,0xf5,0x42,0x79,0x12,0x1f,0x7e,0xaf,0xcb,0xb0,0x30,0x9e,0xb5,0x4d,0x1c,0x85, - 0x37,0x0c,0x6f,0x7d,0x56,0x54,0xfc,0x83,0x89,0x88,0x70,0xab,0x4c,0xe5,0xff,0x2c, - 0xe6,0x4d,0xd3,0xc6,0xe0,0xb2,0x52,0xd5,0x9f,0xf9,0xb6,0xe9,0x56,0xbd,0x8d,0x15, - 0xf7,0xd7,0x9c,0x54,0xaf,0xfe,0xb9,0xfe,0x68,0x3c,0x08,0x3b,0x33,0x26,0xae,0xd6, - 0x2e,0xf1,0x40,0x49,0x54,0x9c,0x0b,0x7d,0xdc,0x3e,0xfd,0x51,0xcd,0x59,0x18,0xbf, - 0x7f,0x6a,0xfc,0x6b,0x2f,0xc7,0xcf,0xe7,0xa7,0x3d,0x80,0x07,0xa1,0xa4,0x41,0x8b, - 0x92,0x08,0x9c,0x61,0xff,0x18,0x12,0xbb,0xef,0xfd,0x03,0x7b,0xc1,0xc4,0x6f,0x39, - 0x5d,0x56,0xfc,0xc3,0xd3,0x2e,0x8c,0x80,0x17,0xb5,0xf3,0x1e,0x52,0xc2,0xdb,0x52, - 0x4b,0xd2,0x06,0x94,0xec,0xa2,0x8b,0x1c,0xa7,0x5b,0x13,0xeb,0x93,0x12,0xff,0x12, - 0xcc,0x78,0xd0,0xf7,0xc9,0x2c,0xed,0x00,0x9b,0x37,0xbc,0x6d,0x39,0x79,0x22,0xf0, - 0x58,0x74,0x85,0x2a,0xaf,0x71,0xbe,0x6e,0xb6,0x12,0x33,0xf3,0xa1,0x26,0xee,0x6f, - 0xe2,0x1f,0x7c,0x7e,0xee,0x86,0xc5,0x41,0x25,0xca,0xe7,0x1c,0x89,0xf4,0xe4,0xa9, - 0x7e,0x87,0x50,0xd3,0x43,0x7e,0x2d,0x79,0xa6,0xd4,0xc7,0x36,0xf9,0x3f,0x37,0x1b, - 0xf3,0x2e,0x34,0x8e,0x09,0x57,0x95,0xca,0xde,0x69,0xfd,0xf2,0xc3,0x08,0x9b,0xab, - 0xb4,0x9b,0x87,0x6b,0x2e,0xc0,0x9f,0x14,0x33,0xff,0x6b,0x2a,0xff,0xc7,0xf7,0x9a, - 0xa3,0x6c,0x49,0x96,0x74,0x8c,0x78,0x7b,0xed,0xdd,0x35,0xdb,0xe1,0x15,0x26,0x32, - 0x37,0x22,0x0a,0xb2,0xe4,0xda,0xfe,0x68,0x28,0x7f,0xa4,0xe2,0x33,0x2d,0x28,0x3d, - 0x94,0xa7,0x21,0xbf,0x07,0xea,0x57,0xe6,0x29,0xeb,0x25,0xb3,0x51,0xda,0xdb,0x09, - 0xc3,0xea,0x9a,0xfe,0x20,0x3c,0xa9,0x6d,0x0d,0xf9,0x1a,0xbe,0xdd,0xec,0x10,0x2d, - 0x27,0xb3,0x48,0x83,0x91,0x1f,0xa2,0x4b,0xc8,0xd1,0x44,0xa3,0xb4,0x6b,0xfa,0x83, - 0x8c,0xfb,0xf3,0xa1,0x3d,0x50,0x68,0x04,0xca,0x89,0xcc,0x1a,0x8e,0x85,0xea,0x22, - 0x1e,0xf2,0x87,0x35,0x8d,0x70,0x6d,0x7f,0x34,0xb8,0x28,0x96,0x71,0xfc,0x53,0x27, - 0xbd,0x04,0x0b,0x99,0xfb,0x19,0xf1,0x30,0x9c,0xd2,0x76,0x76,0xa2,0xd9,0x35,0x2a, - 0x99,0x8d,0xd2,0xae,0xe9,0x0f,0x02,0x09,0xb6,0x33,0x0e,0x0e,0xa1,0x62,0x5a,0x12, - 0xd7,0xcc,0x2b,0x11,0xb3,0x82,0xdf,0x2c,0xee,0x18,0x99,0x82,0x7f,0x50,0xdf,0xb9, - 0xdb,0xe4,0x42,0x54,0x73,0x26,0x2d,0xe4,0x25,0x72,0x8c,0x55,0x86,0x68,0x1b,0x4f, - 0x04,0x93,0xae,0xed,0x8f,0x66,0x3a,0x19,0xfa,0xa2,0xe1,0x42,0xe5,0x71,0x28,0xe0, - 0xd1,0xae,0x81,0xbc,0x37,0x22,0x25,0x75,0xf4,0x39,0xf2,0x87,0x09,0x62,0xf3,0x35, - 0xf1,0x2f,0xfc,0xac,0xc0,0x07,0x21,0x1e,0xf6,0x1a,0xda,0xde,0x3c,0xbd,0xe4,0xf6, - 0x0d,0x51,0xf2,0x9e,0xd4,0x2c,0xf0,0x88,0x98,0xf3,0x9a,0xf8,0x17,0x0f,0x72,0x49, - 0xf4,0x71,0xce,0x7f,0xce,0x25,0xbd,0x74,0xb3,0x1f,0xaf,0x78,0x4c,0xc7,0xc8,0x35, - 0xfd,0xd1,0x12,0xf1,0xaf,0x00,0x9b,0xa6,0xc2,0x30,0xbe,0xd6,0x52,0x26,0x70,0x20, - 0xf4,0x08,0xea,0x58,0x33,0x11,0x6c,0xd6,0xd4,0xfe,0x68,0x03,0xa8,0xd6,0xb3,0x82, - 0x8e,0xb6,0x69,0xe3,0x44,0x68,0xb3,0x2d,0x6c,0xed,0xcd,0x3c,0xbe,0x73,0x79,0x5c, - 0xbf,0x5f,0xd3,0x1f,0xc4,0xa7,0xcd,0x0c,0xf2,0x6a,0xa2,0x9e,0xd2,0xa5,0xf6,0x68, - 0x63,0x99,0xfe,0x4a,0xc8,0x2c,0x8b,0x7d,0x81,0x8d,0x43,0xa9,0xd4,0xfe,0x20,0x83, - 0x50,0x42,0x27,0xa2,0x5d,0xdb,0x8b,0x11,0x08,0xc1,0x86,0x15,0x88,0x7f,0x58,0x76, - 0x7c,0x07,0xa7,0x06,0x5d,0xd3,0x1f,0x0d,0xdf,0xf7,0x5e,0x6a,0xd2,0x7e,0x40,0xd5, - 0xb6,0x29,0x61,0xc9,0x6c,0x94,0x66,0x53,0x48,0x6f,0xef,0x1e,0x58,0x3d,0xa5,0x3f, - 0x1a,0xe2,0x9f,0x5d,0xb0,0xba,0xda,0x84,0x31,0x7b,0xa8,0xb3,0x96,0xfb,0xd3,0x10, - 0x58,0x96,0x04,0x8a,0x70,0x61,0xd9,0x44,0xbf,0xb9,0x24,0xfe,0x49,0xf8,0x7f,0xb4, - 0x40,0xb4,0xa6,0x03,0x15,0x71,0xa2,0x11,0x1e,0x41,0xfb,0x7d,0x39,0x4f,0x84,0xc7, - 0x2f,0xe2,0xbb,0xa6,0x3f,0x2c,0xf0,0xb4,0xf7,0x79,0x26,0x3b,0x28,0xfa,0x5c,0x68, - 0x9e,0x62,0x3a,0x3a,0x2a,0xb5,0xcc,0xb6,0x49,0xfc,0x73,0x4d,0x7f,0x10,0x1f,0xd8, - 0xc3,0xdc,0xdb,0xa3,0x79,0xaf,0x1b,0xe7,0x9f,0x23,0xec,0x89,0x88,0x67,0xb5,0x3e, - 0xb8,0xa6,0x3f,0xda,0xb8,0xff,0x67,0x48,0xec,0x64,0x87,0xa0,0x20,0x9a,0xa9,0x93, - 0x0f,0x60,0xa3,0xf1,0xfb,0x36,0x97,0x4e,0x2e,0x72,0x46,0x34,0x93,0x75,0x71,0xc3, - 0x35,0xf8,0xc7,0xe5,0x21,0xf7,0xf0,0xee,0x30,0xf1,0xeb,0x3d,0xf8,0x76,0x0d,0x77, - 0xa9,0xf5,0x80,0xfb,0xa1,0xb1,0xf1,0xda,0xfe,0x68,0x09,0xfc,0x43,0xd7,0x6c,0x69, - 0x83,0xe7,0xd5,0x02,0x76,0x7d,0xbd,0xb3,0x57,0x5d,0x6f,0xe4,0xfb,0x69,0x3d,0x79, - 0x47,0x18,0x3f,0xbf,0x9d,0xd6,0xf8,0x17,0x9e,0xdf,0xca,0x01,0x3b,0xef,0x8f,0xf6, - 0x27,0xa3,0x34,0x9e,0xf9,0x83,0x9c,0xd7,0xc9,0x49,0x56,0x10,0xb2,0xaf,0x69,0xfc, - 0x7c,0xa2,0x75,0x5a,0x6a,0x7f,0x10,0x94,0x27,0x27,0xe7,0x31,0x5c,0x8d,0x4f,0x13, - 0x66,0xe9,0x00,0xb7,0xdf,0x79,0xc6,0xdc,0x85,0x04,0x35,0x28,0x36,0x05,0xff,0xf0, - 0x6a,0xd8,0xf6,0xc1,0x69,0xff,0xa8,0x5d,0x8d,0xf1,0x6e,0x0e,0x8d,0x57,0x94,0x04, - 0x22,0x32,0xeb,0x43,0xa2,0x69,0x3f,0x6a,0xe5,0x3f,0x27,0xf8,0x87,0xbc,0xbb,0x47, - 0x2e,0x2f,0xfc,0xf8,0x92,0x49,0x3b,0x7c,0x3e,0x17,0x11,0xce,0xf7,0xcc,0xc6,0xf7, - 0xc5,0x53,0xfb,0xa3,0x8d,0xfb,0x8b,0x42,0xb6,0x5c,0xfb,0x81,0x67,0x78,0xf5,0x6f, - 0xf2,0xb6,0xba,0x0f,0x76,0x68,0xf2,0xd9,0x70,0xee,0x38,0x95,0x31,0xdd,0x98,0x1a, - 0xff,0xe2,0xfc,0x0d,0xc9,0xc4,0x93,0x78,0xac,0x4e,0xa9,0x7b,0x99,0x33,0x2c,0xdb, - 0x89,0xcd,0x18,0xef,0x37,0x97,0xc4,0x3f,0xbb,0x4d,0x7f,0x57,0x95,0x81,0xbb,0xdd, - 0x0d,0x9f,0x1a,0x5d,0x71,0xf7,0xb0,0xf8,0x11,0x8c,0x9e,0xf1,0x3a,0x1d,0x11,0xb9, - 0x80,0x70,0x6a,0xa5,0x63,0x2a,0xfe,0xe1,0xf6,0xfe,0x3c,0x8f,0xd8,0x01,0x97,0xf2, - 0x7d,0x3d,0xcb,0xcc,0xfc,0x77,0x5e,0xb1,0xb6,0xa9,0x71,0x10,0xfe,0xaf,0x84,0xbc, - 0x4d,0xc1,0x3f,0x02,0xea,0xbb,0x1e,0x34,0x4b,0x2b,0xf1,0x0f,0x63,0xf5,0xf6,0x61, - 0xb1,0x0d,0x7a,0x79,0xd8,0xcb,0x92,0xef,0x9c,0xda,0x1f,0xe4,0x30,0xcc,0xeb,0x89, - 0x44,0x48,0x07,0x3c,0x2f,0x15,0x2c,0xcf,0x8c,0x91,0x73,0xa8,0x7f,0x57,0x7a,0x68, - 0x1b,0x79,0x77,0xdc,0x35,0x61,0xed,0x0f,0x3b,0x6e,0xef,0xd3,0xb0,0xbf,0x70,0x5c, - 0x71,0x67,0x0f,0x69,0xcd,0x0d,0xce,0x18,0xe2,0x81,0x89,0xf9,0xd7,0xf0,0x9f,0xdd, - 0x5c,0xcd,0x35,0xe1,0x6f,0x55,0xee,0x6f,0x3c,0x49,0x78,0x9b,0x78,0x0a,0xce,0x5e, - 0x61,0xdc,0x55,0x62,0xed,0x0f,0xcb,0x9f,0x67,0xb1,0x81,0xdb,0xbe,0xd0,0x2c,0x24, - 0xee,0x8e,0xe1,0x8b,0xf7,0xa1,0x05,0x64,0xe7,0x61,0xbe,0x4b,0x89,0xf7,0x9d,0xc2, - 0x7f,0xe6,0x49,0xee,0xdc,0xff,0xc3,0xdb,0x9e,0x66,0x0d,0xe7,0x70,0x47,0xd0,0x3c, - 0xf8,0x37,0x2d,0xf9,0xbe,0x56,0xfc,0xf3,0x8e,0xd9,0xbf,0xc6,0x3e,0x32,0x6d,0x16, - 0xbc,0xc0,0xb7,0xcd,0xa0,0xf8,0x1c,0xfc,0x2e,0x7b,0xbe,0x8a,0x3b,0x36,0x1b,0xc6, - 0x58,0x95,0xbe,0x74,0x24,0xc7,0x12,0xff,0x52,0xde,0x55,0xba,0x19,0x0f,0xb2,0x23, - 0xa8,0x8b,0xe0,0x60,0x09,0xac,0x9c,0xa9,0x6e,0xca,0x75,0xaa,0xb4,0x9b,0x14,0xc1, - 0xc1,0x86,0x92,0x38,0x0e,0x62,0xc9,0xf8,0x57,0xda,0x49,0xf3,0x35,0xa9,0x47,0x71, - 0x4b,0x2d,0x5c,0x9b,0xab,0xc4,0xae,0x6d,0x55,0xbf,0xdd,0x80,0x1b,0x03,0x50,0x22, - 0x95,0xf0,0xd2,0xac,0x5e,0x8b,0xff,0x47,0xe7,0x41,0xb4,0xf1,0xfb,0xf3,0x42,0x1f, - 0x2c,0xdb,0xcd,0x61,0x4f,0x3b,0x22,0x22,0xbc,0x3f,0x2b,0xe9,0x8b,0xc4,0x48,0x2c, - 0x89,0x4f,0xb8,0xff,0x47,0x30,0x97,0xc5,0x3d,0x8e,0x46,0x64,0x37,0xbc,0x05,0xdd, - 0x7a,0x6b,0x4c,0x9c,0xc3,0x2e,0x19,0xbe,0x90,0xfb,0x97,0x16,0xfc,0xa3,0x0b,0x31, - 0x18,0xa7,0x45,0xe1,0x80,0x9a,0x6c,0xf0,0x87,0xd1,0xbe,0xc0,0x15,0x1b,0x96,0x71, - 0xe9,0xa4,0x2a,0x4e,0x74,0x49,0xcd,0xff,0x7a,0x4b,0xf1,0x1a,0x99,0xdd,0xe2,0x6a, - 0x9e,0x7f,0x17,0x5f,0x16,0xc3,0x8d,0x7c,0x42,0xf1,0x36,0xd9,0x63,0x39,0x4f,0xf2, - 0x40,0x58,0xaf,0x7d,0x7f,0x8a,0xff,0x47,0xe5,0xfd,0x85,0x73,0xf1,0xeb,0x1f,0xe5, - 0x03,0x15,0xa5,0x65,0x25,0x6c,0x0a,0x5f,0xa7,0x67,0xf2,0x8e,0x30,0x2d,0xcc,0x1d, - 0x8f,0xf8,0xc4,0x7f,0x4c,0xf1,0xff,0x6c,0x65,0xbc,0x7e,0x42,0xf6,0x29,0x68,0x34, - 0x42,0x46,0x06,0x7e,0x59,0x7c,0x5f,0x89,0xe0,0xb2,0x30,0xad,0x91,0xb9,0x35,0x54, - 0xdc,0x9e,0x49,0x7d,0x17,0x17,0xbc,0xd0,0xca,0xf2,0x0b,0x5d,0x77,0xa5,0x7f,0xaa, - 0xb6,0xb6,0xaf,0xf0,0xdc,0x78,0x67,0x98,0x77,0x50,0x9d,0x5d,0x98,0x81,0x46,0xa1, - 0xb0,0xfe,0xc5,0xe2,0x01,0x3a,0x4a,0x1e,0x99,0x8c,0x7f,0xdd,0x85,0xf8,0xe7,0xd7, - 0xe0,0xe9,0xcd,0xe4,0xec,0xfa,0xc6,0x4e,0x4f,0x5f,0xa6,0x5a,0x60,0x87,0x17,0x48, - 0xe1,0x6e,0xbb,0x47,0x64,0x8c,0x07,0xc2,0x5a,0x0b,0x6b,0x92,0xf1,0x2f,0xff,0x4d, - 0xe6,0xfa,0x48,0x8e,0x17,0x12,0x6e,0x43,0x98,0x66,0xf0,0xfe,0xb0,0x66,0x7d,0x24, - 0xdc,0x51,0xcf,0x0b,0x8b,0x7b,0xfe,0xa1,0xde,0x12,0xff,0x7a,0x26,0xed,0x14,0xe7, - 0xef,0x99,0xeb,0x63,0x0e,0x1c,0xdd,0x72,0xb1,0x71,0x89,0x96,0xeb,0x76,0xee,0x11, - 0xba,0x04,0x95,0xf1,0xd6,0xf2,0x1a,0x92,0xc4,0x3f,0x9b,0xa3,0xbc,0x09,0xec,0x44, - 0xb9,0xb4,0x62,0x68,0x09,0x22,0x10,0x3a,0xa0,0x99,0x7c,0xc2,0xd3,0x1c,0x1a,0x71, - 0x09,0xd3,0x35,0x29,0xdf,0x18,0x1a,0xb1,0xeb,0xd9,0x3c,0x93,0xef,0x34,0x81,0x76, - 0x66,0xb5,0x1e,0xd0,0xbf,0xa3,0x67,0xac,0x21,0xaf,0xc3,0x81,0x48,0xf1,0x70,0x64, - 0x0d,0xa1,0x16,0xfc,0x63,0x98,0x65,0x57,0x23,0x70,0x1d,0x7e,0x08,0xae,0x0d,0x39, - 0x7f,0x83,0x47,0xe4,0xf1,0xa0,0xbd,0x1c,0xda,0xdb,0xe0,0xee,0xa7,0x0b,0xfc,0x3f, - 0x49,0xa9,0xff,0x73,0x14,0xc5,0x2c,0xd5,0x65,0x97,0x39,0x70,0x74,0x88,0x2e,0x7a, - 0x08,0x16,0xe9,0xbc,0x2d,0x1a,0x7c,0x0e,0x55,0xba,0xfd,0xdc,0x34,0x4b,0xfc,0x0b, - 0x86,0x09,0x2e,0x8b,0x52,0x62,0x88,0x9f,0x90,0xc4,0x46,0x6a,0x34,0x11,0xd1,0xcc, - 0x8d,0x4d,0xbc,0x82,0x34,0xf3,0x09,0xf3,0xc2,0x39,0xd6,0xf8,0x97,0xe9,0xff,0xa9, - 0x5b,0xba,0x19,0x8f,0x2d,0x0f,0x7b,0xd9,0x1f,0x9f,0xc6,0xfd,0x39,0xfb,0x27,0xe3, - 0x5f,0xdf,0x76,0x6c,0x4b,0xcd,0x7f,0xe7,0x24,0xdb,0x3a,0x94,0x36,0xef,0xb1,0x66, - 0x56,0x16,0xa4,0x3f,0x76,0x0e,0x40,0xb3,0xe2,0xfc,0x12,0xef,0xe8,0x21,0x1d,0x34, - 0x1b,0xc5,0x4e,0xc1,0x3f,0xbf,0x64,0x05,0x5a,0x46,0xff,0xbd,0x9f,0x93,0x47,0xa1, - 0xa0,0x36,0xaf,0x1f,0x15,0xf7,0x66,0xea,0xd4,0x6e,0x8c,0xa6,0x73,0x47,0xb4,0x53, - 0x93,0x37,0x3b,0x4f,0x59,0xea,0xff,0xe4,0x72,0x7b,0x36,0x98,0x77,0x3f,0xf9,0x77, - 0x58,0xcb,0xbe,0x51,0x4f,0xef,0x43,0x98,0xc4,0x1b,0xa3,0xa3,0x98,0x92,0xf0,0x7c, - 0x15,0x86,0x96,0xa0,0xbe,0x4b,0xc5,0x3f,0xb8,0xe7,0x32,0x21,0xc7,0x30,0xd5,0xae, - 0x5b,0x23,0x71,0x7a,0x66,0xbc,0x10,0x50,0xa2,0xfe,0x0c,0xab,0x49,0xe2,0x9f,0x33, - 0x9c,0xff,0x0c,0xcf,0x55,0x27,0xf4,0xfb,0x34,0x53,0x9b,0xbf,0x07,0xa3,0xd5,0xfc, - 0x58,0xa1,0x20,0xfa,0x61,0x82,0x08,0x94,0xca,0x7f,0xfe,0x10,0xaa,0x6a,0xb3,0xfa, - 0xc5,0x05,0x1a,0x77,0xfb,0xe0,0xa0,0x50,0xb9,0x5c,0x37,0x9f,0x4f,0xbb,0x00,0x3d, - 0x64,0x7e,0xb5,0x3d,0x68,0xf1,0xff,0xac,0x41,0xfc,0x13,0x91,0x10,0xff,0x84,0x89, - 0xca,0x22,0x1c,0x08,0x85,0xb3,0x39,0x11,0x9a,0xc0,0x12,0xe6,0x8f,0x73,0x89,0xc1, - 0x10,0x08,0x6d,0x4c,0xb7,0xe2,0x9f,0x1d,0xc4,0x5d,0x6d,0x53,0xc2,0x4d,0xca,0x0e, - 0xc9,0xed,0xa7,0xd1,0x70,0x9a,0xba,0x27,0x1f,0x12,0x7c,0xef,0x46,0x9e,0x61,0xb7, - 0xcd,0x12,0xff,0xe2,0xf8,0xa7,0x99,0xcb,0x73,0xc5,0xcf,0xdb,0xa8,0xd9,0xab,0x4d, - 0x60,0xb9,0x07,0x12,0x1e,0x36,0xd6,0x8c,0x42,0x1a,0xe7,0xaf,0x4b,0xc6,0xbf,0x66, - 0xf0,0x6e,0x2f,0x95,0x5a,0x49,0x34,0xa7,0x83,0xbc,0x0f,0xb3,0x34,0xbb,0x62,0x33, - 0x3f,0xeb,0x7d,0x9c,0xcf,0x43,0x7b,0xc0,0x1b,0x42,0xc4,0x9b,0xf4,0xff,0x0c,0x26, - 0xe2,0x5f,0x7e,0x47,0xb4,0xa5,0x50,0xe5,0xc0,0xb8,0x38,0x5a,0xc0,0x57,0xec,0xc8, - 0x0a,0x3e,0x1f,0xf5,0x1d,0xcf,0xff,0xca,0xb9,0xa6,0x3e,0x76,0xa2,0x2d,0x6f,0x9f, - 0x9a,0xa0,0x5d,0xc1,0xa0,0x5a,0x91,0x6d,0x37,0xf9,0xf6,0x9a,0x37,0x0f,0x81,0x90, - 0x25,0xfe,0x25,0x50,0x38,0xe4,0x9c,0xd7,0x6e,0x1f,0x20,0xe5,0xb0,0x91,0xce,0x6b, - 0x0f,0xf0,0xb0,0x57,0x56,0xa8,0x20,0x4a,0xe3,0xe4,0x38,0x22,0xa2,0x5b,0x19,0x0d, - 0x91,0x54,0xff,0xcf,0x1e,0xe6,0xee,0xcf,0x58,0x60,0x7b,0x94,0x87,0x69,0xfa,0xd4, - 0x72,0xd2,0xaa,0xec,0x4c,0x77,0x69,0x79,0x15,0xb8,0x3e,0xa8,0xc1,0x7b,0x69,0xb9, - 0xd3,0x36,0x05,0xff,0xcc,0x63,0x88,0x1f,0x12,0xc4,0x60,0x3a,0x90,0xbd,0xd1,0x98, - 0x06,0xf9,0x71,0xca,0x1d,0x41,0xcf,0x0b,0xb7,0x18,0xae,0x0b,0x44,0x9d,0x8c,0xd7, - 0x74,0x8e,0xf3,0x9f,0x33,0x07,0xc5,0x43,0xc0,0xcb,0x62,0x4b,0x6b,0x6c,0x4f,0x68, - 0x5f,0x67,0xb7,0x85,0xdc,0xcb,0xc5,0xd7,0xe1,0x4f,0x91,0xf9,0x67,0xed,0x01,0x39, - 0x19,0xff,0xb2,0xdd,0xb4,0x9b,0x5e,0x42,0x89,0x89,0xf8,0x27,0x84,0x82,0x1d,0xcf, - 0xa3,0x22,0x7e,0x87,0x5d,0x4a,0x1b,0xa7,0xf5,0x2e,0x5a,0x31,0x6e,0x2f,0x4c,0xac, - 0x0f,0xac,0x35,0xf1,0xcf,0x90,0x6d,0x34,0xe7,0x23,0x8d,0xa7,0x7d,0xd9,0xcf,0xa0, - 0x21,0x7f,0x95,0x2d,0x5a,0x6d,0x1f,0x44,0xfc,0xf3,0x27,0x56,0x3a,0x60,0xe7,0xfd, - 0xd1,0x26,0xd6,0xc7,0xc4,0x3f,0xb1,0xe2,0x75,0xf4,0xcb,0xe1,0x37,0xe1,0xf9,0x0f, - 0xe6,0xce,0xa1,0x2b,0x10,0xff,0xfc,0x52,0x52,0x7f,0x7e,0x57,0x88,0xc7,0xbf,0x94, - 0xb9,0x27,0xe9,0x83,0xd9,0x1f,0xa4,0xc6,0xbf,0x84,0xe2,0x00,0xfe,0xf6,0x6d,0xfd, - 0x79,0xcf,0x6c,0x2d,0x23,0x88,0xf3,0xff,0x55,0x99,0xab,0x35,0xf7,0x13,0x1e,0xb8, - 0x2f,0x30,0xf0,0x04,0x59,0xf1,0xcf,0x2b,0xea,0x5e,0xc3,0x9e,0xe7,0x92,0xc8,0x0b, - 0xb0,0x57,0x73,0x2b,0x19,0x0a,0x19,0x52,0x50,0x03,0x0e,0xe3,0x7e,0xcb,0x52,0xf7, - 0x14,0xba,0x34,0xb3,0x35,0xfc,0xe4,0xf3,0xcc,0xf8,0x37,0xf5,0x52,0xd4,0xd7,0x6f, - 0x7b,0x8e,0x9c,0xd3,0x46,0xa3,0x65,0xc3,0xc5,0x47,0x72,0x78,0x1a,0xce,0x0f,0xb4, - 0x4c,0x1d,0x2d,0xa6,0x4b,0xe0,0x8c,0xa3,0xa0,0x9e,0x82,0x7f,0x14,0x5f,0xd4,0x61, - 0x76,0x83,0xd5,0x2a,0x02,0x59,0x1d,0x3b,0x87,0xa4,0x4b,0xda,0x23,0xf7,0x65,0x75, - 0x88,0x43,0xdc,0x10,0xab,0x77,0x74,0x4f,0xf5,0xff,0x68,0x55,0x86,0xfb,0x4d,0xf1, - 0x3c,0x8a,0xf1,0x79,0x9c,0xd8,0x30,0x46,0x5e,0x35,0x4a,0x6b,0x1c,0x86,0xf0,0x3d, - 0x76,0x15,0x4a,0x8f,0x22,0x10,0x4a,0xc6,0xbf,0x18,0xc7,0x3f,0x82,0x3b,0x86,0xf8, - 0x1f,0xd1,0x8b,0x81,0x68,0x99,0x91,0x21,0x68,0xee,0x73,0x86,0xe4,0x8d,0xce,0x21, - 0x65,0xef,0xca,0x05,0xf5,0xb8,0xff,0xaf,0x89,0x7f,0x85,0xe6,0xea,0x47,0x3b,0x18, - 0x0f,0x7b,0xdd,0xd8,0x46,0x86,0x28,0xea,0xeb,0x7a,0x39,0x42,0x56,0xc1,0xe1,0x19, - 0xce,0xb3,0x81,0x6e,0xbf,0x9a,0x82,0x7f,0x4a,0x55,0x37,0x50,0xd5,0xdf,0xe7,0xda, - 0xab,0xae,0xce,0x90,0x55,0xef,0x49,0x10,0x40,0x0d,0xf0,0x46,0x21,0xa8,0xfa,0xe7, - 0x18,0xf8,0x7f,0xc8,0x64,0xfc,0x1d,0xcc,0xf8,0x57,0x25,0x14,0x33,0xb1,0x83,0x5d, - 0xd2,0x2a,0xfd,0x0e,0x86,0x62,0xf7,0x38,0x78,0xef,0x41,0xf9,0xb3,0x4a,0xba,0x04, - 0x5d,0xac,0x30,0x26,0x26,0xe3,0x5f,0x1c,0xff,0x5c,0xd2,0xaa,0xe0,0x1f,0x38,0xed, - 0xf9,0x52,0x1d,0xc2,0x42,0xa3,0x7a,0x0c,0x15,0x59,0x65,0x40,0xd6,0x4c,0x7e,0x4b, - 0xa2,0x3f,0x1a,0x4b,0xe2,0x9f,0x61,0xf6,0x8a,0x5a,0x0a,0x59,0x01,0xb9,0x12,0xd1, - 0x0e,0xc2,0x42,0xa3,0x71,0x3e,0x3b,0xc9,0x81,0x50,0xaf,0x98,0x80,0xd6,0xa9,0xfd, - 0x41,0x94,0xdf,0x07,0x33,0x82,0xed,0x2a,0xea,0x77,0xde,0xb6,0xc3,0x09,0xb6,0x08, - 0xc9,0xd7,0x36,0xb0,0xa2,0xb8,0xbc,0xde,0x6f,0xa6,0x86,0x25,0x42,0x63,0x49,0xf9, - 0xd3,0xc7,0xdd,0xce,0xec,0xae,0x18,0xd4,0x0a,0x28,0x46,0x04,0x34,0x3c,0x01,0x25, - 0x18,0xca,0x5b,0xf0,0x4f,0x86,0xc6,0x2c,0xfc,0xe7,0x19,0x9d,0x6a,0x8b,0xcd,0xb9, - 0x07,0xd7,0xff,0x01,0x2e,0xbd,0x75,0x5b,0x24,0x7b,0x0e,0x34,0xf3,0x46,0x51,0xdd, - 0x26,0x9f,0xdc,0xc4,0x93,0x49,0xfe,0xb3,0x3a,0xe3,0x13,0x78,0xa5,0xba,0x54,0xdf, - 0xc8,0xc4,0x1f,0xc2,0x28,0xcb,0x29,0xb7,0xb7,0x8a,0x05,0xac,0x8f,0x03,0xa1,0x8d, - 0xe2,0xd0,0x04,0x3e,0x3c,0x63,0xf1,0xff,0x30,0xf2,0x19,0x1c,0x61,0xcb,0xe2,0xe2, - 0x6e,0x5c,0x8d,0x23,0x68,0xc8,0xdf,0x78,0x9a,0x5c,0x81,0xaa,0x1e,0xb3,0x70,0x3a, - 0xc7,0x87,0x72,0xaa,0xff,0x67,0x57,0xee,0x89,0x2f,0x79,0xcf,0xd8,0xf7,0x88,0xc5, - 0xe4,0x04,0xf7,0x36,0x77,0xc8,0x2e,0xde,0x98,0xc6,0xc8,0x0a,0x73,0xe0,0x9d,0xb8, - 0xbf,0xd5,0xff,0xe3,0x92,0x5a,0x98,0xba,0x97,0x7a,0xb2,0x7f,0xa1,0x36,0x72,0x3c, - 0xcc,0xc8,0x1c,0x75,0x34,0xc1,0x5f,0x9a,0x7c,0x7e,0x4b,0x7f,0xb4,0xb4,0x5a,0x60, - 0x67,0xd5,0x28,0xcd,0x23,0x76,0x88,0x92,0x67,0x78,0xa3,0x10,0x3b,0x3d,0xc8,0x97, - 0x65,0xb1,0xc9,0x87,0x5f,0x9d,0xa8,0xff,0x93,0xf4,0xff,0x5c,0x47,0x9a,0xa2,0xf9, - 0x3b,0x02,0xcb,0xb3,0x7f,0xaa,0xfd,0xa8,0x61,0xee,0x2a,0xba,0x9c,0x5c,0xa7,0x71, - 0x8f,0x90,0xfc,0x7d,0x1e,0xff,0x4a,0x20,0x84,0x24,0xff,0xb9,0x0e,0xf1,0xcf,0x71, - 0xc5,0xc3,0x5c,0xf3,0x73,0xd2,0x10,0x08,0x95,0x87,0xdd,0xb7,0x8a,0x14,0xce,0x43, - 0x65,0x6f,0x16,0x88,0x27,0xb9,0x47,0x88,0xfb,0x7f,0xde,0xb4,0xfa,0x7f,0xb4,0x2b, - 0x6d,0xcf,0xf3,0x32,0xf2,0xc3,0xca,0x1f,0xa0,0x0c,0x97,0x65,0xda,0x05,0xf8,0x23, - 0xae,0xcf,0x26,0x4b,0xfd,0x1f,0xab,0xff,0x67,0x00,0xd5,0xa2,0x87,0xa1,0xd9,0xfb, - 0x01,0x4a,0x7b,0xdc,0x3f,0xfd,0x39,0xc3,0xc2,0x9d,0x30,0xcb,0x70,0x18,0x08,0x44, - 0xff,0xe9,0x5a,0xff,0x4f,0x13,0x9e,0xe1,0x7c,0x86,0x20,0xe7,0x8c,0xb2,0x96,0x27, - 0xa2,0x06,0xc9,0x69,0x61,0xbd,0xa7,0xd8,0xf8,0x3b,0x04,0x42,0xe3,0xf6,0xd4,0x14, - 0xff,0xcf,0x3a,0x56,0xd0,0xe1,0x7a,0xd8,0xf4,0xf6,0xe4,0xeb,0xf4,0x61,0x72,0xc2, - 0xbe,0xee,0xc7,0xf8,0x9a,0x94,0xcc,0x9a,0x78,0xdf,0x54,0xff,0x4f,0x18,0xd4,0xe7, - 0x02,0xe5,0xa4,0x87,0x34,0x12,0xe7,0x51,0xd7,0x4c,0xf2,0x9e,0x6a,0x9a,0xb1,0x6d, - 0x64,0xa2,0xd4,0x5b,0xaa,0xff,0x87,0x9c,0x82,0xbd,0x51,0x94,0x96,0x23,0xf0,0x52, - 0xb8,0x74,0xb3,0xfd,0x43,0x1c,0x98,0x6e,0x9f,0x73,0x39,0x2e,0x7a,0xd1,0xf4,0xff, - 0xa4,0xc4,0xbf,0x0c,0x3c,0x4d,0x47,0x14,0x47,0x93,0x10,0x57,0x47,0xa2,0xbc,0x2d, - 0x9a,0x18,0x27,0x66,0xc7,0x90,0x71,0xfe,0xcf,0xb5,0xf1,0xaf,0x1e,0xe6,0xe1,0xde, - 0x8c,0x73,0xb8,0x3f,0xbd,0xab,0xcc,0xc1,0xb1,0x24,0xd1,0xf7,0xcf,0xf8,0x7f,0x9a, - 0x23,0x05,0xcb,0x71,0xff,0xbf,0xa7,0x1d,0xe4,0xd5,0xf8,0xa3,0xe4,0x9c,0xd2,0x12, - 0x2f,0xe1,0x30,0x86,0x7b,0x78,0xb2,0xae,0xc5,0x3f,0x8f,0x4e,0x6f,0xaf,0x45,0xb3, - 0x6b,0x40,0x3d,0xa8,0x98,0xdd,0xd3,0x06,0xfc,0x2d,0x6a,0x96,0x26,0x46,0xc7,0xf9, - 0x2a,0x62,0x6a,0xfc,0x2b,0x17,0xd6,0x26,0x48,0x3e,0x2f,0x2a,0x7b,0x40,0xed,0x77, - 0x71,0x1a,0x70,0x03,0xe1,0x44,0x44,0xdb,0x78,0x6a,0xd8,0x54,0xff,0xcf,0x49,0xee, - 0x6d,0xd0,0xcd,0xb7,0xf3,0x24,0xf3,0xdf,0x4d,0xfe,0xcf,0xf8,0xfb,0x5a,0xf8,0xcf, - 0x37,0xbd,0x47,0x78,0xda,0xfb,0x3c,0x4e,0xfb,0xb9,0x0c,0xe3,0xfe,0x9f,0xd1,0x04, - 0xed,0x67,0xe0,0xcf,0xf8,0x7f,0x84,0x73,0xf0,0x8a,0x51,0x7a,0x57,0x6b,0xbf,0xb8, - 0xb8,0xe9,0x33,0x58,0xc4,0xdb,0xa6,0xdc,0x0a,0xa6,0x5b,0xac,0x3f,0xb9,0x3e,0xe7, - 0x52,0xfc,0x3f,0x11,0x85,0x67,0x7b,0x89,0x2b,0x58,0xb7,0x80,0x83,0x26,0xee,0xff, - 0xe1,0x40,0x37,0xcc,0xf9,0x3f,0x7f,0xc6,0xff,0xa3,0x35,0xf0,0xfc,0x77,0x25,0xfb, - 0x76,0x7c,0x3b,0xd7,0x72,0x9a,0x4b,0xd2,0xd6,0x99,0x6e,0xae,0xdc,0x0d,0xf8,0xbe, - 0x92,0xfb,0x1a,0xff,0x0f,0x69,0x86,0xf6,0xaf,0xb8,0xda,0x50,0x7a,0x1f,0x54,0xd4, - 0x7a,0xda,0xc6,0xfd,0x3f,0x8a,0xe9,0xf6,0x29,0x84,0x6b,0xfd,0x3f,0xb9,0x4f,0xc1, - 0x31,0xee,0xf6,0x69,0x13,0x57,0xc1,0xe8,0x3d,0x15,0x9a,0x7b,0xdb,0x2d,0xb7,0xa8, - 0x77,0xf2,0xc7,0xde,0x9c,0x7c,0xfe,0x41,0x4b,0xfe,0x57,0x13,0xfb,0xc4,0x5d,0x59, - 0xb3,0x6c,0x4b,0xcd,0x7b,0x89,0xdf,0x66,0x0b,0xbd,0x51,0x73,0x90,0xd7,0x68,0xf1, - 0xff,0x4c,0xcc,0x4f,0xe0,0x9f,0xb2,0xc4,0xb2,0x8f,0x80,0x97,0x98,0xf9,0x5f,0x7d, - 0x56,0x46,0x7a,0xaa,0xff,0x47,0x2a,0x47,0xe9,0xb6,0x93,0xd1,0x07,0xc8,0x28,0x62, - 0xd3,0x85,0x51,0xaa,0xe3,0xf7,0xd8,0x10,0x2f,0xe1,0xb4,0x67,0x0e,0xec,0xcd,0xd2, - 0x88,0xc7,0x27,0x3e,0x2f,0xe2,0x9f,0x00,0xec,0x35,0x0a,0x83,0xd4,0x4b,0x5e,0x50, - 0x71,0x3f,0x70,0x6b,0xf4,0x65,0xd8,0x19,0xb7,0x9b,0xfc,0x9f,0x89,0xf3,0x62,0xed, - 0x0f,0x92,0x07,0x07,0xa8,0x6a,0x44,0xf0,0xd8,0xaa,0xbf,0x24,0xb3,0xa3,0x94,0x07, - 0x86,0x9e,0xe6,0xc7,0xf6,0xbe,0xe4,0xf9,0xed,0xb3,0xe4,0x7f,0xf1,0x22,0x87,0xb7, - 0x86,0xdc,0x6b,0x10,0xed,0x7c,0x86,0x6a,0x05,0x07,0x9f,0x23,0xb4,0x5f,0xcc,0xd3, - 0xbe,0x4c,0x68,0xc4,0xfd,0x3f,0xc7,0x2d,0xfe,0x9f,0xce,0x89,0x45,0x30,0x1b,0x4f, - 0x33,0x07,0x2f,0x3c,0xfb,0x46,0x60,0x82,0xff,0x93,0x90,0x27,0x96,0xfc,0xaf,0xcc, - 0x8b,0xf0,0x2a,0x5b,0xc8,0xb3,0xbd,0xbc,0xf0,0x1e,0x5b,0xb4,0xc2,0x3e,0x2a,0x7e, - 0x6e,0x02,0x21,0x93,0xff,0x73,0x35,0x6a,0xea,0x2f,0x0b,0xff,0x59,0xd8,0xc6,0xcb, - 0x8e,0xf5,0x66,0xd6,0x8b,0x0f,0x6b,0x6b,0x95,0x7c,0xc8,0x7c,0x90,0x9c,0x36,0x78, - 0xfd,0x0d,0xb9,0x9a,0x3f,0x3f,0xbb,0xc6,0xff,0xb3,0x8d,0x27,0xf5,0x6b,0x94,0xb7, - 0xe0,0x7a,0x92,0xce,0xbd,0x8f,0xd6,0x67,0x9f,0x16,0x8e,0x04,0xf2,0x0d,0x59,0x23, - 0xbc,0x14,0x92,0x39,0xbf,0x97,0x4d,0xac,0x7f,0x28,0xb7,0x0f,0x1a,0x0c,0x35,0x98, - 0x91,0xef,0xe7,0xdd,0x40,0x54,0x63,0xee,0x02,0xf2,0x01,0x57,0xd2,0x5c,0xec,0xf3, - 0x54,0x17,0x73,0x3d,0xdf,0xb4,0xe4,0x7f,0x75,0xc2,0xb1,0x07,0xbb,0x82,0xf6,0xce, - 0x9c,0x62,0x76,0x36,0x58,0xa1,0xd9,0x0f,0x8a,0xf1,0xc2,0x8b,0x0d,0xa8,0xbf,0x7e, - 0xc2,0xeb,0x1d,0x25,0xde,0xf7,0xb8,0x05,0xff,0x0c,0xe2,0xf7,0xac,0x08,0xa2,0xd1, - 0xf1,0x21,0x1a,0xba,0xbe,0x26,0xde,0xed,0x4b,0xbd,0x68,0xf2,0x61,0x1a,0x77,0x4f, - 0xcc,0xb7,0xe6,0x7f,0x9d,0xe1,0xd1,0x64,0xbf,0x3d,0x2e,0x9e,0x56,0x5f,0x01,0x4f, - 0xc4,0x3e,0x4c,0x62,0xb0,0x94,0x99,0x62,0xbc,0x72,0xc2,0x1f,0x12,0xb7,0xf8,0x7f, - 0xea,0xd0,0xbe,0x76,0xbb,0x5c,0x8c,0x7c,0xc4,0xde,0xca,0xde,0xd9,0x8d,0x82,0xe5, - 0x5d,0x88,0x04,0xb2,0x78,0xd9,0xd8,0x84,0xab,0xc7,0x91,0xd2,0x1f,0x4d,0xa8,0x23, - 0x2d,0xc6,0x03,0x21,0xba,0xd9,0xf9,0xae,0x62,0xd6,0xeb,0x88,0x91,0x77,0xd5,0x5d, - 0x0a,0xce,0x8f,0xac,0x73,0x27,0xfd,0x3f,0x13,0xfb,0x87,0xe2,0x7f,0x28,0x8d,0xab, - 0x51,0xdf,0xf5,0xc1,0xe3,0xb8,0xcd,0x5d,0xbc,0xcc,0x02,0x5a,0x28,0xc6,0x8d,0x90, - 0xce,0x4b,0x03,0x25,0xf0,0x00,0x24,0x7f,0xea,0xf2,0x4e,0x98,0x65,0xf7,0x70,0xdb, - 0x9b,0xf5,0x25,0x62,0x62,0x87,0xd4,0xc9,0x5f,0x93,0xf3,0x2b,0x2e,0xb9,0x12,0xfe, - 0xae,0x64,0xfe,0xd7,0x8c,0x33,0x1c,0xe4,0x68,0xf3,0x34,0x5e,0xdf,0x0f,0xdf,0x6e, - 0x19,0x77,0x73,0x9d,0x96,0x12,0xfc,0x1f,0x53,0x7f,0x65,0x0d,0x17,0x58,0xf2,0xbf, - 0x1e,0x35,0x41,0x8e,0x81,0xf8,0xfc,0xdd,0xda,0x57,0x7e,0x54,0x5a,0x9b,0x89,0x6a, - 0xae,0xe7,0x63,0x28,0xed,0x43,0xa0,0x58,0x09,0x1f,0x41,0x69,0x21,0x22,0x6a,0x8b, - 0xff,0x87,0xfe,0x82,0xb3,0x9b,0x9e,0x95,0xf5,0x70,0x9c,0x35,0x3b,0x6d,0x11,0xdb, - 0x58,0xf6,0xe5,0xfe,0x0d,0x75,0xce,0x61,0x79,0x37,0xf9,0x05,0x1c,0x32,0x9c,0x40, - 0xb3,0xc3,0x96,0xfa,0x87,0xd2,0x49,0x01,0x3f,0x7a,0x83,0xec,0xcc,0xee,0x6b,0x8a, - 0xa8,0x10,0xe0,0x81,0x30,0x68,0xc8,0x2d,0x7c,0x51,0x16,0x48,0x26,0x0f,0x35,0x66, - 0x50,0x48,0xf7,0x0a,0x13,0xdf,0x37,0x51,0xff,0xa7,0x64,0x58,0xee,0x20,0x83,0x10, - 0x11,0x8a,0x74,0xb3,0x10,0x01,0x13,0x9c,0xbc,0xfe,0xe4,0x6e,0x30,0x5d,0x4f,0x0d, - 0x24,0x96,0x36,0xf1,0x3c,0x42,0x82,0x7f,0x3b,0xec,0xe8,0xa8,0x89,0x5f,0xdf,0xa3, - 0x38,0x3d,0xad,0x31,0x71,0x88,0xec,0x22,0xb8,0x7f,0xf6,0x08,0x6e,0xf8,0xe0,0x2c, - 0xda,0x5f,0xdb,0xc8,0xf4,0xc9,0xe7,0x6f,0x00,0x1e,0xff,0xc2,0xf3,0x15,0x17,0x87, - 0xc9,0x65,0x66,0x1e,0xab,0x31,0xe5,0x72,0xf4,0x8a,0xe1,0xe8,0x46,0xc5,0x76,0x11, - 0xaa,0x56,0x39,0xce,0x7c,0x3d,0x59,0xff,0x70,0x20,0x91,0xff,0x15,0xb4,0xff,0x42, - 0x2e,0x52,0x02,0x50,0x71,0x9f,0x59,0x78,0xf3,0x98,0xe4,0xed,0x31,0x3d,0x96,0x17, - 0x35,0x6f,0xad,0xbb,0x51,0xfe,0xde,0xa4,0xfc,0x89,0x4b,0xee,0xdc,0xc3,0x3c,0x1e, - 0xb1,0x9b,0x14,0x41,0xa4,0x1f,0xf1,0xcf,0x08,0xe7,0xff,0x2c,0xc7,0x81,0x82,0x66, - 0x4d,0x17,0x53,0x43,0xb4,0xc9,0x99,0xe4,0xff,0x18,0x13,0xfe,0xc0,0x05,0x64,0x76, - 0x53,0xa3,0xd1,0xce,0x78,0x7f,0xc6,0xf4,0x06,0xc3,0x85,0x08,0xb9,0x88,0xb7,0xe9, - 0x55,0x59,0x60,0x9f,0x7f,0x62,0x35,0x01,0xfa,0x21,0xa1,0xf4,0xe9,0x88,0xed,0x1f, - 0x61,0xfd,0x33,0xf9,0x9d,0x74,0x0d,0x79,0xc7,0xc6,0xf4,0x7c,0x95,0xd6,0x91,0x27, - 0xe8,0x7e,0xb6,0x43,0xc7,0x2b,0xc9,0xa2,0xed,0x01,0x30,0xf3,0xdf,0x0d,0xb7,0x27, - 0x27,0x8b,0x1c,0xd7,0x3d,0xa3,0x8e,0xd2,0xc6,0x8f,0xa0,0x47,0xef,0xae,0x77,0xab, - 0xa4,0x95,0x9e,0xa7,0x5d,0xcc,0xae,0x8a,0xd9,0xc9,0xfa,0xcf,0x89,0xf5,0x34,0x6e, - 0xf1,0x08,0xad,0x70,0x31,0x5a,0xc6,0x1c,0x7b,0xbe,0x3c,0x04,0x23,0xd9,0x3e,0x6d, - 0x53,0x27,0x9e,0xc7,0x8b,0xca,0x91,0xa6,0x79,0xbb,0xc4,0xe8,0xa4,0x7d,0x64,0xd6, - 0xff,0x41,0xfb,0x37,0x2b,0x96,0x33,0x90,0xf0,0xff,0xec,0x17,0x3f,0xd4,0xdf,0x07, - 0x6f,0xc3,0xa6,0x98,0xb8,0x5b,0xfb,0x14,0x70,0xa1,0x62,0x56,0xff,0x4f,0x9e,0xe9, - 0x4f,0xd6,0x4c,0x6f,0x8f,0xe9,0x6d,0x7e,0x90,0x5c,0x86,0xb5,0x90,0xdf,0x20,0xf2, - 0x42,0xb2,0xfb,0xb9,0x3d,0x55,0x4f,0xa6,0xd6,0x3f,0x2c,0xe6,0x49,0x5e,0x57,0xe0, - 0x29,0x8e,0x76,0xfe,0x89,0x5c,0x69,0xfa,0x65,0x03,0xa7,0xfd,0xa4,0xbf,0x03,0xfb, - 0x59,0x7e,0xdc,0xc5,0xf3,0xfd,0x27,0x9e,0x27,0xc0,0xeb,0xff,0x80,0xfb,0xe1,0x8c, - 0x18,0x8f,0x2f,0x13,0xf7,0x19,0x33,0xd0,0xbc,0xd9,0x50,0x07,0x96,0xf0,0xc2,0xe3, - 0x7b,0x83,0xce,0xd7,0xa8,0x9e,0x7d,0x43,0xb2,0x3e,0x55,0xa2,0x3f,0x2c,0x0f,0x72, - 0xf5,0xc1,0x33,0x30,0x2f,0xba,0x8c,0xb3,0xdf,0x2f,0xea,0xde,0x06,0x47,0x07,0x0e, - 0xf6,0xb3,0xae,0xe8,0x6a,0x5d,0xae,0x48,0xde,0x1f,0x12,0xf6,0x78,0x16,0xaa,0x21, - 0x32,0xa6,0x3d,0x62,0xf6,0xeb,0x84,0x38,0xe5,0x86,0xc6,0x4e,0x33,0x23,0x9e,0xbb, - 0x16,0x2d,0xfd,0x61,0xcd,0x7c,0xe7,0x4a,0x2d,0x93,0x6b,0xc3,0x63,0x70,0x6f,0x60, - 0x69,0x74,0xfa,0x2a,0xf3,0x20,0x3b,0xa6,0x13,0x5e,0x0a,0xd8,0xcb,0x23,0x62,0x56, - 0xfe,0x73,0x42,0xc9,0x06,0xb6,0x90,0x39,0xd0,0x13,0x57,0x43,0x8f,0xf2,0xc4,0xae, - 0x66,0x20,0xda,0x12,0x8e,0x97,0xd0,0xe2,0x08,0x05,0xda,0xc8,0xc4,0x6c,0x5e,0x0f, - 0x30,0x31,0x7f,0x6e,0x34,0xcb,0x07,0x8f,0xb2,0x0f,0x78,0x1b,0xf7,0x5e,0xd4,0xd7, - 0xa2,0x76,0x63,0x3f,0xe9,0xa0,0xb7,0xf1,0x7c,0xf9,0x33,0xd6,0xfa,0xcf,0xb9,0x09, - 0x90,0x43,0x73,0xd3,0x6f,0x85,0x47,0x35,0x57,0x10,0xed,0xd3,0xb5,0x28,0xb1,0x79, - 0xfd,0x6d,0xc2,0x4b,0x25,0xe7,0x07,0xe9,0xfd,0xb6,0x64,0xfe,0xfb,0xf2,0x0c,0xce, - 0xff,0xe1,0x65,0xf7,0x72,0x5c,0xc2,0x49,0xa1,0x88,0xb3,0x31,0x79,0xd8,0xab,0x0b, - 0x5f,0x93,0x27,0x22,0x09,0x5e,0x58,0xaa,0xc9,0x96,0xfa,0xcf,0x33,0x06,0x72,0xcd, - 0xfa,0x87,0xd1,0x2f,0xf7,0x92,0x3f,0xc2,0x42,0x5e,0xf6,0xe7,0x1b,0xca,0x67,0xb7, - 0x9b,0xf5,0x7f,0x66,0x4b,0x97,0xab,0x7d,0xda,0x32,0x6b,0xfd,0xc3,0x3c,0x33,0x5f, - 0x6c,0x31,0x47,0x3b,0xfb,0xe0,0x95,0xb4,0xf9,0x9c,0xff,0x33,0x9b,0x5d,0xce,0xf0, - 0xfa,0xef,0xef,0x6f,0x1c,0x50,0xd1,0x34,0xab,0x75,0xfc,0x4a,0x2c,0x49,0xe2,0x13, - 0xe0,0xcf,0x53,0x32,0x83,0xfb,0x7f,0xb8,0xb7,0x27,0x2f,0xc2,0x88,0x10,0xed,0x86, - 0x32,0xc5,0xac,0x87,0x83,0x57,0xa8,0x4c,0x48,0xb2,0xfe,0x73,0xc8,0x8c,0x7f,0xb9, - 0x34,0x5b,0xf4,0xe8,0x80,0xbe,0x8b,0x16,0xfa,0xa9,0x99,0xf8,0x5f,0x34,0xde,0x21, - 0xae,0xc1,0xa4,0x42,0xa5,0xdf,0x3b,0x29,0x7f,0xba,0xd3,0x3a,0xc6,0xe3,0x89,0xf7, - 0xae,0x82,0x5d,0x40,0x7a,0x80,0xd7,0xd3,0x3e,0x28,0x9a,0x6d,0xe6,0x3a,0xcc,0x8a, - 0x4c,0xf2,0x02,0x72,0xc7,0xe4,0xf7,0x6a,0x97,0xf8,0xf7,0xad,0xf8,0x6a,0x56,0x74, - 0xe5,0x4b,0xe4,0x2c,0xc4,0x96,0x17,0x46,0x73,0x0a,0xd1,0x7e,0x69,0x0f,0xa0,0x99, - 0xdc,0x4b,0x8e,0x45,0xbc,0xf8,0xbe,0x72,0xdd,0xe4,0xfe,0x39,0x9e,0xd8,0x0f,0x9c, - 0xff,0xdc,0xc1,0xcc,0x6a,0x87,0x8a,0x3c,0xa0,0x8c,0x3e,0xee,0xd3,0xe6,0x6d,0x11, - 0x07,0xa4,0x51,0x17,0xf7,0xff,0x34,0x1e,0x9a,0xbc,0xbf,0x0d,0x26,0xf1,0x8f,0x0a, - 0x67,0x6e,0x2f,0x51,0xb6,0x37,0xc8,0x2a,0xf4,0x09,0x95,0x8a,0x9d,0xd5,0xc4,0x69, - 0x9f,0x86,0xeb,0xcf,0xe4,0x24,0xff,0x87,0xe6,0xf2,0xf8,0xd7,0x3c,0x46,0xbf,0x43, - 0x6e,0xd3,0x36,0xde,0x8e,0x83,0xb3,0xc4,0x25,0x6d,0x64,0x25,0x0c,0x81,0xd0,0x08, - 0xbc,0xae,0x39,0x3b,0x51,0x95,0x27,0xf3,0x8b,0x13,0xf1,0x88,0x42,0x46,0xdd,0x44, - 0x86,0x2d,0x71,0xb7,0xb6,0xa1,0x92,0xb4,0x72,0x37,0x35,0x97,0x57,0x7d,0x14,0x55, - 0x79,0x1c,0x07,0xfe,0x49,0xfd,0x25,0x40,0x22,0xff,0x9d,0xc6,0xc3,0xb7,0xc1,0xba, - 0xac,0x62,0xcd,0x56,0x9f,0xfe,0x04,0x5b,0xaf,0x15,0x1b,0x10,0xc4,0x6d,0xf1,0xaf, - 0x5a,0x7e,0x3c,0x12,0x0c,0x07,0x92,0x78,0x9b,0x71,0x90,0x73,0xab,0x6e,0x0f,0xdc, - 0x98,0x0d,0xa7,0x1b,0x16,0x87,0x8a,0xd6,0x88,0x4f,0x84,0x5f,0x64,0x95,0x71,0xd7, - 0x9a,0x69,0x6f,0xc2,0x8b,0x09,0x44,0x74,0xd7,0xa4,0xfc,0x29,0xca,0xe5,0xf2,0x64, - 0x16,0x9b,0x07,0x5f,0x36,0x60,0x24,0xcd,0xa7,0x65,0x7a,0x0a,0x78,0x05,0x18,0x33, - 0x0c,0x34,0x88,0xf6,0xda,0x11,0xae,0xf8,0xc2,0xc9,0xfa,0xcf,0xbc,0x3f,0x2c,0xab, - 0xd2,0xb3,0x06,0x73,0x2e,0x4a,0x1f,0xb1,0x52,0x9e,0xf6,0x55,0xc5,0xcb,0x3e,0x0f, - 0x38,0xce,0x88,0x17,0x4d,0x6a,0xd0,0xcd,0x97,0x72,0x92,0xf2,0xe1,0x19,0xb3,0xdf, - 0x6b,0x31,0x77,0x82,0x5d,0x84,0x70,0x4c,0xbd,0x53,0xfe,0x8c,0x64,0xb1,0x86,0x0e, - 0xfd,0xe4,0xac,0xe5,0xbc,0x51,0x2c,0xaf,0xff,0xfc,0xa5,0x0d,0x45,0x49,0xff,0x5e, - 0x82,0x2f,0x1d,0xb6,0x05,0xd1,0xc8,0xda,0x0d,0xb3,0x83,0x2d,0xc3,0xc4,0xbe,0x6e, - 0x5d,0x7e,0xb1,0x71,0x27,0xcf,0x77,0x7b,0x96,0x27,0x6e,0x3c,0xe4,0x94,0xac,0xf5, - 0x0f,0xb9,0xfc,0x89,0x52,0x5e,0xe6,0x2e,0xcc,0x0a,0x43,0x66,0x20,0x3e,0xa2,0x15, - 0x1a,0x4b,0xca,0x71,0x3d,0xf7,0x86,0x54,0x5e,0x91,0x43,0x99,0xac,0x7f,0x68,0xca, - 0x4f,0xc9,0xc7,0x6c,0xbc,0x3a,0xc1,0x07,0x81,0xfd,0x6b,0x1c,0x31,0xb9,0x12,0x4e, - 0x28,0x65,0xc6,0xb2,0x58,0xe3,0x20,0x1c,0xd6,0xba,0x0c,0xf9,0x39,0xd1,0x36,0x59, - 0xff,0x90,0x25,0xf4,0x51,0xd8,0xc1,0x69,0xa8,0x97,0x68,0x05,0xe7,0x87,0x0f,0x09, - 0x23,0xa4,0xc2,0xc8,0xea,0x12,0x07,0xa9,0x49,0x94,0x8a,0x4e,0x1b,0x4a,0xf6,0x87, - 0x4d,0xe8,0x3b,0x96,0x85,0x66,0x69,0xa2,0x3f,0x5a,0x1c,0x81,0xed,0xab,0x88,0xf7, - 0xec,0x17,0x11,0x21,0xec,0x81,0xad,0xa1,0x59,0x9f,0x6c,0x55,0x27,0xeb,0x1f,0xf6, - 0x48,0x6e,0x5e,0x6d,0x8f,0xc9,0x1b,0xc9,0x0b,0x2c,0xf2,0x6e,0x49,0x61,0x96,0x4e, - 0xdc,0x34,0x12,0x20,0x9c,0x91,0x82,0xcf,0xf3,0x7b,0x67,0xfc,0x46,0x46,0xf2,0xad, - 0xfd,0x61,0xa5,0xc3,0x52,0x09,0x5b,0xd2,0x99,0xfd,0x01,0x6c,0x60,0x25,0x9a,0x6d, - 0x0f,0xd9,0x4d,0x5b,0xa6,0xa7,0x27,0xe6,0x77,0x37,0x14,0xf5,0xc9,0x9c,0xb1,0x3c, - 0x89,0x7f,0x24,0x3b,0xf7,0xc6,0x33,0x59,0x25,0x83,0xe1,0x70,0xbe,0x3b,0x68,0x53, - 0xc8,0xa3,0x90,0x31,0xd7,0x0c,0x14,0xf6,0xf1,0x0a,0xe4,0x9a,0x0c,0x36,0xc2,0x26, - 0x37,0x28,0x20,0x88,0xd2,0x10,0x06,0x23,0xfe,0x61,0x7d,0x2e,0x5f,0x34,0x2b,0x26, - 0x3e,0x07,0x47,0xd5,0x32,0xc3,0xdd,0xd5,0xc8,0x89,0x2b,0xe6,0x0a,0xa8,0x4f,0x4d, - 0x3e,0xcf,0x8f,0xc6,0xe0,0xaa,0x8b,0xe7,0x37,0x89,0x67,0xd5,0x61,0x5a,0x05,0x1b, - 0x87,0xc5,0xef,0xd0,0x11,0x57,0xd5,0x51,0xdc,0x3f,0x1c,0x11,0x2d,0xd4,0x36,0x19, - 0x29,0xf5,0x7f,0x46,0xa2,0x63,0xae,0xf9,0xbc,0x7f,0x5c,0x39,0x1b,0x73,0x56,0x09, - 0x4b,0x7b,0xc5,0x61,0xfd,0x72,0xc8,0x8c,0x9f,0x8e,0xfb,0x7f,0x86,0x53,0xf8,0x3f, - 0xef,0x43,0xb7,0xe1,0x55,0x5c,0xdb,0xc9,0x5c,0xe8,0x8e,0x96,0x78,0xe8,0x7a,0xf2, - 0x7b,0x38,0x18,0x2c,0x8a,0x27,0xea,0xff,0xb0,0x12,0xde,0xff,0xdd,0x93,0xb4,0x7f, - 0xd3,0x8e,0xe5,0xc6,0xd2,0x0b,0xa7,0xd7,0xe5,0x42,0x06,0x20,0x22,0x41,0x8c,0x48, - 0x0c,0x38,0xa8,0x8e,0x33,0xa0,0xc6,0xfd,0x1b,0xde,0x14,0xff,0x4f,0x37,0x75,0x8a, - 0x34,0xea,0x77,0xb9,0x51,0x10,0x91,0x0c,0xf6,0x6e,0x5c,0x3d,0x48,0x8b,0x8c,0x96, - 0x58,0xf6,0xa4,0xff,0xc4,0x52,0xff,0x47,0x39,0x08,0x57,0xb4,0x03,0xd1,0xa5,0x71, - 0xf9,0x36,0xb8,0x42,0xaa,0xa2,0xc5,0x03,0xe2,0xa8,0x74,0xd5,0xef,0x4d,0x30,0xc4, - 0x4c,0x3c,0x5c,0x61,0xa9,0xff,0x70,0x16,0xa5,0xa7,0x99,0x04,0xa7,0xe2,0x6a,0x70, - 0xc5,0x97,0xa5,0x8f,0x03,0xc5,0x44,0x3d,0x04,0x3e,0x18,0xcd,0xb1,0xf6,0xbf,0xd8, - 0x05,0xc7,0x83,0xde,0xcd,0x4b,0xf5,0x2f,0xcf,0x55,0xfe,0x49,0xf1,0x46,0xed,0x1d, - 0x8d,0x73,0xa5,0x4b,0x1a,0x87,0x9d,0x39,0xe3,0xf7,0xd7,0xad,0xfd,0x61,0x25,0x17, - 0x0b,0x33,0xa7,0x4e,0xf5,0x9a,0x6f,0x4b,0x87,0xfb,0x55,0x16,0xe9,0x08,0x17,0x25, - 0xf8,0xf0,0x08,0xe4,0x24,0xf3,0xf9,0x75,0xf2,0xb9,0xc5,0xff,0x73,0xb7,0xda,0x10, - 0x77,0xae,0x09,0x28,0xe4,0x1e,0x29,0xc6,0x40,0xa3,0x33,0x51,0x7a,0x77,0x07,0xdc, - 0x13,0xeb,0xe3,0x4e,0xad,0xff,0xbc,0x52,0xc8,0x12,0xd6,0x46,0x77,0x84,0x02,0xcb, - 0xb3,0xbf,0xa6,0xed,0x0b,0xe7,0xaf,0xa2,0x7f,0x43,0xae,0x83,0x7d,0x11,0xd3,0x0d, - 0x32,0xe9,0xff,0x19,0x9b,0x9c,0xcf,0xfd,0x3f,0x3d,0x8a,0xc7,0x6f,0x57,0xe4,0xa5, - 0xa1,0x4f,0x20,0x56,0xeb,0x9e,0x2e,0x4b,0xfa,0x30,0x54,0xf6,0x3a,0x3c,0x13,0xfe, - 0x1f,0x10,0x5f,0xb3,0xf6,0xbf,0xf0,0x7f,0xa6,0x54,0xd5,0xce,0x3b,0x23,0x8e,0x69, - 0x97,0x95,0xc5,0xa8,0x7d,0x0a,0x2e,0xd0,0x91,0x68,0x62,0x7d,0xa4,0xab,0x3c,0x3f, - 0xae,0xc7,0xd2,0xff,0x82,0xf3,0x7f,0x78,0xd8,0x71,0xa9,0x2e,0xbb,0xe1,0x68,0xa2, - 0xda,0x8f,0x9b,0xfb,0x27,0x2d,0xeb,0x8f,0xf8,0x27,0x99,0xff,0x32,0x9d,0x57,0x3b, - 0xc7,0xdd,0x1e,0xf2,0xdb,0x61,0x1d,0x31,0xb7,0xbd,0x9d,0x86,0xc7,0x3b,0x62,0x4c, - 0xd8,0x8f,0x5e,0x4b,0xfd,0x81,0x27,0xe0,0x31,0x66,0x16,0x35,0xe2,0xfc,0x1f,0xb3, - 0x10,0xe2,0xac,0x8c,0x75,0x89,0xb2,0xcf,0xef,0x98,0xa5,0x00,0xe4,0x3c,0x0b,0xfe, - 0xe1,0xfd,0x61,0xb7,0xb2,0x76,0x83,0xce,0x43,0x6b,0xab,0x71,0x0b,0x4a,0xef,0xdb, - 0x48,0x96,0x10,0x66,0xaa,0x65,0x3d,0xaf,0x23,0x37,0xa4,0xf8,0x7f,0xde,0xdc,0xd1, - 0xd5,0xe9,0x1e,0x10,0xeb,0x78,0x7e,0x53,0xa7,0x5b,0x97,0x8b,0xc2,0xa7,0x74,0x5e, - 0xf6,0xd9,0x24,0x86,0xe1,0xd1,0x1b,0x48,0xe9,0x7f,0x71,0xd6,0xcc,0xfe,0x76,0x68, - 0x22,0xe3,0x6d,0x2f,0x12,0x44,0xa0,0xb1,0x84,0x19,0x3e,0x49,0x0d,0x4a,0xe9,0x7f, - 0x01,0xbf,0x02,0xb3,0x9a,0x0d,0xc7,0x3f,0xa6,0x23,0x48,0x82,0x1e,0xd5,0x6b,0x76, - 0x40,0x48,0x98,0xba,0xdb,0x2c,0xf8,0x47,0x87,0x2f,0x86,0x9a,0x35,0x27,0xea,0x6b, - 0xf1,0x9b,0xd0,0x1c,0x6f,0x0f,0xd1,0xed,0xe1,0x39,0x09,0xb5,0x9b,0xc8,0xc8,0xe6, - 0xa5,0x81,0x2c,0xf8,0xa7,0x5c,0x2a,0x14,0xff,0x25,0xaf,0x40,0xa3,0xfd,0xa4,0x90, - 0x3d,0xaa,0x16,0x04,0xe8,0x6b,0xb6,0x05,0xec,0x51,0x6a,0x9d,0xbf,0xd9,0x5a,0xff, - 0x07,0xd2,0x60,0xad,0x90,0x1f,0xbc,0x2b,0x38,0xe7,0x76,0x0e,0x3b,0x35,0x7a,0x1f, - 0x49,0x78,0x84,0xc6,0xeb,0xff,0xb8,0x35,0x39,0x3b,0x4c,0x92,0xf9,0xef,0x94,0x67, - 0x1b,0x75,0x81,0xdd,0xe0,0x6a,0x37,0x51,0xf6,0x59,0xe5,0x85,0xbb,0x2c,0xef,0x1b, - 0xb6,0xe2,0x9f,0x9b,0xde,0xe3,0x4d,0xde,0x83,0x8e,0xdc,0x1a,0xee,0x08,0x32,0x61, - 0xcf,0x7b,0x13,0x6d,0xdf,0xc7,0xdf,0xf7,0xb5,0xad,0x49,0xfc,0xb3,0x2d,0xed,0x73, - 0xf6,0x4a,0x47,0x69,0x9d,0xfd,0x4d,0xb1,0x0c,0x5e,0xe9,0xc4,0xc1,0xdb,0x9c,0xff, - 0xb3,0xad,0x54,0x5b,0x9a,0x08,0x0c,0xe1,0x7c,0xde,0xff,0x22,0xe9,0xff,0x41,0x90, - 0xa3,0x39,0x29,0xda,0xa7,0xf9,0x64,0x83,0xe6,0x04,0x57,0x13,0x0e,0x22,0x9a,0x73, - 0x3c,0xff,0x3d,0xe1,0xff,0x49,0x4f,0xae,0x50,0xda,0x8b,0x7a,0x43,0xb5,0xca,0xf9, - 0x3f,0x69,0x7a,0x03,0xe8,0x41,0x9a,0x4d,0x24,0x48,0x78,0x84,0xc6,0xdf,0x77,0xc9, - 0x75,0xfe,0x64,0xff,0x8b,0x84,0xff,0x87,0xa3,0x9d,0xec,0x42,0x73,0xd9,0x23,0x88, - 0x7f,0x72,0x13,0x57,0x26,0xd6,0xb3,0xcd,0x9a,0xff,0x95,0xdb,0x81,0x18,0xc9,0xa4, - 0x75,0x2d,0x80,0x63,0x26,0x9b,0x5d,0xe6,0x1f,0x7a,0xa2,0xfe,0x8f,0xf9,0x7d,0x2d, - 0xfd,0x2f,0x22,0xd0,0xe1,0xe1,0x78,0x18,0x41,0xd1,0x00,0x3c,0x48,0x2b,0x79,0x35, - 0x80,0x5e,0xf8,0x44,0xb2,0xae,0xcf,0x4c,0xf1,0xa2,0xd5,0xff,0x43,0xcf,0xa8,0x5e, - 0xc9,0xc4,0x3f,0x7d,0xc1,0xae,0x04,0x11,0xa8,0x4f,0xf5,0x5a,0xd6,0x3f,0xa5,0xff, - 0x45,0x53,0x05,0x6c,0x64,0x05,0x3a,0xea,0x77,0x17,0x6c,0xe4,0xd1,0xc0,0x41,0x3e, - 0x30,0x6e,0xe5,0x6e,0x9f,0x41,0x38,0x44,0x50,0xb5,0x0d,0x26,0xcb,0xed,0x80,0x2b, - 0x6d,0x35,0x44,0xfb,0x55,0x9d,0xaa,0x59,0x6e,0x68,0xd4,0xd4,0xf8,0xb6,0x99,0x24, - 0x0b,0x1a,0x98,0xca,0x92,0xe7,0x65,0x71,0xb6,0xa5,0xff,0x85,0x30,0x9d,0xfb,0x6f, - 0x79,0x91,0xc3,0x99,0xdc,0x91,0xd2,0x4f,0xeb,0xc3,0x37,0x41,0x13,0x9d,0xcd,0x92, - 0xe7,0xd7,0x93,0x52,0xff,0xc7,0x07,0xaf,0xb3,0x98,0xee,0xae,0xcb,0x5e,0x18,0x7e, - 0x81,0x79,0xe2,0x68,0x91,0x64,0xa1,0x6a,0x9d,0xaf,0x8f,0xd7,0xff,0x31,0xfd,0x3f, - 0xb6,0x49,0xf9,0x43,0x6f,0xea,0x20,0x23,0x02,0x0a,0x0d,0x75,0x42,0x7a,0x70,0xb7, - 0xcf,0x95,0x84,0x23,0xe8,0xcf,0xf9,0x7f,0xd2,0xae,0xd0,0xb1,0x86,0x2a,0xdd,0x3d, - 0x88,0xda,0xea,0x55,0x4e,0xe4,0xe0,0x6e,0x9f,0xcb,0xbc,0x63,0xec,0xa4,0xfe,0x1a, - 0x91,0xf3,0x2c,0xf1,0xaf,0x36,0xd8,0xc7,0xeb,0x6f,0xac,0x08,0x8f,0x69,0xeb,0xf9, - 0x8b,0x18,0xf8,0x22,0xcf,0x51,0xd3,0x23,0x9d,0xa8,0xff,0x23,0x0f,0x93,0x24,0xfe, - 0xd9,0x06,0x7c,0x7e,0x31,0xbb,0x21,0x64,0xda,0x6b,0xb3,0x35,0xaa,0xe1,0xfc,0x67, - 0x21,0x9f,0x65,0x58,0xe4,0x95,0x94,0xec,0x7f,0x91,0xdb,0xab,0xf0,0x6c,0x26,0x5b, - 0x91,0x7f,0x08,0x05,0x5d,0xa1,0xe6,0xe2,0x69,0x17,0x87,0x41,0x65,0x19,0x49,0x79, - 0x6e,0x4b,0xe2,0x9f,0xf2,0x19,0xbb,0x61,0x98,0xf8,0x7a,0xb2,0x76,0x8b,0x43,0x26, - 0xdb,0x19,0xf7,0x8f,0x5d,0x1a,0xf5,0x77,0xb1,0xe2,0xc9,0xf7,0xd5,0xe5,0x2c,0x0b, - 0xfe,0xe9,0xe5,0x1f,0xbd,0x3f,0x4d,0xcd,0x31,0xe3,0x5f,0x89,0xb4,0xaf,0x11,0x8e, - 0x70,0x26,0xe7,0xab,0x72,0xb2,0xfe,0x73,0x83,0x32,0x06,0x27,0xa5,0xd2,0xb8,0x3d, - 0x8e,0xfb,0xf3,0x55,0xee,0xd6,0xe8,0x17,0x1f,0x66,0xaf,0xd2,0x52,0x96,0xd4,0x77, - 0x86,0xa5,0xfe,0x4f,0x4f,0xd3,0xff,0xd8,0x10,0x89,0xef,0xe8,0x47,0xb4,0x5c,0x06, - 0x8d,0x86,0x33,0x2e,0x47,0x36,0x94,0xc0,0x99,0x08,0x1a,0xe6,0xb1,0x89,0xf8,0x45, - 0x33,0x29,0xb4,0xe0,0x9f,0x12,0x1a,0x69,0x70,0x9e,0xc1,0xf9,0x6e,0xd6,0x12,0x71, - 0xf2,0x6e,0x29,0x6e,0x68,0x66,0x4e,0xcb,0xfc,0xd8,0x94,0xfa,0x3f,0x9c,0xed,0xe3, - 0x52,0x89,0xc9,0x76,0x36,0x64,0xe0,0x81,0x0f,0x5c,0x9f,0x1b,0x2d,0xeb,0x93,0xc4, - 0x3f,0x8c,0xae,0xa2,0x7d,0x92,0xd7,0x08,0xf0,0x68,0xa0,0xc9,0x6f,0xe1,0x82,0x14, - 0x05,0x91,0x75,0x3f,0xc8,0xea,0xba,0x49,0xff,0xcf,0x4d,0x17,0x12,0x4d,0xa8,0xe3, - 0xe2,0x05,0xb8,0xc0,0xc3,0x3a,0xdc,0xed,0x33,0xc6,0xdb,0x18,0x4d,0xbe,0xef,0xb0, - 0x38,0xe8,0x9f,0x90,0x27,0x00,0xa4,0xd1,0x33,0xde,0x7d,0x6f,0x3d,0x1f,0x7c,0x77, - 0x62,0xa0,0xd9,0x66,0x1e,0xfd,0xff,0x6d,0x3f,0xc4,0x69,0x1e,0x1c,0x7c,0x77,0x62, - 0xa0,0x99,0x6d,0xf8,0xfe,0xcc,0xfd,0x59,0xc2,0x12,0x04,0xda,0xe8,0x9d,0x3a,0x98, - 0xf8,0x95,0xf5,0xe7,0xff,0xbd,0x7e,0x88,0xa2,0x67,0xea,0xe0,0xcf,0xfd,0xfc,0x47, - 0x6d,0x10,0xc1,0x32,0xf8,0x4b,0xd6,0x7f,0xc5,0xc4,0x20,0xff,0x2f,0x5b,0xff,0x15, - 0x13,0x83,0xfc,0xff,0xb4,0x1f,0xa2,0x96,0xda,0x06,0xd1,0xbc,0xc2,0xff,0xa1,0x6b, - 0xee,0x3f,0xd3,0xb8,0xf6,0x1f,0x5a,0xef,0xc1,0xc1,0x77,0xf1,0x57,0x7f,0x66,0xfd, - 0x95,0x94,0x85,0x44,0x81,0x40,0xf3,0xfc,0x92,0x79,0x36,0xe8,0x94,0xef,0x9b,0x98, - 0xa4,0xa4,0x2c,0x7b,0x13,0x0e,0xf2,0xb4,0x26,0x7e,0x25,0x65,0xff,0x24,0xfb,0x21, - 0xda,0xad,0xff,0x28,0x3e,0x36,0xe0,0xf3,0x9b,0x1f,0xa2,0x14,0xec,0x3d,0xff,0xa7, - 0x1f,0xe2,0x7f,0x91,0xfe,0x83,0xff,0xf5,0xe6,0x93,0x26,0x65,0x07,0x75,0xf9,0x33, - 0x38,0x01,0xe8,0x2f,0xeb,0x4f,0xea,0xc2,0x43,0x57,0x0d,0x0a,0xfb,0x4b,0xe5,0xa1, - 0x94,0x4f,0xa9,0x5f,0x50,0xb4,0xff,0x48,0x1e,0x3a,0xa7,0xdc,0x3f,0x57,0xa0,0xff, - 0x0b,0xf2,0x36,0x21,0xf4,0x88,0x13,0x22,0x93,0x82,0xf1,0x9a,0x41,0xca,0xfb,0x9a, - 0xe7,0x49,0xa0,0x76,0xff,0x5f,0x2a,0x0f,0xf1,0xf0,0x48,0x84,0xd8,0xd9,0x5f,0x2a, - 0x0f,0xf1,0xef,0x25,0x22,0x68,0x6c,0xea,0x4a,0xff,0xf9,0x1f,0xd2,0x24,0xed,0x40, - 0xdc,0x60,0x5d,0xf6,0xf5,0x9e,0xd4,0xf5,0x4f,0x91,0x27,0x1e,0x73,0x11,0xfc,0xff, - 0x0b,0xeb,0xcf,0x17,0xb9,0x3a,0xfd,0x3f,0x5e,0xff,0x29,0xf2,0x50,0x92,0x50,0x7a, - 0x3c,0x04,0x33,0xd9,0xb5,0xf2,0xf0,0x3f,0xec,0x0f,0x9b,0xa7,0x09,0x7f,0xa9,0xbe, - 0xf3,0x9a,0x2b,0x2a,0x64,0xfc,0xa5,0xeb,0xaf,0x30,0xbb,0x4a,0xe9,0x5f,0xba,0xfe, - 0x5c,0x1e,0x4a,0x53,0xbf,0xe0,0x35,0x3f,0xd6,0xfe,0xb0,0x1e,0x48,0x3a,0x8b,0xff, - 0xe7,0x3f,0x95,0x95,0xf8,0x0f,0xb0,0xa9,0x4b,0x3c,0xf5,0xc7,0x2a,0x0f,0xc5,0x9e, - 0xc6,0x1e,0xf6,0x97,0xff,0x03,0xb8,0x21,0x74,0xab,0x3b,0xe8,0x7f,0xfa,0x93,0xeb, - 0x92,0x5c,0xff,0x99,0xbe,0x9d,0xfa,0xf3,0x5f,0x4d,0xfe,0xfc,0x17,0x9b,0xbf,0xb6, - 0x5a,0xa8,0xd7,0xde,0x56,0x16,0x42,0x66,0x03,0x31,0x07,0xb9,0x99,0x2f,0xa6,0x3f, - 0x58,0x7b,0x7f,0x70,0x61,0xee,0x4d,0x2f,0x4e,0x7b,0x50,0xbb,0x3f,0xf8,0x57,0xd2, - 0x0c,0x63,0xfe,0xe4,0xfc,0xdb,0x6b,0xd3,0x1e,0x14,0xee,0xd7,0xfe,0x5a,0x81,0xde, - 0xb4,0x07,0xd3,0xf8,0x60,0x46,0xef,0x8c,0x07,0x1b,0xee,0x0f,0xe1,0xe0,0xa4,0x90, - 0xf8,0x15,0xce,0x9f,0xc0,0xc3,0xd0,0x43,0x04,0x95,0x05,0xd4,0x6c,0x2a,0x85,0x27, - 0x06,0xe9,0x38,0xd0,0xd4,0xec,0x3c,0x69,0x23,0xbf,0x12,0xc2,0x2b,0x93,0xe1,0x65, - 0x1e,0xc0,0x13,0x42,0xb0,0x1c,0xae,0x83,0x1f,0x31,0x3e,0x10,0xae,0x53,0xd2,0x58, - 0xda,0x0a,0x21,0x4f,0xbb,0x8e,0xce,0x60,0xc2,0x8a,0x86,0xe5,0xf0,0x55,0x48,0x63, - 0xaa,0x36,0x31,0xbf,0x77,0xb9,0x54,0x26,0xdc,0xcd,0xbe,0x5c,0x2d,0xf5,0xa5,0x3d, - 0x24,0xdc,0xcf,0xfe,0xda,0x35,0xe3,0xb8,0x60,0x0e,0xd4,0x34,0xf3,0x8a,0xfe,0xd7, - 0x6a,0xae,0xe5,0x79,0x7a,0x35,0x4d,0x55,0x28,0xca,0x2b,0x3c,0x4c,0x21,0xc8,0x83, - 0x74,0x10,0x26,0x07,0xe1,0xc9,0x2b,0xf9,0x93,0xcf,0xf3,0x62,0x40,0x5a,0x29,0xe4, - 0xb1,0x3b,0x54,0x68,0x96,0x9c,0x02,0x35,0xfc,0xaa,0x12,0x41,0x2b,0x91,0x32,0xff, - 0x02,0x68,0xc0,0x73,0x4d,0xc1,0xaf,0x28,0x2c,0xb9,0x3e,0x2f,0xde,0x95,0x76,0x6f, - 0xc3,0x7d,0xfa,0x57,0x5c,0x52,0x20,0xcd,0xdf,0x10,0x8c,0xdd,0xe7,0x9a,0x61,0x43, - 0xd9,0x18,0xd4,0x6b,0x5d,0x69,0xe9,0x69,0x38,0x50,0x73,0xed,0x33,0xb4,0xe4,0xf3, - 0xb0,0x99,0xc2,0x5f,0xc3,0x57,0x8c,0x19,0x41,0x69,0xa9,0x39,0x98,0x5e,0x9f,0x76, - 0xbf,0xf0,0x65,0x76,0x9f,0x31,0xc3,0x83,0x03,0x11,0x70,0x50,0x9e,0x34,0xbf,0x70, - 0xbe,0x5a,0x1b,0x00,0xde,0xe3,0x09,0x85,0x8d,0x26,0x29,0x21,0x01,0x45,0xa0,0x52, - 0xc3,0xc5,0x98,0x22,0xd8,0x11,0x73,0xa1,0x98,0x54,0x94,0x9e,0xe4,0xfc,0x17,0x43, - 0x68,0xad,0x86,0xd1,0xfe,0xc8,0x53,0xcd,0x01,0x1a,0x82,0xea,0xf8,0x15,0xea,0x4a, - 0x1f,0x1f,0x54,0x27,0x9f,0xe7,0xc5,0x60,0xda,0x2a,0xe1,0x6f,0xe0,0x3a,0x6d,0x06, - 0x4b,0x5b,0x05,0x7c,0xf0,0x95,0x68,0x1a,0xf7,0x91,0x7c,0x15,0x66,0x44,0xd3,0x54, - 0xe1,0x0c,0xfc,0x23,0xcc,0xb0,0xbc,0xef,0x5a,0x6d,0x1a,0xff,0x6d,0x19,0x8c,0x17, - 0x6e,0xf9,0x47,0x3e,0x58,0x29,0x2c,0x4f,0x5c,0x59,0x09,0xcb,0xd9,0x75,0x29,0xf3, - 0x6f,0xf7,0x4b,0x9e,0x06,0xbb,0x5a,0x43,0x69,0x78,0x7c,0xa0,0x1c,0x9d,0x1c,0xc0, - 0xf8,0xc0,0x98,0x3e,0xf9,0x3c,0x02,0x97,0x58,0x76,0x10,0xb9,0xf0,0x1b,0x1f,0x18, - 0x53,0x06,0xaa,0x66,0xd9,0xd4,0x8c,0x08,0x1e,0xb6,0x54,0xcd,0xa1,0xd2,0x51,0x73, - 0xf0,0x65,0x73,0x60,0x98,0x57,0x5e,0x10,0x3c,0x3d,0x4b,0x3d,0x5f,0x76,0xe7,0x1a, - 0x96,0xf5,0xf1,0x0b,0xa1,0x86,0xe5,0xea,0x57,0x69,0x5a,0x38,0x2d,0x31,0x98,0x81, - 0x83,0x9e,0x3c,0x3e,0x68,0x14,0xd4,0x9e,0xe5,0x9e,0xaf,0xda,0x67,0x58,0x9e,0xe7, - 0x45,0x3f,0x5f,0x30,0x5c,0x42,0x21,0x3c,0x3e,0x30,0x97,0xd0,0x8e,0x03,0x2d,0x2c, - 0xf1,0x81,0x48,0x05,0xeb,0xfb,0x12,0x08,0x35,0xe4,0xa9,0x77,0x04,0x60,0x8b,0x14, - 0x6a,0xb8,0x5e,0xbd,0x83,0x4e,0x0f,0x4b,0xab,0xf0,0x35,0xef,0x08,0x4c,0xdf,0x22, - 0xa9,0xfc,0x7d,0x03,0x8a,0x75,0xbf,0x85,0x84,0xe5,0xc2,0x57,0xe1,0x2b,0x2c,0x2d, - 0x24,0xe1,0xee,0xc7,0xb5,0x9b,0x11,0x4a,0x5b,0x2e,0xdc,0x81,0x57,0xa6,0x87,0xd2, - 0x28,0xdc,0x01,0xd3,0x99,0x64,0xd9,0x3f,0xc6,0x1d,0x69,0x5f,0x62,0xf7,0x85,0x66, - 0x6c,0x13,0xd2,0xa1,0x9a,0x05,0x43,0xb9,0x79,0x69,0xe9,0x42,0x35,0x53,0x26,0x06, - 0xe6,0x15,0x48,0x9e,0x97,0x06,0x92,0x78,0x6c,0x0d,0xb2,0xf1,0x08,0x54,0x27,0xce, - 0x82,0x84,0xe7,0x51,0x09,0x48,0xfc,0x0a,0x1f,0xe4,0x82,0x9a,0x3c,0x2f,0x77,0x90, - 0xe9,0xac,0x29,0x94,0xaf,0xc0,0x1d,0xe2,0x74,0x76,0x3a,0x74,0x6b,0x5e,0xe6,0x1d, - 0xe2,0x97,0xc6,0x07,0xd3,0xc6,0x07,0xda,0xfc,0xc9,0xfb,0xaf,0xbd,0x23,0xc3,0x94, - 0x06,0x79,0xb3,0x5f,0x4a,0x9b,0x8f,0x83,0x2f,0xe6,0xcd,0x78,0x49,0x7a,0x30,0xfc, - 0x36,0x5e,0x99,0xfe,0x52,0xda,0x83,0x0d,0x6f,0x87,0xfe,0x47,0xde,0x0c,0x23,0x99, - 0xff,0x72,0xfb,0x1d,0xe2,0x83,0xec,0xed,0xd0,0x42,0x9c,0xc6,0x07,0x2b,0x16,0xe6, - 0x65,0xbe,0x34,0xed,0xc1,0x86,0x99,0x78,0x45,0x78,0x89,0x3c,0x98,0xb8,0x83,0x31, - 0xdd,0x32,0x5f,0x30,0xef,0xbf,0x1c,0xf8,0xdd,0xee,0x5f,0xf1,0xd7,0xf8,0x87,0x38, - 0xb0,0xe3,0xfd,0xd3,0x5e,0x82,0xf9,0x38,0x10,0xf3,0xa6,0x1b,0xc2,0xe4,0xf3,0xe3, - 0x0e,0x52,0x81,0x9f,0x98,0xb4,0x84,0xfc,0x51,0x12,0x82,0xe8,0x7e,0x53,0x22,0x01, - 0x1f,0xfc,0x15,0xca,0x9f,0xe4,0xfd,0x21,0x5d,0x58,0xc1,0x96,0x87,0xd2,0xf3,0x6e, - 0x5f,0x67,0x0e,0xae,0xcb,0x4b,0xc3,0x41,0xd3,0xf8,0x20,0x9f,0x2d,0x5f,0x71,0x5d, - 0x9e,0xc4,0x92,0xd3,0x6f,0xd7,0xd2,0x3c,0xf9,0x4b,0xe9,0x97,0xa1,0x89,0xa5,0xd5, - 0x0b,0xf7,0xc3,0x5f,0x43,0xae,0x21,0xd4,0x03,0x1f,0xe0,0x6b,0x7a,0xcc,0x2b,0xd3, - 0x2d,0xfb,0xe7,0x76,0x3f,0x53,0x75,0xea,0x22,0x36,0x54,0xe3,0x21,0x3c,0x94,0xe6, - 0x11,0x4c,0x0c,0x84,0x30,0xda,0x47,0xe6,0xc0,0xf2,0x3c,0xb7,0xfb,0x9b,0x42,0x3b, - 0x70,0xff,0xd8,0x00,0x77,0x57,0x03,0x55,0xfd,0xb8,0x7f,0xb8,0xdb,0x00,0x07,0x4a, - 0x18,0x77,0x94,0x39,0xb0,0xce,0xaf,0x99,0x1d,0xec,0xb9,0xcf,0xf3,0x15,0xee,0x10, - 0xd4,0x1a,0x82,0xea,0x7d,0xf6,0x19,0xfe,0xc4,0x80,0xce,0x10,0xd3,0x82,0x89,0x01, - 0x24,0x9f,0x07,0x44,0x21,0x68,0xdc,0xe7,0x99,0x41,0xa5,0x1a,0x3e,0x50,0x67,0xd8, - 0xd3,0x6a,0x12,0x57,0xec,0x69,0xfe,0xf1,0x5f,0xa5,0x4d,0x7e,0x5d,0x04,0x1c,0x9a, - 0xa6,0x29,0x0a,0x62,0x26,0x05,0x25,0x9f,0xa4,0x34,0x20,0x04,0xa3,0x09,0x74,0xa6, - 0xa2,0x20,0xc2,0x01,0x0a,0x45,0xcb,0x6a,0xc2,0xed,0x77,0x01,0x61,0x4c,0x57,0xef, - 0x34,0xc2,0x04,0x18,0x53,0x55,0x17,0x62,0x1b,0x73,0x80,0x40,0x26,0x9d,0x0f,0x80, - 0x52,0xcb,0xf3,0xe0,0x7a,0xe2,0x09,0x80,0xeb,0x44,0x14,0xfb,0x7c,0xc0,0xa5,0xbd, - 0x10,0x22,0xdb,0x70,0x70,0x3d,0xbf,0x92,0x90,0x3f,0xc9,0x7f,0x61,0xad,0x96,0xd0, - 0x17,0x38,0x5f,0x9c,0x10,0x44,0x39,0x21,0xe9,0x7e,0x98,0x83,0x03,0xfc,0xf4,0xf7, - 0xc3,0x34,0xc8,0xb5,0x7c,0x2f,0x18,0x97,0x27,0x02,0x63,0x92,0x47,0xb0,0x03,0x8a, - 0x4e,0x03,0x07,0x79,0xe6,0x40,0xe1,0xf4,0xaf,0x3b,0x40,0xb1,0xce,0x97,0x12,0xf3, - 0x35,0x94,0x3f,0xf3,0xc1,0xae,0xe1,0xe0,0x34,0x2c,0x80,0x0c,0x7e,0xe5,0xb4,0x56, - 0xc8,0xb3,0xfd,0xf9,0xaf,0x92,0x3f,0xd3,0x84,0xf9,0xda,0xd2,0x60,0x4e,0x34,0xf7, - 0x45,0x61,0xbe,0xb1,0x54,0xcb,0xc9,0x95,0x70,0x70,0x3b,0x5e,0xc9,0x95,0x7a,0x85, - 0xfc,0xea,0xa5,0xc1,0x2f,0x2b,0xd6,0xfd,0x03,0xb7,0xa4,0xd5,0xf5,0xfc,0xad,0xe7, - 0xab,0x11,0x69,0x67,0xda,0xb7,0x70,0x70,0x6f,0xeb,0x8c,0xa7,0x13,0x57,0x70,0x20, - 0x8c,0x0f,0xac,0xf3,0x69,0x02,0xe8,0x6b,0x09,0x30,0x18,0x24,0x21,0xd8,0x0c,0xe3, - 0x8f,0xb1,0x59,0xfa,0x33,0xcf,0x03,0xab,0x42,0xd3,0xf3,0xa4,0x3b,0x04,0x88,0xd4, - 0x72,0x45,0xe6,0x17,0xa6,0x47,0xa4,0x95,0xd3,0xf3,0x9a,0xee,0xc8,0x9f,0xce,0x6a, - 0x27,0x06,0xd6,0xf9,0xb7,0x07,0xa7,0xdf,0x27,0x7d,0x45,0x90,0x20,0x8d,0x0f,0x6e, - 0x17,0xbe,0xa2,0xdd,0x8e,0x4a,0x4b,0xfa,0x0a,0xcc,0xc0,0x81,0x72,0x9f,0x34,0x43, - 0x98,0x61,0xd9,0x0f,0xdc,0xbf,0x80,0x92,0x4f,0xc1,0xbd,0x99,0xef,0xa7,0xc1,0x70, - 0xae,0x9a,0x16,0x10,0x70,0xc0,0x70,0x40,0x57,0xdc,0x9b,0x17,0xdc,0x90,0xab,0xae, - 0xb5,0xde,0xde,0x26,0x11,0x5e,0x17,0xc9,0x25,0xd9,0x04,0xc2,0x34,0x5d,0xb9,0x76, - 0xe0,0xce,0xb5,0xce,0xb7,0xa7,0xe7,0x08,0x4d,0xc6,0x0a,0xcf,0xf5,0x4b,0xc5,0x2f, - 0xc3,0x69,0xe3,0x56,0x4f,0xc6,0xc4,0x20,0x73,0x29,0x2a,0x01,0x73,0x60,0x7d,0x9e, - 0x8c,0xb4,0x87,0xaa,0xef,0x8f,0xfe,0xb5,0x7a,0x53,0x9f,0x84,0xda,0x3f,0xf2,0xd7, - 0xea,0x0c,0x84,0x01,0xf0,0x36,0xfb,0x22,0x0e,0xee,0x78,0x48,0x78,0x9b,0xfd,0xfd, - 0x9c,0x19,0x86,0x65,0xbe,0xfc,0xb7,0xfe,0xd7,0xa3,0xcf,0x76,0x14,0x67,0x7c,0xe1, - 0x2e,0x1c,0xec,0xeb,0x28,0xbe,0x53,0xbe,0xf7,0xae,0xfe,0x2d,0xcf,0x16,0xfe,0x3c, - 0x43,0xf6,0xdf,0x75,0xda,0x1c,0x58,0x9f,0x67,0xd1,0xd5,0x7b,0xae,0xfe,0xfa,0xf9, - 0x0b,0x1f,0x8e,0x56,0xfd,0x10,0x07,0x07,0x2e,0x7c,0x3c,0xba,0xe8,0xca,0xb2,0xdf, - 0x6d,0xbd,0x3a,0x70,0x79,0x74,0xd1,0x23,0xcb,0xae,0x9a,0x03,0xf8,0xdf,0xf8,0xf1, - 0x3d,0x9e,0x31,0xc7,0x7f,0x67,0x74,0xcb,0xaa,0xd9,0xa3,0x8e,0xa7,0x6a,0xae,0x46, - 0xb7,0xfc,0xb3,0xef,0x5f,0xef,0xfc,0xe1,0x6b,0x77,0x5e,0x78,0xec,0x72,0xd5,0xd5, - 0x3b,0x6f,0xe1,0x83,0x01,0xeb,0xfc,0xaa,0x47,0xee,0xf9,0xdd,0xd6,0x03,0x03,0x1f, - 0x4e,0x3c,0xc6,0x87,0x97,0x27,0x1e,0x0c,0xe7,0xdf,0xf3,0x3b,0xf3,0x09,0xad,0xf3, - 0xff,0xef,0xf6,0xce,0x2f,0xb6,0xa9,0x2a,0x8e,0xe3,0xbf,0xdb,0x9e,0x96,0x96,0xb5, - 0xe3,0x5e,0xe8,0xa0,0xe0,0xb2,0x74,0xeb,0xd8,0xa6,0x12,0x73,0xc1,0x8d,0x3f,0xc1, - 0xb0,0xb3,0xb5,0xdd,0xca,0xe4,0x4f,0x27,0xa0,0x40,0x8c,0xe9,0x90,0xa8,0xf1,0x69, - 0xc3,0x17,0x13,0x03,0xdc,0x42,0x21,0xc4,0x40,0xb2,0xcc,0xa9,0xd3,0x4c,0x1d,0x89, - 0x1a,0x62,0x40,0x63,0x8c,0xc6,0xc4,0x98,0x5c,0x88,0x08,0x84,0x87,0x2d,0x06,0x12, - 0xa3,0x89,0x40,0xdc,0x8b,0x09,0x09,0x7b,0x20,0x31,0x3e,0xcc,0xf9,0xfb,0x9d,0x7b, - 0xdb,0x9e,0x62,0x84,0x88,0xdc,0x17,0x73,0xbe,0x4f,0xdf,0x9d,0x9d,0xfe,0x76,0x7a, - 0xfa,0xbb,0xbf,0xfb,0xf9,0xdd,0xdb,0x76,0xc9,0x03,0xd9,0x6b,0x23,0x6b,0xa6,0x8f, - 0x0f,0xac,0xa7,0x07,0x7e,0x3e,0x7d,0x02,0x97,0xbd,0xe5,0x97,0x45,0x14,0x21,0x19, - 0x27,0x53,0xbc,0x39,0x20,0xcf,0xd7,0x0e,0x0d,0x66,0xea,0xf5,0xd6,0xba,0x7e,0xbb, - 0x69,0x90,0x8f,0x43,0x6b,0x2c,0x7c,0x1e,0x41,0x71,0x5c,0x6f,0x65,0xda,0x79,0xdf, - 0x90,0x8d,0xa6,0x5e,0x93,0xf7,0x93,0x1d,0x19,0x02,0xc1,0x87,0xc5,0x23,0x2e,0x0d, - 0x7e,0xe7,0x12,0x63,0xc0,0x31,0x29,0x3d,0x20,0xcf,0xf7,0x3b,0x58,0x18,0x65,0x87, - 0x0a,0x2e,0x1f,0x5a,0x58,0x66,0x85,0x39,0x2a,0x0c,0xd5,0xe7,0xaa,0x1d,0xca,0xe3, - 0x41,0x1a,0xd4,0x0b,0x2e,0xb6,0xc5,0x4b,0xd8,0x16,0x77,0x40,0xce,0x17,0xd4,0xbb, - 0xe4,0xf9,0xa1,0xf4,0x3e,0xfa,0xa7,0x0e,0x35,0x70,0x6c,0xef,0x2a,0xad,0xbe,0xd8, - 0x9b,0x30,0x2e,0x32,0x34,0x56,0x6f,0xb3,0x71,0x19,0x33,0x04,0x4d,0xc2,0xa8,0x5a, - 0x3f,0xe4,0xf5,0xd0,0x51,0x5f,0x80,0x4e,0x85,0x10,0xd7,0x89,0x06,0x39,0xd2,0x53, - 0x15,0x28,0xca,0xf1,0x23,0xac,0x89,0xbe,0xcb,0x69,0x10,0x8e,0x23,0x28,0x22,0x16, - 0xe6,0xf5,0x31,0xf6,0x02,0x99,0x41,0x7d,0x9c,0x35,0x6b,0x61,0xab,0x9b,0x57,0xd5, - 0x93,0x47,0x59,0x9f,0xb5,0xf8,0x54,0xe6,0x53,0x78,0x84,0xed,0x2e,0x2c,0x9c,0x48, - 0x9f,0x32,0xd0,0x9c,0x75,0x4d,0x9f,0x33,0x22,0xad,0xde,0x8e,0xc2,0x22,0x88,0xfd, - 0x18,0x78,0x57,0xdf,0x44,0x66,0x0a,0xda,0xb5,0x4d,0xb0,0x0d,0x98,0x1d,0x30,0xd1, - 0xf4,0xc3,0x62,0x3b,0x00,0x1a,0xaf,0x3c,0x00,0x5b,0x55,0x3d,0x81,0x34,0xd8,0x0f, - 0x74,0xcf,0x01,0xdb,0x36,0xea,0x54,0xd3,0xf8,0xac,0x58,0x4e,0x18,0x03,0x10,0x2b, - 0xca,0xb7,0xaf,0x31,0xbe,0x68,0x57,0x87,0x13,0xe0,0x5c,0x29,0xd0,0x13,0x4c,0x34, - 0x98,0x45,0x71,0x87,0x80,0x2a,0x35,0x24,0x12,0x50,0x35,0x9f,0xe5,0xb5,0x31,0x2c, - 0x92,0x71,0xaa,0xf8,0x71,0x2c,0xfd,0xc8,0x23,0x79,0x51,0x36,0xd7,0x55,0x4c,0x79, - 0xbe,0xae,0x81,0x8f,0x36,0xad,0xc5,0xf9,0xc4,0xe7,0x18,0x9a,0xf0,0x1d,0xa6,0x15, - 0xe8,0x8c,0xe6,0x8a,0x13,0x1f,0x5a,0x04,0x45,0x50,0xc5,0x87,0xcc,0x31,0xab,0x08, - 0x9c,0xda,0xac,0xca,0xf9,0x94,0x63,0x67,0x4e,0x65,0xfc,0x4e,0x3e,0x64,0x15,0x3e, - 0xf4,0xd1,0x5d,0xee,0xd2,0x0e,0x71,0xfc,0xd1,0x14,0x90,0x06,0xe7,0x24,0x53,0xac, - 0x1a,0xc1,0x13,0x81,0xbc,0x1e,0xc1,0x6f,0x21,0x38,0xec,0x1a,0x83,0x4e,0xbb,0x3b, - 0x4b,0x06,0x47,0x30,0x1f,0x2a,0xeb,0xd1,0xba,0x65,0x2c,0xfc,0x07,0x53,0xc9,0x87, - 0x1c,0xb8,0xf1,0x23,0xd5,0xf1,0x23,0x52,0xfc,0x90,0x94,0x6f,0x3c,0xc3,0xf1,0x85, - 0x8c,0x41,0x86,0x88,0xdf,0x31,0x06,0x67,0x83,0x25,0xe3,0x8c,0x68,0xdd,0x7a,0x69, - 0x3d,0x59,0x4e,0x58,0x58,0x9f,0x9f,0x17,0x47,0x3e,0xec,0x47,0x2c,0x64,0x55,0xa6, - 0xcb,0x31,0x50,0xe6,0xb1,0x2c,0x11,0x37,0x65,0xbe,0xb8,0x04,0x4c,0x8d,0x3f,0xf2, - 0x21,0x08,0x2c,0x24,0x50,0xc4,0xc6,0xcd,0xd4,0x43,0xd2,0xd5,0x10,0x9e,0x79,0x1a, - 0x69,0x90,0xe5,0x1b,0x73,0xb0,0x18,0x41,0xf1,0xaa,0xc0,0x42,0x5f,0x19,0x14,0x87, - 0xac,0x2b,0xbc,0x23,0x1e,0xe0,0x12,0xcf,0xf7,0xb0,0xa1,0xc3,0x3b,0x11,0xea,0x0c, - 0xc4,0x42,0xc4,0x3c,0xc7,0x58,0xf5,0xd2,0xc8,0xce,0x75,0x76,0x25,0xbe,0xd6,0xe3, - 0x1b,0xb2,0xc6,0xf3,0xad,0x88,0x85,0x41,0x9a,0xf6,0x62,0x3c,0x4c,0x58,0x48,0x23, - 0x64,0xc4,0xaf,0x58,0x65,0x7e,0x2e,0xd3,0x13,0x70,0xf8,0x93,0x1f,0x9d,0x37,0x64, - 0x3d,0x4b,0xb4,0xf9,0xbd,0xd3,0x9f,0x3a,0xa0,0x48,0xe8,0xc8,0xce,0x55,0x5e,0x2f, - 0xa0,0x7b,0xa3,0xc8,0x87,0x69,0x36,0x8c,0xcf,0x6e,0xa3,0x53,0x7f,0x9a,0xa9,0xfe, - 0x64,0xd9,0x88,0x53,0x9a,0xb2,0x4c,0xda,0x7f,0xcc,0xdb,0x01,0x2b,0x9e,0x0f,0x8e, - 0x19,0x1f,0xa3,0x59,0x86,0xa0,0xa8,0x1d,0x85,0x81,0x42,0xdc,0x35,0x56,0x7c,0x40, - 0x14,0xa2,0xb2,0x32,0x79,0xf6,0xaa,0x56,0x0b,0x29,0x0b,0x26,0xac,0xb5,0x5a,0x03, - 0xf8,0x2d,0xfd,0x3a,0x23,0xd3,0x6b,0x19,0x65,0x23,0xe5,0xb3,0xf6,0x14,0x7d,0x45, - 0x4e,0x9b,0x2f,0x0b,0x6f,0x58,0x09,0x6b,0xa9,0x29,0xd2,0xa6,0x99,0xb0,0x30,0xab, - 0x8d,0x38,0xa0,0x98,0x95,0xf3,0x41,0xeb,0x66,0x89,0x93,0x22,0x3f,0x5f,0xb7,0x90, - 0x06,0x27,0x82,0x4e,0xda,0xb8,0x7c,0x98,0x70,0xf9,0xb0,0xea,0xf8,0xe2,0x85,0xd8, - 0xaa,0x0c,0x1e,0x8e,0x90,0x2b,0xe8,0x66,0x20,0x62,0xa4,0x58,0x0e,0x8f,0xfb,0x74, - 0xc8,0x20,0x3e,0x14,0x06,0xa4,0xfd,0xc1,0x96,0xf2,0x62,0x0c,0xa7,0xc1,0x93,0x60, - 0xda,0xb1,0x09,0x2d,0xa2,0xa5,0x00,0xcf,0xee,0x38,0x42,0xc6,0x16,0x86,0x57,0x8e, - 0x17,0x2c,0x1f,0x66,0x8c,0xf8,0x10,0xbd,0x0f,0x2b,0x8e,0x56,0xbe,0x7a,0x97,0x90, - 0x8d,0xb4,0x9e,0xa6,0x85,0xc4,0x87,0x11,0xcb,0xdf,0x84,0xc7,0x45,0x53,0x63,0x5b, - 0x68,0xbe,0xcb,0x87,0x65,0x63,0x49,0xeb,0xd1,0x20,0x24,0x8a,0x0c,0x66,0x69,0xd1, - 0xa9,0x36,0xe5,0xfa,0x43,0x26,0x80,0xf5,0xd9,0xb7,0x4b,0xde,0x1f,0xf0,0xed,0x85, - 0xa5,0xd0,0xd2,0x35,0x35,0x7c,0x28,0x0f,0xef,0x40,0x0b,0xdf,0x38,0x5c,0xaa,0x3f, - 0xc3,0x41,0x61,0x7c,0x61,0xab,0x7c,0x49,0x8c,0x67,0xf2,0xa3,0x6b,0x81,0x5e,0xaf, - 0x63,0x13,0xc5,0xb5,0x5a,0x6d,0x38,0xe5,0xbc,0x5e,0x34,0xa2,0x5f,0x0f,0x0a,0x53, - 0x90,0xfa,0xd3,0x1c,0x3e,0xd1,0x75,0xb9,0xda,0x41,0xff,0x5b,0xf0,0x11,0xbd,0xfb, - 0x41,0xf7,0x33,0xb8,0x51,0x32,0x67,0x4b,0x46,0xaa,0x3f,0x8c,0x41,0x07,0x8f,0xe6, - 0xfc,0xbb,0xad,0x2b,0xb0,0x92,0x47,0xe9,0x9f,0xd6,0x5f,0x25,0xb0,0xcc,0xf9,0x63, - 0x64,0xb8,0x30,0x95,0xf7,0x87,0xf3,0x4c,0x8a,0x61,0x37,0x6a,0xf6,0x00,0xd5,0x07, - 0x32,0x11,0xa3,0xda,0x60,0xe9,0x30,0xe4,0xfa,0xc3,0x21,0x89,0x55,0xda,0x2d,0xe1, - 0x58,0xcb,0xe9,0x8a,0xb0,0x7b,0xd5,0xd0,0x31,0xa2,0x54,0x56,0xf6,0x27,0x9b,0x76, - 0xf9,0xd0,0xda,0xbb,0x47,0x18,0x09,0x0b,0x85,0x49,0xc9,0x7c,0x88,0xf5,0x27,0xbd, - 0xbd,0xbf,0x2e,0x98,0x49,0x41,0x6c,0x7b,0xce,0x88,0x21,0x1f,0x1a,0x3c,0x2d,0x0c, - 0xd6,0x1f,0x20,0xd3,0x85,0x46,0xca,0x1f,0x4a,0x40,0xaa,0x7c,0x05,0xaa,0x7c,0xfa, - 0xa1,0x40,0x42,0xcb,0x62,0x8e,0x53,0x6e,0x62,0xe3,0xe0,0x1a,0x90,0x84,0x10,0x88, - 0x7c,0x08,0x2b,0xf4,0x12,0x16,0xd2,0x48,0xd1,0xe1,0x43,0x70,0x41,0x11,0x34,0xbd, - 0xbc,0x9e,0xcd,0xfe,0x6d,0x5d,0xc5,0xa9,0xc6,0xd5,0xb0,0xd9,0xb7,0x88,0x5f,0x99, - 0x6a,0x6c,0x0f,0x6d,0xf6,0x6d,0x43,0xd3,0xd1,0x1e,0x75,0x46,0x3a,0xda,0x23,0xd2, - 0x7a,0xf0,0xf9,0xee,0xeb,0xaa,0x1f,0xee,0x6d,0x32,0x2e,0x35,0xef,0xc1,0xb3,0xff, - 0xe1,0x84,0x71,0x29,0xe0,0x62,0xc0,0x45,0x97,0x07,0x62,0x52,0x7f,0x0a,0x02,0x0b, - 0x89,0x0f,0x6b,0xfa,0xfa,0x64,0x3e,0xfc,0xb0,0xc4,0x87,0x7b,0xab,0xf9,0x50,0xd0, - 0x17,0xf1,0xe1,0xfa,0x83,0x5b,0x65,0x3e,0xbc,0xfd,0x80,0xf8,0x50,0x60,0xe1,0x6f, - 0xc3,0x73,0xb3,0x9d,0x7f,0x38,0xa0,0xb8,0xbf,0xf9,0x03,0xc2,0xc2,0xe1,0xb7,0x67, - 0x97,0xcf,0xb9,0x46,0x9e,0x2f,0xfe,0xfa,0xef,0xd3,0x38,0xff,0x4f,0x07,0x14,0x67, - 0xd7,0x1f,0x24,0x2c,0x9c,0xbe,0x35,0xbb,0x7e,0xce,0x35,0x55,0xf3,0x1b,0x5c,0x3e, - 0x4c,0x36,0x6c,0xb9,0x36,0xb2,0x12,0xf9,0x30,0x79,0x60,0xcb,0x05,0x41,0x98,0x49, - 0x81,0x9a,0xc5,0x5b,0xff,0x61,0xfd,0x26,0x24,0x34,0x7a,0x7b,0xaa,0x09,0xa9,0xc8, - 0xfd,0x47,0x51,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0xfa,0xbf,0x4b, - 0xf4,0x0e,0x4c,0xf5,0x0e,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a, - 0x77,0x97,0xe8,0x1d,0x82,0xaa,0x77,0x50,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52, - 0x52,0x52,0xba,0xbb,0x44,0xef,0x10,0x12,0xbd,0x03,0xfe,0x14,0x58,0xfb,0xdc,0x2e, - 0xde,0xb9,0xe1,0xb5,0x5d,0x1e,0xfd,0xb5,0xb6,0x0b,0xb0,0x82,0x27,0xd3,0x10,0xb3, - 0xbd,0x89,0xcf,0xe6,0xbf,0xf4,0x8e,0x55,0x53,0xf7,0x4d,0xd6,0x9b,0xf0,0xd0,0x39, - 0x49,0xeb,0xe7,0xd0,0x69,0x7b,0x13,0x9f,0x25,0x46,0x4f,0xda,0xcb,0xae,0x9c,0x38, - 0xe6,0x4d,0x78,0x30,0x27,0xcd,0x9b,0x3c,0x39,0x68,0x9b,0xb6,0x37,0xf1,0xa3,0x6b, - 0xf6,0x1f,0xb1,0xeb,0x3f,0x7b,0x7e,0xab,0x37,0xe1,0x71,0xff,0x9d,0xf5,0x7b,0xb5, - 0xff,0x91,0xd6,0x71,0x0b,0x9e,0x58,0x32,0xe1,0xdd,0xfe,0x2f,0xc0,0xfc,0xd9,0x0a, - 0x5e,0xed,0x7f,0x6d,0xcb,0xd7,0x33,0xf0,0xd0,0x8e,0x2f,0x37,0x7a,0x13,0x1e,0xf7, - 0xdf,0x59,0xbf,0x67,0xf9,0xff,0x58,0xdd,0x27,0xbc,0xe6,0x95,0xd1,0x7b,0x7d,0xe6, - 0xff,0x7e,0x65,0x4e,0x76,0x62,0xfe,0x1c,0xf4,0x2e,0xff,0x75,0x6d,0x35,0x2c,0x0f, - 0x3f,0xec,0x5d,0xfe,0x3b,0xeb,0xf7,0x6a,0xff,0xa3,0x8d,0xe9,0x1e,0x58,0x75,0xbb, - 0xc5,0xab,0xfc,0x31,0xe7,0x6c,0xaa,0x9f,0xe6,0x8c,0xed,0x4d,0x7c,0x16,0x1a,0x7a, - 0xd3,0x5e,0xfd,0xc5,0xa8,0x67,0xf5,0xdf,0x5d,0xff,0xdf,0xbf,0x99,0xe0,0xc1,0x88, - 0x25,0x47,0xcf,0xd8,0xc9,0x25,0x23,0x9e,0xd5,0x9f,0xb9,0x19,0xaa,0x9f,0x33,0x5e, - 0xed,0xff,0x82,0x0d,0xbf,0xde,0xb2,0x3b,0x7e,0x7a,0x66,0xd2,0x9b,0xf0,0xb8,0xff, - 0xce,0xfa,0x3d,0xdb,0xff,0x0d,0xc7,0xdf,0xb7,0x1e,0x5f,0x72,0x3a,0x7c,0xef,0xa9, - 0xf7,0x25,0x73,0x6e,0x92,0xea,0xa7,0x67,0xf9,0x1f,0x6c,0x38,0xf3,0xb2,0xd5,0xf2, - 0xed,0xcf,0x69,0x6f,0xc2,0xe3,0xfe,0x3b,0xeb,0xf7,0x6c,0xff,0x97,0xef,0xf8,0x0a, - 0x12,0x75,0xef,0x79,0x57,0x7f,0xe6,0xa8,0x7e,0x7a,0x97,0xff,0xcb,0x02,0x8d,0x7c, - 0xc3,0xe9,0xe8,0x65,0x6f,0xc2,0xd3,0x97,0x9c,0x88,0xf5,0x7b,0xb3,0xff,0xa6,0xf8, - 0x46,0x8a,0x1b,0x3f,0x98,0x60,0xd1,0x67,0x44,0xfc,0x26,0xf0,0x7f,0x7d,0x3f,0xc1, - 0x7d,0x6c,0xc0,0x84,0x09,0x4d,0x8a,0xb9,0xfb,0xce,0x79,0x7f,0x01,0xf4,0xb7,0xc1, - 0xde,0xf0,0x33,0x01,0x00, + 0x1f,0x8b,0x08,0x08,0x7a,0x8e,0xc6,0x43,0x00,0x03,0x68,0x68,0x34,0x30,0x35,0x5f, + 0x31,0x5f,0x30,0x36,0x2e,0x62,0x69,0x74,0x00,0xec,0xfd,0x7f,0x7c,0x14,0x55,0x9a, + 0x2f,0x8e,0x3f,0x75,0xaa,0x12,0x4e,0xba,0x3a,0xe9,0x22,0x09,0x4e,0x54,0xc4,0x4a, + 0x27,0x30,0x4d,0xec,0x84,0xa6,0x83,0x21,0x42,0x48,0x2a,0x9d,0xe8,0x44,0x40,0xe9, + 0x71,0xdc,0x59,0x76,0xae,0x77,0xb6,0x65,0x98,0xbd,0x99,0xb9,0xe8,0x46,0xc7,0xbb, + 0x97,0xf1,0xce,0x8f,0x93,0x4e,0x80,0x4e,0x82,0xd0,0x20,0x33,0x46,0x87,0x71,0x9b, + 0x10,0x35,0x2a,0x33,0xdb,0x04,0x94,0xf0,0x63,0xb0,0x12,0xa3,0x36,0x10,0x20,0x32, + 0xdc,0x19,0x54,0x46,0x1b,0x8c,0x4c,0xd4,0xe8,0x04,0x44,0x4d,0xf8,0xf9,0x7d,0x4e, + 0x75,0xa7,0xbb,0x1a,0x77,0xf7,0xce,0xfd,0xdc,0xd7,0xf7,0xf3,0xda,0xd7,0xeb,0x73, + 0xb3,0x7f,0xec,0x99,0xea,0x43,0x59,0x75,0xea,0x9c,0xe7,0x79,0x3f,0xbf,0xde,0x0f, + 0x64,0xd8,0x46,0x63,0xff,0x07,0x20,0xdc,0x0f,0xb6,0xfa,0xfa,0x39,0xae,0x5b,0xff, + 0x7e,0xf6,0xdf,0xbb,0xca,0x4a,0x1e,0xfc,0xde,0x72,0x58,0x06,0xb2,0xfb,0x47,0xb7, + 0xba,0xbe,0xff,0xc8,0x43,0xb3,0xe7,0xcc,0x81,0xef,0xe1,0xff,0x72,0xb9,0xca,0x66, + 0xb9,0x66,0xcf,0x9a,0xed,0x86,0xe5,0x90,0x31,0xbb,0x7c,0xde,0xec,0x39,0xf3,0x4a, + 0x6f,0x85,0xef,0x83,0x50,0xda,0x79,0x15,0xff,0x5e,0x78,0xf2,0x6f,0xfe,0xc1,0x05, + 0x4c,0x00,0x80,0x49,0x2e,0xc1,0xc7,0xff,0xbf,0xec,0x12,0x54,0x01,0x58,0x55,0xb1, + 0x0b,0x74,0xfe,0xbf,0x21,0xfe,0x7b,0x86,0x0b,0x54,0xf3,0xff,0x16,0x5c,0xa0,0x81, + 0x17,0xb4,0xb5,0x6a,0x36,0xfc,0x15,0x7f,0x92,0xc4,0x26,0x86,0x7f,0xd5,0x7c,0x48, + 0xcc,0xbf,0x7a,0x90,0xfd,0x9b,0x93,0x92,0x7f,0x55,0xe7,0x42,0xf1,0x91,0x4a,0x5c, + 0xff,0xeb,0xe9,0x42,0x2d,0x4c,0xdc,0xf5,0xbd,0xb7,0xff,0x9a,0xfb,0xcf,0xff,0x62, + 0xe2,0xfe,0xff,0xbb,0xf3,0x41,0xf9,0x2b,0xa6,0xe3,0xfb,0x4e,0x0c,0xde,0x53,0x04, + 0x1f,0xe4,0xc1,0x75,0x90,0xc6,0x80,0x0f,0xd2,0x41,0xf8,0x57,0x06,0xf3,0xfb,0x27, + 0xe6,0xeb,0x8d,0xfb,0xe0,0x08,0x2b,0x55,0xad,0x11,0xd1,0x0d,0xef,0xe5,0x57,0x45, + 0x96,0x9c,0xcb,0xd9,0xd7,0x7c,0xf5,0x7b,0x73,0x23,0xb6,0x73,0x62,0x39,0x3b,0x09, + 0x3f,0x1a,0xb5,0x8e,0xe5,0x8c,0x4a,0x0d,0x13,0xf3,0xe9,0x08,0x6d,0x65,0xee,0x7c, + 0x1a,0x90,0xed,0x70,0x48,0x29,0x19,0x92,0x1b,0x49,0xd1,0xd2,0x3d,0xd9,0x25,0x47, + 0x6c,0xfb,0x48,0x97,0x16,0x90,0xca,0x22,0x96,0x1e,0x31,0x2c,0x4d,0xac,0x62,0x44, + 0x5a,0xbb,0xa5,0x55,0x98,0xa1,0x65,0x30,0xbb,0x0f,0x1e,0x17,0x9c,0xda,0x8d,0x2e, + 0xb2,0x56,0xda,0xa1,0x3a,0x41,0xce,0x25,0x54,0xd9,0x20,0x86,0x74,0xea,0x22,0xe7, + 0x84,0xc4,0xfd,0xa5,0x6d,0xe9,0xad,0xcc,0xae,0x65,0x04,0x48,0x3e,0x6b,0xcb,0x2b, + 0xd1,0x64,0xd6,0xba,0x0d,0xf6,0x92,0x12,0x62,0x09,0xf6,0x75,0x41,0x06,0xfb,0x07, + 0xdd,0x12,0xf6,0x8c,0x4a,0xbe,0xf8,0xfc,0xea,0x29,0x2b,0x20,0xd2,0x38,0x67,0x4e, + 0x71,0xab,0x28,0xc2,0xdb,0x5a,0xa5,0xbe,0x64,0x8e,0xfc,0x5b,0xed,0x62,0xb0,0x64, + 0xb0,0x26,0x5c,0x9a,0x05,0xdf,0x09,0xd9,0x7b,0xad,0xe1,0x82,0x41,0x98,0xb8,0x7f, + 0x48,0xd8,0x0c,0x97,0x68,0x15,0xcb,0xd2,0x73,0xba,0xe1,0x8a,0x50,0xa5,0x2f,0x89, + 0x36,0xd5,0xc3,0x05,0xa8,0xd4,0xd7,0x87,0x0b,0x46,0xd8,0x85,0x8c,0xaa,0xb3,0xb6, + 0x51,0xb1,0x0b,0x26,0xee,0xdf,0xaf,0x6c,0x83,0x71,0xbf,0xdb,0x63,0x63,0xe2,0x29, + 0x38,0xa8,0xb9,0xf5,0x69,0x3b,0x73,0xb6,0xd1,0x43,0xe0,0xde,0x60,0xdd,0x29,0x3a, + 0xe1,0x10,0x2b,0xd3,0x97,0x84,0x6b,0x46,0x41,0x8d,0xcf,0x3f,0x91,0x56,0x21,0x6c, + 0xd7,0xec,0x63,0x8b,0x24,0x32,0xcc,0x5a,0xc1,0x1d,0x99,0xda,0x49,0x9c,0xd0,0x26, + 0xd9,0x19,0x2d,0xc7,0xc1,0x3b,0x7e,0xbb,0x2e,0x87,0xc9,0x17,0xb8,0xfb,0x27,0xde, + 0x77,0xb1,0xb5,0x5b,0xdb,0x16,0x92,0x67,0xa4,0xbf,0xaa,0x36,0x0a,0x85,0xa1,0x0c, + 0x17,0x59,0x0d,0x1b,0x24,0x9f,0x6e,0x71,0x10,0x02,0xcf,0xd7,0xe2,0x7c,0x17,0x19, + 0xc3,0xb3,0x12,0xfb,0x1b,0x85,0xef,0xb2,0x97,0x59,0xf1,0x29,0xd9,0x97,0x7e,0x4c, + 0x12,0x98,0x1a,0xa5,0x27,0x48,0xb6,0xba,0x69,0x63,0x7e,0xd4,0x52,0x8f,0x83,0x5d, + 0x41,0x21,0x2a,0xaf,0xd4,0xae,0x24,0xee,0x5f,0x07,0x8b,0xb5,0x6e,0xa8,0x60,0xb6, + 0x7c,0x51,0xef,0xeb,0x85,0x39,0x8a,0x1c,0x16,0x9b,0xc9,0x9b,0x10,0xd6,0x4a,0x94, + 0x36,0x20,0xef,0x87,0x82,0xba,0xcd,0x25,0x1e,0x23,0x13,0xfb,0x41,0xbb,0x69,0xdf, + 0xd0,0x17,0x50,0xaa,0xdb,0xb6,0x88,0x83,0xda,0x65,0xe5,0x95,0xda,0x59,0x1b,0xc4, + 0xf3,0xf0,0x3c,0x54,0xd5,0x66,0x0e,0x0a,0xe7,0x16,0x1f,0x82,0xf9,0xfd,0xeb,0xc3, + 0xe2,0x60,0xfa,0xc4,0xfa,0x50,0x69,0x1b,0xf4,0x41,0xf7,0x54,0x1b,0x2b,0x50,0xe1, + 0x22,0x71,0x33,0x67,0x38,0xc7,0x09,0x17,0xc1,0xad,0x5b,0x43,0xe2,0xc8,0xe4,0xcf, + 0x04,0x1c,0x84,0xc5,0x8f,0x94,0x89,0xf5,0x8f,0xe4,0x6d,0x66,0xab,0xe1,0xd6,0x81, + 0x2c,0x8d,0x04,0x95,0x1d,0xe9,0x2a,0xff,0xfa,0x79,0xb0,0x1f,0x1c,0x3a,0xf5,0x91, + 0x93,0xf0,0x12,0xb9,0x55,0xa7,0x0d,0xe4,0x5c,0xe2,0xfb,0xaa,0x30,0x0d,0x1e,0x63, + 0xf9,0x2e,0x39,0x42,0x1e,0xa7,0xcf,0xb1,0xfc,0x10,0x5d,0x49,0x9e,0x86,0x57,0x58, + 0x7e,0x14,0x07,0xef,0xc2,0xef,0x9a,0xbf,0x7e,0x9a,0xae,0xcc,0x8e,0x26,0xd6,0xbf, + 0x5e,0x5a,0x0b,0x4d,0x9a,0x53,0xb7,0xe4,0x2d,0x4b,0x63,0x3b,0x74,0x5c,0x9f,0x72, + 0x92,0xa5,0xed,0x08,0x3a,0x86,0xe8,0x6d,0xf0,0xa9,0xb6,0x7d,0xe3,0x0c,0x1f,0xfe, + 0x17,0x8f,0x25,0xf6,0xe7,0xf0,0x94,0x7a,0xfa,0x3a,0xb8,0x99,0x6d,0x79,0xd3,0x1e, + 0xeb,0x47,0x1d,0xdd,0x5d,0xd6,0x17,0xe4,0x2e,0xdc,0x0f,0x6e,0xd6,0x15,0x12,0x87, + 0xe1,0x0a,0xcc,0x60,0xce,0x50,0xc1,0x85,0xc4,0xf3,0xd4,0x55,0x87,0xc8,0x98,0x5a, + 0xa6,0xd8,0x98,0xff,0x14,0x8c,0x41,0x25,0xe0,0xc6,0x88,0xc2,0xa8,0x50,0x81,0x83, + 0x9c,0x51,0x35,0x76,0xa5,0xe6,0x18,0x4c,0xdc,0x9f,0x2a,0xcf,0x06,0x0e,0x40,0x91, + 0x36,0x29,0x98,0xf3,0x0c,0x6c,0xa7,0x2e,0xcd,0xaa,0x88,0x85,0x30,0x0e,0x6e,0xcd, + 0x1a,0x14,0x87,0xf2,0x7a,0x83,0xc6,0xa0,0x2f,0xf1,0x3c,0x4c,0xfa,0x07,0x68,0xd1, + 0x7e,0x78,0x42,0xde,0x44,0x9e,0x81,0xdd,0x60,0xd7,0xe8,0x26,0x9c,0xbf,0x1b,0x88, + 0x46,0xdb,0xed,0x1f,0x40,0x8b,0x5e,0xa4,0xd1,0x20,0x89,0x26,0xc4,0x42,0x79,0x9a, + 0x04,0x2d,0xaf,0xe3,0x26,0x09,0x6a,0xcb,0xa5,0x27,0xe1,0x96,0x5a,0x3a,0xe8,0x9f, + 0xa3,0xfd,0x0e,0x44,0x6d,0xe6,0x31,0x72,0x3e,0xd4,0xa2,0xd9,0xb5,0xfa,0xa0,0xfd, + 0xf5,0xc4,0x7e,0x50,0x73,0x25,0xad,0x05,0x1c,0xda,0x8d,0x0a,0xe9,0x87,0x5b,0xb5, + 0x7c,0x8d,0xde,0x4b,0x72,0xe1,0x25,0x2d,0xdf,0x4b,0xbd,0xe4,0x7f,0x42,0xa3,0xe6, + 0xf0,0x52,0x85,0xf4,0x4d,0x9e,0xd8,0x0f,0x2b,0xad,0x42,0x47,0x44,0xb0,0x83,0x2d, + 0x54,0x33,0x0c,0x4b,0xa1,0x1b,0x9c,0x4c,0x56,0xf1,0xc5,0xbb,0x21,0x93,0x89,0xa3, + 0x24,0x22,0xb9,0xf1,0x8a,0x78,0x44,0x9c,0xd8,0x9f,0xed,0x69,0x43,0xec,0xa7,0x50, + 0xa9,0x2d,0x69,0xc8,0xd9,0x09,0xbb,0x3d,0x95,0x5e,0xdb,0x26,0xf9,0x19,0x18,0xd7, + 0xf8,0x40,0xfc,0x00,0xae,0xd6,0xfe,0x4e,0xb3,0x05,0xc5,0x33,0xe9,0x13,0xfb,0x21, + 0x6f,0xca,0xe7,0xec,0x28,0xae,0x86,0x6d,0x50,0xcc,0x85,0x71,0x5f,0xa9,0x66,0x1d, + 0x6c,0xda,0xe9,0x38,0x30,0x7b,0xde,0x3d,0xeb,0x8f,0x89,0x73,0xd8,0x61,0xcd,0x5d, + 0x6b,0xf5,0x8a,0xe9,0x89,0xf3,0x5b,0xae,0x9c,0x62,0x01,0xb0,0x83,0xcc,0xec,0x21, + 0x29,0x90,0x66,0x57,0xa8,0xbf,0x49,0x85,0x80,0xd6,0xd1,0xee,0x58,0x65,0x51,0x03, + 0x01,0x4f,0x99,0x40,0x99,0x65,0x5d,0x62,0x3d,0xeb,0x60,0x15,0xb4,0x08,0x21,0x4d, + 0x0e,0xa6,0x17,0xc2,0x86,0xfb,0x43,0xde,0x3c,0x85,0x34,0x4b,0x8d,0x3e,0x47,0x1d, + 0x55,0xb2,0xd3,0xd4,0x36,0x9f,0xaf,0xce,0xa1,0xcc,0xc8,0x4e,0xc8,0x9f,0x76,0xa9, + 0x33,0xab,0x45,0xb1,0x57,0x2f,0x0a,0xe2,0xfa,0x37,0xe2,0xfa,0x3b,0x82,0x96,0x4e, + 0xa1,0x85,0xd8,0x35,0x08,0x92,0x42,0xc8,0x50,0x0a,0xf9,0xfa,0xaf,0x4e,0xec,0x87, + 0x50,0xda,0x10,0x3d,0x50,0xe7,0xbe,0x47,0xde,0x64,0xff,0xba,0x77,0x1c,0xba,0xf1, + 0xfb,0xe6,0x74,0xfa,0x0f,0xe4,0xcf,0xf3,0x91,0x8d,0x62,0x21,0x39,0xa0,0xbb,0x35, + 0xa7,0x52,0xe3,0x48,0xc8,0xcf,0x88,0xd0,0x09,0xe3,0xac,0x92,0x2f,0xc2,0x90,0x3a, + 0x0e,0x95,0xcb,0xe5,0x60,0x8d,0x84,0xfb,0xa1,0xe2,0x07,0xd3,0xb2,0xc5,0x7e,0x8a, + 0x3f,0xd5,0xe3,0x4f,0x17,0x12,0xf2,0x87,0x42,0x08,0x22,0x3e,0xb7,0x62,0x6b,0x2e, + 0xb8,0x1f,0x4e,0x80,0x1b,0xd6,0xb2,0xa6,0x7c,0x88,0x68,0x6e,0xc8,0x6c,0x16,0x55, + 0x75,0x8c,0xcc,0x03,0x2b,0x13,0x2d,0xd2,0xc4,0xfe,0x77,0x4c,0xe9,0x82,0xd5,0x5a, + 0x47,0xb0,0x6d,0x88,0x5c,0xef,0x68,0x25,0x6a,0x23,0x1d,0xf1,0x38,0xa0,0x55,0x2a, + 0x62,0x96,0xae,0xec,0x72,0x78,0x19,0x05,0x51,0x20,0x5a,0xb3,0x30,0xb1,0x1f,0x1c, + 0xd2,0x83,0x10,0x64,0x8e,0x63,0xf2,0x3f,0x7b,0x96,0xc0,0xe3,0x50,0x18,0xbd,0x7e, + 0x0e,0x59,0x47,0x7f,0x05,0x85,0xba,0xa5,0x9c,0x58,0xaa,0x51,0x50,0xeb,0x54,0x25, + 0x0b,0x13,0xf2,0x87,0x29,0x7f,0xa2,0x4f,0x6b,0x33,0x75,0x79,0xd0,0x52,0x01,0x6b, + 0xa0,0xd0,0x9b,0xf1,0x08,0xd9,0xac,0x3e,0xe1,0x2e,0xd6,0x2d,0x0d,0xfe,0x3c,0x78, + 0x45,0x7c,0x20,0x42,0x7d,0x30,0x3c,0xb1,0x7d,0x20,0x10,0xf8,0x27,0x72,0x9c,0xdd, + 0x76,0xda,0xb6,0xb4,0xe6,0xbb,0xf0,0xde,0xf0,0x2f,0xa2,0xc5,0xe5,0xf2,0x3a,0xf2, + 0x7b,0xf6,0x5c,0x64,0x4d,0xb9,0x3c,0x0d,0xae,0xb2,0xaa,0x31,0x67,0x3d,0xfc,0x30, + 0x21,0x7f,0x68,0xda,0x33,0xf8,0xee,0x65,0xed,0x36,0xc5,0xb6,0x4d,0xba,0xa8,0xcd, + 0xd3,0xd7,0x85,0xc5,0x15,0xf0,0x31,0xb8,0xfb,0x32,0xc3,0xe2,0x08,0xdd,0x0b,0xee, + 0xc1,0x25,0x21,0xd1,0x33,0x69,0xe2,0x7d,0x41,0x7a,0x4e,0x3b,0xc8,0xaa,0x42,0xb6, + 0x88,0xfc,0x36,0xfd,0x4b,0x70,0x7e,0x74,0xc9,0xd8,0x8d,0x95,0xd2,0xd1,0xbe,0xaa, + 0xd3,0x4b,0x7a,0xc4,0x32,0xed,0xa7,0x6c,0xc7,0xa8,0xb5,0x3e,0x87,0xe3,0x8d,0xd8, + 0x5f,0x6b,0xde,0x2f,0x61,0x75,0xb8,0x58,0x97,0xbf,0x23,0xde,0xe7,0x59,0xe3,0xca, + 0x8f,0xc8,0x63,0xe2,0x66,0xeb,0x9a,0x50,0x81,0x9e,0xf1,0x28,0xe4,0xc2,0x0e,0x96, + 0xaf,0xd3,0x1f,0x0a,0x2f,0x24,0xd6,0x13,0xe0,0xe9,0x60,0xb3,0x5a,0xcc,0xe4,0x6f, + 0x92,0x7d,0xf0,0x9c,0x30,0x53,0xbf,0xf1,0x11,0xb2,0x18,0xd6,0xa8,0xf8,0xbe,0x6e, + 0xa2,0x08,0x2f,0xc1,0x74,0x9d,0x2e,0x4b,0xd7,0x12,0xf2,0x47,0x95,0xd6,0x4a,0x8d, + 0xe0,0xec,0x94,0x15,0xff,0x61,0xad,0x0d,0xd4,0x08,0x4a,0xef,0xc7,0xa0,0xa9,0x96, + 0x72,0x41,0x27,0xab,0x3b,0xa0,0xb0,0xdf,0xa1,0x5a,0x22,0xd2,0xc4,0xf9,0xed,0x9a, + 0x32,0x42,0x0e,0x36,0x57,0x8e,0xda,0x94,0x82,0xd5,0xf0,0x2f,0x30,0x6f,0xd0,0xb6, + 0x4f,0xbc,0x0b,0x8e,0xde,0xfe,0xf7,0xa8,0x8f,0x64,0x07,0xdb,0xc1,0xe6,0x72,0x41, + 0xfa,0xc3,0xc4,0x7e,0x63,0xc2,0x36,0xe5,0x82,0x77,0x9a,0xb6,0x7e,0x93,0xbc,0x02, + 0xc5,0x6c,0xa5,0x8e,0xf3,0x47,0xe8,0x45,0x69,0x86,0x6e,0x0b,0xa3,0xbc,0xba,0xd8, + 0x38,0x4f,0xb7,0x85,0xc4,0x50,0x42,0xfe,0xe4,0x2b,0x3b,0xe1,0x12,0xec,0x3d,0x6d, + 0x7b,0xb3,0xe0,0x27,0xea,0x21,0xd8,0x11,0x91,0x47,0xc5,0x9f,0x84,0xd6,0xd0,0xb9, + 0xbd,0xd6,0x73,0xe2,0x15,0xf8,0x29,0x94,0xf6,0x66,0x45,0x45,0xbd,0x76,0x62,0xfe, + 0x16,0x69,0xb9,0x12,0xd6,0xf1,0x7c,0x3d,0x45,0xfe,0x25,0x70,0x08,0xec,0xa7,0x6c, + 0xa8,0xb6,0x50,0x53,0xd8,0xf5,0xcc,0x1e,0x72,0x46,0xda,0x3d,0x50,0xa4,0xd3,0x10, + 0x89,0x2a,0x4a,0xe2,0x79,0x0a,0x61,0x4f,0xc0,0x1e,0xb8,0x31,0x7c,0x5d,0x09,0xf0, + 0x69,0x8b,0x36,0x93,0x6d,0xf0,0x22,0xa8,0x7a,0x46,0xd8,0x3e,0xc4,0x76,0x37,0x3a, + 0x7a,0x2d,0x21,0x35,0x9a,0xd8,0x6f,0x54,0x92,0xe8,0x1e,0xb5,0x5e,0xbb,0x31,0x4c, + 0xd6,0x92,0xc7,0x71,0xda,0x8d,0xc4,0xb2,0x16,0xb6,0x42,0x48,0xbf,0xd3,0x8d,0x12, + 0x69,0xaf,0xaf,0x5e,0xaf,0x53,0xb5,0x3e,0x21,0xb1,0xfc,0xd6,0xa9,0x52,0x8f,0x1d, + 0xe5,0x73,0x58,0x74,0xd2,0xf5,0x82,0xbb,0xd7,0xb6,0xb1,0xad,0x93,0xfc,0x19,0x35, + 0x94,0x14,0x46,0xc1,0x3b,0x5e,0x77,0x9b,0x9e,0x15,0x22,0x7a,0x42,0xfe,0x3c,0x7b, + 0xd3,0x25,0xed,0x92,0x32,0x17,0x6c,0xb3,0x73,0x2e,0xc1,0x5f,0xa0,0x4a,0xcf,0x0a, + 0x8a,0x3f,0x81,0x77,0xb4,0xf9,0xba,0xed,0xb8,0x38,0x8a,0x62,0xa4,0x0a,0x55,0xdb, + 0xd7,0xea,0x13,0xf2,0x47,0x9f,0x72,0x49,0xbf,0x42,0x4b,0x07,0x6c,0xdb,0xc5,0x4b, + 0x7e,0x04,0x42,0x51,0xdb,0x58,0xc1,0x15,0xb8,0xaa,0xe2,0xa0,0x4b,0xfc,0xae,0x77, + 0x40,0xd9,0xa5,0x5b,0xe7,0x7c,0xaf,0x21,0xb1,0x7f,0x58,0xde,0x27,0xf0,0x91,0x66, + 0x3f,0x2c,0x7f,0x41,0xae,0x68,0xad,0x60,0x8f,0xca,0x3d,0xe4,0x53,0x78,0x25,0x58, + 0x14,0x95,0x43,0x7e,0x27,0x8b,0xa8,0xf6,0x68,0x66,0x30,0x5b,0x4d,0xca,0xff,0xb4, + 0xc3,0x28,0x2b,0x55,0x5d,0x9e,0x6d,0x1f,0x00,0x3f,0x1f,0xb8,0xc8,0x00,0xec,0x40, + 0x7d,0x27,0xdb,0xc9,0x62,0xf6,0x94,0x5a,0xa2,0xd7,0xd9,0x09,0x49,0xdc,0x5f,0x4f, + 0xdb,0x46,0x5f,0xc0,0x65,0x6c,0x0b,0x93,0x11,0xf0,0x07,0x0c,0xb4,0x30,0x02,0x7b, + 0xa1,0x48,0x97,0x1d,0xab,0x8b,0xa1,0x9d,0xbd,0x10,0xba,0x93,0x59,0x5c,0x89,0xfd, + 0x00,0xb9,0xdb,0xe0,0x5c,0x5e,0x37,0xff,0xfa,0x23,0x88,0x4f,0xe2,0x83,0x8b,0x80, + 0xdb,0x60,0x9b,0xf8,0x5f,0x73,0x23,0xac,0xd2,0x65,0xdd,0xd9,0xa4,0x24,0xe4,0xcf, + 0x29,0xc4,0x7b,0x57,0x48,0xa5,0x7e,0xf3,0x68,0xc1,0x25,0xd4,0x6e,0x55,0xfa,0xfa, + 0x51,0xf1,0x92,0x72,0x95,0x2f,0x4b,0x54,0xbe,0xe0,0xfd,0x98,0xe2,0xd2,0x0d,0x89, + 0x63,0x09,0xf9,0xa3,0x23,0xfe,0xb9,0x40,0xf7,0xa0,0x12,0x97,0x9d,0x70,0x10,0xd5, + 0xba,0x71,0xff,0xcf,0xf8,0xc6,0xeb,0x14,0xdf,0x87,0xb7,0x01,0xe5,0xcf,0x46,0xd1, + 0x95,0x38,0x2f,0x07,0xd3,0x2a,0x60,0x0f,0x14,0xf4,0xd2,0x51,0x32,0x15,0xf8,0x8b, + 0x18,0xcf,0xff,0x0a,0x94,0xe8,0xf2,0x8b,0x64,0x0b,0x34,0xf9,0x10,0x41,0xfa,0x6b, + 0x1e,0x4e,0xec,0x87,0xd3,0x69,0x8b,0x71,0x7d,0xba,0x74,0x84,0x3d,0x56,0x5c,0x9f, + 0xd0,0xc4,0xfa,0x38,0x75,0x19,0x2c,0x5d,0x69,0x41,0xdd,0xd1,0x49,0xc3,0x9e,0xf2, + 0x84,0xfc,0xf1,0x09,0xd3,0x60,0x7f,0x28,0x7f,0x24,0x63,0x25,0xb1,0xea,0xcf,0xb2, + 0xfc,0x61,0x99,0xc3,0x80,0x5d,0xac,0x38,0x2a,0xd7,0x59,0xf6,0x6a,0xcd,0xac,0x20, + 0x4a,0x7f,0x68,0x5f,0x9a,0xc4,0x3f,0xd4,0xaa,0x9d,0x0b,0x95,0x0f,0x67,0xee,0x11, + 0xb3,0xf0,0xf9,0x5d,0x51,0x44,0x3b,0x03,0xf8,0xfc,0x78,0xff,0x2e,0x31,0xa0,0x0d, + 0x42,0x39,0xb3,0xde,0x20,0x27,0x8d,0x0a,0xc4,0x3f,0xea,0x79,0xa8,0xea,0x5f,0x77, + 0x4e,0xbc,0x3c,0x9b,0xaf,0xcf,0x24,0x5c,0x1f,0xed,0x2a,0xc5,0xf5,0x79,0x7f,0x51, + 0x8f,0x36,0x06,0x0b,0xd8,0x2c,0x5d,0x0c,0x26,0xf0,0x4f,0x57,0xda,0x25,0x8e,0x16, + 0xfa,0xad,0x2f,0xb7,0x39,0xd9,0x85,0x89,0xf5,0xb9,0xe8,0xc0,0xf5,0x61,0xa2,0x43, + 0x42,0x68,0xc4,0xf1,0x4f,0x51,0x42,0x7f,0x45,0x26,0x6f,0x46,0xb4,0x93,0x3f,0x4c, + 0x1f,0x21,0x53,0xd9,0xcb,0x30,0x53,0xcf,0x6a,0x40,0xd8,0xb3,0x0b,0xe5,0x89,0xac, + 0x89,0x2b,0xe1,0x8f,0xb0,0x85,0x65,0x46,0x89,0x3b,0xf1,0x7d,0x75,0x78,0x9a,0xed, + 0x62,0xd1,0x28,0x7d,0xd4,0x33,0x2d,0xc0,0x61,0x4f,0xf2,0x7d,0xeb,0x2d,0x37,0xc0, + 0xba,0x80,0x7a,0x9a,0x2e,0x45,0x9b,0x65,0x62,0xfd,0xeb,0x72,0x47,0x70,0x3d,0x7d, + 0x3a,0x0d,0x5f,0x67,0x85,0xed,0xb8,0xcd,0x2c,0x89,0xf5,0x74,0xf9,0xeb,0xb4,0x5f, + 0x1d,0x50,0x07,0x33,0xac,0xad,0xd9,0x26,0xfc,0x33,0x0c,0x2f,0xbb,0xba,0x99,0x35, + 0x64,0x71,0xc0,0x15,0x0d,0x0f,0x1a,0x87,0x3d,0x88,0x87,0x99,0x6d,0x48,0x9e,0x9f, + 0x7d,0x44,0x9f,0x1d,0xb2,0x7e,0x4a,0xe6,0x25,0xf1,0x0f,0xea,0x23,0x0e,0x72,0x66, + 0xb1,0x49,0x51,0x18,0xb3,0x54,0x42,0x96,0x31,0x10,0x38,0xec,0x91,0x4f,0xa9,0x63, + 0xda,0x7e,0x82,0x2f,0x6e,0xc6,0x3f,0x43,0x70,0x00,0x2a,0x38,0xc8,0x91,0xc8,0x01, + 0xae,0xe8,0x51,0xf1,0xc1,0x5b,0x88,0x10,0x6c,0xed,0x08,0x6c,0x3e,0xd4,0xbf,0xd0, + 0xac,0x93,0x45,0x92,0x78,0x9e,0x90,0xb4,0x1c,0x41,0x0e,0xc2,0x9e,0xa0,0xa5,0x90, + 0x72,0xfd,0x2b,0x07,0xc9,0x10,0xe2,0x1f,0x34,0x04,0x14,0x32,0x89,0x19,0x3f,0x6d, + 0x12,0x7d,0x26,0xfc,0x53,0x08,0x2d,0xf7,0x96,0xe0,0x7c,0x4f,0x21,0x3c,0x29,0xf0, + 0xf9,0xf6,0xce,0xd8,0xfc,0x0d,0x96,0x42,0xed,0x79,0xcd,0xae,0x3b,0x82,0xfe,0x74, + 0x93,0xfc,0x41,0x3c,0xc0,0x41,0x4e,0x2e,0x91,0xe0,0x7a,0x4d,0xd5,0x32,0x38,0x10, + 0xda,0x0e,0x4e,0x0d,0x11,0xd7,0x74,0xc4,0x3f,0x78,0xff,0x5c,0xe2,0x49,0xc8,0x9f, + 0x76,0xaa,0x42,0x04,0xdf,0xd7,0x0a,0x35,0x2a,0xea,0xdf,0xee,0x18,0xde,0x3b,0x01, + 0x25,0x60,0x03,0x51,0x45,0x45,0x57,0x26,0x2c,0x66,0x62,0x49,0x12,0xff,0xdc,0xf4, + 0xc1,0xa4,0xcb,0x5a,0x99,0xf7,0x39,0x8e,0x76,0x3e,0xe0,0xaf,0x19,0x2c,0x18,0xe2, + 0xf8,0x87,0x23,0x9c,0xf3,0x70,0x59,0xab,0xf2,0xce,0x3a,0x3e,0x29,0x89,0x7f,0x38, + 0x5e,0xfa,0xdc,0xe1,0x5e,0x6c,0x0d,0xe6,0xcc,0xa1,0x17,0xb5,0xf8,0xfa,0x8c,0xd3, + 0x9f,0x69,0xb6,0x37,0x27,0xcd,0x81,0x4f,0x1c,0xbb,0xea,0xac,0xc7,0x9e,0x98,0x91, + 0x38,0xbf,0x79,0x4a,0x34,0x14,0x29,0xec,0xb0,0x52,0xa9,0xed,0x7e,0x3c,0x68,0x1d, + 0x08,0x84,0x50,0x1a,0xf7,0xe0,0x13,0xca,0x4c,0xf0,0x85,0x02,0xaa,0x5b,0xb2,0x3e, + 0x4b,0xb2,0xd2,0x13,0x56,0x6c,0x5a,0x7f,0x64,0x8b,0x23,0x5a,0x67,0xc9,0x29,0x4a, + 0x83,0xdd,0xaa,0xaa,0x59,0x12,0xef,0x8b,0x78,0x86,0x3d,0xef,0x98,0xa1,0x51,0xc5, + 0x4f,0x84,0x89,0xe7,0xcf,0x9b,0xd2,0x09,0x6d,0x94,0xaf,0x3f,0x59,0x6e,0xe0,0xcf, + 0xf8,0xfa,0x17,0xf1,0xc1,0x72,0x68,0x53,0xed,0xb5,0x75,0x41,0xcf,0x1d,0x09,0xf9, + 0xd0,0xa1,0x74,0x0a,0x1f,0x22,0x88,0x75,0x06,0x51,0x11,0x6c,0xd7,0x89,0x96,0x65, + 0x3c,0x3f,0xae,0xbf,0xed,0x29,0x5c,0xe1,0xe7,0xa1,0xcc,0xe3,0xfc,0x75,0x86,0x23, + 0x21,0x1f,0x02,0xd0,0x09,0xa7,0xd8,0x3e,0xc4,0xc3,0x22,0x02,0x21,0xb5,0x32,0xfe, + 0xbe,0x7c,0xa1,0x36,0x35,0xfd,0x19,0xc6,0x03,0xf3,0xee,0xcf,0x0a,0x36,0xbd,0x90, + 0xd8,0xcf,0x45,0x4a,0x88,0x8e,0xe9,0x6e,0xbe,0xcd,0x70,0xe3,0x69,0xf1,0xf5,0xe7, + 0x3b,0xf0,0xee,0x66,0xd1,0xd7,0x3c,0x0c,0x6e,0xc5,0xca,0x72,0x0e,0x26,0xf1,0x4f, + 0xad,0x03,0x3e,0x0d,0xd8,0x59,0x5d,0x48,0xac,0xc7,0xf5,0xb1,0x33,0x39,0x44,0x86, + 0x71,0xf0,0x33,0x26,0xaf,0xf0,0xf4,0xc0,0xea,0x5a,0x95,0x59,0x86,0xc4,0x83,0x89, + 0xf3,0xee,0x48,0x5b,0x21,0xec,0xe0,0x68,0x07,0xf5,0x91,0x62,0x88,0x65,0xe3,0xbc, + 0x88,0x4e,0x7e,0x70,0xee,0xd2,0xb6,0xb2,0x68,0x3f,0xdd,0x77,0xcf,0xc1,0x84,0xfc, + 0xc9,0x17,0xa6,0x0a,0x2f,0x93,0xe9,0x11,0x34,0x52,0x36,0xe3,0xb1,0x45,0x3c,0x60, + 0x9c,0x5f,0x3c,0xc8,0x72,0x83,0x7f,0x13,0xac,0xd1,0x0a,0xb4,0xa7,0x1a,0xfc,0x91, + 0x24,0xbe,0xa2,0x37,0x07,0xbe,0x64,0xbb,0x3e,0xcc,0xfa,0x19,0x9a,0x2d,0x57,0xdf, + 0xbc,0x2d,0xba,0x7e,0xa5,0xf8,0x2e,0x7c,0x89,0xe7,0x37,0x6b,0x4c,0x7c,0x94,0xfc, + 0x85,0xcd,0x8e,0x3a,0xeb,0xc5,0x83,0x49,0xfc,0x73,0xe7,0x6f,0xe1,0x23,0x98,0xd7, + 0x6f,0xeb,0x7e,0x15,0xf5,0xbb,0x56,0x66,0xc8,0x13,0x6a,0x28,0xfa,0xb0,0x38,0x44, + 0x2e,0xe0,0x51,0xc2,0x13,0xea,0x4f,0xc8,0x1f,0x6d,0xca,0x15,0xf8,0x04,0xd5,0x96, + 0x75,0x4c,0xac,0x60,0x57,0x71,0x90,0x39,0x86,0x6a,0xfd,0xa2,0xa1,0xc8,0xc4,0xfd, + 0x70,0xb4,0x71,0x76,0xd4,0xda,0x83,0x5f,0x77,0x62,0xff,0x74,0xa1,0xfc,0x61,0x79, + 0xaa,0xee,0x68,0x58,0x68,0xc5,0xc7,0x56,0x87,0x65,0x7c,0x7e,0xba,0x8b,0xdd,0xaa, + 0xcb,0xfa,0xe4,0x47,0x1a,0xdf,0xa3,0xb7,0xd6,0x65,0xd6,0xdf,0xf2,0x42,0xe2,0xfb, + 0x06,0x61,0x33,0x3c,0x07,0xf9,0xfd,0x28,0x9f,0xa7,0x6a,0xbb,0x00,0xf1,0x52,0xec, + 0x7d,0xf3,0xf1,0x7d,0xc9,0x26,0xba,0x09,0xf1,0xcf,0xf5,0x2e,0x7b,0x33,0x9b,0x58, + 0x7f,0x9f,0x34,0x00,0xad,0xb5,0x45,0x31,0x79,0xbe,0x23,0x98,0xd0,0x77,0x85,0xfa, + 0xa2,0x19,0x44,0xa5,0x7e,0xad,0xd0,0x77,0x7d,0x21,0x69,0x4f,0x9c,0x77,0x47,0xda, + 0x3e,0xf8,0xa8,0xbf,0x54,0xcf,0x1c,0x45,0xeb,0x78,0x2e,0x74,0x4c,0xe8,0x2f,0x2e, + 0x48,0x49,0x17,0xd9,0xe8,0x9d,0x73,0x36,0xb3,0x67,0x92,0x45,0x4a,0x3e,0xcf,0x08, + 0x5c,0xc0,0x65,0xc9,0x0a,0xe7,0x8c,0xc4,0xf0,0x4f,0x58,0x48,0xae,0x8f,0x84,0x83, + 0xd7,0x8f,0x36,0xe1,0x56,0x9c,0xb8,0xff,0x06,0xb6,0x82,0x5e,0xa4,0xdd,0x68,0x54, + 0x7a,0x2a,0x50,0x0d,0xa1,0x61,0x8b,0xf2,0x1c,0xff,0xe1,0xcd,0xba,0xed,0xbc,0x5c, + 0x9e,0xf6,0x29,0xda,0xb3,0x74,0x54,0x8c,0xd6,0x4e,0xc8,0x93,0xde,0xdc,0x15,0x7c, + 0xdb,0xe8,0x8e,0x30,0xc2,0x98,0xbd,0x90,0xd0,0xbf,0x0f,0xea,0x72,0x8f,0xfd,0x39, + 0xb5,0x95,0xbd,0xa0,0x77,0xb1,0x82,0x21,0x2d,0x81,0x7f,0xd2,0x9c,0xfc,0x98,0xf4, + 0xde,0x70,0xcd,0x7c,0xd4,0x77,0x0a,0xf9,0x07,0x61,0x6f,0xe3,0x0b,0xda,0x0d,0xdb, + 0x57,0x47,0x13,0xfb,0x87,0x4a,0x56,0x08,0x23,0x0c,0xb0,0x70,0x58,0xb8,0x17,0x42, + 0x6f,0xc5,0xd6,0x07,0x61,0xb6,0x2c,0x10,0x26,0xb5,0xe0,0x41,0xb3,0xa8,0xa4,0x2f, + 0x6d,0x62,0x3f,0xb0,0x0c,0xbe,0x0d,0xdc,0xfa,0xdd,0x67,0x0b,0x7e,0x43,0xbf,0x04, + 0xf7,0xdb,0x71,0xfd,0x82,0xf7,0x0f,0x8a,0xcb,0xa5,0x31,0x98,0xa7,0x65,0x3d,0xd1, + 0x94,0xb4,0x07,0x43,0x99,0xa8,0xd6,0x9d,0xaf,0xf4,0xdd,0x85,0xaf,0xc9,0xae,0x42, + 0x65,0xc4,0x78,0x5f,0x43,0xbf,0xa3,0x2a,0x23,0x97,0xa0,0xaa,0xfa,0xae,0x3e,0xb1, + 0x2b,0x2d,0x89,0x37,0x46,0xd8,0x21,0x1f,0x82,0xcc,0x73,0xe2,0xc9,0x8e,0xa3,0xf6, + 0xf9,0xf8,0x21,0xc4,0x8a,0xd0,0x51,0x75,0x7e,0x24,0xb3,0xbb,0x60,0x5f,0x33,0x02, + 0x21,0x7d,0xed,0x69,0x03,0x38,0xc5,0xe7,0x2b,0xa7,0xb4,0xd6,0x06,0xfb,0x1c,0xba, + 0x2f,0x67,0x16,0xb4,0x29,0x68,0x7f,0xfd,0xda,0xf3,0x75,0xe8,0xca,0xb5,0x0f,0xd2, + 0xed,0x24,0xa4,0x7d,0x18,0xb4,0x9f,0xb5,0x6c,0x23,0xa3,0x89,0xf5,0x8f,0xa4,0x0d, + 0x90,0x46,0xfc,0xfa,0x01,0x89,0x04,0x50,0x5a,0x39,0x06,0xf1,0x7d,0xad,0x92,0x48, + 0x0a,0x07,0xa9,0xb1,0x43,0x88,0xaa,0xd4,0x4d,0x4e,0x37,0xf9,0x7f,0x26,0x77,0x49, + 0x68,0xdf,0x11,0xca,0xfa,0xba,0xd4,0x17,0xa8,0x9d,0x58,0x82,0x7e,0x14,0xe3,0x60, + 0xef,0xa3,0xe1,0xec,0x90,0xf0,0x3c,0xb5,0x03,0x09,0x92,0xa4,0xff,0xa7,0x76,0xca, + 0x27,0x70,0x08,0x5e,0x1e,0x74,0xce,0x11,0x7f,0x23,0xbd,0xef,0x41,0xfc,0xbc,0x53, + 0x2e,0x92,0x0e,0xc1,0x05,0x65,0xed,0xf6,0xad,0xbf,0x65,0x17,0xab,0xdd,0xbd,0xd6, + 0xd0,0xa4,0xc1,0x84,0xfc,0x0c,0x09,0x61,0xbe,0x6d,0xd8,0x92,0xb0,0xf8,0x5d,0xff, + 0x3b,0xa1,0x4a,0x76,0x57,0x58,0xec,0x53,0x2e,0xc0,0x65,0x98,0x15,0x2e,0x38,0x5d, + 0xfb,0xb1,0x54,0xd1,0x67,0x0b,0xe1,0xd6,0x9a,0xb8,0xff,0xa0,0xf2,0x18,0xbc,0x2f, + 0x95,0x9d,0xb0,0x76,0x4e,0x9a,0x89,0xf8,0xca,0x35,0x68,0x9d,0x23,0x3e,0x48,0x0e, + 0x41,0x59,0x30,0xd3,0xd5,0xe4,0x94,0x3e,0xbe,0xdf,0xad,0xaf,0x0d,0x17,0x84,0x13, + 0xf2,0x27,0x92,0xe6,0x60,0x6d,0x01,0x35,0x80,0x20,0xd9,0x01,0x6f,0x7b,0xed,0x3d, + 0x81,0x30,0x9a,0x8d,0x2f,0x7e,0xd3,0xce,0x68,0x98,0xe4,0x4b,0x4d,0xba,0xbd,0x97, + 0x76,0x93,0xb2,0x84,0x7c,0x88,0x22,0xfe,0xd9,0xaa,0xaa,0x83,0x68,0x6d,0x49,0x6a, + 0x23,0x38,0x22,0xf8,0xf5,0x17,0xc3,0x8b,0x4c,0xd5,0x5b,0x80,0x64,0x0d,0x76,0xf7, + 0xab,0x9f,0x5b,0x54,0xbf,0xc9,0xff,0x23,0xa4,0x6b,0xab,0x9f,0xb9,0xbf,0x3e,0xb0, + 0x92,0x7c,0x1b,0x7e,0xc1,0xf2,0x7d,0x96,0x85,0xf6,0x69,0xd0,0xd9,0xae,0x46,0x69, + 0x9d,0x65,0x1a,0xec,0x6c,0x37,0x1c,0x41,0x3f,0x31,0xe1,0x9f,0xac,0xe0,0xa9,0x50, + 0x58,0x2f,0xc9,0x6b,0xb3,0xb2,0x5e,0xe8,0xd1,0x4b,0x1c,0xe2,0x62,0x78,0x35,0xbc, + 0x53,0xcf,0xcc,0x93,0xad,0xec,0xb3,0x70,0x18,0x4a,0xf2,0x84,0x63,0x13,0xdb,0x0d, + 0xb4,0xcc,0x7d,0xb9,0x97,0x94,0xf9,0x75,0xb6,0x37,0x6b,0xf6,0xc1,0x65,0xa5,0xaa, + 0x36,0x53,0xc7,0xfd,0xf3,0x27,0xf8,0x79,0xbf,0xed,0x4d,0x1c,0x1c,0x86,0x2a,0x29, + 0xf3,0x44,0x0a,0xfe,0x19,0x81,0x8f,0x05,0xbe,0x08,0x39,0x85,0xca,0x21,0xee,0xf6, + 0x09,0x17,0xfc,0x10,0xbf,0x88,0x5b,0xcb,0x0c,0x89,0x88,0x18,0x99,0x5b,0xc7,0xc1, + 0x47,0x26,0xfc,0x83,0x42,0x12,0xb8,0xdb,0x87,0x4a,0xd0,0x44,0x0c,0xff,0x4f,0x00, + 0x9e,0x05,0x87,0x96,0xe9,0x43,0xc4,0xe8,0x17,0x0c,0x47,0xd0,0xb9,0xc4,0xfa,0x33, + 0xf8,0x2d,0x3c,0xc7,0x1a,0xb9,0xb7,0x67,0x1a,0x3c,0xc1,0xa6,0xc7,0x06,0x5b,0x63, + 0xfe,0x9f,0xbb,0x61,0x0d,0x0a,0x52,0x84,0x82,0x51,0x13,0xfe,0x19,0x80,0xb6,0xa0, + 0x3a,0x44,0x6f,0xf3,0x58,0xe1,0x57,0xc1,0xc2,0x21,0x5a,0x4e,0x1e,0x53,0xb7,0x06, + 0x1d,0x7d,0x19,0xbb,0x71,0x61,0x9b,0x82,0xce,0x4b,0x79,0xa9,0xfe,0x9f,0x2e,0xc4, + 0xf3,0x6e,0xb6,0x4d,0x95,0x29,0x79,0x1b,0x5e,0x66,0x8e,0xdf,0x8a,0x33,0x51,0x02, + 0xbb,0xc3,0xce,0x90,0x5c,0x4f,0x0e,0xc2,0x83,0xc1,0xcc,0x17,0x44,0x93,0xff,0x07, + 0x7c,0xca,0xd8,0xc2,0x0a,0xb4,0xc7,0x6b,0x4e,0x29,0xc3,0x88,0x7e,0x6d,0xac,0x29, + 0x04,0xa8,0x7f,0xa5,0x2c,0x26,0x32,0x18,0xab,0xa6,0xca,0xcd,0xfd,0x29,0xf8,0xa7, + 0x1f,0x0e,0xe8,0x95,0xbe,0xcc,0x76,0xf1,0x59,0x18,0xd7,0xc3,0xdc,0xff,0xb3,0x1c, + 0xc6,0x37,0xba,0xb4,0xcc,0x20,0xe2,0x9f,0x03,0x50,0xf9,0x90,0x75,0x43,0x8a,0xff, + 0xe7,0xfb,0xd0,0x02,0x1d,0xb5,0x74,0x13,0x99,0xd1,0xd7,0xa2,0x77,0x78,0x2d,0xdc, + 0xed,0xb0,0x9b,0x75,0x78,0x69,0xd0,0x5e,0x28,0xb5,0x68,0x25,0xdf,0xc4,0x9f,0x92, + 0xe7,0x3d,0x2f,0x6d,0x01,0x3c,0x06,0x05,0x1e,0xf9,0x4d,0xb2,0x13,0x7e,0xa7,0x15, + 0x78,0xe9,0x20,0xd9,0x29,0x3d,0x23,0x18,0x83,0x39,0xf0,0x98,0xef,0x1f,0x35,0x7a, + 0x9c,0xbc,0x6e,0xc2,0x3f,0xb9,0x9e,0x55,0xb5,0xf9,0x5a,0x5d,0x03,0xc9,0x85,0x34, + 0x2d,0xdf,0x4b,0xbc,0xe9,0x31,0xff,0x8f,0xe3,0x5e,0x32,0x05,0x56,0xc1,0x03,0x3a, + 0xf5,0x92,0xa4,0xfd,0x55,0x9e,0x79,0x3f,0x87,0xfd,0x5c,0xed,0x86,0x60,0x25,0x0e, + 0xac,0x4c,0xe6,0xfa,0xd7,0x0d,0x77,0x81,0xac,0x12,0x0e,0x8d,0x9c,0x7a,0xc1,0x11, + 0xc1,0x84,0x7f,0xd8,0x59,0xed,0x65,0xee,0xed,0xf9,0x3e,0xc2,0x9e,0xfd,0xde,0xf5, + 0x1c,0x08,0x4d,0xf8,0x7f,0x68,0x7c,0x60,0xf2,0xff,0xa4,0x7d,0x1e,0x3a,0x5c,0x58, + 0x5a,0x67,0x1d,0x6c,0x3a,0x2f,0x1d,0x56,0x4a,0xb5,0xcc,0x8d,0xe2,0x79,0x76,0x58, + 0xa9,0xf4,0x5a,0x7f,0x29,0x4e,0x67,0x87,0x0d,0xc4,0xe8,0x37,0xfb,0x7f,0x7a,0x37, + 0x06,0x1c,0x76,0xa0,0xcd,0xe2,0x16,0x4d,0xf5,0x86,0xf2,0x1c,0xcc,0x73,0x0a,0x02, + 0xdf,0x2c,0x9a,0x5a,0xb4,0x9a,0xcc,0x6e,0x0e,0x40,0x99,0x22,0xf7,0x5b,0xb2,0x12, + 0xf6,0x75,0x5d,0x5a,0x3f,0x82,0x3a,0xd5,0x1b,0xe0,0xb0,0xa7,0x51,0x55,0xef,0x41, + 0x74,0xd7,0xaf,0x35,0xaa,0xd3,0xb5,0x3a,0x7c,0x5f,0x65,0xcb,0xed,0x33,0xbd,0x8b, + 0xbc,0x64,0x63,0x42,0xfe,0x20,0xfe,0x61,0x2d,0x6a,0x87,0x86,0xa7,0xb5,0x93,0x6e, + 0x05,0x1f,0x07,0x42,0x43,0xf8,0x45,0x66,0x72,0x47,0xd9,0x1c,0x61,0x26,0xcc,0xf2, + 0xdc,0x38,0x68,0xf6,0xff,0x4c,0x19,0x22,0x07,0x98,0x4b,0x73,0x3e,0x7d,0xcf,0x99, + 0xe0,0x01,0x35,0xe6,0xd6,0x6b,0x3a,0xa0,0x96,0xf9,0x16,0x07,0xe5,0x42,0xf2,0xa1, + 0x7d,0x5e,0x83,0xed,0x09,0xb1,0x2b,0x21,0x7f,0x86,0x85,0x4e,0x38,0x4b,0x11,0xed, + 0x3c,0x55,0x30,0xd4,0x81,0xb0,0xc7,0x63,0xe0,0x9f,0x1f,0x43,0x65,0xdd,0xcd,0x7c, + 0xf0,0x26,0x94,0xd5,0xda,0x94,0xa6,0x47,0x13,0xfb,0xdf,0xa1,0x84,0x10,0x7f,0xce, + 0x83,0xc7,0x56,0x15,0x44,0x35,0xee,0x76,0xcb,0xe2,0x8e,0xe8,0xc8,0x20,0x7e,0x88, + 0x66,0x51,0x31,0x1c,0x41,0xb6,0x55,0x05,0x26,0xfc,0x93,0x56,0x0e,0xeb,0xd4,0x02, + 0x46,0x87,0x71,0x37,0xaf,0xd3,0x70,0x10,0x22,0x11,0xb5,0xb5,0xba,0x8c,0x39,0x42, + 0x76,0x07,0x94,0xac,0xb5,0x37,0x23,0x22,0x3a,0x98,0xc4,0x27,0x69,0xcb,0x09,0xae, + 0x4f,0x6d,0x86,0x4a,0x5e,0x83,0x1d,0x2d,0x85,0x67,0xf1,0x3c,0xbe,0x0e,0x2d,0x04, + 0x0c,0xc7,0x69,0x7e,0xf7,0x16,0x90,0x64,0x0a,0x49,0xfc,0x13,0x12,0xa6,0x52,0x3c, + 0xbf,0x1a,0x1e,0xd2,0x41,0xb2,0x46,0x9b,0x3e,0x88,0x40,0xe8,0xb8,0xb4,0x1a,0x70, + 0xb0,0xdc,0x7e,0x13,0xbc,0x14,0x03,0x06,0xc3,0x89,0xfb,0x77,0xd1,0x6c,0x78,0xad, + 0x79,0x76,0x34,0x73,0x25,0x39,0x06,0x9f,0xb3,0x97,0xa2,0xce,0x95,0xe2,0xeb,0xe4, + 0x55,0xb6,0x23,0xe4,0x1c,0x93,0x2b,0xc9,0x67,0x6c,0x7b,0xd4,0xb6,0x52,0xfc,0x28, + 0x89,0x7f,0x6e,0xea,0x52,0x3e,0x4b,0xff,0xad,0xbe,0x3e,0x2c,0xea,0xca,0x38,0xcc, + 0xe3,0x86,0xff,0x10,0x5c,0x10,0x2b,0xb9,0x61,0x32,0x82,0x82,0x65,0x1a,0xbf,0xd2, + 0x97,0x90,0x3f,0x90,0xf6,0x05,0x9c,0x64,0x93,0x7c,0x4b,0x3e,0x14,0xbb,0xe1,0xa4, + 0x3e,0xdf,0x97,0xc5,0xf1,0xcf,0x97,0xac,0x6a,0x85,0xf5,0x84,0xe8,0x66,0xff,0x23, + 0x58,0x35,0x64,0x1b,0x17,0xf5,0xc4,0xfa,0x77,0x09,0x53,0x61,0x35,0xdc,0xba,0x54, + 0xce,0x27,0x5e,0xed,0xb8,0x82,0xeb,0xe3,0x22,0xc7,0xb5,0x1d,0xca,0xad,0xb5,0x54, + 0x23,0x8a,0xb4,0x7d,0x7b,0x31,0x57,0xc4,0x1f,0x25,0xed,0x6b,0x25,0x08,0xbf,0x54, + 0xa6,0xe3,0x4b,0x79,0x06,0x51,0x71,0xcf,0xd4,0x66,0xc6,0xf1,0x0f,0xcd,0x98,0x4c, + 0xb2,0x57,0xed,0xca,0x2f,0xd6,0xe4,0x86,0x74,0x3d,0xe9,0xff,0xc9,0x8d,0xd4,0xb5, + 0xfa,0x0a,0xcf,0xa1,0xf6,0xd7,0x70,0xbe,0xbd,0x19,0x81,0x50,0x3f,0xec,0x28,0x9c, + 0x01,0x19,0x40,0x54,0x6d,0x87,0x84,0x8a,0xbe,0x1c,0x8f,0xcd,0xc4,0x79,0xdf,0x36, + 0x65,0x1b,0xbc,0xa5,0x95,0x55,0xe3,0xf9,0xea,0x44,0xb3,0x6b,0x9e,0x9e,0xd9,0x23, + 0x9e,0x81,0xcf,0xa2,0x38,0x08,0x5b,0x9c,0x08,0xe4,0x0c,0x0f,0xcf,0x47,0x26,0x79, + 0x38,0xe2,0xb8,0x58,0x5d,0x59,0x6b,0x6b,0x16,0x99,0xf2,0x8e,0x56,0xd5,0x77,0xf7, + 0x76,0x71,0x48,0xbb,0x00,0x7b,0xf4,0xac,0xd0,0xa4,0x11,0xc7,0xb8,0x82,0x5b,0x6b, + 0x07,0x22,0xe4,0x89,0xfb,0x0b,0xca,0x88,0x78,0x18,0x61,0xcf,0xfa,0x80,0xd8,0x23, + 0xbc,0x11,0x42,0x45,0x3f,0x8a,0x66,0xc8,0xcf,0xd5,0xb9,0xfd,0x38,0xb8,0x24,0xad, + 0x27,0x55,0x11,0xab,0x5e,0xa3,0x6b,0x49,0xf9,0xf3,0xa0,0xb7,0xd5,0x83,0x9b,0x64, + 0x2d,0x2e,0xc2,0x8b,0x9a,0x9d,0xad,0x0d,0xe3,0xfe,0xdf,0xc3,0xec,0xc7,0x96,0x84, + 0xec,0x23,0xd2,0x3b,0xcd,0xf3,0x74,0x54,0xf4,0x49,0xf9,0xc3,0xd2,0xac,0x6a,0x40, + 0x2b,0xea,0x95,0xfd,0xe9,0x51,0x16,0x80,0x19,0x1a,0x02,0xa1,0x21,0x8d,0xe3,0x1f, + 0x1a,0xcc,0x8e,0x4a,0xcf,0xeb,0xce,0x20,0xdd,0x49,0xa2,0xd2,0xc4,0x7e,0x40,0xfc, + 0x43,0xfc,0x92,0x43,0xc3,0x45,0xd6,0x71,0x6b,0xab,0x6c,0xe1,0xec,0xf4,0x7e,0x69, + 0x87,0xf2,0x43,0xdd,0x22,0x65,0xeb,0xc2,0x76,0x5f,0x91,0xee,0x98,0x63,0x92,0x3f, + 0x90,0xf6,0x80,0xa7,0xf5,0x9b,0xf3,0x74,0x43,0xfe,0x58,0x85,0x32,0xad,0x28,0xec, + 0x19,0x42,0x0d,0x5e,0x81,0xf7,0x2f,0x88,0x4a,0x1f,0xd6,0x57,0xea,0xd6,0x9d,0xa2, + 0x2e,0x4e,0x4c,0x0f,0x4d,0xb9,0x04,0x5f,0xe4,0xef,0x12,0x6c,0x7d,0xe2,0x20,0x20, + 0xda,0x69,0x44,0x60,0x73,0x1e,0xae,0xaa,0xbb,0x74,0x5b,0xdf,0xa4,0x51,0xf8,0x93, + 0x3a,0x1f,0xd6,0xeb,0xe2,0xf0,0xa4,0x04,0xde,0x48,0xbb,0x02,0xaf,0xb3,0xb9,0xfd, + 0x8b,0x1b,0x6a,0x7e,0x4a,0x8e,0x82,0x9b,0xc3,0x66,0xc4,0x4b,0x52,0x15,0x1f,0x8c, + 0xfe,0x62,0xc4,0x55,0x9a,0x6e,0xed,0x15,0x5d,0x09,0xf9,0xc3,0x94,0x4f,0xa1,0x15, + 0x61,0x1e,0x0d,0x7b,0x16,0x68,0xeb,0xa1,0xa3,0x4f,0xee,0x21,0x57,0xb5,0x57,0x06, + 0x4b,0xa2,0x88,0x0f,0xcf,0x68,0xbb,0x5d,0x88,0x88,0xd6,0x10,0x35,0x21,0xcf,0x69, + 0xda,0x30,0xc2,0x1e,0x3b,0xc7,0x7b,0x6b,0x59,0x13,0xea,0x77,0x8e,0xf7,0xd0,0xd0, + 0x58,0x61,0x00,0x63,0xbe,0x02,0xa8,0x31,0x3c,0xfe,0x24,0xfe,0x99,0xd2,0x15,0x7a, + 0xa1,0xc5,0xee,0xb3,0xb4,0x23,0x3e,0x6f,0x83,0x22,0x5d,0x4c,0xe0,0xc9,0x30,0xf9, + 0x14,0xf6,0xf4,0x77,0x6c,0xa7,0x9b,0x49,0x38,0xb1,0x3f,0xb5,0x29,0x9f,0x4a,0x1f, + 0x37,0x97,0x8d,0x96,0x94,0xd7,0xac,0x80,0x43,0x64,0xde,0x04,0x7e,0x36,0xf0,0xf0, + 0xa7,0xc2,0x30,0x73,0xab,0xd6,0x80,0x1c,0x4c,0xec,0xff,0xa8,0xb0,0x8f,0xbc,0x47, + 0x5e,0x41,0x98,0x67,0xc1,0xd5,0x81,0xb9,0xdc,0xbf,0x31,0x42,0x0d,0x7c,0xc8,0xf7, + 0xc3,0x38,0xad,0xf4,0xcc,0x6a,0x10,0x57,0x9a,0xfc,0x3f,0x5d,0xea,0xc7,0x93,0xcb, + 0x06,0xb3,0x7a,0x26,0x39,0xe1,0x7d,0xe8,0x46,0xe0,0x6d,0x1c,0xc3,0xb8,0xa3,0xe3, + 0xad,0xbf,0x75,0x7b,0xad,0xcd,0x35,0xa3,0x26,0xfc,0x63,0x61,0x6d,0x83,0xa8,0xd6, + 0x7f,0x43,0x2a,0x60,0x7d,0x0c,0x0f,0x5f,0x82,0xf7,0xa0,0x0c,0x07,0xf6,0x11,0x34, + 0xbd,0xed,0xf7,0xd0,0x5f,0xa3,0x7e,0x9f,0xd8,0x0f,0xd1,0xb4,0x3b,0xe1,0x05,0x44, + 0x3b,0x84,0xa3,0xc1,0xad,0x13,0xfe,0xb1,0x26,0x44,0x8c,0x38,0x88,0x40,0x6b,0x23, + 0x02,0x27,0x35,0xbd,0xc7,0xe4,0xff,0xb9,0x01,0x56,0x1b,0x61,0x20,0x4b,0x56,0x5d, + 0x53,0x63,0xdc,0x1f,0xf2,0x78,0xf3,0xf7,0xf9,0xe0,0xca,0x3d,0xc6,0x4f,0xdf,0xd9, + 0x78,0x42,0x99,0xb8,0x7f,0x1d,0xa5,0x10,0x55,0xdd,0x11,0x8b,0x1b,0xef,0xff,0xbe, + 0xe0,0xfa,0x24,0x8b,0xfb,0x7f,0x5e,0x65,0xb9,0xba,0x6d,0xb6,0x38,0x40,0xf8,0x99, + 0x76,0x5a,0xc4,0x8d,0xa6,0xf8,0x57,0x3b,0x1e,0xc3,0xbd,0x6c,0xc9,0xe8,0xa4,0x4b, + 0xea,0x55,0xad,0xd2,0x58,0x16,0x5f,0x6c,0x7d,0x6a,0x4e,0x2a,0x57,0xe0,0x15,0x86, + 0x40,0x68,0xd0,0x84,0x7f,0x86,0xe1,0x6d,0x5c,0x8d,0xc5,0x61,0xd1,0xc9,0x0e,0x55, + 0x77,0xf7,0xde,0x1c,0x16,0x3f,0x51,0xdf,0x71,0xf1,0x78,0x22,0xae,0xcf,0x9f,0xfc, + 0xa5,0xd5,0xb6,0x68,0x8a,0xff,0xa7,0x1d,0xd6,0x91,0xad,0x3c,0xc8,0x55,0x61,0x5f, + 0xaf,0x1a,0xd2,0xf2,0x24,0xdb,0xe5,0x28,0xd6,0x17,0x71,0xc1,0xf2,0x98,0x90,0xaf, + 0xb5,0x8d,0x16,0x99,0xfd,0x3f,0xdd,0xf0,0x4b,0xee,0xf6,0x29,0xf7,0x3c,0xcd,0x9e, + 0x0b,0x26,0xfd,0x3f,0xa7,0x70,0x70,0x04,0x11,0xe0,0xfd,0x3e,0xb9,0x8e,0x34,0x98, + 0xf0,0x4f,0x44,0xf3,0x07,0xd4,0x51,0x4b,0x97,0x79,0x3d,0x63,0xfe,0x1f,0xfb,0x80, + 0xd6,0xa8,0x75,0x34,0xc8,0xbf,0xb0,0x98,0xfd,0x3f,0x7b,0xe0,0x5d,0xa9,0x74,0xe7, + 0xac,0x11,0xb9,0x0b,0x5e,0x80,0xb8,0xff,0xe7,0x6d,0x30,0xe4,0xed,0xdb,0xf0,0x2e, + 0x2d,0xed,0xb0,0x0d,0x8b,0x8f,0x9a,0xf0,0x0f,0x6a,0x7f,0x65,0xbf,0x94,0xb9,0xca, + 0x70,0x83,0x70,0xb7,0x0f,0x9e,0xee,0x98,0xff,0x47,0x3c,0x2d,0x8d,0xd1,0xca,0x6c, + 0xdb,0xea,0x14,0xfc,0x73,0x86,0x1d,0xc8,0xee,0xae,0xce,0x0a,0x6e,0x95,0xc8,0x87, + 0xd0,0x6d,0xd8,0xfb,0x92,0x61,0xef,0x73,0x7d,0x77,0x40,0xad,0xd4,0x9c,0x1b,0x44, + 0x8f,0x09,0xff,0xdc,0x01,0x8d,0xcc,0xae,0xd1,0x8d,0xa4,0x90,0xb6,0x4c,0xf8,0x1f, + 0x6e,0xe3,0xfe,0x1c,0x43,0x11,0x7b,0x4a,0x1e,0xa1,0x4f,0x5b,0x54,0x13,0xfe,0x29, + 0x44,0xed,0x8c,0xf6,0xd4,0x06,0xb2,0x1c,0xb6,0xa4,0x9b,0xfd,0x45,0xc6,0xfc,0x0c, + 0xee,0x1a,0x22,0x66,0xff,0x8f,0x84,0x9b,0x50,0xf5,0xd2,0x5c,0xcb,0xed,0x06,0x30, + 0x90,0x15,0x77,0xdc,0x1f,0xa2,0xe0,0xfc,0x46,0xcd,0x39,0x08,0xb9,0xd9,0xc4,0x84, + 0x7f,0x7c,0xb8,0x0d,0xdd,0xc2,0xdd,0xac,0xc6,0x47,0x87,0x05,0x37,0xac,0x9f,0xf0, + 0x3f,0x18,0x8e,0x08,0x8e,0x7f,0x16,0x33,0x31,0xcb,0xe4,0xff,0x39,0x49,0x7f,0x07, + 0x55,0x5e,0xdb,0x79,0xf1,0x99,0x98,0xdb,0x27,0x18,0xc3,0x3f,0x7c,0xf0,0x39,0xb9, + 0x5c,0x8b,0x3f,0x1d,0xaf,0x79,0xd6,0x84,0x7f,0x8e,0xa3,0xed,0xe1,0xae,0xcd,0xf2, + 0xca,0x08,0x0b,0x35,0xb7,0xd7,0x16,0xac,0x19,0x32,0xe2,0x83,0x7c,0x7d,0xd8,0x9f, + 0x7c,0xa5,0x8b,0xac,0xc7,0x9a,0x5e,0x37,0xe1,0x9f,0x28,0x84,0x55,0xfb,0x94,0xba, + 0x55,0x44,0x45,0x79,0x5b,0xc6,0xfd,0x3f,0xa7,0xa0,0xc7,0x1b,0x1f,0x04,0x7c,0xf6, + 0x3c,0xfa,0x2c,0x39,0x62,0x92,0x3f,0xfd,0xb0,0x3b,0xd3,0x59,0x67,0x51,0xfc,0xb7, + 0xbb,0x36,0x68,0x6a,0x35,0xbe,0xe6,0x6b,0xf8,0xbe,0x2a,0x7f,0xdf,0x37,0x60,0x83, + 0xae,0x7a,0xea,0x14,0x7f,0x9f,0x19,0xff,0x18,0xab,0x47,0x37,0x66,0xe1,0x42,0xa1, + 0x3c,0x8f,0xaf,0x67,0x7c,0xd0,0x22,0xd8,0x3d,0x34,0xe8,0x79,0xdd,0x84,0x7f,0xce, + 0xc0,0x59,0xa8,0xac,0xbe,0x7b,0x73,0xc1,0x72,0x78,0x2b,0xfe,0xd8,0xd2,0x38,0x79, + 0x38,0xee,0xe8,0x63,0x28,0x1f,0x36,0x8b,0xc3,0x26,0xfd,0xdb,0xc9,0xc6,0x83,0xe1, + 0x7a,0x9b,0x92,0x13,0x77,0x03,0xf2,0x69,0x67,0x63,0x83,0x7e,0xed,0xac,0xba,0x6f, + 0xe1,0xac,0xcd,0x26,0x7d,0x87,0xf8,0x87,0x0d,0x53,0x03,0xed,0xf8,0x70,0xb5,0x39, + 0xfe,0x14,0x63,0xf8,0x33,0xe6,0x88,0x63,0x6e,0x65,0x31,0xdb,0xda,0x6a,0xc2,0x3f, + 0xb7,0xb9,0xd6,0x69,0x7e,0x46,0xa3,0x68,0x7f,0xbd,0x00,0x76,0x96,0x16,0xf3,0xff, + 0xcc,0x8b,0x39,0x82,0xd6,0xa5,0xa1,0xc6,0x1f,0x21,0xad,0x26,0xfc,0x73,0x97,0x71, + 0x4c,0x68,0x79,0xba,0x95,0xb4,0xf1,0xb0,0xc5,0x84,0xbf,0x82,0x1f,0x1c,0xb2,0x81, + 0xa9,0x0d,0x54,0x49,0x6f,0x35,0xe1,0x9f,0x4a,0x58,0xad,0xe1,0xfc,0x06,0xff,0x54, + 0xb6,0x55,0x99,0x39,0x7c,0x7d,0xd2,0xff,0x83,0x82,0x6e,0x0d,0x0f,0xa4,0x5a,0x49, + 0x57,0xe2,0xfe,0xdb,0xe8,0x34,0xb4,0x5f,0x66,0x23,0xec,0xb1,0x64,0xa9,0x6f,0x84, + 0x76,0x8c,0x64,0x72,0xff,0xcf,0x67,0xec,0x56,0x0e,0x7b,0xde,0x55,0x4e,0x72,0x20, + 0xb4,0xb4,0xe6,0x05,0x13,0xfe,0xd9,0xc6,0xbd,0xaf,0x7f,0xc0,0xd3,0xb7,0x4d,0x7f, + 0xa7,0xbe,0xcc,0xe4,0xcf,0x0f,0x8b,0x03,0x93,0xae,0x40,0x15,0xb3,0xe9,0xa2,0xc7, + 0x84,0x7f,0xae,0x48,0x3f,0x67,0xf3,0xa3,0xb6,0xdd,0xa5,0x3f,0xa3,0x47,0x59,0xe9, + 0x69,0x1b,0xc7,0x3f,0x57,0xf9,0x95,0x1e,0x1c,0xfc,0x69,0x53,0xd5,0x72,0x5b,0x4f, + 0x8d,0x6e,0xf2,0xff,0xe4,0xb1,0x57,0x82,0xf9,0x43,0x6d,0x17,0x3c,0x95,0x6c,0x0d, + 0xe4,0x1b,0xfe,0x1f,0x6d,0x07,0x7f,0xfe,0x47,0x71,0xb0,0xaa,0xbc,0xf8,0x6e,0x79, + 0x66,0x8e,0x09,0xff,0xc0,0xe6,0xb4,0x5d,0xf0,0xbc,0xde,0xd6,0x40,0xee,0xf3,0xaf, + 0x49,0xfa,0x7f,0x70,0xfe,0xc3,0xf8,0xbe,0xcd,0x88,0x88,0x65,0xaf,0x3d,0x05,0xff, + 0x20,0x9a,0x42,0xb1,0xa3,0xfa,0xad,0x28,0xc6,0x93,0xf1,0x8e,0x5e,0x1c,0x1c,0x66, + 0x7e,0xea,0x6c,0x91,0xe7,0x90,0x48,0x62,0x7f,0x76,0x4d,0xf9,0x2d,0x82,0x9c,0xf9, + 0xba,0x6d,0x4f,0xc1,0x4f,0xe0,0xa8,0x50,0x1a,0x13,0x9b,0xb1,0xf7,0x15,0x06,0xa0, + 0x85,0x55,0x36,0xd8,0x7e,0xbd,0x35,0xf9,0x3c,0x8c,0xfb,0x7f,0xa0,0xf2,0xb4,0x2d, + 0x5c,0x33,0x20,0xc5,0xd5,0xdc,0x40,0x2c,0x1e,0xc1,0x1d,0x65,0x1f,0xf3,0x83,0xc6, + 0x4c,0xf1,0x2f,0x01,0x45,0xf6,0x55,0x68,0xd2,0x9d,0x0d,0xe2,0x3e,0xcb,0x22,0x04, + 0x42,0x1c,0xf6,0xa0,0xfe,0x9a,0x8b,0xf2,0xbc,0xe0,0x12,0x0c,0xf0,0xf5,0xf4,0x8a, + 0x90,0x88,0x7f,0x35,0x4a,0x0f,0x42,0xb8,0x19,0xf5,0x3b,0x23,0x4e,0x90,0xb9,0xe2, + 0xe6,0xfa,0xf7,0x45,0xc9,0x1d,0x73,0xec,0x74,0xbd,0x5e,0xe2,0x96,0x03,0x08,0xe4, + 0x4c,0xfe,0x1f,0xb6,0x97,0x39,0xf4,0xba,0x6e,0xcf,0x36,0x5a,0x80,0xef,0x9b,0xc7, + 0xa7,0xb5,0xc1,0x8c,0xd8,0xfc,0xdd,0xbd,0x25,0x3e,0xb9,0xa7,0x43,0x35,0xc9,0x1f, + 0x0a,0x7b,0xa9,0x1a,0xe1,0xde,0x0f,0x86,0x1b,0x6f,0x90,0xfb,0xe7,0x25,0x43,0x50, + 0xbb,0x71,0x7e,0x08,0xf0,0xbf,0x9a,0x9e,0x9e,0x94,0x3f,0x90,0xb9,0x1c,0x57,0x63, + 0xbe,0xbe,0xb8,0xdb,0xb3,0x4f,0xfd,0x0b,0x94,0x0e,0x5a,0x0d,0xfd,0xab,0xe0,0xc6, + 0xe8,0x6e,0x1a,0x99,0x8c,0x82,0xb4,0xda,0xb6,0xba,0x0d,0x12,0xf2,0x27,0x94,0x39, + 0x86,0xf3,0xf7,0x0f,0xda,0x86,0x70,0xda,0x7b,0x50,0xd9,0x2f,0x4f,0xf8,0x7f,0x96, + 0x8c,0x8a,0x27,0x15,0xae,0xf3,0x71,0xff,0x0c,0x27,0xe3,0x5f,0x69,0xfc,0xd7,0x52, + 0xbd,0x78,0x54,0xae,0xe4,0xdb,0x26,0x92,0xf9,0xd9,0xab,0x3f,0x83,0xab,0xae,0xb9, + 0x3e,0x9b,0x2e,0x8c,0xe2,0x89,0x2b,0x05,0x6b,0x5f,0x93,0x19,0xff,0x7c,0xa2,0xed, + 0x69,0x42,0xf9,0x3c,0x46,0x4a,0x60,0xaf,0x5a,0xf4,0x7b,0x7a,0x1e,0x07,0xaf,0xf8, + 0xe6,0x68,0xf2,0x6a,0x32,0x4b,0x0b,0xe8,0xf6,0xa0,0xe5,0x59,0xbb,0x19,0xff,0x0c, + 0x48,0x3b,0x04,0x55,0x6f,0x51,0xb8,0xb7,0x87,0x3a,0x06,0x32,0xdc,0x68,0x86,0xef, + 0x50,0x0a,0x35,0x39,0xd7,0xaf,0x01,0xab,0x56,0x95,0x3c,0x78,0x99,0x98,0xf0,0xcf, + 0x36,0xd8,0xdb,0xbc,0xac,0x16,0x85,0xb6,0xd3,0x08,0x7b,0xa1,0x21,0xe6,0xa4,0x37, + 0xc2,0x0c,0x9f,0xbc,0x89,0x94,0x08,0xad,0xcd,0xcb,0x1a,0xb3,0xbb,0x56,0xa7,0xc4, + 0xbf,0xa4,0x8b,0x2c,0xac,0x65,0xf6,0xc8,0x4e,0x63,0xdb,0x64,0xf2,0x78,0xf1,0x45, + 0x28,0xd3,0x6c,0x9b,0xe4,0xef,0x91,0x43,0xba,0x7b,0xbb,0xb5,0x5d,0x84,0x64,0xfc, + 0x0b,0xf6,0xc5,0xd0,0xd1,0x6e,0x63,0x59,0xf6,0xf7,0xc6,0xfd,0x81,0x55,0x1a,0x22, + 0x46,0xbe,0x91,0xf6,0x6f,0xb0,0x35,0xc8,0xa9,0xf1,0xaf,0x8f,0x89,0x9b,0x9b,0xed, + 0xfc,0xfe,0x65,0xfa,0x5d,0xae,0x1a,0x1e,0xff,0x9a,0xa7,0x65,0xb9,0x26,0x7d,0x08, + 0xef,0xf8,0xf6,0x04,0x9d,0x3b,0x45,0x13,0xfe,0x91,0x2a,0x59,0x93,0xb7,0xe3,0x34, + 0x5a,0xeb,0x4e,0xdc,0xf6,0x05,0xbd,0x75,0xa3,0x46,0xfc,0x0b,0x57,0xac,0x3b,0xfb, + 0x53,0xd6,0xba,0xd0,0x1e,0xa0,0x7b,0x6a,0xba,0x4d,0xf8,0xe7,0x2e,0xb6,0x95,0x15, + 0x7a,0x8a,0x14,0xbe,0x2c,0xec,0x59,0x3d,0x2f,0x7e,0x5e,0x34,0x44,0x2c,0x01,0xc1, + 0xdf,0x5b,0x42,0x64,0xbb,0x29,0xff,0xc7,0x87,0xf2,0xe7,0x97,0xa1,0xe9,0xcb,0xe9, + 0x52,0xcf,0x34,0xd8,0x15,0x88,0xa7,0xc1,0xec,0x62,0xf9,0x3e,0x5a,0xef,0x79,0x97, + 0x6e,0x0a,0x4d,0xbf,0xff,0xc6,0x1f,0xa4,0xb7,0x27,0xfd,0x3f,0x75,0xce,0xe6,0xf7, + 0x2d,0x73,0x6a,0x71,0xdb,0x5a,0xe9,0x67,0x30,0x47,0x2f,0x46,0xfc,0xa3,0x7d,0x86, + 0xe7,0x31,0xcb,0x25,0xf4,0x92,0x63,0x7a,0x45,0x70,0x3d,0xa4,0xe4,0xff,0xe0,0xfb, + 0xaa,0xf3,0x6b,0x27,0x8d,0xe5,0x5c,0x82,0x2f,0xf9,0x42,0x9d,0xe5,0xf1,0x2f,0x8e, + 0x7f,0x76,0x8a,0x63,0xf0,0x17,0xdc,0x8a,0x78,0x82,0x4c,0xf8,0x67,0xca,0xa7,0xda, + 0xef,0x71,0x59,0xd6,0x05,0xd7,0xac,0xc0,0x65,0x71,0xf3,0x83,0x8c,0x0b,0x85,0x86, + 0x30,0xce,0xaf,0xe7,0x8e,0x5c,0x6e,0xaf,0x99,0xf1,0xcf,0x3e,0xb6,0x0a,0x0a,0xf4, + 0x3a,0x6f,0xf6,0x54,0x09,0x05,0x4b,0x44,0x3e,0xbf,0x71,0x2a,0xec,0x72,0xdc,0x5a, + 0x2d,0x47,0xc5,0xfb,0x94,0x5d,0xb0,0x45,0x97,0x7d,0xa9,0xf1,0x2f,0x54,0xb9,0xd3, + 0x11,0xff,0x90,0x69,0x14,0x5f,0x73,0xe8,0xc9,0x47,0xc9,0x34,0xd8,0xf1,0xcb,0x7c, + 0x9f,0xbc,0x72,0xf5,0x34,0xfe,0xe2,0xef,0x2f,0x2a,0x4f,0x77,0xa5,0xf8,0x7f,0x9a, + 0x34,0xfb,0x50,0xcc,0xff,0x6c,0xf8,0xf3,0x2d,0x56,0xdc,0x48,0xcb,0x7d,0x72,0x37, + 0xb9,0xab,0x7a,0x87,0x57,0x1d,0x95,0xe7,0x98,0xe3,0x5f,0x88,0xdf,0x5e,0xa7,0x65, + 0x88,0x76,0x6c,0x75,0x70,0x0e,0xdc,0x8d,0x99,0x21,0xd1,0xc1,0x23,0x7a,0x5d,0xeb, + 0x43,0xe2,0x3c,0xf8,0x82,0x95,0x06,0x6d,0x23,0x93,0x52,0xe2,0x5f,0x64,0xf8,0xce, + 0x4a,0xc8,0x02,0x31,0x94,0x84,0x01,0x7c,0xb0,0xa4,0x59,0x8c,0xaa,0x88,0x7f,0xc0, + 0xd6,0x68,0xc6,0x3f,0x70,0x26,0x63,0xbc,0xba,0xc3,0xdb,0x15,0x94,0xb9,0xb7,0xc7, + 0x8e,0x6a,0xee,0x5b,0x43,0x78,0x6c,0xcb,0x34,0x67,0x58,0x9c,0xc1,0xc6,0x25,0xf7, + 0x42,0x5b,0x9e,0x29,0xfe,0xc5,0x6a,0xff,0x2c,0xec,0xf6,0xd9,0x1f,0xc6,0xfd,0x5f, + 0xa8,0x3c,0xaf,0xd9,0xb5,0x2c,0x43,0xff,0x0a,0x68,0x71,0x6f,0xcc,0xee,0xa4,0xbb, + 0x49,0xc7,0x43,0x59,0x9b,0x89,0x09,0xff,0x48,0xcf,0x34,0xf3,0xe8,0x8c,0x25,0x98, + 0x5e,0xa8,0xb5,0x68,0x2f,0x24,0xf1,0x0f,0xe5,0x19,0x2f,0xbb,0xab,0x11,0x11,0xfd, + 0x32,0x05,0xff,0xa4,0xe1,0xaf,0x0e,0xef,0x0d,0x4a,0xba,0x04,0x5b,0x34,0xea,0xb5, + 0xe4,0xf2,0x78,0x50,0x6d,0x11,0x22,0xa2,0xf4,0xe6,0x8c,0xed,0x82,0xca,0xaf,0x98, + 0xf0,0x4f,0x86,0x0f,0x7a,0x60,0x9e,0x25,0x8b,0xa7,0xd9,0x70,0x47,0x84,0x81,0x7f, + 0x78,0xbc,0x09,0x15,0xb1,0x4a,0x57,0x42,0x37,0x5b,0xc2,0xe4,0x94,0xf8,0x97,0x74, + 0xb9,0x7a,0xae,0x96,0x36,0x68,0x84,0x75,0xca,0xbc,0xeb,0x36,0xf1,0x81,0x36,0x17, + 0xcf,0xa3,0xf8,0x39,0xfd,0x5c,0xab,0xf2,0x66,0x1d,0x37,0xfb,0x7f,0x84,0xf3,0x70, + 0xd8,0x31,0xf7,0xef,0x96,0x6c,0xac,0x39,0x9f,0x7b,0xb9,0x16,0xb7,0xcd,0x2f,0x79, + 0x60,0xc8,0x37,0x4f,0xb3,0xfd,0x41,0xd8,0x09,0x87,0xd5,0xd2,0xc5,0xf0,0x7b,0x71, + 0x86,0x39,0xff,0xc7,0x1e,0x20,0x76,0x2a,0xaf,0x42,0x23,0x74,0xa7,0xda,0x41,0x65, + 0x3f,0xae,0x46,0x8f,0xcf,0x6e,0xb1,0x3d,0x6b,0xc9,0xc7,0x27,0xec,0xd8,0x5c,0xb7, + 0xc6,0x92,0x95,0x58,0x4f,0xb8,0xbd,0xbf,0xbf,0x05,0x9c,0x4b,0x65,0xc5,0xc3,0x61, + 0x9e,0xea,0x91,0x73,0x49,0x33,0x6c,0xd7,0xd0,0x02,0xcd,0x4d,0x4f,0x83,0xc6,0x5a, + 0x5c,0x58,0x85,0x10,0x33,0xfe,0x11,0x5a,0xaa,0xf9,0x32,0xa2,0x99,0xb9,0x1d,0xec, + 0xd5,0x3c,0x4c,0x06,0xdb,0x85,0x65,0xda,0x22,0x1e,0x61,0xcc,0xc0,0x2f,0xa8,0x6c, + 0x20,0xe9,0x49,0xfc,0xa3,0x74,0xe6,0x1e,0x60,0x3f,0xd3,0x96,0x24,0x61,0x5b,0x01, + 0x3e,0xbf,0x34,0xef,0xf6,0x45,0x9b,0xc5,0x19,0xfa,0x81,0x90,0xbb,0xa1,0xf0,0x69, + 0x31,0x99,0xff,0xf3,0x02,0xe0,0xaf,0xed,0x28,0x9d,0x9e,0x2a,0x8d,0x87,0xbd,0x94, + 0x9a,0xd8,0x20,0xeb,0x49,0x71,0xc8,0xf2,0xa1,0xbd,0xa2,0x76,0x52,0x7b,0x4e,0x0a, + 0xfe,0x51,0x23,0x9a,0x1b,0x8d,0x47,0x91,0xc7,0x1f,0xdd,0x42,0x7c,0xbf,0x95,0x41, + 0x66,0xba,0x98,0x2f,0x8d,0x79,0xdc,0xd4,0xda,0x68,0xf6,0xff,0x48,0xb7,0xb9,0x5e, + 0xd7,0x9a,0x98,0x25,0x54,0x5a,0x04,0xad,0xac,0xac,0x51,0x0e,0xb9,0x87,0x63,0x81, + 0xb0,0x21,0xd2,0x1a,0x7c,0x19,0xb6,0x32,0x3a,0x64,0xf6,0xff,0x34,0xaf,0x90,0x1e, + 0xd7,0x0d,0x37,0xec,0x1d,0xf0,0x78,0x48,0x35,0xcc,0x04,0x69,0x87,0x84,0xf8,0x47, + 0xc5,0x2b,0x3b,0xd4,0xc2,0x7b,0x17,0xed,0xf4,0x9b,0xe2,0x5f,0xd5,0x14,0x9a,0x68, + 0xfe,0x69,0xcb,0x4a,0x72,0x9d,0xba,0x8a,0x4e,0xe7,0x30,0x00,0xf1,0x00,0x99,0x8e, + 0xc0,0xc0,0xcf,0x81,0x01,0xfe,0xc3,0x06,0x18,0x36,0xc5,0xbf,0xee,0x81,0x3f,0x22, + 0xc8,0xb1,0x96,0xcb,0xdf,0x85,0x3f,0x04,0x66,0x47,0x6d,0x3f,0x46,0xfc,0x73,0x35, + 0x70,0xeb,0x70,0xe6,0xb0,0xf8,0x5d,0xe9,0x4b,0x36,0xc5,0x37,0xab,0xde,0xec,0xff, + 0xb9,0x3e,0x9c,0x77,0x51,0xd8,0xcf,0xfd,0xf3,0x03,0x30,0xa6,0x55,0xf6,0xdb,0x5e, + 0xe2,0x78,0xc0,0x3b,0xef,0x24,0x47,0x44,0x5c,0xf0,0xf6,0x6e,0x36,0xfb,0x7f,0xb4, + 0xb4,0x0b,0xda,0x55,0x56,0x15,0xb5,0xf6,0x88,0xd7,0xc1,0x07,0x71,0xd8,0xa3,0x5d, + 0x64,0xa5,0xa3,0xd6,0x61,0x52,0xa9,0x1d,0xda,0x38,0xb9,0xf0,0xbe,0x1e,0x53,0xfe, + 0x67,0xd7,0xe4,0xa7,0x60,0x57,0xa8,0x38,0x80,0x30,0x2c,0x17,0xfe,0xa7,0x92,0xdf, + 0xdf,0xb6,0xd2,0x8e,0x8f,0x1d,0x9e,0xdb,0x9f,0xb9,0x10,0xa6,0xde,0xb3,0xa6,0x33, + 0x7f,0x60,0xe9,0x22,0x62,0xc6,0x1b,0x41,0x6d,0x97,0x5a,0xec,0x47,0x7b,0xed,0x5e, + 0x78,0xc6,0x80,0x79,0xd9,0x27,0x15,0x1e,0xff,0xa2,0xf6,0xac,0xa9,0xda,0x13,0xe4, + 0x7d,0xed,0xb6,0xef,0xe1,0x09,0x9a,0x58,0x7f,0x5f,0xae,0x8f,0xe7,0x56,0x36,0x66, + 0xb8,0xdc,0x12,0xcf,0x1f,0x8b,0xe3,0x1f,0xa1,0x50,0xcf,0x90,0xd2,0x6d,0xbe,0xc7, + 0xeb,0xd4,0xc1,0xeb,0xb7,0x5d,0xf7,0x76,0xc2,0x3f,0xc9,0xf3,0xb5,0xc6,0xa5,0x4a, + 0xcd,0x1a,0xbe,0x65,0x39,0x02,0xd1,0xf9,0xdc,0xde,0x1c,0x31,0x34,0xb2,0xb5,0x53, + 0x2c,0x81,0xdf,0xab,0x6e,0x5f,0x46,0x8f,0x78,0xd0,0xf4,0x3c,0x51,0x18,0xf7,0x56, + 0x2a,0x86,0x5b,0x0c,0xb7,0x4d,0x2f,0x87,0x3d,0x4a,0x1c,0x08,0x8d,0x28,0x1f,0x42, + 0x65,0xf4,0xee,0x5d,0xf8,0x53,0x12,0xff,0x8c,0xc2,0x6b,0x74,0x7e,0x48,0x0a,0x4f, + 0x3a,0xaf,0x5d,0xd1,0x0d,0xfc,0xb3,0x0f,0x7e,0x6e,0xe4,0x7b,0x34,0x3d,0x20,0x5c, + 0x15,0x4a,0xfb,0x6c,0xa3,0x72,0x28,0x71,0x5e,0x7a,0x61,0x19,0x69,0x61,0x76,0xd5, + 0xc1,0xa3,0x69,0x3d,0xd0,0x81,0xfa,0xd4,0x50,0xc4,0x3f,0xc3,0xfd,0x60,0x71,0xd2, + 0xdd,0x8d,0xf6,0x21,0x79,0x8f,0x18,0x32,0xe1,0x1f,0xbb,0xd0,0xa2,0xff,0xf0,0x84, + 0x25,0x9c,0x3d,0x64,0xc4,0xbf,0x22,0x2e,0xb2,0x4d,0xda,0x9b,0x56,0xa2,0x23,0xde, + 0x76,0x66,0xbc,0xd8,0x6b,0x57,0x6e,0xec,0x9a,0x11,0x32,0xc9,0x1f,0x42,0x1b,0x55, + 0x95,0xa1,0x76,0x6b,0xe6,0xe7,0x51,0xbf,0xde,0x85,0x40,0x71,0x87,0xea,0xd0,0x45, + 0x42,0xac,0xc2,0x76,0x97,0x0a,0xbf,0x22,0x66,0xfc,0x63,0x55,0x03,0x2d,0xea,0x3c, + 0x96,0x15,0xf6,0x73,0xb7,0x4f,0x37,0x7f,0xfe,0x6d,0xf0,0xa5,0x63,0x16,0x4f,0x73, + 0x72,0xc2,0xc7,0x3c,0x22,0xec,0x6f,0x0a,0x25,0xf1,0xcf,0x4d,0xd1,0xda,0x71,0x65, + 0x01,0x7b,0x60,0xb4,0xe0,0xbc,0x74,0x19,0xaa,0x7a,0x93,0xf1,0xaf,0x46,0xf1,0x92, + 0x74,0x5e,0xe3,0xf8,0xb9,0xa0,0xcb,0x84,0x7f,0x2e,0xc0,0x09,0xa9,0x72,0xd0,0x79, + 0x3e,0x67,0x85,0xf4,0xde,0x86,0xb2,0x53,0xeb,0x7f,0x2c,0xba,0xc9,0xd1,0x6c,0x23, + 0x7e,0x7a,0x3e,0x34,0xe0,0x2e,0xc8,0x5f,0xfc,0x6a,0x8e,0xcb,0x14,0xff,0xfa,0x08, + 0x41,0xe9,0xac,0x41,0xfa,0x85,0x7d,0x41,0xf3,0x8b,0x50,0x14,0xcd,0xea,0x26,0x33, + 0x60,0x7d,0x03,0x4f,0x04,0xf2,0x7c,0x10,0x6e,0x7f,0xc4,0x1e,0xa2,0xab,0x89,0x2b, + 0x11,0x7f,0x8f,0xa0,0xfd,0xc5,0xc0,0x79,0x82,0xce,0x21,0x77,0xa9,0x4d,0xaa,0x11, + 0x5f,0x1e,0xca,0x6d,0x52,0x63,0xf6,0x45,0x63,0x50,0xb0,0x03,0x15,0x88,0xdb,0x14, + 0xff,0xfa,0x17,0xd2,0xe2,0x2f,0x41,0xd8,0x63,0x5f,0x81,0xfb,0xa1,0xa8,0x17,0xf1, + 0xe7,0x19,0x04,0xd2,0x06,0x9e,0xfc,0x94,0x3c,0xc5,0xec,0x8c,0xb6,0x13,0x57,0x32, + 0x3f,0x79,0xf2,0x47,0x10,0x89,0x54,0xea,0x8b,0xc3,0xf2,0x0a,0x84,0xb5,0x65,0xb8, + 0x1f,0x6a,0x1e,0xe4,0x03,0x7d,0x52,0x58,0xfc,0xb3,0xe3,0x40,0x9f,0x2b,0x7b,0xf1, + 0x66,0x51,0x31,0xc5,0xbf,0x7a,0xd4,0x71,0xbe,0x2c,0x61,0xdc,0x06,0x7c,0x59,0xe4, + 0xf3,0xa4,0x02,0x07,0x7b,0x39,0x3e,0x1c,0xc2,0xcd,0xf5,0x4a,0x64,0x89,0x26,0x0f, + 0x9b,0xe2,0x5f,0xdb,0xb8,0x76,0xd3,0xd7,0x86,0xc5,0xb5,0xf4,0x1d,0x63,0x9b,0xdd, + 0xe8,0x94,0x0e,0x49,0x71,0xff,0xcf,0x30,0x5f,0xff,0xb0,0x19,0xff,0xa4,0x65,0xb1, + 0xdd,0x6a,0x81,0x4e,0x47,0xc5,0x9f,0xe0,0x7c,0xdc,0x06,0x3d,0xa8,0x88,0xd7,0x4b, + 0x86,0x23,0xe8,0xe3,0xbe,0xc0,0x52,0x1c,0xfc,0xda,0x94,0xff,0x8c,0xf8,0x07,0xc2, + 0x43,0x33,0x38,0xcc,0x5b,0x8b,0xaf,0xe9,0xd4,0x33,0xb6,0x27,0x1d,0x17,0x51,0xd4, + 0x2e,0x68,0x98,0x3b,0x96,0x9d,0x4d,0xe8,0xbb,0x51,0x01,0x95,0xbe,0xdf,0x37,0x44, + 0x1f,0x25,0xdf,0x5d,0xf5,0x04,0x4f,0x83,0x59,0x49,0x2a,0xd1,0xc2,0x9a,0xce,0x07, + 0x6f,0x6b,0xbf,0x60,0xd3,0x55,0xb9,0x8e,0x5c,0x49,0x9c,0xaf,0x3b,0xa9,0x55,0x1a, + 0x0d,0x3f,0x32,0xb2,0xb8,0x5c,0xfe,0x2d,0xbc,0x2a,0x54,0x8c,0xac,0x77,0x89,0x56, + 0xf8,0x18,0xc2,0xba,0x6d,0xbe,0x18,0x81,0xcf,0xb4,0x39,0x77,0xd8,0x2a,0x9a,0x7e, + 0x4f,0x26,0xe6,0x6b,0x37,0xf1,0x65,0xb1,0x45,0xe4,0xd1,0xa6,0xd8,0xfa,0xe0,0xfe, + 0x39,0x49,0xde,0xa1,0xf3,0x0c,0x47,0x10,0x41,0xfc,0x03,0xb6,0x0d,0xe2,0x60,0xe2, + 0x3c,0xf2,0xf8,0xd7,0x25,0xa8,0x7c,0x0b,0x61,0xf9,0x8a,0xc8,0xa1,0xd8,0x31,0x74, + 0xc2,0xa1,0xe5,0x95,0xb1,0x7c,0xbc,0xdf,0x08,0x25,0x7f,0xc4,0xfd,0x46,0x92,0xf9, + 0x9f,0x1b,0x36,0xa3,0xb4,0x2c,0x3e,0x1e,0x98,0x5d,0x64,0x55,0xd7,0x40,0x31,0xca, + 0x13,0x71,0x2a,0x59,0xe3,0xb8,0x8d,0xfb,0x7f,0x4e,0xc0,0x2a,0x7e,0x45,0xb7,0xb8, + 0x4d,0xfe,0xde,0xa7,0x1d,0xbb,0xf4,0x99,0xc3,0x1c,0xe6,0x65,0x3c,0x67,0xbc,0xaf, + 0xe5,0x0a,0xc4,0x5f,0xfc,0xa0,0xb2,0x6a,0x75,0x71,0xb4,0x6d,0x25,0xc9,0x33,0xe1, + 0x9f,0x23,0x46,0xf6,0x42,0x1d,0x1e,0x43,0x61,0x2f,0x77,0xfb,0xb4,0x13,0x5b,0xe1, + 0xe3,0xb1,0xc4,0x86,0x61,0x7f,0x8b,0xb6,0x62,0x50,0xde,0x40,0x6e,0x48,0xf1,0xff, + 0x5c,0x61,0xf3,0x78,0x92,0xf3,0x30,0xf9,0x28,0xe6,0xf6,0x59,0xa9,0xc6,0xfd,0x3f, + 0xe3,0xec,0xc8,0xd2,0xca,0x6e,0xdb,0x08,0x02,0xa1,0x89,0xe7,0x37,0xfc,0x3f,0xbd, + 0x3c,0xdb,0x59,0xf0,0x49,0xdc,0xfb,0xb1,0xa4,0x11,0x81,0x50,0x2c,0x10,0x26,0x46, + 0x09,0x4a,0x6c,0x6a,0xf8,0x7f,0x26,0x9e,0x9f,0x2a,0x67,0xb4,0x03,0xfe,0x79,0x5a, + 0x49,0xf0,0xc6,0xc2,0xb8,0x7e,0x34,0x80,0x90,0x1b,0x35,0xac,0xf8,0x67,0x38,0xc0, + 0xdc,0xb5,0xb6,0x8d,0x84,0x24,0x9e,0x9f,0xfb,0x7f,0x5a,0xee,0xcc,0xd2,0x78,0xb4, + 0x0b,0x5a,0x24,0x44,0x2f,0x9b,0xb2,0x25,0x69,0xc2,0x11,0x64,0x6f,0xf1,0x76,0xe8, + 0xf2,0x53,0x29,0xfe,0x9f,0xe9,0xd0,0xa2,0x20,0xfe,0x51,0xee,0x29,0x84,0xe7,0xb9, + 0x9b,0x62,0x23,0xca,0x2b,0x9e,0x38,0x64,0x09,0x92,0x4e,0xee,0xc1,0xf0,0xe0,0x3f, + 0x5c,0x97,0xd8,0x6f,0x20,0x15,0xe2,0xaf,0xce,0x6f,0xd2,0x5c,0x82,0xda,0x5f,0x0b, + 0x55,0xcb,0x53,0xef,0x28,0xe4,0x8e,0x20,0xcd,0x70,0x8c,0x34,0xd6,0x2c,0xd7,0x0e, + 0xe5,0x66,0xb7,0x26,0xe2,0xef,0xe5,0x99,0x3e,0x88,0x08,0xe5,0x50,0xc2,0x64,0x55, + 0x19,0x8e,0xb9,0x1d,0x78,0xd8,0xcb,0x08,0xc4,0x44,0xe1,0xa0,0x54,0xc6,0xaf,0xac, + 0x4b,0xc4,0xbf,0x4e,0xdc,0x74,0xde,0x72,0xb9,0xba,0xd2,0xbb,0xc4,0x08,0x7b,0x71, + 0xfd,0xee,0x15,0x8f,0x73,0xff,0x4f,0xb5,0x2d,0x28,0x5e,0x86,0xcb,0x1a,0x02,0x9b, + 0xe3,0xe2,0x3f,0x24,0xf3,0x79,0xd2,0x76,0xc2,0x65,0x07,0x0f,0x1b,0xb5,0x15,0xaa, + 0x07,0xf8,0xfc,0x41,0x59,0x82,0xb7,0xc0,0xf0,0x9f,0xec,0xd4,0x0e,0xf3,0x2b,0xbf, + 0x8f,0xa6,0x27,0xe6,0xaf,0x54,0x10,0x7d,0x79,0xec,0x53,0xeb,0x9a,0x49,0x3e,0x04, + 0xa0,0x44,0x90,0x99,0x47,0xcd,0x38,0x11,0xf7,0xff,0x68,0x01,0x5f,0x09,0xc8,0xcd, + 0x24,0x2b,0x71,0x1e,0xa9,0x84,0xb0,0x87,0xa9,0x9e,0xfa,0xec,0x3e,0x29,0xd4,0xe8, + 0xc0,0xd3,0x94,0xbd,0x11,0xdf,0xb7,0xc8,0x78,0xdf,0x7e,0xd6,0x78,0xa7,0xb3,0x5a, + 0xce,0x26,0xd9,0xc2,0xc4,0xfc,0xbc,0x29,0xcf,0x48,0xbb,0x55,0x23,0xff,0x87,0x3b, + 0xd6,0x4a,0x34,0x3c,0xb6,0xcb,0xe1,0x49,0x5c,0xd8,0x1b,0x71,0xfd,0x2d,0x6d,0x86, + 0x63,0xad,0x23,0x3d,0x71,0xff,0xd0,0x64,0xee,0xdd,0x72,0x57,0x5b,0x83,0x62,0x21, + 0x35,0x9e,0x3f,0x4f,0x4c,0x6b,0x8a,0x01,0xdd,0x9c,0x3f,0xd7,0xb6,0x6c,0xc1,0x2b, + 0x9b,0xff,0x8b,0xc3,0x14,0xff,0x7a,0x56,0x3b,0x0b,0xfb,0xf8,0x36,0x18,0x22,0xc6, + 0xfa,0x6c,0x24,0x9d,0x19,0xa7,0x62,0xfe,0x9f,0xd7,0xe9,0xb8,0x13,0x07,0xd9,0xf2, + 0x39,0x13,0xfe,0xd9,0xa2,0x8d,0x4d,0x9e,0x07,0x25,0x50,0x83,0xeb,0x2f,0x54,0x0a, + 0x7f,0xcf,0x81,0x10,0x5a,0x59,0xb0,0x8e,0x89,0xa7,0xd4,0x08,0xb8,0x33,0x70,0xfd, + 0x89,0x39,0xfe,0xa5,0xed,0xf7,0xdb,0x1b,0x29,0xcf,0xff,0x69,0xc5,0xcf,0xb6,0x84, + 0x3b,0x82,0x5a,0x63,0x89,0x40,0x63,0x70,0x44,0xb3,0x07,0xdb,0x3e,0x20,0x16,0x93, + 0xff,0xe7,0x1b,0xc2,0x76,0x9f,0x43,0x2f,0x72,0xa5,0x3b,0x63,0xf6,0x42,0x39,0xb1, + 0x8a,0x4d,0xb1,0xc4,0xb9,0x37,0xa0,0x91,0xf9,0x74,0x39,0x0f,0xe7,0x27,0xfd,0x3f, + 0x79,0xc2,0x76,0x92,0xff,0x1a,0x37,0x63,0xf5,0x27,0xf8,0x69,0xbd,0x97,0x54,0xd0, + 0xa6,0x98,0x23,0xf7,0x2d,0xd8,0xd4,0x97,0xaf,0xc9,0xb5,0x44,0x4d,0xc4,0x3b,0xba, + 0x02,0xd7,0xa5,0xbd,0xc4,0xe6,0x8f,0x94,0xfc,0x4c,0x9c,0x06,0x5f,0x86,0x17,0x44, + 0xe5,0x31,0x79,0x1a,0xbc,0x31,0xbc,0x20,0x9a,0xb5,0x52,0xfc,0x82,0x1c,0x65,0xdb, + 0x4f,0xdb,0xc6,0xd0,0xc2,0x9b,0xd8,0x6f,0xf4,0xa6,0x2e,0xbe,0x6d,0x06,0xb3,0x76, + 0xa2,0x74,0xfd,0x18,0xe5,0x49,0x96,0xc9,0x9f,0x3f,0xa6,0x7c,0xca,0x07,0x51,0xb1, + 0x2f,0x69,0xff,0xfe,0xe2,0x0b,0xe5,0x32,0xab,0x3a,0x65,0xbd,0x64,0xab,0xd4,0x8e, + 0x06,0x2a,0xb9,0xda,0xaa,0x84,0xa3,0xec,0x96,0x21,0x1c,0x7c,0x01,0xbf,0xe1,0x89, + 0x40,0x6f,0x89,0x90,0x38,0x5f,0x3c,0xff,0xe7,0x25,0xa5,0x98,0xe3,0xbd,0xcd,0xfa, + 0x73,0x80,0x62,0xe4,0x9b,0x6d,0x28,0x7f,0x82,0x5b,0xb8,0x7c,0x18,0xd4,0x8e,0xab, + 0xf9,0x5a,0x5b,0xc6,0x3d,0x45,0xe9,0x13,0xf3,0x11,0xd1,0x23,0xa8,0x2b,0xee,0x77, + 0xcc,0x26,0x3c,0xf0,0x37,0x5d,0x6f,0xf5,0x5a,0x2a,0xe0,0x71,0xb8,0x9f,0x7b,0x84, + 0xee,0x25,0xab,0xa4,0x7c,0x26,0xdf,0x63,0x49,0xe6,0x3f,0x17,0x4a,0x07,0xa5,0xed, + 0x28,0x76,0xf0,0xfe,0x6b,0x95,0xad,0x5c,0xfe,0xe4,0x91,0x4c,0xf8,0x55,0x4c,0x9e, + 0x1f,0x80,0xa7,0x42,0x2a,0x93,0x0b,0x49,0x5d,0xf2,0x79,0xd2,0x3a,0x83,0xe3,0xbd, + 0x55,0xfa,0xe2,0xd1,0x9c,0x0a,0x38,0x1a,0x7b,0xcd,0x62,0x78,0x2f,0x16,0x5f,0xf8, + 0x00,0x0e,0x44,0xdd,0x41,0xb9,0xbd,0xe9,0x87,0x66,0xfc,0xa3,0x8c,0x77,0xc6,0xdd, + 0x3e,0xb8,0x2c,0xbd,0x4b,0x76,0x8a,0xdb,0xa4,0x8f,0x63,0xff,0xf0,0x23,0x36,0x06, + 0xfb,0xed,0x72,0xf3,0xf7,0x4c,0xfe,0x1f,0x78,0x04,0x0f,0xdd,0x02,0xae,0x8f,0x46, + 0x28,0xb7,0x5e,0x6d,0x51,0xb9,0x42,0x3d,0x1a,0x4b,0x04,0xaa,0x45,0x69,0x5e,0x5a, + 0x2b,0x87,0xb7,0x44,0x4c,0xfe,0x9f,0x65,0xb0,0x3b,0xc0,0xf5,0xaf,0x36,0x02,0x32, + 0xd7,0x5f,0x4e,0xd4,0x47,0xef,0xf0,0xfc,0x5b,0x54,0xc4,0xca,0xf3,0xfd,0xf6,0x7b, + 0x50,0xa2,0x0e,0x27,0xf1,0xcf,0x94,0x19,0xd0,0x23,0xcc,0xd0,0x49,0x98,0xac,0x80, + 0x17,0xa1,0xa4,0xb7,0xad,0x3d,0x7b,0x85,0x10,0x4f,0x04,0x3a,0x83,0x50,0x61,0x06, + 0xb3,0x6c,0x26,0xa1,0x14,0xff,0x33,0x5f,0x9f,0xa2,0x58,0x98,0xc3,0xfa,0x16,0x1e, + 0xc3,0x15,0x62,0x3c,0xf1,0xac,0x0f,0x8d,0x4b,0x15,0x64,0x21,0xbd,0x6f,0x55,0x62, + 0xf9,0x51,0xfe,0x8c,0x57,0xdf,0x3a,0x58,0x74,0x56,0xfc,0x04,0xad,0xef,0x79,0x11, + 0xdc,0xed,0x2b,0xe0,0x2f,0xd4,0x58,0x1f,0x9e,0x68,0xcf,0x25,0x52,0x23,0x4b,0xe0, + 0x9f,0x2d,0x37,0x8d,0xc2,0x02,0x87,0xed,0xe0,0x5d,0xe7,0x0a,0x2e,0x85,0x50,0x7f, + 0x9d,0xb0,0x69,0xe2,0x66,0x38,0x24,0xa1,0x22,0x3b,0xd7,0x34,0x8a,0xaa,0xea,0x15, + 0xe1,0x66,0x26,0x0e,0xd7,0x26,0xfd,0x2d,0xa3,0xf0,0x27,0x69,0x2e,0x58,0x41,0xdc, + 0x08,0x87,0xd9,0x5c,0x75,0x5a,0x40,0xac,0x94,0x06,0x89,0x81,0x7f,0x2e,0xb1,0x0b, + 0x4a,0xa9,0x86,0xd0,0x7a,0xd4,0xe4,0xff,0xf9,0x02,0xbf,0x81,0xc8,0x1c,0x8c,0xd8, + 0x11,0x28,0x16,0xe5,0xd3,0x00,0x31,0x22,0x62,0x3c,0x11,0xfa,0x92,0x8e,0x2f,0xfe, + 0x2d,0x6b,0x98,0x44,0x4d,0xfe,0x1f,0x9d,0x34,0x82,0x84,0x76,0x70,0x3a,0x43,0xc1, + 0x3b,0x03,0xbe,0x03,0xcb,0xd6,0x5a,0x37,0x4a,0xaa,0xbe,0xc8,0xe5,0x19,0x50,0xc3, + 0x6a,0xe1,0xc0,0x22,0x97,0x3d,0xe9,0x7f,0xd6,0xd3,0x50,0x68,0x07,0x10,0x44,0x35, + 0x72,0x7b,0x16,0x8a,0xa8,0x25,0x40,0xb6,0x41,0xab,0xd2,0xa1,0xdf,0x18,0x26,0x23, + 0xca,0x0e,0xa9,0x23,0x8a,0x88,0x28,0x99,0xff,0xa3,0x09,0x9f,0xc2,0xab,0x7a,0x99, + 0xdd,0x5a,0xd8,0xd4,0x84,0xda,0xa4,0x8c,0x5a,0xac,0x05,0xdb,0xe0,0x1d,0xe6,0xd6, + 0x6f,0x0e,0xe7,0x8c,0x48,0x17,0xde,0x76,0x8f,0xe2,0x42,0x0d,0x9a,0xe2,0x5f,0xeb, + 0x5a,0x0d,0x27,0x6a,0x54,0x1c,0x83,0xcb,0xc1,0xaa,0xd0,0x63,0xfa,0xa4,0x4b,0xea, + 0x95,0x40,0x3c,0xfe,0x75,0x89,0x55,0xfa,0x8b,0x47,0xcd,0xf9,0xcf,0xb0,0x0d,0x0e, + 0xdd,0x13,0x96,0xac,0x21,0x31,0x9f,0x46,0x94,0x79,0x92,0xb5,0x39,0x67,0x04,0x0e, + 0x22,0x10,0x35,0x1c,0x95,0x28,0xd8,0x83,0xce,0x54,0xfc,0xe3,0x94,0xda,0x98,0x7d, + 0x93,0x23,0x24,0x3e,0xa0,0x37,0x82,0xfa,0x0b,0xf1,0x31,0xb0,0xc1,0x0b,0x01,0xbe, + 0x7f,0xe0,0x12,0x45,0xc3,0x7c,0x23,0x84,0xcd,0xf1,0xaf,0x29,0x1a,0x2e,0x8b,0x0a, + 0xd4,0xe2,0xc1,0xc1,0x16,0x07,0x64,0x58,0xa5,0x23,0x5a,0x2b,0xab,0x8f,0x25,0xee, + 0x76,0xc3,0x83,0x0d,0xe0,0x4a,0xf1,0xff,0x5c,0x07,0xab,0x98,0xda,0xe9,0xf8,0x8e, + 0xff,0x1e,0xf2,0x6b,0x96,0xaf,0x2e,0xfa,0x3b,0x32,0x0d,0x9e,0x65,0x3f,0x30,0x02, + 0x43,0xd6,0x97,0x43,0xc5,0x68,0x94,0x13,0x73,0xfc,0x8b,0x40,0x6f,0xc8,0x05,0x56, + 0x8b,0x58,0x8d,0xe0,0xbe,0xbc,0xf6,0xa6,0xcc,0xa6,0x01,0xad,0xcf,0x5f,0xae,0xdb, + 0xca,0xc5,0x81,0xdc,0xcf,0x42,0x15,0x41,0xeb,0xfc,0x14,0xff,0xcf,0x4e,0xed,0x32, + 0xec,0x65,0x69,0x83,0x05,0xa3,0xda,0x9f,0x95,0x2a,0xcd,0xa6,0x15,0x9c,0x54,0x2e, + 0xc0,0xdc,0x7e,0xdb,0x59,0xf1,0x32,0xbd,0xa8,0x54,0x81,0x2d,0xc5,0xff,0x83,0xf8, + 0x67,0x9c,0xd8,0x17,0x5a,0x55,0xbb,0xce,0xfd,0xff,0x5c,0x1b,0x6e,0x83,0x8b,0xcc, + 0x48,0x44,0xff,0x54,0x8f,0xe0,0x41,0x58,0x12,0xae,0x31,0xe5,0xff,0x08,0x9b,0xd4, + 0x57,0x10,0xdf,0xd1,0x06,0xc8,0x23,0xab,0x20,0x1f,0xda,0x78,0x22,0xe5,0xcb,0xb1, + 0xb4,0x81,0x4b,0xd0,0x0c,0x33,0x41,0x6e,0xf0,0x24,0xeb,0xbf,0x74,0xe5,0x9f,0xb9, + 0x93,0x47,0xa5,0x11,0xf7,0x31,0xb5,0x93,0xa3,0x3b,0xdd,0xff,0xb4,0xd4,0xcd,0x66, + 0x1a,0xef,0xbb,0x61,0x83,0xff,0xfe,0xd0,0xa1,0x95,0xf6,0x64,0xfd,0x5d,0x9d,0x72, + 0x18,0x76,0x04,0x7d,0x5d,0xb4,0x1c,0x41,0xc5,0xd6,0x85,0x85,0x85,0x32,0x2d,0x5a, + 0x4b,0xbb,0xb5,0x98,0x23,0x5a,0x78,0xb2,0xdd,0xa1,0xc8,0xa9,0xf9,0x3f,0xbb,0xb5, + 0x2f,0xd8,0x8f,0x98,0xf5,0xa3,0xef,0x8d,0xe1,0x46,0x9e,0xcb,0x96,0x0c,0x93,0x2e, + 0xeb,0x15,0x57,0x51,0x2c,0x10,0xf6,0x2e,0x2b,0xdd,0x88,0x83,0x0b,0x09,0x79,0x6e, + 0xe0,0x1f,0xad,0x42,0x9a,0xc5,0x26,0x9f,0x02,0xaa,0xed,0xc9,0xb6,0x35,0x73,0x7b, + 0x1c,0x51,0xa9,0x81,0x7f,0x86,0x63,0x1e,0xa1,0xd4,0xfc,0xe7,0xf1,0x90,0x9b,0xa7, + 0xb5,0x0c,0xc1,0x81,0x66,0x77,0x9d,0x75,0x93,0xd8,0xa9,0x8d,0x37,0xfe,0x4c,0x5b, + 0x1f,0x4b,0x7c,0x75,0xff,0xd0,0xd6,0x9e,0x92,0xff,0xb3,0x9c,0xee,0xa6,0xff,0xa4, + 0xd1,0x1b,0x48,0xb3,0xd6,0xa8,0xab,0x3e,0x7a,0x9d,0xb8,0x1c,0x76,0xb7,0xcf,0xd3, + 0x32,0x0c,0xc7,0x8e,0x54,0xb4,0x4c,0x6e,0x47,0xc4,0x65,0x8e,0x7f,0xed,0x26,0x45, + 0xdf,0xb8,0xd3,0x40,0x3b,0xca,0xe9,0x18,0xec,0x49,0xc4,0xbf,0x76,0x73,0x0f,0xc6, + 0xc6,0x94,0xfc,0x1f,0x09,0x76,0x6b,0x2a,0xe2,0x1f,0x7b,0xb3,0xd0,0x04,0xaa,0x56, + 0xa4,0x78,0x6a,0xe9,0x76,0xcd,0xa9,0x65,0x28,0xf6,0xd7,0x84,0xed,0x1a,0xf5,0xca, + 0xb9,0xc4,0x9f,0xf4,0xff,0xa4,0xf9,0x10,0xff,0x17,0x09,0x99,0x8c,0x74,0x21,0xde, + 0xeb,0x66,0x77,0x33,0xc3,0xf1,0x55,0x12,0x77,0x7c,0x09,0xd9,0x7c,0x60,0xaa,0xff, + 0x9a,0xf2,0xb9,0xf4,0x53,0xed,0x15,0x2f,0x82,0x9c,0x9d,0xe4,0x8f,0x50,0xa5,0xad, + 0xf2,0x8a,0x9d,0x0a,0x87,0x3d,0x93,0x78,0x20,0xec,0xb2,0x76,0xb3,0x97,0xd7,0x7f, + 0x91,0x24,0xfe,0x19,0x0a,0xfd,0x49,0xab,0xf2,0x5a,0x8f,0xcb,0x9b,0xe0,0x03,0x98, + 0xab,0x4d,0xf3,0x8a,0x73,0xe0,0xb2,0x52,0xc2,0xe7,0xe3,0xfa,0xf8,0xe6,0xd7,0xd9, + 0x06,0xc5,0xd5,0x66,0xff,0x0f,0x04,0x08,0x1a,0x4d,0x6b,0xec,0x2a,0xc4,0x0a,0xc1, + 0xbe,0xa7,0x42,0x8f,0xf7,0x41,0x03,0xff,0x84,0x7a,0xf2,0x4b,0xa8,0xec,0xf7,0x9b, + 0xe2,0x5f,0xb7,0x0f,0xc1,0x06,0xad,0xcb,0x4b,0xb3,0x4b,0xfa,0x11,0x1f,0x2e,0x47, + 0xa0,0x68,0xa9,0x85,0xed,0xaa,0x33,0x1e,0x08,0xf3,0xad,0xb8,0x67,0x91,0x92,0x9d, + 0x1a,0xff,0x6a,0xa9,0xe1,0xf1,0xc7,0x2c,0x2e,0x7f,0x96,0xd5,0xe0,0xea,0x15,0x26, + 0xd6,0x53,0xd9,0xad,0x3c,0xe8,0xc5,0x81,0x29,0xfe,0x35,0xf9,0x0c,0xbc,0xa5,0xcd, + 0x7b,0xd8,0x19,0x2c,0xe8,0x6f,0xbe,0x9f,0x95,0x79,0xd3,0x6f,0x98,0x8e,0xdf,0x4b, + 0x2d,0x89,0x27,0x36,0xd7,0xcd,0xf3,0xad,0x0f,0x4e,0xea,0x4a,0x8d,0x7f,0x75,0xcd, + 0x5b,0x6e,0x53,0x6a,0x9e,0x85,0xf1,0xcd,0x3c,0x0d,0xfe,0x55,0x9c,0xa6,0xfe,0x2c, + 0x3e,0x5f,0xfa,0x59,0x1d,0x02,0xa7,0x8f,0x52,0xf3,0x7f,0x48,0x19,0x38,0xd9,0xab, + 0x3e,0x38,0x51,0x5b,0xa6,0x64,0x35,0x17,0xc4,0xc2,0x8e,0x36,0x56,0xc0,0xb7,0x62, + 0x59,0x9e,0xb5,0x51,0x34,0xe7,0xff,0x50,0x44,0x46,0x05,0x9b,0xe8,0x69,0x71,0x65, + 0x60,0x5d,0x60,0x2b,0x93,0x47,0x48,0x79,0x60,0x9d,0xab,0xa4,0x91,0xc7,0xbf,0xe8, + 0x9e,0xb4,0x5b,0x3a,0x68,0x57,0xb6,0x39,0xff,0x67,0x31,0xb4,0x09,0x33,0x36,0xd1, + 0x0a,0xcb,0x42,0xd8,0xa1,0xab,0xf5,0xb2,0x74,0x87,0xae,0x36,0x49,0xf5,0x13,0x81, + 0x1b,0x55,0x41,0x55,0x9e,0x92,0xff,0x23,0x20,0x6c,0x66,0x01,0x8d,0xdc,0x27,0x3c, + 0x07,0xf9,0xe4,0x46,0x8d,0x1d,0x23,0x6b,0x84,0x62,0xfd,0xc6,0x06,0xcf,0xc9,0xc6, + 0x5d,0x9b,0x66,0xaa,0xd4,0x9c,0xff,0xb3,0x8d,0x66,0xc1,0x1b,0xc1,0x5b,0x55,0xeb, + 0x98,0xfc,0x5d,0xeb,0x97,0x4d,0xb3,0x43,0x77,0xd7,0xe1,0xe9,0x78,0x83,0x2d,0x88, + 0x4e,0x5a,0x29,0xbe,0x07,0x9f,0x85,0x4a,0x55,0x67,0x6a,0xfe,0xcf,0xb6,0xec,0x8b, + 0xf9,0x95,0x60,0x48,0xd7,0x77,0x0c,0xb3,0x42,0x06,0x03,0xff,0x18,0xf5,0x5f,0x17, + 0xef,0xc0,0x2b,0xe1,0x82,0x3e,0x32,0xb1,0x3e,0x90,0x76,0x85,0xbc,0xde,0x58,0xaa, + 0x5a,0x97,0xc2,0xa3,0xf0,0x65,0xb0,0xb4,0xf0,0xa6,0x3a,0xf1,0x29,0xfa,0x06,0xc2, + 0x9e,0x25,0x63,0xe2,0x15,0xe9,0xe8,0xe8,0xac,0xce,0xf5,0x63,0x44,0x33,0xf9,0x7f, + 0xd6,0x6a,0x7e,0x4f,0x7e,0x00,0xee,0xe9,0xf8,0xcf,0xc1,0x35,0xae,0x5b,0x21,0xef, + 0x0e,0x4b,0x10,0xbe,0x80,0x05,0xfc,0x7d,0x4f,0xc2,0x9a,0x40,0xf1,0x51,0xf9,0x2c, + 0x29,0x32,0xc5,0xbf,0xd6,0xc2,0xba,0x3c,0x94,0xcf,0x83,0xb4,0x62,0xce,0xbf,0x64, + 0x14,0xe0,0x99,0x3f,0x18,0x84,0xf5,0x1a,0xca,0xab,0x87,0x70,0x7d,0xd6,0xa8,0x0f, + 0xb0,0x36,0x2f,0x31,0xc7,0xbf,0x8e,0xd2,0x56,0x4d,0x9d,0x5a,0x97,0x97,0xbe,0x84, + 0xf9,0xf5,0x42,0xa0,0xb9,0xcf,0xb2,0x78,0xfc,0x9d,0x0c,0x48,0x4d,0xcc,0xe9,0xc1, + 0x8d,0x17,0x30,0xc5,0xbf,0x66,0xb1,0x03,0x7d,0xee,0x51,0xe7,0x4e,0xd9,0x06,0xef, + 0x33,0xd7,0x70,0xa6,0x44,0x98,0xf4,0xaa,0x6e,0xe8,0xf7,0x4b,0xc4,0xd6,0x5b,0x19, + 0xe6,0xc0,0xc6,0x1c,0xff,0x52,0xc6,0x7d,0x15,0x41,0xdb,0xce,0xa6,0xdf,0x70,0x7c, + 0x08,0x59,0x9d,0xb8,0x0d,0x2e,0x7a,0x2b,0xe3,0x81,0x42,0x5a,0x19,0x34,0x80,0x41, + 0xd2,0xff,0x73,0x32,0x7f,0x40,0xcf,0x01,0xeb,0x98,0xf8,0x13,0xf8,0x4b,0xa4,0x34, + 0x60,0x3d,0x28,0x36,0x40,0x1c,0xff,0x9c,0xc4,0xc1,0x02,0xee,0x51,0xd1,0x4d,0xf8, + 0x67,0x85,0x25,0xc0,0x3a,0xca,0xe9,0x6c,0x54,0xbb,0x6d,0x60,0x57,0xf1,0x74,0x2f, + 0x63,0x2f,0xb2,0xa2,0x58,0x3c,0x0b,0xf1,0x7f,0xbd,0x23,0xec,0x89,0xa6,0xe4,0x3f, + 0x07,0xa0,0x28,0x54,0xb4,0x33,0x7d,0x1b,0xc3,0xf9,0x50,0xc7,0x3c,0x67,0xa4,0x36, + 0xdd,0xc8,0x57,0x19,0x21,0x88,0x88,0x42,0x74,0x23,0x31,0xd7,0x7f,0x59,0x81,0x09, + 0x21,0x66,0x99,0x83,0xf7,0x47,0xf9,0x03,0xbf,0x12,0x50,0x71,0xbc,0x08,0x9d,0xfa, + 0xa2,0x39,0x1c,0x11,0xe5,0x59,0x75,0x5e,0x7f,0x6a,0x8a,0x7f,0x3d,0xa0,0xad,0xbd, + 0xb7,0x08,0x10,0x06,0x77,0xf2,0xb4,0x13,0xee,0x76,0x1e,0x82,0x43,0xf1,0xc4,0x78, + 0x03,0x31,0x5a,0x7f,0x51,0xa0,0x9b,0xe2,0x5f,0x97,0xe0,0x12,0x99,0x0b,0x8f,0x71, + 0xb3,0xfd,0x12,0xfc,0x0e,0xee,0xee,0xc3,0xf7,0xbd,0xec,0x40,0xe0,0x77,0x4e,0xbc, + 0x44,0x2f,0xda,0x51,0xa3,0x1d,0x4b,0x89,0x7f,0x7d,0x01,0xaf,0xb3,0xd9,0xbe,0xc7, + 0xa2,0x62,0x8f,0x76,0x94,0x55,0x45,0x33,0x23,0xe2,0x39,0x1e,0x91,0x8c,0xa2,0xbe, + 0x73,0x85,0x06,0xd4,0x52,0x6a,0x6b,0x4a,0xc1,0x3f,0x67,0xa0,0x95,0xd9,0x7d,0xb4, + 0x8b,0x38,0x68,0x1b,0x73,0x1e,0xa0,0x3d,0xea,0xa7,0x74,0xaf,0x03,0xf1,0xcf,0x17, + 0x24,0x9f,0xb5,0xe4,0xd9,0x97,0xcb,0x6b,0x52,0xf0,0x4f,0x14,0x5a,0x89,0x43,0xcb, + 0x50,0x89,0x93,0x3d,0x0e,0xce,0x3e,0x6a,0xd4,0xbf,0x23,0xfe,0x91,0xcb,0x88,0xee, + 0x62,0x6a,0x3d,0xc8,0x8a,0x19,0xff,0x4c,0x79,0x96,0xb6,0x42,0x91,0x2f,0xb0,0xa5, + 0xb5,0x18,0x61,0x73,0x89,0x5e,0x1f,0x44,0xd8,0xb3,0x57,0xe1,0x78,0x32,0x7d,0x86, + 0xda,0xc2,0x96,0xd9,0xe5,0xf6,0x74,0x13,0xfe,0x99,0x72,0x06,0x0e,0xb1,0xf2,0xb1, + 0xcc,0x2e,0xb1,0x88,0xbc,0x23,0xe1,0x31,0xd9,0x2d,0x8e,0xd4,0x7e,0xc6,0xe6,0x71, + 0x0f,0xcf,0x19,0x1a,0x89,0xcc,0x9b,0xfd,0x8d,0x40,0x0a,0xfe,0xd9,0x07,0x57,0x36, + 0xed,0xd2,0x27,0xf5,0x88,0x17,0x8d,0xfa,0x38,0x04,0x42,0xa3,0x70,0x95,0xcd,0xea, + 0x5d,0x34,0x2a,0x2f,0x57,0x46,0xc9,0x7e,0x1d,0x05,0x91,0x39,0xfe,0xf5,0x2c,0x5c, + 0x94,0xdc,0x91,0xb5,0x8d,0xe2,0x6f,0xfc,0xdc,0xbf,0x61,0x0d,0x17,0xcc,0x82,0x8b, + 0x19,0x95,0xfa,0x92,0xed,0x72,0xbd,0x8a,0x5f,0xc4,0x6b,0xdd,0x62,0xaa,0xff,0x8a, + 0xa4,0xa5,0xd3,0xee,0x41,0x7b,0x1f,0xa5,0xc4,0xa6,0xb6,0xf1,0x34,0xb0,0x1d,0x76, + 0x27,0xe2,0x09,0xdc,0x0f,0x9f,0x93,0xe9,0xac,0xa5,0xdd,0xee,0xab,0x0b,0x12,0xb7, + 0xc9,0xff,0x53,0x0b,0x1b,0x05,0xd5,0x15,0xa8,0xd8,0xd8,0x82,0xfb,0xa1,0x44,0xb7, + 0x54,0x10,0xab,0xb4,0x83,0x39,0xb9,0xe3,0xe8,0x87,0xd0,0x01,0x85,0x21,0x4b,0x11, + 0x59,0x69,0xae,0xff,0xf2,0xbe,0xdc,0x51,0x30,0x54,0xbf,0x32,0x7b,0x9a,0x91,0xfd, + 0x6b,0x59,0x79,0xc3,0x34,0xd8,0xd5,0x53,0xcc,0x23,0x44,0xd7,0x01,0x22,0x84,0xf2, + 0xef,0xfc,0x5d,0xb6,0xb9,0xfe,0x0b,0xe0,0x1c,0x75,0xf5,0x5b,0x5d,0xe2,0x36,0xf6, + 0x2a,0x54,0x0c,0x67,0x4d,0x17,0x41,0xfa,0x2c,0x7c,0x1f,0x2f,0x7b,0xd7,0xe0,0x14, + 0xec,0x24,0xce,0x12,0xf1,0x1e,0x73,0xfd,0xbb,0x74,0xa9,0xb0,0xaa,0xdf,0xb6,0x25, + 0xe6,0x36,0xec,0x2f,0x6e,0xa8,0xb9,0x54,0x7b,0x55,0xc1,0x2b,0xdb,0x1f,0xdf,0x09, + 0x7f,0x9a,0x3c,0x9f,0x66,0x06,0x53,0xf2,0x9f,0xfb,0x71,0xfd,0xdd,0x4c,0x2a,0x2f, + 0x28,0x04,0xee,0x1f,0x43,0x45,0x70,0xc4,0xf0,0xbf,0x2d,0x09,0xe7,0x94,0x93,0x23, + 0x50,0x1a,0xb5,0xea,0xdf,0x4b,0xad,0xff,0x5a,0x2d,0x6d,0xd1,0xeb,0xbc,0x84,0xd7, + 0xcf,0xce,0xe2,0x89,0x40,0x27,0xa5,0xf5,0x88,0x7f,0xda,0xdc,0xfe,0x4d,0xb0,0x56, + 0xc8,0xd7,0xe9,0xa0,0xc5,0x1c,0xff,0x7a,0x02,0xfe,0xd9,0x7f,0x4b,0x88,0x9e,0x58, + 0x3d,0xcd,0x70,0xfb,0x64,0x20,0xec,0xc9,0x5d,0xb3,0x7a,0x7a,0x54,0x7e,0x94,0x58, + 0x84,0x27,0x98,0xea,0xfb,0x41,0x7d,0x4a,0xfd,0xd7,0x11,0xd8,0xa8,0x3b,0xde,0xa2, + 0x84,0x14,0x33,0xc3,0x9f,0x26,0x2c,0xeb,0xa5,0xcf,0x73,0xfb,0x2b,0xcc,0x81,0x41, + 0x30,0xe4,0x45,0x20,0x71,0x4d,0xfe,0x8f,0x3e,0xbf,0xdb,0x1a,0xfd,0xda,0x3c,0xc2, + 0xdd,0x3e,0x99,0x5d,0x05,0xc3,0x9e,0x83,0x21,0x1e,0x11,0xb3,0xcc,0x67,0xef,0x0a, + 0xa5,0x2c,0xf3,0x8c,0x68,0x8e,0x7f,0x9d,0xb2,0x0f,0xcf,0x2e,0x83,0x7f,0x69,0x96, + 0x4f,0x69,0x3c,0xec,0x95,0x15,0xe0,0x69,0x18,0x1e,0x03,0xf6,0x9c,0x92,0x02,0xac, + 0x32,0x3d,0xab,0xf9,0xf1,0x6b,0xf2,0x7f,0x82,0x95,0xda,0xe2,0x0d,0x05,0x67,0xd8, + 0x87,0x68,0xe6,0x5b,0x6f,0xe0,0xf5,0xef,0xd5,0x8f,0x6a,0x4b,0x36,0x8a,0x33,0x7c, + 0x07,0x1a,0xdd,0x5e,0xdb,0x53,0x82,0x29,0xfe,0x05,0x77,0xa0,0xd1,0xe4,0x6c,0xa0, + 0x4f,0x7f,0xe3,0x0c,0xe1,0xfe,0x07,0xda,0xee,0x41,0xfd,0x8b,0x88,0x48,0xde,0xdc, + 0x8a,0xfb,0x67,0xb0,0xc3,0x2b,0x6f,0x16,0x53,0xf2,0x7f,0x14,0x9c,0x56,0xeb,0x08, + 0xba,0x87,0xf0,0x35,0x9d,0x5a,0xde,0x20,0xa9,0x84,0xdd,0xa2,0x51,0xaf,0x34,0x24, + 0xb4,0x50,0x3b,0xf7,0xff,0xac,0x36,0xcb,0x1f,0xb4,0x47,0x4a,0xb8,0x90,0x79,0xcc, + 0x70,0x04,0xe5,0x9d,0x20,0xb9,0xb0,0x9d,0xfb,0x7f,0x72,0xc9,0x2a,0x85,0x3b,0x82, + 0x6e,0x9c,0x63,0xc6,0x3f,0x99,0x3e,0x1a,0x11,0x78,0xb4,0x0b,0x85,0xd8,0xb0,0x11, + 0xf6,0x92,0x5d,0x1c,0x11,0xc5,0xf0,0x5e,0xc4,0x40,0xbc,0xf2,0x3a,0x53,0xfc,0xeb, + 0x3c,0xfd,0x5c,0x58,0xc0,0x9d,0x3c,0x9f,0x1b,0xfe,0x9f,0x59,0x5c,0xad,0xff,0x94, + 0x87,0xe9,0x37,0x89,0xff,0xcd,0xa8,0xff,0xc2,0x9f,0x66,0x5c,0x93,0xff,0x53,0xaa, + 0xdd,0x75,0xac,0xe0,0x7c,0xd7,0x01,0x7c,0x11,0x3a,0x58,0x73,0x09,0xa7,0xb9,0x35, + 0xdb,0xef,0xc5,0x39,0xda,0x61,0xab,0xdb,0xb3,0xe2,0x4d,0x30,0xe7,0x3f,0x0f,0x43, + 0x0f,0x8a,0x59,0x8a,0xda,0x9c,0x75,0x21,0x0c,0xa3,0xcc,0x1e,0x85,0x1e,0xbb,0x1d, + 0x6c,0xab,0xc9,0x16,0x0f,0x47,0x44,0x74,0xd5,0x3d,0x59,0xe6,0xfc,0x9f,0x8c,0xdd, + 0x92,0xea,0x93,0x27,0x93,0xe6,0x50,0x23,0xac,0xa8,0x2b,0xcf,0x23,0xfd,0x12,0x5e, + 0xc1,0xf7,0xb5,0x4b,0x6c,0x0b,0x55,0x35,0x9a,0x6d,0x49,0x89,0x7f,0x29,0xbb,0x05, + 0x7b,0x5d,0x2b,0x8a,0x1d,0xc4,0x4b,0x3c,0x11,0xc8,0xf3,0x81,0xb6,0x9b,0xd9,0x35, + 0x94,0x3f,0xdb,0xb4,0xe7,0x61,0x99,0x97,0x06,0x67,0x98,0xe2,0x5f,0x53,0xfe,0xac, + 0x9d,0x6d,0x74,0x35,0xcc,0xda,0x2c,0x3e,0xc7,0xb3,0xd9,0x79,0xfe,0xf3,0x07,0xd2, + 0x59,0xe8,0xd6,0x96,0x04,0xe5,0xe9,0x8e,0x0f,0xa3,0x6e,0x6d,0xf1,0x53,0x93,0x1c, + 0x66,0xfc,0x83,0x68,0x67,0xbf,0x76,0xd7,0xa6,0x9a,0x21,0x3f,0xcf,0x5e,0x58,0x82, + 0x68,0xd0,0xc8,0x07,0xbb,0x4e,0x11,0x5f,0x87,0xb7,0x42,0xfb,0x86,0x6d,0x93,0x53, + 0xf2,0x7f,0xb6,0x48,0x91,0x8c,0xca,0xfc,0xb5,0xcd,0x62,0xbe,0x91,0x6d,0x6e,0xe3, + 0xfb,0x6d,0x2c,0xc8,0x97,0xdd,0x88,0x48,0x56,0xce,0x41,0xf9,0x6c,0x31,0xfb,0x7f, + 0x94,0x75,0x74,0x16,0x0b,0x9c,0x22,0xe5,0xd0,0x2a,0x94,0xb0,0xef,0x9e,0xb6,0x0f, + 0xab,0xfb,0x63,0xf1,0xaf,0xdb,0xb4,0xbb,0xbf,0x59,0xc2,0xe4,0x68,0xba,0xd9,0xff, + 0x53,0xab,0x6d,0x00,0x67,0x14,0x66,0x93,0x19,0x4a,0x93,0x80,0x62,0xca,0x81,0x68, + 0xd9,0x90,0xcf,0x53,0xc9,0x37,0xd2,0x9e,0x6c,0x76,0x46,0x17,0xe5,0xa6,0xf8,0x7f, + 0xca,0xa4,0x4d,0xc2,0x2c,0xaf,0xa3,0x3c,0x6b,0x32,0x1e,0xcd,0xe2,0xde,0x85,0xde, + 0xec,0x93,0xc0,0xcb,0xc0,0xe5,0xe5,0xe4,0x3f,0xd3,0x55,0x5a,0x71,0xa3,0xec,0x25, + 0xf5,0xa6,0xfc,0xe7,0xeb,0xf0,0xd8,0x2e,0x88,0x5a,0x97,0x8a,0x65,0x06,0xec,0x91, + 0x57,0x8a,0xef,0x4a,0x57,0x79,0xda,0xf3,0x09,0xf9,0x61,0x72,0xbc,0x69,0xc1,0x69, + 0x1c,0x14,0x99,0xf1,0x4f,0xfa,0x47,0x78,0x6c,0x51,0x08,0x0f,0x73,0xfd,0xde,0x67, + 0xa8,0xb9,0xdd,0x3c,0x1f,0x26,0x5a,0xd0,0xc3,0x5d,0xcd,0x75,0x4b,0x06,0x4d,0xf5, + 0x5f,0x90,0xf6,0x07,0x38,0xd1,0x5c,0x31,0x64,0xfd,0x50,0x3c,0x03,0x47,0x83,0x95, + 0xa7,0x9d,0x46,0xfd,0x72,0x33,0xda,0xef,0x27,0xc4,0x32,0x76,0x95,0x55,0xf9,0xac, + 0x1f,0x0a,0x66,0xfc,0xb3,0xb9,0xa3,0xf9,0x5c,0xf1,0x30,0xfd,0x0e,0x39,0x16,0xf9, + 0x23,0x38,0x87,0x2c,0x5e,0x5e,0xff,0x25,0xe4,0xf7,0xcb,0x77,0x92,0x5c,0xf5,0x25, + 0xa1,0x18,0x32,0x7f,0x90,0x6d,0xc6,0x3f,0x3b,0xa5,0xd5,0x6e,0x14,0x53,0x5a,0xfa, + 0xf1,0xc6,0x35,0xf0,0xc0,0x6b,0x34,0x16,0xe6,0x43,0xfc,0x73,0x0f,0x51,0x9e,0x7c, + 0x59,0x29,0x5e,0x4d,0x3d,0x59,0x60,0xc2,0x3f,0xb5,0xe0,0xf7,0x38,0x75,0x9a,0x99, + 0x1e,0x0d,0xa2,0xbe,0xe3,0x34,0x02,0x87,0xd5,0x1d,0x5c,0xfe,0xa8,0xc4,0xb2,0xa1, + 0xdb,0xe5,0x74,0x65,0x38,0x08,0x4d,0xec,0xcf,0x6d,0x53,0x56,0x41,0x9f,0xaf,0xc2, + 0x6f,0x0d,0xda,0x3f,0x60,0x87,0x50,0x1e,0x5a,0x7b,0x0c,0x7f,0x17,0xda,0x8f,0xc1, + 0x82,0xaf,0x4b,0xe3,0xac,0xf2,0xbc,0xb5,0xbd,0xa0,0xc8,0x84,0x7f,0x3e,0x81,0x61, + 0x5a,0xd9,0x37,0x2b,0x38,0x29,0x1a,0xcb,0xff,0x09,0x8a,0x23,0xda,0x38,0x33,0xea, + 0x91,0x3f,0xc9,0xdd,0x5d,0x9d,0xc5,0x6c,0xbf,0xd8,0x6a,0xce,0xff,0x19,0x55,0x3f, + 0x15,0x4a,0xf5,0x80,0x17,0x2f,0x1a,0xfa,0x6e,0x74,0x2b,0x9e,0x2f,0xf8,0xb9,0x6e, + 0x53,0x44,0x17,0x9c,0x97,0x4a,0xf9,0x7f,0xc8,0x84,0x7f,0xe0,0x7b,0x52,0xab,0xd7, + 0xae,0xd3,0xcd,0x4d,0x45,0xc0,0xe3,0x17,0x8b,0xf6,0xf9,0x71,0xfd,0x1b,0x1f,0xd4, + 0xe5,0xcd,0xd9,0x05,0xd0,0xb3,0x05,0x0f,0xc2,0xda,0x26,0x53,0xfc,0x4b,0x28,0xf4, + 0x75,0xc1,0x32,0xee,0xfd,0x78,0x96,0xfb,0x7f,0xb8,0xbf,0x7d,0x44,0xdb,0xdb,0x68, + 0x0c,0xfe,0x21,0xe3,0x45,0x3c,0x38,0x37,0x76,0xa5,0x9b,0xf1,0x8f,0x13,0x98,0xba, + 0x6c,0x78,0xa1,0xe2,0xaf,0x03,0x5c,0x9f,0x08,0xa2,0x41,0x84,0xd9,0x5c,0xdf,0x81, + 0x1f,0x84,0x30,0x84,0xe0,0x46,0x65,0xb5,0x3f,0xc1,0xbf,0xc1,0xfd,0x3f,0x1f,0x11, + 0xb7,0x9e,0xe5,0x47,0xb3,0xeb,0x63,0x58,0x30,0xc0,0xdf,0x17,0xc6,0xef,0x29,0xd1, + 0x97,0xf8,0xe5,0x42,0xf8,0x90,0xe7,0x57,0xac,0x31,0xe3,0x9f,0x9b,0x46,0xe1,0x4a, + 0x35,0xaa,0x2d,0x26,0xec,0xe6,0xfa,0xeb,0x04,0xee,0x96,0x4b,0xf4,0xbc,0x5a,0xc5, + 0x33,0xa8,0xb9,0xff,0x67,0x01,0x2c,0xf1,0x8b,0x0e,0x13,0xfe,0xb9,0x42,0x0e,0xc3, + 0xdc,0xa8,0x6d,0x18,0x61,0xd2,0x5f,0xf8,0x6e,0x19,0x45,0xf9,0xc3,0x81,0x90,0x6d, + 0x0c,0x81,0xd0,0x49,0x4e,0x0d,0x74,0x02,0x7f,0x4a,0xe2,0x9f,0x91,0x50,0x0b,0x8a, + 0x1c,0xb9,0x0b,0x8d,0xb0,0x36,0x56,0xe2,0x0b,0xf4,0x20,0xcc,0x42,0x45,0xcf,0x57, + 0x20,0x8a,0x50,0x10,0xa1,0x72,0x30,0x25,0xff,0x79,0x80,0xf9,0xfd,0x2a,0x8f,0x06, + 0xd6,0xa1,0xd9,0xef,0xd4,0x1c,0xdc,0xac,0xd8,0x4a,0x0c,0x3c,0xac,0x43,0x90,0xcf, + 0x57,0x88,0xc7,0x14,0xff,0x42,0xd8,0xc9,0x66,0xe8,0x72,0x07,0x71,0x6a,0xdc,0xdb, + 0x1c,0x08,0xc3,0x08,0x69,0x83,0x07,0x7b,0x51,0x7f,0x45,0x0d,0x8b,0x0f,0xef,0x9f, + 0xcc,0xff,0xd1,0x26,0xc7,0xb3,0x91,0x9d,0xe2,0xf7,0x70,0x7d,0x2a,0xfa,0x79,0x7e, + 0x94,0xf4,0xb1,0x60,0x04,0x46,0xd1,0x34,0x63,0xdd,0xb5,0x4e,0x41,0xf4,0xa6,0xe0, + 0x1f,0x1e,0xed,0xb2,0xe9,0x1c,0xf6,0x00,0xbe,0x26,0xcf,0x4f,0x8e,0xe7,0x47,0x7d, + 0xa1,0x5d,0x0e,0x56,0xf9,0x6c,0x91,0xd4,0xfa,0x77,0xe1,0x9c,0x8a,0xbb,0x6b,0x6b, + 0xec,0x3c,0x9e,0xb6,0x85,0x73,0xac,0x4a,0x3c,0x1f,0xef,0x8c,0x8a,0x1b,0xcf,0x67, + 0x6d,0x6c,0x72,0xa5,0xf8,0x7f,0xf6,0xd6,0x72,0xf4,0x2b,0x2e,0xd1,0x70,0xff,0x0c, + 0x66,0x8e,0xa2,0xa2,0x8f,0xe7,0x6f,0x9f,0x81,0xdd,0xac,0x64,0x39,0x0d,0xa4,0xe0, + 0x9f,0x15,0xb0,0x43,0x73,0xf6,0xca,0x4e,0xd2,0x17,0x5f,0x16,0xcb,0xda,0x78,0xe2, + 0x0a,0xf9,0x10,0x5e,0x28,0x2c,0x09,0x3a,0x5c,0x96,0xd4,0xfa,0xf7,0x5d,0x41,0x5e, + 0xfd,0x4d,0xbc,0x1c,0x0f,0x0c,0x5d,0xcf,0xf9,0x70,0x76,0xc5,0xe2,0x41,0x6f,0x0b, + 0x2f,0x37,0x17,0x87,0xe8,0xca,0xf4,0x3c,0x93,0xff,0x87,0xa7,0xc1,0x54,0xbc,0x66, + 0x2b,0x14,0x7b,0x7d,0xef,0xf3,0xea,0x51,0x97,0xb8,0x16,0x3e,0x0b,0x97,0x23,0xfe, + 0x29,0x88,0xb0,0x73,0xac,0xa2,0x45,0x0a,0x8b,0xd9,0x66,0xfc,0x03,0x57,0x85,0xaa, + 0x5e,0x9b,0x2a,0x0e,0xe2,0xb2,0x2c,0xa8,0xc6,0xd7,0xfc,0x29,0x5c,0x24,0x86,0x7f, + 0x6c,0x0c,0x2e,0xb8,0xaa,0x98,0x6d,0xf7,0x35,0xfe,0x1f,0x9e,0x16,0x85,0xf3,0x83, + 0xf8,0x21,0x2a,0xb4,0x8c,0x1e,0xb9,0x78,0xc2,0x5f,0x1d,0xfb,0x34,0x0f,0x74,0x5d, + 0x53,0xff,0xbe,0x4b,0xda,0xc0,0x93,0x7c,0x14,0xfa,0xb7,0x50,0xcc,0xf1,0xcf,0xaf, + 0xd9,0x2e,0xb4,0x1f,0x33,0x78,0x21,0xea,0x1a,0x1e,0x58,0x8f,0xa6,0xe4,0x3f,0x4f, + 0x83,0x1d,0xcd,0xf9,0xd1,0x45,0xf5,0xe9,0x1b,0x11,0xef,0x4d,0x5f,0x96,0x71,0x5b, + 0x36,0x4f,0x04,0x9a,0x7e,0xaa,0x8d,0x27,0x3e,0xad,0x61,0x33,0xa3,0x19,0xa9,0xf8, + 0x87,0x9f,0x26,0x95,0x8b,0x71,0x50,0xf0,0x7c,0x45,0x39,0xde,0x36,0xec,0xaf,0xeb, + 0x5d,0xe4,0x93,0xb5,0x4d,0x50,0xaf,0xd3,0x42,0xbf,0x19,0xff,0x74,0xc1,0x15,0x2b, + 0x1e,0x22,0x9f,0xd8,0x0e,0x07,0xa1,0x32,0x14,0xcf,0xff,0xa9,0x6c,0xb4,0x85,0xc4, + 0x0f,0xc9,0x41,0x6d,0x4f,0x10,0xaf,0x98,0xf1,0x4f,0x14,0x46,0x11,0x61,0xd8,0x9a, + 0x0a,0x0c,0xfe,0x1f,0xc5,0xc6,0x6a,0x26,0xea,0xdf,0xc5,0xa8,0x34,0x46,0x67,0x10, + 0xdc,0x5a,0xd7,0xf8,0x7f,0x78,0xda,0x73,0x7b,0xac,0xda,0xcb,0x8b,0xfa,0xb1,0xdf, + 0x50,0x94,0xdc,0x0d,0xa2,0xb5,0xb0,0x79,0xf7,0x5f,0xc3,0xff,0xb3,0x1c,0x76,0xfb, + 0xec,0xd5,0xf2,0x66,0x52,0xa8,0xbe,0x85,0xf8,0xc4,0xc2,0xdd,0x0e,0xcf,0xc7,0xfc, + 0x0f,0x1f,0x40,0x8b,0xd7,0xde,0x40,0x37,0x9b,0xeb,0xbf,0x04,0x5e,0x1d,0x66,0xd7, + 0x16,0x6d,0x68,0x2d,0x54,0x9e,0xc4,0x69,0x0b,0x83,0x9e,0x21,0xda,0x02,0x59,0x31, + 0xff,0xcf,0x33,0x30,0xb3,0x96,0x9e,0x4c,0xf1,0xff,0xa4,0xc5,0xb2,0x7f,0x79,0x7c, + 0x67,0x03,0xc7,0xdb,0xdc,0x0d,0xb2,0x45,0xe3,0xf9,0xcf,0xd9,0x7f,0x84,0x67,0xf4, + 0xfc,0x06,0x7a,0x6f,0x4a,0xfd,0x97,0x6f,0x22,0xdb,0x96,0xe7,0x9f,0x4c,0x8b,0x85, + 0xbd,0x62,0xfe,0x07,0x51,0xc7,0x07,0x29,0x07,0xab,0x6e,0xf6,0xff,0xdc,0x34,0x84, + 0xe8,0xc5,0xa8,0x76,0xff,0x1c,0x7e,0xcc,0xd3,0xea,0x12,0x81,0xb0,0x89,0xc2,0xff, + 0x7f,0x4c,0xe1,0xff,0x49,0x1b,0x82,0xc3,0xd4,0x08,0x93,0xcd,0x81,0x4f,0xa4,0x05, + 0x88,0x1f,0x5e,0x1d,0x92,0xc6,0x73,0x8d,0xf9,0xe7,0xb5,0x07,0xa4,0x52,0x2d,0x73, + 0x30,0x85,0xff,0x27,0x1a,0x38,0xa1,0x95,0x80,0x1c,0x12,0x7f,0x00,0x11,0x52,0x02, + 0x99,0xcd,0xd9,0xa7,0xb4,0x1e,0x04,0x42,0x32,0x43,0x79,0xd2,0xa3,0xda,0x29,0xf5, + 0x5b,0x52,0xf0,0x8f,0xda,0x18,0xab,0x76,0x4f,0x83,0x2d,0x46,0x9a,0xb7,0xa7,0x3f, + 0xb4,0x5d,0x75,0xc6,0xe2,0x5f,0x5b,0x2c,0x3e,0x4f,0x06,0xaf,0x7f,0x4f,0xe2,0x9f, + 0xe6,0xdc,0x5f,0xf9,0x8c,0xd5,0x5e,0xae,0xb5,0x90,0x12,0x6d,0x51,0x10,0x92,0xf9, + 0xe4,0x94,0x67,0x04,0xf1,0x7c,0x72,0x73,0xfd,0x17,0x1c,0x90,0x78,0x1a,0x8f,0xf8, + 0x75,0x94,0xc6,0x25,0x3e,0x5b,0xa2,0xfe,0x9d,0x0f,0x78,0xc6,0x3b,0xda,0x0b,0xd7, + 0xe0,0x1f,0xce,0xff,0xb3,0xa1,0xe9,0x75,0x15,0xf1,0xf0,0xc3,0x19,0x89,0xfa,0xf7, + 0x98,0xff,0x87,0x0f,0x9a,0x52,0xfd,0x3f,0x63,0x3e,0x23,0xc8,0x98,0x0f,0x0e,0x5c, + 0xf6,0x4c,0x5c,0x7f,0x25,0x02,0xc6,0x95,0xa8,0xce,0x03,0xaf,0x68,0x11,0x9b,0xf3, + 0x9f,0x1d,0xb0,0x5f,0x42,0xb4,0x33,0xec,0x2f,0x87,0x3d,0x50,0x1c,0xe6,0xf9,0x6a, + 0x84,0x07,0xc2,0x16,0x85,0xc8,0x05,0x58,0x17,0x28,0x68,0x76,0x0c,0xa7,0xc4,0xbf, + 0x38,0xff,0x46,0xa1,0xbe,0xa8,0x70,0x61,0x06,0x97,0xcf,0xb5,0x8d,0xae,0x74,0x1e, + 0x98,0x30,0xea,0x53,0x0e,0xc3,0x56,0xb5,0xe4,0x38,0xdd,0x46,0xcc,0xf9,0xcf,0x53, + 0xb5,0x5d,0x2c,0x9f,0x47,0xab,0xbd,0x3c,0x30,0x04,0x79,0x0d,0xe4,0x5d,0x6d,0x8d, + 0xc2,0x03,0xd9,0xe4,0x0f,0xb0,0x4a,0x9a,0xae,0x21,0x42,0x70,0x98,0xf0,0xcf,0xb4, + 0xd0,0x97,0xb1,0x6c,0xe7,0x69,0xf0,0x67,0xb6,0xc0,0x97,0xb9,0x52,0xbc,0xa2,0xbe, + 0x11,0xbb,0xf2,0x36,0xf9,0x94,0x55,0x85,0x50,0xbf,0xa4,0xe4,0x3f,0xb3,0xcf,0x24, + 0x43,0x7a,0x84,0xb8,0x18,0xd1,0x0c,0x31,0x72,0x95,0xc5,0xe4,0x49,0xee,0x05,0x61, + 0x1e,0x5f,0x28,0x73,0xfd,0xd7,0xa7,0xda,0x55,0x36,0x97,0xa7,0x15,0xed,0x21,0x6f, + 0xa0,0x21,0x5f,0x1c,0xcb,0x7f,0xae,0x8a,0xe5,0x3f,0xbf,0x87,0x86,0xfc,0x92,0x71, + 0xd1,0x9c,0xff,0xfc,0x74,0xf3,0xae,0xc9,0x88,0x5e,0x7e,0xda,0xad,0xa0,0xfd,0x75, + 0xab,0x27,0xe3,0x7f,0x88,0x9b,0x61,0x07,0x67,0x04,0x7a,0x94,0x9c,0x00,0x7f,0xf0, + 0xb6,0x88,0xbc,0x94,0xa4,0xe4,0x3f,0x33,0x03,0xed,0x3c,0x4c,0xda,0x79,0x21,0xbc, + 0x46,0x63,0xf9,0x4e,0x0f,0xf0,0x2b,0x27,0x10,0x01,0xce,0xd4,0x70,0x60,0xf6,0xff, + 0xf0,0x6c,0x1f,0xe0,0xd5,0xdf,0x80,0xf6,0x57,0xa1,0x4f,0xe0,0xf2,0x67,0x6f,0xcc, + 0xff,0x33,0x0c,0xad,0x9c,0x48,0x61,0xaa,0xdf,0x9c,0xff,0xbc,0x0f,0xbf,0x7e,0x36, + 0x2f,0xf2,0x62,0x9c,0xe6,0x48,0x43,0xfd,0xc5,0xf9,0x58,0xf8,0xfb,0x7e,0x6b,0x44, + 0x7a,0x87,0x2b,0x9a,0xee,0x94,0x7c,0xa4,0x11,0x3a,0x5e,0xcd,0x2f,0x72,0xb7,0x0f, + 0x4f,0x1b,0x4b,0x16,0xc2,0xe3,0x41,0x1b,0xd3,0x2a,0x19,0xae,0x8f,0xb9,0xfe,0xeb, + 0x12,0x7c,0x49,0x11,0xe4,0x8c,0xd9,0x54,0xae,0xe6,0x34,0x2b,0x2f,0x02,0xe7,0xfe, + 0x9f,0xac,0x51,0x3c,0x5f,0x87,0x95,0x52,0xc5,0x3a,0x96,0xea,0xff,0x51,0xf6,0xf6, + 0xdb,0x75,0x79,0x81,0xc5,0xce,0xde,0xc1,0xfd,0xe0,0x30,0xf2,0x9f,0x8d,0xfa,0x1d, + 0xf2,0x81,0x1a,0xa8,0xb3,0x4f,0xa6,0xed,0xc4,0xe4,0xff,0x11,0x9c,0x88,0x8e,0xec, + 0x5c,0x3b,0xdb,0xb9,0x9a,0xf3,0x5a,0xc2,0xd9,0x03,0xb4,0x2d,0x96,0x38,0x1d,0x85, + 0x16,0xb0,0x07,0x69,0xb7,0x3f,0xd5,0xff,0xb3,0x5d,0xf0,0xf5,0xca,0x2e,0xbf,0x4a, + 0x1e,0x47,0x1d,0x6f,0x71,0xdb,0x07,0x94,0xad,0x79,0xb8,0x03,0xdd,0x44,0x27,0x2c, + 0x23,0xc4,0xae,0xf1,0xff,0xfc,0x24,0xc6,0x06,0xd0,0x4d,0x54,0xe3,0x35,0xb3,0xc2, + 0x3c,0x7f,0x5b,0x75,0xf3,0x81,0x0e,0x07,0x34,0x37,0x58,0xbb,0x9b,0xcc,0xf8,0xe7, + 0x52,0xed,0x97,0x1c,0xe6,0x85,0x63,0xfa,0x5d,0x2b,0xde,0xc9,0xf3,0x7b,0x39,0xfe, + 0x39,0x8f,0x57,0xc6,0x1c,0x55,0x80,0xf2,0xc7,0xe4,0xff,0x99,0x72,0x05,0x61,0xf9, + 0xdc,0x83,0x59,0x67,0xc5,0x8a,0xf0,0x49,0xa8,0x2a,0xb4,0x1e,0x10,0xdd,0xd2,0x61, + 0x8e,0x9f,0x7b,0x6a,0xce,0xc1,0x97,0x6c,0xae,0x8a,0x78,0xc0,0xec,0xff,0xf9,0x94, + 0xb4,0xb1,0x82,0xb3,0xf4,0x2c,0x59,0x20,0x05,0x06,0x9d,0x94,0x6e,0xc4,0x07,0x6b, + 0x34,0xe2,0x5f,0xf6,0xd3,0xbc,0x50,0x4e,0x45,0xe0,0x67,0xf6,0xff,0x8c,0xd0,0x17, + 0x49,0x21,0x8f,0x87,0xe2,0x41,0x33,0xc0,0x1f,0x81,0xae,0x46,0x87,0x11,0x8f,0x78, + 0x3d,0x63,0x2f,0x14,0x82,0x0c,0xc4,0x1c,0xff,0xfa,0xad,0xf4,0x22,0x2c,0xc3,0xf9, + 0xca,0x0a,0x78,0x9e,0xa2,0x7d,0x17,0xc6,0xfb,0xb7,0x18,0xf1,0xc4,0xec,0x68,0xf5, + 0x5e,0xb0,0xe7,0xa3,0xa0,0x33,0xf9,0x7f,0xd2,0xfe,0xa2,0xbe,0x8a,0x5f,0x67,0x71, + 0x98,0xac,0xc8,0xc5,0xaf,0x5f,0xeb,0x64,0x93,0x66,0x90,0x88,0x62,0xc4,0x5f,0x3e, + 0x82,0xf1,0xf4,0xb2,0x3a,0xdb,0xf3,0xd7,0xf8,0x7f,0xde,0x0d,0x2d,0xd0,0x8b,0x47, + 0x17,0xe1,0x00,0x66,0xf9,0x6c,0x83,0xb7,0x7c,0xa1,0x5d,0x62,0x06,0x11,0xd0,0x18, + 0xbc,0x17,0x42,0x89,0x3d,0x66,0xae,0xff,0x82,0x90,0xf6,0xb1,0x64,0xac,0xf6,0x00, + 0x6a,0x43,0x44,0x3b,0x21,0x71,0x06,0xd7,0x08,0xb1,0x7c,0xfb,0x0f,0xa1,0x8c,0x5d, + 0x93,0xff,0x63,0x85,0x36,0xbd,0xe0,0x04,0x8c,0xda,0x2b,0x78,0xfc,0xf4,0x11,0xda, + 0xd3,0xfa,0x75,0xad,0xa7,0xc1,0x88,0x87,0x7e,0x08,0x3b,0xa6,0x76,0xf8,0xe5,0xb0, + 0xdf,0x1c,0xff,0xba,0xdb,0x55,0xc0,0xd4,0x13,0x16,0x0e,0x7b,0xd0,0x30,0xe7,0x81, + 0x45,0x07,0x27,0x46,0x30,0xf0,0xa1,0xba,0x15,0x0a,0x43,0x87,0xe8,0x75,0x63,0x29, + 0xfe,0x9f,0xf5,0x83,0xea,0x70,0xdd,0x4a,0xfb,0x3a,0xd6,0xcc,0x10,0xed,0x9c,0x20, + 0x37,0x70,0x89,0xc4,0xeb,0xa1,0xfe,0xa0,0xbd,0xcc,0xf2,0x43,0xf2,0xdf,0xa5,0x9f, + 0x30,0xf3,0xff,0xc0,0xfb,0x81,0xf0,0x70,0x56,0x58,0x5e,0x07,0xaf,0xaa,0x15,0x9d, + 0xd6,0x7c,0x91,0x6a,0x9f,0x81,0x4b,0xff,0xfb,0xf9,0x35,0x03,0xf0,0x3e,0xcc,0xd1, + 0x6c,0xf9,0x29,0xf1,0xaf,0xcd,0x70,0x59,0x99,0xdf,0x6f,0x1b,0x2d,0x58,0x80,0x66, + 0x02,0xc2,0x80,0x87,0xc4,0x31,0x9e,0x61,0x68,0xc4,0x07,0xd5,0xbd,0xbc,0xb4,0xe7, + 0x54,0x4e,0x2a,0xfe,0xf9,0xbd,0xdf,0x75,0x6c,0x6d,0x58,0x7c,0x40,0x7f,0x12,0xf7, + 0xe7,0xcd,0x8c,0x13,0x31,0x19,0xe7,0x31,0xe7,0xfd,0x19,0x87,0xa0,0x2c,0x72,0xf3, + 0xda,0xa6,0x6b,0xfc,0x3f,0x90,0x7f,0xc2,0x31,0xc7,0x3f,0x15,0x9e,0x45,0xfc,0x93, + 0x85,0xf6,0x17,0x5e,0x31,0xe4,0xe7,0x71,0x58,0x23,0xbd,0xa4,0xa3,0xfd,0x68,0xc6, + 0x3f,0xfb,0xe1,0x9f,0xd9,0x96,0x61,0xcb,0x4a,0x72,0x77,0x23,0x87,0x79,0x87,0xea, + 0x11,0xf6,0xac,0x66,0x46,0xda,0xcf,0x15,0x8e,0x88,0x46,0xe4,0x8b,0xd9,0x29,0xf8, + 0x47,0x6a,0xd2,0x54,0x7d,0x21,0xdf,0x6f,0x3c,0xfe,0x6e,0x84,0x11,0xfd,0x71,0xff, + 0xb3,0xd6,0xa4,0x17,0x9e,0x90,0xcb,0xaf,0x33,0xe3,0x9f,0x1e,0x78,0x57,0x73,0x31, + 0x6b,0xa8,0xa6,0x1e,0xde,0x55,0x2b,0x83,0x71,0xd8,0x63,0xe4,0xff,0x7c,0x04,0xaf, + 0x9f,0x78,0xb9,0xcb,0xf6,0x82,0x9c,0xe2,0xff,0x61,0x63,0xae,0x4a,0x25,0x2d,0x56, + 0x0f,0x5e,0x49,0xf0,0x7d,0xa3,0xea,0x25,0x1a,0xf3,0xff,0xc0,0x58,0xad,0x61,0xa1, + 0xa7,0xe0,0x1f,0x72,0x80,0x55,0x36,0x58,0x15,0xb9,0xd9,0x72,0x00,0xa6,0x69,0x8b, + 0x83,0xc2,0x19,0x76,0x40,0x99,0x20,0xba,0xd1,0x63,0xf2,0xdc,0x84,0x7f,0x6e,0x57, + 0x5a,0x58,0x49,0xfd,0x44,0xfe,0x49,0x43,0x71,0xbb,0xfd,0xcf,0xa4,0x45,0x7f,0x19, + 0x15,0x31,0xf9,0x24,0xf0,0xa1,0x6e,0xd7,0xdb,0x7a,0x4c,0xfc,0x63,0x79,0x69,0x85, + 0xa4,0x65,0xf2,0x0c,0xcd,0xc1,0x69,0x7f,0x5a,0x24,0x67,0x1d,0xee,0x87,0xe3,0xb0, + 0x0a,0x96,0xf1,0x0c,0xde,0x33,0x9c,0xb8,0xa6,0xfa,0xd0,0x46,0x4f,0x6a,0xfc,0x8b, + 0xe3,0x81,0x58,0xfe,0x0f,0x14,0x37,0x5c,0x7f,0x2f,0xf9,0x23,0xac,0xd2,0x0b,0x0d, + 0x60,0xc0,0x13,0xcf,0x7c,0x6d,0xae,0x14,0xfc,0x53,0x0f,0xbc,0xcc,0xca,0xca,0x08, + 0x0f,0xc4,0x54,0x02,0x45,0xd8,0x03,0x03,0x88,0x88,0x26,0xb1,0x1c,0x9e,0x88,0xbb, + 0xe7,0x9a,0xf8,0xd7,0x4d,0xc7,0xc9,0x65,0x14,0x83,0xb6,0x4d,0x05,0x1f,0x50,0x0e, + 0x84,0xe2,0x7c,0x38,0xc6,0x6b,0xf6,0x53,0xce,0x08,0xb4,0x5e,0x29,0x30,0xe3,0x9f, + 0x93,0xf0,0x27,0x61,0xee,0x9d,0xce,0xc7,0xc5,0xe5,0x08,0x0b,0x67,0x79,0xad,0x6f, + 0x22,0x70,0x3a,0xac,0x95,0x6a,0x03,0xfc,0x1f,0x5e,0x36,0x1c,0x29,0x62,0x6a,0xfd, + 0x57,0x80,0x27,0x0d,0xae,0x11,0xf3,0x23,0x5d,0x50,0x82,0x68,0x07,0xc5,0x2c,0xe3, + 0x66,0x11,0x5b,0x16,0xcd,0xeb,0x21,0x3c,0x22,0x46,0x8e,0x98,0xf8,0xc7,0x06,0x60, + 0xbb,0xa4,0x7e,0x13,0x85,0x6a,0x6d,0x7e,0x23,0xc2,0x3c,0x07,0xc2,0x1e,0x7f,0x93, + 0x6a,0xa4,0x3d,0x0f,0xa0,0x8d,0xc8,0x13,0x81,0x3c,0xa6,0xf8,0xd7,0xe4,0x67,0xc8, + 0xf3,0xbe,0x8e,0x58,0xf6,0xf8,0xf3,0x3c,0x91,0x23,0x48,0xfa,0xb9,0xfc,0xe1,0x19, + 0x41,0x1f,0xc0,0x6e,0xcd,0xae,0x1f,0x4a,0x89,0x7f,0x4d,0x79,0x43,0x1b,0xd7,0xdd, + 0xda,0xda,0xa0,0xb8,0x3c,0xef,0x40,0x61,0xa5,0x66,0x6d,0xe7,0x81,0x4e,0x7c,0x6c, + 0x67,0x50,0xfc,0xa0,0xf6,0xac,0xd6,0x5d,0x67,0x6b,0x6f,0x4a,0xa9,0xff,0x22,0x6f, + 0x19,0xfc,0x87,0xf2,0x10,0xfc,0x58,0xe7,0xf9,0x3f,0xa9,0xf8,0x67,0xff,0x42,0xbc, + 0x72,0x4d,0xfe,0xb3,0x54,0x4e,0xb2,0x40,0xd4,0x29,0xe2,0x6d,0x62,0x35,0xf2,0x7f, + 0x54,0x77,0x7c,0xbf,0x79,0x8d,0x81,0x39,0xfe,0x75,0x1b,0xa4,0x6b,0x05,0x41,0x1a, + 0xca,0xe6,0x34,0x56,0x36,0x1c,0x90,0xdb,0x60,0x9d,0xb6,0x85,0xc9,0xd1,0xec,0x61, + 0xba,0xbf,0xb9,0x23,0x2c,0x87,0x3c,0x29,0xf1,0x2f,0xd2,0x74,0x50,0x0d,0xc7,0x68, + 0xb2,0x24,0x2b,0x2f,0x7b,0xb7,0xb1,0x16,0x50,0x99,0xac,0x1a,0xf1,0xaf,0xd0,0xa8, + 0xec,0x4e,0xa9,0x7f,0xaf,0xe0,0xd1,0x1f,0x3f,0x87,0x01,0x08,0x0c,0x8a,0xbd,0xf4, + 0x27,0xf6,0x29,0xb0,0x86,0xe4,0x37,0xa2,0x45,0x73,0x02,0x5e,0x81,0xfc,0x3e,0x5e, + 0xff,0x9e,0xcc,0xff,0xa1,0xd3,0xd2,0xdf,0x60,0xae,0x50,0xd6,0xca,0xa6,0x77,0x03, + 0x5f,0x22,0xda,0x71,0x9e,0x90,0xe7,0x91,0xd7,0xd9,0xf6,0x90,0xad,0x5e,0xfc,0x83, + 0xfa,0xa5,0x7f,0x76,0xa7,0xed,0x07,0xf8,0xbe,0x13,0x7f,0xbc,0xfe,0xeb,0x2c,0xec, + 0x67,0xeb,0x5f,0x16,0x47,0x34,0xb4,0x37,0xd9,0x2c,0x9e,0x46,0x38,0x06,0x3f,0xc3, + 0xf3,0x58,0xf0,0x01,0xfb,0x0c,0x7f,0xc2,0xf7,0x35,0xe5,0xff,0xa4,0xbd,0x6d,0xa4, + 0x6d,0x3c,0x36,0xde,0x54,0xc9,0xd1,0xce,0x90,0x95,0xfb,0x7f,0x0e,0xac,0x72,0x77, + 0x5a,0x87,0x73,0xae,0xd4,0x7e,0xce,0x76,0x9c,0xb2,0xf6,0xa4,0xe0,0x9f,0xcd,0xb5, + 0x8d,0x4a,0x88,0x39,0xce,0x5a,0xac,0xd9,0x6b,0xc0,0xee,0xa0,0x5e,0x32,0x08,0xeb, + 0xba,0xf2,0x3b,0xa9,0x4f,0x3c,0x81,0x88,0x6e,0x4b,0x2d,0xfd,0x1f,0xa9,0xf8,0x87, + 0x87,0xe9,0x59,0xc6,0x43,0xe9,0x9b,0xb5,0x26,0x4e,0x83,0xe0,0xc5,0xf3,0xf5,0x84, + 0x3a,0x3d,0x90,0xe1,0x23,0xf7,0x0a,0xbb,0x94,0x02,0x9d,0xa6,0xe2,0x9f,0xc3,0x7a, + 0xa3,0x56,0xc8,0xa8,0x2b,0x7d,0x1b,0x3c,0xae,0xa9,0xe0,0x08,0xfa,0xa3,0xb4,0x1d, + 0x0a,0x59,0x86,0x4a,0xfa,0xd3,0x76,0x68,0x21,0x8d,0x66,0xa7,0xd4,0x7f,0x3d,0x06, + 0x07,0x6a,0xe7,0x30,0x34,0x93,0xf7,0xd1,0x77,0xd4,0x79,0xba,0x75,0xe7,0x37,0x46, + 0xe0,0x2d,0x14,0xe4,0xc5,0x21,0xf1,0x13,0xb8,0x18,0xc5,0xad,0xb5,0x29,0x25,0xfe, + 0xf5,0x09,0x8c,0x1f,0xe4,0xb4,0x00,0x84,0xd3,0x42,0xa2,0x7c,0x0e,0x8b,0x1f,0xd2, + 0x8f,0xb4,0x79,0x2c,0x2b,0x24,0x76,0xa9,0x17,0x39,0xbf,0x44,0xf8,0x1a,0xfc,0x73, + 0x18,0xba,0x19,0x4f,0x1b,0xce,0x7d,0xc3,0xca,0xeb,0xdf,0x0b,0x2a,0xe0,0x28,0x2d, + 0xe5,0x19,0x20,0x7b,0xd8,0x15,0xcb,0x5c,0x90,0xf5,0x14,0xfc,0xf3,0x8f,0xb0,0x85, + 0xd9,0x43,0x34,0x6c,0x77,0xc2,0x3b,0xc4,0x1e,0x76,0xf4,0x90,0x5b,0x68,0x60,0xd0, + 0xce,0xf7,0x83,0x83,0xee,0xa8,0x76,0xcf,0xe1,0x8c,0x5b,0x26,0xfc,0x53,0x62,0x6f, + 0xd1,0xff,0x61,0x2b,0x75,0x79,0x78,0xbc,0xac,0xb0,0x2e,0x63,0x03,0x99,0xce,0x5e, + 0xa4,0x46,0xbe,0x59,0x27,0x3c,0xaf,0xe1,0xc0,0x9f,0xe2,0xff,0x29,0x84,0x10,0xf8, + 0x82,0x06,0xfb,0xcd,0xe3,0xa0,0x0a,0x78,0x0c,0x71,0x57,0x41,0xc8,0xbf,0xa8,0xd0, + 0x43,0xa4,0xbd,0xb8,0x90,0x68,0xba,0x9a,0xf1,0xcf,0x0a,0x38,0xe0,0x75,0x0f,0x5a, + 0x47,0x73,0x7e,0xc3,0x69,0x67,0x16,0x5b,0x83,0x44,0xe2,0x40,0x91,0x19,0x34,0x8f, + 0x17,0xf0,0xd5,0xb8,0x21,0x96,0x90,0x3f,0x9d,0x37,0x9d,0x87,0xf3,0x50,0x15,0x98, + 0x85,0xda,0x2a,0x84,0x30,0x32,0x13,0x0d,0xb1,0x51,0x7a,0x52,0x59,0xc0,0x6c,0xa7, + 0x51,0x4d,0x5f,0x15,0x6e,0x03,0x5b,0x7f,0x0a,0xfe,0xf9,0x14,0xd1,0xf2,0xdc,0x50, + 0xd6,0x58,0xcd,0xdb,0x30,0x80,0x6a,0x0e,0x17,0x6a,0x4c,0xc5,0x8d,0xdf,0x9f,0xd5, + 0x23,0x5e,0x62,0x97,0xdd,0x55,0x0b,0xad,0x63,0xb2,0x2b,0x21,0x1f,0x18,0x7c,0x0a, + 0x7b,0x79,0x12,0x72,0x37,0xf9,0x14,0xde,0xf6,0xcf,0x3a,0x41,0xbf,0xf4,0x9f,0x22, + 0x81,0xfa,0x82,0x13,0xb8,0x50,0x57,0xb4,0xbd,0xca,0x83,0x75,0xb8,0xdf,0x5c,0x89, + 0xf5,0x77,0xa4,0x71,0xf4,0x1b,0x62,0x16,0x57,0xc7,0x41,0xd8,0x20,0x38,0x8f,0x19, + 0xf5,0x4d,0xad,0x4a,0xac,0xf0,0x0d,0x76,0xd8,0x1d,0x07,0x71,0x29,0xdc,0x89,0xf9, + 0x3a,0xea,0x53,0xbc,0x7f,0x3b,0x0d,0x67,0x7f,0x04,0x4f,0xa2,0xfc,0x09,0x84,0xc9, + 0x90,0xda,0x4a,0x79,0xc5,0x3d,0x2f,0x84,0x67,0x25,0xe1,0x8c,0xb0,0xc9,0xff,0x03, + 0xd2,0x36,0xeb,0xf6,0xba,0xb2,0xd1,0x2c,0x8e,0x76,0x22,0x81,0x4a,0xdd,0xc9,0xbf, + 0xfe,0x41,0xcd,0xdd,0x6b,0x24,0xce,0xed,0x0e,0x4d,0x8b,0x3a,0xc2,0xa2,0x92,0xd8, + 0xff,0x5b,0xc0,0x48,0xeb,0x0d,0x71,0xb4,0x23,0x5d,0xd1,0xb8,0x5a,0x47,0xb0,0x72, + 0x85,0xeb,0xeb,0xd1,0x82,0x11,0xb8,0x42,0x2b,0x39,0x30,0x1e,0x36,0xe9,0xdf,0x6d, + 0xca,0x78,0x34,0x96,0xcd,0xab,0xdd,0xa9,0xf2,0xf8,0x57,0x4d,0x3e,0x1c,0x24,0x2e, + 0xdd,0x28,0xc4,0x3b,0xe8,0x9d,0xd7,0x8e,0x83,0xb3,0x49,0xfc,0x73,0xbb,0x13,0xf6, + 0x6a,0x25,0x51,0x44,0x3b,0x07,0xe1,0xf9,0xc0,0x2c,0xfd,0xae,0x51,0xd2,0x85,0xfa, + 0xf7,0xbf,0xf6,0x1a,0x8e,0xa6,0x56,0x36,0x23,0x40,0x5d,0xe2,0xcb,0x49,0xfe,0xe7, + 0x5c,0xee,0x9f,0x29,0xe9,0x96,0x5d,0xe9,0x11,0x95,0xe9,0x4e,0x5e,0x7f,0x9a,0xc1, + 0x18,0x14,0xf6,0x52,0xbe,0x3e,0x8d,0x8d,0x25,0x0d,0x38,0x18,0x4d,0xd8,0xfb,0x3e, + 0x98,0xc6,0x10,0x06,0x84,0xd0,0x5a,0xb9,0x00,0xcf,0xb2,0xe2,0xa1,0x8c,0x47,0xd3, + 0x37,0x6a,0xcd,0xc1,0xe2,0xa8,0xe5,0x51,0xf2,0x2e,0x59,0x1d,0x9e,0xae,0xd2,0x47, + 0xf1,0x3f,0x34,0xf1,0x57,0x97,0x97,0x25,0xed,0x10,0x2a,0xfc,0xeb,0x6f,0x13,0x23, + 0xb5,0x7e,0x52,0xf9,0x5a,0xe6,0x9e,0x1a,0x07,0x59,0x18,0x44,0x44,0x3a,0x4f,0x1c, + 0x90,0xfa,0xfc,0x3f,0x89,0x38,0xe7,0x89,0xc7,0xd2,0x27,0xe6,0x6b,0x8b,0x0d,0xff, + 0x0f,0x4f,0xf2,0x19,0xc5,0xd5,0xa8,0x7a,0xcd,0x36,0xda,0x84,0x03,0x32,0x7f,0x70, + 0xfd,0x59,0x04,0xd2,0x57,0xa4,0x9f,0xf3,0x9f,0x82,0x64,0xe2,0x7d,0x11,0xdf,0xc2, + 0x67,0xcc,0x28,0xf2,0xaa,0x87,0x71,0xb5,0xec,0xb2,0xf5,0x65,0x31,0x4a,0x0f,0xc1, + 0x9e,0xf3,0xd6,0x30,0xf9,0x0b,0x3b,0x10,0xfb,0xa9,0x2f,0xb1,0xfe,0xc3,0xc2,0x66, + 0xee,0x3d,0x66,0x32,0xcf,0x76,0xde,0x65,0x29,0xee,0x43,0x6b,0x71,0x8c,0x3e,0x07, + 0x6a,0x24,0xb3,0x81,0x1c,0xee,0xe8,0x87,0x7c,0x90,0xcd,0xfc,0xcf,0x00,0x9c,0xed, + 0x79,0x7a,0x48,0x5e,0x79,0xc7,0xdb,0xf0,0x04,0x73,0x0e,0x67,0x3c,0x4a,0xfe,0x40, + 0xfc,0xac,0x78,0x98,0xae,0x4c,0x7f,0x97,0x06,0xf5,0xfc,0xd0,0x8d,0x2b,0xd1,0x34, + 0x9b,0x78,0x1e,0xee,0xff,0xe9,0x66,0x85,0x5d,0x72,0xf8,0xba,0x83,0xea,0x8e,0x3a, + 0xa7,0xde,0xe2,0x22,0x47,0x7c,0x1d,0x11,0x5e,0xd8,0x6b,0x1f,0x40,0xf4,0x1d,0xe2, + 0xf9,0x3f,0x6f,0x9b,0xea,0xbf,0xba,0xf0,0x35,0xe7,0x76,0xa1,0x74,0xfd,0x4f,0x8d, + 0x17,0x84,0x32,0x36,0x33,0x84,0x30,0xf8,0x48,0xff,0xcf,0x10,0x11,0xa1,0xbd,0xf6, + 0xb4,0x56,0xea,0x97,0x43,0xe2,0x1e,0x61,0xe2,0x79,0xea,0x14,0x15,0xc6,0x7a,0xb9, + 0xd2,0xcf,0x89,0x95,0x7d,0x19,0xfe,0x90,0xb1,0xc9,0xfb,0xe3,0xfe,0x1f,0xad,0x92, + 0x4c,0x62,0xe2,0xb1,0x64,0xfe,0xad,0xd2,0xa9,0xa0,0xbd,0xdf,0x30,0x29,0x28,0x4e, + 0x07,0xce,0x06,0x6c,0x53,0x20,0x1d,0xee,0xe4,0xf5,0x89,0x86,0xbe,0xd3,0x2a,0xeb, + 0x96,0x04,0x73,0x4c,0xf8,0xa7,0xb6,0x13,0x76,0xaf,0x2d,0xe1,0x41,0xab,0x42,0x69, + 0x2b,0x23,0x5a,0x5b,0xd0,0x33,0x03,0x15,0x31,0xcf,0x7f,0xce,0x1e,0x82,0x27,0xfb, + 0x1e,0xf4,0xb6,0x71,0xfe,0xe7,0x89,0x3f,0x23,0xff,0x27,0xbf,0x44,0xab,0x09,0xc2, + 0xf2,0xc2,0x16,0x6a,0xd4,0x2b,0x75,0xd6,0x6d,0xc7,0xf9,0x6d,0x38,0x9f,0xee,0x16, + 0x4a,0x8c,0x7c,0x95,0xd4,0xfc,0x43,0xc9,0xe9,0x95,0x73,0x8b,0x24,0x3a,0x13,0x42, + 0x3c,0xdb,0x67,0x15,0x6c,0xd7,0xc0,0x2b,0x2b,0x4a,0x3f,0x6c,0xd0,0xf0,0x27,0xb3, + 0xfd,0x55,0x3e,0xd5,0x37,0x51,0xe6,0xa6,0x2a,0x11,0x92,0x1d,0x23,0x02,0xe2,0x1e, + 0xa1,0x35,0xac,0x34,0x0a,0x17,0x84,0x12,0x58,0xc2,0x26,0x7d,0x9a,0x90,0x3f,0x3d, + 0x99,0x9d,0x08,0x5a,0xaa,0x0c,0xef,0x0d,0xda,0x6b,0x1c,0x08,0x2d,0xfa,0x6f,0xd2, + 0x27,0xda,0x7e,0xaf,0x51,0x08,0x7f,0xd9,0x33,0x17,0x07,0x93,0x3e,0x4d,0xc8,0x9f, + 0xf2,0xbf,0xe9,0xa4,0x9f,0xc3,0xfc,0x5a,0xba,0xa9,0xe6,0x3c,0x87,0x01,0x0b,0x79, + 0xda,0x33,0xc7,0x87,0x8b,0xac,0xdc,0x7f,0x75,0x19,0x4a,0xbf,0x63,0x1d,0x14,0x3f, + 0x4d,0xec,0x9f,0x3c,0x9e,0xff,0x0c,0x76,0xea,0x60,0xd9,0x51,0xda,0x23,0xcd,0xcb, + 0x93,0xfd,0x1b,0x01,0x02,0xde,0x8e,0xbc,0x4c,0x46,0x4e,0x79,0x7b,0xd4,0x0e,0x05, + 0x2d,0x88,0xd7,0x13,0xf2,0x44,0xe3,0xf9,0x4e,0xe0,0xe0,0x4a,0xa7,0x9f,0xbb,0x01, + 0x3d,0x72,0xae,0xe5,0x19,0x4e,0x04,0xe4,0xc9,0x33,0x88,0x10,0x23,0xaa,0x76,0x83, + 0x42,0x8e,0x25,0xf6,0x4f,0x9e,0xc4,0xb3,0xa7,0x78,0x91,0xbb,0x7d,0xc8,0x17,0xa7, + 0x3d,0x2c,0xa4,0x8d,0x3e,0x7b,0x3c,0xff,0x0a,0xec,0xd5,0x16,0x5e,0xff,0x3e,0x31, + 0x3f,0xc4,0xe7,0xd3,0x72,0x0d,0x9f,0xf6,0x8c,0x32,0x3e,0x58,0xc9,0xd1,0x5a,0xa7, + 0x7a,0x00,0x3a,0x34,0x89,0xcf,0x1f,0x97,0xec,0xf5,0x16,0x1e,0xca,0x99,0x98,0xff, + 0x11,0xaf,0xff,0x82,0xfd,0x75,0xeb,0x11,0x06,0x73,0x7e,0x1b,0x44,0x83,0x39,0x43, + 0x64,0x9c,0x55,0xc4,0xf2,0xc1,0xce,0x7a,0x2a,0x97,0x67,0x06,0xc5,0x0b,0x49,0x3c, + 0xc3,0xf9,0x36,0x95,0x79,0x0a,0xa7,0xfd,0x51,0xe2,0x6e,0xb7,0x7c,0x3d,0x52,0xed, + 0x16,0x16,0x1b,0xf9,0x3f,0xe0,0x56,0xad,0x66,0xfc,0x43,0x25,0x07,0x9c,0x01,0x83, + 0xf6,0xe7,0xa2,0x91,0xff,0x8c,0x6a,0xe8,0x57,0xf0,0xb6,0x60,0x67,0x16,0xbe,0x9f, + 0xf7,0xeb,0x5b,0x99,0x35,0x4a,0xfa,0x12,0xfb,0x87,0xfe,0x82,0x97,0x9d,0x3a,0x74, + 0x87,0x8b,0x1c,0x62,0x5b,0x63,0x66,0x82,0x8d,0x26,0x0a,0xb7,0xc3,0xd1,0x19,0xaa, + 0xa0,0xe2,0xfc,0x89,0xef,0x9b,0x3f,0x79,0x2a,0x5a,0x24,0x05,0xcc,0xd2,0x60,0xbf, + 0x10,0xab,0x5f,0x70,0x5b,0x36,0x2b,0x4f,0x28,0x31,0x22,0x0b,0xd8,0xa9,0xa9,0x0a, + 0xe5,0x8c,0x09,0x13,0xfb,0xcd,0x51,0x37,0x4d,0xf9,0x9c,0xdd,0x16,0xb5,0xfc,0x44, + 0x7c,0x17,0xfe,0x1c,0xb8,0x69,0x74,0xc9,0x4f,0xda,0xa6,0xc1,0x7a,0xb6,0xc3,0xa8, + 0x7f,0x87,0x2b,0xec,0xd6,0x10,0xe7,0x3f,0x4c,0xc8,0x1f,0x3a,0x79,0x1b,0x7c,0x08, + 0x15,0x2c,0xb3,0x47,0x8c,0xa0,0x84,0xab,0x3c,0xc1,0xcd,0x4c,0xe9,0x62,0x5d,0x65, + 0xdf,0x44,0x22,0x34,0x2a,0x7a,0x53,0xfe,0x8f,0x4f,0xda,0x8f,0xfa,0xab,0x34,0x62, + 0x1d,0xff,0xde,0xdb,0xca,0xd1,0xe6,0xaa,0x51,0xeb,0x98,0xe8,0xe6,0x57,0x4e,0x5b, + 0xb9,0x23,0x68,0x2c,0x58,0xa5,0xae,0x1f,0x36,0xd5,0x47,0x04,0x60,0xaa,0xf6,0x72, + 0xde,0xad,0x7e,0x3a,0xdb,0x3d,0x28,0xad,0xc9,0x2b,0xd6,0xeb,0x66,0x67,0x2b,0xf0, + 0xb1,0x5a,0x10,0xcd,0xe4,0xfe,0xe7,0x70,0xe8,0x01,0x2a,0xe7,0x93,0xa2,0xc4,0x7a, + 0x32,0xd8,0x0c,0x2f,0x01,0x82,0x9c,0x87,0xd2,0xc7,0xd4,0x55,0x1c,0x0f,0x37,0x90, + 0x3c,0x6d,0x97,0x50,0x60,0x04,0xee,0xe1,0x65,0xb5,0xf8,0xd8,0x8d,0x3e,0x8b,0x94, + 0xe0,0x3f,0xd4,0x72,0xd7,0xe2,0x69,0x2a,0xec,0xa2,0x2e,0xfb,0x41,0xc2,0x8c,0x44, + 0x68,0x0b,0xe5,0x69,0x54,0x31,0x62,0x81,0xdd,0xed,0x4e,0xdf,0x8d,0x2a,0xc9,0x36, + 0xe1,0xd5,0x6d,0x5c,0x7e,0x8e,0x5a,0x47,0x85,0x03,0x70,0x20,0xa6,0x7f,0x4b,0x50, + 0x43,0x15,0xa0,0x7e,0x41,0x7d,0xb7,0x47,0x2b,0x09,0xe1,0x17,0xa4,0x09,0x3c,0x1c, + 0x52,0x46,0x60,0xdc,0x6e,0xd4,0x7f,0x0d,0xab,0xdc,0x1f,0xb2,0xde,0x25,0x7e,0xa8, + 0x7d,0x3c,0xe1,0x6f,0xbf,0x40,0x2a,0x79,0x61,0xd4,0xb0,0x64,0xc6,0x3f,0x57,0x59, + 0x41,0xad,0x51,0xf6,0x7e,0x54,0x37,0xcc,0xd8,0x39,0xec,0xe8,0x44,0x21,0xfc,0x15, + 0x28,0x65,0x59,0x51,0x31,0x9a,0xc0,0x3f,0xbd,0xd2,0x0a,0x69,0xf7,0xdb,0x8e,0x41, + 0xd4,0xb6,0x1f,0x71,0xb7,0x61,0x6f,0x5b,0x98,0x14,0xf0,0xc4,0x1e,0xce,0x88,0x38, + 0x42,0xf7,0xf2,0xd0,0x4f,0xc8,0x6e,0xc2,0x3f,0x92,0x51,0xa6,0xdd,0x87,0x4a,0xf9, + 0x23,0x6e,0xaf,0x71,0x37,0x85,0x64,0x14,0xfe,0xc7,0xf4,0xb5,0x6e,0xef,0xc0,0x8d, + 0x67,0xe2,0x3f,0x84,0x4c,0x4e,0xb3,0x09,0x19,0x73,0x70,0x93,0x34,0x09,0xb8,0xdf, + 0xe6,0x10,0x48,0xc7,0xf9,0x11,0x3a,0x1b,0xd7,0x67,0xbb,0x1a,0xd2,0x10,0x68,0xf5, + 0x25,0xfa,0x59,0x40,0xde,0x03,0xbc,0xac,0x5b,0x2b,0xde,0x59,0x30,0x0c,0x07,0x78, + 0x18,0xe2,0x11,0xb9,0x10,0x8e,0x4e,0xfe,0x91,0xbe,0x38,0x5c,0x83,0xfb,0x21,0xd7, + 0xad,0x67,0x6d,0x11,0xa3,0x89,0xfa,0x9d,0x50,0xe6,0x25,0xf6,0x25,0x2c,0xd0,0xb3, + 0xce,0x15,0x8c,0x71,0xfe,0x1f,0x7d,0xfd,0xb9,0x9a,0x51,0x8a,0x40,0xa8,0x9f,0xe7, + 0xff,0xc0,0x65,0x17,0x8a,0xa6,0x65,0xe2,0x70,0x73,0x02,0xff,0x08,0xc7,0xa0,0x9f, + 0xcd,0x8e,0x2e,0x1e,0xcd,0xf9,0x29,0x9c,0x64,0x06,0xff,0x0f,0xe7,0x8f,0x2a,0x1d, + 0x28,0x79,0x5d,0x74,0xb1,0xf7,0x58,0xa9,0x68,0xed,0x37,0xf3,0xff,0xc0,0x19,0x25, + 0x03,0xf1,0x61,0xdd,0xcb,0xd9,0xc5,0x7d,0x01,0xd5,0x1e,0xcd,0xe0,0xfc,0xcf,0x7b, + 0x0b,0xdd,0x4a,0x71,0x30,0x5b,0x0d,0xb5,0x51,0x37,0xe7,0x9f,0x4f,0xd6,0x7f,0xd1, + 0xb4,0x21,0x34,0x33,0x1d,0x3a,0x9d,0xf3,0xec,0x00,0x04,0x68,0xfc,0x58,0xed,0xa5, + 0xea,0xa0,0x9c,0x4e,0x40,0x7f,0x11,0xba,0x08,0x95,0xcc,0xf5,0x5f,0x53,0x9e,0x81, + 0x16,0x56,0x84,0xf8,0x13,0xf1,0x24,0x77,0xfb,0x64,0xc4,0x60,0xcf,0x0c,0x2d,0xa3, + 0xdd,0x6f,0x87,0x36,0xc5,0xa2,0xd2,0xcd,0x5a,0xb2,0xfe,0x0b,0xd2,0xce,0xc0,0x81, + 0xd0,0x9e,0x90,0x35,0x8c,0xe8,0x65,0x10,0xba,0x7b,0xe3,0xfc,0xcc,0x6e,0x32,0x8b, + 0xca,0x5f,0x27,0x1f,0xea,0x37,0x34,0x38,0x37,0x9b,0xea,0xdf,0x43,0x93,0x77,0x91, + 0xcb,0x64,0x2e,0xc3,0x6d,0x70,0x9f,0xc1,0xff,0xcc,0xf9,0xc0,0xe1,0xaa,0x34,0xef, + 0x03,0xdc,0x36,0xba,0xf2,0x27,0xdc,0x38,0x36,0x9f,0x38,0x6c,0x8a,0x7f,0x3d,0xc3, + 0xd3,0x7a,0xd7,0x3e,0xc6,0x6f,0x3b,0xa6,0x4d,0xa4,0x99,0xb1,0x0a,0x4e,0xe3,0x36, + 0x93,0x1c,0xa2,0xdd,0x9b,0x9c,0xbf,0x14,0x1b,0x4c,0xfe,0x1f,0x89,0x4b,0x57,0x46, + 0x47,0x55,0x1e,0xf6,0x9a,0x37,0xc1,0x87,0x69,0x8f,0xa0,0xfd,0x58,0xa0,0x89,0x5a, + 0x11,0xd0,0xa7,0x97,0x99,0xfb,0x5f,0x48,0xd2,0xe3,0x8c,0x8d,0xce,0x0c,0x5b,0xac, + 0x10,0xc4,0xf3,0x22,0xc6,0xf9,0x6a,0xd8,0x7f,0x55,0x09,0x62,0xe3,0x60,0xb4,0x85, + 0xaa,0xe4,0x9c,0x09,0xff,0x94,0x49,0x4f,0xa0,0xd2,0xa7,0x3f,0xbe,0x6e,0x9a,0xb4, + 0x33,0x9e,0xf6,0x0c,0xbb,0x42,0x5b,0x42,0xb4,0x9e,0x5c,0x87,0x82,0xe5,0x07,0x3e, + 0x7a,0x27,0xb9,0x94,0xe4,0x7f,0x03,0x09,0x7e,0x0f,0x2e,0x3d,0x73,0xbb,0x68,0x15, + 0x06,0xd5,0x8a,0x11,0x9b,0xab,0x60,0x00,0x4f,0x5c,0x45,0xd4,0xa6,0x88,0x69,0x6a, + 0x9f,0xe6,0xf2,0x5a,0x6f,0x10,0xef,0x49,0xd6,0x7f,0x4d,0xdd,0x49,0x3e,0xe4,0xd5, + 0x4f,0x67,0xc5,0x6d,0xc2,0x65,0x88,0xf1,0xff,0x18,0xf5,0xef,0xb3,0x06,0xe5,0xf3, + 0xf0,0x25,0x57,0x6d,0x83,0xa6,0xfa,0x2f,0x3a,0x65,0x08,0xde,0x49,0xab,0x60,0x88, + 0x96,0x4b,0xb4,0x13,0x6c,0x82,0xff,0x19,0x5f,0xbc,0x58,0x2f,0xa8,0xa0,0x9f,0xc1, + 0xdc,0xa8,0x35,0x2a,0x93,0xa4,0xff,0x27,0x83,0xf3,0x1f,0x16,0xb3,0x00,0x2f,0xbb, + 0x5b,0x23,0xc5,0xc5,0x26,0x2f,0x7b,0x47,0x04,0x97,0x0b,0xbb,0x48,0xa9,0x46,0xa3, + 0xa4,0x34,0xe1,0x5f,0x52,0xe1,0x97,0x3c,0xcd,0xc9,0xee,0x78,0x34,0xeb,0x67,0xb0, + 0x2f,0x9e,0xf6,0x0c,0xbb,0x98,0x23,0x9a,0xb1,0x94,0x4c,0xe3,0xd0,0x28,0x4a,0x97, + 0x92,0x3c,0x65,0x62,0xfd,0xeb,0xa5,0xc3,0xd0,0x74,0xc8,0x19,0x42,0xf9,0xb3,0x18, + 0x78,0x61,0xaf,0xb1,0xdf,0x50,0x6d,0x0d,0xe1,0xfe,0x99,0xee,0xdb,0xa1,0xab,0xb5, + 0x8e,0x5c,0x72,0x63,0x42,0x3f,0x0e,0xe7,0xee,0x51,0x8f,0x84,0x8a,0x43,0xbc,0x5e, + 0x86,0x5e,0x09,0x77,0xc7,0xf9,0x9f,0xd9,0xfc,0x70,0xe6,0x90,0x38,0x0f,0xae,0xe4, + 0xcd,0x0d,0x59,0x3f,0x16,0xe7,0x25,0xf6,0x4f,0x1d,0x6c,0xf1,0x0f,0x8b,0x95,0x54, + 0xe0,0x30,0x60,0xd8,0x08,0x7b,0x4d,0x42,0x35,0xe4,0xad,0x24,0xb3,0x38,0x23,0xd0, + 0x98,0xb6,0x7f,0xb2,0xad,0xf9,0x5b,0xc7,0x4c,0xf6,0x7b,0xa7,0x11,0xf4,0x29,0x36, + 0x87,0x39,0xa4,0xb7,0x04,0xb7,0x96,0xb9,0x59,0x2e,0x64,0x77,0x42,0xf7,0x1d,0xb6, + 0x1b,0x4c,0xf5,0x3b,0x21,0x48,0x1f,0x6c,0xd1,0x4b,0xbc,0x14,0xd5,0x28,0x4d,0xa6, + 0x31,0x6b,0xbc,0x11,0x83,0xe7,0x39,0xd2,0x38,0x58,0xd4,0x20,0xa7,0xd4,0xbf,0xa7, + 0x15,0x0a,0x4f,0xaa,0x45,0xdf,0xa0,0x41,0x69,0x88,0xe7,0xcb,0xc5,0xe6,0x3f,0x89, + 0x6a,0x3a,0x23,0x98,0x5d,0xe8,0x68,0xe1,0x8e,0xa0,0x4d,0x37,0x64,0x99,0xed,0x2f, + 0xa1,0x71,0xb5,0xe1,0xff,0xe1,0xb0,0x27,0x16,0x06,0xc2,0x41,0xc8,0x4b,0xe7,0x10, + 0x4e,0x0d,0x5d,0xcf,0x11,0x91,0x25,0x51,0xff,0x95,0x77,0x93,0x0f,0x4e,0xc0,0x3c, + 0x61,0xaa,0x99,0xf6,0x27,0xf7,0x6d,0xc4,0x3f,0x99,0x2c,0x47,0xa5,0x07,0xd1,0x10, + 0x5b,0x82,0x36,0xa0,0xd9,0xff,0x83,0xa0,0xe5,0x1f,0xb5,0xbb,0x37,0xd5,0x3c,0x23, + 0x7d,0x3e,0xe1,0xd6,0xf8,0x1c,0xaa,0xbc,0xb3,0xce,0x8b,0x9f,0xe3,0x4f,0xaf,0x70, + 0x6a,0xa0,0x33,0x89,0xf5,0x2c,0x9f,0x72,0x1e,0x3e,0x91,0x6e,0xd5,0xac,0xbf,0x14, + 0x6f,0x5d,0xfb,0x56,0x9c,0x1f,0x09,0x2e,0x6b,0x3b,0xbc,0xff,0x78,0x8f,0x78,0x6b, + 0x10,0xf1,0x52,0xb5,0xf5,0x58,0x4d,0xb2,0xfe,0x3d,0x0f,0x42,0xd6,0x00,0x94,0x80, + 0x75,0x75,0x4e,0x3e,0xeb,0x32,0xf2,0x9f,0x89,0x81,0x88,0xa6,0x16,0x37,0x93,0x7c, + 0xd6,0xa3,0x16,0xdd,0x54,0xb7,0xba,0x35,0xc9,0xff,0x5c,0x27,0x3d,0x0b,0x5b,0x61, + 0x86,0x76,0x4b,0x2e,0xb9,0x1d,0x9e,0xa7,0xdc,0xdb,0x93,0xce,0x0b,0xe1,0xeb,0xf9, + 0x15,0x4e,0x05,0xd0,0xe9,0xa1,0x93,0xd5,0xec,0x24,0xfe,0xc9,0xe5,0x69,0xe4,0x25, + 0xb7,0xc7,0x68,0x27,0x35,0x7b,0x8c,0xf6,0x79,0xb7,0xdd,0xc1,0xf1,0x4f,0x21,0xec, + 0xcd,0x2d,0x8a,0xd0,0x8d,0x24,0x3d,0x31,0x3f,0x94,0xbb,0x1a,0x3e,0xb4,0xce,0xf1, + 0xdd,0x1d,0xcc,0x58,0x0e,0x0f,0x69,0x46,0x59,0x9f,0xe1,0xef,0xaa,0x9b,0x75,0x5c, + 0x9c,0xee,0x3b,0x0b,0xd7,0xd5,0x39,0x82,0xe6,0xfe,0x17,0xd0,0xd9,0xcc,0x83,0x5c, + 0xc5,0x8a,0x11,0x1d,0x4b,0xb8,0x7d,0xca,0xb4,0x59,0xd9,0x6d,0x67,0x60,0x5c,0x2c, + 0xe3,0x15,0x64,0xe6,0xfa,0xaf,0x0e,0x88,0xe8,0x31,0xb6,0x81,0x44,0x99,0x21,0x7e, + 0x88,0x79,0x9c,0xff,0x39,0x1f,0x22,0xab,0xdd,0x24,0xa5,0xfe,0x8b,0x4a,0xe5,0xb0, + 0x8e,0xcc,0xe2,0xf8,0x67,0x3e,0xe3,0x65,0x5f,0x8b,0x42,0x62,0x17,0xf0,0xfc,0x1f, + 0x3a,0x44,0xca,0xb5,0x75,0xb0,0xb5,0x43,0x8e,0x7a,0x92,0xfc,0x3f,0x34,0x6d,0xb1, + 0x51,0x76,0xaa,0xba,0x6e,0xf8,0x17,0xbf,0x88,0x82,0xba,0x8d,0x9f,0x97,0x3d,0xdc, + 0x71,0x0a,0x64,0x12,0x6c,0x98,0x8c,0x08,0xf0,0x06,0x53,0xfe,0x8f,0x2a,0x54,0xa8, + 0xcd,0xe9,0xc5,0x0c,0xb5,0xd5,0xda,0x8c,0xe7,0x5c,0x46,0x20,0x8c,0xd7,0x2f,0x4c, + 0xd7,0xa9,0x87,0x7c,0x0b,0x9e,0x90,0x66,0x82,0xfc,0x08,0x09,0x25,0xfc,0x3f,0x8e, + 0xbc,0xeb,0x50,0xbf,0x14,0x6f,0xb1,0x3e,0x9a,0xf3,0xb4,0x70,0x14,0x81,0xd0,0xa4, + 0x18,0xec,0xa9,0x8a,0xae,0xfb,0x89,0x5c,0x49,0x4e,0xb2,0xdb,0x7c,0xb6,0x13,0x29, + 0xf5,0x5f,0xcd,0x64,0x0c,0xa6,0xf1,0xa2,0xda,0x15,0xc2,0x3b,0x6c,0x42,0xad,0xc3, + 0x9e,0xb7,0x67,0xf5,0x88,0x3d,0xa8,0xfc,0xe7,0x72,0xfb,0xcb,0x93,0x90,0x3f,0x3e, + 0xe9,0x65,0xb8,0x1c,0x5c,0x30,0x64,0xa8,0xad,0x25,0xf1,0xb4,0x67,0xbc,0xff,0xfc, + 0x53,0x59,0x2d,0x05,0x65,0xc2,0xe1,0xe0,0xdc,0xa1,0xb5,0x27,0xc4,0x41,0x13,0xfe, + 0xd9,0x54,0xb7,0xf3,0x77,0xc5,0x5d,0x75,0x0d,0xd9,0xdf,0x95,0xfe,0x18,0xe7,0xff, + 0x81,0x6e,0xa9,0x43,0xa7,0x75,0xfe,0xc9,0xe1,0x3f,0xce,0xce,0x6f,0xa6,0xd9,0xf0, + 0x91,0xa9,0xfe,0x6b,0x13,0xec,0x54,0x67,0xae,0xbe,0xe5,0x21,0x44,0x47,0xaf,0x4c, + 0xf0,0xff,0xbc,0x4c,0x67,0xf6,0x5b,0x7e,0x44,0x36,0x29,0xfb,0x60,0xfa,0x1d,0x75, + 0x5e,0x4f,0x73,0xe2,0xfe,0x5a,0xee,0x2a,0x25,0xac,0x3b,0x55,0x34,0xdb,0x39,0xcd, + 0x4b,0x9c,0xcf,0xbf,0x9b,0x21,0x1e,0x70,0x5b,0x7e,0xcb,0x5e,0x04,0x7b,0x37,0xdd, + 0xe6,0x3f,0x61,0xf6,0x0f,0x68,0xb8,0x5b,0x3a,0x6d,0xa3,0x68,0x4f,0x7d,0xa9,0x71, + 0xf9,0x39,0x89,0xeb,0x97,0xf2,0xfa,0xbb,0x03,0xe2,0xb3,0xb0,0xdb,0x5b,0xe6,0xb5, + 0xae,0xdd,0x15,0x31,0xf1,0x2d,0x8c,0x68,0x63,0xc2,0x34,0xc4,0x3f,0x35,0x51,0xf8, + 0x4f,0x34,0xbe,0x3e,0x88,0xa8,0xfb,0x6c,0xcd,0xc2,0xfd,0xca,0x3b,0x50,0x29,0xa0, + 0x04,0x3b,0x65,0xf2,0xff,0x9c,0x87,0x81,0xc0,0x7c,0xe6,0x1c,0xcd,0xe9,0x46,0x18, + 0x90,0x13,0xe3,0x7f,0xbe,0xa2,0xcd,0xd5,0xac,0x4f,0xe6,0x8c,0x28,0x56,0x34,0x94, + 0xac,0x3a,0xee,0xcf,0xa4,0xff,0x67,0x39,0x0b,0x44,0x9d,0xae,0x3a,0x84,0x3d,0xea, + 0x5e,0xe8,0x30,0xf4,0x97,0x14,0xce,0x78,0x41,0x77,0x6c,0x26,0xa7,0xa1,0x4b,0xef, + 0x68,0xa8,0x5b,0x8b,0xa7,0x21,0x99,0xff,0xbc,0x1c,0x02,0x6a,0x56,0x07,0xa2,0x9d, + 0x6d,0xcd,0x7b,0xa1,0x68,0x42,0xdf,0xcd,0xb8,0x33,0xc0,0x36,0x9e,0x49,0x7b,0xbe, + 0xf1,0x85,0x28,0x5d,0x7b,0x8f,0x89,0xff,0x07,0xf5,0x11,0xa3,0x4e,0x12,0x70,0x11, + 0x2b,0xde,0x3f,0xc6,0x07,0x68,0x10,0xf5,0x53,0x42,0x74,0x81,0x21,0x34,0xa2,0xe0, + 0x21,0x09,0xf9,0x03,0x79,0x9c,0xf6,0xaa,0x32,0x60,0x0d,0xe7,0xac,0xe5,0x6a,0xe5, + 0xf5,0xd8,0x7e,0x50,0x76,0x79,0xad,0x7e,0x31,0x9a,0x61,0xc4,0x7f,0x37,0x08,0x6a, + 0x4a,0xfe,0xcf,0x4a,0xbe,0x08,0x9c,0x46,0xe0,0x4b,0x28,0x8b,0xf1,0x3f,0x9f,0x57, + 0x5f,0x39,0x68,0xeb,0x45,0x8b,0xfe,0x3c,0xdf,0x3f,0xfa,0xa4,0x24,0xfe,0x01,0x20, + 0xcd,0xb0,0x85,0xd3,0xcd,0x28,0xff,0xce,0x00,0xcc,0x7f,0x12,0xa0,0x75,0xa8,0xa1, + 0x04,0xfe,0x77,0x06,0xe6,0xbf,0x66,0xb4,0xe9,0x39,0xb9,0xe6,0xbf,0x37,0xf8,0x3f, + 0xb9,0x3f,0xe3,0x39,0x44,0x40,0xfe,0xdd,0x81,0xe9,0xef,0xdf,0x9f,0x18,0x1b,0xfc, + 0x9f,0xdc,0xff,0x7f,0xf7,0xef,0x3f,0xd8,0xfa,0x2b,0xbc,0x97,0xdf,0x00,0xfc,0x08, + 0xa6,0xea,0xff,0xce,0x40,0xfa,0x7f,0x7c,0xff,0xff,0x3f,0xaf,0xbf,0xa4,0xb0,0xbf, + 0x62,0xcd,0x05,0x53,0x7f,0x9f,0xff,0xbd,0xbf,0x8a,0x8a,0xbf,0x66,0x96,0xcd,0xf6, + 0xff,0xf0,0xf6,0xff,0x2f,0xfc,0x55,0x5d,0xbd,0x7a,0x55,0xff,0x5f,0x0c,0xfe,0xbf, + 0x3c,0xff,0x3f,0xd8,0x79,0xfc,0xbf,0xf2,0xf0,0xff,0xca,0xc3,0xff,0x83,0xf5,0xff, + 0xbf,0xf2,0xf0,0x7f,0xf5,0xf7,0x1f,0x4d,0xfe,0xfc,0xc7,0x9a,0xcf,0xf9,0x21,0x8f, + 0x2a,0xb3,0xf5,0xac,0x51,0xb9,0x0c,0xfe,0x02,0xa5,0xaa,0x4d,0x17,0xcb,0xc9,0x7a, + 0xb5,0xca,0x67,0x5b,0x29,0x56,0xc0,0x81,0xfe,0xd9,0x43,0xd6,0xb1,0x49,0xe6,0xfc, + 0xa8,0xa8,0xda,0xa2,0xd9,0xcf,0xd3,0xcd,0xd9,0x85,0x6c,0x7d,0x6f,0x91,0x2a,0x8b, + 0x7d,0xbf,0x91,0xd6,0x07,0x4b,0x7c,0x8b,0x7a,0xb2,0x7f,0xa7,0xb6,0xa9,0x65,0x11, + 0xca,0xf9,0x04,0x92,0xfe,0xb1,0x6d,0x5a,0xe3,0xe4,0x90,0x6e,0x99,0x4d,0x9e,0x55, + 0xb7,0x56,0xab,0xea,0x0d,0x1b,0xd3,0x1d,0x5a,0x53,0x7a,0x21,0x27,0x1e,0xc9,0x64, + 0x4d,0x85,0xf6,0x6b,0xfa,0xc3,0x4e,0x19,0x22,0x9c,0x56,0x8b,0xf3,0x03,0xb3,0x36, + 0x20,0x5a,0x4e,0xc0,0xce,0x03,0xaf,0x25,0x20,0xf7,0x90,0x6d,0xa4,0x89,0xf1,0x40, + 0x61,0x76,0x32,0x3f,0x4a,0xc8,0x7d,0x96,0x1d,0xd4,0xed,0x7a,0x96,0xd1,0x86,0x03, + 0x1e,0x66,0xb6,0xb5,0x4d,0xf9,0x81,0x43,0xe4,0x9f,0x34,0xb9,0x47,0x74,0xc2,0x9d, + 0x21,0x35,0x6a,0x0d,0x93,0x41,0x53,0x7c,0xf0,0x59,0xed,0x72,0xf0,0x77,0xba,0xed, + 0x84,0xf0,0x05,0xa7,0xc5,0x4e,0xb7,0xe9,0x35,0x97,0x94,0x8b,0xf0,0x73,0x2f,0x07, + 0xd2,0xf4,0x15,0xa1,0x6a,0xd4,0x36,0x5a,0xd0,0x65,0xaa,0x4f,0xef,0x14,0x0e,0x68, + 0xee,0x88,0x75,0xbb,0xd8,0x09,0xef,0xd1,0xca,0xe6,0xcc,0xa0,0xa8,0xa6,0x1d,0x62, + 0x2f,0x6b,0x06,0x43,0xc5,0x21,0xcd,0x48,0x9d,0x32,0xe5,0x47,0x41,0xba,0xda,0x42, + 0x6f,0x39,0x96,0xc9,0x69,0xf7,0xd6,0xf4,0x96,0x34,0xa4,0x03,0xc9,0xda,0xb0,0x9e, + 0xa7,0x6d,0x4c,0x23,0x15,0xf8,0x22,0x2f,0x9c,0xb4,0x86,0x53,0xf8,0x91,0x6a,0xa1, + 0x31,0xa2,0x0e,0xd2,0x6c,0x14,0x7e,0x8f,0x6b,0x4e,0x6f,0x0e,0x90,0x03,0x81,0x26, + 0x5e,0xbf,0x53,0x6e,0x19,0x10,0xb6,0xf2,0xfc,0x0d,0x1e,0x1f,0x9c,0xf8,0xe3,0xf9, + 0xe1,0xeb,0x79,0x52,0xf4,0xca,0xeb,0xce,0x19,0xf5,0x71,0x37,0xfc,0xc0,0xf3,0xb6, + 0xb4,0x26,0x28,0x0c,0x8b,0x3f,0xb1,0x4c,0x2b,0xfc,0x97,0xc6,0x5b,0x7c,0x94,0x27, + 0x0e,0x4d,0xfc,0xd5,0xf1,0x36,0x1c,0xe0,0xea,0xb5,0x2a,0xe2,0x5a,0xf8,0x3d,0xad, + 0xa0,0x37,0x09,0x72,0xbd,0xd4,0x24,0xe4,0xd6,0xaf,0x9f,0x23,0x8e,0x90,0xf7,0x83, + 0xae,0x08,0xef,0x0f,0x9b,0x8c,0x0f,0xde,0xb4,0xcd,0xf3,0x99,0xc2,0xdd,0x86,0x93, + 0x8e,0x6b,0x7f,0xaf,0x55,0xe9,0x37,0xf7,0xe2,0x7e,0xf8,0x79,0x6d,0x15,0xe3,0x1d, + 0xf4,0xe0,0x8f,0x02,0x27,0x56,0x15,0x07,0x13,0xf1,0x41,0x87,0xb4,0x0d,0x0e,0x08, + 0xbc,0xc8,0xa2,0xa6,0x13,0xde,0x71,0x55,0x9e,0xc0,0xfd,0x13,0x52,0x7e,0xcf,0xdc, + 0x5a,0x5b,0x58,0x74,0x7a,0x0e,0x91,0x69,0x3c,0x90,0x9a,0x8c,0x0f,0x46,0x94,0xcd, + 0xb0,0x06,0xf2,0xa3,0x4d,0x0d,0xf6,0x5c,0xfa,0x47,0xa1,0xf8,0xd8,0x22,0xdd,0x33, + 0x95,0x3e,0xa7,0x19,0xfc,0xba,0x53,0xb5,0x35,0xb1,0x8c,0x71,0x73,0x7c,0x30,0x0b, + 0xb6,0xb2,0xe7,0xa3,0x8b,0xf2,0xbc,0xbf,0x74,0xad,0x09,0x15,0x77,0xc8,0x75,0x64, + 0x23,0xac,0x09,0xe5,0xfb,0xe4,0xfa,0xec,0x69,0xb0,0x9a,0xcd,0xf2,0x05,0x56,0x92, + 0x13,0xa6,0xf8,0xe0,0x6f,0xa0,0x29,0xc3,0x30,0x4b,0x57,0xb1,0xc7,0x89,0x33,0x2a, + 0x0b,0x64,0x16,0x6c,0x85,0x2e,0x26,0x3b,0x8a,0x9c,0xb0,0x11,0x4a,0x78,0x7f,0x58, + 0x53,0x7c,0x70,0xca,0xde,0xbe,0x23,0x42,0x07,0x93,0x43,0x39,0x7b,0xe9,0x41,0xa8, + 0x64,0x47,0x87,0x6f,0xd9,0xcb,0x0e,0xc2,0x43,0xcc,0x76,0xe6,0x1b,0x0e,0xfa,0x3a, + 0x94,0x74,0x39,0x43,0xe2,0x85,0xe4,0xfd,0x61,0xc2,0x4d,0x04,0x3e,0x83,0x1f,0x7b, + 0x12,0xa7,0xa9,0x19,0x8e,0xe7,0xeb,0xc2,0xb0,0x1a,0xe3,0x07,0x30,0xc5,0x07,0x87, + 0x0c,0x36,0xa4,0x9b,0x83,0xe2,0x72,0x7a,0x00,0xca,0x7c,0x4b,0x94,0x58,0xa2,0xb8, + 0x66,0x6d,0x6f,0x8a,0x11,0x25,0x19,0xf9,0xe1,0x13,0xf3,0x99,0xb4,0x9c,0x34,0x56, + 0x93,0x6a,0xf9,0x3a,0xbb,0xd1,0x1f,0x4d,0x6f,0xe1,0x81,0xc5,0xb7,0xa4,0x2c,0xcd, + 0x92,0x6b,0x9f,0x4e,0x5b,0x88,0xbd,0xc1,0xc1,0xf3,0x3f,0x27,0xfe,0xf2,0xa4,0x42, + 0xd2,0x96,0x61,0xaf,0x95,0x83,0xa4,0x5f,0x68,0x01,0x7b,0x9d,0x11,0xcf,0x6a,0x61, + 0x33,0x34,0xcb,0x06,0xcb,0xf4,0x34,0x7e,0x85,0x9a,0xe3,0x83,0x20,0xa5,0x91,0x38, + 0x1b,0x52,0x9a,0x75,0x0b,0x7e,0xef,0x0c,0xee,0x26,0xda,0x20,0x65,0x55,0x2f,0x74, + 0x91,0x34,0xa1,0x45,0x63,0x0d,0x29,0xf9,0x99,0x2b,0x33,0xb8,0x7d,0xda,0xd1,0x78, + 0x23,0x4f,0x8b,0x8a,0xa7,0x25,0x53,0x12,0xc1,0xf3,0x98,0x15,0x23,0x4a,0x32,0x2a, + 0x76,0x3f,0x35,0xf9,0xc7,0x3e,0x27,0x57,0xb5,0x12,0x5e,0x04,0xf7,0x08,0x79,0xab, + 0xfa,0x69,0x4d,0x38,0x2e,0xbf,0x04,0xe3,0x5a,0x95,0x76,0xb4,0x41,0x7c,0x2d,0xed, + 0x32,0x2f,0x9d,0x0b,0x8a,0xbf,0x35,0xe5,0x47,0x7d,0x11,0x3a,0xdc,0x3f,0x77,0x99, + 0xed,0x98,0x38,0x24,0x1d,0xe6,0xf5,0x0b,0x9b,0x26,0xed,0x84,0xc3,0x24,0xd6,0x4f, + 0x4d,0x1b,0xf7,0x14,0x70,0x62,0xa5,0x4f,0x4d,0xf9,0x51,0xa7,0xfd,0x01,0x56,0xa6, + 0x88,0x8c,0x0c,0x33,0x7c,0x1e,0x26,0x83,0x78,0xbf,0xb7,0xeb,0xde,0x12,0x66,0xf0, + 0x23,0xf5,0x48,0x65,0x54,0x4e,0x89,0x0f,0xa6,0xf5,0x77,0x34,0xc6,0xaa,0xff,0x3a, + 0xd5,0x0d,0x38,0xf8,0xd5,0x26,0xde,0x1f,0x36,0xc6,0x07,0xde,0xdf,0xb8,0x1b,0x54, + 0xcf,0x22,0x73,0x7c,0xb0,0x7d,0xca,0x2a,0x83,0x16,0x7b,0x51,0xac,0x2d,0xc8,0x8c, + 0x5e,0x5c,0xcf,0x5a,0x2b,0xcf,0xcf,0x17,0x63,0x8e,0xca,0x19,0xb7,0x1b,0xfc,0x00, + 0x13,0xf3,0x3b,0x50,0x5e,0xf5,0xea,0x46,0xb6,0xdb,0xeb,0x9e,0xb7,0x78,0x1a,0xd8, + 0x66,0x7f,0x27,0x9e,0x88,0x9f,0xf1,0x7a,0x40,0x1e,0xff,0xed,0xd0,0x6c,0xe6,0xf8, + 0xe0,0xb0,0x50,0x98,0x68,0x8b,0xa6,0x8c,0xd3,0x58,0x7e,0x54,0x2e,0x77,0x9c,0xae, + 0x37,0x12,0xa5,0x72,0x8c,0x44,0x32,0x53,0x7c,0x50,0x51,0x8d,0x26,0x20,0x95,0xac, + 0xc9,0x07,0x83,0xb8,0xda,0x59,0xcd,0xa2,0x8f,0x8e,0x15,0x96,0x29,0xab,0x9b,0x45, + 0xa3,0x3e,0x8e,0xa6,0xe6,0x47,0x09,0x0e,0x58,0xa7,0x14,0xb0,0xcc,0x11,0x82,0x03, + 0x56,0xc4,0xa8,0x9a,0x53,0xae,0xee,0x67,0xcb,0x58,0xc6,0xb0,0xf8,0x63,0xf0,0x93, + 0x59,0x41,0x39,0x64,0x8a,0x0f,0x3a,0x24,0x2b,0x69,0xd2,0xba,0x4e,0x65,0xcc,0x21, + 0x8b,0x33,0x1e,0xd7,0xd5,0xa8,0xec,0x4a,0x5f,0x2c,0xec,0x18,0x2c,0xd4,0x2d,0xf3, + 0x88,0xcc,0x1e,0x87,0x15,0x85,0x3c,0x5f,0x2e,0x19,0x1f,0x84,0x5c,0x58,0x05,0xcf, + 0x9f,0xce,0xc8,0xf3,0x57,0x80,0x48,0xff,0xeb,0xb2,0x8c,0x87,0xc8,0x54,0xd8,0xd5, + 0x9c,0xaf,0x67,0xac,0xf4,0xff,0x27,0x78,0xc2,0xf5,0x00,0x8f,0xef,0xd7,0x25,0xe3, + 0x83,0x01,0xce,0x56,0x34,0xf3,0x94,0x75,0xe5,0xdc,0xef,0xce,0xf9,0x63,0xa3,0xc0, + 0xc3,0x82,0xdf,0x81,0xcf,0xd8,0x4b,0xd1,0x75,0x2b,0x85,0x4a,0xf2,0x47,0xff,0x4f, + 0x43,0xb6,0x95,0x5f,0x37,0xc5,0x07,0xad,0xcf,0xc0,0x98,0x36,0x47,0xcf,0x0c,0x7e, + 0xe3,0x30,0xbb,0x08,0x95,0x6f,0x67,0xbd,0xcc,0xdb,0x9e,0x72,0x47,0xbd,0xca,0x19, + 0x93,0x28,0x27,0x0a,0xf8,0x86,0x89,0x1f,0x72,0xd5,0xd5,0xc0,0x51,0xbd,0x34,0x6a, + 0x7b,0xd2,0x56,0x19,0xba,0xcc,0x4a,0x4f,0x2d,0xde,0x57,0xb3,0x1f,0x3e,0xf6,0x7f, + 0x2d,0x7a,0xf7,0x78,0x41,0x99,0x72,0xc8,0x3f,0x57,0xb5,0xee,0x16,0x93,0xf2,0xa1, + 0x6b,0xf2,0x2f,0xa3,0xab,0xe8,0x96,0x7e,0xf9,0xd1,0xd5,0x53,0xd5,0x33,0x70,0x4b, + 0x5d,0xe6,0xff,0x20,0xb9,0xca,0x9a,0x90,0xa3,0x8f,0x8e,0x91,0x4d,0x64,0x4d,0x30, + 0x5f,0x72,0xac,0x14,0x3f,0x32,0xc5,0x07,0x9f,0xae,0x5b,0xc3,0xf2,0x35,0xb9,0x9a, + 0x4c,0x6d,0x7f,0x09,0x0a,0x7a,0xaf,0x6f,0xf0,0xb7,0xe3,0x6b,0xde,0xa2,0x5b,0xce, + 0x91,0x5c,0xf8,0x67,0xf2,0x75,0x96,0xf1,0x30,0x79,0x5d,0x9b,0x98,0xef,0xcb,0x7d, + 0x03,0x02,0x3a,0x70,0xa1,0x3d,0x0b,0x3a,0x40,0x3d,0x96,0x31,0xc7,0x4e,0xc8,0xe3, + 0x50,0x3f,0x4a,0x15,0x4f,0x33,0xfc,0x8a,0xd9,0xb5,0x0c,0x17,0x09,0x26,0xbf,0x57, + 0xee,0xb3,0xe4,0x80,0xbf,0x9b,0xd9,0xda,0x49,0x25,0xcf,0xf6,0x39,0x97,0x79,0x9e, + 0x3c,0xc7,0x4e,0x80,0x7b,0x28,0xeb,0x29,0xd1,0x81,0x1a,0xa7,0x8c,0x65,0x86,0xc9, + 0x11,0xe6,0x4b,0x3c,0xcf,0x36,0xf5,0xe2,0x22,0x23,0x09,0x7c,0x45,0xf3,0x29,0xa8, + 0x0c,0xda,0xba,0xc5,0x0f,0xe1,0x23,0xcf,0x31,0x7d,0x09,0x8a,0x05,0x81,0x67,0x94, + 0x65,0x85,0x27,0x99,0xe3,0x83,0xbf,0xd4,0x0e,0x43,0x69,0x08,0x4f,0xd3,0x4f,0xe0, + 0xa0,0x32,0x97,0x97,0x45,0xa7,0x87,0x0e,0x0a,0x55,0x3a,0x5e,0x59,0xc1,0xae,0x42, + 0x01,0x4f,0x9d,0x52,0x4d,0xf1,0xc1,0x12,0x68,0x6d,0xef,0xe8,0x47,0x6d,0xe5,0x54, + 0x9e,0xaf,0xb3,0x87,0xe4,0xb0,0xa5,0x08,0x5e,0x60,0x0f,0xea,0x87,0xa6,0xa6,0x3f, + 0xcb,0x03,0x3d,0x51,0xd4,0xbf,0x66,0x7e,0x00,0x9e,0xc6,0x69,0x6f,0x5a,0xd4,0xee, + 0x59,0xc1,0xab,0xb7,0x6a,0x2d,0x61,0x32,0x1d,0xda,0xfa,0x7e,0x18,0x6b,0x14,0xbb, + 0x17,0x8a,0x4e,0xd3,0xb0,0x39,0x3e,0x28,0x59,0xed,0x22,0x84,0x98,0x9c,0xed,0xb1, + 0x42,0x08,0x54,0x41,0x76,0x3d,0x05,0x74,0xab,0xea,0xec,0xc7,0x63,0xd5,0x0c,0x3b, + 0x7c,0x54,0xa3,0x6e,0xd2,0xd7,0x9c,0xd8,0xa0,0x99,0xf7,0xc2,0x6b,0xbc,0x2d,0xe3, + 0xc6,0xa6,0x9f,0x28,0x11,0xe8,0xd6,0xb2,0xce,0x7d,0xa3,0x10,0x0e,0x39,0xe6,0x0d, + 0x1a,0x85,0x72,0x57,0x79,0x46,0x59,0x58,0xf4,0x25,0xe3,0x83,0x37,0x8d,0xc4,0xd8, + 0x2f,0xbd,0x39,0x97,0x88,0xc1,0x86,0x3d,0x6a,0x24,0x8a,0x2f,0x88,0xac,0xdf,0x20, + 0x9e,0xa7,0x5f,0xfa,0x5e,0xd2,0x6c,0xe7,0x73,0x4c,0xfc,0x48,0x69,0x5f,0xc0,0x38, + 0x73,0x83,0x6d,0x4c,0x5c,0xa6,0x1d,0xe5,0xcb,0x3e,0x26,0x8e,0x86,0x2e,0x3b,0xe6, + 0x46,0x33,0x07,0xc5,0x2b,0x70,0xd2,0x35,0x37,0xcf,0xaa,0xdf,0xe8,0x4a,0xf0,0x99, + 0xe8,0x01,0x5e,0xe4,0x65,0x77,0xf1,0x6a,0xb8,0x60,0x9b,0x6e,0x47,0xb4,0x43,0xde, + 0x87,0xdd,0x7c,0xb0,0x8f,0x8c,0xb0,0x40,0x83,0x5d,0xa1,0xab,0xd3,0x93,0xf9,0x51, + 0x11,0xb4,0x09,0xb6,0x0b,0x0e,0x09,0x6f,0xa1,0x41,0x53,0xb5,0x1a,0x69,0xe5,0x6d, + 0x2f,0x76,0x40,0x61,0x1f,0x0a,0xde,0x11,0x15,0x37,0x82,0xd5,0x22,0xf9,0x93,0xf1, + 0xc1,0xa8,0xd4,0xa9,0xe0,0xfd,0x19,0xa2,0xa3,0x57,0x2d,0x32,0xd8,0x7b,0x71,0xf5, + 0x3e,0x81,0xbd,0x0c,0x70,0x90,0x3e,0x62,0x69,0xd1,0x79,0xeb,0x10,0x53,0x7e,0x94, + 0x90,0x76,0x46,0x39,0x1b,0xea,0xce,0x46,0x34,0xf2,0x3d,0xa3,0x1a,0x2b,0xcb,0xc8, + 0x27,0xec,0x2d,0xd3,0xef,0x0a,0x8b,0x07,0xf2,0xde,0xd2,0x5f,0x6e,0xc8,0x6a,0x6f, + 0x4a,0xe6,0x47,0x85,0x26,0xef,0xd4,0x2e,0x93,0xca,0xe5,0x4b,0x2e,0xe5,0x8c,0x25, + 0xcb,0xbe,0x2e,0x73,0xfe,0xa8,0x28,0x19,0xeb,0xf8,0x5c,0x58,0xc0,0x32,0xf5,0x9a, + 0x24,0xfe,0x39,0xae,0x74,0x6a,0xe3,0x3e,0xb7,0x62,0xe5,0x69,0x57,0x3c,0x51,0x1c, + 0x07,0x1f,0xc2,0x21,0x56,0xd9,0x87,0x83,0x4f,0xe0,0xed,0x3b,0x2b,0x97,0xda,0x76, + 0x9a,0xf3,0xa3,0xd2,0x66,0xf0,0x68,0x54,0x07,0x0d,0x7b,0xa2,0xa8,0xe8,0x63,0x69, + 0x5d,0xac,0x09,0x1e,0x3c,0x41,0x43,0x64,0xc4,0xde,0xb2,0xb8,0xc4,0x27,0x6e,0x10, + 0xcd,0xf1,0xc1,0x74,0x36,0x5b,0x57,0x59,0xc6,0x1c,0xbf,0x0e,0x5b,0x25,0xbb,0x9e, + 0xe1,0xca,0x7e,0x9d,0x67,0xf0,0x0e,0xd6,0x29,0xe4,0x48,0xce,0x46,0xe6,0x0c,0xb6, + 0x3d,0x6f,0x4f,0xe2,0x9f,0x51,0xe5,0x3a,0xfa,0xbb,0x70,0x7e,0xe8,0xce,0x95,0xe4, + 0x61,0xed,0x39,0x96,0x3f,0x74,0xcb,0x4a,0x94,0xf6,0xab,0x9a,0x8b,0xa3,0xf4,0xd1, + 0xec,0x2b,0x91,0xb4,0x8e,0xe2,0x90,0x7c,0x67,0x7a,0x32,0x3f,0xaa,0x3e,0xcf,0x0a, + 0xa3,0x3d,0x2e,0x5f,0xa6,0x0b,0x41,0xc8,0xfb,0x92,0x7b,0x38,0xd3,0xe8,0x0f,0x22, + 0x94,0xe8,0xce,0x1b,0x26,0x0d,0xb0,0xc1,0xc9,0x15,0xf7,0xa0,0x46,0x36,0xf5,0x47, + 0x9b,0xb2,0x0f,0x3e,0xc7,0xd5,0x28,0x41,0x90,0xa3,0xbd,0x87,0x40,0xc8,0xc9,0x69, + 0x21,0x0d,0xf9,0x73,0xb6,0xe0,0x64,0xe0,0xf2,0xad,0x3f,0x47,0xf9,0xfc,0x8d,0x60, + 0x62,0x7d,0x1c,0x52,0x27,0x9c,0x65,0xf3,0x98,0xb5,0x3c,0x27,0x0b,0xde,0x31,0xfa, + 0xa3,0xe5,0x8c,0x28,0x47,0x25,0xa3,0x3f,0xc8,0x90,0x74,0x04,0x4a,0xc1,0x19,0x15, + 0x3d,0x89,0xf5,0x1f,0xa1,0x9b,0xe0,0x73,0x1e,0x3d,0x6f,0x10,0xef,0x83,0x35,0x7a, + 0x2c,0xcd,0x80,0xae,0xf1,0x17,0xeb,0xb2,0x2f,0x9b,0x27,0x36,0x6f,0x61,0x54,0x13, + 0x93,0xfc,0x90,0x3c,0x3f,0x6a,0x17,0x9b,0xe9,0xcb,0x58,0x69,0x9f,0x0b,0x3b,0x42, + 0x06,0x1f,0xf8,0x11,0x58,0xc3,0x2b,0x04,0x57,0xce,0xb8,0x02,0xdd,0x7e,0xd5,0x77, + 0x67,0xb9,0x29,0xff,0x61,0xb1,0xb4,0x16,0x76,0x44,0xd4,0x37,0x33,0x14,0xcf,0x1d, + 0x88,0x1e,0x3b,0x38,0xba,0x3e,0x82,0x12,0xde,0xa9,0xcb,0xd3,0xc9,0xe1,0xc5,0x19, + 0x5e,0x7b,0x43,0xc6,0x54,0x8b,0x89,0x1f,0x52,0xea,0x82,0x2b,0xda,0x6d,0xcd,0x99, + 0x5d,0x8f,0x97,0x73,0x5a,0x6c,0x66,0x45,0xb4,0xc3,0x8e,0xf0,0x08,0x69,0x54,0xbc, + 0x48,0xee,0x66,0xa5,0xa1,0xcc,0x8f,0xc4,0x79,0x26,0xfe,0xa5,0x90,0x30,0xac,0x54, + 0x42,0x09,0xcb,0x39,0x05,0x4b,0x8d,0x46,0xb1,0x08,0x0c,0x0c,0x7e,0x6c,0xd6,0x14, + 0x2d,0x1c,0x93,0x2b,0xd3,0xb3,0x58,0xd3,0x46,0x73,0x7e,0x14,0x8c,0x4f,0xae,0xf4, + 0xf1,0xb6,0x59,0xea,0x43,0xc4,0xcd,0xab,0xa5,0x86,0xb4,0x03,0x01,0xa3,0x90,0xfc, + 0x8c,0x72,0xa0,0xc3,0x5d,0x6f,0x9d,0x4a,0x88,0x09,0xff,0xfc,0x17,0x3c,0x4d,0x25, + 0x1e,0xcb,0x66,0xf2,0x01,0xdb,0x0d,0x65,0x9c,0xef,0xe8,0x0c,0x3c,0xe6,0x77,0x6a, + 0x8e,0x20,0x79,0xc3,0xd7,0xc2,0xec,0xf5,0x46,0x45,0xc6,0xc4,0x79,0x2f,0x4f,0xfb, + 0x3a,0x2a,0xe5,0xac,0xda,0xbc,0xcd,0x64,0x48,0xe3,0xfd,0x4c,0x8d,0x34,0x9e,0xb6, + 0xfc,0x07,0xef,0x47,0xd8,0xb3,0x0d,0x78,0xc6,0x14,0x35,0xf3,0x03,0xa8,0xb9,0x12, + 0x6c,0x27,0xce,0x6a,0x8b,0x72,0x0f,0x6f,0x93,0x51,0xe8,0x35,0xe2,0x83,0x8d,0xf0, + 0x20,0x87,0x3d,0x1f,0x18,0x1d,0x43,0xf2,0xcc,0xfc,0x48,0x2b,0x6f,0x8a,0xe5,0x47, + 0x59,0x63,0xf9,0x60,0x46,0x58,0xd0,0xa8,0x8f,0x13,0xac,0x3c,0x42,0xca,0x89,0x22, + 0x9d,0x4c,0xfe,0xed,0xa4,0x44,0x7e,0xd4,0xe4,0xf3,0x3c,0x3f,0xea,0x9b,0x1c,0xbd, + 0x48,0xe3,0xb1,0xfc,0xf0,0xcf,0xc9,0x65,0xc4,0x3f,0xb6,0xe3,0x39,0xc7,0x49,0x8c, + 0x1f,0xe0,0x6b,0x0f,0x26,0xf3,0xa3,0xa6,0xf0,0xf9,0xf3,0xeb,0xac,0x83,0x93,0x70, + 0xa0,0x1a,0x40,0xe2,0xbc,0x7a,0x94,0x17,0xf2,0x04,0xc5,0x5b,0x39,0x3f,0xb6,0xc7, + 0x7a,0xec,0xf5,0x4f,0x93,0xf9,0xdb,0x88,0x3f,0x7b,0x24,0xbb,0x54,0xc7,0x48,0x54, + 0x1d,0x53,0xca,0x2c,0x94,0xc7,0x07,0x03,0xd2,0x3c,0x52,0xd7,0x28,0xd6,0xb3,0x88, + 0xda,0x01,0x8e,0x66,0x13,0xfe,0xa9,0x43,0xf9,0xb3,0x1b,0x1c,0x3e,0xaa,0x64,0xf7, + 0x2b,0xdb,0x41,0xad,0xb3,0xf0,0x34,0xf8,0x46,0xe6,0xac,0xc6,0xf7,0x2d,0x64,0xdb, + 0x7f,0xa0,0x2e,0x8c,0x64,0xfb,0x8f,0x25,0xf2,0xdf,0xda,0x73,0x8d,0xfc,0x28,0x4e, + 0xe2,0x31,0x42,0x39,0xdf,0x26,0x2e,0xfb,0x10,0x69,0x91,0x68,0x35,0x0e,0x56,0x68, + 0x6d,0xd5,0xf6,0x85,0xf4,0x17,0x8a,0x29,0x3f,0x4a,0x79,0x96,0x9e,0xf5,0x95,0x6b, + 0xce,0x60,0xf6,0x19,0xef,0x6d,0x88,0x66,0x79,0x3e,0xbc,0x7e,0x00,0xf1,0x12,0x3e, + 0xff,0x8c,0xc9,0xe3,0x9c,0x3f,0xa4,0x5d,0x4d,0xe2,0x9f,0x08,0x74,0x06,0x38,0xfe, + 0x59,0xb2,0xc1,0x7e,0x46,0xe2,0x6d,0x41,0x62,0xf9,0xf3,0xfa,0xa3,0x1e,0x9b,0x22, + 0x0e,0xc9,0xbb,0x95,0x4a,0x5f,0x0a,0xfe,0xa1,0xbc,0x3e,0x4e,0x43,0x50,0xed,0xc7, + 0x65,0x1f,0x26,0x7c,0xfd,0x0b,0x4e,0x41,0x24,0xe3,0x67,0xb8,0xec,0x46,0xc5,0xa2, + 0x9b,0x2e,0x5e,0x95,0xd3,0x6a,0x8a,0x0f,0xce,0xaf,0xde,0xaf,0xcf,0x0a,0xb6,0x45, + 0x27,0xf5,0xb0,0x56,0x7f,0x51,0x63,0x16,0xef,0x86,0xb6,0x2e,0xfa,0x73,0x96,0x19, + 0x22,0x79,0x64,0x9d,0xaf,0x20,0x44,0x87,0x26,0x79,0x12,0xa7,0x8b,0x4a,0x77,0xe1, + 0xb1,0x72,0x6e,0x93,0x55,0xf7,0x80,0xb2,0x05,0xad,0xcb,0xeb,0x5d,0x33,0xfa,0x01, + 0xcf,0x0b,0xef,0x5f,0x99,0xd6,0xfb,0xbc,0xaf,0xa3,0x81,0x4e,0x4b,0x4f,0xe2,0x1f, + 0x50,0xbe,0x09,0xbb,0x68,0x31,0x3b,0xd4,0x40,0xf6,0xc3,0x16,0x3a,0x93,0xc7,0xcb, + 0x0e,0xe3,0xb1,0x9d,0xa9,0xd3,0x51,0x54,0x42,0xab,0x20,0xdf,0x53,0xe7,0x4d,0x4f, + 0xe2,0x1f,0xda,0xfe,0x6d,0x78,0x99,0x2d,0x40,0xd8,0x83,0x20,0xf3,0x19,0x56,0x7a, + 0xfa,0xa6,0x95,0xe2,0xbb,0xe4,0xb5,0xe6,0x59,0xd1,0xba,0x95,0x72,0x25,0xfc,0x89, + 0xfd,0xc8,0xe7,0x5c,0x2a,0xb6,0x26,0xf1,0xcf,0x94,0x90,0x70,0x21,0x96,0xed,0xc3, + 0xf9,0xd6,0x2a,0x23,0x3c,0x0d,0x95,0x18,0x44,0xd0,0x2e,0x71,0x94,0x5c,0x86,0x9f, + 0x6b,0xeb,0xcd,0xfc,0x00,0xbe,0xdc,0x97,0xe1,0x8f,0x46,0x37,0xd8,0x9a,0xfd,0xf4, + 0x28,0x73,0x9f,0x36,0xfa,0xa3,0x0d,0x18,0x8d,0x62,0x49,0x99,0x7e,0x94,0x55,0x85, + 0xe8,0x98,0xb8,0x34,0xb1,0xfe,0xcf,0xd3,0x0d,0xb0,0x2b,0x3b,0xbf,0x5f,0x6e,0x10, + 0x37,0xc3,0x1f,0xd5,0x5b,0x87,0xbb,0x78,0xbc,0xaf,0x79,0x72,0x7e,0x33,0x75,0x89, + 0x0d,0x1e,0xb4,0xc8,0x02,0xf4,0x3b,0xa4,0x28,0x31,0x9f,0x77,0x64,0xdd,0x17,0xcb, + 0xe7,0x1c,0xd5,0x9e,0x83,0xfb,0x79,0x63,0xdc,0x01,0xdc,0x53,0xd3,0xb9,0xe0,0x9a, + 0xca,0x56,0x41,0xb1,0xd0,0xf5,0xf0,0x31,0x29,0x19,0x1f,0x94,0x18,0x74,0xab,0x6a, + 0x50,0x2e,0x27,0x1d,0xb0,0x43,0x98,0xc1,0xe5,0xcf,0x61,0x3f,0xd3,0x50,0x11,0x54, + 0x90,0xc5,0x74,0xa3,0x8e,0x0b,0xbb,0xcd,0x63,0xca,0x8f,0x9a,0xa2,0x4b,0x9f,0x69, + 0xee,0xe7,0x11,0xc6,0x8c,0xb0,0x8f,0x85,0x02,0xae,0xbf,0x3e,0x81,0x48,0x75,0x99, + 0x6e,0xdd,0xd7,0x24,0x09,0x91,0x87,0x2a,0xeb,0x07,0x02,0x45,0xb6,0x64,0x7e,0x94, + 0xb0,0x05,0xe6,0x7b,0x2a,0x79,0x7e,0xf8,0x27,0x70,0xe3,0x44,0x7f,0x90,0xb1,0xea, + 0x79,0x7a,0x49,0x58,0x3c,0x95,0x31,0x0c,0x95,0x75,0x36,0xbf,0xd8,0x95,0x90,0x6f, + 0xf9,0x4a,0x18,0xde,0x85,0xd2,0xd7,0xf1,0x3c,0x5e,0xa5,0xaf,0x2a,0xbc,0x11,0xad, + 0x78,0x15,0x22,0xb4,0x6a,0xd8,0x1a,0x6e,0xba,0x44,0x8e,0x4f,0x72,0xf3,0x7e,0x22, + 0xf9,0xcb,0x27,0xe6,0x6f,0x91,0x96,0x41,0x6b,0xc8,0xde,0x2b,0x6f,0xf6,0xfc,0x05, + 0x5e,0x94,0x62,0xfa,0x4b,0x09,0xf4,0x97,0xf0,0x8e,0x81,0xa7,0x15,0x34,0x3d,0xca, + 0xe5,0xcd,0x7f,0x36,0xf3,0x63,0x2f,0x53,0x9e,0x52,0x3a,0x74,0xb9,0xc7,0x3f,0xc4, + 0xf9,0x94,0x8c,0x7c,0x1e,0x12,0xd0,0x4b,0xf4,0xf6,0x30,0x39,0x23,0xec,0x69,0x26, + 0x21,0xb9,0xeb,0x3a,0x35,0x89,0x7f,0xf0,0x1f,0xfe,0xca,0x30,0xea,0x3d,0xfd,0x8b, + 0xb7,0x42,0x28,0x02,0x3c,0x3e,0xc8,0x60,0x05,0xcb,0xe3,0x7c,0xc8,0x1b,0x78,0xbd, + 0x18,0x31,0xe1,0x73,0x1e,0x1f,0x3c,0xa1,0xb8,0x9b,0x8d,0x30,0xfa,0x21,0x98,0x3d, + 0x98,0xc9,0xe3,0x8f,0x11,0xb2,0x42,0x77,0x6e,0x37,0x3a,0x34,0x71,0x7e,0xec,0x36, + 0x35,0x3d,0x81,0x7f,0x7e,0x31,0x0a,0x23,0x85,0x55,0x8d,0xf8,0xbe,0xc7,0x11,0xdd, + 0x55,0xbd,0x6d,0xc4,0x07,0x2f,0xf1,0xb4,0x16,0x0e,0x84,0x46,0x38,0xbf,0x31,0xcb, + 0xe9,0x5a,0x9d,0xc4,0x3f,0xf1,0x6a,0xca,0x80,0xf8,0x85,0x72,0x84,0x55,0x45,0xd6, + 0x76,0x17,0xb8,0x39,0x3f,0x92,0x7a,0x77,0x44,0x1c,0x27,0x07,0x58,0x29,0x35,0xf2, + 0xbd,0x13,0xf3,0xdb,0x79,0x7e,0x78,0x8c,0x0d,0x80,0xb5,0xb1,0x59,0x43,0xf4,0x12, + 0xb1,0x2b,0x78,0x45,0xa5,0xed,0xe4,0xc3,0x46,0x94,0xcf,0x85,0xb4,0x87,0x03,0xbb, + 0x89,0xf3,0x9e,0xb6,0x36,0xde,0xed,0x9d,0x0c,0xa1,0x6c,0x72,0xea,0x96,0xd9,0x37, + 0x30,0x69,0x07,0x94,0x34,0x2e,0x84,0xec,0x68,0x6d,0x8b,0xa4,0x6e,0xc1,0x1d,0x42, + 0x84,0x89,0xf9,0xba,0xb4,0x2d,0x5e,0x4d,0xef,0x1f,0x51,0xdb,0x7c,0x25,0x7a,0x7d, + 0x98,0x84,0xf8,0x7f,0xf1,0x0e,0x5e,0x96,0xc8,0x5b,0x67,0xaa,0xf8,0x21,0xc2,0x89, + 0x7c,0x83,0xea,0x29,0x71,0x76,0xf4,0xb5,0x64,0x80,0xf3,0x1b,0xf7,0x2e,0x0e,0x17, + 0xbc,0xa0,0x5e,0xd4,0xf3,0xd4,0xac,0x9e,0xff,0x32,0xcc,0x5a,0xb2,0xdd,0x3e,0x67, + 0x58,0x54,0x12,0x78,0x2f,0x24,0xc4,0x69,0x9f,0x4f,0x89,0x97,0x24,0x5e,0xf6,0xd5, + 0x36,0x2a,0xfe,0x44,0xbb,0x4a,0x7e,0x0e,0xb8,0x31,0x3e,0x62,0x57,0xfd,0x15,0x7c, + 0xa1,0x52,0xf8,0xb1,0x63,0xf7,0x5f,0x25,0x3e,0x03,0x17,0xb4,0x0a,0xdd,0xea,0xca, + 0x99,0xa9,0x5d,0xe4,0x8d,0x0b,0x11,0x6f,0x6b,0x11,0xde,0x5a,0xbd,0x7b,0x52,0x0a, + 0x3f,0x64,0xec,0xf9,0xbb,0x78,0x98,0x38,0x30,0x2b,0x92,0x39,0x8a,0x86,0xc0,0x6e, + 0x6f,0x49,0x35,0xbe,0xd1,0x21,0xed,0x4d,0x86,0xfa,0xa8,0xcc,0xc4,0x0f,0xa9,0x4b, + 0x8b,0x63,0xeb,0x43,0xd3,0xfb,0xa5,0xb0,0xe4,0xe0,0xf5,0xec,0xcd,0xea,0x8e,0x6a, + 0xa7,0x26,0x3a,0x10,0x28,0x36,0xea,0x0e,0x8d,0xba,0xec,0xc9,0xfe,0x68,0x63,0xca, + 0x77,0x99,0xc1,0x06,0xb0,0x94,0xfc,0x01,0x76,0x32,0x67,0xb4,0x7e,0xfe,0x0d,0x4f, + 0x4d,0x36,0x32,0xc6,0xff,0x87,0xe7,0x5d,0xe9,0x17,0xe1,0x99,0x3e,0xca,0x0b,0x5d, + 0x27,0xee,0x5f,0x47,0xef,0xe6,0xfc,0x00,0xfd,0x36,0x59,0xec,0x87,0x73,0x50,0x11, + 0xa1,0xf3,0xe5,0x66,0xf8,0x4c,0xaf,0xe8,0x9f,0x54,0x24,0xea,0xe4,0xd5,0x50,0x39, + 0x73,0xce,0x37,0xfb,0x7f,0xa6,0xc4,0xd7,0xe7,0x18,0x0f,0xa3,0xd3,0xaa,0x41,0xdb, + 0xf6,0x9a,0x7a,0xb8,0xc8,0xf9,0x91,0xce,0x8a,0xe7,0x61,0xbb,0x34,0x97,0x77,0x0c, + 0x49,0xd6,0xc7,0x51,0xfc,0x5e,0xc6,0xfa,0xec,0x79,0x6e,0x31,0xef,0xf6,0x35,0x60, + 0xdb,0x25,0x76,0x06,0x1e,0x66,0xee,0x7b,0x6c,0xe5,0x39,0xe5,0x70,0x96,0x27,0x42, + 0x87,0xc5,0x83,0xc9,0xfd,0x90,0xc7,0xf3,0xc3,0x11,0xed,0xfc,0x93,0x7b,0xaa,0xb4, + 0x2a,0xab,0x58,0xcf,0x98,0x2d,0x4e,0x0d,0xbd,0x0c,0xb7,0xb6,0x2f,0xe2,0x88,0xe8, + 0x25,0xc8,0xaf,0x36,0xf2,0xc3,0x27,0xe6,0xab,0xf0,0x34,0x9d,0xcb,0x1e,0x88,0xca, + 0x57,0xc8,0x3f,0x49,0x4f,0x6c,0x29,0x9e,0x28,0x03,0x9c,0x39,0x2c,0xff,0x84,0xdc, + 0x00,0xfb,0x74,0x9e,0x3a,0x6e,0xaa,0x4f,0xa9,0x97,0x8c,0xfd,0xd6,0x2b,0xcf,0xf1, + 0x97,0xb0,0xc7,0x11,0xf6,0xdc,0xe9,0x22,0x6b,0xb5,0xee,0x66,0x5c,0xe1,0x0a,0xff, + 0xdd,0xda,0x76,0x9e,0x98,0xc7,0xf9,0x21,0x27,0xe6,0x0f,0x4f,0xe1,0x65,0x44,0x28, + 0x4f,0xb6,0x89,0x8f,0xb2,0xb7,0x8d,0xb2,0x38,0x79,0x18,0xae,0xe8,0xf3,0x58,0xdb, + 0x70,0x41,0xb9,0xf4,0x45,0xed,0x7f,0x67,0x06,0x3f,0xe4,0xc4,0xfb,0xd6,0x09,0xc9, + 0xb6,0x20,0x64,0x98,0x56,0x2a,0x99,0xcd,0xa8,0x3b,0xc7,0xf2,0x66,0x20,0xfe,0x89, + 0x65,0x10,0x11,0x5b,0x73,0x4a,0x7d,0x5c,0x67,0x2c,0x2d,0xea,0x29,0x5e,0x1d,0x8f, + 0xfa,0x7d,0xf1,0x0d,0xe2,0x72,0x75,0x5c,0xa8,0xf4,0xa6,0x3d,0xc9,0x15,0x1f,0xdb, + 0xc3,0x2b,0xe8,0xaf,0xe1,0x07,0x00,0xdc,0x2d,0x3d,0x08,0x63,0x9a,0x54,0xd5,0x1b, + 0xd8,0x2c,0xae,0x80,0xdd,0xd5,0x25,0xfa,0x9d,0x86,0xff,0x21,0xdb,0xe8,0xf7,0x11, + 0x35,0xe1,0x9f,0x42,0xd8,0x2d,0xf0,0x32,0xf6,0xec,0x21,0x4e,0xa3,0xed,0xa1,0xc1, + 0x8d,0xc6,0x1d,0x38,0x0d,0xd4,0x10,0x22,0xa8,0x22,0x5f,0x4a,0x7e,0xb8,0x81,0x7f, + 0x62,0xde,0x8f,0xd7,0x84,0x16,0x08,0x71,0x18,0x50,0x0b,0xdb,0x19,0xe7,0x87,0x24, + 0xaf,0xd1,0xdd,0xa0,0xfa,0xf0,0x27,0x3d,0x89,0x7f,0x0c,0x7e,0x80,0x12,0x83,0x8d, + 0x90,0x44,0x24,0xc3,0xdb,0xe3,0xe3,0x85,0x5a,0x70,0x93,0x41,0x8c,0x00,0xf3,0xf8, + 0x8b,0xbf,0x6b,0xe2,0x87,0x8c,0xa5,0x81,0x21,0xa8,0x36,0xf2,0xbd,0xbd,0xff,0xb2, + 0xc9,0x28,0x73,0x8b,0x33,0x06,0xa0,0xa1,0xe1,0xc5,0x41,0x2a,0x3f,0x40,0x3c,0x6d, + 0x6c,0xb9,0x36,0x1e,0xcb,0xbe,0x93,0xe8,0x65,0x04,0x8a,0x1c,0x41,0xa9,0x08,0xa5, + 0x38,0x3f,0xa4,0x89,0x1f,0x20,0x8f,0x67,0x43,0x19,0x6c,0x00,0x51,0x12,0x80,0x92, + 0x5c,0x79,0x15,0xef,0x0f,0x02,0xa4,0x51,0xe6,0x8d,0x62,0x7b,0x48,0x89,0xb2,0x88, + 0x59,0xd6,0x99,0xf1,0x4f,0xc6,0x44,0xf7,0x37,0xc6,0x89,0x79,0x71,0xc0,0x57,0xa0, + 0xcb,0xf0,0xff,0x74,0xe2,0x8b,0xf3,0xfc,0xf9,0xec,0x04,0xbe,0x6a,0x97,0x12,0xec, + 0x9a,0x1f,0x68,0x2d,0x86,0xdb,0xc7,0x82,0x2b,0xac,0x16,0xc5,0x13,0xd5,0x9a,0x4b, + 0xf8,0x7a,0x3e,0x6b,0xe2,0x87,0x9c,0x78,0xfe,0x7b,0xbe,0xcf,0xd9,0x6c,0xb4,0xa3, + 0x4a,0x4e,0x21,0x6e,0x7b,0xc3,0x8d,0x33,0x24,0x8c,0x43,0x49,0x3d,0x2e,0x85,0x29, + 0x3f,0x4a,0x88,0xef,0x07,0x4e,0x3b,0x90,0x74,0x04,0x05,0xca,0x78,0xbe,0xe5,0x9f, + 0x05,0x9e,0x3a,0xb5,0x1e,0xf1,0x8f,0x89,0x5f,0x3d,0xb9,0xdf,0xa4,0x13,0x42,0x25, + 0x59,0xcc,0xda,0x78,0xa2,0x54,0x25,0xb5,0x35,0x8a,0x51,0x65,0xac,0x19,0xbf,0x48, + 0x20,0xa5,0x3e,0xce,0x01,0x7b,0x78,0x5a,0x78,0xa7,0x18,0x80,0x56,0x36,0x2b,0x68, + 0x1d,0x26,0xcf,0xc3,0x3a,0x7f,0x56,0x40,0xee,0xb2,0x8f,0xa9,0xfb,0x59,0x01,0x0b, + 0x9c,0x36,0xf7,0x07,0x91,0x16,0x0b,0x86,0xfc,0x71,0x73,0x76,0xbe,0x51,0xe7,0xa0, + 0xe3,0x56,0xb2,0x9e,0x6d,0x55,0x8c,0x85,0x42,0x43,0x55,0x08,0x45,0x03,0x9c,0x1f, + 0x32,0xa1,0xef,0x94,0xfb,0x62,0xe7,0xf7,0x91,0x3b,0x36,0xa3,0xf6,0x77,0x46,0x2d, + 0x08,0x84,0xd4,0x35,0xf0,0x80,0x2e,0x22,0x90,0x50,0x5e,0x09,0xa8,0xa3,0x11,0x8d, + 0x0c,0x27,0xe6,0x07,0x02,0xdf,0x45,0xfb,0x05,0xf1,0xcf,0xd2,0x9c,0xab,0x9e,0x37, + 0xd8,0x02,0xde,0x28,0xe4,0x69,0xf8,0xb3,0xff,0x26,0xbc,0x52,0x70,0x0c,0xbe,0x34, + 0x5a,0xa7,0x89,0x1f,0xcd,0x98,0x98,0x4f,0xa7,0xc4,0xe5,0xc9,0x2f,0x39,0x1e,0xf0, + 0x55,0x32,0x4e,0x0b,0xc9,0x2e,0x0a,0x86,0xa2,0x3f,0x1f,0x6b,0x04,0x16,0xcc,0x31, + 0xf1,0x03,0x48,0xfb,0x8d,0xfe,0x20,0xb6,0x4b,0xdf,0xb8,0x92,0x7b,0x55,0xc7,0xc1, + 0x52,0xf1,0x15,0xb8,0x1a,0xfc,0xf9,0xf9,0x25,0x27,0x6a,0xe6,0xc1,0x1b,0x7e,0x83, + 0x28,0x09,0x12,0xfb,0xe7,0x85,0xbc,0xb5,0xda,0x2e,0xce,0x06,0x89,0xf8,0x27,0x80, + 0x2f,0xc2,0xeb,0xdd,0x14,0xf5,0x89,0x1e,0xbc,0xa2,0x88,0x8f,0x78,0x57,0x6f,0xcf, + 0xef,0x5f,0xe4,0x25,0x45,0xcd,0x89,0xfb,0xc3,0xe6,0x3a,0xe3,0x7d,0xff,0x1b,0x9a, + 0x69,0x2f,0xe3,0xc0,0xa2,0x11,0x94,0x60,0x85,0xc5,0x20,0x0f,0xfa,0x15,0x58,0xef, + 0xb9,0x9f,0xd7,0xf3,0x9a,0xf8,0x91,0xa4,0x18,0xbb,0x4b,0x9b,0x8b,0x3c,0xa6,0x76, + 0x6b,0x4e,0x8d,0x02,0x5a,0x37,0x8f,0x83,0x73,0xb2,0xac,0xf8,0xbf,0x0f,0x7e,0x09, + 0xe5,0x8f,0x62,0xe2,0x47,0xea,0x9a,0xc2,0xb3,0x49,0x4b,0x74,0x5b,0x8f,0x78,0x99, + 0xee,0x85,0x0a,0x2d,0x2b,0x54,0xf0,0x9c,0x36,0xc6,0x4a,0x1c,0x6b,0xda,0xc5,0x62, + 0xcf,0x21,0xf6,0xf0,0x25,0xdc,0x21,0x45,0x89,0xfd,0xc3,0x84,0xf8,0xfa,0x6c,0x10, + 0x7f,0xcb,0x37,0x92,0x9e,0xa5,0xd6,0x8c,0xd0,0xb7,0xc8,0xbc,0xbc,0xf5,0xc1,0x9c, + 0x0f,0xb4,0x71,0x65,0x3f,0x6f,0xe4,0x14,0x4d,0xec,0x9f,0x7c,0x25,0x2e,0xcf,0x2f, + 0x88,0xfb,0xa4,0xa3,0x28,0xaf,0xac,0x83,0xe2,0x3f,0x29,0x97,0x60,0x16,0x6f,0x1c, + 0x76,0x1e,0x0e,0xf3,0xfe,0x5f,0x83,0x22,0xd4,0x4e,0x3c,0xff,0x16,0x69,0x85,0xa1, + 0xbf,0xda,0x36,0x93,0x91,0xbc,0x43,0xc1,0x12,0x46,0x7f,0x75,0xdd,0x36,0xe8,0x61, + 0x25,0xfa,0xa2,0x1e,0xf2,0x67,0xd2,0xc8,0x54,0xa0,0xb9,0xe6,0xfe,0x68,0x42,0x5c, + 0xdf,0x75,0xe2,0xfe,0xc1,0xf3,0x02,0x8e,0x90,0xbd,0xb0,0x79,0x0f,0x2b,0x51,0xe4, + 0x0d,0xe4,0x53,0xb5,0xad,0xd1,0xee,0xa3,0x9b,0x3d,0xe6,0xfe,0x68,0xd6,0x38,0x1e, + 0xf0,0x0c,0x20,0xda,0x71,0xaa,0x54,0x25,0x8c,0xb7,0x81,0x00,0xc3,0x10,0x0b,0xdc, + 0xaf,0xfa,0x1c,0xe6,0xfe,0x44,0x24,0x73,0xc5,0x52,0xe3,0x7d,0x9f,0x11,0xf7,0xc5, + 0xba,0x31,0xae,0x92,0x0b,0xa5,0x0b,0x0f,0xe3,0x89,0x78,0x49,0x1c,0xa2,0x87,0x7c, + 0x68,0xb1,0x6e,0x12,0x93,0xfd,0xd1,0xb6,0xdc,0x74,0xc9,0x6a,0xbc,0x6f,0x9f,0x78, + 0x89,0x8e,0xc0,0xcd,0x60,0xd3,0x73,0x46,0xe9,0x05,0xad,0x0a,0x6c,0x0f,0xe3,0xfb, + 0x5e,0x50,0x8c,0x7e,0x70,0xc3,0x49,0x7f,0x8e,0x70,0x05,0xfe,0xb4,0xaa,0x34,0xc3, + 0xa6,0x17,0x9c,0xd7,0xbf,0x64,0xb1,0xb6,0x20,0xea,0x51,0x1c,0xf0,0xfa,0x02,0x7a, + 0x72,0x66,0x69,0xbe,0x55,0x4f,0xed,0x0f,0x2b,0xf5,0xb0,0x19,0x0b,0xe5,0x76,0xcf, + 0x29,0xcd,0xc8,0x96,0xef,0x41,0x43,0x95,0x27,0x8a,0xd3,0x1e,0x32,0xd2,0x1c,0xf0, + 0xd9,0x55,0xda,0x64,0x49,0xe1,0x47,0x42,0x04,0xbd,0xdc,0xba,0x48,0xe0,0xde,0xad, + 0x58,0xd9,0x7b,0x24,0x56,0xef,0xe6,0x22,0x23,0xea,0x06,0x8b,0x9d,0x51,0x33,0x3f, + 0x09,0xe7,0x47,0xda,0x4d,0xce,0xf8,0xe4,0x76,0x78,0x1f,0xe2,0x34,0xe3,0x9f,0x92, + 0xd6,0xec,0x8e,0x5e,0x23,0xdf,0xbe,0xc5,0x7f,0xda,0xe8,0x0f,0x92,0x8c,0x8f,0xe0, + 0xfe,0x41,0x23,0xe8,0x21,0xdb,0xda,0xad,0x23,0xd2,0xc5,0x58,0xd9,0xfe,0xfb,0xfe, + 0x48,0xc4,0x7d,0x0c,0x61,0xcf,0x80,0xef,0x44,0x28,0xfc,0xed,0xc5,0x6b,0x0b,0x94, + 0x14,0x7e,0x80,0x9f,0x06,0xe7,0x73,0xb1,0x33,0x3a,0xd1,0xff,0xa2,0x5f,0xba,0xcc, + 0xaa,0x8e,0xd9,0x46,0x6b,0xae,0xd0,0xcf,0xb9,0xc7,0xcc,0xdb,0x94,0xda,0x1f,0xed, + 0x00,0x45,0x6d,0xfe,0x78,0xc1,0x03,0x08,0x03,0x8c,0xfb,0x7f,0x02,0x07,0x95,0x6e, + 0xdd,0xf0,0xff,0x7c,0x04,0xee,0xde,0x25,0xcf,0xa4,0xf0,0x43,0x3a,0x81,0x44,0xec, + 0xdf,0x14,0x37,0x93,0x7c,0xed,0xfd,0x18,0xad,0xc4,0xa7,0xcc,0xcf,0xe6,0x9c,0xa3, + 0xdd,0xe4,0x2f,0xb5,0x2d,0x5e,0xfb,0x26,0x79,0x73,0xcd,0xc3,0xa6,0xf8,0xd7,0x62, + 0x60,0xba,0x1a,0x5c,0xe4,0x82,0x66,0x61,0xc7,0x80,0x91,0xcf,0xdc,0xcb,0x18,0x53, + 0x83,0x94,0xd7,0x73,0x75,0x28,0x85,0xb0,0x48,0x25,0xa9,0xfc,0x48,0x8f,0x05,0xbf, + 0xef,0x93,0x97,0x5a,0x9e,0x16,0xe2,0x6d,0x41,0xde,0xd5,0x9a,0x07,0xb7,0x86,0x78, + 0xd8,0x4b,0x5a,0x15,0xc4,0x2b,0x6f,0x11,0x33,0x3f,0xa4,0x15,0x7a,0xc1,0x35,0xb8, + 0xc4,0x9d,0xdd,0xcc,0x3e,0x03,0x57,0x14,0xcd,0xa8,0x08,0x39,0x34,0x59,0xd5,0x9d, + 0x2e,0xb1,0x5f,0x1d,0x56,0xe6,0x08,0xa8,0xaf,0xcd,0xfc,0x48,0x9b,0xc9,0x79,0x98, + 0xaf,0x2f,0x19,0x14,0x2b,0x62,0xeb,0x63,0x94,0xc5,0x29,0x0b,0xfa,0xf1,0xc5,0x4f, + 0x48,0x97,0x95,0xbd,0xaf,0xe3,0xd2,0xa5,0xf0,0x03,0x08,0xe3,0x7e,0xce,0x46,0x2e, + 0x6e,0x83,0x43,0x13,0x65,0x1a,0x3a,0xb8,0x86,0x8d,0xfa,0xc1,0x23,0x68,0xff,0x5e, + 0xd3,0x1f,0x76,0x73,0xda,0xcb,0x52,0xbe,0x66,0xa4,0x59,0x7e,0x19,0xa3,0x05,0x38, + 0xc9,0xf3,0x06,0x6a,0x51,0x90,0x9e,0x24,0x8f,0xa5,0xe5,0x0f,0xc8,0x5e,0x4b,0x6a, + 0x7f,0xb4,0x7d,0xfe,0x99,0x1c,0xef,0x1d,0x31,0xe2,0x7d,0x46,0x5b,0xd8,0x75,0xac, + 0x80,0xbf,0xef,0x17,0xb0,0x9a,0xfd,0xc0,0x27,0x5f,0xc3,0x8f,0x24,0xec,0x18,0x74, + 0x9c,0x90,0xa7,0xa4,0x8f,0x68,0x8f,0xc7,0xea,0x7d,0x0e,0x6b,0x6d,0x4c,0xb5,0x52, + 0xce,0x4f,0xd2,0xe2,0xad,0x1f,0x94,0x37,0x91,0x6b,0xf8,0x91,0x94,0xf9,0xc1,0x25, + 0xc3,0xe2,0x18,0xa7,0x35,0x30,0xd0,0x0e,0x1c,0x19,0x75,0x07,0x9d,0x46,0xa1,0x9c, + 0xbe,0xa7,0xd9,0xf6,0x61,0x53,0x2a,0x3f,0xd2,0x98,0xf0,0x4b,0x58,0xbf,0x1a,0x4e, + 0xc5,0x15,0x53,0x41,0xd4,0x3e,0x26,0xec,0x57,0xb8,0x86,0xa2,0x63,0xf6,0x19,0xc2, + 0x35,0xf8,0xc7,0xd0,0x8f,0xcb,0x6d,0x1b,0x72,0x86,0xb4,0x03,0x8c,0xd7,0x4f,0x15, + 0xbc,0x46,0x0e,0x4c,0x76,0x47,0x71,0x19,0x9f,0xe5,0xfd,0x41,0xaa,0x11,0x1a,0x11, + 0x33,0xfe,0x91,0x38,0x7a,0x91,0x37,0x93,0x33,0xec,0xf9,0xc0,0x44,0x9b,0x57,0x66, + 0x5f,0x89,0xf2,0x61,0x86,0xbd,0x85,0x9b,0x5a,0x4f,0xa5,0xe6,0x87,0xc3,0x5e,0xca, + 0x8b,0xe0,0x3c,0x38,0x4d,0x9d,0x98,0x0f,0x46,0x44,0xac,0x53,0x8b,0x0f,0x52,0xfb, + 0xc3,0x1a,0xf5,0x71,0x88,0x76,0xa4,0x2d,0x71,0x20,0x04,0x8d,0xb5,0x21,0x23,0x22, + 0x86,0x86,0x3f,0xe2,0x9f,0x5c,0x7b,0xd2,0x1e,0x31,0xf8,0x91,0x38,0x1f,0x54,0x08, + 0xdf,0x2e,0x92,0x6c,0x0b,0xeb,0x8e,0x15,0xca,0xc5,0xf9,0x21,0xcd,0xf9,0xe1,0x43, + 0xf8,0x59,0x67,0x79,0x97,0x4c,0xf0,0x43,0xda,0x82,0xc2,0xe7,0xbc,0x11,0x21,0x0e, + 0x6a,0x8e,0xc7,0xa8,0x93,0x1e,0x49,0xc1,0x3f,0xe7,0xe1,0xf3,0xf4,0x4a,0x4f,0xd6, + 0x60,0x13,0x0e,0x62,0x40,0xe8,0x73,0xc6,0x19,0x23,0x51,0x2c,0xff,0x37,0xf8,0x93, + 0x03,0x81,0xd0,0xb1,0xa6,0x19,0x29,0xfc,0x00,0x3d,0x42,0x49,0x3b,0x6d,0x26,0x28, + 0x71,0x62,0x40,0xe8,0x14,0x84,0xa1,0x43,0xa0,0x8c,0xa8,0x81,0x56,0x9f,0x1d,0xe4, + 0xd5,0x24,0x85,0x1f,0x89,0xe3,0x3d,0xcf,0x42,0x25,0xfd,0xb5,0xd0,0x8e,0x78,0xd8, + 0x4b,0x47,0x18,0xac,0xd5,0xf1,0xc4,0xef,0x0d,0x46,0xc6,0xb8,0x3f,0xb5,0x3f,0xda, + 0x6e,0xc5,0xa9,0x59,0xda,0x3d,0x43,0xd2,0x04,0x10,0x0a,0x6c,0x57,0x3b,0xbc,0x34, + 0x98,0x3d,0xbd,0xf9,0xc9,0x6c,0x94,0x78,0x1b,0xcd,0xfc,0x48,0xb9,0xbc,0x1b,0x5a, + 0xa5,0x2f,0xeb,0xa9,0x94,0x32,0x7f,0xdd,0xcd,0xf9,0x01,0xfe,0x0b,0xbc,0xa5,0xb9, + 0x11,0xcf,0xc8,0x8e,0x84,0x7c,0xe8,0x02,0x83,0x1f,0x29,0xf2,0x58,0x0a,0x8d,0x12, + 0xe2,0xe1,0xd8,0xe0,0x14,0xdd,0xcf,0xa9,0x96,0x3e,0x4a,0xec,0x67,0x83,0x1f,0x09, + 0x8d,0xdc,0x25,0x2c,0x27,0x2a,0x45,0x48,0x9c,0x16,0x20,0xa2,0x75,0x23,0x10,0x6d, + 0xc2,0x2f,0xa2,0x55,0xc2,0x12,0x7f,0x8d,0x89,0x1f,0x52,0x72,0xc0,0xfe,0x46,0xe2, + 0x37,0xba,0x8f,0xac,0x53,0x62,0x6d,0x41,0xf4,0x75,0x90,0x1f,0xa4,0x51,0xf2,0xce, + 0x0f,0xd7,0x31,0x84,0x46,0x1f,0x11,0xcb,0xc4,0x71,0x07,0x27,0xca,0x9f,0x1d,0x42, + 0x61,0x44,0x94,0xc9,0x51,0xe6,0xd7,0x0c,0x5a,0xb6,0x23,0xd0,0x14,0x50,0x23,0xb8, + 0x9e,0xaf,0x91,0x46,0xdd,0x19,0x95,0xa7,0xa6,0xe4,0x87,0x4f,0x85,0x97,0x02,0xd3, + 0xf5,0x36,0x1f,0x79,0x87,0x36,0x33,0xa3,0xbe,0xe3,0x5d,0xb2,0x86,0xe6,0x33,0x5a, + 0x4b,0x4e,0xd0,0x66,0x4b,0x71,0x1f,0xe2,0x01,0x9a,0xc4,0x57,0x74,0x1a,0x7c,0xd1, + 0x78,0x6b,0xa7,0xad,0xae,0xe0,0x20,0xbc,0xc6,0x76,0xf3,0xf8,0xd7,0x15,0x78,0xa3, + 0x71,0xb6,0xea,0xac,0x13,0xbf,0xc0,0x2b,0x0b,0x78,0x7e,0xb8,0xc5,0xcc,0x8f,0x94, + 0x87,0xa0,0x3a,0x60,0x94,0x69,0x8c,0x4d,0xc8,0x93,0x8b,0x02,0xef,0xc8,0x63,0xf0, + 0xfb,0x55,0x2a,0x88,0x87,0x4d,0xf1,0xaf,0x29,0x57,0xf8,0x7a,0x0e,0xad,0x39,0x31, + 0xe9,0x8c,0xf6,0x09,0xcb,0x8e,0x25,0x8a,0x1f,0xf5,0xcf,0x0e,0x59,0xc7,0xf1,0xfe, + 0xef,0xb1,0xaa,0xd1,0x25,0x11,0x53,0x7d,0x74,0xd7,0xf5,0x9b,0xe1,0xa5,0x9d,0xc5, + 0xfb,0xf0,0xb1,0x8f,0xa9,0x3b,0xc1,0x11,0x5d,0xd4,0x40,0xc6,0x60,0xb5,0x94,0x1f, + 0xa1,0xdf,0x24,0x6f,0x41,0xbf,0xc4,0xfb,0x13,0xa5,0xf0,0x63,0x6f,0x86,0x9d,0xf0, + 0x00,0xc5,0x97,0x3a,0x41,0x9f,0x89,0xe7,0x87,0xab,0x6b,0x94,0x7c,0xa8,0x6b,0x20, + 0xe7,0xb5,0x27,0xf2,0x8a,0x5f,0x97,0x35,0x53,0xbd,0x80,0x4f,0x1a,0x90,0xc2,0xb0, + 0x82,0xde,0x98,0x9d,0x1e,0xc1,0x6d,0xe9,0x88,0xb5,0x79,0x62,0x83,0x06,0x0d,0xe0, + 0xd1,0xa0,0x9f,0x39,0x83,0x72,0xda,0x3d,0x79,0x89,0xfd,0xe9,0x40,0xbc,0x87,0xdb, + 0x46,0x59,0xb2,0x96,0x77,0x77,0x8d,0xe9,0xaf,0x4f,0xc8,0x21,0x70,0x0f,0x3b,0x15, + 0x71,0x88,0xbd,0xa5,0x57,0x86,0x6c,0x3d,0xb2,0x25,0xa5,0x3f,0xec,0x18,0xab,0xcc, + 0xb5,0x75,0x09,0xc3,0x2c,0xbe,0x3e,0xc3,0xdc,0x3f,0x0f,0x47,0x37,0x89,0xc3,0x74, + 0xf8,0xfe,0xca,0x41,0x5b,0xf8,0x71,0x73,0x7f,0xb4,0x4b,0x70,0x89,0xfe,0x58,0xb5, + 0x72,0x92,0x9f,0xcb,0x31,0x5a,0xec,0xf3,0xf6,0xc3,0x33,0x0d,0xd8,0x33,0x87,0x1c, + 0x86,0x2a,0x8b,0xed,0xef,0x44,0x35,0xe1,0xff,0x69,0x44,0xfc,0x83,0xc7,0xaa,0xd0, + 0xb1,0x4d,0x7b,0x5f,0x0a,0x1b,0xb4,0xcc,0xe4,0x34,0x20,0xec,0xe1,0xfe,0x8d,0x26, + 0xa5,0x45,0x2f,0x71,0xc9,0x6b,0xfd,0xe6,0xfe,0xb0,0x2b,0xb8,0xbf,0x9a,0xd1,0x5f, + 0xc2,0x69,0x75,0x42,0x5f,0xab,0x6d,0x60,0x0f,0xd1,0x5f,0x7a,0x66,0x40,0x9b,0xce, + 0xa9,0xcc,0x88,0xc9,0xff,0x03,0x56,0x08,0x17,0x3a,0x5b,0x28,0x78,0xf4,0xe6,0xb0, + 0x5f,0x35,0xf2,0xc3,0x49,0x2b,0x18,0x7c,0x1d,0x21,0xde,0x4a,0x0c,0xcf,0x63,0x91, + 0x29,0xc3,0x8b,0xae,0x80,0x31,0xc7,0x3c,0x6a,0xb4,0x45,0x1e,0x87,0xee,0xb7,0x8d, + 0xc6,0x70,0xaf,0x72,0x43,0x2c,0x18,0x8b,0xff,0xa2,0x68,0x2a,0x50,0x4d,0xf1,0x2f, + 0xc3,0xdb,0x23,0x4d,0xd2,0xc5,0x51,0xed,0x3c,0x54,0x1d,0xe4,0xef,0x1b,0x0b,0x84, + 0x0d,0x8a,0x83,0xf4,0x12,0xe1,0xfd,0x61,0xbf,0x65,0xe6,0xc7,0x8e,0xfb,0x7f,0xc6, + 0x73,0x2a,0xc8,0xd3,0xbe,0xd2,0xc8,0x4d,0x11,0xe1,0x3e,0x6d,0x80,0xdd,0xac,0x4e, + 0x3a,0x27,0x56,0x44,0xae,0x2a,0xf9,0xaa,0xf5,0x64,0x0a,0xfe,0x19,0x09,0x19,0x6c, + 0xcf,0x61,0xb2,0xc0,0x1b,0xa8,0x2e,0x88,0x5a,0xba,0xec,0x97,0xf5,0x00,0x7b,0x30, + 0x24,0xff,0xc9,0x52,0x51,0xbb,0xf7,0x9b,0x76,0x4a,0xb3,0x53,0xf9,0x21,0x63,0x78, + 0x2f,0x48,0xac,0xc0,0x5c,0xa1,0x41,0x4e,0x4b,0xa2,0xe0,0x6b,0x56,0x1f,0x52,0x97, + 0x59,0x9b,0xbb,0xd5,0x65,0x96,0xba,0xec,0xf4,0x6b,0xfa,0xc3,0x42,0x49,0xaf,0x1c, + 0xb6,0x38,0xa1,0xd5,0x6a,0xd7,0x2d,0xdd,0xfe,0x11,0x12,0x60,0x25,0xfd,0x62,0x17, + 0x71,0x22,0x10,0xb5,0x2b,0x88,0x3f,0xcd,0xf8,0x67,0x45,0x0c,0x0f,0x97,0x8b,0x56, + 0x23,0x1b,0x07,0xad,0xa1,0x91,0x8c,0x43,0x7a,0x89,0xdb,0x66,0x74,0x8c,0x0d,0xb9, + 0x14,0xe7,0x06,0x53,0x7d,0x5c,0x34,0xee,0xff,0x59,0x7f,0x8e,0x77,0x37,0x83,0x05, + 0xbd,0xb6,0x48,0x13,0xe7,0x87,0xfc,0xb9,0x6a,0xf3,0x71,0xfe,0x79,0x5a,0x95,0x8d, + 0xf6,0x42,0x2a,0xfe,0x89,0xb3,0xd3,0x3b,0xd9,0x01,0xad,0x2c,0x82,0x68,0x73,0x84, + 0xff,0x87,0x34,0x23,0x03,0xff,0xa0,0x72,0x4e,0x75,0x6e,0x4a,0xc5,0x3f,0x0a,0xc7, + 0xc3,0x88,0xd6,0x2a,0xa0,0x15,0x0a,0x06,0xeb,0x36,0xfb,0x2f,0x6b,0x2f,0x0e,0xda, + 0xff,0x49,0x0e,0xa5,0x5f,0x92,0x5a,0xf5,0x32,0x17,0x6e,0x24,0x33,0x3f,0xe4,0x62, + 0xca,0xd7,0x27,0xc3,0x45,0xee,0x92,0x5a,0xa1,0x70,0x90,0x52,0xcf,0xa7,0xd0,0xa8, + 0xab,0x2e,0xdc,0x18,0x8f,0x31,0x54,0xdc,0x6f,0xde,0xe9,0x58,0x68,0xe2,0xc7,0xae, + 0x9e,0x66,0xb0,0x41,0xd2,0x1f,0x93,0x69,0x34,0x97,0xa9,0xa7,0xf2,0x7e,0x48,0xde, + 0x3d,0xf5,0x4c,0x20,0xbf,0xf3,0xc6,0xbf,0xf3,0xbc,0xab,0xad,0x09,0x3f,0x13,0xcd, + 0x58,0x71,0x0d,0xfe,0x41,0xa3,0xa9,0x1f,0x9f,0xdf,0xca,0x74,0x61,0x4e,0xc4,0x6a, + 0x21,0x47,0x58,0x6f,0xb6,0x0b,0x6c,0x20,0x0e,0x80,0xde,0xe9,0xd2,0xff,0xb3,0xfa, + 0x6a,0x0a,0x3f,0x36,0x5f,0x9f,0x5e,0xdb,0xa8,0xe7,0x32,0x7c,0xa4,0x54,0x71,0xe0, + 0x3d,0x02,0x9f,0x2b,0x95,0x8d,0xb6,0xfe,0x9c,0x4b,0x64,0x6c,0xce,0x2b,0xfd,0x59, + 0x1f,0xa6,0xf0,0x63,0x7f,0x8a,0xa7,0xb5,0xb2,0xd7,0xd6,0x63,0xfb,0x49,0xa4,0x95, + 0x97,0x61,0xee,0x28,0x18,0xd1,0x5b,0xa0,0xf2,0x9c,0xf5,0x92,0xb8,0xc2,0xb7,0x90, + 0xd8,0xf5,0xbb,0x42,0x35,0x66,0xfc,0xc3,0x69,0xb1,0x39,0xec,0x99,0x61,0x85,0xd7, + 0x84,0xe2,0x7e,0xf9,0x61,0x32,0xe0,0x58,0x03,0xb3,0x7a,0x33,0x7d,0xb8,0x43,0x9e, + 0x85,0x02,0xdd,0x71,0x6d,0x7f,0x58,0x03,0xf6,0x8c,0x91,0xa7,0xdb,0x9b,0xfd,0xc5, + 0xa7,0xc4,0x47,0xc9,0xbb,0xfe,0x27,0x1a,0x67,0x9d,0xa7,0x79,0xfe,0x69,0xcd,0xcd, + 0xbd,0xf9,0x5f,0xe5,0x87,0xe4,0xf5,0x3e,0x8b,0x6e,0x23,0x6b,0x49,0x1b,0x0e,0x6e, + 0xbc,0x8d,0x8c,0xa4,0x23,0x10,0x1a,0xce,0xa0,0xad,0x4e,0xa1,0x8b,0x17,0xaa,0xa8, + 0xd7,0xe0,0x9f,0x38,0xec,0x19,0x96,0xee,0xe6,0xfe,0x9f,0x4e,0x1c,0xfc,0xa1,0xb3, + 0x24,0xb4,0x36,0x9a,0xee,0x80,0x23,0xac,0x9b,0x65,0x86,0xe4,0x6b,0xf0,0x8f,0x01, + 0x03,0x2c,0x9a,0x32,0x4c,0xb3,0x62,0xfa,0x88,0xa7,0xfd,0x2c,0x31,0x0a,0xe7,0x9b, + 0xf7,0x73,0xfe,0x8d,0xaf,0xe0,0x9f,0x58,0x59,0xdc,0x01,0x28,0x5b,0xbe,0x24,0xf8, + 0xea,0x07,0xf0,0x96,0xdf,0x08,0xf4,0x7c,0x00,0x07,0x54,0x77,0xfd,0xdd,0x41,0x99, + 0x5c,0xeb,0xff,0x89,0xc3,0x18,0xc9,0xee,0xe3,0xb4,0x6c,0xd0,0x12,0xb4,0xf3,0x13, + 0x34,0x64,0x7d,0x8b,0xa9,0x3e,0xfa,0xcb,0x6b,0xf0,0x4f,0x7c,0xfe,0x19,0xee,0x1d, + 0xd5,0x10,0xdd,0xf1,0x42,0x39,0x5e,0xd8,0x95,0xfe,0x01,0xbf,0xe2,0xfd,0xe1,0xd2, + 0x6b,0xfa,0xc3,0x22,0x1e,0xe0,0x45,0x70,0x6f,0x10,0x61,0xa2,0x2d,0x5a,0x1b,0x44, + 0x71,0x60,0x7f,0x0d,0x36,0xe8,0xf9,0x5e,0x7a,0xaf,0x25,0x69,0x7f,0xf5,0x58,0x13, + 0xfc,0x00,0x51,0xa5,0x0e,0xca,0xa0,0x8d,0xa1,0x98,0x3d,0x61,0x28,0xe2,0x1c,0x8e, + 0x88,0xba,0xe1,0x6e,0x4d,0x34,0xe1,0x9f,0xcc,0xce,0x89,0xb6,0x68,0xbc,0x1b,0x48, + 0x65,0x9c,0x16,0x80,0x5f,0x39,0x2e,0x7e,0x20,0x7d,0x5e,0x1d,0x23,0xc6,0x4c,0xc8, + 0x9f,0xf6,0xb4,0x4e,0x85,0xbb,0x89,0xb2,0x36,0x89,0x9f,0x4b,0x07,0xd4,0x2a,0xde, + 0x88,0xf9,0x73,0xf5,0x70,0xac,0x7f,0xdc,0xad,0xf0,0xb9,0x6b,0x47,0x6d,0x66,0x30, + 0xa5,0x3f,0x6c,0x94,0xf5,0x70,0x5a,0x24,0x0e,0x7b,0xba,0x1c,0x31,0x7e,0x6c,0xa9, + 0x0b,0x3a,0x0c,0x31,0x2b,0xf4,0x3c,0x82,0xf2,0x87,0x90,0x75,0x49,0xf9,0x23,0xf5, + 0xab,0xf8,0xbe,0x75,0x96,0x6c,0xf2,0x1a,0x6b,0xd4,0x56,0xa0,0xfc,0xf1,0xd4,0xf2, + 0x8e,0x3c,0xb8,0x50,0x96,0x18,0x55,0xe6,0x35,0xfc,0x90,0xdc,0xff,0x83,0xf8,0x67, + 0x43,0x36,0xa7,0xe5,0x7c,0x90,0x87,0xbd,0x86,0x0c,0x7e,0x86,0x1b,0x79,0x62,0xd5, + 0x6e,0xb5,0x83,0x0b,0xea,0xd5,0x29,0xfc,0x90,0x46,0x77,0xd7,0x18,0x2d,0x52,0x85, + 0x66,0x0d,0x36,0x2d,0x87,0xde,0x46,0x77,0x5d,0x8d,0x52,0x5a,0x28,0xed,0xa6,0x6e, + 0xed,0x3f,0x73,0xfc,0x93,0xd0,0xbf,0x71,0xff,0x0f,0x0f,0x83,0xaa,0xdc,0xff,0x73, + 0x94,0xf3,0x85,0x8e,0xeb,0x95,0xd5,0x31,0xa2,0x24,0xb6,0xdf,0xf3,0x4a,0x58,0xbc, + 0x86,0x1f,0x72,0x62,0xfd,0x71,0x20,0xac,0x6f,0x6e,0x52,0xa5,0x13,0xf1,0xfe,0x74, + 0xca,0xd8,0x9d,0x6e,0x1e,0x81,0xb5,0x7c,0xc5,0xff,0x23,0x86,0xb4,0x0b,0x38,0x98, + 0xc5,0xd0,0x30,0x9f,0xc7,0xd6,0x4d,0xb6,0xaf,0x31,0x80,0xd0,0xfe,0xc5,0x05,0xc1, + 0xbc,0x90,0xb8,0x30,0x85,0x1f,0x92,0xcb,0x9f,0x1b,0x5d,0xe4,0x2f,0xdc,0x71,0x71, + 0x4c,0x9e,0x43,0x32,0xfd,0x1b,0xfa,0xd4,0x68,0xab,0x2b,0xfd,0x88,0xb0,0x47,0x5a, + 0xa6,0x17,0xcd,0x4f,0xe1,0xc7,0x9e,0xaa,0xf1,0x7e,0x61,0x6d,0x1c,0x06,0x18,0x8e, + 0x91,0xb1,0x8d,0x53,0x85,0xc7,0x68,0xac,0xd0,0x55,0x30,0x1a,0xa7,0xfa,0x52,0xf8, + 0xb1,0xa7,0xb1,0x2f,0xd9,0x82,0xd3,0x9c,0x0d,0x40,0xf9,0xb2,0x8b,0x07,0xc2,0x9a, + 0xb2,0xa4,0xbf,0x61,0xf9,0xa7,0xb3,0x78,0xa1,0xdc,0x97,0x8d,0xa5,0xa1,0x59,0x4b, + 0xc5,0x14,0x7e,0x6c,0xee,0x0f,0x89,0xd8,0x8c,0xb4,0x1f,0x4f,0x89,0x51,0xed,0xce, + 0x25,0xd8,0x09,0xa3,0x63,0xc8,0x5e,0xb2,0x9f,0xa1,0x7d,0x61,0xee,0x0f,0xfb,0x69, + 0xdc,0xff,0xd3,0xe4,0x86,0xa3,0xed,0xff,0x7d,0xc8,0x7a,0x40,0xbc,0x62,0xfd,0x4b, + 0x68,0xee,0x72,0xdb,0x6e,0xb1,0x12,0x7f,0x2a,0xdd,0x76,0xd7,0xe5,0x02,0x13,0xfe, + 0x99,0xfc,0x34,0xa7,0x75,0xd2,0x6d,0x0d,0xf6,0x5c,0x6d,0x4d,0xe0,0x56,0x66,0x29, + 0x27,0x07,0xd9,0xea,0x40,0x7e,0x48,0x5e,0x29,0xde,0xa4,0x84,0x83,0x5b,0x9a,0x1d, + 0xdf,0xf3,0x27,0xf1,0x8f,0x62,0xf0,0x43,0x1a,0x66,0x9a,0x02,0x6b,0x54,0xdc,0x2d, + 0x1a,0x39,0xa9,0xff,0x76,0xf2,0x96,0x3a,0xd1,0x9d,0x7d,0xaf,0x84,0xef,0x1b,0xb8, + 0x73,0x30,0x3b,0x19,0xff,0xf2,0xe5,0xc6,0xf4,0x9d,0xc5,0x85,0x87,0xb4,0x49,0x2b, + 0x04,0x19,0x95,0x34,0xf5,0x73,0xbe,0xa9,0x72,0x3f,0xa7,0xaa,0x40,0x7b,0x3f,0x9d, + 0x98,0xf1,0x0f,0xef,0x57,0x5e,0x85,0xcb,0x88,0xda,0x6d,0x8d,0xe6,0x82,0xcc,0xae, + 0xd9,0x23,0xe4,0xe3,0x46,0x7b,0xa3,0xbc,0xbf,0x66,0x39,0x5c,0x58,0xdb,0xcd,0x6e, + 0xea,0x42,0xfc,0x33,0xb1,0x9e,0x41,0x88,0xb1,0x41,0xae,0xdf,0x2e,0xf3,0x36,0xb2, + 0xfb,0xe1,0xee,0x5f,0x18,0xf9,0x51,0xf3,0x1a,0x6e,0xe6,0xfc,0x90,0xf8,0x93,0x32, + 0x2b,0x84,0x83,0x84,0x3c,0x51,0x62,0xec,0xc7,0x59,0xa3,0xe2,0x72,0x38,0x4a,0x77, + 0xb0,0xcc,0xa8,0x78,0x92,0xbe,0x97,0x56,0xca,0x16,0xf3,0x78,0xd0,0x45,0x44,0x44, + 0xce,0x13,0x62,0x52,0x5f,0x6f,0x88,0xfb,0x7f,0x64,0xfe,0xfc,0x08,0x63,0xc2,0x74, + 0x35,0xf9,0x0b,0x6b,0xf2,0xab,0xcb,0x1d,0x61,0xcf,0x3f,0x70,0xea,0x9e,0x10,0x6d, + 0x4e,0xc1,0x3f,0x71,0xff,0x4f,0x38,0xbb,0x9e,0xa1,0xd8,0xb9,0xe3,0xfa,0x46,0x32, + 0xa2,0xb5,0xae,0xfe,0x07,0x85,0xf2,0x7e,0x6a,0x38,0x3f,0x4c,0xed,0x24,0xc5,0xff, + 0xc3,0x0c,0x3c,0x10,0x26,0x56,0xd2,0xa6,0xaa,0x50,0x97,0x4d,0x22,0x7e,0x7f,0x00, + 0x8f,0xad,0xcb,0x5f,0x2b,0x74,0xe7,0x85,0x10,0x22,0x99,0xe4,0x0f,0xcb,0x5c,0x11, + 0xe2,0xeb,0x63,0x6b,0x10,0x7d,0xca,0x1f,0xf1,0x34,0xdd,0xd5,0x5c,0xf3,0x49,0xf3, + 0xdb,0xea,0xcb,0x60,0xed,0xe6,0xe7,0x45,0x75,0x33,0x5e,0x3a,0x6a,0xe6,0x87,0xe4, + 0xfe,0x9f,0xde,0x9b,0x47,0xf3,0x47,0x95,0x8b,0x1c,0xf6,0x34,0x35,0xe9,0xd1,0x73, + 0x50,0x29,0xdd,0xcc,0xfd,0x5d,0xe3,0xea,0x02,0x66,0xd3,0xcc,0xfc,0x48,0xab,0xae, + 0xc0,0x25,0x75,0x3e,0x0b,0xd4,0xd5,0x9c,0x0d,0x19,0x1b,0x69,0x14,0xf7,0xcf,0x25, + 0x69,0x6e,0xf4,0xae,0x57,0x73,0x5c,0xfe,0x81,0xa6,0x52,0xd7,0x92,0xfe,0x9a,0x24, + 0xfe,0xe9,0xcb,0xfb,0x14,0x76,0xd7,0xdb,0x7d,0x34,0x80,0xf2,0x27,0x1e,0x08,0xfb, + 0x94,0xd3,0x20,0x44,0xe5,0x26,0xbb,0xaa,0x07,0x1a,0xed,0x54,0x6e,0x36,0xf5,0x87, + 0x3d,0x08,0x03,0xd0,0xad,0x38,0x42,0xf5,0x90,0xae,0xb3,0x38,0xed,0xf3,0x00,0x67, + 0x4f,0xd3,0x33,0xb2,0x09,0x14,0x06,0xc0,0x51,0x27,0xa7,0x93,0xee,0x64,0xfe,0x4f, + 0xda,0x36,0xe8,0xc9,0xb3,0x47,0xe9,0x36,0x14,0x3b,0xf3,0x63,0xb4,0xd2,0x9c,0x1f, + 0xa0,0xa8,0x57,0x0e,0x58,0x66,0xa0,0x3c,0x6f,0xd5,0xe4,0x76,0xd2,0x93,0x90,0x0f, + 0xd5,0x53,0x78,0x7f,0xd2,0x79,0xdc,0x09,0x7c,0xfa,0xef,0x12,0xb4,0xcc,0x17,0x19, + 0x22,0x96,0x56,0xd1,0xbe,0xb6,0x6f,0xc3,0x0d,0x4e,0xdb,0x66,0x79,0x93,0xa9,0x3f, + 0xec,0x3e,0x8e,0x9f,0x61,0xfd,0x20,0x82,0x1c,0xbe,0x31,0x32,0xc3,0x05,0x97,0xe8, + 0x55,0x98,0x6b,0xf4,0x1f,0x44,0x41,0xf3,0x35,0xbe,0x3e,0xf5,0xc9,0xfe,0xb3,0xbc, + 0x3f,0xac,0xe2,0x6e,0xb1,0x36,0x8b,0x21,0x76,0x71,0xa2,0xff,0xa9,0x31,0xd8,0x24, + 0x16,0xb2,0x61,0x09,0x45,0xd3,0x2e,0xf1,0x7c,0x42,0xfe,0xe8,0xb8,0x1f,0x7a,0x26, + 0xab,0x7d,0xf4,0x77,0x1b,0xbf,0xce,0x8c,0x8d,0x31,0x4a,0x78,0xe3,0xc5,0x2c,0x5d, + 0x6e,0x6f,0x9d,0xce,0x55,0xd5,0x26,0x54,0x55,0xa9,0xf1,0xaf,0x1e,0x2d,0x14,0xa6, + 0x79,0x44,0x9b,0x68,0xa3,0x63,0xc5,0x15,0xb3,0xea,0x72,0xa7,0xbf,0xa4,0x76,0xcb, + 0xaf,0xad,0x9d,0x72,0xa1,0x96,0xe4,0x47,0x1a,0x55,0xb8,0x3f,0x39,0x3f,0xea,0x88, + 0x58,0xee,0x61,0x71,0x5a,0x6c,0xce,0x17,0x8d,0x83,0x3b,0x49,0xb6,0xf2,0x12,0x0f, + 0x84,0xd5,0x99,0xf9,0x01,0xe8,0xe2,0x8c,0xcf,0xc0,0xb5,0xcd,0xa9,0xe4,0x2c,0x6c, + 0xfc,0x0c,0x38,0x3f,0x00,0x02,0xc5,0x73,0x50,0xa1,0xdb,0xa0,0x46,0xd2,0x4f,0xf3, + 0x81,0x22,0x1e,0x4b,0xf2,0x03,0xc4,0xe2,0x5f,0xec,0x1f,0x7b,0x79,0xff,0x5c,0x05, + 0x81,0xcd,0xa8,0x8c,0x27,0x88,0x03,0x21,0x5d,0x3c,0x5f,0x6b,0x04,0xc2,0x10,0x48, + 0x27,0xe5,0x73,0x2c,0xfe,0xc5,0x6c,0x79,0x62,0x61,0x6c,0x59,0x46,0x8d,0x7e,0xcd, + 0xdd,0x7c,0x50,0x0e,0x17,0xf3,0x2b,0x17,0xda,0xa2,0xe2,0xc1,0x24,0xfe,0x89,0xc5, + 0xbf,0x98,0xec,0xcd,0x9e,0x2a,0xc4,0x02,0x61,0x24,0xce,0xb7,0xdf,0xe0,0xc9,0x93, + 0x76,0x29,0xc5,0xbd,0x68,0x4f,0x9d,0x4b,0xf0,0x9f,0xc4,0xf2,0x7f,0xf0,0xa5,0x96, + 0x92,0x1b,0x27,0x68,0xc0,0xdf,0x85,0x1d,0xb8,0x02,0x72,0x1e,0xb9,0x0e,0x5e,0x0e, + 0x3f,0xe0,0xc3,0x2b,0x83,0xa6,0xf8,0xd7,0x80,0xb4,0x63,0x33,0x1a,0x59,0xd9,0x64, + 0x56,0xa2,0x2d,0x11,0xec,0x08,0xa8,0xfa,0x8d,0x9b,0x88,0xa4,0xee,0xe0,0x3b,0x76, + 0x8a,0xff,0xed,0x24,0x3f,0xc0,0x94,0x61,0x4e,0x13,0xd1,0x25,0x47,0x6f,0x28,0x8f, + 0x05,0xc2,0xb8,0xbc,0xbd,0xa2,0xbb,0xd9,0xfa,0x4f,0xc5,0x79,0xec,0x42,0xa8,0x32, + 0x6c,0x1b,0x16,0x2f,0x24,0xf9,0x01,0x62,0xf1,0x2f,0x5e,0x94,0xcd,0x15,0x71,0xdc, + 0x1f,0xd2,0xa3,0xe0,0x60,0xb5,0x6c,0x34,0x8e,0xbf,0xce,0xf0,0xff,0x4c,0x3c,0x3f, + 0x8f,0x7f,0x9d,0x55,0xdc,0xf5,0x3c,0xff,0xa7,0xf6,0xad,0x09,0xff,0xc0,0x59,0xa3, + 0x51,0xac,0x98,0x26,0x1d,0x10,0x2a,0x7b,0xad,0xd9,0xa2,0x39,0xff,0x07,0xf1,0x8f, + 0x47,0xfd,0x11,0x82,0x1c,0xae,0x4f,0x93,0x6d,0xce,0xb8,0xbe,0x2e,0xe4,0x1d,0x67, + 0x6a,0x1d,0x66,0xff,0x4f,0xb9,0xc0,0xbb,0x87,0xd8,0xb5,0xfa,0x0d,0x9e,0x11,0xf5, + 0xc9,0xe4,0xfc,0x0e,0x7e,0x4c,0x0a,0x09,0x67,0x98,0x47,0x41,0x94,0x95,0x1a,0xff, + 0xd2,0x0c,0x6b,0xeb,0x35,0x88,0xa5,0x01,0x1b,0xf5,0xf2,0x46,0x86,0x30,0x67,0x8c, + 0x74,0x7a,0x69,0xae,0x25,0xc9,0x0f,0xb0,0x32,0xce,0x8f,0x6d,0xd8,0x5f,0x27,0x26, + 0xde,0xd7,0x60,0xcc,0x0e,0xa1,0xd8,0x44,0xfb,0x8b,0xcb,0x9f,0xac,0x44,0x7f,0x58, + 0x1e,0xff,0xba,0xac,0xbd,0xe2,0xfd,0xfb,0xc1,0xaf,0x7d,0x4e,0x8d,0xfa,0x77,0x23, + 0xfe,0xc5,0xdd,0x3e,0xc7,0x73,0x3e,0x37,0x1a,0x61,0xd8,0x8e,0xd7,0x9c,0xc9,0x35, + 0xc7,0xbf,0x2e,0x53,0xee,0xed,0xa9,0x99,0x13,0x4a,0xf8,0x4f,0x2e,0x5b,0xdc,0x5a, + 0xe6,0x1f,0xc4,0x39,0xda,0x01,0xa8,0xaa,0xb5,0x1d,0xbb,0x36,0xfe,0xa5,0xd9,0x39, + 0x09,0x52,0x3e,0x33,0xfc,0x3f,0xcd,0x1e,0xee,0x11,0x2a,0x03,0xf9,0x59,0x4b,0xbe, + 0x27,0x22,0x95,0x40,0xdb,0x6a,0x7f,0x56,0xa2,0xbe,0x9b,0xe7,0xff,0x6c,0x77,0x14, + 0x7a,0xdb,0x15,0x52,0xab,0x1a,0x81,0x30,0x5e,0x98,0xc0,0x07,0x19,0xb9,0x44,0x62, + 0x1b,0xc0,0x51,0x7f,0xe3,0x64,0x53,0x7f,0xd8,0x76,0x89,0xd3,0x32,0xcc,0xe0,0xf6, + 0x8b,0x09,0x88,0xf2,0xc1,0x8d,0x1b,0x49,0xb1,0xd7,0x20,0x1e,0xdf,0x64,0xe6,0x07, + 0xe0,0xf8,0x27,0xea,0xfe,0x27,0x6b,0x9e,0xbc,0x9c,0x25,0x80,0xae,0x81,0x70,0xda, + 0x6b,0x66,0x28,0x6f,0x45,0x6f,0xd0,0x6c,0xed,0xf2,0x35,0xf1,0xaf,0x50,0x8f,0x66, + 0x7b,0x2a,0xe7,0xd9,0xc4,0x7c,0xe5,0xac,0x32,0x83,0xbb,0x7d,0x5e,0xa7,0xe3,0x21, + 0xbc,0xf2,0x64,0xcd,0xb9,0x94,0xf8,0xd7,0x28,0xb8,0xa9,0x8d,0x35,0xe5,0xab,0x27, + 0x12,0x7c,0x5c,0xb1,0x44,0xe8,0xfc,0xba,0x13,0x9c,0x1f,0xd8,0x9f,0xd2,0x1f,0xd6, + 0x01,0xfb,0xeb,0x4a,0x39,0x1b,0x64,0xb9,0x12,0xe7,0x47,0x1a,0x86,0x3d,0x6a,0x07, + 0x5b,0xf4,0x91,0x65,0xbe,0xd4,0x1a,0x2a,0xe5,0x44,0x01,0x26,0x7e,0x6c,0x40,0xfc, + 0x53,0xa7,0x9e,0x97,0x6f,0x25,0x56,0xe9,0x71,0xb0,0x4e,0xb4,0x45,0x03,0xdd,0xa2, + 0xf8,0x25,0x7f,0x53,0xa8,0x70,0x59,0x46,0x7b,0x76,0x12,0xff,0xf0,0xf8,0x57,0x37, + 0x3f,0xad,0xa3,0x64,0x1a,0x18,0xfd,0x61,0x1b,0xd2,0x4f,0xe2,0x7a,0xe6,0xeb,0x37, + 0x7a,0x49,0xae,0xf5,0x31,0xf6,0x83,0x70,0xc6,0x23,0xe9,0xc9,0xfe,0xb0,0x3c,0xfe, + 0xf5,0x05,0x9b,0x8d,0xb0,0x27,0xa7,0x12,0xfe,0xc8,0x78,0x5b,0xd8,0xf4,0x77,0x8d, + 0xb0,0x57,0x56,0x44,0x2c,0x83,0xf7,0x5a,0x4b,0x7d,0xc5,0x29,0xfc,0x00,0x46,0xfc, + 0x6b,0x8f,0xb6,0xc4,0x75,0xcb,0x18,0x24,0x68,0x7f,0xc6,0x79,0xfc,0x0b,0xe5,0x8f, + 0x32,0xae,0xce,0x65,0xa8,0xca,0x4d,0xfc,0x90,0xd2,0x7e,0xed,0x12,0xde,0xf6,0xee, + 0xb1,0x1a,0xce,0x0f,0x59,0x15,0xe3,0xb7,0xb9,0xc8,0x4a,0x63,0x8e,0xa0,0x2c,0x69, + 0x81,0xcf,0x7a,0xc2,0xd4,0x1f,0xf6,0x05,0x94,0x3f,0x2f,0x4d,0x76,0xfa,0xe9,0x32, + 0x32,0xc0,0xd6,0xa0,0x59,0xc4,0x61,0x9b,0xb6,0x6b,0x67,0x3e,0x0f,0x63,0x1d,0x87, + 0x35,0xae,0xe2,0x8c,0xcc,0x7b,0x88,0xb9,0x3f,0xec,0x66,0xe5,0x25,0x98,0xa5,0x5b, + 0x1a,0xfc,0xbc,0x70,0xa3,0x38,0x12,0xe7,0x33,0xc9,0xef,0x95,0x7d,0xfe,0x93,0xf0, + 0xec,0xe4,0x59,0x9e,0x3a,0x73,0xfc,0xab,0x50,0x5a,0xab,0x74,0xdb,0x9d,0x90,0x37, + 0x87,0x1c,0x30,0x0c,0x31,0x83,0x6f,0x61,0x07,0xef,0xcf,0x58,0x41,0x86,0x1f,0x6a, + 0xd2,0x4a,0x42,0x19,0x9d,0x33,0x68,0x32,0x1f,0x7b,0xca,0x88,0xc2,0xd3,0x2a,0xb2, + 0x42,0xe2,0xac,0xb8,0xff,0x9c,0x8c,0xc4,0x18,0xa1,0xdb,0xc5,0xf7,0xc9,0x21,0xce, + 0x48,0xec,0x97,0x4d,0xfd,0x41,0x84,0x6d,0xf0,0x99,0x82,0xd3,0x9e,0x15,0xde,0x30, + 0xad,0x0f,0xea,0xbb,0xf5,0xc1,0x26,0x83,0xa8,0x3f,0x68,0xeb,0x30,0xf1,0x43,0xf2, + 0xf8,0xd7,0x5f,0x60,0xee,0xb3,0x08,0x7b,0x3e,0x55,0x8f,0xc2,0x2d,0xbd,0x69,0x3c, + 0x1f,0xe6,0x62,0xc0,0x90,0xe7,0x51,0x44,0x44,0x68,0x71,0x30,0xb1,0x2e,0x91,0xff, + 0xcc,0xe3,0x5f,0xfb,0x58,0x87,0x82,0xfa,0xfd,0x23,0xc6,0xfb,0x7d,0x2c,0x0a,0xdb, + 0x47,0x60,0x77,0x10,0x15,0xd9,0x3a,0xb4,0xb0,0x02,0x3c,0xd1,0x25,0x40,0x1c,0x29, + 0xf8,0x87,0xf3,0xf3,0x67,0x04,0x48,0x3d,0xe3,0xfd,0xb0,0x32,0xc2,0x64,0x1b,0x3f, + 0x2f,0xbd,0x08,0x0c,0x3e,0xa2,0x01,0x47,0xd1,0x32,0x1a,0xf0,0x9b,0xf0,0x4f,0xae, + 0x15,0xc2,0x6c,0x06,0x50,0xd5,0xde,0x0b,0x5b,0x61,0x85,0xe1,0xff,0x49,0xdb,0x2e, + 0x58,0x79,0x86,0x8c,0x2e,0x31,0xc1,0xa9,0x05,0xc0,0xe2,0x37,0xf5,0x87,0x5d,0x61, + 0x34,0x81,0xcd,0x44,0xb3,0x0b,0xd7,0x67,0xde,0xc9,0xbb,0x38,0x5f,0xd6,0xb8,0x3a, + 0x4d,0x8f,0x3b,0xa2,0x2b,0xb9,0x23,0xc8,0x14,0xff,0x9a,0xc2,0xbb,0x9f,0xcc,0xe7, + 0x4d,0x0a,0xc6,0xd8,0x55,0x52,0x39,0x60,0x1b,0x9d,0x84,0x57,0x62,0xfa,0x6b,0xd4, + 0x70,0x04,0xad,0xd7,0xc5,0x7a,0x53,0xfe,0x33,0xe7,0x87,0x2c,0x8e,0x5a,0xf5,0x49, + 0x2e,0x58,0xab,0xcc,0xd7,0xad,0x1f,0x8a,0x15,0xbe,0xa3,0x50,0x15,0x58,0x1b,0x10, + 0xe7,0x04,0x0e,0xb3,0x02,0xe0,0xfc,0x90,0xe6,0xf8,0x17,0xec,0xe5,0xfd,0xeb,0x03, + 0xbc,0x3f,0xa3,0x7a,0xcb,0xc9,0x4c,0x95,0x2c,0x80,0xb6,0xc7,0x4b,0x3a,0x1d,0x2a, + 0x29,0xd2,0x9e,0xb7,0xdb,0x97,0x5a,0x7a,0xfe,0x15,0xff,0x0f,0x85,0x74,0x89,0x30, + 0x70,0xbc,0x6a,0xe9,0xb0,0x5b,0x59,0x93,0xe4,0x64,0x14,0x6e,0xb0,0x0a,0x3b,0xa8, + 0x7a,0x8f,0x83,0xe7,0xff,0x98,0xfc,0x3f,0xb9,0x08,0x1b,0xfa,0x21,0x7c,0xc7,0x24, + 0xf0,0x43,0x91,0x3e,0xb9,0xab,0x75,0x71,0x76,0x9b,0x54,0x12,0xa2,0x15,0xf6,0x99, + 0xda,0x5e,0x62,0xd7,0x2c,0xe1,0x6b,0xfa,0x83,0x70,0xb5,0xeb,0x0c,0xdb,0x54,0x8a, + 0xeb,0xa3,0x67,0x39,0x10,0x9f,0x2c,0x82,0x69,0x5d,0x8b,0xb7,0xd5,0x14,0xc3,0x59, + 0xda,0x1d,0xa2,0xae,0xd4,0xf8,0x17,0x35,0xc2,0x3a,0x83,0x08,0xea,0x0c,0x47,0x47, + 0x34,0x87,0x6b,0x7c,0x9e,0xef,0x9a,0x73,0x02,0xfe,0xb2,0xb5,0xaa,0x73,0x49,0x4a, + 0x7f,0x58,0x05,0xd1,0x0e,0x9e,0x3e,0x29,0x5f,0x7e,0xa0,0x79,0xac,0x76,0x81,0x9e, + 0xb9,0xf3,0x6f,0x9d,0xd2,0xc7,0x90,0x1d,0xb4,0x6e,0x13,0x9d,0xca,0xa1,0xba,0x0a, + 0xfd,0xda,0xfe,0xb0,0x1c,0x0f,0x9f,0xa1,0xe1,0x9a,0x12,0x6e,0x7f,0xf5,0x66,0x71, + 0x47,0xd0,0x7a,0xc4,0xff,0x75,0x21,0x52,0xd4,0xd7,0xa6,0xcf,0xeb,0xb3,0xa4,0xf4, + 0x87,0x35,0xec,0xaf,0x12,0xdd,0x42,0xaf,0x93,0x21,0xcc,0x1d,0x41,0x2a,0xe2,0x9f, + 0x26,0xc9,0x51,0x47,0x01,0xd5,0x56,0xf6,0x31,0x27,0xd0,0xd4,0xfe,0xb0,0xd3,0x0c, + 0x9a,0xe8,0xa2,0xba,0xec,0x69,0xd2,0xce,0x4e,0xc4,0x03,0x3f,0xc8,0x9e,0xb6,0x7a, + 0x0d,0x9b,0x69,0xa7,0x0f,0x90,0x79,0xda,0x2f,0x43,0x33,0x7d,0x96,0x95,0x29,0xf9, + 0x3f,0x59,0x08,0x3b,0xf1,0x7c,0x81,0x48,0x43,0x67,0xa3,0x15,0xfa,0xaf,0x67,0x5a, + 0x9c,0xf0,0x6a,0x63,0x79,0xbf,0x53,0x96,0xad,0xf0,0xfb,0x70,0xa5,0xd7,0xea,0x32, + 0xf3,0x63,0x67,0xc6,0xfc,0x63,0x3f,0x68,0x10,0x0c,0xc3,0xa1,0x2f,0x2b,0x2a,0x5e, + 0x0a,0xff,0x11,0xbe,0xd6,0x6c,0xd3,0x2d,0x27,0x94,0xbf,0xa0,0x3e,0xca,0xbc,0xb6, + 0x3f,0x2c,0x5f,0xff,0x92,0x70,0x8e,0x8a,0xfb,0xb3,0xea,0x84,0xd4,0x25,0xae,0x50, + 0x3f,0x36,0xdc,0x92,0xb2,0x53,0x3a,0x40,0x0d,0xc6,0xce,0x8f,0xcc,0xf1,0x2f,0x23, + 0x7f,0x80,0x7a,0x49,0xb3,0x84,0xf2,0xe4,0x20,0xd5,0x2c,0x53,0xfd,0x6b,0x7c,0xd3, + 0x41,0xf6,0x71,0x06,0x7e,0x32,0x2b,0xb5,0xfe,0x4b,0x8f,0xe1,0x9f,0xa8,0xc5,0x31, + 0x78,0x83,0xb2,0x8a,0x39,0xa3,0x74,0xd8,0x3e,0x8d,0xad,0x61,0xc5,0xaa,0x5c,0x67, + 0xff,0x2e,0x59,0x13,0x28,0xe6,0x19,0xd1,0xa3,0x29,0xfe,0x1f,0xdc,0x6f,0xb7,0xd7, + 0xcd,0x59,0x58,0x42,0x9a,0x98,0x53,0xaf,0xc7,0xf5,0x94,0x9a,0xa0,0xb0,0x03,0xcf, + 0xd7,0x61,0x78,0x91,0x39,0xef,0xa5,0xa9,0xfd,0x61,0xbb,0x38,0xec,0x09,0x65,0x45, + 0x73,0xe6,0x91,0x23,0x37,0xa0,0x36,0x3f,0x23,0x3a,0xe0,0x23,0xa8,0xea,0xb1,0x0d, + 0x6f,0xfd,0x71,0xe1,0xc1,0x37,0xab,0x76,0x5a,0x53,0xf2,0x7f,0x12,0xfe,0x9f,0xa6, + 0x28,0xc2,0xd2,0x4a,0x81,0x0f,0x8c,0x2b,0x32,0x6b,0xda,0xe2,0x30,0x42,0x45,0x5f, + 0xe9,0x0f,0xcb,0xab,0xbd,0x26,0x1b,0x65,0x5f,0xf3,0xb4,0x69,0xc1,0x9c,0x7e,0x89, + 0x37,0x0a,0x59,0xdf,0xae,0x49,0x70,0xa8,0xd3,0x55,0xf7,0xd5,0xfe,0x20,0x1c,0x84, + 0xb4,0x5b,0xa6,0xc3,0x01,0x81,0x13,0x35,0x93,0x21,0xa9,0xc5,0xa0,0x79,0xb4,0x7c, + 0x1d,0xde,0x62,0x76,0x5f,0x66,0xf0,0xda,0xfe,0x20,0xa8,0x9d,0x39,0x3f,0x36,0x69, + 0xe1,0x6e,0x64,0x4e,0x23,0xd9,0xc2,0x23,0x68,0x93,0x5b,0x3b,0x7d,0x2d,0x82,0x41, + 0xec,0x7c,0x0d,0x3f,0x24,0xac,0xe0,0xd9,0xce,0x99,0x46,0xb6,0x33,0xcd,0x25,0xaf, + 0x11,0x41,0xe0,0xc0,0x20,0xbd,0x19,0x36,0xe0,0x95,0x7c,0xe5,0x2b,0xfd,0x41,0x2a, + 0xc0,0x3a,0x11,0xed,0x72,0xf0,0x7c,0xef,0x00,0x7f,0x4d,0xc0,0x2b,0x07,0x81,0x07, + 0x62,0xae,0xe9,0x0f,0xc2,0xdb,0x82,0xcc,0x3a,0x2e,0x5e,0x86,0x4f,0x6a,0xcb,0xbc, + 0x93,0xbc,0x05,0x1f,0x28,0x3f,0xe6,0x6d,0x61,0x07,0x6b,0xfe,0x86,0x8e,0x93,0x2a, + 0xaf,0xed,0xda,0xfe,0x20,0xe3,0xb0,0xa0,0x36,0x6b,0x10,0xad,0xb3,0x03,0xb4,0x68, + 0xe1,0x02,0xee,0x18,0x39,0x8c,0x62,0x39,0x3d,0x98,0x33,0x87,0xbd,0x06,0x55,0x8b, + 0xe9,0xb5,0xfc,0xd8,0x86,0xff,0xa7,0x99,0xdc,0x4f,0x02,0x0e,0x7b,0x1e,0x0d,0x11, + 0xde,0x2f,0xa3,0x84,0xa7,0x4d,0x86,0x68,0x97,0x5a,0xb2,0xb6,0x28,0x95,0x1f,0xbb, + 0xdf,0x8a,0xef,0xab,0x59,0xf0,0x35,0xd5,0x46,0xa8,0xf7,0xa0,0x5a,0x37,0x3a,0x86, + 0xdc,0xbe,0x08,0xf5,0xbb,0x67,0x43,0xd7,0x8a,0x48,0x06,0xbe,0x6f,0x9a,0xc9,0xff, + 0xa3,0xe0,0xfa,0xfb,0xe8,0xe6,0xf4,0xd7,0x85,0x16,0x2f,0xd1,0x2c,0xc1,0xf4,0x21, + 0xe9,0x7a,0x09,0x81,0xd0,0xe4,0x8e,0x67,0xe1,0x79,0x56,0x52,0x27,0x07,0xd3,0x5f, + 0xff,0xaa,0xff,0x87,0xc3,0x98,0x03,0xd5,0xf3,0xb4,0xac,0xcd,0x1c,0xb8,0x8a,0x95, + 0xda,0xb4,0xcd,0xe2,0x8c,0x99,0x88,0x6f,0xb5,0xe2,0xe0,0xb7,0x86,0xbf,0xe2,0xff, + 0xe1,0xf9,0x4e,0x12,0xa7,0x85,0xcc,0x7c,0xb2,0x60,0x88,0x7c,0x08,0x3f,0xf3,0xae, + 0xef,0xe1,0x8d,0x62,0xa9,0x71,0xab,0xaf,0xfa,0x7f,0x50,0xfe,0x6f,0x81,0x88,0x86, + 0x86,0x5e,0x73,0x8d,0x1e,0x8b,0x48,0x36,0xe7,0xa8,0x6a,0xbc,0xfe,0x2e,0x25,0xff, + 0x47,0x41,0xb1,0xb3,0x9a,0x76,0x90,0x0b,0xd0,0x0a,0x2f,0xf0,0xb4,0x67,0xc4,0x3f, + 0x85,0xff,0xc8,0xfb,0x83,0x5c,0x4f,0xd6,0xe9,0x76,0x46,0xa3,0x62,0xeb,0xb5,0xfe, + 0x9f,0x68,0x46,0x1e,0xf7,0x97,0x0a,0xcb,0x7b,0x05,0x57,0xfa,0x40,0xee,0x8e,0x26, + 0xc3,0x70,0x10,0xa0,0xa9,0x77,0x06,0xf7,0x97,0xa6,0xf4,0x87,0x35,0xda,0x82,0x04, + 0x1a,0xd2,0x0f,0xc0,0x13,0xea,0x03,0x91,0x8c,0x1f,0xd9,0x4f,0xf2,0xfe,0x3e,0x9a, + 0xfc,0x48,0x76,0x5e,0xce,0x1a,0x7d,0x3a,0xf7,0xff,0x74,0x99,0xfd,0x3f,0xb0,0xab, + 0x71,0x41,0xf4,0xae,0x95,0xe2,0xd3,0xf0,0x6a,0x68,0xee,0x98,0xf5,0xd1,0x57,0xdf, + 0x0b,0x7d,0x89,0x16,0xcd,0xfa,0x95,0x6d,0x37,0x40,0x3f,0xdb,0x15,0x75,0xd6,0x5f, + 0xc3,0x8f,0xbd,0x97,0x9f,0x2f,0x5e,0xc6,0xf2,0xb1,0xd7,0x3d,0x68,0xeb,0xce,0x19, + 0x11,0xf6,0x4a,0x59,0xc2,0x92,0x67,0x49,0x84,0xe7,0x9b,0x71,0x8f,0x90,0x99,0x1f, + 0x3b,0x16,0xbf,0xc8,0x1a,0xcb,0xf9,0x27,0x58,0xa2,0xff,0x68,0xf4,0xe9,0x71,0xf1, + 0x8a,0xf6,0xd8,0x86,0xd2,0xe8,0x63,0x63,0x19,0xd9,0x10,0xf1,0x97,0x46,0x9d,0xc3, + 0x66,0x7e,0x6c,0x83,0x9f,0xb6,0x18,0x78,0x7f,0x6a,0xd6,0xa6,0xde,0x1a,0x91,0x67, + 0xfb,0x2f,0x69,0x8d,0xca,0x4c,0xaf,0xec,0xf1,0xe4,0x41,0x20,0x94,0x5f,0x83,0xcf, + 0x6f,0xe2,0xc7,0x56,0x62,0xf2,0xca,0x32,0x87,0x4c,0x91,0xd6,0x08,0x31,0x37,0x97, + 0xf4,0x0b,0xc8,0xf7,0xa3,0xbc,0xba,0x4f,0x5b,0xa3,0x1a,0xfe,0x2e,0x33,0x3f,0xb6, + 0xe1,0xcf,0x57,0xe9,0x6d,0x16,0x87,0xd0,0x24,0x15,0x22,0x7e,0x30,0x12,0x5d,0x1c, + 0xd0,0xa6,0x5a,0xee,0xa4,0x4d,0x7e,0xb5,0x01,0x15,0xa5,0x99,0x1f,0x1b,0xf1,0x9e, + 0x54,0x19,0x4d,0x47,0xb3,0x9a,0x1c,0x85,0x02,0x7d,0x1a,0xc7,0x27,0x4f,0x12,0x7b, + 0xa7,0x2d,0xfc,0x8d,0x3a,0xa2,0x0b,0xdd,0x83,0x8b,0x43,0xa9,0xfd,0x61,0xb9,0xbc, + 0xdd,0x34,0x8b,0xf7,0x4b,0xbd,0x88,0x40,0xe8,0x66,0x9e,0x1f,0x8e,0x86,0x86,0xd7, + 0xf6,0x6e,0xcd,0xb3,0x8e,0x8b,0xf7,0x54,0x44,0x78,0xa8,0x3a,0x25,0xfe,0xc5,0xe5, + 0xb9,0x75,0x6c,0xd2,0x30,0x7b,0x03,0xef,0xbf,0x7e,0x54,0xae,0x80,0x5e,0x98,0x8d, + 0xdf,0x3c,0xa7,0x1c,0x0e,0xb3,0x6c,0xdd,0x1a,0x4d,0xed,0x0f,0xc2,0xbb,0x99,0x70, + 0x5a,0xec,0x28,0x69,0x8b,0xc5,0xb3,0x9c,0x28,0x4f,0xca,0x5c,0x01,0xe7,0xc6,0x99, + 0xac,0x15,0x0d,0x2b,0x7e,0xe2,0x52,0xf0,0x0f,0xc2,0xa4,0x65,0x96,0xed,0xd9,0x43, + 0x46,0x3f,0xd0,0x36,0xee,0xd8,0x79,0x92,0x33,0x1c,0xfa,0x89,0x63,0x63,0xe0,0x9b, + 0x45,0x11,0x3e,0xdf,0xec,0xff,0xe1,0xeb,0x03,0x16,0x17,0x9a,0x21,0x4d,0x31,0x7f, + 0x88,0x55,0x68,0x84,0x42,0x2d,0xc0,0x50,0x09,0xb5,0x51,0x87,0x8e,0xeb,0x63,0xe2, + 0xc7,0x4e,0x5b,0xa1,0x19,0x6d,0x70,0x79,0x3d,0xd1,0x51,0xef,0xcf,0x75,0xdb,0xe7, + 0x62,0x05,0xbc,0x75,0x0f,0x6e,0x7b,0x90,0x1d,0xf4,0x80,0x30,0x4f,0x77,0x86,0x4c, + 0xfc,0xd8,0xa1,0x29,0x97,0xd8,0x55,0x58,0x00,0xc5,0xa3,0x9c,0x0d,0x5b,0xdd,0xc5, + 0xdb,0x5e,0x70,0x44,0x84,0xb0,0xa7,0xaf,0x69,0x8c,0x53,0x01,0x6b,0x68,0x8f,0xa7, + 0xc6,0xbf,0x3e,0xe7,0xfc,0xa2,0x67,0xc5,0x13,0xec,0xaa,0x56,0x5a,0x6b,0x1d,0x13, + 0x1f,0x81,0xf7,0x54,0x1e,0x11,0xbb,0xc5,0xd5,0x3f,0xe0,0xaf,0x92,0x96,0xf4,0xa5, + 0xe6,0xff,0xc0,0xee,0xa2,0x82,0x41,0xfa,0xdf,0xc8,0x27,0xec,0x57,0x12,0x4a,0xd7, + 0x1e,0x52,0x08,0xeb,0x83,0x68,0x56,0x77,0x93,0xe9,0x3a,0xe2,0xc3,0xa5,0x72,0x8b, + 0x3d,0x15,0xff,0xec,0x56,0xd5,0x7e,0x54,0x3a,0x75,0xbe,0xbd,0x21,0xf5,0x4e,0x8b, + 0x2b,0xbb,0x56,0x79,0x3c,0xe6,0x01,0x03,0xa9,0xb1,0x79,0xc5,0xf5,0x32,0xa4,0x93, + 0xc9,0x29,0xf9,0x3f,0x31,0x36,0xce,0x0f,0x78,0xa2,0x78,0x5d,0x11,0x2f,0x6c,0x6f, + 0x8b,0x39,0x82,0x8a,0xf2,0x03,0xea,0x83,0xaa,0xdc,0x93,0x6e,0xc2,0x3f,0x53,0x10, + 0xfd,0xea,0xb3,0xf5,0xc5,0xa3,0x39,0x0f,0xc3,0x15,0x56,0x5a,0x97,0x15,0x16,0xef, + 0x30,0x1a,0x95,0xe2,0x09,0x2a,0x10,0x0e,0xb2,0xca,0xd9,0x4b,0x5a,0x6b,0x52,0xf3, + 0x7f,0x2e,0x57,0x57,0xe9,0xb3,0x46,0xe1,0x61,0xed,0x42,0xb0,0x2a,0x8a,0xda,0xfc, + 0x0b,0xaf,0x81,0x88,0xc6,0x5f,0xed,0x4f,0xbf,0xc4,0x2a,0xfd,0xeb,0x35,0x39,0x35, + 0xfe,0x35,0xe6,0x75,0xf7,0x2d,0x0e,0xcb,0xd3,0x21,0xc2,0xd0,0x2c,0x0d,0x8b,0x43, + 0x9a,0xd1,0x28,0x96,0xa1,0x46,0xc3,0x81,0xe2,0xdc,0x74,0x0d,0xfe,0xd9,0xae,0x17, + 0xe8,0xf5,0x9f,0xf7,0x15,0xc2,0x20,0x18,0x69,0x4e,0x67,0xe0,0xbd,0x58,0x47,0xce, + 0xaf,0x73,0x6a,0x3b,0x07,0x6a,0xa8,0x6b,0xf0,0x4f,0x44,0x1d,0xa5,0xe5,0x68,0x94, + 0x89,0xa0,0x72,0xf6,0x81,0xd7,0xfc,0xbc,0x3f,0x51,0xc6,0xad,0x24,0x43,0x0d,0x82, + 0x93,0x05,0xae,0xc1,0x3f,0xf0,0x3b,0x96,0x3f,0x44,0x57,0x7a,0x6e,0x24,0x4f,0x34, + 0x7f,0x2f,0x6a,0x59,0xe9,0x7f,0x57,0x7b,0x62,0x8b,0xd1,0x38,0x35,0xdb,0xe8,0xa0, + 0x4a,0x17,0x92,0xd4,0xfe,0x20,0x67,0xc1,0xdd,0x47,0xdd,0xa2,0x35,0xf4,0xaa,0x1a, + 0xee,0xb7,0xb9,0xc4,0x21,0xcf,0xab,0x6c,0xaa,0x9e,0xd9,0x2d,0xd2,0x65,0x6f,0x4e, + 0xaa,0xf0,0x2e,0x2e,0x4f,0xe9,0x0f,0xb2,0x0f,0x7e,0x07,0x25,0x7d,0x46,0x74,0xef, + 0x2a,0x54,0xf4,0xde,0x64,0xf0,0x43,0x5a,0x16,0xe8,0x25,0xa3,0xf2,0x98,0xc6,0xf1, + 0x8f,0xed,0xab,0xf8,0xc7,0x7d,0x2c,0xeb,0x65,0x34,0x72,0x0f,0x05,0x8d,0xf8,0x35, + 0x4f,0xd4,0x7f,0x54,0xb7,0xf5,0xd4,0xcc,0x91,0xf6,0x04,0xd0,0xb4,0xd7,0xaf,0xc1, + 0x3f,0x2f,0xc1,0x16,0xdd,0xe1,0x6e,0xa5,0xbc,0xdf,0x10,0x2f,0xac,0x38,0x49,0x9a, + 0x1c,0x5c,0xb0,0x88,0x86,0x3f,0x59,0xa7,0xda,0x35,0xf8,0xe7,0x25,0x56,0x38,0xcc, + 0xe3,0x7d,0xc2,0xe3,0xb1,0x7c,0xa7,0xd7,0x61,0x4d,0x68,0x66,0x54,0x1e,0x26,0xd7, + 0x09,0xff,0xbc,0x41,0xbd,0x3f,0xb0,0x34,0x15,0xff,0x48,0xbb,0xc1,0xe8,0x47,0x63, + 0x53,0x77,0x44,0x0a,0x43,0xb2,0x2b,0x7b,0xc4,0xe0,0x6b,0x95,0x6f,0x23,0xb7,0xa7, + 0xed,0x60,0x1d,0x3e,0x7a,0xfd,0x35,0xf8,0xe7,0x8a,0x56,0xd6,0x88,0x20,0x67,0x3e, + 0x79,0x57,0x7f,0x29,0x6c,0xf8,0x7f,0x0e,0x42,0x39,0xb3,0x7d,0x22,0x96,0xb3,0xa7, + 0x58,0xe9,0x46,0xe7,0xd0,0xb5,0xf8,0x47,0x2a,0x47,0xed,0x23,0x9e,0xd2,0x86,0x95, + 0x79,0xe9,0x71,0x7f,0x48,0xac,0x3f,0x48,0xe1,0x98,0xb7,0x32,0x7b,0x3d,0x6b,0xba, + 0x06,0xff,0x74,0x95,0xf9,0xac,0x9b,0x6f,0x94,0x08,0x2f,0x7b,0x77,0x6e,0x10,0x3f, + 0x40,0xf9,0x63,0x94,0xbd,0x7f,0xc0,0xed,0x7d,0x9f,0x35,0x08,0xd7,0xe2,0x1f,0xbb, + 0xcf,0xb1,0x99,0x4c,0x87,0xc3,0x46,0x7f,0x58,0x3c,0x08,0x6f,0x01,0xd1,0xe8,0x3f, + 0x93,0x0f,0xd8,0xde,0x42,0x4e,0x1d,0x39,0x29,0x94,0x82,0x7f,0xf6,0xd2,0x33,0xb5, + 0x08,0x63,0xa6,0x57,0xb7,0x4c,0x7e,0xb0,0xda,0x68,0x63,0x11,0xef,0x67,0x31,0x24, + 0x3c,0x0f,0x25,0xf7,0xd2,0xd4,0xfe,0xb0,0xdc,0xff,0xe3,0xf3,0x3a,0x0c,0x6f,0x8f, + 0x86,0x77,0xe3,0x8e,0xa0,0xc9,0x08,0x9c,0xf0,0xca,0x6b,0x46,0x68,0xcc,0xa1,0x5c, + 0x97,0xd2,0x1f,0x16,0x46,0xa1,0x8c,0xb7,0x05,0x89,0x45,0xdb,0xb9,0x23,0x48,0x8a, + 0x40,0x87,0x31,0x10,0x62,0x1d,0x63,0x85,0x75,0x29,0xf8,0xe7,0x32,0x4c,0xf3,0x2e, + 0xd9,0x24,0x5e,0xce,0xfe,0x84,0x57,0x7b,0x05,0x0b,0x3e,0xe7,0x34,0xe0,0xda,0x7a, + 0x6f,0xc1,0xe7,0xc2,0x67,0x60,0xf4,0x87,0x7d,0x36,0x05,0xff,0x5c,0x86,0x1d,0xb5, + 0xb6,0x63,0x72,0x6e,0xe8,0xb0,0xcb,0xed,0xb5,0x0e,0xd6,0x9c,0xd7,0x0f,0xa8,0xa5, + 0x9a,0xed,0x4d,0x4e,0x94,0x8d,0xf8,0xc7,0x7a,0x4d,0x7f,0x34,0xe8,0x91,0xed,0x92, + 0xec,0xf7,0xab,0x78,0x32,0xec,0x37,0x51,0x46,0xde,0xf7,0x07,0x34,0x83,0x28,0x52, + 0x0d,0xe1,0xf9,0xda,0x4c,0x9f,0xf9,0x4a,0xfe,0x8f,0xaa,0xc9,0x39,0x44,0x0a,0x71, + 0xf6,0x5d,0xaa,0x64,0xf3,0x40,0x98,0xd1,0x21,0xae,0xf9,0x20,0xf7,0x80,0xd5,0x2b, + 0x77,0x98,0xe2,0x5f,0x93,0x3b,0x71,0x7d,0x8c,0xe8,0x61,0x21,0x6e,0xa4,0x90,0x56, + 0x1e,0xcf,0xa7,0xd2,0xe4,0x97,0x16,0x16,0xc2,0xf3,0xa4,0xa4,0x0e,0x52,0xfa,0xa3, + 0xf1,0xfc,0x67,0xaf,0x9b,0x17,0xe9,0xcf,0x90,0xc6,0xa5,0x52,0xcd,0x19,0xac,0x89, + 0xf5,0x07,0xb9,0x39,0x57,0x7c,0x4e,0x3d,0xa0,0x55,0x7a,0x6b,0x37,0xa7,0xc6,0xbf, + 0xa4,0xf1,0x00,0xc7,0x3f,0x39,0x43,0xfe,0x5e,0xdd,0x00,0x42,0xfd,0x70,0x36,0x9e, + 0xff,0xc3,0xde,0x82,0x8a,0x65,0xb6,0xec,0x54,0xfc,0x23,0x8c,0x81,0x5b,0xba,0x8f, + 0xd9,0xf2,0xb5,0x48,0x0c,0x6d,0x72,0xb3,0xf7,0xe1,0x58,0xc7,0xba,0x88,0x54,0xa9, + 0x58,0x9b,0xe5,0xd4,0xf8,0xd7,0x7e,0xb6,0x95,0x39,0x4e,0xd5,0xfc,0x18,0xbe,0x03, + 0x76,0x4e,0xf3,0x3e,0x06,0x6f,0x83,0x9b,0xc9,0x1f,0x90,0xf9,0x5a,0xeb,0x37,0x67, + 0xa1,0x21,0x56,0x93,0xda,0x1f,0x6d,0x07,0xf3,0x45,0xe9,0x4e,0xb2,0xc2,0xd1,0xa4, + 0xa8,0xfa,0xf5,0x3c,0xed,0x19,0xed,0x05,0x5d,0x9e,0x6a,0xf9,0x3a,0x6d,0xd2,0x9c, + 0x0d,0x16,0x57,0x2a,0xfe,0x11,0x76,0xd1,0xfc,0x28,0x5d,0x4e,0x96,0xc2,0xe3,0xf0, + 0x3d,0x5e,0x0f,0xc5,0xdb,0x84,0xe1,0xf9,0xbd,0x97,0x58,0xf3,0xd7,0xd0,0xe2,0x37, + 0x71,0x7e,0x4a,0x7f,0x34,0x78,0x85,0x95,0xfa,0xea,0x4e,0x58,0xbe,0xcb,0xfb,0x97, + 0x8d,0x66,0x2e,0x15,0xaf,0xc0,0xab,0xec,0x99,0xa8,0x6d,0x4c,0xbe,0x0e,0xde,0x08, + 0x54,0xf9,0x4a,0x56,0x8a,0x1f,0x25,0xfd,0x3f,0x99,0xdb,0x0c,0x7b,0xf3,0x66,0x96, + 0x33,0x8c,0x40,0x71,0x9f,0x3e,0xcb,0x20,0x5a,0x27,0x31,0xa2,0x5a,0xc2,0x1b,0x5d, + 0x3d,0x16,0x4e,0xe9,0x8f,0x76,0x05,0x78,0xd9,0xfb,0x63,0x63,0xa2,0x5b,0x3b,0x1c, + 0x2e,0x1d,0xb2,0x9e,0xf8,0xd6,0x05,0xe5,0x28,0xab,0x1a,0xb2,0xdd,0x20,0xbe,0xcc, + 0x3b,0x3e,0xa8,0x37,0xaf,0x14,0xc0,0x14,0xff,0x32,0xf8,0xae,0x23,0x8e,0x65,0x35, + 0x6e,0xed,0x25,0xe5,0xd6,0x61,0x7c,0xfe,0x31,0xd2,0xc4,0xfb,0xbb,0xfd,0x1d,0x99, + 0x03,0xcd,0x50,0x2c,0xc9,0xee,0xd6,0xd4,0xfc,0x9f,0x97,0x94,0x7c,0xad,0xce,0x5b, + 0xa6,0x84,0x7e,0xa1,0xde,0x1f,0x45,0xc3,0xed,0xa4,0x41,0x0c,0xbe,0x68,0x90,0x6c, + 0x32,0xa0,0x14,0x4a,0x30,0x73,0x7f,0xd8,0x01,0xfc,0x48,0x2a,0xda,0xfb,0xa4,0x1a, + 0x0f,0x72,0xe1,0x71,0x3c,0x5f,0x67,0x0c,0x47,0x90,0x5c,0x48,0x8a,0x60,0x87,0x52, + 0xd2,0x2c,0x97,0x5f,0x67,0xee,0x0f,0xbb,0x0d,0x2e,0x68,0x3c,0x9b,0x54,0x76,0xa2, + 0x5a,0x71,0x8d,0xa2,0xb5,0xf8,0x69,0xcc,0x11,0x94,0x26,0x76,0xbc,0x7a,0x91,0x03, + 0x9b,0xdf,0x89,0x45,0x29,0xf8,0xe7,0x82,0x5e,0x19,0xcc,0xea,0x14,0xbb,0xb8,0xff, + 0xa7,0xd7,0x16,0x9e,0x14,0xe7,0x07,0xe0,0x1e,0x12,0xd9,0x52,0x19,0xf9,0x4a,0x7f, + 0x90,0x2b,0x74,0x87,0xb6,0x62,0xa9,0x5c,0xee,0x3f,0x10,0x74,0xf7,0x65,0x5e,0xc8, + 0xb9,0x44,0xde,0x80,0x1f,0xf1,0xc6,0xe8,0x2e,0x18,0x68,0xac,0xaa,0x5e,0x3b,0x7a, + 0x0d,0xfe,0xd9,0xf7,0x50,0xfe,0x36,0xfa,0xa6,0x5f,0xf1,0x3f,0xc6,0xe6,0xea,0x68, + 0x7d,0x9c,0x65,0x6d,0x70,0xba,0xb7,0x2d,0x40,0xb6,0xaa,0x81,0xd3,0x25,0x6a,0x5d, + 0x58,0x0c,0xa5,0xe0,0x9f,0x30,0x6f,0x1a,0x38,0xd1,0xc6,0x2b,0x23,0x9c,0x3d,0x22, + 0xb5,0x09,0x08,0x9c,0x02,0xc4,0xae,0x04,0xd4,0x12,0xbb,0xd1,0x28,0x6d,0x62,0x3f, + 0x18,0xfd,0xd1,0x70,0xb7,0x96,0x03,0x01,0xd6,0x08,0x33,0x5e,0x45,0x41,0x1d,0x91, + 0x9a,0x04,0x94,0xcf,0x7e,0xd2,0x2c,0x30,0x30,0xec,0xfd,0xa4,0xfc,0xe1,0xfe,0x9f, + 0x51,0x4e,0x62,0xa9,0x8a,0x8e,0xd0,0x01,0x28,0xe5,0x89,0x28,0x23,0x70,0xc8,0x6b, + 0xe7,0x8d,0x71,0x39,0xff,0x46,0xa5,0x56,0xb2,0xdd,0xdc,0x1f,0xf6,0x7a,0x9e,0xff, + 0x63,0x63,0x86,0x77,0xcb,0xe0,0x37,0x1e,0x14,0xc3,0xb1,0x44,0xd6,0x5e,0x79,0x94, + 0x1a,0x89,0x40,0xe7,0xc4,0x2e,0x13,0xfe,0x79,0xd7,0xc0,0xcf,0xd6,0x95,0xe2,0xcd, + 0x60,0xa4,0x3d,0x0f,0x8b,0x15,0xf4,0xb0,0x63,0x07,0xb3,0x72,0xff,0xe4,0x40,0xf3, + 0x6c,0xd7,0xe2,0xa5,0x05,0x49,0xfe,0x1f,0x5d,0x39,0xcd,0xb3,0xc1,0x81,0x67,0x1b, + 0x2a,0x01,0xc6,0xdb,0x12,0xf9,0xab,0x48,0x8b,0x6e,0x0f,0x5b,0xda,0xc9,0x6f,0xa1, + 0xad,0xd1,0x2e,0xa0,0xc4,0x1e,0x4d,0xc4,0xbf,0x22,0x13,0xfe,0x9f,0xb0,0xdd,0x89, + 0xcb,0xa8,0xf2,0xc6,0xaf,0x56,0x4f,0x23,0x51,0x9b,0xeb,0x18,0xb1,0x22,0x30,0xb6, + 0x53,0xdc,0x21,0xe7,0x12,0xf5,0xa7,0xfa,0x94,0x90,0xd2,0xc3,0x17,0x01,0xef,0xcf, + 0xf9,0x04,0x84,0x5b,0xd8,0x32,0x27,0xcf,0xff,0x0c,0x59,0x82,0xfe,0xdf,0xaa,0xbf, + 0x62,0x46,0x7f,0xd8,0x51,0x93,0xbf,0x28,0xe6,0x7f,0xb0,0xf2,0xb0,0xd4,0x21,0x1e, + 0x76,0xe9,0x6c,0x73,0xd2,0x03,0xcc,0xd5,0x65,0xcd,0x10,0xbf,0x0e,0x6f,0x32,0x97, + 0xc3,0xda,0x62,0xea,0x8f,0x16,0x12,0xc2,0x60,0x2c,0x82,0x6e,0x64,0xd3,0x55,0x81, + 0x55,0xff,0x16,0xe2,0xc3,0x8c,0x4a,0xb6,0x7e,0x50,0x1c,0xb5,0xfc,0x25,0xa3,0x4a, + 0xc2,0x9f,0x86,0x53,0xf0,0x0f,0x47,0x53,0xd6,0xed,0x4d,0xfc,0xfe,0x95,0xfd,0xa8, + 0x28,0xd7,0x2a,0xe3,0xe0,0x6e,0xcf,0x6a,0x9e,0x34,0x9d,0xf7,0xa7,0x53,0xd7,0x32, + 0x71,0xb6,0x09,0xff,0xf0,0xc7,0x46,0x90,0x83,0xdf,0x57,0x62,0xde,0x12,0x15,0x07, + 0x15,0xb0,0xdd,0x83,0x66,0xd7,0x1e,0x8f,0x14,0x6c,0x0b,0xd9,0x55,0x7c,0x71,0x57, + 0x0a,0xfe,0xe1,0x68,0x90,0xce,0xc9,0x5e,0x0c,0x4d,0x7a,0xc9,0x58,0xac,0x9f,0xa9, + 0xa6,0x2a,0x16,0xf0,0x58,0x0d,0xc5,0xed,0x70,0x59,0x5c,0x09,0x7d,0x17,0x15,0xdc, + 0xd0,0xcc,0x8a,0x55,0x1a,0x49,0x7f,0x18,0x9a,0x03,0xb3,0x54,0xba,0x94,0x4c,0x93, + 0x76,0xf8,0xf3,0x55,0x5a,0x87,0x46,0xe1,0x9a,0xe0,0x96,0x51,0x3a,0x46,0x2a,0x12, + 0xf1,0xaf,0x3b,0x11,0xff,0xfc,0x5e,0xaa,0xd4,0x9d,0xb3,0xc5,0xc5,0xf0,0x2a,0x54, + 0xf0,0xb2,0xc1,0xb5,0x70,0xd6,0xe5,0xa2,0xeb,0x88,0xc7,0x4a,0x5f,0xd5,0x5c,0xba, + 0xd5,0x25,0x66,0x27,0xe3,0x5f,0x37,0x25,0xd6,0x27,0xac,0x5d,0x52,0x16,0x80,0xed, + 0x4d,0xe1,0x32,0xfc,0x44,0xc1,0x2b,0x9a,0x78,0x52,0xfb,0x52,0xaa,0xea,0xb7,0x8d, + 0x99,0xf8,0xb1,0xe3,0xfe,0x9f,0xa8,0x91,0xed,0xfc,0x31,0x8b,0xe7,0x87,0x5f,0x84, + 0x8a,0x53,0xd6,0x80,0xe8,0x94,0x3e,0x23,0x6e,0xdd,0xda,0x65,0xe6,0xc7,0xde,0x10, + 0x84,0x9d,0x28,0x34,0x22,0x1a,0x19,0x44,0x55,0x9c,0x0f,0x32,0xca,0x93,0xdc,0x5d, + 0x90,0xc9,0x79,0xd3,0xa6,0x1a,0x44,0xd9,0x68,0x4f,0x75,0x27,0xe4,0x1b,0x83,0xa7, + 0x95,0x5d,0x6c,0x16,0x77,0xf2,0xbc,0x0b,0xff,0xc2,0xc3,0x5e,0x3c,0xdf,0xfb,0x25, + 0x56,0xdc,0x91,0x11,0xf1,0x4f,0x33,0x42,0x81,0x19,0xf5,0x84,0x9a,0xf0,0x8f,0x0e, + 0xf1,0xfd,0x13,0x05,0x26,0xa8,0x20,0x2b,0xe9,0x03,0xb0,0xdd,0xb7,0xa2,0xf1,0x4e, + 0xb8,0x27,0x53,0xdd,0xa1,0xd9,0xb9,0x87,0xed,0x29,0x53,0xfc,0x2b,0x00,0x17,0xa0, + 0x84,0x97,0xbd,0x0f,0x4b,0x2f,0x90,0x38,0x3f,0xf6,0x15,0xa8,0xe2,0xa1,0xb6,0xdb, + 0xe0,0x0b,0xcd,0xcd,0x8a,0x3b,0x53,0xf8,0xb1,0x63,0xdb,0x66,0x56,0x3f,0x19,0x9d, + 0x58,0xa8,0x28,0xaf,0x87,0xca,0x5e,0xcb,0x33,0x54,0xc7,0x6e,0x47,0x53,0x45,0x6f, + 0x32,0xc7,0xbf,0x62,0xfc,0x3f,0x78,0x5a,0x0b,0xf3,0x0e,0x28,0xbc,0xec,0xdd,0xd3, + 0x09,0xe3,0x8d,0x65,0xf1,0xc6,0x58,0xed,0x5f,0xe5,0xff,0x89,0xa5,0xf1,0x3c,0x6d, + 0xff,0xba,0xef,0x00,0x2b,0xd1,0x8c,0x46,0x69,0xbb,0x83,0x25,0xf7,0xb4,0x6d,0xbe, + 0xe7,0x0c,0xdd,0xad,0x95,0x69,0x81,0x6b,0xfd,0x3f,0x8f,0x09,0xdf,0xbb,0x5f,0x7e, + 0xd3,0x32,0x07,0x1e,0x8b,0xd5,0xb3,0x74,0x72,0x0f,0xa4,0x76,0x63,0xd0,0xf3,0xac, + 0xc4,0x03,0x67,0x74,0x90,0x1c,0x31,0xf1,0xff,0xf0,0x69,0xf9,0x0d,0xa8,0xad,0xa6, + 0xc0,0x2f,0x58,0xb1,0x97,0xde,0x4b,0x9a,0x73,0x79,0x3c,0xe8,0xc6,0xbc,0xec,0x7e, + 0x94,0xd8,0xcf,0x34,0x38,0xbc,0xe4,0x60,0x22,0xfe,0xc5,0xf1,0x4f,0x3c,0xdb,0xd9, + 0x90,0x36,0xb8,0x55,0x09,0xf7,0x48,0x70,0x22,0xa0,0x9a,0x10,0xbd,0x20,0xb8,0x05, + 0xab,0x5e,0x90,0xf4,0xff,0x9c,0xb8,0x89,0x27,0xde,0x56,0x18,0x6a,0x5d,0x3a,0xc5, + 0x0b,0xc1,0x82,0xe4,0xfb,0xd2,0x65,0xad,0xea,0x4d,0x9b,0x37,0xe7,0x3c,0x5c,0x16, + 0x2a,0x78,0xa0,0x27,0xc9,0x8f,0x9d,0x27,0x18,0x4d,0x40,0x6a,0x11,0xe4,0xe4,0x0a, + 0x87,0x79,0xd9,0xbb,0x22,0x0c,0xb1,0xcf,0x11,0xff,0x38,0x07,0x6b,0x2a,0x38,0xb1, + 0xb6,0x66,0x1d,0x2c,0x48,0xe2,0x9f,0x95,0xf1,0xfe,0x20,0xd4,0xc0,0x3f,0xf1,0x44, + 0x20,0xad,0x87,0xd3,0xce,0x33,0x34,0xbb,0x7a,0x88,0x71,0x25,0xc9,0x8f,0x8d,0xf8, + 0x47,0xda,0x2d,0x15,0xf2,0x78,0x9f,0xe4,0x6a,0x14,0x9c,0x9e,0x40,0xb6,0x9f,0xf3, + 0x81,0xab,0xb7,0x53,0x9e,0x91,0xc8,0x3b,0x86,0x38,0x14,0x62,0xe2,0xc7,0x9e,0xd2, + 0x39,0x75,0x37,0x74,0xf2,0xf9,0xdc,0x9f,0xe6,0xac,0xae,0xe7,0xfd,0x79,0x77,0x6b, + 0x45,0xdc,0xb1,0x36,0x1d,0x76,0xd7,0x94,0xf0,0x8e,0x69,0x29,0xf1,0xaf,0xbc,0xed, + 0x50,0x86,0xb0,0xc7,0x22,0xe1,0x87,0xab,0xc4,0x69,0x46,0x62,0xb3,0xdb,0x67,0xdd, + 0x20,0xce,0xd0,0x38,0xf0,0x73,0x9a,0xfb,0xc3,0x0e,0x73,0xff,0x8f,0x64,0x54,0x87, + 0x2d,0xe7,0xde,0x1e,0x4f,0x2c,0xff,0xb9,0xbd,0x62,0xb9,0x2d,0x28,0x9f,0xe1,0xae, + 0xa1,0x1a,0x1c,0x9c,0xbb,0xc6,0xff,0xc3,0x9d,0x3c,0x3c,0x91,0x04,0x0f,0xff,0x7a, + 0xfc,0x10,0x92,0x0e,0xf3,0x14,0x5b,0xc0,0xc8,0x48,0x77,0x0b,0x46,0xbf,0xb0,0x89, + 0xe7,0x41,0xfc,0x23,0xec,0xe1,0xfd,0x41,0xa2,0x64,0x1e,0x59,0xc7,0xe6,0x06,0xb3, + 0x42,0x77,0x38,0x60,0x9d,0x56,0x10,0x90,0xeb,0xc9,0x30,0xbc,0xab,0xcc,0x65,0xb2, + 0x2f,0xd5,0xff,0xa3,0xec,0xe0,0xdd,0x19,0x5c,0xf8,0x52,0x7e,0xa6,0x0e,0xb6,0xb8, + 0xec,0x28,0x76,0x14,0xc7,0xc3,0xf2,0x64,0xd2,0xaf,0x34,0x49,0xf6,0xe3,0xf2,0xb5, + 0xfe,0x9f,0x57,0xa0,0x40,0xcf,0x6b,0x20,0xb9,0xae,0x35,0x81,0xe9,0x44,0xbe,0x40, + 0xb2,0x60,0x0d,0xdc,0x5f,0x7d,0xa3,0x97,0x7c,0x01,0xff,0xdc,0x38,0x1d,0xef,0x6f, + 0xe2,0xc7,0x36,0xfc,0x3f,0x6c,0x36,0x57,0x2b,0x88,0x76,0x70,0x90,0xf1,0x63,0xcb, + 0x34,0xf2,0x1a,0xcb,0xf0,0x2d,0x59,0x9a,0xf3,0x07,0x8a,0x57,0x78,0xa3,0xb4,0xd3, + 0xe6,0xfc,0x1f,0xfa,0x19,0xec,0xd3,0x66,0x31,0x5c,0x96,0xcf,0x84,0x4a,0xb8,0x7b, + 0x47,0x2c,0xfe,0xc5,0xcb,0x48,0xfb,0xa5,0x8b,0xb1,0x08,0xb5,0xc9,0xff,0xb3,0xea, + 0x8a,0x37,0x5e,0xb6,0x53,0xc6,0xdb,0x9a,0x0f,0xdd,0xbc,0x9b,0x5c,0xc9,0x43,0x8d, + 0xf6,0xc1,0xda,0xb7,0x72,0xca,0xea,0x2e,0x06,0x4b,0x3b,0xd7,0xd6,0xcb,0x49,0x7c, + 0x62,0xe4,0xff,0x38,0x78,0x13,0x37,0x7b,0x2e,0xac,0x91,0x8a,0x3d,0x59,0x8f,0x92, + 0x93,0xc1,0x97,0x97,0x67,0x1e,0x7f,0xe1,0x9b,0x1b,0x73,0x23,0xbb,0x42,0xb7,0x34, + 0xd3,0xfb,0xfd,0x2f,0x98,0xe3,0x5f,0x28,0x94,0xee,0xe7,0x2f,0x35,0xd5,0xf7,0x04, + 0x14,0xf7,0xca,0x0d,0x7d,0x27,0xa5,0x5d,0x5a,0xb1,0x9f,0xea,0xf6,0xbf,0x51,0x5e, + 0xa9,0xce,0x6f,0xce,0xf0,0x5d,0x83,0x7f,0x76,0x80,0x3d,0x4f,0xb6,0x12,0x1b,0x79, + 0xdc,0xeb,0xf4,0x59,0xca,0xb3,0x07,0x94,0x6e,0xe2,0x1c,0xb6,0x48,0x9e,0x3b,0xb4, + 0xed,0xcd,0x45,0x6c,0xa6,0x9d,0x04,0x4c,0xf1,0xaf,0xdf,0x96,0x7f,0x06,0xdd,0x8a, + 0xed,0x49,0xd4,0x56,0x6f,0x1d,0x2f,0x39,0x6f,0xbb,0x64,0x1f,0x51,0x2e,0x70,0x8f, + 0x71,0x8f,0xb8,0x02,0x3e,0x0b,0xd9,0x59,0xe6,0x36,0xb9,0xe8,0x5a,0xff,0x8f,0x62, + 0xdb,0x22,0x7f,0xc0,0x3e,0xae,0xad,0x0c,0x1a,0x7c,0xda,0x17,0x08,0x6f,0x8b,0xf6, + 0x9f,0xb6,0x49,0x08,0x1d,0x95,0xac,0x6b,0xfc,0x3f,0xea,0x55,0x3a,0x37,0x6a,0x3d, + 0x11,0xab,0xf7,0xe9,0xb7,0x8e,0x36,0x71,0x84,0x80,0xf6,0x45,0xb4,0xe9,0x11,0xbc, + 0xf2,0x23,0x7d,0x71,0x54,0x8c,0x24,0xf0,0x0f,0x33,0xfc,0x3f,0x76,0x5f,0xdd,0x5a, + 0x7f,0xb4,0x79,0xef,0x01,0xe7,0xc6,0x3a,0x1e,0xff,0x0a,0x43,0xc7,0xfd,0xb2,0x13, + 0xb1,0xff,0x6e,0xcd,0xee,0xe2,0x1e,0xc5,0x6b,0xf2,0x7f,0x66,0xe4,0xd1,0x8d,0x9e, + 0x4e,0xb6,0x97,0x19,0xfd,0x4c,0x47,0x60,0xb7,0x6a,0xf7,0xc9,0xed,0x7e,0xfc,0x29, + 0x30,0x63,0xcb,0xb5,0xfe,0x1f,0xb6,0x83,0xb3,0x58,0xaa,0x1e,0xde,0xaf,0xa7,0x44, + 0xa0,0x6e,0xfb,0x80,0xd4,0x83,0x16,0xca,0xa2,0x60,0x3a,0x9e,0x47,0x55,0xe5,0x8d, + 0xe4,0xfa,0x92,0xfc,0xd8,0x99,0x3c,0xbf,0xb7,0x8c,0x59,0x15,0x31,0x44,0x79,0x9a, + 0xb7,0x73,0xf4,0x71,0xbc,0x3f,0x4a,0xd4,0x25,0x8c,0xe7,0xf7,0xe6,0x1b,0xa6,0xab, + 0xde,0x94,0xcc,0xff,0xf9,0x84,0xbf,0x26,0xcc,0xd2,0x73,0x06,0xe9,0x55,0x81,0x77, + 0xb3,0xaa,0xe6,0xef,0xbb,0xa0,0x7a,0x92,0x26,0x5e,0x82,0x2f,0x94,0x57,0x38,0xb1, + 0x89,0x99,0xff,0xe7,0x2a,0x77,0x9b,0xf0,0xfc,0xf0,0x15,0x70,0x14,0xdc,0x51,0xeb, + 0x69,0x84,0x85,0xb8,0x3e,0x14,0xcd,0xf6,0x39,0xd5,0x03,0xb7,0x23,0x42,0xe8,0x25, + 0x29,0xf9,0xcf,0x6c,0x0f,0xb3,0xd3,0xba,0xf6,0xfc,0x4f,0x69,0x2b,0xf8,0xa3,0x34, + 0xe4,0xb1,0x43,0x4f,0xb0,0xc8,0x45,0x1f,0x23,0xcf,0xe8,0x81,0xea,0x92,0xa9,0x74, + 0xf5,0x35,0xf1,0xaf,0x3d,0xa0,0x12,0xca,0x2c,0x5c,0x9b,0xdb,0x75,0x9a,0x4f,0x40, + 0xc3,0xf7,0x6d,0xa6,0x90,0x2d,0x01,0x82,0x1b,0x91,0x0a,0xa9,0xf1,0x2f,0xd8,0x13, + 0xb0,0x8b,0x68,0x8f,0x8c,0xb0,0x56,0x84,0x91,0x34,0xe4,0x57,0xd5,0x1e,0x5a,0xe4, + 0x77,0xb0,0xbe,0xce,0x82,0x17,0x59,0xc9,0x29,0xda,0x05,0x49,0xff,0x8f,0x3a,0x79, + 0x04,0xce,0xe9,0xdd,0x5e,0x6b,0x9a,0x78,0x2b,0x0c,0x84,0xc2,0xba,0x75,0x48,0x9c, + 0x5d,0x77,0xc9,0x5b,0xaa,0x58,0x5f,0x13,0x17,0x40,0x40,0xaf,0xac,0xb7,0x6e,0x16, + 0xf2,0x52,0xfc,0x3f,0xa8,0xdd,0x1c,0xb6,0x13,0x4d,0x73,0xc8,0x15,0xbd,0xaa,0x6f, + 0x56,0x54,0x3c,0x0d,0x63,0xac,0x8a,0xb7,0xf5,0x1c,0x51,0xfe,0x44,0x2b,0x61,0x16, + 0x5c,0xe3,0xff,0xb9,0xc0,0xd3,0x38,0x9b,0x51,0x2d,0x1e,0xa0,0xa8,0xdf,0x3b,0x39, + 0x2d,0xbf,0xe6,0x0e,0x5a,0x9b,0xc5,0x62,0xfd,0x84,0x56,0xe9,0x41,0xfb,0x2b,0xb5, + 0xfe,0x6b,0x0f,0xf7,0xc6,0xef,0x13,0x03,0xd0,0xd6,0x6c,0x1f,0x44,0xbc,0x97,0xaf, + 0xe1,0x7e,0x67,0x99,0x94,0x14,0x2b,0x19,0x91,0x92,0x06,0x5c,0xa8,0x64,0xfe,0xb3, + 0xce,0xed,0x2f,0x1f,0xce,0xbf,0x95,0x1c,0xd1,0x5a,0xfc,0x6a,0xbf,0x1c,0x26,0x59, + 0xa4,0x0d,0x42,0x3e,0x5a,0x6e,0xb1,0xe3,0x8a,0x95,0x84,0xa9,0x83,0x84,0x53,0xfc, + 0x3f,0x3b,0x1b,0x8d,0xfa,0xf7,0x75,0xad,0xab,0x59,0xfe,0x70,0xdb,0x4a,0x32,0x4d, + 0x5d,0xe3,0xcf,0x5f,0x96,0xf1,0x63,0x14,0xe3,0xab,0xb6,0x14,0x87,0x10,0x11,0xb5, + 0x27,0xee,0x5f,0x8f,0xf8,0xe7,0x9c,0x5a,0x01,0x36,0xd7,0x37,0x8e,0x40,0xcb,0xcc, + 0xf0,0x90,0x2d,0x2c,0x5b,0xe1,0x55,0xd5,0x15,0xb1,0xce,0x6f,0x02,0xd2,0xe7,0xad, + 0xf0,0x58,0xcb,0x9a,0x9e,0x4a,0xf1,0xff,0xec,0xe7,0x4e,0x9e,0xb3,0xe2,0x25,0x3a, + 0x51,0xff,0xa5,0x5d,0x84,0x05,0xdc,0xfe,0x3a,0x57,0xfb,0x97,0xd9,0x46,0xeb,0x61, + 0x6f,0x8a,0xff,0xc7,0x38,0xad,0xe1,0x49,0x03,0x42,0x44,0xe8,0xee,0xb5,0xf5,0x18, + 0x40,0xd4,0x68,0xf4,0x5c,0x04,0x03,0xb1,0xfa,0xca,0xd4,0xfe,0xb0,0x2f,0xa3,0x9a, + 0x8e,0x78,0xb3,0x4f,0x12,0xc6,0xcd,0x46,0x9e,0xef,0xd4,0xc4,0x03,0x37,0x2e,0x42, + 0x95,0xc7,0xa0,0x00,0xa8,0xf7,0x9a,0xfc,0xe7,0x97,0xf5,0x62,0x4e,0xea,0xf8,0x2e, + 0x5d,0xa5,0x1b,0xf8,0x67,0x1a,0x3c,0xc1,0x0c,0x22,0xa0,0x1b,0xf2,0x9a,0x59,0xfe, + 0xb2,0xc0,0x54,0x73,0xfe,0xb3,0x82,0xf6,0x97,0xea,0x5c,0x46,0x8d,0x6e,0xb0,0x88, + 0x1e,0x17,0xc5,0x1b,0x11,0x72,0x8f,0x50,0xab,0xb7,0x51,0x08,0x35,0x38,0x36,0x5f, + 0x5b,0xff,0xa5,0xfd,0x9c,0x39,0x7d,0xe2,0x45,0x38,0xa2,0xf3,0xb6,0x83,0xb2,0x83, + 0x1c,0xe3,0x15,0x99,0xaa,0x5c,0x4e,0x8e,0x44,0x4a,0x43,0xd6,0xa1,0x6b,0xf3,0x9f, + 0xb5,0x4a,0x09,0xf7,0x43,0x54,0x1d,0x8d,0xb1,0x1d,0xea,0xa8,0xd5,0x8c,0xfa,0x94, + 0x87,0x60,0x8c,0xf2,0xfa,0xf7,0xc7,0xaf,0xf1,0xff,0x30,0x54,0x82,0x9b,0x0b,0x24, + 0x38,0x90,0xeb,0xae,0xe5,0xb4,0x3f,0x2c,0x4e,0x7b,0x58,0x08,0x67,0xed,0x2e,0x9f, + 0x14,0x14,0xaf,0xc9,0x7f,0xc6,0xf9,0x68,0x44,0x14,0x42,0x8b,0xae,0x1a,0xfe,0x1c, + 0x3f,0xe2,0x7f,0xbc,0x22,0xfe,0x03,0xef,0x58,0xe1,0xa5,0x4f,0x5f,0x9b,0xff,0x9c, + 0xe7,0xe4,0x30,0xc9,0x49,0x5a,0xaa,0x8d,0x78,0xd9,0x79,0x78,0x4c,0x2d,0xd0,0x1c, + 0xc7,0xc8,0x1c,0x6d,0x37,0x25,0x0b,0x2d,0x1b,0xfe,0x95,0xfc,0x67,0x8e,0x07,0xa0, + 0x51,0xb3,0x73,0xb7,0xcf,0x71,0x61,0x15,0x6f,0xfc,0xed,0x25,0xff,0x19,0x81,0x7a, + 0xc8,0xfb,0x91,0xb9,0xfe,0x34,0x11,0xff,0x0a,0xdd,0x82,0xfa,0x97,0xd8,0x27,0xfc, + 0x0f,0xdc,0x11,0x21,0xbb,0x10,0x6a,0xbb,0x61,0xdd,0x35,0xf5,0x5f,0xf4,0x32,0xcc, + 0x8f,0x55,0xbb,0x5f,0xf5,0x54,0x69,0xb3,0x36,0xd5,0x7c,0x00,0xe3,0xbc,0x3f,0xda, + 0x26,0xf1,0x03,0x7a,0x55,0xab,0xf2,0xde,0x75,0xbc,0x26,0x25,0xfe,0xa5,0x5d,0x86, + 0x0a,0xaf,0x6d,0x30,0x67,0x8e,0x83,0x27,0x02,0xd9,0xde,0x16,0xcb,0xd4,0xc3,0x81, + 0xd2,0x7a,0xeb,0x89,0xa6,0xb9,0x80,0x88,0xc8,0x6b,0x7d,0xb3,0xe9,0x8c,0x92,0xf4, + 0xff,0x9c,0x66,0x7b,0x84,0x12,0x4e,0x72,0x98,0xaf,0xf4,0xa8,0x1d,0x80,0x66,0x63, + 0x3e,0x04,0xb4,0x0e,0xa0,0xcd,0x16,0x1c,0xa8,0x28,0x81,0x3b,0xc9,0x11,0xb3,0xff, + 0x87,0x19,0x69,0x3f,0x41,0x5e,0xe6,0xcf,0xab,0xbd,0x72,0xfd,0xbc,0x43,0xae,0xca, + 0x57,0x20,0x0d,0x1a,0xeb,0x70,0x29,0xb2,0x4d,0xfd,0xa9,0x8d,0xfc,0xe7,0xe6,0x92, + 0x3a,0x79,0xa3,0x7d,0x79,0xe7,0x6e,0x81,0x3b,0x82,0xec,0x85,0x34,0xee,0x4f,0x2b, + 0x14,0xda,0xd4,0x92,0x41,0x9a,0xd2,0x1f,0x36,0xd7,0x88,0x67,0xf9,0x6c,0xfc,0xeb, + 0x8c,0x73,0xa0,0x3b,0x88,0x86,0x3e,0x7e,0x5f,0x1f,0xc2,0x1e,0x1c,0xdc,0x5e,0xb9, + 0xdc,0xda,0x8e,0xd0,0x7a,0x62,0x7f,0x1a,0xf5,0x5f,0x50,0x59,0xbd,0xa4,0x5d,0xee, + 0x84,0xb3,0xfa,0xfe,0x89,0x7c,0xb0,0x8a,0x06,0x84,0x85,0xfd,0xf8,0x53,0x85,0x6f, + 0xd6,0xc6,0x82,0x6b,0xea,0xbf,0xa8,0x11,0xe4,0x3a,0x05,0x63,0x8d,0x0f,0x1b,0xb4, + 0x3f,0x2c,0x16,0xf6,0xca,0x51,0x03,0x11,0x1f,0xff,0x10,0x05,0xd7,0xd4,0x7f,0x05, + 0xca,0x1a,0x69,0xbd,0x7f,0x98,0x37,0x32,0xf3,0xa3,0xf6,0xb9,0x01,0x5a,0x25,0xb4, + 0xbf,0x42,0xe2,0x3c,0x78,0x57,0x2f,0x08,0xd2,0xa8,0x27,0xc9,0x30,0xed,0x10,0x16, + 0xa3,0x76,0x53,0x63,0xdd,0x18,0x51,0x31,0x9d,0x0e,0x84,0x49,0x26,0x6d,0xf2,0xfb, + 0x50,0xfe,0x90,0x3b,0xd0,0x3e,0x55,0x1f,0xa6,0x79,0xfe,0xd4,0xfa,0xaf,0x9d,0xfe, + 0xaf,0x0f,0x53,0xce,0xd6,0xf5,0x12,0xe0,0x31,0xf4,0xfa,0x33,0x61,0x8d,0x96,0xef, + 0xa1,0x8f,0x90,0x5c,0xf5,0x89,0x40,0xbe,0x97,0xde,0x77,0x6d,0xfd,0x17,0x7b,0x68, + 0xcc,0xc9,0xb3,0x9d,0xaf,0xb2,0x2d,0x51,0x5a,0x21,0x4e,0x23,0xaf,0xb2,0xed,0x3e, + 0x67,0xb9,0x7c,0x37,0x9c,0x6c,0x2e,0x0d,0x39,0x87,0x53,0xeb,0xbf,0xe0,0x1c,0x54, + 0x46,0xf0,0x34,0x0d,0xa1,0xb5,0x5e,0x81,0x66,0xbe,0xcc,0x35,0x7e,0x85,0xb6,0x3e, + 0x6c,0xf4,0xf3,0xaa,0xe2,0xfa,0xcb,0x9c,0xff,0x7c,0x05,0x2e,0x07,0x77,0x8d,0x4e, + 0x7d,0x4b,0xac,0xac,0x3e,0x12,0x2c,0xf5,0x65,0x1a,0xf5,0x5f,0xc1,0x2a,0x9f,0xf5, + 0x82,0xf8,0x05,0x1c,0xc6,0x2b,0x36,0xde,0x1f,0xc4,0xec,0xff,0xd9,0xe9,0x2a,0xd0, + 0x03,0xf7,0xe7,0xdc,0x0b,0x6b,0xcb,0xf3,0xbd,0x75,0x0d,0x9e,0x93,0xd2,0x9a,0x50, + 0x31,0x97,0x3f,0xe7,0xd9,0x2a,0x57,0xfe,0x1d,0xf2,0x77,0x52,0xfb,0xc3,0xc2,0xcb, + 0x24,0x5f,0x77,0x78,0xed,0xd6,0x8c,0xd5,0xfc,0x98,0xf0,0xfc,0x9f,0x55,0xdc,0xd0, + 0x78,0xd8,0x7e,0x7c,0x3a,0x27,0xbc,0x96,0x3d,0xa4,0x9f,0x4d,0xac,0xbf,0x2f,0x77, + 0xc4,0xda,0xad,0x15,0x0e,0x52,0x2b,0xa9,0x55,0xda,0x21,0xa4,0x39,0xc2,0xbc,0xcd, + 0x25,0xee,0x40,0x87,0x8b,0x7c,0x28,0xf8,0x75,0xb5,0x5d,0xfe,0xad,0x89,0x7f,0x95, + 0xe7,0x3f,0x8f,0x45,0x6f,0xed,0xb7,0x86,0x9b,0x0a,0xe1,0x10,0x33,0xf8,0xe5,0x46, + 0xc8,0xab,0x3c,0x91,0x3e,0x8c,0xb0,0x10,0x35,0x8e,0xcf,0xf6,0x94,0x78,0x30,0xb5, + 0xfe,0x8b,0xce,0x7b,0xcd,0xb6,0x13,0x77,0xcb,0x30,0xad,0x7c,0x33,0x2b,0x68,0xd8, + 0x9b,0x06,0x3e,0x8c,0x36,0x5e,0xbc,0xb3,0x32,0xd6,0x68,0xcf,0x84,0x7f,0xd0,0xfa, + 0x29,0xd5,0xad,0xd1,0xa6,0xf3,0xda,0x9f,0xb8,0xff,0x64,0x34,0xa7,0x02,0x8e,0xaa, + 0xee,0xda,0x15,0xe7,0xc4,0x31,0x18,0x04,0xa3,0x51,0xac,0x6a,0xf2,0xff,0xfc,0x04, + 0xfc,0x8d,0x5b,0x75,0x4b,0xf3,0xc6,0x21,0xe5,0xa4,0xee,0x68,0xa0,0x27,0x88,0x0d, + 0xda,0x58,0x19,0x0f,0xf4,0x9c,0x91,0x02,0xba,0xbd,0xa1,0x6d,0xed,0x46,0x73,0xfd, + 0xfb,0x0a,0x08,0xb0,0x19,0x68,0x14,0xc0,0x10,0xb4,0xea,0x76,0x5f,0xc6,0x76,0x32, + 0x0b,0xda,0xf0,0xe0,0xd0,0x30,0x9c,0x56,0x51,0x70,0x21,0x10,0xba,0xa6,0xfe,0x8b, + 0xb1,0x65,0xba,0xc5,0xe5,0xe9,0x9f,0x14,0x84,0x22,0x25,0x4f,0xe1,0xc0,0x40,0x35, + 0x3c,0xf6,0x3a,0x6a,0x84,0x10,0xc8,0xa8,0x00,0x13,0xab,0xcf,0xeb,0xbf,0x22,0x30, + 0x57,0x5f,0xcb,0xc8,0x50,0x75,0x84,0x18,0xf1,0x17,0xd4,0x2f,0x0e,0x94,0x9f,0x1b, + 0x50,0x10,0x1d,0xe0,0x16,0xc1,0x46,0x31,0xa5,0xfe,0x4b,0x39,0xcf,0xd5,0x96,0x26, + 0x9e,0x67,0x23,0xb0,0xc0,0x28,0xfb,0x22,0x3c,0x83,0x7a,0xc9,0xb9,0xb8,0xc7,0xc3, + 0xd6,0xf8,0x3d,0x53,0xfc,0x2b,0x93,0xc7,0x4f,0xe7,0x46,0x6d,0x0d,0xe2,0x20,0x1d, + 0x81,0x2a,0x8a,0x62,0xf9,0x13,0xb6,0xbe,0xbf,0x52,0xb4,0xae,0x2c,0xa8,0x84,0x48, + 0x6f,0xe9,0xd9,0xcd,0x63,0x66,0xfe,0x9f,0xc0,0x6f,0xf3,0xe2,0x69,0xcf,0x1f,0xe7, + 0x06,0x06,0x4b,0x6e,0x40,0x43,0xec,0x92,0xde,0xaa,0x3a,0x07,0x2d,0x68,0x7b,0x19, + 0x08,0x27,0x2f,0x4c,0x4c,0xfc,0x87,0xd2,0x00,0xc4,0xd3,0x9e,0x5f,0x95,0x3a,0xc0, + 0x29,0xdd,0x09,0xd9,0x8b,0xa5,0x46,0xe2,0x5c,0xe8,0x70,0x79,0xac,0xb0,0x31,0xbf, + 0xf0,0x80,0xc5,0xbd,0xda,0xd4,0x1f,0x2d,0x6d,0x82,0xff,0x87,0x7c,0x0a,0xad,0x7d, + 0x25,0xae,0x3b,0x03,0x88,0x27,0x79,0xfc,0xcb,0xc2,0x03,0x61,0xbf,0x62,0x2a,0x0e, + 0xec,0x26,0xfe,0x43,0x89,0xf3,0xf3,0xcc,0xd3,0x8d,0x26,0xa4,0x5d,0xac,0x32,0x54, + 0xbc,0x0f,0xf7,0xcf,0x21,0xa1,0xf2,0x36,0x09,0x17,0x4a,0x7d,0x0b,0x77,0x54,0x51, + 0x98,0x24,0xf3,0xff,0x37,0x40,0x9c,0x0f,0x61,0xb4,0xe0,0x92,0x51,0x5f,0x99,0x15, + 0xce,0x19,0xa1,0x57,0xab,0xab,0x46,0x79,0xa0,0xd0,0xfb,0x89,0xf4,0x0a,0xee,0x10, + 0x39,0xd9,0x1f,0x76,0x14,0xe2,0x7c,0x0b,0x61,0x51,0x55,0x3f,0xf2,0x3d,0xdc,0xbe, + 0x36,0x54,0xb0,0x18,0xf5,0xbb,0xeb,0x38,0xae,0xff,0x4c,0x0d,0x15,0x7d,0x24,0x33, + 0x5c,0xf3,0x48,0x92,0x4f,0x46,0x8a,0xe7,0xc3,0x8f,0x66,0x3b,0xa0,0x15,0x96,0x05, + 0x69,0x07,0xcf,0x8f,0xaa,0xb3,0x47,0x33,0x15,0xf1,0x6e,0xa5,0x89,0x75,0x0c,0xd2, + 0x9d,0x1d,0x26,0xfc,0x33,0xc1,0x87,0xe0,0xba,0x87,0x82,0x7f,0xd0,0x8e,0x68,0x27, + 0x7d,0xc0,0xde,0x14,0x50,0x0f,0xe0,0x0e,0xc9,0x64,0x8d,0x93,0x43,0x83,0xd0,0xe3, + 0x9f,0x58,0x4d,0xc0,0x0d,0x1b,0xab,0xff,0x92,0x7f,0x8c,0x62,0x6d,0x55,0x30,0x5f, + 0xa5,0x8f,0x66,0x3f,0x0d,0xab,0x83,0xf9,0x51,0x71,0x8c,0xfc,0x8c,0xae,0x09,0x1a, + 0xc0,0xa0,0x32,0x31,0xbf,0x0e,0xb2,0xf4,0xcf,0xb8,0x18,0x71,0x89,0xc0,0xfc,0x4a, + 0xc8,0xe2,0xac,0x10,0x8f,0xf0,0xe7,0x8f,0x66,0xb9,0x44,0x2b,0x7b,0x75,0xb0,0x5b, + 0x77,0x6e,0x97,0xb3,0x93,0xfc,0x3f,0x13,0x7c,0x3e,0xe1,0x45,0xc3,0xe4,0x6d,0x9e, + 0xd6,0x1b,0xce,0x46,0x04,0x9e,0x6e,0x54,0xc0,0x0d,0xc0,0x45,0x95,0xaf,0x98,0x18, + 0x4c,0xd8,0x47,0x71,0xfe,0x9f,0x28,0x5e,0x0c,0x81,0x2e,0x18,0xfc,0x93,0xc5,0xec, + 0x10,0xcc,0xd3,0xa6,0x72,0x20,0xd4,0x1b,0xab,0xe8,0x4c,0xe5,0x7f,0xe6,0xf1,0xf4, + 0x48,0x03,0xc9,0x83,0x66,0xc9,0x88,0x7f,0xdd,0xe4,0x59,0x8f,0x40,0xa8,0xb8,0x81, + 0x6c,0x26,0x6b,0xe0,0x79,0x1e,0x61,0x4f,0xda,0xbf,0xf1,0xfc,0x67,0x0e,0x7b,0xfc, + 0xb0,0x1a,0xe1,0x8b,0x65,0x65,0xeb,0x34,0xb6,0x9e,0x15,0x9f,0xca,0x38,0xc1,0xfd, + 0x5d,0xb1,0x88,0x98,0x99,0xff,0x39,0xc6,0x37,0x95,0xe1,0x22,0x16,0xb4,0x67,0xed, + 0x21,0x79,0x3f,0xc7,0x57,0x5e,0x3c,0xa1,0x4a,0xf6,0x3a,0xad,0x69,0xb0,0x84,0x23, + 0xa2,0xa4,0xfc,0x89,0x48,0x5d,0x13,0x69,0xcf,0x7b,0xc8,0xeb,0xfa,0x8e,0x9e,0xac, + 0x21,0xd1,0x01,0xaf,0x6b,0x3f,0x7f,0x3e,0xa3,0xa3,0xe0,0x06,0x58,0x27,0xfd,0x53, + 0xac,0x22,0x3e,0x71,0x7f,0x88,0xe5,0x63,0x64,0x21,0xfe,0xf1,0x8d,0xe5,0x5d,0x21, + 0x36,0x56,0xd0,0xcb,0x25,0x92,0x62,0x63,0x35,0x51,0x36,0x26,0xcd,0xe3,0x16,0xba, + 0x89,0xff,0x19,0xe2,0xf5,0x3e,0x8a,0x51,0x1f,0x64,0xd7,0xaa,0x83,0x39,0xcb,0xc9, + 0x01,0xd6,0xbd,0x3c,0xf3,0x29,0xf1,0xcc,0xda,0x03,0x8e,0xaf,0xf8,0x7f,0x12,0xf5, + 0x5c,0xdc,0x9f,0x60,0xaf,0xab,0x33,0x80,0x90,0x66,0xbf,0x3f,0xb0,0x99,0x9c,0x81, + 0x46,0x66,0x28,0xe2,0x68,0x62,0x75,0xf2,0xa4,0x42,0x69,0xb7,0x54,0xa2,0x65,0x04, + 0xfd,0x9d,0xd0,0x22,0xbc,0x50,0x2b,0x6f,0x20,0xcb,0xd5,0x16,0xf5,0xb4,0x07,0x82, + 0x9e,0x21,0xf5,0x79,0x1e,0xaf,0x0f,0xda,0xcd,0xfc,0xcf,0x09,0xfe,0x9f,0x18,0x0c, + 0xb0,0x6c,0x22,0x69,0xd6,0x36,0xcd,0xc0,0x03,0xfd,0x96,0x17,0x8d,0xd0,0x18,0x24, + 0xe3,0xef,0x4b,0x33,0xa2,0x13,0xf9,0x27,0xf1,0x6a,0x77,0x10,0x35,0x88,0x08,0x2e, + 0x70,0x86,0x38,0x23,0x5f,0x9c,0xff,0x79,0x92,0x09,0xff,0x80,0xe1,0xff,0xc9,0x35, + 0x68,0x0f,0xe7,0x7a,0x33,0x8f,0x8b,0x1f,0xc0,0xef,0x48,0x95,0xf7,0x46,0xaf,0x78, + 0x12,0xfe,0x14,0x4b,0x7d,0x49,0xf6,0x87,0xcd,0xcb,0x4c,0xf2,0xff,0xb0,0x0f,0xd5, + 0xb9,0x8b,0xad,0xbf,0xaf,0x29,0x1c,0x1c,0xd7,0xaa,0xfe,0x6e,0xea,0xa0,0x38,0x07, + 0x0e,0x6b,0x88,0x18,0x37,0x88,0xd7,0xf0,0x1f,0xc6,0xca,0xde,0xf3,0x61,0xad,0x17, + 0xad,0xad,0x49,0xa8,0x9d,0xf6,0xa9,0x25,0x79,0x79,0xcc,0xc3,0x33,0x12,0x55,0x4a, + 0xfb,0x10,0x9f,0x4c,0x7c,0x5f,0x1f,0xcf,0x7f,0x26,0xc6,0xfb,0x7e,0x5b,0x7b,0x86, + 0x19,0x8e,0xa0,0x5c,0xe5,0x25,0x70,0x7e,0x93,0xf3,0x1f,0x42,0x8b,0xca,0x43,0x1b, + 0x24,0xc9,0x7f,0xd8,0x93,0xdb,0x69,0x8d,0xaf,0xff,0x1c,0xfa,0x18,0x94,0xd4,0xd1, + 0xa0,0x65,0x0e,0x2c,0x10,0x4a,0xbc,0x74,0x03,0x4f,0x84,0x68,0xdc,0xa2,0xd3,0x41, + 0x92,0xda,0x1f,0x36,0xfe,0xfc,0xff,0x05,0x3e,0xd4,0x66,0x78,0x9c,0x1b,0x63,0x0c, + 0xcf,0x8f,0x38,0xda,0xc5,0x19,0x9e,0x5e,0xc6,0xbf,0x6f,0x4e,0x0a,0xff,0x61,0x6c, + 0xbe,0x82,0xcb,0x62,0x64,0x3b,0x1b,0xfc,0x3f,0x3a,0xae,0x58,0xfb,0xa2,0xd8,0x52, + 0xcc,0x0a,0x12,0x13,0xff,0x21,0x84,0x92,0xeb,0xbf,0x96,0x94,0x11,0xa7,0x5f,0x54, + 0xbd,0x03,0x86,0xdb,0x27,0xe7,0x14,0x44,0x18,0xf7,0xc8,0x99,0xea,0xbf,0x68,0xb3, + 0x83,0x1a,0x65,0x5f,0xbc,0xa9,0x68,0x2b,0x14,0x84,0xa8,0x4a,0x8a,0x24,0x1c,0xf4, + 0xd8,0x56,0xe0,0xb6,0x6f,0xd5,0x4a,0x10,0x08,0x79,0x92,0xfa,0x25,0xce,0xc7,0xc2, + 0x32,0xb8,0xdb,0xd9,0x0f,0x33,0x7c,0x34,0x97,0xac,0x25,0x5b,0x99,0x1a,0x91,0x15, + 0xff,0x00,0x6b,0x14,0x9c,0xa7,0x10,0x08,0x91,0x84,0xfe,0x12,0xc0,0xc8,0xff,0x61, + 0x6d,0x2e,0x3c,0xbf,0x68,0x7f,0x79,0xa8,0xf7,0x8e,0xa7,0x26,0x3f,0xa7,0xe7,0xeb, + 0x16,0xaf,0xff,0x92,0xba,0x86,0x16,0xf7,0xd1,0x9f,0x78,0x68,0xc2,0xff,0x43,0xd9, + 0xd3,0xf0,0x25,0x5b,0x10,0xca,0xac,0x17,0x9f,0x4e,0x5f,0xcd,0xe6,0xfa,0xac,0x4b, + 0xf1,0x44,0x7e,0x8a,0xf8,0x47,0x5e,0x99,0xf3,0x07,0xf2,0x7a,0xf3,0x82,0xa8,0x75, + 0xcc,0x84,0x7f,0x12,0xf5,0x14,0x21,0x31,0x22,0x9d,0x8b,0x2d,0xec,0x0a,0x78,0x3b, + 0xa6,0xdf,0xfb,0x21,0x4e,0x8d,0x98,0xf4,0xff,0x68,0xd2,0x7e,0xef,0x55,0x56,0x15, + 0xb2,0x8d,0x15,0x4c,0x83,0x77,0x79,0x20,0x23,0x22,0xee,0xcf,0x38,0xec,0xaf,0x8a, + 0x66,0x9e,0x10,0xde,0x85,0x37,0x58,0x29,0xcf,0x7f,0x4e,0xca,0x87,0x17,0x60,0x6d, + 0xac,0xfe,0xa2,0xc1,0x82,0xcf,0xef,0x98,0x15,0xa1,0x0b,0xc9,0x0d,0x7d,0xff,0x53, + 0x9d,0x05,0x16,0x2f,0x39,0xe9,0x59,0xa3,0xe4,0x6b,0x8e,0x6f,0x92,0x24,0xfe,0x0c, + 0x29,0x9b,0x15,0x63,0xbe,0x8f,0x4c,0x45,0xf9,0x53,0xac,0xd3,0x6a,0xc4,0x3f,0xab, + 0x5b,0x71,0xf0,0x10,0x1a,0x1a,0xab,0xe9,0x33,0xb5,0x19,0x4b,0x49,0x7f,0x92,0xff, + 0x30,0x26,0x7f,0x78,0x37,0x79,0x94,0xe7,0xcc,0xb9,0x9d,0x12,0xb2,0x02,0xfc,0x21, + 0x67,0xde,0x42,0x17,0x39,0xaa,0xf8,0x99,0xc1,0x50,0x3a,0x68,0xfa,0xbe,0x46,0xbd, + 0x1b,0x6f,0xa2,0x3d,0x89,0xa7,0x05,0x7e,0xdb,0xc9,0xd1,0x4b,0x1b,0xab,0x3c,0x46, + 0xc3,0xe2,0xc1,0x3b,0x5e,0x65,0x6e,0x96,0x19,0x42,0x89,0x3d,0xf1,0xbe,0x0c,0xe2, + 0xeb,0xc3,0xd1,0xd1,0x87,0x3e,0xbe,0x3e,0x93,0x42,0x70,0x51,0xac,0xf4,0x66,0x05, + 0x6b,0x3e,0xd1,0x2e,0x6a,0x95,0x83,0xd3,0x3a,0x0b,0x3e,0x4c,0xf2,0x3f,0x1b,0xfa, + 0x6e,0x3e,0x07,0x39,0x73,0xd5,0xc3,0xbd,0x55,0x9a,0xed,0x06,0xf1,0xfb,0xf4,0x5d, + 0x98,0xdd,0x25,0x45,0x11,0x4f,0x1e,0xa1,0x3b,0x42,0xd6,0xe1,0x02,0x33,0xff,0xb3, + 0x51,0xbf,0xcc,0xb2,0x54,0x1e,0xcf,0xf2,0x95,0x9c,0x5a,0xd4,0xe3,0x2f,0x04,0x3f, + 0xb1,0x97,0x67,0x76,0xf9,0xff,0xa2,0xb4,0xe6,0xdb,0x07,0x11,0x51,0xab,0xbe,0x04, + 0xfe,0x89,0xcf,0xb7,0x84,0x2d,0x78,0x9a,0x84,0x92,0xd3,0x72,0x30,0x7d,0x85,0xf4, + 0x24,0xc2,0x80,0x85,0x46,0x3c,0x48,0xb1,0x07,0xea,0x9e,0x4d,0xc1,0x3f,0x99,0xc6, + 0xfa,0x58,0x5c,0xf8,0xc9,0x1b,0xf9,0x42,0x4d,0x26,0x0e,0xd6,0xc2,0x61,0x8f,0xcb, + 0x33,0x92,0xde,0x56,0xcd,0xeb,0x73,0x6f,0x30,0x77,0x38,0x59,0x11,0x6f,0x0a,0x2c, + 0xf2,0xfb,0xf3,0xb2,0xa3,0x9c,0x07,0xaa,0xdf,0x06,0xf7,0xf1,0x69,0x3c,0x03,0x0a, + 0x15,0x19,0x73,0x86,0xc4,0x24,0xff,0x21,0xfb,0x05,0xcf,0xff,0xa9,0x62,0x59,0x3e, + 0x83,0x2d,0x13,0x15,0xfd,0x0e,0x32,0xa2,0x21,0x6c,0x06,0x04,0x7e,0x97,0xe2,0x19, + 0xbf,0xe2,0xf0,0x8c,0x04,0xde,0x10,0x8c,0xfc,0xb1,0x08,0x8f,0xfe,0x04,0xfe,0xc4, + 0xe7,0xfb,0x44,0x17,0x8b,0x38,0x4a,0x79,0x7d,0xf7,0x97,0xc2,0x80,0xef,0xe7,0x2a, + 0x9a,0xba,0xd7,0xe4,0x3f,0xab,0xb3,0x3e,0x90,0x7b,0xee,0x89,0x6a,0x2d,0x3a,0x2a, + 0xfa,0x10,0xb7,0xbf,0x74,0xfb,0x23,0xbc,0x50,0xab,0x31,0x80,0x2b,0x26,0xaf,0x36, + 0xe1,0x1f,0x23,0xff,0x39,0xc3,0xd9,0x8b,0xf8,0x47,0x4f,0x67,0xda,0x0a,0x5d,0xce, + 0x27,0x19,0x92,0x1f,0x1c,0xf8,0xbe,0x08,0x6c,0x98,0x07,0x07,0x42,0x4a,0x7f,0xd8, + 0x38,0xfe,0xd9,0xc7,0x69,0x5d,0x01,0x81,0x56,0xa8,0xd5,0xa1,0xb6,0xd2,0xd3,0xc0, + 0xef,0x4f,0xda,0x78,0xe9,0xfd,0xbe,0x85,0xa6,0xfa,0xf7,0x5c,0xee,0xf4,0xab,0xea, + 0x5d,0x72,0xa2,0x66,0x54,0x3f,0x0a,0x55,0xf5,0xb6,0xa1,0x9c,0xd9,0x68,0xfa,0xef, + 0xd0,0x97,0xec,0xac,0x19,0x81,0x8c,0x96,0x79,0x74,0xc9,0xda,0x6f,0x25,0xf1,0xcf, + 0x29,0x16,0xc7,0x3f,0x83,0x1b,0x4f,0xc3,0x8b,0xfc,0x34,0x45,0x63,0xb4,0x12,0xb1, + 0xc6,0x79,0x97,0xe9,0xcd,0x11,0x9b,0x97,0x24,0xf1,0x8f,0x51,0xff,0x3e,0xa9,0xf2, + 0xd5,0xc5,0xc1,0x9a,0xa8,0x74,0x10,0xba,0xfb,0xad,0x85,0xe2,0x4c,0x38,0x58,0xed, + 0x66,0xce,0x55,0xb2,0x93,0x45,0x3c,0x06,0xff,0xbc,0x89,0xff,0x59,0x72,0x4a,0x7b, + 0x61,0xd6,0xa8,0x65,0x63,0xf6,0xfb,0x5a,0x2b,0xb8,0xcf,0xd3,0x17,0x48,0x11,0xf1, + 0x9f,0x28,0x63,0x74,0x95,0x25,0x83,0xb4,0x0c,0xe0,0xf3,0xff,0xda,0xf3,0x45,0xaa, + 0xff,0x07,0x50,0xc8,0x80,0x32,0x92,0xdd,0x08,0x85,0x51,0x5a,0x99,0xfd,0x75,0xd6, + 0x88,0x82,0x3a,0xa3,0x1c,0xcd,0xf6,0x0e,0xb6,0x42,0x91,0xcb,0x53,0xfb,0x5f,0x28, + 0xbb,0x1a,0x8b,0xa3,0xdf,0xf9,0x71,0xf6,0xbb,0xb0,0xaa,0x31,0xbf,0xcb,0xb1,0x92, + 0x5c,0xe7,0x5b,0x15,0x9a,0xee,0xa3,0xb7,0x91,0x4a,0xdf,0x33,0x9b,0x1e,0x50,0xe5, + 0xbf,0x23,0x97,0x12,0xf6,0x5d,0xbd,0x51,0xff,0x5e,0xd1,0x37,0x30,0x7b,0xc6,0x80, + 0xaa,0xc3,0xce,0x11,0xab,0x4b,0x74,0x6a,0xaf,0xb2,0x39,0xe0,0x9c,0x2e,0x5a,0xe1, + 0x74,0x2e,0x1a,0x56,0x45,0x4d,0xe6,0xfe,0x17,0x7c,0x7d,0x16,0x1c,0xb3,0x9d,0xfd, + 0xc6,0x25,0xb8,0xc4,0xaa,0x9a,0x6d,0x67,0xe5,0x4b,0xda,0x97,0x50,0x55,0x68,0xdb, + 0x22,0x9e,0x94,0xde,0xcb,0xae,0xf2,0xd8,0x46,0x6b,0x06,0x13,0xf8,0xa7,0x2b,0x0d, + 0xd1,0x94,0xe0,0x1e,0x5e,0x1c,0xcc,0x71,0x4a,0x87,0x84,0x6e,0x01,0x0f,0xa6,0xd1, + 0xd6,0x41,0xaf,0x08,0x8b,0xdb,0xc8,0x00,0x7b,0x38,0xb0,0x44,0x37,0xc7,0xbf,0x26, + 0x23,0xc8,0x91,0x6e,0x8d,0xdc,0xd5,0x90,0x3d,0x95,0xae,0xe1,0xd6,0x93,0xcb,0x50, + 0xc4,0xf9,0x3c,0xed,0xb9,0x02,0x0d,0xab,0xfb,0x9b,0x65,0x2f,0x49,0xf2,0x3f,0xeb, + 0xf0,0x34,0x59,0x6f,0x78,0x7b,0xfc,0xd3,0xe0,0x59,0x96,0xaf,0x22,0xda,0xf9,0x2e, + 0x87,0x3d,0x21,0xba,0x14,0x81,0x5f,0x88,0x47,0xc4,0x28,0x49,0xf2,0xbb,0xd6,0xe7, + 0x0e,0x20,0x5a,0x2e,0xec,0x6d,0x29,0xf7,0x5b,0xc1,0x1f,0x54,0xcb,0xf1,0xfe,0xbc, + 0x03,0x66,0x61,0x27,0xfd,0x25,0x1e,0xb4,0xc6,0x7c,0x35,0x2a,0x07,0x3d,0xdf,0xb9, + 0xa6,0xfe,0xdd,0xcd,0xac,0x43,0xb2,0xc3,0x7a,0x84,0x94,0x76,0xdb,0x42,0x72,0x3d, + 0x39,0x88,0x98,0x8b,0x7e,0x24,0xf6,0xb0,0x23,0x01,0x77,0x17,0xee,0x90,0x47,0xff, + 0x95,0xfe,0x17,0x05,0x3a,0xb9,0x64,0x0c,0x6e,0xd9,0x42,0x46,0xab,0x6f,0x83,0x9b, + 0x59,0xac,0x3f,0x2c,0xd8,0x56,0x35,0x6d,0x4c,0xfa,0x1f,0x94,0x58,0x34,0xc4,0xc6, + 0xdb,0x5e,0xf4,0x72,0x36,0xa4,0x20,0x99,0x6e,0x44,0xc4,0x16,0x6f,0x12,0x67,0xb0, + 0x03,0x52,0xa5,0x36,0x29,0x68,0xe2,0x7f,0x0e,0xc5,0xf2,0x7f,0x38,0x69,0x4f,0x21, + 0x31,0xd2,0x4e,0x14,0x92,0xc6,0x5a,0x96,0x75,0x68,0x81,0xa0,0x65,0x86,0xf0,0x96, + 0xb7,0xa4,0x7f,0x51,0xbb,0x45,0x15,0x26,0x3e,0x70,0xb9,0x81,0x97,0x78,0xd9,0xbb, + 0x65,0xba,0xf4,0x6b,0xb0,0x73,0x36,0xbf,0x9d,0x86,0xff,0xa7,0x2e,0x98,0x6d,0x48, + 0x24,0x4d,0xde,0xe0,0xbf,0x36,0xff,0xc7,0x28,0x7b,0x9f,0x82,0xab,0x1d,0xe2,0x85, + 0xf0,0xbf,0x20,0x86,0xff,0x27,0xdb,0x3f,0x09,0x1a,0x35,0xa7,0xd6,0x66,0xe6,0x7f, + 0xee,0xa1,0x6a,0xac,0xda,0x8b,0xc7,0xbf,0x06,0xd0,0xda,0x92,0x51,0xb5,0xa2,0x16, + 0x2f,0x05,0xa7,0xbf,0x46,0x25,0xad,0xbc,0xfe,0x91,0xd5,0xfc,0x36,0x05,0xff,0x7c, + 0x0e,0x15,0xde,0xf5,0xf7,0xd6,0xbc,0x06,0x67,0x79,0xfe,0xcf,0x26,0xf1,0xfb,0x30, + 0xee,0xa9,0xf0,0xde,0x7c,0x4f,0xd3,0xf9,0xf4,0x58,0x21,0x58,0x41,0x92,0xff,0xb9, + 0x3d,0xed,0x3c,0x39,0x00,0x55,0x1e,0xa7,0xb7,0xa9,0x2c,0x74,0xb8,0xab,0x74,0xa1, + 0x75,0xa9,0x58,0xc6,0x5e,0x63,0x55,0xf5,0xd6,0xe3,0x4d,0xb7,0xe2,0x79,0x44,0xfc, + 0xf0,0xa6,0x58,0x92,0x92,0xff,0x13,0x20,0x3c,0xfe,0x9e,0x9d,0xaf,0xb4,0x6a,0x45, + 0x79,0x56,0x46,0x42,0x10,0x50,0x50,0xad,0x77,0x58,0x54,0xd6,0xa3,0xd9,0x21,0xf3, + 0x19,0x3c,0x38,0x09,0x8b,0x21,0xad,0x5f,0x6a,0xcc,0xe0,0x6c,0xcf,0x45,0x92,0x8a, + 0x78,0xcf,0x43,0xaf,0xf3,0xa7,0xf1,0xfc,0xe7,0xda,0x99,0x8a,0x05,0x97,0xc2,0xf1, + 0x02,0xbe,0x78,0x6a,0xfc,0x0b,0x5a,0x48,0x89,0xee,0x08,0xfa,0x79,0xda,0x67,0x51, + 0xf5,0x9d,0x41,0xd2,0xc9,0x38,0x11,0x62,0x46,0xd0,0x52,0x58,0xb8,0xdb,0xf7,0x43, + 0x6f,0x46,0xd0,0x93,0x9e,0xfc,0x5e,0xb9,0x9d,0xb1,0x6e,0x26,0x41,0x79,0x0e,0x39, + 0xe0,0x31,0x68,0x7f,0x0a,0x11,0xdf,0x56,0x7a,0x33,0x37,0x89,0x5f,0x87,0x71,0xad, + 0x5c,0xb3,0xfe,0x5a,0x76,0x24,0xee,0xdf,0x6a,0xe0,0x1f,0x3c,0x74,0xd9,0x22,0x4f, + 0x14,0xdf,0xb7,0x1c,0xed,0xf7,0x33,0xbc,0xfe,0x5d,0xcb,0xba,0x41,0x3c,0xa3,0x9d, + 0x45,0x43,0xfb,0x9a,0xfe,0x17,0x06,0xfe,0x51,0x17,0x37,0xcb,0xc0,0x22,0x5a,0x37, + 0xb1,0x05,0x44,0x1f,0x44,0xa8,0x5b,0x71,0xae,0x96,0xf3,0x61,0x4c,0x35,0x3e,0x8d, + 0xc9,0xff,0xd3,0x4c,0x8d,0xb2,0x77,0xfa,0xa1,0x7f,0x3e,0xac,0x86,0x82,0xa0,0xfc, + 0x11,0x6f,0x0b,0x1b,0xca,0x37,0xfa,0xc3,0xc2,0x7e,0xcd,0x1f,0x90,0xa3,0x24,0xa9, + 0x5f,0x26,0xf2,0x9f,0x03,0x4a,0xb6,0xa5,0xd6,0x0f,0xaa,0x2a,0x77,0x91,0x07,0x35, + 0x56,0xab,0x32,0xb4,0xc7,0x25,0xc7,0x76,0x56,0x18,0x91,0xdb,0x37,0x26,0xf1,0x4f, + 0xbe,0x30,0x95,0xee,0x52,0x8b,0x07,0x03,0xde,0xec,0x3c,0xb6,0x1a,0xf2,0x15,0xde, + 0xb6,0x86,0x03,0xa1,0x46,0x3c,0xbf,0xb9,0x85,0x2f,0x69,0xd3,0x75,0xb9,0xf6,0x1a, + 0xff,0xcf,0x97,0xd1,0x8a,0xa8,0x73,0xa9,0x38,0x0f,0xfa,0xd8,0x6c,0x9f,0xad,0x5e, + 0x7c,0x98,0xf4,0xb3,0x70,0xc8,0xca,0xf3,0x7f,0xae,0xb0,0x97,0x78,0x22,0x90,0x25, + 0xc9,0xff,0x7c,0x53,0xcc,0xfe,0x9a,0x14,0x14,0x87,0x3d,0x7b,0x50,0xf1,0xdd,0xcc, + 0xf3,0x09,0x71,0x05,0xd8,0xdf,0x73,0xfe,0xc3,0x2b,0x30,0x6f,0xd0,0x16,0x2d,0x48, + 0xf5,0xff,0x5c,0x65,0x95,0x85,0xd6,0x95,0x35,0x2f,0x2c,0x3c,0xd2,0x58,0xb9,0xdc, + 0x39,0x26,0xfe,0x0c,0x06,0x98,0xa1,0xd6,0xa7,0x69,0x9f,0xb0,0x1f,0x9d,0xb7,0x9d, + 0x98,0x94,0x67,0x8a,0x7f,0x19,0xf6,0x97,0xc3,0xe1,0xf5,0xdc,0xc0,0x56,0xe7,0x95, + 0xd4,0xd3,0x51,0xf2,0x0b,0xce,0x3f,0xd6,0x4c,0x1f,0xc5,0x17,0xf9,0x9f,0x90,0xdf, + 0x28,0x6b,0xe9,0x49,0xfe,0xe7,0x0d,0x46,0xfc,0xcb,0x49,0x11,0xed,0xb4,0x6b,0xab, + 0xa1,0x38,0x92,0x81,0xaf,0x89,0xf3,0x55,0x96,0x61,0xcf,0x9e,0xa3,0x36,0xc3,0x74, + 0xad,0xcd,0x4b,0xfa,0x4d,0xfd,0x2f,0x06,0x14,0x5c,0x4f,0x81,0x0a,0xa4,0x8b,0xf8, + 0xf3,0x9d,0xbc,0x91,0x41,0x33,0xa2,0x96,0xd0,0xda,0x8c,0xb0,0x85,0xc2,0x53,0xac, + 0x10,0xe4,0x22,0x13,0xfe,0x71,0x4c,0xd9,0xa6,0x5c,0xc5,0xf7,0x5d,0xbc,0x29,0xa7, + 0x8b,0x1c,0xec,0xaf,0x1c,0xcc,0x0c,0x15,0x38,0x89,0x0e,0xee,0x60,0x31,0x5a,0xdc, + 0xf0,0x61,0xe0,0x65,0xc5,0xb6,0x59,0x4e,0xe2,0x9f,0xe0,0x44,0xfc,0x2b,0x28,0xfc, + 0x80,0x3b,0xca,0xd2,0xd1,0xcc,0xff,0x0d,0x19,0x33,0xda,0x5e,0x88,0x51,0x65,0xbc, + 0x6e,0x9e,0xba,0xa4,0x91,0x24,0xfb,0xbd,0x6e,0x88,0xe5,0x3f,0x37,0xd8,0x06,0xb7, + 0xd6,0xc3,0x11,0x69,0xb6,0x4e,0x4f,0x8b,0xcb,0xd1,0x7e,0x99,0xcd,0xa6,0xbe,0x25, + 0xba,0xd4,0xb7,0x61,0x6e,0xba,0x2d,0x4c,0xa2,0x26,0xfc,0xb3,0x02,0x5e,0x41,0xfb, + 0xa2,0x6d,0x9a,0x67,0x9e,0xd2,0xca,0x69,0x7c,0xc6,0xc8,0xd7,0x20,0x10,0xe9,0x60, + 0xb4,0xa7,0x48,0x24,0x5d,0xcc,0x9e,0xd7,0xb6,0xd6,0x3f,0xa4,0x99,0xf0,0x4f,0x4c, + 0x5f,0xb7,0x93,0x92,0xf4,0xa7,0xc0,0xbe,0xcc,0x12,0xc6,0xd3,0x19,0xe0,0x8d,0x57, + 0x42,0xe4,0x16,0xe9,0xc9,0x80,0x1d,0x7f,0x4a,0x8f,0xa6,0xf8,0x7f,0x70,0x7d,0x08, + 0xca,0x1f,0x28,0xf4,0x43,0xc8,0x52,0xc4,0x8f,0x21,0x53,0x1c,0xcc,0xe1,0x46,0x7b, + 0x24,0xc4,0x89,0x02,0x72,0x3d,0x49,0xfb,0x8b,0x51,0x03,0xff,0xd4,0xd9,0x82,0xb2, + 0xc3,0x7f,0x90,0xb8,0x4f,0x64,0x85,0x73,0x9c,0x24,0xa2,0xcd,0x63,0x14,0x0d,0x01, + 0xe9,0x2d,0xce,0xaf,0x8b,0x82,0x37,0x3d,0x19,0xff,0xba,0xa4,0xf0,0xf8,0xd7,0x12, + 0xc4,0x33,0x28,0x9d,0xab,0x5a,0x33,0x79,0x61,0xc5,0x65,0x75,0x2e,0xb3,0xed,0xe4, + 0x8a,0x9e,0xbc,0x02,0x36,0xbd,0x60,0xf8,0x1b,0x13,0xf2,0xc4,0xdc,0x8f,0x6f,0x8d, + 0xeb,0x3f,0x40,0x3f,0x3e,0xd3,0xfd,0x27,0xb9,0xfe,0x9a,0xfb,0x4f,0x64,0x0a,0x59, + 0x23,0xc6,0xa0,0xd4,0x9e,0xb8,0x02,0xb4,0xc9,0xad,0x0e,0xf0,0x9f,0x74,0xd3,0xfc, + 0xff,0xb7,0xfa,0x21,0xc6,0xff,0xa3,0xa5,0xe6,0x6b,0x3c,0xe3,0xec,0xda,0x79,0xff, + 0x4a,0x1b,0xc4,0xaf,0x7c,0x88,0xff,0x17,0xd7,0xff,0xdf,0xe8,0x87,0x08,0xc9,0x2b, + 0xda,0x57,0xfb,0x21,0x0e,0xf0,0xe4,0x1d,0x7d,0x8d,0x2b,0x3e,0x30,0xdf,0x3f,0x76, + 0x25,0x75,0xfd,0x1b,0xc1,0xa0,0x03,0x93,0x26,0x06,0xa6,0x85,0x8c,0x5d,0xb9,0x66, + 0xfd,0xf3,0xf9,0x6f,0xf1,0xa7,0xe5,0x03,0xd3,0xfa,0xc7,0xaf,0x24,0x17,0xc7,0xe8, + 0x87,0x38,0x60,0xac,0x7f,0x7c,0xb5,0x53,0xbe,0x7e,0xec,0xef,0xff,0xf6,0x43,0xfc, + 0xf7,0x07,0xff,0x5f,0x9e,0x4f,0x9a,0xa5,0xd8,0xa1,0xf3,0xa4,0x1e,0xcc,0x1f,0xfd, + 0x5b,0xe7,0x31,0x0d,0x0f,0x5d,0x5a,0x35,0x28,0xec,0xaf,0x3c,0x8f,0xab,0xf9,0xa6, + 0xf5,0x88,0x5f,0x39,0x86,0xf6,0x7f,0x4b,0x1e,0x5a,0x05,0x20,0x78,0x13,0x2d,0xf5, + 0xb6,0x3f,0xfa,0x37,0xe5,0xa1,0x85,0x97,0x28,0xdb,0x51,0x09,0x4d,0x88,0xc1,0xaf, + 0x0c,0x52,0xde,0xd7,0x70,0x3a,0x0a,0x54,0xf3,0x7f,0x55,0xb0,0x11,0x85,0x35,0x7f, + 0x55,0x1e,0x4a,0x2a,0xa5,0x44,0x04,0xfd,0xab,0x62,0xd0,0xaf,0xf0,0xbc,0x86,0xaf, + 0xca,0xc3,0xf8,0xac,0xaf,0xfc,0xfd,0x6b,0xf2,0x30,0x7b,0x8d,0x73,0x0b,0x0f,0x87, + 0x4f,0xed,0xc3,0xd5,0x1e,0x98,0x58,0xff,0x01,0xb3,0x3c,0x4c,0x91,0x27,0x30,0x49, + 0xc1,0xf5,0xf7,0xfc,0xf5,0xf2,0x70,0x8d,0x9a,0x0f,0xd6,0xea,0x49,0x7f,0xbd,0x3c, + 0x74,0x26,0x84,0xde,0x5f,0xd3,0x1f,0x56,0x45,0x63,0x02,0xac,0x35,0xa2,0x97,0xfd, + 0x75,0xfa,0x2e,0x9b,0xf0,0xf5,0x23,0x19,0xe0,0xf9,0xeb,0xf4,0x91,0xc2,0x45,0xa4, + 0x55,0x14,0x81,0xfd,0x95,0xfd,0x61,0x05,0xfe,0x70,0xe2,0xbf,0xba,0xfe,0x13,0x7f, + 0x66,0x79,0xc8,0x73,0x09,0xb4,0x7f,0x7b,0xea,0x35,0x7f,0x15,0x15,0x28,0x70,0x19, + 0x5c,0xb3,0xc4,0xd7,0xfe,0x99,0xe5,0x21,0x59,0x4a,0xfe,0xfa,0xdb,0xf3,0x3f,0x7c, + 0x21,0xf6,0xbf,0x31,0x3d,0x57,0xc8,0xce,0x77,0xfd,0xaf,0xa7,0x25,0xfe,0xfe,0xa3, + 0xc9,0x9f,0xff,0x60,0xf3,0x5f,0xab,0x16,0x1b,0xb4,0x93,0xca,0x5c,0xc8,0xec,0x35, + 0x06,0xff,0x3d,0x37,0xf3,0x35,0xf1,0xa1,0xea,0xfb,0xbc,0x73,0x8d,0x81,0x36,0xb5, + 0xe1,0x6b,0xd2,0x64,0x7d,0x76,0x62,0xfe,0xed,0xb5,0x69,0x0f,0x09,0xf7,0x69,0x7f, + 0xab,0x40,0xbf,0x31,0xf0,0x2a,0x53,0x8c,0x81,0xef,0x6f,0x71,0x20,0xe4,0x1b,0x3f, + 0xa5,0xe9,0xb3,0x27,0xf0,0x2a,0x34,0x7b,0x04,0x95,0xd5,0xa9,0xd9,0x14,0xfa,0x62, + 0x83,0x3c,0xc9,0x1f,0xbf,0x22,0xad,0x16,0xf2,0x63,0x03,0x96,0xfc,0xa0,0x0c,0x04, + 0x1f,0x2c,0x85,0xeb,0xe0,0x7f,0x32,0x63,0x70,0x2f,0x4d,0x5b,0x2d,0xdc,0xcf,0x96, + 0x6a,0xd7,0x29,0x69,0x78,0x45,0x58,0xaa,0x7d,0x1b,0xd2,0x12,0xe1,0x68,0x7c,0xfe, + 0xa5,0x69,0x65,0xc2,0x5d,0xec,0x5b,0xd5,0x52,0x20,0xed,0x61,0xe1,0x3e,0xfd,0x6f, + 0xd5,0x29,0x91,0xb4,0x87,0xe1,0x3e,0xf6,0xb7,0xce,0x29,0x07,0x85,0x7b,0x84,0xfb, + 0xd8,0xb7,0xd4,0x5c,0xd3,0xf3,0xbc,0xa6,0x69,0xaa,0x42,0x25,0x22,0x00,0xef,0xf0, + 0x99,0x07,0xe9,0x20,0x30,0x25,0x3e,0x58,0x25,0xf9,0x58,0xec,0x4a,0xf2,0x7d,0x5f, + 0xab,0x93,0x96,0x09,0x79,0xec,0x0e,0x80,0x80,0x64,0x17,0x28,0xf3,0xa8,0x4a,0x40, + 0xc2,0x53,0xce,0x07,0xcd,0x92,0x2a,0x50,0x3c,0xd7,0x8a,0x79,0xfe,0xc2,0xb4,0x7b, + 0x1a,0xef,0x0d,0xfd,0x0d,0x95,0x68,0x9a,0xa7,0xd1,0x3b,0x2a,0x39,0xa6,0x58,0xd2, + 0xb4,0x46,0x6f,0xe8,0xde,0xf2,0x29,0x62,0x9a,0xc6,0xbc,0xea,0x94,0xa9,0x53,0xb4, + 0xe4,0xf3,0xb0,0xa9,0xc2,0xdf,0xc2,0xdf,0xe8,0x53,0xbc,0xa8,0x06,0xf8,0x60,0x72, + 0x43,0xda,0x7d,0xc2,0xb7,0xd8,0xbd,0xfa,0x14,0x17,0x0e,0x44,0xc0,0x41,0xb9,0x94, + 0x30,0xbf,0x70,0x3e,0xae,0x1d,0x64,0x83,0x14,0x02,0xee,0xf4,0x50,0x34,0x81,0x8b, + 0xc0,0x1a,0x2e,0x0b,0x15,0x41,0x42,0xa8,0x85,0x6a,0x4a,0x81,0x6a,0xd3,0xfa,0xf8, + 0xb8,0xa3,0x1a,0xcd,0x0e,0x30,0x3c,0xd6,0x80,0x86,0xb2,0x1a,0xbf,0x42,0xd5,0xf4, + 0xf8,0x4f,0xd5,0xa6,0xf5,0xf1,0x66,0x2c,0x17,0xfe,0x0e,0xbe,0xad,0x15,0xb2,0xb4, + 0xe5,0x69,0x7c,0x30,0x25,0x98,0xe6,0x23,0x27,0xe0,0xdb,0x80,0x03,0x55,0x38,0x01, + 0xff,0x04,0x0b,0xcc,0xef,0xab,0x89,0xbc,0x51,0x6a,0x99,0x2a,0xb1,0xd8,0x80,0x87, + 0x32,0x96,0xe1,0x60,0x86,0x31,0x10,0x96,0xb2,0xeb,0xf0,0x7b,0x99,0xf6,0x8f,0x47, + 0x72,0xf5,0x5a,0xd5,0x1a,0x9a,0xe7,0x97,0x5c,0x8d,0x7c,0xa0,0xf4,0x49,0x2e,0xdd, + 0xaa,0x56,0x53,0xe5,0x55,0x88,0x5d,0xc9,0xd3,0x27,0x27,0x9e,0x07,0xb8,0xc4,0xb2, + 0xc6,0xe4,0x5b,0x7c,0xa0,0x4f,0x0c,0x22,0xb1,0x81,0xaa,0x99,0x36,0x35,0x23,0x82, + 0x4b,0x5f,0xac,0xe6,0x50,0xdc,0x66,0x2e,0xc6,0x07,0xb5,0x7d,0x82,0xab,0xd1,0xb8, + 0x72,0x90,0xff,0xe4,0xfa,0x96,0x53,0xd2,0x4d,0xeb,0xe3,0x49,0xf3,0x35,0x2e,0x55, + 0xbf,0x8d,0xf3,0xe3,0x83,0x29,0x38,0xe8,0x35,0x06,0x4d,0x82,0xda,0xbb,0xd4,0xf5, + 0x6d,0xeb,0x14,0xf3,0xfe,0xf1,0x18,0x2b,0x97,0x58,0xc2,0xf8,0x40,0x32,0x06,0x92, + 0xca,0xac,0xaa,0x48,0x85,0xd4,0xf7,0xf5,0x35,0xe6,0xa9,0x77,0xe0,0x47,0xc3,0xc1, + 0xf5,0xea,0x1d,0x74,0xb2,0x5f,0x5a,0x8e,0xaf,0x79,0x47,0xdd,0xe4,0x8d,0x92,0xca, + 0xdf,0xb7,0x2e,0x65,0xff,0xf8,0xd2,0x96,0x0a,0xdf,0x86,0xbf,0x61,0x69,0x3e,0x29, + 0x36,0x98,0x82,0x57,0xa4,0x3b,0xe0,0x76,0x3e,0xa0,0xc2,0x1d,0x30,0x99,0x49,0xa6, + 0xfd,0xd3,0x9b,0x2e,0x3c,0xc4,0xee,0xf5,0x4d,0x69,0x4f,0xbb,0x43,0xa8,0x66,0x5e, + 0x5f,0x6e,0x9e,0x90,0x8e,0x03,0x65,0x62,0xc0,0xaf,0xa4,0x25,0xcc,0x7d,0x3c,0x8f, + 0x5c,0x8d,0x50,0x54,0x01,0x4a,0x36,0x1e,0x81,0xea,0xd8,0x59,0x90,0x18,0x1e,0x8a, + 0x3a,0x89,0x5f,0xe1,0x83,0xdc,0xa4,0x7b,0x09,0x5e,0xbb,0x83,0x4c,0x66,0xcd,0xbe, + 0x7c,0x85,0xde,0x21,0x7e,0x93,0x1d,0xf7,0xdd,0x9a,0x97,0xc9,0x07,0xf7,0x1a,0x83, + 0x49,0xf1,0x2b,0xa6,0xe7,0x79,0x2d,0x3d,0xed,0xa1,0x46,0x94,0x06,0x79,0x53,0x5e, + 0x97,0x62,0x83,0xb4,0xd7,0x13,0x57,0x70,0x70,0xd2,0xf7,0xdf,0xf3,0xa6,0x98,0xe5, + 0xc9,0x1d,0xe2,0x43,0x6c,0xb3,0x6f,0x2e,0x4e,0x23,0x7c,0xf0,0xdf,0xf3,0x32,0x5e, + 0xc7,0x2b,0xf7,0xe1,0x95,0xcc,0xd7,0x27,0x3d,0xc4,0xa6,0xfa,0xbe,0x86,0xf3,0x27, + 0x9b,0xe6,0xc7,0xee,0xb6,0x94,0xa6,0xdc,0xd6,0x6a,0x0c,0x94,0xd9,0x38,0xa8,0xe1, + 0xf3,0x4d,0xfb,0x47,0x50,0x81,0x9f,0x98,0xb4,0x84,0xd8,0xe1,0x83,0xfb,0x8c,0x01, + 0xf0,0xc1,0xd7,0x50,0xfe,0x98,0x76,0x5b,0xfa,0x64,0x94,0x36,0xbe,0xeb,0xf2,0x62, + 0x62,0xc7,0xf7,0x6d,0x63,0xd0,0x18,0xbb,0x92,0x96,0xdf,0xc8,0xaf,0x4c,0x31,0xcd, + 0xbf,0x5d,0x4b,0x73,0x09,0x8b,0xc9,0xb7,0x40,0x62,0x69,0x0d,0xc2,0x7d,0xf0,0x35, + 0xc8,0xd5,0x8d,0xc1,0xdf,0xc2,0x14,0x1d,0x7f,0x8a,0x0d,0x92,0xcf,0x73,0xbb,0x69, + 0xff,0xa0,0xb4,0x51,0xa5,0x89,0x41,0x3a,0x15,0xf8,0xf3,0x18,0x03,0x66,0x7a,0xdf, + 0xf8,0xfe,0x31,0x76,0x57,0x23,0xff,0x87,0x93,0x63,0x03,0x0f,0x55,0xfc,0xf8,0x13, + 0x1f,0x78,0xcd,0xf3,0x6b,0xd2,0xbc,0xbd,0xf7,0xba,0xfe,0x86,0xae,0x22,0x5c,0xec, + 0xa8,0xb9,0xd6,0x29,0x1e,0x49,0x6b,0xf6,0xaa,0xf7,0xd2,0x29,0xa2,0xe0,0x45,0xf9, + 0x93,0x4b,0xd3,0xc0,0xb4,0x3e,0x62,0xbe,0x37,0x72,0xaf,0x6b,0x0a,0x95,0xf0,0x57, + 0xfd,0x5e,0x75,0x8a,0x35,0xad,0x86,0x0f,0x5c,0x38,0xf0,0xc4,0x06,0x34,0x4d,0x33, + 0xad,0x0f,0x68,0x9a,0xa2,0x48,0x92,0xa0,0xc4,0x24,0x1f,0x82,0xa6,0xf8,0x40,0x45, + 0x41,0x14,0x1b,0x4c,0x36,0xcd,0xbe,0x7d,0x21,0x21,0x8c,0x85,0xd4,0xba,0x76,0x3f, + 0x02,0x21,0xa6,0xaa,0x0e,0x4a,0x62,0x03,0x04,0x99,0xe9,0xf1,0x81,0xe9,0x79,0x6e, + 0xd7,0xb8,0x90,0x47,0x69,0x93,0x8b,0x27,0x40,0xe0,0x8a,0x60,0x0a,0x0e,0xc0,0x90, + 0x3f,0xfc,0x0a,0x97,0x3f,0x53,0x4c,0xef,0xbb,0x4a,0x13,0xf9,0xaf,0xd7,0xc1,0x49, + 0x26,0xc6,0xe4,0x4f,0x1a,0xcb,0xf6,0x49,0xf7,0xc5,0x04,0x91,0x0f,0x8c,0x2f,0x62, + 0xfe,0xbe,0x90,0xeb,0x12,0xb8,0xf4,0x60,0x4c,0xe2,0x03,0x14,0x9d,0x3a,0x0e,0xf2, + 0x8c,0x81,0xa2,0xe2,0xe0,0x8e,0x54,0x28,0x25,0xc5,0x84,0x8c,0x86,0x17,0x67,0x83, + 0x55,0xc3,0xc1,0x71,0x98,0x03,0x19,0x60,0x0c,0x0a,0x71,0x40,0xb4,0x94,0xf9,0x69, + 0xc2,0x6c,0x6d,0xb1,0x37,0x27,0xb8,0x69,0x15,0x1f,0x68,0x62,0xae,0xf4,0x9a,0x30, + 0xfb,0x76,0xbc,0x92,0x2b,0xbd,0x2e,0xcc,0xae,0x5e,0xec,0xfd,0x96,0x52,0x6b,0x9e, + 0xff,0xf5,0xb4,0xfa,0xde,0xef,0xb8,0xbe,0x1d,0x48,0xdb,0x8a,0x83,0x1b,0x5c,0xf7, + 0xac,0x9d,0xf2,0x5c,0xec,0xca,0xda,0x29,0x5b,0x85,0xf8,0xc0,0x3c,0x3f,0x23,0x06, + 0xf4,0xf9,0x7f,0xd4,0x48,0x6a,0xf4,0x19,0x4d,0xc5,0x8c,0xc7,0xd8,0x24,0xfd,0x2b, + 0xcf,0x03,0xcb,0x7d,0x93,0xf3,0xa4,0x3b,0x04,0x08,0xd4,0x72,0x45,0xe6,0x11,0x26, + 0x07,0xa4,0x65,0x93,0xf3,0x9a,0xef,0xc8,0x9f,0xcc,0x6a,0x27,0x06,0xe6,0xf9,0xb7, + 0x7b,0x27,0xdf,0x2b,0xdd,0x8e,0xa8,0x32,0xcd,0x3b,0x39,0x57,0xfa,0x1b,0x61,0x8a, + 0x76,0xbb,0x17,0xee,0x95,0xfe,0x06,0x26,0x6b,0x1f,0x78,0x5d,0xf7,0x4a,0x53,0xf0, + 0x8a,0x69,0x3a,0xcd,0xe7,0x7b,0x59,0xc1,0x2d,0xc9,0x83,0xc5,0xfe,0x5c,0x35,0xad, + 0x4e,0xf0,0x38,0x14,0x96,0x8b,0xba,0x31,0xff,0x1e,0xea,0x6d,0xcd,0x55,0x57,0x99, + 0x6f,0x6f,0x11,0x78,0x16,0x94,0xd7,0x21,0xf1,0x81,0x16,0x52,0x1c,0xca,0xc4,0x60, + 0xe2,0x8a,0xd3,0xec,0x7d,0x00,0x2b,0x9e,0xad,0x66,0xfd,0xfb,0xae,0xeb,0x17,0x8b, + 0xdf,0x82,0xe3,0x7d,0xb7,0xba,0xa8,0x31,0xd0,0x6f,0x75,0x65,0x2e,0x4e,0xcf,0x31, + 0x06,0x29,0xfb,0x33,0x23,0xed,0xe1,0xea,0xfb,0x82,0x1c,0x06,0x48,0x88,0x07,0xd8, + 0x37,0x62,0x78,0xe0,0x24,0xe3,0x57,0xa6,0x2f,0x13,0x4e,0xb2,0xff,0x5e,0xf8,0xa4, + 0x6e,0x9a,0x2f,0x7f,0xc7,0xf3,0x87,0xe0,0x4b,0x9d,0xc5,0x19,0xb7,0x2c,0xc4,0xc1, + 0xce,0xce,0xe2,0x3b,0xe5,0x7b,0x16,0x0e,0x6e,0x7c,0xa9,0xf0,0x37,0x19,0xb2,0x67, + 0xe1,0x71,0x63,0x60,0x7e,0x9e,0xf9,0x57,0xef,0xbe,0xfa,0xfb,0x57,0xce,0x7f,0x32, + 0x5e,0xf5,0x73,0x1c,0xec,0x3a,0xff,0x97,0xf1,0xf9,0x57,0x96,0xbc,0xf7,0xf8,0xd5, + 0xa1,0xcb,0xe3,0xf3,0x7f,0xb6,0xe4,0xaa,0x31,0x80,0xff,0x83,0xbf,0xca,0x27,0x33, + 0x66,0x78,0xee,0x0c,0x6e,0x5c,0x3e,0x7d,0xdc,0xf6,0x6c,0xcd,0xd5,0xe0,0xc6,0x9f, + 0x56,0xfe,0xf3,0x9d,0x3f,0x3f,0x76,0xe7,0xf9,0x27,0x2e,0x57,0x5d,0xbd,0xf3,0xeb, + 0x7c,0x30,0x64,0x9e,0x5f,0xf5,0xb3,0xbb,0xdf,0x7b,0x7c,0xd7,0xd0,0x27,0x13,0x8f, + 0xf1,0xc9,0xe5,0x89,0x07,0xc3,0xf9,0x77,0xbf,0x67,0x3c,0xa1,0x79,0x7e,0xc1,0xcf, + 0xea,0xde,0xdb,0x38,0x77,0x68,0xed,0xfd,0xf3,0xf9,0x3f,0xdc,0x3e,0xf4,0x18,0x3e, + 0xf6,0xdd,0xef,0xe6,0xf0,0x3b,0x14,0xe4,0xf1,0x41,0xf3,0xc8,0xfd,0xe6,0xf9,0x82, + 0xa7,0x41,0xdb,0xac,0x7c,0x3d,0x3b,0x43,0x8f,0x0d,0x72,0x33,0x5e,0x4b,0x6f,0xd0, + 0xa7,0x2a,0x93,0xa4,0x8c,0xd7,0x08,0xe2,0x43,0xbc,0x22,0x98,0xd7,0x53,0x8a,0xe1, + 0xc3,0xa9,0x71,0x7c,0xc8,0x61,0xe1,0xa4,0x87,0xe0,0x3e,0xed,0x6b,0x0a,0x17,0xd4, + 0x38,0xa8,0x41,0x7c,0x68,0x9a,0x2f,0x4e,0xe0,0x43,0x43,0x3e,0xbb,0x10,0xda,0xb0, + 0x24,0x3e,0xe4,0x83,0xaf,0x95,0xa7,0x9e,0xdf,0x18,0x6c,0x53,0x58,0x1c,0xbf,0x71, + 0xb1,0x79,0xbf,0x71,0x45,0x60,0x70,0xbf,0x94,0x47,0xd2,0x55,0xc1,0x3c,0x9b,0xfe, + 0xff,0xda,0x39,0xbf,0xd8,0x28,0x8a,0x38,0x8e,0xff,0xe6,0x6e,0xef,0xd8,0x2b,0x77, + 0x65,0xb7,0xbd,0xc2,0x15,0x9b,0x66,0x8f,0x2b,0x47,0xfd,0x13,0xdc,0x22,0xc5,0x1a, + 0x4c,0x3b,0xed,0xed,0xb5,0x47,0xd3,0xc2,0x81,0x80,0x40,0x8c,0xb9,0x2a,0x21,0xc6, + 0x27,0xd0,0x17,0xa3,0x41,0xf6,0xca,0x41,0x8c,0xd1,0xa4,0xa9,0x35,0x96,0x04,0xf5, + 0x30,0x6a,0x8c,0x81,0xf8,0xe0,0x9f,0x90,0x18,0x93,0x05,0x8d,0x48,0x34,0x29,0x0f, + 0xf0,0xa2,0x26,0x42,0xe4,0xc5,0xc4,0x84,0x3e,0x90,0x18,0x1f,0xea,0xf9,0x9b,0x99, + 0xbd,0xee,0x1e,0x44,0x88,0xc8,0xbe,0x98,0xf9,0x3e,0x7d,0xbb,0x37,0x37,0x3b,0x37, + 0xf3,0xbb,0xdf,0x7c,0x7e,0xdb,0xdd,0xb3,0x9e,0x23,0xf1,0xc9,0x5c,0x18,0xce,0x5b, + 0xeb,0x48,0x47,0x65,0xc4,0xd0,0xd9,0x43,0x35,0x1d,0x18,0x18,0xfa,0x0f,0x18,0x21, + 0x68,0x54,0xdd,0x69,0xec,0x3f,0xa5,0x56,0x42,0x7c,0x2b,0x84,0x94,0xc6,0x68,0xd0, + 0x32,0xc4,0x89,0xca,0xee,0xa9,0x89,0x7f,0x3c,0x2a,0x62,0x21,0x26,0x0d,0x0b,0xf9, + 0xf0,0x29,0xc6,0x87,0x25,0x6d,0x56,0xd9,0x27,0xcc,0x71,0x25,0x5b,0x8e,0x31,0xe3, + 0x6f,0xff,0xa0,0x32,0x5a,0x5e,0x5e,0xcd,0xdb,0xda,0x5a,0x65,0x4f,0xb9,0xa5,0x6a, + 0x7d,0xa4,0xdf,0x07,0x7b,0xce,0xa0,0x39,0xad,0xdf,0x8f,0x2f,0xa1,0x99,0xf5,0xe5, + 0x4f,0xd5,0x49,0x40,0x2b,0xdb,0x52,0x3e,0x83,0x31,0x4c,0x5a,0xc9,0x0b,0xb0,0x9e, + 0x8c,0x01,0xee,0x36,0x4e,0xa4,0x8f,0x8c,0x91,0x56,0x58,0xce,0x36,0x19,0xea,0xbd, + 0xc1,0x89,0x22,0x0b,0x22,0x0d,0x6e,0x85,0x0a,0x05,0xf6,0x98,0x20,0x25,0x1a,0x58, + 0x98,0xc5,0x94,0x22,0xd1,0xb4,0xa4,0xa2,0x33,0xe3,0xed,0xef,0xaa,0xc3,0xca,0x55, + 0xcc,0xc2,0x5d,0xe2,0x4a,0x81,0xc6,0x36,0xa4,0x10,0xcb,0x7a,0xac,0x30,0x6b,0x61, + 0x65,0x9f,0x01,0xd0,0xd0,0x5e,0x29,0x11,0x06,0xc9,0x3c,0xe3,0xa7,0xc8,0x10,0xe3, + 0x91,0x12,0x99,0x85,0x7d,0x68,0x22,0xcc,0x0c,0x43,0x8f,0xc7,0xf3,0x1a,0xa1,0x98, + 0xa1,0x66,0x21,0x6b,0x20,0x99,0x71,0x03,0x31,0x61,0xd6,0xa1,0x01,0x66,0xd6,0x00, + 0xae,0x60,0x5d,0x94,0xf1,0x21,0x87,0x22,0x38,0xec,0xe3,0x43,0xd7,0x70,0x3e,0x1c, + 0x56,0x1d,0x47,0x5f,0x7c,0x9e,0x11,0xfe,0x89,0x0f,0x43,0x7e,0xa3,0xd5,0x67,0x88, + 0x2a,0x43,0x60,0x72,0x48,0x83,0xaf,0xeb,0xe6,0xec,0xa2,0xd1,0x84,0xa1,0x1e,0x6f, + 0xd0,0xfa,0xfe,0x1b,0x87,0x49,0x77,0x23,0xd6,0x3d,0x13,0xe1,0x06,0x3f,0xf8,0xe2, + 0xfe,0x45,0x09,0xdf,0xdf,0xd3,0x37,0xf2,0xe1,0xe2,0x8e,0xcf,0x8d,0x17,0x0f,0x45, + 0x72,0xab,0xfe,0x71,0xa3,0xe7,0xc6,0x6b,0x4f,0xf3,0x14,0xd7,0x2f,0x09,0x79,0x28, + 0xd6,0x8d,0x7e,0xb3,0x19,0x5a,0x1c,0x4f,0x01,0x57,0x6a,0xd0,0x4e,0x96,0x96,0xb0, + 0x25,0xdb,0x8a,0x58,0xa8,0x20,0x16,0x7a,0x66,0x50,0x18,0x2f,0x7c,0x0a,0xec,0x96, + 0x12,0xbb,0xce,0x8b,0x36,0x56,0x18,0xa2,0x56,0x72,0x8b,0x26,0x43,0x18,0xf0,0x8d, + 0x67,0x27,0xd2,0x20,0xf2,0x61,0x11,0x76,0x22,0x28,0x5e,0xe2,0x58,0x18,0x22,0x2e, + 0x28,0x12,0xe4,0x43,0xda,0x9b,0x8a,0x50,0x6f,0x7f,0x27,0xc3,0x88,0x85,0x1d,0xa5, + 0x91,0x54,0xfb,0xb7,0xae,0xd1,0x3d,0x13,0xe5,0x66,0x57,0xbb,0xe3,0xf5,0x4f,0x86, + 0x39,0x16,0xae,0x41,0xba,0x23,0xc2,0xc4,0x58,0xb3,0x9f,0x27,0x98,0x01,0x71,0x24, + 0xe9,0x2c,0x5e,0x9e,0x28,0xd6,0xf9,0x30,0x05,0x47,0x49,0x4f,0xf9,0x89,0x09,0x86, + 0x85,0x4b,0x0e,0x94,0xc7,0x38,0x1f,0xb6,0x09,0x74,0xb4,0xce,0x7a,0xeb,0x05,0xec, + 0xb7,0x31,0x91,0x0f,0xa9,0x32,0x45,0x4a,0xf6,0x26,0x5e,0x8d,0x92,0x2e,0x7b,0x97, + 0xd1,0x52,0x50,0xa6,0x45,0x22,0x2a,0xe0,0x91,0xc5,0xf8,0xc1,0x00,0x9e,0xb0,0x53, + 0xa5,0xe8,0x6c,0xf1,0x43,0x34,0x2b,0x4b,0xd1,0x14,0x39,0x2a,0x8e,0xb8,0x66,0x22, + 0x9a,0xc2,0xf5,0xaa,0xb7,0x87,0x7c,0x49,0x79,0x21,0xdd,0xac,0xe6,0x70,0xcf,0x53, + 0xfa,0x48,0x27,0xe4,0x6c,0xed,0xb2,0xd2,0x07,0x9d,0x30,0x62,0xeb,0x97,0xf9,0x91, + 0x11,0x9b,0x38,0xbe,0xf8,0xd9,0x06,0xa5,0xcb,0x6a,0x5f,0x68,0x0c,0xde,0xc0,0x52, + 0xaf,0x5d,0x84,0x4d,0x17,0xc3,0xc2,0x02,0x99,0x16,0x7c,0x58,0xf0,0xe5,0x1f,0x1a, + 0x09,0x29,0xc6,0x09,0xce,0x87,0xaf,0x56,0x90,0x06,0xab,0x22,0x7e,0xec,0x06,0x3e, + 0xf4,0xc5,0x1b,0xcd,0x87,0x14,0x5a,0x4e,0x1a,0x79,0xfc,0x5e,0x28,0xc5,0xb2,0x86, + 0x46,0xcf,0x41,0xf1,0x88,0x66,0x58,0xaa,0x1e,0xe6,0x47,0x2c,0x95,0x80,0x6f,0x7e, + 0xb0,0xa4,0x74,0x92,0x66,0x24,0x6e,0x8f,0x1a,0xe0,0x24,0xab,0x24,0x4e,0xb0,0xbd, + 0xcd,0x8e,0x30,0xc3,0x5f,0x22,0xd4,0xfb,0xbe,0x60,0xd6,0x30,0x05,0x1f,0x02,0x0d, + 0x61,0xfe,0xe1,0xf5,0xa9,0xcb,0x87,0x6a,0x52,0x98,0x41,0x7f,0xfc,0x0c,0xad,0x6a, + 0x61,0x7c,0x98,0xb0,0x43,0x59,0xcc,0x43,0xab,0xd2,0xdd,0x6a,0x53,0x9d,0x0f,0xeb, + 0xc6,0xf6,0x8d,0x87,0xd0,0x0a,0xcf,0x3f,0x24,0x6d,0x1f,0x45,0xa3,0xf2,0x7a,0x88, + 0xa5,0x65,0x61,0xd8,0x4b,0xa1,0xdd,0xbe,0xcf,0x4b,0xe8,0x7b,0x7b,0xe1,0x18,0x64, + 0x07,0x63,0x53,0x93,0x25,0x38,0xd6,0x94,0x65,0xf7,0x67,0xb9,0x89,0xc8,0x35,0xa1, + 0x98,0xb7,0x5e,0x14,0xd7,0xab,0x8f,0x34,0xe3,0x32,0xd9,0x55,0xd7,0xb0,0xf5,0x6a, + 0x30,0x65,0xcd,0x5b,0xaf,0x22,0x7e,0xbc,0x47,0x9c,0xe6,0xfd,0xe1,0xe3,0xf6,0x07, + 0x86,0xc9,0x7e,0xdd,0x5e,0x81,0x2b,0xe0,0x9a,0x33,0x75,0xe3,0xcb,0x3f,0x98,0x59, + 0x7b,0x69,0xa2,0x18,0x2e,0x22,0x3d,0xf6,0xd0,0x04,0x0d,0x6f,0x87,0x4b,0x0c,0x2c, + 0x8b,0xe1,0x24,0x33,0x94,0x9b,0xb3,0xbe,0xf9,0xc9,0x29,0xa5,0xc1,0xd4,0x7e,0x5c, + 0xdf,0xc3,0x4a,0xe9,0x4c,0xca,0x1c,0x8e,0xeb,0x37,0x9b,0x86,0xf9,0x11,0x7c,0xc8, + 0x2e,0x46,0xf2,0x8b,0x85,0xec,0x8a,0x70,0xc3,0xe5,0xc3,0x86,0x4b,0x85,0x94,0x14, + 0x2c,0xc1,0x87,0x36,0xa7,0x41,0x34,0x3e,0x2c,0x64,0x66,0x26,0x97,0x6e,0xcc,0x3f, + 0xd6,0xf6,0xf6,0xb6,0x68,0x3e,0xa7,0x25,0xf7,0x32,0x3e,0xcc,0x63,0xc6,0xb1,0xb8, + 0xe1,0xf9,0x07,0xcd,0x20,0x1a,0x5f,0xfc,0xf0,0x48,0x0c,0xb9,0x29,0x50,0x9b,0x8c, + 0x18,0xa4,0xc0,0x62,0x6a,0x92,0x5f,0x3b,0xd9,0x26,0x0c,0xf8,0x84,0x10,0xe8,0x40, + 0x15,0xba,0xa1,0x09,0xf8,0xed,0xf2,0xc2,0xf8,0xf9,0xb0,0xbb,0x21,0xff,0x8c,0x87, + 0x1f,0xa3,0x95,0x0b,0xe9,0xf5,0xf6,0xf8,0xaa,0x56,0xfa,0x0d,0x1a,0x75,0x3c,0xd4, + 0x4a,0x2f,0x5e,0xe8,0x5d,0x9f,0x18,0x0f,0x85,0xb9,0x89,0xfb,0xc6,0x43,0x0a,0x15, + 0xdc,0xf4,0xa7,0x70,0xf7,0x3f,0xcf,0xf8,0x10,0x5c,0xc3,0x79,0xe0,0x3b,0xd7,0x24, + 0x1d,0xdf,0x78,0x38,0x16,0x32,0x3e,0x5c,0x3a,0x3a,0xea,0xe7,0xc3,0xf7,0xeb,0x7c, + 0xb8,0xb7,0x91,0x0f,0x39,0x7d,0x31,0x3e,0xdc,0x78,0x68,0x8b,0x9f,0x0f,0xaf,0xdf, + 0x25,0x3e,0xe4,0x58,0xf8,0xdb,0x54,0x6d,0x61,0xe0,0x4f,0x01,0x8a,0x07,0xbb,0xde, + 0x65,0x58,0x38,0xf5,0xd6,0xc2,0xea,0x9a,0x6b,0xfc,0xed,0xf9,0xd9,0xff,0xb8,0x8a, + 0xed,0xff,0x12,0xa0,0xb8,0xb0,0xf1,0x10,0xc3,0xc2,0xab,0xd7,0x16,0x36,0xd6,0x5c, + 0xd3,0xd0,0xbe,0xd3,0xe5,0xc3,0x4c,0xe7,0xe6,0x5f,0xa6,0x7b,0x90,0x0f,0x33,0x2f, + 0x6f,0x3e,0xc7,0x09,0x33,0xc3,0x51,0xb3,0x72,0xed,0x3f,0x8c,0xdf,0x04,0x83,0xb0, + 0xdb,0x33,0x4c,0xc8,0xc5,0xef,0xbc,0x17,0x29,0x29,0x29,0x29,0x29,0x29,0x29,0x29, + 0x29,0x29,0xa9,0xff,0xbb,0x78,0xed,0xa0,0xc8,0xda,0x41,0x4a,0x4a,0x4a,0x4a,0x4a, + 0x4a,0x4a,0x4a,0x4a,0x4a,0xea,0xd6,0xe2,0xb5,0x43,0x54,0xd6,0x0e,0x52,0x52,0x52, + 0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0xb7,0x16,0xaf,0x1d,0x54,0x5e,0x3b,0xe0, + 0x5f,0x91,0xbe,0x27,0x77,0xd3,0x81,0xfe,0x97,0x76,0x07,0x74,0xb6,0xee,0x73,0xf0, + 0x00,0xcd,0x58,0xd0,0x70,0x13,0xda,0x5d,0x94,0xd2,0xf4,0xcc,0x31,0x7b,0x69,0xdb, + 0x97,0x85,0x60,0xba,0x87,0x81,0x39,0x36,0x7e,0x0a,0x03,0x4e,0x30,0xfd,0x2b,0xc6, + 0xcc,0x09,0x67,0xe5,0xc5,0xd7,0x5f,0x09,0xa6,0x7b,0x30,0xe7,0xcc,0xdf,0x69,0x66, + 0xbf,0x63,0x3a,0xc1,0xf4,0x9f,0x78,0xf8,0xe0,0x11,0xa7,0xe3,0x93,0xa7,0xb7,0x04, + 0xd3,0x3d,0xce,0xbf,0x18,0x7f,0x50,0xf3,0x1f,0x5f,0x73,0xdc,0x86,0x47,0x57,0x54, + 0x83,0x9b,0xff,0x65,0x18,0x3f,0x5b,0x20,0xa8,0xf9,0x6f,0xce,0x9e,0x9e,0x87,0x7b, + 0x76,0x7c,0xbe,0x29,0x98,0xee,0x71,0xfe,0xc5,0xf8,0x03,0x8b,0xff,0xb5,0x6d,0x1f, + 0xd3,0xa5,0xcf,0xcf,0xa8,0xb7,0x6f,0x7a,0x47,0x32,0xe7,0x06,0x30,0x7e,0x0e,0x05, + 0x17,0xff,0x1a,0xd9,0x00,0xab,0x63,0xf7,0x06,0x17,0xff,0x62,0xfc,0x41,0xcd,0x7f, + 0x22,0x6d,0x0d,0xc3,0xba,0xeb,0xd9,0xa0,0xe2,0xc7,0xac,0x39,0x2c,0x7f,0x9a,0xf3, + 0x4e,0x30,0xfd,0x2b,0xea,0x81,0x37,0x9d,0x0d,0x9f,0xce,0x04,0x96,0xff,0xdd,0xf1, + 0xdf,0xfc,0xcb,0x04,0x77,0x47,0x4a,0x66,0xe6,0x94,0x93,0x59,0x31,0x1d,0x58,0xfe, + 0xa9,0xcd,0xb3,0xfc,0x39,0x1f,0xd4,0xfc,0x2f,0xeb,0xff,0xf5,0x9a,0xd3,0xfb,0xe3, + 0xe3,0x73,0xc1,0x74,0x8f,0xf3,0x2f,0xc6,0x1f,0xd8,0xfc,0xf7,0xbf,0xf6,0x8e,0xfd, + 0xd0,0x8a,0x93,0xb1,0xdb,0x37,0xbd,0x23,0x99,0xb5,0x39,0x96,0x3f,0x03,0x8b,0xff, + 0x68,0xe7,0xa9,0x67,0xed,0xec,0x57,0x3f,0x59,0xc1,0x74,0x8f,0xf3,0x2f,0xc6,0x1f, + 0xd8,0xfc,0xaf,0xde,0xf1,0x05,0x18,0x6d,0x6f,0x07,0x97,0x7f,0x6a,0x2c,0x7f,0x06, + 0x17,0xff,0x2b,0x23,0x69,0xda,0x7f,0x32,0xf1,0x7d,0x30,0xdd,0xb3,0x1f,0x39,0xe1, + 0xe3,0x0f,0x66,0xfe,0x4d,0xf6,0x7c,0x1c,0xbc,0xd8,0x6a,0x82,0xcd,0x9e,0x5a,0x09, + 0x9b,0x40,0xff,0xf5,0xff,0x13,0xdc,0xf7,0x46,0x4c,0xa8,0x12,0xaf,0xcf,0x2b,0x7b, + 0x6e,0x6c,0xf7,0x37,0xea,0xe7,0xba,0x8f,0xf0,0x33,0x01,0x00, diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index 3158803..99fd556 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -5,6 +5,9 @@ * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * + * (C) Copyright 2006 + * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com + * * See file CREDITS for list of people who contributed to this * project. * @@ -31,7 +34,6 @@ #include <pci.h> #include <sm501.h> - #ifdef CONFIG_VIDEO_SM501 #define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\ @@ -66,10 +68,12 @@ static const SMI_REGS init_regs_800x600 [] = {0x00040, SWAP32(0x00021807)}, {0x00044, SWAP32(0x221a0a01)}, {0x00054, SWAP32(0x00000000)}, + /* GPIO */ + {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ /* panel control regs... */ {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ + {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */ {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */ {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */ @@ -100,10 +104,12 @@ static const SMI_REGS init_regs_1024x768 [] = {0x00040, SWAP32(0x00021807)}, {0x00044, SWAP32(0x011a0a01)}, {0x00054, SWAP32(0x00000000)}, + /* GPIO */ + {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ /* panel control regs... */ {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ + {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */ {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */ {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */ @@ -144,10 +150,12 @@ static const SMI_REGS init_regs_800x600 [] = {0x00040, SWAP32(0x00021807)}, {0x00044, SWAP32(0x221a0a01)}, {0x00054, SWAP32(0x00000000)}, + /* GPIO */ + {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ /* panel control regs... */ {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ + {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */ {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */ {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */ @@ -178,10 +186,12 @@ static const SMI_REGS init_regs_1024x768 [] = {0x00040, SWAP32(0x00021807)}, {0x00044, SWAP32(0x011a0a01)}, {0x00054, SWAP32(0x00000000)}, + /* GPIO */ + {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */ /* panel control regs... */ {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ + {0x8000C, SWAP32(0x00010000)}, /* panel fb address */ {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */ {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */ {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */ @@ -272,6 +282,9 @@ au_image_t au_image[] = { int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); +/* + * Get version of HH405 board from GPIO's + */ int board_revision(void) { unsigned long osrh_reg; @@ -280,10 +293,6 @@ int board_revision(void) unsigned long value; /* - * Get version of HH405 board from GPIO's - */ - - /* * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO) */ osrh_reg = in32(GPIO0_OSRH); @@ -305,15 +314,13 @@ int board_revision(void) if (value & 0x80000000) { /* Revision 1.0 or 1.1 detected */ - return 0x0101; + return 1; } else { if (value & 0x00400000) { /* unused */ - return 0x0103; + return 3; } else { - /* Revision >= 2.0 detected */ - /* rev. 2.x uses four SM501 GPIOs for revision coding */ - return 0x0200; + return 2; } } } @@ -349,6 +356,38 @@ int board_early_init_f (void) return 0; } +int cf_enable(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int i; + + volatile unsigned short *fpga_ctrl = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + volatile unsigned short *fpga_status = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2); + + if (gd->board_type >= 2) { + if (*fpga_status & CFG_FPGA_STATUS_CF_DETECT) { + if (!(*fpga_ctrl & CFG_FPGA_CTRL_CF_BUS_EN)) { + *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_PWRN; + + for (i=0; i<300; i++) + udelay(1000); + + *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN; + + for (i=0; i<20; i++) + udelay(1000); + } + } else { + *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_BUS_EN; + *fpga_ctrl |= CFG_FPGA_CTRL_CF_PWRN; + } + } + + return 0; +} int misc_init_r (void) { @@ -433,9 +472,6 @@ int misc_init_r (void) * Write Board revision into FPGA */ *fpga_ctrl |= gd->board_type & 0x0003; - if (gd->board_type >= 0x0200) { - *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN; - } /* * Setup and enable EEPROM write protection @@ -471,7 +507,7 @@ int misc_init_r (void) contrast0 = simple_strtol(str, NULL, 16); if (contrast0 > 255) { printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0); - contrast0 = 0; + contrast0 = 0xffffffff; } } @@ -544,9 +580,9 @@ int misc_init_r (void) */ *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE; /* - * Set lcd clock (small epson) + * Set lcd clock (small epson), enable 1-wire interface */ - *fpga_ctrl |= LCD_CLK_08330; + *fpga_ctrl |= LCD_CLK_08330 | CFG_FPGA_CTRL_OW_ENABLE; lcd_setup(0, 1); lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, @@ -565,8 +601,10 @@ int misc_init_r (void) puts("VGA: SM501 with 8 MB "); if (strcmp(str, "ppc221") == 0) { printf("(800*600, %dbpp)\n", BPP); + *lcd_backlight = 0x002d; /* max. allowed brightness */ } else if (strcmp(str, "ppc231") == 0) { printf("(1024*768, %dbpp)\n", BPP); + *lcd_backlight = 0x0000; } else { printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); return 0; @@ -578,6 +616,8 @@ int misc_init_r (void) #endif /* CONFIG_VIDEO_SM501 */ } + cf_enable(); + return (0); } @@ -590,7 +630,7 @@ int checkboard (void) { DECLARE_GLOBAL_DATA_PTR; - unsigned char str[64]; + char str[64]; int i = getenv_r ("serial#", str, sizeof(str)); puts ("Board: "); @@ -608,14 +648,7 @@ int checkboard (void) } gd->board_type = board_revision(); - printf(", Rev %ld.%ld)\n", - (gd->board_type >> 8) & 0xff, - gd->board_type & 0xff); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); + printf(", Rev %ld.x)\n", gd->board_type); return 0; } @@ -637,35 +670,34 @@ long int initdram (int board_type) } -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - #ifdef CONFIG_IDE_RESET void ide_set_reset(int on) { + DECLARE_GLOBAL_DATA_PTR; + volatile unsigned short *fpga_mode = (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + volatile unsigned short *fpga_status = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2); - /* - * Assert or deassert CompactFlash Reset Pin - */ - if (on) { /* assert RESET */ - *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); - } else { /* release RESET */ - *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; + if (((gd->board_type >= 2) && (*fpga_status & CFG_FPGA_STATUS_CF_DETECT)) || + (gd->board_type < 2)) { + /* + * Assert or deassert CompactFlash Reset Pin + */ + if (on) { /* assert RESET */ + cf_enable(); + *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); + } else { /* release RESET */ + *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; + } } } #endif /* CONFIG_IDE_RESET */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) @@ -778,8 +810,7 @@ void video_get_info_str (int line_number, char *info) strcat(str, " (Missing bd_type!"); } - sprintf(str2, ", Rev %ld.%ld)", - (gd->board_type >> 8) & 0xff, gd->board_type & 0xff); + sprintf(str2, ", Rev %ld.x)", gd->board_type); strcat(str, str2); strcpy(info, str); } else { @@ -822,7 +853,11 @@ unsigned int board_video_get_fb (void) devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); if (devbusfn != -1) { pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr); - return (addr & 0xfffffffe); + addr &= 0xfffffffe; +#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET + addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET; +#endif + return addr; } return 0; @@ -875,3 +910,15 @@ int board_get_height (void) } #endif /* CONFIG_VIDEO_SM501 */ + + +void reset_phy(void) +{ +#ifdef CONFIG_LXT971_NO_SLEEP + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); +#endif +} diff --git a/board/esd/hub405/config.mk b/board/esd/hub405/config.mk index a6d31aa..4c60c35 100644 --- a/board/esd/hub405/config.mk +++ b/board/esd/hub405/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0xFFFC0000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c index e77dba8..0c6771f 100644 --- a/board/esd/hub405/hub405.c +++ b/board/esd/hub405/hub405.c @@ -265,7 +265,7 @@ int testdram (void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/plu405/config.mk b/board/esd/plu405/config.mk index 25b2105..916b285 100644 --- a/board/esd/plu405/config.mk +++ b/board/esd/plu405/config.mk @@ -27,3 +27,6 @@ TEXT_BASE = 0xFFFC0000 #TEXT_BASE = 0x00FC0000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index 5b9d063..37b92fb 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -269,7 +269,7 @@ void ide_set_reset(int on) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile index 1281be7..741e4aa 100644 --- a/board/esd/pmc405/Makefile +++ b/board/esd/pmc405/Makefile @@ -30,7 +30,7 @@ CPLD = ../common/xilinx_jtag/lenval.o \ ../common/xilinx_jtag/micro.o \ ../common/xilinx_jtag/ports.o -OBJS = $(BOARD).o ../common/misc.o $(CPLD) +OBJS = $(BOARD).o ../common/misc.o ../common/cmd_loadpci.o $(CPLD) $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c index 33b5f77..f9e4d43 100644 --- a/board/esd/pmc405/pmc405.c +++ b/board/esd/pmc405/pmc405.c @@ -1,6 +1,9 @@ /* * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2005 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this * project. @@ -66,16 +69,27 @@ int board_early_init_f (void) mtebc (epcr, 0xa8400000); /* - * Setup GPIO pins (CS6+CS7 as GPIO) + * Setup GPIO pins */ - mtdcr(cntrl0, mfdcr(cntrl0) | 0x00300000); - /* - * Configure GPIO pins + mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_FPGA_INIT | \ + CFG_FPGA_DONE | \ + CFG_XEREADY | \ + CFG_NONMONARCH | \ + CFG_REV1_2) << 5)); + + if (!(in32(GPIO0_IR) & CFG_REV1_2)) { + /* rev 1.2 boards */ + mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_INTA_FAKE | \ + CFG_SELF_RST) << 5)); + } + + out32(GPIO0_OR, 0); + out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA | CFG_XEREADY); /* setup for output */ + + /* - check if rev1_2 is low, then: + * - set/reset CFG_INTA_FAKE/CFG_SELF_RST in TCR to assert INTA# or SELFRST# */ - out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA); /* setup for output */ - out32(GPIO0_OR, 0); /* outputs -> low */ return 0; } @@ -83,11 +97,6 @@ int board_early_init_f (void) /* ------------------------------------------------------------------------- */ -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - int misc_init_r (void) { @@ -97,16 +106,30 @@ int misc_init_r (void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_XEREADY); /* deassert EREADY# */ return (0); } +ushort pmc405_pci_subsys_deviceid(void) +{ + ulong val; + val = in32(GPIO0_IR); + if (!(val & CFG_REV1_2)) { /* low=rev1.2 */ + if (val & CFG_NONMONARCH) { /* monarch# signal */ + return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH; + } + return CFG_PCI_SUBSYS_DEVICEID_MONARCH; + } + return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH; +} /* * Check Board Identity: */ - int checkboard (void) { + ulong val; + char str[64]; int i = getenv_r ("serial#", str, sizeof(str)); @@ -118,12 +141,18 @@ int checkboard (void) puts(str); } - putc ('\n'); + val = in32(GPIO0_IR); + if (!(val & CFG_REV1_2)) { /* low=rev1.2 */ + puts(" rev1.2 ("); + if (val & CFG_NONMONARCH) { /* monarch# signal */ + puts("non-"); + } + puts("monarch)"); + } else { + puts(" <=rev1.1"); + } - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); + putc ('\n'); return 0; } @@ -145,17 +174,19 @@ long int initdram (int board_type) return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } -/* ------------------------------------------------------------------------- */ -int testdram (void) +/* ------------------------------------------------------------------------- */ +void reset_phy(void) { - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); +#ifdef CONFIG_LXT971_NO_SLEEP - return (0); + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); +#endif } -/* ------------------------------------------------------------------------- */ int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { diff --git a/board/esd/voh405/config.mk b/board/esd/voh405/config.mk index 219a4eb..72e8103 100644 --- a/board/esd/voh405/config.mk +++ b/board/esd/voh405/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0xFFF80000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index eda3fd9..22995b5 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -343,7 +343,7 @@ void ide_set_reset(int on) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c index 445b8fc..bc5fa7c 100644 --- a/board/esd/vom405/vom405.c +++ b/board/esd/vom405/vom405.c @@ -97,7 +97,7 @@ int misc_init_r (void) int checkboard (void) { - unsigned char str[64]; + char str[64]; int i = getenv_r ("serial#", str, sizeof(str)); int flashcnt; int delay; diff --git a/board/esd/wuh405/config.mk b/board/esd/wuh405/config.mk index 1d743a9..3cf5dd8 100644 --- a/board/esd/wuh405/config.mk +++ b/board/esd/wuh405/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0xFFFC0000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index db24122..5a1a3f3 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -239,7 +239,7 @@ int testdram (void) /* ------------------------------------------------------------------------- */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/ezkit533/Makefile b/board/ezkit533/Makefile new file mode 100644 index 0000000..c9b3c92 --- /dev/null +++ b/board/ezkit533/Makefile @@ -0,0 +1,44 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005 blackfin.uclinux.org +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ezkit533.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/ezkit533/config.mk b/board/ezkit533/config.mk new file mode 100644 index 0000000..36c9f99 --- /dev/null +++ b/board/ezkit533/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x01FC0000 +PLATFORM_CPPFLAGS += -I$(TOPDIR) diff --git a/board/ezkit533/ezkit533.c b/board/ezkit533/ezkit533.c new file mode 100644 index 0000000..f8ee900 --- /dev/null +++ b/board/ezkit533/ezkit533.c @@ -0,0 +1,71 @@ +/* + * U-boot - ezkit533.c + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#if defined(CONFIG_MISC_INIT_R) +#include "psd4256.h" +#endif + +int checkboard(void) +{ + printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28); + printf("Board: ADI BF533 EZ-Kit Lite board\n"); + printf(" Support: http://blackfin.uclinux.org/\n"); + printf(" Richard Klingler <richard@uclinux.net>\n"); + return 0; +} + +long int initdram(int board_type) +{ + DECLARE_GLOBAL_DATA_PTR; +#ifdef DEBUG + int brate; + char *tmp = getenv("baudrate"); + brate = simple_strtoul(tmp, NULL, 16); + printf("Serial Port initialized with Baud rate = %x\n",brate); + printf("SDRAM attributes:\n"); + printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles" + "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n", + 3, 3, 6, 2, 3); + printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE); + printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20); +#endif + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_MAX_RAM_SIZE; + return CFG_MAX_RAM_SIZE; +} + +#if defined(CONFIG_MISC_INIT_R) +/* miscellaneous platform dependent initialisations */ +int misc_init_r(void) +{ + /* Set direction bits for Video en/decoder reset as output */ + *(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) = PSDA_VDEC_RST | PSDA_VENC_RST; + /* Deactivate Video en/decoder reset lines */ + *(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) = PSDA_VDEC_RST | PSDA_VENC_RST; +} +#endif diff --git a/board/ezkit533/flash-defines.h b/board/ezkit533/flash-defines.h new file mode 100644 index 0000000..8f9dff5 --- /dev/null +++ b/board/ezkit533/flash-defines.h @@ -0,0 +1,130 @@ +/* + * U-boot - flash-defines.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FLASHDEFINES_H__ +#define __FLASHDEFINES_H__ + +#include <common.h> + +#define V_ULONG(a) (*(volatile unsigned long *)( a )) +#define V_BYTE(a) (*(volatile unsigned char *)( a )) +#define TRUE 0x1 +#define FALSE 0x0 +#define BUFFER_SIZE 0x80000 +#define NO_COMMAND 0 +#define GET_CODES 1 +#define RESET 2 +#define WRITE 3 +#define FILL 4 +#define ERASE_ALL 5 +#define ERASE_SECT 6 +#define READ 7 +#define GET_SECTNUM 8 +#define FLASH_START_L 0x0000 +#define FLASH_START_H 0x2000 +#define FLASH_TOT_SECT 40 +#define FLASH_SIZE 0x220000 +#define FLASH_MAN_ST 2 +#define CFG_FLASH0_BASE 0x20000000 +#define RESET_VAL 0xF0 + + +asm("#define FLASH_START_L 0x0000"); +asm("#define FLASH_START_H 0x2000"); + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +int get_codes(void); +int poll_toggle_bit(long lOffset); +void reset_flash(void); +int erase_flash(void); +int erase_block_flash(int,unsigned long); +void unlock_flash(long lOffset); +int write_data(long lStart, long lCount, long lStride, int *pnData); +int FillData(long lStart, long lCount, long lStride, int *pnData); +int read_data(long lStart, long lCount, long lStride, int *pnData); +int read_flash(long nOffset, int *pnValue); +int write_flash(long nOffset, int nValue); +void get_sector_number(long lOffset, int *pnSector); +int GetSectorProtectionStatus(flash_info_t * info, int nSector); +int GetOffset(int nBlock); +int AFP_NumSectors = 40; +long AFP_SectorSize1 = 0x10000; +int AFP_SectorSize2 = 0x4000; + +#define WRITESEQ1 0x0AAA +#define WRITESEQ2 0x0554 +#define WRITESEQ3 0x0AAA +#define WRITESEQ4 0x0AAA +#define WRITESEQ5 0x0554 +#define WRITESEQ6 0x0AAA +#define WRITEDATA1 0xaa +#define WRITEDATA2 0x55 +#define WRITEDATA3 0x80 +#define WRITEDATA4 0xaa +#define WRITEDATA5 0x55 +#define WRITEDATA6 0x10 +#define PriFlashABegin 0 +#define SecFlashABegin 32 +#define SecFlashBBegin 36 +#define PriFlashAOff 0x0 +#define PriFlashBOff 0x100000 +#define SecFlashAOff 0x200000 +#define SecFlashBOff 0x280000 +#define INVALIDLOCNSTART 0x20270000 +#define INVALIDLOCNEND 0x20280000 +#define BlockEraseVal 0x30 +#define UNLOCKDATA1 0xaa +#define UNLOCKDATA2 0x55 +#define UNLOCKDATA3 0xa0 +#define GETCODEDATA1 0xaa +#define GETCODEDATA2 0x55 +#define GETCODEDATA3 0x90 +#define SecFlashASec1Off 0x200000 +#define SecFlashASec2Off 0x204000 +#define SecFlashASec3Off 0x206000 +#define SecFlashASec4Off 0x208000 +#define SecFlashAEndOff 0x210000 +#define SecFlashBSec1Off 0x280000 +#define SecFlashBSec2Off 0x284000 +#define SecFlashBSec3Off 0x286000 +#define SecFlashBSec4Off 0x288000 +#define SecFlashBEndOff 0x290000 + +#define SECT32 32 +#define SECT33 33 +#define SECT34 34 +#define SECT35 35 +#define SECT36 36 +#define SECT37 37 +#define SECT38 38 +#define SECT39 39 + +#define FLASH_SUCCESS 0 +#define FLASH_FAIL -1 + +#endif diff --git a/board/ezkit533/flash.c b/board/ezkit533/flash.c new file mode 100644 index 0000000..b0a0796 --- /dev/null +++ b/board/ezkit533/flash.c @@ -0,0 +1,476 @@ +/* + * U-boot - flash.c Flash driver for PSD4256GV + * + * Copyright (c) 2005 blackfin.uclinux.org + * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "flash-defines.h" + +void flash_reset(void) +{ + reset_flash(); +} + +unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, + int bank_flag) +{ + int id = 0, i = 0; + static int FlagDev = 1; + + id = get_codes(); + if(FlagDev) { +#ifdef DEBUG + printf("Device ID of the Flash is %x\n", id); +#endif + FlagDev = 0; + } + info->flash_id = id; + + switch (bank_flag) { + case 0: + for (i = PriFlashABegin; i < SecFlashABegin; i++) + info->start[i] = (baseaddr + (i * AFP_SectorSize1)); + info->size = 0x200000; + info->sector_count = 32; + break; + case 1: + info->start[0] = baseaddr + SecFlashASec1Off; + info->start[1] = baseaddr + SecFlashASec2Off; + info->start[2] = baseaddr + SecFlashASec3Off; + info->start[3] = baseaddr + SecFlashASec4Off; + info->size = 0x10000; + info->sector_count = 4; + break; + case 2: + info->start[0] = baseaddr + SecFlashBSec1Off; + info->start[1] = baseaddr + SecFlashBSec2Off; + info->start[2] = baseaddr + SecFlashBSec3Off; + info->start[3] = baseaddr + SecFlashBSec4Off; + info->size = 0x10000; + info->sector_count = 4; + break; + } + return (info->size); +} + +unsigned long flash_init(void) +{ + unsigned long size_b0, size_b1, size_b2; + int i; + + size_b0 = size_b1 = size_b2 = 0; +#ifdef DEBUG + printf("Flash Memory Start 0x%x\n", CFG_FLASH_BASE); + printf("Memory Map for the Flash\n"); + printf("0x20000000 - 0x200FFFFF Flash A Primary (1MB)\n"); + printf("0x20100000 - 0x201FFFFF Flash B Primary (1MB)\n"); + printf("0x20200000 - 0x2020FFFF Flash A Secondary (64KB)\n"); + printf("0x20280000 - 0x2028FFFF Flash B Secondary (64KB)\n"); + printf("Please type command flinfo for information on Sectors \n"); +#endif + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + size_b0 = flash_get_size(CFG_FLASH0_BASE, &flash_info[0], 0); + size_b1 = flash_get_size(CFG_FLASH0_BASE, &flash_info[1], 1); + size_b2 = flash_get_size(CFG_FLASH0_BASE, &flash_info[2], 2); + + if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { + printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 >> 20); + } + + (void)flash_protect(FLAG_PROTECT_SET,CFG_FLASH0_BASE,(flash_info[0].start[2] - 1),&flash_info[0]); + + return (size_b0 + size_b1 + size_b2); +} + +void flash_print_info(flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id) { + case FLASH_PSD4256GV: + printf("ST Microelectronics "); + break; + default: + printf("Unknown Vendor "); + break; + } + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf("\n"); + return; +} + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + int cnt = 0,i; + int prot,sect; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + + if (prot) + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + else + printf ("\n"); + + cnt = s_last - s_first + 1; + + if (cnt == FLASH_TOT_SECT) { + printf("Erasing flash, Please Wait \n"); + if(erase_flash() < 0) { + printf("Erasing flash failed \n"); + return FLASH_FAIL; + } + } else { + printf("Erasing Flash locations, Please Wait\n"); + for (i = s_first; i <= s_last; i++) { + if (info->protect[i] == 0) { /* not protected */ + if(erase_block_flash(i, info->start[i]) < 0) { + printf("Error Sector erasing \n"); + return FLASH_FAIL; + } + } + } + } + return FLASH_SUCCESS; +} + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int ret; + + ret = write_data(addr, cnt, 1, (int *) src); + if(ret == FLASH_FAIL) + return ERR_NOT_ERASED; + return FLASH_SUCCESS; +} + + +int write_data(long lStart, long lCount, long lStride, int *pnData) +{ + long i = 0; + int j = 0; + unsigned long ulOffset = lStart - CFG_FLASH_BASE; + int d; + int iShift = 0; + int iNumWords = 2; + int nLeftover = lCount % 4; + int nSector = 0; + + for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) { + for (iShift = 0, j = 0; (j < iNumWords); + j++, ulOffset += (lStride * 2)) { + if ((ulOffset >= INVALIDLOCNSTART) + && (ulOffset < INVALIDLOCNEND)) { + printf("Invalid locations, Try writing to another location \n"); + return FLASH_FAIL; + } + get_sector_number(ulOffset, &nSector); + read_flash(ulOffset,&d); + if(d != 0xffff) { + printf("Flash not erased at offset 0x%x Please erase to reprogram \n",ulOffset); + return FLASH_FAIL; + } + unlock_flash(ulOffset); + if(write_flash(ulOffset, (pnData[i] >> iShift)) < 0) { + printf("Error programming the flash \n"); + return FLASH_FAIL; + } + iShift += 16; + } + } + if (nLeftover > 0) { + if ((ulOffset >= INVALIDLOCNSTART) + && (ulOffset < INVALIDLOCNEND)) + return FLASH_FAIL; + get_sector_number(ulOffset, &nSector); + read_flash(ulOffset,&d); + if(d != 0xffff) { + printf("Flash already programmed. Please erase to reprogram \n"); + printf("uloffset = 0x%x \t d = 0x%x\n",ulOffset,d); + return FLASH_FAIL; + } + unlock_flash(ulOffset); + if(write_flash(ulOffset, pnData[i]) < 0) { + printf("Error programming the flash \n"); + return FLASH_FAIL; + } + } + return FLASH_SUCCESS; +} + +int read_data(long ulStart, long lCount, long lStride, int *pnData) +{ + long i = 0; + int j = 0; + long ulOffset = ulStart; + int iShift = 0; + int iNumWords = 2; + int nLeftover = lCount % 4; + int nHi, nLow; + int nSector = 0; + + for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) { + for (iShift = 0, j = 0; j < iNumWords; j += 2) { + if ((ulOffset >= INVALIDLOCNSTART) + && (ulOffset < INVALIDLOCNEND)) + return FLASH_FAIL; + + get_sector_number(ulOffset, &nSector); + read_flash(ulOffset, &nLow); + ulOffset += (lStride * 2); + read_flash(ulOffset, &nHi); + ulOffset += (lStride * 2); + pnData[i] = (nHi << 16) | nLow; + } + } + if (nLeftover > 0) { + if ((ulOffset >= INVALIDLOCNSTART) + && (ulOffset < INVALIDLOCNEND)) + return FLASH_FAIL; + + get_sector_number(ulOffset, &nSector); + read_flash(ulOffset, &pnData[i]); + } + return FLASH_SUCCESS; +} + +int write_flash(long nOffset, int nValue) +{ + long addr; + + addr = (CFG_FLASH_BASE + nOffset); + asm("ssync;"); + *(unsigned volatile short *) addr = nValue; + asm("ssync;"); + if(poll_toggle_bit(nOffset) < 0) + return FLASH_FAIL; + return FLASH_SUCCESS; +} + +int read_flash(long nOffset, int *pnValue) +{ + int nValue = 0x0; + long addr = (CFG_FLASH_BASE + nOffset); + + if (nOffset != 0x2) + reset_flash(); + asm("ssync;"); + nValue = *(volatile unsigned short *) addr; + asm("ssync;"); + *pnValue = nValue; + return TRUE; +} + +int poll_toggle_bit(long lOffset) +{ + unsigned int u1,u2; + unsigned long timeout = 0xFFFFFFFF; + volatile unsigned long *FB = (volatile unsigned long *)(0x20000000 + lOffset); + while(1) { + if(timeout < 0) + break; + u1 = *(volatile unsigned short *)FB; + u2 = *(volatile unsigned short *)FB; + if((u1 & 0x0040) == (u2 & 0x0040)) + return FLASH_SUCCESS; + if((u2 & 0x0020) == 0x0000) + continue; + u1 = *(volatile unsigned short *)FB; + if((u2 & 0x0040) == (u1 & 0x0040)) + return FLASH_SUCCESS; + else { + reset_flash(); + return FLASH_FAIL; + } + timeout--; + } + printf("Time out occured \n"); + if(timeout <0) return FLASH_FAIL; +} + +void reset_flash(void) +{ + write_flash(WRITESEQ1, RESET_VAL); + /* Wait for 10 micro seconds */ + udelay(10); +} + +int erase_flash(void) +{ + write_flash(WRITESEQ1, WRITEDATA1); + write_flash(WRITESEQ2, WRITEDATA2); + write_flash(WRITESEQ3, WRITEDATA3); + write_flash(WRITESEQ4, WRITEDATA4); + write_flash(WRITESEQ5, WRITEDATA5); + write_flash(WRITESEQ6, WRITEDATA6); + + if(poll_toggle_bit(0x0000) < 0) + return FLASH_FAIL; + + write_flash(SecFlashAOff + WRITESEQ1, WRITEDATA1); + write_flash(SecFlashAOff + WRITESEQ2, WRITEDATA2); + write_flash(SecFlashAOff + WRITESEQ3, WRITEDATA3); + write_flash(SecFlashAOff + WRITESEQ4, WRITEDATA4); + write_flash(SecFlashAOff + WRITESEQ5, WRITEDATA5); + write_flash(SecFlashAOff + WRITESEQ6, WRITEDATA6); + + if(poll_toggle_bit(SecFlashASec1Off) < 0) + return FLASH_FAIL; + + write_flash(PriFlashBOff + WRITESEQ1, WRITEDATA1); + write_flash(PriFlashBOff + WRITESEQ2, WRITEDATA2); + write_flash(PriFlashBOff + WRITESEQ3, WRITEDATA3); + write_flash(PriFlashBOff + WRITESEQ4, WRITEDATA4); + write_flash(PriFlashBOff + WRITESEQ5, WRITEDATA5); + write_flash(PriFlashBOff + WRITESEQ6, WRITEDATA6); + + if(poll_toggle_bit(PriFlashBOff) <0) + return FLASH_FAIL; + + write_flash(SecFlashBOff + WRITESEQ1, WRITEDATA1); + write_flash(SecFlashBOff + WRITESEQ2, WRITEDATA2); + write_flash(SecFlashBOff + WRITESEQ3, WRITEDATA3); + write_flash(SecFlashBOff + WRITESEQ4, WRITEDATA4); + write_flash(SecFlashBOff + WRITESEQ5, WRITEDATA5); + write_flash(SecFlashBOff + WRITESEQ6, WRITEDATA6); + + if(poll_toggle_bit(SecFlashBOff) < 0) + return FLASH_FAIL; + + return FLASH_SUCCESS; +} + +int erase_block_flash(int nBlock, unsigned long address) +{ + long ulSectorOff = 0x0; + + if ((nBlock < 0) || (nBlock > AFP_NumSectors)) + return FALSE; + + ulSectorOff = (address - CFG_FLASH_BASE); + + write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1); + write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2); + write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3); + write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4); + write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5); + + write_flash(ulSectorOff, BlockEraseVal); + + if(poll_toggle_bit(ulSectorOff) < 0) + return FLASH_FAIL; + + return FLASH_SUCCESS; +} + +void unlock_flash(long ulOffset) +{ + unsigned long ulOffsetAddr = ulOffset; + ulOffsetAddr &= 0xFFFF0000; + + write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1); + write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2); + write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3); +} + +int get_codes() +{ + int dev_id = 0; + + write_flash(WRITESEQ1, GETCODEDATA1); + write_flash(WRITESEQ2, GETCODEDATA2); + write_flash(WRITESEQ3, GETCODEDATA3); + + read_flash(0x0002, &dev_id); + dev_id &= 0x00FF; + + reset_flash(); + + return dev_id; +} + +void get_sector_number(long ulOffset, int *pnSector) +{ + int nSector = 0; + + if (ulOffset >= SecFlashAOff) { + if ((ulOffset < SecFlashASec1Off) + && (ulOffset < SecFlashASec2Off)) { + nSector = SECT32; + } else if ((ulOffset >= SecFlashASec2Off) + && (ulOffset < SecFlashASec3Off)) { + nSector = SECT33; + } else if ((ulOffset >= SecFlashASec3Off) + && (ulOffset < SecFlashASec4Off)) { + nSector = SECT34; + } else if ((ulOffset >= SecFlashASec4Off) + && (ulOffset < SecFlashAEndOff)) { + nSector = SECT35; + } + } else if (ulOffset >= SecFlashBOff) { + if ((ulOffset < SecFlashBSec1Off) + && (ulOffset < SecFlashBSec2Off)) { + nSector = SECT36; + } + if ((ulOffset < SecFlashBSec2Off) + && (ulOffset < SecFlashBSec3Off)) { + nSector = SECT37; + } + if ((ulOffset < SecFlashBSec3Off) + && (ulOffset < SecFlashBSec4Off)) { + nSector = SECT38; + } + if ((ulOffset < SecFlashBSec4Off) + && (ulOffset < SecFlashBEndOff)) { + nSector = SECT39; + } + } else if ((ulOffset >= PriFlashAOff) && (ulOffset < SecFlashAOff)) { + nSector = ulOffset & 0xffff0000; + nSector = ulOffset >> 16; + nSector = nSector & 0x000ff; + } + + if ((nSector >= 0) && (nSector < AFP_NumSectors)) { + *pnSector = nSector; + } +} diff --git a/board/ezkit533/psd4256.h b/board/ezkit533/psd4256.h new file mode 100644 index 0000000..01f6566 --- /dev/null +++ b/board/ezkit533/psd4256.h @@ -0,0 +1,67 @@ +/* + * U-boot - psd4256.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Flash A/B Port A configuration registers. + * Addresses are offset values to CFG_FLASH1_BASE + * for Flash A and CFG_FLASH2_BASE for Flash B. + */ + +#define PSD_PORTA_DIN 0x070000 +#define PSD_PORTA_DOUT 0x070004 +#define PSD_PORTA_DIR 0x070006 + +/* + * Flash A/B Port B configuration registers + * Addresses are offset values to CFG_FLASH1_BASE + * for Flash A and CFG_FLASH2_BASE for Flash B. + */ + +#define PSD_PORTB_DIN 0x070001 +#define PSD_PORTB_DOUT 0x070005 +#define PSD_PORTB_DIR 0x070007 + +/* + * Flash A Port A Bit definitions + */ + +#define PSDA_PPICLK1 0x20 /* PPI Clock select bit 1 */ +#define PSDA_PPICLK0 0x10 /* PPI Clock select bit 0 */ +#define PSDA_VDEC_RST 0x08 /* Video decoder reset, 0 = RESET */ +#define PSDA_VENC_RST 0x04 /* Video encoder reset, 0 = RESET */ +#define PSDA_CODEC_RST 0x01 /* Codec reset, 0 = RESET */ + +/* + * Flash A Port B Bit definitions + */ + +#define PSDA_LED9 0x20 /* LED 9, 1 = LED ON */ +#define PSDA_LED8 0x10 /* LED 8, 1 = LED ON */ +#define PSDA_LED7 0x08 /* LED 7, 1 = LED ON */ +#define PSDA_LED6 0x04 /* LED 6, 1 = LED ON */ +#define PSDA_LED5 0x02 /* LED 5, 1 = LED ON */ +#define PSDA_LED4 0x01 /* LED 4, 1 = LED ON */ diff --git a/board/ezkit533/u-boot.lds b/board/ezkit533/u-boot.lds new file mode 100644 index 0000000..10203ff --- /dev/null +++ b/board/ezkit533/u-boot.lds @@ -0,0 +1,148 @@ +/* + * U-boot - u-boot.lds + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(bfin) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector before the environment sector. If it throws */ + /* an error during compilation remove an object here to get */ + /* it linked after the configuration sector. */ + + cpu/bf533/start.o (.text) + cpu/bf533/start1.o (.text) + cpu/bf533/traps.o (.text) + cpu/bf533/interrupt.o (.text) + cpu/bf533/serial.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + board/ezkit533/ezkit533.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/fads/fads.c b/board/fads/fads.c index 013b3cb..7b04af5 100644 --- a/board/fads/fads.c +++ b/board/fads/fads.c @@ -726,24 +726,23 @@ static void checkdboard(void) int checkboard (void) { - /* get revision from BCSR 3 */ +#if defined(CONFIG_MPC86xADS) + puts ("Board: MPC86xADS\n"); +#elif defined(CONFIG_MPC885ADS) + puts ("Board: MPC885ADS\n"); +#else /* Only old ADS/FADS have got revision ID in BCSR3 */ uint r = (((*((uint *) BCSR3) >> 23) & 1) << 3) | (((*((uint *) BCSR3) >> 19) & 1) << 2) | (((*((uint *) BCSR3) >> 16) & 3)); puts ("Board: "); - -#if defined(CONFIG_MPC86xADS) - puts ("MPC86xADS"); -#elif defined(CONFIG_MPC885ADS) - puts ("MPC885ADS"); - r = 0; /* I've got NR (No Revision) board */ -#elif defined(CONFIG_FADS) +#if defined(CONFIG_FADS) puts ("FADS"); checkdboard (); #else puts ("ADS"); #endif + puts (" rev "); switch (r) { @@ -758,13 +757,9 @@ int checkboard (void) puts ("A - warning, read errata \n"); break; case 0x03: - puts ("B \n"); + puts ("B\n"); break; -#elif defined(CONFIG_MPC885ADS) - case 0x00: - puts ("NR\n"); - break; -#else /* FADS and newer */ +#else /* FADS */ case 0x00: puts ("ENG\n"); break; @@ -776,6 +771,7 @@ int checkboard (void) printf ("unknown (0x%x)\n", r); return -1; } +#endif /* CONFIG_MPC86xADS */ return 0; } @@ -848,7 +844,7 @@ int pcmcia_init(void) switch ((pcmp->pcmc_pipr >> 14) & 3) #endif { - case 0x00 : + case 0x03 : printf("5V"); v = 5; break; @@ -860,7 +856,7 @@ int pcmcia_init(void) v = 5; #endif break; - case 0x03 : + case 0x00 : printf("5V, 3V and x.xV"); #ifdef CONFIG_FADS v = 3; /* User lower voltage if supported! */ diff --git a/board/fads/fads.h b/board/fads/fads.h index 1127c7f..e981be0 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -55,18 +55,26 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_NFSBOOTCOMMAND \ "dhcp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ "bootm" +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ + "bootm fe080000" + +#undef CONFIG_BOOTARGS + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_BZIP2 /* include support for bzip2 compressed images */ /* - * New MPC86xADS and Duet provide two Ethernet connectivity options: + * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options: * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have * got FEC so FEC is the default. @@ -89,7 +97,9 @@ #ifndef CONFIG_COMMANDS #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ | CFG_CMD_DHCP \ + | CFG_CMD_ECHO \ | CFG_CMD_IMMAP \ | CFG_CMD_JFFS2 \ | CFG_CMD_MII \ @@ -104,16 +114,18 @@ /* * Miscellaneous configurable options */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=>" /* Monitor Command Prompt */ +#define CFG_PROMPT "=>" /* Monitor Command Prompt */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_LONGHELP /* #undef to save memory */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x00100000 @@ -126,6 +138,7 @@ * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. */ + /*----------------------------------------------------------------------- * Internal Memory Mapped Register */ @@ -148,6 +161,14 @@ #define CFG_SDRAM_BASE 0x00000000 #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */ #define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ +/* + * 2048 SDRAM rows + * 1000 factor s -> ms + * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + */ +#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64)) #elif defined(CONFIG_FADS) /* Old/new FADS */ #define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */ #else /* Old ADS */ @@ -223,9 +244,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif /*----------------------------------------------------------------------- * I2C configuration @@ -277,31 +296,21 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) +#define CFG_SCCR SCCR_TBS /*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 14-22 + * DER - Debug Enable Register *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control - */ -#ifndef CFG_PLPRCR -#define CFG_PLPRCR PLPRCR_TEXPS -#endif - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * + * Set to zero to prevent the processor from entering debug mode */ #define CFG_DER 0 -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ +/* Because of the way the 860 starts up and assigns CS0 the entire + * address space, we have to set the memory controller differently. + * Normally, you write the option register first, and then enable the + * chip select by writing the base register. For CS0, you must write + * the base register first, followed by the option register. + */ /* * Init Memory Controller: @@ -335,9 +344,6 @@ /* values according to the manual */ -#define PCMCIA_MEM_ADDR ((uint)0xFF020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - #define BCSR0 ((uint) (BCSR_ADDR + 0x00)) #define BCSR1 ((uint) (BCSR_ADDR + 0x04)) #define BCSR2 ((uint) (BCSR_ADDR + 0x08)) @@ -396,59 +402,28 @@ #define BCSR4_TFPLDL ((uint)0x40000000) #define BCSR4_TPSQEL ((uint)0x20000000) #define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#define BCSR4_FETH_EN ((uint)0x08000000) -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#define BCSR4_FETHFDE ((uint)0x02000000) -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#define BCSR4_FETHRST ((uint)0x00200000) - -#ifdef CONFIG_MPC823 +#if defined(CONFIG_MPC823) #define BCSR4_USB_EN ((uint)0x08000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860SAR -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860SAR */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETH_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 #define BCSR4_USB_SPEED ((uint)0x04000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 #define BCSR4_VCCO ((uint)0x02000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHFDE ((uint)0x02000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 #define BCSR4_VIDEO_ON ((uint)0x00800000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 #define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 #define BCSR4_VIDEO_RST ((uint)0x00200000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHRST ((uint)0x00200000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 #define BCSR4_MODEM_EN ((uint)0x00100000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 #define BCSR4_DATA_VOICE ((uint)0x00080000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC850 +#elif defined(CONFIG_MPC850) #define BCSR4_DATA_VOICE ((uint)0x00080000) -#endif /* CONFIG_MPC850 */ +#elif defined(CONFIG_MPC860SAR) +#define BCSR4_UTOPIA_EN ((uint)0x08000000) +#else /* MPC860T and other chips with FEC */ +#define BCSR4_FETH_EN ((uint)0x08000000) +#define BCSR4_FETHCFG0 ((uint)0x04000000) +#define BCSR4_FETHFDE ((uint)0x02000000) +#define BCSR4_FETHCFG1 ((uint)0x00400000) +#define BCSR4_FETHRST ((uint)0x00200000) +#endif -/* BSCR5 exists on MPC86xADS and Duet ADS only */ +/* BSCR5 exists on MPC86xADS and MPC885ADS only */ #define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000) @@ -511,4 +486,4 @@ #define CFG_ATA_ALT_OFFSET 0x0000 #define CONFIG_DISK_SPINUP_TIME 1000000 -#undef CONFIG_DISK_SPINUP_TIME /* usin´ Compact Flash */ +/* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */ diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index 3f78753..39b5c70 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -185,7 +185,7 @@ int testdram (void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/lart/flash.c b/board/lart/flash.c index 5232ed2..28c4531 100644 --- a/board/lart/flash.c +++ b/board/lart/flash.c @@ -348,7 +348,7 @@ outahere: * Copy memory to flash */ -volatile static int write_word (flash_info_t *info, ulong dest, ulong data) +static int write_word (flash_info_t *info, ulong dest, ulong data) { vu_long *addr = (vu_long *)dest; ulong result; diff --git a/board/lpd7a40x/flash.c b/board/lpd7a40x/flash.c index 2dfe376..d18720e 100644 --- a/board/lpd7a40x/flash.c +++ b/board/lpd7a40x/flash.c @@ -351,8 +351,7 @@ outahere: * Copy memory to flash */ -volatile static int write_word (flash_info_t * info, ulong dest, - ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { vu_long *addr = (vu_long *) dest; ulong result; diff --git a/board/m5272c3/flash.c b/board/m5272c3/flash.c index fb91843..f156342 100644 --- a/board/m5272c3/flash.c +++ b/board/m5272c3/flash.c @@ -256,8 +256,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) return rc; } - -volatile static int write_word (flash_info_t * info, ulong dest, ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { volatile u16 *addr = (volatile u16 *) dest; ulong result; diff --git a/board/m5282evb/flash.c b/board/m5282evb/flash.c index ff70783..95f35ad 100644 --- a/board/m5282evb/flash.c +++ b/board/m5282evb/flash.c @@ -256,8 +256,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) return rc; } - -volatile static int write_word (flash_info_t * info, ulong dest, ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { volatile u16 *addr = (volatile u16 *) dest; ulong result; diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile new file mode 100644 index 0000000..7fdc088 --- /dev/null +++ b/board/mcc200/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mcc200/config.mk b/board/mcc200/config.mk new file mode 100644 index 0000000..fa55673 --- /dev/null +++ b/board/mcc200/config.mk @@ -0,0 +1,43 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MCC200 board: +# +# Valid values for TEXT_BASE are: +# +# 0xFFF00000 boot high (standard configuration) +# 0xFE000000 boot low +# 0x00100000 boot from RAM (for testing only) +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Standard: boot high +TEXT_BASE = 0xFFF00000 +## For testing: boot from RAM +# TEXT_BASE = 0x00100000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c new file mode 100644 index 0000000..d1c99fd --- /dev/null +++ b/board/mcc200/mcc200.c @@ -0,0 +1,276 @@ +/* + * (C) Copyright 2003-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc5xxx.h> +#include <pci.h> + +#include "mt48lc8m32b2-6-7.h" + +extern flash_info_t flash_info[]; /* FLASH chips info */ + +ulong flash_get_size (ulong base, int banknum); + +#ifndef CFG_RAMBOOT +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +long int initdram (int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ + + /* find RAM size using SDRAM CS1 only */ + if (!dramsize) + sdram_start(0); + test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + if (!dramsize) { + sdram_start(1); + test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + } + if (test1 > test2) { + sdram_start(0); + dramsize2 = test1; + } else { + dramsize2 = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) { + dramsize2 = 0; + } + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + } else { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + } + +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } + +#endif /* CFG_RAMBOOT */ + + return dramsize + dramsize2; +} + +int checkboard (void) +{ + puts ("Board: MCC200\n"); + return 0; +} + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* + * Adjust flash start and offset to detected values + */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* + * Check if boot FLASH isn't max size + */ + if (gd->bd->bi_flashsize < (0 - CFG_FLASH_BASE)) { + /* adjust mapping */ + *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = + START_REG(gd->bd->bi_flashstart); + *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = + STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize); + + /* + * Re-check to get correct base address + */ + flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); + + /* + * Re-do flash protection upon new addresses + */ + flash_protect (FLAG_PROTECT_CLEAR, + gd->bd->bi_flashstart, 0xffffffff, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Redundant environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + } + + return (0); +} + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +void init_ide_reset (void) +{ + debug ("init_ide_reset\n"); + +} + +void ide_set_reset (int idereset) +{ + debug ("ide_reset(%d)\n", idereset); + +} +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) +extern void doc_probe (ulong physadr); +void doc_init (void) +{ + doc_probe (CFG_DOC_BASE); +} +#endif diff --git a/board/mcc200/mt46v16m16-75.h b/board/mcc200/mt46v16m16-75.h new file mode 100644 index 0000000..f650faa --- /dev/null +++ b/board/mcc200/mt46v16m16-75.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +#else +#error CONFIG_MPC5200 not defined +#endif diff --git a/board/mcc200/mt48lc16m16a2-75.h b/board/mcc200/mt48lc16m16a2-75.h new file mode 100644 index 0000000..ffdf039 --- /dev/null +++ b/board/mcc200/mt48lc16m16a2-75.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 0 /* is SDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +#define SDRAM_CONFIG2 0x8AD70000 + +#elif defined(CONFIG_MGT5100) +/* Settings for XLB = 66 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xC2222600 +#define SDRAM_CONFIG2 0x88B70004 +#define SDRAM_ADDRSEL 0x02000000 + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h new file mode 100644 index 0000000..13aebbd --- /dev/null +++ b/board/mcc200/mt48lc8m32b2-6-7.h @@ -0,0 +1,12 @@ +/* + * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform + */ + +#define SDRAM_DDR 0 /* is SDR */ + +/* Settings for XLB = 132 MHz */ + +#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */ +#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */ +#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */ +#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */ diff --git a/board/mcc200/u-boot.lds b/board/mcc200/u-boot.lds new file mode 100644 index 0000000..4fdea6b --- /dev/null +++ b/board/mcc200/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/netphone/config.mk b/board/netphone/config.mk index 8497ebc..de179c2 100644 --- a/board/netphone/config.mk +++ b/board/netphone/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0x40000000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c index dd03e4b..297de97 100644 --- a/board/netphone/netphone.c +++ b/board/netphone/netphone.c @@ -599,7 +599,7 @@ int board_early_init_f(void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/netstar/Makefile b/board/netstar/Makefile new file mode 100644 index 0000000..3a20501 --- /dev/null +++ b/board/netstar/Makefile @@ -0,0 +1,85 @@ +# +# (C) Copyright 2005 +# Ladislav Michl, 2N Telekomunikace, michl@2n.cz +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := netstar.o flash.o nand.o +SOBJS := setup.o crcek.o + +gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) + +LOAD_ADDR = 0x10400000 +LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds + +HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include + +all: $(LIB) eeprom.srec eeprom.bin crcek.srec crcek.bin crcit + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +eeprom.srec: eeprom.o eeprom_start.o + $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \ + -o $(<:.o=) -e $(<:.o=) $^ \ + -L../../examples -lstubs \ + -L../../lib_generic -lgeneric \ + -L$(gcclibdir) -lgcc + $(OBJCOPY) -O srec $(<:.o=) $@ + +eeprom.bin: eeprom.srec + $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null + +crcek.srec: crcek.o + $(LD) -g -Ttext 0x00000000 \ + -o $(<:.o=) -e $(<:.o=) $^ + $(OBJCOPY) -O srec $(<:.o=) $@ + +crcek.bin: crcek.srec + $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null + +crcit: crcit.o crc32.o + $(HOSTCC) $(HOST_CFLAGS) -o $@ $^ + +crcit.o: crcit.c + $(HOSTCC) $(HOST_CFLAGS) -c $< + +crc32.o: $(TOPDIR)/tools/crc32.c + $(HOSTCC) $(HOST_CFLAGS) -DUSE_HOSTCC -c $< + +clean: + rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin \ + crcek crcek.srec crcek.bin + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/netstar/config.mk b/board/netstar/config.mk new file mode 100644 index 0000000..50d647a --- /dev/null +++ b/board/netstar/config.mk @@ -0,0 +1,14 @@ +# +# Linux-Kernel is expected to be at 1000'8000, +# entry 1000'8000 (mem base + reserved) +# +# We load ourself to internal RAM at 2001'2000 +# Check map file when changing TEXT_BASE. +# Everything has fit into 192kB internal SRAM! +# + +# XXX TEXT_BASE = 0x20012000 +TEXT_BASE = 0x13FC0000 + +# Compile the new NAND code +BOARDLIBS = drivers/nand/libnand.a diff --git a/board/netstar/crcek.S b/board/netstar/crcek.S new file mode 100644 index 0000000..6ca4d11 --- /dev/null +++ b/board/netstar/crcek.S @@ -0,0 +1,177 @@ +/** + * (C) Copyright 2005 + * 2N Telekomunikace, Ladislav Michl <michl@2n.cz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2. + * + * Image layout looks like following: + * u32 - size + * u32 - version + * ... - data + * u32 - crc32 + */ + +#include "crcek.h" + +/** + * do_crc32 - calculate CRC32 of given buffer + * r0 - crc + * r1 - pointer to buffer + * r2 - buffer len + */ + .macro do_crc32 + ldr r5, FFFFFFFF + eor r0, r0, r5 + adr r3, CRC32_TABLE +1: + ldrb r4, [r1], #1 + eor r4, r4, r0 + and r4, r4, #0xff + ldr r4, [r3, r4, lsl#2] + eor r0, r4, r0, lsr#8 + subs r2, r2, #0x1 + bne 1b + eor r0, r0, r5 + .endm + + .macro crcuj, offset, size + mov r0, #0 + ldr r1, \offset + ldr r2, [r1] + cmp r2, r0 @ no data, no problem + beq 2f + tst r2, #3 @ unaligned size + bne 2f + ldr r3, \size + cmp r2, r3 @ bogus size + bhi 2f + add r1, r1, #4 + do_crc32 + ldr r1, [r1] +2: + cmp r0, r1 + .endm + + .macro wait, reg + mov \reg, #0x1000 +3: + subs \reg, \reg, #0x1 + bne 3b + + .endm +.text +.globl crcek +crcek: + b crc2_bad + mov r6, #0 + crcuj _LOADER1_OFFSET, _LOADER_SIZE + bne crc1_bad + orr r6, r6, #1 +crc1_bad: + crcuj _LOADER2_OFFSET, _LOADER_SIZE + bne crc2_bad + orr r6, r6, #2 +crc2_bad: + ldr r3, _LOADER1_OFFSET + ldr r4, _LOADER2_OFFSET + b boot_2nd + tst r6, #3 + beq one_is_bad @ one of them (or both) has bad crc + ldr r1, [r3, #4] + ldr r2, [r4, #4] + cmp r1, r2 @ boot 2nd loader if versions differ + beq boot_1st + b boot_2nd +one_is_bad: + tst r6, #1 + bne boot_1st + tst r6, #2 + bne boot_2nd +@ We are doomed, so let user know. + ldr r0, GPIO_BASE @ configure GPIO pins + ldr r1, GPIO_DIRECTION + strh r1, [r0, #0x08] +blink_loop: + mov r1, #0x08 + strh r1, [r0, #0x04] + wait r3 + mov r1, #0x10 + strh r1, [r0, #0x04] + wait r3 + b blink_loop +boot_1st: + add pc, r3, #8 +boot_2nd: + add pc, r4, #8 + +_LOADER_SIZE: + .word LOADER_SIZE - 8 @ minus size and crc32 +_LOADER1_OFFSET: + .word LOADER1_OFFSET +_LOADER2_OFFSET: + .word LOADER2_OFFSET + +FFFFFFFF: + .word 0xffffffff +CRC32_TABLE: + .word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419 + .word 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4 + .word 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07 + .word 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de + .word 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856 + .word 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9 + .word 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4 + .word 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b + .word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3 + .word 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a + .word 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599 + .word 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924 + .word 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190 + .word 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f + .word 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e + .word 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01 + .word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed + .word 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950 + .word 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3 + .word 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2 + .word 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a + .word 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5 + .word 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010 + .word 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f + .word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17 + .word 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6 + .word 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615 + .word 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8 + .word 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344 + .word 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb + .word 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a + .word 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5 + .word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1 + .word 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c + .word 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef + .word 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236 + .word 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe + .word 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31 + .word 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c + .word 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713 + .word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b + .word 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242 + .word 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1 + .word 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c + .word 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278 + .word 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7 + .word 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66 + .word 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9 + .word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605 + .word 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8 + .word 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b + .word 0x2d02ef8d + +GPIO_BASE: + .word 0xfffce000 +GPIO_DIRECTION: + .word 0x0000ffe7 + +.end diff --git a/board/netstar/crcek.h b/board/netstar/crcek.h new file mode 100644 index 0000000..30c0860 --- /dev/null +++ b/board/netstar/crcek.h @@ -0,0 +1,3 @@ +#define LOADER_SIZE (448 * 1024) +#define LOADER1_OFFSET (128 * 1024) +#define LOADER2_OFFSET (LOADER1_OFFSET + LOADER_SIZE) diff --git a/board/netstar/crcit b/board/netstar/crcit Binary files differnew file mode 100755 index 0000000..98ae42e --- /dev/null +++ b/board/netstar/crcit diff --git a/board/netstar/crcit.c b/board/netstar/crcit.c new file mode 100644 index 0000000..f6d3066 --- /dev/null +++ b/board/netstar/crcit.c @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2005 + * 2N Telekomunikace, Ladislav Michl <michl@2n.cz> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <stdio.h> +#include <stdlib.h> +#include <stdint.h> +#include <fcntl.h> +#include <string.h> +#include <unistd.h> +#include <sys/types.h> +#include <sys/stat.h> +#include "crcek.h" + +extern unsigned long crc32(unsigned long, const unsigned char *, unsigned int); + +uint32_t data[LOADER_SIZE/4 + 3]; + +int doit(char *path, unsigned version) +{ + uint32_t *p; + ssize_t size; + int fd; + + fd = open(path, O_RDONLY); + if (fd == -1) { + perror("Error opening file"); + return EXIT_FAILURE; + } + p = data + 2; + size = read(fd, p, LOADER_SIZE + 4); + if (size == -1) { + perror("Error reading file"); + return EXIT_FAILURE; + } + if (size > LOADER_SIZE) { + fprintf(stderr, "File too large\n"); + return EXIT_FAILURE; + } + size = (((size - 1) >> 2) + 1) << 2; + data[0] = size + 4; /* add size of version field */ + data[1] = version; + data[(size >> 2) + 2] = crc32(0, (unsigned char *)(data + 1), data[0]); + close(fd); + + if (write(STDOUT_FILENO, data, size + 3*4) == -1) { + perror("Error writing file"); + return EXIT_FAILURE; + } + + return EXIT_SUCCESS; +} + +int main(int argc, char **argv) +{ + if (argc == 2) { + return doit(argv[1], 0); + } else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) { + char *endptr, *nptr = argv[2]; + unsigned ver = strtoul(nptr, &endptr, 0); + if (nptr != '\0' && endptr == '\0') + return doit(argv[3], ver); + } + fprintf(stderr, "Usage: crcit [-v version] <image>\n"); + + return EXIT_FAILURE; +} diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c new file mode 100644 index 0000000..fef3822 --- /dev/null +++ b/board/netstar/eeprom.c @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2005 + * Ladislav Michl, 2N Telekomunikace, michl@2n.cz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Some code shamelessly stolen back from Robin Getz. + */ + +#define DEBUG + +#include <common.h> +#include <exports.h> +#include "../drivers/smc91111.h" + +#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE + +static u16 read_eeprom_reg(u16 reg) +{ + int timeout; + + SMC_SELECT_BANK(2); + SMC_outw(reg, PTR_REG); + + SMC_SELECT_BANK(1); + SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD, + CTL_REG); + timeout = 100; + while((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout) + udelay(100); + if (timeout == 0) { + printf("Timeout Reading EEPROM register %02x\n", reg); + return 0; + } + + return SMC_inw (GP_REG); +} + +static int write_eeprom_reg(u16 value, u16 reg) +{ + int timeout; + + SMC_SELECT_BANK(2); + SMC_outw(reg, PTR_REG); + + SMC_SELECT_BANK(1); + SMC_outw(value, GP_REG); + SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG); + timeout = 100; + while ((SMC_inw(CTL_REG) & CTL_STORE) && --timeout) + udelay (100); + if (timeout == 0) { + printf("Timeout Writing EEPROM register %02x\n", reg); + return 0; + } + + return 1; +} + +static int write_data(u16 *buf, int len) +{ + u16 reg = 0x23; + + while (len--) + write_eeprom_reg(*buf++, reg++); + + return 0; +} + +static int verify_macaddr(char *s) +{ + u16 reg; + int i, err = 0; + + printf("MAC Address: "); + err = i = 0; + for (i = 0; i < 3; i++) { + reg = read_eeprom_reg(0x20 + i); + printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n'); + if (s) + err |= reg != ((u16 *)s)[i]; + } + + return err ? 0 : 1; +} + +static int set_mac(char *s) +{ + int i; + char *e, eaddr[6]; + + /* turn string into mac value */ + for (i = 0; i < 6; i++) { + eaddr[i] = simple_strtoul(s, &e, 16); + s = (*e) ? e+1 : e; + } + + for (i = 0; i < 3; i++) + write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i); + + return 0; +} + +static int parse_element(char *s, unsigned char *buf, int len) +{ + int cnt; + char *p, num[3]; + unsigned char id; + + id = simple_strtoul(s, &p, 16); + if (*p++ != ':') + return -1; + cnt = 2; + num[2] = 0; + for (; *p; p += 2) { + if (p[1] == 0) + return -2; + if (cnt + 3 > len) + return -3; + num[0] = p[0]; + num[1] = p[1]; + buf[cnt++] = simple_strtoul(num, NULL, 16); + } + buf[0] = id; + buf[1] = cnt - 2; + + return cnt; +} + +extern int crcek(void); + +int eeprom(int argc, char *argv[]) +{ + int i, len, ret; + unsigned char buf[58], *p; + + app_startup(argv); + if (get_version() != XF_VERSION) { + printf("Wrong XF_VERSION.\n"); + printf("Application expects ABI version %d\n", XF_VERSION); + printf("Actual U-Boot ABI version %d\n", (int)get_version()); + return 1; + } + + return crcek(); + + if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) { + printf("SMSC91111 not found.\n"); + return 2; + } + + /* Called without parameters - print MAC address */ + if (argc < 2) { + verify_macaddr(NULL); + return 0; + } + + /* Print help message */ + if (argv[1][1] == 'h') { + printf("VoiceBlue EEPROM writer\n"); + printf("Built: %s at %s\n", __DATE__ , __TIME__ ); + printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n"); + return 0; + } + + /* Try to parse information elements */ + len = sizeof(buf); + p = buf; + for (i = 2; i < argc; i++) { + ret = parse_element(argv[i], p, len); + switch (ret) { + case -1: + printf("Element %d: malformed\n", i - 1); + return 3; + case -2: + printf("Element %d: odd character count\n", i - 1); + return 3; + case -3: + printf("Out of EEPROM memory\n"); + return 3; + default: + p += ret; + len -= ret; + } + } + + /* First argument (MAC) is mandatory */ + set_mac(argv[1]); + if (verify_macaddr(argv[1])) { + printf("*** MAC address does not match! ***\n"); + return 4; + } + + while (len--) + *p++ = 0; + + write_data((u16 *)buf, sizeof(buf) >> 1); + + return 0; +} diff --git a/board/netstar/eeprom.lds b/board/netstar/eeprom.lds new file mode 100644 index 0000000..317550d --- /dev/null +++ b/board/netstar/eeprom.lds @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * (C) Copyright 2005 + * Ladislav Michl, 2N Telekomunikace, <michl@2n.cz> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = ALIGN(4); + .text : + { + eeprom_start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/netstar/eeprom_start.S b/board/netstar/eeprom_start.S new file mode 100644 index 0000000..75d9f05 --- /dev/null +++ b/board/netstar/eeprom_start.S @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2005 2N Telekomunikace + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +.globl _start +_start: b eeprom + +#include "crcek.h" + +/** + * do_crc32 - calculate CRC32 of given buffer + * r0 - crc + * r1 - pointer to buffer + * r2 - buffer len + */ + .macro do_crc32 + ldr r5, FFFFFFFF + eor r0, r0, r5 + adr r3, CRC32_TABLE +1: + ldrb r4, [r1], #1 + eor r4, r4, r0 + and r4, r4, #0xff + ldr r4, [r3, r4, lsl#2] + eor r0, r4, r0, lsr#8 + subs r2, r2, #0x1 + bne 1b + eor r0, r0, r5 + .endm + + .macro crcuj, offset, size + ldr r1, \offset + ldr r2, [r1] + cmp r2, #0 @ no data, no problem + beq 2f + mov r7, #1 + tst r2, #3 @ unaligned size + bne 2f + mov r7, #2 + ldr r0, \size + cmp r2, r0 @ bogus size + bhi 2f + mov r7, #3 + add r1, r1, #4 + mov r0, #0 + do_crc32 + ldr r1, [r1] +2: + cmp r0, r1 + .endm + + .macro wait, reg + mov \reg, #0x1000 +3: + subs \reg, \reg, #0x1 + bne 3b + + .endm +.text +.globl crcek +crcek: + mov r6, #0 +@ crcuj _LOADER1_OFFSET, _LOADER_SIZE +@ bne crc1_bad +@ orr r6, r6, #1 +crc1_bad: + crcuj _LOADER2_OFFSET, _LOADER_SIZE + bne crc2_bad + orr r6, r6, #2 +crc2_bad: +@ mov r0, r6 + mov pc, lr + ldr r3, _LOADER1_OFFSET + ldr r4, _LOADER2_OFFSET + tst r6, #3 + beq one_is_bad @ one of them (or both) has bad crc + ldr r1, [r3, #4] + ldr r2, [r4, #4] + cmp r1, r2 @ boot 2nd loader if versions differ + beq boot_1st + b boot_2nd +one_is_bad: + tst r6, #1 + bne boot_1st + tst r6, #2 + bne boot_2nd +@ We are doomed, so let user know. + ldr r0, GPIO_BASE @ configure GPIO pins + ldr r1, GPIO_DIRECTION + strh r1, [r0, #0x08] +blink_loop: + mov r1, #0x08 + strh r1, [r0, #0x04] + wait r3 + mov r1, #0x10 + strh r1, [r0, #0x04] + wait r3 + b blink_loop +boot_1st: + add pc, r3, #8 +boot_2nd: + add pc, r4, #8 + +_LOADER_SIZE: + .word LOADER_SIZE - 8 @ minus size and crc32 +_LOADER1_OFFSET: + .word LOADER1_OFFSET +_LOADER2_OFFSET: + .word LOADER2_OFFSET + +FFFFFFFF: + .word 0xffffffff +CRC32_TABLE: + .word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419 + .word 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4 + .word 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07 + .word 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de + .word 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856 + .word 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9 + .word 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4 + .word 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b + .word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3 + .word 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a + .word 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599 + .word 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924 + .word 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190 + .word 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f + .word 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e + .word 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01 + .word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed + .word 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950 + .word 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3 + .word 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2 + .word 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a + .word 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5 + .word 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010 + .word 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f + .word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17 + .word 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6 + .word 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615 + .word 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8 + .word 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344 + .word 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb + .word 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a + .word 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5 + .word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1 + .word 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c + .word 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef + .word 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236 + .word 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe + .word 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31 + .word 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c + .word 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713 + .word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b + .word 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242 + .word 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1 + .word 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c + .word 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278 + .word 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7 + .word 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66 + .word 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9 + .word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605 + .word 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8 + .word 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b + .word 0x2d02ef8d + +GPIO_BASE: + .word 0xfffce000 +GPIO_DIRECTION: + .word 0x0000ffe7 + +.end diff --git a/board/netstar/flash.c b/board/netstar/flash.c new file mode 100644 index 0000000..692c416 --- /dev/null +++ b/board/netstar/flash.c @@ -0,0 +1,343 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu@sysgo.de> + * + * (C) Copyright 2005 + * 2N Telekomunikace, a.s. <www.2n.cz> + * Ladislav Michl <michl@2n.cz> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/*#if 0 */ +#if (PHYS_SDRAM_1_SIZE != SZ_32M) + +#include "crcek.h" + +#if (CFG_MAX_FLASH_BANKS > 1) +#error There is always only _one_ flash chip +#endif + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +#define CMD_READ_ARRAY 0x000000f0 +#define CMD_UNLOCK1 0x000000aa +#define CMD_UNLOCK2 0x00000055 +#define CMD_ERASE_SETUP 0x00000080 +#define CMD_ERASE_CONFIRM 0x00000030 +#define CMD_PROGRAM 0x000000a0 +#define CMD_UNLOCK_BYPASS 0x00000020 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002aa << 1))) + +#define BIT_ERASE_DONE 0x00000080 +#define BIT_RDY_MASK 0x00000080 +#define BIT_PROGRAM_ERROR 0x00000020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +/*----------------------------------------------------------------------- + */ + +ulong flash_init(void) +{ + int i; + + flash_info[0].flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV800B & FLASH_TYPEMASK); + flash_info[0].size = PHYS_FLASH_1_SIZE; + flash_info[0].sector_count = CFG_MAX_FLASH_SECT; + memset(flash_info[0].protect, 0, CFG_MAX_FLASH_SECT); + + for (i = 0; i < flash_info[0].sector_count; i++) { + switch (i) { + case 0: /* 16kB */ + flash_info[0].start[0] = CFG_FLASH_BASE; + break; + case 1: /* 8kB */ + flash_info[0].start[1] = CFG_FLASH_BASE + 0x4000; + break; + case 2: /* 8kB */ + flash_info[0].start[2] = CFG_FLASH_BASE + 0x4000 + + 0x2000; + break; + case 3: /* 32 KB */ + flash_info[0].start[3] = CFG_FLASH_BASE + 0x4000 + + 2 * 0x2000; + break; + case 4: + flash_info[0].start[4] = CFG_FLASH_BASE + 0x4000 + + 2 * 0x2000 + 0x8000; + break; + default: /* 64kB */ + flash_info[0].start[i] = flash_info[0].start[i-1] + + 0x10000; + break; + } + } + + /* U-Boot */ + flash_protect(FLAG_PROTECT_SET, + LOADER1_OFFSET, + LOADER1_OFFSET + LOADER_SIZE - 1, flash_info); + /* Protect crcek, env and r_env as well */ + flash_protect(FLAG_PROTECT_SET, 0, 0x8000 - 1, flash_info); + + return flash_info[0].size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info(flash_info_t *info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (AMD_MANUFACT & FLASH_VENDMASK): + puts("AMD: "); + break; + default: + puts("Unknown vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_LV800B & FLASH_TYPEMASK): + puts("AM29LV800BB (8Mb)\n"); + break; + default: + puts("Unknown chip type\n"); + return; + } + + printf(" Size: %ld MB in %d sectors\n", + info->size >> 20, info->sector_count); + + puts(" Sector start addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) + puts("\n "); + + printf(" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + puts("\n"); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + ushort result; + int prot, sect; + int rc = ERR_OK; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) + return ERR_INVAL; + + if ((info->flash_id & FLASH_VENDMASK) != + (AMD_MANUFACT & FLASH_VENDMASK)) + return ERR_UNKNOWN_FLASH_VENDOR; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) + if (info->protect[sect]) + prot++; + + if (prot) + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + else + putc('\n'); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_short *addr = (vu_short *) (info->start[sect]); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + while (1) { + result = *addr; + + /* check timeout */ + if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + rc = ERR_TIMOUT; + break; + } + + if ((result & 0xfff) & BIT_ERASE_DONE) + break; + + if ((result & 0xffff) & BIT_PROGRAM_ERROR) { + rc = ERR_PROG_ERROR; + break; + } + } + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (rc != ERR_OK) + goto out; + + putc('.'); + } + } +out: + /* allow flash to settle - wait 10 ms */ + udelay_masked(10000); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +static int write_hword(flash_info_t *info, ulong dest, ushort data) +{ + vu_short *addr = (vu_short *) dest; + ushort result; + int rc = ERR_OK; + + /* check if flash is (sufficiently) erased */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + + /* wait until flash is ready */ + while (1) { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + rc = ERR_TIMOUT; + break; + } + + if ((result & 0x80) == (data & 0x80)) + break; + + if ((result & 0xffff) & BIT_PROGRAM_ERROR) { + result = *addr; + + if ((result & 0x80) != (data & 0x80)) + rc = ERR_PROG_ERROR; + } + } + + *addr = CMD_READ_ARRAY; + + if (*addr != data) + rc = ERR_PROG_ERROR; + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + int l; + int i, rc; + ushort data; + + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) + data = (data >> 8) | (*(uchar *) cp << 8); + for (; i < 2 && cnt > 0; ++i) { + data = (data >> 8) | (*src++ << 8); + --cnt; + ++cp; + } + for (; cnt == 0 && i < 2; ++i, ++cp) + data = (data >> 8) | (*(uchar *) cp << 8); + + if ((rc = write_hword(info, wp, data)) != 0) + return (rc); + wp += 2; + } + + /* + * handle word aligned part + */ + while (cnt >= 2) { + data = *((vu_short *) src); + if ((rc = write_hword(info, wp, data)) != 0) + return (rc); + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 0) + return ERR_OK; + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i < 2; ++i, ++cp) + data = (data >> 8) | (*(uchar *) cp << 8); + + return write_hword(info, wp, data); +} + +#endif diff --git a/board/netstar/nand.c b/board/netstar/nand.c new file mode 100644 index 0000000..f470c1a --- /dev/null +++ b/board/netstar/nand.c @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <nand.h> + +/* + * hardware specific access to control-lines + */ +#define MASK_CLE 0x02 +#define MASK_ALE 0x04 + +static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); + switch (cmd) { + case NAND_CTL_SETCLE: IO_ADDR_W |= MASK_CLE; break; + case NAND_CTL_SETALE: IO_ADDR_W |= MASK_ALE; break; + } + this->IO_ADDR_W = (void *) IO_ADDR_W; +} + +/* + * chip R/B detection + */ +/*** +static int netstar_nand_ready(struct mtd_info *mtd) +{ + return (*(volatile ushort *)GPIO_DATA_INPUT_REG) & 0x02; +} +***/ + +void board_nand_init(struct nand_chip *nand) +{ + nand->options = NAND_SAMSUNG_LP_OPTIONS; + nand->eccmode = NAND_ECC_SOFT; + nand->hwcontrol = netstar_nand_hwcontrol; +/* nand->dev_ready = netstar_nand_ready; */ + nand->chip_delay = 18; +} +#endif diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c new file mode 100644 index 0000000..62615e5 --- /dev/null +++ b/board/netstar/netstar.c @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of NetStar board */ + /* TODO: use define from asm/mach-types.h */ + gd->bd->bi_arch_number = 692; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x10000100; + + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + /* Take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. */ + *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80; + udelay(10); /* doesn't work before interrupt_init call */ + *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80; + udelay(500); + + return 0; +} + +extern void partition_flash(void); + +int misc_init_r(void) +{ + return 0; +} + +extern void nand_init(void); + +int board_late_init(void) +{ + return 0; +} diff --git a/board/netstar/setup.S b/board/netstar/setup.S new file mode 100644 index 0000000..f67786d --- /dev/null +++ b/board/netstar/setup.S @@ -0,0 +1,287 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004 Ales Jindra <jindra@2n.cz> + * (C) Copyright 2005 Ladislav Michl <michl@2n.cz> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +_TEXT_BASE: + .word TEXT_BASE /* SDRAM load addr from config.mk */ + +OMAP5910_LPG1_BASE: .word 0xfffbd000 +OMAP5910_TIPB_SWITCHES_BASE: .word 0xfffbc800 +OMAP5910_MPU_TC_BASE: .word 0xfffecc00 +OMAP5910_MPU_CLKM_BASE: .word 0xfffece00 +OMAP5910_ULPD_PWR_MNG_BASE: .word 0xfffe0800 +OMAP5910_DPLL1_BASE: .word 0xfffecf00 +OMAP5910_GPIO_BASE: .word 0xfffce000 +OMAP5910_MPU_WD_TIMER_BASE: .word 0xfffec800 +OMAP5910_MPUI_BASE: .word 0xfffec900 + +_OMAP5910_ARM_CKCTL: .word OMAP5910_ARM_CKCTL +_OMAP5910_ARM_EN_CLK: .word OMAP5910_ARM_EN_CLK + +OMAP5910_MPUI_CTRL: .word 0x0000ff1b + +VAL_EMIFS_CS0_CONFIG: .word 0x00009090 +VAL_EMIFS_CS1_CONFIG: .word 0x00003031 +VAL_EMIFS_CS2_CONFIG: .word 0x0000a0a1 +VAL_EMIFS_CS3_CONFIG: .word 0x0000c0c0 +VAL_EMIFS_DYN_WAIT: .word 0x00000000 +/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */ + /* SLRF SD_RET ARE SDRAM_TYPE ARCV SDRAM_FREQUENCY PWD CLK */ + +#if (PHYS_SDRAM_1_SIZE == SZ_32M) +VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xf << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) +#else +VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) +#endif + +VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003 +VAL_EMIFF_MRS: .word 0x00000037 + +/* + * GPIO04 - Green LED (Red LED is connected to LED Pulse Generator) + * GPIO07 - LAN91C111 reset + */ +GPIO_DIRECTION: + .word 0x0000ff6f +/* + * Disable everything (green LED is connected via invertor) + */ +GPIO_OUTPUT: + .word 0x00000010 + +MUX_CONFIG_BASE: + .word 0xfffe1000 + +MUX_CONFIG_VALUES: + .align 4 + .word 0x00000000 @ FUNC_MUX_CTRL_0 + .word 0x00000000 @ FUNC_MUX_CTRL_1 + .word 0x00000000 @ FUNC_MUX_CTRL_2 + .word 0x00000000 @ FUNC_MUX_CTRL_3 + .word 0x00000000 @ FUNC_MUX_CTRL_4 + .word 0x02080480 @ FUNC_MUX_CTRL_5 + .word 0x0100001c @ FUNC_MUX_CTRL_6 + .word 0x0004800b @ FUNC_MUX_CTRL_7 + .word 0x10001200 @ FUNC_MUX_CTRL_8 + .word 0x01201012 @ FUNC_MUX_CTRL_9 + .word 0x02082248 @ FUNC_MUX_CTRL_A + .word 0x00000248 @ FUNC_MUX_CTRL_B + .word 0x12240000 @ FUNC_MUX_CTRL_C + .word 0x00002000 @ FUNC_MUX_CTRL_D + .word 0x00000000 @ PULL_DWN_CTRL_0 + .word 0x00000800 @ PULL_DWN_CTRL_1 + .word 0x01801000 @ PULL_DWN_CTRL_2 + .word 0x00000000 @ PULL_DWN_CTRL_3 + .word 0x00000000 @ GATE_INH_CTRL_0 + .word 0x00000000 @ VOLTAGE_CTRL_0 + .word 0x00000000 @ TEST_DBG_CTRL_0 + .word 0x00000006 @ MOD_CONF_CTRL_0 + .word 0x0000eaef @ COMP_MODE_CTRL_0 + +MUX_CONFIG_OFFSETS: + .align 1 + .byte 0x00 @ FUNC_MUX_CTRL_0 + .byte 0x04 @ FUNC_MUX_CTRL_1 + .byte 0x08 @ FUNC_MUX_CTRL_2 + .byte 0x10 @ FUNC_MUX_CTRL_3 + .byte 0x14 @ FUNC_MUX_CTRL_4 + .byte 0x18 @ FUNC_MUX_CTRL_5 + .byte 0x1c @ FUNC_MUX_CTRL_6 + .byte 0x20 @ FUNC_MUX_CTRL_7 + .byte 0x24 @ FUNC_MUX_CTRL_8 + .byte 0x28 @ FUNC_MUX_CTRL_9 + .byte 0x2c @ FUNC_MUX_CTRL_A + .byte 0x30 @ FUNC_MUX_CTRL_B + .byte 0x34 @ FUNC_MUX_CTRL_C + .byte 0x38 @ FUNC_MUX_CTRL_D + .byte 0x40 @ PULL_DWN_CTRL_0 + .byte 0x44 @ PULL_DWN_CTRL_1 + .byte 0x48 @ PULL_DWN_CTRL_2 + .byte 0x4c @ PULL_DWN_CTRL_3 + .byte 0x50 @ GATE_INH_CTRL_0 + .byte 0x60 @ VOLTAGE_CTRL_0 + .byte 0x70 @ TEST_DBG_CTRL_0 + .byte 0x80 @ MOD_CONF_CTRL_0 + .byte 0x0c @ COMP_MODE_CTRL_0 + .byte 0xff + +.globl lowlevel_init +lowlevel_init: + /* Improve performance a bit... */ + mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register + mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register + mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register + orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000 + mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register + mov r1, #0x00 + mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache + nop + nop + nop + nop + + /* Setup clocking mode */ + ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit + ldrh r1, [r0, #0x18] @ get reset status + bic r1, r1, #(7 << 11) @ clear clock select + orr r1, r1, #(2 << 11) @ set synchronous scalable + mov r2, #0 @ set wait counter to 100 clock cycles + +icache_loop: + cmp r2, #0x01 + streqh r1, [r0, #0x18] + add r2, r2, #0x01 + cmp r2, #0x10 + bne icache_loop + nop + + /* Setup clock divisors */ + ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit + ldr r1, _OMAP5910_ARM_CKCTL + orr r1, r1, #0x2000 @ enable DSP clock + strh r1, [r0, #0x00] @ setup clock divisors + + /* Setup DPLL to generate requested freq */ + ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register + mov r1, #0x0010 @ set PLL_ENABLE + orr r1, r1, #0x2000 @ set IOB to new locking + orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF + orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF + strh r1, [r0] @ write + +locking: + ldrh r1, [r0] @ get DPLL value + tst r1, #0x01 + beq locking @ while LOCK not set + + /* Enable clock */ + ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit + mov r1, #(1 << 10) @ disable idle mode do not check + @ nWAKEUP pin, other remain active + strh r1, [r0, #0x04] + ldr r1, _OMAP5910_ARM_EN_CLK + strh r1, [r0, #0x08] + mov r1, #0x003f @ FLASH.RP not enabled in idle and + @ max delayed ( 32 x CLKIN ) + strh r1, [r0, #0x0c] + + /* Configure 5910 pins functions to match our board. */ + ldr r0, MUX_CONFIG_BASE + adr r1, MUX_CONFIG_VALUES + adr r2, MUX_CONFIG_OFFSETS +next_mux_cfg: + ldrb r3, [r2], #1 + ldr r4, [r1], #4 + cmp r3, #0xff + strne r4, [r0, r3] + bne next_mux_cfg + + /* Configure GPIO pins (also disables Green LED) */ + ldr r0, OMAP5910_GPIO_BASE + ldr r1, GPIO_OUTPUT + strh r1, [r0, #0x04] + ldr r1, GPIO_DIRECTION + strh r1, [r0, #0x08] + + /* EnablePeripherals */ + ldr r0, OMAP5910_MPU_CLKM_BASE @ CLOCK unit + mov r1, #0x0001 @ Peripheral enable + strh r1, [r0, #0x14] + + /* Program LED Pulse Generator */ + ldr r0, OMAP5910_LPG1_BASE @ 1st LED Pulse Generator + mov r1, #0x7F @ Set obscure frequency in + strb r1, [r0, #0x00] @ LCR + mov r1, #0x01 @ Enable clock (CLK_EN) in + strb r1, [r0, #0x04] @ PMR + + /* TIPB Lock UART1 */ + ldr r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches + mov r1, #1 @ ARM allocated + strh r1, [r0,#0x04] @ clear IRQ line and status bits + strh r1, [r0,#0x00] + ldrh r1, [r0,#0x04] + + /* Disable watchdog */ + ldr r0, OMAP5910_MPU_WD_TIMER_BASE + mov r1, #0xf5 + strh r1, [r0, #0x8] + mov r1, #0xa0 + strh r1, [r0, #0x8] + + /* Enable MCLK */ + ldr r0, OMAP5910_ULPD_PWR_MNG_BASE + mov r1, #0x6 + strh r1, [r0, #0x34] + strh r1, [r0, #0x34] + + /* Setup clock divisors */ + ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register + + mov r1, #0x0010 @ set PLL_ENABLE + orr r1, r1, #0x2000 @ set IOB to new locking + strh r1, [r0] @ write + +ulocking: + ldrh r1, [r0] @ get DPLL value + tst r1, #1 + beq ulocking @ while LOCK not set + + /* EMIF init */ + ldr r0, OMAP5910_MPU_TC_BASE + ldrh r1, [r0, #0x0c] @ EMIFS_CONFIG_REG + bic r1, r1, #0x0c @ pwr down disabled, flash WP + orr r1, r1, #0x01 + str r1, [r0, #0x0c] + + ldr r1, VAL_EMIFS_CS0_CONFIG + str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG + ldr r1, VAL_EMIFS_CS1_CONFIG + str r1, [r0, #0x14] @ EMIFS_CS1_CONFIG + ldr r1, VAL_EMIFS_CS2_CONFIG + str r1, [r0, #0x18] @ EMIFS_CS2_CONFIG + ldr r1, VAL_EMIFS_CS3_CONFIG + str r1, [r0, #0x1c] @ EMIFS_CS3_CONFIG + ldr r1, VAL_EMIFS_DYN_WAIT + str r1, [r0, #0x40] @ EMIFS_CFG_DYN_WAIT + + /* Setup SDRAM */ + ldr r1, VAL_EMIFF_SDRAM_CONFIG + str r1, [r0, #0x20] @ EMIFF_SDRAM_CONFIG + ldr r1, VAL_EMIFF_SDRAM_CONFIG2 + str r1, [r0, #0x3c] @ EMIFF_SDRAM_CONFIG2 + ldr r1, VAL_EMIFF_MRS + str r1, [r0, #0x24] @ EMIFF_MRS + /* SDRAM needs 100us to stabilize */ + mov r0, #0x4000 +sdelay: + subs r0, r0, #0x1 + bne sdelay + + /* back to arch calling code */ + mov pc, lr +.end diff --git a/board/netstar/u-boot.lds b/board/netstar/u-boot.lds new file mode 100644 index 0000000..8317f72 --- /dev/null +++ b/board/netstar/u-boot.lds @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm925t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/netta2/config.mk b/board/netta2/config.mk index 8497ebc..de179c2 100644 --- a/board/netta2/config.mk +++ b/board/netta2/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0x40000000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c index c9b4051..3ca7bd3 100644 --- a/board/netta2/netta2.c +++ b/board/netta2/netta2.c @@ -597,7 +597,7 @@ int board_early_init_f(void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/netvia/config.mk b/board/netvia/config.mk index 9dddaad..583174a 100644 --- a/board/netvia/config.mk +++ b/board/netvia/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0x40000000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/netvia/netvia.c b/board/netvia/netvia.c index fb7f770..3e6c616 100644 --- a/board/netvia/netvia.c +++ b/board/netvia/netvia.c @@ -418,7 +418,7 @@ int board_early_init_f(void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c index 6ae1a49..2387176 100644 --- a/board/omap2420h4/omap2420h4.c +++ b/board/omap2420h4/omap2420h4.c @@ -32,7 +32,7 @@ #include <i2c.h> #include <asm/mach-types.h> #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; #endif diff --git a/board/pm520/flash.c b/board/pm520/flash.c index ccd0bd1..38f579b 100644 --- a/board/pm520/flash.c +++ b/board/pm520/flash.c @@ -242,10 +242,11 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) case (FPW) INTEL_ID_28F256J3A: info->flash_id += FLASH_28F256J3A; - info->sector_count = 256; - info->size = 0x04000000; - info->start[0] = CFG_FLASH_BASE; - break; /* => 64 MB */ + /* In U-Boot we support only 32 MB (no bank-switching) */ + info->sector_count = 256 / 2; + info->size = 0x04000000 / 2; + info->start[0] = CFG_FLASH_BASE + 0x02000000; + break; /* => 32 MB */ case (FPW) INTEL_ID_28F128J3A: info->flash_id += FLASH_28F128J3A; diff --git a/board/shannon/flash.c b/board/shannon/flash.c index 13c01d8..475b76b 100644 --- a/board/shannon/flash.c +++ b/board/shannon/flash.c @@ -315,7 +315,7 @@ outahere: * Copy memory to flash */ -volatile static int write_word (flash_info_t *info, ulong dest, ulong data) +static int write_word (flash_info_t *info, ulong dest, ulong data) { vu_long *addr = (vu_long *)dest; ulong result; diff --git a/board/sixnet/config.mk b/board/sixnet/config.mk index 0cd8f44..8e73d2f 100644 --- a/board/sixnet/config.mk +++ b/board/sixnet/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0xF8000000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c index 867589f..a25dffd 100644 --- a/board/sixnet/sixnet.c +++ b/board/sixnet/sixnet.c @@ -34,7 +34,7 @@ #endif #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; #endif diff --git a/board/smdk2400/flash.c b/board/smdk2400/flash.c index a108af7..fd9992d 100644 --- a/board/smdk2400/flash.c +++ b/board/smdk2400/flash.c @@ -353,8 +353,7 @@ outahere: * Copy memory to flash */ -volatile static int write_word (flash_info_t * info, ulong dest, - ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { vu_long *addr = (vu_long *) dest; ulong result; diff --git a/board/stamp/Makefile b/board/stamp/Makefile new file mode 100644 index 0000000..ab97e1b --- /dev/null +++ b/board/stamp/Makefile @@ -0,0 +1,68 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005 blackfin.uclinux.org +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o stamp.o +SOBJS = + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/stamp/config.mk b/board/stamp/config.mk new file mode 100644 index 0000000..0d00730 --- /dev/null +++ b/board/stamp/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x07FC0000 +PLATFORM_CPPFLAGS += -I$(TOPDIR) diff --git a/board/stamp/stamp.c b/board/stamp/stamp.c new file mode 100644 index 0000000..3fe0134 --- /dev/null +++ b/board/stamp/stamp.c @@ -0,0 +1,275 @@ +/* + * U-boot - stamp.c STAMP board specific routines + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mem_init.h> +#include "stamp.h" + +#define STATUS_LED_OFF 0 +#define STATUS_LED_ON 1 + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +int checkboard (void) +{ + printf ("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28); + printf ("Board: ADI BF533 Stamp board\n"); + printf (" Support: http://blackfin.uclinux.org/\n"); + printf (" Richard Klingler <richard@uclinux.net>\n"); + return 0; +} + +long int initdram (int board_type) +{ + DECLARE_GLOBAL_DATA_PTR; +#ifdef DEBUG + printf ("SDRAM attributes:\n"); + printf (" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; " + "CAS Latency:%d cycles\n", + (SDRAM_tRCD >> 15), + (SDRAM_tRP >> 11), + (SDRAM_tRAS >> 6), + (SDRAM_tWR >> 19), + (SDRAM_CL >> 2)); + printf ("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE); + printf ("Bank size = %d MB\n", 128); +#endif + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_MAX_RAM_SIZE; + return (gd->bd->bi_memsize); +} + +void swap_to (int device_id) +{ + + if (device_id == ETHERNET) { + *pFIO_DIR = PF0; + asm ("ssync;"); + *pFIO_FLAG_S = PF0; + asm ("ssync;"); + } else if (device_id == FLASH) { + *pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0); + *pFIO_FLAG_S = (PF4 | PF3 | PF2); + *pFIO_MASKA_D = (PF8 | PF6 | PF5); + *pFIO_MASKB_D = (PF7); + *pFIO_POLAR = (PF8 | PF6 | PF5); + *pFIO_EDGE = (PF8 | PF7 | PF6 | PF5); + *pFIO_INEN = (PF8 | PF7 | PF6 | PF5); + *pFIO_FLAG_D = (PF4 | PF3 | PF2); + asm ("ssync;"); + } else { + printf ("Unknown bank to switch\n"); + } + + return; +} + +#if defined(CONFIG_MISC_INIT_R) +/* miscellaneous platform dependent initialisations */ +int misc_init_r (void) +{ + int i; + int cf_stat = 0; + + /* Check whether CF card is inserted */ + *pFIO_EDGE = FIO_EDGE_CF_BITS; + *pFIO_POLAR = FIO_POLAR_CF_BITS; + for (i = 0; i < 0x300; i++) + asm ("nop;"); + + if ((*pFIO_FLAG_S) & CF_STAT_BITS) { + cf_stat = 0; + } else { + cf_stat = 1; + } + + *pFIO_EDGE = FIO_EDGE_BITS; + *pFIO_POLAR = FIO_POLAR_BITS; + + + if (cf_stat) { + printf ("Booting from COMPACT flash\n"); + + /* Set cycle time for CF */ + *(volatile unsigned long *) ambctl1 = CF_AMBCTL1VAL; + + for (i = 0; i < 0x1000; i++) + asm ("nop;"); + for (i = 0; i < 0x1000; i++) + asm ("nop;"); + for (i = 0; i < 0x1000; i++) + asm ("nop;"); + + serial_setbrg (); + ide_init (); + + setenv ("bootargs", ""); + setenv ("bootcmd", + "fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000"); + } else { + printf ("Booting from FLASH\n"); + } + + return 1; +} +#endif + +#ifdef CONFIG_STAMP_CF + +void cf_outb (unsigned char val, volatile unsigned char *addr) +{ + /* + * Set PF1 PF0 respectively to 0 1 to divert address + * to the expansion memory banks + */ + *pFIO_FLAG_S = CF_PF0; + *pFIO_FLAG_C = CF_PF1; + asm ("ssync;"); + + *(addr) = val; + asm ("ssync;"); + + /* Setback PF1 PF0 to 0 0 to address external + * memory banks */ + *(volatile unsigned short *) pFIO_FLAG_C = CF_PF1_PF0; + asm ("ssync;"); +} + +unsigned char cf_inb (volatile unsigned char *addr) +{ + volatile unsigned char c; + + *pFIO_FLAG_S = CF_PF0; + *pFIO_FLAG_C = CF_PF1; + asm ("ssync;"); + + c = *(addr); + asm ("ssync;"); + + *pFIO_FLAG_C = CF_PF1_PF0; + asm ("ssync;"); + + return c; +} + +void cf_insw (unsigned short *sect_buf, unsigned short *addr, int words) +{ + int i; + + *pFIO_FLAG_S = CF_PF0; + *pFIO_FLAG_C = CF_PF1; + asm ("ssync;"); + + for (i = 0; i < words; i++) { + *(sect_buf + i) = *(addr); + asm ("ssync;"); + } + + *pFIO_FLAG_C = CF_PF1_PF0; + asm ("ssync;"); +} + +void cf_outsw (unsigned short *addr, unsigned short *sect_buf, int words) +{ + int i; + + *pFIO_FLAG_S = CF_PF0; + *pFIO_FLAG_C = CF_PF1; + asm ("ssync;"); + + for (i = 0; i < words; i++) { + *(addr) = *(sect_buf + i); + asm ("ssync;"); + } + + *pFIO_FLAG_C = CF_PF1_PF0; + asm ("ssync;"); +} +#endif + +void stamp_led_set (int LED1, int LED2, int LED3) +{ + *pFIO_INEN &= ~(PF2 | PF3 | PF4); + *pFIO_DIR |= (PF2 | PF3 | PF4); + + if (LED1 == STATUS_LED_OFF) + *pFIO_FLAG_S = PF2; + else + *pFIO_FLAG_C = PF2; + if (LED2 == STATUS_LED_OFF) + *pFIO_FLAG_S = PF3; + else + *pFIO_FLAG_C = PF3; + if (LED3 == STATUS_LED_OFF) + *pFIO_FLAG_S = PF4; + else + *pFIO_FLAG_C = PF4; + asm ("ssync;"); +} + +void show_boot_progress (int status) +{ + switch (status) { + case 1: + stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON); + break; + case 2: + stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF); + break; + case 3: + stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON); + break; + case 4: + stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF); + break; + case 5: + case 6: + stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON); + break; + case 7: + case 8: + stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF); + break; + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF, + STATUS_LED_OFF); + break; + default: + stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON); + break; + } +} diff --git a/board/stamp/stamp.h b/board/stamp/stamp.h new file mode 100644 index 0000000..7bc33b4 --- /dev/null +++ b/board/stamp/stamp.h @@ -0,0 +1,57 @@ +/* + * U-boot - stamp.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __STAMP_H__ +#define __STAMP_H__ + +extern void init_Flags(void); + +extern volatile unsigned long *ambctl0; +extern volatile unsigned long *ambctl1; +extern volatile unsigned long *amgctl; + +extern unsigned long pll_div_fact; +extern void serial_setbrg(void); +extern void pll_set(int vco, int crystal_frq, int pll_div); + +/* Definitions used in Compact Flash Boot support */ +#define FIO_EDGE_CF_BITS 0x0000 +#define FIO_POLAR_CF_BITS 0x0000 +#define FIO_EDGE_BITS 0x1E0 +#define FIO_POLAR_BITS 0x160 + +/* Compact flash status bits in status register */ +#define CF_STAT_BITS 0x00000060 + +/* CF Flags used to switch between expansion and external + * memory banks + */ +#define CF_PF0 0x0001 +#define CF_PF1 0x0002 +#define CF_PF1_PF0 0x0003 + +#endif diff --git a/board/stamp/u-boot.lds b/board/stamp/u-boot.lds new file mode 100644 index 0000000..9a22e50 --- /dev/null +++ b/board/stamp/u-boot.lds @@ -0,0 +1,147 @@ +/* + * U-boot - u-boot.lds + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(bfin) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector before the environment sector. If it throws */ + /* an error during compilation remove an object here to get */ + /* it linked after the configuration sector. */ + + cpu/bf533/start.o (.text) + cpu/bf533/start1.o (.text) + cpu/bf533/traps.o (.text) + cpu/bf533/interrupt.o (.text) + cpu/bf533/serial.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/stxxtc/stxxtc.c b/board/stxxtc/stxxtc.c index aa3d129..7caf06a 100644 --- a/board/stxxtc/stxxtc.c +++ b/board/stxxtc/stxxtc.c @@ -576,7 +576,7 @@ int board_early_init_f(void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c index 13ea6f4..c03b60d 100644 --- a/board/tqm85xx/tqm85xx.c +++ b/board/tqm85xx/tqm85xx.c @@ -296,7 +296,7 @@ int misc_init_r (void) /* Monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, 0xffffffff, + CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[CFG_MAX_FLASH_BANKS - 1]); /* Environment protection ON by default */ diff --git a/board/trab/Makefile b/board/trab/Makefile index ced9bc5..159404b 100644 --- a/board/trab/Makefile +++ b/board/trab/Makefile @@ -47,7 +47,7 @@ trab_fkt.srec: trab_fkt.o rs485.o tsc2000.o $(LIB) $(OBJCOPY) -O srec $(<:.o=) $@ trab_fkt.bin: trab_fkt.srec - $(OBJCOPY) -O binary $< $@ 2>/dev/null + $(OBJCOPY) -I srec -O binary $< $@ clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/trab/flash.c b/board/trab/flash.c index b4435e3..8cdd824 100644 --- a/board/trab/flash.c +++ b/board/trab/flash.c @@ -308,8 +308,7 @@ outahere: * Copy memory to flash */ -volatile static int write_word (flash_info_t * info, ulong dest, - ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { vu_long *addr = (vu_long *) dest; ulong result; diff --git a/board/xilinx/xilinx_enet/emac_adapter.c b/board/xilinx/xilinx_enet/emac_adapter.c index 1076345..5c492eb 100644 --- a/board/xilinx/xilinx_enet/emac_adapter.c +++ b/board/xilinx/xilinx_enet/emac_adapter.c @@ -148,7 +148,7 @@ eth_rx(void) RecvFrameLength = PKTSIZE; Result = XEmac_PollRecv(&Emac, (u8 *) etherrxbuff, &RecvFrameLength); if (Result == XST_SUCCESS) { - NetReceive((uchar)etherrxbuff, RecvFrameLength); + NetReceive((uchar *)etherrxbuff, RecvFrameLength); return (1); } else { return (0); diff --git a/board/zpc1900/config.mk b/board/zpc1900/config.mk index 1072dc7..3e53b2b 100644 --- a/board/zpc1900/config.mk +++ b/board/zpc1900/config.mk @@ -27,4 +27,4 @@ # ZPC.1900 board # -TEXT_BASE = 0xFFE00000 +TEXT_BASE = 0xFE000000 diff --git a/board/zpc1900/zpc1900.c b/board/zpc1900/zpc1900.c index 6d16a0d..7db535e 100644 --- a/board/zpc1900/zpc1900.c +++ b/board/zpc1900/zpc1900.c @@ -2,7 +2,7 @@ * (C) Copyright 2001-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2003 Arabella Software Ltd. + * (C) Copyright 2003-2005 Arabella Software Ltd. * Yuli Barcohen <yuli@arabellasw.com> * * See file CREDITS for list of people who contributed to this @@ -27,9 +27,6 @@ #include <common.h> #include <ioports.h> #include <mpc8260.h> -#include <asm/m8260_pci.h> -#include <i2c.h> -#include <spd.h> #include <miiphy.h> /* @@ -167,8 +164,8 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ @@ -231,11 +228,10 @@ long int initdram(int board_type) vu_char *ramaddr; uchar c = 0xFF; long int msize = CFG_SDRAM_SIZE; - uint psdmr = CFG_PSDMR; int i; if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */ - immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; + immap->im_clkrst.car_sccr |= SCCR_PCI_MODE; immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) | SIUMCR_LBPC01; @@ -255,10 +251,10 @@ long int initdram(int board_type) */ if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) { memctl->memc_lsrt = CFG_LSRT; - memctl->memc_or4 = 0xFFC01480; - memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861; - memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA; + memctl->memc_or4 = CFG_LSDRAM_OR; + memctl->memc_br4 = CFG_LSDRAM_BR; ramaddr = (vu_char *)CFG_LSDRAM_BASE; + memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA; *ramaddr = c; memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR; for (i = 0; i < 8; i++) @@ -271,8 +267,8 @@ long int initdram(int board_type) /* Initialise 60x bus SDRAM */ memctl->memc_psrt = CFG_PSRT; - memctl->memc_or2 = 0xFC0028C0; - memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041; + memctl->memc_or2 = CFG_PSDRAM_OR; + memctl->memc_br2 = CFG_PSDRAM_BR; /* * The mode data for Mode Register Write command must appear on * the address lines during a mode-set cycle. It is driven by @@ -283,15 +279,15 @@ long int initdram(int board_type) * length must be 4. */ ramaddr = (vu_char *)(CFG_SDRAM_BASE | - ((psdmr & PSDMR_CL_MSK) << 7) | 0x10); - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ + ((CFG_PSDMR & PSDMR_CL_MSK) << 7) | 0x10); + memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */ *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ + memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */ for (i = 0; i < 8; i++) *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ + memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_MRW; /* Mode Register write */ *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ + memctl->memc_psdmr = CFG_PSDMR | PSDMR_RFEN; /* Refresh enable */ *ramaddr = c; #endif /* CFG_RAMBOOT */ diff --git a/board/zylonite/Makefile b/board/zylonite/Makefile new file mode 100644 index 0000000..999647f --- /dev/null +++ b/board/zylonite/Makefile @@ -0,0 +1,48 @@ + +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := zylonite.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/zylonite/config.mk b/board/zylonite/config.mk new file mode 100644 index 0000000..09b0f71 --- /dev/null +++ b/board/zylonite/config.mk @@ -0,0 +1,4 @@ +#TEXT_BASE = 0x0 +#TEXT_BASE = 0xa1700000 +#TEXT_BASE = 0xa3080000 +TEXT_BASE = 0xa3008000 diff --git a/board/zylonite/flash.c b/board/zylonite/flash.c new file mode 100644 index 0000000..883c1ba --- /dev/null +++ b/board/zylonite/flash.c @@ -0,0 +1,434 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/byteorder/swab.h> + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#define FLASH_PORT_WIDTH32 +#undef FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info); +static int write_data (flash_info_t *info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t *info); +void inline spin_wheel (void); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ +#if 0 + int i; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + break; + case 1: + flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect ( FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0] ); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); + + return size; +#endif + return 0; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + printf ("28F128J3A\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW *addr, flash_info_t *info) +{ + volatile FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0]; + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + + switch (value) { + + case (FPW) INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 128; + info->size = 0x02000000; + break; /* => 16 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = (FPW) 0x00B000B0; /* suspend erase */ + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + rcode = 1; + break; + } + } + + *addr = 0x00500050; /* clear status register cmd. */ + *addr = 0x00FF00FF; /* resest to read mode */ + + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t *info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/zylonite/lowlevel_init.S b/board/zylonite/lowlevel_init.S new file mode 100644 index 0000000..c3bb4eb --- /dev/null +++ b/board/zylonite/lowlevel_init.S @@ -0,0 +1,371 @@ +/* + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> + +DRAM_SIZE: .long CFG_DRAM_SIZE + +/* wait for coprocessor write complete */ +.macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 +.endm + + +.macro wait time + ldr r2, =OSCR + mov r3, #0 + str r3, [r2] +0: + ldr r3, [r2] + cmp r3, \time + bls 0b +.endm + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + /* Set up GPIO pins first ----------------------------------------- */ + mov r10, lr + + /* Configure GPIO Pins 41 - 48 as UART1 / altern. Fkt. 2 */ + ldr r0, =0x40E10438 @ GPIO41 FFRXD + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E1043C @ GPIO42 FFTXD + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10440 @ GPIO43 FFCTS + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10444 @ GPIO 44 FFDCD + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10448 @ GPIO 45 FFDSR + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E1044C @ GPIO 46 FFRI + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10450 @ GPIO 47 FFDTR + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10454 @ GPIO 48 + ldr r1, =0x802 + str r1, [r0] + + /* tebrandt - ASCR, clear the RDH bit */ + ldr r0, =ASCR + ldr r1, [r0] + bic r1, r1, #0x80000000 + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + /* mk: replaced with wait macro */ +/* ldr r3, =OSCR /\* reset the OS Timer Count to zero *\/ */ +/* mov r2, #0 */ +/* str r2, [r3] */ +/* ldr r4, =0x300 /\* really 0x2E1 is about 200usec, *\/ */ +/* /\* so 0x300 should be plenty *\/ */ +/* 1: */ +/* ldr r2, [r3] */ +/* cmp r4, r2 */ +/* bgt 1b */ + wait #300 + +mem_init: + + /* configure the MEMCLKCFG register */ + ldr r1, =MEMCLKCFG + ldr r2, =0x00010001 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[0] to data flash SRAM mode */ + ldr r1, =CSADRCFG0 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[1] to data flash SRAM mode */ + ldr r1, =CSADRCFG1 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set MSC 0 register for SRAM memory */ + ldr r1, =MSC0 + ldr r2, =0x11191119 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[2] to data flash SRAM mode */ + ldr r1, =CSADRCFG2 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set CSADRCFG[3] to VLIO mode */ + ldr r1, =CSADRCFG3 + ldr r2, =0x0032080B + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + + /* set MSC 1 register for VLIO memory */ + ldr r1, =MSC1 + ldr r2, =0x123C1119 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + +#if 0 + /* This does not work in Zylonite. -SC */ + ldr r0, =0x15fffff0 + ldr r1, =0xb10b + str r1, [r0] + str r1, [r0, #4] +#endif + + /* Configure ACCR Register */ + ldr r0, =ACCR @ ACCR + ldr r1, =0x0180b108 + str r1, [r0] + ldr r1, [r0] + + /* Configure MDCNFG Register */ + ldr r0, =MDCNFG @ MDCNFG + ldr r1, =0x403 + str r1, [r0] + ldr r1, [r0] + + /* Perform Resistive Compensation by configuring RCOMP register */ + ldr r1, =RCOMP @ RCOMP + ldr r2, =0x000000ff + str r2, [r1] + ldr r2, [r1] + + /* Configure MDMRS Register for SDCS0 */ + ldr r1, =MDMRS @ MDMRS + ldr r2, =0x60000023 + ldr r3, [r1] + orr r2, r2, r3 + str r2, [r1] + ldr r2, [r1] + + /* Configure MDMRS Register for SDCS1 */ + ldr r1, =MDMRS @ MDMRS + ldr r2, =0xa0000023 + ldr r3, [r1] + orr r2, r2, r3 + str r2, [r1] + ldr r2, [r1] + + /* Configure MDREFR */ + ldr r1, =MDREFR @ MDREFR + ldr r2, =0x00000006 + str r2, [r1] + ldr r2, [r1] + + /* Configure EMPI */ + ldr r1, =EMPI @ EMPI + ldr r2, =0x80000000 + str r2, [r1] + ldr r2, [r1] + + /* Hardware DDR Read-Strobe Delay Calibration */ + ldr r0, =DDR_HCAL @ DDR_HCAL + ldr r1, =0x803ffc07 @ the offset is correct? -SC + str r1, [r0] + wait #5 + ldr r1, [r0] + + /* Here we assume the hardware calibration alwasy be successful. -SC */ + /* Set DMCEN bit in MDCNFG Register */ + ldr r0, =MDCNFG @ MDCNFG + ldr r1, [r0] + orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access + str r1, [r0] + + /* scrub/init SDRAM if enabled/present */ +/* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */ +/* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */ +/* mov r8,r12 /\* save DRAM size (mk: why???) *\/ */ + ldr r8, =0xa0000000 /* base address of SDRAM (CFG_DRAM_BASE) */ + ldr r9, =0x04000000 /* size of memory to scrub (CFG_DRAM_SIZE) */ + mov r0, #0 /* scrub with 0x0000:0000 */ + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov r4, #0 + mov r5, #0 + mov r6, #0 + mov r7, #0 +10: /* fastScrubLoop */ + subs r9, r9, #32 /* 32 bytes/line */ + stmia r8!, {r0-r7} + beq 15f + b 10b + +15: + /* Mask all interrupts */ + mov r1, #0 + mcr p6, 0, r1, c1, c0, 0 @ ICMR + + /* Disable software and data breakpoints */ + mov r0, #0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /* Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ + + /* We are finished with Intel's memory controller initialisation */ + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr + +/* +@******************************************************************************** +@ DDR calibration +@ +@ This function is used to calibrate DQS delay lines. +@ Monahans supports three ways to do it. One is software +@ calibration. Two is hardware calibration. Three is hybrid +@ calibration. +@ +@ TBD +@ -SC +ddr_calibration: + + @ Case 1: Write the correct delay value once + @ Configure DDR_SCAL Register + ldr r0, =DDR_SCAL @ DDR_SCAL +q ldr r1, =0xaf2f2f2f + str r1, [r0] + ldr r1, [r0] +*/ +/* @ Case 2: Software Calibration + @ Write test pattern to memory + ldr r5, =0x0faf0faf @ Data Pattern + ldr r4, =0xa0000000 @ DDR ram + str r5, [r4] + + mov r1, =0x0 @ delay count + mov r6, =0x0 + mov r7, =0x0 +ddr_loop1: + add r1, r1, =0x1 + cmp r1, =0xf + ble end_loop + mov r3, r1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + str r3, [r2] + + ldr r2, [r4] + cmp r2, r5 + bne ddr_loop1 + mov r6, r1 +ddr_loop2: + add r1, r1, =0x1 + cmp r1, =0xf + ble end_loop + mov r3, r1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + str r3, [r2] + + ldr r2, [r4] + cmp r2, r5 + be ddr_loop2 + mov r7, r2 + + add r3, r6, r7 + lsr r3, r3, =0x1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + +end_loop: + + @ Case 3: Hardware Calibratoin + ldr r0, =DDR_HCAL @ DDR_HCAL + ldr r1, =0x803ffc07 @ the offset is correct? -SC + str r1, [r0] + wait #5 + ldr r1, [r0] + mov pc, lr +*/ diff --git a/board/zylonite/u-boot.lds b/board/zylonite/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/zylonite/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/zylonite/zylonite.c b/board/zylonite/zylonite.c new file mode 100644 index 0000000..e618ab9 --- /dev/null +++ b/board/zylonite/zylonite.c @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of Lubbock-Board */ + gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int board_late_init(void) +{ + setenv("stdout", "serial"); + setenv("stderr", "serial"); + return 0; +} + + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 8599a49..a20e584 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -252,6 +252,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (hdr->ih_arch != IH_CPU_MICROBLAZE) #elif defined(__nios2__) if (hdr->ih_arch != IH_CPU_NIOS2) +#elif defined(__blackfin__) + if (hdr->ih_arch != IH_CPU_BLACKFIN) #else # error Unknown CPU type #endif @@ -606,7 +608,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, #endif /* CONFIG_MPC5xxx */ } - kernel = (void (*)(bd_t *, ulong, ulong, ulong, ulong))hdr->ih_ep; + kernel = (void (*)(bd_t *, ulong, ulong, ulong, ulong)) ntohl(hdr->ih_ep); /* * Check if there is an initrd image @@ -621,7 +623,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, /* Copy header so we can blank CRC field for re-calculation */ memmove (&header, (char *)addr, sizeof(image_header_t)); - if (hdr->ih_magic != IH_MAGIC) { + if (ntohl(hdr->ih_magic) != IH_MAGIC) { puts ("Bad Magic Number\n"); SHOW_BOOT_PROGRESS (-10); do_reset (cmdtp, flag, argc, argv); @@ -630,7 +632,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, data = (ulong)&header; len = sizeof(image_header_t); - checksum = hdr->ih_hcrc; + checksum = ntohl(hdr->ih_hcrc); hdr->ih_hcrc = 0; if (crc32 (0, (uchar *)data, len) != checksum) { @@ -644,7 +646,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, print_image_hdr (hdr); data = addr + sizeof(image_header_t); - len = hdr->ih_size; + len = ntohl(hdr->ih_size); if (verify) { ulong csum = 0; @@ -670,7 +672,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, csum = crc32 (0, (uchar *)data, len); #endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ - if (csum != hdr->ih_dcrc) { + if (csum != ntohl(hdr->ih_dcrc)) { puts ("Bad Data CRC\n"); SHOW_BOOT_PROGRESS (-12); do_reset (cmdtp, flag, argc, argv); @@ -819,7 +821,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); #else - ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd); + ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd, initrd_start, initrd_end); /* ft_dump_blob(of_flat_tree); */ #if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) @@ -828,12 +830,16 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, /* * Linux Kernel Parameters: * r3: ptr to OF flat tree, followed by the board info data - * r4: initrd_start or 0 if no initrd - * r5: initrd_end - unused if r4 is 0 - * r6: Start of command line string - * r7: End of command line string + * r4: physical pointer to the kernel itself + * r5: NULL + * r6: NULL + * r7: NULL */ - (*kernel) ((bd_t *)of_flat_tree, initrd_start, initrd_end, cmd_start, cmd_end); + if (getenv("disable_of") != NULL) + (*kernel) ((bd_t *)of_flat_tree, initrd_start, initrd_end, + cmd_start, cmd_end); + else + (*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0); #endif } @@ -902,7 +908,7 @@ do_bootm_netbsd (cmd_tbl_t *cmdtp, int flag, cmdline = ""; } - loader = (void (*)(bd_t *, image_header_t *, char *, char *)) hdr->ih_ep; + loader = (void (*)(bd_t *, image_header_t *, char *, char *)) ntohl(hdr->ih_ep); printf ("## Transferring control to NetBSD stage-2 loader (at address %08lx) ...\n", (ulong)loader); @@ -1364,7 +1370,7 @@ do_bootm_rtems (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], image_header_t *hdr = &header; void (*entry_point)(bd_t *); - entry_point = (void (*)(bd_t *)) hdr->ih_ep; + entry_point = (void (*)(bd_t *)) ntohl(hdr->ih_ep); printf ("## Transferring control to RTEMS (at address %08lx) ...\n", (ulong)entry_point); @@ -1387,7 +1393,7 @@ do_bootm_vxworks (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], image_header_t *hdr = &header; char str[80]; - sprintf(str, "%x", hdr->ih_ep); /* write entry-point into string */ + sprintf(str, "%x", ntohl(hdr->ih_ep)); /* write entry-point into string */ setenv("loadaddr", str); do_bootvx(cmdtp, 0, 0, NULL); } @@ -1400,7 +1406,7 @@ do_bootm_qnxelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], char *local_args[2]; char str[16]; - sprintf(str, "%x", hdr->ih_ep); /* write entry-point into string */ + sprintf(str, "%x", ntohl(hdr->ih_ep)); /* write entry-point into string */ local_args[0] = argv[0]; local_args[1] = str; /* and provide it via the arguments */ do_bootelf(cmdtp, 0, 2, local_args); diff --git a/common/cmd_doc.c b/common/cmd_doc.c index 5e9bea3..37b7325 100644 --- a/common/cmd_doc.c +++ b/common/cmd_doc.c @@ -22,8 +22,9 @@ #if (CONFIG_COMMANDS & CFG_CMD_DOC) #include <linux/mtd/nftl.h> -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> #include <linux/mtd/nand_ids.h> + #include <linux/mtd/doc2000.h> #include <linux/mtd/nftl.h> @@ -249,7 +250,7 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) print_image_hdr (hdr); - cnt = (hdr->ih_size + sizeof(image_header_t)); + cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t)); cnt -= SECTORSIZE; } else { puts ("\n** Bad Magic Number **\n"); diff --git a/common/cmd_fdc.c b/common/cmd_fdc.c index 02dffa3..03f4ce6 100644 --- a/common/cmd_fdc.c +++ b/common/cmd_fdc.c @@ -836,13 +836,13 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } hdr = (image_header_t *)addr; - if (hdr->ih_magic != IH_MAGIC) { + if (ntohl(hdr->ih_magic) != IH_MAGIC) { printf ("Bad Magic Number\n"); return 1; } print_image_hdr(hdr); - imsize= hdr->ih_size+sizeof(image_header_t); + imsize= ntohl(hdr->ih_size)+sizeof(image_header_t); nrofblk=imsize/512; if((imsize%512)>0) nrofblk++; diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c index 34920b1..201c3c1 100644 --- a/common/cmd_jffs2.c +++ b/common/cmd_jffs2.c @@ -91,7 +91,6 @@ #include <command.h> #include <malloc.h> #include <jffs2/jffs2.h> -#include <linux/mtd/nand.h> #include <linux/list.h> #include <linux/ctype.h> @@ -99,11 +98,19 @@ #include <cramfs/cramfs_fs.h> +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#ifdef CFG_NAND_LEGACY +#include <linux/mtd/nand_legacy.h> +#else /* !CFG_NAND_LEGACY */ +#include <linux/mtd/nand.h> +#include <nand.h> +#endif /* !CFG_NAND_LEGACY */ +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ /* enable/disable debugging messages */ -#define DEBUG -#undef DEBUG +#define DEBUG_JFFS +#undef DEBUG_JFFS -#ifdef DEBUG +#ifdef DEBUG_JFFS # define DEBUGF(fmt, args...) printf(fmt ,##args) #else # define DEBUGF(fmt, args...) @@ -123,7 +130,7 @@ /* this flag needs to be set in part_info struct mask_flags * field for read-only partitions */ -#define MTD_WRITEABLE 1 +#define MTD_WRITEABLE_CMD 1 #ifdef CONFIG_JFFS2_CMDLINE /* default values for mtdids and mtdparts variables */ @@ -365,10 +372,9 @@ static int part_validate_nand(struct mtdids *id, struct part_info *part) { #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) /* info for NAND chips */ - extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - struct nand_chip *nand; + nand_info_t *nand; - nand = &nand_dev_desc[id->num]; + nand = &nand_info[id->num]; if ((unsigned long)(part->offset) % nand->erasesize) { printf("%s%d: partition (%s) start offset alignment incorrect\n", @@ -464,7 +470,9 @@ static int part_del(struct mtd_device *dev, struct part_info *part) } } +#ifdef CFG_NAND_LEGACY jffs2_free_cache(part); +#endif list_del(&part->link); free(part); dev->num_parts--; @@ -491,7 +499,9 @@ static void part_delall(struct list_head *head) list_for_each_safe(entry, n, head) { part_tmp = list_entry(entry, struct part_info, link); +#ifdef CFG_NAND_LEGACY jffs2_free_cache(part_tmp); +#endif list_del(entry); free(part_tmp); } @@ -646,7 +656,7 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i /* test for options */ mask_flags = 0; if (strncmp(p, "ro", 2) == 0) { - mask_flags |= MTD_WRITEABLE; + mask_flags |= MTD_WRITEABLE_CMD; p += 2; } @@ -713,6 +723,7 @@ static int device_validate(u8 type, u8 num, u32 *size) if (num < CFG_MAX_FLASH_BANKS) { extern flash_info_t flash_info[]; *size = flash_info[num].size; + return 0; } @@ -724,8 +735,12 @@ static int device_validate(u8 type, u8 num, u32 *size) } else if (type == MTD_DEV_TYPE_NAND) { #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) if (num < CFG_MAX_NAND_DEVICE) { +#ifndef CFG_NAND_LEGACY + *size = nand_info[num].size; +#else extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; *size = nand_dev_desc[num].totlen; +#endif return 0; } @@ -1169,7 +1184,7 @@ static int generate_mtdparts(char *buf, u32 buflen) } /* ro mask flag */ - if (part->mask_flags && MTD_WRITEABLE) { + if (part->mask_flags && MTD_WRITEABLE_CMD) { len = 2; if (len > maxlen) goto cleanup; diff --git a/common/cmd_nand.c b/common/cmd_nand.c index b0c01d1..21adb1b 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -9,6 +9,387 @@ */ #include <common.h> + + +#ifndef CFG_NAND_LEGACY +/* + * + * New NAND support + * + */ +#include <common.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <command.h> +#include <watchdog.h> +#include <malloc.h> +#include <asm/byteorder.h> + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include <status_led.h> +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +#include <jffs2/jffs2.h> +#include <nand.h> + +extern nand_info_t nand_info[]; /* info for NAND chips */ + +static int nand_dump_oob(nand_info_t *nand, ulong off) +{ + return 0; +} + +static int nand_dump(nand_info_t *nand, ulong off) +{ + int i; + u_char *buf, *p; + + buf = malloc(nand->oobblock + nand->oobsize); + if (!buf) { + puts("No memory for page buffer\n"); + return 1; + } + off &= ~(nand->oobblock - 1); + i = nand_read_raw(nand, buf, off, nand->oobblock, nand->oobsize); + if (i < 0) { + printf("Error (%d) reading page %08x\n", i, off); + free(buf); + return 1; + } + printf("Page %08x dump:\n", off); + i = nand->oobblock >> 4; p = buf; + while (i--) { + printf( "\t%02x %02x %02x %02x %02x %02x %02x %02x" + " %02x %02x %02x %02x %02x %02x %02x %02x\n", + p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], + p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]); + p += 16; + } + puts("OOB:\n"); + i = nand->oobsize >> 3; + while (i--) { + printf( "\t%02x %02x %02x %02x %02x %02x %02x %02x\n", + p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); + p += 8; + } + free(buf); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +static void +arg_off_size(int argc, char *argv[], ulong *off, ulong *size, ulong totsize) +{ + *off = 0; + *size = 0; + +#if defined(CONFIG_JFFS2_NAND) && defined(CFG_JFFS_CUSTOM_PART) + if (argc >= 1 && strcmp(argv[0], "partition") == 0) { + int part_num; + struct part_info *part; + const char *partstr; + + if (argc >= 2) + partstr = argv[1]; + else + partstr = getenv("partition"); + + if (partstr) + part_num = (int)simple_strtoul(partstr, NULL, 10); + else + part_num = 0; + + part = jffs2_part_info(part_num); + if (part == NULL) { + printf("\nInvalid partition %d\n", part_num); + return; + } + *size = part->size; + *off = (ulong)part->offset; + } else +#endif + { + if (argc >= 1) + *off = (ulong)simple_strtoul(argv[0], NULL, 16); + else + *off = 0; + + if (argc >= 2) + *size = (ulong)simple_strtoul(argv[1], NULL, 16); + else + *size = totsize - *off; + + } + +} + +int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int i, dev, ret; + ulong addr, off, size; + char *cmd, *s; + nand_info_t *nand; + + /* at least two arguments please */ + if (argc < 2) + goto usage; + + cmd = argv[1]; + + if (strcmp(cmd, "info") == 0) { + + putc('\n'); + for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) { + if (nand_info[i].name) + printf("Device %d: %s, sector size %lu KiB\n", + i, nand_info[i].name, + nand_info[i].erasesize >> 10); + } + return 0; + } + + if (strcmp(cmd, "device") == 0) { + + if (argc < 3) { + if ((nand_curr_device < 0) || + (nand_curr_device >= CFG_MAX_NAND_DEVICE)) + puts("\nno devices available\n"); + else + printf("\nDevice %d: %s\n", nand_curr_device, + nand_info[nand_curr_device].name); + return 0; + } + dev = (int)simple_strtoul(argv[2], NULL, 10); + if (dev < 0 || dev >= CFG_MAX_NAND_DEVICE || !nand_info[dev].name) { + puts("No such device\n"); + return 1; + } + printf("Device %d: %s", dev, nand_info[dev].name); + puts("... is now current device\n"); + nand_curr_device = dev; + return 0; + } + + if (strcmp(cmd, "bad") != 0 && strcmp(cmd, "erase") != 0 && + strncmp(cmd, "dump", 4) != 0 && + strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0) + goto usage; + + /* the following commands operate on the current device */ + if (nand_curr_device < 0 || nand_curr_device >= CFG_MAX_NAND_DEVICE || + !nand_info[nand_curr_device].name) { + puts("\nno devices available\n"); + return 1; + } + nand = &nand_info[nand_curr_device]; + + if (strcmp(cmd, "bad") == 0) { + printf("\nDevice %d bad blocks:\n", nand_curr_device); + for (off = 0; off < nand->size; off += nand->erasesize) + if (nand_block_isbad(nand, off)) + printf(" %08x\n", off); + return 0; + } + + if (strcmp(cmd, "erase") == 0) { + arg_off_size(argc - 2, argv + 2, &off, &size, nand->size); + if (off == 0 && size == 0) + return 1; + + printf("\nNAND erase: device %d offset 0x%x, size 0x%x ", + nand_curr_device, off, size); + ret = nand_erase(nand, off, size); + printf("%s\n", ret ? "ERROR" : "OK"); + + return ret == 0 ? 0 : 1; + } + + if (strncmp(cmd, "dump", 4) == 0) { + if (argc < 3) + goto usage; + + s = strchr(cmd, '.'); + off = (int)simple_strtoul(argv[2], NULL, 16); + + if (s != NULL && strcmp(s, ".oob") == 0) + ret = nand_dump_oob(nand, off); + else + ret = nand_dump(nand, off); + + return ret == 0 ? 1 : 0; + + } + + /* read write */ + if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) { + if (argc < 4) + goto usage; +/* + s = strchr(cmd, '.'); + clean = CLEAN_NONE; + if (s != NULL) { + if (strcmp(s, ".jffs2") == 0 || strcmp(s, ".e") == 0 + || strcmp(s, ".i")) + clean = CLEAN_JFFS2; + } +*/ + addr = (ulong)simple_strtoul(argv[2], NULL, 16); + + arg_off_size(argc - 3, argv + 3, &off, &size, nand->size); + if (off == 0 && size == 0) + return 1; + + i = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */ + printf("\nNAND %s: device %d offset %u, size %u ... ", + i ? "read" : "write", nand_curr_device, off, size); + + if (i) + ret = nand_read(nand, off, &size, (u_char *)addr); + else + ret = nand_write(nand, off, &size, (u_char *)addr); + + printf(" %d bytes %s: %s\n", size, + i ? "read" : "written", ret ? "ERROR" : "OK"); + + return ret == 0 ? 0 : 1; + } +usage: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD(nand, 5, 1, do_nand, + "nand - NAND sub-system\n", + "info - show available NAND devices\n" + "nand device [dev] - show or set current device\n" + "nand read[.jffs2] - addr off size\n" + "nand write[.jffs2] - addr off size - read/write `size' bytes starting\n" + " at offset `off' to/from memory address `addr'\n" + "nand erase [clean] [off size] - erase `size' bytes from\n" + " offset `off' (entire device if not specified)\n" + "nand bad - show bad blocks\n" + "nand dump[.oob] off - dump page\n" + "nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n" + "nand markbad off - mark bad block at offset (UNSAFE)\n" + "nand biterr off - make a bit error at offset (UNSAFE)\n"); + +int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + char *boot_device = NULL; + char *ep; + int dev; + int r; + ulong addr, cnt, offset = 0; + image_header_t *hdr; + nand_info_t *nand; + + switch (argc) { + case 1: + addr = CFG_LOAD_ADDR; + boot_device = getenv("bootdevice"); + break; + case 2: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = getenv("bootdevice"); + break; + case 3: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = argv[2]; + break; + case 4: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = argv[2]; + offset = simple_strtoul(argv[3], NULL, 16); + break; + default: + printf("Usage:\n%s\n", cmdtp->usage); + SHOW_BOOT_PROGRESS(-1); + return 1; + } + + if (!boot_device) { + puts("\n** No boot device **\n"); + SHOW_BOOT_PROGRESS(-1); + return 1; + } + + dev = simple_strtoul(boot_device, &ep, 16); + + if (dev < 0 || dev >= CFG_MAX_NAND_DEVICE || !nand_info[dev].name) { + printf("\n** Device %d not available\n", dev); + SHOW_BOOT_PROGRESS(-1); + return 1; + } + + nand = &nand_info[dev]; + printf("\nLoading from device %d: %s (offset 0x%lx)\n", + dev, nand->name, offset); + + cnt = nand->oobblock; + r = nand_read(nand, offset, &cnt, (u_char *) addr); + if (r) { + printf("** Read error on %d\n", dev); + SHOW_BOOT_PROGRESS(-1); + return 1; + } + + hdr = (image_header_t *) addr; + + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + printf("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic); + SHOW_BOOT_PROGRESS(-1); + return 1; + } + + print_image_hdr(hdr); + + cnt = (ntohl(hdr->ih_size) + sizeof (image_header_t)); + + r = nand_read(nand, offset, &cnt, (u_char *) addr); + if (r) { + printf("** Read error on %d\n", dev); + SHOW_BOOT_PROGRESS(-1); + return 1; + } + + /* Loading ok, update default load address */ + + load_addr = addr; + + /* Check if we should attempt an auto-start */ + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) { + char *local_args[2]; + extern int do_bootm(cmd_tbl_t *, int, int, char *[]); + + local_args[0] = argv[0]; + local_args[1] = NULL; + + printf("Automatic boot of image at addr 0x%08lx ...\n", addr); + + do_bootm(cmdtp, 0, 1, local_args); + return 1; + } + return 0; +} + +U_BOOT_CMD(nboot, 4, 1, do_nandboot, + "nboot - boot from NAND device\n", "loadAddr dev\n"); + + +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ + +#else /* CFG_NAND_LEGACY */ +/* + * + * Legacy NAND support - to be phased out + * + */ #include <command.h> #include <malloc.h> #include <asm/io.h> @@ -22,10 +403,11 @@ #endif #if (CONFIG_COMMANDS & CFG_CMD_NAND) - -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> +#if 0 #include <linux/mtd/nand_ids.h> #include <jffs2/jffs2.h> +#endif #ifdef CONFIG_OMAP1510 void archflashwp(void *archdata, int wp); @@ -33,15 +415,6 @@ void archflashwp(void *archdata, int wp); #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) -/* - * Definition of the out of band configuration structure - */ -struct nand_oob_config { - int ecc_pos[6]; /* position of ECC bytes inside oob */ - int badblock_pos; /* position of bad block flag inside oob -1 = inactive */ - int eccvalid_pos; /* position of ECC valid flag inside oob -1 = inactive */ -} oob_config = { {0}, 0, 0}; - #undef NAND_DEBUG #undef PSYCHO_DEBUG @@ -63,41 +436,28 @@ struct nand_oob_config { #define CONFIG_MTD_NAND_ECC /* enable ECC */ #define CONFIG_MTD_NAND_ECC_JFFS2 -/* bits for nand_rw() `cmd'; or together as needed */ +/* bits for nand_legacy_rw() `cmd'; or together as needed */ #define NANDRW_READ 0x01 #define NANDRW_WRITE 0x00 #define NANDRW_JFFS2 0x02 #define NANDRW_JFFS2_SKIP 0x04 /* - * Function Prototypes + * Imports from nand_legacy.c */ -static void nand_print(struct nand_chip *nand); -int nand_rw (struct nand_chip* nand, int cmd, - size_t start, size_t len, - size_t * retlen, u_char * buf); -int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); -static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len, - size_t * retlen, u_char *buf, u_char *ecc_code); -static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len, - size_t * retlen, const u_char * buf, u_char * ecc_code); -static void nand_print_bad(struct nand_chip *nand); -static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len, - size_t * retlen, u_char * buf); -static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len, - size_t * retlen, const u_char * buf); -static int NanD_WaitReady(struct nand_chip *nand, int ale_wait); -#ifdef CONFIG_MTD_NAND_ECC -static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc); -static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code); -#endif - -struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}}; - -/* Current NAND Device */ -static int curr_device = -1; +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +extern int curr_device; +extern int nand_legacy_erase(struct nand_chip *nand, size_t ofs, + size_t len, int clean); +extern int nand_legacy_rw(struct nand_chip *nand, int cmd, size_t start, + size_t len, size_t *retlen, u_char *buf); +extern void nand_print(struct nand_chip *nand); +extern void nand_print_bad(struct nand_chip *nand); +extern int nand_read_oob(struct nand_chip *nand, size_t ofs, + size_t len, size_t *retlen, u_char *buf); +extern int nand_write_oob(struct nand_chip *nand, size_t ofs, + size_t len, size_t *retlen, const u_char *buf); -/* ------------------------------------------------------------------------- */ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { @@ -174,7 +534,7 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf ("\nNAND erase: device %d offset %ld, size %ld ... ", curr_device, off, size); - ret = nand_erase (nand, off, size, 1); + ret = nand_legacy_erase (nand, off, size, 1); printf("%s\n", ret ? "ERROR" : "OK"); @@ -240,7 +600,7 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) (cmd & NANDRW_READ) ? "read" : "write", curr_device, off, size); - ret = nand_rw(nand_dev_desc + curr_device, cmd, off, size, + ret = nand_legacy_rw(nand_dev_desc + curr_device, cmd, off, size, (size_t *)&total, (u_char*)addr); printf (" %d bytes %s: %s\n", total, @@ -258,7 +618,8 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf ("\nNAND erase: device %d offset %ld, size %ld ... ", curr_device, off, size); - ret = nand_erase (nand_dev_desc + curr_device, off, size, clean); + ret = nand_legacy_erase (nand_dev_desc + curr_device, + off, size, clean); printf("%s\n", ret ? "ERROR" : "OK"); @@ -340,8 +701,8 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR, offset); - if (nand_rw (nand_dev_desc + dev, NANDRW_READ, offset, - SECTORSIZE, NULL, (u_char *)addr)) { + if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, offset, + SECTORSIZE, NULL, (u_char *)addr)) { printf ("** Read error on %d\n", dev); SHOW_BOOT_PROGRESS (-1); return 1; @@ -356,13 +717,14 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t)); cnt -= SECTORSIZE; } else { - printf ("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic); + printf ("\n** Bad Magic Number 0x%x **\n", ntohl(hdr->ih_magic)); SHOW_BOOT_PROGRESS (-1); return 1; } - if (nand_rw (nand_dev_desc + dev, NANDRW_READ, offset + SECTORSIZE, cnt, - NULL, (u_char *)(addr+SECTORSIZE))) { + if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, + offset + SECTORSIZE, cnt, NULL, + (u_char *)(addr+SECTORSIZE))) { printf ("** Read error on %d\n", dev); SHOW_BOOT_PROGRESS (-1); return 1; @@ -394,1505 +756,6 @@ U_BOOT_CMD( "loadAddr dev\n" ); -/* returns 0 if block containing pos is OK: - * valid erase block and - * not marked bad, or no bad mark position is specified - * returns 1 if marked bad or otherwise invalid - */ -int check_block (struct nand_chip *nand, unsigned long pos) -{ - size_t retlen; - uint8_t oob_data; - uint16_t oob_data16[6]; - int page0 = pos & (-nand->erasesize); - int page1 = page0 + nand->oobblock; - int badpos = oob_config.badblock_pos; - - if (pos >= nand->totlen) - return 1; - - if (badpos < 0) - return 0; /* no way to check, assume OK */ - - if (nand->bus16) { - if (nand_read_oob(nand, (page0 + 0), 12, &retlen, (uint8_t *)oob_data16) - || (oob_data16[2] & 0xff00) != 0xff00) - return 1; - if (nand_read_oob(nand, (page1 + 0), 12, &retlen, (uint8_t *)oob_data16) - || (oob_data16[2] & 0xff00) != 0xff00) - return 1; - } else { - /* Note - bad block marker can be on first or second page */ - if (nand_read_oob(nand, page0 + badpos, 1, &retlen, (unsigned char *)&oob_data) - || oob_data != 0xff - || nand_read_oob (nand, page1 + badpos, 1, &retlen, (unsigned char *)&oob_data) - || oob_data != 0xff) - return 1; - } - - return 0; -} - -/* print bad blocks in NAND flash */ -static void nand_print_bad(struct nand_chip* nand) -{ - unsigned long pos; - - for (pos = 0; pos < nand->totlen; pos += nand->erasesize) { - if (check_block(nand, pos)) - printf(" 0x%8.8lx\n", pos); - } - puts("\n"); -} - -/* cmd: 0: NANDRW_WRITE write, fail on bad block - * 1: NANDRW_READ read, fail on bad block - * 2: NANDRW_WRITE | NANDRW_JFFS2 write, skip bad blocks - * 3: NANDRW_READ | NANDRW_JFFS2 read, data all 0xff for bad blocks - * 7: NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP read, skip bad blocks - */ -int nand_rw (struct nand_chip* nand, int cmd, - size_t start, size_t len, - size_t * retlen, u_char * buf) -{ - int ret = 0, n, total = 0; - char eccbuf[6]; - /* eblk (once set) is the start of the erase block containing the - * data being processed. - */ - unsigned long eblk = ~0; /* force mismatch on first pass */ - unsigned long erasesize = nand->erasesize; - - while (len) { - if ((start & (-erasesize)) != eblk) { - /* have crossed into new erase block, deal with - * it if it is sure marked bad. - */ - eblk = start & (-erasesize); /* start of block */ - if (check_block(nand, eblk)) { - if (cmd == (NANDRW_READ | NANDRW_JFFS2)) { - while (len > 0 && - start - eblk < erasesize) { - *(buf++) = 0xff; - ++start; - ++total; - --len; - } - continue; - } else if (cmd == (NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP)) { - start += erasesize; - continue; - } else if (cmd == (NANDRW_WRITE | NANDRW_JFFS2)) { - /* skip bad block */ - start += erasesize; - continue; - } else { - ret = 1; - break; - } - } - } - /* The ECC will not be calculated correctly if - less than 512 is written or read */ - /* Is request at least 512 bytes AND it starts on a proper boundry */ - if((start != ROUND_DOWN(start, 0x200)) || (len < 0x200)) - printf("Warning block writes should be at least 512 bytes and start on a 512 byte boundry\n"); - - if (cmd & NANDRW_READ) { - ret = nand_read_ecc(nand, start, - min(len, eblk + erasesize - start), - (size_t *)&n, (u_char*)buf, (u_char *)eccbuf); - } else { - ret = nand_write_ecc(nand, start, - min(len, eblk + erasesize - start), - (size_t *)&n, (u_char*)buf, (u_char *)eccbuf); - } - - if (ret) - break; - - start += n; - buf += n; - total += n; - len -= n; - } - if (retlen) - *retlen = total; - - return ret; -} - -static void nand_print(struct nand_chip *nand) -{ - if (nand->numchips > 1) { - printf("%s at 0x%lx,\n" - "\t %d chips %s, size %d MB, \n" - "\t total size %ld MB, sector size %ld kB\n", - nand->name, nand->IO_ADDR, nand->numchips, - nand->chips_name, 1 << (nand->chipshift - 20), - nand->totlen >> 20, nand->erasesize >> 10); - } - else { - printf("%s at 0x%lx (", nand->chips_name, nand->IO_ADDR); - print_size(nand->totlen, ", "); - print_size(nand->erasesize, " sector)\n"); - } -} - -/* ------------------------------------------------------------------------- */ - -static int NanD_WaitReady(struct nand_chip *nand, int ale_wait) -{ - /* This is inline, to optimise the common case, where it's ready instantly */ - int ret = 0; - -#ifdef NAND_NO_RB /* in config file, shorter delays currently wrap accesses */ - if(ale_wait) - NAND_WAIT_READY(nand); /* do the worst case 25us wait */ - else - udelay(10); -#else /* has functional r/b signal */ - NAND_WAIT_READY(nand); -#endif - return ret; -} - -/* NanD_Command: Send a flash command to the flash chip */ - -static inline int NanD_Command(struct nand_chip *nand, unsigned char command) -{ - unsigned long nandptr = nand->IO_ADDR; - - /* Assert the CLE (Command Latch Enable) line to the flash chip */ - NAND_CTL_SETCLE(nandptr); - - /* Send the command */ - WRITE_NAND_COMMAND(command, nandptr); - - /* Lower the CLE line */ - NAND_CTL_CLRCLE(nandptr); - -#ifdef NAND_NO_RB - if(command == NAND_CMD_RESET){ - u_char ret_val; - NanD_Command(nand, NAND_CMD_STATUS); - do { - ret_val = READ_NAND(nandptr);/* wait till ready */ - } while((ret_val & 0x40) != 0x40); - } -#endif - return NanD_WaitReady(nand, 0); -} - -/* NanD_Address: Set the current address for the flash chip */ - -static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs) -{ - unsigned long nandptr; - int i; - - nandptr = nand->IO_ADDR; - - /* Assert the ALE (Address Latch Enable) line to the flash chip */ - NAND_CTL_SETALE(nandptr); - - /* Send the address */ - /* Devices with 256-byte page are addressed as: - * Column (bits 0-7), Page (bits 8-15, 16-23, 24-31) - * there is no device on the market with page256 - * and more than 24 bits. - * Devices with 512-byte page are addressed as: - * Column (bits 0-7), Page (bits 9-16, 17-24, 25-31) - * 25-31 is sent only if the chip support it. - * bit 8 changes the read command to be sent - * (NAND_CMD_READ0 or NAND_CMD_READ1). - */ - - if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE) - WRITE_NAND_ADDRESS(ofs, nandptr); - - ofs = ofs >> nand->page_shift; - - if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) { - for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8) { - WRITE_NAND_ADDRESS(ofs, nandptr); - } - } - - /* Lower the ALE line */ - NAND_CTL_CLRALE(nandptr); - - /* Wait for the chip to respond */ - return NanD_WaitReady(nand, 1); -} - -/* NanD_SelectChip: Select a given flash chip within the current floor */ - -static inline int NanD_SelectChip(struct nand_chip *nand, int chip) -{ - /* Wait for it to be ready */ - return NanD_WaitReady(nand, 0); -} - -/* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */ - -static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip) -{ - int mfr, id, i; - - NAND_ENABLE_CE(nand); /* set pin low */ - /* Reset the chip */ - if (NanD_Command(nand, NAND_CMD_RESET)) { -#ifdef NAND_DEBUG - printf("NanD_Command (reset) for %d,%d returned true\n", - floor, chip); -#endif - NAND_DISABLE_CE(nand); /* set pin high */ - return 0; - } - - /* Read the NAND chip ID: 1. Send ReadID command */ - if (NanD_Command(nand, NAND_CMD_READID)) { -#ifdef NAND_DEBUG - printf("NanD_Command (ReadID) for %d,%d returned true\n", - floor, chip); -#endif - NAND_DISABLE_CE(nand); /* set pin high */ - return 0; - } - - /* Read the NAND chip ID: 2. Send address byte zero */ - NanD_Address(nand, ADDR_COLUMN, 0); - - /* Read the manufacturer and device id codes from the device */ - - mfr = READ_NAND(nand->IO_ADDR); - - id = READ_NAND(nand->IO_ADDR); - - NAND_DISABLE_CE(nand); /* set pin high */ - -#ifdef NAND_DEBUG - printf("NanD_Command (ReadID) got %x %x\n", mfr, id); -#endif - if (mfr == 0xff || mfr == 0) { - /* No response - return failure */ - return 0; - } - - /* Check it's the same as the first chip we identified. - * M-Systems say that any given nand_chip device should only - * contain _one_ type of flash part, although that's not a - * hardware restriction. */ - if (nand->mfr) { - if (nand->mfr == mfr && nand->id == id) { - return 1; /* This is another the same the first */ - } else { - printf("Flash chip at floor %d, chip %d is different:\n", - floor, chip); - } - } - - /* Print and store the manufacturer and ID codes. */ - for (i = 0; nand_flash_ids[i].name != NULL; i++) { - if (mfr == nand_flash_ids[i].manufacture_id && - id == nand_flash_ids[i].model_id) { -#ifdef NAND_DEBUG - printf("Flash chip found:\n\t Manufacturer ID: 0x%2.2X, " - "Chip ID: 0x%2.2X (%s)\n", mfr, id, - nand_flash_ids[i].name); -#endif - if (!nand->mfr) { - nand->mfr = mfr; - nand->id = id; - nand->chipshift = - nand_flash_ids[i].chipshift; - nand->page256 = nand_flash_ids[i].page256; - nand->eccsize = 256; - if (nand->page256) { - nand->oobblock = 256; - nand->oobsize = 8; - nand->page_shift = 8; - } else { - nand->oobblock = 512; - nand->oobsize = 16; - nand->page_shift = 9; - } - nand->pageadrlen = nand_flash_ids[i].pageadrlen; - nand->erasesize = nand_flash_ids[i].erasesize; - nand->chips_name = nand_flash_ids[i].name; - nand->bus16 = nand_flash_ids[i].bus16; - return 1; - } - return 0; - } - } - - -#ifdef NAND_DEBUG - /* We haven't fully identified the chip. Print as much as we know. */ - printf("Unknown flash chip found: %2.2X %2.2X\n", - id, mfr); -#endif - - return 0; -} - -/* NanD_ScanChips: Find all NAND chips present in a nand_chip, and identify them */ - -static void NanD_ScanChips(struct nand_chip *nand) -{ - int floor, chip; - int numchips[NAND_MAX_FLOORS]; - int maxchips = NAND_MAX_CHIPS; - int ret = 1; - - nand->numchips = 0; - nand->mfr = 0; - nand->id = 0; - - - /* For each floor, find the number of valid chips it contains */ - for (floor = 0; floor < NAND_MAX_FLOORS; floor++) { - ret = 1; - numchips[floor] = 0; - for (chip = 0; chip < maxchips && ret != 0; chip++) { - - ret = NanD_IdentChip(nand, floor, chip); - if (ret) { - numchips[floor]++; - nand->numchips++; - } - } - } - - /* If there are none at all that we recognise, bail */ - if (!nand->numchips) { -#ifdef NAND_DEBUG - puts ("No NAND flash chips recognised.\n"); -#endif - return; - } - - /* Allocate an array to hold the information for each chip */ - nand->chips = malloc(sizeof(struct Nand) * nand->numchips); - if (!nand->chips) { - puts ("No memory for allocating chip info structures\n"); - return; - } - - ret = 0; - - /* Fill out the chip array with {floor, chipno} for each - * detected chip in the device. */ - for (floor = 0; floor < NAND_MAX_FLOORS; floor++) { - for (chip = 0; chip < numchips[floor]; chip++) { - nand->chips[ret].floor = floor; - nand->chips[ret].chip = chip; - nand->chips[ret].curadr = 0; - nand->chips[ret].curmode = 0x50; - ret++; - } - } - - /* Calculate and print the total size of the device */ - nand->totlen = nand->numchips * (1 << nand->chipshift); - -#ifdef NAND_DEBUG - printf("%d flash chips found. Total nand_chip size: %ld MB\n", - nand->numchips, nand->totlen >> 20); -#endif -} - -/* we need to be fast here, 1 us per read translates to 1 second per meg */ -static void NanD_ReadBuf (struct nand_chip *nand, u_char * data_buf, int cntr) -{ - unsigned long nandptr = nand->IO_ADDR; - - NanD_Command (nand, NAND_CMD_READ0); - - if (nand->bus16) { - u16 val; - - while (cntr >= 16) { - val = READ_NAND (nandptr); - *data_buf++ = val & 0xff; - *data_buf++ = val >> 8; - val = READ_NAND (nandptr); - *data_buf++ = val & 0xff; - *data_buf++ = val >> 8; - val = READ_NAND (nandptr); - *data_buf++ = val & 0xff; - *data_buf++ = val >> 8; - val = READ_NAND (nandptr); - *data_buf++ = val & 0xff; - *data_buf++ = val >> 8; - val = READ_NAND (nandptr); - *data_buf++ = val & 0xff; - *data_buf++ = val >> 8; - val = READ_NAND (nandptr); - *data_buf++ = val & 0xff; - *data_buf++ = val >> 8; - val = READ_NAND (nandptr); - *data_buf++ = val & 0xff; - *data_buf++ = val >> 8; - val = READ_NAND (nandptr); - *data_buf++ = val & 0xff; - *data_buf++ = val >> 8; - cntr -= 16; - } - - while (cntr > 0) { - val = READ_NAND (nandptr); - *data_buf++ = val & 0xff; - *data_buf++ = val >> 8; - cntr -= 2; - } - } else { - while (cntr >= 16) { - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - cntr -= 16; - } - - while (cntr > 0) { - *data_buf++ = READ_NAND (nandptr); - cntr--; - } - } -} - -/* - * NAND read with ECC - */ -static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len, - size_t * retlen, u_char *buf, u_char *ecc_code) -{ - int col, page; - int ecc_status = 0; -#ifdef CONFIG_MTD_NAND_ECC - int j; - int ecc_failed = 0; - u_char *data_poi; - u_char ecc_calc[6]; -#endif - - /* Do not allow reads past end of device */ - if ((start + len) > nand->totlen) { - printf ("%s: Attempt read beyond end of device %x %x %x\n", - __FUNCTION__, (uint) start, (uint) len, (uint) nand->totlen); - *retlen = 0; - return -1; - } - - /* First we calculate the starting page */ - /*page = shr(start, nand->page_shift);*/ - page = start >> nand->page_shift; - - /* Get raw starting column */ - col = start & (nand->oobblock - 1); - - /* Initialize return value */ - *retlen = 0; - - /* Select the NAND device */ - NAND_ENABLE_CE(nand); /* set pin low */ - - /* Loop until all data read */ - while (*retlen < len) { - -#ifdef CONFIG_MTD_NAND_ECC - /* Do we have this page in cache ? */ - if (nand->cache_page == page) - goto readdata; - /* Send the read command */ - NanD_Command(nand, NAND_CMD_READ0); - if (nand->bus16) { - NanD_Address(nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + (col >> 1)); - } else { - NanD_Address(nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + col); - } - - /* Read in a page + oob data */ - NanD_ReadBuf(nand, nand->data_buf, nand->oobblock + nand->oobsize); - - /* copy data into cache, for read out of cache and if ecc fails */ - if (nand->data_cache) { - memcpy (nand->data_cache, nand->data_buf, - nand->oobblock + nand->oobsize); - } - - /* Pick the ECC bytes out of the oob data */ - for (j = 0; j < 6; j++) { - ecc_code[j] = nand->data_buf[(nand->oobblock + oob_config.ecc_pos[j])]; - } - - /* Calculate the ECC and verify it */ - /* If block was not written with ECC, skip ECC */ - if (oob_config.eccvalid_pos != -1 && - (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0x0f) != 0x0f) { - - nand_calculate_ecc (&nand->data_buf[0], &ecc_calc[0]); - switch (nand_correct_data (&nand->data_buf[0], &ecc_code[0], &ecc_calc[0])) { - case -1: - printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page); - ecc_failed++; - break; - case 1: - case 2: /* transfer ECC corrected data to cache */ - if (nand->data_cache) - memcpy (nand->data_cache, nand->data_buf, 256); - break; - } - } - - if (oob_config.eccvalid_pos != -1 && - nand->oobblock == 512 && (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0xf0) != 0xf0) { - - nand_calculate_ecc (&nand->data_buf[256], &ecc_calc[3]); - switch (nand_correct_data (&nand->data_buf[256], &ecc_code[3], &ecc_calc[3])) { - case -1: - printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page); - ecc_failed++; - break; - case 1: - case 2: /* transfer ECC corrected data to cache */ - if (nand->data_cache) - memcpy (&nand->data_cache[256], &nand->data_buf[256], 256); - break; - } - } -readdata: - /* Read the data from ECC data buffer into return buffer */ - data_poi = (nand->data_cache) ? nand->data_cache : nand->data_buf; - data_poi += col; - if ((*retlen + (nand->oobblock - col)) >= len) { - memcpy (buf + *retlen, data_poi, len - *retlen); - *retlen = len; - } else { - memcpy (buf + *retlen, data_poi, nand->oobblock - col); - *retlen += nand->oobblock - col; - } - /* Set cache page address, invalidate, if ecc_failed */ - nand->cache_page = (nand->data_cache && !ecc_failed) ? page : -1; - - ecc_status += ecc_failed; - ecc_failed = 0; - -#else - /* Send the read command */ - NanD_Command(nand, NAND_CMD_READ0); - if (nand->bus16) { - NanD_Address(nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + (col >> 1)); - } else { - NanD_Address(nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + col); - } - - /* Read the data directly into the return buffer */ - if ((*retlen + (nand->oobblock - col)) >= len) { - NanD_ReadBuf(nand, buf + *retlen, len - *retlen); - *retlen = len; - /* We're done */ - continue; - } else { - NanD_ReadBuf(nand, buf + *retlen, nand->oobblock - col); - *retlen += nand->oobblock - col; - } -#endif - /* For subsequent reads align to page boundary. */ - col = 0; - /* Increment page address */ - page++; - } - - /* De-select the NAND device */ - NAND_DISABLE_CE(nand); /* set pin high */ - - /* - * Return success, if no ECC failures, else -EIO - * fs driver will take care of that, because - * retlen == desired len and result == -EIO - */ - return ecc_status ? -1 : 0; -} - -/* - * Nand_page_program function is used for write and writev ! - */ -static int nand_write_page (struct nand_chip *nand, - int page, int col, int last, u_char * ecc_code) -{ - - int i; - unsigned long nandptr = nand->IO_ADDR; - -#ifdef CONFIG_MTD_NAND_ECC -#ifdef CONFIG_MTD_NAND_VERIFY_WRITE - int ecc_bytes = (nand->oobblock == 512) ? 6 : 3; -#endif -#endif - /* pad oob area */ - for (i = nand->oobblock; i < nand->oobblock + nand->oobsize; i++) - nand->data_buf[i] = 0xff; - -#ifdef CONFIG_MTD_NAND_ECC - /* Zero out the ECC array */ - for (i = 0; i < 6; i++) - ecc_code[i] = 0x00; - - /* Read back previous written data, if col > 0 */ - if (col) { - NanD_Command (nand, NAND_CMD_READ0); - if (nand->bus16) { - NanD_Address (nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + (col >> 1)); - } else { - NanD_Address (nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + col); - } - - if (nand->bus16) { - u16 val; - - for (i = 0; i < col; i += 2) { - val = READ_NAND (nandptr); - nand->data_buf[i] = val & 0xff; - nand->data_buf[i + 1] = val >> 8; - } - } else { - for (i = 0; i < col; i++) - nand->data_buf[i] = READ_NAND (nandptr); - } - } - - /* Calculate and write the ECC if we have enough data */ - if ((col < nand->eccsize) && (last >= nand->eccsize)) { - nand_calculate_ecc (&nand->data_buf[0], &(ecc_code[0])); - for (i = 0; i < 3; i++) { - nand->data_buf[(nand->oobblock + - oob_config.ecc_pos[i])] = ecc_code[i]; - } - if (oob_config.eccvalid_pos != -1) { - nand->data_buf[nand->oobblock + - oob_config.eccvalid_pos] = 0xf0; - } - } - - /* Calculate and write the second ECC if we have enough data */ - if ((nand->oobblock == 512) && (last == nand->oobblock)) { - nand_calculate_ecc (&nand->data_buf[256], &(ecc_code[3])); - for (i = 3; i < 6; i++) { - nand->data_buf[(nand->oobblock + - oob_config.ecc_pos[i])] = ecc_code[i]; - } - if (oob_config.eccvalid_pos != -1) { - nand->data_buf[nand->oobblock + - oob_config.eccvalid_pos] &= 0x0f; - } - } -#endif - /* Prepad for partial page programming !!! */ - for (i = 0; i < col; i++) - nand->data_buf[i] = 0xff; - - /* Postpad for partial page programming !!! oob is already padded */ - for (i = last; i < nand->oobblock; i++) - nand->data_buf[i] = 0xff; - - /* Send command to begin auto page programming */ - NanD_Command (nand, NAND_CMD_READ0); - NanD_Command (nand, NAND_CMD_SEQIN); - if (nand->bus16) { - NanD_Address (nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + (col >> 1)); - } else { - NanD_Address (nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + col); - } - - /* Write out complete page of data */ - if (nand->bus16) { - for (i = 0; i < (nand->oobblock + nand->oobsize); i += 2) { - WRITE_NAND (nand->data_buf[i] + - (nand->data_buf[i + 1] << 8), - nand->IO_ADDR); - } - } else { - for (i = 0; i < (nand->oobblock + nand->oobsize); i++) - WRITE_NAND (nand->data_buf[i], nand->IO_ADDR); - } - - /* Send command to actually program the data */ - NanD_Command (nand, NAND_CMD_PAGEPROG); - NanD_Command (nand, NAND_CMD_STATUS); -#ifdef NAND_NO_RB - { - u_char ret_val; - - do { - ret_val = READ_NAND (nandptr); /* wait till ready */ - } while ((ret_val & 0x40) != 0x40); - } -#endif - /* See if device thinks it succeeded */ - if (READ_NAND (nand->IO_ADDR) & 0x01) { - printf ("%s: Failed write, page 0x%08x, ", __FUNCTION__, - page); - return -1; - } -#ifdef CONFIG_MTD_NAND_VERIFY_WRITE - /* - * The NAND device assumes that it is always writing to - * a cleanly erased page. Hence, it performs its internal - * write verification only on bits that transitioned from - * 1 to 0. The device does NOT verify the whole page on a - * byte by byte basis. It is possible that the page was - * not completely erased or the page is becoming unusable - * due to wear. The read with ECC would catch the error - * later when the ECC page check fails, but we would rather - * catch it early in the page write stage. Better to write - * no data than invalid data. - */ - - /* Send command to read back the page */ - if (col < nand->eccsize) - NanD_Command (nand, NAND_CMD_READ0); - else - NanD_Command (nand, NAND_CMD_READ1); - if (nand->bus16) { - NanD_Address (nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + (col >> 1)); - } else { - NanD_Address (nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + col); - } - - /* Loop through and verify the data */ - if (nand->bus16) { - for (i = col; i < last; i = +2) { - if ((nand->data_buf[i] + - (nand->data_buf[i + 1] << 8)) != READ_NAND (nand->IO_ADDR)) { - printf ("%s: Failed write verify, page 0x%08x ", - __FUNCTION__, page); - return -1; - } - } - } else { - for (i = col; i < last; i++) { - if (nand->data_buf[i] != READ_NAND (nand->IO_ADDR)) { - printf ("%s: Failed write verify, page 0x%08x ", - __FUNCTION__, page); - return -1; - } - } - } - -#ifdef CONFIG_MTD_NAND_ECC - /* - * We also want to check that the ECC bytes wrote - * correctly for the same reasons stated above. - */ - NanD_Command (nand, NAND_CMD_READOOB); - if (nand->bus16) { - NanD_Address (nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + (col >> 1)); - } else { - NanD_Address (nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + col); - } - if (nand->bus16) { - for (i = 0; i < nand->oobsize; i += 2) { - u16 val; - - val = READ_NAND (nand->IO_ADDR); - nand->data_buf[i] = val & 0xff; - nand->data_buf[i + 1] = val >> 8; - } - } else { - for (i = 0; i < nand->oobsize; i++) { - nand->data_buf[i] = READ_NAND (nand->IO_ADDR); - } - } - for (i = 0; i < ecc_bytes; i++) { - if ((nand->data_buf[(oob_config.ecc_pos[i])] != ecc_code[i]) && ecc_code[i]) { - printf ("%s: Failed ECC write " - "verify, page 0x%08x, " - "%6i bytes were succesful\n", - __FUNCTION__, page, i); - return -1; - } - } -#endif /* CONFIG_MTD_NAND_ECC */ -#endif /* CONFIG_MTD_NAND_VERIFY_WRITE */ - return 0; -} - -static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len, - size_t * retlen, const u_char * buf, u_char * ecc_code) -{ - int i, page, col, cnt, ret = 0; - - /* Do not allow write past end of device */ - if ((to + len) > nand->totlen) { - printf ("%s: Attempt to write past end of page\n", __FUNCTION__); - return -1; - } - - /* Shift to get page */ - page = ((int) to) >> nand->page_shift; - - /* Get the starting column */ - col = to & (nand->oobblock - 1); - - /* Initialize return length value */ - *retlen = 0; - - /* Select the NAND device */ -#ifdef CONFIG_OMAP1510 - archflashwp(0,0); -#endif -#ifdef CFG_NAND_WP - NAND_WP_OFF(); -#endif - - NAND_ENABLE_CE(nand); /* set pin low */ - - /* Check the WP bit */ - NanD_Command(nand, NAND_CMD_STATUS); - if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { - printf ("%s: Device is write protected!!!\n", __FUNCTION__); - ret = -1; - goto out; - } - - /* Loop until all data is written */ - while (*retlen < len) { - /* Invalidate cache, if we write to this page */ - if (nand->cache_page == page) - nand->cache_page = -1; - - /* Write data into buffer */ - if ((col + len) >= nand->oobblock) { - for (i = col, cnt = 0; i < nand->oobblock; i++, cnt++) { - nand->data_buf[i] = buf[(*retlen + cnt)]; - } - } else { - for (i = col, cnt = 0; cnt < (len - *retlen); i++, cnt++) { - nand->data_buf[i] = buf[(*retlen + cnt)]; - } - } - /* We use the same function for write and writev !) */ - ret = nand_write_page (nand, page, col, i, ecc_code); - if (ret) - goto out; - - /* Next data start at page boundary */ - col = 0; - - /* Update written bytes count */ - *retlen += cnt; - - /* Increment page address */ - page++; - } - - /* Return happy */ - *retlen = len; - -out: - /* De-select the NAND device */ - NAND_DISABLE_CE(nand); /* set pin high */ -#ifdef CONFIG_OMAP1510 - archflashwp(0,1); -#endif -#ifdef CFG_NAND_WP - NAND_WP_ON(); -#endif - - return ret; -} - -/* read from the 16 bytes of oob data that correspond to a 512 byte - * page or 2 256-byte pages. - */ -static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len, - size_t * retlen, u_char * buf) -{ - int len256 = 0; - struct Nand *mychip; - int ret = 0; - - mychip = &nand->chips[ofs >> nand->chipshift]; - - /* update address for 2M x 8bit devices. OOB starts on the second */ - /* page to maintain compatibility with nand_read_ecc. */ - if (nand->page256) { - if (!(ofs & 0x8)) - ofs += 0x100; - else - ofs -= 0x8; - } - - NAND_ENABLE_CE(nand); /* set pin low */ - NanD_Command(nand, NAND_CMD_READOOB); - if (nand->bus16) { - NanD_Address(nand, ADDR_COLUMN_PAGE, - ((ofs >> nand->page_shift) << nand->page_shift) + - ((ofs & (nand->oobblock - 1)) >> 1)); - } else { - NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); - } - - /* treat crossing 8-byte OOB data for 2M x 8bit devices */ - /* Note: datasheet says it should automaticaly wrap to the */ - /* next OOB block, but it didn't work here. mf. */ - if (nand->page256 && ofs + len > (ofs | 0x7) + 1) { - len256 = (ofs | 0x7) + 1 - ofs; - NanD_ReadBuf(nand, buf, len256); - - NanD_Command(nand, NAND_CMD_READOOB); - NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff)); - } - - NanD_ReadBuf(nand, &buf[len256], len - len256); - - *retlen = len; - /* Reading the full OOB data drops us off of the end of the page, - * causing the flash device to go into busy mode, so we need - * to wait until ready 11.4.1 and Toshiba TC58256FT nands */ - - ret = NanD_WaitReady(nand, 1); - NAND_DISABLE_CE(nand); /* set pin high */ - - return ret; - -} - -/* write to the 16 bytes of oob data that correspond to a 512 byte - * page or 2 256-byte pages. - */ -static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len, - size_t * retlen, const u_char * buf) -{ - int len256 = 0; - int i; - unsigned long nandptr = nand->IO_ADDR; - -#ifdef PSYCHO_DEBUG - printf("nand_write_oob(%lx, %d): %2.2X %2.2X %2.2X %2.2X ... %2.2X %2.2X .. %2.2X %2.2X\n", - (long)ofs, len, buf[0], buf[1], buf[2], buf[3], - buf[8], buf[9], buf[14],buf[15]); -#endif - - NAND_ENABLE_CE(nand); /* set pin low to enable chip */ - - /* Reset the chip */ - NanD_Command(nand, NAND_CMD_RESET); - - /* issue the Read2 command to set the pointer to the Spare Data Area. */ - NanD_Command(nand, NAND_CMD_READOOB); - if (nand->bus16) { - NanD_Address(nand, ADDR_COLUMN_PAGE, - ((ofs >> nand->page_shift) << nand->page_shift) + - ((ofs & (nand->oobblock - 1)) >> 1)); - } else { - NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); - } - - /* update address for 2M x 8bit devices. OOB starts on the second */ - /* page to maintain compatibility with nand_read_ecc. */ - if (nand->page256) { - if (!(ofs & 0x8)) - ofs += 0x100; - else - ofs -= 0x8; - } - - /* issue the Serial Data In command to initial the Page Program process */ - NanD_Command(nand, NAND_CMD_SEQIN); - if (nand->bus16) { - NanD_Address(nand, ADDR_COLUMN_PAGE, - ((ofs >> nand->page_shift) << nand->page_shift) + - ((ofs & (nand->oobblock - 1)) >> 1)); - } else { - NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); - } - - /* treat crossing 8-byte OOB data for 2M x 8bit devices */ - /* Note: datasheet says it should automaticaly wrap to the */ - /* next OOB block, but it didn't work here. mf. */ - if (nand->page256 && ofs + len > (ofs | 0x7) + 1) { - len256 = (ofs | 0x7) + 1 - ofs; - for (i = 0; i < len256; i++) - WRITE_NAND(buf[i], nandptr); - - NanD_Command(nand, NAND_CMD_PAGEPROG); - NanD_Command(nand, NAND_CMD_STATUS); -#ifdef NAND_NO_RB - { u_char ret_val; - do { - ret_val = READ_NAND(nandptr); /* wait till ready */ - } while ((ret_val & 0x40) != 0x40); - } -#endif - if (READ_NAND(nandptr) & 1) { - puts ("Error programming oob data\n"); - /* There was an error */ - NAND_DISABLE_CE(nand); /* set pin high */ - *retlen = 0; - return -1; - } - NanD_Command(nand, NAND_CMD_SEQIN); - NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff)); - } - - if (nand->bus16) { - for (i = len256; i < len; i += 2) { - WRITE_NAND(buf[i] + (buf[i+1] << 8), nandptr); - } - } else { - for (i = len256; i < len; i++) - WRITE_NAND(buf[i], nandptr); - } - - NanD_Command(nand, NAND_CMD_PAGEPROG); - NanD_Command(nand, NAND_CMD_STATUS); -#ifdef NAND_NO_RB - { u_char ret_val; - do { - ret_val = READ_NAND(nandptr); /* wait till ready */ - } while ((ret_val & 0x40) != 0x40); - } -#endif - if (READ_NAND(nandptr) & 1) { - puts ("Error programming oob data\n"); - /* There was an error */ - NAND_DISABLE_CE(nand); /* set pin high */ - *retlen = 0; - return -1; - } - - NAND_DISABLE_CE(nand); /* set pin high */ - *retlen = len; - return 0; - -} - -int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean) -{ - /* This is defined as a structure so it will work on any system - * using native endian jffs2 (the default). - */ - static struct jffs2_unknown_node clean_marker = { - JFFS2_MAGIC_BITMASK, - JFFS2_NODETYPE_CLEANMARKER, - 8 /* 8 bytes in this node */ - }; - unsigned long nandptr; - struct Nand *mychip; - int ret = 0; - - if (ofs & (nand->erasesize-1) || len & (nand->erasesize-1)) { - printf ("Offset and size must be sector aligned, erasesize = %d\n", - (int) nand->erasesize); - return -1; - } - - nandptr = nand->IO_ADDR; - - /* Select the NAND device */ -#ifdef CONFIG_OMAP1510 - archflashwp(0,0); -#endif -#ifdef CFG_NAND_WP - NAND_WP_OFF(); -#endif - NAND_ENABLE_CE(nand); /* set pin low */ - - /* Check the WP bit */ - NanD_Command(nand, NAND_CMD_STATUS); - if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { - printf ("nand_write_ecc: Device is write protected!!!\n"); - ret = -1; - goto out; - } - - /* Check the WP bit */ - NanD_Command(nand, NAND_CMD_STATUS); - if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { - printf ("%s: Device is write protected!!!\n", __FUNCTION__); - ret = -1; - goto out; - } - - /* FIXME: Do nand in the background. Use timers or schedule_task() */ - while(len) { - /*mychip = &nand->chips[shr(ofs, nand->chipshift)];*/ - mychip = &nand->chips[ofs >> nand->chipshift]; - - /* always check for bad block first, genuine bad blocks - * should _never_ be erased. - */ - if (ALLOW_ERASE_BAD_DEBUG || !check_block(nand, ofs)) { - /* Select the NAND device */ - NAND_ENABLE_CE(nand); /* set pin low */ - - NanD_Command(nand, NAND_CMD_ERASE1); - NanD_Address(nand, ADDR_PAGE, ofs); - NanD_Command(nand, NAND_CMD_ERASE2); - - NanD_Command(nand, NAND_CMD_STATUS); - -#ifdef NAND_NO_RB - { u_char ret_val; - do { - ret_val = READ_NAND(nandptr); /* wait till ready */ - } while ((ret_val & 0x40) != 0x40); - } -#endif - if (READ_NAND(nandptr) & 1) { - printf ("%s: Error erasing at 0x%lx\n", - __FUNCTION__, (long)ofs); - /* There was an error */ - ret = -1; - goto out; - } - if (clean) { - int n; /* return value not used */ - int p, l; - - /* clean marker position and size depend - * on the page size, since 256 byte pages - * only have 8 bytes of oob data - */ - if (nand->page256) { - p = NAND_JFFS2_OOB8_FSDAPOS; - l = NAND_JFFS2_OOB8_FSDALEN; - } else { - p = NAND_JFFS2_OOB16_FSDAPOS; - l = NAND_JFFS2_OOB16_FSDALEN; - } - - ret = nand_write_oob(nand, ofs + p, l, (size_t *)&n, - (u_char *)&clean_marker); - /* quit here if write failed */ - if (ret) - goto out; - } - } - ofs += nand->erasesize; - len -= nand->erasesize; - } - -out: - /* De-select the NAND device */ - NAND_DISABLE_CE(nand); /* set pin high */ -#ifdef CONFIG_OMAP1510 - archflashwp(0,1); -#endif -#ifdef CFG_NAND_WP - NAND_WP_ON(); -#endif - - return ret; -} - -static inline int nandcheck(unsigned long potential, unsigned long physadr) -{ - return 0; -} - -unsigned long nand_probe(unsigned long physadr) -{ - struct nand_chip *nand = NULL; - int i = 0, ChipID = 1; - -#ifdef CONFIG_MTD_NAND_ECC_JFFS2 - oob_config.ecc_pos[0] = NAND_JFFS2_OOB_ECCPOS0; - oob_config.ecc_pos[1] = NAND_JFFS2_OOB_ECCPOS1; - oob_config.ecc_pos[2] = NAND_JFFS2_OOB_ECCPOS2; - oob_config.ecc_pos[3] = NAND_JFFS2_OOB_ECCPOS3; - oob_config.ecc_pos[4] = NAND_JFFS2_OOB_ECCPOS4; - oob_config.ecc_pos[5] = NAND_JFFS2_OOB_ECCPOS5; - oob_config.eccvalid_pos = 4; -#else - oob_config.ecc_pos[0] = NAND_NOOB_ECCPOS0; - oob_config.ecc_pos[1] = NAND_NOOB_ECCPOS1; - oob_config.ecc_pos[2] = NAND_NOOB_ECCPOS2; - oob_config.ecc_pos[3] = NAND_NOOB_ECCPOS3; - oob_config.ecc_pos[4] = NAND_NOOB_ECCPOS4; - oob_config.ecc_pos[5] = NAND_NOOB_ECCPOS5; - oob_config.eccvalid_pos = NAND_NOOB_ECCVPOS; -#endif - oob_config.badblock_pos = 5; - - for (i=0; i<CFG_MAX_NAND_DEVICE; i++) { - if (nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN) { - nand = &nand_dev_desc[i]; - break; - } - } - if (!nand) - return (0); - - memset((char *)nand, 0, sizeof(struct nand_chip)); - - nand->IO_ADDR = physadr; - nand->cache_page = -1; /* init the cache page */ - NanD_ScanChips(nand); - - if (nand->totlen == 0) { - /* no chips found, clean up and quit */ - memset((char *)nand, 0, sizeof(struct nand_chip)); - nand->ChipID = NAND_ChipID_UNKNOWN; - return (0); - } - - nand->ChipID = ChipID; - if (curr_device == -1) - curr_device = i; - - nand->data_buf = malloc (nand->oobblock + nand->oobsize); - if (!nand->data_buf) { - puts ("Cannot allocate memory for data structures.\n"); - return (0); - } - - return (nand->totlen); -} - -#ifdef CONFIG_MTD_NAND_ECC -/* - * Pre-calculated 256-way 1 byte column parity - */ -static const u_char nand_ecc_precalc_table[] = { - 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, - 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00, - 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, - 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, - 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, - 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, - 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, - 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, - 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, - 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, - 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, - 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, - 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, - 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, - 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, - 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, - 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, - 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, - 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, - 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, - 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, - 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, - 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, - 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, - 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, - 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, - 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, - 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, - 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, - 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, - 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, - 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00 -}; - - -/* - * Creates non-inverted ECC code from line parity - */ -static void nand_trans_result(u_char reg2, u_char reg3, - u_char *ecc_code) -{ - u_char a, b, i, tmp1, tmp2; - - /* Initialize variables */ - a = b = 0x80; - tmp1 = tmp2 = 0; - - /* Calculate first ECC byte */ - for (i = 0; i < 4; i++) { - if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */ - tmp1 |= b; - b >>= 1; - if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */ - tmp1 |= b; - b >>= 1; - a >>= 1; - } - - /* Calculate second ECC byte */ - b = 0x80; - for (i = 0; i < 4; i++) { - if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */ - tmp2 |= b; - b >>= 1; - if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */ - tmp2 |= b; - b >>= 1; - a >>= 1; - } - - /* Store two of the ECC bytes */ - ecc_code[0] = tmp1; - ecc_code[1] = tmp2; -} - -/* - * Calculate 3 byte ECC code for 256 byte block - */ -static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code) -{ - u_char idx, reg1, reg3; - int j; - - /* Initialize variables */ - reg1 = reg3 = 0; - ecc_code[0] = ecc_code[1] = ecc_code[2] = 0; - - /* Build up column parity */ - for(j = 0; j < 256; j++) { - - /* Get CP0 - CP5 from table */ - idx = nand_ecc_precalc_table[dat[j]]; - reg1 ^= idx; - - /* All bit XOR = 1 ? */ - if (idx & 0x40) { - reg3 ^= (u_char) j; - } - } - - /* Create non-inverted ECC code from line parity */ - nand_trans_result((reg1 & 0x40) ? ~reg3 : reg3, reg3, ecc_code); - - /* Calculate final ECC code */ - ecc_code[0] = ~ecc_code[0]; - ecc_code[1] = ~ecc_code[1]; - ecc_code[2] = ((~reg1) << 2) | 0x03; -} - -/* - * Detect and correct a 1 bit error for 256 byte block - */ -static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc) -{ - u_char a, b, c, d1, d2, d3, add, bit, i; - - /* Do error detection */ - d1 = calc_ecc[0] ^ read_ecc[0]; - d2 = calc_ecc[1] ^ read_ecc[1]; - d3 = calc_ecc[2] ^ read_ecc[2]; - - if ((d1 | d2 | d3) == 0) { - /* No errors */ - return 0; - } else { - a = (d1 ^ (d1 >> 1)) & 0x55; - b = (d2 ^ (d2 >> 1)) & 0x55; - c = (d3 ^ (d3 >> 1)) & 0x54; - - /* Found and will correct single bit error in the data */ - if ((a == 0x55) && (b == 0x55) && (c == 0x54)) { - c = 0x80; - add = 0; - a = 0x80; - for (i=0; i<4; i++) { - if (d1 & c) - add |= a; - c >>= 2; - a >>= 1; - } - c = 0x80; - for (i=0; i<4; i++) { - if (d2 & c) - add |= a; - c >>= 2; - a >>= 1; - } - bit = 0; - b = 0x04; - c = 0x80; - for (i=0; i<3; i++) { - if (d3 & c) - bit |= b; - c >>= 2; - b >>= 1; - } - b = 0x01; - a = dat[add]; - a ^= (b << bit); - dat[add] = a; - return 1; - } - else { - i = 0; - while (d1) { - if (d1 & 0x01) - ++i; - d1 >>= 1; - } - while (d2) { - if (d2 & 0x01) - ++i; - d2 >>= 1; - } - while (d3) { - if (d3 & 0x01) - ++i; - d3 >>= 1; - } - if (i == 1) { - /* ECC Code Error Correction */ - read_ecc[0] = calc_ecc[0]; - read_ecc[1] = calc_ecc[1]; - read_ecc[2] = calc_ecc[2]; - return 2; - } - else { - /* Uncorrectable Error */ - return -1; - } - } - } - - /* Should never happen */ - return -1; -} - -#endif - -#ifdef CONFIG_JFFS2_NAND - -int read_jffs2_nand(size_t start, size_t len, - size_t * retlen, u_char * buf, int nanddev) -{ - return nand_rw(nand_dev_desc + nanddev, NANDRW_READ | NANDRW_JFFS2, - start, len, retlen, buf); -} - -#endif /* CONFIG_JFFS2_NAND */ - - #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ + +#endif /* CFG_NAND_LEGACY */ diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 1babffe..ecf1db4 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -532,7 +532,9 @@ int getenv_r (char *name, char *buf, unsigned len) #if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || \ ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == \ - (CFG_CMD_ENV|CFG_CMD_FLASH)) + (CFG_CMD_ENV|CFG_CMD_FLASH)) || \ + ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_NAND)) == \ + (CFG_CMD_ENV|CFG_CMD_NAND)) int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { extern char * env_name_spec; @@ -588,7 +590,9 @@ U_BOOT_CMD( #if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || \ ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == \ - (CFG_CMD_ENV|CFG_CMD_FLASH)) + (CFG_CMD_ENV|CFG_CMD_FLASH)) || \ + ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_NAND)) == \ + (CFG_CMD_ENV|CFG_CMD_NAND)) U_BOOT_CMD( saveenv, 1, 0, do_saveenv, "saveenv - save environment variables to persistent storage\n", diff --git a/common/command.c b/common/command.c index 2b4c554..e917975 100644 --- a/common/command.c +++ b/common/command.c @@ -42,6 +42,8 @@ U_BOOT_CMD( NULL ); +#if (CONFIG_COMMANDS & CFG_CMD_ECHO) + int do_echo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { @@ -74,6 +76,8 @@ U_BOOT_CMD( " - echo args to console; \\c suppresses newline\n" ); +#endif /* CFG_CMD_ECHO */ + #ifdef CFG_HUSH_PARSER int diff --git a/common/env_nand.c b/common/env_nand.c index 60aba1e..dd27f7b 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -36,7 +36,7 @@ #include <command.h> #include <environment.h> #include <linux/stddef.h> -#include <linux/mtd/nand.h> +#include <nand.h> #if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_NAND)) == (CFG_CMD_ENV|CFG_CMD_NAND)) #define CMD_SAVEENV @@ -55,16 +55,12 @@ #error CONFIG_INFERNO not supported yet #endif -/* references to names in cmd_nand.c */ -#define NANDRW_READ 0x01 -#define NANDRW_WRITE 0x00 -#define NANDRW_JFFS2 0x02 -extern struct nand_chip nand_dev_desc[]; -int nand_rw (struct nand_chip* nand, int cmd, +int nand_legacy_rw (struct nand_chip* nand, int cmd, size_t start, size_t len, size_t * retlen, u_char * buf); -int nand_erase(struct nand_chip* nand, size_t ofs, - size_t len, int clean); + +/* info for NAND chips, defined in drivers/nand/nand.c */ +extern nand_info_t nand_info[]; /* references to names in env_common.c */ extern uchar default_environment[]; @@ -110,34 +106,43 @@ int env_init(void) } #ifdef CMD_SAVEENV +/* + * The legacy NAND code saved the environment in the first NAND device i.e., + * nand_dev_desc + 0. This is also the behaviour using the new NAND code. + */ int saveenv(void) { - int total, ret = 0; - puts ("Erasing Nand..."); - if (nand_erase(nand_dev_desc + 0, CFG_ENV_OFFSET, CFG_ENV_SIZE, 0)) - return 1; + ulong total; + int ret = 0; + + puts ("Erasing Nand..."); + if (nand_erase(&nand_info[0], CFG_ENV_OFFSET, CFG_ENV_SIZE)) + return 1; puts ("Writing to Nand... "); - ret = nand_rw(nand_dev_desc + 0, - NANDRW_WRITE | NANDRW_JFFS2, CFG_ENV_OFFSET, CFG_ENV_SIZE, - &total, (u_char*)env_ptr); - if (ret || total != CFG_ENV_SIZE) + total = CFG_ENV_SIZE; + ret = nand_write(&nand_info[0], CFG_ENV_OFFSET, &total, (u_char*)env_ptr); + if (ret || total != CFG_ENV_SIZE) return 1; - puts ("done\n"); - return ret; + puts ("done\n"); + return ret; } #endif /* CMD_SAVEENV */ +/* + * The legacy NAND code saved the environment in the first NAND device i.e., + * nand_dev_desc + 0. This is also the behaviour using the new NAND code. + */ void env_relocate_spec (void) { #if !defined(ENV_IS_EMBEDDED) - int ret, total; + ulong total; + int ret; - ret = nand_rw(nand_dev_desc + 0, - NANDRW_READ | NANDRW_JFFS2, CFG_ENV_OFFSET, CFG_ENV_SIZE, - &total, (u_char*)env_ptr); + total = CFG_ENV_SIZE; + ret = nand_read(&nand_info[0], CFG_ENV_OFFSET, &total, (u_char*)env_ptr); if (ret || total != CFG_ENV_SIZE) return use_default(); diff --git a/common/ft_build.c b/common/ft_build.c index 65a274f..9e9c906 100644 --- a/common/ft_build.c +++ b/common/ft_build.c @@ -163,7 +163,7 @@ void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size) ((u64 *) cxt->pres)[0] = cpu_to_be64(physaddr); /* phys = 0, size = 0, terminate */ ((u64 *) cxt->pres)[1] = cpu_to_be64(size); - cxt->pres += 18; /* advance */ + cxt->pres += 16; /* advance */ ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */ ((u64 *) cxt->pres)[1] = 0; @@ -529,6 +529,7 @@ extern uchar(*env_get_char) (int); #define BDM(x) { .name = #x, .offset = offsetof(bd_t, bi_ ##x ) } +#ifdef CONFIG_OF_HAS_BD_T static const struct { const char *name; int offset; @@ -574,19 +575,24 @@ static const struct { #endif BDM(baudrate), }; +#endif -void ft_setup(void *blob, int size, bd_t * bd) +void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end) { - DECLARE_GLOBAL_DATA_PTR; - u8 *end; u32 *p; int len; struct ft_cxt cxt; - int i, k, nxt; - static char tmpenv[256]; - char *s, *lval, *rval; ulong clock; - uint32_t v; +#if defined(CONFIG_OF_HAS_UBOOT_ENV) + int k, nxt; +#endif +#if defined(CONFIG_OF_HAS_BD_T) + u8 *end; +#endif +#if defined(CONFIG_OF_HAS_UBOOT_ENV) || defined(CONFIG_OF_HAS_BD_T) + int i; + static char tmpenv[256]; +#endif /* disable OF tree; booting old kernel */ if (getenv("disable_of") != NULL) { @@ -596,7 +602,8 @@ void ft_setup(void *blob, int size, bd_t * bd) ft_begin(&cxt, blob, size); - /* fs_add_rsvmap not used */ + if (initrd_start && initrd_end) + ft_add_rsvmap(&cxt, initrd_start, initrd_end - initrd_start + 1); ft_begin_tree(&cxt); @@ -610,9 +617,12 @@ void ft_setup(void *blob, int size, bd_t * bd) /* back into root */ ft_backtrack_node(&cxt); +#ifdef CONFIG_OF_HAS_UBOOT_ENV ft_begin_node(&cxt, "u-boot-env"); for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) { + char *s, *lval, *rval; + for (nxt = i; env_get_char(nxt) != '\0'; ++nxt) ; s = tmpenv; for (k = i; k < nxt && s < &tmpenv[sizeof(tmpenv) - 1]; ++k) @@ -629,12 +639,20 @@ void ft_setup(void *blob, int size, bd_t * bd) } ft_end_node(&cxt); +#endif ft_begin_node(&cxt, "chosen"); ft_prop_str(&cxt, "name", "chosen"); ft_prop_str(&cxt, "bootargs", getenv("bootargs")); ft_prop_int(&cxt, "linux,platform", 0x600); /* what is this? */ + if (initrd_start && initrd_end) { + ft_prop_int(&cxt, "linux,initrd-start", initrd_start); + ft_prop_int(&cxt, "linux,initrd-end", initrd_end); + } +#ifdef OF_STDOUT_PATH + ft_prop_str(&cxt, "linux,stdout-path", OF_STDOUT_PATH); +#endif ft_end_node(&cxt); @@ -647,14 +665,19 @@ void ft_setup(void *blob, int size, bd_t * bd) ft_dump_blob(blob); */ +#ifdef CONFIG_OF_HAS_BD_T /* paste the bd_t at the end of the flat tree */ end = (char *)blob + be32_to_cpu(((struct boot_param_header *)blob)->totalsize); memcpy(end, bd, sizeof(*bd)); +#endif #ifdef CONFIG_PPC +#ifdef CONFIG_OF_HAS_BD_T for (i = 0; i < sizeof(bd_map)/sizeof(bd_map[0]); i++) { + uint32_t v; + sprintf(tmpenv, "/bd_t/%s", bd_map[i].name); v = *(uint32_t *)((char *)bd + bd_map[i].offset); @@ -670,6 +693,7 @@ void ft_setup(void *blob, int size, bd_t * bd) p = ft_get_prop(blob, "/bd_t/ethspeed", &len); if (p != NULL) *p = cpu_to_be32((uint32_t) bd->bi_ethspeed); +#endif clock = bd->bi_intfreq; p = ft_get_prop(blob, "/cpus/" OF_CPU "/clock-frequency", &len); @@ -680,11 +704,14 @@ void ft_setup(void *blob, int size, bd_t * bd) clock = OF_TBCLK; p = ft_get_prop(blob, "/cpus/" OF_CPU "/timebase-frequency", &len); if (p != NULL) - *p = cpu_to_be32(OF_TBCLK); + *p = cpu_to_be32(clock); #endif - #endif /* __powerpc__ */ +#ifdef CONFIG_OF_BOARD_SETUP + ft_board_setup(blob, bd); +#endif + /* printf("final OF-tree\n"); ft_dump_blob(blob); diff --git a/common/lynxkdi.c b/common/lynxkdi.c index 797d8cc..ed1b595 100644 --- a/common/lynxkdi.c +++ b/common/lynxkdi.c @@ -23,11 +23,11 @@ #if defined(CONFIG_MPC8260) || defined(CONFIG_440EP) || defined(CONFIG_440GR) void lynxkdi_boot ( image_header_t *hdr ) { - void (*lynxkdi)(void) = (void(*)(void))hdr->ih_ep; + void (*lynxkdi)(void) = (void(*)(void)) ntohl(hdr->ih_ep); lynxos_bootparms_t *parms = (lynxos_bootparms_t *)0x0020; bd_t *kbd; DECLARE_GLOBAL_DATA_PTR; - u32 *psz = (u32 *)(hdr->ih_load + 0x0204); + u32 *psz = (u32 *)(ntohl(hdr->ih_load) + 0x0204); memset( parms, 0, sizeof(*parms)); kbd = gd->bd; @@ -39,9 +39,9 @@ void lynxkdi_boot ( image_header_t *hdr ) /* Do a simple check for Bluecat so we can pass the * kernel command line parameters. */ - if( le32_to_cpu(*psz) == hdr->ih_size ){ + if( le32_to_cpu(*psz) == ntohl(hdr->ih_size) ){ /* FIXME: NOT SURE HERE ! */ char *args; - char *cmdline = (char *)(hdr->ih_load + 0x020c); + char *cmdline = (char *)(ntohl(hdr->ih_load) + 0x020c); int len; printf("Booting Bluecat KDI ...\n"); diff --git a/common/main.c b/common/main.c index f042f3a..445cb18 100644 --- a/common/main.c +++ b/common/main.c @@ -919,7 +919,10 @@ int run_command (const char *cmd, int flag) process_macros (token, finaltoken); /* Extract arguments */ - argc = parse_line (finaltoken, argv); + if ((argc = parse_line (finaltoken, argv)) == 0) { + rc = -1; /* no command at all */ + continue; + } /* Look up command in command table */ if ((cmdtp = find_cmd(argv[0])) == NULL) { @@ -945,9 +948,9 @@ int run_command (const char *cmd, int flag) puts ("'bootd' recursion detected\n"); rc = -1; continue; - } - else + } else { flag |= CMD_FLAG_BOOTD; + } } #endif /* CFG_CMD_BOOTD */ diff --git a/common/soft_i2c.c b/common/soft_i2c.c index 3d0e08c..48e3d3e 100644 --- a/common/soft_i2c.c +++ b/common/soft_i2c.c @@ -288,7 +288,10 @@ int i2c_probe(uchar addr) { int rc; - /* perform 1 byte read transaction */ + /* + * perform 1 byte write transaction with just address byte + * (fake write) + */ send_start(); rc = write_byte ((addr << 1) | 0); send_stop(); @@ -53,6 +53,10 @@ PLATFORM_CPPFLAGS+= -D__ARM__ endif endif +ifeq ($(ARCH),blackfin) +PLATFORM_CPPFLAGS+= -D__BLACKFIN__ -mno-underscore +endif + ifdef ARCH sinclude $(TOPDIR)/$(ARCH)_config.mk # include architecture dependend rules endif diff --git a/cpu/arm920t/at91rm9200/i2c.c b/cpu/arm920t/at91rm9200/i2c.c index 2565998..826cea8 100644 --- a/cpu/arm920t/at91rm9200/i2c.c +++ b/cpu/arm920t/at91rm9200/i2c.c @@ -111,7 +111,7 @@ at91_xfer(unsigned char chip, unsigned int addr, int alen, int i2c_probe(unsigned char chip) { - char buffer[1]; + unsigned char buffer[1]; return at91_xfer(chip, 0, 0, buffer, 1, 1); } @@ -191,7 +191,7 @@ i2c_init(int speed, int slaveaddr) uchar i2c_reg_read(uchar i2c_addr, uchar reg) { - char buf; + unsigned char buf; i2c_read(i2c_addr, reg, 1, &buf, 1); diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c index b4cc744..869ca79 100644 --- a/cpu/arm920t/s3c24x0/usb_ohci.c +++ b/cpu/arm920t/s3c24x0/usb_ohci.c @@ -1647,7 +1647,8 @@ int usb_lowlevel_init(void) } /* FIXME this is a second HC reset; why?? */ - writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control); + gohci.hc_control = OHCI_USB_RESET; + writel (gohci.hc_control, &gohci.regs->control); wait_ms (10); if (hc_start (&gohci) < 0) { diff --git a/cpu/bf533/Makefile b/cpu/bf533/Makefile new file mode 100644 index 0000000..c63a8f6 --- /dev/null +++ b/cpu/bf533/Makefile @@ -0,0 +1,46 @@ +# U-boot - Makefile +# +# Copyright (c) 2005 blackfin.uclinux.org +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o start1.o interrupt.o cache.o cplbhdlr.o cplbmgr.o flush.o +OBJS = cpu.o traps.o ints.o serial.o interrupts.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/bf533/bf533_serial.h b/cpu/bf533/bf533_serial.h new file mode 100644 index 0000000..d430e6c --- /dev/null +++ b/cpu/bf533/bf533_serial.h @@ -0,0 +1,78 @@ +/* + * U-boot - bf533_serial.h Serial Driver defines + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver. + * Copyright (C) 2003 Bas Vermeulen <bas@buyways.nl> + * BuyWays B.V. (www.buyways.nl) + * + * Based heavily on: + * blkfinserial.h: Definitions for the BlackFin DSP serial driver. + * + * Copyright (C) 2001 Tony Z. Kou tonyko@arcturusnetworks.com + * Copyright (C) 2001 Arcturus Networks Inc. <www.arcturusnetworks.com> + * + * Based on code from 68328serial.c which was: + * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu> + * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com> + * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org> + * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com> + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _Bf533_SERIAL_H +#define _Bf533_SERIAL_H + +#include <linux/config.h> +#include <asm/blackfin.h> + +#define SYNC_ALL __asm__ __volatile__ ("ssync;\n") +#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB; +#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB); + +void serial_setbrg(void); +static void local_put_char(char ch); +void calc_baud(void); +void serial_setbrg(void); +int serial_init(void); +void serial_putc(const char c); +int serial_tstc(void); +int serial_getc(void); +void serial_puts(const char *s); +static void local_put_char(char ch); + +extern int get_clock(void); +int baud_table[5] = {9600, 19200, 38400, 57600, 115200}; + +struct { + unsigned char dl_high; + unsigned char dl_low; +} hw_baud_table[5]; + +#ifdef CONFIG_STAMP +extern unsigned long pll_div_fact; +#endif + +#endif diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S new file mode 100644 index 0000000..8fac402 --- /dev/null +++ b/cpu/bf533/cache.S @@ -0,0 +1,125 @@ + + +#define ASSEMBLY +#include <asm/linkage.h> +#include <asm/cpu/def_LPBlackfin.h> + +.text +.align 2 +ENTRY(blackfin_icache_flush_range) + R2 = -32; + R2 = R0 & R2; + P0 = R2; + P1 = R1; + CSYNC; +1: + IFLUSH[P0++]; + CC = P0 < P1(iu); + IF CC JUMP 1b(bp); + IFLUSH[P0]; + SSYNC; + RTS; + +ENTRY(blackfin_dcache_flush_range) + R2 = -32; + R2 = R0 & R2; + P0 = R2; + P1 = R1; + CSYNC; +1: + FLUSH[P0++]; + CC = P0 < P1(iu); + IF CC JUMP 1b(bp); + FLUSH[P0]; + SSYNC; + RTS; + +ENTRY(_icache_invalidate) +ENTRY(invalidate_entire_icache) + [--SP] = ( R7:5); + + P0.L = (IMEM_CONTROL & 0xFFFF); + P0.H = (IMEM_CONTROL >> 16); + R7 = [P0]; + + /* Clear the IMC bit , All valid bits in the instruction + * cache are set to the invalid state + */ + BITCLR(R7,IMC_P); + CLI R6; + SSYNC; /* SSYNC required before invalidating cache. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + + /* Configures the instruction cache agian */ + R6 = (IMC | ENICPLB); + R7 = R7 | R6; + + CLI R6; + SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + + ( R7:5) = [SP++]; + RTS; + +/* Invalidate the Entire Data cache by + * clearing DMC[1:0] bits + */ +ENTRY(invalidate_entire_dcache) +ENTRY(_dcache_invalidate) + [--SP] = ( R7:6); + + P0.L = (DMEM_CONTROL & 0xFFFF); + P0.H = (DMEM_CONTROL >> 16); + R7 = [P0]; + + /* Clear the DMC[1:0] bits, All valid bits in the data + * cache are set to the invalid state + */ + BITCLR(R7,DMC0_P); + BITCLR(R7,DMC1_P); + CLI R6; + SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + + /* Configures the data cache again */ + + R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0); + R7 = R7 | R6; + + CLI R6; + SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + + ( R7:6) = [SP++]; + RTS; + +ENTRY(blackfin_dcache_invalidate_range) + R2 = -32; + R2 = R0 & R2; + P0 = R2; + P1 = R1; + CSYNC; +1: + FLUSHINV[P0++]; + CC = P0 < P1 (iu); + IF CC JUMP 1b (bp); + + /* If the data crosses a cache line, then we'll be pointing to + ** the last cache line, but won't have flushed/invalidated it yet, so do + ** one more. + */ + FLUSHINV[P0]; + SSYNC; + RTS; diff --git a/cpu/bf533/config.mk b/cpu/bf533/config.mk new file mode 100644 index 0000000..a9d529e --- /dev/null +++ b/cpu/bf533/config.mk @@ -0,0 +1,27 @@ +# U-boot - config.mk +# +# Copyright (c) 2005 blackfin.uclinux.org +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -ffixed-P5 diff --git a/cpu/bf533/cplbhdlr.S b/cpu/bf533/cplbhdlr.S new file mode 100644 index 0000000..61be5bb --- /dev/null +++ b/cpu/bf533/cplbhdlr.S @@ -0,0 +1,193 @@ +/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. + * + * Blackfin BF533/2.6 support : LG Soft India + */ + + +/* Include an exception handler to invoke the CPLB manager + */ + +#include <asm-blackfin/linkage.h> +#include <asm/cplb.h> +#include <asm/entry.h> + + +.text + +.globl _cplb_hdr; +.type _cplb_hdr, STT_FUNC; +.extern _cplb_mgr; +.type _cplb_mgr, STT_FUNC; +.extern __unknown_exception_occurred; +.type __unknown_exception_occurred, STT_FUNC; +.extern __cplb_miss_all_locked; +.type __cplb_miss_all_locked, STT_FUNC; +.extern __cplb_miss_without_replacement; +.type __cplb_miss_without_replacement, STT_FUNC; +.extern __cplb_protection_violation; +.type __cplb_protection_violation, STT_FUNC; +.extern panic_pv; + +.align 2; + +ENTRY(_cplb_hdr) + SSYNC; + [--SP] = ( R7:0, P5:0 ); + [--SP] = ASTAT; + [--SP] = SEQSTAT; + [--SP] = I0; + [--SP] = I1; + [--SP] = I2; + [--SP] = I3; + [--SP] = LT0; + [--SP] = LB0; + [--SP] = LC0; + [--SP] = LT1; + [--SP] = LB1; + [--SP] = LC1; + R2 = SEQSTAT; + + /*Mask the contents of SEQSTAT and leave only EXCAUSE in R2*/ + R2 <<= 26; + R2 >>= 26; + + R1 = 0x23; /* Data access CPLB protection violation */ + CC = R2 == R1; + IF !CC JUMP not_data_write; + R0 = 2; /* is a write to data space*/ + JUMP is_icplb_miss; + +not_data_write: + R1 = 0x2C; /* CPLB miss on an instruction fetch */ + CC = R2 == R1; + R0 = 0; /* is_data_miss == False*/ + IF CC JUMP is_icplb_miss; + + R1 = 0x26; + CC = R2 == R1; + IF !CC JUMP unknown; + + R0 = 1; /* is_data_miss == True*/ + +is_icplb_miss: + +#if ( defined (CONFIG_BLKFIN_CACHE) || defined (CONFIG_BLKFIN_DCACHE)) +#if ( defined (CONFIG_BLKFIN_CACHE) && !defined (CONFIG_BLKFIN_DCACHE)) + R1 = CPLB_ENABLE_ICACHE; +#endif +#if ( !defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE)) + R1 = CPLB_ENABLE_DCACHE; +#endif +#if ( defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE)) + R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE; +#endif +#else + R1 = 0; +#endif + + [--SP] = RETS; + CALL _cplb_mgr; + RETS = [SP++]; + CC = R0 == 0; + IF !CC JUMP not_replaced; + LC1 = [SP++]; + LB1 = [SP++]; + LT1 = [SP++]; + LC0 = [SP++]; + LB0 = [SP++]; + LT0 = [SP++]; + I3 = [SP++]; + I2 = [SP++]; + I1 = [SP++]; + I0 = [SP++]; + SEQSTAT = [SP++]; + ASTAT = [SP++]; + ( R7:0, P5:0 ) = [SP++]; + RTS; + +unknown: + [--SP] = RETS; + CALL __unknown_exception_occurred; + RETS = [SP++]; + JUMP unknown; +not_replaced: + CC = R0 == CPLB_NO_UNLOCKED; + IF !CC JUMP next_check; + [--SP] = RETS; + CALL __cplb_miss_all_locked; + RETS = [SP++]; +next_check: + CC = R0 == CPLB_NO_ADDR_MATCH; + IF !CC JUMP next_check2; + [--SP] = RETS; + CALL __cplb_miss_without_replacement; + RETS = [SP++]; + JUMP not_replaced; +next_check2: + CC = R0 == CPLB_PROT_VIOL; + IF !CC JUMP strange_return_from_cplb_mgr; + [--SP] = RETS; + CALL __cplb_protection_violation; + RETS = [SP++]; + JUMP not_replaced; +strange_return_from_cplb_mgr: + IDLE; + CSYNC; + JUMP strange_return_from_cplb_mgr; + +/************************************ + * Diagnostic exception handlers + */ + +__cplb_miss_all_locked: + sp += -12; + R0 = CPLB_NO_UNLOCKED; + call panic_bfin; + SP += 12; + RTS; + + __cplb_miss_without_replacement: + sp += -12; + R0 = CPLB_NO_ADDR_MATCH; + call panic_bfin; + SP += 12; + RTS; + +__cplb_protection_violation: + sp += -12; + R0 = CPLB_PROT_VIOL; + call panic_bfin; + SP += 12; + RTS; + +__unknown_exception_occurred: + + /* This function is invoked by the default exception + * handler, if it does not recognise the kind of + * exception that has occurred. In other words, the + * default handler only handles some of the system's + * exception types, and it does not expect any others + * to occur. If your application is going to be using + * other kinds of exceptions, you must replace the + * default handler with your own, that handles all the + * exceptions you will use. + * + * Since there's nothing we can do, we just loop here + * at what we hope is a suitably informative label. + */ + + IDLE; +do_not_know_what_to_do: + CSYNC; + JUMP __unknown_exception_occurred; + + RTS; +.__unknown_exception_occurred.end: +.global __unknown_exception_occurred; +.type __unknown_exception_occurred, STT_FUNC; + +panic_bfin: + RTS; diff --git a/cpu/bf533/cplbmgr.S b/cpu/bf533/cplbmgr.S new file mode 100644 index 0000000..7a0b048 --- /dev/null +++ b/cpu/bf533/cplbmgr.S @@ -0,0 +1,601 @@ +/*This file is subject to the terms and conditions of the GNU General Public + * License. + * + * Blackfin BF533/2.6 support : LG Soft India + * Modification: Dec 07 2004 + * 1. Correction in icheck_lock. Valid lock entries were + * geting victimized, for instruction cplb replacement. + * 2. Setup loop's are modified as now toolchain support's P Indexed + * addressing + * :LG Soft India + * + */ + +/* Usage: int _cplb_mgr(is_data_miss,int enable_cache) + * is_data_miss==2 => Mark as Dirty, write to the clean data page + * is_data_miss==1 => Replace a data CPLB. + * is_data_miss==0 => Replace an instruction CPLB. + * + * Returns: + * CPLB_RELOADED => Successfully updated CPLB table. + * CPLB_NO_UNLOCKED => All CPLBs are locked, so cannot be evicted.This indicates + * that the CPLBs in the configuration tablei are badly + * configured, as this should never occur. + * CPLB_NO_ADDR_MATCH => The address being accessed, that triggered the exception, + * is not covered by any of the CPLBs in the configuration + * table. The application isi presumably misbehaving. + * CPLB_PROT_VIOL => The address being accessed, that triggered thei exception, + * was not a first-write to a clean Write Back Data page, + * and so presumably is a genuine violation of the page's + * protection attributes. The application is misbehaving. + */ +#define ASSEMBLY + +#include <asm-blackfin/linkage.h> +#include <asm-blackfin/blackfin.h> +#include <asm-blackfin/cplbtab.h> +#include <asm-blackfin/cplb.h> + +.text + +.align 2; +ENTRY(_cplb_mgr) + + [--SP]=( R7:0,P5:0 ); + + CC = R0 == 2; + IF CC JUMP dcplb_write; + + CC = R0 == 0; + IF !CC JUMP dcplb_miss_compare; + + /* ICPLB Miss Exception. We need to choose one of the + * currently-installed CPLBs, and replace it with one + * from the configuration table. + */ + + P4.L = (ICPLB_FAULT_ADDR & 0xFFFF); + P4.H = (ICPLB_FAULT_ADDR >> 16); + + P1 = 16; + P5.L = page_size_table; + P5.H = page_size_table; + + P0.L = (ICPLB_DATA0 & 0xFFFF); + P0.H = (ICPLB_DATA0 >> 16); + R4 = [P4]; /* Get faulting address*/ + R6 = 64; /* Advance past the fault address, which*/ + R6 = R6 + R4; /* we'll use if we find a match*/ + R3 = ((16 << 8) | 2); /* Extract mask, bits 16 and 17.*/ + + R5 = 0; +isearch: + + R1 = [P0-0x100]; /* Address for this CPLB */ + + R0 = [P0++]; /* Info for this CPLB*/ + CC = BITTST(R0,0); /* Is the CPLB valid?*/ + IF !CC JUMP nomatch; /* Skip it, if not.*/ + CC = R4 < R1(IU); /* If fault address less than page start*/ + IF CC JUMP nomatch; /* then skip this one.*/ + R2 = EXTRACT(R0,R3.L) (Z); /* Get page size*/ + P1 = R2; + P1 = P5 + (P1<<2); /* index into page-size table*/ + R2 = [P1]; /* Get the page size*/ + R1 = R1 + R2; /* and add to page start, to get page end*/ + CC = R4 < R1(IU); /* and see whether fault addr is in page.*/ + IF !CC R4 = R6; /* If so, advance the address and finish loop.*/ + IF !CC JUMP isearch_done; +nomatch: + /* Go around again*/ + R5 += 1; + CC = BITTST(R5, 4); /* i.e CC = R5 >= 16*/ + IF !CC JUMP isearch; + +isearch_done: + I0 = R4; /* Fault address we'll search for*/ + + /* set up pointers */ + P0.L = (ICPLB_DATA0 & 0xFFFF); + P0.H = (ICPLB_DATA0 >> 16); + + /* The replacement procedure for ICPLBs */ + + P4.L = (IMEM_CONTROL & 0xFFFF); + P4.H = (IMEM_CONTROL >> 16); + + /* disable cplbs */ + R5 = [P4]; /* Control Register*/ + BITCLR(R5,ENICPLB_P); + CLI R1; + SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ + .align 8; + [P4] = R5; + SSYNC; + STI R1; + + R1 = -1; /* end point comparison */ + R3 = 16; /* counter */ + + /* Search through CPLBs for first non-locked entry */ + /* Overwrite it by moving everyone else up by 1 */ +icheck_lock: + R0 = [P0++]; + R3 = R3 + R1; + CC = R3 == R1; + IF CC JUMP all_locked; + CC = BITTST(R0, 0); /* an invalid entry is good */ + IF !CC JUMP ifound_victim; + CC = BITTST(R0,1); /* but a locked entry isn't */ + IF CC JUMP icheck_lock; + +ifound_victim: +#ifdef CONFIG_CPLB_INFO + R7 = [P0 - 0x104]; + P2.L = ipdt_table; + P2.H = ipdt_table; + P3.L = ipdt_swapcount_table; + P3.H = ipdt_swapcount_table; + P3 += -4; +icount: + R2 = [P2]; /* address from config table */ + P2 += 8; + P3 += 8; + CC = R2==-1; + IF CC JUMP icount_done; + CC = R7==R2; + IF !CC JUMP icount; + R7 = [P3]; + R7 += 1; + [P3] = R7; + CSYNC; +icount_done: +#endif + LC0=R3; + LSETUP(is_move,ie_move) LC0; +is_move: + R0 = [P0]; + [P0 - 4] = R0; + R0 = [P0 - 0x100]; + [P0-0x104] = R0; +ie_move:P0+=4; + + /* We've made space in the ICPLB table, so that ICPLB15 + * is now free to be overwritten. Next, we have to determine + * which CPLB we need to install, from the configuration + * table. This is a matter of getting the start-of-page + * addresses and page-lengths from the config table, and + * determining whether the fault address falls within that + * range. + */ + + P2.L = ipdt_table; + P2.H = ipdt_table; +#ifdef CONFIG_CPLB_INFO + P3.L = ipdt_swapcount_table; + P3.H = ipdt_swapcount_table; + P3 += -8; +#endif + P0.L = page_size_table; + P0.H = page_size_table; + + /* Retrieve our fault address (which may have been advanced + * because the faulting instruction crossed a page boundary). + */ + + R0 = I0; + + /* An extraction pattern, to get the page-size bits from + * the CPLB data entry. Bits 16-17, so two bits at posn 16. + */ + + R1 = ((16<<8)|2); +inext: R4 = [P2++]; /* address from config table */ + R2 = [P2++]; /* data from config table */ +#ifdef CONFIG_CPLB_INFO + P3 += 8; +#endif + + CC = R4 == -1; /* End of config table*/ + IF CC JUMP no_page_in_table; + + /* See if failed address > start address */ + CC = R4 <= R0(IU); + IF !CC JUMP inext; + + /* extract page size (17:16)*/ + R3 = EXTRACT(R2, R1.L) (Z); + + /* add page size to addr to get range */ + + P5 = R3; + P5 = P0 + (P5 << 2); /* scaled, for int access*/ + R3 = [P5]; + R3 = R3 + R4; + + /* See if failed address < (start address + page size) */ + CC = R0 < R3(IU); + IF !CC JUMP inext; + + /* We've found a CPLB in the config table that covers + * the faulting address, so install this CPLB into the + * last entry of the table. + */ + + P1.L = (ICPLB_DATA15 & 0xFFFF); /*ICPLB_DATA15*/ + P1.H = (ICPLB_DATA15 >> 16); + [P1] = R2; + [P1-0x100] = R4; +#ifdef CONFIG_CPLB_INFO + R3 = [P3]; + R3 += 1; + [P3] = R3; +#endif + + /* P4 points to IMEM_CONTROL, and R5 contains its old + * value, after we disabled ICPLBS. Re-enable them. + */ + + BITSET(R5,ENICPLB_P); + CLI R2; + SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ + .align 8; + [P4] = R5; + SSYNC; + STI R2; + + ( R7:0,P5:0 ) = [SP++]; + R0 = CPLB_RELOADED; + RTS; + +/* FAILED CASES*/ +no_page_in_table: + ( R7:0,P5:0 ) = [SP++]; + R0 = CPLB_NO_ADDR_MATCH; + RTS; +all_locked: + ( R7:0,P5:0 ) = [SP++]; + R0 = CPLB_NO_UNLOCKED; + RTS; +prot_violation: + ( R7:0,P5:0 ) = [SP++]; + R0 = CPLB_PROT_VIOL; + RTS; + +dcplb_write: + + /* if a DCPLB is marked as write-back (CPLB_WT==0), and + * it is clean (CPLB_DIRTY==0), then a write to the + * CPLB's page triggers a protection violation. We have to + * mark the CPLB as dirty, to indicate that there are + * pending writes associated with the CPLB. + */ + + P4.L = (DCPLB_STATUS & 0xFFFF); + P4.H = (DCPLB_STATUS >> 16); + P3.L = (DCPLB_DATA0 & 0xFFFF); + P3.H = (DCPLB_DATA0 >> 16); + R5 = [P4]; + + /* A protection violation can be caused by more than just writes + * to a clean WB page, so we have to ensure that: + * - It's a write + * - to a clean WB page + * - and is allowed in the mode the access occurred. + */ + + CC = BITTST(R5, 16); /* ensure it was a write*/ + IF !CC JUMP prot_violation; + + /* to check the rest, we have to retrieve the DCPLB.*/ + + /* The low half of DCPLB_STATUS is a bit mask*/ + + R2 = R5.L (Z); /* indicating which CPLB triggered the event.*/ + R3 = 30; /* so we can use this to determine the offset*/ + R2.L = SIGNBITS R2; + R2 = R2.L (Z); /* into the DCPLB table.*/ + R3 = R3 - R2; + P4 = R3; + P3 = P3 + (P4<<2); + R3 = [P3]; /* Retrieve the CPLB*/ + + /* Now we can check whether it's a clean WB page*/ + + CC = BITTST(R3, 14); /* 0==WB, 1==WT*/ + IF CC JUMP prot_violation; + CC = BITTST(R3, 7); /* 0 == clean, 1 == dirty*/ + IF CC JUMP prot_violation; + + /* Check whether the write is allowed in the mode that was active.*/ + + R2 = 1<<3; /* checking write in user mode*/ + CC = BITTST(R5, 17); /* 0==was user, 1==was super*/ + R5 = CC; + R2 <<= R5; /* if was super, check write in super mode*/ + R2 = R3 & R2; + CC = R2 == 0; + IF CC JUMP prot_violation; + + /* It's a genuine write-to-clean-page.*/ + + BITSET(R3, 7); /* mark as dirty*/ + [P3] = R3; /* and write back.*/ + CSYNC; + ( R7:0,P5:0 ) = [SP++]; + R0 = CPLB_RELOADED; + RTS; + +dcplb_miss_compare: + + /* Data CPLB Miss event. We need to choose a CPLB to + * evict, and then locate a new CPLB to install from the + * config table, that covers the faulting address. + */ + + P1.L = (DCPLB_DATA15 & 0xFFFF); + P1.H = (DCPLB_DATA15 >> 16); + + P4.L = (DCPLB_FAULT_ADDR & 0xFFFF); + P4.H = (DCPLB_FAULT_ADDR >> 16); + R4 = [P4]; + I0 = R4; + + /* The replacement procedure for DCPLBs*/ + + R6 = R1; /* Save for later*/ + + /* Turn off CPLBs while we work.*/ + P4.L = (DMEM_CONTROL & 0xFFFF); + P4.H = (DMEM_CONTROL >> 16); + R5 = [P4]; + BITCLR(R5,ENDCPLB_P); + CLI R0; + SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ + .align 8; + [P4] = R5; + SSYNC; + STI R0; + + /* Start looking for a CPLB to evict. Our order of preference + * is: invalid CPLBs, clean CPLBs, dirty CPLBs. Locked CPLBs + * are no good. + */ + + I1.L = (DCPLB_DATA0 & 0xFFFF); + I1.H = (DCPLB_DATA0 >> 16); + P1 = 3; + P2 = 16; + I2.L = dcplb_preference; + I2.H = dcplb_preference; + LSETUP(sdsearch1, edsearch1) LC0 = P1; +sdsearch1: + R0 = [I2++]; /* Get the bits we're interested in*/ + P0 = I1; /* Go back to start of table*/ + LSETUP (sdsearch2, edsearch2) LC1 = P2; +sdsearch2: + R1 = [P0++]; /* Fetch each installed CPLB in turn*/ + R2 = R1 & R0; /* and test for interesting bits.*/ + CC = R2 == 0; /* If none are set, it'll do.*/ + IF !CC JUMP skip_stack_check; + + R2 = [P0 - 0x104]; /* R2 - PageStart */ + P3.L = page_size_table; /* retrive end address */ + P3.H = page_size_table; /* retrive end address */ + R3 = 0x2; /* 0th - position, 2 bits -length */ + nop; /*Anamoly 05000209*/ + R7 = EXTRACT(R1,R3.l); + R7 = R7 << 2; /* Page size index offset */ + P5 = R7; + P3 = P3 + P5; + R7 = [P3]; /* page size in 1K bytes */ + + R7 = R7 << 0xA; /* in bytes * 1024*/ + R7 = R2 + R7; /* R7 - PageEnd */ + R4 = SP; /* Test SP is in range */ + + CC = R7 < R4; /* if PageEnd < SP */ + IF CC JUMP dfound_victim; + R3 = 0x284; /* stack length from start of trap till the point */ + /* 20 stack locations for future modifications */ + R4 = R4 + R3; + CC = R4 < R2; /* if SP + stacklen < PageStart */ + IF CC JUMP dfound_victim; +skip_stack_check: + +edsearch2: NOP; +edsearch1: NOP; + + /* If we got here, we didn't find a DCPLB we considered + * replacable, which means all of them were locked. + */ + + JUMP all_locked; +dfound_victim: + +#ifdef CONFIG_CPLB_INFO + R1 = [P0 - 0x104]; + P2.L = dpdt_table; + P2.H = dpdt_table; + P3.L = dpdt_swapcount_table; + P3.H = dpdt_swapcount_table; + P3 += -4; +dicount: + R2 = [P2]; + P2 += 8; + P3 += 8; + CC = R2==-1; + IF CC JUMP dicount_done; + CC = R1==R2; + IF !CC JUMP dicount; + R1 = [P3]; + R1 += 1; + [P3] = R1; + CSYNC; +dicount_done: +#endif + + /* Clean down the hardware loops*/ + R2 = 0; + LC1 = R2; + LC0 = R2; + + /* There's a suitable victim in [P0-4] (because we've + * advanced already). If it's a valid dirty write-back + * CPLB, we need to flush the pending writes first. + */ + + CC = BITTST(R1, 0); /* Is it valid?*/ + IF !CC JUMP Ddoverwrite;/* nope.*/ + CC = BITTST(R1, 7); /* Is it dirty?*/ + IF !CC JUMP Ddoverwrite (BP); /* Nope.*/ + CC = BITTST(R1, 14); /* Is it Write-Through?*/ + IF CC JUMP Ddoverwrite; /* Yep*/ + + /* This is a dirty page, so we need to flush all writes + * that are pending on the page. + */ + + /* Retrieve the page start address*/ + R0 = [P0 - 0x104]; + [--sp] = rets; + CALL dcplb_flush; /* R0==CPLB addr, R1==CPLB data*/ + rets = [sp++]; +Ddoverwrite: + + /* [P0-4] is a suitable victim CPLB, so we want to + * overwrite it by moving all the following CPLBs + * one space closer to the start. + */ + + R1.L = ((DCPLB_DATA15+4) & 0xFFFF); /*DCPLB_DATA15+4*/ + R1.H = ((DCPLB_DATA15+4) >> 16); + R0 = P0; + + /* If the victim happens to be in DCPLB15, + * we don't need to move anything. + */ + + CC = R1 == R0; + IF CC JUMP de_moved; + R1 = R1 - R0; + R1 >>= 2; + P1 = R1; + LSETUP(ds_move, de_move) LC0=P1; +ds_move: + R0 = [P0++]; /* move data */ + [P0 - 8] = R0; + R0 = [P0-0x104] /* move address */ +de_move: [P0-0x108] = R0; + + /* We've now made space in DCPLB15 for the new CPLB to be + * installed. The next stage is to locate a CPLB in the + * config table that covers the faulting address. + */ + +de_moved:NOP; + R0 = I0; /* Our faulting address */ + + P2.L = dpdt_table; + P2.H = dpdt_table; +#ifdef CONFIG_CPLB_INFO + P3.L = dpdt_swapcount_table; + P3.H = dpdt_swapcount_table; + P3 += -8; +#endif + + P1.L = page_size_table; + P1.H = page_size_table; + + /* An extraction pattern, to retrieve bits 17:16.*/ + + R1 = (16<<8)|2; +dnext: R4 = [P2++]; /* address */ + R2 = [P2++]; /* data */ +#ifdef CONFIG_CPLB_INFO + P3 += 8; +#endif + + CC = R4 == -1; + IF CC JUMP no_page_in_table; + + /* See if failed address > start address */ + CC = R4 <= R0(IU); + IF !CC JUMP dnext; + + /* extract page size (17:16)*/ + R3 = EXTRACT(R2, R1.L) (Z); + + /* add page size to addr to get range */ + + P5 = R3; + P5 = P1 + (P5 << 2); + R3 = [P5]; + R3 = R3 + R4; + + /* See if failed address < (start address + page size) */ + CC = R0 < R3(IU); + IF !CC JUMP dnext; + + /* We've found the CPLB that should be installed, so + * write it into CPLB15, masking off any caching bits + * if necessary. + */ + + P1.L = (DCPLB_DATA15 & 0xFFFF); + P1.H = (DCPLB_DATA15 >> 16); + + /* If the DCPLB has cache bits set, but caching hasn't + * been enabled, then we want to mask off the cache-in-L1 + * bit before installing. Moreover, if caching is off, we + * also want to ensure that the DCPLB has WT mode set, rather + * than WB, since WB pages still trigger first-write exceptions + * even when not caching is off, and the page isn't marked as + * cachable. Finally, we could mark the page as clean, not dirty, + * but we choose to leave that decision to the user; if the user + * chooses to have a CPLB pre-defined as dirty, then they always + * pay the cost of flushing during eviction, but don't pay the + * cost of first-write exceptions to mark the page as dirty. + */ + +#ifdef CONFIG_BLKFIN_WT + BITSET(R6, 14); /* Set WT*/ +#endif + + [P1] = R2; + [P1-0x100] = R4; +#ifdef CONFIG_CPLB_INFO + R3 = [P3]; + R3 += 1; + [P3] = R3; +#endif + + /* We've installed the CPLB, so re-enable CPLBs. P4 + * points to DMEM_CONTROL, and R5 is the value we + * last wrote to it, when we were disabling CPLBs. + */ + + BITSET(R5,ENDCPLB_P); + CLI R2; + .align 8; + [P4] = R5; + SSYNC; + STI R2; + + ( R7:0,P5:0 ) = [SP++]; + R0 = CPLB_RELOADED; + RTS; + +.data +.align 4; +page_size_table: +.byte4 0x00000400; /* 1K */ +.byte4 0x00001000; /* 4K */ +.byte4 0x00100000; /* 1M */ +.byte4 0x00400000; /* 4M */ + +.align 4; +dcplb_preference: +.byte4 0x00000001; /* valid bit */ +.byte4 0x00000082; /* dirty+lock bits */ +.byte4 0x00000002; /* lock bit */ diff --git a/cpu/bf533/cpu.c b/cpu/bf533/cpu.c new file mode 100644 index 0000000..78e2b96 --- /dev/null +++ b/cpu/bf533/cpu.c @@ -0,0 +1,189 @@ +/* + * U-boot - cpu.c CPU specific functions + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/blackfin.h> +#include <command.h> +#include <asm/entry.h> + +#define SSYNC() asm("ssync;") +#define CACHE_ON 1 +#define CACHE_OFF 0 + +/* Data Attibutes*/ + +#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) + +#define ANOMALY_05000158 0x200 +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) +#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) + +static unsigned int icplb_table[16][2]={ + {0xFFA00000, L1_IMEMORY}, + {0x00000000, SDRAM_IKERNEL}, /*SDRAM_Page1*/ + {0x00400000, SDRAM_IKERNEL}, /*SDRAM_Page1*/ + {0x07C00000, SDRAM_IKERNEL}, /*SDRAM_Page14*/ + {0x00800000, SDRAM_IGENERIC}, /*SDRAM_Page2*/ + {0x00C00000, SDRAM_IGENERIC}, /*SDRAM_Page2*/ + {0x01000000, SDRAM_IGENERIC}, /*SDRAM_Page4*/ + {0x01400000, SDRAM_IGENERIC}, /*SDRAM_Page5*/ + {0x01800000, SDRAM_IGENERIC}, /*SDRAM_Page6*/ + {0x01C00000, SDRAM_IGENERIC}, /*SDRAM_Page7*/ + {0x02000000, SDRAM_IGENERIC}, /*SDRAM_Page8*/ + {0x02400000, SDRAM_IGENERIC}, /*SDRAM_Page9*/ + {0x02800000, SDRAM_IGENERIC}, /*SDRAM_Page10*/ + {0x02C00000, SDRAM_IGENERIC}, /*SDRAM_Page11*/ + {0x03000000, SDRAM_IGENERIC}, /*SDRAM_Page12*/ + {0x03400000, SDRAM_IGENERIC}, /*SDRAM_Page13*/ +}; + +static unsigned int dcplb_table[16][2]={ + {0xFFA00000,L1_DMEMORY}, + {0x00000000,SDRAM_DKERNEL}, /*SDRAM_Page1*/ + {0x00400000,SDRAM_DKERNEL}, /*SDRAM_Page1*/ + {0x07C00000,SDRAM_DKERNEL}, /*SDRAM_Page15*/ + {0x00800000,SDRAM_DGENERIC}, /*SDRAM_Page2*/ + {0x00C00000,SDRAM_DGENERIC}, /*SDRAM_Page3*/ + {0x01000000,SDRAM_DGENERIC}, /*SDRAM_Page4*/ + {0x01400000,SDRAM_DGENERIC}, /*SDRAM_Page5*/ + {0x01800000,SDRAM_DGENERIC}, /*SDRAM_Page6*/ + {0x01C00000,SDRAM_DGENERIC}, /*SDRAM_Page7*/ + {0x02000000,SDRAM_DGENERIC}, /*SDRAM_Page8*/ + {0x02400000,SDRAM_DGENERIC}, /*SDRAM_Page9*/ + {0x02800000,SDRAM_DGENERIC}, /*SDRAM_Page10*/ + {0x02C00000,SDRAM_DGENERIC}, /*SDRAM_Page11*/ + {0x03000000,SDRAM_DGENERIC}, /*SDRAM_Page12*/ + {0x20000000,SDRAM_EBIU}, /*For Network */ +}; + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + __asm__ __volatile__ + ("cli r3;" + "P0 = %0;" + "JUMP (P0);" + : + : "r" (L1_ISRAM) + ); + + return 0; +} + +/* These functions are just used to satisfy the linker */ +int cpu_init(void) +{ + return 0; +} + +int cleanup_before_linux(void) +{ + return 0; +} + +void icache_enable(void) +{ + unsigned int *I0,*I1; + int i; + + I0 = (unsigned int *)ICPLB_ADDR0; + I1 = (unsigned int *)ICPLB_DATA0; + + for(i=0;i<16;i++){ + *I0++ = icplb_table[i][0]; + *I1++ = icplb_table[i][1]; + } + cli(); + SSYNC(); + *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; + SSYNC(); + sti(); +} + +void icache_disable(void) +{ + cli(); + SSYNC(); + *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); + SSYNC(); + sti(); +} + +int icache_status(void) +{ + unsigned int value; + value = *(unsigned int *)IMEM_CONTROL; + + if( value & (IMC|ENICPLB) ) + return CACHE_ON; + else + return CACHE_OFF; +} + +void dcache_enable(void) +{ + unsigned int *I0,*I1; + unsigned int temp; + int i; + I0 = (unsigned int *)DCPLB_ADDR0; + I1 = (unsigned int *)DCPLB_DATA0; + + for(i=0;i<16;i++){ + *I0++ = dcplb_table[i][0]; + *I1++ = dcplb_table[i][1]; + } + cli(); + temp = *(unsigned int *)DMEM_CONTROL; + SSYNC(); + *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE |ENDCPLB |PORT_PREF0|temp; + SSYNC(); + sti(); +} + +void dcache_disable(void) +{ + cli(); + SSYNC(); + *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE |ENDCPLB |PORT_PREF0); + SSYNC(); + sti(); +} + +int dcache_status(void) +{ + unsigned int value; + value = *(unsigned int *)DMEM_CONTROL; + if( value & (ENDCPLB)) + return CACHE_ON; + else + return CACHE_OFF; +} diff --git a/cpu/bf533/cpu.h b/cpu/bf533/cpu.h new file mode 100644 index 0000000..7ec3387 --- /dev/null +++ b/cpu/bf533/cpu.h @@ -0,0 +1,65 @@ +/* + * U-boot - cpu.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _CPU_H_ +#define _CPU_H_ + +#include <command.h> + +#define INTERNAL_IRQS (32) +#define NUM_IRQ_NODES 16 +#define DEF_INTERRUPT_FLAGS 1 +#define MAX_TIM_LOAD 0xFFFFFFFF + +void blackfin_irq_panic(int reason, struct pt_regs * reg); +extern void dump(struct pt_regs * regs); +void display_excp(void); +asmlinkage void evt_nmi(void); +asmlinkage void evt_exception(void); +asmlinkage void trap(void); +asmlinkage void evt_ivhw(void); +asmlinkage void evt_rst(void); +asmlinkage void evt_timer(void); +asmlinkage void evt_evt7(void); +asmlinkage void evt_evt8(void); +asmlinkage void evt_evt9(void); +asmlinkage void evt_evt10(void); +asmlinkage void evt_evt11(void); +asmlinkage void evt_evt12(void); +asmlinkage void evt_evt13(void); +asmlinkage void evt_soft_int1(void); +asmlinkage void evt_system_call(void); +void blackfin_irq_panic(int reason, struct pt_regs * regs); +void blackfin_free_irq(unsigned int irq, void *dev_id); +void call_isr(int irq, struct pt_regs * fp); +void blackfin_do_irq(int vec, struct pt_regs *fp); +void blackfin_init_IRQ(void); +void blackfin_enable_irq(unsigned int irq); +void blackfin_disable_irq(unsigned int irq); +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +int blackfin_request_irq(unsigned int irq, + void (*handler)(int, void *, struct pt_regs *), + unsigned long flags,const char *devname,void *dev_id); +void timer_init(void); +#endif diff --git a/cpu/bf533/flush.S b/cpu/bf533/flush.S new file mode 100644 index 0000000..9fbdefc --- /dev/null +++ b/cpu/bf533/flush.S @@ -0,0 +1,402 @@ +/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved. + * Copyright (C) 2004 LG SOft India. All Rights Reserved. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. + * + * Blackfin BF533/2.6 support : LG Soft India + */ +#define ASSEMBLY + +#include <asm/linkage.h> +#include <asm/cplb.h> +#include <asm/blackfin.h> + +.text + +/* This is an external function being called by the user + * application through __flush_cache_all. Currently this function + * serves the purpose of flushing all the pending writes in + * in the instruction cache. + */ + +ENTRY(flush_instruction_cache) + [--SP] = ( R7:6, P5:4 ); + LINK 12; + SP += -12; + P5.H = (ICPLB_ADDR0 >> 16); + P5.L = (ICPLB_ADDR0 & 0xFFFF); + P4.H = (ICPLB_DATA0 >> 16); + P4.L = (ICPLB_DATA0 & 0xFFFF); + R7 = CPLB_VALID | CPLB_L1_CHBL; + R6 = 16; +inext: R0 = [P5++]; + R1 = [P4++]; + [--SP] = RETS; + CALL icplb_flush; /* R0 = page, R1 = data*/ + RETS = [SP++]; +iskip: R6 += -1; + CC = R6; + IF CC JUMP inext; + SSYNC; + SP += 12; + UNLINK; + ( R7:6, P5:4 ) = [SP++]; + RTS; + +/* This is an internal function to flush all pending + * writes in the cache associated with a particular ICPLB. + * + * R0 - page's start address + * R1 - CPLB's data field. + */ + +.align 2 +ENTRY(icplb_flush) + [--SP] = ( R7:0, P5:0 ); + [--SP] = LC0; + [--SP] = LT0; + [--SP] = LB0; + [--SP] = LC1; + [--SP] = LT1; + [--SP] = LB1; + + /* If it's a 1K or 4K page, then it's quickest to + * just systematically flush all the addresses in + * the page, regardless of whether they're in the + * cache, or dirty. If it's a 1M or 4M page, there + * are too many addresses, and we have to search the + * cache for lines corresponding to the page. + */ + + CC = BITTST(R1, 17); /* 1MB or 4MB */ + IF !CC JUMP iflush_whole_page; + + /* We're only interested in the page's size, so extract + * this from the CPLB (bits 17:16), and scale to give an + * offset into the page_size and page_prefix tables. + */ + + R1 <<= 14; + R1 >>= 30; + R1 <<= 2; + + /* We can also determine the sub-bank used, because this is + * taken from bits 13:12 of the address. + */ + + R3 = ((12<<8)|2); /* Extraction pattern */ + nop; /*Anamoly 05000209*/ + R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/ + R3.H = R4.L << 0 ; /* Save in extraction pattern for later deposit.*/ + + + /* So: + * R0 = Page start + * R1 = Page length (actually, offset into size/prefix tables) + * R3 = sub-bank deposit values + * + * The cache has 2 Ways, and 64 sets, so we iterate through + * the sets, accessing the tag for each Way, for our Bank and + * sub-bank, looking for dirty, valid tags that match our + * address prefix. + */ + + P5.L = (ITEST_COMMAND & 0xFFFF); + P5.H = (ITEST_COMMAND >> 16); + P4.L = (ITEST_DATA0 & 0xFFFF); + P4.H = (ITEST_DATA0 >> 16); + + P0.L = page_prefix_table; + P0.H = page_prefix_table; + P1 = R1; + R5 = 0; /* Set counter*/ + P0 = P1 + P0; + R4 = [P0]; /* This is the address prefix*/ + + /* We're reading (bit 1==0) the tag (bit 2==0), and we + * don't care about which double-word, since we're only + * fetching tags, so we only have to set Set, Bank, + * Sub-bank and Way. + */ + + P2 = 4; + LSETUP (ifs1, ife1) LC1 = P2; +ifs1: P0 = 32; /* iterate over all sets*/ + LSETUP (ifs0, ife0) LC0 = P0; +ifs0: R6 = R5 << 5; /* Combine set*/ + R6.H = R3.H << 0 ; /* and sub-bank*/ + [P5] = R6; /* Issue Command*/ + SSYNC; /* CSYNC will not work here :(*/ + R7 = [P4]; /* and read Tag.*/ + CC = BITTST(R7, 0); /* Check if valid*/ + IF !CC JUMP ifskip; /* and skip if not.*/ + + /* Compare against the page address. First, plant bits 13:12 + * into the tag, since those aren't part of the returned data. + */ + + R7 = DEPOSIT(R7, R3); /* set 13:12*/ + R1 = R7 & R4; /* Mask off lower bits*/ + CC = R1 == R0; /* Compare against page start.*/ + IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/ + + /* Tag address matches against page, so this is an entry + * we must flush. + */ + + R7 >>= 10; /* Mask off the non-address bits*/ + R7 <<= 10; + P3 = R7; + IFLUSH [P3]; /* And flush the entry*/ +ifskip: +ife0: R5 += 1; /* Advance to next Set*/ +ife1: NOP; + +ifinished: + SSYNC; /* Ensure the data gets out to mem.*/ + + /*Finished. Restore context.*/ + LB1 = [SP++]; + LT1 = [SP++]; + LC1 = [SP++]; + LB0 = [SP++]; + LT0 = [SP++]; + LC0 = [SP++]; + ( R7:0, P5:0 ) = [SP++]; + RTS; + +iflush_whole_page: + /* It's a 1K or 4K page, so quicker to just flush the + * entire page. + */ + + P1 = 32; /* For 1K pages*/ + P2 = P1 << 2; /* For 4K pages*/ + P0 = R0; /* Start of page*/ + CC = BITTST(R1, 16); /* Whether 1K or 4K*/ + IF CC P1 = P2; + P1 += -1; /* Unroll one iteration*/ + SSYNC; + IFLUSH [P0++]; /* because CSYNC can't end loops.*/ + LSETUP (isall, ieall) LC0 = P1; +isall:IFLUSH [P0++]; +ieall: NOP; + SSYNC; + JUMP ifinished; + +/* This is an external function being called by the user + * application through __flush_cache_all. Currently this function + * serves the purpose of flushing all the pending writes in + * in the data cache. + */ + +ENTRY(flush_data_cache) + [--SP] = ( R7:6, P5:4 ); + LINK 12; + SP += -12; + P5.H = (DCPLB_ADDR0 >> 16); + P5.L = (DCPLB_ADDR0 & 0xFFFF); + P4.H = (DCPLB_DATA0 >> 16); + P4.L = (DCPLB_DATA0 & 0xFFFF); + R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z); + R6 = 16; +next: R0 = [P5++]; + R1 = [P4++]; + CC = BITTST(R1, 14); /* Is it write-through?*/ + IF CC JUMP skip; /* If so, ignore it.*/ + R2 = R1 & R7; /* Is it a dirty, cached page?*/ + CC = R2; + IF !CC JUMP skip; /* If not, ignore it.*/ + [--SP] = RETS; + CALL dcplb_flush; /* R0 = page, R1 = data*/ + RETS = [SP++]; +skip: R6 += -1; + CC = R6; + IF CC JUMP next; + SSYNC; + SP += 12; + UNLINK; + ( R7:6, P5:4 ) = [SP++]; + RTS; + +/* This is an internal function to flush all pending + * writes in the cache associated with a particular DCPLB. + * + * R0 - page's start address + * R1 - CPLB's data field. + */ + +.align 2 +ENTRY(dcplb_flush) + [--SP] = ( R7:0, P5:0 ); + [--SP] = LC0; + [--SP] = LT0; + [--SP] = LB0; + [--SP] = LC1; + [--SP] = LT1; + [--SP] = LB1; + + /* If it's a 1K or 4K page, then it's quickest to + * just systematically flush all the addresses in + * the page, regardless of whether they're in the + * cache, or dirty. If it's a 1M or 4M page, there + * are too many addresses, and we have to search the + * cache for lines corresponding to the page. + */ + + CC = BITTST(R1, 17); /* 1MB or 4MB */ + IF !CC JUMP dflush_whole_page; + + /* We're only interested in the page's size, so extract + * this from the CPLB (bits 17:16), and scale to give an + * offset into the page_size and page_prefix tables. + */ + + R1 <<= 14; + R1 >>= 30; + R1 <<= 2; + + /* The page could be mapped into Bank A or Bank B, depending + * on (a) whether both banks are configured as cache, and + * (b) on whether address bit A[x] is set. x is determined + * by DCBS in DMEM_CONTROL + */ + + R2 = 0; /* Default to Bank A (Bank B would be 1)*/ + + P0.L = (DMEM_CONTROL & 0xFFFF); + P0.H = (DMEM_CONTROL >> 16); + + R3 = [P0]; /* If Bank B is not enabled as cache*/ + CC = BITTST(R3, 2); /* then Bank A is our only option.*/ + IF CC JUMP bank_chosen; + + R4 = 1<<14; /* If DCBS==0, use A[14].*/ + R5 = R4 << 7; /* If DCBS==1, use A[23];*/ + CC = BITTST(R3, 4); + IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/ + R5 = R0 & R4; /* Use it to test the Page address*/ + CC = R5; /* and if that bit is set, we use Bank B,*/ + R2 = CC; /* else we use Bank A.*/ + R2 <<= 23; /* The Bank selection's at posn 23.*/ + +bank_chosen: + + /* We can also determine the sub-bank used, because this is + * taken from bits 13:12 of the address. + */ + + R3 = ((12<<8)|2); /* Extraction pattern */ + nop; /*Anamoly 05000209*/ + R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/ + R3.H = R4.L << 0 ; /* Save in extraction pattern for later deposit.*/ + + /* So: + * R0 = Page start + * R1 = Page length (actually, offset into size/prefix tables) + * R2 = Bank select mask + * R3 = sub-bank deposit values + * + * The cache has 2 Ways, and 64 sets, so we iterate through + * the sets, accessing the tag for each Way, for our Bank and + * sub-bank, looking for dirty, valid tags that match our + * address prefix. + */ + + P5.L = (DTEST_COMMAND & 0xFFFF); + P5.H = (DTEST_COMMAND >> 16); + P4.L = (DTEST_DATA0 & 0xFFFF); + P4.H = (DTEST_DATA0 >> 16); + + P0.L = page_prefix_table; + P0.H = page_prefix_table; + P1 = R1; + R5 = 0; /* Set counter*/ + P0 = P1 + P0; + R4 = [P0]; /* This is the address prefix*/ + + + /* We're reading (bit 1==0) the tag (bit 2==0), and we + * don't care about which double-word, since we're only + * fetching tags, so we only have to set Set, Bank, + * Sub-bank and Way. + */ + + P2 = 2; + LSETUP (fs1, fe1) LC1 = P2; +fs1: P0 = 64; /* iterate over all sets*/ + LSETUP (fs0, fe0) LC0 = P0; +fs0: R6 = R5 << 5; /* Combine set*/ + R6.H = R3.H << 0 ; /* and sub-bank*/ + R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/ + BITSET(R6,14); + [P5] = R6; /* Issue Command*/ + SSYNC; + R7 = [P4]; /* and read Tag.*/ + CC = BITTST(R7, 0); /* Check if valid*/ + IF !CC JUMP fskip; /* and skip if not.*/ + CC = BITTST(R7, 1); /* Check if dirty*/ + IF !CC JUMP fskip; /* and skip if not.*/ + + /* Compare against the page address. First, plant bits 13:12 + * into the tag, since those aren't part of the returned data. + */ + + R7 = DEPOSIT(R7, R3); /* set 13:12*/ + R1 = R7 & R4; /* Mask off lower bits*/ + CC = R1 == R0; /* Compare against page start.*/ + IF !CC JUMP fskip; /* Skip it if it doesn't match.*/ + + /* Tag address matches against page, so this is an entry + * we must flush. + */ + + R7 >>= 10; /* Mask off the non-address bits*/ + R7 <<= 10; + P3 = R7; + SSYNC; + FLUSHINV [P3]; /* And flush the entry*/ +fskip: +fe0: R5 += 1; /* Advance to next Set*/ +fe1: BITSET(R2, 26); /* Go to next Way.*/ + +dfinished: + SSYNC; /* Ensure the data gets out to mem.*/ + + /*Finished. Restore context.*/ + LB1 = [SP++]; + LT1 = [SP++]; + LC1 = [SP++]; + LB0 = [SP++]; + LT0 = [SP++]; + LC0 = [SP++]; + ( R7:0, P5:0 ) = [SP++]; + RTS; + +dflush_whole_page: + + /* It's a 1K or 4K page, so quicker to just flush the + * entire page. + */ + + P1 = 32; /* For 1K pages*/ + P2 = P1 << 2; /* For 4K pages*/ + P0 = R0; /* Start of page*/ + CC = BITTST(R1, 16); /* Whether 1K or 4K*/ + IF CC P1 = P2; + P1 += -1; /* Unroll one iteration*/ + SSYNC; + FLUSHINV [P0++]; /* because CSYNC can't end loops.*/ + LSETUP (eall, eall) LC0 = P1; +eall: FLUSHINV [P0++]; + SSYNC; + JUMP dfinished; + +.align 4; +page_prefix_table: +.byte4 0xFFFFFC00; /* 1K */ +.byte4 0xFFFFF000; /* 4K */ +.byte4 0xFFF00000; /* 1M */ +.byte4 0xFFC00000; /* 4M */ +.page_prefix_table.end: diff --git a/cpu/bf533/interrupt.S b/cpu/bf533/interrupt.S new file mode 100644 index 0000000..e780dc6 --- /dev/null +++ b/cpu/bf533/interrupt.S @@ -0,0 +1,391 @@ +/* + * U-boot - interrupt.S Processing of interrupts and exception handling + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This file is based on interrupt.S + * + * Copyright (C) 2003 Metrowerks, Inc. <mwaddel@metrowerks.com> + * Copyright (C) 2002 Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca> + * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>, + * Kenneth Albanowski <kjahds@kjahds.com>, + * The Silver Hammer Group, Ltd. + * + * (c) 1995, Dionne & Associates + * (c) 1995, DKG Display Tech. + * + * This file is also based on exception.asm + * (C) Copyright 2001-2005 - Analog Devices, Inc. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define ASSEMBLY + +#include <asm/hw_irq.h> +#include <asm/entry.h> +#include <asm/blackfin_defs.h> +#include <asm/cpu/bf533_irq.h> + +.global blackfin_irq_panic; + +.text +.align 2 + +#ifndef CONFIG_KGDB +.global evt_emulation +evt_emulation: + SAVE_CONTEXT + r0 = IRQ_EMU; + r1 = seqstat; + sp += -12; + call blackfin_irq_panic; + sp += 12; + rte; +#endif + +.global evt_nmi +evt_nmi: + SAVE_CONTEXT + r0 = IRQ_NMI; + r1 = RETN; + sp += -12; + call blackfin_irq_panic; + sp += 12; + +_evt_nmi_exit: + rtn; + +.global trap +trap: + [--sp] = r0; + [--sp] = r1; + [--sp] = p0; + [--sp] = p1; + [--sp] = astat; + r0 = seqstat; + R0 <<= 26; + R0 >>= 26; + p0 = r0; + p1.l = EVTABLE; + p1.h = EVTABLE; + p0 = p1 + (p0 << 1); + r1 = W[p0] (Z); + p1 = r1; + jump (pc + p1); + +.global _EVENT1 +_EVENT1: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT2 +_EVENT2: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT3 +_EVENT3: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT4 +_EVENT4: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT5 +_EVENT5: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT6 +_EVENT6: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT7 +_EVENT7: + RAISE 15; + JUMP.S _EXIT; + +.global _EVENT8 +_EVENT8: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT9 +_EVENT9: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT10 +_EVENT10: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT11 +_EVENT11: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT12 +_EVENT12: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT13 +_EVENT13: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT14 +_EVENT14: +/* RAISE 14; */ + CALL _cplb_hdr; + JUMP.S _EXIT; + +.global _EVENT19 +_EVENT19: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT20 +_EVENT20: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT21 +_EVENT21: + RAISE 14; + JUMP.S _EXIT; + +.global _EXIT +_EXIT: + ASTAT = [sp++]; + p1 = [sp++]; + p0 = [sp++]; + r1 = [sp++]; + r0 = [sp++]; + RTX; + +EVTABLE: + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x003E; + .byte2 0x0042; + .byte4 0x0000; + .byte4 0x0000; + .byte4 0x0000; + .byte4 0x0000; + .byte4 0x0000; + .byte4 0x0000; + .byte4 0x0000; + .byte2 0x0000; + .byte2 0x001E; + .byte2 0x0022; + .byte2 0x0032; + .byte2 0x002e; + .byte2 0x0002; + .byte2 0x0036; + .byte2 0x002A; + .byte2 0x001A; + .byte2 0x0016; + .byte2 0x000A; + .byte2 0x000E; + .byte2 0x0012; + .byte2 0x0006; + .byte2 0x0026; + +.global evt_rst +evt_rst: + SAVE_CONTEXT + r0 = IRQ_RST; + r1 = RETN; + sp += -12; + call do_reset; + sp += 12; + +_evt_rst_exit: + rtn; + +irq_panic: + r0 = IRQ_EVX; + r1 = sp; + sp += -12; + call blackfin_irq_panic; + sp += 12; + +.global evt_ivhw +evt_ivhw: + SAVE_CONTEXT + RAISE 14; + +_evt_ivhw_exit: + rti; + +.global evt_timer +evt_timer: + SAVE_CONTEXT + r0 = IRQ_CORETMR; + sp += -12; + /* Polling method used now. */ + /* call timer_int; */ + sp += 12; + RESTORE_CONTEXT + rti; + nop; + +.global evt_evt7 +evt_evt7: + SAVE_CONTEXT + r0 = 7; + sp += -12; + call process_int; + sp += 12; + +evt_evt7_exit: + RESTORE_CONTEXT + rti; + +.global evt_evt8 +evt_evt8: + SAVE_CONTEXT + r0 = 8; + sp += -12; + call process_int; + sp += 12; + +evt_evt8_exit: + RESTORE_CONTEXT + rti; + +.global evt_evt9 +evt_evt9: + SAVE_CONTEXT + r0 = 9; + sp += -12; + call process_int; + sp += 12; + +evt_evt9_exit: + RESTORE_CONTEXT + rti; + +.global evt_evt10 +evt_evt10: + SAVE_CONTEXT + r0 = 10; + sp += -12; + call process_int; + sp += 12; + +evt_evt10_exit: + RESTORE_CONTEXT + rti; + +.global evt_evt11 +evt_evt11: + SAVE_CONTEXT + r0 = 11; + sp += -12; + call process_int; + sp += 12; + +evt_evt11_exit: + RESTORE_CONTEXT + rti; + +.global evt_evt12 +evt_evt12: + SAVE_CONTEXT + r0 = 12; + sp += -12; + call process_int; + sp += 12; +evt_evt12_exit: + RESTORE_CONTEXT + rti; + +.global evt_evt13 +evt_evt13: + SAVE_CONTEXT + r0 = 13; + sp += -12; + call process_int; + sp += 12; + +evt_evt13_exit: + RESTORE_CONTEXT + rti; + +.global evt_system_call +evt_system_call: + [--sp] = r0; + [--SP] = RETI; + r0 = [sp++]; + r0 += 2; + [--sp] = r0; + RETI = [SP++]; + r0 = [SP++]; + SAVE_CONTEXT + sp += -12; + call display_excp; + sp += 12; + RESTORE_CONTEXT + RTI; + +evt_system_call_exit: + rti; + +.global evt_soft_int1 +evt_soft_int1: + [--sp] = r0; + [--SP] = RETI; + r0 = [sp++]; + r0 += 2; + [--sp] = r0; + RETI = [SP++]; + r0 = [SP++]; + SAVE_CONTEXT + sp += -12; + call display_excp; + sp += 12; + RESTORE_CONTEXT + RTI; + +evt_soft_int1_exit: + rti; diff --git a/cpu/bf533/interrupts.c b/cpu/bf533/interrupts.c new file mode 100644 index 0000000..df1a25e --- /dev/null +++ b/cpu/bf533/interrupts.c @@ -0,0 +1,165 @@ +/* + * U-boot - interrupts.c Interrupt related routines + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on interrupts.c + * Copyright 1996 Roman Zippel + * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org> + * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca> + * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> + * Copyright 2003 Metrowerks/Motorola + * Copyright 2003 Bas Vermeulen <bas@buyways.nl>, + * BuyWays B.V. (www.buyways.nl) + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/machdep.h> +#include <asm/irq.h> +#include <asm/cpu/defBF533.h> +#include "cpu.h" + +static ulong timestamp; +static ulong last_time; +static int int_flag; + +int irq_flags; /* needed by asm-blackfin/system.h */ + +/* Functions just to satisfy the linker */ + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On BF533 it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On BF533 it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + + tbclk = CFG_HZ; + return tbclk; +} + +void enable_interrupts(void) +{ + restore_flags(int_flag); +} + +int disable_interrupts(void) +{ + save_and_cli(int_flag); + return 1; +} + +int interrupt_init(void) +{ + return (0); +} + +void udelay(unsigned long usec) +{ + unsigned long delay, start, stop; + unsigned long cclk; + cclk = (CONFIG_CCLK_HZ); + + while ( usec > 1 ) { + /* + * how many clock ticks to delay? + * - request(in useconds) * clock_ticks(Hz) / useconds/second + */ + if (usec < 1000) { + delay = (usec * (cclk/244)) >> 12 ; + usec = 0; + } else { + delay = (1000 * (cclk/244)) >> 12 ; + usec -= 1000; + } + + asm volatile (" %0 = CYCLES;": "=g"(start)); + do { + asm volatile (" %0 = CYCLES; ": "=g"(stop)); + } while (stop - start < delay); + } + + return; +} + +void timer_init(void) +{ + *pTCNTL = 0x1; + *pTSCALE = 0x0; + *pTCOUNT = MAX_TIM_LOAD; + *pTPERIOD = MAX_TIM_LOAD; + *pTCNTL = 0x7; + asm("CSYNC;"); + + timestamp = 0; + last_time = 0; +} + +/* Any network command or flash + * command is started get_timer shall + * be called before TCOUNT gets reset, + * to implement the accurate timeouts. + * + * How ever milliconds doesn't return + * the number that has been elapsed from + * the last reset. + * + * As get_timer is used in the u-boot + * only for timeouts this should be + * sufficient + */ +ulong get_timer(ulong base) +{ + ulong milisec; + + /* Number of clocks elapsed */ + ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT)); + + /* Find if the TCOUNT is reset + timestamp gives the number of times + TCOUNT got reset */ + if(clocks < last_time) + timestamp++; + last_time = clocks; + + /* Get the number of milliseconds */ + milisec = clocks/(CONFIG_CCLK_HZ / 1000); + + /* Find the number of millisonds + that got elapsed before this TCOUNT + cycle */ + milisec += timestamp * (MAX_TIM_LOAD/(CONFIG_CCLK_HZ / 1000)); + + return (milisec - base); +} diff --git a/cpu/bf533/ints.c b/cpu/bf533/ints.c new file mode 100644 index 0000000..859f4b2 --- /dev/null +++ b/cpu/bf533/ints.c @@ -0,0 +1,107 @@ +/* + * U-boot - ints.c Interrupt related routines + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on ints.c + * + * Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin + * drivers + * + * Copyright 1996 Roman Zippel + * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org> + * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca> + * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> + * Copyright 2003 Metrowerks/Motorola + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/stddef.h> +#include <asm/system.h> +#include <asm/irq.h> +#include <asm/traps.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/machdep.h> +#include <asm/setup.h> +#include <asm/blackfin.h> +#include "cpu.h" + +void blackfin_irq_panic(int reason, struct pt_regs *regs) +{ + printf("\n\nException: IRQ 0x%x entered\n", reason); + printf("code=[0x%x], ", (unsigned int) (regs->seqstat & 0x3f)); + printf("stack frame=0x%x, ", (unsigned int) regs); + printf("bad PC=0x%04x\n", (unsigned int) regs->pc); + dump(regs); + printf("Unhandled IRQ or exceptions!\n"); + printf("Please reset the board \n"); +} + +void blackfin_init_IRQ(void) +{ + *(unsigned volatile long *) (SIC_IMASK) = SIC_UNMASK_ALL; + cli(); +#ifndef CONFIG_KGDB + *(unsigned volatile long *) (EVT_EMULATION_ADDR) = 0x0; +#endif + *(unsigned volatile long *) (EVT_NMI_ADDR) = + (unsigned volatile long) evt_nmi; + *(unsigned volatile long *) (EVT_EXCEPTION_ADDR) = + (unsigned volatile long) trap; + *(unsigned volatile long *) (EVT_HARDWARE_ERROR_ADDR) = + (unsigned volatile long) evt_ivhw; + *(unsigned volatile long *) (EVT_RESET_ADDR) = + (unsigned volatile long) evt_rst; + *(unsigned volatile long *) (EVT_TIMER_ADDR) = + (unsigned volatile long) evt_timer; + *(unsigned volatile long *) (EVT_IVG7_ADDR) = + (unsigned volatile long) evt_evt7; + *(unsigned volatile long *) (EVT_IVG8_ADDR) = + (unsigned volatile long) evt_evt8; + *(unsigned volatile long *) (EVT_IVG9_ADDR) = + (unsigned volatile long) evt_evt9; + *(unsigned volatile long *) (EVT_IVG10_ADDR) = + (unsigned volatile long) evt_evt10; + *(unsigned volatile long *) (EVT_IVG11_ADDR) = + (unsigned volatile long) evt_evt11; + *(unsigned volatile long *) (EVT_IVG12_ADDR) = + (unsigned volatile long) evt_evt12; + *(unsigned volatile long *) (EVT_IVG13_ADDR) = + (unsigned volatile long) evt_evt13; + *(unsigned volatile long *) (EVT_IVG14_ADDR) = + (unsigned volatile long) evt_system_call; + *(unsigned volatile long *) (EVT_IVG15_ADDR) = + (unsigned volatile long) evt_soft_int1; + *(volatile unsigned long *) ILAT = 0; + asm("csync;"); + sti(); + *(volatile unsigned long *) IMASK = 0xffbf; + asm("csync;"); +} + +void display_excp(void) +{ + printf("Exception!\n"); +} diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c new file mode 100644 index 0000000..84ae9d9 --- /dev/null +++ b/cpu/bf533/serial.c @@ -0,0 +1,194 @@ +/* + * U-boot - serial.c Serial driver for BF533 + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * bf533_serial.c: Serial driver for BlackFin BF533 DSP internal UART. + * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>, + * BuyWays B.V. (www.buyways.nl) + * + * Based heavily on blkfinserial.c + * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs. + * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com> + * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com> + * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com> + * + * Based on code from 68328 version serial driver imlpementation which was: + * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu> + * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com> + * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org> + * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com> + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/irq.h> +#include <asm/system.h> +#include <asm/segment.h> +#include <asm/bitops.h> +#include <asm/delay.h> +#include <asm/uaccess.h> +#include "bf533_serial.h" + +unsigned long pll_div_fact; + +void calc_baud(void) +{ + unsigned char i; + int temp; + + for(i = 0; i < sizeof(baud_table)/sizeof(int); i++) { + temp = CONFIG_SCLK_HZ/(baud_table[i]*8); + if ( temp && 0x1 == 1 ) { + temp++; + } + temp = temp/2; + hw_baud_table[i].dl_high = (temp >> 8)& 0xFF; + hw_baud_table[i].dl_low = (temp) & 0xFF; + } +} + +void serial_setbrg(void) +{ + int i; + DECLARE_GLOBAL_DATA_PTR; + + calc_baud(); + + for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) { + if (gd->baudrate == baud_table[i]) + break; + } + + /* Enable UART */ + *pUART_GCTL |= UART_GCTL_UCEN; + asm("ssync;"); + + /* Set DLAB in LCR to Access DLL and DLH */ + ACCESS_LATCH; + asm("ssync;"); + + *pUART_DLL = hw_baud_table[i].dl_low; + asm("ssync;"); + *pUART_DLH = hw_baud_table[i].dl_high; + asm("ssync;"); + + /* Clear DLAB in LCR to Access THR RBR IER */ + ACCESS_PORT_IER; + asm("ssync;"); + + /* Enable ERBFI and ELSI interrupts + * to poll SIC_ISR register*/ + *pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI; + asm("ssync;"); + + /* Set LCR to Word Lengh 8-bit word select */ + *pUART_LCR = UART_LCR_WLS8; + asm("ssync;"); + + return; +} + +int serial_init(void) +{ + serial_setbrg(); + return (0); +} + +void serial_putc(const char c) +{ + if ((*pUART_LSR) & UART_LSR_TEMT) + { + if (c == '\n') + serial_putc('\r'); + + local_put_char(c); + } + + while (!((*pUART_LSR) & UART_LSR_TEMT)) + SYNC_ALL; + + return; +} + +int serial_tstc(void) +{ + if (*pUART_LSR & UART_LSR_DR) + return 1; + else + return 0; +} + +int serial_getc(void) +{ + unsigned short uart_lsr_val, uart_rbr_val; + unsigned long isr_val; + int ret; + + /* Poll for RX Interrupt */ + while (!((isr_val = *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)); + asm("csync;"); + + uart_lsr_val = *pUART_LSR; /* Clear status bit */ + uart_rbr_val = *pUART_RBR; /* getc() */ + + if (isr_val & IRQ_UART_ERROR_BIT) { + ret = -1; + } + else + { + ret = uart_rbr_val & 0xff; + } + + return ret; +} + +void serial_puts(const char *s) +{ + while (*s) { + serial_putc(*s++); + } +} + +static void local_put_char(char ch) +{ + int flags = 0; + unsigned long isr_val; + + save_and_cli(flags); + + /* Poll for TX Interruput */ + while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)); + asm("csync;"); + + *pUART_THR = ch; /* putc() */ + + if (isr_val & IRQ_UART_ERROR_BIT) { + printf("?"); + } + + restore_flags(flags); + + return ; +} diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S new file mode 100644 index 0000000..6d58575 --- /dev/null +++ b/cpu/bf533/start.S @@ -0,0 +1,435 @@ +/* + * U-boot - start.S Startup file of u-boot for BF533 + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on head.S + * Copyright (c) 2003 Metrowerks/Motorola + * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>, + * Kenneth Albanowski <kjahds@kjahds.com>, + * The Silver Hammer Group, Ltd. + * (c) 1995, Dionne & Associates + * (c) 1995, DKG Display Tech. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Note: A change in this file subsequently requires a change in + * board/$(board_name)/config.mk for a valid u-boot.bin + */ + +#define ASSEMBLY + +#include <linux/config.h> +#include <asm/blackfin.h> +#include <config.h> +#include <asm/mem_init.h> + +#if (CONFIG_CCLK_DIV == 1) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 +#endif +#if (CONFIG_CCLK_DIV == 2) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 +#endif +#if (CONFIG_CCLK_DIV == 4) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 +#endif +#if (CONFIG_CCLK_DIV == 8) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 +#endif +#ifndef CONFIG_CCLK_ACT_DIV +#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly +#endif + +.global _stext; +.global __bss_start; +.global start; +.global _start; +.global _rambase; +.global _ramstart; +.global _ramend; +.global _bf533_data_dest; +.global _bf533_data_size; +.global edata; +.global _initialize; +.global _exit; +.global flashdataend; + +.text +_start: +start: +_stext: + + R0 = 0x30; + SYSCFG = R0; + SSYNC; + + /* As per HW reference manual DAG registers, + * DATA and Address resgister shall be zero'd + * in initialization, after a reset state + */ + r1 = 0; /* Data registers zero'd */ + r2 = 0; + r3 = 0; + r4 = 0; + r5 = 0; + r6 = 0; + r7 = 0; + + p0 = 0; /* Address registers zero'd */ + p1 = 0; + p2 = 0; + p3 = 0; + p4 = 0; + p5 = 0; + + i0 = 0; /* DAG Registers zero'd */ + i1 = 0; + i2 = 0; + i3 = 0; + m0 = 0; + m1 = 0; + m3 = 0; + m3 = 0; + l0 = 0; + l1 = 0; + l2 = 0; + l3 = 0; + b0 = 0; + b1 = 0; + b2 = 0; + b3 = 0; + + /* Set loop counters to zero, to make sure that + * hw loops are disabled. + */ + lc0 = 0; + lc1 = 0; + + SSYNC; + + /* Check soft reset status */ + p0.h = SWRST >> 16; + p0.l = SWRST & 0xFFFF; + r0.l = w[p0]; + + cc = bittst(r0, 15); + if !cc jump no_soft_reset; + + /* Clear Soft reset */ + r0 = 0x0000; + w[p0] = r0; + ssync; + +no_soft_reset: + nop; + + /* Clear EVT registers */ + p0.h = (EVT_EMULATION_ADDR >> 16); + p0.l = (EVT_EMULATION_ADDR & 0xFFFF); + p0 += 8; + p1 = 14; + r1 = 0; + LSETUP(4,4) lc0 = p1; + [ p0 ++ ] = r1; + + /* + * Set PLL_CTL + * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors + * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK + * - [7] = output delay (add 200ps of delay to mem signals) + * - [6] = input delay (add 200ps of input delay to mem signals) + * - [5] = PDWN : 1=All Clocks off + * - [3] = STOPCK : 1=Core Clock off + * - [1] = PLL_OFF : 1=Disable Power to PLL + * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL + * all other bits set to zero + */ + + r0 = CONFIG_VCO_MULT; /* Load the VCO multiplier */ + r0 = r0 << 9; /* Shift it over */ + r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2? */ + r0 = r1 | r0; + r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */ + r1 = r1 << 8; /* Shift it over */ + r0 = r1 | r0; /* add them all together */ + + p0.h = (PLL_CTL >> 16); + p0.l = (PLL_CTL & 0xFFFF); /* Load the address */ + cli r2; /* Disable interrupts */ + w[p0] = r0; /* Set the value */ + idle; /* Wait for the PLL to stablize */ + sti r2; /* Enable interrupts */ + ssync; + + /* + * Turn on the CYCLES COUNTER + */ + r2 = SYSCFG; + BITSET (r2,1); + SYSCFG = r2; + + /* Configure SCLK & CCLK Dividers */ + r0 = CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV; + p0.h = (PLL_DIV >> 16); + p0.l = (PLL_DIV & 0xFFFF); + w[p0] = r0; + ssync; + +wait_for_pll_stab: + p0.h = (PLL_STAT >> 16); + p0.l = (PLL_STAT & 0xFFFF); + r0.l = w[p0]; + cc = bittst(r0,5); + if !cc jump wait_for_pll_stab; + + /* Configure SDRAM if SDRAM is already not enabled */ + p0.l = (EBIU_SDSTAT & 0xFFFF); + p0.h = (EBIU_SDSTAT >> 16); + r0.l = w[p0]; + cc = bittst(r0, 3); + if !cc jump skip_sdram_enable; + + /* SDRAM initialization */ + p0.l = (EBIU_SDGCTL & 0xFFFF); + p0.h = (EBIU_SDGCTL >> 16); /* SDRAM Memory Global Control Register */ + r0.h = (mem_SDGCTL >> 16); + r0.l = (mem_SDGCTL & 0xFFFF); + [p0] = r0; + ssync; + + p0.l = (EBIU_SDBCTL & 0xFFFF); + p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */ + r0 = mem_SDBCTL; + w[p0] = r0.l; + ssync; + + p0.l = (EBIU_SDRRC & 0xFFFF); + p0.h = (EBIU_SDRRC >> 16); /* SDRAM Refresh Rate Control Register */ + r0 = mem_SDRRC; + w[p0] = r0.l; + ssync; + +skip_sdram_enable: + nop; + +#ifndef CFG_NO_FLASH + /* relocate into to RAM */ + p1.l = (CFG_FLASH_BASE & 0xffff); + p1.h = (CFG_FLASH_BASE >> 16); + p2.l = (CFG_MONITOR_BASE & 0xffff); + p2.h = (CFG_MONITOR_BASE >> 16); + r0.l = (CFG_MONITOR_LEN & 0xffff); + r0.h = (CFG_MONITOR_LEN >> 16); +loop1: + r1 = [p1]; + [p2] = r1; + p3=0x4; + p1=p1+p3; + p2=p2+p3; + r2=0x4; + r0=r0-r2; + cc=r0==0x0; + if !cc jump loop1; +#endif + /* + * configure STACK + */ + r0.h = (CONFIG_STACKBASE >> 16); + r0.l = (CONFIG_STACKBASE & 0xFFFF); + sp = r0; + fp = sp; + + /* + * This next section keeps the processor in supervisor mode + * during kernel boot. Switches to user mode at end of boot. + * See page 3-9 of Hardware Reference manual for documentation. + */ + + /* To keep ourselves in the supervisor mode */ + p0.l = (EVT_IVG15_ADDR & 0xFFFF); + p0.h = (EVT_IVG15_ADDR >> 16); + + p1.l = _real_start; + p1.h = _real_start; + [p0] = p1; + + p0.l = (IMASK & 0xFFFF); + p0.h = (IMASK >> 16); + r0 = IVG15_POS; + [p0] = r0; + raise 15; + p0.l = WAIT_HERE; + p0.h = WAIT_HERE; + reti = p0; + rti; + +WAIT_HERE: + jump WAIT_HERE; + +.global _real_start; +_real_start: + [ -- sp ] = reti; + +#ifdef CONFIG_EZKIT533 + p0.l = (WDOG_CTL & 0xFFFF); + p0.h = (WDOG_CTL >> 16); + r0 = WATCHDOG_DISABLE(z); + w[p0] = r0; +#endif + + /* Code for initializing Async mem banks */ + p2.h = (EBIU_AMBCTL1 >> 16); + p2.l = (EBIU_AMBCTL1 & 0xFFFF); + r0.h = (AMBCTL1VAL >> 16); + r0.l = (AMBCTL1VAL & 0xFFFF); + [p2] = r0; + ssync; + + p2.h = (EBIU_AMBCTL0 >> 16); + p2.l = (EBIU_AMBCTL0 & 0xFFFF); + r0.h = (AMBCTL0VAL >> 16); + r0.l = (AMBCTL0VAL & 0xFFFF); + [p2] = r0; + ssync; + + p2.h = (EBIU_AMGCTL >> 16); + p2.l = (EBIU_AMGCTL & 0xffff); + r0 = AMGCTLVAL; + w[p2] = r0; + ssync; + + /* DMA reset code to Hi of L1 SRAM */ +copy: + P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */ + P1.L = lo(SYSMMR_BASE); + + R0.H = reset_start; /* Source Address (high) */ + R0.L = reset_start; /* Source Address (low) */ + R1.H = reset_end; + R1.L = reset_end; + R2 = R1 - R0; /* Count */ + R1.H = hi(L1_ISRAM); /* Destination Address (high) */ + R1.L = lo(L1_ISRAM); /* Destination Address (low) */ + R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ + R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */ + +DMA: + R6 = 0x1 (Z); + W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */ + W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */ + + [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */ + W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */ + /* Set Source DMAConfig = DMA Enable, + Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */ + W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3; + + [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */ + W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */ + /* Set Destination DMAConfig = DMA Enable, + Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */ + W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4; + + IDLE; /* Wait for DMA to Complete */ + + R0 = 0x1; + W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */ + + /* DMA reset code to DATA BANK A which uses this port + * to avoid following problem + * " Data from a Data Cache fill can be corrupoted after or during + * instruction DMA if certain core stalls exist" + */ + +copy_as_data: + R0.H = reset_start; /* Source Address (high) */ + R0.L = reset_start; /* Source Address (low) */ + R1.H = reset_end; + R1.L = reset_end; + R2 = R1 - R0; /* Count */ + R1.H = hi(DATA_BANKA_SRAM); /* Destination Address (high) */ + R1.L = lo(DATA_BANKA_SRAM); /* Destination Address (low) */ + R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ + R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */ + +DMA_DATA: + R6 = 0x1 (Z); + W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */ + W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */ + + [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */ + W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */ + /* Set Source DMAConfig = DMA Enable, + Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */ + W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3; + + [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */ + W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */ + /* Set Destination DMAConfig = DMA Enable, + Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */ + W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4; + + IDLE; /* Wait for DMA to Complete */ + + R0 = 0x1; + W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */ + +copy_end: nop; + + /* Initialize BSS Section with 0 s */ + p1.l = __bss_start; + p1.h = __bss_start; + p2.l = _end; + p2.h = _end; + r1 = p1; + r2 = p2; + r3 = r2 - r1; + r3 = r3 >> 2; + p3 = r3; + lsetup (_clear_bss, _clear_bss_end ) lc1 = p3; + CC = p2<=p1; + if CC jump _clear_bss_skip; + r0 = 0; +_clear_bss: +_clear_bss_end: + [p1++] = r0; +_clear_bss_skip: + + p0.l = _start1; + p0.h = _start1; + jump (p0); + +reset_start: + p0.h = WDOG_CNT >> 16; + p0.l = WDOG_CNT & 0xffff; + r0 = 0x0010; + w[p0] = r0; + p0.h = WDOG_CTL >> 16; + p0.l = WDOG_CTL & 0xffff; + r0 = 0x0000; + w[p0] = r0; +reset_wait: + jump reset_wait; + +reset_end: nop; + +_exit: + jump.s _exit; diff --git a/cpu/bf533/start1.S b/cpu/bf533/start1.S new file mode 100644 index 0000000..6f48124 --- /dev/null +++ b/cpu/bf533/start1.S @@ -0,0 +1,38 @@ +/* + * U-boot - start1.S Code running out of RAM after relocation + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define ASSEMBLY +#include <linux/config.h> +#include <asm/blackfin.h> +#include <config.h> + +.global start1; +.global _start1; + +.text +_start1: +start1: + sp += -12; + call board_init_f; + sp += 12; diff --git a/cpu/bf533/traps.c b/cpu/bf533/traps.c new file mode 100644 index 0000000..37470d5 --- /dev/null +++ b/cpu/bf533/traps.c @@ -0,0 +1,73 @@ +/* + * U-boot - traps.c Routines related to interrupts and exceptions + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * No original Copyright holder listed, + * Probabily original (C) Roman Zippel (assigned DJD, 1999) + * + * Copyright 2003 Metrowerks - for Blackfin + * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca> + * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org> + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/types.h> +#include <asm/errno.h> +#include <asm/irq.h> +#include <asm/system.h> +#include <asm/traps.h> +#include <asm/page.h> +#include <asm/machdep.h> +#include "cpu.h" + +void init_IRQ(void) +{ + blackfin_init_IRQ(); + return; +} + +void process_int(unsigned long vec, struct pt_regs *fp) +{ + return; +} + +void dump(struct pt_regs *fp) +{ + printf("PC: %08lx\n", fp->pc); + printf("SEQSTAT: %08lx SP: %08lx\n", (long) fp->seqstat, + (long) fp); + printf("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n", + fp->r0, fp->r1, fp->r2, fp->r3); + printf("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n", + fp->r4, fp->r5, fp->r6, fp->r7); + printf("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n", + fp->p0, fp->p1, fp->p2, fp->p3); + printf("P4: %08lx P5: %08lx FP: %08lx\n", fp->p4, fp->p5, + fp->fp); + printf("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n", + fp->a0w, fp->a0x, fp->a1w, fp->a1x); + printf("\n"); +} diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c index 86c8ce6..2e8e549 100644 --- a/cpu/mpc5xxx/fec.c +++ b/cpu/mpc5xxx/fec.c @@ -880,8 +880,9 @@ int mpc5xxx_fec_initialize(bd_t * bis) fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD)); #if defined(CONFIG_CANMB) || defined(CONFIG_HMI1001) || \ defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \ + defined(CONFIG_MCC200) || defined(CONFIG_O2DNT) || \ defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \ - defined(CONFIG_TQM5200) || defined(CONFIG_O2DNT) + defined(CONFIG_TQM5200) # ifndef CONFIG_FEC_10MBIT fec->xcv_type = MII100; # else diff --git a/cpu/mpc8260/speed.c b/cpu/mpc8260/speed.c index a761a17..99afe76 100644 --- a/cpu/mpc8260/speed.c +++ b/cpu/mpc8260/speed.c @@ -163,7 +163,7 @@ int prt_8260_clks (void) volatile immap_t *immap = (immap_t *) CFG_IMMR; ulong sccr, dfbrg; - ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf; + ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf, pcidf; corecnf_t *cp; sccr = immap->im_clkrst.car_sccr; @@ -175,6 +175,7 @@ int prt_8260_clks (void) cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT; plldf = (scmr & SCMR_PLLDF) ? 1 : 0; pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT; + pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT; cp = &corecnf_tab[corecnf]; @@ -204,8 +205,9 @@ int prt_8260_clks (void) cp->vco_div, cp->freq_60x, cp->freq_core); printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, " - "plldf %ld, pllmf %ld\n", dfbrg, corecnf, busdf, cpmdf, plldf, - pllmf); + "plldf %ld, pllmf %ld, pcidf %ld\n", + dfbrg, corecnf, busdf, cpmdf, + plldf, pllmf, pcidf); printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n", gd->vco_out, gd->scc_clk, gd->brg_clk); @@ -215,9 +217,20 @@ int prt_8260_clks (void) if (sccr & SCCR_PCI_MODE) { uint pci_div; - - pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) * - ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1); + uint pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT; + + if (sccr & SCCR_PCI_MODCK) { + pci_div = 2; + if (pcidf == 9) { + pci_div *= 5; + } else if (pcidf == 0xB) { + pci_div *= 6; + } else { + pci_div *= (pcidf + 1); + } + } else { + pci_div = pcidf + 1; + } printf (" - pci_clk %10ld\n", (gd->cpm_clk * 2) / pci_div); } @@ -225,5 +238,3 @@ int prt_8260_clks (void) return (0); } - -/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 8c9b515..e49e4fe 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -35,6 +35,7 @@ #include <watchdog.h> #include <command.h> #include <mpc83xx.h> +#include <ft_build.h> #include <asm/processor.h> @@ -151,3 +152,40 @@ void watchdog_reset (void) hang(); /* FIXME: implement watchdog_reset()? */ } #endif /* CONFIG_WATCHDOG */ + +#if defined(CONFIG_OF_FLAT_TREE) +void +ft_cpu_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + ulong clock; + + clock = bd->bi_busfreq; + p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + + p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + + p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + + p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + +#ifdef CONFIG_MPC83XX_TSEC1 + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len); + memcpy(p, bd->bi_enetaddr, 6); +#endif + +#ifdef CONFIG_MPC83XX_TSEC2 + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len); + memcpy(p, bd->bi_enet1addr, 6); +#endif +} +#endif diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index dcb3445..acf6862 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -63,8 +63,12 @@ void cpu_init_f (volatile immap_t * im) im->sysconf.spcr |= SPCR_TBEN; /* System General Purpose Register */ - im->sysconf.sicrh = SICRH_TSOBI1; - im->sysconf.sicrl = SICRL_LDP_A; +#ifdef CFG_SICRH + im->sysconf.sicrh = CFG_SICRH; +#endif +#ifdef CFG_SICRL + im->sysconf.sicrl = CFG_SICRL; +#endif /* * Memory Controller: @@ -87,69 +91,70 @@ void cpu_init_f (volatile immap_t * im) #error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined #endif -#if defined(CFG_BR1_PRELIM) \ - && defined(CFG_OR1_PRELIM) \ - && defined(CFG_LBLAWBAR1_PRELIM) \ - && defined(CFG_LBLAWAR1_PRELIM) +#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) im->lbus.bank[1].br = CFG_BR1_PRELIM; im->lbus.bank[1].or = CFG_OR1_PRELIM; +#endif +#if defined(CFG_LBLAWBAR1_PRELIM) && defined(CFG_LBLAWAR1_PRELIM) im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM; im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM; #endif -#if defined(CFG_BR2_PRELIM) \ - && defined(CFG_OR2_PRELIM) \ - && defined(CFG_LBLAWBAR2_PRELIM) \ - && defined(CFG_LBLAWAR2_PRELIM) +#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) im->lbus.bank[2].br = CFG_BR2_PRELIM; im->lbus.bank[2].or = CFG_OR2_PRELIM; +#endif +#if defined(CFG_LBLAWBAR2_PRELIM) && defined(CFG_LBLAWAR2_PRELIM) im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM; im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM; #endif -#if defined(CFG_BR3_PRELIM) \ - && defined(CFG_OR3_PRELIM) \ - && defined(CFG_LBLAWBAR3_PRELIM) \ - && defined(CFG_LBLAWAR3_PRELIM) +#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) im->lbus.bank[3].br = CFG_BR3_PRELIM; im->lbus.bank[3].or = CFG_OR3_PRELIM; +#endif +#if defined(CFG_LBLAWBAR3_PRELIM) && defined(CFG_LBLAWAR3_PRELIM) im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM; im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM; #endif -#if defined(CFG_BR4_PRELIM) \ - && defined(CFG_OR4_PRELIM) \ - && defined(CFG_LBLAWBAR4_PRELIM) \ - && defined(CFG_LBLAWAR4_PRELIM) +#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) im->lbus.bank[4].br = CFG_BR4_PRELIM; im->lbus.bank[4].or = CFG_OR4_PRELIM; +#endif +#if defined(CFG_LBLAWBAR4_PRELIM) && defined(CFG_LBLAWAR4_PRELIM) im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM; im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM; #endif -#if defined(CFG_BR5_PRELIM) \ - && defined(CFG_OR5_PRELIM) \ - && defined(CFG_LBLAWBAR5_PRELIM) \ - && defined(CFG_LBLAWAR5_PRELIM) +#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) im->lbus.bank[5].br = CFG_BR5_PRELIM; im->lbus.bank[5].or = CFG_OR5_PRELIM; +#endif +#if defined(CFG_LBLAWBAR5_PRELIM) && defined(CFG_LBLAWAR5_PRELIM) im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM; im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM; #endif -#if defined(CFG_BR6_PRELIM) \ - && defined(CFG_OR6_PRELIM) \ - && defined(CFG_LBLAWBAR6_PRELIM) \ - && defined(CFG_LBLAWAR6_PRELIM) +#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM) im->lbus.bank[6].br = CFG_BR6_PRELIM; im->lbus.bank[6].or = CFG_OR6_PRELIM; +#endif +#if defined(CFG_LBLAWBAR6_PRELIM) && defined(CFG_LBLAWAR6_PRELIM) im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM; im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM; #endif -#if defined(CFG_BR7_PRELIM) \ - && defined(CFG_OR7_PRELIM) \ - && defined(CFG_LBLAWBAR7_PRELIM) \ - && defined(CFG_LBLAWAR7_PRELIM) +#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM) im->lbus.bank[7].br = CFG_BR7_PRELIM; im->lbus.bank[7].or = CFG_OR7_PRELIM; +#endif +#if defined(CFG_LBLAWBAR7_PRELIM) && defined(CFG_LBLAWAR7_PRELIM) im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM; im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM; #endif +#ifdef CFG_GPIO1_PRELIM + im->pgio[0].dir = CFG_GPIO1_DIR; + im->pgio[0].dat = CFG_GPIO1_DAT; +#endif +#ifdef CFG_GPIO2_PRELIM + im->pgio[1].dir = CFG_GPIO2_DIR; + im->pgio[1].dat = CFG_GPIO2_DAT; +#endif } diff --git a/cpu/mpc83xx/interrupts.c b/cpu/mpc83xx/interrupts.c index 53474f6..dfd51c1 100644 --- a/cpu/mpc83xx/interrupts.c +++ b/cpu/mpc83xx/interrupts.c @@ -43,6 +43,16 @@ struct irq_action { int interrupt_init_cpu (unsigned *decrementer_count) { + DECLARE_GLOBAL_DATA_PTR; + + volatile immap_t *immr = (immap_t *) CFG_IMMRBAR; + + *decrementer_count = (gd->bus_clk / 4) / CFG_HZ; + + /* Enable e300 time base */ + + immr->sysconf.spcr |= 0x00400000; + return 0; } diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index fb001a6..46c748f 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -179,10 +179,47 @@ in_flash: #endif #endif /* CFG_RAMBOOT */ - bl setup_stack_in_data_cache_on_r1 + /* setup the bats */ + bl setup_bats + sync + + /* + * Cache must be enabled here for stack-in-cache trick. + * This means we need to enable the BATS. + * This means: + * 1) for the EVB, original gt regs need to be mapped + * 2) need to have an IBAT for the 0xf region, + * we are running there! + * Cache should be turned on after BATs, since by default + * everything is write-through. + * The init-mem BAT can be reused after reloc. The old + * gt-regs BAT can be reused after board_init_f calls + * board_early_init_f (EVB only). + */ + /* enable address translation */ + bl enable_addr_trans + sync + + /* enable and invalidate the data cache */ + bl dcache_enable + sync +#ifdef CFG_INIT_RAM_LOCK + bl lock_ram_in_cache + sync +#endif + + /* set up the stack pointer in our newly created + * cache-ram (r1) */ + lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h + ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l + + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + /* let the C-code set up the rest */ - /* */ + /* */ /* Be careful to keep code relocatable & stack humble */ /*------------------------------------------------------*/ @@ -426,8 +463,14 @@ init_e300_core: /* time t 10 */ #else /* Disable Wathcdog */ /*-------------------*/ + lwz r4, SWCRR(r3) + /* Check to see if its enabled for disabling + once disabled by SW you can't re-enable */ + andi. r4, r4, 0x4 + beq 1f xor r4, r4, r4 stw r4, SWCRR(r3) +1: #endif /* CONFIG_WATCHDOG */ /* Initialize the Hardware Implementation-dependent Registers */ @@ -503,6 +546,221 @@ init_e300_core: /* time t 10 */ /*------------------------------*/ blr + .globl invalidate_bats +invalidate_bats: + /* invalidate BATs */ + mtspr IBAT0U, r0 + mtspr IBAT1U, r0 + mtspr IBAT2U, r0 + mtspr IBAT3U, r0 +#if (CFG_HID2 & HID2_HBE) + mtspr IBAT4U, r0 + mtspr IBAT5U, r0 + mtspr IBAT6U, r0 + mtspr IBAT7U, r0 +#endif + isync + mtspr DBAT0U, r0 + mtspr DBAT1U, r0 + mtspr DBAT2U, r0 + mtspr DBAT3U, r0 +#if (CFG_HID2 & HID2_HBE) + mtspr DBAT4U, r0 + mtspr DBAT5U, r0 + mtspr DBAT6U, r0 + mtspr DBAT7U, r0 +#endif + isync + sync + blr + + /* setup_bats - set them up to some initial state */ + .globl setup_bats +setup_bats: + addis r0, r0, 0x0000 + + /* IBAT 0 */ + addis r4, r0, CFG_IBAT0L@h + ori r4, r4, CFG_IBAT0L@l + addis r3, r0, CFG_IBAT0U@h + ori r3, r3, CFG_IBAT0U@l + mtspr IBAT0L, r4 + mtspr IBAT0U, r3 + isync + + /* DBAT 0 */ + addis r4, r0, CFG_DBAT0L@h + ori r4, r4, CFG_DBAT0L@l + addis r3, r0, CFG_DBAT0U@h + ori r3, r3, CFG_DBAT0U@l + mtspr DBAT0L, r4 + mtspr DBAT0U, r3 + isync + + /* IBAT 1 */ + addis r4, r0, CFG_IBAT1L@h + ori r4, r4, CFG_IBAT1L@l + addis r3, r0, CFG_IBAT1U@h + ori r3, r3, CFG_IBAT1U@l + mtspr IBAT1L, r4 + mtspr IBAT1U, r3 + isync + + /* DBAT 1 */ + addis r4, r0, CFG_DBAT1L@h + ori r4, r4, CFG_DBAT1L@l + addis r3, r0, CFG_DBAT1U@h + ori r3, r3, CFG_DBAT1U@l + mtspr DBAT1L, r4 + mtspr DBAT1U, r3 + isync + + /* IBAT 2 */ + addis r4, r0, CFG_IBAT2L@h + ori r4, r4, CFG_IBAT2L@l + addis r3, r0, CFG_IBAT2U@h + ori r3, r3, CFG_IBAT2U@l + mtspr IBAT2L, r4 + mtspr IBAT2U, r3 + isync + + /* DBAT 2 */ + addis r4, r0, CFG_DBAT2L@h + ori r4, r4, CFG_DBAT2L@l + addis r3, r0, CFG_DBAT2U@h + ori r3, r3, CFG_DBAT2U@l + mtspr DBAT2L, r4 + mtspr DBAT2U, r3 + isync + + /* IBAT 3 */ + addis r4, r0, CFG_IBAT3L@h + ori r4, r4, CFG_IBAT3L@l + addis r3, r0, CFG_IBAT3U@h + ori r3, r3, CFG_IBAT3U@l + mtspr IBAT3L, r4 + mtspr IBAT3U, r3 + isync + + /* DBAT 3 */ + addis r4, r0, CFG_DBAT3L@h + ori r4, r4, CFG_DBAT3L@l + addis r3, r0, CFG_DBAT3U@h + ori r3, r3, CFG_DBAT3U@l + mtspr DBAT3L, r4 + mtspr DBAT3U, r3 + isync + +#if (CFG_HID2 & HID2_HBE) + /* IBAT 4 */ + addis r4, r0, CFG_IBAT4L@h + ori r4, r4, CFG_IBAT4L@l + addis r3, r0, CFG_IBAT4U@h + ori r3, r3, CFG_IBAT4U@l + mtspr IBAT4L, r4 + mtspr IBAT4U, r3 + isync + + /* DBAT 4 */ + addis r4, r0, CFG_DBAT4L@h + ori r4, r4, CFG_DBAT4L@l + addis r3, r0, CFG_DBAT4U@h + ori r3, r3, CFG_DBAT4U@l + mtspr DBAT4L, r4 + mtspr DBAT4U, r3 + isync + + /* IBAT 5 */ + addis r4, r0, CFG_IBAT5L@h + ori r4, r4, CFG_IBAT5L@l + addis r3, r0, CFG_IBAT5U@h + ori r3, r3, CFG_IBAT5U@l + mtspr IBAT5L, r4 + mtspr IBAT5U, r3 + isync + + /* DBAT 5 */ + addis r4, r0, CFG_DBAT5L@h + ori r4, r4, CFG_DBAT5L@l + addis r3, r0, CFG_DBAT5U@h + ori r3, r3, CFG_DBAT5U@l + mtspr DBAT5L, r4 + mtspr DBAT5U, r3 + isync + + /* IBAT 6 */ + addis r4, r0, CFG_IBAT6L@h + ori r4, r4, CFG_IBAT6L@l + addis r3, r0, CFG_IBAT6U@h + ori r3, r3, CFG_IBAT6U@l + mtspr IBAT6L, r4 + mtspr IBAT6U, r3 + isync + + /* DBAT 6 */ + addis r4, r0, CFG_DBAT6L@h + ori r4, r4, CFG_DBAT6L@l + addis r3, r0, CFG_DBAT6U@h + ori r3, r3, CFG_DBAT6U@l + mtspr DBAT6L, r4 + mtspr DBAT6U, r3 + isync + + /* IBAT 7 */ + addis r4, r0, CFG_IBAT7L@h + ori r4, r4, CFG_IBAT7L@l + addis r3, r0, CFG_IBAT7U@h + ori r3, r3, CFG_IBAT7U@l + mtspr IBAT7L, r4 + mtspr IBAT7U, r3 + isync + + /* DBAT 7 */ + addis r4, r0, CFG_DBAT7L@h + ori r4, r4, CFG_DBAT7L@l + addis r3, r0, CFG_DBAT7U@h + ori r3, r3, CFG_DBAT7U@l + mtspr DBAT7L, r4 + mtspr DBAT7U, r3 + isync +#endif + + /* Invalidate TLBs. + * -> for (val = 0; val < 0x20000; val+=0x1000) + * -> tlbie(val); + */ + lis r3, 0 + lis r5, 2 + +1: + tlbie r3 + addi r3, r3, 0x1000 + cmp 0, 0, r3, r5 + blt 1b + + blr + + .globl enable_addr_trans +enable_addr_trans: + /* enable address translation */ + mfmsr r5 + ori r5, r5, (MSR_IR | MSR_DR) + mtmsr r5 + isync + blr + + .globl disable_addr_trans +disable_addr_trans: + /* disable address translation */ + mflr r4 + mfmsr r3 + andi. r0, r3, (MSR_IR | MSR_DR) + beqlr + andc r3, r3, r0 + mtspr SRR0, r4 + mtspr SRR1, r3 + rfi + /* Cache functions. * * Note: requires that all cache bits in @@ -544,26 +802,25 @@ icache_status: .globl dcache_enable dcache_enable: mfspr r3, HID0 - ori r3, r3, HID0_ENABLE_DATA_CACHE - lis r4, 0 - ori r4, r4, HID0_LOCK_DATA_CACHE - andc r3, r3, r4 - ori r4, r3, HID0_LOCK_INSTRUCTION_CACHE + li r5, HID0_DCFI|HID0_DLOCK + andc r3, r3, r5 + mtspr HID0, r3 /* no invalidate, unlock */ + ori r3, r3, HID0_DCE + ori r5, r3, HID0_DCFI + mtspr HID0, r5 /* enable + invalidate */ + mtspr HID0, r3 /* enable */ sync - mtspr HID0, r4 /* sets enable and invalidate, clears lock */ - sync - mtspr HID0, r3 /* clears invalidate */ blr .globl dcache_disable dcache_disable: mfspr r3, HID0 lis r4, 0 - ori r4, r4, HID0_ENABLE_DATA_CACHE|HID0_LOCK_DATA_CACHE + ori r4, r4, HID0_DCE|HID0_DLOCK andc r3, r3, r4 - ori r4, r3, HID0_INVALIDATE_DATA_CACHE + ori r4, r3, HID0_DCI sync - mtspr HID0, r4 /* sets invalidate, clears enable and lock */ + mtspr HID0, r4 /* sets invalidate, clears enable and lock */ sync mtspr HID0, r3 /* clears invalidate */ blr @@ -668,46 +925,29 @@ relocate_code: * Now flush the cache: note that we must start from a cache aligned * address. Otherwise we might miss one cache line. */ -4: - bl un_setup_stack_in_data_cache - mr r7, r3 - mr r8, r4 - bl dcache_disable - mr r3, r7 - mr r4, r8 - - cmpwi r6,0 +4: cmpwi r6,0 add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ + beq 7f /* Always flush prefetch queue in any case */ subi r0,r6,1 andc r3,r3,r0 - mfspr r7,HID0 /* don't do dcbst if dcache is disabled*/ - rlwinm r7,r7,HID0_DCE_SHIFT,31,31 - cmpwi r7,0 - beq 9f mr r4,r3 5: dcbst 0,r4 add r4,r4,r6 cmplw r4,r5 blt 5b - sync /* Wait for all dcbst to complete on bus */ -9: mfspr r7,HID0 /* don't do icbi if icache is disabled */ - rlwinm r7,r7,HID0_DCE_SHIFT,31,31 - cmpwi r7,0 - beq 7f + sync /* Wait for all dcbst to complete on bus */ mr r4,r3 6: icbi 0,r4 add r4,r4,r6 cmplw r4,r5 blt 6b -7: sync /* Wait for all icbi to complete on bus */ +7: sync /* Wait for all icbi to complete on bus */ isync /* * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET mtlr r0 blr @@ -865,6 +1105,27 @@ trap_reloc: blr #ifdef CFG_INIT_RAM_LOCK +lock_ram_in_cache: + /* Allocate Initial RAM in data cache. + */ + lis r3, (CFG_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l + li r2, ((CFG_INIT_RAM_END & ~31) + \ + (CFG_INIT_RAM_ADDR & 31) + 31) / 32 + mtctr r2 +1: + dcbz r0, r3 + addi r3, r3, 32 + bdnz 1b + + /* Lock the data cache */ + mfspr r0, HID0 + ori r0, r0, 0x1000 + sync + mtspr HID0, r0 + sync + blr + .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ @@ -878,6 +1139,15 @@ unlock_ram_in_cache: bdnz 1b sync /* Wait for all icbi to complete on bus */ isync + + /* Unlock the data cache and invalidate it */ + mfspr r3, HID0 + li r5, HID0_DLOCK|HID0_DCFI + andc r3, r3, r5 /* no invalidate, unlock */ + ori r5, r3, HID0_DCFI /* invalidate, unlock */ + mtspr HID0, r5 /* invalidate, unlock */ + mtspr HID0, r3 /* no invalidate, unlock */ + sync blr #endif @@ -946,148 +1216,3 @@ remap_flash_by_law0: stw r4, LBLAWBAR1(r3) stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ blr - -setup_stack_in_data_cache_on_r1: - lis r3, (CFG_IMMRBAR)@h - - /* setup D-BAT for the D-Cache (with out real memory backup) */ - - lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h - mtspr DBAT0U, r4 - ori r4, r4, 0x0002 - mtspr DBAT0L, r4 - isync - -#if 0 - /* Enable MMU */ - mfmsr r4 - ori r4, r4, (MSR_DR | MSR_IR)@l - mtmsr r4 -#endif - - /* Enable and invalidate data cache. */ - mfspr r4, HID0 - mr r5, r4 - ori r4, r4, HID0_DCE | HID0_DCI - ori r5, r5, HID0_DCE - sync - mtspr HID0, r4 - mtspr HID0, r5 - sync - - /* Allocate Initial RAM in data cache.*/ - li r0, 0 - lis r4, (CFG_INIT_RAM_ADDR)@h - ori r4, r4, (CFG_INIT_RAM_ADDR)@l - li r5, 128*8 /* 128*8*32=32Kb */ - mtctr r5 -1: - dcbz r0, r4 - addi r4, r4, 32 - bdnz 1b - isync - - /* Lock all the D-cache, basically leaving the reset of the program without dcache */ - mfspr r4, HID0 - ori r4, r4, (HID0_DLOCK)@l - sync - mtspr HID0 , r4 - - /* setup the stack pointer in r1 */ - lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h - ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l - li r0, 0 /* Make room for stack frame header and */ - - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - blr - -un_setup_stack_in_data_cache: - blr - mr r14, r4 - mr r15, r5 - - - lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h - mtspr DBAT0U, r4 - ori r4, r4, 0x0002 - mtspr DBAT0L, r4 - isync - - /* un lock all the D-cache */ - mfspr r4, HID0 - lis r5, (~(HID0_DLOCK))@h - ori r5, r5, (~(HID0_DLOCK))@l - and r4, r4, r5 - sync - mtspr HID0 , r4 - - /* Re - Allocate Initial RAM in data cache.*/ - li r0, 0 - lis r4, (CFG_INIT_RAM_ADDR)@h - ori r4, r4, (CFG_INIT_RAM_ADDR)@l - li r5, 128*8 /* 128*8*32=32Kb */ - mtctr r5 -1: - dcbz r0, r4 - addi r4, r4, 32 - bdnz 1b - isync - - mflr r16 - bl dcache_disable - mtlr r16 - - blr - -#if 0 -#define GREEN_LIGHT 0x2B0D4046 -#define RED_LIGHT 0x250D4046 -#define LIB_CNT 0x4FFF - -/* - * Lib Light - */ - - .globl liblight -liblight: - lis r3, CFG_IMMRBAR@h - ori r3, r3, CFG_IMMRBAR@l - li r4, 0x3002 - mtmsr r4 - xor r4, r4, r4 - mtspr HID0, r4 - mtspr HID2, r4 - lis r4, 0xF8000000@h - ori r4, r4, 0xF8000000@l - stw r4, LBLAWBAR1(r3) - lis r4, 0x8000000E@h - ori r4, r4, 0x8000000E@l - stw r4, LBLAWAR1(r3) - lis r4, 0xF8000801@h - ori r4, r4, 0xF8000801@l - stw r4, BR1(r3) - lis r4, 0xFFFFE8f0@h - ori r4, r4, 0xFFFFE8f0@l - stw r4, OR1(r3) - - lis r4, 0xF8000000@h - ori r4, r4, 0xF8000000@l - lis r5, GREEN_LIGHT@h - ori r5, r5, GREEN_LIGHT@l - lis r6, RED_LIGHT@h - ori r6, r6, RED_LIGHT@l - lis r7, LIB_CNT@h - ori r7, r7, LIB_CNT@l - -1: - stw r5, 0(r4) - mtctr r7 -2: bdnz 2b - stw r6, 0(r4) - mtctr r7 -3: bdnz 3b - b 1b - -#endif diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index 64431ab..f6b29e9 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -81,6 +81,10 @@ #ifdef CONFIG_PCI +#if defined(CONFIG_PMC405) +ushort pmc405_pci_subsys_deviceid(void); +#endif + /*#define DEBUG*/ /*-----------------------------------------------------------------------------+ @@ -96,13 +100,10 @@ void pci_405gp_init(struct pci_controller *hose) unsigned short temp_short; unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI}; #if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) - unsigned long ptmla[2] = {bd->bi_memstart, bd->bi_flashstart}; - unsigned long ptmms[2] = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1}; char *ptmla_str, *ptmms_str; -#else +#endif unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA}; unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS}; -#endif #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405) unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0}; unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0}; diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c index d1551dd..b33d674 100644 --- a/cpu/pxa/cpu.c +++ b/cpu/pxa/cpu.c @@ -143,6 +143,7 @@ int dcache_status (void) return 0; /* always off */ } +#ifndef CONFIG_CPU_MONAHANS void set_GPIO_mode(int gpio_mode) { int gpio = gpio_mode & GPIO_MD_MASK_NR; @@ -160,3 +161,4 @@ void set_GPIO_mode(int gpio_mode) gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2)); GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2)); } +#endif /* CONFIG_CPU_MONAHANS */ diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c index cedebfe..9bf2a7c 100644 --- a/cpu/pxa/serial.c +++ b/cpu/pxa/serial.c @@ -54,7 +54,11 @@ void serial_setbrg (void) hang (); #ifdef CONFIG_FFUART +#ifdef CONFIG_CPU_MONAHANS + CKENA |= CKENA_22_FFUART; +#else CKEN |= CKEN6_FFUART; +#endif /* CONFIG_CPU_MONAHANS */ FFIER = 0; /* Disable for now */ FFFCR = 0; /* No fifos enabled */ @@ -68,7 +72,11 @@ void serial_setbrg (void) FFIER = IER_UUE; /* Enable FFUART */ #elif defined(CONFIG_BTUART) +#ifdef CONFIG_CPU_MONAHANS + CKENA |= CKENA_21_BTUART; +#else CKEN |= CKEN7_BTUART; +#endif /* CONFIG_CPU_MONAHANS */ BTIER = 0; BTFCR = 0; @@ -82,7 +90,11 @@ void serial_setbrg (void) BTIER = IER_UUE; /* Enable BFUART */ #elif defined(CONFIG_STUART) +#ifdef CONFIG_CPU_MONAHANS + CKENA |= CKENA_23_STUART; +#else CKEN |= CKEN5_STUART; +#endif /* CONFIG_CPU_MONAHANS */ STIER = 0; STFCR = 0; diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S index a8cc080..9541c9b 100644 --- a/cpu/pxa/start.S +++ b/cpu/pxa/start.S @@ -6,8 +6,8 @@ * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de> * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net> - * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> - * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> + * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> + * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> * * See file CREDITS for list of people who contributed to this * project. @@ -30,6 +30,7 @@ #include <config.h> #include <version.h> +#include <asm/arch/pxa-regs.h> .globl _start _start: b reset @@ -116,13 +117,13 @@ reset: relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ - beq stack_setup + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup ldr r2, _armboot_start ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ @@ -134,19 +135,19 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ +clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 ble clbss_l @@ -164,8 +165,16 @@ _start_armboot: .word start_armboot /* - setup memory timing */ /* */ /****************************************************************************/ +/* mk@tbd: Fix this! */ +#ifdef CONFIG_CPU_MONAHANS +#undef ICMR +#undef OSMR3 +#undef OSCR +#undef OWER +#undef OIER +#endif -/* Interrupt-Controller base address */ +/* Interrupt-Controller base address */ IC_BASE: .word 0x40d00000 #define ICMR 0x04 @@ -180,7 +189,7 @@ OSTIMER_BASE: .word 0x40a00000 #define OWER 0x18 #define OIER 0x1C -/* Clock Manager Registers */ +/* Clock Manager Registers */ #ifdef CFG_CPUSPEED CC_BASE: .word 0x41300000 #define CCCR 0x00 @@ -189,25 +198,44 @@ cpuspeed: .word CFG_CPUSPEED #error "You have to define CFG_CPUSPEED!!" #endif - - /* RS: ??? */ - .macro CPWAIT - mrc p15,0,r0,c2,c0,0 - mov r0,r0 + /* takes care the CP15 update has taken place */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg sub pc,pc,#4 .endm - cpu_init_crit: /* mask all IRQs */ +#ifndef CONFIG_CPU_MONAHANS ldr r0, IC_BASE mov r1, #0x00 str r1, [r0, #ICMR] +#else + /* Step 1 - Enable CP6 permission */ + mrc p15, 0, r1, c15, c1, 0 @ read CPAR + orr r1, r1, #0x40 + mcr p15, 0, r1, c15, c1, 0 + CPWAIT r1 + + /* Step 2 - Mask ICMR & ICMR2 */ + mov r1, #0 + mcr p6, 0, r1, c1, c0, 0 @ ICMR + mcr p6, 0, r1, c7, c0, 0 @ ICMR2 + + /* turn off all clocks but the ones we will definitly require */ + ldr r1, =CKENA + ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC) + str r2, [r1] + ldr r1, =CKENB + ldr r2, =(CKENB_6_IRQ) + str r2, [r1] +#endif -#if defined(CFG_CPUSPEED) - - /* set clock speed */ +#ifndef CONFIG_CPU_MONAHANS +#ifdef CFG_CPUSPEED + /* set clock speed tbd@mk: required for monahans? */ ldr r0, CC_BASE ldr r1, cpuspeed str r1, [r0, #CCCR] @@ -215,7 +243,9 @@ cpu_init_crit: mcr p14, 0, r0, c6, c0, 0 setspeed_done: -#endif + +#endif /* CFG_CPUSPEED */ +#endif /* CONFIG_CPU_MONAHANS */ /* * before relocating, we have to setup RAM timing @@ -227,19 +257,21 @@ setspeed_done: mov lr, ip /* Memory interfaces are working. Disable MMU and enable I-cache. */ + /* mk: hmm, this is not in the monahans docs, leave it now but + * check here if it doesn't work :-) */ ldr r0, =0x2001 /* enable access to all coproc. */ mcr p15, 0, r0, c15, c1, 0 - CPWAIT + CPWAIT r0 mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */ - CPWAIT + CPWAIT r0 mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */ - CPWAIT + CPWAIT r0 mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */ - CPWAIT + CPWAIT r0 /* Enable the Icache */ /* @@ -292,7 +324,7 @@ setspeed_done: ldr r2, _armboot_start sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ @@ -419,17 +451,17 @@ fiq: #endif /****************************************************************************/ -/* */ +/* */ /* Reset function: the PXA250 doesn't have a reset function, so we have to */ -/* perform a watchdog timeout for a soft reset. */ -/* */ +/* perform a watchdog timeout for a soft reset. */ +/* */ /****************************************************************************/ .align 5 .globl reset_cpu - /* FIXME: this code is PXA250 specific. How is this handled on */ - /* other XScale processors? */ + /* FIXME: this code is PXA250 specific. How is this handled on */ + /* other XScale processors? */ reset_cpu: @@ -437,13 +469,13 @@ reset_cpu: ldr r0, OSTIMER_BASE ldr r1, [r0, #OWER] - orr r1, r1, #0x0001 /* bit0: WME */ + orr r1, r1, #0x0001 /* bit0: WME */ str r1, [r0, #OWER] /* OS timer does only wrap every 1165 seconds, so we have to set */ - /* the match register as well. */ + /* the match register as well. */ - ldr r1, [r0, #OSCR] /* read OS timer */ + ldr r1, [r0, #OSCR] /* read OS timer */ add r1, r1, #0x800 /* let OSMR3 match after */ add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */ str r1, [r0, #OSMR3] diff --git a/doc/README.nand b/doc/README.nand index 0f2bdc5..f2d6a5b 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -1,5 +1,9 @@ NAND FLASH commands and notes + +See NOTE below!!! + + # (C) Copyright 2003 # Dave Ellis, SIXNET, dge@sixnetio.com # @@ -173,3 +177,33 @@ More Definitions: #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 + + +NOTE: +===== + +We now use a complete rewrite of the NAND code based on what is in +2.6.12 Linux kernel. + +The old NAND handling code has been re-factored and is now confined +to only board-specific files and - unfortunately - to the DoC code +(see below). A new configuration variable has been introduced: +CFG_NAND_LEGACY, which has to be defined in the board config file if +that board uses legacy code. If CFG_NAND_LEGACY is defined, the board +specific config.mk file should also have "BOARDLIBS = +drivers/nand_legacy/libnand_legacy.a". For boards using the new NAND +approach (PPChameleon and netstar at the moment) no variable is +necessary, but the config.mk should have "BOARDLIBS = +drivers/nand/libnand.a". + +The necessary changes have been made to all affected boards, and no +build breakage has been introduced, except for NETTA and NETTA_ISDN +targets from MAKEALL. This is due to the fact that these two boards +use JFFS, which has been adopted to use the new NAND, and at the same +time use NAND in legacy mode. The breakage will disappear when the +board-specific code is changed to the new NAND. + +As mentioned above, the legacy code is still used by the DoC subsystem. +The consequence of this is that the legacy NAND can't be removed from +the tree until the DoC is ported to use the new NAND support (or boards +with DoC will break). diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c index 4b7a110..a989d34 100644 --- a/drivers/cfi_flash.c +++ b/drivers/cfi_flash.c @@ -104,12 +104,15 @@ #define AMD_CMD_ERASE_SECTOR 0x30 #define AMD_CMD_UNLOCK_START 0xAA #define AMD_CMD_UNLOCK_ACK 0x55 +#define AMD_CMD_WRITE_TO_BUFFER 0x25 +#define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29 #define AMD_STATUS_TOGGLE 0x40 #define AMD_STATUS_ERROR 0x20 -#define AMD_ADDR_ERASE_START 0x555 -#define AMD_ADDR_START 0x555 -#define AMD_ADDR_ACK 0x2AA + +#define AMD_ADDR_ERASE_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555) +#define AMD_ADDR_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555) +#define AMD_ADDR_ACK ((info->portwidth == FLASH_CFI_8BIT) ? 0x555 : 0x2AA) #define FLASH_OFFSET_CFI 0x55 #define FLASH_OFFSET_CFI_RESP 0x10 @@ -175,6 +178,13 @@ static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST; flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */ #endif +/* + * Check if chip width is defined. If not, start detecting with 8bit. + */ +#ifndef CFG_FLASH_CFI_WIDTH +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#endif + /*----------------------------------------------------------------------- * Functions @@ -190,10 +200,10 @@ static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, u static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); static int flash_detect_cfi (flash_info_t * info); -ulong flash_get_size (ulong base, int banknum); static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword); static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, ulong tout, char *prompt); +ulong flash_get_size (ulong base, int banknum); #if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE) static flash_info_t *flash_get_info(ulong base); #endif @@ -328,6 +338,7 @@ ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset) return retval; } + /*----------------------------------------------------------------------- */ unsigned long flash_init (void) @@ -345,6 +356,24 @@ unsigned long flash_init (void) i, flash_info[i].size, flash_info[i].size << 20); #endif /* CFG_FLASH_QUIET_TEST */ } +#ifdef CFG_FLASH_PROTECTION + else { + char *s = getenv("unlock"); + + if (((s = getenv("unlock")) != NULL) && (strcmp(s, "yes") == 0)) { + /* + * Only the U-Boot image and it's environment is protected, + * all other sectors are unprotected (unlocked) if flash + * hardware protection is used (CFG_FLASH_PROTECTION) and + * the environment variable "unlock" is set to "yes". + */ + flash_protect (FLAG_PROTECT_CLEAR, + flash_info[i].start[0], + flash_info[i].start[0] + flash_info[i].size - 1, + &flash_info[i]); + } + } +#endif /* CFG_FLASH_PROTECTION */ } /* Monitor protection ON by default */ @@ -565,7 +594,22 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) buffered_size = (info->portwidth / info->chipwidth); buffered_size *= info->buffer_size; while (cnt >= info->portwidth) { - i = buffered_size > cnt ? cnt : buffered_size; + /* prohibit buffer write when buffer_size is 1 */ + if (info->buffer_size == 1) { + cword.l = 0; + for (i = 0; i < info->portwidth; i++) + flash_add_byte (info, &cword, *src++); + if ((rc = flash_write_cfiword (info, wp, cword)) != 0) + return rc; + wp += info->portwidth; + cnt -= info->portwidth; + continue; + } + + /* write buffer until next buffered_size aligned boundary */ + i = buffered_size - (wp % buffered_size); + if (i > cnt) + i = cnt; if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) return rc; i -= i & (info->portwidth - 1); @@ -705,7 +749,7 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector, /* Wait for command completion */ start = get_timer (0); while (flash_is_busy (info, sector)) { - if (get_timer (start) > info->erase_blk_tout * CFG_HZ) { + if (get_timer (start) > tout) { printf ("Flash %s timeout at address %lx data %lx\n", prompt, info->start[sector], flash_read_long (info, sector, 0)); @@ -729,7 +773,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, switch (info->vendor) { case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: - if ((retcode != ERR_OK) + if ((retcode == ERR_OK) && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { retcode = ERR_INVAL; printf ("Flash %s error at address %lx\n", prompt, @@ -834,18 +878,27 @@ static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd, cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); *addr.cp = cword.c; +#ifdef CONFIG_BLACKFIN + asm("ssync;"); +#endif break; case FLASH_CFI_16BIT: debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp, cmd, cword.w, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); *addr.wp = cword.w; +#ifdef CONFIG_BLACKFIN + asm("ssync;"); +#endif break; case FLASH_CFI_32BIT: debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp, cmd, cword.l, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); *addr.lp = cword.l; +#ifdef CONFIG_BLACKFIN + asm("ssync;"); +#endif break; case FLASH_CFI_64BIT: #ifdef DEBUG @@ -860,6 +913,9 @@ static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset } #endif *addr.llp = cword.ll; +#ifdef CONFIG_BLACKFIN + asm("ssync;"); +#endif break; } } @@ -985,7 +1041,7 @@ static int flash_detect_cfi (flash_info_t * info) { debug ("flash detect cfi\n"); - for (info->portwidth = FLASH_CFI_8BIT; + for (info->portwidth = CFG_FLASH_CFI_WIDTH; info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { for (info->chipwidth = FLASH_CFI_BY8; info->chipwidth <= info->portwidth; @@ -1106,8 +1162,9 @@ ulong flash_get_size (ulong base, int banknum) info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT))); tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT); info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000; + tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT)) * + (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT)); + info->write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0); /* round up when converting to ms */ info->flash_id = FLASH_MAN_CFI; if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) { info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */ @@ -1118,13 +1175,26 @@ ulong flash_get_size (ulong base, int banknum) return (info->size); } +/* loop through the sectors from the highest address + * when the passed address is greater or equal to the sector address + * we have a match + */ +static flash_sect_t find_sector (flash_info_t * info, ulong addr) +{ + flash_sect_t sector; + + for (sector = info->sector_count - 1; sector >= 0; sector--) { + if (addr >= info->start[sector]) + break; + } + return sector; +} /*----------------------------------------------------------------------- */ static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword) { - cfiptr_t ctladdr; cfiptr_t cptr; int flag; @@ -1188,26 +1258,12 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, if (flag) enable_interrupts (); - return flash_full_status_check (info, 0, info->write_tout, "write"); + return flash_full_status_check (info, find_sector (info, dest), + info->write_tout, "write"); } #ifdef CFG_FLASH_USE_BUFFER_WRITE -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static flash_sect_t find_sector (flash_info_t * info, ulong addr) -{ - flash_sect_t sector; - - for (sector = info->sector_count - 1; sector >= 0; sector--) { - if (addr >= info->start[sector]) - break; - } - return sector; -} - static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len) { @@ -1216,66 +1272,106 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int retcode; volatile cfiptr_t src; volatile cfiptr_t dst; - /* buffered writes in the AMD chip set is not supported yet */ - if((info->vendor == CFI_CMDSET_AMD_STANDARD) || - (info->vendor == CFI_CMDSET_AMD_EXTENDED)) - return ERR_INVAL; - src.cp = cp; - dst.cp = (uchar *) dest; - sector = find_sector (info, dest); - flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if ((retcode = - flash_status_check (info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - /* reduce the number of loops by the width of the port */ + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + src.cp = cp; + dst.cp = (uchar *) dest; + sector = find_sector (info, dest); + flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + if ((retcode = flash_status_check (info, sector, info->buffer_write_tout, + "write to buffer")) == ERR_OK) { + /* reduce the number of loops by the width of the port */ + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + break; + case FLASH_CFI_64BIT: + cnt = len >> 3; + break; + default: + return ERR_INVAL; + break; + } + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) { + switch (info->portwidth) { + case FLASH_CFI_8BIT: + *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + *dst.lp++ = *src.lp++; + break; + case FLASH_CFI_64BIT: + *dst.llp++ = *src.llp++; + break; + default: + return ERR_INVAL; + break; + } + } + flash_write_cmd (info, sector, 0, + FLASH_CMD_WRITE_BUFFER_CONFIRM); + retcode = flash_full_status_check (info, sector, + info->buffer_write_tout, + "buffer write"); + } + return retcode; + + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + src.cp = cp; + dst.cp = (uchar *) dest; + sector = find_sector (info, dest); + + flash_unlock_seq(info,0); + flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_TO_BUFFER); + switch (info->portwidth) { case FLASH_CFI_8BIT: cnt = len; + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) *dst.cp++ = *src.cp++; break; case FLASH_CFI_16BIT: cnt = len >> 1; + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) *dst.wp++ = *src.wp++; break; case FLASH_CFI_32BIT: cnt = len >> 2; + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) *dst.lp++ = *src.lp++; break; case FLASH_CFI_64BIT: cnt = len >> 3; + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) *dst.llp++ = *src.llp++; break; default: return ERR_INVAL; - break; - } - flash_write_cmd (info, sector, 0, (uchar) cnt - 1); - while (cnt-- > 0) { - switch (info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - case FLASH_CFI_64BIT: - *dst.llp++ = *src.llp++; - break; - default: - return ERR_INVAL; - break; - } } - flash_write_cmd (info, sector, 0, - FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = - flash_full_status_check (info, sector, - info->buffer_write_tout, - "buffer write"); + + flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); + retcode = flash_full_status_check (info, sector, info->buffer_write_tout, + "buffer write"); + return retcode; + + default: + debug ("Unknown Command Set\n"); + return ERR_INVAL; } - flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; } #endif /* CFG_FLASH_USE_BUFFER_WRITE */ #endif /* CFG_FLASH_CFI */ diff --git a/drivers/ct69000.c b/drivers/ct69000.c index 7bcf19f..29d82e4 100644 --- a/drivers/ct69000.c +++ b/drivers/ct69000.c @@ -272,6 +272,9 @@ struct ctfb_chips_properties { static const struct ctfb_chips_properties chips[] = { {PCI_DEVICE_ID_CT_69000, 0x200000, 1, 4, -2, 3, 257, 100, 220}, +#ifdef CONFIG_USE_CPCIDVI + {PCI_DEVICE_ID_CT_69030, 0x400000, 1, 4, -2, 3, 257, 100, 220}, +#endif {PCI_DEVICE_ID_CT_65555, 0x100000, 16, 4, 0, 1, 255, 48, 220}, /* NOT TESTED */ {0, 0, 0, 0, 0, 0, 0, 0, 0} /* Terminator */ }; @@ -957,6 +960,9 @@ SetDrawingEngine (int bits_per_pixel) */ static struct pci_device_id supported[] = { {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000}, +#ifdef CONFIG_USE_CPCIDVI + {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030}, +#endif {} }; @@ -1121,7 +1127,22 @@ video_hw_init (void) pGD->cprBase = pci_mem_base; /* Dummy */ /* set up Hardware */ +#ifdef CONFIG_USE_CPCIDVI + if (device_id == PCI_DEVICE_ID_CT_69030) { + ctWrite (CT_MSR_W_O, 0x0b); + ctWrite (0x3cd, 0x13); + ctWrite_i (CT_FP_O, 0x02, 0x00); + ctWrite_i (CT_FP_O, 0x05, 0x00); + ctWrite_i (CT_FP_O, 0x06, 0x00); + ctWrite (0x3c2, 0x0b); + ctWrite_i (CT_FP_O, 0x02, 0x10); + ctWrite_i (CT_FP_O, 0x01, 0x09); + } else { + ctWrite (CT_MSR_W_O, 0x01); + } +#else ctWrite (CT_MSR_W_O, 0x01); +#endif /* set the extended Registers */ ctLoadRegs (CT_XR_O, xreg); diff --git a/drivers/dataflash.c b/drivers/dataflash.c index ded0395..17eb859 100644 --- a/drivers/dataflash.c +++ b/drivers/dataflash.c @@ -174,8 +174,7 @@ void dataflash_print_info (void) /* Function Name : AT91F_DataflashSelect */ /* Object : Select the correct device */ /*------------------------------------------------------------------------------*/ -AT91PS_DataFlash AT91F_DataflashSelect (AT91PS_DataFlash pFlash, - unsigned int *addr) +AT91PS_DataFlash AT91F_DataflashSelect (AT91PS_DataFlash pFlash, unsigned long *addr) { char addr_valid = 0; int i; @@ -291,7 +290,7 @@ int i,j, area1, area2, addr_valid = 0; /*------------------------------------------------------------------------------*/ int read_dataflash (unsigned long addr, unsigned long size, char *result) { - int AddrToRead = addr; + unsigned long AddrToRead = addr; AT91PS_DataFlash pFlash = &DataFlashInst; pFlash = AT91F_DataflashSelect (pFlash, &AddrToRead); @@ -313,7 +312,7 @@ int read_dataflash (unsigned long addr, unsigned long size, char *result) int write_dataflash (unsigned long addr_dest, unsigned long addr_src, unsigned long size) { - int AddrToWrite = addr_dest; + unsigned long AddrToWrite = addr_dest; AT91PS_DataFlash pFlash = &DataFlashInst; pFlash = AT91F_DataflashSelect (pFlash, &AddrToWrite); @@ -330,7 +329,7 @@ int write_dataflash (unsigned long addr_dest, unsigned long addr_src, if (AddrToWrite == -1) return -1; - return AT91F_DataFlashWrite (pFlash, (char *) addr_src, AddrToWrite, size); + return AT91F_DataFlashWrite (pFlash, (uchar *)addr_src, AddrToWrite, size); } diff --git a/drivers/i8042.c b/drivers/i8042.c index e21978d..22c2a4e 100644 --- a/drivers/i8042.c +++ b/drivers/i8042.c @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -29,6 +29,14 @@ #ifdef CONFIG_I8042_KBD +#ifdef CONFIG_USE_CPCIDVI +extern u8 gt_cpcidvi_in8(u32 offset); +extern void gt_cpcidvi_out8(u32 offset, u8 data); + +#define in8(a) gt_cpcidvi_in8(a) +#define out8(a, b) gt_cpcidvi_out8(a,b) +#endif + #include <i8042.h> /* defines */ @@ -41,10 +49,10 @@ static int cursor_state = 0; /* locals */ -static int kbd_input = -1; /* no input yet */ -static int kbd_mapping = KBD_US; /* default US keyboard */ -static int kbd_flags = NORMAL; /* after reset */ -static int kbd_state = 0; /* unshift code */ +static int kbd_input = -1; /* no input yet */ +static int kbd_mapping = KBD_US; /* default US keyboard */ +static int kbd_flags = NORMAL; /* after reset */ +static int kbd_state = 0; /* unshift code */ static void kbd_conv_char (unsigned char scan_code); static void kbd_led_set (void); @@ -60,230 +68,230 @@ static int kbd_reset (void); static unsigned char kbd_fct_map [144] = { /* kbd_fct_map table for scan code */ - 0, AS, AS, AS, AS, AS, AS, AS, /* scan 0- 7 */ - AS, AS, AS, AS, AS, AS, AS, AS, /* scan 8- F */ - AS, AS, AS, AS, AS, AS, AS, AS, /* scan 10-17 */ - AS, AS, AS, AS, AS, CN, AS, AS, /* scan 18-1F */ - AS, AS, AS, AS, AS, AS, AS, AS, /* scan 20-27 */ - AS, AS, SH, AS, AS, AS, AS, AS, /* scan 28-2F */ - AS, AS, AS, AS, AS, AS, SH, AS, /* scan 30-37 */ - AS, AS, CP, 0, 0, 0, 0, 0, /* scan 38-3F */ - 0, 0, 0, 0, 0, NM, ST, ES, /* scan 40-47 */ - ES, ES, ES, ES, ES, ES, ES, ES, /* scan 48-4F */ - ES, ES, ES, ES, 0, 0, AS, 0, /* scan 50-57 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ - AS, 0, 0, AS, 0, 0, AS, 0, /* scan 70-77 */ - 0, AS, 0, 0, 0, AS, 0, 0, /* scan 78-7F */ - AS, CN, AS, AS, AK, ST, EX, EX, /* enhanced */ - AS, EX, EX, AS, EX, AS, EX, EX /* enhanced */ + 0, AS, AS, AS, AS, AS, AS, AS, /* scan 0- 7 */ + AS, AS, AS, AS, AS, AS, AS, AS, /* scan 8- F */ + AS, AS, AS, AS, AS, AS, AS, AS, /* scan 10-17 */ + AS, AS, AS, AS, AS, CN, AS, AS, /* scan 18-1F */ + AS, AS, AS, AS, AS, AS, AS, AS, /* scan 20-27 */ + AS, AS, SH, AS, AS, AS, AS, AS, /* scan 28-2F */ + AS, AS, AS, AS, AS, AS, SH, AS, /* scan 30-37 */ + AS, AS, CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, ES, /* scan 40-47 */ + ES, ES, ES, ES, ES, ES, ES, ES, /* scan 48-4F */ + ES, ES, ES, ES, 0, 0, AS, 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + AS, 0, 0, AS, 0, 0, AS, 0, /* scan 70-77 */ + 0, AS, 0, 0, 0, AS, 0, 0, /* scan 78-7F */ + AS, CN, AS, AS, AK, ST, EX, EX, /* enhanced */ + AS, EX, EX, AS, EX, AS, EX, EX /* enhanced */ }; static unsigned char kbd_key_map [2][5][144] = { { /* US keyboard */ { /* unshift code */ - 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ - '7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */ - 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */ - 'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */ - 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */ - '\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */ - 'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */ - ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ - 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ - '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ - '2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ - '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ - 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ + '7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */ + 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */ + 'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */ + '\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */ + 'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ + '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ + '2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ }, { /* shift code */ - 0, 0x1b, '!', '@', '#', '$', '%', '^', /* scan 0- 7 */ - '&', '*', '(', ')', '_', '+', 0x08, '\t', /* scan 8- F */ - 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', /* scan 10-17 */ - 'O', 'P', '{', '}', '\r', CN, 'A', 'S', /* scan 18-1F */ - 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', /* scan 20-27 */ - '"', '~', SH, '|', 'Z', 'X', 'C', 'V', /* scan 28-2F */ - 'B', 'N', 'M', '<', '>', '?', SH, '*', /* scan 30-37 */ - ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ - 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ - '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ - '2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ - '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ - 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + 0, 0x1b, '!', '@', '#', '$', '%', '^', /* scan 0- 7 */ + '&', '*', '(', ')', '_', '+', 0x08, '\t', /* scan 8- F */ + 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', /* scan 10-17 */ + 'O', 'P', '{', '}', '\r', CN, 'A', 'S', /* scan 18-1F */ + 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', /* scan 20-27 */ + '"', '~', SH, '|', 'Z', 'X', 'C', 'V', /* scan 28-2F */ + 'B', 'N', 'M', '<', '>', '?', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ + '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ + '2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ }, { /* control code */ - 0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */ - 0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */ - 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */ - 0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */ - 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */ - 0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */ - 0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */ - 0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */ - 0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */ - '\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ + 0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */ + 0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */ + 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */ + 0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */ + 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */ + 0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */ + 0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */ + 0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */ + 0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ }, { /* non numeric code */ - 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ - '7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */ - 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */ - 'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */ - 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */ - '\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */ - 'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */ - ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ - 0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */ - 'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */ - 'r', 's', 'p', 'n', 0, 0, 0, 0, /* scan 50-57 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ - '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ - 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ + '7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */ + 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */ + 'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */ + '\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */ + 'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */ + 'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */ + 'r', 's', 'p', 'n', 0, 0, 0, 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ }, { /* right alt mode - not used in US keyboard */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 8 - F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50 -57 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 8 - F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50 -57 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ } }, { /* german keyboard */ { /* unshift code */ - 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ - '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */ - 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */ - 'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */ - 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */ - 0x84, '^', SH, '#', 'y', 'x', 'c', 'v', /* scan 28-2F */ - 'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */ - ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ - 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ - '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ - '2', '3', '0', ',', 0, 0, '<', 0, /* scan 50-57 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ - '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ - 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ + '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */ + 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */ + 'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */ + 0x84, '^', SH, '#', 'y', 'x', 'c', 'v', /* scan 28-2F */ + 'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ + '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ + '2', '3', '0', ',', 0, 0, '<', 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ }, { /* shift code */ - 0, 0x1b, '!', '"', 0x15, '$', '%', '&', /* scan 0- 7 */ - '/', '(', ')', '=', '?', '`', 0x08, '\t', /* scan 8- F */ - 'Q', 'W', 'E', 'R', 'T', 'Z', 'U', 'I', /* scan 10-17 */ - 'O', 'P', 0x9a, '*', '\r', CN, 'A', 'S', /* scan 18-1F */ - 'D', 'F', 'G', 'H', 'J', 'K', 'L', 0x99, /* scan 20-27 */ - 0x8e, 0xf8, SH, '\'', 'Y', 'X', 'C', 'V', /* scan 28-2F */ - 'B', 'N', 'M', ';', ':', '_', SH, '*', /* scan 30-37 */ - ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ - 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ - '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ - '2', '3', '0', ',', 0, 0, '>', 0, /* scan 50-57 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ - '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ - 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + 0, 0x1b, '!', '"', 0x15, '$', '%', '&', /* scan 0- 7 */ + '/', '(', ')', '=', '?', '`', 0x08, '\t', /* scan 8- F */ + 'Q', 'W', 'E', 'R', 'T', 'Z', 'U', 'I', /* scan 10-17 */ + 'O', 'P', 0x9a, '*', '\r', CN, 'A', 'S', /* scan 18-1F */ + 'D', 'F', 'G', 'H', 'J', 'K', 'L', 0x99, /* scan 20-27 */ + 0x8e, 0xf8, SH, '\'', 'Y', 'X', 'C', 'V', /* scan 28-2F */ + 'B', 'N', 'M', ';', ':', '_', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ + '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ + '2', '3', '0', ',', 0, 0, '>', 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ }, { /* control code */ - 0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */ - 0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */ - 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */ - 0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */ - 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */ - 0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */ - 0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */ - 0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */ - 0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */ - '\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ + 0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */ + 0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */ + 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */ + 0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */ + 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */ + 0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */ + 0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */ + 0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */ + 0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ }, { /* non numeric code */ - 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ - '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */ - 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */ - 'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */ - 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */ - 0x84, '^', SH, 0, 'y', 'x', 'c', 'v', /* scan 28-2F */ - 'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */ - ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ - 0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */ - 'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */ - 'r', 's', 'p', 'n', 0, 0, '<', 0, /* scan 50-57 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ - 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ - '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ - 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ + '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */ + 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */ + 'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */ + 0x84, '^', SH, 0, 'y', 'x', 'c', 'v', /* scan 28-2F */ + 'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */ + 'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */ + 'r', 's', 'p', 'n', 0, 0, '<', 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ }, { /* Right alt mode - is used in German keyboard */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */ - '{', '[', ']', '}', '\\', 0xff, 0xff, 0xff, /* scan 8 - F */ - '@', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */ - 0xff, 0xff, 0xff, '~', 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */ - 0xff, 0xff, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '|', 0xff, /* scan 50 -57 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */ + '{', '[', ']', '}', '\\', 0xff, 0xff, 0xff, /* scan 8 - F */ + '@', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */ + 0xff, 0xff, 0xff, '~', 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */ + 0xff, 0xff, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '|', 0xff, /* scan 50 -57 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ } } }; @@ -318,6 +326,13 @@ int i8042_kbd_init (void) int keymap, try; char *penv; +#ifdef CONFIG_USE_CPCIDVI + if ((penv = getenv ("console")) != NULL) { + if (strncmp (penv, "serial", 7) == 0) { + return -1; + } + } +#endif /* Init keyboard device (default US layout) */ keymap = KBD_US; if ((penv = getenv ("keymap")) != NULL) @@ -330,9 +345,9 @@ int i8042_kbd_init (void) { if (kbd_reset() == 0) { - kbd_mapping = keymap; - kbd_flags = NORMAL; - kbd_state = 0; + kbd_mapping = keymap; + kbd_flags = NORMAL; + kbd_state = 0; kbd_led_set(); return 0; } @@ -344,7 +359,7 @@ int i8042_kbd_init (void) /******************************************************************************* * * i8042_tstc - test if keyboard input is available - * option: cursor blinking if called in a loop + * option: cursor blinking if called in a loop */ int i8042_tstc (void) { @@ -380,7 +395,7 @@ int i8042_tstc (void) /******************************************************************************* * * i8042_getc - wait till keyboard input is available - * option: turn on/off cursor while waiting + * option: turn on/off cursor while waiting */ int i8042_getc (void) { @@ -433,8 +448,8 @@ static void kbd_conv_char (unsigned char scan_code) { if (scan_code == 0xe1) { - kbd_flags ^= BRK; /* reset the break flag */ - kbd_flags ^= E1; /* bitwise EXOR with E1 flag */ + kbd_flags ^= BRK; /* reset the break flag */ + kbd_flags ^= E1; /* bitwise EXOR with E1 flag */ } return; } @@ -545,7 +560,7 @@ static void kbd_caps (unsigned char scan_code) if ((kbd_flags & BRK) == NORMAL) { kbd_flags ^= CAPS; - kbd_led_set (); /* update keyboard LED */ + kbd_led_set (); /* update keyboard LED */ } } @@ -558,7 +573,7 @@ static void kbd_num (unsigned char scan_code) { kbd_flags ^= NUM; kbd_state = (kbd_flags & NUM) ? AS : NM; - kbd_led_set (); /* update keyboard LED */ + kbd_led_set (); /* update keyboard LED */ } } @@ -570,7 +585,7 @@ static void kbd_scroll (unsigned char scan_code) if ((kbd_flags & BRK) == NORMAL) { kbd_flags ^= STP; - kbd_led_set (); /* update keyboard LED */ + kbd_led_set (); /* update keyboard LED */ if (kbd_flags & STP) kbd_input = 0x13; else @@ -600,9 +615,9 @@ static void kbd_alt (unsigned char scan_code) static void kbd_led_set (void) { kbd_input_empty(); - out8 (I8042_DATA_REG, 0xed); /* SET LED command */ + out8 (I8042_DATA_REG, 0xed); /* SET LED command */ kbd_input_empty(); - out8 (I8042_DATA_REG, (kbd_flags & 0x7)); /* LED bits only */ + out8 (I8042_DATA_REG, (kbd_flags & 0x7)); /* LED bits only */ } @@ -633,7 +648,11 @@ static int kbd_reset (void) if (kbd_input_empty() == 0) return -1; +#ifdef CONFIG_USE_CPCIDVI + out8 (I8042_COMMAND_REG, 0x60); +#else out8 (I8042_DATA_REG, 0x60); +#endif if (kbd_input_empty() == 0) return -1; diff --git a/drivers/ks8695eth.c b/drivers/ks8695eth.c index a4b03ae..a0f5be8 100644 --- a/drivers/ks8695eth.c +++ b/drivers/ks8695eth.c @@ -18,8 +18,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifdef CONFIG_DRIVER_KS8695ETH - /****************************************************************************/ #include <common.h> @@ -28,6 +26,7 @@ #include <asm/io.h> #include <asm/arch/platform.h> +#ifdef CONFIG_DRIVER_KS8695ETH /****************************************************************************/ /* @@ -216,10 +215,10 @@ int eth_send(volatile void *packet, int len) packet, len); dp = &ks8695_tx[next]; - memcpy((void *) dp->addr, packet, len); + memcpy((void *) dp->addr, (void *) packet, len); if (len < 64) { - memset(dp->addr+len, 0, 64-len); + memset((void *) (dp->addr + len), 0, 64-len); len = 64; } diff --git a/drivers/lan91c96.c b/drivers/lan91c96.c index bb03dae..a50c5f0 100644 --- a/drivers/lan91c96.c +++ b/drivers/lan91c96.c @@ -185,21 +185,21 @@ static int smc_rcv (void); . If an EEPROM is present it really should be consulted. */ int smc_get_ethaddr(bd_t *bd); -int get_rom_mac(char *v_rom_mac); +int get_rom_mac(unsigned char *v_rom_mac); /* ------------------------------------------------------------ * Internal routines * ------------------------------------------------------------ */ -static char smc_mac_addr[] = { 0xc0, 0x00, 0x00, 0x1b, 0x62, 0x9c }; +static unsigned char smc_mac_addr[] = { 0xc0, 0x00, 0x00, 0x1b, 0x62, 0x9c }; /* * This function must be called before smc_open() if you want to override * the default mac address. */ -void smc_set_mac_addr (const char *addr) +void smc_set_mac_addr (const unsigned char *addr) { int i; @@ -883,7 +883,7 @@ int smc_get_ethaddr (bd_t * bd) char *s = NULL; char *e = NULL; char *v_mac, es[] = "11:22:33:44:55:66"; - uchar s_env_mac[64]; + char s_env_mac[64]; uchar v_env_mac[6]; uchar v_rom_mac[6]; @@ -905,7 +905,7 @@ int smc_get_ethaddr (bd_t * bd) if (!env_present) { /* if NO env */ if (rom_valid) { /* but ROM is valid */ - v_mac = v_rom_mac; + v_mac = (char *)v_rom_mac; sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", v_mac[0], v_mac[1], v_mac[2], v_mac[3], v_mac[4], v_mac[5]); @@ -915,7 +915,7 @@ int smc_get_ethaddr (bd_t * bd) return (-1); } } else { /* good env, don't care ROM */ - v_mac = v_env_mac; /* always use a good env over a ROM */ + v_mac = (char *)v_env_mac; /* always use a good env over a ROM */ } if (env_present && rom_valid) { /* if both env and ROM are good */ @@ -935,7 +935,7 @@ int smc_get_ethaddr (bd_t * bd) } } memcpy (bd->bi_enetaddr, v_mac, 6); /* update global address to match env (allows env changing) */ - smc_set_mac_addr (v_mac); /* use old function to update smc default */ + smc_set_mac_addr ((unsigned char *)v_mac); /* use old function to update smc default */ PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1], v_mac[2], v_mac[3], v_mac[4], v_mac[5]); return (0); @@ -946,7 +946,7 @@ int smc_get_ethaddr (bd_t * bd) * Note, this has omly been tested for the OMAP730 P2. */ -int get_rom_mac (char *v_rom_mac) +int get_rom_mac (unsigned char *v_rom_mac) { #ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */ char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 }; diff --git a/drivers/lan91c96.h b/drivers/lan91c96.h index b7d7455..7d33a82 100644 --- a/drivers/lan91c96.h +++ b/drivers/lan91c96.h @@ -51,7 +51,7 @@ * in order to override the default mac address. */ -void smc_set_mac_addr(const char *addr); +void smc_set_mac_addr(const unsigned char *addr); /* I want some simple types */ diff --git a/drivers/nand/Makefile b/drivers/nand/Makefile new file mode 100644 index 0000000..96f67df --- /dev/null +++ b/drivers/nand/Makefile @@ -0,0 +1,16 @@ +include $(TOPDIR)/config.mk + +LIB := libnand.a + +OBJS := nand.o nand_base.o nand_ids.o nand_ecc.o nand_bbt.o +all: $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend diff --git a/drivers/nand/diskonchip.c b/drivers/nand/diskonchip.c new file mode 100644 index 0000000..afaae83 --- /dev/null +++ b/drivers/nand/diskonchip.c @@ -0,0 +1,1788 @@ +/* + * drivers/mtd/nand/diskonchip.c + * + * (C) 2003 Red Hat, Inc. + * (C) 2004 Dan Brown <dan_brown@ieee.org> + * (C) 2004 Kalev Lember <kalev@smartlink.ee> + * + * Author: David Woodhouse <dwmw2@infradead.org> + * Additional Diskonchip 2000 and Millennium support by Dan Brown <dan_brown@ieee.org> + * Diskonchip Millennium Plus support by Kalev Lember <kalev@smartlink.ee> + * + * Error correction code lifted from the old docecc code + * Author: Fabrice Bellard (fabrice.bellard@netgem.com) + * Copyright (C) 2000 Netgem S.A. + * converted to the generic Reed-Solomon library by Thomas Gleixner <tglx@linutronix.de> + * + * Interface to generic NAND code for M-Systems DiskOnChip devices + * + * $Id: diskonchip.c,v 1.45 2005/01/05 18:05:14 dwmw2 Exp $ + */ + +#include <common.h> + +#ifdef CFG_NAND_LEGACY +#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support! +#endif + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/delay.h> +#include <linux/rslib.h> +#include <linux/moduleparam.h> +#include <asm/io.h> + +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/doc2000.h> +#include <linux/mtd/compatmac.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/inftl.h> + +/* Where to look for the devices? */ +#ifndef CONFIG_MTD_DISKONCHIP_PROBE_ADDRESS +#define CONFIG_MTD_DISKONCHIP_PROBE_ADDRESS 0 +#endif + +static unsigned long __initdata doc_locations[] = { +#if defined (__alpha__) || defined(__i386__) || defined(__x86_64__) +#ifdef CONFIG_MTD_DISKONCHIP_PROBE_HIGH + 0xfffc8000, 0xfffca000, 0xfffcc000, 0xfffce000, + 0xfffd0000, 0xfffd2000, 0xfffd4000, 0xfffd6000, + 0xfffd8000, 0xfffda000, 0xfffdc000, 0xfffde000, + 0xfffe0000, 0xfffe2000, 0xfffe4000, 0xfffe6000, + 0xfffe8000, 0xfffea000, 0xfffec000, 0xfffee000, +#else /* CONFIG_MTD_DOCPROBE_HIGH */ + 0xc8000, 0xca000, 0xcc000, 0xce000, + 0xd0000, 0xd2000, 0xd4000, 0xd6000, + 0xd8000, 0xda000, 0xdc000, 0xde000, + 0xe0000, 0xe2000, 0xe4000, 0xe6000, + 0xe8000, 0xea000, 0xec000, 0xee000, +#endif /* CONFIG_MTD_DOCPROBE_HIGH */ +#elif defined(__PPC__) + 0xe4000000, +#elif defined(CONFIG_MOMENCO_OCELOT) + 0x2f000000, + 0xff000000, +#elif defined(CONFIG_MOMENCO_OCELOT_G) || defined (CONFIG_MOMENCO_OCELOT_C) + 0xff000000, +##else +#warning Unknown architecture for DiskOnChip. No default probe locations defined +#endif + 0xffffffff }; + +static struct mtd_info *doclist = NULL; + +struct doc_priv { + void __iomem *virtadr; + unsigned long physadr; + u_char ChipID; + u_char CDSNControl; + int chips_per_floor; /* The number of chips detected on each floor */ + int curfloor; + int curchip; + int mh0_page; + int mh1_page; + struct mtd_info *nextdoc; +}; + +/* Max number of eraseblocks to scan (from start of device) for the (I)NFTL + MediaHeader. The spec says to just keep going, I think, but that's just + silly. */ +#define MAX_MEDIAHEADER_SCAN 8 + +/* This is the syndrome computed by the HW ecc generator upon reading an empty + page, one with all 0xff for data and stored ecc code. */ +static u_char empty_read_syndrome[6] = { 0x26, 0xff, 0x6d, 0x47, 0x73, 0x7a }; +/* This is the ecc value computed by the HW ecc generator upon writing an empty + page, one with all 0xff for data. */ +static u_char empty_write_ecc[6] = { 0x4b, 0x00, 0xe2, 0x0e, 0x93, 0xf7 }; + +#define INFTL_BBT_RESERVED_BLOCKS 4 + +#define DoC_is_MillenniumPlus(doc) ((doc)->ChipID == DOC_ChipID_DocMilPlus16 || (doc)->ChipID == DOC_ChipID_DocMilPlus32) +#define DoC_is_Millennium(doc) ((doc)->ChipID == DOC_ChipID_DocMil) +#define DoC_is_2000(doc) ((doc)->ChipID == DOC_ChipID_Doc2k) + +static void doc200x_hwcontrol(struct mtd_info *mtd, int cmd); +static void doc200x_select_chip(struct mtd_info *mtd, int chip); + +static int debug=0; +module_param(debug, int, 0); + +static int try_dword=1; +module_param(try_dword, int, 0); + +static int no_ecc_failures=0; +module_param(no_ecc_failures, int, 0); + +#ifdef CONFIG_MTD_PARTITIONS +static int no_autopart=0; +module_param(no_autopart, int, 0); +#endif + +#ifdef MTD_NAND_DISKONCHIP_BBTWRITE +static int inftl_bbt_write=1; +#else +static int inftl_bbt_write=0; +#endif +module_param(inftl_bbt_write, int, 0); + +static unsigned long doc_config_location = CONFIG_MTD_DISKONCHIP_PROBE_ADDRESS; +module_param(doc_config_location, ulong, 0); +MODULE_PARM_DESC(doc_config_location, "Physical memory address at which to probe for DiskOnChip"); + + +/* Sector size for HW ECC */ +#define SECTOR_SIZE 512 +/* The sector bytes are packed into NB_DATA 10 bit words */ +#define NB_DATA (((SECTOR_SIZE + 1) * 8 + 6) / 10) +/* Number of roots */ +#define NROOTS 4 +/* First consective root */ +#define FCR 510 +/* Number of symbols */ +#define NN 1023 + +/* the Reed Solomon control structure */ +static struct rs_control *rs_decoder; + +/* + * The HW decoder in the DoC ASIC's provides us a error syndrome, + * which we must convert to a standard syndrom usable by the generic + * Reed-Solomon library code. + * + * Fabrice Bellard figured this out in the old docecc code. I added + * some comments, improved a minor bit and converted it to make use + * of the generic Reed-Solomon libary. tglx + */ +static int doc_ecc_decode (struct rs_control *rs, uint8_t *data, uint8_t *ecc) +{ + int i, j, nerr, errpos[8]; + uint8_t parity; + uint16_t ds[4], s[5], tmp, errval[8], syn[4]; + + /* Convert the ecc bytes into words */ + ds[0] = ((ecc[4] & 0xff) >> 0) | ((ecc[5] & 0x03) << 8); + ds[1] = ((ecc[5] & 0xfc) >> 2) | ((ecc[2] & 0x0f) << 6); + ds[2] = ((ecc[2] & 0xf0) >> 4) | ((ecc[3] & 0x3f) << 4); + ds[3] = ((ecc[3] & 0xc0) >> 6) | ((ecc[0] & 0xff) << 2); + parity = ecc[1]; + + /* Initialize the syndrom buffer */ + for (i = 0; i < NROOTS; i++) + s[i] = ds[0]; + /* + * Evaluate + * s[i] = ds[3]x^3 + ds[2]x^2 + ds[1]x^1 + ds[0] + * where x = alpha^(FCR + i) + */ + for(j = 1; j < NROOTS; j++) { + if(ds[j] == 0) + continue; + tmp = rs->index_of[ds[j]]; + for(i = 0; i < NROOTS; i++) + s[i] ^= rs->alpha_to[rs_modnn(rs, tmp + (FCR + i) * j)]; + } + + /* Calc s[i] = s[i] / alpha^(v + i) */ + for (i = 0; i < NROOTS; i++) { + if (syn[i]) + syn[i] = rs_modnn(rs, rs->index_of[s[i]] + (NN - FCR - i)); + } + /* Call the decoder library */ + nerr = decode_rs16(rs, NULL, NULL, 1019, syn, 0, errpos, 0, errval); + + /* Incorrectable errors ? */ + if (nerr < 0) + return nerr; + + /* + * Correct the errors. The bitpositions are a bit of magic, + * but they are given by the design of the de/encoder circuit + * in the DoC ASIC's. + */ + for(i = 0;i < nerr; i++) { + int index, bitpos, pos = 1015 - errpos[i]; + uint8_t val; + if (pos >= NB_DATA && pos < 1019) + continue; + if (pos < NB_DATA) { + /* extract bit position (MSB first) */ + pos = 10 * (NB_DATA - 1 - pos) - 6; + /* now correct the following 10 bits. At most two bytes + can be modified since pos is even */ + index = (pos >> 3) ^ 1; + bitpos = pos & 7; + if ((index >= 0 && index < SECTOR_SIZE) || + index == (SECTOR_SIZE + 1)) { + val = (uint8_t) (errval[i] >> (2 + bitpos)); + parity ^= val; + if (index < SECTOR_SIZE) + data[index] ^= val; + } + index = ((pos >> 3) + 1) ^ 1; + bitpos = (bitpos + 10) & 7; + if (bitpos == 0) + bitpos = 8; + if ((index >= 0 && index < SECTOR_SIZE) || + index == (SECTOR_SIZE + 1)) { + val = (uint8_t)(errval[i] << (8 - bitpos)); + parity ^= val; + if (index < SECTOR_SIZE) + data[index] ^= val; + } + } + } + /* If the parity is wrong, no rescue possible */ + return parity ? -1 : nerr; +} + +static void DoC_Delay(struct doc_priv *doc, unsigned short cycles) +{ + volatile char dummy; + int i; + + for (i = 0; i < cycles; i++) { + if (DoC_is_Millennium(doc)) + dummy = ReadDOC(doc->virtadr, NOP); + else if (DoC_is_MillenniumPlus(doc)) + dummy = ReadDOC(doc->virtadr, Mplus_NOP); + else + dummy = ReadDOC(doc->virtadr, DOCStatus); + } + +} + +#define CDSN_CTRL_FR_B_MASK (CDSN_CTRL_FR_B0 | CDSN_CTRL_FR_B1) + +/* DOC_WaitReady: Wait for RDY line to be asserted by the flash chip */ +static int _DoC_WaitReady(struct doc_priv *doc) +{ + void __iomem *docptr = doc->virtadr; + unsigned long timeo = jiffies + (HZ * 10); + + if(debug) printk("_DoC_WaitReady...\n"); + /* Out-of-line routine to wait for chip response */ + if (DoC_is_MillenniumPlus(doc)) { + while ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) { + if (time_after(jiffies, timeo)) { + printk("_DoC_WaitReady timed out.\n"); + return -EIO; + } + udelay(1); + cond_resched(); + } + } else { + while (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) { + if (time_after(jiffies, timeo)) { + printk("_DoC_WaitReady timed out.\n"); + return -EIO; + } + udelay(1); + cond_resched(); + } + } + + return 0; +} + +static inline int DoC_WaitReady(struct doc_priv *doc) +{ + void __iomem *docptr = doc->virtadr; + int ret = 0; + + if (DoC_is_MillenniumPlus(doc)) { + DoC_Delay(doc, 4); + + if ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) + /* Call the out-of-line routine to wait */ + ret = _DoC_WaitReady(doc); + } else { + DoC_Delay(doc, 4); + + if (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) + /* Call the out-of-line routine to wait */ + ret = _DoC_WaitReady(doc); + DoC_Delay(doc, 2); + } + + if(debug) printk("DoC_WaitReady OK\n"); + return ret; +} + +static void doc2000_write_byte(struct mtd_info *mtd, u_char datum) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + if(debug)printk("write_byte %02x\n", datum); + WriteDOC(datum, docptr, CDSNSlowIO); + WriteDOC(datum, docptr, 2k_CDSN_IO); +} + +static u_char doc2000_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + u_char ret; + + ReadDOC(docptr, CDSNSlowIO); + DoC_Delay(doc, 2); + ret = ReadDOC(docptr, 2k_CDSN_IO); + if (debug) printk("read_byte returns %02x\n", ret); + return ret; +} + +static void doc2000_writebuf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + if (debug)printk("writebuf of %d bytes: ", len); + for (i=0; i < len; i++) { + WriteDOC_(buf[i], docptr, DoC_2k_CDSN_IO + i); + if (debug && i < 16) + printk("%02x ", buf[i]); + } + if (debug) printk("\n"); +} + +static void doc2000_readbuf(struct mtd_info *mtd, + u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + if (debug)printk("readbuf of %d bytes: ", len); + + for (i=0; i < len; i++) { + buf[i] = ReadDOC(docptr, 2k_CDSN_IO + i); + } +} + +static void doc2000_readbuf_dword(struct mtd_info *mtd, + u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + if (debug) printk("readbuf_dword of %d bytes: ", len); + + if (unlikely((((unsigned long)buf)|len) & 3)) { + for (i=0; i < len; i++) { + *(uint8_t *)(&buf[i]) = ReadDOC(docptr, 2k_CDSN_IO + i); + } + } else { + for (i=0; i < len; i+=4) { + *(uint32_t*)(&buf[i]) = readl(docptr + DoC_2k_CDSN_IO + i); + } + } +} + +static int doc2000_verifybuf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + for (i=0; i < len; i++) + if (buf[i] != ReadDOC(docptr, 2k_CDSN_IO)) + return -EFAULT; + return 0; +} + +static uint16_t __init doc200x_ident_chip(struct mtd_info *mtd, int nr) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + uint16_t ret; + + doc200x_select_chip(mtd, nr); + doc200x_hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_READID); + doc200x_hwcontrol(mtd, NAND_CTL_CLRCLE); + doc200x_hwcontrol(mtd, NAND_CTL_SETALE); + this->write_byte(mtd, 0); + doc200x_hwcontrol(mtd, NAND_CTL_CLRALE); + + ret = this->read_byte(mtd) << 8; + ret |= this->read_byte(mtd); + + if (doc->ChipID == DOC_ChipID_Doc2k && try_dword && !nr) { + /* First chip probe. See if we get same results by 32-bit access */ + union { + uint32_t dword; + uint8_t byte[4]; + } ident; + void __iomem *docptr = doc->virtadr; + + doc200x_hwcontrol(mtd, NAND_CTL_SETCLE); + doc2000_write_byte(mtd, NAND_CMD_READID); + doc200x_hwcontrol(mtd, NAND_CTL_CLRCLE); + doc200x_hwcontrol(mtd, NAND_CTL_SETALE); + doc2000_write_byte(mtd, 0); + doc200x_hwcontrol(mtd, NAND_CTL_CLRALE); + + ident.dword = readl(docptr + DoC_2k_CDSN_IO); + if (((ident.byte[0] << 8) | ident.byte[1]) == ret) { + printk(KERN_INFO "DiskOnChip 2000 responds to DWORD access\n"); + this->read_buf = &doc2000_readbuf_dword; + } + } + + return ret; +} + +static void __init doc2000_count_chips(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + uint16_t mfrid; + int i; + + /* Max 4 chips per floor on DiskOnChip 2000 */ + doc->chips_per_floor = 4; + + /* Find out what the first chip is */ + mfrid = doc200x_ident_chip(mtd, 0); + + /* Find how many chips in each floor. */ + for (i = 1; i < 4; i++) { + if (doc200x_ident_chip(mtd, i) != mfrid) + break; + } + doc->chips_per_floor = i; + printk(KERN_DEBUG "Detected %d chips per floor.\n", i); +} + +static int doc200x_wait(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + struct doc_priv *doc = this->priv; + + int status; + + DoC_WaitReady(doc); + this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); + DoC_WaitReady(doc); + status = (int)this->read_byte(mtd); + + return status; +} + +static void doc2001_write_byte(struct mtd_info *mtd, u_char datum) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + WriteDOC(datum, docptr, CDSNSlowIO); + WriteDOC(datum, docptr, Mil_CDSN_IO); + WriteDOC(datum, docptr, WritePipeTerm); +} + +static u_char doc2001_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + /*ReadDOC(docptr, CDSNSlowIO); */ + /* 11.4.5 -- delay twice to allow extended length cycle */ + DoC_Delay(doc, 2); + ReadDOC(docptr, ReadPipeInit); + /*return ReadDOC(docptr, Mil_CDSN_IO); */ + return ReadDOC(docptr, LastDataRead); +} + +static void doc2001_writebuf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + for (i=0; i < len; i++) + WriteDOC_(buf[i], docptr, DoC_Mil_CDSN_IO + i); + /* Terminate write pipeline */ + WriteDOC(0x00, docptr, WritePipeTerm); +} + +static void doc2001_readbuf(struct mtd_info *mtd, + u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + /* Start read pipeline */ + ReadDOC(docptr, ReadPipeInit); + + for (i=0; i < len-1; i++) + buf[i] = ReadDOC(docptr, Mil_CDSN_IO + (i & 0xff)); + + /* Terminate read pipeline */ + buf[i] = ReadDOC(docptr, LastDataRead); +} + +static int doc2001_verifybuf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + /* Start read pipeline */ + ReadDOC(docptr, ReadPipeInit); + + for (i=0; i < len-1; i++) + if (buf[i] != ReadDOC(docptr, Mil_CDSN_IO)) { + ReadDOC(docptr, LastDataRead); + return i; + } + if (buf[i] != ReadDOC(docptr, LastDataRead)) + return i; + return 0; +} + +static u_char doc2001plus_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + u_char ret; + + ReadDOC(docptr, Mplus_ReadPipeInit); + ReadDOC(docptr, Mplus_ReadPipeInit); + ret = ReadDOC(docptr, Mplus_LastDataRead); + if (debug) printk("read_byte returns %02x\n", ret); + return ret; +} + +static void doc2001plus_writebuf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + if (debug)printk("writebuf of %d bytes: ", len); + for (i=0; i < len; i++) { + WriteDOC_(buf[i], docptr, DoC_Mil_CDSN_IO + i); + if (debug && i < 16) + printk("%02x ", buf[i]); + } + if (debug) printk("\n"); +} + +static void doc2001plus_readbuf(struct mtd_info *mtd, + u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + if (debug)printk("readbuf of %d bytes: ", len); + + /* Start read pipeline */ + ReadDOC(docptr, Mplus_ReadPipeInit); + ReadDOC(docptr, Mplus_ReadPipeInit); + + for (i=0; i < len-2; i++) { + buf[i] = ReadDOC(docptr, Mil_CDSN_IO); + if (debug && i < 16) + printk("%02x ", buf[i]); + } + + /* Terminate read pipeline */ + buf[len-2] = ReadDOC(docptr, Mplus_LastDataRead); + if (debug && i < 16) + printk("%02x ", buf[len-2]); + buf[len-1] = ReadDOC(docptr, Mplus_LastDataRead); + if (debug && i < 16) + printk("%02x ", buf[len-1]); + if (debug) printk("\n"); +} + +static int doc2001plus_verifybuf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + if (debug)printk("verifybuf of %d bytes: ", len); + + /* Start read pipeline */ + ReadDOC(docptr, Mplus_ReadPipeInit); + ReadDOC(docptr, Mplus_ReadPipeInit); + + for (i=0; i < len-2; i++) + if (buf[i] != ReadDOC(docptr, Mil_CDSN_IO)) { + ReadDOC(docptr, Mplus_LastDataRead); + ReadDOC(docptr, Mplus_LastDataRead); + return i; + } + if (buf[len-2] != ReadDOC(docptr, Mplus_LastDataRead)) + return len-2; + if (buf[len-1] != ReadDOC(docptr, Mplus_LastDataRead)) + return len-1; + return 0; +} + +static void doc2001plus_select_chip(struct mtd_info *mtd, int chip) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int floor = 0; + + if(debug)printk("select chip (%d)\n", chip); + + if (chip == -1) { + /* Disable flash internally */ + WriteDOC(0, docptr, Mplus_FlashSelect); + return; + } + + floor = chip / doc->chips_per_floor; + chip -= (floor * doc->chips_per_floor); + + /* Assert ChipEnable and deassert WriteProtect */ + WriteDOC((DOC_FLASH_CE), docptr, Mplus_FlashSelect); + this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + + doc->curchip = chip; + doc->curfloor = floor; +} + +static void doc200x_select_chip(struct mtd_info *mtd, int chip) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int floor = 0; + + if(debug)printk("select chip (%d)\n", chip); + + if (chip == -1) + return; + + floor = chip / doc->chips_per_floor; + chip -= (floor * doc->chips_per_floor); + + /* 11.4.4 -- deassert CE before changing chip */ + doc200x_hwcontrol(mtd, NAND_CTL_CLRNCE); + + WriteDOC(floor, docptr, FloorSelect); + WriteDOC(chip, docptr, CDSNDeviceSelect); + + doc200x_hwcontrol(mtd, NAND_CTL_SETNCE); + + doc->curchip = chip; + doc->curfloor = floor; +} + +static void doc200x_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + switch(cmd) { + case NAND_CTL_SETNCE: + doc->CDSNControl |= CDSN_CTRL_CE; + break; + case NAND_CTL_CLRNCE: + doc->CDSNControl &= ~CDSN_CTRL_CE; + break; + case NAND_CTL_SETCLE: + doc->CDSNControl |= CDSN_CTRL_CLE; + break; + case NAND_CTL_CLRCLE: + doc->CDSNControl &= ~CDSN_CTRL_CLE; + break; + case NAND_CTL_SETALE: + doc->CDSNControl |= CDSN_CTRL_ALE; + break; + case NAND_CTL_CLRALE: + doc->CDSNControl &= ~CDSN_CTRL_ALE; + break; + case NAND_CTL_SETWP: + doc->CDSNControl |= CDSN_CTRL_WP; + break; + case NAND_CTL_CLRWP: + doc->CDSNControl &= ~CDSN_CTRL_WP; + break; + } + if (debug)printk("hwcontrol(%d): %02x\n", cmd, doc->CDSNControl); + WriteDOC(doc->CDSNControl, docptr, CDSNControl); + /* 11.4.3 -- 4 NOPs after CSDNControl write */ + DoC_Delay(doc, 4); +} + +static void doc2001plus_command (struct mtd_info *mtd, unsigned command, int column, int page_addr) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + /* + * Must terminate write pipeline before sending any commands + * to the device. + */ + if (command == NAND_CMD_PAGEPROG) { + WriteDOC(0x00, docptr, Mplus_WritePipeTerm); + WriteDOC(0x00, docptr, Mplus_WritePipeTerm); + } + + /* + * Write out the command to the device. + */ + if (command == NAND_CMD_SEQIN) { + int readcmd; + + if (column >= mtd->oobblock) { + /* OOB area */ + column -= mtd->oobblock; + readcmd = NAND_CMD_READOOB; + } else if (column < 256) { + /* First 256 bytes --> READ0 */ + readcmd = NAND_CMD_READ0; + } else { + column -= 256; + readcmd = NAND_CMD_READ1; + } + WriteDOC(readcmd, docptr, Mplus_FlashCmd); + } + WriteDOC(command, docptr, Mplus_FlashCmd); + WriteDOC(0, docptr, Mplus_WritePipeTerm); + WriteDOC(0, docptr, Mplus_WritePipeTerm); + + if (column != -1 || page_addr != -1) { + /* Serially input address */ + if (column != -1) { + /* Adjust columns for 16 bit buswidth */ + if (this->options & NAND_BUSWIDTH_16) + column >>= 1; + WriteDOC(column, docptr, Mplus_FlashAddress); + } + if (page_addr != -1) { + WriteDOC((unsigned char) (page_addr & 0xff), docptr, Mplus_FlashAddress); + WriteDOC((unsigned char) ((page_addr >> 8) & 0xff), docptr, Mplus_FlashAddress); + /* One more address cycle for higher density devices */ + if (this->chipsize & 0x0c000000) { + WriteDOC((unsigned char) ((page_addr >> 16) & 0x0f), docptr, Mplus_FlashAddress); + printk("high density\n"); + } + } + WriteDOC(0, docptr, Mplus_WritePipeTerm); + WriteDOC(0, docptr, Mplus_WritePipeTerm); + /* deassert ALE */ + if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 || command == NAND_CMD_READOOB || command == NAND_CMD_READID) + WriteDOC(0, docptr, Mplus_FlashControl); + } + + /* + * program and erase have their own busy handlers + * status and sequential in needs no delay + */ + switch (command) { + + case NAND_CMD_PAGEPROG: + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + case NAND_CMD_SEQIN: + case NAND_CMD_STATUS: + return; + + case NAND_CMD_RESET: + if (this->dev_ready) + break; + udelay(this->chip_delay); + WriteDOC(NAND_CMD_STATUS, docptr, Mplus_FlashCmd); + WriteDOC(0, docptr, Mplus_WritePipeTerm); + WriteDOC(0, docptr, Mplus_WritePipeTerm); + while ( !(this->read_byte(mtd) & 0x40)); + return; + + /* This applies to read commands */ + default: + /* + * If we don't have access to the busy pin, we apply the given + * command delay + */ + if (!this->dev_ready) { + udelay (this->chip_delay); + return; + } + } + + /* Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. */ + ndelay (100); + /* wait until command is processed */ + while (!this->dev_ready(mtd)); +} + +static int doc200x_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + if (DoC_is_MillenniumPlus(doc)) { + /* 11.4.2 -- must NOP four times before checking FR/B# */ + DoC_Delay(doc, 4); + if ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) { + if(debug) + printk("not ready\n"); + return 0; + } + if (debug)printk("was ready\n"); + return 1; + } else { + /* 11.4.2 -- must NOP four times before checking FR/B# */ + DoC_Delay(doc, 4); + if (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) { + if(debug) + printk("not ready\n"); + return 0; + } + /* 11.4.2 -- Must NOP twice if it's ready */ + DoC_Delay(doc, 2); + if (debug)printk("was ready\n"); + return 1; + } +} + +static int doc200x_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) +{ + /* This is our last resort if we couldn't find or create a BBT. Just + pretend all blocks are good. */ + return 0; +} + +static void doc200x_enable_hwecc(struct mtd_info *mtd, int mode) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + /* Prime the ECC engine */ + switch(mode) { + case NAND_ECC_READ: + WriteDOC(DOC_ECC_RESET, docptr, ECCConf); + WriteDOC(DOC_ECC_EN, docptr, ECCConf); + break; + case NAND_ECC_WRITE: + WriteDOC(DOC_ECC_RESET, docptr, ECCConf); + WriteDOC(DOC_ECC_EN | DOC_ECC_RW, docptr, ECCConf); + break; + } +} + +static void doc2001plus_enable_hwecc(struct mtd_info *mtd, int mode) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + /* Prime the ECC engine */ + switch(mode) { + case NAND_ECC_READ: + WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf); + WriteDOC(DOC_ECC_EN, docptr, Mplus_ECCConf); + break; + case NAND_ECC_WRITE: + WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf); + WriteDOC(DOC_ECC_EN | DOC_ECC_RW, docptr, Mplus_ECCConf); + break; + } +} + +/* This code is only called on write */ +static int doc200x_calculate_ecc(struct mtd_info *mtd, const u_char *dat, + unsigned char *ecc_code) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + int emptymatch = 1; + + /* flush the pipeline */ + if (DoC_is_2000(doc)) { + WriteDOC(doc->CDSNControl & ~CDSN_CTRL_FLASH_IO, docptr, CDSNControl); + WriteDOC(0, docptr, 2k_CDSN_IO); + WriteDOC(0, docptr, 2k_CDSN_IO); + WriteDOC(0, docptr, 2k_CDSN_IO); + WriteDOC(doc->CDSNControl, docptr, CDSNControl); + } else if (DoC_is_MillenniumPlus(doc)) { + WriteDOC(0, docptr, Mplus_NOP); + WriteDOC(0, docptr, Mplus_NOP); + WriteDOC(0, docptr, Mplus_NOP); + } else { + WriteDOC(0, docptr, NOP); + WriteDOC(0, docptr, NOP); + WriteDOC(0, docptr, NOP); + } + + for (i = 0; i < 6; i++) { + if (DoC_is_MillenniumPlus(doc)) + ecc_code[i] = ReadDOC_(docptr, DoC_Mplus_ECCSyndrome0 + i); + else + ecc_code[i] = ReadDOC_(docptr, DoC_ECCSyndrome0 + i); + if (ecc_code[i] != empty_write_ecc[i]) + emptymatch = 0; + } + if (DoC_is_MillenniumPlus(doc)) + WriteDOC(DOC_ECC_DIS, docptr, Mplus_ECCConf); + else + WriteDOC(DOC_ECC_DIS, docptr, ECCConf); +#if 0 + /* If emptymatch=1, we might have an all-0xff data buffer. Check. */ + if (emptymatch) { + /* Note: this somewhat expensive test should not be triggered + often. It could be optimized away by examining the data in + the writebuf routine, and remembering the result. */ + for (i = 0; i < 512; i++) { + if (dat[i] == 0xff) continue; + emptymatch = 0; + break; + } + } + /* If emptymatch still =1, we do have an all-0xff data buffer. + Return all-0xff ecc value instead of the computed one, so + it'll look just like a freshly-erased page. */ + if (emptymatch) memset(ecc_code, 0xff, 6); +#endif + return 0; +} + +static int doc200x_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) +{ + int i, ret = 0; + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + volatile u_char dummy; + int emptymatch = 1; + + /* flush the pipeline */ + if (DoC_is_2000(doc)) { + dummy = ReadDOC(docptr, 2k_ECCStatus); + dummy = ReadDOC(docptr, 2k_ECCStatus); + dummy = ReadDOC(docptr, 2k_ECCStatus); + } else if (DoC_is_MillenniumPlus(doc)) { + dummy = ReadDOC(docptr, Mplus_ECCConf); + dummy = ReadDOC(docptr, Mplus_ECCConf); + dummy = ReadDOC(docptr, Mplus_ECCConf); + } else { + dummy = ReadDOC(docptr, ECCConf); + dummy = ReadDOC(docptr, ECCConf); + dummy = ReadDOC(docptr, ECCConf); + } + + /* Error occured ? */ + if (dummy & 0x80) { + for (i = 0; i < 6; i++) { + if (DoC_is_MillenniumPlus(doc)) + calc_ecc[i] = ReadDOC_(docptr, DoC_Mplus_ECCSyndrome0 + i); + else + calc_ecc[i] = ReadDOC_(docptr, DoC_ECCSyndrome0 + i); + if (calc_ecc[i] != empty_read_syndrome[i]) + emptymatch = 0; + } + /* If emptymatch=1, the read syndrome is consistent with an + all-0xff data and stored ecc block. Check the stored ecc. */ + if (emptymatch) { + for (i = 0; i < 6; i++) { + if (read_ecc[i] == 0xff) continue; + emptymatch = 0; + break; + } + } + /* If emptymatch still =1, check the data block. */ + if (emptymatch) { + /* Note: this somewhat expensive test should not be triggered + often. It could be optimized away by examining the data in + the readbuf routine, and remembering the result. */ + for (i = 0; i < 512; i++) { + if (dat[i] == 0xff) continue; + emptymatch = 0; + break; + } + } + /* If emptymatch still =1, this is almost certainly a freshly- + erased block, in which case the ECC will not come out right. + We'll suppress the error and tell the caller everything's + OK. Because it is. */ + if (!emptymatch) ret = doc_ecc_decode (rs_decoder, dat, calc_ecc); + if (ret > 0) + printk(KERN_ERR "doc200x_correct_data corrected %d errors\n", ret); + } + if (DoC_is_MillenniumPlus(doc)) + WriteDOC(DOC_ECC_DIS, docptr, Mplus_ECCConf); + else + WriteDOC(DOC_ECC_DIS, docptr, ECCConf); + if (no_ecc_failures && (ret == -1)) { + printk(KERN_ERR "suppressing ECC failure\n"); + ret = 0; + } + return ret; +} + +/*u_char mydatabuf[528]; */ + +static struct nand_oobinfo doc200x_oobinfo = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 6, + .eccpos = {0, 1, 2, 3, 4, 5}, + .oobfree = { {8, 8} } +}; + +/* Find the (I)NFTL Media Header, and optionally also the mirror media header. + On sucessful return, buf will contain a copy of the media header for + further processing. id is the string to scan for, and will presumably be + either "ANAND" or "BNAND". If findmirror=1, also look for the mirror media + header. The page #s of the found media headers are placed in mh0_page and + mh1_page in the DOC private structure. */ +static int __init find_media_headers(struct mtd_info *mtd, u_char *buf, + const char *id, int findmirror) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + unsigned offs, end = (MAX_MEDIAHEADER_SCAN << this->phys_erase_shift); + int ret; + size_t retlen; + + end = min(end, mtd->size); /* paranoia */ + for (offs = 0; offs < end; offs += mtd->erasesize) { + ret = mtd->read(mtd, offs, mtd->oobblock, &retlen, buf); + if (retlen != mtd->oobblock) continue; + if (ret) { + printk(KERN_WARNING "ECC error scanning DOC at 0x%x\n", + offs); + } + if (memcmp(buf, id, 6)) continue; + printk(KERN_INFO "Found DiskOnChip %s Media Header at 0x%x\n", id, offs); + if (doc->mh0_page == -1) { + doc->mh0_page = offs >> this->page_shift; + if (!findmirror) return 1; + continue; + } + doc->mh1_page = offs >> this->page_shift; + return 2; + } + if (doc->mh0_page == -1) { + printk(KERN_WARNING "DiskOnChip %s Media Header not found.\n", id); + return 0; + } + /* Only one mediaheader was found. We want buf to contain a + mediaheader on return, so we'll have to re-read the one we found. */ + offs = doc->mh0_page << this->page_shift; + ret = mtd->read(mtd, offs, mtd->oobblock, &retlen, buf); + if (retlen != mtd->oobblock) { + /* Insanity. Give up. */ + printk(KERN_ERR "Read DiskOnChip Media Header once, but can't reread it???\n"); + return 0; + } + return 1; +} + +static inline int __init nftl_partscan(struct mtd_info *mtd, + struct mtd_partition *parts) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + int ret = 0; + u_char *buf; + struct NFTLMediaHeader *mh; + const unsigned psize = 1 << this->page_shift; + unsigned blocks, maxblocks; + int offs, numheaders; + + buf = kmalloc(mtd->oobblock, GFP_KERNEL); + if (!buf) { + printk(KERN_ERR "DiskOnChip mediaheader kmalloc failed!\n"); + return 0; + } + if (!(numheaders=find_media_headers(mtd, buf, "ANAND", 1))) goto out; + mh = (struct NFTLMediaHeader *) buf; + +/*#ifdef CONFIG_MTD_DEBUG_VERBOSE */ +/* if (CONFIG_MTD_DEBUG_VERBOSE >= 2) */ + printk(KERN_INFO " DataOrgID = %s\n" + " NumEraseUnits = %d\n" + " FirstPhysicalEUN = %d\n" + " FormattedSize = %d\n" + " UnitSizeFactor = %d\n", + mh->DataOrgID, mh->NumEraseUnits, + mh->FirstPhysicalEUN, mh->FormattedSize, + mh->UnitSizeFactor); +/*#endif */ + + blocks = mtd->size >> this->phys_erase_shift; + maxblocks = min(32768U, mtd->erasesize - psize); + + if (mh->UnitSizeFactor == 0x00) { + /* Auto-determine UnitSizeFactor. The constraints are: + - There can be at most 32768 virtual blocks. + - There can be at most (virtual block size - page size) + virtual blocks (because MediaHeader+BBT must fit in 1). + */ + mh->UnitSizeFactor = 0xff; + while (blocks > maxblocks) { + blocks >>= 1; + maxblocks = min(32768U, (maxblocks << 1) + psize); + mh->UnitSizeFactor--; + } + printk(KERN_WARNING "UnitSizeFactor=0x00 detected. Correct value is assumed to be 0x%02x.\n", mh->UnitSizeFactor); + } + + /* NOTE: The lines below modify internal variables of the NAND and MTD + layers; variables with have already been configured by nand_scan. + Unfortunately, we didn't know before this point what these values + should be. Thus, this code is somewhat dependant on the exact + implementation of the NAND layer. */ + if (mh->UnitSizeFactor != 0xff) { + this->bbt_erase_shift += (0xff - mh->UnitSizeFactor); + mtd->erasesize <<= (0xff - mh->UnitSizeFactor); + printk(KERN_INFO "Setting virtual erase size to %d\n", mtd->erasesize); + blocks = mtd->size >> this->bbt_erase_shift; + maxblocks = min(32768U, mtd->erasesize - psize); + } + + if (blocks > maxblocks) { + printk(KERN_ERR "UnitSizeFactor of 0x%02x is inconsistent with device size. Aborting.\n", mh->UnitSizeFactor); + goto out; + } + + /* Skip past the media headers. */ + offs = max(doc->mh0_page, doc->mh1_page); + offs <<= this->page_shift; + offs += mtd->erasesize; + + /*parts[0].name = " DiskOnChip Boot / Media Header partition"; */ + /*parts[0].offset = 0; */ + /*parts[0].size = offs; */ + + parts[0].name = " DiskOnChip BDTL partition"; + parts[0].offset = offs; + parts[0].size = (mh->NumEraseUnits - numheaders) << this->bbt_erase_shift; + + offs += parts[0].size; + if (offs < mtd->size) { + parts[1].name = " DiskOnChip Remainder partition"; + parts[1].offset = offs; + parts[1].size = mtd->size - offs; + ret = 2; + goto out; + } + ret = 1; +out: + kfree(buf); + return ret; +} + +/* This is a stripped-down copy of the code in inftlmount.c */ +static inline int __init inftl_partscan(struct mtd_info *mtd, + struct mtd_partition *parts) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + int ret = 0; + u_char *buf; + struct INFTLMediaHeader *mh; + struct INFTLPartition *ip; + int numparts = 0; + int blocks; + int vshift, lastvunit = 0; + int i; + int end = mtd->size; + + if (inftl_bbt_write) + end -= (INFTL_BBT_RESERVED_BLOCKS << this->phys_erase_shift); + + buf = kmalloc(mtd->oobblock, GFP_KERNEL); + if (!buf) { + printk(KERN_ERR "DiskOnChip mediaheader kmalloc failed!\n"); + return 0; + } + + if (!find_media_headers(mtd, buf, "BNAND", 0)) goto out; + doc->mh1_page = doc->mh0_page + (4096 >> this->page_shift); + mh = (struct INFTLMediaHeader *) buf; + + mh->NoOfBootImageBlocks = le32_to_cpu(mh->NoOfBootImageBlocks); + mh->NoOfBinaryPartitions = le32_to_cpu(mh->NoOfBinaryPartitions); + mh->NoOfBDTLPartitions = le32_to_cpu(mh->NoOfBDTLPartitions); + mh->BlockMultiplierBits = le32_to_cpu(mh->BlockMultiplierBits); + mh->FormatFlags = le32_to_cpu(mh->FormatFlags); + mh->PercentUsed = le32_to_cpu(mh->PercentUsed); + +/*#ifdef CONFIG_MTD_DEBUG_VERBOSE */ +/* if (CONFIG_MTD_DEBUG_VERBOSE >= 2) */ + printk(KERN_INFO " bootRecordID = %s\n" + " NoOfBootImageBlocks = %d\n" + " NoOfBinaryPartitions = %d\n" + " NoOfBDTLPartitions = %d\n" + " BlockMultiplerBits = %d\n" + " FormatFlgs = %d\n" + " OsakVersion = %d.%d.%d.%d\n" + " PercentUsed = %d\n", + mh->bootRecordID, mh->NoOfBootImageBlocks, + mh->NoOfBinaryPartitions, + mh->NoOfBDTLPartitions, + mh->BlockMultiplierBits, mh->FormatFlags, + ((unsigned char *) &mh->OsakVersion)[0] & 0xf, + ((unsigned char *) &mh->OsakVersion)[1] & 0xf, + ((unsigned char *) &mh->OsakVersion)[2] & 0xf, + ((unsigned char *) &mh->OsakVersion)[3] & 0xf, + mh->PercentUsed); +/*#endif */ + + vshift = this->phys_erase_shift + mh->BlockMultiplierBits; + + blocks = mtd->size >> vshift; + if (blocks > 32768) { + printk(KERN_ERR "BlockMultiplierBits=%d is inconsistent with device size. Aborting.\n", mh->BlockMultiplierBits); + goto out; + } + + blocks = doc->chips_per_floor << (this->chip_shift - this->phys_erase_shift); + if (inftl_bbt_write && (blocks > mtd->erasesize)) { + printk(KERN_ERR "Writeable BBTs spanning more than one erase block are not yet supported. FIX ME!\n"); + goto out; + } + + /* Scan the partitions */ + for (i = 0; (i < 4); i++) { + ip = &(mh->Partitions[i]); + ip->virtualUnits = le32_to_cpu(ip->virtualUnits); + ip->firstUnit = le32_to_cpu(ip->firstUnit); + ip->lastUnit = le32_to_cpu(ip->lastUnit); + ip->flags = le32_to_cpu(ip->flags); + ip->spareUnits = le32_to_cpu(ip->spareUnits); + ip->Reserved0 = le32_to_cpu(ip->Reserved0); + +/*#ifdef CONFIG_MTD_DEBUG_VERBOSE */ +/* if (CONFIG_MTD_DEBUG_VERBOSE >= 2) */ + printk(KERN_INFO " PARTITION[%d] ->\n" + " virtualUnits = %d\n" + " firstUnit = %d\n" + " lastUnit = %d\n" + " flags = 0x%x\n" + " spareUnits = %d\n", + i, ip->virtualUnits, ip->firstUnit, + ip->lastUnit, ip->flags, + ip->spareUnits); +/*#endif */ + +/* + if ((i == 0) && (ip->firstUnit > 0)) { + parts[0].name = " DiskOnChip IPL / Media Header partition"; + parts[0].offset = 0; + parts[0].size = mtd->erasesize * ip->firstUnit; + numparts = 1; + } +*/ + + if (ip->flags & INFTL_BINARY) + parts[numparts].name = " DiskOnChip BDK partition"; + else + parts[numparts].name = " DiskOnChip BDTL partition"; + parts[numparts].offset = ip->firstUnit << vshift; + parts[numparts].size = (1 + ip->lastUnit - ip->firstUnit) << vshift; + numparts++; + if (ip->lastUnit > lastvunit) lastvunit = ip->lastUnit; + if (ip->flags & INFTL_LAST) break; + } + lastvunit++; + if ((lastvunit << vshift) < end) { + parts[numparts].name = " DiskOnChip Remainder partition"; + parts[numparts].offset = lastvunit << vshift; + parts[numparts].size = end - parts[numparts].offset; + numparts++; + } + ret = numparts; +out: + kfree(buf); + return ret; +} + +static int __init nftl_scan_bbt(struct mtd_info *mtd) +{ + int ret, numparts; + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + struct mtd_partition parts[2]; + + memset((char *) parts, 0, sizeof(parts)); + /* On NFTL, we have to find the media headers before we can read the + BBTs, since they're stored in the media header eraseblocks. */ + numparts = nftl_partscan(mtd, parts); + if (!numparts) return -EIO; + this->bbt_td->options = NAND_BBT_ABSPAGE | NAND_BBT_8BIT | + NAND_BBT_SAVECONTENT | NAND_BBT_WRITE | + NAND_BBT_VERSION; + this->bbt_td->veroffs = 7; + this->bbt_td->pages[0] = doc->mh0_page + 1; + if (doc->mh1_page != -1) { + this->bbt_md->options = NAND_BBT_ABSPAGE | NAND_BBT_8BIT | + NAND_BBT_SAVECONTENT | NAND_BBT_WRITE | + NAND_BBT_VERSION; + this->bbt_md->veroffs = 7; + this->bbt_md->pages[0] = doc->mh1_page + 1; + } else { + this->bbt_md = NULL; + } + + /* It's safe to set bd=NULL below because NAND_BBT_CREATE is not set. + At least as nand_bbt.c is currently written. */ + if ((ret = nand_scan_bbt(mtd, NULL))) + return ret; + add_mtd_device(mtd); +#ifdef CONFIG_MTD_PARTITIONS + if (!no_autopart) + add_mtd_partitions(mtd, parts, numparts); +#endif + return 0; +} + +static int __init inftl_scan_bbt(struct mtd_info *mtd) +{ + int ret, numparts; + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + struct mtd_partition parts[5]; + + if (this->numchips > doc->chips_per_floor) { + printk(KERN_ERR "Multi-floor INFTL devices not yet supported.\n"); + return -EIO; + } + + if (DoC_is_MillenniumPlus(doc)) { + this->bbt_td->options = NAND_BBT_2BIT | NAND_BBT_ABSPAGE; + if (inftl_bbt_write) + this->bbt_td->options |= NAND_BBT_WRITE; + this->bbt_td->pages[0] = 2; + this->bbt_md = NULL; + } else { + this->bbt_td->options = NAND_BBT_LASTBLOCK | NAND_BBT_8BIT | + NAND_BBT_VERSION; + if (inftl_bbt_write) + this->bbt_td->options |= NAND_BBT_WRITE; + this->bbt_td->offs = 8; + this->bbt_td->len = 8; + this->bbt_td->veroffs = 7; + this->bbt_td->maxblocks = INFTL_BBT_RESERVED_BLOCKS; + this->bbt_td->reserved_block_code = 0x01; + this->bbt_td->pattern = "MSYS_BBT"; + + this->bbt_md->options = NAND_BBT_LASTBLOCK | NAND_BBT_8BIT | + NAND_BBT_VERSION; + if (inftl_bbt_write) + this->bbt_md->options |= NAND_BBT_WRITE; + this->bbt_md->offs = 8; + this->bbt_md->len = 8; + this->bbt_md->veroffs = 7; + this->bbt_md->maxblocks = INFTL_BBT_RESERVED_BLOCKS; + this->bbt_md->reserved_block_code = 0x01; + this->bbt_md->pattern = "TBB_SYSM"; + } + + /* It's safe to set bd=NULL below because NAND_BBT_CREATE is not set. + At least as nand_bbt.c is currently written. */ + if ((ret = nand_scan_bbt(mtd, NULL))) + return ret; + memset((char *) parts, 0, sizeof(parts)); + numparts = inftl_partscan(mtd, parts); + /* At least for now, require the INFTL Media Header. We could probably + do without it for non-INFTL use, since all it gives us is + autopartitioning, but I want to give it more thought. */ + if (!numparts) return -EIO; + add_mtd_device(mtd); +#ifdef CONFIG_MTD_PARTITIONS + if (!no_autopart) + add_mtd_partitions(mtd, parts, numparts); +#endif + return 0; +} + +static inline int __init doc2000_init(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + + this->write_byte = doc2000_write_byte; + this->read_byte = doc2000_read_byte; + this->write_buf = doc2000_writebuf; + this->read_buf = doc2000_readbuf; + this->verify_buf = doc2000_verifybuf; + this->scan_bbt = nftl_scan_bbt; + + doc->CDSNControl = CDSN_CTRL_FLASH_IO | CDSN_CTRL_ECC_IO; + doc2000_count_chips(mtd); + mtd->name = "DiskOnChip 2000 (NFTL Model)"; + return (4 * doc->chips_per_floor); +} + +static inline int __init doc2001_init(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + + this->write_byte = doc2001_write_byte; + this->read_byte = doc2001_read_byte; + this->write_buf = doc2001_writebuf; + this->read_buf = doc2001_readbuf; + this->verify_buf = doc2001_verifybuf; + + ReadDOC(doc->virtadr, ChipID); + ReadDOC(doc->virtadr, ChipID); + ReadDOC(doc->virtadr, ChipID); + if (ReadDOC(doc->virtadr, ChipID) != DOC_ChipID_DocMil) { + /* It's not a Millennium; it's one of the newer + DiskOnChip 2000 units with a similar ASIC. + Treat it like a Millennium, except that it + can have multiple chips. */ + doc2000_count_chips(mtd); + mtd->name = "DiskOnChip 2000 (INFTL Model)"; + this->scan_bbt = inftl_scan_bbt; + return (4 * doc->chips_per_floor); + } else { + /* Bog-standard Millennium */ + doc->chips_per_floor = 1; + mtd->name = "DiskOnChip Millennium"; + this->scan_bbt = nftl_scan_bbt; + return 1; + } +} + +static inline int __init doc2001plus_init(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + + this->write_byte = NULL; + this->read_byte = doc2001plus_read_byte; + this->write_buf = doc2001plus_writebuf; + this->read_buf = doc2001plus_readbuf; + this->verify_buf = doc2001plus_verifybuf; + this->scan_bbt = inftl_scan_bbt; + this->hwcontrol = NULL; + this->select_chip = doc2001plus_select_chip; + this->cmdfunc = doc2001plus_command; + this->enable_hwecc = doc2001plus_enable_hwecc; + + doc->chips_per_floor = 1; + mtd->name = "DiskOnChip Millennium Plus"; + + return 1; +} + +static inline int __init doc_probe(unsigned long physadr) +{ + unsigned char ChipID; + struct mtd_info *mtd; + struct nand_chip *nand; + struct doc_priv *doc; + void __iomem *virtadr; + unsigned char save_control; + unsigned char tmp, tmpb, tmpc; + int reg, len, numchips; + int ret = 0; + + virtadr = ioremap(physadr, DOC_IOREMAP_LEN); + if (!virtadr) { + printk(KERN_ERR "Diskonchip ioremap failed: 0x%x bytes at 0x%lx\n", DOC_IOREMAP_LEN, physadr); + return -EIO; + } + + /* It's not possible to cleanly detect the DiskOnChip - the + * bootup procedure will put the device into reset mode, and + * it's not possible to talk to it without actually writing + * to the DOCControl register. So we store the current contents + * of the DOCControl register's location, in case we later decide + * that it's not a DiskOnChip, and want to put it back how we + * found it. + */ + save_control = ReadDOC(virtadr, DOCControl); + + /* Reset the DiskOnChip ASIC */ + WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_RESET, + virtadr, DOCControl); + WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_RESET, + virtadr, DOCControl); + + /* Enable the DiskOnChip ASIC */ + WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_NORMAL, + virtadr, DOCControl); + WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_NORMAL, + virtadr, DOCControl); + + ChipID = ReadDOC(virtadr, ChipID); + + switch(ChipID) { + case DOC_ChipID_Doc2k: + reg = DoC_2k_ECCStatus; + break; + case DOC_ChipID_DocMil: + reg = DoC_ECCConf; + break; + case DOC_ChipID_DocMilPlus16: + case DOC_ChipID_DocMilPlus32: + case 0: + /* Possible Millennium Plus, need to do more checks */ + /* Possibly release from power down mode */ + for (tmp = 0; (tmp < 4); tmp++) + ReadDOC(virtadr, Mplus_Power); + + /* Reset the Millennium Plus ASIC */ + tmp = DOC_MODE_RESET | DOC_MODE_MDWREN | DOC_MODE_RST_LAT | + DOC_MODE_BDECT; + WriteDOC(tmp, virtadr, Mplus_DOCControl); + WriteDOC(~tmp, virtadr, Mplus_CtrlConfirm); + + mdelay(1); + /* Enable the Millennium Plus ASIC */ + tmp = DOC_MODE_NORMAL | DOC_MODE_MDWREN | DOC_MODE_RST_LAT | + DOC_MODE_BDECT; + WriteDOC(tmp, virtadr, Mplus_DOCControl); + WriteDOC(~tmp, virtadr, Mplus_CtrlConfirm); + mdelay(1); + + ChipID = ReadDOC(virtadr, ChipID); + + switch (ChipID) { + case DOC_ChipID_DocMilPlus16: + reg = DoC_Mplus_Toggle; + break; + case DOC_ChipID_DocMilPlus32: + printk(KERN_ERR "DiskOnChip Millennium Plus 32MB is not supported, ignoring.\n"); + default: + ret = -ENODEV; + goto notfound; + } + break; + + default: + ret = -ENODEV; + goto notfound; + } + /* Check the TOGGLE bit in the ECC register */ + tmp = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT; + tmpb = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT; + tmpc = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT; + if ((tmp == tmpb) || (tmp != tmpc)) { + printk(KERN_WARNING "Possible DiskOnChip at 0x%lx failed TOGGLE test, dropping.\n", physadr); + ret = -ENODEV; + goto notfound; + } + + for (mtd = doclist; mtd; mtd = doc->nextdoc) { + unsigned char oldval; + unsigned char newval; + nand = mtd->priv; + doc = nand->priv; + /* Use the alias resolution register to determine if this is + in fact the same DOC aliased to a new address. If writes + to one chip's alias resolution register change the value on + the other chip, they're the same chip. */ + if (ChipID == DOC_ChipID_DocMilPlus16) { + oldval = ReadDOC(doc->virtadr, Mplus_AliasResolution); + newval = ReadDOC(virtadr, Mplus_AliasResolution); + } else { + oldval = ReadDOC(doc->virtadr, AliasResolution); + newval = ReadDOC(virtadr, AliasResolution); + } + if (oldval != newval) + continue; + if (ChipID == DOC_ChipID_DocMilPlus16) { + WriteDOC(~newval, virtadr, Mplus_AliasResolution); + oldval = ReadDOC(doc->virtadr, Mplus_AliasResolution); + WriteDOC(newval, virtadr, Mplus_AliasResolution); /* restore it */ + } else { + WriteDOC(~newval, virtadr, AliasResolution); + oldval = ReadDOC(doc->virtadr, AliasResolution); + WriteDOC(newval, virtadr, AliasResolution); /* restore it */ + } + newval = ~newval; + if (oldval == newval) { + printk(KERN_DEBUG "Found alias of DOC at 0x%lx to 0x%lx\n", doc->physadr, physadr); + goto notfound; + } + } + + printk(KERN_NOTICE "DiskOnChip found at 0x%lx\n", physadr); + + len = sizeof(struct mtd_info) + + sizeof(struct nand_chip) + + sizeof(struct doc_priv) + + (2 * sizeof(struct nand_bbt_descr)); + mtd = kmalloc(len, GFP_KERNEL); + if (!mtd) { + printk(KERN_ERR "DiskOnChip kmalloc (%d bytes) failed!\n", len); + ret = -ENOMEM; + goto fail; + } + memset(mtd, 0, len); + + nand = (struct nand_chip *) (mtd + 1); + doc = (struct doc_priv *) (nand + 1); + nand->bbt_td = (struct nand_bbt_descr *) (doc + 1); + nand->bbt_md = nand->bbt_td + 1; + + mtd->priv = nand; + mtd->owner = THIS_MODULE; + + nand->priv = doc; + nand->select_chip = doc200x_select_chip; + nand->hwcontrol = doc200x_hwcontrol; + nand->dev_ready = doc200x_dev_ready; + nand->waitfunc = doc200x_wait; + nand->block_bad = doc200x_block_bad; + nand->enable_hwecc = doc200x_enable_hwecc; + nand->calculate_ecc = doc200x_calculate_ecc; + nand->correct_data = doc200x_correct_data; + + nand->autooob = &doc200x_oobinfo; + nand->eccmode = NAND_ECC_HW6_512; + nand->options = NAND_USE_FLASH_BBT | NAND_HWECC_SYNDROME; + + doc->physadr = physadr; + doc->virtadr = virtadr; + doc->ChipID = ChipID; + doc->curfloor = -1; + doc->curchip = -1; + doc->mh0_page = -1; + doc->mh1_page = -1; + doc->nextdoc = doclist; + + if (ChipID == DOC_ChipID_Doc2k) + numchips = doc2000_init(mtd); + else if (ChipID == DOC_ChipID_DocMilPlus16) + numchips = doc2001plus_init(mtd); + else + numchips = doc2001_init(mtd); + + if ((ret = nand_scan(mtd, numchips))) { + /* DBB note: i believe nand_release is necessary here, as + buffers may have been allocated in nand_base. Check with + Thomas. FIX ME! */ + /* nand_release will call del_mtd_device, but we haven't yet + added it. This is handled without incident by + del_mtd_device, as far as I can tell. */ + nand_release(mtd); + kfree(mtd); + goto fail; + } + + /* Success! */ + doclist = mtd; + return 0; + +notfound: + /* Put back the contents of the DOCControl register, in case it's not + actually a DiskOnChip. */ + WriteDOC(save_control, virtadr, DOCControl); +fail: + iounmap(virtadr); + return ret; +} + +static void release_nanddoc(void) +{ + struct mtd_info *mtd, *nextmtd; + struct nand_chip *nand; + struct doc_priv *doc; + + for (mtd = doclist; mtd; mtd = nextmtd) { + nand = mtd->priv; + doc = nand->priv; + + nextmtd = doc->nextdoc; + nand_release(mtd); + iounmap(doc->virtadr); + kfree(mtd); + } +} + +static int __init init_nanddoc(void) +{ + int i, ret = 0; + + /* We could create the decoder on demand, if memory is a concern. + * This way we have it handy, if an error happens + * + * Symbolsize is 10 (bits) + * Primitve polynomial is x^10+x^3+1 + * first consecutive root is 510 + * primitve element to generate roots = 1 + * generator polinomial degree = 4 + */ + rs_decoder = init_rs(10, 0x409, FCR, 1, NROOTS); + if (!rs_decoder) { + printk (KERN_ERR "DiskOnChip: Could not create a RS decoder\n"); + return -ENOMEM; + } + + if (doc_config_location) { + printk(KERN_INFO "Using configured DiskOnChip probe address 0x%lx\n", doc_config_location); + ret = doc_probe(doc_config_location); + if (ret < 0) + goto outerr; + } else { + for (i=0; (doc_locations[i] != 0xffffffff); i++) { + doc_probe(doc_locations[i]); + } + } + /* No banner message any more. Print a message if no DiskOnChip + found, so the user knows we at least tried. */ + if (!doclist) { + printk(KERN_INFO "No valid DiskOnChip devices found\n"); + ret = -ENODEV; + goto outerr; + } + return 0; +outerr: + free_rs(rs_decoder); + return ret; +} + +static void __exit cleanup_nanddoc(void) +{ + /* Cleanup the nand/DoC resources */ + release_nanddoc(); + + /* Free the reed solomon resources */ + if (rs_decoder) { + free_rs(rs_decoder); + } +} + +module_init(init_nanddoc); +module_exit(cleanup_nanddoc); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>"); +MODULE_DESCRIPTION("M-Systems DiskOnChip 2000, Millennium and Millennium Plus device driver\n"); diff --git a/drivers/nand/nand.c b/drivers/nand/nand.c new file mode 100644 index 0000000..dd80026 --- /dev/null +++ b/drivers/nand/nand.c @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2005 + * 2N Telekomunikace, a.s. <www.2n.cz> + * Ladislav Michl <michl@2n.cz> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#ifdef CFG_NAND_LEGACY +#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support! +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <nand.h> + +#ifndef CFG_NAND_BASE_LIST +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#endif + +int nand_curr_device = -1; +nand_info_t nand_info[CFG_MAX_NAND_DEVICE]; + +static struct nand_chip nand_chip[CFG_MAX_NAND_DEVICE]; +static ulong base_address[CFG_MAX_NAND_DEVICE] = CFG_NAND_BASE_LIST; + +static const char default_nand_name[] = "nand"; + +extern void board_nand_init(struct nand_chip *nand); + +static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand, + ulong base_addr) +{ + mtd->priv = nand; + + nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr; + board_nand_init(nand); + + if (nand_scan(mtd, 1) == 0) { + if (!mtd->name) + mtd->name = (char *)default_nand_name; + } else + mtd->name = NULL; + +} + +void nand_init(void) +{ + int i; + unsigned int size = 0; + for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) { + nand_init_chip(&nand_info[i], &nand_chip[i], base_address[i]); + size += nand_info[i].size; + if (nand_curr_device == -1) + nand_curr_device = i; +} + printf("%lu MiB\n", size / (1024 * 1024)); +} + +#endif diff --git a/drivers/nand/nand_base.c b/drivers/nand/nand_base.c new file mode 100644 index 0000000..e0b4060 --- /dev/null +++ b/drivers/nand/nand_base.c @@ -0,0 +1,2669 @@ +/* + * drivers/mtd/nand.c + * + * Overview: + * This is the generic MTD driver for NAND flash devices. It should be + * capable of working with almost all NAND chips currently available. + * Basic support for AG-AND chips is provided. + * + * Additional technical information is available on + * http://www.linux-mtd.infradead.org/tech/nand.html + * + * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) + * 2002 Thomas Gleixner (tglx@linutronix.de) + * + * 02-08-2004 tglx: support for strange chips, which cannot auto increment + * pages on read / read_oob + * + * 03-17-2004 tglx: Check ready before auto increment check. Simon Bayes + * pointed this out, as he marked an auto increment capable chip + * as NOAUTOINCR in the board driver. + * Make reads over block boundaries work too + * + * 04-14-2004 tglx: first working version for 2k page size chips + * + * 05-19-2004 tglx: Basic support for Renesas AG-AND chips + * + * 09-24-2004 tglx: add support for hardware controllers (e.g. ECC) shared + * among multiple independend devices. Suggestions and initial patch + * from Ben Dooks <ben-mtd@fluff.org> + * + * Credits: + * David Woodhouse for adding multichip support + * + * Aleph One Ltd. and Toby Churchill Ltd. for supporting the + * rework for 2K page size chips + * + * TODO: + * Enable cached programming for 2k page size chips + * Check, if mtd->ecctype should be set to MTD_ECC_HW + * if we have HW ecc support. + * The AG-AND chips have nice features for speed improvement, + * which are not supported yet. Read / program 4 pages in one go. + * + * $Id: nand_base.c,v 1.126 2004/12/13 11:22:25 lavinen Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/* XXX U-BOOT XXX */ +#if 0 +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <linux/types.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/nand_ecc.h> +#include <linux/mtd/compatmac.h> +#include <linux/interrupt.h> +#include <linux/bitops.h> +#include <asm/io.h> + +#ifdef CONFIG_MTD_PARTITIONS +#include <linux/mtd/partitions.h> +#endif + +#endif + +#include <common.h> + +#ifdef CFG_NAND_LEGACY +#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support! +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <malloc.h> +#include <watchdog.h> +#include <linux/mtd/compat.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/nand_ecc.h> + +#include <asm/io.h> +#include <asm/errno.h> + +#ifdef CONFIG_JFFS2_NAND +#include <jffs2/jffs2.h> +#endif + +/* Define default oob placement schemes for large and small page devices */ +static struct nand_oobinfo nand_oob_8 = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 3, + .eccpos = {0, 1, 2}, + .oobfree = { {3, 2}, {6, 2} } +}; + +static struct nand_oobinfo nand_oob_16 = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 6, + .eccpos = {0, 1, 2, 3, 6, 7}, + .oobfree = { {8, 8} } +}; + +static struct nand_oobinfo nand_oob_64 = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 24, + .eccpos = { + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63}, + .oobfree = { {2, 38} } +}; + +/* This is used for padding purposes in nand_write_oob */ +static u_char ffchars[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +}; + +/* + * NAND low-level MTD interface functions + */ +static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len); +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len); +static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len); + +static int nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf); +static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, + size_t * retlen, u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel); +static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf); +static int nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf); +static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len, + size_t * retlen, const u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel); +static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char *buf); +/* XXX U-BOOT XXX */ +#if 0 +static int nand_writev (struct mtd_info *mtd, const struct kvec *vecs, + unsigned long count, loff_t to, size_t * retlen); +static int nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs, + unsigned long count, loff_t to, size_t * retlen, u_char *eccbuf, struct nand_oobinfo *oobsel); +#endif +static int nand_erase (struct mtd_info *mtd, struct erase_info *instr); +static void nand_sync (struct mtd_info *mtd); + +/* Some internal functions */ +static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page, u_char *oob_buf, + struct nand_oobinfo *oobsel, int mode); +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE +static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int page, int numpages, + u_char *oob_buf, struct nand_oobinfo *oobsel, int chipnr, int oobmode); +#else +#define nand_verify_pages(...) (0) +#endif + +static void nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state); + +/** + * nand_release_device - [GENERIC] release chip + * @mtd: MTD device structure + * + * Deselect, release chip lock and wake up anyone waiting on the device + */ +/* XXX U-BOOT XXX */ +#if 0 +static void nand_release_device (struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + + /* De-select the NAND device */ + this->select_chip(mtd, -1); + /* Do we have a hardware controller ? */ + if (this->controller) { + spin_lock(&this->controller->lock); + this->controller->active = NULL; + spin_unlock(&this->controller->lock); + } + /* Release the chip */ + spin_lock (&this->chip_lock); + this->state = FL_READY; + wake_up (&this->wq); + spin_unlock (&this->chip_lock); +} +#else +static void nand_release_device (struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + this->select_chip(mtd, -1); /* De-select the NAND device */ +} +#endif + +/** + * nand_read_byte - [DEFAULT] read one byte from the chip + * @mtd: MTD device structure + * + * Default read function for 8bit buswith + */ +static u_char nand_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + return readb(this->IO_ADDR_R); +} + +/** + * nand_write_byte - [DEFAULT] write one byte to the chip + * @mtd: MTD device structure + * @byte: pointer to data byte to write + * + * Default write function for 8it buswith + */ +static void nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + struct nand_chip *this = mtd->priv; + writeb(byte, this->IO_ADDR_W); +} + +/** + * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip + * @mtd: MTD device structure + * + * Default read function for 16bit buswith with + * endianess conversion + */ +static u_char nand_read_byte16(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + return (u_char) cpu_to_le16(readw(this->IO_ADDR_R)); +} + +/** + * nand_write_byte16 - [DEFAULT] write one byte endianess aware to the chip + * @mtd: MTD device structure + * @byte: pointer to data byte to write + * + * Default write function for 16bit buswith with + * endianess conversion + */ +static void nand_write_byte16(struct mtd_info *mtd, u_char byte) +{ + struct nand_chip *this = mtd->priv; + writew(le16_to_cpu((u16) byte), this->IO_ADDR_W); +} + +/** + * nand_read_word - [DEFAULT] read one word from the chip + * @mtd: MTD device structure + * + * Default read function for 16bit buswith without + * endianess conversion + */ +static u16 nand_read_word(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + return readw(this->IO_ADDR_R); +} + +/** + * nand_write_word - [DEFAULT] write one word to the chip + * @mtd: MTD device structure + * @word: data word to write + * + * Default write function for 16bit buswith without + * endianess conversion + */ +static void nand_write_word(struct mtd_info *mtd, u16 word) +{ + struct nand_chip *this = mtd->priv; + writew(word, this->IO_ADDR_W); +} + +/** + * nand_select_chip - [DEFAULT] control CE line + * @mtd: MTD device structure + * @chip: chipnumber to select, -1 for deselect + * + * Default select function for 1 chip devices. + */ +static void nand_select_chip(struct mtd_info *mtd, int chip) +{ + struct nand_chip *this = mtd->priv; + switch(chip) { + case -1: + this->hwcontrol(mtd, NAND_CTL_CLRNCE); + break; + case 0: + this->hwcontrol(mtd, NAND_CTL_SETNCE); + break; + + default: + BUG(); + } +} + +/** + * nand_write_buf - [DEFAULT] write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + * + * Default write function for 8bit buswith + */ +static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i=0; i<len; i++) + writeb(buf[i], this->IO_ADDR_W); +} + +/** + * nand_read_buf - [DEFAULT] read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + * + * Default read function for 8bit buswith + */ +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i=0; i<len; i++) + buf[i] = readb(this->IO_ADDR_R); +} + +/** + * nand_verify_buf - [DEFAULT] Verify chip data against buffer + * @mtd: MTD device structure + * @buf: buffer containing the data to compare + * @len: number of bytes to compare + * + * Default verify function for 8bit buswith + */ +static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i=0; i<len; i++) + if (buf[i] != readb(this->IO_ADDR_R)) + return -EFAULT; + + return 0; +} + +/** + * nand_write_buf16 - [DEFAULT] write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + * + * Default write function for 16bit buswith + */ +static void nand_write_buf16(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u16 *p = (u16 *) buf; + len >>= 1; + + for (i=0; i<len; i++) + writew(p[i], this->IO_ADDR_W); + +} + +/** + * nand_read_buf16 - [DEFAULT] read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + * + * Default read function for 16bit buswith + */ +static void nand_read_buf16(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u16 *p = (u16 *) buf; + len >>= 1; + + for (i=0; i<len; i++) + p[i] = readw(this->IO_ADDR_R); +} + +/** + * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer + * @mtd: MTD device structure + * @buf: buffer containing the data to compare + * @len: number of bytes to compare + * + * Default verify function for 16bit buswith + */ +static int nand_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u16 *p = (u16 *) buf; + len >>= 1; + + for (i=0; i<len; i++) + if (p[i] != readw(this->IO_ADDR_R)) + return -EFAULT; + + return 0; +} + +/** + * nand_block_bad - [DEFAULT] Read bad block marker from the chip + * @mtd: MTD device structure + * @ofs: offset from device start + * @getchip: 0, if the chip is already selected + * + * Check, if the block is bad. + */ +static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) +{ + int page, chipnr, res = 0; + struct nand_chip *this = mtd->priv; + u16 bad; + + if (getchip) { + page = (int)(ofs >> this->page_shift); + chipnr = (int)(ofs >> this->chip_shift); + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd, FL_READING); + + /* Select the NAND device */ + this->select_chip(mtd, chipnr); + } else + page = (int) ofs; + + if (this->options & NAND_BUSWIDTH_16) { + this->cmdfunc (mtd, NAND_CMD_READOOB, this->badblockpos & 0xFE, page & this->pagemask); + bad = cpu_to_le16(this->read_word(mtd)); + if (this->badblockpos & 0x1) + bad >>= 1; + if ((bad & 0xFF) != 0xff) + res = 1; + } else { + this->cmdfunc (mtd, NAND_CMD_READOOB, this->badblockpos, page & this->pagemask); + if (this->read_byte(mtd) != 0xff) + res = 1; + } + + if (getchip) { + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + } + + return res; +} + +/** + * nand_default_block_markbad - [DEFAULT] mark a block bad + * @mtd: MTD device structure + * @ofs: offset from device start + * + * This is the default implementation, which can be overridden by + * a hardware specific driver. +*/ +static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) +{ + struct nand_chip *this = mtd->priv; + u_char buf[2] = {0, 0}; + size_t retlen; + int block; + + /* Get block number */ + block = ((int) ofs) >> this->bbt_erase_shift; + this->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); + + /* Do we have a flash based bad block table ? */ + if (this->options & NAND_USE_FLASH_BBT) + return nand_update_bbt (mtd, ofs); + + /* We write two bytes, so we dont have to mess with 16 bit access */ + ofs += mtd->oobsize + (this->badblockpos & ~0x01); + return nand_write_oob (mtd, ofs , 2, &retlen, buf); +} + +/** + * nand_check_wp - [GENERIC] check if the chip is write protected + * @mtd: MTD device structure + * Check, if the device is write protected + * + * The function expects, that the device is already selected + */ +static int nand_check_wp (struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + /* Check the WP bit */ + this->cmdfunc (mtd, NAND_CMD_STATUS, -1, -1); + return (this->read_byte(mtd) & 0x80) ? 0 : 1; +} + +/** + * nand_block_checkbad - [GENERIC] Check if a block is marked bad + * @mtd: MTD device structure + * @ofs: offset from device start + * @getchip: 0, if the chip is already selected + * @allowbbt: 1, if its allowed to access the bbt area + * + * Check, if the block is bad. Either by reading the bad block table or + * calling of the scan function. + */ +static int nand_block_checkbad (struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt) +{ + struct nand_chip *this = mtd->priv; + + if (!this->bbt) + return this->block_bad(mtd, ofs, getchip); + + /* Return info from the table */ + return nand_isbad_bbt (mtd, ofs, allowbbt); +} + +/** + * nand_command - [DEFAULT] Send command to NAND device + * @mtd: MTD device structure + * @command: the command to be sent + * @column: the column address for this command, -1 if none + * @page_addr: the page address for this command, -1 if none + * + * Send command to NAND device. This function is used for small page + * devices (256/512 Bytes per page) + */ +static void nand_command (struct mtd_info *mtd, unsigned command, int column, int page_addr) +{ + register struct nand_chip *this = mtd->priv; + + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* + * Write out the command to the device. + */ + if (command == NAND_CMD_SEQIN) { + int readcmd; + + if (column >= mtd->oobblock) { + /* OOB area */ + column -= mtd->oobblock; + readcmd = NAND_CMD_READOOB; + } else if (column < 256) { + /* First 256 bytes --> READ0 */ + readcmd = NAND_CMD_READ0; + } else { + column -= 256; + readcmd = NAND_CMD_READ1; + } + this->write_byte(mtd, readcmd); + } + this->write_byte(mtd, command); + + /* Set ALE and clear CLE to start address cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + + if (column != -1 || page_addr != -1) { + this->hwcontrol(mtd, NAND_CTL_SETALE); + + /* Serially input address */ + if (column != -1) { + /* Adjust columns for 16 bit buswidth */ + if (this->options & NAND_BUSWIDTH_16) + column >>= 1; + this->write_byte(mtd, column); + } + if (page_addr != -1) { + this->write_byte(mtd, (unsigned char) (page_addr & 0xff)); + this->write_byte(mtd, (unsigned char) ((page_addr >> 8) & 0xff)); + /* One more address cycle for devices > 32MiB */ + if (this->chipsize > (32 << 20)) + this->write_byte(mtd, (unsigned char) ((page_addr >> 16) & 0x0f)); + } + /* Latch in address */ + this->hwcontrol(mtd, NAND_CTL_CLRALE); + } + + /* + * program and erase have their own busy handlers + * status and sequential in needs no delay + */ + switch (command) { + + case NAND_CMD_PAGEPROG: + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + case NAND_CMD_SEQIN: + case NAND_CMD_STATUS: + return; + + case NAND_CMD_RESET: + if (this->dev_ready) + break; + udelay(this->chip_delay); + this->hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_STATUS); + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + while ( !(this->read_byte(mtd) & 0x40)); + return; + + /* This applies to read commands */ + default: + /* + * If we don't have access to the busy pin, we apply the given + * command delay + */ + if (!this->dev_ready) { + udelay (this->chip_delay); + return; + } + } + + /* Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. */ + ndelay (100); + /* wait until command is processed */ + while (!this->dev_ready(mtd)); +} + +/** + * nand_command_lp - [DEFAULT] Send command to NAND large page device + * @mtd: MTD device structure + * @command: the command to be sent + * @column: the column address for this command, -1 if none + * @page_addr: the page address for this command, -1 if none + * + * Send command to NAND device. This is the version for the new large page devices + * We dont have the seperate regions as we have in the small page devices. + * We must emulate NAND_CMD_READOOB to keep the code compatible. + * + */ +static void nand_command_lp (struct mtd_info *mtd, unsigned command, int column, int page_addr) +{ + register struct nand_chip *this = mtd->priv; + + /* Emulate NAND_CMD_READOOB */ + if (command == NAND_CMD_READOOB) { + column += mtd->oobblock; + command = NAND_CMD_READ0; + } + + + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* Write out the command to the device. */ + this->write_byte(mtd, command); + /* End command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + + if (column != -1 || page_addr != -1) { + this->hwcontrol(mtd, NAND_CTL_SETALE); + + /* Serially input address */ + if (column != -1) { + /* Adjust columns for 16 bit buswidth */ + if (this->options & NAND_BUSWIDTH_16) + column >>= 1; + this->write_byte(mtd, column & 0xff); + this->write_byte(mtd, column >> 8); + } + if (page_addr != -1) { + this->write_byte(mtd, (unsigned char) (page_addr & 0xff)); + this->write_byte(mtd, (unsigned char) ((page_addr >> 8) & 0xff)); + /* One more address cycle for devices > 128MiB */ + if (this->chipsize > (128 << 20)) + this->write_byte(mtd, (unsigned char) ((page_addr >> 16) & 0xff)); + } + /* Latch in address */ + this->hwcontrol(mtd, NAND_CTL_CLRALE); + } + + /* + * program and erase have their own busy handlers + * status and sequential in needs no delay + */ + switch (command) { + + case NAND_CMD_CACHEDPROG: + case NAND_CMD_PAGEPROG: + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + case NAND_CMD_SEQIN: + case NAND_CMD_STATUS: + return; + + + case NAND_CMD_RESET: + if (this->dev_ready) + break; + udelay(this->chip_delay); + this->hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_STATUS); + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + while ( !(this->read_byte(mtd) & 0x40)); + return; + + case NAND_CMD_READ0: + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* Write out the start read command */ + this->write_byte(mtd, NAND_CMD_READSTART); + /* End command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + /* Fall through into ready check */ + + /* This applies to read commands */ + default: + /* + * If we don't have access to the busy pin, we apply the given + * command delay + */ + if (!this->dev_ready) { + udelay (this->chip_delay); + return; + } + } + + /* Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. */ + ndelay (100); + /* wait until command is processed */ + while (!this->dev_ready(mtd)); +} + +/** + * nand_get_device - [GENERIC] Get chip for selected access + * @this: the nand chip descriptor + * @mtd: MTD device structure + * @new_state: the state which is requested + * + * Get the device and lock it for exclusive access + */ +/* XXX U-BOOT XXX */ +#if 0 +static void nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state) +{ + struct nand_chip *active = this; + + DECLARE_WAITQUEUE (wait, current); + + /* + * Grab the lock and see if the device is available + */ +retry: + /* Hardware controller shared among independend devices */ + if (this->controller) { + spin_lock (&this->controller->lock); + if (this->controller->active) + active = this->controller->active; + else + this->controller->active = this; + spin_unlock (&this->controller->lock); + } + + if (active == this) { + spin_lock (&this->chip_lock); + if (this->state == FL_READY) { + this->state = new_state; + spin_unlock (&this->chip_lock); + return; + } + } + set_current_state (TASK_UNINTERRUPTIBLE); + add_wait_queue (&active->wq, &wait); + spin_unlock (&active->chip_lock); + schedule (); + remove_wait_queue (&active->wq, &wait); + goto retry; +} +#else +static void nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state) {} +#endif + +/** + * nand_wait - [DEFAULT] wait until the command is done + * @mtd: MTD device structure + * @this: NAND chip structure + * @state: state to select the max. timeout value + * + * Wait for command done. This applies to erase and program only + * Erase can take up to 400ms and program up to 20ms according to + * general NAND and SmartMedia specs + * +*/ +/* XXX U-BOOT XXX */ +#if 0 +static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + unsigned long timeo = jiffies; + int status; + + if (state == FL_ERASING) + timeo += (HZ * 400) / 1000; + else + timeo += (HZ * 20) / 1000; + + /* Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. */ + ndelay (100); + + if ((state == FL_ERASING) && (this->options & NAND_IS_AND)) + this->cmdfunc (mtd, NAND_CMD_STATUS_MULTI, -1, -1); + else + this->cmdfunc (mtd, NAND_CMD_STATUS, -1, -1); + + while (time_before(jiffies, timeo)) { + /* Check, if we were interrupted */ + if (this->state != state) + return 0; + + if (this->dev_ready) { + if (this->dev_ready(mtd)) + break; + } else { + if (this->read_byte(mtd) & NAND_STATUS_READY) + break; + } + yield (); + } + status = (int) this->read_byte(mtd); + return status; + + return 0; +} +#else +static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + unsigned long timeo; + + if (state == FL_ERASING) + timeo = CFG_HZ * 400; + else + timeo = CFG_HZ * 20; + + if ((state == FL_ERASING) && (this->options & NAND_IS_AND)) + this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); + else + this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); + + reset_timer(); + + while (1) { + if (get_timer(0) > timeo) { + printf("Timeout!"); + return 0; + } + + if (this->dev_ready) { + if (this->dev_ready(mtd)) + break; + } else { + if (this->read_byte(mtd) & NAND_STATUS_READY) + break; + } + } +#ifdef PPCHAMELON_NAND_TIMER_HACK + reset_timer(); + while (get_timer(0) < 10); +#endif /* PPCHAMELON_NAND_TIMER_HACK */ + + return this->read_byte(mtd); +} +#endif + +/** + * nand_write_page - [GENERIC] write one page + * @mtd: MTD device structure + * @this: NAND chip structure + * @page: startpage inside the chip, must be called with (page & this->pagemask) + * @oob_buf: out of band data buffer + * @oobsel: out of band selecttion structre + * @cached: 1 = enable cached programming if supported by chip + * + * Nand_page_program function is used for write and writev ! + * This function will always program a full page of data + * If you call it with a non page aligned buffer, you're lost :) + * + * Cached programming is not supported yet. + */ +static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page, + u_char *oob_buf, struct nand_oobinfo *oobsel, int cached) +{ + int i, status; + u_char ecc_code[32]; + int eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE; + uint *oob_config = oobsel->eccpos; + int datidx = 0, eccidx = 0, eccsteps = this->eccsteps; + int eccbytes = 0; + + /* FIXME: Enable cached programming */ + cached = 0; + + /* Send command to begin auto page programming */ + this->cmdfunc (mtd, NAND_CMD_SEQIN, 0x00, page); + + /* Write out complete page of data, take care of eccmode */ + switch (eccmode) { + /* No ecc, write all */ + case NAND_ECC_NONE: + printk (KERN_WARNING "Writing data without ECC to NAND-FLASH is not recommended\n"); + this->write_buf(mtd, this->data_poi, mtd->oobblock); + break; + + /* Software ecc 3/256, write all */ + case NAND_ECC_SOFT: + for (; eccsteps; eccsteps--) { + this->calculate_ecc(mtd, &this->data_poi[datidx], ecc_code); + for (i = 0; i < 3; i++, eccidx++) + oob_buf[oob_config[eccidx]] = ecc_code[i]; + datidx += this->eccsize; + } + this->write_buf(mtd, this->data_poi, mtd->oobblock); + break; + default: + eccbytes = this->eccbytes; + for (; eccsteps; eccsteps--) { + /* enable hardware ecc logic for write */ + this->enable_hwecc(mtd, NAND_ECC_WRITE); + this->write_buf(mtd, &this->data_poi[datidx], this->eccsize); + this->calculate_ecc(mtd, &this->data_poi[datidx], ecc_code); + for (i = 0; i < eccbytes; i++, eccidx++) + oob_buf[oob_config[eccidx]] = ecc_code[i]; + /* If the hardware ecc provides syndromes then + * the ecc code must be written immidiately after + * the data bytes (words) */ + if (this->options & NAND_HWECC_SYNDROME) + this->write_buf(mtd, ecc_code, eccbytes); + datidx += this->eccsize; + } + break; + } + + /* Write out OOB data */ + if (this->options & NAND_HWECC_SYNDROME) + this->write_buf(mtd, &oob_buf[oobsel->eccbytes], mtd->oobsize - oobsel->eccbytes); + else + this->write_buf(mtd, oob_buf, mtd->oobsize); + + /* Send command to actually program the data */ + this->cmdfunc (mtd, cached ? NAND_CMD_CACHEDPROG : NAND_CMD_PAGEPROG, -1, -1); + + if (!cached) { + /* call wait ready function */ + status = this->waitfunc (mtd, this, FL_WRITING); + /* See if device thinks it succeeded */ + if (status & 0x01) { + DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write, page 0x%08x, ", __FUNCTION__, page); + return -EIO; + } + } else { + /* FIXME: Implement cached programming ! */ + /* wait until cache is ready*/ + /* status = this->waitfunc (mtd, this, FL_CACHEDRPG); */ + } + return 0; +} + +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE +/** + * nand_verify_pages - [GENERIC] verify the chip contents after a write + * @mtd: MTD device structure + * @this: NAND chip structure + * @page: startpage inside the chip, must be called with (page & this->pagemask) + * @numpages: number of pages to verify + * @oob_buf: out of band data buffer + * @oobsel: out of band selecttion structre + * @chipnr: number of the current chip + * @oobmode: 1 = full buffer verify, 0 = ecc only + * + * The NAND device assumes that it is always writing to a cleanly erased page. + * Hence, it performs its internal write verification only on bits that + * transitioned from 1 to 0. The device does NOT verify the whole page on a + * byte by byte basis. It is possible that the page was not completely erased + * or the page is becoming unusable due to wear. The read with ECC would catch + * the error later when the ECC page check fails, but we would rather catch + * it early in the page write stage. Better to write no data than invalid data. + */ +static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int page, int numpages, + u_char *oob_buf, struct nand_oobinfo *oobsel, int chipnr, int oobmode) +{ + int i, j, datidx = 0, oobofs = 0, res = -EIO; + int eccsteps = this->eccsteps; + int hweccbytes; + u_char oobdata[64]; + + hweccbytes = (this->options & NAND_HWECC_SYNDROME) ? (oobsel->eccbytes / eccsteps) : 0; + + /* Send command to read back the first page */ + this->cmdfunc (mtd, NAND_CMD_READ0, 0, page); + + for(;;) { + for (j = 0; j < eccsteps; j++) { + /* Loop through and verify the data */ + if (this->verify_buf(mtd, &this->data_poi[datidx], mtd->eccsize)) { + DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page); + goto out; + } + datidx += mtd->eccsize; + /* Have we a hw generator layout ? */ + if (!hweccbytes) + continue; + if (this->verify_buf(mtd, &this->oob_buf[oobofs], hweccbytes)) { + DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page); + goto out; + } + oobofs += hweccbytes; + } + + /* check, if we must compare all data or if we just have to + * compare the ecc bytes + */ + if (oobmode) { + if (this->verify_buf(mtd, &oob_buf[oobofs], mtd->oobsize - hweccbytes * eccsteps)) { + DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page); + goto out; + } + } else { + /* Read always, else autoincrement fails */ + this->read_buf(mtd, oobdata, mtd->oobsize - hweccbytes * eccsteps); + + if (oobsel->useecc != MTD_NANDECC_OFF && !hweccbytes) { + int ecccnt = oobsel->eccbytes; + + for (i = 0; i < ecccnt; i++) { + int idx = oobsel->eccpos[i]; + if (oobdata[idx] != oob_buf[oobofs + idx] ) { + DEBUG (MTD_DEBUG_LEVEL0, + "%s: Failed ECC write " + "verify, page 0x%08x, " "%6i bytes were succesful\n", __FUNCTION__, page, i); + goto out; + } + } + } + } + oobofs += mtd->oobsize - hweccbytes * eccsteps; + page++; + numpages--; + + /* Apply delay or wait for ready/busy pin + * Do this before the AUTOINCR check, so no problems + * arise if a chip which does auto increment + * is marked as NOAUTOINCR by the board driver. + * Do this also before returning, so the chip is + * ready for the next command. + */ + if (!this->dev_ready) + udelay (this->chip_delay); + else + while (!this->dev_ready(mtd)); + + /* All done, return happy */ + if (!numpages) + return 0; + + + /* Check, if the chip supports auto page increment */ + if (!NAND_CANAUTOINCR(this)) + this->cmdfunc (mtd, NAND_CMD_READ0, 0x00, page); + } + /* + * Terminate the read command. We come here in case of an error + * So we must issue a reset command. + */ +out: + this->cmdfunc (mtd, NAND_CMD_RESET, -1, -1); + return res; +} +#endif + +/** + * nand_read - [MTD Interface] MTD compability function for nand_read_ecc + * @mtd: MTD device structure + * @from: offset to read from + * @len: number of bytes to read + * @retlen: pointer to variable to store the number of read bytes + * @buf: the databuffer to put data + * + * This function simply calls nand_read_ecc with oob buffer and oobsel = NULL +*/ +static int nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf) +{ + return nand_read_ecc (mtd, from, len, retlen, buf, NULL, NULL); +} + + +/** + * nand_read_ecc - [MTD Interface] Read data with ECC + * @mtd: MTD device structure + * @from: offset to read from + * @len: number of bytes to read + * @retlen: pointer to variable to store the number of read bytes + * @buf: the databuffer to put data + * @oob_buf: filesystem supplied oob data buffer + * @oobsel: oob selection structure + * + * NAND read with ECC + */ +static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, + size_t * retlen, u_char * buf, u_char * oob_buf, struct nand_oobinfo *oobsel) +{ + int i, j, col, realpage, page, end, ecc, chipnr, sndcmd = 1; + int read = 0, oob = 0, ecc_status = 0, ecc_failed = 0; + struct nand_chip *this = mtd->priv; + u_char *data_poi, *oob_data = oob_buf; + u_char ecc_calc[32]; + u_char ecc_code[32]; + int eccmode, eccsteps; + unsigned *oob_config; + int datidx; + int blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1; + int eccbytes; + int compareecc = 1; + int oobreadlen; + + + DEBUG (MTD_DEBUG_LEVEL3, "nand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); + + /* Do not allow reads past end of device */ + if ((from + len) > mtd->size) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: Attempt read beyond end of device\n"); + *retlen = 0; + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd ,FL_READING); + + /* use userspace supplied oobinfo, if zero */ + if (oobsel == NULL) + oobsel = &mtd->oobinfo; + + /* Autoplace of oob data ? Use the default placement scheme */ + if (oobsel->useecc == MTD_NANDECC_AUTOPLACE) + oobsel = this->autooob; + + eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE; + oob_config = oobsel->eccpos; + + /* Select the NAND device */ + chipnr = (int)(from >> this->chip_shift); + this->select_chip(mtd, chipnr); + + /* First we calculate the starting page */ + realpage = (int) (from >> this->page_shift); + page = realpage & this->pagemask; + + /* Get raw starting column */ + col = from & (mtd->oobblock - 1); + + end = mtd->oobblock; + ecc = this->eccsize; + eccbytes = this->eccbytes; + + if ((eccmode == NAND_ECC_NONE) || (this->options & NAND_HWECC_SYNDROME)) + compareecc = 0; + + oobreadlen = mtd->oobsize; + if (this->options & NAND_HWECC_SYNDROME) + oobreadlen -= oobsel->eccbytes; + + /* Loop until all data read */ + while (read < len) { + + int aligned = (!col && (len - read) >= end); + /* + * If the read is not page aligned, we have to read into data buffer + * due to ecc, else we read into return buffer direct + */ + if (aligned) + data_poi = &buf[read]; + else + data_poi = this->data_buf; + + /* Check, if we have this page in the buffer + * + * FIXME: Make it work when we must provide oob data too, + * check the usage of data_buf oob field + */ + if (realpage == this->pagebuf && !oob_buf) { + /* aligned read ? */ + if (aligned) + memcpy (data_poi, this->data_buf, end); + goto readdata; + } + + /* Check, if we must send the read command */ + if (sndcmd) { + this->cmdfunc (mtd, NAND_CMD_READ0, 0x00, page); + sndcmd = 0; + } + + /* get oob area, if we have no oob buffer from fs-driver */ + if (!oob_buf || oobsel->useecc == MTD_NANDECC_AUTOPLACE || + oobsel->useecc == MTD_NANDECC_AUTOPL_USR) + oob_data = &this->data_buf[end]; + + eccsteps = this->eccsteps; + + switch (eccmode) { + case NAND_ECC_NONE: { /* No ECC, Read in a page */ +/* XXX U-BOOT XXX */ +#if 0 + static unsigned long lastwhinge = 0; + if ((lastwhinge / HZ) != (jiffies / HZ)) { + printk (KERN_WARNING "Reading data from NAND FLASH without ECC is not recommended\n"); + lastwhinge = jiffies; + } +#else + puts("Reading data from NAND FLASH without ECC is not recommended\n"); +#endif + this->read_buf(mtd, data_poi, end); + break; + } + + case NAND_ECC_SOFT: /* Software ECC 3/256: Read in a page + oob data */ + this->read_buf(mtd, data_poi, end); + for (i = 0, datidx = 0; eccsteps; eccsteps--, i+=3, datidx += ecc) + this->calculate_ecc(mtd, &data_poi[datidx], &ecc_calc[i]); + break; + + default: + for (i = 0, datidx = 0; eccsteps; eccsteps--, i+=eccbytes, datidx += ecc) { + this->enable_hwecc(mtd, NAND_ECC_READ); + this->read_buf(mtd, &data_poi[datidx], ecc); + + /* HW ecc with syndrome calculation must read the + * syndrome from flash immidiately after the data */ + if (!compareecc) { + /* Some hw ecc generators need to know when the + * syndrome is read from flash */ + this->enable_hwecc(mtd, NAND_ECC_READSYN); + this->read_buf(mtd, &oob_data[i], eccbytes); + /* We calc error correction directly, it checks the hw + * generator for an error, reads back the syndrome and + * does the error correction on the fly */ + if (this->correct_data(mtd, &data_poi[datidx], &oob_data[i], &ecc_code[i]) == -1) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " + "Failed ECC read, page 0x%08x on chip %d\n", page, chipnr); + ecc_failed++; + } + } else { + this->calculate_ecc(mtd, &data_poi[datidx], &ecc_calc[i]); + } + } + break; + } + + /* read oobdata */ + this->read_buf(mtd, &oob_data[mtd->oobsize - oobreadlen], oobreadlen); + + /* Skip ECC check, if not requested (ECC_NONE or HW_ECC with syndromes) */ + if (!compareecc) + goto readoob; + + /* Pick the ECC bytes out of the oob data */ + for (j = 0; j < oobsel->eccbytes; j++) + ecc_code[j] = oob_data[oob_config[j]]; + + /* correct data, if neccecary */ + for (i = 0, j = 0, datidx = 0; i < this->eccsteps; i++, datidx += ecc) { + ecc_status = this->correct_data(mtd, &data_poi[datidx], &ecc_code[j], &ecc_calc[j]); + + /* Get next chunk of ecc bytes */ + j += eccbytes; + + /* Check, if we have a fs supplied oob-buffer, + * This is the legacy mode. Used by YAFFS1 + * Should go away some day + */ + if (oob_buf && oobsel->useecc == MTD_NANDECC_PLACE) { + int *p = (int *)(&oob_data[mtd->oobsize]); + p[i] = ecc_status; + } + + if (ecc_status == -1) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " "Failed ECC read, page 0x%08x\n", page); + ecc_failed++; + } + } + + readoob: + /* check, if we have a fs supplied oob-buffer */ + if (oob_buf) { + /* without autoplace. Legacy mode used by YAFFS1 */ + switch(oobsel->useecc) { + case MTD_NANDECC_AUTOPLACE: + case MTD_NANDECC_AUTOPL_USR: + /* Walk through the autoplace chunks */ + for (i = 0, j = 0; j < mtd->oobavail; i++) { + int from = oobsel->oobfree[i][0]; + int num = oobsel->oobfree[i][1]; + memcpy(&oob_buf[oob], &oob_data[from], num); + j+= num; + } + oob += mtd->oobavail; + break; + case MTD_NANDECC_PLACE: + /* YAFFS1 legacy mode */ + oob_data += this->eccsteps * sizeof (int); + default: + oob_data += mtd->oobsize; + } + } + readdata: + /* Partial page read, transfer data into fs buffer */ + if (!aligned) { + for (j = col; j < end && read < len; j++) + buf[read++] = data_poi[j]; + this->pagebuf = realpage; + } else + read += mtd->oobblock; + + /* Apply delay or wait for ready/busy pin + * Do this before the AUTOINCR check, so no problems + * arise if a chip which does auto increment + * is marked as NOAUTOINCR by the board driver. + */ + if (!this->dev_ready) + udelay (this->chip_delay); + else + while (!this->dev_ready(mtd)); + + if (read == len) + break; + + /* For subsequent reads align to page boundary. */ + col = 0; + /* Increment page address */ + realpage++; + + page = realpage & this->pagemask; + /* Check, if we cross a chip boundary */ + if (!page) { + chipnr++; + this->select_chip(mtd, -1); + this->select_chip(mtd, chipnr); + } + /* Check, if the chip supports auto page increment + * or if we have hit a block boundary. + */ + if (!NAND_CANAUTOINCR(this) || !(page & blockcheck)) + sndcmd = 1; + } + + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + + /* + * Return success, if no ECC failures, else -EBADMSG + * fs driver will take care of that, because + * retlen == desired len and result == -EBADMSG + */ + *retlen = read; + return ecc_failed ? -EBADMSG : 0; +} + +/** + * nand_read_oob - [MTD Interface] NAND read out-of-band + * @mtd: MTD device structure + * @from: offset to read from + * @len: number of bytes to read + * @retlen: pointer to variable to store the number of read bytes + * @buf: the databuffer to put data + * + * NAND read out-of-band data from the spare area + */ +static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf) +{ + int i, col, page, chipnr; + struct nand_chip *this = mtd->priv; + int blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1; + + DEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); + + /* Shift to get page */ + page = (int)(from >> this->page_shift); + chipnr = (int)(from >> this->chip_shift); + + /* Mask to get column */ + col = from & (mtd->oobsize - 1); + + /* Initialize return length value */ + *retlen = 0; + + /* Do not allow reads past end of device */ + if ((from + len) > mtd->size) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: Attempt read beyond end of device\n"); + *retlen = 0; + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd , FL_READING); + + /* Select the NAND device */ + this->select_chip(mtd, chipnr); + + /* Send the read command */ + this->cmdfunc (mtd, NAND_CMD_READOOB, col, page & this->pagemask); + /* + * Read the data, if we read more than one page + * oob data, let the device transfer the data ! + */ + i = 0; + while (i < len) { + int thislen = mtd->oobsize - col; + thislen = min_t(int, thislen, len); + this->read_buf(mtd, &buf[i], thislen); + i += thislen; + + /* Apply delay or wait for ready/busy pin + * Do this before the AUTOINCR check, so no problems + * arise if a chip which does auto increment + * is marked as NOAUTOINCR by the board driver. + */ + if (!this->dev_ready) + udelay (this->chip_delay); + else + while (!this->dev_ready(mtd)); + + /* Read more ? */ + if (i < len) { + page++; + col = 0; + + /* Check, if we cross a chip boundary */ + if (!(page & this->pagemask)) { + chipnr++; + this->select_chip(mtd, -1); + this->select_chip(mtd, chipnr); + } + + /* Check, if the chip supports auto page increment + * or if we have hit a block boundary. + */ + if (!NAND_CANAUTOINCR(this) || !(page & blockcheck)) { + /* For subsequent page reads set offset to 0 */ + this->cmdfunc (mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask); + } + } + } + + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + + /* Return happy */ + *retlen = len; + return 0; +} + +/** + * nand_read_raw - [GENERIC] Read raw data including oob into buffer + * @mtd: MTD device structure + * @buf: temporary buffer + * @from: offset to read from + * @len: number of bytes to read + * @ooblen: number of oob data bytes to read + * + * Read raw data including oob into buffer + */ +int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen) +{ + struct nand_chip *this = mtd->priv; + int page = (int) (from >> this->page_shift); + int chip = (int) (from >> this->chip_shift); + int sndcmd = 1; + int cnt = 0; + int pagesize = mtd->oobblock + mtd->oobsize; + int blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1; + + /* Do not allow reads past end of device */ + if ((from + len) > mtd->size) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_read_raw: Attempt read beyond end of device\n"); + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd , FL_READING); + + this->select_chip (mtd, chip); + + /* Add requested oob length */ + len += ooblen; + + while (len) { + if (sndcmd) + this->cmdfunc (mtd, NAND_CMD_READ0, 0, page & this->pagemask); + sndcmd = 0; + + this->read_buf (mtd, &buf[cnt], pagesize); + + len -= pagesize; + cnt += pagesize; + page++; + + if (!this->dev_ready) + udelay (this->chip_delay); + else + while (!this->dev_ready(mtd)); + + /* Check, if the chip supports auto page increment */ + if (!NAND_CANAUTOINCR(this) || !(page & blockcheck)) + sndcmd = 1; + } + + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + return 0; +} + + +/** + * nand_prepare_oobbuf - [GENERIC] Prepare the out of band buffer + * @mtd: MTD device structure + * @fsbuf: buffer given by fs driver + * @oobsel: out of band selection structre + * @autoplace: 1 = place given buffer into the oob bytes + * @numpages: number of pages to prepare + * + * Return: + * 1. Filesystem buffer available and autoplacement is off, + * return filesystem buffer + * 2. No filesystem buffer or autoplace is off, return internal + * buffer + * 3. Filesystem buffer is given and autoplace selected + * put data from fs buffer into internal buffer and + * retrun internal buffer + * + * Note: The internal buffer is filled with 0xff. This must + * be done only once, when no autoplacement happens + * Autoplacement sets the buffer dirty flag, which + * forces the 0xff fill before using the buffer again. + * +*/ +static u_char * nand_prepare_oobbuf (struct mtd_info *mtd, u_char *fsbuf, struct nand_oobinfo *oobsel, + int autoplace, int numpages) +{ + struct nand_chip *this = mtd->priv; + int i, len, ofs; + + /* Zero copy fs supplied buffer */ + if (fsbuf && !autoplace) + return fsbuf; + + /* Check, if the buffer must be filled with ff again */ + if (this->oobdirty) { + memset (this->oob_buf, 0xff, + mtd->oobsize << (this->phys_erase_shift - this->page_shift)); + this->oobdirty = 0; + } + + /* If we have no autoplacement or no fs buffer use the internal one */ + if (!autoplace || !fsbuf) + return this->oob_buf; + + /* Walk through the pages and place the data */ + this->oobdirty = 1; + ofs = 0; + while (numpages--) { + for (i = 0, len = 0; len < mtd->oobavail; i++) { + int to = ofs + oobsel->oobfree[i][0]; + int num = oobsel->oobfree[i][1]; + memcpy (&this->oob_buf[to], fsbuf, num); + len += num; + fsbuf += num; + } + ofs += mtd->oobavail; + } + return this->oob_buf; +} + +#define NOTALIGNED(x) (x & (mtd->oobblock-1)) != 0 + +/** + * nand_write - [MTD Interface] compability function for nand_write_ecc + * @mtd: MTD device structure + * @to: offset to write to + * @len: number of bytes to write + * @retlen: pointer to variable to store the number of written bytes + * @buf: the data to write + * + * This function simply calls nand_write_ecc with oob buffer and oobsel = NULL + * +*/ +static int nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf) +{ + return (nand_write_ecc (mtd, to, len, retlen, buf, NULL, NULL)); +} + +/** + * nand_write_ecc - [MTD Interface] NAND write with ECC + * @mtd: MTD device structure + * @to: offset to write to + * @len: number of bytes to write + * @retlen: pointer to variable to store the number of written bytes + * @buf: the data to write + * @eccbuf: filesystem supplied oob data buffer + * @oobsel: oob selection structure + * + * NAND write with ECC + */ +static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len, + size_t * retlen, const u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel) +{ + int startpage, page, ret = -EIO, oob = 0, written = 0, chipnr; + int autoplace = 0, numpages, totalpages; + struct nand_chip *this = mtd->priv; + u_char *oobbuf, *bufstart; + int ppblock = (1 << (this->phys_erase_shift - this->page_shift)); + + DEBUG (MTD_DEBUG_LEVEL3, "nand_write_ecc: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); + + /* Initialize retlen, in case of early exit */ + *retlen = 0; + + /* Do not allow write past end of device */ + if ((to + len) > mtd->size) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: Attempt to write past end of page\n"); + return -EINVAL; + } + + /* reject writes, which are not page aligned */ + if (NOTALIGNED (to) || NOTALIGNED(len)) { + printk (KERN_NOTICE "nand_write_ecc: Attempt to write not page aligned data\n"); + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd, FL_WRITING); + + /* Calculate chipnr */ + chipnr = (int)(to >> this->chip_shift); + /* Select the NAND device */ + this->select_chip(mtd, chipnr); + + /* Check, if it is write protected */ + if (nand_check_wp(mtd)) + goto out; + + /* if oobsel is NULL, use chip defaults */ + if (oobsel == NULL) + oobsel = &mtd->oobinfo; + + /* Autoplace of oob data ? Use the default placement scheme */ + if (oobsel->useecc == MTD_NANDECC_AUTOPLACE) { + oobsel = this->autooob; + autoplace = 1; + } + if (oobsel->useecc == MTD_NANDECC_AUTOPL_USR) + autoplace = 1; + + /* Setup variables and oob buffer */ + totalpages = len >> this->page_shift; + page = (int) (to >> this->page_shift); + /* Invalidate the page cache, if we write to the cached page */ + if (page <= this->pagebuf && this->pagebuf < (page + totalpages)) + this->pagebuf = -1; + + /* Set it relative to chip */ + page &= this->pagemask; + startpage = page; + /* Calc number of pages we can write in one go */ + numpages = min (ppblock - (startpage & (ppblock - 1)), totalpages); + oobbuf = nand_prepare_oobbuf (mtd, eccbuf, oobsel, autoplace, numpages); + bufstart = (u_char *)buf; + + /* Loop until all data is written */ + while (written < len) { + + this->data_poi = (u_char*) &buf[written]; + /* Write one page. If this is the last page to write + * or the last page in this block, then use the + * real pageprogram command, else select cached programming + * if supported by the chip. + */ + ret = nand_write_page (mtd, this, page, &oobbuf[oob], oobsel, (--numpages > 0)); + if (ret) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: write_page failed %d\n", ret); + goto out; + } + /* Next oob page */ + oob += mtd->oobsize; + /* Update written bytes count */ + written += mtd->oobblock; + if (written == len) + goto cmp; + + /* Increment page address */ + page++; + + /* Have we hit a block boundary ? Then we have to verify and + * if verify is ok, we have to setup the oob buffer for + * the next pages. + */ + if (!(page & (ppblock - 1))){ + int ofs; + this->data_poi = bufstart; + ret = nand_verify_pages (mtd, this, startpage, + page - startpage, + oobbuf, oobsel, chipnr, (eccbuf != NULL)); + if (ret) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: verify_pages failed %d\n", ret); + goto out; + } + *retlen = written; + + ofs = autoplace ? mtd->oobavail : mtd->oobsize; + if (eccbuf) + eccbuf += (page - startpage) * ofs; + totalpages -= page - startpage; + numpages = min (totalpages, ppblock); + page &= this->pagemask; + startpage = page; + oob = 0; + this->oobdirty = 1; + oobbuf = nand_prepare_oobbuf (mtd, eccbuf, oobsel, + autoplace, numpages); + /* Check, if we cross a chip boundary */ + if (!page) { + chipnr++; + this->select_chip(mtd, -1); + this->select_chip(mtd, chipnr); + } + } + } + /* Verify the remaining pages */ +cmp: + this->data_poi = bufstart; + ret = nand_verify_pages (mtd, this, startpage, totalpages, + oobbuf, oobsel, chipnr, (eccbuf != NULL)); + if (!ret) + *retlen = written; + else + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: verify_pages failed %d\n", ret); + +out: + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + + return ret; +} + + +/** + * nand_write_oob - [MTD Interface] NAND write out-of-band + * @mtd: MTD device structure + * @to: offset to write to + * @len: number of bytes to write + * @retlen: pointer to variable to store the number of written bytes + * @buf: the data to write + * + * NAND write out-of-band + */ +static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf) +{ + int column, page, status, ret = -EIO, chipnr; + struct nand_chip *this = mtd->priv; + + DEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); + + /* Shift to get page */ + page = (int) (to >> this->page_shift); + chipnr = (int) (to >> this->chip_shift); + + /* Mask to get column */ + column = to & (mtd->oobsize - 1); + + /* Initialize return length value */ + *retlen = 0; + + /* Do not allow write past end of page */ + if ((column + len) > mtd->oobsize) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: Attempt to write past end of page\n"); + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd, FL_WRITING); + + /* Select the NAND device */ + this->select_chip(mtd, chipnr); + + /* Reset the chip. Some chips (like the Toshiba TC5832DC found + in one of my DiskOnChip 2000 test units) will clear the whole + data page too if we don't do this. I have no clue why, but + I seem to have 'fixed' it in the doc2000 driver in + August 1999. dwmw2. */ + this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + + /* Check, if it is write protected */ + if (nand_check_wp(mtd)) + goto out; + + /* Invalidate the page cache, if we write to the cached page */ + if (page == this->pagebuf) + this->pagebuf = -1; + + if (NAND_MUST_PAD(this)) { + /* Write out desired data */ + this->cmdfunc (mtd, NAND_CMD_SEQIN, mtd->oobblock, page & this->pagemask); + /* prepad 0xff for partial programming */ + this->write_buf(mtd, ffchars, column); + /* write data */ + this->write_buf(mtd, buf, len); + /* postpad 0xff for partial programming */ + this->write_buf(mtd, ffchars, mtd->oobsize - (len+column)); + } else { + /* Write out desired data */ + this->cmdfunc (mtd, NAND_CMD_SEQIN, mtd->oobblock + column, page & this->pagemask); + /* write data */ + this->write_buf(mtd, buf, len); + } + /* Send command to program the OOB data */ + this->cmdfunc (mtd, NAND_CMD_PAGEPROG, -1, -1); + + status = this->waitfunc (mtd, this, FL_WRITING); + + /* See if device thinks it succeeded */ + if (status & 0x01) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write, page 0x%08x\n", page); + ret = -EIO; + goto out; + } + /* Return happy */ + *retlen = len; + +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE + /* Send command to read back the data */ + this->cmdfunc (mtd, NAND_CMD_READOOB, column, page & this->pagemask); + + if (this->verify_buf(mtd, buf, len)) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write verify, page 0x%08x\n", page); + ret = -EIO; + goto out; + } +#endif + ret = 0; +out: + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + + return ret; +} + +/* XXX U-BOOT XXX */ +#if 0 +/** + * nand_writev - [MTD Interface] compabilty function for nand_writev_ecc + * @mtd: MTD device structure + * @vecs: the iovectors to write + * @count: number of vectors + * @to: offset to write to + * @retlen: pointer to variable to store the number of written bytes + * + * NAND write with kvec. This just calls the ecc function + */ +static int nand_writev (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, + loff_t to, size_t * retlen) +{ + return (nand_writev_ecc (mtd, vecs, count, to, retlen, NULL, NULL)); +} + +/** + * nand_writev_ecc - [MTD Interface] write with iovec with ecc + * @mtd: MTD device structure + * @vecs: the iovectors to write + * @count: number of vectors + * @to: offset to write to + * @retlen: pointer to variable to store the number of written bytes + * @eccbuf: filesystem supplied oob data buffer + * @oobsel: oob selection structure + * + * NAND write with iovec with ecc + */ +static int nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, + loff_t to, size_t * retlen, u_char *eccbuf, struct nand_oobinfo *oobsel) +{ + int i, page, len, total_len, ret = -EIO, written = 0, chipnr; + int oob, numpages, autoplace = 0, startpage; + struct nand_chip *this = mtd->priv; + int ppblock = (1 << (this->phys_erase_shift - this->page_shift)); + u_char *oobbuf, *bufstart; + + /* Preset written len for early exit */ + *retlen = 0; + + /* Calculate total length of data */ + total_len = 0; + for (i = 0; i < count; i++) + total_len += (int) vecs[i].iov_len; + + DEBUG (MTD_DEBUG_LEVEL3, + "nand_writev: to = 0x%08x, len = %i, count = %ld\n", (unsigned int) to, (unsigned int) total_len, count); + + /* Do not allow write past end of page */ + if ((to + total_len) > mtd->size) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_writev: Attempted write past end of device\n"); + return -EINVAL; + } + + /* reject writes, which are not page aligned */ + if (NOTALIGNED (to) || NOTALIGNED(total_len)) { + printk (KERN_NOTICE "nand_write_ecc: Attempt to write not page aligned data\n"); + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd, FL_WRITING); + + /* Get the current chip-nr */ + chipnr = (int) (to >> this->chip_shift); + /* Select the NAND device */ + this->select_chip(mtd, chipnr); + + /* Check, if it is write protected */ + if (nand_check_wp(mtd)) + goto out; + + /* if oobsel is NULL, use chip defaults */ + if (oobsel == NULL) + oobsel = &mtd->oobinfo; + + /* Autoplace of oob data ? Use the default placement scheme */ + if (oobsel->useecc == MTD_NANDECC_AUTOPLACE) { + oobsel = this->autooob; + autoplace = 1; + } + if (oobsel->useecc == MTD_NANDECC_AUTOPL_USR) + autoplace = 1; + + /* Setup start page */ + page = (int) (to >> this->page_shift); + /* Invalidate the page cache, if we write to the cached page */ + if (page <= this->pagebuf && this->pagebuf < ((to + total_len) >> this->page_shift)) + this->pagebuf = -1; + + startpage = page & this->pagemask; + + /* Loop until all kvec' data has been written */ + len = 0; + while (count) { + /* If the given tuple is >= pagesize then + * write it out from the iov + */ + if ((vecs->iov_len - len) >= mtd->oobblock) { + /* Calc number of pages we can write + * out of this iov in one go */ + numpages = (vecs->iov_len - len) >> this->page_shift; + /* Do not cross block boundaries */ + numpages = min (ppblock - (startpage & (ppblock - 1)), numpages); + oobbuf = nand_prepare_oobbuf (mtd, NULL, oobsel, autoplace, numpages); + bufstart = (u_char *)vecs->iov_base; + bufstart += len; + this->data_poi = bufstart; + oob = 0; + for (i = 1; i <= numpages; i++) { + /* Write one page. If this is the last page to write + * then use the real pageprogram command, else select + * cached programming if supported by the chip. + */ + ret = nand_write_page (mtd, this, page & this->pagemask, + &oobbuf[oob], oobsel, i != numpages); + if (ret) + goto out; + this->data_poi += mtd->oobblock; + len += mtd->oobblock; + oob += mtd->oobsize; + page++; + } + /* Check, if we have to switch to the next tuple */ + if (len >= (int) vecs->iov_len) { + vecs++; + len = 0; + count--; + } + } else { + /* We must use the internal buffer, read data out of each + * tuple until we have a full page to write + */ + int cnt = 0; + while (cnt < mtd->oobblock) { + if (vecs->iov_base != NULL && vecs->iov_len) + this->data_buf[cnt++] = ((u_char *) vecs->iov_base)[len++]; + /* Check, if we have to switch to the next tuple */ + if (len >= (int) vecs->iov_len) { + vecs++; + len = 0; + count--; + } + } + this->pagebuf = page; + this->data_poi = this->data_buf; + bufstart = this->data_poi; + numpages = 1; + oobbuf = nand_prepare_oobbuf (mtd, NULL, oobsel, autoplace, numpages); + ret = nand_write_page (mtd, this, page & this->pagemask, + oobbuf, oobsel, 0); + if (ret) + goto out; + page++; + } + + this->data_poi = bufstart; + ret = nand_verify_pages (mtd, this, startpage, numpages, oobbuf, oobsel, chipnr, 0); + if (ret) + goto out; + + written += mtd->oobblock * numpages; + /* All done ? */ + if (!count) + break; + + startpage = page & this->pagemask; + /* Check, if we cross a chip boundary */ + if (!startpage) { + chipnr++; + this->select_chip(mtd, -1); + this->select_chip(mtd, chipnr); + } + } + ret = 0; +out: + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + + *retlen = written; + return ret; +} +#endif + +/** + * single_erease_cmd - [GENERIC] NAND standard block erase command function + * @mtd: MTD device structure + * @page: the page address of the block which will be erased + * + * Standard erase command for NAND chips + */ +static void single_erase_cmd (struct mtd_info *mtd, int page) +{ + struct nand_chip *this = mtd->priv; + /* Send commands to erase a block */ + this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page); + this->cmdfunc (mtd, NAND_CMD_ERASE2, -1, -1); +} + +/** + * multi_erease_cmd - [GENERIC] AND specific block erase command function + * @mtd: MTD device structure + * @page: the page address of the block which will be erased + * + * AND multi block erase command function + * Erase 4 consecutive blocks + */ +static void multi_erase_cmd (struct mtd_info *mtd, int page) +{ + struct nand_chip *this = mtd->priv; + /* Send commands to erase a block */ + this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page++); + this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page++); + this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page++); + this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page); + this->cmdfunc (mtd, NAND_CMD_ERASE2, -1, -1); +} + +/** + * nand_erase - [MTD Interface] erase block(s) + * @mtd: MTD device structure + * @instr: erase instruction + * + * Erase one ore more blocks + */ +static int nand_erase (struct mtd_info *mtd, struct erase_info *instr) +{ + return nand_erase_nand (mtd, instr, 0); +} + +/** + * nand_erase_intern - [NAND Interface] erase block(s) + * @mtd: MTD device structure + * @instr: erase instruction + * @allowbbt: allow erasing the bbt area + * + * Erase one ore more blocks + */ +int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt) +{ + int page, len, status, pages_per_block, ret, chipnr; + struct nand_chip *this = mtd->priv; + + DEBUG (MTD_DEBUG_LEVEL3, + "nand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len); + + /* Start address must align on block boundary */ + if (instr->addr & ((1 << this->phys_erase_shift) - 1)) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n"); + return -EINVAL; + } + + /* Length must align on block boundary */ + if (instr->len & ((1 << this->phys_erase_shift) - 1)) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Length not block aligned\n"); + return -EINVAL; + } + + /* Do not allow erase past end of device */ + if ((instr->len + instr->addr) > mtd->size) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Erase past end of device\n"); + return -EINVAL; + } + + instr->fail_addr = 0xffffffff; + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd, FL_ERASING); + + /* Shift to get first page */ + page = (int) (instr->addr >> this->page_shift); + chipnr = (int) (instr->addr >> this->chip_shift); + + /* Calculate pages in each block */ + pages_per_block = 1 << (this->phys_erase_shift - this->page_shift); + + /* Select the NAND device */ + this->select_chip(mtd, chipnr); + + /* Check the WP bit */ + /* Check, if it is write protected */ + if (nand_check_wp(mtd)) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Device is write protected!!!\n"); + instr->state = MTD_ERASE_FAILED; + goto erase_exit; + } + + /* Loop through the pages */ + len = instr->len; + + instr->state = MTD_ERASING; + + while (len) { +#ifndef NAND_ALLOW_ERASE_ALL + /* Check if we have a bad block, we do not erase bad blocks ! */ + if (nand_block_checkbad(mtd, ((loff_t) page) << this->page_shift, 0, allowbbt)) { + printk (KERN_WARNING "nand_erase: attempt to erase a bad block at page 0x%08x\n", page); + instr->state = MTD_ERASE_FAILED; + goto erase_exit; + } +#endif + /* Invalidate the page cache, if we erase the block which contains + the current cached page */ + if (page <= this->pagebuf && this->pagebuf < (page + pages_per_block)) + this->pagebuf = -1; + + this->erase_cmd (mtd, page & this->pagemask); + + status = this->waitfunc (mtd, this, FL_ERASING); + + /* See if block erase succeeded */ + if (status & 0x01) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: " "Failed erase, page 0x%08x\n", page); + instr->state = MTD_ERASE_FAILED; + instr->fail_addr = (page << this->page_shift); + goto erase_exit; + } + + /* Increment page address and decrement length */ + len -= (1 << this->phys_erase_shift); + page += pages_per_block; + + /* Check, if we cross a chip boundary */ + if (len && !(page & this->pagemask)) { + chipnr++; + this->select_chip(mtd, -1); + this->select_chip(mtd, chipnr); + } + } + instr->state = MTD_ERASE_DONE; + +erase_exit: + + ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; + /* Do call back function */ + if (!ret) + mtd_erase_callback(instr); + + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + + /* Return more or less happy */ + return ret; +} + +/** + * nand_sync - [MTD Interface] sync + * @mtd: MTD device structure + * + * Sync is actually a wait for chip ready function + */ +static void nand_sync (struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + + DEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n"); + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd, FL_SYNCING); + /* Release it and go back */ + nand_release_device (mtd); +} + + +/** + * nand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad + * @mtd: MTD device structure + * @ofs: offset relative to mtd start + */ +static int nand_block_isbad (struct mtd_info *mtd, loff_t ofs) +{ + /* Check for invalid offset */ + if (ofs > mtd->size) + return -EINVAL; + + return nand_block_checkbad (mtd, ofs, 1, 0); +} + +/** + * nand_block_markbad - [MTD Interface] Mark the block at the given offset as bad + * @mtd: MTD device structure + * @ofs: offset relative to mtd start + */ +static int nand_block_markbad (struct mtd_info *mtd, loff_t ofs) +{ + struct nand_chip *this = mtd->priv; + int ret; + + if ((ret = nand_block_isbad(mtd, ofs))) { + /* If it was bad already, return success and do nothing. */ + if (ret > 0) + return 0; + return ret; + } + + return this->block_markbad(mtd, ofs); +} + +/** + * nand_scan - [NAND Interface] Scan for the NAND device + * @mtd: MTD device structure + * @maxchips: Number of chips to scan for + * + * This fills out all the not initialized function pointers + * with the defaults. + * The flash ID is read and the mtd/chip structures are + * filled with the appropriate values. Buffers are allocated if + * they are not provided by the board driver + * + */ +int nand_scan (struct mtd_info *mtd, int maxchips) +{ + int i, j, nand_maf_id, nand_dev_id, busw; + struct nand_chip *this = mtd->priv; + + /* Get buswidth to select the correct functions*/ + busw = this->options & NAND_BUSWIDTH_16; + + /* check for proper chip_delay setup, set 20us if not */ + if (!this->chip_delay) + this->chip_delay = 20; + + /* check, if a user supplied command function given */ + if (this->cmdfunc == NULL) + this->cmdfunc = nand_command; + + /* check, if a user supplied wait function given */ + if (this->waitfunc == NULL) + this->waitfunc = nand_wait; + + if (!this->select_chip) + this->select_chip = nand_select_chip; + if (!this->write_byte) + this->write_byte = busw ? nand_write_byte16 : nand_write_byte; + if (!this->read_byte) + this->read_byte = busw ? nand_read_byte16 : nand_read_byte; + if (!this->write_word) + this->write_word = nand_write_word; + if (!this->read_word) + this->read_word = nand_read_word; + if (!this->block_bad) + this->block_bad = nand_block_bad; + if (!this->block_markbad) + this->block_markbad = nand_default_block_markbad; + if (!this->write_buf) + this->write_buf = busw ? nand_write_buf16 : nand_write_buf; + if (!this->read_buf) + this->read_buf = busw ? nand_read_buf16 : nand_read_buf; + if (!this->verify_buf) + this->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; + if (!this->scan_bbt) + this->scan_bbt = nand_default_bbt; + + /* Select the device */ + this->select_chip(mtd, 0); + + /* Send the command for reading device ID */ + this->cmdfunc (mtd, NAND_CMD_READID, 0x00, -1); + + /* Read manufacturer and device IDs */ + nand_maf_id = this->read_byte(mtd); + nand_dev_id = this->read_byte(mtd); + + /* Print and store flash device information */ + for (i = 0; nand_flash_ids[i].name != NULL; i++) { + + if (nand_dev_id != nand_flash_ids[i].id) + continue; + + if (!mtd->name) mtd->name = nand_flash_ids[i].name; + this->chipsize = nand_flash_ids[i].chipsize << 20; + + /* New devices have all the information in additional id bytes */ + if (!nand_flash_ids[i].pagesize) { + int extid; + /* The 3rd id byte contains non relevant data ATM */ + extid = this->read_byte(mtd); + /* The 4th id byte is the important one */ + extid = this->read_byte(mtd); + /* Calc pagesize */ + mtd->oobblock = 1024 << (extid & 0x3); + extid >>= 2; + /* Calc oobsize */ + mtd->oobsize = (8 << (extid & 0x03)) * (mtd->oobblock / 512); + extid >>= 2; + /* Calc blocksize. Blocksize is multiples of 64KiB */ + mtd->erasesize = (64 * 1024) << (extid & 0x03); + extid >>= 2; + /* Get buswidth information */ + busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; + + } else { + /* Old devices have this data hardcoded in the + * device id table */ + mtd->erasesize = nand_flash_ids[i].erasesize; + mtd->oobblock = nand_flash_ids[i].pagesize; + mtd->oobsize = mtd->oobblock / 32; + busw = nand_flash_ids[i].options & NAND_BUSWIDTH_16; + } + + /* Check, if buswidth is correct. Hardware drivers should set + * this correct ! */ + if (busw != (this->options & NAND_BUSWIDTH_16)) { + printk (KERN_INFO "NAND device: Manufacturer ID:" + " 0x%02x, Chip ID: 0x%02x (%s %s)\n", nand_maf_id, nand_dev_id, + nand_manuf_ids[i].name , mtd->name); + printk (KERN_WARNING + "NAND bus width %d instead %d bit\n", + (this->options & NAND_BUSWIDTH_16) ? 16 : 8, + busw ? 16 : 8); + this->select_chip(mtd, -1); + return 1; + } + + /* Calculate the address shift from the page size */ + this->page_shift = ffs(mtd->oobblock) - 1; + this->bbt_erase_shift = this->phys_erase_shift = ffs(mtd->erasesize) - 1; + this->chip_shift = ffs(this->chipsize) - 1; + + /* Set the bad block position */ + this->badblockpos = mtd->oobblock > 512 ? + NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS; + + /* Get chip options, preserve non chip based options */ + this->options &= ~NAND_CHIPOPTIONS_MSK; + this->options |= nand_flash_ids[i].options & NAND_CHIPOPTIONS_MSK; + /* Set this as a default. Board drivers can override it, if neccecary */ + this->options |= NAND_NO_AUTOINCR; + /* Check if this is a not a samsung device. Do not clear the options + * for chips which are not having an extended id. + */ + if (nand_maf_id != NAND_MFR_SAMSUNG && !nand_flash_ids[i].pagesize) + this->options &= ~NAND_SAMSUNG_LP_OPTIONS; + + /* Check for AND chips with 4 page planes */ + if (this->options & NAND_4PAGE_ARRAY) + this->erase_cmd = multi_erase_cmd; + else + this->erase_cmd = single_erase_cmd; + + /* Do not replace user supplied command function ! */ + if (mtd->oobblock > 512 && this->cmdfunc == nand_command) + this->cmdfunc = nand_command_lp; + + /* Try to identify manufacturer */ + for (j = 0; nand_manuf_ids[j].id != 0x0; j++) { + if (nand_manuf_ids[j].id == nand_maf_id) + break; + } + break; + } + + if (!nand_flash_ids[i].name) { + printk (KERN_WARNING "No NAND device found!!!\n"); + this->select_chip(mtd, -1); + return 1; + } + + for (i=1; i < maxchips; i++) { + this->select_chip(mtd, i); + + /* Send the command for reading device ID */ + this->cmdfunc (mtd, NAND_CMD_READID, 0x00, -1); + + /* Read manufacturer and device IDs */ + if (nand_maf_id != this->read_byte(mtd) || + nand_dev_id != this->read_byte(mtd)) + break; + } + if (i > 1) + printk(KERN_INFO "%d NAND chips detected\n", i); + + /* Allocate buffers, if neccecary */ + if (!this->oob_buf) { + size_t len; + len = mtd->oobsize << (this->phys_erase_shift - this->page_shift); + this->oob_buf = kmalloc (len, GFP_KERNEL); + if (!this->oob_buf) { + printk (KERN_ERR "nand_scan(): Cannot allocate oob_buf\n"); + return -ENOMEM; + } + this->options |= NAND_OOBBUF_ALLOC; + } + + if (!this->data_buf) { + size_t len; + len = mtd->oobblock + mtd->oobsize; + this->data_buf = kmalloc (len, GFP_KERNEL); + if (!this->data_buf) { + if (this->options & NAND_OOBBUF_ALLOC) + kfree (this->oob_buf); + printk (KERN_ERR "nand_scan(): Cannot allocate data_buf\n"); + return -ENOMEM; + } + this->options |= NAND_DATABUF_ALLOC; + } + + /* Store the number of chips and calc total size for mtd */ + this->numchips = i; + mtd->size = i * this->chipsize; + /* Convert chipsize to number of pages per chip -1. */ + this->pagemask = (this->chipsize >> this->page_shift) - 1; + /* Preset the internal oob buffer */ + memset(this->oob_buf, 0xff, mtd->oobsize << (this->phys_erase_shift - this->page_shift)); + + /* If no default placement scheme is given, select an + * appropriate one */ + if (!this->autooob) { + /* Select the appropriate default oob placement scheme for + * placement agnostic filesystems */ + switch (mtd->oobsize) { + case 8: + this->autooob = &nand_oob_8; + break; + case 16: + this->autooob = &nand_oob_16; + break; + case 64: + this->autooob = &nand_oob_64; + break; + default: + printk (KERN_WARNING "No oob scheme defined for oobsize %d\n", + mtd->oobsize); +/* BUG(); */ + } + } + + /* The number of bytes available for the filesystem to place fs dependend + * oob data */ + if (this->options & NAND_BUSWIDTH_16) { + mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 2); + if (this->autooob->eccbytes & 0x01) + mtd->oobavail--; + } else + mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 1); + + /* + * check ECC mode, default to software + * if 3byte/512byte hardware ECC is selected and we have 256 byte pagesize + * fallback to software ECC + */ + this->eccsize = 256; /* set default eccsize */ + this->eccbytes = 3; + + switch (this->eccmode) { + case NAND_ECC_HW12_2048: + if (mtd->oobblock < 2048) { + printk(KERN_WARNING "2048 byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", + mtd->oobblock); + this->eccmode = NAND_ECC_SOFT; + this->calculate_ecc = nand_calculate_ecc; + this->correct_data = nand_correct_data; + } else + this->eccsize = 2048; + break; + + case NAND_ECC_HW3_512: + case NAND_ECC_HW6_512: + case NAND_ECC_HW8_512: + if (mtd->oobblock == 256) { + printk (KERN_WARNING "512 byte HW ECC not possible on 256 Byte pagesize, fallback to SW ECC \n"); + this->eccmode = NAND_ECC_SOFT; + this->calculate_ecc = nand_calculate_ecc; + this->correct_data = nand_correct_data; + } else + this->eccsize = 512; /* set eccsize to 512 */ + break; + + case NAND_ECC_HW3_256: + break; + + case NAND_ECC_NONE: + printk (KERN_WARNING "NAND_ECC_NONE selected by board driver. This is not recommended !!\n"); + this->eccmode = NAND_ECC_NONE; + break; + + case NAND_ECC_SOFT: + this->calculate_ecc = nand_calculate_ecc; + this->correct_data = nand_correct_data; + break; + + default: + printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode); +/* BUG(); */ + } + + /* Check hardware ecc function availability and adjust number of ecc bytes per + * calculation step + */ + switch (this->eccmode) { + case NAND_ECC_HW12_2048: + this->eccbytes += 4; + case NAND_ECC_HW8_512: + this->eccbytes += 2; + case NAND_ECC_HW6_512: + this->eccbytes += 3; + case NAND_ECC_HW3_512: + case NAND_ECC_HW3_256: + if (this->calculate_ecc && this->correct_data && this->enable_hwecc) + break; + printk (KERN_WARNING "No ECC functions supplied, Hardware ECC not possible\n"); +/* BUG(); */ + } + + mtd->eccsize = this->eccsize; + + /* Set the number of read / write steps for one page to ensure ECC generation */ + switch (this->eccmode) { + case NAND_ECC_HW12_2048: + this->eccsteps = mtd->oobblock / 2048; + break; + case NAND_ECC_HW3_512: + case NAND_ECC_HW6_512: + case NAND_ECC_HW8_512: + this->eccsteps = mtd->oobblock / 512; + break; + case NAND_ECC_HW3_256: + case NAND_ECC_SOFT: + this->eccsteps = mtd->oobblock / 256; + break; + + case NAND_ECC_NONE: + this->eccsteps = 1; + break; + } + +/* XXX U-BOOT XXX */ +#if 0 + /* Initialize state, waitqueue and spinlock */ + this->state = FL_READY; + init_waitqueue_head (&this->wq); + spin_lock_init (&this->chip_lock); +#endif + + /* De-select the device */ + this->select_chip(mtd, -1); + + /* Invalidate the pagebuffer reference */ + this->pagebuf = -1; + + /* Fill in remaining MTD driver data */ + mtd->type = MTD_NANDFLASH; + mtd->flags = MTD_CAP_NANDFLASH | MTD_ECC; + mtd->ecctype = MTD_ECC_SW; + mtd->erase = nand_erase; + mtd->point = NULL; + mtd->unpoint = NULL; + mtd->read = nand_read; + mtd->write = nand_write; + mtd->read_ecc = nand_read_ecc; + mtd->write_ecc = nand_write_ecc; + mtd->read_oob = nand_read_oob; + mtd->write_oob = nand_write_oob; +/* XXX U-BOOT XXX */ +#if 0 + mtd->readv = NULL; + mtd->writev = nand_writev; + mtd->writev_ecc = nand_writev_ecc; +#endif + mtd->sync = nand_sync; +/* XXX U-BOOT XXX */ +#if 0 + mtd->lock = NULL; + mtd->unlock = NULL; + mtd->suspend = NULL; + mtd->resume = NULL; +#endif + mtd->block_isbad = nand_block_isbad; + mtd->block_markbad = nand_block_markbad; + + /* and make the autooob the default one */ + memcpy(&mtd->oobinfo, this->autooob, sizeof(mtd->oobinfo)); +/* XXX U-BOOT XXX */ +#if 0 + mtd->owner = THIS_MODULE; +#endif + /* Build bad block table */ + return this->scan_bbt (mtd); +} + +/** + * nand_release - [NAND Interface] Free resources held by the NAND device + * @mtd: MTD device structure + */ +void nand_release (struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + +#ifdef CONFIG_MTD_PARTITIONS + /* Deregister partitions */ + del_mtd_partitions (mtd); +#endif + /* Deregister the device */ +/* XXX U-BOOT XXX */ +#if 0 + del_mtd_device (mtd); +#endif + /* Free bad block table memory, if allocated */ + if (this->bbt) + kfree (this->bbt); + /* Buffer allocated by nand_scan ? */ + if (this->options & NAND_OOBBUF_ALLOC) + kfree (this->oob_buf); + /* Buffer allocated by nand_scan ? */ + if (this->options & NAND_DATABUF_ALLOC) + kfree (this->data_buf); +} + +#endif diff --git a/drivers/nand/nand_bbt.c b/drivers/nand/nand_bbt.c new file mode 100644 index 0000000..ac16872 --- /dev/null +++ b/drivers/nand/nand_bbt.c @@ -0,0 +1,1056 @@ +/* + * drivers/mtd/nand_bbt.c + * + * Overview: + * Bad block table support for the NAND driver + * + * Copyright (C) 2004 Thomas Gleixner (tglx@linutronix.de) + * + * $Id: nand_bbt.c,v 1.28 2004/11/13 10:19:09 gleixner Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Description: + * + * When nand_scan_bbt is called, then it tries to find the bad block table + * depending on the options in the bbt descriptor(s). If a bbt is found + * then the contents are read and the memory based bbt is created. If a + * mirrored bbt is selected then the mirror is searched too and the + * versions are compared. If the mirror has a greater version number + * than the mirror bbt is used to build the memory based bbt. + * If the tables are not versioned, then we "or" the bad block information. + * If one of the bbt's is out of date or does not exist it is (re)created. + * If no bbt exists at all then the device is scanned for factory marked + * good / bad blocks and the bad block tables are created. + * + * For manufacturer created bbts like the one found on M-SYS DOC devices + * the bbt is searched and read but never created + * + * The autogenerated bad block table is located in the last good blocks + * of the device. The table is mirrored, so it can be updated eventually. + * The table is marked in the oob area with an ident pattern and a version + * number which indicates which of both tables is more up to date. + * + * The table uses 2 bits per block + * 11b: block is good + * 00b: block is factory marked bad + * 01b, 10b: block is marked bad due to wear + * + * The memory bad block table uses the following scheme: + * 00b: block is good + * 01b: block is marked bad due to wear + * 10b: block is reserved (to protect the bbt area) + * 11b: block is factory marked bad + * + * Multichip devices like DOC store the bad block info per floor. + * + * Following assumptions are made: + * - bbts start at a page boundary, if autolocated on a block boundary + * - the space neccecary for a bbt in FLASH does not exceed a block boundary + * + */ + +#include <common.h> + +#ifdef CFG_NAND_LEGACY +#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support! +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <malloc.h> +#include <linux/mtd/compat.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> + +#include <asm/errno.h> + +/** + * check_pattern - [GENERIC] check if a pattern is in the buffer + * @buf: the buffer to search + * @len: the length of buffer to search + * @paglen: the pagelength + * @td: search pattern descriptor + * + * Check for a pattern at the given place. Used to search bad block + * tables and good / bad block identifiers. + * If the SCAN_EMPTY option is set then check, if all bytes except the + * pattern area contain 0xff + * +*/ +static int check_pattern (uint8_t *buf, int len, int paglen, struct nand_bbt_descr *td) +{ + int i, end; + uint8_t *p = buf; + + end = paglen + td->offs; + if (td->options & NAND_BBT_SCANEMPTY) { + for (i = 0; i < end; i++) { + if (p[i] != 0xff) + return -1; + } + } + p += end; + + /* Compare the pattern */ + for (i = 0; i < td->len; i++) { + if (p[i] != td->pattern[i]) + return -1; + } + + p += td->len; + end += td->len; + if (td->options & NAND_BBT_SCANEMPTY) { + for (i = end; i < len; i++) { + if (*p++ != 0xff) + return -1; + } + } + return 0; +} + +/** + * read_bbt - [GENERIC] Read the bad block table starting from page + * @mtd: MTD device structure + * @buf: temporary buffer + * @page: the starting page + * @num: the number of bbt descriptors to read + * @bits: number of bits per block + * @offs: offset in the memory table + * @reserved_block_code: Pattern to identify reserved blocks + * + * Read the bad block table starting from page. + * + */ +static int read_bbt (struct mtd_info *mtd, uint8_t *buf, int page, int num, + int bits, int offs, int reserved_block_code) +{ + int res, i, j, act = 0; + struct nand_chip *this = mtd->priv; + size_t retlen, len, totlen; + loff_t from; + uint8_t msk = (uint8_t) ((1 << bits) - 1); + + totlen = (num * bits) >> 3; + from = ((loff_t)page) << this->page_shift; + + while (totlen) { + len = min (totlen, (size_t) (1 << this->bbt_erase_shift)); + res = mtd->read_ecc (mtd, from, len, &retlen, buf, NULL, this->autooob); + if (res < 0) { + if (retlen != len) { + printk (KERN_INFO "nand_bbt: Error reading bad block table\n"); + return res; + } + printk (KERN_WARNING "nand_bbt: ECC error while reading bad block table\n"); + } + + /* Analyse data */ + for (i = 0; i < len; i++) { + uint8_t dat = buf[i]; + for (j = 0; j < 8; j += bits, act += 2) { + uint8_t tmp = (dat >> j) & msk; + if (tmp == msk) + continue; + if (reserved_block_code && + (tmp == reserved_block_code)) { + printk (KERN_DEBUG "nand_read_bbt: Reserved block at 0x%08x\n", + ((offs << 2) + (act >> 1)) << this->bbt_erase_shift); + this->bbt[offs + (act >> 3)] |= 0x2 << (act & 0x06); + continue; + } + /* Leave it for now, if its matured we can move this + * message to MTD_DEBUG_LEVEL0 */ + printk (KERN_DEBUG "nand_read_bbt: Bad block at 0x%08x\n", + ((offs << 2) + (act >> 1)) << this->bbt_erase_shift); + /* Factory marked bad or worn out ? */ + if (tmp == 0) + this->bbt[offs + (act >> 3)] |= 0x3 << (act & 0x06); + else + this->bbt[offs + (act >> 3)] |= 0x1 << (act & 0x06); + } + } + totlen -= len; + from += len; + } + return 0; +} + +/** + * read_abs_bbt - [GENERIC] Read the bad block table starting at a given page + * @mtd: MTD device structure + * @buf: temporary buffer + * @td: descriptor for the bad block table + * @chip: read the table for a specific chip, -1 read all chips. + * Applies only if NAND_BBT_PERCHIP option is set + * + * Read the bad block table for all chips starting at a given page + * We assume that the bbt bits are in consecutive order. +*/ +static int read_abs_bbt (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td, int chip) +{ + struct nand_chip *this = mtd->priv; + int res = 0, i; + int bits; + + bits = td->options & NAND_BBT_NRBITS_MSK; + if (td->options & NAND_BBT_PERCHIP) { + int offs = 0; + for (i = 0; i < this->numchips; i++) { + if (chip == -1 || chip == i) + res = read_bbt (mtd, buf, td->pages[i], this->chipsize >> this->bbt_erase_shift, bits, offs, td->reserved_block_code); + if (res) + return res; + offs += this->chipsize >> (this->bbt_erase_shift + 2); + } + } else { + res = read_bbt (mtd, buf, td->pages[0], mtd->size >> this->bbt_erase_shift, bits, 0, td->reserved_block_code); + if (res) + return res; + } + return 0; +} + +/** + * read_abs_bbts - [GENERIC] Read the bad block table(s) for all chips starting at a given page + * @mtd: MTD device structure + * @buf: temporary buffer + * @td: descriptor for the bad block table + * @md: descriptor for the bad block table mirror + * + * Read the bad block table(s) for all chips starting at a given page + * We assume that the bbt bits are in consecutive order. + * +*/ +static int read_abs_bbts (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td, + struct nand_bbt_descr *md) +{ + struct nand_chip *this = mtd->priv; + + /* Read the primary version, if available */ + if (td->options & NAND_BBT_VERSION) { + nand_read_raw (mtd, buf, td->pages[0] << this->page_shift, mtd->oobblock, mtd->oobsize); + td->version[0] = buf[mtd->oobblock + td->veroffs]; + printk (KERN_DEBUG "Bad block table at page %d, version 0x%02X\n", td->pages[0], td->version[0]); + } + + /* Read the mirror version, if available */ + if (md && (md->options & NAND_BBT_VERSION)) { + nand_read_raw (mtd, buf, md->pages[0] << this->page_shift, mtd->oobblock, mtd->oobsize); + md->version[0] = buf[mtd->oobblock + md->veroffs]; + printk (KERN_DEBUG "Bad block table at page %d, version 0x%02X\n", md->pages[0], md->version[0]); + } + + return 1; +} + +/** + * create_bbt - [GENERIC] Create a bad block table by scanning the device + * @mtd: MTD device structure + * @buf: temporary buffer + * @bd: descriptor for the good/bad block search pattern + * @chip: create the table for a specific chip, -1 read all chips. + * Applies only if NAND_BBT_PERCHIP option is set + * + * Create a bad block table by scanning the device + * for the given good/bad block identify pattern + */ +static void create_bbt (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd, int chip) +{ + struct nand_chip *this = mtd->priv; + int i, j, numblocks, len, scanlen; + int startblock; + loff_t from; + size_t readlen, ooblen; + + if (bd->options & NAND_BBT_SCANALLPAGES) + len = 1 << (this->bbt_erase_shift - this->page_shift); + else { + if (bd->options & NAND_BBT_SCAN2NDPAGE) + len = 2; + else + len = 1; + } + scanlen = mtd->oobblock + mtd->oobsize; + readlen = len * mtd->oobblock; + ooblen = len * mtd->oobsize; + + if (chip == -1) { + /* Note that numblocks is 2 * (real numblocks) here, see i+=2 below as it + * makes shifting and masking less painful */ + numblocks = mtd->size >> (this->bbt_erase_shift - 1); + startblock = 0; + from = 0; + } else { + if (chip >= this->numchips) { + printk (KERN_WARNING "create_bbt(): chipnr (%d) > available chips (%d)\n", + chip + 1, this->numchips); + return; + } + numblocks = this->chipsize >> (this->bbt_erase_shift - 1); + startblock = chip * numblocks; + numblocks += startblock; + from = startblock << (this->bbt_erase_shift - 1); + } + + for (i = startblock; i < numblocks;) { + nand_read_raw (mtd, buf, from, readlen, ooblen); + for (j = 0; j < len; j++) { + if (check_pattern (&buf[j * scanlen], scanlen, mtd->oobblock, bd)) { + this->bbt[i >> 3] |= 0x03 << (i & 0x6); + break; + } + } + i += 2; + from += (1 << this->bbt_erase_shift); + } +} + +/** + * search_bbt - [GENERIC] scan the device for a specific bad block table + * @mtd: MTD device structure + * @buf: temporary buffer + * @td: descriptor for the bad block table + * + * Read the bad block table by searching for a given ident pattern. + * Search is preformed either from the beginning up or from the end of + * the device downwards. The search starts always at the start of a + * block. + * If the option NAND_BBT_PERCHIP is given, each chip is searched + * for a bbt, which contains the bad block information of this chip. + * This is neccecary to provide support for certain DOC devices. + * + * The bbt ident pattern resides in the oob area of the first page + * in a block. + */ +static int search_bbt (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td) +{ + struct nand_chip *this = mtd->priv; + int i, chips; + int bits, startblock, block, dir; + int scanlen = mtd->oobblock + mtd->oobsize; + int bbtblocks; + + /* Search direction top -> down ? */ + if (td->options & NAND_BBT_LASTBLOCK) { + startblock = (mtd->size >> this->bbt_erase_shift) -1; + dir = -1; + } else { + startblock = 0; + dir = 1; + } + + /* Do we have a bbt per chip ? */ + if (td->options & NAND_BBT_PERCHIP) { + chips = this->numchips; + bbtblocks = this->chipsize >> this->bbt_erase_shift; + startblock &= bbtblocks - 1; + } else { + chips = 1; + bbtblocks = mtd->size >> this->bbt_erase_shift; + } + + /* Number of bits for each erase block in the bbt */ + bits = td->options & NAND_BBT_NRBITS_MSK; + + for (i = 0; i < chips; i++) { + /* Reset version information */ + td->version[i] = 0; + td->pages[i] = -1; + /* Scan the maximum number of blocks */ + for (block = 0; block < td->maxblocks; block++) { + int actblock = startblock + dir * block; + /* Read first page */ + nand_read_raw (mtd, buf, actblock << this->bbt_erase_shift, mtd->oobblock, mtd->oobsize); + if (!check_pattern(buf, scanlen, mtd->oobblock, td)) { + td->pages[i] = actblock << (this->bbt_erase_shift - this->page_shift); + if (td->options & NAND_BBT_VERSION) { + td->version[i] = buf[mtd->oobblock + td->veroffs]; + } + break; + } + } + startblock += this->chipsize >> this->bbt_erase_shift; + } + /* Check, if we found a bbt for each requested chip */ + for (i = 0; i < chips; i++) { + if (td->pages[i] == -1) + printk (KERN_WARNING "Bad block table not found for chip %d\n", i); + else + printk (KERN_DEBUG "Bad block table found at page %d, version 0x%02X\n", td->pages[i], td->version[i]); + } + return 0; +} + +/** + * search_read_bbts - [GENERIC] scan the device for bad block table(s) + * @mtd: MTD device structure + * @buf: temporary buffer + * @td: descriptor for the bad block table + * @md: descriptor for the bad block table mirror + * + * Search and read the bad block table(s) +*/ +static int search_read_bbts (struct mtd_info *mtd, uint8_t *buf, + struct nand_bbt_descr *td, struct nand_bbt_descr *md) +{ + /* Search the primary table */ + search_bbt (mtd, buf, td); + + /* Search the mirror table */ + if (md) + search_bbt (mtd, buf, md); + + /* Force result check */ + return 1; +} + + +/** + * write_bbt - [GENERIC] (Re)write the bad block table + * + * @mtd: MTD device structure + * @buf: temporary buffer + * @td: descriptor for the bad block table + * @md: descriptor for the bad block table mirror + * @chipsel: selector for a specific chip, -1 for all + * + * (Re)write the bad block table + * +*/ +static int write_bbt (struct mtd_info *mtd, uint8_t *buf, + struct nand_bbt_descr *td, struct nand_bbt_descr *md, int chipsel) +{ + struct nand_chip *this = mtd->priv; + struct nand_oobinfo oobinfo; + struct erase_info einfo; + int i, j, res, chip = 0; + int bits, startblock, dir, page, offs, numblocks, sft, sftmsk; + int nrchips, bbtoffs, pageoffs; + uint8_t msk[4]; + uint8_t rcode = td->reserved_block_code; + size_t retlen, len = 0; + loff_t to; + + if (!rcode) + rcode = 0xff; + /* Write bad block table per chip rather than per device ? */ + if (td->options & NAND_BBT_PERCHIP) { + numblocks = (int) (this->chipsize >> this->bbt_erase_shift); + /* Full device write or specific chip ? */ + if (chipsel == -1) { + nrchips = this->numchips; + } else { + nrchips = chipsel + 1; + chip = chipsel; + } + } else { + numblocks = (int) (mtd->size >> this->bbt_erase_shift); + nrchips = 1; + } + + /* Loop through the chips */ + for (; chip < nrchips; chip++) { + + /* There was already a version of the table, reuse the page + * This applies for absolute placement too, as we have the + * page nr. in td->pages. + */ + if (td->pages[chip] != -1) { + page = td->pages[chip]; + goto write; + } + + /* Automatic placement of the bad block table */ + /* Search direction top -> down ? */ + if (td->options & NAND_BBT_LASTBLOCK) { + startblock = numblocks * (chip + 1) - 1; + dir = -1; + } else { + startblock = chip * numblocks; + dir = 1; + } + + for (i = 0; i < td->maxblocks; i++) { + int block = startblock + dir * i; + /* Check, if the block is bad */ + switch ((this->bbt[block >> 2] >> (2 * (block & 0x03))) & 0x03) { + case 0x01: + case 0x03: + continue; + } + page = block << (this->bbt_erase_shift - this->page_shift); + /* Check, if the block is used by the mirror table */ + if (!md || md->pages[chip] != page) + goto write; + } + printk (KERN_ERR "No space left to write bad block table\n"); + return -ENOSPC; +write: + + /* Set up shift count and masks for the flash table */ + bits = td->options & NAND_BBT_NRBITS_MSK; + switch (bits) { + case 1: sft = 3; sftmsk = 0x07; msk[0] = 0x00; msk[1] = 0x01; msk[2] = ~rcode; msk[3] = 0x01; break; + case 2: sft = 2; sftmsk = 0x06; msk[0] = 0x00; msk[1] = 0x01; msk[2] = ~rcode; msk[3] = 0x03; break; + case 4: sft = 1; sftmsk = 0x04; msk[0] = 0x00; msk[1] = 0x0C; msk[2] = ~rcode; msk[3] = 0x0f; break; + case 8: sft = 0; sftmsk = 0x00; msk[0] = 0x00; msk[1] = 0x0F; msk[2] = ~rcode; msk[3] = 0xff; break; + default: return -EINVAL; + } + + bbtoffs = chip * (numblocks >> 2); + + to = ((loff_t) page) << this->page_shift; + + memcpy (&oobinfo, this->autooob, sizeof(oobinfo)); + oobinfo.useecc = MTD_NANDECC_PLACEONLY; + + /* Must we save the block contents ? */ + if (td->options & NAND_BBT_SAVECONTENT) { + /* Make it block aligned */ + to &= ~((loff_t) ((1 << this->bbt_erase_shift) - 1)); + len = 1 << this->bbt_erase_shift; + res = mtd->read_ecc (mtd, to, len, &retlen, buf, &buf[len], &oobinfo); + if (res < 0) { + if (retlen != len) { + printk (KERN_INFO "nand_bbt: Error reading block for writing the bad block table\n"); + return res; + } + printk (KERN_WARNING "nand_bbt: ECC error while reading block for writing bad block table\n"); + } + /* Calc the byte offset in the buffer */ + pageoffs = page - (int)(to >> this->page_shift); + offs = pageoffs << this->page_shift; + /* Preset the bbt area with 0xff */ + memset (&buf[offs], 0xff, (size_t)(numblocks >> sft)); + /* Preset the bbt's oob area with 0xff */ + memset (&buf[len + pageoffs * mtd->oobsize], 0xff, + ((len >> this->page_shift) - pageoffs) * mtd->oobsize); + if (td->options & NAND_BBT_VERSION) { + buf[len + (pageoffs * mtd->oobsize) + td->veroffs] = td->version[chip]; + } + } else { + /* Calc length */ + len = (size_t) (numblocks >> sft); + /* Make it page aligned ! */ + len = (len + (mtd->oobblock-1)) & ~(mtd->oobblock-1); + /* Preset the buffer with 0xff */ + memset (buf, 0xff, len + (len >> this->page_shift) * mtd->oobsize); + offs = 0; + /* Pattern is located in oob area of first page */ + memcpy (&buf[len + td->offs], td->pattern, td->len); + if (td->options & NAND_BBT_VERSION) { + buf[len + td->veroffs] = td->version[chip]; + } + } + + /* walk through the memory table */ + for (i = 0; i < numblocks; ) { + uint8_t dat; + dat = this->bbt[bbtoffs + (i >> 2)]; + for (j = 0; j < 4; j++ , i++) { + int sftcnt = (i << (3 - sft)) & sftmsk; + /* Do not store the reserved bbt blocks ! */ + buf[offs + (i >> sft)] &= ~(msk[dat & 0x03] << sftcnt); + dat >>= 2; + } + } + + memset (&einfo, 0, sizeof (einfo)); + einfo.mtd = mtd; + einfo.addr = (unsigned long) to; + einfo.len = 1 << this->bbt_erase_shift; + res = nand_erase_nand (mtd, &einfo, 1); + if (res < 0) { + printk (KERN_WARNING "nand_bbt: Error during block erase: %d\n", res); + return res; + } + + res = mtd->write_ecc (mtd, to, len, &retlen, buf, &buf[len], &oobinfo); + if (res < 0) { + printk (KERN_WARNING "nand_bbt: Error while writing bad block table %d\n", res); + return res; + } + printk (KERN_DEBUG "Bad block table written to 0x%08x, version 0x%02X\n", + (unsigned int) to, td->version[chip]); + + /* Mark it as used */ + td->pages[chip] = page; + } + return 0; +} + +/** + * nand_memory_bbt - [GENERIC] create a memory based bad block table + * @mtd: MTD device structure + * @bd: descriptor for the good/bad block search pattern + * + * The function creates a memory based bbt by scanning the device + * for manufacturer / software marked good / bad blocks +*/ +static int nand_memory_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd) +{ + struct nand_chip *this = mtd->priv; + + /* Ensure that we only scan for the pattern and nothing else */ + bd->options = 0; + create_bbt (mtd, this->data_buf, bd, -1); + return 0; +} + +/** + * check_create - [GENERIC] create and write bbt(s) if neccecary + * @mtd: MTD device structure + * @buf: temporary buffer + * @bd: descriptor for the good/bad block search pattern + * + * The function checks the results of the previous call to read_bbt + * and creates / updates the bbt(s) if neccecary + * Creation is neccecary if no bbt was found for the chip/device + * Update is neccecary if one of the tables is missing or the + * version nr. of one table is less than the other +*/ +static int check_create (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd) +{ + int i, chips, writeops, chipsel, res; + struct nand_chip *this = mtd->priv; + struct nand_bbt_descr *td = this->bbt_td; + struct nand_bbt_descr *md = this->bbt_md; + struct nand_bbt_descr *rd, *rd2; + + /* Do we have a bbt per chip ? */ + if (td->options & NAND_BBT_PERCHIP) + chips = this->numchips; + else + chips = 1; + + for (i = 0; i < chips; i++) { + writeops = 0; + rd = NULL; + rd2 = NULL; + /* Per chip or per device ? */ + chipsel = (td->options & NAND_BBT_PERCHIP) ? i : -1; + /* Mirrored table avilable ? */ + if (md) { + if (td->pages[i] == -1 && md->pages[i] == -1) { + writeops = 0x03; + goto create; + } + + if (td->pages[i] == -1) { + rd = md; + td->version[i] = md->version[i]; + writeops = 1; + goto writecheck; + } + + if (md->pages[i] == -1) { + rd = td; + md->version[i] = td->version[i]; + writeops = 2; + goto writecheck; + } + + if (td->version[i] == md->version[i]) { + rd = td; + if (!(td->options & NAND_BBT_VERSION)) + rd2 = md; + goto writecheck; + } + + if (((int8_t) (td->version[i] - md->version[i])) > 0) { + rd = td; + md->version[i] = td->version[i]; + writeops = 2; + } else { + rd = md; + td->version[i] = md->version[i]; + writeops = 1; + } + + goto writecheck; + + } else { + if (td->pages[i] == -1) { + writeops = 0x01; + goto create; + } + rd = td; + goto writecheck; + } +create: + /* Create the bad block table by scanning the device ? */ + if (!(td->options & NAND_BBT_CREATE)) + continue; + + /* Create the table in memory by scanning the chip(s) */ + create_bbt (mtd, buf, bd, chipsel); + + td->version[i] = 1; + if (md) + md->version[i] = 1; +writecheck: + /* read back first ? */ + if (rd) + read_abs_bbt (mtd, buf, rd, chipsel); + /* If they weren't versioned, read both. */ + if (rd2) + read_abs_bbt (mtd, buf, rd2, chipsel); + + /* Write the bad block table to the device ? */ + if ((writeops & 0x01) && (td->options & NAND_BBT_WRITE)) { + res = write_bbt (mtd, buf, td, md, chipsel); + if (res < 0) + return res; + } + + /* Write the mirror bad block table to the device ? */ + if ((writeops & 0x02) && md && (md->options & NAND_BBT_WRITE)) { + res = write_bbt (mtd, buf, md, td, chipsel); + if (res < 0) + return res; + } + } + return 0; +} + +/** + * mark_bbt_regions - [GENERIC] mark the bad block table regions + * @mtd: MTD device structure + * @td: bad block table descriptor + * + * The bad block table regions are marked as "bad" to prevent + * accidental erasures / writes. The regions are identified by + * the mark 0x02. +*/ +static void mark_bbt_region (struct mtd_info *mtd, struct nand_bbt_descr *td) +{ + struct nand_chip *this = mtd->priv; + int i, j, chips, block, nrblocks, update; + uint8_t oldval, newval; + + /* Do we have a bbt per chip ? */ + if (td->options & NAND_BBT_PERCHIP) { + chips = this->numchips; + nrblocks = (int)(this->chipsize >> this->bbt_erase_shift); + } else { + chips = 1; + nrblocks = (int)(mtd->size >> this->bbt_erase_shift); + } + + for (i = 0; i < chips; i++) { + if ((td->options & NAND_BBT_ABSPAGE) || + !(td->options & NAND_BBT_WRITE)) { + if (td->pages[i] == -1) continue; + block = td->pages[i] >> (this->bbt_erase_shift - this->page_shift); + block <<= 1; + oldval = this->bbt[(block >> 3)]; + newval = oldval | (0x2 << (block & 0x06)); + this->bbt[(block >> 3)] = newval; + if ((oldval != newval) && td->reserved_block_code) + nand_update_bbt(mtd, block << (this->bbt_erase_shift - 1)); + continue; + } + update = 0; + if (td->options & NAND_BBT_LASTBLOCK) + block = ((i + 1) * nrblocks) - td->maxblocks; + else + block = i * nrblocks; + block <<= 1; + for (j = 0; j < td->maxblocks; j++) { + oldval = this->bbt[(block >> 3)]; + newval = oldval | (0x2 << (block & 0x06)); + this->bbt[(block >> 3)] = newval; + if (oldval != newval) update = 1; + block += 2; + } + /* If we want reserved blocks to be recorded to flash, and some + new ones have been marked, then we need to update the stored + bbts. This should only happen once. */ + if (update && td->reserved_block_code) + nand_update_bbt(mtd, (block - 2) << (this->bbt_erase_shift - 1)); + } +} + +/** + * nand_scan_bbt - [NAND Interface] scan, find, read and maybe create bad block table(s) + * @mtd: MTD device structure + * @bd: descriptor for the good/bad block search pattern + * + * The function checks, if a bad block table(s) is/are already + * available. If not it scans the device for manufacturer + * marked good / bad blocks and writes the bad block table(s) to + * the selected place. + * + * The bad block table memory is allocated here. It must be freed + * by calling the nand_free_bbt function. + * +*/ +int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd) +{ + struct nand_chip *this = mtd->priv; + int len, res = 0; + uint8_t *buf; + struct nand_bbt_descr *td = this->bbt_td; + struct nand_bbt_descr *md = this->bbt_md; + + len = mtd->size >> (this->bbt_erase_shift + 2); + /* Allocate memory (2bit per block) */ + this->bbt = kmalloc (len, GFP_KERNEL); + if (!this->bbt) { + printk (KERN_ERR "nand_scan_bbt: Out of memory\n"); + return -ENOMEM; + } + /* Clear the memory bad block table */ + memset (this->bbt, 0x00, len); + + /* If no primary table decriptor is given, scan the device + * to build a memory based bad block table + */ + if (!td) + return nand_memory_bbt(mtd, bd); + + /* Allocate a temporary buffer for one eraseblock incl. oob */ + len = (1 << this->bbt_erase_shift); + len += (len >> this->page_shift) * mtd->oobsize; + buf = kmalloc (len, GFP_KERNEL); + if (!buf) { + printk (KERN_ERR "nand_bbt: Out of memory\n"); + kfree (this->bbt); + this->bbt = NULL; + return -ENOMEM; + } + + /* Is the bbt at a given page ? */ + if (td->options & NAND_BBT_ABSPAGE) { + res = read_abs_bbts (mtd, buf, td, md); + } else { + /* Search the bad block table using a pattern in oob */ + res = search_read_bbts (mtd, buf, td, md); + } + + if (res) + res = check_create (mtd, buf, bd); + + /* Prevent the bbt regions from erasing / writing */ + mark_bbt_region (mtd, td); + if (md) + mark_bbt_region (mtd, md); + + kfree (buf); + return res; +} + + +/** + * nand_update_bbt - [NAND Interface] update bad block table(s) + * @mtd: MTD device structure + * @offs: the offset of the newly marked block + * + * The function updates the bad block table(s) +*/ +int nand_update_bbt (struct mtd_info *mtd, loff_t offs) +{ + struct nand_chip *this = mtd->priv; + int len, res = 0, writeops = 0; + int chip, chipsel; + uint8_t *buf; + struct nand_bbt_descr *td = this->bbt_td; + struct nand_bbt_descr *md = this->bbt_md; + + if (!this->bbt || !td) + return -EINVAL; + + len = mtd->size >> (this->bbt_erase_shift + 2); + /* Allocate a temporary buffer for one eraseblock incl. oob */ + len = (1 << this->bbt_erase_shift); + len += (len >> this->page_shift) * mtd->oobsize; + buf = kmalloc (len, GFP_KERNEL); + if (!buf) { + printk (KERN_ERR "nand_update_bbt: Out of memory\n"); + return -ENOMEM; + } + + writeops = md != NULL ? 0x03 : 0x01; + + /* Do we have a bbt per chip ? */ + if (td->options & NAND_BBT_PERCHIP) { + chip = (int) (offs >> this->chip_shift); + chipsel = chip; + } else { + chip = 0; + chipsel = -1; + } + + td->version[chip]++; + if (md) + md->version[chip]++; + + /* Write the bad block table to the device ? */ + if ((writeops & 0x01) && (td->options & NAND_BBT_WRITE)) { + res = write_bbt (mtd, buf, td, md, chipsel); + if (res < 0) + goto out; + } + /* Write the mirror bad block table to the device ? */ + if ((writeops & 0x02) && md && (md->options & NAND_BBT_WRITE)) { + res = write_bbt (mtd, buf, md, td, chipsel); + } + +out: + kfree (buf); + return res; +} + +/* Define some generic bad / good block scan pattern which are used + * while scanning a device for factory marked good / bad blocks + * + * The memory based patterns just + */ +static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr smallpage_memorybased = { + .options = 0, + .offs = 5, + .len = 1, + .pattern = scan_ff_pattern +}; + +static struct nand_bbt_descr largepage_memorybased = { + .options = 0, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern +}; + +static struct nand_bbt_descr smallpage_flashbased = { + .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, + .offs = 5, + .len = 1, + .pattern = scan_ff_pattern +}; + +static struct nand_bbt_descr largepage_flashbased = { + .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern +}; + +static uint8_t scan_agand_pattern[] = { 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xC7 }; + +static struct nand_bbt_descr agand_flashbased = { + .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, + .offs = 0x20, + .len = 6, + .pattern = scan_agand_pattern +}; + +/* Generic flash bbt decriptors +*/ +static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; +static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 8, + .len = 4, + .veroffs = 12, + .maxblocks = 4, + .pattern = bbt_pattern +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 8, + .len = 4, + .veroffs = 12, + .maxblocks = 4, + .pattern = mirror_pattern +}; + +/** + * nand_default_bbt - [NAND Interface] Select a default bad block table for the device + * @mtd: MTD device structure + * + * This function selects the default bad block table + * support for the device and calls the nand_scan_bbt function + * +*/ +int nand_default_bbt (struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + + /* Default for AG-AND. We must use a flash based + * bad block table as the devices have factory marked + * _good_ blocks. Erasing those blocks leads to loss + * of the good / bad information, so we _must_ store + * this information in a good / bad table during + * startup + */ + if (this->options & NAND_IS_AND) { + /* Use the default pattern descriptors */ + if (!this->bbt_td) { + this->bbt_td = &bbt_main_descr; + this->bbt_md = &bbt_mirror_descr; + } + this->options |= NAND_USE_FLASH_BBT; + return nand_scan_bbt (mtd, &agand_flashbased); + } + + + /* Is a flash based bad block table requested ? */ + if (this->options & NAND_USE_FLASH_BBT) { + /* Use the default pattern descriptors */ + if (!this->bbt_td) { + this->bbt_td = &bbt_main_descr; + this->bbt_md = &bbt_mirror_descr; + } + if (!this->badblock_pattern) { + this->badblock_pattern = (mtd->oobblock > 512) ? + &largepage_flashbased : &smallpage_flashbased; + } + } else { + this->bbt_td = NULL; + this->bbt_md = NULL; + if (!this->badblock_pattern) { + this->badblock_pattern = (mtd->oobblock > 512) ? + &largepage_memorybased : &smallpage_memorybased; + } + } + return nand_scan_bbt (mtd, this->badblock_pattern); +} + +/** + * nand_isbad_bbt - [NAND Interface] Check if a block is bad + * @mtd: MTD device structure + * @offs: offset in the device + * @allowbbt: allow access to bad block table region + * + */ +int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt) +{ + struct nand_chip *this = mtd->priv; + int block; + uint8_t res; + + /* Get block number * 2 */ + block = (int) (offs >> (this->bbt_erase_shift - 1)); + res = (this->bbt[block >> 3] >> (block & 0x06)) & 0x03; + + DEBUG (MTD_DEBUG_LEVEL2, "nand_isbad_bbt(): bbt info for offs 0x%08x: (block %d) 0x%02x\n", + (unsigned int)offs, res, block >> 1); + + switch ((int)res) { + case 0x00: return 0; + case 0x01: return 1; + case 0x02: return allowbbt ? 0 : 1; + } + return 1; +} + +#endif diff --git a/drivers/nand/nand_ecc.c b/drivers/nand/nand_ecc.c new file mode 100644 index 0000000..e0d0e8b --- /dev/null +++ b/drivers/nand/nand_ecc.c @@ -0,0 +1,248 @@ +/* + * This file contains an ECC algorithm from Toshiba that detects and + * corrects 1 bit errors in a 256 byte block of data. + * + * drivers/mtd/nand/nand_ecc.c + * + * Copyright (C) 2000-2004 Steven J. Hill (sjhill@realitydiluted.com) + * Toshiba America Electronics Components, Inc. + * + * $Id: nand_ecc.c,v 1.14 2004/06/16 15:34:37 gleixner Exp $ + * + * This file is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 or (at your option) any + * later version. + * + * This file is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this file; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + * + * As a special exception, if other files instantiate templates or use + * macros or inline functions from these files, or you compile these + * files and link them with other works to produce a work based on these + * files, these files do not by themselves cause the resulting work to be + * covered by the GNU General Public License. However the source code for + * these files must still be made available in accordance with section (3) + * of the GNU General Public License. + * + * This exception does not invalidate any other reasons why a work based on + * this file might be covered by the GNU General Public License. + */ + +#include <common.h> + +#ifdef CFG_NAND_LEGACY +#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support! +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include<linux/mtd/mtd.h> +/* + * Pre-calculated 256-way 1 byte column parity + */ +static const u_char nand_ecc_precalc_table[] = { + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00 +}; + + +/** + * nand_trans_result - [GENERIC] create non-inverted ECC + * @reg2: line parity reg 2 + * @reg3: line parity reg 3 + * @ecc_code: ecc + * + * Creates non-inverted ECC code from line parity + */ +static void nand_trans_result(u_char reg2, u_char reg3, + u_char *ecc_code) +{ + u_char a, b, i, tmp1, tmp2; + + /* Initialize variables */ + a = b = 0x80; + tmp1 = tmp2 = 0; + + /* Calculate first ECC byte */ + for (i = 0; i < 4; i++) { + if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */ + tmp1 |= b; + b >>= 1; + if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */ + tmp1 |= b; + b >>= 1; + a >>= 1; + } + + /* Calculate second ECC byte */ + b = 0x80; + for (i = 0; i < 4; i++) { + if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */ + tmp2 |= b; + b >>= 1; + if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */ + tmp2 |= b; + b >>= 1; + a >>= 1; + } + + /* Store two of the ECC bytes */ + ecc_code[0] = tmp1; + ecc_code[1] = tmp2; +} + +/** + * nand_calculate_ecc - [NAND Interface] Calculate 3 byte ECC code for 256 byte block + * @mtd: MTD block structure + * @dat: raw data + * @ecc_code: buffer for ECC + */ +int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) +{ + u_char idx, reg1, reg2, reg3; + int j; + + /* Initialize variables */ + reg1 = reg2 = reg3 = 0; + ecc_code[0] = ecc_code[1] = ecc_code[2] = 0; + + /* Build up column parity */ + for(j = 0; j < 256; j++) { + + /* Get CP0 - CP5 from table */ + idx = nand_ecc_precalc_table[dat[j]]; + reg1 ^= (idx & 0x3f); + + /* All bit XOR = 1 ? */ + if (idx & 0x40) { + reg3 ^= (u_char) j; + reg2 ^= ~((u_char) j); + } + } + + /* Create non-inverted ECC code from line parity */ + nand_trans_result(reg2, reg3, ecc_code); + + /* Calculate final ECC code */ + ecc_code[0] = ~ecc_code[0]; + ecc_code[1] = ~ecc_code[1]; + ecc_code[2] = ((~reg1) << 2) | 0x03; + return 0; +} + +/** + * nand_correct_data - [NAND Interface] Detect and correct bit error(s) + * @mtd: MTD block structure + * @dat: raw data read from the chip + * @read_ecc: ECC from the chip + * @calc_ecc: the ECC calculated from raw data + * + * Detect and correct a 1 bit error for 256 byte block + */ +int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) +{ + u_char a, b, c, d1, d2, d3, add, bit, i; + + /* Do error detection */ + d1 = calc_ecc[0] ^ read_ecc[0]; + d2 = calc_ecc[1] ^ read_ecc[1]; + d3 = calc_ecc[2] ^ read_ecc[2]; + + if ((d1 | d2 | d3) == 0) { + /* No errors */ + return 0; + } + else { + a = (d1 ^ (d1 >> 1)) & 0x55; + b = (d2 ^ (d2 >> 1)) & 0x55; + c = (d3 ^ (d3 >> 1)) & 0x54; + + /* Found and will correct single bit error in the data */ + if ((a == 0x55) && (b == 0x55) && (c == 0x54)) { + c = 0x80; + add = 0; + a = 0x80; + for (i=0; i<4; i++) { + if (d1 & c) + add |= a; + c >>= 2; + a >>= 1; + } + c = 0x80; + for (i=0; i<4; i++) { + if (d2 & c) + add |= a; + c >>= 2; + a >>= 1; + } + bit = 0; + b = 0x04; + c = 0x80; + for (i=0; i<3; i++) { + if (d3 & c) + bit |= b; + c >>= 2; + b >>= 1; + } + b = 0x01; + a = dat[add]; + a ^= (b << bit); + dat[add] = a; + return 1; + } else { + i = 0; + while (d1) { + if (d1 & 0x01) + ++i; + d1 >>= 1; + } + while (d2) { + if (d2 & 0x01) + ++i; + d2 >>= 1; + } + while (d3) { + if (d3 & 0x01) + ++i; + d3 >>= 1; + } + if (i == 1) { + /* ECC Code Error Correction */ + read_ecc[0] = calc_ecc[0]; + read_ecc[1] = calc_ecc[1]; + read_ecc[2] = calc_ecc[2]; + return 2; + } + else { + /* Uncorrectable Error */ + return -1; + } + } + } + + /* Should never happen */ + return -1; +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */ diff --git a/drivers/nand/nand_ids.c b/drivers/nand/nand_ids.c new file mode 100644 index 0000000..3d4d372 --- /dev/null +++ b/drivers/nand/nand_ids.c @@ -0,0 +1,132 @@ +/* + * drivers/mtd/nandids.c + * + * Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de) + * + * $Id: nand_ids.c,v 1.10 2004/05/26 13:40:12 gleixner Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <common.h> + +#ifdef CFG_NAND_LEGACY +#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support! +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <linux/mtd/nand.h> + +/* +* Chip ID list +* +* Name. ID code, pagesize, chipsize in MegaByte, eraseblock size, +* options +* +* Pagesize; 0, 256, 512 +* 0 get this information from the extended chip ID ++ 256 256 Byte page size +* 512 512 Byte page size +*/ +struct nand_flash_dev nand_flash_ids[] = { + {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0}, + {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0}, + {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0}, + {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0}, + {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0}, + {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0}, + {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0}, + {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0}, + {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0}, + {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0}, + + {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0}, + {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0}, + {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16}, + {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16}, + + {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0}, + {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0}, + {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16}, + {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16}, + + {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0}, + {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0}, + {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16}, + {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16}, + + {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0}, + {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0}, + {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16}, + {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16}, + + {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0}, + {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0}, + {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16}, + {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16}, + + {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0}, + + {"NAND 512MiB 3,3V 8-bit", 0xDC, 512, 512, 0x4000, 0}, + + /* These are the new chips with large page size. The pagesize + * and the erasesize is determined from the extended id bytes + */ + /* 1 Gigabit */ + {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + + /* 2 Gigabit */ + {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + + /* 4 Gigabit */ + {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + + /* 8 Gigabit */ + {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + + /* 16 Gigabit */ + {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + + /* Renesas AND 1 Gigabit. Those chips do not support extended id and have a strange page/block layout ! + * The chosen minimum erasesize is 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page planes + * 1 block = 2 pages, but due to plane arrangement the blocks 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7 + * Anyway JFFS2 would increase the eraseblock size so we chose a combined one which can be erased in one go + * There are more speed improvements for reads and writes possible, but not implemented now + */ + {"AND 128MiB 3,3V 8-bit", 0x01, 2048, 128, 0x4000, NAND_IS_AND | NAND_NO_AUTOINCR | NAND_4PAGE_ARRAY}, + + {NULL,} +}; + +/* +* Manufacturer ID list +*/ +struct nand_manufacturers nand_manuf_ids[] = { + {NAND_MFR_TOSHIBA, "Toshiba"}, + {NAND_MFR_SAMSUNG, "Samsung"}, + {NAND_MFR_FUJITSU, "Fujitsu"}, + {NAND_MFR_NATIONAL, "National"}, + {NAND_MFR_RENESAS, "Renesas"}, + {NAND_MFR_STMICRO, "ST Micro"}, + {0x0, "Unknown"} +}; +#endif diff --git a/drivers/nand_legacy/Makefile b/drivers/nand_legacy/Makefile new file mode 100644 index 0000000..7e2cf66 --- /dev/null +++ b/drivers/nand_legacy/Makefile @@ -0,0 +1,16 @@ +include $(TOPDIR)/config.mk + +LIB := libnand_legacy.a + +OBJS := nand_legacy.o +all: $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend diff --git a/drivers/nand_legacy/nand_legacy.c b/drivers/nand_legacy/nand_legacy.c new file mode 100644 index 0000000..3989ca2 --- /dev/null +++ b/drivers/nand_legacy/nand_legacy.c @@ -0,0 +1,1615 @@ +/* + * (C) 2006 Denx + * Driver for NAND support, Rick Bronson + * borrowed heavily from: + * (c) 1999 Machine Vision Holdings, Inc. + * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org> + * + * Added 16-bit nand support + * (C) 2004 Texas Instruments + */ + +#include <common.h> + +#ifndef CFG_NAND_LEGACY +#error CFG_NAND_LEGACY not defined in a file using the legacy NAND support! +#endif + +#include <command.h> +#include <malloc.h> +#include <asm/io.h> +#include <watchdog.h> + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include <status_led.h> +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <linux/mtd/nand_legacy.h> +#include <linux/mtd/nand_ids.h> +#include <jffs2/jffs2.h> + +#ifdef CONFIG_OMAP1510 +void archflashwp(void *archdata, int wp); +#endif + +#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) + +#undef PSYCHO_DEBUG +#undef NAND_DEBUG + +/* ****************** WARNING ********************* + * When ALLOW_ERASE_BAD_DEBUG is non-zero the erase command will + * erase (or at least attempt to erase) blocks that are marked + * bad. This can be very handy if you are _sure_ that the block + * is OK, say because you marked a good block bad to test bad + * block handling and you are done testing, or if you have + * accidentally marked blocks bad. + * + * Erasing factory marked bad blocks is a _bad_ idea. If the + * erase succeeds there is no reliable way to find them again, + * and attempting to program or erase bad blocks can affect + * the data in _other_ (good) blocks. + */ +#define ALLOW_ERASE_BAD_DEBUG 0 + +#define CONFIG_MTD_NAND_ECC /* enable ECC */ +#define CONFIG_MTD_NAND_ECC_JFFS2 + +/* bits for nand_legacy_rw() `cmd'; or together as needed */ +#define NANDRW_READ 0x01 +#define NANDRW_WRITE 0x00 +#define NANDRW_JFFS2 0x02 +#define NANDRW_JFFS2_SKIP 0x04 + + +/* + * Exported variables etc. + */ + +/* Definition of the out of band configuration structure */ +struct nand_oob_config { + /* position of ECC bytes inside oob */ + int ecc_pos[6]; + /* position of bad blk flag inside oob -1 = inactive */ + int badblock_pos; + /* position of ECC valid flag inside oob -1 = inactive */ + int eccvalid_pos; +} oob_config = { {0}, 0, 0}; + +struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}}; + +int curr_device = -1; /* Current NAND Device */ + + +/* + * Exported functionss + */ +int nand_legacy_erase(struct nand_chip* nand, size_t ofs, + size_t len, int clean); +int nand_legacy_rw(struct nand_chip* nand, int cmd, + size_t start, size_t len, + size_t * retlen, u_char * buf); +void nand_print(struct nand_chip *nand); +void nand_print_bad(struct nand_chip *nand); +int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len, + size_t * retlen, u_char * buf); +int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len, + size_t * retlen, const u_char * buf); + +/* + * Internals + */ +static int NanD_WaitReady(struct nand_chip *nand, int ale_wait); +static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len, + size_t * retlen, u_char *buf, u_char *ecc_code); +static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len, + size_t * retlen, const u_char * buf, + u_char * ecc_code); +#ifdef CONFIG_MTD_NAND_ECC +static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc); +static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code); +#endif + + +/* + * + * Function definitions + * + */ + +/* returns 0 if block containing pos is OK: + * valid erase block and + * not marked bad, or no bad mark position is specified + * returns 1 if marked bad or otherwise invalid + */ +static int check_block (struct nand_chip *nand, unsigned long pos) +{ + size_t retlen; + uint8_t oob_data; + uint16_t oob_data16[6]; + int page0 = pos & (-nand->erasesize); + int page1 = page0 + nand->oobblock; + int badpos = oob_config.badblock_pos; + + if (pos >= nand->totlen) + return 1; + + if (badpos < 0) + return 0; /* no way to check, assume OK */ + + if (nand->bus16) { + if (nand_read_oob(nand, (page0 + 0), 12, &retlen, (uint8_t *)oob_data16) + || (oob_data16[2] & 0xff00) != 0xff00) + return 1; + if (nand_read_oob(nand, (page1 + 0), 12, &retlen, (uint8_t *)oob_data16) + || (oob_data16[2] & 0xff00) != 0xff00) + return 1; + } else { + /* Note - bad block marker can be on first or second page */ + if (nand_read_oob(nand, page0 + badpos, 1, &retlen, (unsigned char *)&oob_data) + || oob_data != 0xff + || nand_read_oob (nand, page1 + badpos, 1, &retlen, (unsigned char *)&oob_data) + || oob_data != 0xff) + return 1; + } + + return 0; +} + +/* print bad blocks in NAND flash */ +void nand_print_bad(struct nand_chip* nand) +{ + unsigned long pos; + + for (pos = 0; pos < nand->totlen; pos += nand->erasesize) { + if (check_block(nand, pos)) + printf(" 0x%8.8lx\n", pos); + } + puts("\n"); +} + +/* cmd: 0: NANDRW_WRITE write, fail on bad block + * 1: NANDRW_READ read, fail on bad block + * 2: NANDRW_WRITE | NANDRW_JFFS2 write, skip bad blocks + * 3: NANDRW_READ | NANDRW_JFFS2 read, data all 0xff for bad blocks + * 7: NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP read, skip bad blocks + */ +int nand_legacy_rw (struct nand_chip* nand, int cmd, + size_t start, size_t len, + size_t * retlen, u_char * buf) +{ + int ret = 0, n, total = 0; + char eccbuf[6]; + /* eblk (once set) is the start of the erase block containing the + * data being processed. + */ + unsigned long eblk = ~0; /* force mismatch on first pass */ + unsigned long erasesize = nand->erasesize; + + while (len) { + if ((start & (-erasesize)) != eblk) { + /* have crossed into new erase block, deal with + * it if it is sure marked bad. + */ + eblk = start & (-erasesize); /* start of block */ + if (check_block(nand, eblk)) { + if (cmd == (NANDRW_READ | NANDRW_JFFS2)) { + while (len > 0 && + start - eblk < erasesize) { + *(buf++) = 0xff; + ++start; + ++total; + --len; + } + continue; + } else if (cmd == (NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP)) { + start += erasesize; + continue; + } else if (cmd == (NANDRW_WRITE | NANDRW_JFFS2)) { + /* skip bad block */ + start += erasesize; + continue; + } else { + ret = 1; + break; + } + } + } + /* The ECC will not be calculated correctly if + less than 512 is written or read */ + /* Is request at least 512 bytes AND it starts on a proper boundry */ + if((start != ROUND_DOWN(start, 0x200)) || (len < 0x200)) + printf("Warning block writes should be at least 512 bytes and start on a 512 byte boundry\n"); + + if (cmd & NANDRW_READ) { + ret = nand_read_ecc(nand, start, + min(len, eblk + erasesize - start), + (size_t *)&n, (u_char*)buf, (u_char *)eccbuf); + } else { + ret = nand_write_ecc(nand, start, + min(len, eblk + erasesize - start), + (size_t *)&n, (u_char*)buf, (u_char *)eccbuf); + } + + if (ret) + break; + + start += n; + buf += n; + total += n; + len -= n; + } + if (retlen) + *retlen = total; + + return ret; +} + +void nand_print(struct nand_chip *nand) +{ + if (nand->numchips > 1) { + printf("%s at 0x%lx,\n" + "\t %d chips %s, size %d MB, \n" + "\t total size %ld MB, sector size %ld kB\n", + nand->name, nand->IO_ADDR, nand->numchips, + nand->chips_name, 1 << (nand->chipshift - 20), + nand->totlen >> 20, nand->erasesize >> 10); + } + else { + printf("%s at 0x%lx (", nand->chips_name, nand->IO_ADDR); + print_size(nand->totlen, ", "); + print_size(nand->erasesize, " sector)\n"); + } +} + +/* ------------------------------------------------------------------------- */ + +static int NanD_WaitReady(struct nand_chip *nand, int ale_wait) +{ + /* This is inline, to optimise the common case, where it's ready instantly */ + int ret = 0; + +#ifdef NAND_NO_RB /* in config file, shorter delays currently wrap accesses */ + if(ale_wait) + NAND_WAIT_READY(nand); /* do the worst case 25us wait */ + else + udelay(10); +#else /* has functional r/b signal */ + NAND_WAIT_READY(nand); +#endif + return ret; +} + +/* NanD_Command: Send a flash command to the flash chip */ + +static inline int NanD_Command(struct nand_chip *nand, unsigned char command) +{ + unsigned long nandptr = nand->IO_ADDR; + + /* Assert the CLE (Command Latch Enable) line to the flash chip */ + NAND_CTL_SETCLE(nandptr); + + /* Send the command */ + WRITE_NAND_COMMAND(command, nandptr); + + /* Lower the CLE line */ + NAND_CTL_CLRCLE(nandptr); + +#ifdef NAND_NO_RB + if(command == NAND_CMD_RESET){ + u_char ret_val; + NanD_Command(nand, NAND_CMD_STATUS); + do { + ret_val = READ_NAND(nandptr);/* wait till ready */ + } while((ret_val & 0x40) != 0x40); + } +#endif + return NanD_WaitReady(nand, 0); +} + +/* NanD_Address: Set the current address for the flash chip */ + +static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs) +{ + unsigned long nandptr; + int i; + + nandptr = nand->IO_ADDR; + + /* Assert the ALE (Address Latch Enable) line to the flash chip */ + NAND_CTL_SETALE(nandptr); + + /* Send the address */ + /* Devices with 256-byte page are addressed as: + * Column (bits 0-7), Page (bits 8-15, 16-23, 24-31) + * there is no device on the market with page256 + * and more than 24 bits. + * Devices with 512-byte page are addressed as: + * Column (bits 0-7), Page (bits 9-16, 17-24, 25-31) + * 25-31 is sent only if the chip support it. + * bit 8 changes the read command to be sent + * (NAND_CMD_READ0 or NAND_CMD_READ1). + */ + + if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE) + WRITE_NAND_ADDRESS(ofs, nandptr); + + ofs = ofs >> nand->page_shift; + + if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) { + for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8) { + WRITE_NAND_ADDRESS(ofs, nandptr); + } + } + + /* Lower the ALE line */ + NAND_CTL_CLRALE(nandptr); + + /* Wait for the chip to respond */ + return NanD_WaitReady(nand, 1); +} + +/* NanD_SelectChip: Select a given flash chip within the current floor */ + +static inline int NanD_SelectChip(struct nand_chip *nand, int chip) +{ + /* Wait for it to be ready */ + return NanD_WaitReady(nand, 0); +} + +/* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */ + +static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip) +{ + int mfr, id, i; + + NAND_ENABLE_CE(nand); /* set pin low */ + /* Reset the chip */ + if (NanD_Command(nand, NAND_CMD_RESET)) { +#ifdef NAND_DEBUG + printf("NanD_Command (reset) for %d,%d returned true\n", + floor, chip); +#endif + NAND_DISABLE_CE(nand); /* set pin high */ + return 0; + } + + /* Read the NAND chip ID: 1. Send ReadID command */ + if (NanD_Command(nand, NAND_CMD_READID)) { +#ifdef NAND_DEBUG + printf("NanD_Command (ReadID) for %d,%d returned true\n", + floor, chip); +#endif + NAND_DISABLE_CE(nand); /* set pin high */ + return 0; + } + + /* Read the NAND chip ID: 2. Send address byte zero */ + NanD_Address(nand, ADDR_COLUMN, 0); + + /* Read the manufacturer and device id codes from the device */ + + mfr = READ_NAND(nand->IO_ADDR); + + id = READ_NAND(nand->IO_ADDR); + + NAND_DISABLE_CE(nand); /* set pin high */ + +#ifdef NAND_DEBUG + printf("NanD_Command (ReadID) got %x %x\n", mfr, id); +#endif + if (mfr == 0xff || mfr == 0) { + /* No response - return failure */ + return 0; + } + + /* Check it's the same as the first chip we identified. + * M-Systems say that any given nand_chip device should only + * contain _one_ type of flash part, although that's not a + * hardware restriction. */ + if (nand->mfr) { + if (nand->mfr == mfr && nand->id == id) { + return 1; /* This is another the same the first */ + } else { + printf("Flash chip at floor %d, chip %d is different:\n", + floor, chip); + } + } + + /* Print and store the manufacturer and ID codes. */ + for (i = 0; nand_flash_ids[i].name != NULL; i++) { + if (mfr == nand_flash_ids[i].manufacture_id && + id == nand_flash_ids[i].model_id) { +#ifdef NAND_DEBUG + printf("Flash chip found:\n\t Manufacturer ID: 0x%2.2X, " + "Chip ID: 0x%2.2X (%s)\n", mfr, id, + nand_flash_ids[i].name); +#endif + if (!nand->mfr) { + nand->mfr = mfr; + nand->id = id; + nand->chipshift = + nand_flash_ids[i].chipshift; + nand->page256 = nand_flash_ids[i].page256; + nand->eccsize = 256; + if (nand->page256) { + nand->oobblock = 256; + nand->oobsize = 8; + nand->page_shift = 8; + } else { + nand->oobblock = 512; + nand->oobsize = 16; + nand->page_shift = 9; + } + nand->pageadrlen = nand_flash_ids[i].pageadrlen; + nand->erasesize = nand_flash_ids[i].erasesize; + nand->chips_name = nand_flash_ids[i].name; + nand->bus16 = nand_flash_ids[i].bus16; + return 1; + } + return 0; + } + } + + +#ifdef NAND_DEBUG + /* We haven't fully identified the chip. Print as much as we know. */ + printf("Unknown flash chip found: %2.2X %2.2X\n", + id, mfr); +#endif + + return 0; +} + +/* NanD_ScanChips: Find all NAND chips present in a nand_chip, and identify them */ + +static void NanD_ScanChips(struct nand_chip *nand) +{ + int floor, chip; + int numchips[NAND_MAX_FLOORS]; + int maxchips = NAND_MAX_CHIPS; + int ret = 1; + + nand->numchips = 0; + nand->mfr = 0; + nand->id = 0; + + + /* For each floor, find the number of valid chips it contains */ + for (floor = 0; floor < NAND_MAX_FLOORS; floor++) { + ret = 1; + numchips[floor] = 0; + for (chip = 0; chip < maxchips && ret != 0; chip++) { + + ret = NanD_IdentChip(nand, floor, chip); + if (ret) { + numchips[floor]++; + nand->numchips++; + } + } + } + + /* If there are none at all that we recognise, bail */ + if (!nand->numchips) { +#ifdef NAND_DEBUG + puts ("No NAND flash chips recognised.\n"); +#endif + return; + } + + /* Allocate an array to hold the information for each chip */ + nand->chips = malloc(sizeof(struct Nand) * nand->numchips); + if (!nand->chips) { + puts ("No memory for allocating chip info structures\n"); + return; + } + + ret = 0; + + /* Fill out the chip array with {floor, chipno} for each + * detected chip in the device. */ + for (floor = 0; floor < NAND_MAX_FLOORS; floor++) { + for (chip = 0; chip < numchips[floor]; chip++) { + nand->chips[ret].floor = floor; + nand->chips[ret].chip = chip; + nand->chips[ret].curadr = 0; + nand->chips[ret].curmode = 0x50; + ret++; + } + } + + /* Calculate and print the total size of the device */ + nand->totlen = nand->numchips * (1 << nand->chipshift); + +#ifdef NAND_DEBUG + printf("%d flash chips found. Total nand_chip size: %ld MB\n", + nand->numchips, nand->totlen >> 20); +#endif +} + +/* we need to be fast here, 1 us per read translates to 1 second per meg */ +static void NanD_ReadBuf (struct nand_chip *nand, u_char * data_buf, int cntr) +{ + unsigned long nandptr = nand->IO_ADDR; + + NanD_Command (nand, NAND_CMD_READ0); + + if (nand->bus16) { + u16 val; + + while (cntr >= 16) { + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + cntr -= 16; + } + + while (cntr > 0) { + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + cntr -= 2; + } + } else { + while (cntr >= 16) { + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + cntr -= 16; + } + + while (cntr > 0) { + *data_buf++ = READ_NAND (nandptr); + cntr--; + } + } +} + +/* + * NAND read with ECC + */ +static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len, + size_t * retlen, u_char *buf, u_char *ecc_code) +{ + int col, page; + int ecc_status = 0; +#ifdef CONFIG_MTD_NAND_ECC + int j; + int ecc_failed = 0; + u_char *data_poi; + u_char ecc_calc[6]; +#endif + + /* Do not allow reads past end of device */ + if ((start + len) > nand->totlen) { + printf ("%s: Attempt read beyond end of device %x %x %x\n", + __FUNCTION__, (uint) start, (uint) len, (uint) nand->totlen); + *retlen = 0; + return -1; + } + + /* First we calculate the starting page */ + /*page = shr(start, nand->page_shift);*/ + page = start >> nand->page_shift; + + /* Get raw starting column */ + col = start & (nand->oobblock - 1); + + /* Initialize return value */ + *retlen = 0; + + /* Select the NAND device */ + NAND_ENABLE_CE(nand); /* set pin low */ + + /* Loop until all data read */ + while (*retlen < len) { + +#ifdef CONFIG_MTD_NAND_ECC + /* Do we have this page in cache ? */ + if (nand->cache_page == page) + goto readdata; + /* Send the read command */ + NanD_Command(nand, NAND_CMD_READ0); + if (nand->bus16) { + NanD_Address(nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + (col >> 1)); + } else { + NanD_Address(nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + col); + } + + /* Read in a page + oob data */ + NanD_ReadBuf(nand, nand->data_buf, nand->oobblock + nand->oobsize); + + /* copy data into cache, for read out of cache and if ecc fails */ + if (nand->data_cache) { + memcpy (nand->data_cache, nand->data_buf, + nand->oobblock + nand->oobsize); + } + + /* Pick the ECC bytes out of the oob data */ + for (j = 0; j < 6; j++) { + ecc_code[j] = nand->data_buf[(nand->oobblock + oob_config.ecc_pos[j])]; + } + + /* Calculate the ECC and verify it */ + /* If block was not written with ECC, skip ECC */ + if (oob_config.eccvalid_pos != -1 && + (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0x0f) != 0x0f) { + + nand_calculate_ecc (&nand->data_buf[0], &ecc_calc[0]); + switch (nand_correct_data (&nand->data_buf[0], &ecc_code[0], &ecc_calc[0])) { + case -1: + printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page); + ecc_failed++; + break; + case 1: + case 2: /* transfer ECC corrected data to cache */ + if (nand->data_cache) + memcpy (nand->data_cache, nand->data_buf, 256); + break; + } + } + + if (oob_config.eccvalid_pos != -1 && + nand->oobblock == 512 && (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0xf0) != 0xf0) { + + nand_calculate_ecc (&nand->data_buf[256], &ecc_calc[3]); + switch (nand_correct_data (&nand->data_buf[256], &ecc_code[3], &ecc_calc[3])) { + case -1: + printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page); + ecc_failed++; + break; + case 1: + case 2: /* transfer ECC corrected data to cache */ + if (nand->data_cache) + memcpy (&nand->data_cache[256], &nand->data_buf[256], 256); + break; + } + } +readdata: + /* Read the data from ECC data buffer into return buffer */ + data_poi = (nand->data_cache) ? nand->data_cache : nand->data_buf; + data_poi += col; + if ((*retlen + (nand->oobblock - col)) >= len) { + memcpy (buf + *retlen, data_poi, len - *retlen); + *retlen = len; + } else { + memcpy (buf + *retlen, data_poi, nand->oobblock - col); + *retlen += nand->oobblock - col; + } + /* Set cache page address, invalidate, if ecc_failed */ + nand->cache_page = (nand->data_cache && !ecc_failed) ? page : -1; + + ecc_status += ecc_failed; + ecc_failed = 0; + +#else + /* Send the read command */ + NanD_Command(nand, NAND_CMD_READ0); + if (nand->bus16) { + NanD_Address(nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + (col >> 1)); + } else { + NanD_Address(nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + col); + } + + /* Read the data directly into the return buffer */ + if ((*retlen + (nand->oobblock - col)) >= len) { + NanD_ReadBuf(nand, buf + *retlen, len - *retlen); + *retlen = len; + /* We're done */ + continue; + } else { + NanD_ReadBuf(nand, buf + *retlen, nand->oobblock - col); + *retlen += nand->oobblock - col; + } +#endif + /* For subsequent reads align to page boundary. */ + col = 0; + /* Increment page address */ + page++; + } + + /* De-select the NAND device */ + NAND_DISABLE_CE(nand); /* set pin high */ + + /* + * Return success, if no ECC failures, else -EIO + * fs driver will take care of that, because + * retlen == desired len and result == -EIO + */ + return ecc_status ? -1 : 0; +} + +/* + * Nand_page_program function is used for write and writev ! + */ +static int nand_write_page (struct nand_chip *nand, + int page, int col, int last, u_char * ecc_code) +{ + + int i; + unsigned long nandptr = nand->IO_ADDR; + +#ifdef CONFIG_MTD_NAND_ECC +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE + int ecc_bytes = (nand->oobblock == 512) ? 6 : 3; +#endif +#endif + /* pad oob area */ + for (i = nand->oobblock; i < nand->oobblock + nand->oobsize; i++) + nand->data_buf[i] = 0xff; + +#ifdef CONFIG_MTD_NAND_ECC + /* Zero out the ECC array */ + for (i = 0; i < 6; i++) + ecc_code[i] = 0x00; + + /* Read back previous written data, if col > 0 */ + if (col) { + NanD_Command (nand, NAND_CMD_READ0); + if (nand->bus16) { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + (col >> 1)); + } else { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + col); + } + + if (nand->bus16) { + u16 val; + + for (i = 0; i < col; i += 2) { + val = READ_NAND (nandptr); + nand->data_buf[i] = val & 0xff; + nand->data_buf[i + 1] = val >> 8; + } + } else { + for (i = 0; i < col; i++) + nand->data_buf[i] = READ_NAND (nandptr); + } + } + + /* Calculate and write the ECC if we have enough data */ + if ((col < nand->eccsize) && (last >= nand->eccsize)) { + nand_calculate_ecc (&nand->data_buf[0], &(ecc_code[0])); + for (i = 0; i < 3; i++) { + nand->data_buf[(nand->oobblock + + oob_config.ecc_pos[i])] = ecc_code[i]; + } + if (oob_config.eccvalid_pos != -1) { + nand->data_buf[nand->oobblock + + oob_config.eccvalid_pos] = 0xf0; + } + } + + /* Calculate and write the second ECC if we have enough data */ + if ((nand->oobblock == 512) && (last == nand->oobblock)) { + nand_calculate_ecc (&nand->data_buf[256], &(ecc_code[3])); + for (i = 3; i < 6; i++) { + nand->data_buf[(nand->oobblock + + oob_config.ecc_pos[i])] = ecc_code[i]; + } + if (oob_config.eccvalid_pos != -1) { + nand->data_buf[nand->oobblock + + oob_config.eccvalid_pos] &= 0x0f; + } + } +#endif + /* Prepad for partial page programming !!! */ + for (i = 0; i < col; i++) + nand->data_buf[i] = 0xff; + + /* Postpad for partial page programming !!! oob is already padded */ + for (i = last; i < nand->oobblock; i++) + nand->data_buf[i] = 0xff; + + /* Send command to begin auto page programming */ + NanD_Command (nand, NAND_CMD_READ0); + NanD_Command (nand, NAND_CMD_SEQIN); + if (nand->bus16) { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + (col >> 1)); + } else { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + col); + } + + /* Write out complete page of data */ + if (nand->bus16) { + for (i = 0; i < (nand->oobblock + nand->oobsize); i += 2) { + WRITE_NAND (nand->data_buf[i] + + (nand->data_buf[i + 1] << 8), + nand->IO_ADDR); + } + } else { + for (i = 0; i < (nand->oobblock + nand->oobsize); i++) + WRITE_NAND (nand->data_buf[i], nand->IO_ADDR); + } + + /* Send command to actually program the data */ + NanD_Command (nand, NAND_CMD_PAGEPROG); + NanD_Command (nand, NAND_CMD_STATUS); +#ifdef NAND_NO_RB + { + u_char ret_val; + + do { + ret_val = READ_NAND (nandptr); /* wait till ready */ + } while ((ret_val & 0x40) != 0x40); + } +#endif + /* See if device thinks it succeeded */ + if (READ_NAND (nand->IO_ADDR) & 0x01) { + printf ("%s: Failed write, page 0x%08x, ", __FUNCTION__, + page); + return -1; + } +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE + /* + * The NAND device assumes that it is always writing to + * a cleanly erased page. Hence, it performs its internal + * write verification only on bits that transitioned from + * 1 to 0. The device does NOT verify the whole page on a + * byte by byte basis. It is possible that the page was + * not completely erased or the page is becoming unusable + * due to wear. The read with ECC would catch the error + * later when the ECC page check fails, but we would rather + * catch it early in the page write stage. Better to write + * no data than invalid data. + */ + + /* Send command to read back the page */ + if (col < nand->eccsize) + NanD_Command (nand, NAND_CMD_READ0); + else + NanD_Command (nand, NAND_CMD_READ1); + if (nand->bus16) { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + (col >> 1)); + } else { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + col); + } + + /* Loop through and verify the data */ + if (nand->bus16) { + for (i = col; i < last; i = +2) { + if ((nand->data_buf[i] + + (nand->data_buf[i + 1] << 8)) != READ_NAND (nand->IO_ADDR)) { + printf ("%s: Failed write verify, page 0x%08x ", + __FUNCTION__, page); + return -1; + } + } + } else { + for (i = col; i < last; i++) { + if (nand->data_buf[i] != READ_NAND (nand->IO_ADDR)) { + printf ("%s: Failed write verify, page 0x%08x ", + __FUNCTION__, page); + return -1; + } + } + } + +#ifdef CONFIG_MTD_NAND_ECC + /* + * We also want to check that the ECC bytes wrote + * correctly for the same reasons stated above. + */ + NanD_Command (nand, NAND_CMD_READOOB); + if (nand->bus16) { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + (col >> 1)); + } else { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + col); + } + if (nand->bus16) { + for (i = 0; i < nand->oobsize; i += 2) { + u16 val; + + val = READ_NAND (nand->IO_ADDR); + nand->data_buf[i] = val & 0xff; + nand->data_buf[i + 1] = val >> 8; + } + } else { + for (i = 0; i < nand->oobsize; i++) { + nand->data_buf[i] = READ_NAND (nand->IO_ADDR); + } + } + for (i = 0; i < ecc_bytes; i++) { + if ((nand->data_buf[(oob_config.ecc_pos[i])] != ecc_code[i]) && ecc_code[i]) { + printf ("%s: Failed ECC write " + "verify, page 0x%08x, " + "%6i bytes were succesful\n", + __FUNCTION__, page, i); + return -1; + } + } +#endif /* CONFIG_MTD_NAND_ECC */ +#endif /* CONFIG_MTD_NAND_VERIFY_WRITE */ + return 0; +} + +static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len, + size_t * retlen, const u_char * buf, u_char * ecc_code) +{ + int i, page, col, cnt, ret = 0; + + /* Do not allow write past end of device */ + if ((to + len) > nand->totlen) { + printf ("%s: Attempt to write past end of page\n", __FUNCTION__); + return -1; + } + + /* Shift to get page */ + page = ((int) to) >> nand->page_shift; + + /* Get the starting column */ + col = to & (nand->oobblock - 1); + + /* Initialize return length value */ + *retlen = 0; + + /* Select the NAND device */ +#ifdef CONFIG_OMAP1510 + archflashwp(0,0); +#endif +#ifdef CFG_NAND_WP + NAND_WP_OFF(); +#endif + + NAND_ENABLE_CE(nand); /* set pin low */ + + /* Check the WP bit */ + NanD_Command(nand, NAND_CMD_STATUS); + if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { + printf ("%s: Device is write protected!!!\n", __FUNCTION__); + ret = -1; + goto out; + } + + /* Loop until all data is written */ + while (*retlen < len) { + /* Invalidate cache, if we write to this page */ + if (nand->cache_page == page) + nand->cache_page = -1; + + /* Write data into buffer */ + if ((col + len) >= nand->oobblock) { + for (i = col, cnt = 0; i < nand->oobblock; i++, cnt++) { + nand->data_buf[i] = buf[(*retlen + cnt)]; + } + } else { + for (i = col, cnt = 0; cnt < (len - *retlen); i++, cnt++) { + nand->data_buf[i] = buf[(*retlen + cnt)]; + } + } + /* We use the same function for write and writev !) */ + ret = nand_write_page (nand, page, col, i, ecc_code); + if (ret) + goto out; + + /* Next data start at page boundary */ + col = 0; + + /* Update written bytes count */ + *retlen += cnt; + + /* Increment page address */ + page++; + } + + /* Return happy */ + *retlen = len; + +out: + /* De-select the NAND device */ + NAND_DISABLE_CE(nand); /* set pin high */ +#ifdef CONFIG_OMAP1510 + archflashwp(0,1); +#endif +#ifdef CFG_NAND_WP + NAND_WP_ON(); +#endif + + return ret; +} + +/* read from the 16 bytes of oob data that correspond to a 512 byte + * page or 2 256-byte pages. + */ +int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len, + size_t * retlen, u_char * buf) +{ + int len256 = 0; + struct Nand *mychip; + int ret = 0; + + mychip = &nand->chips[ofs >> nand->chipshift]; + + /* update address for 2M x 8bit devices. OOB starts on the second */ + /* page to maintain compatibility with nand_read_ecc. */ + if (nand->page256) { + if (!(ofs & 0x8)) + ofs += 0x100; + else + ofs -= 0x8; + } + + NAND_ENABLE_CE(nand); /* set pin low */ + NanD_Command(nand, NAND_CMD_READOOB); + if (nand->bus16) { + NanD_Address(nand, ADDR_COLUMN_PAGE, + ((ofs >> nand->page_shift) << nand->page_shift) + + ((ofs & (nand->oobblock - 1)) >> 1)); + } else { + NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); + } + + /* treat crossing 8-byte OOB data for 2M x 8bit devices */ + /* Note: datasheet says it should automaticaly wrap to the */ + /* next OOB block, but it didn't work here. mf. */ + if (nand->page256 && ofs + len > (ofs | 0x7) + 1) { + len256 = (ofs | 0x7) + 1 - ofs; + NanD_ReadBuf(nand, buf, len256); + + NanD_Command(nand, NAND_CMD_READOOB); + NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff)); + } + + NanD_ReadBuf(nand, &buf[len256], len - len256); + + *retlen = len; + /* Reading the full OOB data drops us off of the end of the page, + * causing the flash device to go into busy mode, so we need + * to wait until ready 11.4.1 and Toshiba TC58256FT nands */ + + ret = NanD_WaitReady(nand, 1); + NAND_DISABLE_CE(nand); /* set pin high */ + + return ret; + +} + +/* write to the 16 bytes of oob data that correspond to a 512 byte + * page or 2 256-byte pages. + */ +int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len, + size_t * retlen, const u_char * buf) +{ + int len256 = 0; + int i; + unsigned long nandptr = nand->IO_ADDR; + +#ifdef PSYCHO_DEBUG + printf("nand_write_oob(%lx, %d): %2.2X %2.2X %2.2X %2.2X ... %2.2X %2.2X .. %2.2X %2.2X\n", + (long)ofs, len, buf[0], buf[1], buf[2], buf[3], + buf[8], buf[9], buf[14],buf[15]); +#endif + + NAND_ENABLE_CE(nand); /* set pin low to enable chip */ + + /* Reset the chip */ + NanD_Command(nand, NAND_CMD_RESET); + + /* issue the Read2 command to set the pointer to the Spare Data Area. */ + NanD_Command(nand, NAND_CMD_READOOB); + if (nand->bus16) { + NanD_Address(nand, ADDR_COLUMN_PAGE, + ((ofs >> nand->page_shift) << nand->page_shift) + + ((ofs & (nand->oobblock - 1)) >> 1)); + } else { + NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); + } + + /* update address for 2M x 8bit devices. OOB starts on the second */ + /* page to maintain compatibility with nand_read_ecc. */ + if (nand->page256) { + if (!(ofs & 0x8)) + ofs += 0x100; + else + ofs -= 0x8; + } + + /* issue the Serial Data In command to initial the Page Program process */ + NanD_Command(nand, NAND_CMD_SEQIN); + if (nand->bus16) { + NanD_Address(nand, ADDR_COLUMN_PAGE, + ((ofs >> nand->page_shift) << nand->page_shift) + + ((ofs & (nand->oobblock - 1)) >> 1)); + } else { + NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); + } + + /* treat crossing 8-byte OOB data for 2M x 8bit devices */ + /* Note: datasheet says it should automaticaly wrap to the */ + /* next OOB block, but it didn't work here. mf. */ + if (nand->page256 && ofs + len > (ofs | 0x7) + 1) { + len256 = (ofs | 0x7) + 1 - ofs; + for (i = 0; i < len256; i++) + WRITE_NAND(buf[i], nandptr); + + NanD_Command(nand, NAND_CMD_PAGEPROG); + NanD_Command(nand, NAND_CMD_STATUS); +#ifdef NAND_NO_RB + { u_char ret_val; + do { + ret_val = READ_NAND(nandptr); /* wait till ready */ + } while ((ret_val & 0x40) != 0x40); + } +#endif + if (READ_NAND(nandptr) & 1) { + puts ("Error programming oob data\n"); + /* There was an error */ + NAND_DISABLE_CE(nand); /* set pin high */ + *retlen = 0; + return -1; + } + NanD_Command(nand, NAND_CMD_SEQIN); + NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff)); + } + + if (nand->bus16) { + for (i = len256; i < len; i += 2) { + WRITE_NAND(buf[i] + (buf[i+1] << 8), nandptr); + } + } else { + for (i = len256; i < len; i++) + WRITE_NAND(buf[i], nandptr); + } + + NanD_Command(nand, NAND_CMD_PAGEPROG); + NanD_Command(nand, NAND_CMD_STATUS); +#ifdef NAND_NO_RB + { u_char ret_val; + do { + ret_val = READ_NAND(nandptr); /* wait till ready */ + } while ((ret_val & 0x40) != 0x40); + } +#endif + if (READ_NAND(nandptr) & 1) { + puts ("Error programming oob data\n"); + /* There was an error */ + NAND_DISABLE_CE(nand); /* set pin high */ + *retlen = 0; + return -1; + } + + NAND_DISABLE_CE(nand); /* set pin high */ + *retlen = len; + return 0; + +} + +int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean) +{ + /* This is defined as a structure so it will work on any system + * using native endian jffs2 (the default). + */ + static struct jffs2_unknown_node clean_marker = { + JFFS2_MAGIC_BITMASK, + JFFS2_NODETYPE_CLEANMARKER, + 8 /* 8 bytes in this node */ + }; + unsigned long nandptr; + struct Nand *mychip; + int ret = 0; + + if (ofs & (nand->erasesize-1) || len & (nand->erasesize-1)) { + printf ("Offset and size must be sector aligned, erasesize = %d\n", + (int) nand->erasesize); + return -1; + } + + nandptr = nand->IO_ADDR; + + /* Select the NAND device */ +#ifdef CONFIG_OMAP1510 + archflashwp(0,0); +#endif +#ifdef CFG_NAND_WP + NAND_WP_OFF(); +#endif + NAND_ENABLE_CE(nand); /* set pin low */ + + /* Check the WP bit */ + NanD_Command(nand, NAND_CMD_STATUS); + if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { + printf ("nand_write_ecc: Device is write protected!!!\n"); + ret = -1; + goto out; + } + + /* Check the WP bit */ + NanD_Command(nand, NAND_CMD_STATUS); + if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { + printf ("%s: Device is write protected!!!\n", __FUNCTION__); + ret = -1; + goto out; + } + + /* FIXME: Do nand in the background. Use timers or schedule_task() */ + while(len) { + /*mychip = &nand->chips[shr(ofs, nand->chipshift)];*/ + mychip = &nand->chips[ofs >> nand->chipshift]; + + /* always check for bad block first, genuine bad blocks + * should _never_ be erased. + */ + if (ALLOW_ERASE_BAD_DEBUG || !check_block(nand, ofs)) { + /* Select the NAND device */ + NAND_ENABLE_CE(nand); /* set pin low */ + + NanD_Command(nand, NAND_CMD_ERASE1); + NanD_Address(nand, ADDR_PAGE, ofs); + NanD_Command(nand, NAND_CMD_ERASE2); + + NanD_Command(nand, NAND_CMD_STATUS); + +#ifdef NAND_NO_RB + { u_char ret_val; + do { + ret_val = READ_NAND(nandptr); /* wait till ready */ + } while ((ret_val & 0x40) != 0x40); + } +#endif + if (READ_NAND(nandptr) & 1) { + printf ("%s: Error erasing at 0x%lx\n", + __FUNCTION__, (long)ofs); + /* There was an error */ + ret = -1; + goto out; + } + if (clean) { + int n; /* return value not used */ + int p, l; + + /* clean marker position and size depend + * on the page size, since 256 byte pages + * only have 8 bytes of oob data + */ + if (nand->page256) { + p = NAND_JFFS2_OOB8_FSDAPOS; + l = NAND_JFFS2_OOB8_FSDALEN; + } else { + p = NAND_JFFS2_OOB16_FSDAPOS; + l = NAND_JFFS2_OOB16_FSDALEN; + } + + ret = nand_write_oob(nand, ofs + p, l, (size_t *)&n, + (u_char *)&clean_marker); + /* quit here if write failed */ + if (ret) + goto out; + } + } + ofs += nand->erasesize; + len -= nand->erasesize; + } + +out: + /* De-select the NAND device */ + NAND_DISABLE_CE(nand); /* set pin high */ +#ifdef CONFIG_OMAP1510 + archflashwp(0,1); +#endif +#ifdef CFG_NAND_WP + NAND_WP_ON(); +#endif + + return ret; +} + + +static inline int nandcheck(unsigned long potential, unsigned long physadr) +{ + return 0; +} + +unsigned long nand_probe(unsigned long physadr) +{ + struct nand_chip *nand = NULL; + int i = 0, ChipID = 1; + +#ifdef CONFIG_MTD_NAND_ECC_JFFS2 + oob_config.ecc_pos[0] = NAND_JFFS2_OOB_ECCPOS0; + oob_config.ecc_pos[1] = NAND_JFFS2_OOB_ECCPOS1; + oob_config.ecc_pos[2] = NAND_JFFS2_OOB_ECCPOS2; + oob_config.ecc_pos[3] = NAND_JFFS2_OOB_ECCPOS3; + oob_config.ecc_pos[4] = NAND_JFFS2_OOB_ECCPOS4; + oob_config.ecc_pos[5] = NAND_JFFS2_OOB_ECCPOS5; + oob_config.eccvalid_pos = 4; +#else + oob_config.ecc_pos[0] = NAND_NOOB_ECCPOS0; + oob_config.ecc_pos[1] = NAND_NOOB_ECCPOS1; + oob_config.ecc_pos[2] = NAND_NOOB_ECCPOS2; + oob_config.ecc_pos[3] = NAND_NOOB_ECCPOS3; + oob_config.ecc_pos[4] = NAND_NOOB_ECCPOS4; + oob_config.ecc_pos[5] = NAND_NOOB_ECCPOS5; + oob_config.eccvalid_pos = NAND_NOOB_ECCVPOS; +#endif + oob_config.badblock_pos = 5; + + for (i=0; i<CFG_MAX_NAND_DEVICE; i++) { + if (nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN) { + nand = &nand_dev_desc[i]; + break; + } + } + if (!nand) + return (0); + + memset((char *)nand, 0, sizeof(struct nand_chip)); + + nand->IO_ADDR = physadr; + nand->cache_page = -1; /* init the cache page */ + NanD_ScanChips(nand); + + if (nand->totlen == 0) { + /* no chips found, clean up and quit */ + memset((char *)nand, 0, sizeof(struct nand_chip)); + nand->ChipID = NAND_ChipID_UNKNOWN; + return (0); + } + + nand->ChipID = ChipID; + if (curr_device == -1) + curr_device = i; + + nand->data_buf = malloc (nand->oobblock + nand->oobsize); + if (!nand->data_buf) { + puts ("Cannot allocate memory for data structures.\n"); + return (0); + } + + return (nand->totlen); +} + +#ifdef CONFIG_MTD_NAND_ECC +/* + * Pre-calculated 256-way 1 byte column parity + */ +static const u_char nand_ecc_precalc_table[] = { + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, + 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, + 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, + 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, + 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, + 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, + 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, + 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, + 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, + 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, + 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, + 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, + 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, + 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, + 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, + 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, + 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00 +}; + + +/* + * Creates non-inverted ECC code from line parity + */ +static void nand_trans_result(u_char reg2, u_char reg3, + u_char *ecc_code) +{ + u_char a, b, i, tmp1, tmp2; + + /* Initialize variables */ + a = b = 0x80; + tmp1 = tmp2 = 0; + + /* Calculate first ECC byte */ + for (i = 0; i < 4; i++) { + if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */ + tmp1 |= b; + b >>= 1; + if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */ + tmp1 |= b; + b >>= 1; + a >>= 1; + } + + /* Calculate second ECC byte */ + b = 0x80; + for (i = 0; i < 4; i++) { + if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */ + tmp2 |= b; + b >>= 1; + if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */ + tmp2 |= b; + b >>= 1; + a >>= 1; + } + + /* Store two of the ECC bytes */ + ecc_code[0] = tmp1; + ecc_code[1] = tmp2; +} + +/* + * Calculate 3 byte ECC code for 256 byte block + */ +static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code) +{ + u_char idx, reg1, reg3; + int j; + + /* Initialize variables */ + reg1 = reg3 = 0; + ecc_code[0] = ecc_code[1] = ecc_code[2] = 0; + + /* Build up column parity */ + for(j = 0; j < 256; j++) { + + /* Get CP0 - CP5 from table */ + idx = nand_ecc_precalc_table[dat[j]]; + reg1 ^= idx; + + /* All bit XOR = 1 ? */ + if (idx & 0x40) { + reg3 ^= (u_char) j; + } + } + + /* Create non-inverted ECC code from line parity */ + nand_trans_result((reg1 & 0x40) ? ~reg3 : reg3, reg3, ecc_code); + + /* Calculate final ECC code */ + ecc_code[0] = ~ecc_code[0]; + ecc_code[1] = ~ecc_code[1]; + ecc_code[2] = ((~reg1) << 2) | 0x03; +} + +/* + * Detect and correct a 1 bit error for 256 byte block + */ +static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc) +{ + u_char a, b, c, d1, d2, d3, add, bit, i; + + /* Do error detection */ + d1 = calc_ecc[0] ^ read_ecc[0]; + d2 = calc_ecc[1] ^ read_ecc[1]; + d3 = calc_ecc[2] ^ read_ecc[2]; + + if ((d1 | d2 | d3) == 0) { + /* No errors */ + return 0; + } else { + a = (d1 ^ (d1 >> 1)) & 0x55; + b = (d2 ^ (d2 >> 1)) & 0x55; + c = (d3 ^ (d3 >> 1)) & 0x54; + + /* Found and will correct single bit error in the data */ + if ((a == 0x55) && (b == 0x55) && (c == 0x54)) { + c = 0x80; + add = 0; + a = 0x80; + for (i=0; i<4; i++) { + if (d1 & c) + add |= a; + c >>= 2; + a >>= 1; + } + c = 0x80; + for (i=0; i<4; i++) { + if (d2 & c) + add |= a; + c >>= 2; + a >>= 1; + } + bit = 0; + b = 0x04; + c = 0x80; + for (i=0; i<3; i++) { + if (d3 & c) + bit |= b; + c >>= 2; + b >>= 1; + } + b = 0x01; + a = dat[add]; + a ^= (b << bit); + dat[add] = a; + return 1; + } + else { + i = 0; + while (d1) { + if (d1 & 0x01) + ++i; + d1 >>= 1; + } + while (d2) { + if (d2 & 0x01) + ++i; + d2 >>= 1; + } + while (d3) { + if (d3 & 0x01) + ++i; + d3 >>= 1; + } + if (i == 1) { + /* ECC Code Error Correction */ + read_ecc[0] = calc_ecc[0]; + read_ecc[1] = calc_ecc[1]; + read_ecc[2] = calc_ecc[2]; + return 2; + } + else { + /* Uncorrectable Error */ + return -1; + } + } + } + + /* Should never happen */ + return -1; +} + +#endif + +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ diff --git a/drivers/pci.c b/drivers/pci.c index 5360030..3c24b99 100644 --- a/drivers/pci.c +++ b/drivers/pci.c @@ -459,6 +459,7 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus) PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); if (cfg) { cfg->config_device(hose, dev, cfg); + sub_bus = max(sub_bus, hose->current_busno); #ifdef CONFIG_PCI_PNP } else { int n = pciauto_config_device(hose, dev); diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 3302457..15f7432 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -77,6 +77,7 @@ int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned void pciauto_setup_device(struct pci_controller *hose, pci_dev_t dev, int bars_num, struct pci_region *mem, + struct pci_region *prefetch, struct pci_region *io) { unsigned int bar_value, bar_response, bar_size; @@ -111,7 +112,10 @@ void pciauto_setup_device(struct pci_controller *hose, found_mem64 = 1; bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1; - bar_res = mem; + if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH)) + bar_res = prefetch; + else + bar_res = mem; DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size); } @@ -148,6 +152,7 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose, pci_dev_t dev, int sub_bus) { struct pci_region *pci_mem = hose->pci_mem; + struct pci_region *pci_prefetch = hose->pci_prefetch; struct pci_region *pci_io = hose->pci_io; unsigned int cmdstat; @@ -169,6 +174,21 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose, cmdstat |= PCI_COMMAND_MEMORY; } + if (pci_prefetch) { + /* Round memory allocator to 1MB boundary */ + pciauto_region_align(pci_prefetch, 0x100000); + + /* Set up memory and I/O filter limits, assume 32-bit I/O space */ + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, + (pci_prefetch->bus_lower & 0xfff00000) >> 16); + + cmdstat |= PCI_COMMAND_MEMORY; + } else { + /* We don't support prefetchable memory for now, so disable */ + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000); + } + if (pci_io) { /* Round I/O allocator to 4KB boundary */ pciauto_region_align(pci_io, 0x1000); @@ -181,10 +201,6 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose, cmdstat |= PCI_COMMAND_IO; } - /* We don't support prefetchable memory for now, so disable */ - pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); - pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000); - /* Enable memory and I/O accesses, enable bus master */ pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER); } @@ -193,6 +209,7 @@ static void pciauto_postscan_setup_bridge(struct pci_controller *hose, pci_dev_t dev, int sub_bus) { struct pci_region *pci_mem = hose->pci_mem; + struct pci_region *pci_prefetch = hose->pci_prefetch; struct pci_region *pci_io = hose->pci_io; /* Configure bus number registers */ @@ -206,6 +223,14 @@ static void pciauto_postscan_setup_bridge(struct pci_controller *hose, (pci_mem->bus_lower-1) >> 16); } + if (pci_prefetch) { + /* Round memory allocator to 1MB boundary */ + pciauto_region_align(pci_prefetch, 0x100000); + + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, + (pci_prefetch->bus_lower-1) >> 16); + } + if (pci_io) { /* Round I/O allocator to 4KB boundary */ pciauto_region_align(pci_io, 0x1000); @@ -239,6 +264,11 @@ void pciauto_config_init(struct pci_controller *hose) hose->pci_mem->size < hose->regions[i].size) hose->pci_mem = hose->regions + i; break; + case (PCI_REGION_MEM | PCI_REGION_PREFETCH): + if (!hose->pci_prefetch || + hose->pci_prefetch->size < hose->regions[i].size) + hose->pci_prefetch = hose->regions + i; + break; } } @@ -251,6 +281,14 @@ void pciauto_config_init(struct pci_controller *hose) hose->pci_mem->bus_start + hose->pci_mem->size - 1); } + if (hose->pci_prefetch) { + pciauto_region_init(hose->pci_prefetch); + + DEBUGF("PCI Autoconfig: Prefetchable Memory region: [%lx-%lx]\n", + hose->pci_prefetch->bus_start, + hose->pci_prefetch->bus_start + hose->pci_prefetch->size - 1); + } + if (hose->pci_io) { pciauto_region_init(hose->pci_io); @@ -275,7 +313,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) switch(class) { case PCI_CLASS_BRIDGE_PCI: hose->current_busno++; - pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io); + pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io); DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev)); @@ -301,12 +339,12 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) return sub_bus; } - pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io); + pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io); break; case PCI_CLASS_BRIDGE_CARDBUS: /* just do a minimal setup of the bridge, let the OS take care of the rest */ - pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io); + pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev)); @@ -328,11 +366,11 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) * the PIMMR window to be allocated (BAR0 - 1MB size) */ DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n"); - pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io); + pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); break; #endif default: - pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io); + pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io); break; } diff --git a/drivers/pci_indirect.c b/drivers/pci_indirect.c index e8f19f5..f0c4a1c 100644 --- a/drivers/pci_indirect.c +++ b/drivers/pci_indirect.c @@ -36,6 +36,10 @@ static int \ indirect_##rw##_config_##size(struct pci_controller *hose, \ pci_dev_t dev, int offset, type val) \ { \ + u32 b, d,f; \ + b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \ + b = b - hose->first_busno; \ + dev = PCI_BDF(b, d, f); \ out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ sync(); \ cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ @@ -47,6 +51,10 @@ static int \ indirect_##rw##_config_##size(struct pci_controller *hose, \ pci_dev_t dev, int offset, type val) \ { \ + u32 b, d,f; \ + b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \ + b = b - hose->first_busno; \ + dev = PCI_BDF(b, d, f); \ *(hose->cfg_addr) = dev | (offset & 0xfc) | 0x80000000; \ sync(); \ cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ @@ -58,6 +66,10 @@ static int \ indirect_##rw##_config_##size(struct pci_controller *hose, \ pci_dev_t dev, int offset, type val) \ { \ + u32 b, d,f; \ + b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \ + b = b - hose->first_busno; \ + dev = PCI_BDF(b, d, f); \ if (PCI_BUS(dev) > 0) \ out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); \ else \ @@ -71,6 +83,10 @@ static int \ indirect_##rw##_config_##size(struct pci_controller *hose, \ pci_dev_t dev, int offset, type val) \ { \ + u32 b, d,f; \ + b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \ + b = b - hose->first_busno; \ + dev = PCI_BDF(b, d, f); \ out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ return 0; \ diff --git a/drivers/smc91111.c b/drivers/smc91111.c index 060da8f..f91e4b9 100644 --- a/drivers/smc91111.c +++ b/drivers/smc91111.c @@ -160,6 +160,9 @@ extern void eth_halt(void); extern int eth_rx(void); extern int eth_send(volatile void *packet, int length); +#ifdef SHARED_RESOURCES + extern void swap_to(int device_id); +#endif /* . This is called by register_netdev(). It is responsible for @@ -210,7 +213,7 @@ static int smc_rcv(void); . If an EEPROM is present it really should be consulted. */ int smc_get_ethaddr(bd_t *bd); -int get_rom_mac(char *v_rom_mac); +int get_rom_mac(uchar *v_rom_mac); /* ------------------------------------------------------------ @@ -276,17 +279,23 @@ static inline void SMC_outb(byte value, dword offset) static inline void SMC_insw(dword offset, volatile uchar* buf, dword len) { + volatile word *p = (volatile word *)buf; + while (len-- > 0) { - *((word*)buf)++ = SMC_inw(offset); - barrier(); *((volatile u32*)(0xc0000000)); + *p++ = SMC_inw(offset); + barrier(); + *((volatile u32*)(0xc0000000)); } } static inline void SMC_outsw(dword offset, uchar* buf, dword len) { + volatile word *p = (volatile word *)buf; + while (len-- > 0) { - SMC_outw(*((word*)buf)++, offset); - barrier(); *(volatile u32*)(0xc0000000); + SMC_outw(*p++, offset); + barrier(); + *(volatile u32*)(0xc0000000); } } #endif /* CONFIG_SMC_USE_IOFUNCS */ @@ -298,7 +307,7 @@ static char unsigned smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8}; * the default mac address. */ -void smc_set_mac_addr(const char *addr) { +void smc_set_mac_addr(const unsigned char *addr) { int i; for (i=0; i < sizeof(smc_mac_addr); i++){ @@ -527,6 +536,9 @@ static void smc_shutdown() SMC_SELECT_BANK( 0 ); SMC_outb( RCR_CLEAR, RCR_REG ); SMC_outb( TCR_CLEAR, TCR_REG ); +#ifdef SHARED_RESOURCES + swap_to(FLASH); +#endif } @@ -1505,6 +1517,9 @@ static void print_packet( byte * buf, int length ) #endif int eth_init(bd_t *bd) { +#ifdef SHARED_RESOURCES + swap_to(ETHERNET); +#endif return (smc_open(bd)); } @@ -1524,7 +1539,8 @@ int smc_get_ethaddr (bd_t * bd) { int env_size, rom_valid, env_present = 0, reg; char *s = NULL, *e, *v_mac, es[] = "11:22:33:44:55:66"; - uchar s_env_mac[64], v_env_mac[6], v_rom_mac[6]; + char s_env_mac[64]; + uchar v_env_mac[6], v_rom_mac[6]; env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac)); if ((env_size > 0) && (env_size < sizeof (es))) { /* exit if env is bad */ @@ -1547,7 +1563,7 @@ int smc_get_ethaddr (bd_t * bd) if (!env_present) { /* if NO env */ if (rom_valid) { /* but ROM is valid */ - v_mac = v_rom_mac; + v_mac = (char *)v_rom_mac; sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", v_mac[0], v_mac[1], v_mac[2], v_mac[3], v_mac[4], v_mac[5]); @@ -1557,7 +1573,7 @@ int smc_get_ethaddr (bd_t * bd) return (-1); } } else { /* good env, don't care ROM */ - v_mac = v_env_mac; /* always use a good env over a ROM */ + v_mac = (char *)v_env_mac; /* always use a good env over a ROM */ } if (env_present && rom_valid) { /* if both env and ROM are good */ @@ -1577,13 +1593,13 @@ int smc_get_ethaddr (bd_t * bd) } } memcpy (bd->bi_enetaddr, v_mac, 6); /* update global address to match env (allows env changing) */ - smc_set_mac_addr (v_mac); /* use old function to update smc default */ + smc_set_mac_addr ((uchar *)v_mac); /* use old function to update smc default */ PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1], v_mac[2], v_mac[3], v_mac[4], v_mac[5]); return (0); } -int get_rom_mac (char *v_rom_mac) +int get_rom_mac (uchar *v_rom_mac) { #ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */ char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 }; diff --git a/drivers/smc91111.h b/drivers/smc91111.h index cf08582..d03cbc3 100644 --- a/drivers/smc91111.h +++ b/drivers/smc91111.h @@ -49,7 +49,7 @@ * in order to override the default mac address. */ -void smc_set_mac_addr(const char *addr); +void smc_set_mac_addr (const unsigned char *addr); /* I want some simple types */ @@ -185,6 +185,8 @@ typedef unsigned long int dword; #ifdef CONFIG_ADNPESC1 #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1)))) +#elif CONFIG_BLACKFIN +#define SMC_inw(r) ({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); asm("ssync;"); __v;}) #else #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) #endif @@ -192,6 +194,8 @@ typedef unsigned long int dword; #ifdef CONFIG_ADNPESC1 #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d) +#elif CONFIG_BLACKFIN +#define SMC_outw(d,r) {(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d);asm("ssync;");} #else #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) #endif diff --git a/drivers/tsec.h b/drivers/tsec.h index c26fcc0..e92b53a 100644 --- a/drivers/tsec.h +++ b/drivers/tsec.h @@ -124,7 +124,7 @@ /* Cicada 8204 Extended PHY Control Register 1 */ #define MIIM_CIS8204_EPHY_CON 0x17 #define MIIM_CIS8204_EPHYCON_INIT 0x0006 -#define MIIM_CIS8204_EPHYCON_RGMII 0x1000 +#define MIIM_CIS8204_EPHYCON_RGMII 0x1100 /* Cicada 8204 Serial LED Control Register */ #define MIIM_CIS8204_SLED_CON 0x1b @@ -161,12 +161,12 @@ #define MIIM_DM9161_10BTCSR_INIT 0x7800 /* LXT971 Status 2 registers */ -#define MIIM_LXT971_SR2 17 /* Status Register 2 */ -#define MIIM_LXT971_SR2_SPEED_MASK 0xf000 -#define MIIM_LXT971_SR2_10HDX 0x1000 /* 10 Mbit half duplex selected */ -#define MIIM_LXT971_SR2_10FDX 0x2000 /* 10 Mbit full duplex selected */ -#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ -#define MIIM_LXT971_SR2_100FDX 0x8000 /* 100 Mbit full duplex selected */ +#define MIIM_LXT971_SR2 0x11 /* Status Register 2 */ +#define MIIM_LXT971_SR2_SPEED_MASK 0x4200 +#define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */ +#define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */ +#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ +#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ #define MIIM_READ_COMMAND 0x00000001 diff --git a/examples/Makefile b/examples/Makefile index 2f8c4c4..fee2674 100644 --- a/examples/Makefile +++ b/examples/Makefile @@ -53,6 +53,10 @@ ifeq ($(ARCH),microblaze) LOAD_ADDR = 0x80F00000 endif +ifeq ($(ARCH),blackfin) +LOAD_ADDR = 0x1000 +endif + include $(TOPDIR)/config.mk SREC = hello_world.srec @@ -73,6 +77,11 @@ SREC += sched.srec BIN += sched.bin sched endif +ifeq ($(ARCH),blackfin) +SREC += smc91111_eeprom.srec +BIN += smc91111_eeprom.bin smc91111_eeprom +endif + # The following example is pretty 8xx specific... ifeq ($(CPU),mpc8xx) SREC += timer.srec diff --git a/examples/smc91111_eeprom.c b/examples/smc91111_eeprom.c index 885f933..98e3e86 100644 --- a/examples/smc91111_eeprom.c +++ b/examples/smc91111_eeprom.c @@ -214,13 +214,11 @@ int smc91111_eeprom (int argc, char *argv[]) switch (what) { case 1: - printf ("Writing EEPROM register %02x with %04x\n", - reg, value); + printf ("Writing EEPROM register %02x with %04x\n", reg, value); write_eeprom_reg (value, reg); break; case 2: - printf ("Writing MAC register bank %i, - reg %02x with %04x\n", reg >> 4, reg & 0xE, value); + printf ("Writing MAC register bank %i, reg %02x with %04x\n", reg >> 4, reg & 0xE, value); SMC_SELECT_BANK (reg >> 4); SMC_outw (value, reg & 0xE); break; diff --git a/examples/stubs.c b/examples/stubs.c index d4c6e06..250a9af 100644 --- a/examples/stubs.c +++ b/examples/stubs.c @@ -125,6 +125,19 @@ gd_t *global_data; " lwi r5, r5, %1\n" \ " bra r5\n" \ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r5"); +#elif defined(CONFIG_BLACKFIN) +/* + * P5 holds the pointer to the global_data, P0 is a call-clobbered + * register + */ +#define EXPORT_FUNC(x) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" P0 = [P5 + %0]\n" \ +" P0 = [P0 + %1]\n" \ +" JUMP (P0)\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "P0"); #else #error stubs definition missing for this architecture #endif diff --git a/fs/ext2/ext2fs.c b/fs/ext2/ext2fs.c index c21d2d6..9cf2fb7 100644 --- a/fs/ext2/ext2fs.c +++ b/fs/ext2/ext2fs.c @@ -389,7 +389,7 @@ int ext2fs_read_file int blockcnt; int log2blocksize = LOG2_EXT2_BLOCK_SIZE (node->data); int blocksize = 1 << (log2blocksize + DISK_SECTOR_BITS); - unsigned int filesize = node->inode.size; + unsigned int filesize = __le32_to_cpu(node->inode.size); /* Adjust len so it we can't read past the end of the file. */ if (len > filesize) { diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c index c6c0c2a..49c8652 100644 --- a/fs/jffs2/jffs2_1pass.c +++ b/fs/jffs2/jffs2_1pass.c @@ -144,6 +144,7 @@ static struct part_info *current_part; #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) +#include <nand.h> /* * Support for jffs2 on top of NAND-flash * @@ -154,9 +155,8 @@ static struct part_info *current_part; * */ -/* this one defined in cmd_nand.c */ -int read_jffs2_nand(size_t start, size_t len, - size_t * retlen, u_char * buf, int nanddev); +/* info for NAND chips, defined in drivers/nand/nand.c */ +extern nand_info_t nand_info[]; #define NAND_PAGE_SIZE 512 #define NAND_PAGE_SHIFT 9 @@ -167,6 +167,7 @@ int read_jffs2_nand(size_t start, size_t len, #endif #define NAND_CACHE_SIZE (NAND_CACHE_PAGES*NAND_PAGE_SIZE) +#ifdef CFG_NAND_LEGACY static u8* nand_cache = NULL; static u32 nand_cache_off = (u32)-1; @@ -174,7 +175,7 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf) { struct mtdids *id = current_part->dev->id; u32 bytes_read = 0; - size_t retlen; + ulong retlen; int cpy_bytes; while (bytes_read < size) { @@ -191,8 +192,10 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf) return -1; } } - if (read_jffs2_nand(nand_cache_off, NAND_CACHE_SIZE, - &retlen, nand_cache, id->num) < 0 || + + retlen = NAND_CACHE_SIZE; + if (nand_read(&nand_info[id->num], nand_cache_off, + &retlen, nand_cache) != 0 || retlen != NAND_CACHE_SIZE) { printf("read_nand_cached: error reading nand off %#x size %d bytes\n", nand_cache_off, NAND_CACHE_SIZE); @@ -248,6 +251,7 @@ static void put_fl_mem_nand(void *buf) { free(buf); } +#endif /* CFG_NAND_LEGACY */ #endif /* #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) */ @@ -290,7 +294,7 @@ static inline void *get_fl_mem(u32 off, u32 size, void *ext_buf) return get_fl_mem_nor(off); #endif -#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) +#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) if (id->type == MTD_DEV_TYPE_NAND) return get_fl_mem_nand(off, size, ext_buf); #endif @@ -308,7 +312,7 @@ static inline void *get_node_mem(u32 off) return get_node_mem_nor(off); #endif -#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) +#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) if (id->type == MTD_DEV_TYPE_NAND) return get_node_mem_nand(off); #endif @@ -319,7 +323,7 @@ static inline void *get_node_mem(u32 off) static inline void put_fl_mem(void *buf) { -#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) +#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) struct mtdids *id = current_part->dev->id; if (id->type == MTD_DEV_TYPE_NAND) @@ -1167,7 +1171,8 @@ jffs2_1pass_build_lists(struct part_info * part) if (node->magic == JFFS2_MAGIC_BITMASK && hdr_crc(node)) { /* if its a fragment add it */ if (node->nodetype == JFFS2_NODETYPE_INODE && - inode_crc((struct jffs2_raw_inode *) node)) { + inode_crc((struct jffs2_raw_inode *) node) && + data_crc((struct jffs2_raw_inode *) node)) { if (insert_node(&pL->frag, (u32) part->offset + offset) == NULL) { put_fl_mem(node); diff --git a/fs/jffs2/jffs2_nand_1pass.c b/fs/jffs2/jffs2_nand_1pass.c new file mode 100644 index 0000000..e78af75 --- /dev/null +++ b/fs/jffs2/jffs2_nand_1pass.c @@ -0,0 +1,1036 @@ +#include <common.h> + +#if !defined(CFG_NAND_LEGACY) && (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +#include <malloc.h> +#include <linux/stat.h> +#include <linux/time.h> + +#include <jffs2/jffs2.h> +#include <jffs2/jffs2_1pass.h> +#include <nand.h> + +#include "jffs2_nand_private.h" + +#define NODE_CHUNK 1024 /* size of memory allocation chunk in b_nodes */ + +/* Debugging switches */ +#undef DEBUG_DIRENTS /* print directory entry list after scan */ +#undef DEBUG_FRAGMENTS /* print fragment list after scan */ +#undef DEBUG /* enable debugging messages */ + +#ifdef DEBUG +# define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +# define DEBUGF(fmt,args...) +#endif + +static nand_info_t *nand; + +/* Compression names */ +static char *compr_names[] = { + "NONE", + "ZERO", + "RTIME", + "RUBINMIPS", + "COPY", + "DYNRUBIN", + "ZLIB", +#if defined(CONFIG_JFFS2_LZO_LZARI) + "LZO", + "LZARI", +#endif +}; + +/* Spinning wheel */ +static char spinner[] = { '|', '/', '-', '\\' }; + +/* Memory management */ +struct mem_block { + unsigned index; + struct mem_block *next; + char nodes[0]; +}; + +static void +free_nodes(struct b_list *list) +{ + while (list->listMemBase != NULL) { + struct mem_block *next = list->listMemBase->next; + free(list->listMemBase); + list->listMemBase = next; + } +} + +static struct b_node * +add_node(struct b_list *list, int size) +{ + u32 index = 0; + struct mem_block *memBase; + struct b_node *b; + + memBase = list->listMemBase; + if (memBase != NULL) + index = memBase->index; + + if (memBase == NULL || index >= NODE_CHUNK) { + /* we need more space before we continue */ + memBase = mmalloc(sizeof(struct mem_block) + NODE_CHUNK * size); + if (memBase == NULL) { + putstr("add_node: malloc failed\n"); + return NULL; + } + memBase->next = list->listMemBase; + index = 0; + } + /* now we have room to add it. */ + b = (struct b_node *)&memBase->nodes[size * index]; + index ++; + + memBase->index = index; + list->listMemBase = memBase; + list->listCount++; + return b; +} + +static struct b_node * +insert_node(struct b_list *list, struct b_node *new) +{ +#ifdef CFG_JFFS2_SORT_FRAGMENTS + struct b_node *b, *prev; + + if (list->listTail != NULL && list->listCompare(new, list->listTail)) + prev = list->listTail; + else if (list->listLast != NULL && list->listCompare(new, list->listLast)) + prev = list->listLast; + else + prev = NULL; + + for (b = (prev ? prev->next : list->listHead); + b != NULL && list->listCompare(new, b); + prev = b, b = b->next) { + list->listLoops++; + } + if (b != NULL) + list->listLast = prev; + + if (b != NULL) { + new->next = b; + if (prev != NULL) + prev->next = new; + else + list->listHead = new; + } else +#endif + { + new->next = (struct b_node *) NULL; + if (list->listTail != NULL) { + list->listTail->next = new; + list->listTail = new; + } else { + list->listTail = list->listHead = new; + } + } + + return new; +} + +static struct b_node * +insert_inode(struct b_list *list, struct jffs2_raw_inode *node, u32 offset) +{ + struct b_inode *new; + + if (!(new = (struct b_inode *)add_node(list, sizeof(struct b_inode)))) { + putstr("add_node failed!\r\n"); + return NULL; + } + new->offset = offset; + new->version = node->version; + new->ino = node->ino; + new->isize = node->isize; + new->csize = node->csize; + + return insert_node(list, (struct b_node *)new); +} + +static struct b_node * +insert_dirent(struct b_list *list, struct jffs2_raw_dirent *node, u32 offset) +{ + struct b_dirent *new; + + if (!(new = (struct b_dirent *)add_node(list, sizeof(struct b_dirent)))) { + putstr("add_node failed!\r\n"); + return NULL; + } + new->offset = offset; + new->version = node->version; + new->pino = node->pino; + new->ino = node->ino; + new->nhash = full_name_hash(node->name, node->nsize); + new->nsize = node->nsize; + new->type = node->type; + + return insert_node(list, (struct b_node *)new); +} + +#ifdef CFG_JFFS2_SORT_FRAGMENTS +/* Sort data entries with the latest version last, so that if there + * is overlapping data the latest version will be used. + */ +static int compare_inodes(struct b_node *new, struct b_node *old) +{ + struct jffs2_raw_inode ojNew; + struct jffs2_raw_inode ojOld; + struct jffs2_raw_inode *jNew = + (struct jffs2_raw_inode *)get_fl_mem(new->offset, sizeof(ojNew), &ojNew); + struct jffs2_raw_inode *jOld = + (struct jffs2_raw_inode *)get_fl_mem(old->offset, sizeof(ojOld), &ojOld); + + return jNew->version > jOld->version; +} + +/* Sort directory entries so all entries in the same directory + * with the same name are grouped together, with the latest version + * last. This makes it easy to eliminate all but the latest version + * by marking the previous version dead by setting the inode to 0. + */ +static int compare_dirents(struct b_node *new, struct b_node *old) +{ + struct jffs2_raw_dirent ojNew; + struct jffs2_raw_dirent ojOld; + struct jffs2_raw_dirent *jNew = + (struct jffs2_raw_dirent *)get_fl_mem(new->offset, sizeof(ojNew), &ojNew); + struct jffs2_raw_dirent *jOld = + (struct jffs2_raw_dirent *)get_fl_mem(old->offset, sizeof(ojOld), &ojOld); + int cmp; + + /* ascending sort by pino */ + if (jNew->pino != jOld->pino) + return jNew->pino > jOld->pino; + + /* pino is the same, so use ascending sort by nsize, so + * we don't do strncmp unless we really must. + */ + if (jNew->nsize != jOld->nsize) + return jNew->nsize > jOld->nsize; + + /* length is also the same, so use ascending sort by name + */ + cmp = strncmp(jNew->name, jOld->name, jNew->nsize); + if (cmp != 0) + return cmp > 0; + + /* we have duplicate names in this directory, so use ascending + * sort by version + */ + if (jNew->version > jOld->version) { + /* since jNew is newer, we know jOld is not valid, so + * mark it with inode 0 and it will not be used + */ + jOld->ino = 0; + return 1; + } + + return 0; +} +#endif + +static u32 +jffs_init_1pass_list(struct part_info *part) +{ + struct b_lists *pL; + + if (part->jffs2_priv != NULL) { + pL = (struct b_lists *)part->jffs2_priv; + free_nodes(&pL->frag); + free_nodes(&pL->dir); + free(pL); + } + if (NULL != (part->jffs2_priv = malloc(sizeof(struct b_lists)))) { + pL = (struct b_lists *)part->jffs2_priv; + + memset(pL, 0, sizeof(*pL)); +#ifdef CFG_JFFS2_SORT_FRAGMENTS + pL->dir.listCompare = compare_dirents; + pL->frag.listCompare = compare_inodes; +#endif + } + return 0; +} + +/* find the inode from the slashless name given a parent */ +static long +jffs2_1pass_read_inode(struct b_lists *pL, u32 ino, char *dest, + struct stat *stat) +{ + struct b_inode *jNode; + u32 totalSize = 0; + u32 latestVersion = 0; + long ret; + +#ifdef CFG_JFFS2_SORT_FRAGMENTS + /* Find file size before loading any data, so fragments that + * start past the end of file can be ignored. A fragment + * that is partially in the file is loaded, so extra data may + * be loaded up to the next 4K boundary above the file size. + * This shouldn't cause trouble when loading kernel images, so + * we will live with it. + */ + for (jNode = (struct b_inode *)pL->frag.listHead; jNode; jNode = jNode->next) { + if ((ino == jNode->ino)) { + /* get actual file length from the newest node */ + if (jNode->version >= latestVersion) { + totalSize = jNode->isize; + latestVersion = jNode->version; + } + } + } +#endif + + for (jNode = (struct b_inode *)pL->frag.listHead; jNode; jNode = jNode->next) { + if ((ino != jNode->ino)) + continue; +#ifndef CFG_JFFS2_SORT_FRAGMENTS + /* get actual file length from the newest node */ + if (jNode->version >= latestVersion) { + totalSize = jNode->isize; + latestVersion = jNode->version; + } +#endif + if (dest || stat) { + char *src, *dst; + char data[4096 + sizeof(struct jffs2_raw_inode)]; + struct jffs2_raw_inode *inode; + size_t len; + + inode = (struct jffs2_raw_inode *)&data; + len = sizeof(struct jffs2_raw_inode); + if (dest) + len += jNode->csize; + nand_read(nand, jNode->offset, &len, inode); + /* ignore data behind latest known EOF */ + if (inode->offset > totalSize) + continue; + + if (stat) { + stat->st_mtime = inode->mtime; + stat->st_mode = inode->mode; + stat->st_ino = inode->ino; + stat->st_size = totalSize; + } + + if (!dest) + continue; + + src = ((char *) inode) + sizeof(struct jffs2_raw_inode); + dst = (char *) (dest + inode->offset); + + switch (inode->compr) { + case JFFS2_COMPR_NONE: + ret = 0; + memcpy(dst, src, inode->dsize); + break; + case JFFS2_COMPR_ZERO: + ret = 0; + memset(dst, 0, inode->dsize); + break; + case JFFS2_COMPR_RTIME: + ret = 0; + rtime_decompress(src, dst, inode->csize, inode->dsize); + break; + case JFFS2_COMPR_DYNRUBIN: + /* this is slow but it works */ + ret = 0; + dynrubin_decompress(src, dst, inode->csize, inode->dsize); + break; + case JFFS2_COMPR_ZLIB: + ret = zlib_decompress(src, dst, inode->csize, inode->dsize); + break; +#if defined(CONFIG_JFFS2_LZO_LZARI) + case JFFS2_COMPR_LZO: + ret = lzo_decompress(src, dst, inode->csize, inode->dsize); + break; + case JFFS2_COMPR_LZARI: + ret = lzari_decompress(src, dst, inode->csize, inode->dsize); + break; +#endif + default: + /* unknown */ + putLabeledWord("UNKOWN COMPRESSION METHOD = ", inode->compr); + return -1; + } + } + } + + return totalSize; +} + +/* find the inode from the slashless name given a parent */ +static u32 +jffs2_1pass_find_inode(struct b_lists * pL, const char *name, u32 pino) +{ + struct b_dirent *jDir; + int len = strlen(name); /* name is assumed slash free */ + unsigned int nhash = full_name_hash(name, len); + u32 version = 0; + u32 inode = 0; + + /* we need to search all and return the inode with the highest version */ + for (jDir = (struct b_dirent *)pL->dir.listHead; jDir; jDir = jDir->next) { + if ((pino == jDir->pino) && (jDir->ino) && /* 0 for unlink */ + (len == jDir->nsize) && (nhash == jDir->nhash)) { + /* TODO: compare name */ + if (jDir->version < version) + continue; + + if (jDir->version == version && inode != 0) { + /* I'm pretty sure this isn't legal */ + putstr(" ** ERROR ** "); +/* putnstr(jDir->name, jDir->nsize); */ +/* putLabeledWord(" has dup version =", version); */ + } + inode = jDir->ino; + version = jDir->version; + } + } + return inode; +} + +char *mkmodestr(unsigned long mode, char *str) +{ + static const char *l = "xwr"; + int mask = 1, i; + char c; + + switch (mode & S_IFMT) { + case S_IFDIR: str[0] = 'd'; break; + case S_IFBLK: str[0] = 'b'; break; + case S_IFCHR: str[0] = 'c'; break; + case S_IFIFO: str[0] = 'f'; break; + case S_IFLNK: str[0] = 'l'; break; + case S_IFSOCK: str[0] = 's'; break; + case S_IFREG: str[0] = '-'; break; + default: str[0] = '?'; + } + + for(i = 0; i < 9; i++) { + c = l[i%3]; + str[9-i] = (mode & mask)?c:'-'; + mask = mask<<1; + } + + if(mode & S_ISUID) str[3] = (mode & S_IXUSR)?'s':'S'; + if(mode & S_ISGID) str[6] = (mode & S_IXGRP)?'s':'S'; + if(mode & S_ISVTX) str[9] = (mode & S_IXOTH)?'t':'T'; + str[10] = '\0'; + return str; +} + +static inline void dump_stat(struct stat *st, const char *name) +{ + char str[20]; + char s[64], *p; + + if (st->st_mtime == (time_t)(-1)) /* some ctimes really hate -1 */ + st->st_mtime = 1; + + ctime_r(&st->st_mtime, s/*,64*/); /* newlib ctime doesn't have buflen */ + + if ((p = strchr(s,'\n')) != NULL) *p = '\0'; + if ((p = strchr(s,'\r')) != NULL) *p = '\0'; + +/* + printf("%6lo %s %8ld %s %s\n", st->st_mode, mkmodestr(st->st_mode, str), + st->st_size, s, name); +*/ + + printf(" %s %8ld %s %s", mkmodestr(st->st_mode,str), st->st_size, s, name); +} + +static inline int +dump_inode(struct b_lists *pL, struct b_dirent *d, struct b_inode *i) +{ + char fname[JFFS2_MAX_NAME_LEN + 1]; + struct stat st; + size_t len; + + if(!d || !i) return -1; + len = d->nsize; + nand_read(nand, d->offset + sizeof(struct jffs2_raw_dirent), + &len, &fname); + fname[d->nsize] = '\0'; + + memset(&st, 0, sizeof(st)); + + jffs2_1pass_read_inode(pL, i->ino, NULL, &st); + + dump_stat(&st, fname); +/* FIXME + if (d->type == DT_LNK) { + unsigned char *src = (unsigned char *) (&i[1]); + putstr(" -> "); + putnstr(src, (int)i->dsize); + } +*/ + putstr("\r\n"); + + return 0; +} + +/* list inodes with the given pino */ +static u32 +jffs2_1pass_list_inodes(struct b_lists * pL, u32 pino) +{ + struct b_dirent *jDir; + u32 i_version = 0; + + for (jDir = (struct b_dirent *)pL->dir.listHead; jDir; jDir = jDir->next) { + if ((pino == jDir->pino) && (jDir->ino)) { /* ino=0 -> unlink */ + struct b_inode *jNode = (struct b_inode *)pL->frag.listHead; + struct b_inode *i = NULL; + + while (jNode) { + if (jNode->ino == jDir->ino && jNode->version >= i_version) { + i_version = jNode->version; + i = jNode; + } + jNode = jNode->next; + } + dump_inode(pL, jDir, i); + } + } + return pino; +} + +static u32 +jffs2_1pass_search_inode(struct b_lists * pL, const char *fname, u32 pino) +{ + int i; + char tmp[256]; + char working_tmp[256]; + char *c; + + /* discard any leading slash */ + i = 0; + while (fname[i] == '/') + i++; + strcpy(tmp, &fname[i]); + + while ((c = (char *) strchr(tmp, '/'))) /* we are still dired searching */ + { + strncpy(working_tmp, tmp, c - tmp); + working_tmp[c - tmp] = '\0'; +#if 0 + putstr("search_inode: tmp = "); + putstr(tmp); + putstr("\r\n"); + putstr("search_inode: wtmp = "); + putstr(working_tmp); + putstr("\r\n"); + putstr("search_inode: c = "); + putstr(c); + putstr("\r\n"); +#endif + for (i = 0; i < strlen(c) - 1; i++) + tmp[i] = c[i + 1]; + tmp[i] = '\0'; +#if 0 + putstr("search_inode: post tmp = "); + putstr(tmp); + putstr("\r\n"); +#endif + + if (!(pino = jffs2_1pass_find_inode(pL, working_tmp, pino))) { + putstr("find_inode failed for name="); + putstr(working_tmp); + putstr("\r\n"); + return 0; + } + } + /* this is for the bare filename, directories have already been mapped */ + if (!(pino = jffs2_1pass_find_inode(pL, tmp, pino))) { + putstr("find_inode failed for name="); + putstr(tmp); + putstr("\r\n"); + return 0; + } + return pino; + +} + +static u32 +jffs2_1pass_resolve_inode(struct b_lists * pL, u32 ino) +{ + struct b_dirent *jDir; + struct b_inode *jNode; + u8 jDirFoundType = 0; + u32 jDirFoundIno = 0; + u32 jDirFoundPino = 0; + char tmp[JFFS2_MAX_NAME_LEN + 1]; + u32 version = 0; + u32 pino; + + /* we need to search all and return the inode with the highest version */ + for (jDir = (struct b_dirent *)pL->dir.listHead; jDir; jDir = jDir->next) { + if (ino == jDir->ino) { + if (jDir->version < version) + continue; + + if (jDir->version == version && jDirFoundType) { + /* I'm pretty sure this isn't legal */ + putstr(" ** ERROR ** "); +/* putnstr(jDir->name, jDir->nsize); */ +/* putLabeledWord(" has dup version (resolve) = ", */ +/* version); */ + } + + jDirFoundType = jDir->type; + jDirFoundIno = jDir->ino; + jDirFoundPino = jDir->pino; + version = jDir->version; + } + } + /* now we found the right entry again. (shoulda returned inode*) */ + if (jDirFoundType != DT_LNK) + return jDirFoundIno; + + /* it's a soft link so we follow it again. */ + for (jNode = (struct b_inode *)pL->frag.listHead; jNode; jNode = jNode->next) { + if (jNode->ino == jDirFoundIno) { + size_t len = jNode->csize; + nand_read(nand, jNode->offset + sizeof(struct jffs2_raw_inode), &len, &tmp); + tmp[jNode->csize] = '\0'; + break; + } + } + /* ok so the name of the new file to find is in tmp */ + /* if it starts with a slash it is root based else shared dirs */ + if (tmp[0] == '/') + pino = 1; + else + pino = jDirFoundPino; + + return jffs2_1pass_search_inode(pL, tmp, pino); +} + +static u32 +jffs2_1pass_search_list_inodes(struct b_lists * pL, const char *fname, u32 pino) +{ + int i; + char tmp[256]; + char working_tmp[256]; + char *c; + + /* discard any leading slash */ + i = 0; + while (fname[i] == '/') + i++; + strcpy(tmp, &fname[i]); + working_tmp[0] = '\0'; + while ((c = (char *) strchr(tmp, '/'))) /* we are still dired searching */ + { + strncpy(working_tmp, tmp, c - tmp); + working_tmp[c - tmp] = '\0'; + for (i = 0; i < strlen(c) - 1; i++) + tmp[i] = c[i + 1]; + tmp[i] = '\0'; + /* only a failure if we arent looking at top level */ + if (!(pino = jffs2_1pass_find_inode(pL, working_tmp, pino)) && + (working_tmp[0])) { + putstr("find_inode failed for name="); + putstr(working_tmp); + putstr("\r\n"); + return 0; + } + } + + if (tmp[0] && !(pino = jffs2_1pass_find_inode(pL, tmp, pino))) { + putstr("find_inode failed for name="); + putstr(tmp); + putstr("\r\n"); + return 0; + } + /* this is for the bare filename, directories have already been mapped */ + if (!(pino = jffs2_1pass_list_inodes(pL, pino))) { + putstr("find_inode failed for name="); + putstr(tmp); + putstr("\r\n"); + return 0; + } + return pino; + +} + +unsigned char +jffs2_1pass_rescan_needed(struct part_info *part) +{ + struct b_node *b; + struct jffs2_unknown_node onode; + struct jffs2_unknown_node *node; + struct b_lists *pL = (struct b_lists *)part->jffs2_priv; + + if (part->jffs2_priv == 0){ + DEBUGF ("rescan: First time in use\n"); + return 1; + } + /* if we have no list, we need to rescan */ + if (pL->frag.listCount == 0) { + DEBUGF ("rescan: fraglist zero\n"); + return 1; + } + + /* or if we are scanning a new partition */ + if (pL->partOffset != part->offset) { + DEBUGF ("rescan: different partition\n"); + return 1; + } + + /* FIXME */ +#if 0 + /* but suppose someone reflashed a partition at the same offset... */ + b = pL->dir.listHead; + while (b) { + node = (struct jffs2_unknown_node *) get_fl_mem(b->offset, + sizeof(onode), &onode); + if (node->nodetype != JFFS2_NODETYPE_DIRENT) { + DEBUGF ("rescan: fs changed beneath me? (%lx)\n", + (unsigned long) b->offset); + return 1; + } + b = b->next; + } +#endif + return 0; +} + +#ifdef DEBUG_FRAGMENTS +static void +dump_fragments(struct b_lists *pL) +{ + struct b_node *b; + struct jffs2_raw_inode ojNode; + struct jffs2_raw_inode *jNode; + + putstr("\r\n\r\n******The fragment Entries******\r\n"); + b = pL->frag.listHead; + while (b) { + jNode = (struct jffs2_raw_inode *) get_fl_mem(b->offset, + sizeof(ojNode), &ojNode); + putLabeledWord("\r\n\tbuild_list: FLASH_OFFSET = ", b->offset); + putLabeledWord("\tbuild_list: totlen = ", jNode->totlen); + putLabeledWord("\tbuild_list: inode = ", jNode->ino); + putLabeledWord("\tbuild_list: version = ", jNode->version); + putLabeledWord("\tbuild_list: isize = ", jNode->isize); + putLabeledWord("\tbuild_list: atime = ", jNode->atime); + putLabeledWord("\tbuild_list: offset = ", jNode->offset); + putLabeledWord("\tbuild_list: csize = ", jNode->csize); + putLabeledWord("\tbuild_list: dsize = ", jNode->dsize); + putLabeledWord("\tbuild_list: compr = ", jNode->compr); + putLabeledWord("\tbuild_list: usercompr = ", jNode->usercompr); + putLabeledWord("\tbuild_list: flags = ", jNode->flags); + putLabeledWord("\tbuild_list: offset = ", b->offset); /* FIXME: ? [RS] */ + b = b->next; + } +} +#endif + +#ifdef DEBUG_DIRENTS +static void +dump_dirents(struct b_lists *pL) +{ + struct b_node *b; + struct jffs2_raw_dirent *jDir; + + putstr("\r\n\r\n******The directory Entries******\r\n"); + b = pL->dir.listHead; + while (b) { + jDir = (struct jffs2_raw_dirent *) get_node_mem(b->offset); + putstr("\r\n"); + putnstr(jDir->name, jDir->nsize); + putLabeledWord("\r\n\tbuild_list: magic = ", jDir->magic); + putLabeledWord("\tbuild_list: nodetype = ", jDir->nodetype); + putLabeledWord("\tbuild_list: hdr_crc = ", jDir->hdr_crc); + putLabeledWord("\tbuild_list: pino = ", jDir->pino); + putLabeledWord("\tbuild_list: version = ", jDir->version); + putLabeledWord("\tbuild_list: ino = ", jDir->ino); + putLabeledWord("\tbuild_list: mctime = ", jDir->mctime); + putLabeledWord("\tbuild_list: nsize = ", jDir->nsize); + putLabeledWord("\tbuild_list: type = ", jDir->type); + putLabeledWord("\tbuild_list: node_crc = ", jDir->node_crc); + putLabeledWord("\tbuild_list: name_crc = ", jDir->name_crc); + putLabeledWord("\tbuild_list: offset = ", b->offset); /* FIXME: ? [RS] */ + b = b->next; + put_fl_mem(jDir); + } +} +#endif + +static int +jffs2_fill_scan_buf(nand_info_t *nand, unsigned char *buf, + unsigned ofs, unsigned len) +{ + int ret; + unsigned olen; + + olen = len; + ret = nand_read(nand, ofs, &olen, buf); + if (ret) { + printf("nand_read(0x%x bytes from 0x%x) returned %d\n", len, ofs, ret); + return ret; + } + if (olen < len) { + printf("Read at 0x%x gave only 0x%x bytes\n", ofs, olen); + return -1; + } + return 0; +} + +#define EMPTY_SCAN_SIZE 1024 +static u32 +jffs2_1pass_build_lists(struct part_info * part) +{ + struct b_lists *pL; + struct jffs2_unknown_node *node; + unsigned nr_blocks, sectorsize, ofs, offset; + char *buf; + int i; + u32 counter = 0; + u32 counter4 = 0; + u32 counterF = 0; + u32 counterN = 0; + + struct mtdids *id = part->dev->id; + nand = nand_info + id->num; + + /* if we are building a list we need to refresh the cache. */ + jffs_init_1pass_list(part); + pL = (struct b_lists *)part->jffs2_priv; + pL->partOffset = part->offset; + puts ("Scanning JFFS2 FS: "); + + sectorsize = nand->erasesize; + nr_blocks = part->size / sectorsize; + buf = malloc(sectorsize); + if (!buf) + return 0; + + for (i = 0; i < nr_blocks; i++) { + printf("\b\b%c ", spinner[counter++ % sizeof(spinner)]); + + offset = part->offset + i * sectorsize; + + if (nand_block_isbad(nand, offset)) + continue; + + if (jffs2_fill_scan_buf(nand, buf, offset, EMPTY_SCAN_SIZE)) + return 0; + + ofs = 0; + /* Scan only 4KiB of 0xFF before declaring it's empty */ + while (ofs < EMPTY_SCAN_SIZE && *(uint32_t *)(&buf[ofs]) == 0xFFFFFFFF) + ofs += 4; + if (ofs == EMPTY_SCAN_SIZE) + continue; + + if (jffs2_fill_scan_buf(nand, buf + EMPTY_SCAN_SIZE, offset + EMPTY_SCAN_SIZE, sectorsize - EMPTY_SCAN_SIZE)) + return 0; + offset += ofs; + + while (ofs < sectorsize - sizeof(struct jffs2_unknown_node)) { + node = (struct jffs2_unknown_node *)&buf[ofs]; + if (node->magic != JFFS2_MAGIC_BITMASK || !hdr_crc(node)) { + offset += 4; + ofs += 4; + counter4++; + continue; + } + /* if its a fragment add it */ + if (node->nodetype == JFFS2_NODETYPE_INODE && + inode_crc((struct jffs2_raw_inode *) node)) { + if (insert_inode(&pL->frag, (struct jffs2_raw_inode *) node, + offset) == NULL) { + return 0; + } + } else if (node->nodetype == JFFS2_NODETYPE_DIRENT && + dirent_crc((struct jffs2_raw_dirent *) node) && + dirent_name_crc((struct jffs2_raw_dirent *) node)) { + if (! (counterN%100)) + puts ("\b\b. "); + if (insert_dirent(&pL->dir, (struct jffs2_raw_dirent *) node, + offset) == NULL) { + return 0; + } + counterN++; + } else if (node->nodetype == JFFS2_NODETYPE_CLEANMARKER) { + if (node->totlen != sizeof(struct jffs2_unknown_node)) + printf("OOPS Cleanmarker has bad size " + "%d != %d\n", node->totlen, + sizeof(struct jffs2_unknown_node)); + } else if (node->nodetype == JFFS2_NODETYPE_PADDING) { + if (node->totlen < sizeof(struct jffs2_unknown_node)) + printf("OOPS Padding has bad size " + "%d < %d\n", node->totlen, + sizeof(struct jffs2_unknown_node)); + } else { + printf("Unknown node type: %x len %d " + "offset 0x%x\n", node->nodetype, + node->totlen, offset); + } + offset += ((node->totlen + 3) & ~3); + ofs += ((node->totlen + 3) & ~3); + counterF++; + } + } + + putstr("\b\b done.\r\n"); /* close off the dots */ + +#if 0 + putLabeledWord("dir entries = ", pL->dir.listCount); + putLabeledWord("frag entries = ", pL->frag.listCount); + putLabeledWord("+4 increments = ", counter4); + putLabeledWord("+file_offset increments = ", counterF); +#endif + +#ifdef DEBUG_DIRENTS + dump_dirents(pL); +#endif + +#ifdef DEBUG_FRAGMENTS + dump_fragments(pL); +#endif + + /* give visual feedback that we are done scanning the flash */ + led_blink(0x0, 0x0, 0x1, 0x1); /* off, forever, on 100ms, off 100ms */ + free(buf); + + return 1; +} + + +static u32 +jffs2_1pass_fill_info(struct b_lists * pL, struct b_jffs2_info * piL) +{ + struct b_node *b; + struct jffs2_raw_inode ojNode; + struct jffs2_raw_inode *jNode; + int i; + + for (i = 0; i < JFFS2_NUM_COMPR; i++) { + piL->compr_info[i].num_frags = 0; + piL->compr_info[i].compr_sum = 0; + piL->compr_info[i].decompr_sum = 0; + } +/* FIXME + b = pL->frag.listHead; + while (b) { + jNode = (struct jffs2_raw_inode *) get_fl_mem(b->offset, + sizeof(ojNode), &ojNode); + if (jNode->compr < JFFS2_NUM_COMPR) { + piL->compr_info[jNode->compr].num_frags++; + piL->compr_info[jNode->compr].compr_sum += jNode->csize; + piL->compr_info[jNode->compr].decompr_sum += jNode->dsize; + } + b = b->next; + } +*/ + return 0; +} + + +static struct b_lists * +jffs2_get_list(struct part_info * part, const char *who) +{ + if (jffs2_1pass_rescan_needed(part)) { + if (!jffs2_1pass_build_lists(part)) { + printf("%s: Failed to scan JFFSv2 file structure\n", who); + return NULL; + } + } + return (struct b_lists *)part->jffs2_priv; +} + + +/* Print directory / file contents */ +u32 +jffs2_1pass_ls(struct part_info * part, const char *fname) +{ + struct b_lists *pl; + long ret = 0; + u32 inode; + + if (! (pl = jffs2_get_list(part, "ls"))) + return 0; + + if (! (inode = jffs2_1pass_search_list_inodes(pl, fname, 1))) { + putstr("ls: Failed to scan jffs2 file structure\r\n"); + return 0; + } + +#if 0 + putLabeledWord("found file at inode = ", inode); + putLabeledWord("read_inode returns = ", ret); +#endif + + return ret; +} + + +/* Load a file from flash into memory. fname can be a full path */ +u32 +jffs2_1pass_load(char *dest, struct part_info * part, const char *fname) +{ + + struct b_lists *pl; + long ret = 0; + u32 inode; + + if (! (pl = jffs2_get_list(part, "load"))) + return 0; + + if (! (inode = jffs2_1pass_search_inode(pl, fname, 1))) { + putstr("load: Failed to find inode\r\n"); + return 0; + } + + /* Resolve symlinks */ + if (! (inode = jffs2_1pass_resolve_inode(pl, inode))) { + putstr("load: Failed to resolve inode structure\r\n"); + return 0; + } + + if ((ret = jffs2_1pass_read_inode(pl, inode, dest, NULL)) < 0) { + putstr("load: Failed to read inode\r\n"); + return 0; + } + + DEBUGF ("load: loaded '%s' to 0x%lx (%ld bytes)\n", fname, + (unsigned long) dest, ret); + return ret; +} + +/* Return information about the fs on this partition */ +u32 +jffs2_1pass_info(struct part_info * part) +{ + struct b_jffs2_info info; + struct b_lists *pl; + int i; + + if (! (pl = jffs2_get_list(part, "info"))) + return 0; + + jffs2_1pass_fill_info(pl, &info); + for (i = 0; i < JFFS2_NUM_COMPR; i++) { + printf ("Compression: %s\n" + "\tfrag count: %d\n" + "\tcompressed sum: %d\n" + "\tuncompressed sum: %d\n", + compr_names[i], + info.compr_info[i].num_frags, + info.compr_info[i].compr_sum, + info.compr_info[i].decompr_sum); + } + return 1; +} + +#endif /* CFG_CMD_JFFS2 */ diff --git a/fs/jffs2/jffs2_nand_private.h b/fs/jffs2/jffs2_nand_private.h new file mode 100644 index 0000000..18cca8d --- /dev/null +++ b/fs/jffs2/jffs2_nand_private.h @@ -0,0 +1,133 @@ +#ifndef jffs2_private_h +#define jffs2_private_h + +#include <jffs2/jffs2.h> + +struct b_node { + struct b_node *next; +}; + +struct b_inode { + struct b_inode *next; + u32 offset; /* physical offset to beginning of real inode */ + u32 version; + u32 ino; + u32 isize; + u32 csize; +}; + +struct b_dirent { + struct b_dirent *next; + u32 offset; /* physical offset to beginning of real dirent */ + u32 version; + u32 pino; + u32 ino; + unsigned int nhash; + unsigned char nsize; + unsigned char type; +}; + +struct b_list { + struct b_node *listTail; + struct b_node *listHead; + unsigned int listCount; + struct mem_block *listMemBase; +}; + +struct b_lists { + char *partOffset; + struct b_list dir; + struct b_list frag; +}; + +struct b_compr_info { + u32 num_frags; + u32 compr_sum; + u32 decompr_sum; +}; + +struct b_jffs2_info { + struct b_compr_info compr_info[JFFS2_NUM_COMPR]; +}; + +static inline int +hdr_crc(struct jffs2_unknown_node *node) +{ +#if 1 + u32 crc = crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_unknown_node) - 4); +#else + /* what's the semantics of this? why is this here? */ + u32 crc = crc32_no_comp(~0, (unsigned char *)node, sizeof(struct jffs2_unknown_node) - 4); + + crc ^= ~0; +#endif + if (node->hdr_crc != crc) { + return 0; + } else { + return 1; + } +} + +static inline int +dirent_crc(struct jffs2_raw_dirent *node) +{ + if (node->node_crc != crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_raw_dirent) - 8)) { + return 0; + } else { + return 1; + } +} + +static inline int +dirent_name_crc(struct jffs2_raw_dirent *node) +{ + if (node->name_crc != crc32_no_comp(0, (unsigned char *)&(node->name), node->nsize)) { + return 0; + } else { + return 1; + } +} + +static inline int +inode_crc(struct jffs2_raw_inode *node) +{ + if (node->node_crc != crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_raw_inode) - 8)) { + return 0; + } else { + return 1; + } +} + +/* Borrowed from include/linux/dcache.h */ + +/* Name hashing routines. Initial hash value */ +/* Hash courtesy of the R5 hash in reiserfs modulo sign bits */ +#define init_name_hash() 0 + +/* partial hash update function. Assume roughly 4 bits per character */ +static inline unsigned long +partial_name_hash(unsigned long c, unsigned long prevhash) +{ + return (prevhash + (c << 4) + (c >> 4)) * 11; +} + +/* + * Finally: cut down the number of bits to a int value (and try to avoid + * losing bits) + */ +static inline unsigned long end_name_hash(unsigned long hash) +{ + return (unsigned int) hash; +} + +/* Compute the hash for a name string. */ +static inline unsigned int +full_name_hash(const unsigned char *name, unsigned int len) +{ + unsigned long hash = init_name_hash(); + while (len--) + hash = partial_name_hash(*name++, hash); + return end_name_hash(hash); +} + +#endif /* jffs2_private.h */ diff --git a/fs/jffs2/jffs2_private.h b/fs/jffs2/jffs2_private.h index 65ca6eb..3e1fff4 100644 --- a/fs/jffs2/jffs2_private.h +++ b/fs/jffs2/jffs2_private.h @@ -85,4 +85,16 @@ inode_crc(struct jffs2_raw_inode *node) } } +static inline int +data_crc(struct jffs2_raw_inode *node) +{ + if (node->data_crc != crc32_no_comp(0, (unsigned char *) + ((int) &node->node_crc + sizeof (node->node_crc)), + node->csize)) { + return 0; + } else { + return 1; + } +} + #endif /* jffs2_private.h */ diff --git a/include/asm-arm/arch-arm720t/s3c4510b.h b/include/asm-arm/arch-arm720t/s3c4510b.h index 517b1ad..73a3b6d 100644 --- a/include/asm-arm/arch-arm720t/s3c4510b.h +++ b/include/asm-arm/arch-arm720t/s3c4510b.h @@ -267,8 +267,6 @@ struct _irq_handler { void (*m_func)( void *data); }; -extern struct _irq_handler IRQ_HANDLER[]; - #endif #endif /* __S3C4510_h */ diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index 3ff1d26..c8c479a 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -92,6 +92,10 @@ typedef struct { volatile u32 offset[4096]; } __regbase; # define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) # else # define __REG(x) (x) +# ifdef CONFIG_CPU_MONAHANS /* Hack to make this work with mona's pxa-regs.h */ +# define __REG_2(x) (x) +# define __REG_3(x) (x) +# endif # endif #endif /* UBOOT_REG_FIX */ diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 41d37d7..83ae5e3 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -33,12 +33,21 @@ typedef void (*ExcpHndlr) (void) ; /* * PXA Chip selects */ +#ifdef CONFIG_CPU_MONAHANS +#define PXA_CS0_PHYS 0x00000000 /* for both small and large same start */ +#define PXA_CS1_PHYS 0x04000000 /* Small partition start address (64MB) */ +#define PXA_CS1_LPHYS 0x30000000 /* Large partition start address (256MB) */ +#define PXA_CS2_PHYS 0x10000000 /* (64MB) */ +#define PXA_CS3_PHYS 0x14000000 /* (64MB) */ +#define PXA_PCMCIA_PHYS 0x20000000 /* (256MB) */ +#else #define PXA_CS0_PHYS 0x00000000 #define PXA_CS1_PHYS 0x04000000 #define PXA_CS2_PHYS 0x08000000 #define PXA_CS3_PHYS 0x0C000000 #define PXA_CS4_PHYS 0x10000000 #define PXA_CS5_PHYS 0x14000000 +#endif /* CONFIG_CPU_MONAHANS */ /* * Personal Computer Memory Card International Association (PCMCIA) sockets @@ -49,10 +58,12 @@ typedef void (*ExcpHndlr) (void) ; #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ +#ifndef CONFIG_CPU_MONAHANS /* Monahans supports only one slot */ #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ +#endif #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ @@ -72,10 +83,12 @@ typedef void (*ExcpHndlr) (void) ; #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ +#ifndef CONFIG_CPU_MONAHANS /* Monahans supports only one slot */ #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ +#endif /* * DMA Controller @@ -96,6 +109,24 @@ typedef void (*ExcpHndlr) (void) ; #define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */ #define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */ #define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */ +#ifdef CONFIG_CPU_MONAHANS +#define DCSR16 __REG(0x40000040) /* DMA Control / Status Register for Channel 16 */ +#define DCSR17 __REG(0x40000044) /* DMA Control / Status Register for Channel 17 */ +#define DCSR18 __REG(0x40000048) /* DMA Control / Status Register for Channel 18 */ +#define DCSR19 __REG(0x4000004c) /* DMA Control / Status Register for Channel 19 */ +#define DCSR20 __REG(0x40000050) /* DMA Control / Status Register for Channel 20 */ +#define DCSR21 __REG(0x40000054) /* DMA Control / Status Register for Channel 21 */ +#define DCSR22 __REG(0x40000058) /* DMA Control / Status Register for Channel 22 */ +#define DCSR23 __REG(0x4000005c) /* DMA Control / Status Register for Channel 23 */ +#define DCSR24 __REG(0x40000060) /* DMA Control / Status Register for Channel 24 */ +#define DCSR25 __REG(0x40000064) /* DMA Control / Status Register for Channel 25 */ +#define DCSR26 __REG(0x40000068) /* DMA Control / Status Register for Channel 26 */ +#define DCSR27 __REG(0x4000006c) /* DMA Control / Status Register for Channel 27 */ +#define DCSR28 __REG(0x40000070) /* DMA Control / Status Register for Channel 28 */ +#define DCSR29 __REG(0x40000074) /* DMA Control / Status Register for Channel 29 */ +#define DCSR30 __REG(0x40000078) /* DMA Control / Status Register for Channel 30 */ +#define DCSR31 __REG(0x4000007c) /* DMA Control / Status Register for Channel 31 */ +#endif /* CONFIG_CPU_MONAHANS */ #define DCSR(x) __REG2(0x40000000, (x) << 2) @@ -103,7 +134,7 @@ typedef void (*ExcpHndlr) (void) ; #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ -#if defined(CONFIG_PXA27X) +#if defined(CONFIG_PXA27X) || defined (CONFIG_CPU_MONAHANS) #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ @@ -813,15 +844,47 @@ typedef void (*ExcpHndlr) (void) ; /* * OS Timer & Match Registers */ -#define OSMR0 __REG(0x40A00000) /* */ -#define OSMR1 __REG(0x40A00004) /* */ -#define OSMR2 __REG(0x40A00008) /* */ -#define OSMR3 __REG(0x40A0000C) /* */ +#define OSMR0 __REG(0x40A00000) /* OS Timer Match Register 0 */ +#define OSMR1 __REG(0x40A00004) /* OS Timer Match Register 1 */ +#define OSMR2 __REG(0x40A00008) /* OS Timer Match Register 2 */ +#define OSMR3 __REG(0x40A0000C) /* OS Timer Match Register 3 */ #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ #define OSSR __REG(0x40A00014) /* OS Timer Status Register */ #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ +#ifdef CONFIG_CPU_MONAHANS +#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register 4 */ +#define OSCR5 __REG(0x40A00044) /* OS Timer Counter Register 5 */ +#define OSCR6 __REG(0x40A00048) /* OS Timer Counter Register 6 */ +#define OSCR7 __REG(0x40A0004C) /* OS Timer Counter Register 7 */ +#define OSCR8 __REG(0x40A00050) /* OS Timer Counter Register 8 */ +#define OSCR9 __REG(0x40A00054) /* OS Timer Counter Register 9 */ +#define OSCR10 __REG(0x40A00058) /* OS Timer Counter Register 10 */ +#define OSCR11 __REG(0x40A0005C) /* OS Timer Counter Register 11 */ + +#define OSMR4 __REG(0x40A00080) /* OS Timer Match Register 4 */ +#define OSMR5 __REG(0x40A00084) /* OS Timer Match Register 5 */ +#define OSMR6 __REG(0x40A00088) /* OS Timer Match Register 6 */ +#define OSMR7 __REG(0x40A0008C) /* OS Timer Match Register 7 */ +#define OSMR8 __REG(0x40A00090) /* OS Timer Match Register 8 */ +#define OSMR9 __REG(0x40A00094) /* OS Timer Match Register 9 */ +#define OSMR10 __REG(0x40A00098) /* OS Timer Match Register 10 */ +#define OSMR11 __REG(0x40A0009C) /* OS Timer Match Register 11 */ + +#define OMCR4 __REG(0x40A000C0) /* OS Match Control Register 4 */ +#define OMCR5 __REG(0x40A000C4) /* OS Match Control Register 5 */ +#define OMCR6 __REG(0x40A000C8) /* OS Match Control Register 6 */ +#define OMCR7 __REG(0x40A000CC) /* OS Match Control Register 7 */ +#define OMCR8 __REG(0x40A000D0) /* OS Match Control Register 8 */ +#define OMCR9 __REG(0x40A000D4) /* OS Match Control Register 9 */ +#define OMCR10 __REG(0x40A000D8) /* OS Match Control Register 10 */ +#define OMCR11 __REG(0x40A000DC) /* OS Match Control Register 11 */ + +#define OSCR_CLK_FREQ 3.250 /* MHz */ +#endif /* CONFIG_CPU_MONAHANS */ + +#define OSSR_M4 (1 << 4) /* Match status channel 4 */ #define OSSR_M3 (1 << 3) /* Match status channel 3 */ #define OSSR_M2 (1 << 2) /* Match status channel 2 */ #define OSSR_M1 (1 << 1) /* Match status channel 1 */ @@ -829,6 +892,7 @@ typedef void (*ExcpHndlr) (void) ; #define OWER_WME (1 << 0) /* Watchdog Match Enable */ +#define OIER_E4 (1 << 4) /* Interrupt enable channel 4 */ #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ @@ -855,6 +919,19 @@ typedef void (*ExcpHndlr) (void) ; #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ +#ifdef CONFIG_CPU_MONAHANS +#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */ +/* Missing: 32 Interrupt priority registers */ +/* mk@tbd: These are the same as beneath for PXA27x: maybe can be + * merged if GPIO Stuff is same too. */ +#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ +#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ +#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ +#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ +#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ +/* Missing: 2 Interrupt priority registers */ +#endif /* CONFIG_CPU_MONAHANS */ + /* * General Purpose I/O */ @@ -886,12 +963,287 @@ typedef void (*ExcpHndlr) (void) ; #define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */ #define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */ +#ifdef CONFIG_CPU_MONAHANS +#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */ +#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */ +#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */ +#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */ +#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */ +#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */ +#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */ + +#define GSDR0 __REG(0x40E00400) /* Bit-wise Set of GPDR[31:0] */ +#define GSDR1 __REG(0x40E00404) /* Bit-wise Set of GPDR[63:32] */ +#define GSDR2 __REG(0x40E00408) /* Bit-wise Set of GPDR[95:64] */ +#define GSDR3 __REG(0x40E0040C) /* Bit-wise Set of GPDR[127:96] */ + +#define GCDR0 __REG(0x40E00420) /* Bit-wise Clear of GPDR[31:0] */ +#define GCDR1 __REG(0x40E00424) /* Bit-wise Clear of GPDR[63:32] */ +#define GCDR2 __REG(0x40E00428) /* Bit-wise Clear of GPDR[95:64] */ +#define GCDR3 __REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */ + +#define GSRER0 __REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */ +#define GSRER1 __REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */ +#define GSRER2 __REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */ +#define GSRER3 __REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */ + +#define GCRER0 __REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */ +#define GCRER1 __REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */ +#define GCRER2 __REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */ +#define GCRER3 __REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */ + +#define GSFER0 __REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */ +#define GSFER1 __REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */ +#define GSFER2 __REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */ +#define GSFER3 __REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */ + +#define GCFER0 __REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */ +#define GCFER1 __REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */ +#define GCFER2 __REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */ +#define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */ + +#define GSDR(x) __REG2(0x40E00400, ((x) & 0x60) >> 3) +#define GCDR(x) __REG2(0x40300420, ((x) & 0x60) >> 3) + +/* Multi-funktion Pin Registers, uncomplete, only: + * - GPIO + * - Data Flash DF_* pins defined. + */ +#define GPIO0 __REG(0x40e10124) +#define GPIO1 __REG(0x40e10128) +#define GPIO2 __REG(0x40e1012c) +#define GPIO3 __REG(0x40e10130) +#define GPIO4 __REG(0x40e10134) +#define nXCVREN __REG(0x40e10138) + +#define DF_CLE_NOE __REG(0x40e10204) +#define DF_ALE_WE1 __REG(0x40e10208) + +#define DF_SCLK_E __REG(0x40e10210) +#define nBE0 __REG(0x40e10214) +#define nBE1 __REG(0x40e10218) +#define DF_ALE_WE2 __REG(0x40e1021c) +#define DF_INT_RnB __REG(0x40e10220) +#define DF_nCS0 __REG(0x40e10224) +#define DF_nCS1 __REG(0x40e10228) +#define DF_nWE __REG(0x40e1022c) +#define DF_nRE __REG(0x40e10230) +#define nLUA __REG(0x40e10234) +#define nLLA __REG(0x40e10238) +#define DF_ADDR0 __REG(0x40e1023c) +#define DF_ADDR1 __REG(0x40e10240) +#define DF_ADDR2 __REG(0x40e10244) +#define DF_ADDR3 __REG(0x40e10248) +#define DF_IO0 __REG(0x40e1024c) +#define DF_IO8 __REG(0x40e10250) +#define DF_IO1 __REG(0x40e10254) +#define DF_IO9 __REG(0x40e10258) +#define DF_IO2 __REG(0x40e1025c) +#define DF_IO10 __REG(0x40e10260) +#define DF_IO3 __REG(0x40e10264) +#define DF_IO11 __REG(0x40e10268) +#define DF_IO4 __REG(0x40e1026c) +#define DF_IO12 __REG(0x40e10270) +#define DF_IO5 __REG(0x40e10274) +#define DF_IO13 __REG(0x40e10278) +#define DF_IO6 __REG(0x40e1027c) +#define DF_IO14 __REG(0x40e10280) +#define DF_IO7 __REG(0x40e10284) +#define DF_IO15 __REG(0x40e10288) + +#define GPIO5 __REG(0x40e1028c) +#define GPIO6 __REG(0x40e10290) +#define GPIO7 __REG(0x40e10294) +#define GPIO8 __REG(0x40e10298) +#define GPIO9 __REG(0x40e1029c) + +#define GPIO11 __REG(0x40e102a0) +#define GPIO12 __REG(0x40e102a4) +#define GPIO13 __REG(0x40e102a8) +#define GPIO14 __REG(0x40e102ac) +#define GPIO15 __REG(0x40e102b0) +#define GPIO16 __REG(0x40e102b4) +#define GPIO17 __REG(0x40e102b8) +#define GPIO18 __REG(0x40e102bc) +#define GPIO19 __REG(0x40e102c0) +#define GPIO20 __REG(0x40e102c4) +#define GPIO21 __REG(0x40e102c8) +#define GPIO22 __REG(0x40e102cc) +#define GPIO23 __REG(0x40e102d0) +#define GPIO24 __REG(0x40e102d4) +#define GPIO25 __REG(0x40e102d8) +#define GPIO26 __REG(0x40e102dc) + +#define GPIO27 __REG(0x40e10400) +#define GPIO28 __REG(0x40e10404) +#define GPIO29 __REG(0x40e10408) +#define GPIO30 __REG(0x40e1040c) +#define GPIO31 __REG(0x40e10410) +#define GPIO32 __REG(0x40e10414) +#define GPIO33 __REG(0x40e10418) +#define GPIO34 __REG(0x40e1041c) +#define GPIO35 __REG(0x40e10420) +#define GPIO36 __REG(0x40e10424) +#define GPIO37 __REG(0x40e10428) +#define GPIO38 __REG(0x40e1042c) +#define GPIO39 __REG(0x40e10430) +#define GPIO40 __REG(0x40e10434) +#define GPIO41 __REG(0x40e10438) +#define GPIO42 __REG(0x40e1043c) +#define GPIO43 __REG(0x40e10440) +#define GPIO44 __REG(0x40e10444) +#define GPIO45 __REG(0x40e10448) +#define GPIO46 __REG(0x40e1044c) +#define GPIO47 __REG(0x40e10450) +#define GPIO48 __REG(0x40e10454) + +#define GPIO10 __REG(0x40e10458) + +#define GPIO49 __REG(0x40e1045c) +#define GPIO50 __REG(0x40e10460) +#define GPIO51 __REG(0x40e10464) +#define GPIO52 __REG(0x40e10468) +#define GPIO53 __REG(0x40e1046c) +#define GPIO54 __REG(0x40e10470) +#define GPIO55 __REG(0x40e10474) +#define GPIO56 __REG(0x40e10478) +#define GPIO57 __REG(0x40e1047c) +#define GPIO58 __REG(0x40e10480) +#define GPIO59 __REG(0x40e10484) +#define GPIO60 __REG(0x40e10488) +#define GPIO61 __REG(0x40e1048c) +#define GPIO62 __REG(0x40e10490) + +#define GPIO6_2 __REG(0x40e10494) +#define GPIO7_2 __REG(0x40e10498) +#define GPIO8_2 __REG(0x40e1049c) +#define GPIO9_2 __REG(0x40e104a0) +#define GPIO10_2 __REG(0x40e104a4) +#define GPIO11_2 __REG(0x40e104a8) +#define GPIO12_2 __REG(0x40e104ac) +#define GPIO13_2 __REG(0x40e104b0) + +#define GPIO63 __REG(0x40e104b4) +#define GPIO64 __REG(0x40e104b8) +#define GPIO65 __REG(0x40e104bc) +#define GPIO66 __REG(0x40e104c0) +#define GPIO67 __REG(0x40e104c4) +#define GPIO68 __REG(0x40e104c8) +#define GPIO69 __REG(0x40e104cc) +#define GPIO70 __REG(0x40e104d0) +#define GPIO71 __REG(0x40e104d4) +#define GPIO72 __REG(0x40e104d8) +#define GPIO73 __REG(0x40e104dc) + +#define GPIO14_2 __REG(0x40e104e0) +#define GPIO15_2 __REG(0x40e104e4) +#define GPIO16_2 __REG(0x40e104e8) +#define GPIO17_2 __REG(0x40e104ec) + +#define GPIO74 __REG(0x40e104f0) +#define GPIO75 __REG(0x40e104f4) +#define GPIO76 __REG(0x40e104f8) +#define GPIO77 __REG(0x40e104fc) +#define GPIO78 __REG(0x40e10500) +#define GPIO79 __REG(0x40e10504) +#define GPIO80 __REG(0x40e10508) +#define GPIO81 __REG(0x40e1050c) +#define GPIO82 __REG(0x40e10510) +#define GPIO83 __REG(0x40e10514) +#define GPIO84 __REG(0x40e10518) +#define GPIO85 __REG(0x40e1051c) +#define GPIO86 __REG(0x40e10520) +#define GPIO87 __REG(0x40e10524) +#define GPIO88 __REG(0x40e10528) +#define GPIO89 __REG(0x40e1052c) +#define GPIO90 __REG(0x40e10530) +#define GPIO91 __REG(0x40e10534) +#define GPIO92 __REG(0x40e10538) +#define GPIO93 __REG(0x40e1053c) +#define GPIO94 __REG(0x40e10540) +#define GPIO95 __REG(0x40e10544) +#define GPIO96 __REG(0x40e10548) +#define GPIO97 __REG(0x40e1054c) +#define GPIO98 __REG(0x40e10550) + +#define GPIO99 __REG(0x40e10600) +#define GPIO100 __REG(0x40e10604) +#define GPIO101 __REG(0x40e10608) +#define GPIO102 __REG(0x40e1060c) +#define GPIO103 __REG(0x40e10610) +#define GPIO104 __REG(0x40e10614) +#define GPIO105 __REG(0x40e10618) +#define GPIO106 __REG(0x40e1061c) +#define GPIO107 __REG(0x40e10620) +#define GPIO108 __REG(0x40e10624) +#define GPIO109 __REG(0x40e10628) +#define GPIO110 __REG(0x40e1062c) +#define GPIO111 __REG(0x40e10630) +#define GPIO112 __REG(0x40e10634) + +#define GPIO113 __REG(0x40e10638) +#define GPIO114 __REG(0x40e1063c) +#define GPIO115 __REG(0x40e10640) +#define GPIO116 __REG(0x40e10644) +#define GPIO117 __REG(0x40e10648) +#define GPIO118 __REG(0x40e1064c) +#define GPIO119 __REG(0x40e10650) +#define GPIO120 __REG(0x40e10654) +#define GPIO121 __REG(0x40e10658) +#define GPIO122 __REG(0x40e1065c) +#define GPIO123 __REG(0x40e10660) +#define GPIO124 __REG(0x40e10664) +#define GPIO125 __REG(0x40e10668) +#define GPIO126 __REG(0x40e1066c) +#define GPIO127 __REG(0x40e10670) + +#define GPIO0_2 __REG(0x40e10674) +#define GPIO1_2 __REG(0x40e10678) +#define GPIO2_2 __REG(0x40e1067c) +#define GPIO3_2 __REG(0x40e10680) +#define GPIO4_2 __REG(0x40e10684) +#define GPIO5_2 __REG(0x40e10688) + +/* MFPR Bit Definitions, see 4-10, Vol. 1 */ +#define PULL_SEL 0x8000 +#define PULLUP_EN 0x4000 +#define PULLDOWN_EN 0x2000 + +#define DRIVE_FAST_1mA 0x0 +#define DRIVE_FAST_2mA 0x400 +#define DRIVE_FAST_3mA 0x800 +#define DRIVE_FAST_4mA 0xC00 +#define DRIVE_SLOW_6mA 0x1000 +#define DRIVE_FAST_6mA 0x1400 +#define DRIVE_SLOW_10mA 0x1800 +#define DRIVE_FAST_10mA 0x1C00 + +#define SLEEP_SEL 0x200 +#define SLEEP_DATA 0x100 +#define SLEEP_OE_N 0x80 +#define EDGE_CLEAR 0x40 +#define EDGE_FALL_EN 0x20 +#define EDGE_RISE_EN 0x10 + +#define AF_SEL_0 0x0 /* Alternate function 0 (reset state) */ +#define AF_SEL_1 0x1 /* Alternate function 1 */ +#define AF_SEL_2 0x2 /* Alternate function 2 */ +#define AF_SEL_3 0x3 /* Alternate function 3 */ +#define AF_SEL_4 0x4 /* Alternate function 4 */ +#define AF_SEL_5 0x5 /* Alternate function 5 */ +#define AF_SEL_6 0x6 /* Alternate function 6 */ +#define AF_SEL_7 0x7 /* Alternate function 7 */ + + +#else /* CONFIG_CPU_MONAHANS */ + #define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */ #define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */ #define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */ #define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */ #define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */ #define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO 80 */ +#endif /* CONFIG_CPU_MONAHANS */ /* More handy macros. The argument is a literal GPIO number. */ @@ -1142,6 +1494,79 @@ typedef void (*ExcpHndlr) (void) ; /* * Power Manager */ +#ifdef CONFIG_CPU_MONAHANS + +#define ASCR __REG(0x40F40000) /* Application Subsystem Power Status/Control Register */ +#define ARSR __REG(0x40F40004) /* Application Subsystem Reset Status Register */ +#define AD3ER __REG(0x40F40008) /* Application Subsystem D3 state Wakeup Enable Register */ +#define AD3SR __REG(0x40F4000C) /* Application Subsystem D3 state Wakeup Status Register */ +#define AD2D0ER __REG(0x40F40010) /* Application Subsystem D2 to D0 state Wakeup Enable Register */ +#define AD2D0SR __REG(0x40F40014) /* Application Subsystem D2 to D0 state Wakeup Status Register */ +#define AD2D1ER __REG(0x40F40018) /* Application Subsystem D2 to D1 state Wakeup Enable Register */ +#define AD2D1SR __REG(0x40F4001C) /* Application Subsystem D2 to D1 state Wakeup Status Register */ +#define AD1D0ER __REG(0x40F40020) /* Application Subsystem D1 to D0 state Wakeup Enable Register */ +#define AD1D0SR __REG(0x40F40024) /* Application Subsystem D1 to D0 state Wakeup Status Register */ +#define ASDCNT __REG(0x40F40028) /* Application Subsystem SRAM Drowsy Count Register */ +#define AD3R __REG(0x40F40030) /* Application Subsystem D3 State Configuration Register */ +#define AD2R __REG(0x40F40034) /* Application Subsystem D2 State Configuration Register */ +#define AD1R __REG(0x40F40038) /* Application Subsystem D1 State Configuration Register */ + +#define PMCR __REG(0x40F50000) /* Power Manager Control Register */ +#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */ +#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */ +#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */ +#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */ +#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */ +#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */ +#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */ +#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */ +#define PCMD(x) __REG(0x40F50110 + x*4) +#define PCMD0 __REG(0x40F50110 + 0 * 4) +#define PCMD1 __REG(0x40F50110 + 1 * 4) +#define PCMD2 __REG(0x40F50110 + 2 * 4) +#define PCMD3 __REG(0x40F50110 + 3 * 4) +#define PCMD4 __REG(0x40F50110 + 4 * 4) +#define PCMD5 __REG(0x40F50110 + 5 * 4) +#define PCMD6 __REG(0x40F50110 + 6 * 4) +#define PCMD7 __REG(0x40F50110 + 7 * 4) +#define PCMD8 __REG(0x40F50110 + 8 * 4) +#define PCMD9 __REG(0x40F50110 + 9 * 4) +#define PCMD10 __REG(0x40F50110 + 10 * 4) +#define PCMD11 __REG(0x40F50110 + 11 * 4) +#define PCMD12 __REG(0x40F50110 + 12 * 4) +#define PCMD13 __REG(0x40F50110 + 13 * 4) +#define PCMD14 __REG(0x40F50110 + 14 * 4) +#define PCMD15 __REG(0x40F50110 + 15 * 4) +#define PCMD16 __REG(0x40F50110 + 16 * 4) +#define PCMD17 __REG(0x40F50110 + 17 * 4) +#define PCMD18 __REG(0x40F50110 + 18 * 4) +#define PCMD19 __REG(0x40F50110 + 19 * 4) +#define PCMD20 __REG(0x40F50110 + 20 * 4) +#define PCMD21 __REG(0x40F50110 + 21 * 4) +#define PCMD22 __REG(0x40F50110 + 22 * 4) +#define PCMD23 __REG(0x40F50110 + 23 * 4) +#define PCMD24 __REG(0x40F50110 + 24 * 4) +#define PCMD25 __REG(0x40F50110 + 25 * 4) +#define PCMD26 __REG(0x40F50110 + 26 * 4) +#define PCMD27 __REG(0x40F50110 + 27 * 4) +#define PCMD28 __REG(0x40F50110 + 28 * 4) +#define PCMD29 __REG(0x40F50110 + 29 * 4) +#define PCMD30 __REG(0x40F50110 + 30 * 4) +#define PCMD31 __REG(0x40F50110 + 31 * 4) + +#define PCMD_MBC (1<<12) +#define PCMD_DCE (1<<11) +#define PCMD_LC (1<<10) +#define PCMD_SQC (3<<8) /* only 00 and 01 are valid */ + +#define PVCR_FVC (0x1 << 28) +#define PVCR_VCSA (0x1<<14) +#define PVCR_CommandDelay (0xf80) +#define PVCR_ReadPointer (0x01f00000) +#define PVCR_SlaveAddress (0x7f) + +#else /* ifdef CONFIG_CPU_MONAHANS */ + #define PMCR __REG(0x40F00000) /* Power Manager Control Register */ #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ @@ -1225,6 +1650,8 @@ typedef void (*ExcpHndlr) (void) ; #define RCSR_WDR (1 << 1) /* Watchdog Reset */ #define RCSR_HWR (1 << 0) /* Hardware Reset */ +#endif /* CONFIG_CPU_MONAHANS */ + /* * SSP Serial Port Registers */ @@ -1259,6 +1686,67 @@ typedef void (*ExcpHndlr) (void) ; /* * Core Clock */ + +#if defined(CONFIG_CPU_MONAHANS) +#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ +#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ +#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ +#define CKENA __REG(0x4134000C) /* A Clock Enable Register */ +#define CKENB __REG(0x41340010) /* B Clock Enable Register */ +#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ + +#define ACCR_SMC_MASK 0x03800000 /* Static Memory Controller Frequency Select */ +#define ACCR_SRAM_MASK 0x000c0000 /* SRAM Controller Frequency Select */ +#define ACCR_FC_MASK 0x00030000 /* Frequency Change Frequency Select */ +#define ACCR_HSIO_MASK 0x0000c000 /* High Speed IO Frequency Select */ +#define ACCR_DDR_MASK 0x00003000 /* DDR Memory Controller Frequency Select */ +#define ACCR_XN_MASK 0x00000700 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ +#define ACCR_XL_MASK 0x0000001f /* Crystal Frequency to Memory Frequency Multiplier */ +#define ACCR_XPDIS (1 << 31) +#define ACCR_SPDIS (1 << 30) +#define ACCR_13MEND1 (1 << 27) +#define ACCR_D0CS (1 << 26) +#define ACCR_13MEND2 (1 << 21) +#define ACCR_PCCE (1 << 11) + +#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */ +#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */ +#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */ +#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */ +#define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */ +#define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */ +#define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */ +#define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */ +#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */ +#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */ +#define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */ +#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */ +#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */ +#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */ +#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */ +#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */ +#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */ +#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */ +#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */ +#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */ +#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */ +#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */ +#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */ +#define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */ +#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */ +#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */ +#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */ +#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */ + +#define CKENB_8_1WIRE ((1 << 8) + 32) /* One Wire Interface Unit Clock Enable */ +#define CKENB_7_GPIO ((1 << 7) + 32) /* GPIO Clock Enable */ +#define CKENB_6_IRQ ((1 << 6) + 32) /* Interrupt Controller Clock Enable */ +#define CKENB_4_I2C ((1 << 4) + 32) /* I2C Unit Clock Enable */ +#define CKENB_1_PWM1 ((1 << 1) + 32) /* PWM2 & PWM3 Clock Enable */ +#define CKENB_0_PWM0 ((1 << 0) + 32) /* PWM0 & PWM1 Clock Enable */ + +#else /* if defined CONFIG_CPU_MONAHANS */ + #define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ #define CKEN __REG(0x41300004) /* Clock Enable Register */ #define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ @@ -1318,6 +1806,8 @@ typedef void (*ExcpHndlr) (void) ; #define CCCR_N30 (0x6 << 7) #endif +#endif /* CONFIG_CPU_MONAHANS */ + /* * LCD */ @@ -1502,6 +1992,163 @@ typedef void (*ExcpHndlr) (void) ; /* * Memory controller */ + +#ifdef CONFIG_CPU_MONAHANS +/* Static Memory Controller Registers */ +#define MSC0 __REG_2(0x4A000008) /* Static Memory Control Register 0 */ +#define MSC1 __REG_2(0x4A00000C) /* Static Memory Control Register 1 */ +#define MECR __REG_2(0x4A000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ +#define SXCNFG __REG_2(0x4A00001C) /* Synchronous Static Memory Control Register */ +#define MCMEM0 __REG_2(0x4A000028) /* Card interface Common Memory Space Socket 0 Timing */ +#define MCATT0 __REG_2(0x4A000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ +#define MCIO0 __REG_2(0x4A000038) /* Card interface I/O Space Socket 0 Timing Configuration */ +#define MEMCLKCFG __REG_2(0x4A000068) /* SCLK speed configuration */ +#define CSADRCFG0 __REG_2(0x4A000080) /* Address Configuration for chip select 0 */ +#define CSADRCFG1 __REG_2(0x4A000084) /* Address Configuration for chip select 1 */ +#define CSADRCFG2 __REG_2(0x4A000088) /* Address Configuration for chip select 2 */ +#define CSADRCFG3 __REG_2(0x4A00008C) /* Address Configuration for chip select 3 */ +#define CSADRCFG_P __REG_2(0x4A000090) /* Address Configuration for pcmcia card interface */ +#define CSMSADRCFG __REG_2(0x4A0000A0) /* Master Address Configuration Register */ +#define CLK_RET_DEL __REG_2(0x4A0000B0) /* Delay line and mux selects for return data latching for sync. flash */ +#define ADV_RET_DEL __REG_2(0x4A0000B4) /* Delay line and mux selects for return data latching for sync. flash */ + +/* Dynamic Memory Controller Registers */ +#define MDCNFG __REG_2(0x48100000) /* SDRAM Configuration Register 0 */ +#define MDREFR __REG_2(0x48100004) /* SDRAM Refresh Control Register */ +#define FLYCNFG __REG_2(0x48100020) /* Fly-by DMA DVAL[1:0] polarities */ +#define MDMRS __REG_2(0x48100040) /* MRS value to be written to SDRAM */ +#define DDR_SCAL __REG_2(0x48100050) /* Software Delay Line Calibration/Configuration for external DDR memory. */ +#define DDR_HCAL __REG_2(0x48100060) /* Hardware Delay Line Calibration/Configuration for external DDR memory. */ +#define DDR_WCAL __REG_2(0x48100068) /* DDR Write Strobe Calibration Register */ +#define DMCIER __REG_2(0x48100070) /* Dynamic MC Interrupt Enable Register. */ +#define DMCISR __REG_2(0x48100078) /* Dynamic MC Interrupt Status Register. */ +#define DDR_DLS __REG_2(0x48100080) /* DDR Delay Line Value Status register for external DDR memory. */ +#define EMPI __REG_2(0x48100090) /* EMPI Control Register */ +#define RCOMP __REG_2(0x48100100) +#define PAD_MA __REG_2(0x48100110) +#define PAD_MDMSB __REG_2(0x48100114) +#define PAD_MDLSB __REG_2(0x48100118) +#define PAD_DMEM __REG_2(0x4810011c) +#define PAD_SDCLK __REG_2(0x48100120) +#define PAD_SDCS __REG_2(0x48100124) +#define PAD_SMEM __REG_2(0x48100128) +#define PAD_SCLK __REG_2(0x4810012C) +#define TAI __REG_2(0x48100F00) /* TAI Tavor Address Isolation Register */ + +/* Some frequently used bits */ +#define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */ +#define MDCNFG_DMCEN 0x40000000 /* Enable Dynamic Memory Controller */ +#define MDCNFG_HWFREQ 0x20000000 /* Hardware Frequency Change Calibration */ +#define MDCNFG_DTYPE 0x400 /* SDRAM Type: 1=DDR SDRAM */ + +#define MDCNFG_DTC_0 0x0 /* Timing Category of SDRAM */ +#define MDCNFG_DTC_1 0x100 +#define MDCNFG_DTC_2 0x200 +#define MDCNFG_DTC_3 0x300 + +#define MDCNFG_DRAC_12 0x0 /* Number of Row Access Bits */ +#define MDCNFG_DRAC_13 0x20 +#define MDCNFG_DRAC_14 0x40 + +#define MDCNFG_DCAC_9 0x0 /* Number of Column Acess Bits */ +#define MDCNFG_DCAC_10 0x08 +#define MDCNFG_DCAC_11 0x10 + +#define MDCNFG_DBW_16 0x4 /* SDRAM Data Bus width 16bit */ +#define MDCNFG_DCSE1 0x2 /* SDRAM CS 1 Enable */ +#define MDCNFG_DCSE0 0x1 /* SDRAM CS 0 Enable */ + + +/* Data Flash Controller Registers */ + +#define NDCR __REG(0x43100000) /* Data Flash Control register */ +#define NDTR0CS0 __REG(0x43100004) /* Data Controller Timing Parameter 0 Register for ND_nCS0 */ +/* #define NDTR0CS1 __REG(0x43100008) /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */ +#define NDTR1CS0 __REG(0x4310000C) /* Data Controller Timing Parameter 1 Register for ND_nCS0 */ +/* #define NDTR1CS1 __REG(0x43100010) /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */ +#define NDSR __REG(0x43100014) /* Data Controller Status Register */ +#define NDPCR __REG(0x43100018) /* Data Controller Page Count Register */ +#define NDBDR0 __REG(0x4310001C) /* Data Controller Bad Block Register 0 */ +#define NDBDR1 __REG(0x43100020) /* Data Controller Bad Block Register 1 */ +#define NDDB __REG(0x43100040) /* Data Controller Data Buffer */ +#define NDCB0 __REG(0x43100048) /* Data Controller Command Buffer0 */ +#define NDCB1 __REG(0x4310004C) /* Data Controller Command Buffer1 */ +#define NDCB2 __REG(0x43100050) /* Data Controller Command Buffer2 */ + +#define NDCR_SPARE_EN (0x1<<31) +#define NDCR_ECC_EN (0x1<<30) +#define NDCR_DMA_EN (0x1<<29) +#define NDCR_ND_RUN (0x1<<28) +#define NDCR_DWIDTH_C (0x1<<27) +#define NDCR_DWIDTH_M (0x1<<26) +#define NDCR_PAGE_SZ (0x3<<24) +#define NDCR_NCSX (0x1<<23) +#define NDCR_ND_STOP (0x1<<22) +/* reserved: + * #define NDCR_ND_MODE (0x3<<21) + * #define NDCR_NAND_MODE 0x0 */ +#define NDCR_CLR_PG_CNT (0x1<<20) +#define NDCR_CLR_ECC (0x1<<19) +#define NDCR_RD_ID_CNT (0x7<<16) +#define NDCR_RA_START (0x1<<15) +#define NDCR_PG_PER_BLK (0x1<<14) +#define NDCR_ND_ARB_EN (0x1<<12) +#define NDCR_RDYM (0x1<<11) +#define NDCR_CS0_PAGEDM (0x1<<10) +#define NDCR_CS1_PAGEDM (0x1<<9) +#define NDCR_CS0_CMDDM (0x1<<8) +#define NDCR_CS1_CMDDM (0x1<<7) +#define NDCR_CS0_BBDM (0x1<<6) +#define NDCR_CS1_BBDM (0x1<<5) +#define NDCR_DBERRM (0x1<<4) +#define NDCR_SBERRM (0x1<<3) +#define NDCR_WRDREQM (0x1<<2) +#define NDCR_RDDREQM (0x1<<1) +#define NDCR_WRCMDREQM (0x1) + +#define NDSR_RDY (0x1<<11) +#define NDSR_CS0_PAGED (0x1<<10) +#define NDSR_CS1_PAGED (0x1<<9) +#define NDSR_CS0_CMDD (0x1<<8) +#define NDSR_CS1_CMDD (0x1<<7) +#define NDSR_CS0_BBD (0x1<<6) +#define NDSR_CS1_BBD (0x1<<5) +#define NDSR_DBERR (0x1<<4) +#define NDSR_SBERR (0x1<<3) +#define NDSR_WRDREQ (0x1<<2) +#define NDSR_RDDREQ (0x1<<1) +#define NDSR_WRCMDREQ (0x1) + +#define NDCB0_AUTO_RS (0x1<<25) +#define NDCB0_CSEL (0x1<<24) +#define NDCB0_CMD_TYPE (0x7<<21) +#define NDCB0_NC (0x1<<20) +#define NDCB0_DBC (0x1<<19) +#define NDCB0_ADDR_CYC (0x7<<16) +#define NDCB0_CMD2 (0xff<<8) +#define NDCB0_CMD1 (0xff) +#define MCMEM(s) MCMEM0 +#define MCATT(s) MCATT0 +#define MCIO(s) MCIO0 +#define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */ + +/* Maximum values for NAND Interface Timing Registers in DFC clock + * periods */ +#define DFC_MAX_tCH 7 +#define DFC_MAX_tCS 7 +#define DFC_MAX_tWH 7 +#define DFC_MAX_tWP 7 +#define DFC_MAX_tRH 7 +#define DFC_MAX_tRP 15 +#define DFC_MAX_tR 65535 +#define DFC_MAX_tWHR 15 +#define DFC_MAX_tAR 15 + +#define DFC_CLOCK 104 /* DFC Clock is 104 MHz */ +#define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */ + +#else /* CONFIG_CPU_MONAHANS */ + #define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */ #define MDCNFG_OFFSET 0x0 #define MDREFR_OFFSET 0x4 @@ -1573,6 +2220,8 @@ typedef void (*ExcpHndlr) (void) ; #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ +#endif /* CONFIG_CPU_MONAHANS */ + /* Interrupt Controller */ #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index c2b69fb..648a10d 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -58,6 +58,14 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen); #define __raw_readw(a) __arch_getw(a) #define __raw_readl(a) __arch_getl(a) +#define writeb(v,a) __arch_putb(v,a) +#define writew(v,a) __arch_putw(v,a) +#define writel(v,a) __arch_putl(v,a) + +#define readb(a) __arch_getb(a) +#define readw(a) __arch_getw(a) +#define readl(a) __arch_getl(a) + /* * The compiler seems to be incapable of optimising constants * properly. Spell it out to the compiler in some cases. diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h new file mode 100644 index 0000000..65d2c25 --- /dev/null +++ b/include/asm-blackfin/bitops.h @@ -0,0 +1,380 @@ +/* + * U-boot - bitops.h Routines for bit operations + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_BITOPS_H +#define _BLACKFIN_BITOPS_H + +/* + * Copyright 1992, Linus Torvalds. + */ + +#include <linux/config.h> +#include <asm/byteorder.h> +#include <asm/system.h> + +#ifdef __KERNEL__ +/* + * Function prototypes to keep gcc -Wall happy + */ + +/* + * The __ functions are not atomic + */ + +/* + * ffz = Find First Zero in word. Undefined if no zero exists, + * so code should check against ~0UL first.. + */ +static __inline__ unsigned long ffz(unsigned long word) +{ + unsigned long result = 0; + + while (word & 1) { + result++; + word >>= 1; + } + return result; +} + +static __inline__ void set_bit(int nr, volatile void *addr) +{ + int *a = (int *) addr; + int mask; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_and_cli(flags); + *a |= mask; + restore_flags(flags); +} + +static __inline__ void __set_bit(int nr, volatile void *addr) +{ + int *a = (int *) addr; + int mask; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a |= mask; +} + +/* + * clear_bit() doesn't provide any barrier for the compiler. + */ +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() + +static __inline__ void clear_bit(int nr, volatile void *addr) +{ + int *a = (int *) addr; + int mask; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_and_cli(flags); + *a &= ~mask; + restore_flags(flags); +} + +static __inline__ void change_bit(int nr, volatile void *addr) +{ + int mask, flags; + unsigned long *ADDR = (unsigned long *) addr; + + ADDR += nr >> 5; + mask = 1 << (nr & 31); + save_and_cli(flags); + *ADDR ^= mask; + restore_flags(flags); +} + +static __inline__ void __change_bit(int nr, volatile void *addr) +{ + int mask; + unsigned long *ADDR = (unsigned long *) addr; + + ADDR += nr >> 5; + mask = 1 << (nr & 31); + *ADDR ^= mask; +} + +static __inline__ int test_and_set_bit(int nr, volatile void *addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_and_cli(flags); + retval = (mask & *a) != 0; + *a |= mask; + restore_flags(flags); + + return retval; +} + +static __inline__ int __test_and_set_bit(int nr, volatile void *addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a |= mask; + return retval; +} + +static __inline__ int test_and_clear_bit(int nr, volatile void *addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_and_cli(flags); + retval = (mask & *a) != 0; + *a &= ~mask; + restore_flags(flags); + + return retval; +} + +static __inline__ int __test_and_clear_bit(int nr, volatile void *addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a &= ~mask; + return retval; +} + +static __inline__ int test_and_change_bit(int nr, volatile void *addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + save_and_cli(flags); + retval = (mask & *a) != 0; + *a ^= mask; + restore_flags(flags); + + return retval; +} + +static __inline__ int __test_and_change_bit(int nr, volatile void *addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *) addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a ^= mask; + return retval; +} + +/* + * This routine doesn't need to be atomic. + */ +static __inline__ int __constant_test_bit(int nr, + const volatile void *addr) +{ + return ((1UL << (nr & 31)) & + (((const volatile unsigned int *) addr)[nr >> 5])) != 0; +} + +static __inline__ int __test_bit(int nr, volatile void *addr) +{ + int *a = (int *) addr; + int mask; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + return ((mask & *a) != 0); +} + +#define test_bit(nr,addr) \ +(__builtin_constant_p(nr) ? \ + __constant_test_bit((nr),(addr)) : \ + __test_bit((nr),(addr))) + +#define find_first_zero_bit(addr, size) \ + find_next_zero_bit((addr), (size), 0) + +static __inline__ int find_next_zero_bit(void *addr, int size, int offset) +{ + unsigned long *p = ((unsigned long *) addr) + (offset >> 5); + unsigned long result = offset & ~31UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if (offset) { + tmp = *(p++); + tmp |= ~0UL >> (32 - offset); + if (size < 32) + goto found_first; + if (~tmp) + goto found_middle; + size -= 32; + result += 32; + } + while (size & ~31UL) { + if (~(tmp = *(p++))) + goto found_middle; + result += 32; + size -= 32; + } + if (!size) + return result; + tmp = *p; + + found_first: + tmp |= ~0UL >> size; + found_middle: + return result + ffz(tmp); +} + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ + +#define ffs(x) generic_ffs(x) + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +static __inline__ int ext2_set_bit(int nr, volatile void *addr) +{ + int mask, retval; + unsigned long flags; + volatile unsigned char *ADDR = (unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + save_and_cli(flags); + retval = (mask & *ADDR) != 0; + *ADDR |= mask; + restore_flags(flags); + return retval; +} + +static __inline__ int ext2_clear_bit(int nr, volatile void *addr) +{ + int mask, retval; + unsigned long flags; + volatile unsigned char *ADDR = (unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + save_and_cli(flags); + retval = (mask & *ADDR) != 0; + *ADDR &= ~mask; + restore_flags(flags); + return retval; +} + +static __inline__ int ext2_test_bit(int nr, const volatile void *addr) +{ + int mask; + const volatile unsigned char *ADDR = (const unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + return ((mask & *ADDR) != 0); +} + +#define ext2_find_first_zero_bit(addr, size) \ + ext2_find_next_zero_bit((addr), (size), 0) + +static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, + unsigned long size, + unsigned long + offset) +{ + unsigned long *p = ((unsigned long *) addr) + (offset >> 5); + unsigned long result = offset & ~31UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if (offset) { + tmp = *(p++); + tmp |= ~0UL >> (32 - offset); + if (size < 32) + goto found_first; + if (~tmp) + goto found_middle; + size -= 32; + result += 32; + } + while (size & ~31UL) { + if (~(tmp = *(p++))) + goto found_middle; + result += 32; + size -= 32; + } + if (!size) + return result; + tmp = *p; + + found_first: + tmp |= ~0UL >> size; + found_middle: + return result + ffz(tmp); +} + +/* Bitmap functions for the minix filesystem. */ +#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) +#define minix_set_bit(nr,addr) set_bit(nr,addr) +#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) +#define minix_test_bit(nr,addr) test_bit(nr,addr) +#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) + +#endif + +#endif diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h new file mode 100644 index 0000000..fbdbf30 --- /dev/null +++ b/include/asm-blackfin/blackfin.h @@ -0,0 +1,46 @@ +/* + * U-boot - blackfin.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_H_ +#define _BLACKFIN_H_ + +#include <asm/cpu/defBF533.h> +#include <asm/cpu/bf533_serial.h> + +#ifndef __ASSEMBLY__ +#ifndef ASSEMBLY + +#ifdef SHARED_RESOURCES + #include <asm/shared_resources.h> +#endif +#include <asm/cpu/cdefBF53x.h> + +#endif +#endif + +#include <asm/cpu/defBF533.h> +#include <asm/cpu/defBF533_extn.h> +#include <asm/cpu/bf533_serial.h> + +#endif diff --git a/include/asm-blackfin/blackfin_defs.h b/include/asm-blackfin/blackfin_defs.h new file mode 100644 index 0000000..2190215 --- /dev/null +++ b/include/asm-blackfin/blackfin_defs.h @@ -0,0 +1,83 @@ +/* + * U-boot - blackfin_defs.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BLACKFIN_DEFS_H__ +#define __BLACKFIN_DEFS_H__ + +#define TS_MAGICKEY 0x5a5a5a5a +#define TASK_STATE 0 +#define TASK_FLAGS 4 +#define TASK_PTRACE 24 +#define TASK_BLOCKED 636 +#define TASK_COUNTER 32 +#define TASK_SIGPENDING 8 +#define TASK_NEEDRESCHED 20 +#define TASK_THREAD 600 +#define TASK_MM 44 +#define TASK_ACTIVE_MM 80 +#define THREAD_KSP 0 +#define THREAD_USP 4 +#define THREAD_SR 8 +#define THREAD_ESP0 12 +#define THREAD_PC 16 +#define PT_ORIG_R0 208 +#define PT_R0 204 +#define PT_R1 200 +#define PT_R2 196 +#define PT_R3 192 +#define PT_R4 188 +#define PT_R5 184 +#define PT_R6 180 +#define PT_R7 176 +#define PT_P0 172 +#define PT_P1 168 +#define PT_P2 164 +#define PT_P3 160 +#define PT_P4 156 +#define PT_P5 152 +#define PT_A0w 72 +#define PT_A1w 64 +#define PT_A0x 76 +#define PT_A1x 68 +#define PT_RETS 28 +#define PT_RESERVED 32 +#define PT_ASTAT 36 +#define PT_SEQSTAT 8 +#define PT_PC 24 +#define PT_IPEND 0 +#define PT_USP 144 +#define PT_FP 148 +#define PT_SYSCFG 4 +#define IRQ_HANDLER 0 +#define IRQ_DEVID 8 +#define IRQ_NEXT 16 +#define STAT_IRQ 5148 +#define SIGSEGV 11 +#define SEGV_MAPERR 196609 +#define SIGTRAP 5 +#define PT_PTRACED 1 +#define PT_TRACESYS 2 +#define PT_DTRACE 4 + +#endif diff --git a/include/asm-blackfin/byteorder.h b/include/asm-blackfin/byteorder.h new file mode 100644 index 0000000..3b4df4e --- /dev/null +++ b/include/asm-blackfin/byteorder.h @@ -0,0 +1,40 @@ +/* + * U-boot - byteorder.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_BYTEORDER_H +#define _BLACKFIN_BYTEORDER_H + +#include <asm/types.h> + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#include <linux/byteorder/little_endian.h> + +#endif diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h new file mode 100644 index 0000000..7715f64 --- /dev/null +++ b/include/asm-blackfin/cplb.h @@ -0,0 +1,48 @@ +/************************************************************************ + * + * cplb.h + * + * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved. + * + ************************************************************************/ + +/* Defines necessary for cplb initialisation routines. */ + +#ifndef _CPLB_H +#define _CPLB_H + +#define CPLB_ENABLE_ICACHE_P 0 +#define CPLB_ENABLE_DCACHE_P 1 +#define CPLB_ENABLE_DCACHE2_P 2 +#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated!*/ +#define CPLB_ENABLE_ICPLBS_P 4 +#define CPLB_ENABLE_DCPLBS_P 5 + +#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P) +#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P) +#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P) +#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P) +#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P) +#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P) +#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \ + CPLB_ENABLE_ICPLBS | \ + CPLB_ENABLE_DCPLBS + +#define CPLB_RELOADED 0x0000 +#define CPLB_NO_UNLOCKED 0x0001 +#define CPLB_NO_ADDR_MATCH 0x0002 +#define CPLB_PROT_VIOL 0x0003 + +#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT +#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY + +#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR + +#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID +#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID +#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID +#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE +#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID +#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL + +#endif /* _CPLB_H */ diff --git a/include/asm-blackfin/cplbtab.h b/include/asm-blackfin/cplbtab.h new file mode 100644 index 0000000..ab7d989 --- /dev/null +++ b/include/asm-blackfin/cplbtab.h @@ -0,0 +1,572 @@ +/*This file is subject to the terms and conditions of the GNU General Public + * License. + * + * Blackfin BF533/2.6 support : LG Soft India + * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd + * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's + * shouldn't be victimized. cplbmgr.S search logic is corrected + * to findout the appropriate victim. + * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC + * : LG Soft India + */ +#include <config.h> + +#ifndef __ARCH_BFINNOMMU_CPLBTAB_H +#define __ARCH_BFINNOMMU_CPLBTAB_H + +/************************************************************************* + * ICPLB TABLE + *************************************************************************/ + +.data + +/* This table is configurable */ + +.align 4; + +/* Data Attibutes*/ + +#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) + +/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ + +#define ANOMALY_05000158 0x200 +#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ + #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) + #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) + #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) + #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) + #define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) + +#else /*Write Through*/ + #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) + #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) + #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) + #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) + #define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) +#endif + +.global icplb_table +icplb_table: +.byte4 0xFFA00000; +.byte4 (L1_IMEMORY); +.byte4 0x00000000; +.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/ +.byte4 0x00400000; +.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/ +.byte4 0x07C00000; +.byte4 (SDRAM_IKERNEL); /*SDRAM_Page14*/ +.byte4 0x00800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/ +.byte4 0x00C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/ +.byte4 0x01000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/ +.byte4 0x01400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/ +.byte4 0x01800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/ +.byte4 0x01C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/ +#ifndef CONFIG_EZKIT /*STAMP Memory regions*/ +.byte4 0x02000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/ +.byte4 0x02400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/ +.byte4 0x02800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/ +.byte4 0x02C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/ +.byte4 0x03000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/ +.byte4 0x03400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/ +#endif +.byte4 0xffffffff; /* end of section - termination*/ + +.align 4; +.global ipdt_table +ipdt_table: +#ifdef CONFIG_CPLB_INFO +.byte4 0x00000000; +.byte4 (SDRAM_IKERNEL); /*SDRAM_Page0*/ +.byte4 0x00400000; +.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/ +#endif +.byte4 0x00800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/ +.byte4 0x00C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page3*/ +.byte4 0x01000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/ +.byte4 0x01400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/ +.byte4 0x01800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/ +.byte4 0x01C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/ +#ifndef CONFIG_EZKIT /*STAMP Memory regions*/ +.byte4 0x02000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/ +.byte4 0x02400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/ +.byte4 0x02800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/ +.byte4 0x02C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/ +.byte4 0x03000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/ +.byte4 0x03400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/ +.byte4 0x03800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page14*/ +.byte4 0x03C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page15*/ +#endif +.byte4 0x20200000; +.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/ +.byte4 0x20100000; +.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/ +.byte4 0x20000000; +.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/ +.byte4 0x20300000; /*Fix for Network*/ +.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/ + +#ifdef CONFIG_STAMP +.byte4 0x04000000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x04400000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x04800000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x04C00000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x05000000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x05400000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x05800000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x05C00000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x06000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page25*/ +.byte4 0x06400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page26*/ +.byte4 0x06800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page27*/ +.byte4 0x06C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page28*/ +.byte4 0x07000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page29*/ +.byte4 0x07400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page30*/ +.byte4 0x07800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page31*/ +#ifdef CONFIG_CPLB_INFO +.byte4 0x07C00000; +.byte4 (SDRAM_IKERNEL); /*SDRAM_Page32*/ +#endif +#endif +.byte4 0xffffffff; /* end of section - termination*/ + +/********************************************************************* + * DCPLB TABLE + ********************************************************************/ + +.global dcplb_table +dcplb_table: +.byte4 0x00000000; +.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/ +.byte4 0x00400000; +.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/ +.byte4 0x07C00000; +.byte4 (SDRAM_DKERNEL); /*SDRAM_Page15*/ +.byte4 0x00800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/ +.byte4 0x00C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/ +.byte4 0x01000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/ +.byte4 0x01400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/ +.byte4 0x01800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/ +.byte4 0x01C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/ +#ifndef CONFIG_EZKIT +.byte4 0x02000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/ +.byte4 0x02400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/ +.byte4 0x02800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/ +.byte4 0x02C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/ +.byte4 0x03000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/ +.byte4 0x03400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/ +.byte4 0x03800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/ +#endif +.byte4 0xffffffff; /*end of section - termination*/ + +/********************************************************************** + * PAGE DESCRIPTOR TABLE + * + **********************************************************************/ + +/* Till here we are discussing about the static memory management model. + * However, the operating envoronments commonly define more CPLB + * descriptors to cover the entire addressable memory than will fit into + * the available on-chip 16 CPLB MMRs. When this happens, the below table + * will be used which will hold all the potentially required CPLB descriptors + * + * This is how Page descriptor Table is implemented in uClinux/Blackfin. + */ +.global dpdt_table +dpdt_table: +#ifdef CONFIG_CPLB_INFO +.byte4 0x00000000; +.byte4 (SDRAM_DKERNEL); /*SDRAM_Page0*/ +.byte4 0x00400000; +.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/ +#endif +.byte4 0x00800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/ +.byte4 0x00C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/ +.byte4 0x01000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/ +.byte4 0x01400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/ +.byte4 0x01800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/ +.byte4 0x01C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/ + +#ifndef CONFIG_EZKIT +.byte4 0x02000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/ +.byte4 0x02400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/ +.byte4 0x02800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/ +.byte4 0x02C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/ +.byte4 0x03000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/ +.byte4 0x03400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/ +.byte4 0x03800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/ +.byte4 0x03C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page15*/ +#endif +.byte4 0x20200000; +.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/ +.byte4 0x20100000; +.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/ +.byte4 0x20000000; +.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/ +.byte4 0x20300000; /*Fix for Network*/ +.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/ + +#ifdef CONFIG_STAMP +.byte4 0x04000000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x04400000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x04800000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x04C00000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x05000000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x05400000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x05800000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x05C00000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x06000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page25*/ +.byte4 0x06400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page26*/ +.byte4 0x06800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page27*/ +.byte4 0x06C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page28*/ +.byte4 0x07000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page29*/ +.byte4 0x07400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page30*/ +.byte4 0x07800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page31*/ +#ifdef CONFIG_CPLB_INFO +.byte4 0x07C00000; +.byte4 (SDRAM_DKERNEL); /*SDRAM_Page32*/ +#endif +#endif + +.byte4 0xFF900000; +.byte4 (L1_DMEMORY); +.byte4 0xFF901000; +.byte4 (L1_DMEMORY); +.byte4 0xFF902000; +.byte4 (L1_DMEMORY); +.byte4 0xFF903000; +.byte4 (L1_DMEMORY); +.byte4 0xFF904000; +.byte4 (L1_DMEMORY); +.byte4 0xFF905000; +.byte4 (L1_DMEMORY); +.byte4 0xFF906000; +.byte4 (L1_DMEMORY); +.byte4 0xFF907000; +.byte4 (L1_DMEMORY); +.byte4 0xFF800000; +.byte4 (L1_DMEMORY); +.byte4 0xFF801000; +.byte4 (L1_DMEMORY); +.byte4 0xFF802000; +.byte4 (L1_DMEMORY); +.byte4 0xFF803000; +.byte4 (L1_DMEMORY); + +.byte4 0xffffffff; /*end of section - termination*/ + +#ifdef CONFIG_CPLB_INFO +.global ipdt_swapcount_table; /* swapin count first, then swapout count*/ +ipdt_swapcount_table: +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 10 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 20 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 30 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 40 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 50 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 60 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 70 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 80 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 90 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 100 */ + +.global dpdt_swapcount_table; /* swapin count first, then swapout count*/ +dpdt_swapcount_table: +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 10 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 20 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 30 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 40 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 50 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 60 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 70 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 80 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 80 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 100 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 110 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 120 */ + +#endif + +#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/ diff --git a/include/asm-blackfin/cpu/bf533_irq.h b/include/asm-blackfin/cpu/bf533_irq.h new file mode 100644 index 0000000..9c5230d --- /dev/null +++ b/include/asm-blackfin/cpu/bf533_irq.h @@ -0,0 +1,137 @@ +/* + * U-boot bf533_irq.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c + * Changed by HuTao Apr18, 2003 + * + * Copyright was missing when I got the code so took from MIPS arch ...MaTed--- + * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle + * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle + * + * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca> + * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) + * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com> + * + * Adapted for BlackFin BF533 by Bas Vermeulen <bas@buyways.nl> + * Copyright (c) 2003 BuyWays B.V. (www.buyways.nl) + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BF533_IRQ_H_ +#define _BF533_IRQ_H_ + +/* + * Interrupt source definitions + * Event Source Core Event Name Number + * EMU 0 + * Reset RST 1 + * NMI NMI 2 + * Exception EVX 3 + * Reserved -- 4 + * Hardware Error IVHW 5 + * Core Timer IVTMR 6 + * PLL Wakeup Interrupt IVG7 7 + * DMA Error (generic) IVG7 8 + * PPI Error Interrupt IVG7 9 + * SPORT0 Error Interrupt IVG7 10 + * SPORT1 Error Interrupt IVG7 11 + * SPI Error Interrupt IVG7 12 + * UART Error Interrupt IVG7 13 + * RTC Interrupt IVG8 14 + * DMA0 Interrupt (PPI) IVG8 15 + * DMA1 (SPORT0 RX) IVG9 16 + * DMA2 (SPORT0 TX) IVG9 17 + * DMA3 (SPORT1 RX) IVG9 18 + * DMA4 (SPORT1 TX) IVG9 19 + * DMA5 (PPI) IVG10 20 + * DMA6 (UART RX) IVG10 21 + * DMA7 (UART TX) IVG10 22 + * Timer0 IVG11 23 + * Timer1 IVG11 24 + * Timer2 IVG11 25 + * PF Interrupt A IVG12 26 + * PF Interrupt B IVG12 27 + * DMA8/9 Interrupt IVG13 28 + * DMA10/11 Interrupt IVG13 29 + * Watchdog Timer IVG13 30 + * Software Interrupt 1 IVG14 31 + * Software Interrupt 2 -- + * (lowest priority) IVG15 32 + */ + +/* The ABSTRACT IRQ definitions */ + +/* The first seven of the following are fixed, + * the rest you change if you need to + */ + +#define IRQ_EMU 0 /* Emulation */ +#define IRQ_RST 1 /* reset */ +#define IRQ_NMI 2 /* Non Maskable */ +#define IRQ_EVX 3 /* Exception */ +#define IRQ_UNUSED 4 /* - unused interrupt */ +#define IRQ_HWERR 5 /* Hardware Error */ +#define IRQ_CORETMR 6 /* Core timer */ +#define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */ +#define IRQ_DMA_ERROR 8 /* DMA Error (general) */ +#define IRQ_PPI_ERROR 9 /* PPI Error Interrupt */ +#define IRQ_SPORT0_ERROR 10 /* SPORT0 Error Interrupt */ +#define IRQ_SPORT1_ERROR 11 /* SPORT1 Error Interrupt */ +#define IRQ_SPI_ERROR 12 /* SPI Error Interrupt */ +#define IRQ_UART_ERROR 13 /* UART Error Interrupt */ +#define IRQ_RTC 14 /* RTC Interrupt */ +#define IRQ_PPI 15 /* DMA0 Interrupt (PPI) */ +#define IRQ_SPORT0 16 /* DMA1 Interrupt (SPORT0 RX) */ +#define IRQ_SPARE1 17 /* DMA2 Interrupt (SPORT0 TX) */ +#define IRQ_SPORT1 18 /* DMA3 Interrupt (SPORT1 RX) */ +#define IRQ_SPARE2 19 /* DMA4 Interrupt (SPORT1 TX) */ +#define IRQ_SPI 20 /* DMA5 Interrupt (SPI) */ +#define IRQ_UART 21 /* DMA6 Interrupt (UART RX) */ +#define IRQ_SPARE3 22 /* DMA7 Interrupt (UART TX) */ +#define IRQ_TMR0 23 /* Timer 0 */ +#define IRQ_TMR1 24 /* Timer 1 */ +#define IRQ_TMR2 25 /* Timer 2 */ +#define IRQ_PROG_INTA 26 /* Programmable Flags A (8) */ +#define IRQ_PROG_INTB 27 /* Programmable Flags B (8) */ +#define IRQ_MEM_DMA0 28 /* DMA8/9 Interrupt (Memory DMA Stream 0) */ +#define IRQ_MEM_DMA1 29 /* DMA10/11 Interrupt (Memory DMA Stream 1) */ +#define IRQ_WATCH 30 /* Watch Dog Timer */ +#define IRQ_SW_INT1 31 /* Software Int 1 */ +#define IRQ_SW_INT2 32 /* Software Int 2 (reserved for SYSCALL) */ + +#define IRQ_UART_RX_BIT 0x4000 +#define IRQ_UART_TX_BIT 0x8000 +#define IRQ_UART_ERROR_BIT 0x40 + +#define IVG7 7 +#define IVG8 8 +#define IVG9 9 +#define IVG10 10 +#define IVG11 11 +#define IVG12 12 +#define IVG13 13 +#define IVG14 14 +#define IVG15 15 +#define SYS_IRQS 33 + +#endif diff --git a/include/asm-blackfin/cpu/bf533_rtc.h b/include/asm-blackfin/cpu/bf533_rtc.h new file mode 100644 index 0000000..bc09922 --- /dev/null +++ b/include/asm-blackfin/cpu/bf533_rtc.h @@ -0,0 +1,46 @@ +/* + * U-boot - bf533_rtc.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BF533_RTC_H_ +#define _BF533_RTC_H_ + +void rtc_init(void); +void wait_for_complete(void); +void rtc_reset(void); + +#define MIN_TO_SECS(_x_) (60 * _x_) +#define HRS_TO_SECS(_x_) (60 * 60 * _x_) +#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_) + +#define NUM_SECS_IN_DAY (24 * 3600) +#define NUM_SECS_IN_HOUR (3600) +#define NUM_SECS_IN_MIN (60) + +/* Shift values for RTC_STAT register */ +#define DAY_BITS_OFF 17 +#define HOUR_BITS_OFF 12 +#define MIN_BITS_OFF 6 +#define SEC_BITS_OFF 0 + +#endif diff --git a/include/asm-blackfin/cpu/bf533_serial.h b/include/asm-blackfin/cpu/bf533_serial.h new file mode 100644 index 0000000..d5e162a --- /dev/null +++ b/include/asm-blackfin/cpu/bf533_serial.h @@ -0,0 +1,79 @@ +/* + * U-boot bf533_serial.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef _BF533_SERIAL_H_ +#define _BF533_SERIAL_H_ + +#define BYTE_REF(addr) (*((volatile char*)addr)) +#define HALFWORD_REF(addr) (*((volatile short*)addr)) +#define WORD_REF(addr) (*((volatile long*)addr)) + +#define UART_THR_LO HALFWORD_REF(UART_THR) +#define UART_RBR_LO HALFWORD_REF(UART_RBR) +#define UART_DLL_LO HALFWORD_REF(UART_DLL) +#define UART_IER_LO HALFWORD_REF(UART_IER) +#define UART_IER_ERBFI 0x01 +#define UART_IER_ETBEI 0x02 +#define UART_IER_ELSI 0x04 +#define UART_IER_EDDSI 0x08 + +#define UART_DLH_LO HALFWORD_REF(UART_DLH) +#define UART_IIR_LO HALFWORD_REF(UART_IIR) +#define UART_IIR_NOINT 0x01 +#define UART_IIR_STATUS 0x06 +#define UART_IIR_LSR 0x06 +#define UART_IIR_RBR 0x04 +#define UART_IIR_THR 0x02 +#define UART_IIR_MSR 0x00 + +#define UART_LCR_LO HALFWORD_REF(UART_LCR) +#define UART_LCR_WLS5 0 +#define UART_LCR_WLS6 0x01 +#define UART_LCR_WLS7 0x02 +#define UART_LCR_WLS8 0x03 +#define UART_LCR_STB 0x04 +#define UART_LCR_PEN 0x08 +#define UART_LCR_EPS 0x10 +#define UART_LCR_SP 0x20 +#define UART_LCR_SB 0x40 +#define UART_LCR_DLAB 0x80 + +#define UART_MCR_LO HALFWORD_REF(UART_MCR) + +#define UART_LSR_LO HALFWORD_REF(UART_LSR) +#define UART_LSR_DR 0x01 +#define UART_LSR_OE 0x02 +#define UART_LSR_PE 0x04 +#define UART_LSR_FE 0x08 +#define UART_LSR_BI 0x10 +#define UART_LSR_THRE 0x20 +#define UART_LSR_TEMT 0x40 + +#define UART_MSR_LO HALFWORD_REF(UART_MSR) +#define UART_SCR_LO HALFWORD_REF(UART_SCR) +#define UART_GCTL_LO HALFWORD_REF(UART_GCTL) +#define UART_GCTL_UCEN 0x01 + +#endif diff --git a/include/asm-blackfin/cpu/cdefBF531.h b/include/asm-blackfin/cpu/cdefBF531.h new file mode 100644 index 0000000..68d841d --- /dev/null +++ b/include/asm-blackfin/cpu/cdefBF531.h @@ -0,0 +1,24 @@ +/* + * cdefBF531.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _CDEFBF531_H +#define _CDEFBF531_H + +#include <cdefBF532.h> + +#endif /* _CDEFBF531_H */ diff --git a/include/asm-blackfin/cpu/cdefBF532.h b/include/asm-blackfin/cpu/cdefBF532.h new file mode 100644 index 0000000..a4d422f --- /dev/null +++ b/include/asm-blackfin/cpu/cdefBF532.h @@ -0,0 +1,398 @@ +/* + * cdefBF532.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _CDEF_BF532_H +#define _CDEF_BF532_H + +/* + * #if !defined(__ADSPLPBLACKFIN__) + * #warning cdefBF532.h should only be included for 532 compatible chips. + * #endif + */ + +/* include all Core registers and bit definitions */ +#include <asm/cpu/defBF532.h> + +/* include core specific register pointer definitions */ +#include <asm/cpu/cdef_LPBlackfin.h> + +/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ +#define pPLL_CTL ((volatile unsigned short *)PLL_CTL) +#define pPLL_STAT ((volatile unsigned short *)PLL_STAT) +#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT) +#define pCHIPID ((volatile unsigned long *)CHIPID) +#define pSWRST ((volatile unsigned short *)SWRST) +#define pSYSCR ((volatile unsigned short *)SYSCR) +#define pPLL_DIV ((volatile unsigned short *)PLL_DIV) +#define pVR_CTL ((volatile unsigned short *)VR_CTL) + +/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ +#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0) +#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1) +#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2) +#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3) +#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK) +#define pSIC_ISR ((volatile unsigned long *)SIC_ISR) +#define pSIC_IWR ((volatile unsigned long *)SIC_IWR) + +/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */ +#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL) +#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT) +#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT) + +/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */ +#define pRTC_STAT ((volatile unsigned long *)RTC_STAT) +#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL) +#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT) +#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT) +#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM) +#define pRTC_FAST ((volatile unsigned short *)RTC_FAST) +#define pRTC_PREN ((volatile unsigned short *)RTC_PREN) + +/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ +#define pFIO_DIR ((volatile unsigned short *)FIO_DIR) +#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C) +#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S) +#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C) +#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S) +#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C) +#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S) +#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR) +#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE) +#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH) +#define pFIO_INEN ((volatile unsigned short *)FIO_INEN) +#define pFIO_FLAG_D ((volatile unsigned short *)FIO_FLAG_D) +#define pFIO_FLAG_T ((volatile unsigned short *)FIO_FLAG_T) +#define pFIO_MASKA_D ((volatile unsigned short *)FIO_MASKA_D) +#define pFIO_MASKA_T ((volatile unsigned short *)FIO_MASKA_T) +#define pFIO_MASKB_D ((volatile unsigned short *)FIO_MASKB_D) +#define pFIO_MASKB_T ((volatile unsigned short *)FIO_MASKB_T) + +/* DMA Test Registers */ +#define pDMA_CCOMP ((volatile unsigned long *)DMA_CCOMP) +#define pDMA_ACOMP ((volatile unsigned long *)DMA_ACOMP) +#define pDMA_MISR ((volatile unsigned long *)DMA_MISR) +#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER) +#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT) +#define pDMA_TMODE ((volatile unsigned short *)DMA_TMODE) +#define pDMA_TMCHAN ((volatile unsigned short *)DMA_TMCHAN) +#define pDMA_TMSTAT ((volatile unsigned short *)DMA_TMSTAT) +#define pDMA_TMBD ((volatile unsigned short *)DMA_TMBD) +#define pDMA_TMM0D ((volatile unsigned short *)DMA_TMM0D) +#define pDMA_TMM1D ((volatile unsigned short *)DMA_TMM1D) +#define pDMA_TMMA ((volatile void **)DMA_TMMA) + +/* DMA Controller */ +#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG) +#define pDMA0_NEXT_DESC_PTR ((volatile void **)DMA0_NEXT_DESC_PTR) +#define pDMA0_START_ADDR ((volatile void **)DMA0_START_ADDR) +#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT) +#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT) +#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY) +#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY) +#define pDMA0_CURR_DESC_PTR ((volatile void **)DMA0_CURR_DESC_PTR) +#define pDMA0_CURR_ADDR ((volatile void **)DMA0_CURR_ADDR) +#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT) +#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT) +#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS) +#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP) + +#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG) +#define pDMA1_NEXT_DESC_PTR ((volatile void **)DMA1_NEXT_DESC_PTR) +#define pDMA1_START_ADDR ((volatile void **)DMA1_START_ADDR) +#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT) +#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT) +#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY) +#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY) +#define pDMA1_CURR_DESC_PTR ((volatile void **)DMA1_CURR_DESC_PTR) +#define pDMA1_CURR_ADDR ((volatile void **)DMA1_CURR_ADDR) +#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT) +#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT) +#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS) +#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP) + +#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG) +#define pDMA2_NEXT_DESC_PTR ((volatile void **)DMA2_NEXT_DESC_PTR) +#define pDMA2_START_ADDR ((volatile void **)DMA2_START_ADDR) +#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT) +#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT) +#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY) +#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY) +#define pDMA2_CURR_DESC_PTR ((volatile void **)DMA2_CURR_DESC_PTR) +#define pDMA2_CURR_ADDR ((volatile void **)DMA2_CURR_ADDR) +#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT) +#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT) +#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS) +#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP) + +#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG) +#define pDMA3_NEXT_DESC_PTR ((volatile void **)DMA3_NEXT_DESC_PTR) +#define pDMA3_START_ADDR ((volatile void **)DMA3_START_ADDR) +#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT) +#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT) +#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY) +#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY) +#define pDMA3_CURR_DESC_PTR ((volatile void **)DMA3_CURR_DESC_PTR) +#define pDMA3_CURR_ADDR ((volatile void **)DMA3_CURR_ADDR) +#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT) +#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT) +#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS) +#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP) + +#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG) +#define pDMA4_NEXT_DESC_PTR ((volatile void **)DMA4_NEXT_DESC_PTR) +#define pDMA4_START_ADDR ((volatile void **)DMA4_START_ADDR) +#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT) +#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT) +#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY) +#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY) +#define pDMA4_CURR_DESC_PTR ((volatile void **)DMA4_CURR_DESC_PTR) +#define pDMA4_CURR_ADDR ((volatile void **)DMA4_CURR_ADDR) +#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT) +#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT) +#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS) +#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP) + +#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG) +#define pDMA5_NEXT_DESC_PTR ((volatile void **)DMA5_NEXT_DESC_PTR) +#define pDMA5_START_ADDR ((volatile void **)DMA5_START_ADDR) +#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT) +#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT) +#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY) +#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY) +#define pDMA5_CURR_DESC_PTR ((volatile void **)DMA5_CURR_DESC_PTR) +#define pDMA5_CURR_ADDR ((volatile void **)DMA5_CURR_ADDR) +#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT) +#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT) +#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS) +#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP) + +#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG) +#define pDMA6_NEXT_DESC_PTR ((volatile void **)DMA6_NEXT_DESC_PTR) +#define pDMA6_START_ADDR ((volatile void **)DMA6_START_ADDR) +#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT) +#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT) +#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY) +#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY) +#define pDMA6_CURR_DESC_PTR ((volatile void **)DMA6_CURR_DESC_PTR) +#define pDMA6_CURR_ADDR ((volatile void **)DMA6_CURR_ADDR) +#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT) +#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT) +#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS) +#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP) + +#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG) +#define pDMA7_NEXT_DESC_PTR ((volatile void **)DMA7_NEXT_DESC_PTR) +#define pDMA7_START_ADDR ((volatile void **)DMA7_START_ADDR) +#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT) +#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT) +#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY) +#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY) +#define pDMA7_CURR_DESC_PTR ((volatile void **)DMA7_CURR_DESC_PTR) +#define pDMA7_CURR_ADDR ((volatile void **)DMA7_CURR_ADDR) +#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT) +#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT) +#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS) +#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP) + +#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG) +#define pMDMA_D1_NEXT_DESC_PTR ((volatile void **)MDMA_D1_NEXT_DESC_PTR) +#define pMDMA_D1_START_ADDR ((volatile void **)MDMA_D1_START_ADDR) +#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT) +#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT) +#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY) +#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY) +#define pMDMA_D1_CURR_DESC_PTR ((volatile void **)MDMA_D1_CURR_DESC_PTR) +#define pMDMA_D1_CURR_ADDR ((volatile void **)MDMA_D1_CURR_ADDR) +#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT) +#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT) +#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS) +#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP) + +#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG) +#define pMDMA_S1_NEXT_DESC_PTR ((volatile void **)MDMA_S1_NEXT_DESC_PTR) +#define pMDMA_S1_START_ADDR ((volatile void **)MDMA_S1_START_ADDR) +#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT) +#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT) +#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY) +#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY) +#define pMDMA_S1_CURR_DESC_PTR ((volatile void **)MDMA_S1_CURR_DESC_PTR) +#define pMDMA_S1_CURR_ADDR ((volatile void **)MDMA_S1_CURR_ADDR) +#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT) +#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT) +#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS) +#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP) + +#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG) +#define pMDMA_D0_NEXT_DESC_PTR ((volatile void **)MDMA_D0_NEXT_DESC_PTR) +#define pMDMA_D0_START_ADDR ((volatile void **)MDMA_D0_START_ADDR) +#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT) +#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT) +#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY) +#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY) +#define pMDMA_D0_CURR_DESC_PTR ((volatile void **)MDMA_D0_CURR_DESC_PTR) +#define pMDMA_D0_CURR_ADDR ((volatile void **)MDMA_D0_CURR_ADDR) +#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT) +#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT) +#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS) +#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP) + +#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG) +#define pMDMA_S0_NEXT_DESC_PTR ((volatile void **)MDMA_S0_NEXT_DESC_PTR) +#define pMDMA_S0_START_ADDR ((volatile void **)MDMA_S0_START_ADDR) +#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT) +#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT) +#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY) +#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY) +#define pMDMA_S0_CURR_DESC_PTR ((volatile void **)MDMA_S0_CURR_DESC_PTR) +#define pMDMA_S0_CURR_ADDR ((volatile void **)MDMA_S0_CURR_ADDR) +#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT) +#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT) +#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS) +#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP) + +/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */ +#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL) +#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0) +#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1) + +/* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */ +/* #define L1SBAR 0xFFC04840 */ /* L1 SRAM Base Address Register */ +/* #define L1CSR 0xFFC04844 */ /* L1 SRAM Control Initialization Register */ + +/* + * #define pDB_ACOMP ((volatile void **)DB_ACOMP) + * #define pDB_CCOMP ((volatile unsigned long *)DB_CCOMP) + */ + +/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */ +#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL) +#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC) +#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT) +#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL) + +/* UART Controller */ +#define pUART_THR ((volatile unsigned short *)UART_THR) +#define pUART_RBR ((volatile unsigned short *)UART_RBR) +#define pUART_DLL ((volatile unsigned short *)UART_DLL) +#define pUART_IER ((volatile unsigned short *)UART_IER) +#define pUART_DLH ((volatile unsigned short *)UART_DLH) +#define pUART_IIR ((volatile unsigned short *)UART_IIR) +#define pUART_LCR ((volatile unsigned short *)UART_LCR) +#define pUART_MCR ((volatile unsigned short *)UART_MCR) +#define pUART_LSR ((volatile unsigned short *)UART_LSR) + +/* + * #define UART_MSR + */ +#define pUART_SCR ((volatile unsigned short *)UART_SCR) +#define pUART_GCTL ((volatile unsigned short *)UART_GCTL) + +/* SPI Controller */ +#define pSPI_CTL ((volatile unsigned short *)SPI_CTL) +#define pSPI_FLG ((volatile unsigned short *)SPI_FLG) +#define pSPI_STAT ((volatile unsigned short *)SPI_STAT) +#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR) +#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR) +#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD) +#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW) + +/* TIMER 0, 1, 2 Registers */ +#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG) +#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER) +#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD) +#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH) + +#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG) +#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER) +#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD) +#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH) + +#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG) +#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER) +#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD) +#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH) + +#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE) +#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE) +#define pTIMER_STATUS ((volatile unsigned short *)TIMER_STATUS) + +/* SPORT0 Controller */ +#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1) +#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2) +#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV) +#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV) +#define pSPORT0_TX ((volatile long *)SPORT0_TX) +#define pSPORT0_RX ((volatile long *)SPORT0_RX) +#define pSPORT0_TX32 ((volatile long *)SPORT0_TX) +#define pSPORT0_RX32 ((volatile long *)SPORT0_RX) +#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX) +#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX) +#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1) +#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2) +#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV) +#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV) +#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT) +#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL) +#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1) +#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2) +#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0) +#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1) +#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2) +#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3) +#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0) +#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1) +#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2) +#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3) + +/* SPORT1 Controller */ +#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1) +#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2) +#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV) +#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV) +#define pSPORT1_TX ((volatile long *)SPORT1_TX) +#define pSPORT1_RX ((volatile long *)SPORT1_RX) +#define pSPORT1_TX32 ((volatile long *)SPORT1_TX) +#define pSPORT1_RX32 ((volatile long *)SPORT1_RX) +#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX) +#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX) +#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1) +#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2) +#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV) +#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV) +#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT) +#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL) +#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1) +#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2) +#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0) +#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1) +#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2) +#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3) +#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0) +#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1) +#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2) +#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3) + +/* Parallel Peripheral Interface (PPI) */ +#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL) +#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS) +#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY) +#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT) +#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME) + +#endif /* _CDEF_BF532_H */ diff --git a/include/asm-blackfin/cpu/cdefBF533.h b/include/asm-blackfin/cpu/cdefBF533.h new file mode 100644 index 0000000..8c751e6 --- /dev/null +++ b/include/asm-blackfin/cpu/cdefBF533.h @@ -0,0 +1,24 @@ +/* + * cdefBF533.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _CDEFBF533_H +#define _CDEFBF533_H + +#include <asm/cpu/cdefBF532.h> + +#endif /* _CDEFBF533_H */ diff --git a/include/asm-blackfin/cpu/cdefBF53x.h b/include/asm-blackfin/cpu/cdefBF53x.h new file mode 100644 index 0000000..db4eaa9 --- /dev/null +++ b/include/asm-blackfin/cpu/cdefBF53x.h @@ -0,0 +1,32 @@ +/************************************************************************ + * + * cdefBF53x.h + * + * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved. + * + ************************************************************************/ + +#ifndef _CDEFBF53x_H +#define _CDEFBF53x_H + +#if defined(__ADSPBF531__) + #include <asm/cpu/cdefBF531.h> +#elif defined(__ADSPBF532__) + #include <asm/cpu/cdefBF532.h> +#elif defined(__ADSPBF533__) + #include <asm/cpu/cdefBF533.h> +#elif defined(__ADSPBF561__) + #include <asm/cpu/cdefBF561.h> +#elif defined(__ADSPBF535__) + #include <asm/cpu/cdefBF535.h> +#elif defined(__AD6532__) + #include <sam/cpu/cdefAD6532.h> +#else + #if defined(__ADSPLPBLACKFIN__) + #include <asm/cpu/cdefBF532.h> + #else + #include <asm/cpu/cdefBF535.h> + #endif +#endif + +#endif /* _CDEFBF53x_H */ diff --git a/include/asm-blackfin/cpu/cdef_LPBlackfin.h b/include/asm-blackfin/cpu/cdef_LPBlackfin.h new file mode 100644 index 0000000..e6471cb --- /dev/null +++ b/include/asm-blackfin/cpu/cdef_LPBlackfin.h @@ -0,0 +1,185 @@ +/* + * cdef_LPBlackfin.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _CDEF_LPBLACKFIN_H +#define _CDEF_LPBLACKFIN_H + +/* + * #if !defined(__ADSPLPBLACKFIN__) + * #warning cdef_LPBlackfin.h should only be included for 532 compatible chips. + * #endif + */ +#include <asm/cpu/def_LPBlackfin.h> + +/* Cache & SRAM Memory */ +#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS) +#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL) +#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS) +#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR) + +/* #define MMR_TIMEOUT 0xFFE00010 */ /* Memory-Mapped Register Timeout Register */ +#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0) +#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1) +#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2) +#define pDCPLB_ADDR3 ((volatile void **)DCPLB_ADDR3) +#define pDCPLB_ADDR4 ((volatile void **)DCPLB_ADDR4) +#define pDCPLB_ADDR5 ((volatile void **)DCPLB_ADDR5) +#define pDCPLB_ADDR6 ((volatile void **)DCPLB_ADDR6) +#define pDCPLB_ADDR7 ((volatile void **)DCPLB_ADDR7) +#define pDCPLB_ADDR8 ((volatile void **)DCPLB_ADDR8) +#define pDCPLB_ADDR9 ((volatile void **)DCPLB_ADDR9) +#define pDCPLB_ADDR10 ((volatile void **)DCPLB_ADDR10) +#define pDCPLB_ADDR11 ((volatile void **)DCPLB_ADDR11) +#define pDCPLB_ADDR12 ((volatile void **)DCPLB_ADDR12) +#define pDCPLB_ADDR13 ((volatile void **)DCPLB_ADDR13) +#define pDCPLB_ADDR14 ((volatile void **)DCPLB_ADDR14) +#define pDCPLB_ADDR15 ((volatile void **)DCPLB_ADDR15) +#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0) +#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1) +#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2) +#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3) +#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4) +#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5) +#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6) +#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7) +#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8) +#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9) +#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10) +#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11) +#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12) +#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13) +#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14) +#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15) +#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND) + +/* #define DTEST_INDEX 0xFFE00304 */ /* Data Test Index Register */ +#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0) +#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1) + +/* + * # define DTEST_DATA2 0xFFE00408 Data Test Data Register + * #define DTEST_DATA3 0xFFE0040C Data Test Data Register + */ +#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL) +#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS) +#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR) +#define pICPLB_ADDR0 ((volatile void **)ICPLB_ADDR0) +#define pICPLB_ADDR1 ((volatile void **)ICPLB_ADDR1) +#define pICPLB_ADDR2 ((volatile void **)ICPLB_ADDR2) +#define pICPLB_ADDR3 ((volatile void **)ICPLB_ADDR3) +#define pICPLB_ADDR4 ((volatile void **)ICPLB_ADDR4) +#define pICPLB_ADDR5 ((volatile void **)ICPLB_ADDR5) +#define pICPLB_ADDR6 ((volatile void **)ICPLB_ADDR6) +#define pICPLB_ADDR7 ((volatile void **)ICPLB_ADDR7) +#define pICPLB_ADDR8 ((volatile void **)ICPLB_ADDR8) +#define pICPLB_ADDR9 ((volatile void **)ICPLB_ADDR9) +#define pICPLB_ADDR10 ((volatile void **)ICPLB_ADDR10) +#define pICPLB_ADDR11 ((volatile void **)ICPLB_ADDR11) +#define pICPLB_ADDR12 ((volatile void **)ICPLB_ADDR12) +#define pICPLB_ADDR13 ((volatile void **)ICPLB_ADDR13) +#define pICPLB_ADDR14 ((volatile void **)ICPLB_ADDR14) +#define pICPLB_ADDR15 ((volatile void **)ICPLB_ADDR15) +#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0) +#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1) +#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2) +#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3) +#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4) +#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5) +#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6) +#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7) +#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8) +#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9) +#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10) +#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11) +#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12) +#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13) +#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14) +#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15) +#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND) + +/* #define ITEST_INDEX 0xFFE01304 */ /* Instruction Test Index Register */ +#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0) +#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1) + +/* Event/Interrupt Registers */ +#define pEVT0 ((volatile void **)EVT0) +#define pEVT1 ((volatile void **)EVT1) +#define pEVT2 ((volatile void **)EVT2) +#define pEVT3 ((volatile void **)EVT3) +#define pEVT4 ((volatile void **)EVT4) +#define pEVT5 ((volatile void **)EVT5) +#define pEVT6 ((volatile void **)EVT6) +#define pEVT7 ((volatile void **)EVT7) +#define pEVT8 ((volatile void **)EVT8) +#define pEVT9 ((volatile void **)EVT9) +#define pEVT10 ((volatile void **)EVT10) +#define pEVT11 ((volatile void **)EVT11) +#define pEVT12 ((volatile void **)EVT12) +#define pEVT13 ((volatile void **)EVT13) +#define pEVT14 ((volatile void **)EVT14) +#define pEVT15 ((volatile void **)EVT15) +#define pIMASK ((volatile unsigned long *)IMASK) +#define pIPEND ((volatile unsigned long *)IPEND) +#define pILAT ((volatile unsigned long *)ILAT) + +/* Core Timer Registers */ +#define pTCNTL ((volatile unsigned long *)TCNTL) +#define pTPERIOD ((volatile unsigned long *)TPERIOD) +#define pTSCALE ((volatile unsigned long *)TSCALE) +#define pTCOUNT ((volatile unsigned long *)TCOUNT) + +/* Debug/MP/Emulation Registers */ +#define pDSPID ((volatile unsigned long *)DSPID) +#define pDBGCTL ((volatile unsigned long *)DBGCTL) +#define pDBGSTAT ((volatile unsigned long *)DBGSTAT) +#define pEMUDAT ((volatile unsigned long *)EMUDAT) + +/* Trace Buffer Registers */ +#define pTBUFCTL ((volatile unsigned long *)TBUFCTL) +#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT) +#define pTBUF ((volatile void **)TBUF) + +/* Watch Point Control Registers */ +#define pWPIACTL ((volatile unsigned long *)WPIACTL) +#define pWPIA0 ((volatile void **)WPIA0) +#define pWPIA1 ((volatile void **)WPIA1) +#define pWPIA2 ((volatile void **)WPIA2) +#define pWPIA3 ((volatile void **)WPIA3) +#define pWPIA4 ((volatile void **)WPIA4) +#define pWPIA5 ((volatile void **)WPIA5) +#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0) +#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1) +#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2) +#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3) +#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4) +#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5) +#define pWPDACTL ((volatile unsigned long *)WPDACTL) +#define pWPDA0 ((volatile void **)WPDA0) +#define pWPDA1 ((volatile void **)WPDA1) +#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0) +#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1) +#define pWPSTAT ((volatile unsigned long *)WPSTAT) + +/* Performance Monitor Registers */ +#define pPFCTL ((volatile unsigned long *)PFCTL) +#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0) +#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1) + +/* #define IPRIO 0xFFE02110 */ /* Core Interrupt Priority Register */ + +#endif /* _CDEF_LPBLACKFIN_H */ diff --git a/include/asm-blackfin/cpu/defBF531.h b/include/asm-blackfin/cpu/defBF531.h new file mode 100644 index 0000000..6c7cd5a --- /dev/null +++ b/include/asm-blackfin/cpu/defBF531.h @@ -0,0 +1,24 @@ +/* + * defBF531.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _DEFBF531_H +#define _DEFBF531_H + +#include <defBF532.h> + +#endif /* _DEFBF531_H */ diff --git a/include/asm-blackfin/cpu/defBF532.h b/include/asm-blackfin/cpu/defBF532.h new file mode 100644 index 0000000..26a5fe6 --- /dev/null +++ b/include/asm-blackfin/cpu/defBF532.h @@ -0,0 +1,1159 @@ +/* + * defBF532.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */ + +#ifndef _DEF_BF532_H +#define _DEF_BF532_H + +/* + * #if !defined(__ADSPLPBLACKFIN__) + * #warning defBF532.h should only be included for 532 compatible chips + * #endif + */ + +/* include all Core registers and bit definitions */ +#include <asm/cpu/def_LPBlackfin.h> + +/* Helper macros + * usage: + * P0.H = HI(UART_THR); + * P0.L = LO(UART_THR); + */ + +#define LO(con32) ((con32) & 0xFFFF) +#define lo(con32) ((con32) & 0xFFFF) +#define HI(con32) (((con32) >> 16) & 0xFFFF) +#define hi(con32) (((con32) >> 16) & 0xFFFF) + +/* + * System MMR Register Map + */ + +/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ +#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ +#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ +#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ +#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ +#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ +#define CHIPID 0xFFC00014 /* Chip ID register (32-bit) */ +#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ +#define SYSCR 0xFFC00104 /* System Configuration register */ + +/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ +#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ +#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ +#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ +#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ +#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ + +/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ +#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ +#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ +#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ + +/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ +#define RTC_STAT 0xFFC00300 /* RTC Status Register */ +#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ +#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ +#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ +#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ +#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ +#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ + +/* UART Controller (0xFFC00400 - 0xFFC004FF) */ +#define UART_THR 0xFFC00400 /* Transmit Holding register */ +#define UART_RBR 0xFFC00400 /* Receive Buffer register */ +#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ +#define UART_IER 0xFFC00404 /* Interrupt Enable Register */ +#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ +#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ +#define UART_LCR 0xFFC0040C /* Line Control Register */ +#define UART_MCR 0xFFC00410 /* Modem Control Register */ +#define UART_LSR 0xFFC00414 /* Line Status Register */ +/* #define UART_MSR 0xFFC00418 */ /* Modem Status Register (UNUSED in ADSP-BF532) */ +#define UART_SCR 0xFFC0041C /* SCR Scratch Register */ +#define UART_GCTL 0xFFC00424 /* Global Control Register */ + +/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ +#define SPI_CTL 0xFFC00500 /* SPI Control Register */ +#define SPI_FLG 0xFFC00504 /* SPI Flag register */ +#define SPI_STAT 0xFFC00508 /* SPI Status register */ +#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ +#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ +#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ +#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ + +/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ +#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ +#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ +#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ +#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ + +#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ +#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ +#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ +#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ + +#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ +#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ +#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ +#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ + +#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ +#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ +#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ + +/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */ +#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ +#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ +#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ +#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ +#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ +#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ +#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ +#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ +#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ +#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ +#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ +#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ +#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ +#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ +#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ +#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ +#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ + +/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ +#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ +#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ +#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ +#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ +#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ +#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ +#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ + +/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ +#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ +#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ +#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ +#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ +#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ +#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ +#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ +#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ +#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ +#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ +#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ +#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ +#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ +#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ +#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ +#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ +#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ +#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ + +/* Asynchronous Memory Controller - External Bus Interface Unit */ +#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ +#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ +#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ + +/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ +#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ +#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ +#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ +#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ + +/* DMA Test Registers */ +#define DMA_CCOMP 0xFFC00B04 /* DMA Cycle Count Register */ +#define DMA_ACOMP 0xFFC00B00 /* Debug Compare Address Register */ +#define DMA_MISR 0xFFC00B08 /* MISR Register */ +#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ +#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ +#define DMA_TMODE 0xFFC00B14 /* DMA Test Modes Register */ +#define DMA_TMCHAN 0xFFC00B18 /* DMA Testmode Selected Channel Register */ +#define DMA_TMSTAT 0xFFC00B1C /* DMA Testmode Channel Status Register */ +#define DMA_TMBD 0xFFC00B20 /* DMA Testmode DAB Bus Data Register */ +#define DMA_TMM0D 0xFFC00B24 /* DMA Testmode Mem0 Data Register */ +#define DMA_TMM1D 0xFFC00B28 /* DMA Testmode Mem1 Data Register */ +#define DMA_TMMA 0xFFC00B2C /* DMA Testmode Memory Address Register */ + +/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ +#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ +#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ +#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ +#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ +#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ +#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ +#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ +#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ +#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ +#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ +#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ +#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ +#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ + +#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ +#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ +#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ +#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ +#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ +#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ +#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ +#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ +#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ +#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ +#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ +#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ +#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ + +#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ +#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ +#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ +#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ +#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ +#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ +#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ +#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ +#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ +#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ +#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ +#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ +#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ + +#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ +#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ +#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ +#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ +#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ +#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ +#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ +#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ +#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ +#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ +#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ +#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ +#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ + +#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ +#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ +#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ +#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ +#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ +#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ +#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ +#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ +#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ +#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ +#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ +#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ +#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ + +#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ +#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ +#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ +#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ +#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ +#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ +#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ +#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ +#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ +#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ +#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ +#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ +#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ + +#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ +#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ +#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ +#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ +#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ +#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ +#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ +#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ +#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ +#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ +#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ +#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ +#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ + +#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ +#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ +#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ +#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ +#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ +#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ +#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ +#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ +#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ +#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ +#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ +#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ +#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ + +#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */ +#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ +#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */ +#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */ +#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */ +#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */ +#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */ +#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ +#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */ +#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */ +#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */ +#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ +#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */ + +#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */ +#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ +#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */ +#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */ +#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */ +#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */ +#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */ +#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ +#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */ +#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */ +#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */ +#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ +#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */ + +#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */ +#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ +#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */ +#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */ +#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */ +#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */ +#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */ +#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ +#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */ +#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */ +#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */ +#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ +#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */ + +#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */ +#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ +#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */ +#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */ +#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */ +#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */ +#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */ +#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ +#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */ +#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */ +#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */ +#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */ +#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */ + +/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ +#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ +#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ +#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ +#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ +#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ + +/* + * System MMR Register Bits + */ +/* + * PLL AND RESET MASKS + */ + +/* PLL_CTL Masks */ +#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */ +#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */ +#define PLL_OFF 0x00000002 /* Shut off PLL clocks */ +#define STOPCK_OFF 0x00000008 /* Core clock off */ +#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */ +#define BYPASS 0x00000100 /* Bypass the PLL */ + +/* PLL_DIV Masks */ +#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ + +#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ + +/* SWRST Mask */ +#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */ + +/* + * SYSTEM INTERRUPT CONTROLLER MASKS + */ + +/* SIC_IAR0 Masks */ +#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */ +#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ +#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ +#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */ +#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ +#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ +#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ +#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ + +/* SIC_IAR1 Masks */ +#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */ +#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ +#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ +#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */ +#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ +#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ +#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ +#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ + +/* SIC_IAR2 Masks */ +#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */ +#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ +#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ +#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */ +#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ +#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ +#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ +#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ + +/* SIC_IMASK Masks */ +#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ +#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ +#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ +#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ + +/* SIC_IWR Masks */ +#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ +#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ +#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ +#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ + +/* + * WATCHDOG TIMER MASKS + */ +/* Watchdog Timer WDOG_CTL Register */ +#define ICTL(x) ((x<<1) & 0x0006) +#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */ +#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */ +#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */ +#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */ + +#define TMR_EN 0x0000 +#define TMR_DIS 0x0AD0 +#define TRO 0x8000 + +#define ICTL_P0 0x01 +#define ICTL_P1 0x02 +#define TRO_P 0x0F + +/* RTC_STAT and RTC_ALARM register */ +#define RTSEC 0x0000003F /* Real-Time Clock Seconds */ +#define RTMIN 0x00000FC0 /* Real-Time Clock Minutes */ +#define RTHR 0x0001F000 /* Real-Time Clock Hours */ +#define RTDAY 0xFFFE0000 /* Real-Time Clock Days */ + +/* RTC_ICTL register */ +#define SWIE 0x0001 /* Stopwatch Interrupt Enable */ +#define AIE 0x0002 /* Alarm Interrupt Enable */ +#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */ +#define MIE 0x0008 /* Minutes Interrupt Enable */ +#define HIE 0x0010 /* Hours Interrupt Enable */ +#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */ +#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ +#define WCIE 0x8000 /* Write Complete Interrupt Enable */ + +/* RTC_ISTAT register */ +#define SWEF 0x0001 /* Stopwatch Event Flag */ +#define AEF 0x0002 /* Alarm Event Flag */ +#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */ +#define MEF 0x0008 /* Minutes Event Flag */ +#define HEF 0x0010 /* Hours Event Flag */ +#define DEF 0x0020 /* 24 Hours (Days) Event Flag */ +#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */ +#define WPS 0x4000 /* Write Pending Status (RO) */ +#define WCOM 0x8000 /* Write Complete */ + +/* RTC_FAST Mask (RTC_PREN Mask) */ +#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */ +#define PREN 0x00000001 /* ** Must be set after power-up for proper operation of RTC */ + +/* + * UART CONTROLLER MASKS + */ + +/* UART_LCR Register */ +#define DLAB 0x80 +#define SB 0x40 +#define STP 0x20 +#define EPS 0x10 +#define PEN 0x08 +#define STB 0x04 +#define WLS(x) ((x-5) & 0x03) + +#define DLAB_P 0x07 +#define SB_P 0x06 +#define STP_P 0x05 +#define EPS_P 0x04 +#define PEN_P 0x03 +#define STB_P 0x02 +#define WLS_P1 0x01 +#define WLS_P0 0x00 + +/* UART_MCR Register */ +#define LOOP_ENA 0x10 +#define LOOP_ENA_P 0x04 + +/* UART_LSR Register */ +#define TEMT 0x40 +#define THRE 0x20 +#define BI 0x10 +#define FE 0x08 +#define PE 0x04 +#define OE 0x02 +#define DR 0x01 + +#define TEMP_P 0x06 +#define THRE_P 0x05 +#define BI_P 0x04 +#define FE_P 0x03 +#define PE_P 0x02 +#define OE_P 0x01 +#define DR_P 0x00 + +/* UART_IER Register */ +#define ELSI 0x04 +#define ETBEI 0x02 +#define ERBFI 0x01 + +#define ELSI_P 0x02 +#define ETBEI_P 0x01 +#define ERBFI_P 0x00 + +/* UART_IIR Register */ +#define STATUS(x) ((x << 1) & 0x06) +#define NINT 0x01 +#define STATUS_P1 0x02 +#define STATUS_P0 0x01 +#define NINT_P 0x00 + +/* UART_GCTL Register */ +#define FFE 0x20 +#define FPE 0x10 +#define RPOLC 0x08 +#define TPOLC 0x04 +#define IREN 0x02 +#define UCEN 0x01 + +#define FFE_P 0x05 +#define FPE_P 0x04 +#define RPOLC_P 0x03 +#define TPOLC_P 0x02 +#define IREN_P 0x01 +#define UCEN_P 0x00 + +/* + * SERIAL PORT MASKS + */ +/* SPORTx_TCR1 Masks */ +#define TSPEN 0x0001 /* TX enable */ +#define ITCLK 0x0002 /* Internal TX Clock Select */ +#define TDTYPE 0x000C /* TX Data Formatting Select */ +#define TLSBIT 0x0010 /* TX Bit Order */ +#define ITFS 0x0200 /* Internal TX Frame Sync Select */ +#define TFSR 0x0400 /* TX Frame Sync Required Select */ +#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ +#define LTFS 0x1000 /* Low TX Frame Sync Select */ +#define LATFS 0x2000 /* Late TX Frame Sync Select */ +#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ + +/* SPORTx_TCR2 Masks */ +#define SLEN 0x001F /*TX Word Length */ +#define TXSE 0x0100 /*TX Secondary Enable */ +#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */ +#define TRFST 0x0400 /*TX Right-First Data Order */ + +/* SPORTx_RCR1 Masks */ +#define RSPEN 0x0001 /* RX enable */ +#define IRCLK 0x0002 /* Internal RX Clock Select */ +#define RDTYPE 0x000C /* RX Data Formatting Select */ +#define RULAW 0x0008 /* u-Law enable */ +#define RALAW 0x000C /* A-Law enable */ +#define RLSBIT 0x0010 /* RX Bit Order */ +#define IRFS 0x0200 /* Internal RX Frame Sync Select */ +#define RFSR 0x0400 /* RX Frame Sync Required Select */ +#define LRFS 0x1000 /* Low RX Frame Sync Select */ +#define LARFS 0x2000 /* Late RX Frame Sync Select */ +#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ + +/* SPORTx_RCR2 Masks */ +#define SLEN 0x001F /* RX Word Length */ +#define RXSE 0x0100 /* RX Secondary Enable */ +#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ +#define RRFST 0x0400 /* Right-First Data Order */ + +/* SPORTx_STAT Masks */ +#define RXNE 0x0001 /* RX FIFO Not Empty Status */ +#define RUVF 0x0002 /* RX Underflow Status */ +#define ROVF 0x0004 /* RX Overflow Status */ +#define TXF 0x0008 /* TX FIFO Full Status */ +#define TUVF 0x0010 /* TX Underflow Status */ +#define TOVF 0x0020 /* TX Overflow Status */ +#define TXHRE 0x0040 /* TX Hold Register Empty */ + +/* SPORTx_MCMC1 Masks */ +#define WSIZE 0x0000F000 /* Multichannel Window Size Field */ +#define WOFF 0x000003FF /* /Multichannel Window Offset Field */ + +/* SPORTx_MCMC2 Masks */ +#define MCCRM 0x00000003 /* Multichannel Clock Recovery Mode */ +#define MCDTXPE 0x00000004 /* Multichannel DMA Transmit Packing */ +#define MCDRXPE 0x00000008 /* Multichannel DMA Receive Packing */ +#define MCMEN 0x00000010 /* Multichannel Frame Mode Enable */ +#define FSDR 0x00000080 /* Multichannel Frame Sync to Data Relationship */ +#define MFD 0x0000F000 /* Multichannel Frame Delay */ + +/* + * PARALLEL PERIPHERAL INTERFACE (PPI) MASKS + */ + +/* PPI_CONTROL Masks */ +#define PORT_EN 0x00000001 /* PPI Port Enable */ +#define PORT_DIR 0x00000002 /* PPI Port Direction */ +#define XFR_TYPE 0x0000000C /* PPI Transfer Type */ +#define PORT_CFG 0x00000030 /* PPI Port Configuration */ +#define FLD_SEL 0x00000040 /* PPI Active Field Select */ +#define PACK_EN 0x00000080 /* PPI Packing Mode */ +#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ +#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ +#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ +#define DLENGTH 0x00003800 /* PPI Data Length */ +#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ +#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ +#define POL 0x0000C000 /* PPI Signal Polarities */ + +/* PPI_STATUS Masks */ +#define FLD 0x00000400 /* Field Indicator */ +#define FT_ERR 0x00000800 /* Frame Track Error */ +#define OVR 0x00001000 /* FIFO Overflow Error */ +#define UNDR 0x00002000 /* FIFO Underrun Error */ +#define ERR_DET 0x00004000 /* Error Detected Indicator */ +#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */ + +/* + * DMA CONTROLLER MASKS + */ + +/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ +#define DMAEN 0x00000001 /* Channel Enable */ +#define WNR 0x00000002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x00000000 /* Word Size 8 bits */ +#define WDSIZE_16 0x00000004 /* Word Size 16 bits */ +#define WDSIZE_32 0x00000008 /* Word Size 32 bits */ +#define DMA2D 0x00000010 /* 2D/1D* Mode */ +#define RESTART 0x00000020 /* Restart */ +#define DI_SEL 0x00000040 /* Data Interrupt Select */ +#define DI_EN 0x00000080 /* Data Interrupt Enable */ +#define NDSIZE 0x00000900 /* Next Descriptor Size */ +#define FLOW 0x00007000 /* Flow Control */ + +#define DMAEN_P 0 /* Channel Enable */ +#define WNR_P 1 /* Channel Direction (W/R*) */ +#define DMA2D_P 4 /* 2D/1D* Mode */ +#define RESTART_P 5 /* Restart */ +#define DI_SEL_P 6 /* Data Interrupt Select */ +#define DI_EN_P 7 /* Data Interrupt Enable */ + +/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ +#define DMA_DONE 0x00000001 /* DMA Done Indicator */ +#define DMA_ERR 0x00000002 /* DMA Error Indicator */ +#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ +#define DMA_RUN 0x00000008 /* DMA Running Indicator */ + +#define DMA_DONE_P 0 /* DMA Done Indicator */ +#define DMA_ERR_P 1 /* DMA Error Indicator */ +#define DFETCH_P 2 /* Descriptor Fetch Indicator */ +#define DMA_RUN_P 3 /* DMA Running Indicator */ + +/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ +#define CTYPE 0x00000040 /* DMA Channel Type Indicator */ +#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ +#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */ +#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */ +#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */ +#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */ +#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ +#define PMAP 0x00007000 /* DMA Peripheral Map Field */ + +/* + * GENERAL PURPOSE TIMER MASKS + */ + +/* PWM Timer bit definitions */ + +/* TIMER_ENABLE Register */ +#define TIMEN0 0x0001 +#define TIMEN1 0x0002 +#define TIMEN2 0x0004 + +#define TIMEN0_P 0x00 +#define TIMEN1_P 0x01 +#define TIMEN2_P 0x02 + +/* TIMER_DISABLE Register */ +#define TIMDIS0 0x0001 +#define TIMDIS1 0x0002 +#define TIMDIS2 0x0004 + +#define TIMDIS0_P 0x00 +#define TIMDIS1_P 0x01 +#define TIMDIS2_P 0x02 + +/* TIMER_STATUS Register */ +#define TIMIL0 0x0001 +#define TIMIL1 0x0002 +#define TIMIL2 0x0004 +#define TOVL_ERR0 0x0010 +#define TOVL_ERR1 0x0020 +#define TOVL_ERR2 0x0040 +#define TRUN0 0x1000 +#define TRUN1 0x2000 +#define TRUN2 0x4000 + +#define TIMIL0_P 0x00 +#define TIMIL1_P 0x01 +#define TIMIL2_P 0x02 +#define TOVL_ERR0_P 0x04 +#define TOVL_ERR1_P 0x05 +#define TOVL_ERR2_P 0x06 +#define TRUN0_P 0x0C +#define TRUN1_P 0x0D +#define TRUN2_P 0x0E + +/* TIMERx_CONFIG Registers */ +#define PWM_OUT 0x0001 +#define WDTH_CAP 0x0002 +#define EXT_CLK 0x0003 +#define PULSE_HI 0x0004 +#define PERIOD_CNT 0x0008 +#define IRQ_ENA 0x0010 +#define TIN_SEL 0x0020 +#define OUT_DIS 0x0040 +#define CLK_SEL 0x0080 +#define TOGGLE_HI 0x0100 +#define EMU_RUN 0x0200 +#define ERR_TYP(x) ((x & 0x03) << 14) + +#define TMODE_P0 0x00 +#define TMODE_P1 0x01 +#define PULSE_HI_P 0x02 +#define PERIOD_CNT_P 0x03 +#define IRQ_ENA_P 0x04 +#define TIN_SEL_P 0x05 +#define OUT_DIS_P 0x06 +#define CLK_SEL_P 0x07 +#define TOGGLE_HI_P 0x08 +#define EMU_RUN_P 0x09 +#define ERR_TYP_P0 0x0E +#define ERR_TYP_P1 0x0F + +/* + * PROGRAMMABLE FLAG MASKS + */ + +/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ +#define PF0 0x0001 +#define PF1 0x0002 +#define PF2 0x0004 +#define PF3 0x0008 +#define PF4 0x0010 +#define PF5 0x0020 +#define PF6 0x0040 +#define PF7 0x0080 +#define PF8 0x0100 +#define PF9 0x0200 +#define PF10 0x0400 +#define PF11 0x0800 +#define PF12 0x1000 +#define PF13 0x2000 +#define PF14 0x4000 +#define PF15 0x8000 + +/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ +#define PF0_P 0 +#define PF1_P 1 +#define PF2_P 2 +#define PF3_P 3 +#define PF4_P 4 +#define PF5_P 5 +#define PF6_P 6 +#define PF7_P 7 +#define PF8_P 8 +#define PF9_P 9 +#define PF10_P 10 +#define PF11_P 11 +#define PF12_P 12 +#define PF13_P 13 +#define PF14_P 14 +#define PF15_P 15 + +/* + * SERIAL PERIPHERAL INTERFACE (SPI) MASKS + */ + +/* SPI_CTL Masks */ +#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ +#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ +#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ +#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ +#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ +#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ +#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ +#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ +#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ +#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ +#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ +#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ + +/* SPI_FLG Masks */ +#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ +#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ + +/* SPI_FLG Bit Positions */ +#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ +#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ + +/* SPI_STAT Masks */ +#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ +#define MODF 0x00000002 /* Set(=1)in a master device when some other device tries to become master */ +#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ +#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ +#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ +#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ +#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ + +/* + * ASYNCHRONOUS MEMORY CONTROLLER MASKS + */ + +/* AMGCTL Masks */ +#define AMCKEN 0x00000001 /* Enable CLKOUT */ +#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */ +#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */ +#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ +#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ + +/* AMGCTL Bit Positions */ +#define AMCKEN_P 0x00000000 /* Enable CLKOUT */ +#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ +#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ +#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ + +/* AMBCTL0 Masks */ +#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ +#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ +#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ +#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ +#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ +#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ +#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ +#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ +#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ +#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ +#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ +#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ +#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ +#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ +#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ +#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ +#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ +#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ +#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ +#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ +#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ +#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ +#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ +#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ +#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ +#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ +#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ +#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ +#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ +#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ +#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ +#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ +#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ +#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ +#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ +#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ +#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ +#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ +#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ +#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ +#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ +#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ +#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ +#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ +#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ +#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ +#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ +#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ +#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ +#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ +#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ +#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ +#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ +#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ +#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ +#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ +#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ +#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ +#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ +#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ +#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ +#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ +#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ +#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ +#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ +#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ +#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ +#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ +#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ +#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ +#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ +#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ +#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ +#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ +#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ +#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ +#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ +#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ +#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ +#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ +#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ +#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ +#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ +#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ +#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ +#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ +#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ +#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ + +/* AMBCTL1 Masks */ +#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ +#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ +#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ +#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ +#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ +#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ +#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ +#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ +#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ +#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ +#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ +#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ +#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ +#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ +#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ +#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ +#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ +#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ +#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ +#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ +#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ +#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ +#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ +#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ +#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ +#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ +#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ +#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ +#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ +#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ +#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ +#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ +#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ +#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ +#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ +#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ +#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ +#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ +#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ +#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ +#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ +#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ +#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ +#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ +#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ +#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ +#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ +#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ +#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ +#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ +#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ +#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ +#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ +#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ +#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ +#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ +#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ +#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ +#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ +#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ +#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ +#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ +#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ +#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ +#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ +#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ +#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ +#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ +#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ +#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ +#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ +#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ +#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ +#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ +#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ +#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ +#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ +#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ +#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ +#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ +#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ +#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ +#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ +#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ +#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ +#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ +#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ +#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ + +/* + * SDRAM CONTROLLER MASKS + */ + +/* SDGCTL Masks */ +#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ +#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ +#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ +#define PFE 0x00000010 /* Enable SDRAM prefetch */ +#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ +#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ +#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ +#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ +#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ +#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ +#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ +#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ +#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ +#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ +#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ +#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ +#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ +#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ +#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ +#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ +#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ +#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ +#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ +#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ +#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ +#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ +#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ +#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ +#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ +#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ +#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ +#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ +#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ +#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ +#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ +#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ +#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ +#define PUPSD 0x00200000 /* Power-up start delay */ +#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ +#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ +#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ +#define EBUFE 0x02000000 /* Enable external buffering timing */ +#define FBBRW 0x04000000 /* Fast back-to-back read write enable */ +#define EMREN 0x10000000 /* Extended mode register enable */ +#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ +#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ + +/* EBIU_SDBCTL Masks */ +#define EBE 0x00000001 /* Enable SDRAM external bank */ +#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ +#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ +#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ +#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ +#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ +#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ +#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ +#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ + +/* EBIU_SDSTAT Masks */ +#define SDCI 0x00000001 /* SDRAM controller is idle */ +#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ +#define SDPUA 0x00000004 /* SDRAM power up active */ +#define SDRS 0x00000008 /* SDRAM is in reset state */ +#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ +#define BGSTAT 0x00000020 /* Bus granted */ + +#endif /* _DEF_BF532_H */ diff --git a/include/asm-blackfin/cpu/defBF533.h b/include/asm-blackfin/cpu/defBF533.h new file mode 100644 index 0000000..90e50af --- /dev/null +++ b/include/asm-blackfin/cpu/defBF533.h @@ -0,0 +1,24 @@ +/* + * defBF533.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _DEFBF533_H +#define _DEFBF533_H + +#include <asm/cpu/defBF532.h> + +#endif /* _DEFBF533_H */ diff --git a/include/asm-blackfin/cpu/defBF533_extn.h b/include/asm-blackfin/cpu/defBF533_extn.h new file mode 100644 index 0000000..a9a1c7c --- /dev/null +++ b/include/asm-blackfin/cpu/defBF533_extn.h @@ -0,0 +1,76 @@ +/* + * defBF533_extn.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _DEF_BF533_EXTN_H +#define _DEF_BF533_EXTN_H + +#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */ +/* Delay inserted for PLL transition */ +#define DELAY 0x1000 + +#define L1_ISRAM 0xFFA00000 +#define L1_ISRAM_END 0xFFA10000 +#define DATA_BANKA_SRAM 0xFF800000 +#define DATA_BANKA_SRAM_END 0xFF808000 +#define DATA_BANKB_SRAM 0xFF900000 +#define DATA_BANKB_SRAM_END 0xFF908000 +#define SYSMMR_BASE 0xFFC00000 +#define WDSIZE16 0x00000004 + +/* Event Vector Table Address */ +#define EVT_EMULATION_ADDR 0xffe02000 +#define EVT_RESET_ADDR 0xffe02004 +#define EVT_NMI_ADDR 0xffe02008 +#define EVT_EXCEPTION_ADDR 0xffe0200c +#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010 +#define EVT_HARDWARE_ERROR_ADDR 0xffe02014 +#define EVT_TIMER_ADDR 0xffe02018 +#define EVT_IVG7_ADDR 0xffe0201c +#define EVT_IVG8_ADDR 0xffe02020 +#define EVT_IVG9_ADDR 0xffe02024 +#define EVT_IVG10_ADDR 0xffe02028 +#define EVT_IVG11_ADDR 0xffe0202c +#define EVT_IVG12_ADDR 0xffe02030 +#define EVT_IVG13_ADDR 0xffe02034 +#define EVT_IVG14_ADDR 0xffe02038 +#define EVT_IVG15_ADDR 0xffe0203c +#define EVT_OVERRIDE_ADDR 0xffe02100 + +/* IMASK Bit values */ +#define IVG15_POS 0x00008000 +#define IVG14_POS 0x00004000 +#define IVG13_POS 0x00002000 +#define IVG12_POS 0x00001000 +#define IVG11_POS 0x00000800 +#define IVG10_POS 0x00000400 +#define IVG9_POS 0x00000200 +#define IVG8_POS 0x00000100 +#define IVG7_POS 0x00000080 +#define IVGTMR_POS 0x00000040 +#define IVGHW_POS 0x00000020 + +#define WDOG_TMR_DISABLE (0xAD << 4) +#define ICTL_RST 0x00000000 +#define ICTL_NMI 0x00000002 +#define ICTL_GP 0x00000004 +#define ICTL_DISABLE 0x00000003 + +/* Watch Dog timer values setup */ +#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE + +#endif /* _DEF_BF533_EXTN_H */ diff --git a/include/asm-blackfin/cpu/def_LPBlackfin.h b/include/asm-blackfin/cpu/def_LPBlackfin.h new file mode 100644 index 0000000..9ac78c8 --- /dev/null +++ b/include/asm-blackfin/cpu/def_LPBlackfin.h @@ -0,0 +1,445 @@ +/* + * def_LPBlackfin.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */ + +#ifndef _DEF_LPBLACKFIN_H +#define _DEF_LPBLACKFIN_H + +/* + * #if !defined(__ADSPLPBLACKFIN__) + * #warning def_LPBlackfin.h should only be included for 532 compatible chips. + * #endif + */ + +#define MK_BMSK_( x ) (1<<x) /* Make a bit mask from a bit position */ + +/* + * System Register Bits + */ + +/* + * ASTAT register + */ + +/* definitions of ASTAT bit positions */ +#define ASTAT_AZ_P 0x00000000 /* Result of last ALU0 or shifter operation is zero */ +#define ASTAT_AN_P 0x00000001 /* Result of last ALU0 or shifter operation is negative */ +#define ASTAT_CC_P 0x00000005 /* Condition Code, used for holding comparison results */ +#define ASTAT_AQ_P 0x00000006 /* Quotient Bit */ +#define ASTAT_RND_MOD_P 0x00000008 /* Rounding mode, set for biased, clear for unbiased */ +#define ASTAT_AC0_P 0x0000000C /* Result of last ALU0 operation generated a carry */ +#define ASTAT_AC0_COPY_P 0x00000002 /* Result of last ALU0 operation generated a carry */ +#define ASTAT_AC1_P 0x0000000D /* Result of last ALU1 operation generated a carry */ +#define ASTAT_AV0_P 0x00000010 /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */ +#define ASTAT_AV0S_P 0x00000011 /* Sticky version of ASTAT_AV0 */ +#define ASTAT_AV1_P 0x00000012 /* Result of last MAC1 operation overflowed, sticky for MAC */ +#define ASTAT_AV1S_P 0x00000013 /* Sticky version of ASTAT_AV1 */ +#define ASTAT_V_P 0x00000018 /* Result of last ALU0 or MAC0 operation overflowed */ +#define ASTAT_V_COPY_P 0x00000003 /* Result of last ALU0 or MAC0 operation overflowed */ +#define ASTAT_VS_P 0x00000019 /* Sticky version of ASTAT_V */ + +/* ** Masks */ +#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P) /* Result of last ALU0 or shifter operation is zero */ +#define ASTAT_AN MK_BMSK_(ASTAT_AN_P) /* Result of last ALU0 or shifter operation is negative */ +#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P) /* Result of last ALU0 operation generated a carry */ +#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P) /* Result of last ALU0 operation generated a carry */ +#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P) /* Result of last ALU0 operation generated a carry */ +#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P) /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */ +#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P) /* Result of last MAC1 operation overflowed, sticky for MAC */ +#define ASTAT_CC MK_BMSK_(ASTAT_CC_P) /* Condition Code, used for holding comparison results */ +#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P) /* Quotient Bit */ +#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P) /* Rounding mode, set for biased, clear for unbiased */ +#define ASTAT_V MK_BMSK_(ASTAT_V_P) /* Overflow Bit */ +#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P) /* Overflow Bit */ + +/* + * SEQSTAT register + */ + +/* ** Bit Positions */ +#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */ +#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */ +#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */ +#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */ +#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */ +#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */ +#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request, set by IDLE instruction */ +#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last reset was a software reset (=1) */ +#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */ +#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */ +#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */ +#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */ +#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */ +#define SEQSTAT_HWERRCAUSE5_P 0x00000013 /* Last hw error cause bit 5 */ +#define SEQSTAT_HWERRCAUSE6_P 0x00000014 /* Last hw error cause bit 6 */ +#define SEQSTAT_HWERRCAUSE7_P 0x00000015 /* Last hw error cause bit 7 */ + +/* ** Masks */ +/* Exception cause */ +#define SEQSTAT_EXCAUSE MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \ + MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \ + MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \ + MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \ + MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \ + MK_BMSK_(SEQSTAT_EXCAUSE5_P ) | \ + 0 + +/* Indicates whether the last reset was a software reset (=1) */ +#define SEQSTAT_SFTRESET MK_BMSK_(SEQSTAT_SFTRESET_P ) + +/* Last hw error cause */ +#define SEQSTAT_HWERRCAUSE MK_BMSK_(SEQSTAT_HWERRCAUSE0_P ) | \ + MK_BMSK_(SEQSTAT_HWERRCAUSE1_P ) | \ + MK_BMSK_(SEQSTAT_HWERRCAUSE2_P ) | \ + MK_BMSK_(SEQSTAT_HWERRCAUSE3_P ) | \ + MK_BMSK_(SEQSTAT_HWERRCAUSE4_P ) | \ + 0 + +/* + * SYSCFG register + */ + +/* ** Bit Positions */ +#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when set it forces an exception for each instruction executed */ +#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */ +#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */ + +/* ** Masks */ +#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P) /* Supervisor single step, when set it forces an exception for each instruction executed */ +#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P) /* Enable cycle counter (=1) */ +#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P /* Self Nesting Interrupt Enable */ + +/* Backward-compatibility for typos in prior releases */ +#define SYSCFG_SSSSTEP SYSCFG_SSSTEP +#define SYSCFG_CCCEN SYSCFG_CCEN + +/* + * Core MMR Register Map + */ + +/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */ +#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */ +#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ +#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ +#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */ +#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ +#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ +#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ +#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ +#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection Lookaside Buffer 3 */ +#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection Lookaside Buffer 4 */ +#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection Lookaside Buffer 5 */ +#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection Lookaside Buffer 6 */ +#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection Lookaside Buffer 7 */ +#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection Lookaside Buffer 8 */ +#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection Lookaside Buffer 9 */ +#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection Lookaside Buffer 10 */ +#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection Lookaside Buffer 11 */ +#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection Lookaside Buffer 12 */ +#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection Lookaside Buffer 13 */ +#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection Lookaside Buffer 14 */ +#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection Lookaside Buffer 15 */ +#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ +#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ +#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ +#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ +#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ +#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ +#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ +#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ +#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ +#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ +#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ +#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ +#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ +#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ +#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ +#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ +#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ +#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ +#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ + +/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */ +#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ +#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */ +#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */ +#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */ +#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */ +#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ +#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ +#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ +#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ +#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ +#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ +#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ +#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ +#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ +#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ +#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ +#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ +#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ +#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ +#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ +#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ +#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ +#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ +#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ +#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ +#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ +#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ +#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ +#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ +#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ +#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ +#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ +#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ +#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ +#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ +#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ +#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ +#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ +#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ +#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ + +/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */ +#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ +#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ +#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ +#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ +#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ +#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ +#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ +#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ +#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ +#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ +#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ +#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ +#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ +#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ +#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ +#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ +#define IMASK 0xFFE02104 /* Interrupt Mask Register */ +#define IPEND 0xFFE02108 /* Interrupt Pending Register */ +#define ILAT 0xFFE0210C /* Interrupt Latch Register */ +#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */ + +/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */ +#define TCNTL 0xFFE03000 /* Core Timer Control Register */ +#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ +#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ +#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ + +/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */ +#define DSPID 0xFFE05000 /* DSP Processor ID Register for MP implementations */ +#define DBGSTAT 0xFFE05008 /* Debug Status Register */ + +/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */ +#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ +#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ +#define TBUF 0xFFE06100 /* Trace Buffer */ + +/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */ +#define WPIACTL 0xFFE07000 /* Watchpoint Instruction Address Control Register */ +#define WPIA0 0xFFE07040 /* Watchpoint Instruction Address Register 0 */ +#define WPIA1 0xFFE07044 /* Watchpoint Instruction Address Register 1 */ +#define WPIA2 0xFFE07048 /* Watchpoint Instruction Address Register 2 */ +#define WPIA3 0xFFE0704C /* Watchpoint Instruction Address Register 3 */ +#define WPIA4 0xFFE07050 /* Watchpoint Instruction Address Register 4 */ +#define WPIA5 0xFFE07054 /* Watchpoint Instruction Address Register 5 */ +#define WPIACNT0 0xFFE07080 /* Watchpoint Instruction Address Count Register 0 */ +#define WPIACNT1 0xFFE07084 /* Watchpoint Instruction Address Count Register 1 */ +#define WPIACNT2 0xFFE07088 /* Watchpoint Instruction Address Count Register 2 */ +#define WPIACNT3 0xFFE0708C /* Watchpoint Instruction Address Count Register 3 */ +#define WPIACNT4 0xFFE07090 /* Watchpoint Instruction Address Count Register 4 */ +#define WPIACNT5 0xFFE07094 /* Watchpoint Instruction Address Count Register 5 */ +#define WPDACTL 0xFFE07100 /* Watchpoint Data Address Control Register */ +#define WPDA0 0xFFE07140 /* Watchpoint Data Address Register 0 */ +#define WPDA1 0xFFE07144 /* Watchpoint Data Address Register 1 */ +#define WPDACNT0 0xFFE07180 /* Watchpoint Data Address Count Value Register 0 */ +#define WPDACNT1 0xFFE07184 /* Watchpoint Data Address Count Value Register 1 */ +#define WPSTAT 0xFFE07200 /* Watchpoint Status Register */ + +/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */ +#define PFCTL 0xFFE08000 /* Performance Monitor Control Register */ +#define PFCNTR0 0xFFE08100 /* Performance Monitor Counter Register 0 */ +#define PFCNTR1 0xFFE08104 /* Performance Monitor Counter Register 1 */ + +/* + * Core MMR Register Bits + */ + +/* + * EVT registers (ILAT, IMASK, and IPEND). + */ + +/* ** Bit Positions */ +#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */ +#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */ +#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */ +#define EVT_EVX_P 0x00000003 /* Exception bit position */ +#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */ +#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */ +#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */ +#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */ +#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */ +#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */ +#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */ +#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */ +#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */ +#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */ +#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */ +#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */ + +/* ** Masks */ +#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */ +#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */ +#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */ +#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */ +#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */ +#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */ +#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */ +#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */ +#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */ +#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */ +#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */ +#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */ +#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */ +#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */ +#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */ +#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */ + +/* + * DMEM_CONTROL Register + */ + +/* ** Bit Positions */ +#define ENDM_P 0x00 /* (doesn't really exist) Enable Data Memory L1 */ +#define DMCTL_ENDM_P 0x00 /* "" (older define) */ +#define DMC0_P 0x01 /* Data Memory Configuration, 00 - A SRAM, B SRAM */ +#define DMCTL_DMC0_P 0x01 /* "" (older define) */ +#define DMC1_P 0x02 /* Data Memory Configuration, 10 - A SRAM, B SRAM */ +#define DMCTL_DMC1_P 0x02 /* "" (older define) */ +#define DMC2_P 0x03 /* Data Memory Configuration, 11 - A CACHE, B CACHE */ +#define DMCTL_DMC2_P 0x03 /* "" (older define) */ +#define DCBS_P 0x04 /* L1 Data Cache Bank Select */ +#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */ +#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */ + +/* ** Masks */ +#define ENDM 0x00000001 /* (doesn't really exist) Enable Data Memory L1 */ +#define ENDCPLB 0x00000002 /* Enable DCPLB */ +#define ASRAM_BSRAM 0x00000000 +#define ACACHE_BSRAM 0x00000008 +#define ACACHE_BCACHE 0x0000000C +#define DCBS 0x00000010 /* L1 Data Cache Bank Select */ +#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */ +#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */ + +/* IMEM_CONTROL Register */ +/* ** Bit Positions */ +#define ENIM_P 0x00 /* Enable L1 Code Memory */ +#define IMCTL_ENIM_P 0x00 /* "" (older define) */ +#define ENICPLB_P 0x01 /* Enable ICPLB */ +#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */ +#define IMC_P 0x02 /* Enable */ +#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as cache (0=SRAM) */ +#define ILOC0_P 0x03 /* Lock Way 0 */ +#define ILOC1_P 0x04 /* Lock Way 1 */ +#define ILOC2_P 0x05 /* Lock Way 2 */ +#define ILOC3_P 0x06 /* Lock Way 3 */ +#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement Priority */ + +/* ** Masks */ +#define ENIM 0x00000001 /* Enable L1 Code Memory */ +#define ENICPLB 0x00000002 /* Enable ICPLB */ +#define IMC 0x00000004 /* Configure L1 code memory as cache (0=SRAM) */ +#define ILOC0 0x00000008 /* Lock Way 0 */ +#define ILOC1 0x00000010 /* Lock Way 1 */ +#define ILOC2 0x00000020 /* Lock Way 2 */ +#define ILOC3 0x00000040 /* Lock Way 3 */ +#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement Priority */ + +/* TCNTL Masks */ +#define TMPWR 0x00000001 /* Timer Low Power Control, 0=low power mode, 1=active state */ +#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */ +#define TAUTORLD 0x00000004 /* Timer auto reload */ +#define TINT 0x00000008 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */ + +/* TCNTL Bit Positions */ +#define TMPWR_P 0x00000000 /* Timer Low Power Control, 0=low power mode, 1=active state */ +#define TMREN_P 0x00000001 /* Timer enable, 0=disable, 1=enable */ +#define TAUTORLD_P 0x00000002 /* Timer auto reload */ +#define TINT_P 0x00000003 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */ + +/* DCPLB_DATA and ICPLB_DATA Registers */ +/* ** Bit Positions */ +#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */ +#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */ +#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */ + +/* ** Masks */ +#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ +#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */ +#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */ +#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ +#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ +#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ +#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ +#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */ +#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */ +#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */ + +/* ICPLB_DATA only */ +#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */ + +/* DCPLB_DATA only */ +#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */ +#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */ +#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ +#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes */ + /* 1= allocate cache lines on write-through writes. */ +#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ + +/* ITEST_COMMAND and DTEST_COMMAND Registers */ +/* ** Masks */ +#define TEST_READ 0x00000000 /* Read Access */ +#define TEST_WRITE 0x00000002 /* Write Access */ +#define TEST_TAG 0x00000000 /* Access TAG */ +#define TEST_DATA 0x00000004 /* Access DATA */ +#define TEST_DW0 0x00000000 /* Select Double Word 0 */ +#define TEST_DW1 0x00000008 /* Select Double Word 1 */ +#define TEST_DW2 0x00000010 /* Select Double Word 2 */ +#define TEST_DW3 0x00000018 /* Select Double Word 3 */ +#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */ +#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */ +#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */ +#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */ +#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */ +#define TEST_WAY0 0x00000000 /* Access Way0 */ +#define TEST_WAY1 0x04000000 /* Access Way1 */ + +/* ** ITEST_COMMAND only */ +#define TEST_WAY2 0x08000000 /* Access Way2 */ +#define TEST_WAY3 0x0C000000 /* Access Way3 */ + +/* ** DTEST_COMMAND only */ +#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */ +#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */ + +#endif /* _DEF_LPBLACKFIN_H */ diff --git a/include/asm-blackfin/current.h b/include/asm-blackfin/current.h new file mode 100644 index 0000000..108c279 --- /dev/null +++ b/include/asm-blackfin/current.h @@ -0,0 +1,40 @@ +/* + * U-boot - current.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_CURRENT_H +#define _BLACKFIN_CURRENT_H +/* + * current.h + * (C) Copyright 2000, Lineo, David McCullough <davidm@lineo.com> + * + * rather than dedicate a register (as the m68k source does), we + * just keep a global, we should probably just change it all to be + * current and lose _current_task. + */ + +extern struct task_struct *_current_task; +#define get_current() _current_task +#define current _current_task + +#endif diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h new file mode 100644 index 0000000..dbb7388 --- /dev/null +++ b/include/asm-blackfin/delay.h @@ -0,0 +1,55 @@ +/* + * U-boot - delay.h Routines for introducing delays + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_DELAY_H +#define _BLACKFIN_DELAY_H + +/* + * Changes made by akbar.hussain@Lineo.com, for BLACKFIN + * Copyright (C) 1994 Hamish Macdonald + * + * Delay routines, using a pre-computed "loops_per_second" value. + */ + +extern __inline__ void __delay(unsigned long loops) +{ + __asm__ __volatile__("1:\t%0 += -1;\n\t" + "cc = %0 == 0;\n\t" + "if ! cc jump 1b;\n":"=d"(loops) + :"0"(loops)); +} + +/* + * Use only for very small delays ( < 1 msec). Should probably use a + * lookup table, really, as the multiplications take much too long with + * short delays. This is a "reasonable" implementation, though (and the + * first constant multiplications gets optimized away if the delay is + * a constant) + */ +extern __inline__ void udelay(unsigned long usecs) +{ + __delay(usecs); +} + +#endif diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h new file mode 100644 index 0000000..607a5b8 --- /dev/null +++ b/include/asm-blackfin/entry.h @@ -0,0 +1,385 @@ +/* + * U-boot - entry.h Routines for context saving and restoring + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BLACKFIN_ENTRY_H +#define __BLACKFIN_ENTRY_H + +#include <linux/config.h> +#include <asm/setup.h> +#include <asm/page.h> + +/* + * Stack layout in 'ret_from_exception': + * + */ + +/* + * Register %p2 is now set to the current task throughout + * the whole kernel. + */ + +#ifdef __ASSEMBLY__ + +#define LFLUSH_I_AND_D 0x00000808 +#define LSIGTRAP 5 + +/* process bits for task_struct.flags */ +#define PF_TRACESYS_OFF 3 +#define PF_TRACESYS_BIT 5 +#define PF_PTRACED_OFF 3 +#define PF_PTRACED_BIT 4 +#define PF_DTRACE_OFF 1 +#define PF_DTRACE_BIT 5 + +#define NEW_PT_REGS + +#if defined(NEW_PT_REGS) + +#define SAVE_ALL_INT save_context_no_interrupts +#define SAVE_ALL_SYS save_context_no_interrupts +#define SAVE_CONTEXT save_context_with_interrupts + +#define RESTORE_ALL restore_context_no_interrupts +#define RESTORE_ALL_SYS restore_context_no_interrupts +#define RESTORE_CONTEXT restore_context_with_interrupts + +#else + +#define SAVE_ALL_INT save_all_int +#define SAVE_ALL_SYS save_all_sys +#define SAVE_CONTEXT save_context +#define RESTORE_ALL restore_context +#define RESTORE_CONTEXT restore_context + +#endif + +/* + * Code to save processor context. + * We even save the register which are preserved by a function call + * - r4, r5, r6, r7, p3, p4, p5 + */ +.macro save_context_with_interrupts + [--sp] = R0; + [--sp] = ( R7:0, P5:0 ); + [--sp] = fp; + [--sp] = usp; + + [--sp] = i0; + [--sp] = i1; + [--sp] = i2; + [--sp] = i3; + + [--sp] = m0; + [--sp] = m1; + [--sp] = m2; + [--sp] = m3; + + [--sp] = l0; + [--sp] = l1; + [--sp] = l2; + [--sp] = l3; + + [--sp] = b0; + [--sp] = b1; + [--sp] = b2; + [--sp] = b3; + [--sp] = a0.x; + [--sp] = a0.w; + [--sp] = a1.x; + [--sp] = a1.w; + + [--sp] = LC0; + [--sp] = LC1; + [--sp] = LT0; + [--sp] = LT1; + [--sp] = LB0; + [--sp] = LB1; + + [--sp] = ASTAT; + + [--sp] = r0; /* Skip reserved */ + [--sp] = RETS; + [--sp] = RETI; + [--sp] = RETX; + [--sp] = RETN; + [--sp] = RETE; + [--sp] = SEQSTAT; + [--sp] = SYSCFG; + [--sp] = r0; /* Skip IPEND as well. */ +.endm + +.macro save_context_no_interrupts + [--sp] = R0; + [--sp] = ( R7:0, P5:0 ); + [--sp] = fp; + [--sp] = usp; + + [--sp] = i0; + [--sp] = i1; + [--sp] = i2; + [--sp] = i3; + + [--sp] = m0; + [--sp] = m1; + [--sp] = m2; + [--sp] = m3; + + [--sp] = l0; + [--sp] = l1; + [--sp] = l2; + [--sp] = l3; + + [--sp] = b0; + [--sp] = b1; + [--sp] = b2; + [--sp] = b3; + [--sp] = a0.x; + [--sp] = a0.w; + [--sp] = a1.x; + [--sp] = a1.w; + + [--sp] = LC0; + [--sp] = LC1; + [--sp] = LT0; + [--sp] = LT1; + [--sp] = LB0; + [--sp] = LB1; + + [--sp] = ASTAT; + + [--sp] = r0; /* Skip reserved */ + [--sp] = RETS; + r0 = RETI; + [--sp] = r0; + [--sp] = RETX; + [--sp] = RETN; + [--sp] = RETE; + [--sp] = SEQSTAT; + [--sp] = SYSCFG; + [--sp] = r0; /* Skip IPEND as well. */ +.endm + +.macro restore_context_no_interrupts + sp += 4; + SYSCFG = [sp++]; + SEQSTAT = [sp++]; + RETE = [sp++]; + RETN = [sp++]; + RETX = [sp++]; + r0 = [sp++]; + RETI = r0; + RETS = [sp++]; + + sp += 4; + + ASTAT = [sp++]; + + LB1 = [sp++]; + LB0 = [sp++]; + LT1 = [sp++]; + LT0 = [sp++]; + LC1 = [sp++]; + LC0 = [sp++]; + + a1.w = [sp++]; + a1.x = [sp++]; + a0.w = [sp++]; + a0.x = [sp++]; + b3 = [sp++]; + b2 = [sp++]; + b1 = [sp++]; + b0 = [sp++]; + + l3 = [sp++]; + l2 = [sp++]; + l1 = [sp++]; + l0 = [sp++]; + + m3 = [sp++]; + m2 = [sp++]; + m1 = [sp++]; + m0 = [sp++]; + + i3 = [sp++]; + i2 = [sp++]; + i1 = [sp++]; + i0 = [sp++]; + + sp += 4; + fp = [sp++]; + + ( R7 : 0, P5 : 0) = [ SP ++ ]; + sp += 4; +.endm + +.macro restore_context_with_interrupts + sp += 4; + SYSCFG = [sp++]; + SEQSTAT = [sp++]; + RETE = [sp++]; + RETN = [sp++]; + RETX = [sp++]; + RETI = [sp++]; + RETS = [sp++]; + + sp += 4; + + ASTAT = [sp++]; + + LB1 = [sp++]; + LB0 = [sp++]; + LT1 = [sp++]; + LT0 = [sp++]; + LC1 = [sp++]; + LC0 = [sp++]; + + a1.w = [sp++]; + a1.x = [sp++]; + a0.w = [sp++]; + a0.x = [sp++]; + b3 = [sp++]; + b2 = [sp++]; + b1 = [sp++]; + b0 = [sp++]; + + l3 = [sp++]; + l2 = [sp++]; + l1 = [sp++]; + l0 = [sp++]; + + m3 = [sp++]; + m2 = [sp++]; + m1 = [sp++]; + m0 = [sp++]; + + i3 = [sp++]; + i2 = [sp++]; + i1 = [sp++]; + i0 = [sp++]; + + sp += 4; + fp = [sp++]; + + ( R7 : 0, P5 : 0) = [ SP ++ ]; + sp += 4; +.endm + +#if !defined(NEW_PT_REGS) +/* + * a -1 in the orig_r0 field signifies + * that the stack frame is NOT for syscall + */ +.macro save_all_int +/* reserved and disable the single step of SYSCFG, by Steven Chen 03/07/10 */ + [--sp] = r0; + r0.l = 0x30; /* Errata for BF533 */ + r0.h = 0x0; + syscfg = r0; /* disable single step flag in SYSCFG */ + r0 = [sp++]; + [--sp] = syscfg; /* store SYSCFG */ + + [--sp] = r0; /* Reserved for IPEND */ + [--sp] = fp; + [--sp] = usp; + [--sp] = r0; + + [--sp] = r0; + r0 = [sp + 8]; + [--sp] = a0.x; + [--sp] = a1.x; + [--sp] = a0.w; + [--sp] = a1.w; + [--sp] = rets; + [--sp] = astat; + [--sp] = seqstat; + [--sp] = retx; /* current pc when exception happens */ + [--sp] = ( r7:5, p5:0 ); + [--sp] = r1; + [--sp] = r2; + [--sp] = r4; + [--sp] = r3; +.endm + +.macro save_all_sys + [--sp] = r0; + [--sp] = r0; + [--sp] = a0.x; + [--sp] = a1.x; + [--sp] = a0.w; + [--sp] = a1.w; + [--sp] = rets; + [--sp] = astat; + [--sp] = seqstat; + [--sp] = retx; /* current pc when exception happens */ + [--sp] = ( r7:5, p5:0 ); + [--sp] = r1; + [--sp] = r2; + [--sp] = r4; + [--sp] = r3; +.endm + +.macro restore_all + r3 = [sp++]; + r4 = [sp++]; + r2 = [sp++]; + r1 = [sp++]; + ( r7:5, p5:0 ) = [sp++]; + retx = [sp++]; + seqstat = [sp++]; + astat = [sp++]; + rets = [sp++]; + a1.w = [sp++]; + a0.w = [sp++]; + a1.x = [sp++]; + a0.x = [sp++]; + sp += 4; /* orig r0 */ + r0 = [sp++]; + + sp += 4; + fp = [sp++]; + sp +=4; /* Skip the IPEND */ + + syscfg = [sp++]; + +.endm + +#endif + +#define STR(X) STR1(X) +#define STR1(X) #X + +#if defined(NEW_PT_REGS) + +#define PT_OFF_ORIG_R0 208 +#define PT_OFF_SR 8 + +#else + +#define PT_OFF_ORIG_R0 0x54 +#define PT_OFF_SR 0x38 /* seqstat in pt_regs */ + +#endif +#endif + +#endif diff --git a/include/asm-blackfin/errno.h b/include/asm-blackfin/errno.h new file mode 100644 index 0000000..713bba0 --- /dev/null +++ b/include/asm-blackfin/errno.h @@ -0,0 +1,156 @@ +/* + * U-boot - errno.h Error number defines + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_ERRNO_H +#define _BLACKFIN_ERRNO_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + +#endif diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h new file mode 100644 index 0000000..56a12f0 --- /dev/null +++ b/include/asm-blackfin/global_data.h @@ -0,0 +1,64 @@ +/* + * U-boot - global_data.h Declarations for global data of u-boot + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_GBL_DATA_H +#define __ASM_GBL_DATA_H + +#include <asm/irq.h> + +/* + * The following data structure is placed in some memory wich is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) + */ +typedef struct global_data { + bd_t *bd; + unsigned long flags; + unsigned long board_type; + unsigned long baudrate; + unsigned long have_console; /* serial_init() was called */ + unsigned long ram_size; /* RAM size */ + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid? */ + void **jt; /* jump table */ +} gd_t; + +/* + * Global Data Flags + */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("P5") + +#endif diff --git a/include/asm-blackfin/hw_irq.h b/include/asm-blackfin/hw_irq.h new file mode 100644 index 0000000..1ee050e --- /dev/null +++ b/include/asm-blackfin/hw_irq.h @@ -0,0 +1,37 @@ +/* + * U-boot - hw_irq.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * linux/arch/$(ARCH)/platform/$(PLATFORM)/hw_irq.h + * BlackFin (ADI) assembler restricted values by Ted Ma <mated@sympatico.ca> + * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) + * Copyright (c) 2002 Lineo, Inc <mattw@lineo.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <linux/config.h> +#ifdef CONFIG_EZKIT533 +#include <asm/board/bf533_irq.h> +#endif +#ifdef CONFIG_STAMP +#include <asm/board/bf533_irq.h> +#endif diff --git a/include/asm-blackfin/io-kernel.h b/include/asm-blackfin/io-kernel.h new file mode 100644 index 0000000..0b0572f --- /dev/null +++ b/include/asm-blackfin/io-kernel.h @@ -0,0 +1,135 @@ +/* + * U-boot - io-kernel.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_IO_H +#define _BLACKFIN_IO_H + +#ifdef __KERNEL__ + +#include <linux/config.h> + +/* + * These are for ISA/PCI shared memory _only_ and should never be used + * on any other type of memory, including Zorro memory. They are meant to + * access the bus in the bus byte order which is little-endian!. + * + * readX/writeX() are used to access memory mapped devices. On some + * architectures the memory mapped IO stuff needs to be accessed + * differently. On the m68k architecture, we just read/write the + * memory location directly. + */ +/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates + * two accesses to memory, which may be undesireable for some devices. + */ +#define readb(addr) ({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; }) +#define readw(addr) ({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; }) +#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; }) +#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b)) +#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b)) +#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b)) +#define __raw_readb readb +#define __raw_readw readw +#define __raw_readl readl +#define __raw_writeb writeb +#define __raw_writew writew +#define __raw_writel writel +#define memset_io(a,b,c) memset((void *)(a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) +#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) +#define inb(addr) cf_inb((volatile unsigned char*)(addr)) +#define inw(addr) readw(addr) +#define inl(addr) readl(addr) +#define outb(x,addr) cf_outb((unsigned char)(x), (volatile unsigned char*)(addr)) +#define outw(x,addr) ((void) writew(x,addr)) +#define outl(x,addr) ((void) writel(x,addr)) +#define inb_p(addr) inb(addr) +#define inw_p(addr) inw(addr) +#define inl_p(addr) inl(addr) +#define outb_p(x,addr) outb(x,addr) +#define outw_p(x,addr) outw(x,addr) +#define outl_p(x,addr) outl(x,addr) +#define insb(port, addr, count) memcpy((void*)addr, (void*)port, count) +#define insw(port, addr, count) cf_insw((unsigned short*)addr, (unsigned short*)(port), (count)) +#define insl(port, addr, count) memcpy((void*)addr, (void*)port, (4*count)) +#define outsb(port, addr, count) memcpy((void*)port, (void*)addr, count) +#define outsw(port,addr,count) cf_outsw((unsigned short*)(port), (unsigned short*)addr, (count)) +#define outsl(port, addr, count) memcpy((void*)port, (void*)addr, (4*count)) +#define IO_SPACE_LIMIT 0xffff + +/* Values for nocacheflag and cmode */ +#define IOMAP_FULL_CACHING 0 +#define IOMAP_NOCACHE_SER 1 +#define IOMAP_NOCACHE_NONSER 2 +#define IOMAP_WRITETHROUGH 3 + +#ifndef __ASSEMBLY__ +extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag); +extern void __iounmap(void *addr, unsigned long size); +extern inline void *ioremap(unsigned long physaddr, unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); +} +extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); +} +extern inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); +} +extern inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_FULL_CACHING); +} + +extern void iounmap(void *addr); + +/* Nothing to do */ + +extern void blkfin_inv_cache_all(void); + +#endif + +#define dma_cache_inv(_start,_size) do { blkfin_inv_cache_all();} while (0) +#define dma_cache_wback(_start,_size) do { } while (0) +#define dma_cache_wback_inv(_start,_size) do { blkfin_inv_cache_all();} while (0) + +/* Pages to physical address... */ +#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT) +#define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT) + +#define mm_ptov(vaddr) ((void *) (vaddr)) +#define mm_vtop(vaddr) ((unsigned long) (vaddr)) +#define phys_to_virt(vaddr) ((void *) (vaddr)) +#define virt_to_phys(vaddr) ((unsigned long) (vaddr)) + +#define virt_to_bus virt_to_phys +#define bus_to_virt phys_to_virt + +#endif + +#endif diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h new file mode 100644 index 0000000..e5b388e --- /dev/null +++ b/include/asm-blackfin/io.h @@ -0,0 +1,122 @@ +/* + * U-boot - io.h IO routines + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_IO_H +#define _BLACKFIN_IO_H + +#ifdef __KERNEL__ + +#include <linux/config.h> + +/* function prototypes for CF support */ +extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words); +extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words); +extern unsigned char cf_inb(volatile unsigned char *addr); +extern void cf_outb(unsigned char val, volatile unsigned char* addr); + +/* + * These are for ISA/PCI shared memory _only_ and should never be used + * on any other type of memory, including Zorro memory. They are meant to + * access the bus in the bus byte order which is little-endian!. + * + * readX/writeX() are used to access memory mapped devices. On some + * architectures the memory mapped IO stuff needs to be accessed + * differently. On the m68k architecture, we just read/write the + * memory location directly. + */ + + +#define readb(addr) ({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; }) +#define readw(addr) ({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; }) +#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; }) + +#define writeb(b,addr) {((*(volatile unsigned char *) (addr)) = (b)); asm("ssync;");} +#define writew(b,addr) {((*(volatile unsigned short *) (addr)) = (b)); asm("ssync;");} +#define writel(b,addr) {((*(volatile unsigned int *) (addr)) = (b)); asm("ssync;");} + +#define memset_io(a,b,c) memset((void *)(a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) +#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) + +#define inb_p(addr) readb((addr) + BF533_PCIIO_BASE) +#define inb(addr) cf_inb((volatile unsigned char*)(addr)) + +#define outb(x,addr) cf_outb((unsigned char)(x), (volatile unsigned char*)(addr)) +#define outb_p(x,addr) outb(x, (addr) + BF533_PCIIO_BASE) + +#define inw(addr) readw((addr) + BF533_PCIIO_BASE) +#define inl(addr) readl((addr) + BF533_PCIIO_BASE) + +#define outw(x,addr) writew(x, (addr) + BF533_PCIIO_BASE) +#define outl(x,addr) writel(x, (addr) + BF533_PCIIO_BASE) + +#define insb(port, addr, count) memcpy((void*)addr, (void*)(BF533_PCIIO_BASE + port), count) +#define insw(port, addr, count) cf_insw((unsigned short*)addr, (unsigned short*)(port), (count)) +#define insl(port, addr, count) memcpy((void*)addr, (void*)(BF533_PCIIO_BASE + port), (4*count)) + +#define outsb(port,addr,count) memcpy((void*)(BF533_PCIIO_BASE + port), (void*)addr, count) +#define outsw(port,addr,count) cf_outsw((unsigned short*)(port), (unsigned short*)addr, (count)) +#define outsl(port,addr,count) memcpy((void*)(BF533_PCIIO_BASE + port), (void*)addr, (4*count)) + +#define IO_SPACE_LIMIT 0xffff + +/* Values for nocacheflag and cmode */ +#define IOMAP_FULL_CACHING 0 +#define IOMAP_NOCACHE_SER 1 +#define IOMAP_NOCACHE_NONSER 2 +#define IOMAP_WRITETHROUGH 3 + +extern void *__ioremap(unsigned long physaddr, unsigned long size, + int cacheflag); +extern void __iounmap(void *addr, unsigned long size); + +extern inline void *ioremap(unsigned long physaddr, unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); +} +extern inline void *ioremap_nocache(unsigned long physaddr, + unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); +} +extern inline void *ioremap_writethrough(unsigned long physaddr, + unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); +} +extern inline void *ioremap_fullcache(unsigned long physaddr, + unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_FULL_CACHING); +} + +extern void iounmap(void *addr); + +extern void blkfin_inv_cache_all(void); +#define dma_cache_inv(_start,_size) do { blkfin_inv_cache_all();} while (0) +#define dma_cache_wback(_start,_size) do { } while (0) +#define dma_cache_wback_inv(_start,_size) do { blkfin_inv_cache_all();} while (0) + +#endif +#endif diff --git a/include/asm-blackfin/irq.h b/include/asm-blackfin/irq.h new file mode 100644 index 0000000..5fbc5a3 --- /dev/null +++ b/include/asm-blackfin/irq.h @@ -0,0 +1,142 @@ +/* + * U-boot - irq.h Interrupt related header file + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file was based on + * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c + * + * Changed by HuTao Apr18, 2003 + * + * Copyright was missing when I got the code so took from MIPS arch ...MaTed--- + * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle + * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle + * + * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca> + * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) + * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_IRQ_H_ +#define _BLACKFIN_IRQ_H_ + +#include <linux/config.h> +#include <asm/cpu/bf533_irq.h> + +/* + * On the Blackfin, the interrupt structure allows remmapping of the hardware + * levels. + * - I'm going to assume that the H/W level is going to stay at the default + * settings. If someone wants to go through and abstart this out, feel free + * to mod the interrupt numbering scheme. + * - I'm abstracting the interrupts so that uClinux does not know anything + * about the H/W levels. If you want to change the H/W AND keep the abstracted + * levels that uClinux sees, you should be able to do most of it here. + * - I've left the "abstract" numbering sparce in case someone wants to pull the + * interrupts apart (just the TX/RX for the various devices) + */ + +#define NR_IRQS SYS_IRQS +/* + * "Generic" interrupt sources + */ +#define IRQ_SCHED_TIMER (8) /* interrupt source for scheduling timer */ + +static __inline__ int irq_cannonicalize(int irq) +{ + return irq; +} + +/* + * Machine specific interrupt sources. + * + * Adding an interrupt service routine for a source with this bit + * set indicates a special machine specific interrupt source. + * The machine specific files define these sources. + * + * The IRQ_MACHSPEC bit is now gone - the only thing it did was to + * introduce unnecessary overhead. + * + * All interrupt handling is actually machine specific so it is better + * to use function pointers, as used by the Sparc port, and select the + * interrupt handling functions when initializing the kernel. This way + * we save some unnecessary overhead at run-time. + * 01/11/97 - Jes + */ + +extern void (*mach_enable_irq) (unsigned int); +extern void (*mach_disable_irq) (unsigned int); +extern int sys_request_irq(unsigned int, + void (*)(int, void *, struct pt_regs *), + unsigned long, const char *, void *); +extern void sys_free_irq(unsigned int, void *); + +/* + * various flags for request_irq() - the Amiga now uses the standard + * mechanism like all other architectures - SA_INTERRUPT and SA_SHIRQ + * are your friends. + */ +#define IRQ_FLG_LOCK (0x0001) /* handler is not replaceable */ +#define IRQ_FLG_REPLACE (0x0002) /* replace existing handler */ +#define IRQ_FLG_FAST (0x0004) +#define IRQ_FLG_SLOW (0x0008) +#define IRQ_FLG_STD (0x8000) /* internally used */ + +/* + * This structure is used to chain together the ISRs for a particular + * interrupt source (if it supports chaining). + */ +typedef struct irq_node { + void (*handler) (int, void *, struct pt_regs *); + unsigned long flags; + void *dev_id; + const char *devname; + struct irq_node *next; +} irq_node_t; + +/* + * This structure has only 4 elements for speed reasons + */ +typedef struct irq_handler { + void (*handler) (int, void *, struct pt_regs *); + unsigned long flags; + void *dev_id; + const char *devname; +} irq_handler_t; + +/* count of spurious interrupts */ +extern volatile unsigned int num_spurious; + +/* + * This function returns a new irq_node_t + */ +extern irq_node_t *new_irq_node(void); + +/* + * Some drivers want these entry points + */ +#define enable_irq(x) (mach_enable_irq ? (*mach_enable_irq)(x) : 0) +#define disable_irq(x) (mach_disable_irq ? (*mach_disable_irq)(x) : 0) + +#define enable_irq_nosync(x) enable_irq(x) +#define disable_irq_nosync(x) disable_irq(x) + +#endif diff --git a/include/asm-blackfin/linkage.h b/include/asm-blackfin/linkage.h new file mode 100644 index 0000000..18f0c36 --- /dev/null +++ b/include/asm-blackfin/linkage.h @@ -0,0 +1,60 @@ +/* + * U-boot - linkage.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _LINUX_LINKAGE_H +#define _LINUX_LINKAGE_H + +#include <linux/config.h> + +#ifdef __cplusplus +#define CPP_ASMLINKAGE extern "C" +#else +#define CPP_ASMLINKAGE +#endif + +#define asmlinkage CPP_ASMLINKAGE + +#define SYMBOL_NAME_STR(X) #X +#define SYMBOL_NAME(X) X +#ifdef __STDC__ +#define SYMBOL_NAME_LABEL(X) X##: +#else +#define SYMBOL_NAME_LABEL(X) X: +#endif + +#define __ALIGN .align 4 +#define __ALIGN_STR ".align 4" + +#ifdef __ASSEMBLY__ + +#define ALIGN __ALIGN +#define ALIGN_STR __ALIGN_STR + +#define ENTRY(name) \ + .globl SYMBOL_NAME(name); \ + ALIGN; \ + SYMBOL_NAME_LABEL(name) +#endif + +#endif diff --git a/include/asm-blackfin/machdep.h b/include/asm-blackfin/machdep.h new file mode 100644 index 0000000..0a43ba1 --- /dev/null +++ b/include/asm-blackfin/machdep.h @@ -0,0 +1,89 @@ +/* + * U-boot - machdep.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_MACHDEP_H +#define _BLACKFIN_MACHDEP_H + +/* Machine dependent initial routines: + * + * Based on include/asm-m68knommu/machdep.h + * For blackfin, just now we only have bfin, so they'd point to the default bfin + * + */ + +struct pt_regs; +struct kbd_repeat; +struct mktime; +struct hwclk_time; +struct gendisk; +struct buffer_head; + +extern void (*mach_sched_init) (void (*handler) (int, void *, struct pt_regs *)); + +/* machine dependent keyboard functions */ +extern int (*mach_keyb_init) (void); +extern int (*mach_kbdrate) (struct kbd_repeat *); +extern void (*mach_kbd_leds) (unsigned int); + +/* machine dependent irq functions */ +extern void (*mach_init_IRQ) (void); +extern void (*(*mach_default_handler)[]) (int, void *, struct pt_regs *); +extern int (*mach_request_irq) (unsigned int irq, + void (*handler) (int, void *, + struct pt_regs *), + unsigned long flags, const char *devname, + void *dev_id); +extern void (*mach_free_irq) (unsigned int irq, void *dev_id); +extern void (*mach_get_model) (char *model); +extern int (*mach_get_hardware_list) (char *buffer); +extern int (*mach_get_irq_list) (char *buf); +extern void (*mach_process_int) (int irq, struct pt_regs * fp); + +/* machine dependent timer functions */ +extern unsigned long (*mach_gettimeoffset) (void); +extern void (*mach_gettod) (int *year, int *mon, int *day, int *hour, + int *min, int *sec); +extern int (*mach_hwclk) (int, struct hwclk_time *); +extern int (*mach_set_clock_mmss) (unsigned long); +extern void (*mach_reset) (void); +extern void (*mach_halt) (void); +extern void (*mach_power_off) (void); +extern unsigned long (*mach_hd_init) (unsigned long, unsigned long); +extern void (*mach_hd_setup) (char *, int *); +extern long mach_max_dma_address; +extern void (*mach_floppy_setup) (char *, int *); +extern void (*mach_floppy_eject) (void); +extern void (*mach_heartbeat) (int); +extern void (*mach_l2_flush) (int); +extern int mach_sysrq_key; +extern int mach_sysrq_shift_state; +extern int mach_sysrq_shift_mask; +extern char *mach_sysrq_xlate; + +#ifdef CONFIG_UCLINUX +extern void config_BSP(char *command, int len); +extern void (*mach_tick) (void); +#endif + +#endif diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h new file mode 100644 index 0000000..1a13d90 --- /dev/null +++ b/include/asm-blackfin/mem_init.h @@ -0,0 +1,287 @@ +/* + * U-boot - mem_init.h Header file for memory initialization + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if ( CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E ) + #if ( CONFIG_SCLK_HZ > 119402985 ) + #define SDRAM_tRP TRP_2 + #define SDRAM_tRP_num 2 + #define SDRAM_tRAS TRAS_7 + #define SDRAM_tRAS_num 7 + #define SDRAM_tRCD TRCD_2 + #define SDRAM_tWR TWR_2 + #endif + #if ( CONFIG_SCLK_HZ > 104477612 ) && ( CONFIG_SCLK_HZ <= 119402985 ) + #define SDRAM_tRP TRP_2 + #define SDRAM_tRP_num 2 + #define SDRAM_tRAS TRAS_6 + #define SDRAM_tRAS_num 6 + #define SDRAM_tRCD TRCD_2 + #define SDRAM_tWR TWR_2 + #endif + #if ( CONFIG_SCLK_HZ > 89552239 ) && ( CONFIG_SCLK_HZ <= 104477612 ) + #define SDRAM_tRP TRP_2 + #define SDRAM_tRP_num 2 + #define SDRAM_tRAS TRAS_5 + #define SDRAM_tRAS_num 5 + #define SDRAM_tRCD TRCD_2 + #define SDRAM_tWR TWR_2 + #endif + #if ( CONFIG_SCLK_HZ > 74626866 ) && ( CONFIG_SCLK_HZ <= 89552239 ) + #define SDRAM_tRP TRP_2 + #define SDRAM_tRP_num 2 + #define SDRAM_tRAS TRAS_4 + #define SDRAM_tRAS_num 4 + #define SDRAM_tRCD TRCD_2 + #define SDRAM_tWR TWR_2 + #endif + #if ( CONFIG_SCLK_HZ > 66666667 ) && ( CONFIG_SCLK_HZ <= 74626866 ) + #define SDRAM_tRP TRP_2 + #define SDRAM_tRP_num 2 + #define SDRAM_tRAS TRAS_3 + #define SDRAM_tRAS_num 3 + #define SDRAM_tRCD TRCD_2 + #define SDRAM_tWR TWR_2 + #endif + #if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 ) + #define SDRAM_tRP TRP_1 + #define SDRAM_tRP_num 1 + #define SDRAM_tRAS TRAS_4 + #define SDRAM_tRAS_num 3 + #define SDRAM_tRCD TRCD_1 + #define SDRAM_tWR TWR_2 + #endif + #if ( CONFIG_SCLK_HZ > 44776119 ) && ( CONFIG_SCLK_HZ <= 59701493 ) + #define SDRAM_tRP TRP_1 + #define SDRAM_tRP_num 1 + #define SDRAM_tRAS TRAS_3 + #define SDRAM_tRAS_num 3 + #define SDRAM_tRCD TRCD_1 + #define SDRAM_tWR TWR_2 + #endif + #if ( CONFIG_SCLK_HZ > 29850746 ) && ( CONFIG_SCLK_HZ <= 44776119 ) + #define SDRAM_tRP TRP_1 + #define SDRAM_tRP_num 1 + #define SDRAM_tRAS TRAS_2 + #define SDRAM_tRAS_num 2 + #define SDRAM_tRCD TRCD_1 + #define SDRAM_tWR TWR_2 + #endif + #if ( CONFIG_SCLK_HZ <= 29850746 ) + #define SDRAM_tRP TRP_1 + #define SDRAM_tRP_num 1 + #define SDRAM_tRAS TRAS_1 + #define SDRAM_tRAS_num 1 + #define SDRAM_tRCD TRCD_1 + #define SDRAM_tWR TWR_2 + #endif +#endif + +#if (CONFIG_MEM_MT48LC16M16A2TG_75) + /*SDRAM INFORMATION: */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ + #define SDRAM_CL CL_3 +#endif + +#if (CONFIG_MEM_MT48LC64M4A2FB_7E) + /*SDRAM INFORMATION: */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ + #define SDRAM_CL CL_2 +#endif + +#if ( CONFIG_MEM_SIZE == 128 ) + #define SDRAM_SIZE EBSZ_128 +#endif +#if ( CONFIG_MEM_SIZE == 64 ) + #define SDRAM_SIZE EBSZ_64 +#endif +#if ( CONFIG_MEM_SIZE == 32 ) + #define SDRAM_SIZE EBSZ_32 +#endif +#if ( CONFIG_MEM_SIZE == 16 ) + #define SDRAM_SIZE EBSZ_16 +#endif +#if ( CONFIG_MEM_ADD_WDTH == 11 ) + #define SDRAM_WIDTH EBCAW_11 +#endif +#if ( CONFIG_MEM_ADD_WDTH == 10 ) + #define SDRAM_WIDTH EBCAW_10 +#endif +#if ( CONFIG_MEM_ADD_WDTH == 9 ) + #define SDRAM_WIDTH EBCAW_9 +#endif +#if ( CONFIG_MEM_ADD_WDTH == 8 ) + #define SDRAM_WIDTH EBCAW_8 +#endif + +#define mem_SDBCTL SDRAM_WIDTH | SDRAM_SIZE | EBE + +/* Equation from section 17 (p17-46) of BF533 HRM */ +#define mem_SDRRC ((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) + +/* Enable SCLK Out */ +#define mem_SDGCTL ( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS ) + +#define flash_EBIU_AMBCTL_WAT ( ( CONFIG_FLASH_SPEED_BWAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 +#define flash_EBIU_AMBCTL_RAT ( ( CONFIG_FLASH_SPEED_BRAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 +#define flash_EBIU_AMBCTL_HT ( ( CONFIG_FLASH_SPEED_BHT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) +#define flash_EBIU_AMBCTL_ST ( ( CONFIG_FLASH_SPEED_BST * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 +#define flash_EBIU_AMBCTL_TT ( ( CONFIG_FLASH_SPEED_BTT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 + +#if (flash_EBIU_AMBCTL_TT > 3 ) + #define flash_EBIU_AMBCTL0_TT B0TT_4 +#endif +#if (flash_EBIU_AMBCTL_TT == 3 ) + #define flash_EBIU_AMBCTL0_TT B0TT_3 +#endif +#if (flash_EBIU_AMBCTL_TT == 2 ) + #define flash_EBIU_AMBCTL0_TT B0TT_2 +#endif +#if (flash_EBIU_AMBCTL_TT < 2 ) + #define flash_EBIU_AMBCTL0_TT B0TT_1 +#endif + +#if (flash_EBIU_AMBCTL_ST > 3 ) + #define flash_EBIU_AMBCTL0_ST B0ST_4 +#endif +#if (flash_EBIU_AMBCTL_ST == 3 ) + #define flash_EBIU_AMBCTL0_ST B0ST_3 +#endif +#if (flash_EBIU_AMBCTL_ST == 2 ) + #define flash_EBIU_AMBCTL0_ST B0ST_2 +#endif +#if (flash_EBIU_AMBCTL_ST < 2 ) + #define flash_EBIU_AMBCTL0_ST B0ST_1 +#endif + +#if (flash_EBIU_AMBCTL_HT > 2 ) + #define flash_EBIU_AMBCTL0_HT B0HT_3 +#endif +#if (flash_EBIU_AMBCTL_HT == 2 ) + #define flash_EBIU_AMBCTL0_HT B0HT_2 +#endif +#if (flash_EBIU_AMBCTL_HT == 1 ) + #define flash_EBIU_AMBCTL0_HT B0HT_1 +#endif +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) + #define flash_EBIU_AMBCTL0_HT B0HT_0 +#endif +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) + #define flash_EBIU_AMBCTL0_HT B0HT_1 +#endif + +#if (flash_EBIU_AMBCTL_WAT > 14) + #define flash_EBIU_AMBCTL0_WAT B0WAT_15 +#endif +#if (flash_EBIU_AMBCTL_WAT == 14) + #define flash_EBIU_AMBCTL0_WAT B0WAT_14 +#endif +#if (flash_EBIU_AMBCTL_WAT == 13) + #define flash_EBIU_AMBCTL0_WAT B0WAT_13 +#endif +#if (flash_EBIU_AMBCTL_WAT == 12) + #define flash_EBIU_AMBCTL0_WAT B0WAT_12 +#endif +#if (flash_EBIU_AMBCTL_WAT == 11) + #define flash_EBIU_AMBCTL0_WAT B0WAT_11 +#endif +#if (flash_EBIU_AMBCTL_WAT == 10) + #define flash_EBIU_AMBCTL0_WAT B0WAT_10 +#endif +#if (flash_EBIU_AMBCTL_WAT == 9) + #define flash_EBIU_AMBCTL0_WAT B0WAT_9 +#endif +#if (flash_EBIU_AMBCTL_WAT == 8) + #define flash_EBIU_AMBCTL0_WAT B0WAT_8 +#endif +#if (flash_EBIU_AMBCTL_WAT == 7) + #define flash_EBIU_AMBCTL0_WAT B0WAT_7 +#endif +#if (flash_EBIU_AMBCTL_WAT == 6) + #define flash_EBIU_AMBCTL0_WAT B0WAT_6 +#endif +#if (flash_EBIU_AMBCTL_WAT == 5) + #define flash_EBIU_AMBCTL0_WAT B0WAT_5 +#endif +#if (flash_EBIU_AMBCTL_WAT == 4) + #define flash_EBIU_AMBCTL0_WAT B0WAT_4 +#endif +#if (flash_EBIU_AMBCTL_WAT == 3) + #define flash_EBIU_AMBCTL0_WAT B0WAT_3 +#endif +#if (flash_EBIU_AMBCTL_WAT == 2) + #define flash_EBIU_AMBCTL0_WAT B0WAT_2 +#endif +#if (flash_EBIU_AMBCTL_WAT == 1) + #define flash_EBIU_AMBCTL0_WAT B0WAT_1 +#endif + +#if (flash_EBIU_AMBCTL_RAT > 14) + #define flash_EBIU_AMBCTL0_RAT B0RAT_15 +#endif +#if (flash_EBIU_AMBCTL_RAT == 14) + #define flash_EBIU_AMBCTL0_RAT B0RAT_14 +#endif +#if (flash_EBIU_AMBCTL_RAT == 13) + #define flash_EBIU_AMBCTL0_RAT B0RAT_13 +#endif +#if (flash_EBIU_AMBCTL_RAT == 12) + #define flash_EBIU_AMBCTL0_RAT B0RAT_12 +#endif +#if (flash_EBIU_AMBCTL_RAT == 11) + #define flash_EBIU_AMBCTL0_RAT B0RAT_11 +#endif +#if (flash_EBIU_AMBCTL_RAT == 10) + #define flash_EBIU_AMBCTL0_RAT B0RAT_10 +#endif +#if (flash_EBIU_AMBCTL_RAT == 9) + #define flash_EBIU_AMBCTL0_RAT B0RAT_9 +#endif +#if (flash_EBIU_AMBCTL_RAT == 8) + #define flash_EBIU_AMBCTL0_RAT B0RAT_8 +#endif +#if (flash_EBIU_AMBCTL_RAT == 7) + #define flash_EBIU_AMBCTL0_RAT B0RAT_7 +#endif +#if (flash_EBIU_AMBCTL_RAT == 6) + #define flash_EBIU_AMBCTL0_RAT B0RAT_6 +#endif +#if (flash_EBIU_AMBCTL_RAT == 5) + #define flash_EBIU_AMBCTL0_RAT B0RAT_5 +#endif +#if (flash_EBIU_AMBCTL_RAT == 4) + #define flash_EBIU_AMBCTL0_RAT B0RAT_4 +#endif +#if (flash_EBIU_AMBCTL_RAT == 3) + #define flash_EBIU_AMBCTL0_RAT B0RAT_3 +#endif +#if (flash_EBIU_AMBCTL_RAT == 2) + #define flash_EBIU_AMBCTL0_RAT B0RAT_2 +#endif +#if (flash_EBIU_AMBCTL_RAT == 1) + #define flash_EBIU_AMBCTL0_RAT B0RAT_1 +#endif + +#define flash_EBIU_AMBCTL0 flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h new file mode 100644 index 0000000..406ece5 --- /dev/null +++ b/include/asm-blackfin/page.h @@ -0,0 +1,128 @@ +/* + * U-boot - page.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_PAGE_H +#define _BLACKFIN_PAGE_H + +#include <linux/config.h> + +/* PAGE_SHIFT determines the page size */ + +#define PAGE_SHIFT (12) +#define PAGE_SIZE (4096) +#define PAGE_MASK (~(PAGE_SIZE-1)) + +#ifdef __KERNEL__ + +#include <asm/setup.h> + +#if PAGE_SHIFT < 13 +#define KTHREAD_SIZE (8192) +#else +#define KTHREAD_SIZE PAGE_SIZE +#endif + +#ifndef __ASSEMBLY__ + +#define get_user_page(vaddr) __get_free_page(GFP_KERNEL) +#define free_user_page(page, addr) free_page(addr) + +#define clear_page(page) memset((page), 0, PAGE_SIZE) +#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE) + +#define clear_user_page(page, vaddr) clear_page(page) +#define copy_user_page(to, from, vaddr) copy_page(to, from) + +/* + * These are used to make use of C type-checking.. + */ +typedef struct { + unsigned long pte; +} pte_t; +typedef struct { + unsigned long pmd[16]; +} pmd_t; +typedef struct { + unsigned long pgd; +} pgd_t; +typedef struct { + unsigned long pgprot; +} pgprot_t; + +#define pte_val(x) ((x).pte) +#define pmd_val(x) ((&x)->pmd[0]) +#define pgd_val(x) ((x).pgd) +#define pgprot_val(x) ((x).pgprot) + +#define __pte(x) ((pte_t) { (x) } ) +#define __pmd(x) ((pmd_t) { (x) } ) +#define __pgd(x) ((pgd_t) { (x) } ) +#define __pgprot(x) ((pgprot_t) { (x) } ) + +/* to align the pointer to the (next) page boundary */ +#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) + +/* Pure 2^n version of get_order */ +extern __inline__ int get_order(unsigned long size) +{ + int order; + + size = (size - 1) >> (PAGE_SHIFT - 1); + order = -1; + do { + size >>= 1; + order++; + } while (size); + return order; +} + +#endif /* !__ASSEMBLY__ */ + +#include <asm/page_offset.h> + +#define PAGE_OFFSET (PAGE_OFFSET_RAW) + +#ifndef __ASSEMBLY__ + +#define __pa(vaddr) virt_to_phys((void *)vaddr) +#define __va(paddr) phys_to_virt((unsigned long)paddr) + +#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT) +#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)) +#define VALID_PAGE(page) ((page - mem_map) < max_mapnr) + +#define BUG() do { \ + \ + while (1); /* dead-loop */ \ +} while (0) + +#define PAGE_BUG(page) do { \ + BUG(); \ +} while (0) + +#endif + +#endif + +#endif diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h new file mode 100644 index 0000000..262473f --- /dev/null +++ b/include/asm-blackfin/page_offset.h @@ -0,0 +1,35 @@ +/* + * U-boot - page_offset.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Changes made by Akbar Hussain April 10, 2001 + */ + +#include <linux/config.h> + +/* This handles the memory map.. */ + +#ifdef CONFIG_BLACKFIN +#define PAGE_OFFSET_RAW 0x00000000 +#endif diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h new file mode 100644 index 0000000..f1f2b5f --- /dev/null +++ b/include/asm-blackfin/posix_types.h @@ -0,0 +1,90 @@ +/* + * U-boot - posix_types.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ARCH_BLACKFIN_POSIX_TYPES_H +#define __ARCH_BLACKFIN_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char *__kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) + +#undef __FD_CLR +#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) + +#undef __FD_ISSET +#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) + +#undef __FD_ZERO +#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ + +#endif diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h new file mode 100644 index 0000000..19bd720 --- /dev/null +++ b/include/asm-blackfin/processor.h @@ -0,0 +1,174 @@ +/* + * U-boot - processor.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * include/asm-m68k/processor.h + * Changes made by Akbar Hussain Lineo, Inc, May 2001 for BLACKFIN + * Copyright (C) 1995 Hamish Macdonald + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_BLACKFIN_PROCESSOR_H +#define __ASM_BLACKFIN_PROCESSOR_H + +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l;}) + +#include <linux/config.h> +#include <asm/segment.h> +#include <asm/ptrace.h> +#include <asm/current.h> + +extern inline unsigned long rdusp(void) +{ + unsigned long usp; + + __asm__ __volatile__("%0 = usp;\n\t":"=da"(usp)); + return usp; +} + +extern inline void wrusp(unsigned long usp) +{ + __asm__ __volatile__("usp = %0;\n\t"::"da"(usp)); +} + +/* + * User space process size: 3.75GB. This is hardcoded into a few places, + * so don't change it unless you know what you are doing. + */ +#define TASK_SIZE (0xF0000000UL) + +/* + * Bus types + */ +#define EISA_bus 0 +#define MCA_bus 0 + +/* There is no pc register avaliable for BLACKFIN, so we are going to get + * it indirectly + */ + +#if 0 +inline unsigned long obtain_pc_indirectly(void) +{ + unsigned long pc; + __asm__ __volatile__("%0 = rets;\n":"=d"(pc)); + return (pc - 4); /* call pcrel24 is 4 bytes long */ +} +#endif + +/* + * if you change this structure, you must change the code and offsets + * in m68k/machasm.S + */ + +struct thread_struct { + unsigned long ksp; /* kernel stack pointer */ + unsigned long usp; /* user stack pointer */ + unsigned short seqstat; /* saved status register */ + unsigned long esp0; /* points to SR of stack frame pt_regs */ + unsigned long pc; /* instruction pointer */ +}; + +#define INIT_MMAP { &init_mm, 0, 0x40000000, NULL, __pgprot(_PAGE_PRESENT|_PAGE_ACCESSED), VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL } + +#define INIT_THREAD { \ + sizeof(init_stack) + (unsigned long) init_stack, 0, \ + PS_S, 0\ +} + +/* + * Do necessary setup to start up a newly executed thread. + * + * pass the data segment into user programs if it exists, + * it can't hurt anything as far as I can tell + */ +#define start_thread(_regs, _pc, _usp) \ +do { \ + set_fs(USER_DS); /* reads from user space */ \ + (_regs)->pc = (_pc); \ + if (current->mm) \ + (_regs)->r5 = current->mm->start_data; \ + (_regs)->seqstat &= ~0x0c00; \ + wrusp(_usp); \ + /* Adde by HuTao, May 26, 2003 3:39PM */\ + if ((_regs)->ipend & 0x8000) /* check whether system in supper mode - StChen */\ + (_regs)->ipend = 0x0;\ +} while(0) + +/* Forward declaration, a strange C thing */ +struct task_struct; + +/* Free all resources held by a thread. */ +static inline void release_thread(struct task_struct *dead_task) +{ +} + +extern int kernel_thread(int (*fn) (void *), void *arg, + unsigned long flags); + +#define copy_segments(tsk, mm) do { } while (0) +#define release_segments(mm) do { } while (0) +#define forget_segments() do { } while (0) + +/* + * Free current thread data structures etc.. + */ +static inline void exit_thread(void) +{ +} + +/* + * Return saved PC of a blocked thread. + */ +extern inline unsigned long thread_saved_pc(struct thread_struct *t) +{ + extern void scheduling_functions_start_here(void); + extern void scheduling_functions_end_here(void); + return 0; +} + +unsigned long get_wchan(struct task_struct *p); + +#define KSTK_EIP(tsk) \ + ({ \ + unsigned long eip = 0; \ + if ((tsk)->thread.esp0 > PAGE_SIZE && \ + MAP_NR((tsk)->thread.esp0) < max_mapnr) \ + eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \ + eip; }) +#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) +#define THREAD_SIZE (2*PAGE_SIZE) + +/* Allocation and freeing of basic task resources. */ +#define alloc_task_struct() \ + ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) +#define free_task_struct(p) free_pages((unsigned long)(p),1) +#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) + +#define init_task (init_task_union.task) +#define init_stack (init_task_union.stack) + +#endif diff --git a/include/asm-blackfin/ptrace.h b/include/asm-blackfin/ptrace.h new file mode 100644 index 0000000..afd5777 --- /dev/null +++ b/include/asm-blackfin/ptrace.h @@ -0,0 +1,269 @@ +/* + * U-boot - ptrace.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_PTRACE_H +#define _BLACKFIN_PTRACE_H + +#define NEW_PT_REGS + +/* + * GCC defines register number like this: + * ----------------------------- + * 0 - 7 are data registers R0-R7 + * 8 - 15 are address registers P0-P7 + * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3 + * 32 - 33 A registers A0 & A1 + * 34 - status register + * + * We follows above, except: + * 32-33 --- Low 32-bit of A0&1 + * 34-35 --- High 8-bit of A0&1 + */ + +#if defined(NEW_PT_REGS) + +#define PT_IPEND 0 +#define PT_SYSCFG (PT_IPEND+4) +#define PT_SEQSTAT (PT_SYSCFG+4) +#define PT_RETE (PT_SEQSTAT+4) +#define PT_RETN (PT_RETE+4) +#define PT_RETX (PT_RETN+4) +#define PT_RETI (PT_RETX+4) +#define PT_PC PT_RETI +#define PT_RETS (PT_RETI+4) +#define PT_RESERVED (PT_RETS+4) +#define PT_ASTAT (PT_RESERVED+4) +#define PT_LB1 (PT_ASTAT+4) +#define PT_LB0 (PT_LB1+4) +#define PT_LT1 (PT_LB0+4) +#define PT_LT0 (PT_LT1+4) +#define PT_LC1 (PT_LT0+4) +#define PT_LC0 (PT_LC1+4) +#define PT_A1W (PT_LC0+4) +#define PT_A1X (PT_A1W+4) +#define PT_A0W (PT_A1X+4) +#define PT_A0X (PT_A0W+4) +#define PT_B3 (PT_A0X+4) +#define PT_B2 (PT_B3+4) +#define PT_B1 (PT_B2+4) +#define PT_B0 (PT_B1+4) +#define PT_L3 (PT_B0+4) +#define PT_L2 (PT_L3+4) +#define PT_L1 (PT_L2+4) +#define PT_L0 (PT_L1+4) +#define PT_M3 (PT_L0+4) +#define PT_M2 (PT_M3+4) +#define PT_M1 (PT_M2+4) +#define PT_M0 (PT_M1+4) +#define PT_I3 (PT_M0+4) +#define PT_I2 (PT_I3+4) +#define PT_I1 (PT_I2+4) +#define PT_I0 (PT_I1+4) +#define PT_USP (PT_I0+4) +#define PT_FP (PT_USP+4) +#define PT_P5 (PT_FP+4) +#define PT_P4 (PT_P5+4) +#define PT_P3 (PT_P4+4) +#define PT_P2 (PT_P3+4) +#define PT_P1 (PT_P2+4) +#define PT_P0 (PT_P1+4) +#define PT_R7 (PT_P0+4) +#define PT_R6 (PT_R7+4) +#define PT_R5 (PT_R6+4) +#define PT_R4 (PT_R5+4) +#define PT_R3 (PT_R4+4) +#define PT_R2 (PT_R3+4) +#define PT_R1 (PT_R2+4) +#define PT_R0 (PT_R1+4) +#define PT_ORIG_R0 (PT_R0+4) +#define PT_SR PT_SEQSTAT + +#else +/* + * Here utilize blackfin : dpregs = [pregs + imm16s4] + * [pregs + imm16s4] = dpregs + * to access defferent saved reg in stack + */ +#define PT_R3 0 +#define PT_R4 4 +#define PT_R2 8 +#define PT_R1 12 +#define PT_P5 16 +#define PT_P4 20 +#define PT_P3 24 +#define PT_P2 28 +#define PT_P1 32 +#define PT_P0 36 +#define PT_R7 40 +#define PT_R6 44 +#define PT_R5 48 +#define PT_PC 52 +#define PT_SEQSTAT 56 /* so-called SR reg */ +#define PT_SR PT_SEQSTAT +#define PT_ASTAT 60 +#define PT_RETS 64 +#define PT_A1w 68 +#define PT_A0w 72 +#define PT_A1x 76 +#define PT_A0x 80 +#define PT_ORIG_R0 84 +#define PT_R0 88 +#define PT_USP 92 +#define PT_FP 96 +#define PT_SP 100 + +/* Added by HuTao, May26 2003 3:18PM */ +#define PT_IPEND 100 + +/* Add SYSCFG register for single stepping support */ +#define PT_SYSCFG 104 + +#endif + +#ifndef __ASSEMBLY__ + +#if defined(NEW_PT_REGS) +/* this struct defines the way the registers are stored on the + * stack during a system call. + */ +struct pt_regs { + long ipend; + long syscfg; + long seqstat; + long rete; + long retn; + long retx; + long pc; + long rets; + long reserved; + long astat; + long lb1; + long lb0; + long lt1; + long lt0; + long lc1; + long lc0; + long a1w; + long a1x; + long a0w; + long a0x; + long b3; + long b2; + long b1; + long b0; + long l3; + long l2; + long l1; + long l0; + long m3; + long m2; + long m1; + long m0; + long i3; + long i2; + long i1; + long i0; + long usp; + long fp; + long p5; + long p4; + long p3; + long p2; + long p1; + long p0; + long r7; + long r6; + long r5; + long r4; + long r3; + long r2; + long r1; + long r0; + long orig_r0; +}; + +#else +/* now we don't know what regs the system call will use */ +struct pt_regs { + long r3; + long r4; + long r2; + long r1; + long p5; + long p4; + long p3; + long p2; + long p1; + long p0; + long r7; + long r6; + long r5; + unsigned long pc; + unsigned long seqstat; + unsigned long astat; + unsigned long rets; + long a1w; + long a0w; + long a1x; + long a0x; + long orig_r0; + long r0; + long usp; + long fp; +/* + * Added for supervisor/user mode switch. + * + * HuTao May26 03 3:23PM + */ + long ipend; + long syscfg; +}; + +#endif + +/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 /* ptrace signal */ + +#ifdef __KERNEL__ + +#ifndef PS_S +#define PS_S (0x0c00) + +/* Bit 11:10 of SEQSTAT defines user/supervisor/debug mode + * 00: user + * 01: supervisor + * 1x: debug + */ + +#define PS_M (0x1000) /* I am not sure why this is required here Akbar */ +#endif + +#define user_mode(regs) (!((regs)->seqstat & PS_S)) +#define instruction_pointer(regs) ((regs)->pc) +extern void show_regs(struct pt_regs *); + +#endif +#endif +#endif diff --git a/include/asm-blackfin/segment.h b/include/asm-blackfin/segment.h new file mode 100644 index 0000000..9e6d817 --- /dev/null +++ b/include/asm-blackfin/segment.h @@ -0,0 +1,46 @@ +/* + * U-boot - segment.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_SEGMENT_H +#define _BLACKFIN_SEGMENT_H + +/* define constants */ +typedef unsigned long mm_segment_t; /* domain register */ + +#define KERNEL_CS 0x0 +#define KERNEL_DS 0x0 +#define __KERNEL_CS 0x0 +#define __KERNEL_DS 0x0 + +#define USER_CS 0x1 +#define USER_DS 0x1 +#define __USER_CS 0x1 +#define __USER_DS 0x1 + +#define get_ds() (KERNEL_DS) +#define get_fs() (__USER_DS) +#define segment_eq(a,b) ((a) == (b)) +#define set_fs(val) + +#endif diff --git a/include/asm-blackfin/setup.h b/include/asm-blackfin/setup.h new file mode 100644 index 0000000..6ce9688 --- /dev/null +++ b/include/asm-blackfin/setup.h @@ -0,0 +1,86 @@ +/* + * U-boot - setup.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * asm/setup.h -- Definition of the Linux/Blackfin setup information + * Copyright Lineo, Inc 2001 Tony Kou + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_SETUP_H +#define _BLACKFIN_SETUP_H + +#include <linux/config.h> + +/* + * Linux/Blackfin Architectures + */ + +#define MACH_BFIN 1 + +#ifdef __KERNEL__ + +#ifndef __ASSEMBLY__ +extern unsigned long blackfin_machtype; +#endif + +#if defined(CONFIG_BFIN) +#define MACH_IS_BFIN (blackfin_machtype == MACH_BFIN) +#endif + +#ifndef MACH_TYPE +#define MACH_TYPE (blackfin_machtype) +#endif + +#endif + +/* + * CPU, FPU and MMU types + * + * Note: we don't need now: + * + */ + +#ifndef __ASSEMBLY__ +extern unsigned long blackfin_cputype; +#ifdef CONFIG_VME +extern unsigned long vme_brdtype; +#endif + +/* + * Miscellaneous + */ + +#define NUM_MEMINFO 4 +#define CL_SIZE 256 + +extern int blackfin_num_memory; /* # of memory blocks found (and used) */ +extern int blackfin_realnum_memory; /* real # of memory blocks found */ +extern struct mem_info blackfin_memory[NUM_MEMINFO]; /* memory description */ + +struct mem_info { + unsigned long addr; /* physical address of memory chunk */ + unsigned long size; /* length of memory chunk (in bytes) */ +}; +#endif + +#endif diff --git a/include/asm-blackfin/shared_resources.h b/include/asm-blackfin/shared_resources.h new file mode 100644 index 0000000..fbef186 --- /dev/null +++ b/include/asm-blackfin/shared_resources.h @@ -0,0 +1,33 @@ +/* + * U-boot - setup.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SHARED_RESOURCES_H_ +#define _SHARED_RESOURCES_H_ + +void swap_to(int device_id); + +#define FLASH 0 +#define ETHERNET 1 + +#endif /* _SHARED_RESOURCES_H_ */ diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h new file mode 100644 index 0000000..ffd81d6 --- /dev/null +++ b/include/asm-blackfin/string.h @@ -0,0 +1,79 @@ +/* + * U-boot - string.h String functions + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Changed by Lineo Inc. May 2001 */ + +#ifndef _BLACKFINNOMMU_STRING_H_ +#define _BLACKFINNOMMU_STRING_H_ + +#ifdef __KERNEL__ /* only set these up for kernel code */ + +#include <asm/setup.h> +#include <asm/page.h> +#include <asm/cpu/defBF533.h> + +#define __HAVE_ARCH_STRCPY +#define __HAVE_ARCH_STRNCPY +#define __HAVE_ARCH_STRCMP +#define __HAVE_ARCH_STRNCMP +#define __HAVE_ARCH_MEMCPY + +extern char *strcpy(char *dest, const char *src); +extern char *strncpy(char *dest, const char *src, size_t n); +extern int strcmp(const char *cs, const char *ct); +extern int strncmp(const char *cs, const char *ct, size_t count); +extern void * memcpy(void * dest,const void *src,size_t count); +extern void *memset(void *s, int c, size_t count); +extern int memcmp(const void *, const void *, __kernel_size_t); + +#else /* KERNEL */ + +/* + * let user libraries deal with these, + * IMHO the kernel has no place defining these functions for user apps + */ + +#define __HAVE_ARCH_STRCPY 1 +#define __HAVE_ARCH_STRNCPY 1 +#define __HAVE_ARCH_STRCAT 1 +#define __HAVE_ARCH_STRNCAT 1 +#define __HAVE_ARCH_STRCMP 1 +#define __HAVE_ARCH_STRNCMP 1 +#define __HAVE_ARCH_STRNICMP 1 +#define __HAVE_ARCH_STRCHR 1 +#define __HAVE_ARCH_STRRCHR 1 +#define __HAVE_ARCH_STRSTR 1 +#define __HAVE_ARCH_STRLEN 1 +#define __HAVE_ARCH_STRNLEN 1 +#define __HAVE_ARCH_MEMSET 1 +#define __HAVE_ARCH_MEMCPY 1 +#define __HAVE_ARCH_MEMMOVE 1 +#define __HAVE_ARCH_MEMSCAN 1 +#define __HAVE_ARCH_MEMCMP 1 +#define __HAVE_ARCH_MEMCHR 1 +#define __HAVE_ARCH_STRTOK 1 + +#endif /* KERNEL */ + +#endif /* _BLACKFIN_STRING_H_ */ diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h new file mode 100644 index 0000000..0e53adf --- /dev/null +++ b/include/asm-blackfin/system.h @@ -0,0 +1,182 @@ +/* + * U-boot - system.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_SYSTEM_H +#define _BLACKFIN_SYSTEM_H + +#include <linux/config.h> /* get configuration macros */ +#include <asm/linkage.h> +#include <asm/blackfin.h> +#include <asm/segment.h> +#include <asm/entry.h> + +#define prepare_to_switch() do { } while(0) + +/* + * switch_to(n) should switch tasks to task ptr, first checking that + * ptr isn't the current task, in which case it does nothing. This + * also clears the TS-flag if the task we switched to has used the + * math co-processor latest. + * + * 05/25/01 - Tony Kou (tonyko@lineo.ca) + * + * Adapted for BlackFin (ADI) by Ted Ma, Metrowerks, and Motorola GSG + * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) + * Copyright (c) 2003 Metrowerks (www.metrowerks.com) + */ + +asmlinkage void resume(void); + +#define switch_to(prev,next,last) { \ + void *_last; \ + __asm__ __volatile__( \ + "r0 = %1;\n\t" \ + "r1 = %2;\n\t" \ + "call resume;\n\t" \ + "%0 = r0;\n\t" \ + : "=d" (_last) \ + : "d" (prev), \ + "d" (next) \ + : "CC", "R0", "R1", "R2", "R3", "R4", "R5", "P0", "P1");\ + (last) = _last; \ +} + +/* Force kerenl switch to user mode -- Steven Chen */ +#define switch_to_user_mode() { \ + __asm__ __volatile__( \ + "call kernel_to_user_mode;\n\t" \ + :: \ + : "CC", "R0", "R1", "R2", "R3", "R4", "R5", "P0", "P1");\ +} + +/* + * Interrupt configuring macros. + */ + +extern int irq_flags; + +#define __sti() { \ + __asm__ __volatile__ ( \ + "r3 = %0;" \ + "sti r3;" \ + ::"m"(irq_flags):"R3"); \ +} + +#define __cli() { \ + __asm__ __volatile__ ( \ + "cli r3;" \ + :::"R3"); \ +} + +#define __save_flags(x) { \ + __asm__ __volatile__ ( \ + "cli r3;" \ + "%0 = r3;" \ + "sti r3;" \ + ::"m"(x):"R3"); \ +} + +#define __save_and_cli(x) { \ + __asm__ __volatile__ ( \ + "cli r3;" \ + "%0 = r3;" \ + ::"m"(x):"R3"); \ +} + +#define __restore_flags(x) { \ + __asm__ __volatile__ ( \ + "r3 = %0;" \ + "sti r3;" \ + ::"m"(x):"R3"); \ +} + +/* For spinlocks etc */ +#define local_irq_save(x) __save_and_cli(x) +#define local_irq_restore(x) __restore_flags(x) +#define local_irq_disable() __cli() +#define local_irq_enable() __sti() + +#define cli() __cli() +#define sti() __sti() +#define save_flags(x) __save_flags(x) +#define restore_flags(x) __restore_flags(x) +#define save_and_cli(x) __save_and_cli(x) + +/* + * Force strict CPU ordering. + */ +#define nop() asm volatile ("nop;\n\t"::) +#define mb() asm volatile ("" : : :"memory") +#define rmb() asm volatile ("" : : :"memory") +#define wmb() asm volatile ("" : : :"memory") +#define set_rmb(var, value) do { xchg(&var, value); } while (0) +#define set_mb(var, value) set_rmb(var, value) +#define set_wmb(var, value) do { var = value; wmb(); } while (0) + +#ifdef CONFIG_SMP +#define smp_mb() mb() +#define smp_rmb() rmb() +#define smp_wmb() wmb() +#else +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#endif + +#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) +#define tas(ptr) (xchg((ptr),1)) + +struct __xchg_dummy { + unsigned long a[100]; +}; +#define __xg(x) ((volatile struct __xchg_dummy *)(x)) + +static inline unsigned long __xchg(unsigned long x, volatile void *ptr, + int size) +{ + unsigned long tmp; + unsigned long flags = 0; + + save_and_cli(flags); + + switch (size) { + case 1: + __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory"); + break; + case 2: + __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory"); + break; + case 4: + __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory"); + break; + } + restore_flags(flags); + return tmp; +} + +/* Depend on whether Blackfin has hard reset function */ +/* YES it does, but it is tricky to implement - FIXME later ...MaTed--- */ +#define HARD_RESET_NOW() ({}) + +#endif /* _BLACKFIN_SYSTEM_H */ diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h new file mode 100644 index 0000000..29e6eba --- /dev/null +++ b/include/asm-blackfin/traps.h @@ -0,0 +1,86 @@ +/* + * U-boot - traps.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * linux/include/asm/traps.h + * Copyright (C) 1993 Hamish Macdonald + * Lineo, Inc Jul 2001 Tony Kou + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + */ + +#ifndef _BLACKFIN_TRAPS_H +#define _BLACKFIN_TRAPS_H + +#ifndef __ASSEMBLY__ +typedef void (*e_vector) (void); +extern e_vector vectors[]; +#endif + +#define VEC_SYS (0) +#define VEC_EXCPT01 (1) +#define VEC_EXCPT02 (2) +#define VEC_EXCPT03 (3) +#define VEC_EXCPT04 (4) +#define VEC_EXCPT05 (5) +#define VEC_EXCPT06 (6) +#define VEC_EXCPT07 (7) +#define VEC_EXCPT08 (8) +#define VEC_EXCPT09 (9) +#define VEC_EXCPT10 (10) +#define VEC_EXCPT11 (11) +#define VEC_EXCPT12 (12) +#define VEC_EXCPT13 (13) +#define VEC_EXCPT14 (14) +#define VEC_EXCPT15 (15) +#define VEC_STEP (16) +#define VEC_OVFLOW (17) +#define VEC_UNDEF_I (33) +#define VEC_ILGAL_I (34) +#define VEC_CPLB_VL (35) +#define VEC_MISALI_D (36) +#define VEC_UNCOV (37) +#define VEC_CPLB_M (38) +#define VEC_CPLB_MHIT (39) +#define VEC_WATCH (40) +#define VEC_ISTRU_VL (41) +#define VEC_MISALI_I (42) +#define VEC_CPLB_I_VL (43) +#define VEC_CPLB_I_M (44) +#define VEC_CPLB_I_MHIT (45) +#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */ + +#define VECOFF(vec) ((vec)<<2) + +#ifndef __ASSEMBLY__ + +/* Status register bits */ +#define PS_T (0x8000) +#define PS_S (0x0c00) /* Supervisor mode = 0b01 */ +#define PS_D (0x0c00) /* Debug mode = 0b1x */ +#define PS_M (0x1000) +#define PS_C (0x0001) + +#endif +#endif diff --git a/include/asm-blackfin/types.h b/include/asm-blackfin/types.h new file mode 100644 index 0000000..942ed27 --- /dev/null +++ b/include/asm-blackfin/types.h @@ -0,0 +1,83 @@ +/* + * U-boot - types.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_TYPES_H +#define _BLACKFIN_TYPES_H + +/* + * This file is never included by application software unless + * explicitly requested (e.g., via linux/types.h) in which case the + * application is Linux specific so (user-) name space pollution is + * not a major issue. However, for interoperability, libraries still + * need to be careful to avoid a name clashes. + */ + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +/* HK0617 -- Changes to unsigned long temporarily */ +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +#endif + +#endif diff --git a/include/asm-blackfin/u-boot.h b/include/asm-blackfin/u-boot.h new file mode 100644 index 0000000..ec39338 --- /dev/null +++ b/include/asm-blackfin/u-boot.h @@ -0,0 +1,47 @@ +/* + * U-boot - u-boot.h Structure declarations for board specific data + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _U_BOOT_H_ +#define _U_BOOT_H_ 1 + +typedef struct bd_info { + int bi_baudrate; /* serial console baudrate */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned long bi_arch_number; /* unique id for this board */ + unsigned long bi_boot_params; /* where this board expects params */ + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ +} bd_t; + +#define bi_env_data bi_env->data +#define bi_env_crc bi_env->crc + +#endif /* _U_BOOT_H_ */ diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h new file mode 100644 index 0000000..8578166 --- /dev/null +++ b/include/asm-blackfin/uaccess.h @@ -0,0 +1,207 @@ +/* + * U-boot - uaccess.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * Based on: include/asm-m68knommu/uaccess.h + * Changes made by Lineo Inc. May 2001 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BLACKFIN_UACCESS_H +#define __BLACKFIN_UACCESS_H + +/* + * User space memory access functions + */ +#include <asm/segment.h> +#include <asm/errno.h> + +#define VERIFY_READ 0 +#define VERIFY_WRITE 1 + +/* We let the MMU do all checking */ +static inline int access_ok(int type, const void *addr, unsigned long size) +{ + return ((unsigned long) addr < 0x10f00000); /* need final decision - Tony */ +} + +static inline int verify_area(int type, const void *addr, + unsigned long size) +{ + return access_ok(type, addr, size) ? 0 : -EFAULT; +} + +/* + * The exception table consists of pairs of addresses: the first is the + * address of an instruction that is allowed to fault, and the second is + * the address at which the program should continue. No registers are + * modified, so it is entirely up to the continuation code to figure out + * what to do. + * + * All the routines below use bits of fixup code that are out of line + * with the main instruction path. This means when everything is well, + * we don't even have to jump over them. Further, they do not intrude + * on our cache or tlb entries. + */ + +struct exception_table_entry { + unsigned long insn, fixup; +}; + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +/* + * These are the main single-value transfer routines. They automatically + * use the right size if we just have the right pointer type. + */ + +#define put_user(x, ptr) \ +({ \ + int __pu_err = 0; \ + typeof(*(ptr)) __pu_val = (x); \ + switch (sizeof (*(ptr))) { \ + case 1: \ + __put_user_asm(__pu_err, __pu_val, ptr, B); \ + break; \ + case 2: \ + __put_user_asm(__pu_err, __pu_val, ptr, W); \ + break; \ + case 4: \ + __put_user_asm(__pu_err, __pu_val, ptr, ); \ + break; \ + default: \ + __pu_err = __put_user_bad(); \ + break; \ + } \ + __pu_err; \ +}) +/* + * [pregs] = dregs ==> 32bits + * H[pregs] = dregs ==> 16bits + * B[pregs] = dregs ==> 8 bits + */ + +#define __put_user(x, ptr) put_user(x, ptr) + +static inline int bad_user_access_length(void) +{ + panic("bad_user_access_length"); + return -1; +} + +#define __put_user_bad() (bad_user_access_length(), (-EFAULT)) + +/* + * Tell gcc we read from memory instead of writing: this is because + * we do not write to any memory gcc knows about, so there are no + * aliasing issues. + */ + +#define __ptr(x) ((unsigned long *)(x)) + +#define __put_user_asm(err,x,ptr,bhw) \ + __asm__ (#bhw"[%1] = %0;\n\t" \ + : /* no outputs */ \ + :"d" (x),"a" (__ptr(ptr)) : "memory") + +#define get_user(x, ptr) \ +({ \ + int __gu_err = 0; \ + typeof(*(ptr)) __gu_val = 0; \ + switch (sizeof(*(ptr))) { \ + case 1: \ + __get_user_asm(__gu_err, __gu_val, ptr, B, "=d",(Z)); \ + break; \ + case 2: \ + __get_user_asm(__gu_err, __gu_val, ptr, W, "=r",(Z)); \ + break; \ + case 4: \ + __get_user_asm(__gu_err, __gu_val, ptr, , "=r",); \ + break; \ + default: \ + __gu_val = 0; \ + __gu_err = __get_user_bad(); \ + break; \ + } \ + (x) = __gu_val; \ + __gu_err; \ +}) + +/* dregs = [pregs] ==> 32bits + * H[pregs] ==> 16bits + * B[pregs] ==> 8 bits + */ + +#define __get_user(x, ptr) get_user(x, ptr) +#define __get_user_bad() (bad_user_access_length(), (-EFAULT)) + +#define __get_user_asm(err,x,ptr,bhw,reg,option) \ + __asm__ ("%0 =" #bhw "[%1]"#option";\n\t" \ + : "=d" (x) \ + : "a" (__ptr(ptr))) + +#define copy_from_user(to, from, n) (memcpy(to, from, n), 0) +#define copy_to_user(to, from, n) (memcpy(to, from, n), 0) + +#define __copy_from_user(to, from, n) copy_from_user(to, from, n) +#define __copy_to_user(to, from, n) copy_to_user(to, from, n) + +#define copy_to_user_ret(to,from,n,retval) ({ if (copy_to_user(to,from,n)) return retval; }) +#define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n)) return retval; }) + +/* + * Copy a null terminated string from userspace. + */ + +static inline long strncpy_from_user(char *dst, const char *src, + long count) +{ + char *tmp; + strncpy(dst, src, count); + for (tmp = dst; *tmp && count > 0; tmp++, count--); + return (tmp - dst); /* DAVIDM should we count a NUL ? check getname */ +} + +/* + * Return the size of a string (including the ending 0) + * + * Return 0 on exception, a value greater than N if too long + */ +static inline long strnlen_user(const char *src, long n) +{ + return (strlen(src) + 1); /* DAVIDM make safer */ +} + +#define strlen_user(str) strnlen_user(str, 32767) + +/* + * Zero Userspace + */ + +static inline unsigned long clear_user(void *to, unsigned long n) +{ + memset(to, 0, n); + return (0); +} + +#endif diff --git a/include/asm-blackfin/virtconvert.h b/include/asm-blackfin/virtconvert.h new file mode 100644 index 0000000..769f5a0 --- /dev/null +++ b/include/asm-blackfin/virtconvert.h @@ -0,0 +1,47 @@ +/* + * U-boot - virtconvert.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BLACKFIN_VIRT_CONVERT__ +#define __BLACKFIN_VIRT_CONVERT__ + +/* + * Macros used for converting between virtual and physical mappings. + */ + +#ifdef __KERNEL__ + +#include <linux/config.h> +#include <asm/setup.h> +#include <asm/page.h> + +#define mm_vtop(vaddr) ((unsigned long) vaddr) +#define mm_ptov(vaddr) ((unsigned long) vaddr) +#define phys_to_virt(vaddr) ((unsigned long) vaddr) +#define virt_to_phys(vaddr) ((unsigned long) vaddr) + +#define virt_to_bus virt_to_phys +#define bus_to_virt phys_to_virt + +#endif +#endif diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 6c2c712..f5fec22 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -71,8 +71,8 @@ typedef struct sysconf8349 { | SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP) u32 sicrl; /* System General Purpose Register Low */ #define SICRL_LDP_A 0x80000000 -#define SICRL_USB0 0x40000000 -#define SICRL_USB1 0x20000000 +#define SICRL_USB1 0x40000000 +#define SICRL_USB0 0x20000000 #define SICRL_UART 0x0C000000 #define SICRL_GPIO1_A 0x02000000 #define SICRL_GPIO1_B 0x01000000 diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h index 9ee4849..cf36583 100644 --- a/include/cmd_confdefs.h +++ b/include/cmd_confdefs.h @@ -112,7 +112,6 @@ CFG_CMD_DISPLAY | \ CFG_CMD_DOC | \ CFG_CMD_DTT | \ - CFG_CMD_ECHO | \ CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ CFG_CMD_EXT2 | \ diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 9841893..d03c05b 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -132,6 +132,9 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ + +#define CFG_NAND_LEGACY + #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/Adder.h b/include/configs/Adder.h index f807546..0e6b50f 100644 --- a/include/configs/Adder.h +++ b/include/configs/Adder.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004 Arabella Software Ltd. + * Copyright (C) 2004-2005 Arabella Software Ltd. * Yuli Barcohen <yuli@arabellasw.com> * * Support for Analogue&Micro Adder boards family. @@ -35,11 +35,13 @@ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_BAUDRATE 38400 -#define CONFIG_FEC_ENET /* Ethernet is on FEC */ -#ifdef CONFIG_FEC_ENET +#define CONFIG_ETHER_ON_FEC1 +#define CONFIG_ETHER_ON_FEC2 + +#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) #define CFG_DISCOVER_PHY #define FEC_ENET -#endif /* CONFIG_FEC_ENET */ +#endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */ #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ #define CONFIG_8xx_CPUCLK_DEFAULT 50000000 @@ -47,7 +49,7 @@ #ifdef CONFIG_MPC852T #define CFG_8xx_CPUCLK_MAX 50000000 #else -#define CFG_8xx_CPUCLK_MAX 120000000 +#define CFG_8xx_CPUCLK_MAX 133000000 #endif /* CONFIG_MPC852T */ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ @@ -62,7 +64,7 @@ #define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw" +#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)" #define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ #undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ @@ -79,7 +81,7 @@ #define CFG_MAXARGS 16 /* Max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x100000 /* Default load address */ +#define CFG_LOAD_ADDR 0x400000 /* Default load address */ #define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ @@ -89,24 +91,21 @@ * RAM configuration (note that CFG_SDRAM_BASE must be zero) */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ - -#define CFG_OR1_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_ACS_DIV2) -#define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V) +#define CFG_SDRAM_MAX_SIZE 0x01000000 /* Up to 16 Mbyte */ -#define CFG_MAMR 0x00802114 +#define CFG_MAMR 0x00002114 /* - * 2048 SDRAM rows + * 4096 Up to 4096 SDRAM rows * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 32 PTP (pre-divider from MPTPR) * 4 Number of refresh cycles per period * 64 Refresh cycle in ms per number of rows */ -#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64)) +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00700000 /* 1 ... 7 MB in SDRAM */ +#define CFG_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */ #define CFG_RESET_ADDRESS 0x09900000 @@ -139,6 +138,8 @@ #define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CONFIG_ENV_OVERWRITE + #define CFG_OR0_PRELIM 0xFF000774 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V) diff --git a/include/configs/BMW.h b/include/configs/BMW.h index 050054d..3bd43d8 100644 --- a/include/configs/BMW.h +++ b/include/configs/BMW.h @@ -69,6 +69,10 @@ CFG_CMD_DOC | \ CFG_CMD_ELF | \ 0 ) + +/* CFG_CMD_DOC required legacy NAND support */ +#define CFG_NAND_LEGACY + #if 0 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | \ CFG_CMD_PCI | CFG_CMD_DOC | CFG_CMD_DATE) diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 6025886..1cca285 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -81,6 +81,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 756bb8c..56fd9a6 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -143,8 +143,9 @@ #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ #define CFG_PCI_SUBSYS_DEVICEID 0x040b /* PCI Device ID: CPCI-2DP */ #define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ + +#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ +#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #define CFG_PCI_PTM2LA 0xef000000 /* point to internal regs + PB0/1 */ #define CFG_PCI_PTM2MS 0xff000001 /* 16MB, enable */ @@ -250,14 +251,15 @@ #define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * GPIO definitions */ #define CFG_EEPROM_WP (0x80000000 >> 13) /* GPIO13 */ +#define CFG_SELF_RST (0x80000000 >> 14) /* GPIO14 */ #define CFG_PB_LED (0x80000000 >> 16) /* GPIO16 */ #define CFG_INTA_FAKE (0x80000000 >> 23) /* GPIO23 */ diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index d49020d..047e2f1 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -79,6 +79,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -151,8 +153,8 @@ #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ +#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 13dbe80..d756f44 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -100,6 +100,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -178,8 +180,8 @@ #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ +#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index aaaafa9..852d94a 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -87,6 +87,9 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -161,8 +164,8 @@ #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ +#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 5cd9aba..2260327 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -98,6 +98,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -183,8 +185,8 @@ #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ +#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 8bfd0ee..244e45a 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -57,7 +57,7 @@ #define CONFIG_CPCI750 1 /* this is an CPCI750 board */ -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ +#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ #undef CONFIG_ECC /* enable ECC support */ @@ -70,10 +70,12 @@ #define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX" /*#define CFG_HUSH_PARSER*/ -#undef CFG_HUSH_PARSER +#define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_AUTO_COMPLETE 1 + /* Define which ETH port will be used for connecting the network */ #define CFG_ETH_PORT ETH_0 @@ -82,19 +84,19 @@ * for your console driver. * * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial + * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial * cable onto the second DUART channel, change the CFG_DUART port from 1 * to 0 below. * * to use the MPSC, #define CONFIG_MPSC. If you have wired up another * mpsc channel, change CONFIG_MPSC_PORT to the desired value. */ -#define CONFIG_MPSC +#define CONFIG_MPSC #define CONFIG_MPSC_PORT 0 /* to change the default ethernet port, use this define (options: 0, 1, 2) */ #define CONFIG_NET_MULTI -#define MV_ETH_DEVS 1 +#define MV_ETH_DEVS 1 #define CONFIG_ETHER_PORT 0 #undef CONFIG_ETHER_PORT_MII /* use RMII */ @@ -116,38 +118,38 @@ #define CONFIG_SERIAL "AA000001" #define CONFIG_SERVERIP "10.0.0.79" -#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s" +#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s" #define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n +#define CONFIG_TESTDRAMADDRESS n #define CONFIG_TESETDRAMWALK n /* ----------------------------------------------------------------------------- */ -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ +#undef CONFIG_ALTIVEC /* undef to disable */ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_ASKENV \ - | CFG_CMD_I2C \ + | CFG_CMD_I2C \ | CFG_CMD_CACHE \ | CFG_CMD_EEPROM \ - | CFG_CMD_PCI \ + | CFG_CMD_PCI \ | CFG_CMD_ELF \ | CFG_CMD_DATE \ - | CFG_CMD_NET \ - | CFG_CMD_PING \ - | CFG_CMD_IDE \ - | CFG_CMD_FAT \ - | CFG_CMD_EXT2 \ + | CFG_CMD_NET \ + | CFG_CMD_PING \ + | CFG_CMD_IDE \ + | CFG_CMD_FAT \ + | CFG_CMD_EXT2 \ ) #define CONFIG_DOS_PARTITION @@ -155,28 +157,40 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CONFIG_USE_CPCIDVI + +#ifdef CONFIG_USE_CPCIDVI +#define CONFIG_VIDEO +#define CONFIG_VIDEO_CT69000 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VIDEO_LOGO +#define CONFIG_I8042_KBD +#define CFG_ISA_IO 0 +#endif + /* * Miscellaneous configurable options */ #define CFG_I2C_EEPROM_ADDR_LEN 2 #define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_SPEED 80000 /* I2C speed default */ +#define CFG_I2C_SPEED 80000 /* I2C speed default */ #define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ /*#define CFG_MEMTEST_START 0x00400000*/ /* memtest works on */ /*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ -/*#define CFG_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */ +/*#define CFG_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */ /* #define CFG_DRAM_TEST @@ -184,21 +198,21 @@ * CFG_DRAM_TEST - enables the following tests. * * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. + * Environment variable 'test_dram_data' must be + * set to 'y'. * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. + * addressable. Environment variable + * 'test_dram_address' must be set to 'y'. * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. + * This test takes about 6 minutes to test 64 MB. + * Environment variable 'test_dram_walk' must be + * set to 'y'. */ #define CFG_DRAM_TEST #if defined(CFG_DRAM_TEST) #define CFG_MEMTEST_START 0x00400000 /* memtest works on */ /*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ -#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ +#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ #define CFG_DRAM_TEST_DATA #define CFG_DRAM_TEST_ADDRESS #define CFG_DRAM_TEST_WALK @@ -207,10 +221,10 @@ #define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ #undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ -#define CFG_LOAD_ADDR 0x00300000 /* default load address */ +#define CFG_LOAD_ADDR 0x00300000 /* default load address */ -#define CFG_HZ 1000 /* decr freq: 1ms ticks */ -#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ +#define CFG_HZ 1000 /* decr freq: 1ms ticks */ +#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ #define CFG_BUS_CLK CFG_BUS_HZ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } @@ -237,7 +251,7 @@ * To an unused memory region. The stack will remain in cache until RAM * is initialized */ -#undef CFG_INIT_RAM_LOCK +#undef CFG_INIT_RAM_LOCK /* #define CFG_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */ /* #define CFG_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */ #define CFG_INIT_RAM_ADDR 0xf1080000 /* unused memory region */ @@ -247,7 +261,7 @@ #define RELOCATE_INTERNAL_RAM_ADDR #ifdef RELOCATE_INTERNAL_RAM_ADDR -/*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/ +/*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/ #define CFG_INTERNAL_RAM_ADDR 0xf1080000 #endif @@ -256,28 +270,34 @@ * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE 0x00000000 /* Dummies for BAT 4-7 */ -#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CFG_SDRAM2_BASE 0x20000000 -#define CFG_SDRAM3_BASE 0x30000000 -#define CFG_SDRAM4_BASE 0x40000000 +#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ +#define CFG_SDRAM2_BASE 0x20000000 +#define CFG_SDRAM3_BASE 0x30000000 +#define CFG_SDRAM4_BASE 0x40000000 #define CFG_RESET_ADDRESS 0xfff00100 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MONITOR_BASE 0xfff00000 -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */ /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CFG_FLASH_INCREMENT 0x01000000 /* there is only one bank */ #define CFG_FLASH_PROTECTION 1 /* use hardware protection */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_BASE 0xfc000000 /* start of flash banks */ +#define CFG_FLASH_BASE 0xfc000000 /* start of flash banks */ +#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ +#define CFG_FLASH_INCREMENT 0x01000000 /* size of flash bank */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \ + CFG_FLASH_BASE + 1*CFG_FLASH_INCREMENT, \ + CFG_FLASH_BASE + 2*CFG_FLASH_INCREMENT, \ + CFG_FLASH_BASE + 3*CFG_FLASH_INCREMENT } +#define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */ /* areas to map different things with the GT in physical space */ #define CFG_DRAM_BANKS 4 @@ -288,20 +308,20 @@ /* Peripheral Device section */ /*******************************************************/ -/* We have on the cpci750 Board : */ -/* GT-Chipset Register Area */ -/* GT-Chipset internal SRAM 256k */ -/* SRAM on external device module */ -/* Real time clock on external device module */ -/* dobble UART on external device module */ -/* Data flash on external device module */ -/* Boot flash on external device module */ +/* We have on the cpci750 Board : */ +/* GT-Chipset Register Area */ +/* GT-Chipset internal SRAM 256k */ +/* SRAM on external device module */ +/* Real time clock on external device module */ +/* dobble UART on external device module */ +/* Data flash on external device module */ +/* Boot flash on external device module */ /*******************************************************/ #define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CFG_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */ +#define CFG_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */ -#undef MARVEL_STANDARD_CFG -#ifndef MARVEL_STANDARD_CFG +#undef MARVEL_STANDARD_CFG +#ifndef MARVEL_STANDARD_CFG /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ #define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ /*#define CFG_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */ @@ -313,11 +333,11 @@ #define CFG_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */ #define CFG_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */ -#define CFG_BOOT_SIZE _16M /* cpci750 flash 0 */ -#define CFG_DEV0_SIZE _16M /* cpci750 flash 1 */ -#define CFG_DEV1_SIZE _16M /* cpci750 flash 2 */ -#define CFG_DEV2_SIZE _16M /* cpci750 flash 3 */ -#define CFG_DEV3_SIZE _16M /* cpci750 nvram/can */ +#define CFG_BOOT_SIZE _16M /* cpci750 flash 0 */ +#define CFG_DEV0_SIZE _16M /* cpci750 flash 1 */ +#define CFG_DEV1_SIZE _16M /* cpci750 flash 2 */ +#define CFG_DEV2_SIZE _16M /* cpci750 flash 3 */ +#define CFG_DEV3_SIZE _16M /* cpci750 nvram/can */ /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ #endif @@ -326,22 +346,22 @@ #define CFG_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */ #define CFG_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */ #define CFG_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CFG_DEV3_PAR 0x8FCFFFFF /* nvram/can */ +#define CFG_DEV3_PAR 0x8FCFFFFF /* nvram/can */ #define CFG_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */ - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ + /* c 4 a 8 2 4 1 c */ + /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ /* MPP Control MV64360 Appendix P P. 632*/ -#define CFG_MPP_CONTROL_0 0x00002222 /* */ -#define CFG_MPP_CONTROL_1 0x11110000 /* */ -#define CFG_MPP_CONTROL_2 0x11111111 /* */ -#define CFG_MPP_CONTROL_3 0x00001111 /* */ -/* #define CFG_SERIAL_PORT_MUX 0x00000102*/ /* */ +#define CFG_MPP_CONTROL_0 0x00002222 /* */ +#define CFG_MPP_CONTROL_1 0x11110000 /* */ +#define CFG_MPP_CONTROL_2 0x11111111 /* */ +#define CFG_MPP_CONTROL_3 0x00001111 /* */ +/* #define CFG_SERIAL_PORT_MUX 0x00000102*/ /* */ #define CFG_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/ @@ -358,12 +378,12 @@ ECC disable non registered DRAM */ /* 31:26 25:22 21:20 19 18 17 16 */ - /* 100001 0000 010 0 0 0 0 */ + /* 100001 0000 010 0 0 0 0 */ /* refresh_count=0x400 phisical interleaving disable virtual interleaving enable */ /* 15 14 13:0 */ - /* 0 1 0x400 */ + /* 0 1 0x400 */ # define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ @@ -372,14 +392,14 @@ *----------------------------------------------------------------------- */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ /* PCI MEMORY MAP section */ #define CFG_PCI0_MEM_BASE 0x80000000 @@ -401,6 +421,8 @@ #define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) #define CFG_PCI1_IO_SPACE_PCI 0x00000000 +#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE) + #if defined (CONFIG_750CX) #define CFG_PCI_IDSEL 0x0 #else @@ -411,21 +433,21 @@ * IDE/ATA stuff *----------------------------------------------------------------------- */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET /* no reset for ide supported */ -#define CONFIG_IDE_PREINIT /* check for units */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#define CONFIG_IDE_RESET /* no reset for ide supported */ +#define CONFIG_IDE_PREINIT /* check for units */ -#define CFG_IDE_MAXBUS 2 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */ +#define CFG_IDE_MAXBUS 2 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */ -#define CFG_ATA_BASE_ADDR 0 -#define CFG_ATA_IDE0_OFFSET 0 -#define CFG_ATA_IDE1_OFFSET 0 +#define CFG_ATA_BASE_ADDR 0 +#define CFG_ATA_IDE0_OFFSET 0 +#define CFG_ATA_IDE1_OFFSET 0 -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ /*---------------------------------------------------------------------- @@ -529,7 +551,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization @@ -541,23 +563,23 @@ #define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ #if 0 -#define CFG_ENV_IS_IN_FLASH 0 -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#define CFG_ENV_IS_IN_FLASH 0 +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x10000 #define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ -/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */ +/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */ #endif #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CFG_EEPROM_PAGE_WRITE_BITS 5 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CFG_I2C_EEPROM_ADDR 0x050 +#define CFG_I2C_EEPROM_ADDR 0x050 #define CFG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */ #define CFG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/ #define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ #define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40) +#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40) /*----------------------------------------------------------------------- * Cache Configuration @@ -579,7 +601,7 @@ #if defined (CONFIG_750CX) || defined (CONFIG_750FX) #define L2_INIT 0 #else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) #endif @@ -590,9 +612,9 @@ * * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_BOARD_ASM_INIT 1 +#define CFG_BOARD_ASM_INIT 1 #endif /* __CONFIG_H */ diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h index 16a9ea5..1e9a99e 100644 --- a/include/configs/CPU86.h +++ b/include/configs/CPU86.h @@ -178,6 +178,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + /* * Miscellaneous configurable options */ diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h index a23d7e5..9a98e5c 100644 --- a/include/configs/CPU87.h +++ b/include/configs/CPU87.h @@ -189,6 +189,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + /* * Miscellaneous configurable options */ diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index de8f7ae..6613f90 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -284,6 +284,8 @@ */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + /* * Verbose help from command monitor. */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 131c215..dc40ebc 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -5,6 +5,9 @@ * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * + * (C) Copyright 2006 + * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com + * * See file CREDITS for list of people who contributed to this * project. * @@ -61,9 +64,13 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 + #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ @@ -79,6 +86,7 @@ #else #define CONFIG_VIDEO_SM501_16BPP #endif +#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000 #define CONFIG_CFB_CONSOLE #define CONFIG_VIDEO_LOGO #define CONFIG_VGA_AS_SINGLE_DEVICE @@ -122,6 +130,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + #undef CONFIG_BZIP2 /* include support for bzip2 compressed images */ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -434,9 +444,12 @@ #define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008 #define CFG_FPGA_CTRL_CF_RESET 0x0040 #define CFG_FPGA_CTRL_PS2_PWR 0x0080 -#define CFG_FPGA_CTRL_CF_PWR 0x0100 /* low active */ +#define CFG_FPGA_CTRL_CF_PWRN 0x0100 /* low active */ #define CFG_FPGA_CTRL_CF_BUS_EN 0x0200 #define CFG_FPGA_CTRL_LCD_CLK 0x7000 /* Mask for lcd clock */ +#define CFG_FPGA_CTRL_OW_ENABLE 0x8000 + +#define CFG_FPGA_STATUS_CF_DETECT 0x8000 #define LCD_CLK_OFF 0x0000 /* Off */ #define LCD_CLK_02083 0x1000 /* 2.083 MHz */ diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index eb627e8..f84e356 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -135,6 +135,8 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ +#define CFG_NAND_LEGACY + #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h index 65056a2..706bdb9 100644 --- a/include/configs/ISPAN.h +++ b/include/configs/ISPAN.h @@ -109,7 +109,6 @@ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL \ | CFG_CMD_ASKENV \ | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ | CFG_CMD_IMMAP \ | CFG_CMD_MII \ | CFG_CMD_PING \ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index db2147b..7e57a0f 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -58,7 +58,6 @@ CFG_CMD_CACHE | \ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ CFG_CMD_FAT | \ @@ -87,6 +86,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + #define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " /************************************************************** diff --git a/include/configs/MPC8349ADS.h b/include/configs/MPC8349ADS.h index 5677fa1..1e9a1f7 100644 --- a/include/configs/MPC8349ADS.h +++ b/include/configs/MPC8349ADS.h @@ -149,7 +149,7 @@ #define CONFIG_L1_INIT_RAM #define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ @@ -512,6 +512,10 @@ HRCWH_TSEC2M_IN_GMII ) #endif +/* System IO Config */ +#define CFG_SICRH SICRH_TSOBI1 +#define CFG_SICRL SICRL_LDP_A + #define CFG_HID0_INIT 0x000000000 #define CFG_HID0_FINAL CFG_HID0_INIT @@ -521,7 +525,66 @@ HID0_ENABLE_M_BIT |\ HID0_ENABLE_ADDRESS_BROADCAST ) */ -#define CFG_HID2 0x000000000 +#define CFG_HID2 HID2_HBE + +/* DDR 0 - 256MB */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* stack in DCACHE @ 1GB (no backing mem) */ +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +/* 2G - 3G PCI */ +#ifdef CONFIG_PCI +#define CFG_IBAT2L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT2U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT3U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT2L (0) +#define CFG_IBAT2U (0) +#define CFG_IBAT3L (0) +#define CFG_IBAT3U (0) +#endif + +#ifdef CONFIG_MPC83XX_PCI2 +#define CFG_IBAT4L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT4U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT5L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) +#define CFG_IBAT5L (0) +#define CFG_IBAT5U (0) +#endif + +/* IMMRBAR */ +#define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT6U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* SDRAM, BCSR & FLASH */ +#define CFG_IBAT7L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + /* * Internal Definitions diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h index 565f9bb..831cc5e 100644 --- a/include/configs/MPC86xADS.h +++ b/include/configs/MPC86xADS.h @@ -21,7 +21,7 @@ #define CONFIG_MPC86xADS 1 /* new ADS */ #define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ -/* New MPC86xADS - pick one of these */ +/* CPU type - pick one of these */ #define CONFIG_MPC866T 1 #undef CONFIG_MPC866P #undef CONFIG_MPC859T @@ -33,7 +33,10 @@ #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 38400 -#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */ +#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */ +#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 +#define CFG_8xx_CPUCLK_MIN 40000000 +#define CFG_8xx_CPUCLK_MAX 80000000 #define CONFIG_DRAM_50MHZ 1 #define CONFIG_SDRAM_50MHZ 1 diff --git a/include/configs/MPC885ADS.h b/include/configs/MPC885ADS.h index 74318e5..1867c5b 100644 --- a/include/configs/MPC885ADS.h +++ b/include/configs/MPC885ADS.h @@ -1,44 +1,34 @@ /* * A collection of structures, addresses, and values associated with - * the Motorola DUET ADS board. Values common to all FADS family boards + * the Motorola MPC885ADS board. Values common to all FADS family boards * are in board/fads/fads.h * - * Copyright (C) 2003 Arabella Software Ltd. + * Copyright (C) 2003-2004 Arabella Software Ltd. * Yuli Barcohen <yuli@arabellasw.com> */ #ifndef __CONFIG_H #define __CONFIG_H -/* Board type */ -#define CONFIG_MPC885ADS 1 /* Duet (MPC87x/88x) ADS */ +#define CONFIG_MPC885ADS 1 /* MPC885ADS board */ #define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ -#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ +#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 38400 -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ - -#define CFG_PLPRCR ((1 << PLPRCR_MFD_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS) +#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ +#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 +#define CFG_8xx_CPUCLK_MIN 40000000 +#define CFG_8xx_CPUCLK_MAX 133000000 #define CONFIG_SDRAM_50MHZ 1 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - #include "fads.h" -#undef CFG_SCCR -#define CFG_SCCR (SCCR_TBS|SCCR_EBDF11) - #define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ #define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h index bf4c899..444f721 100644 --- a/include/configs/NETPHONE.h +++ b/include/configs/NETPHONE.h @@ -491,6 +491,7 @@ /****************************************************************/ /* NAND */ +#define CFG_NAND_LEGACY #define CFG_NAND_BASE NAND_BASE #define CONFIG_MTD_NAND_ECC_JFFS2 #define CONFIG_MTD_NAND_VERIFY_WRITE diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h index 529cb4c..e20e724 100644 --- a/include/configs/NETTA2.h +++ b/include/configs/NETTA2.h @@ -491,6 +491,7 @@ /****************************************************************/ /* NAND */ +#define CFG_NAND_LEGACY #define CFG_NAND_BASE NAND_BASE #define CONFIG_MTD_NAND_ECC_JFFS2 #define CONFIG_MTD_NAND_VERIFY_WRITE diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h index dc6b15f..e30be09 100644 --- a/include/configs/NETVIA.h +++ b/include/configs/NETVIA.h @@ -387,6 +387,8 @@ /*****************************************************************************/ +#define CFG_NAND_LEGACY + #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 /* NAND */ diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h index d03706e..3a97fbc 100644 --- a/include/configs/PCIPPC2.h +++ b/include/configs/PCIPPC2.h @@ -77,6 +77,7 @@ */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY /* * Miscellaneous configurable options diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h index 92b2f7c..130beb7 100644 --- a/include/configs/PCIPPC6.h +++ b/include/configs/PCIPPC6.h @@ -79,6 +79,7 @@ */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY /* * Miscellaneous configurable options diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 9668fb0..806e95f 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -50,7 +50,6 @@ CFG_CMD_PCI | \ CFG_CMD_CACHE | \ CFG_CMD_IRQ | \ - CFG_CMD_ECHO | \ CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_REGINFO | \ @@ -69,6 +68,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + #define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " /************************************************************** diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 54ecfa4..dd5d831 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -160,6 +160,8 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ +#define CFG_NAND_LEGACY + #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/PM520.h b/include/configs/PM520.h index 812bfd0..9c241e6 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -101,6 +101,8 @@ #define ADD_DOC_CMD 0 #else #define ADD_DOC_CMD CFG_CMD_DOC +/* DoC requires legacy NAND for now */ +#define CFG_NAND_LEGACY #endif /* @@ -327,11 +329,11 @@ #define CFG_CS0_SIZE CFG_BOOTROM_SIZE #define CFG_CS1_START CFG_FLASH_BASE #define CFG_CS1_SIZE CFG_FLASH_SIZE -#define CFG_CS1_CFG 0x0004fb00 +#define CFG_CS1_CFG 0x0004FF00 #else #define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x0004fb00 +#define CFG_BOOTCS_CFG 0x0004FF00 #define CFG_CS0_START CFG_FLASH_BASE #define CFG_CS0_SIZE CFG_FLASH_SIZE #define CFG_CS1_START CFG_DOC_BASE diff --git a/include/configs/PM826.h b/include/configs/PM826.h index 6e5e3bb..88fdb51 100644 --- a/include/configs/PM826.h +++ b/include/configs/PM826.h @@ -180,6 +180,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + /* * Disk-On-Chip configuration */ diff --git a/include/configs/PM828.h b/include/configs/PM828.h index 982a1f8..37ee977 100644 --- a/include/configs/PM828.h +++ b/include/configs/PM828.h @@ -183,6 +183,7 @@ /* * Disk-On-Chip configuration */ +#define CFG_NAND_LEGACY #define CFG_DOC_SHORT_TIMEOUT #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index 8bcab0b..6e0bd7f 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -53,9 +53,15 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 + #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ CFG_CMD_BSP | \ @@ -154,15 +160,24 @@ #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */ +#define CFG_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID: Non-Monarch */ +#define CFG_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID: Monarch */ +#define CFG_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid() + #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ + +#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ +#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#if 1 +#define CFG_PCI_PTM2LA 0xef000000 /* point to internal regs */ +#define CFG_PCI_PTM2MS 0xff000001 /* 16MB, enable */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ +#else /* old mapping */ #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - +#endif /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) @@ -259,7 +274,7 @@ #define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */ #define CAN_BA 0xF0000000 /* CAN Base Address */ #define RTC_BA 0xF0000500 /* RTC Base Address */ -#define CF_BA 0xF0100000 /* CompactFlash Base Address */ +#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */ /* Memory Bank 0 (Flash Bank 0) initialization */ #define CFG_EBC_PB0AP 0x92015480 @@ -273,9 +288,11 @@ #define CFG_EBC_PB2AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ #define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */ -#define CFG_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ +/* Memory Bank 3 -> unused */ + +/* Memory Bank 4 (NVRAM) initialization */ +#define CFG_EBC_PB4AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ +#define CFG_EBC_PB4CR NVRAM_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ /*----------------------------------------------------------------------- * FPGA stuff @@ -293,6 +310,15 @@ #define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ /*----------------------------------------------------------------------- + * GPIOs + */ +#define CFG_NONMONARCH (0x80000000 >> 14) /* GPIO24 */ +#define CFG_XEREADY (0x80000000 >> 15) /* GPIO15 */ +#define CFG_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */ +#define CFG_SELF_RST (0x80000000 >> 21) /* GPIO21 */ +#define CFG_REV1_2 (0x80000000 >> 23) /* GPIO23 */ + +/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in data cache) */ diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 7ca827f..e1155e2 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -188,34 +188,34 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ +/* + * nand device 1 on dave (PPChameleonEVB) needs more time, + * so we just introduce additional wait in nand_wait(), + * effectively for both devices. + */ +#define PPCHAMELON_NAND_TIMER_HACK + #define CFG_NAND0_BASE 0xFF400000 #define CFG_NAND1_BASE 0xFF000000 +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, CFG_NAND1_BASE } +#define NAND_BIG_DELAY_US 25 +#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ -#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ -#define SECTORSIZE 512 -#define NAND_NO_RB - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 #define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ #define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ #define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */ +#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ #define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */ #define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ -#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ -#define NAND_DISABLE_CE(nand) do \ +#define MACRO_NAND_DISABLE_CE(nandptr) do \ { \ - switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ + switch((unsigned long)nandptr) \ { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \ @@ -226,9 +226,9 @@ } \ } while(0) -#define NAND_ENABLE_CE(nand) do \ +#define MACRO_NAND_ENABLE_CE(nandptr) do \ { \ - switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ + switch((unsigned long)nandptr) \ { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \ @@ -239,7 +239,7 @@ } \ } while(0) -#define NAND_CTL_CLRALE(nandptr) do \ +#define MACRO_NAND_CTL_CLRALE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -252,7 +252,7 @@ } \ } while(0) -#define NAND_CTL_SETALE(nandptr) do \ +#define MACRO_NAND_CTL_SETALE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -265,7 +265,7 @@ } \ } while(0) -#define NAND_CTL_CLRCLE(nandptr) do \ +#define MACRO_NAND_CTL_CLRCLE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -278,7 +278,7 @@ } \ } while(0) -#define NAND_CTL_SETCLE(nandptr) do { \ +#define MACRO_NAND_CTL_SETCLE(nandptr) do { \ switch((unsigned long)nandptr) { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \ @@ -289,6 +289,17 @@ } \ } while(0) +#if 0 +#define SECTORSIZE 512 +#define NAND_NO_RB + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 + #ifdef NAND_NO_RB /* constant delay (see also tR in the datasheet) */ #define NAND_WAIT_READY(nand) do { \ @@ -303,7 +314,7 @@ #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - +#endif /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -338,16 +349,16 @@ #define CFG_SDRAM_BASE 0x00000000 /* Reserve 256 kB for Monitor */ +/* #define CFG_FLASH_BASE 0xFFFC0000 #define CFG_MONITOR_BASE CFG_FLASH_BASE #define CFG_MONITOR_LEN (256 * 1024) +*/ /* Reserve 320 kB for Monitor */ -/* #define CFG_FLASH_BASE 0xFFFB0000 #define CFG_MONITOR_BASE CFG_FLASH_BASE #define CFG_MONITOR_LEN (320 * 1024) -*/ #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h index 242c837..21945a3 100644 --- a/include/configs/RBC823.h +++ b/include/configs/RBC823.h @@ -326,6 +326,8 @@ /************************************************************ * Disk-On-Chip configuration ************************************************************/ +#define CFG_NAND_LEGACY + #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ #define CFG_DOC_SHORT_TIMEOUT #define CFG_DOC_SUPPORT_2000 diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h index 6b65031..48ada0e 100644 --- a/include/configs/RPXlite.h +++ b/include/configs/RPXlite.h @@ -21,10 +21,6 @@ * MA 02111-1307 USA */ -/* - * board/config.h - configuration options, board specific - */ - /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr * U-Boot port on RPXlite board */ @@ -53,8 +49,6 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp; " \ @@ -65,6 +59,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) @@ -86,12 +81,14 @@ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x0040000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_RESET_ADDRESS 0x09900000 -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_LOAD_ADDR 0x400000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } @@ -120,16 +117,14 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFC00000 -/*%%% #define CFG_FLASH_BASE 0xFFF00000 */ -#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) +#define CFG_FLASH_BASE 0xFFC00000 +#define CFG_MONITOR_BASE TEXT_BASE #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#ifdef CONFIG_BZIP2 +#define CFG_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */ #else -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE 0xFFF00000 -/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ +#endif /* CONFIG_BZIP2 */ /* * For booting Linux, the board info and command line data @@ -147,9 +142,13 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_DIRECT_FLASH_TFTP + #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + +#define CONFIG_ENV_OVERWRITE /*----------------------------------------------------------------------- * Cache Configuration @@ -352,12 +351,12 @@ #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ #define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ +#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ +#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ #define BCSR0_COLTEST 0x20 #define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 +#define BCSR0_ETHEN 0x80 #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ #define BCSR1_PCVCTL6 0x02 @@ -371,22 +370,13 @@ #define BCSR2_USBSPD 0x40 #define BCSR2_USBSUSP 0x80 -#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ -#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ +#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ +#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ #define BCSR3_RDY_BSY 0x04 /* Flash Operation */ -#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - - -/* - * Environment setting - */ - -#define CONFIG_ETHADDR 00:10:EC:00:1D:0B -#define CONFIG_IPADDR 192.168.1.65 -#define CONFIG_SERVERIP 192.168.1.27 +#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ +#define BCSR3_D27 0x10 /* Dip Switch settings */ +#define BCSR3_D26 0x20 +#define BCSR3_D25 0x40 +#define BCSR3_D24 0x80 #endif /* __CONFIG_H */ diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h index 8cd7df1..5d17712 100644 --- a/include/configs/RPXlite_DW.h +++ b/include/configs/RPXlite_DW.h @@ -45,7 +45,7 @@ */ /* #define DEBUG 1 */ -/* #ifdef DEPLOYMENT 1 */ +/* #define DEPLOYMENT 1 */ #undef CONFIG_MPC860 #define CONFIG_MPC823 1 /* This is a MPC823e CPU. */ @@ -117,6 +117,36 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +#if 1 /* Enable this staff could make image enlarge about 25KB. Mask it if you + don't want the advanced function */ + +#ifdef CONFIG_SPLASH_SCREEN +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BMP | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_REGINFO | \ + CFG_CMD_DHCP ) +#else +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_REGINFO | \ + CFG_CMD_DHCP ) +#endif /* CONFIG_SPLASH_SCREEN */ + +/* test-only */ +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ + +#define CONFIG_NETCONSOLE + +#endif /* 1 */ + /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -446,5 +476,6 @@ #define CONFIG_SERVERIP 172.16.115.6 #define CONFIG_ROOTPATH /workspace/myfilesystem/target/ #define CONFIG_BOOTFILE uImage.rpxusb +#define CONFIG_HOSTNAME LITE_H1_DW #endif /* __CONFIG_H */ diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h index 6ae9403..45907aa 100644 --- a/include/configs/RPXsuper.h +++ b/include/configs/RPXsuper.h @@ -154,7 +154,6 @@ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ CFG_CMD_IMMAP | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_I2C | \ CFG_CMD_REGINFO & \ ~CFG_CMD_KGDB ) diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h index a170f29..dbc57e8 100644 --- a/include/configs/Rattler.h +++ b/include/configs/Rattler.h @@ -127,7 +127,6 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ | CFG_CMD_IMMAP \ | CFG_CMD_JFFS2 \ | CFG_CMD_MII \ diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h index c1c765f..a8454d9 100644 --- a/include/configs/SXNI855T.h +++ b/include/configs/SXNI855T.h @@ -183,6 +183,7 @@ */ /* NAND flash support */ +#define CFG_NAND_LEGACY #define CONFIG_MTD_NAND_ECC_JFFS2 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 5ad1939..6020998 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -161,7 +161,6 @@ CFG_CMD_ASKENV | \ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_JFFS2 | \ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 41f44c5..cec7e3e 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -417,11 +417,58 @@ extern int tqm834x_num_flash_banks; HRCWH_TSEC2M_IN_GMII ) #endif +/* System IO Config */ +#define CFG_SICRH SICRH_TSOBI1 +#define CFG_SICRL SICRL_LDP_A + /* i-cache and d-cache disabled */ #define CFG_HID0_INIT 0x000000000 #define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID2 0x000000000 +/* DDR 0 - 512M */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT1L (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +/* stack in DCACHE @ 512M (no backing mem) */ +#define CFG_IBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +/* PCI */ +#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP) + +/* IMMRBAR */ +#define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT6U (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP) + +/* FLASH */ +#define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + /* * Internal Definitions * diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 3ca137e..96f3d26 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -141,6 +141,8 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ +#define CFG_NAND_LEGACY + #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index d92f81f..faf855d 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -133,6 +133,8 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ +#define CFG_NAND_LEGACY + #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h index f71e691..a5085cf 100644 --- a/include/configs/ZPC1900.h +++ b/include/configs/ZPC1900.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2003-2004 Arabella Software Ltd. + * Copyright (C) 2003-2005 Arabella Software Ltd. * Yuli Barcohen <yuli@arabellasw.com> * * U-Boot configuration for Zephyr Engineering ZPC.1900 board. @@ -32,11 +32,7 @@ #define CPU_ID_STR "MPC8265" #define CONFIG_CPM2 1 /* Has a CPM2 */ -#undef DEBUG - -#undef CONFIG_BOARD_EARLY_INIT_F /* Don't call board_early_init_f */ - -/* Allow serial number (serial) and MAC address (ethaddr) to be overwritten */ +/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ #define CONFIG_ENV_OVERWRITE /* @@ -113,7 +109,6 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_ASKENV \ | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ | CFG_CMD_IMMAP \ | CFG_CMD_MII \ | CFG_CMD_PING \ @@ -154,31 +149,30 @@ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ +#define CFG_MEMTEST_END 0x03800000 /* 1 ... 56 MB in DRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_LOAD_ADDR 0x400000 /* default load address */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#define CFG_FLASH_BASE 0xFFE00000 -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ - -#define CFG_DEFAULT_IMMR 0x0F010000 - -#define CFG_IMMR 0xF0000000 #define CFG_SDRAM_BASE 0x00000000 #define CFG_SDRAM_SIZE 64 -#define CFG_FLSIMM_BASE 0xFC000000 -#define CFG_LSDRAM_BASE 0xFE000000 + +#define CFG_IMMR 0xF0000000 +#define CFG_LSDRAM_BASE 0xFC000000 +#define CFG_FLASH_BASE 0xFE000000 #define CFG_BCSR 0xFEA00000 #define CFG_EEPROM 0xFEB00000 +#define CFG_FLSIMM_BASE 0xFF000000 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLSIMM_BASE } #define BCSR_PCI_MODE 0x01 @@ -190,10 +184,10 @@ /* Hard reset configuration word */ #define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01| HRCW_CIP |\ - HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB010 |\ - HRCW_BMS | HRCW_LBPC01 | HRCW_APPC10 |\ - HRCW_MODCK_H0101 \ - ) /* 0x16828605 */ + HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\ + HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10 |\ + HRCW_MODCK_H0111 \ + ) /* 0x16848207 */ /* No slaves */ #define CFG_HRCW_SLAVE1 0 #define CFG_HRCW_SLAVE2 0 @@ -211,7 +205,7 @@ #define CFG_RAMBOOT #endif -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ @@ -233,14 +227,14 @@ # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) +#define CFG_HID0_INIT (HID0_ICFI) +#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) #define CFG_HID2 0 #define CFG_SIUMCR 0x42200000 #define CFG_SYPCR 0xFFFFFFC3 -#define CFG_BCR 0x90400000 +#define CFG_BCR 0x90000000 #define CFG_SCCR SCCR_DFBRG01 #define CFG_RMR RMR_CSRE @@ -248,18 +242,23 @@ #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) #define CFG_RCCR 0 -#define CFG_PSDMR 0x014EB45A -#define CFG_PSRT 0x0C -#define CFG_LSDMR 0x008AB552 -#define CFG_LSRT 0x0E +#define CFG_PSDMR /* 0x834DA43B */0x014DA43A +#define CFG_PSRT 0x0F/* 0x0C */ +#define CFG_LSDMR 0x0085A562 +#define CFG_LSRT 0x0F #define CFG_MPTPR 0x4000 +#define CFG_PSDRAM_BR CFG_SDRAM_BASE | 0x00000041 +#define CFG_PSDRAM_OR 0xFC0028C0 +#define CFG_LSDRAM_BR CFG_LSDRAM_BASE | 0x00001861 +#define CFG_LSDRAM_OR 0xFF803480 + #define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801 #define CFG_OR0_PRELIM 0xFFE00856 #define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801 #define CFG_OR5_PRELIM 0xFFFF03F6 -#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00000801 -#define CFG_OR6_PRELIM 0xFE000856 +#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00001801 +#define CFG_OR6_PRELIM 0xFF000856 #define CFG_BR7_PRELIM CFG_BCSR | 0x00000801 #define CFG_OR7_PRELIM 0xFFFF83F6 diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index eacc744..6d32821 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -43,6 +43,7 @@ * 2nd ethernet port you have to "undef" the following define. */ #define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */ +#define CFG_NAND_LEGACY /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the diff --git a/include/configs/delta.h b/include/configs/delta.h new file mode 100644 index 0000000..b42a7e2 --- /dev/null +++ b/include/configs/delta.h @@ -0,0 +1,287 @@ +/* + * Configuation settings for the Delta board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */ +#define CONFIG_DELTA 1 /* Delta board */ + +/* #define CONFIG_LCD 1 */ +#ifdef CONFIG_LCD +#define CONFIG_SHARP_LM8V31 +#endif +/* #define CONFIG_MMC 1 */ +#define BOARD_LATE_INIT 1 + +#undef CONFIG_SKIP_RELOCATE_UBOOT +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +#undef TURN_ON_ETHERNET +#ifdef TURN_ON_ETHERNET +# define CONFIG_DRIVER_SMC91111 1 +# define CONFIG_SMC91111_BASE 0x14000300 +# define CONFIG_SMC91111_EXT_PHY +# define CONFIG_SMC_USE_32_BIT +# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */ +#endif + +/* + * select serial console configuration + */ +#define CONFIG_FFUART 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +/* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */ +#ifdef TURN_ON_ETHERNET +# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING) +#else +# define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_ENV | CFG_CMD_NAND) \ + & ~(CFG_CMD_NET | CFG_CMD_FLASH | CFG_CMD_IMLS)) +#endif + + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_BOOTDELAY -1 +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_IPADDR 192.168.0.21 +#define CONFIG_SERVERIP 192.168.0.250 +#define CONFIG_BOOTCOMMAND "bootm 80000" +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" +#define CONFIG_CMDLINE_TAG +#define CONFIG_TIMESTAMP + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* #define CFG_MMC_BASE 0xF0000000 */ + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa1000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */ +#define PHYS_SDRAM_3 0xa2000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */ +#define PHYS_SDRAM_4 0xa3000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */ + +#define CFG_DRAM_BASE 0xa0000000 /* at CS0 */ +#define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */ + +#undef CFG_SKIP_DRAM_SCRUB + +/* + * NAND Flash + */ +/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */ +#define CONFIG_NEW_NAND_CODE +#define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */ +#undef CFG_NAND1_BASE + +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE } +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 +#define NAND_DELAY_US 25 /* mk@tbd: could be 0, I guess */ + +/* nand timeout values */ +#define CFG_NAND_PROG_ERASE_TO 3000 +#define CFG_NAND_OTHER_TO 100 +#define CFG_NAND_SENDCMD_RETRY 3 +#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */ + +/* NAND Timing Parameters (in ns) */ +#define NAND_TIMING_tCH 10 +#define NAND_TIMING_tCS 0 +#define NAND_TIMING_tWH 20 +#define NAND_TIMING_tWP 40 + +#define NAND_TIMING_tRH 20 +#define NAND_TIMING_tRP 40 + +#define NAND_TIMING_tR 11123 +/* #define NAND_TIMING_tWHR 110 */ +#define NAND_TIMING_tWHR 100 +#define NAND_TIMING_tAR 10 + +/* NAND debugging */ +#define CFG_DFC_DEBUG1 /* usefull */ +#undef CFG_DFC_DEBUG2 /* noisy */ +#undef CFG_DFC_DEBUG3 /* extremly noisy */ + +#define CONFIG_MTD_DEBUG +#define CONFIG_MTD_DEBUG_VERBOSE 1 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NO_FLASH 1 +#ifndef CGF_NO_FLASH +/* these are required by the environment code */ +#define PHYS_FLASH_1 CFG_NAND0_BASE /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x04000000 /* 64 MB */ +#define PHYS_FLASH_BANK_SIZE 0x04000000 /* 64 MB Banks */ +#define PHYS_FLASH_SECT_SIZE (SECTORSIZE*1024) /* KB sectors (x2) */ +#endif + +/* + * GPIO settings + */ +#define CFG_GPSR0_VAL 0x00008000 +#define CFG_GPSR1_VAL 0x00FC0382 +#define CFG_GPSR2_VAL 0x0001FFFF +#define CFG_GPCR0_VAL 0x00000000 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 +#define CFG_GPDR0_VAL 0x0060A800 +#define CFG_GPDR1_VAL 0x00FF0382 +#define CFG_GPDR2_VAL 0x0001C000 +#define CFG_GAFR0_L_VAL 0x98400000 +#define CFG_GAFR0_U_VAL 0x00002950 +#define CFG_GAFR1_L_VAL 0x000A9558 +#define CFG_GAFR1_U_VAL 0x0005AAAA +#define CFG_GAFR2_L_VAL 0xA0000000 +#define CFG_GAFR2_U_VAL 0x00000002 + +#define CFG_PSSR_VAL 0x20 + +/* + * Memory settings + */ +#define CFG_MSC0_VAL 0x23F223F2 +#define CFG_MSC1_VAL 0x3FF1A441 +#define CFG_MSC2_VAL 0x7FF97FF1 +#define CFG_MDCNFG_VAL 0x00001AC9 +#define CFG_MDREFR_VAL 0x00018018 +#define CFG_MDMRS_VAL 0x00000000 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000000 +#define CFG_MCMEM0_VAL 0x00010504 +#define CFG_MCMEM1_VAL 0x00010504 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00004715 +#define CFG_MCIO1_VAL 0x00004715 + +#define _LED 0x08000010 +#define LED_BLANK 0x08000040 + +/* + * FLASH and environment organization + */ +#ifndef CFG_NO_FLASH +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + + +/* NOTE: many default partitioning schemes assume the kernel starts at the + * second sector, not an environment. You have been warned! + */ +#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE +#endif /* #ifndef CFG_NO_FLASH */ + +/* #define CFG_ENV_IS_NOWHERE */ +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_OFFSET 0x40000 +#define CFG_ENV_SIZE 0x4000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/ezkit533.h b/include/configs/ezkit533.h new file mode 100644 index 0000000..5eda673 --- /dev/null +++ b/include/configs/ezkit533.h @@ -0,0 +1,188 @@ +#ifndef __CONFIG_EZKIT533_H__ +#define __CONFIG_EZKIT533_H__ + +#define CFG_LONGHELP 1 +#define CONFIG_BAUDRATE 57600 +#define CONFIG_STAMP 1 +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x20310300 +#if 0 +#define CONFIG_MII +#define CFG_DISCOVER_PHY +#endif + +#define CONFIG_RTC_BF533 1 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ + +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 27000000 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 22 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + +#if ( CONFIG_CLKIN_HALF == 0 ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#else +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#endif + +#if (CONFIG_PLL_BYPASS == 0) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#endif + +#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_MT48LC16M16A2TG_75 1 + +#define CONFIG_LOADS_ECHO 1 + + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_DATE) +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off" + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01F00000 /* 1 ... 31 MB in DRAM */ +#define CFG_LOAD_ADDR 0x01000000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE 0x02000000 +#define CFG_FLASH_BASE 0x20000000 + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_SIZE 0x4000 +#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) + +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_FLASH0_BASE 0x20000000 +#define CFG_FLASH1_BASE 0x20200000 +#define CFG_FLASH2_BASE 0x20280000 +#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x20020000 +#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ + +/* JFFS Partition offset set */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CFG_JFFS2_FIRST_SECTOR 11 + + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +#define POLL_MODE 1 +#define FLASH_TOT_SECT 40 +#define FLASH_SIZE 0x220000 +#define CFG_FLASH_SIZE 0x220000 + +/* + * Initialize PSD4256 registers for using I2C + */ +#define CONFIG_MISC_INIT_R + +/* + * I2C settings + * By default PF1 is used as SDA and PF0 as SCL on the Stamp board + */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +/* + * Software (bit-bang) I2C driver configuration + */ +#define PF_SCL PF0 +#define PF_SDA PF1 + +#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") +#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") +#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") +#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") +#define I2C_SDA(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SDA; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SDA; \ + asm("ssync;"); \ + } +#define I2C_SCL(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SCL; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SCL; \ + asm("ssync;"); \ + } +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE + + +#define __ADSPLPBLACKFIN__ 1 +#define __ADSPBF533__ 1 + +/* 0xFF, 0x7BB07BB0, 0x22547BB0 */ +/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ + ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) +#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ + B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) +*/ +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0x7BB07BB0 +#define AMBCTL1VAL 0xFFC27BB0 + +#define CONFIG_VDSP 1 + +#ifdef CONFIG_VDSP +#define ET_EXEC_VDSP 0x8 +#define SHT_STRTAB_VDSP 0x1 +#define ELFSHDRSIZE_VDSP 0x2C +#define VDSP_ENTRY_ADDR 0xFFA00000 +#endif + +#endif diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h index 6c08043..4f83b19 100644 --- a/include/configs/gw8260.h +++ b/include/configs/gw8260.h @@ -305,7 +305,6 @@ CFG_CMD_BEDBUG | \ CFG_CMD_ELF | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_REGINFO | \ CFG_CMD_IMMAP | \ CFG_CMD_MII) diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index c0cc4f1..773d5d2 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -101,7 +101,7 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ @@ -109,6 +109,16 @@ #undef CONFIG_BOOTARGS +#define CONFIG_ETHADDR 00:a0:a4:03:00:00 +#define CONFIG_OVERWRITE_ETHADDR_ONCE + +#define CONFIG_IPADDR 192.168.100.2 +#define CONFIG_SERVERIP 192.168.100.1 +#define CONFIG_NETMASK 255.255.255.0 +#define HOSTNAME inka4x0 +#define CONFIG_BOOTFILE /tftpboot/inka4x0/uImage +#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx + #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ @@ -117,13 +127,22 @@ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ + "addcons=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate}\0" \ + "flash_nfs=run nfsargs addip addcons;" \ "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ + "net_nfs=tftp 200000 ${bootfile};" \ + "run nfsargs addip addcons;bootm\0" \ + "enable_disp=mw.l 100000 04000000 1;" \ + "cp.l 100000 f0000b20 1;" \ + "cp.l 100000 f0000b28 1\0" \ + "ideargs=setenv bootargs root=/dev/hda1 rw\0" \ + "ide_boot=ext2load ide 0:1 200000 uImage;" \ + "run ideargs addip addcons enable_disp;bootm" \ + "brightness=255\0" \ "" -#define CONFIG_BOOTCOMMAND "run net_nfs" +#define CONFIG_BOOTCOMMAND "run ide_boot" /* * IPB Bus clocking configuration. @@ -193,6 +212,7 @@ */ /* #define CONFIG_FEC_10MBIT 1 */ #define CONFIG_PHY_ADDR 0x00 +#define CONFIG_MII /* * GPIO configuration diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h new file mode 100644 index 0000000..d4dee3b --- /dev/null +++ b/include/configs/mcc200.h @@ -0,0 +1,281 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5200 +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MCC200 1 /* ... on MCC200 board */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ + +#define CONFIG_MISC_INIT_R + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CONFIG_MII 1 + +#define CONFIG_DOS_PARTITION + +/* USB */ +#define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +#define CONFIG_USB_STORAGE + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + ADD_USB_CMD | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=mcc200\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "bootfile=/tftpboot/mcc200/uImage\0" \ + "baudrate=115200\0" \ + "load=tftp 200000 /tftpboot/mcc200/u-boot.bin\0" \ + "update=protect off FFF00000 +${filesize};" \ + "era FFF00000 +${filesize};" \ + "cp.b 200000 FFF00000 ${filesize}\0" \ + "serverip=192.168.1.1\0" \ + "ipaddr=192.168.133.144\0" \ + "netmask=255.255.0.0\0" \ + "unlock=yes\0" \ + "ethaddr=00:02:44:7D:73:3B\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#define CFG_PROMPT_HUSH_PS2 "> " + +/* + * IPB Bus clocking configuration. + */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x58 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* + * RTC configuration + */ +#define CONFIG_RTC_PCF8563 +#define CFG_I2C_RTC_ADDR 0x51 + +/* + * Flash configuration (8,16 or 32 MB) + * TEXT base always at 0xFFF00000 + * ENV_ADDR always at 0xFFF40000 + * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!) + * 0xFE000000 for 32 MB + * 0xFF000000 for 16 MB + * 0xFF800000 for 8 MB + */ +#define CFG_FLASH_BASE 0xfc000000 +#define CFG_FLASH_SIZE 0x04000000 + +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ + +/* + * Memory map + */ +#define CFG_MBAR 0xf0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 1 + +/* + * GPIO configuration + */ +/* 0x10000004 = 32MB SDRAM */ +/* 0x90000004 = 64MB SDRAM */ +#define CFG_GPS_PORT_CONFIG 0x10000004 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Various low-level settings + */ +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x0004fb00 +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00005000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/netstar.h b/include/configs/netstar.h new file mode 100644 index 0000000..697796a --- /dev/null +++ b/include/configs/netstar.h @@ -0,0 +1,265 @@ +/* + * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl + * + * Configuation settings for the TI OMAP NetStar board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/omap1510.h> + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP1510 1 /* which is in a 5910 */ + +/* Input clock of PLL */ +#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */ +#define CONFIG_XTAL_FREQ 12000000 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_MISC_INIT_R /* There is nothing to really init */ +#define BOARD_LATE_INIT /* but we flash the LEDs here */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CFG_DEVICE_NULLDEV 1 /* enable null device */ +#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +/* + * FLASH organization + */ +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MAX_FLASH_BANKS 1 +#if (PHYS_SDRAM_1_SIZE == SZ_32M) +/*#if 1*/ +#define CFG_FLASH_CFI /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER /* Use the common driver */ +#define CFG_FLASH_EMPTY_INFO +#define CFG_MAX_FLASH_SECT 128 +#else +#define PHYS_FLASH_1_SIZE SZ_1M +#define CFG_MAX_FLASH_SECT 19 +#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* in ticks */ +#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) +#endif + +#define CFG_MONITOR_BASE PHYS_FLASH_1 +#define CFG_MONITOR_LEN SZ_256K + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH +#define ENV_IS_SOLITARY +#define CFG_ENV_ADDR 0x4000 +#define CFG_ENV_SIZE SZ_8K +#define CFG_ENV_SECT_SIZE SZ_8K +#define CFG_ENV_ADDR_REDUND 0x6000 +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE +#define CONFIG_ENV_OVERWRITE + +/* + * Size of malloc() pool + */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +/* XXX #define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE)*/ +#define CFG_MALLOC_LEN SZ_4M + +/* + * The stack size is set up in start.S using the settings below + */ +/* XXX #define CONFIG_STACKSIZE SZ_8K /XXX* regular stack */ +#define CONFIG_STACKSIZE SZ_1M /* regular stack */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_SMC91111 +#define CONFIG_SMC91111_BASE 0x04000300 + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */ +#define CFG_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */ + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*#define CONFIG_SKIP_RELOCATE_UBOOT*/ +/*#define CONFIG_SKIP_LOWLEVEL_INIT */ + +/* + * NAND flash + */ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE 0x04000000 + (2 << 23) + +/* + * JFFS2 partitions (mtdparts command line support) + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0" +#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);omapnand.0:48M(rootfs0),48M(rootfs1),-(data)" + +#if 0 +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_BOOTD | \ + CFG_CMD_DHCP | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_LOADB | \ + CFG_CMD_NET | \ + CFG_CMD_MEMORY | \ + CFG_CMD_PING | \ + CFG_CMD_RUN) + +#else +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_BOOTD | \ + CFG_CMD_DHCP | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_NAND | \ + CFG_CMD_IMI | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_LOADB | \ + CFG_CMD_NET | \ + CFG_CMD_MEMORY | \ + CFG_CMD_PING | \ + CFG_CMD_RUN) + +#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ +#endif + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +#define CONFIG_LOOPW + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ +#define CFG_AUTOLOAD "n" /* No autoload */ +#define CONFIG_BOOTCOMMAND "run nboot" +#define CONFIG_PREBOOT "run setup" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "setup=setenv bootargs console=ttyS0,$baudrate " \ + "$mtdparts\0" \ + "ospart=0\0" \ + "setpart=" \ + "if test -n $swapos; then " \ + "if test $ospart -eq 0; then chpart nand0,1; else chpart nand0,0; fi; "\ + "setenv swapos; saveenv; " \ + "else " \ + "chpart nand0,$ospart; " \ + "fi\0" \ + "nfsargs=setenv bootargs $bootargs " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ + "nfsroot=$rootpath root=/dev/nfs\0" \ + "flashargs=run setpart;setenv bootargs $bootargs " \ + "root=/dev/mtdblock$partition ro " \ + "rootfstype=jffs2\0" \ + "initrdargs=setenv bootargs $bootargs " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ + "iboot=bootp;run initrdargs;tftp;bootm\0" \ + "fboot=run flashargs;fsload /boot/uImage;bootm\0" \ + "nboot=bootp;run nfsargs;tftp;bootm\0" + +#if 0 /* feel free to disable for development */ +#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ +#define CONFIG_AUTOBOOT_PROMPT "\nNetStar PBX - boot in %d sec...\n" +#define CONFIG_AUTOBOOT_DELAY_STR "R" /* 1st "password" */ +#define CONFIG_BOOT_RETRY_TIME 30 +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "# " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTO_COMPLETE + +#define CFG_MEMTEST_START PHYS_SDRAM_1 +#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */ + +/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. + * This time is further subdivided by a local divisor. + */ +#define CFG_TIMERBASE OMAP1510_TIMER1_BASE +#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ +#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) + +#define OMAP5910_DPLL_DIV 1 +#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \ + (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ) + +#define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */ +#define OMAP5910_LCD_DIV 2 /* CKL/4 */ +#define OMAP5910_ARM_DIV 0 /* CKL/1 */ +#define OMAP5910_DSP_DIV 0 /* CKL/1 */ +#define OMAP5910_TC_DIV 1 /* CKL/2 */ +#define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */ +#define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */ + +#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */ +#define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \ + (OMAP5910_LCD_DIV << 2) | \ + (OMAP5910_ARM_DIV << 4) | \ + (OMAP5910_DSP_DIV << 6) | \ + (OMAP5910_TC_DIV << 8) | \ + (OMAP5910_DSP_MMU_DIV << 10) | \ + (OMAP5910_ARM_TIM_SEL << 12)) + +#endif /* __CONFIG_H */ diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h index 75792221..d671dcc 100644 --- a/include/configs/ppmc8260.h +++ b/include/configs/ppmc8260.h @@ -279,7 +279,6 @@ #define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ CFG_CMD_ELF | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_REGINFO | \ CFG_CMD_MEMTEST | \ CFG_CMD_MII | \ diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index 4e0cfdb..97b52fa 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -507,7 +507,6 @@ # define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ CFG_CMD_ELF | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_I2C | \ CFG_CMD_SPI | \ CFG_CMD_SDRAM | \ @@ -520,7 +519,6 @@ # define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ CFG_CMD_ELF | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_I2C | \ CFG_CMD_SPI | \ CFG_CMD_SDRAM | \ diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h index 180ce05..9cf0654 100644 --- a/include/configs/sbc8260.h +++ b/include/configs/sbc8260.h @@ -448,7 +448,6 @@ #ifdef CONFIG_ETHER_ON_FCC # define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_ELF | \ CFG_CMD_I2C | \ CFG_CMD_IMMAP | \ @@ -459,7 +458,6 @@ #else # define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ CFG_CMD_ELF | \ CFG_CMD_I2C | \ CFG_CMD_IMMAP | \ diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h new file mode 100644 index 0000000..e106b3b --- /dev/null +++ b/include/configs/smmaco4.h @@ -0,0 +1,373 @@ +/* + * (C) Copyright 2003-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004-2005 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ +#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_I2C) + +#ifdef CONFIG_POST +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG +/* preserve space for the post_word at end of on-chip SRAM */ +#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 +#else +#define CFG_CMD_POST_DIAG 0 +#endif + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_TIMESTAMP /* display image timestamps */ + +#if (TEXT_BASE == 0xFC000000) /* Boot low */ +# define CFG_LOWBOOT 1 +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "bootfile=/tftpboot/smmaco4/uImage\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "u-boot=/tftpboot/smmaco4/u-boot.bin\0" \ + "update=protect off FC000000 FC05FFFF;" \ + "erase FC000000 FC05FFFF;" \ + "cp.b 200000 FC000000 ${filesize};" \ + "protect on FC000000 FC05FFFF\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +/* + * IPB Bus clocking configuration. + */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ + +#if defined(CFG_IPBSPEED_133) +/* + * PCI Bus clocking configuration + * + * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if + * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't + * been tested with a IPB Bus Clock of 66 MHz. + */ +#define CFG_PCISPEED_66 /* define for 66MHz speed */ +#endif + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#ifdef CONFIG_TQM5200_REV100 +#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ +#else +#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ +#endif + +/* + * I2C clock frequency + * + * Please notice, that the resulting clock frequency could differ from the + * configured value. This is because the I2C clock is derived from system + * clock over a frequency divider with only a few divider values. U-boot + * calculates the best approximation for CFG_I2C_SPEED. However the calculated + * approximation allways lies below the configured value, never above. + */ +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work + * also). For other EEPROMs configuration should be verified. On Mini-FAP the + * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the + * same configuration could be used. + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 + +/* + * Flash configuration + */ +#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ + +/* use CFI flash driver if no module variant is spezified */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ + +#if !defined(CFG_LOWBOOT) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) +#else /* CFG_LOWBOOT */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) +#endif /* CFG_LOWBOOT */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +/* Dynamic MTD partition support */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=TQM5200-0" +#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ + "1408k(kernel)," \ + "2m(initrd)," \ + "4m(small-fs)," \ + "16m(big-fs)," \ + "8m(misc)" + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use ON-Chip SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#ifdef CONFIG_POST +/* preserve space for the post_word at end of on-chip SRAM */ +#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE +#else +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE +#endif + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 0x00 + +/* + * GPIO configuration + * + * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): + * Bit 0 (mask: 0x80000000): 1 + * use ALT CAN position: Bits 2-3 (mask: 0x30000000): + * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. + * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. + * Use for REV200 STK52XX boards. Do not use with REV100 modules + * (because, there I2C1 is used as I2C bus) + * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 + * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) + * 000 -> All PSC2 pins are GIOPs + * 001 -> CAN1/2 on PSC2 pins + * Use for REV100 STK52xx boards + * use PSC6: + * on STK52xx: + * use as UART. Pins PSC6_0 to PSC6_3 are used. + * Bits 9:11 (mask: 0x00700000): + * 101 -> PSC6 : Extended POST test is not available + * on MINI-FAP and TQM5200_IB: + * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): + * 000 -> PSC6 could not be used as UART, CODEC or IrDA + * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST + * tests. + */ +#if defined (CONFIG_MINIFAP) +# define CFG_GPS_PORT_CONFIG 0x91000004 +#elif defined (CONFIG_STK52XX) +# if defined (CONFIG_STK52XX_REV100) +# define CFG_GPS_PORT_CONFIG 0x81500014 +# else /* STK52xx REV200 and above */ +# if defined (CONFIG_TQM5200_REV100) +# error TQM5200 REV100 not supported on STK52XX REV200 or above +# else/* TQM5200 REV200 and above */ +# define CFG_GPS_PORT_CONFIG 0x91500004 +# endif +# endif +#else /* TMQ5200 Inbetriebnahme-Board */ +# define CFG_GPS_PORT_CONFIG 0x81000004 +#endif + +/* + * RTC configuration + */ +#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* Enable an alternate, more extensive memory test */ +#define CFG_ALT_MEMTEST + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, + * which is normally part of the default commands (CFV_CMD_DFL) + */ +#define CONFIG_LOOPW + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#ifdef CFG_PCISPEED_66 +#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ +#else +#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ +#endif +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ + +#define CFG_RESET_ADDRESS 0xff000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/stamp.h b/include/configs/stamp.h new file mode 100644 index 0000000..248ca70 --- /dev/null +++ b/include/configs/stamp.h @@ -0,0 +1,333 @@ +/* + * U-boot - stamp.h Configuration file for STAMP board + * having BF533 processor + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_STAMP_H__ +#define __CONFIG_STAMP_H__ + +/* + * Board settings + * + */ + +#define __ADSPLPBLACKFIN__ 1 +#define __ADSPBF533__ 1 +#define CONFIG_STAMP 1 +#define CONFIG_RTC_BF533 1 + +/* FLASH/ETHERNET uses the same address range */ +#define SHARED_RESOURCES 1 + +#define CONFIG_VDSP 1 + +/* + * Clock settings + * + */ + +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 11059200 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 45 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 6 + +/* + * Network Settings + */ +/* network support */ +#define CONFIG_IPADDR 192.168.0.15 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_HOSTNAME STAMP +#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs + +/* To remove hardcoding and enable MAC storage in EEPROM */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ + +/* + * Command settings + * + */ + +#define CFG_LONGHELP 1 + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ +#define CONFIG_BOOTCOMMAND "run ramboot" +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_DATE) +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):eth0:off\0" \ + "ramboot=tftpboot 0x1000000 linux;" \ + "run ramargs;run addip;bootelf\0" \ + "nfsboot=tftpboot 0x1000000 linux;" \ + "run nfsargs;run addip;bootelf\0" \ + "flashboot=bootm 0x20100000\0" \ + "" + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Console settings + * + */ + +#define CONFIG_BAUDRATE 57600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_PROMPT "stamp>" /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_LOADS_ECHO 1 + +/* + * Network settings + * + */ + +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x20300300 +/* To remove hardcoding and enable MAC storage in EEPROM */ +/* #define HARDCODE_MAC 1 */ + +/* + * Flash settings + * + */ + +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET + +#define CFG_ENV_IS_IN_FLASH 1 + +#define CFG_FLASH_BASE 0x20000000 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#define CFG_ENV_ADDR 0x20020000 +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ + +#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */ +#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ + +/* JFFS Partition offset set */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CFG_JFFS2_FIRST_SECTOR 11 + +/* + * following timeouts shall be used once the + * Flash real protection is enabled + */ +#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ +#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ + +/* + * I2C settings + * By default PF2 is used as SDA and PF3 as SCL on the Stamp board + */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +/* + * Software (bit-bang) I2C driver configuration + */ +#define PF_SCL PF3 +#define PF_SDA PF2 + +#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") +#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") +#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") +#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") +#define I2C_SDA(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SDA; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SDA; \ + asm("ssync;"); \ + } +#define I2C_SCL(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SCL; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SCL; \ + asm("ssync;"); \ + } +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE + +/* + * Compact Flash settings + */ + +/* Enabled below option for CF support */ +/* #define CONFIG_STAMP_CF 1 */ + +#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE) + +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_DOS_PARTITION 1 + +/* + * IDE/ATA stuff + */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0x20200000 +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */ + +#define CFG_ATA_STRIDE 2 +#endif + +/* + * SDRAM settings + * + */ + +#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_MT48LC64M4A2FB_7E 1 + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x07EFFFFF /* 1 ... 127 MB in DRAM */ +#define CFG_LOAD_ADDR 0x01000000 /* default load address */ + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE 0x08000000 + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) + +#if ( CONFIG_CLKIN_HALF == 0 ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#else +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#endif + +#if (CONFIG_PLL_BYPASS == 0) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HZ 1000 /* 1ms time tick */ + +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_SIZE 0x4000 +#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) + +#define CFG_LARGE_IMAGE_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ + +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +/* + * FLASH organization and environment definitions + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* 0xFF, 0xBBC3BBc3, 0x99B39983 */ +/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \ + B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN) +#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \ + B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN) +*/ +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0xBBC3BBC3 +#define AMBCTL1VAL 0x99B39983 +#define CF_AMBCTL1VAL 0x99B3ffc2 + +#ifdef CONFIG_VDSP +#define ET_EXEC_VDSP 0x8 +#define SHT_STRTAB_VDSP 0x1 +#define ELFSHDRSIZE_VDSP 0x2C +#define VDSP_ENTRY_ADDR 0xFFA00000 +#endif + +#endif diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index 3ffe6b2..be6c36c 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -584,5 +584,7 @@ typedef unsigned int led_id_t; #define OF_CPU "PowerPC,MPC870@0" #define OF_TBCLK (MPC8XX_HZ / 16) +#define CONFIG_OF_HAS_BD_T 1 +#define CONFIG_OF_HAS_UBOOT_ENV 1 #endif /* __CONFIG_H */ diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h index 7118f3f..92ee8cb 100644 --- a/include/configs/svm_sc8xx.h +++ b/include/configs/svm_sc8xx.h @@ -141,6 +141,7 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY /* * Miscellaneous configurable options diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h index d312b65..e5d4397 100644 --- a/include/configs/utx8245.h +++ b/include/configs/utx8245.h @@ -91,7 +91,6 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}" | CFG_CMD_ENV | CFG_CMD_CONSOLE \ | CFG_CMD_LOADS | CFG_CMD_LOADB \ | CFG_CMD_IMI | CFG_CMD_CACHE \ - | CFG_CMD_RUN | CFG_CMD_ECHO \ | CFG_CMD_REGINFO | CFG_CMD_NET\ | CFG_CMD_DHCP | CFG_CMD_I2C \ | CFG_CMD_DATE) diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h new file mode 100644 index 0000000..4232d50 --- /dev/null +++ b/include/configs/zylonite.h @@ -0,0 +1,256 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * Configuation settings for the Zylonite board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */ +#define CONFIG_ZYLONITE 1 /* Zylonite board */ + +/* #define CONFIG_LCD 1 */ +#ifdef CONFIG_LCD +#define CONFIG_SHARP_LM8V31 +#endif +/* #define CONFIG_MMC 1 */ +#define BOARD_LATE_INIT 1 + +#undef CONFIG_SKIP_RELOCATE_UBOOT +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +#undef TURN_ON_ETHERNET +#ifdef TURN_ON_ETHERNET +# define CONFIG_DRIVER_SMC91111 1 +# define CONFIG_SMC91111_BASE 0x14000300 +# define CONFIG_SMC91111_EXT_PHY +# define CONFIG_SMC_USE_32_BIT +# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */ +#endif + +/* + * select serial console configuration + */ +#define CONFIG_FFUART 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +/* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */ +#ifdef TURN_ON_ETHERNET +# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING) +#else +# define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET) +#endif + + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_BOOTDELAY -1 +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_IPADDR 192.168.0.21 +#define CONFIG_SERVERIP 192.168.0.250 +#define CONFIG_BOOTCOMMAND "bootm 80000" +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" +#define CONFIG_CMDLINE_TAG +#define CONFIG_TIMESTAMP + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0x9c000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x9c400000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* #define CFG_MMC_BASE 0xF0000000 */ + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ +#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +#define FPGA_REGS_BASE_PHYSICAL 0x08000000 + +/* + * GPIO settings + */ +#define CFG_GPSR0_VAL 0x00008000 +#define CFG_GPSR1_VAL 0x00FC0382 +#define CFG_GPSR2_VAL 0x0001FFFF +#define CFG_GPCR0_VAL 0x00000000 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 +#define CFG_GPDR0_VAL 0x0060A800 +#define CFG_GPDR1_VAL 0x00FF0382 +#define CFG_GPDR2_VAL 0x0001C000 +#define CFG_GAFR0_L_VAL 0x98400000 +#define CFG_GAFR0_U_VAL 0x00002950 +#define CFG_GAFR1_L_VAL 0x000A9558 +#define CFG_GAFR1_U_VAL 0x0005AAAA +#define CFG_GAFR2_L_VAL 0xA0000000 +#define CFG_GAFR2_U_VAL 0x00000002 + +#define CFG_PSSR_VAL 0x20 + +/* + * Memory settings + */ +#define CFG_MSC0_VAL 0x23F223F2 +#define CFG_MSC1_VAL 0x3FF1A441 +#define CFG_MSC2_VAL 0x7FF97FF1 +#define CFG_MDCNFG_VAL 0x00001AC9 +#define CFG_MDREFR_VAL 0x00018018 +#define CFG_MDMRS_VAL 0x00000000 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000000 +#define CFG_MCMEM0_VAL 0x00010504 +#define CFG_MCMEM1_VAL 0x00010504 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00004715 +#define CFG_MCIO1_VAL 0x00004715 + +#define _LED 0x08000010 +#define LED_BLANK 0x08000040 + +/* + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +/* NOTE: many default partitioning schemes assume the kernel starts at the + * second sector, not an environment. You have been warned! + */ +#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) +#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE +#define CFG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16) + + +/* + * FPGA Offsets + */ +#define WHOAMI_OFFSET 0x00 +#define HEXLED_OFFSET 0x10 +#define BLANKLED_OFFSET 0x40 +#define DISCRETELED_OFFSET 0x40 +#define CNFG_SWITCHES_OFFSET 0x50 +#define USER_SWITCHES_OFFSET 0x60 +#define MISC_WR_OFFSET 0x80 +#define MISC_RD_OFFSET 0x90 +#define INT_MASK_OFFSET 0xC0 +#define INT_CLEAR_OFFSET 0xD0 +#define GP_OFFSET 0x100 + +#endif /* __CONFIG_H */ diff --git a/include/flash.h b/include/flash.h index 069aa63..4c68c68 100644 --- a/include/flash.h +++ b/include/flash.h @@ -242,6 +242,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */ #define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */ #define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */ +#define FLASH_PSD4256GV 0x00E9 /* PSD4256 Flash and CPLD combination */ #define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */ #define INTEL_ID_28F800B3T 0x88928892 /* 8M = 512K x 16 top boot sector */ @@ -274,6 +275,12 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define INTEL_ID_28F64K3 0x88018801 /* 64M = 32K x 255 + 32k x 4 */ #define INTEL_ID_28F128K3 0x88028802 /* 128M = 64K x 255 + 32k x 4 */ #define INTEL_ID_28F256K3 0x88038803 /* 256M = 128K x 255 + 32k x 4 */ +#define INTEL_ID_28F64P30T 0x88178817 /* 64M = 32K x 255 + 32k x 4 */ +#define INTEL_ID_28F64P30B 0x881A881A /* 64M = 32K x 255 + 32k x 4 */ +#define INTEL_ID_28F128P30T 0x88188818 /* 128M = 64K x 255 + 32k x 4 */ +#define INTEL_ID_28F128P30B 0x881B881B /* 128M = 64K x 255 + 32k x 4 */ +#define INTEL_ID_28F256P30T 0x88198819 /* 256M = 128K x 255 + 32k x 4 */ +#define INTEL_ID_28F256P30B 0x881C881C /* 256M = 128K x 255 + 32k x 4 */ #define INTEL_ID_28F160S3 0x00D000D0 /* 16M = 512K x 32 (64kB x 32) */ #define INTEL_ID_28F320S3 0x00D400D4 /* 32M = 512K x 64 (64kB x 64) */ diff --git a/include/ft_build.h b/include/ft_build.h index 9104b1a..47ca575 100644 --- a/include/ft_build.h +++ b/include/ft_build.h @@ -57,10 +57,12 @@ void ft_prop_int(struct ft_cxt *cxt, const char *name, int val); void ft_begin(struct ft_cxt *cxt, void *blob, int max_size); void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size); -void ft_setup(void *blob, int size, bd_t * bd); +void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end); void ft_dump_blob(const void *bphp); void ft_merge_blob(struct ft_cxt *cxt, void *blob); void *ft_get_prop(void *bphp, const char *propname, int *szp); +void ft_board_setup(void *blob, bd_t *bd); + #endif diff --git a/include/image.h b/include/image.h index af37bca..139df0b 100644 --- a/include/image.h +++ b/include/image.h @@ -75,6 +75,7 @@ #define IH_CPU_NIOS 13 /* Nios-32 */ #define IH_CPU_MICROBLAZE 14 /* MicroBlaze */ #define IH_CPU_NIOS2 15 /* Nios-II */ +#define IH_CPU_BLACKFIN 16 /* Blackfin */ /* * Image Types diff --git a/include/linux/mtd/compat.h b/include/linux/mtd/compat.h new file mode 100644 index 0000000..460cd45 --- /dev/null +++ b/include/linux/mtd/compat.h @@ -0,0 +1,44 @@ +#ifndef _LINUX_COMPAT_H_ +#define _LINUX_COMPAT_H_ + +#define __user +#define __iomem + +#define ndelay(x) udelay(1) + +#define printk printf + +#define KERN_EMERG +#define KERN_ALERT +#define KERN_CRIT +#define KERN_ERR +#define KERN_WARNING +#define KERN_NOTICE +#define KERN_INFO +#define KERN_DEBUG + +#define kmalloc(size, flags) malloc(size) +#define kfree(ptr) free(ptr) + +/* + * ..and if you can't take the strict + * types, you can specify one yourself. + * + * Or not use min/max at all, of course. + */ +#define min_t(type,x,y) \ + ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) +#define max_t(type,x,y) \ + ({ type __x = (x); type __y = (y); __x > __y ? __x: __y; }) + +#define BUG() do { \ + printf("U-Boot BUG at %s:%d!\n", __FILE__, __LINE__); \ +} while (0) + +#define BUG_ON(condition) do { if (condition) BUG(); } while(0) + +#define likely(x) __builtin_expect(!!(x), 1) +#define unlikely(x) __builtin_expect(!!(x), 0) + +#define PAGE_SIZE 4096 +#endif diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h new file mode 100644 index 0000000..3d1d416 --- /dev/null +++ b/include/linux/mtd/mtd-abi.h @@ -0,0 +1,99 @@ +/* + * $Id: mtd-abi.h,v 1.7 2004/11/23 15:37:32 gleixner Exp $ + * + * Portions of MTD ABI definition which are shared by kernel and user space + */ + +#ifndef __MTD_ABI_H__ +#define __MTD_ABI_H__ + +struct erase_info_user { + uint32_t start; + uint32_t length; +}; + +struct mtd_oob_buf { + uint32_t start; + uint32_t length; + unsigned char *ptr; +}; + +#define MTD_ABSENT 0 +#define MTD_RAM 1 +#define MTD_ROM 2 +#define MTD_NORFLASH 3 +#define MTD_NANDFLASH 4 +#define MTD_PEROM 5 +#define MTD_OTHER 14 +#define MTD_UNKNOWN 15 + +#define MTD_CLEAR_BITS 1 /* Bits can be cleared (flash) */ +#define MTD_SET_BITS 2 /* Bits can be set */ +#define MTD_ERASEABLE 4 /* Has an erase function */ +#define MTD_WRITEB_WRITEABLE 8 /* Direct IO is possible */ +#define MTD_VOLATILE 16 /* Set for RAMs */ +#define MTD_XIP 32 /* eXecute-In-Place possible */ +#define MTD_OOB 64 /* Out-of-band data (NAND flash) */ +#define MTD_ECC 128 /* Device capable of automatic ECC */ +#define MTD_NO_VIRTBLOCKS 256 /* Virtual blocks not allowed */ + +/* Some common devices / combinations of capabilities */ +#define MTD_CAP_ROM 0 +#define MTD_CAP_RAM (MTD_CLEAR_BITS|MTD_SET_BITS|MTD_WRITEB_WRITEABLE) +#define MTD_CAP_NORFLASH (MTD_CLEAR_BITS|MTD_ERASEABLE) +#define MTD_CAP_NANDFLASH (MTD_CLEAR_BITS|MTD_ERASEABLE|MTD_OOB) +#define MTD_WRITEABLE (MTD_CLEAR_BITS|MTD_SET_BITS) + + +/* Types of automatic ECC/Checksum available */ +#define MTD_ECC_NONE 0 /* No automatic ECC available */ +#define MTD_ECC_RS_DiskOnChip 1 /* Automatic ECC on DiskOnChip */ +#define MTD_ECC_SW 2 /* SW ECC for Toshiba & Samsung devices */ + +/* ECC byte placement */ +#define MTD_NANDECC_OFF 0 /* Switch off ECC (Not recommended) */ +#define MTD_NANDECC_PLACE 1 /* Use the given placement in the structure (YAFFS1 legacy mode) */ +#define MTD_NANDECC_AUTOPLACE 2 /* Use the default placement scheme */ +#define MTD_NANDECC_PLACEONLY 3 /* Use the given placement in the structure (Do not store ecc result on read) */ +#define MTD_NANDECC_AUTOPL_USR 4 /* Use the given autoplacement scheme rather than using the default */ + +struct mtd_info_user { + uint8_t type; + uint32_t flags; + uint32_t size; /* Total size of the MTD */ + uint32_t erasesize; + uint32_t oobblock; /* Size of OOB blocks (e.g. 512) */ + uint32_t oobsize; /* Amount of OOB data per block (e.g. 16) */ + uint32_t ecctype; + uint32_t eccsize; +}; + +struct region_info_user { + uint32_t offset; /* At which this region starts, + * from the beginning of the MTD */ + uint32_t erasesize; /* For this region */ + uint32_t numblocks; /* Number of blocks in this region */ + uint32_t regionindex; +}; + +#define MEMGETINFO _IOR('M', 1, struct mtd_info_user) +#define MEMERASE _IOW('M', 2, struct erase_info_user) +#define MEMWRITEOOB _IOWR('M', 3, struct mtd_oob_buf) +#define MEMREADOOB _IOWR('M', 4, struct mtd_oob_buf) +#define MEMLOCK _IOW('M', 5, struct erase_info_user) +#define MEMUNLOCK _IOW('M', 6, struct erase_info_user) +#define MEMGETREGIONCOUNT _IOR('M', 7, int) +#define MEMGETREGIONINFO _IOWR('M', 8, struct region_info_user) +#define MEMSETOOBSEL _IOW('M', 9, struct nand_oobinfo) +#define MEMGETOOBSEL _IOR('M', 10, struct nand_oobinfo) +#define MEMGETBADBLOCK _IOW('M', 11, loff_t) +#define MEMSETBADBLOCK _IOW('M', 12, loff_t) + +struct nand_oobinfo { + uint32_t useecc; + uint32_t eccbytes; + uint32_t oobfree[8][2]; + uint32_t eccpos[32]; +}; + +#endif /* __MTD_ABI_H__ */ diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h new file mode 100644 index 0000000..13e9080 --- /dev/null +++ b/include/linux/mtd/mtd.h @@ -0,0 +1,214 @@ +/* + * $Id: mtd.h,v 1.56 2004/08/09 18:46:04 dmarlin Exp $ + * + * Copyright (C) 1999-2003 David Woodhouse <dwmw2@infradead.org> et al. + * + * Released under GPL + */ + +#ifndef __MTD_MTD_H__ +#define __MTD_MTD_H__ +#include <linux/types.h> +#include <linux/mtd/mtd-abi.h> + +#define MAX_MTD_DEVICES 16 + +#define MTD_ERASE_PENDING 0x01 +#define MTD_ERASING 0x02 +#define MTD_ERASE_SUSPEND 0x04 +#define MTD_ERASE_DONE 0x08 +#define MTD_ERASE_FAILED 0x10 + +/* If the erase fails, fail_addr might indicate exactly which block failed. If + fail_addr = 0xffffffff, the failure was not at the device level or was not + specific to any particular block. */ +struct erase_info { + struct mtd_info *mtd; + u_int32_t addr; + u_int32_t len; + u_int32_t fail_addr; + u_long time; + u_long retries; + u_int dev; + u_int cell; + void (*callback) (struct erase_info *self); + u_long priv; + u_char state; + struct erase_info *next; +}; + +struct mtd_erase_region_info { + u_int32_t offset; /* At which this region starts, from the beginning of the MTD */ + u_int32_t erasesize; /* For this region */ + u_int32_t numblocks; /* Number of blocks of erasesize in this region */ +}; + +struct mtd_info { + u_char type; + u_int32_t flags; + u_int32_t size; /* Total size of the MTD */ + + /* "Major" erase size for the device. Naïve users may take this + * to be the only erase size available, or may use the more detailed + * information below if they desire + */ + u_int32_t erasesize; + + u_int32_t oobblock; /* Size of OOB blocks (e.g. 512) */ + u_int32_t oobsize; /* Amount of OOB data per block (e.g. 16) */ + u_int32_t oobavail; /* Number of bytes in OOB area available for fs */ + u_int32_t ecctype; + u_int32_t eccsize; + + + /* Kernel-only stuff starts here. */ + char *name; + int index; + + /* oobinfo is a nand_oobinfo structure, which can be set by iotcl (MEMSETOOBINFO) */ + struct nand_oobinfo oobinfo; + + /* Data for variable erase regions. If numeraseregions is zero, + * it means that the whole device has erasesize as given above. + */ + int numeraseregions; + struct mtd_erase_region_info *eraseregions; + + /* This really shouldn't be here. It can go away in 2.5 */ + u_int32_t bank_size; + + int (*erase) (struct mtd_info *mtd, struct erase_info *instr); + + /* This stuff for eXecute-In-Place */ + int (*point) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char **mtdbuf); + + /* We probably shouldn't allow XIP if the unpoint isn't a NULL */ + void (*unpoint) (struct mtd_info *mtd, u_char * addr, loff_t from, size_t len); + + + int (*read) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + int (*write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); + + int (*read_ecc) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf, u_char *eccbuf, struct nand_oobinfo *oobsel); + int (*write_ecc) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf, u_char *eccbuf, struct nand_oobinfo *oobsel); + + int (*read_oob) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + int (*write_oob) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); + + /* + * Methods to access the protection register area, present in some + * flash devices. The user data is one time programmable but the + * factory data is read only. + */ + int (*read_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + + int (*read_fact_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + + /* This function is not yet implemented */ + int (*write_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); +#if 0 + /* kvec-based read/write methods. We need these especially for NAND flash, + with its limited number of write cycles per erase. + NB: The 'count' parameter is the number of _vectors_, each of + which contains an (ofs, len) tuple. + */ + int (*readv) (struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from, size_t *retlen); + int (*readv_ecc) (struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from, + size_t *retlen, u_char *eccbuf, struct nand_oobinfo *oobsel); + int (*writev) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to, size_t *retlen); + int (*writev_ecc) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to, + size_t *retlen, u_char *eccbuf, struct nand_oobinfo *oobsel); +#endif + /* Sync */ + void (*sync) (struct mtd_info *mtd); +#if 0 + /* Chip-supported device locking */ + int (*lock) (struct mtd_info *mtd, loff_t ofs, size_t len); + int (*unlock) (struct mtd_info *mtd, loff_t ofs, size_t len); + + /* Power Management functions */ + int (*suspend) (struct mtd_info *mtd); + void (*resume) (struct mtd_info *mtd); +#endif + /* Bad block management functions */ + int (*block_isbad) (struct mtd_info *mtd, loff_t ofs); + int (*block_markbad) (struct mtd_info *mtd, loff_t ofs); + + void *priv; + + struct module *owner; + int usecount; +}; + + + /* Kernel-side ioctl definitions */ + +extern int add_mtd_device(struct mtd_info *mtd); +extern int del_mtd_device (struct mtd_info *mtd); + +extern struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num); + +extern void put_mtd_device(struct mtd_info *mtd); + +#if 0 +struct mtd_notifier { + void (*add)(struct mtd_info *mtd); + void (*remove)(struct mtd_info *mtd); + struct list_head list; +}; + + +extern void register_mtd_user (struct mtd_notifier *new); +extern int unregister_mtd_user (struct mtd_notifier *old); + +int default_mtd_writev(struct mtd_info *mtd, const struct kvec *vecs, + unsigned long count, loff_t to, size_t *retlen); + +int default_mtd_readv(struct mtd_info *mtd, struct kvec *vecs, + unsigned long count, loff_t from, size_t *retlen); +#endif + +#define MTD_ERASE(mtd, args...) (*(mtd->erase))(mtd, args) +#define MTD_POINT(mtd, a,b,c,d) (*(mtd->point))(mtd, a,b,c, (u_char **)(d)) +#define MTD_UNPOINT(mtd, arg) (*(mtd->unpoint))(mtd, (u_char *)arg) +#define MTD_READ(mtd, args...) (*(mtd->read))(mtd, args) +#define MTD_WRITE(mtd, args...) (*(mtd->write))(mtd, args) +#define MTD_READV(mtd, args...) (*(mtd->readv))(mtd, args) +#define MTD_WRITEV(mtd, args...) (*(mtd->writev))(mtd, args) +#define MTD_READECC(mtd, args...) (*(mtd->read_ecc))(mtd, args) +#define MTD_WRITEECC(mtd, args...) (*(mtd->write_ecc))(mtd, args) +#define MTD_READOOB(mtd, args...) (*(mtd->read_oob))(mtd, args) +#define MTD_WRITEOOB(mtd, args...) (*(mtd->write_oob))(mtd, args) +#define MTD_SYNC(mtd) do { if (mtd->sync) (*(mtd->sync))(mtd); } while (0) + + +#ifdef CONFIG_MTD_PARTITIONS +void mtd_erase_callback(struct erase_info *instr); +#else +static inline void mtd_erase_callback(struct erase_info *instr) +{ + if (instr->callback) + instr->callback(instr); +} +#endif + +/* + * Debugging macro and defines + */ +#define MTD_DEBUG_LEVEL0 (0) /* Quiet */ +#define MTD_DEBUG_LEVEL1 (1) /* Audible */ +#define MTD_DEBUG_LEVEL2 (2) /* Loud */ +#define MTD_DEBUG_LEVEL3 (3) /* Noisy */ + +#ifdef CONFIG_MTD_DEBUG +#define DEBUG(n, args...) \ + do { \ + if (n <= CONFIG_MTD_DEBUG_VERBOSE) \ + printk(KERN_INFO args); \ + } while(0) +#else /* CONFIG_MTD_DEBUG */ +#define DEBUG(n, args...) do { } while(0) + +#endif /* CONFIG_MTD_DEBUG */ + +#endif /* __MTD_MTD_H__ */ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 5236904..a522718 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -2,10 +2,10 @@ * linux/include/linux/mtd/nand.h * * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com> - * Steven J. Hill <sjhill@cotw.com> - * Thomas Gleixner <gleixner@autronix.de> + * Steven J. Hill <sjhill@realitydiluted.com> + * Thomas Gleixner <tglx@linutronix.de> * - * $Id: nand.h,v 1.7 2003/07/24 23:30:46 a0384864 Exp $ + * $Id: nand.h,v 1.68 2004/11/12 10:40:37 gleixner Exp $ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -32,10 +32,65 @@ * command delay times for different chips * 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate * defines in jffs2/wbuf.c + * 08-07-2002 TG forced bad block location to byte 5 of OOB, even if + * CONFIG_MTD_NAND_ECC_JFFS2 is not set + * 08-10-2002 TG extensions to nand_chip structure to support HW-ECC + * + * 08-29-2002 tglx nand_chip structure: data_poi for selecting + * internal / fs-driver buffer + * support for 6byte/512byte hardware ECC + * read_ecc, write_ecc extended for different oob-layout + * oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB, + * NAND_YAFFS_OOB + * 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL + * Split manufacturer and device ID structures + * + * 02-08-2004 tglx added option field to nand structure for chip anomalities + * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id + * update of nand_chip structure description */ #ifndef __LINUX_MTD_NAND_H #define __LINUX_MTD_NAND_H +#include <linux/mtd/compat.h> +#include <linux/mtd/mtd.h> + +struct mtd_info; +/* Scan and identify a NAND device */ +extern int nand_scan (struct mtd_info *mtd, int max_chips); +/* Free resources held by the NAND device */ +extern void nand_release (struct mtd_info *mtd); + +/* Read raw data from the device without ECC */ +extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen); + + +/* This constant declares the max. oobsize / page, which + * is supported now. If you add a chip with bigger oobsize/page + * adjust this accordingly. + */ +#define NAND_MAX_OOBSIZE 64 + +/* + * Constants for hardware specific CLE/ALE/NCE function +*/ +/* Select the chip by setting nCE to low */ +#define NAND_CTL_SETNCE 1 +/* Deselect the chip by setting nCE to high */ +#define NAND_CTL_CLRNCE 2 +/* Select the command latch by setting CLE to high */ +#define NAND_CTL_SETCLE 3 +/* Deselect the command latch by setting CLE to low */ +#define NAND_CTL_CLRCLE 4 +/* Select the address latch by setting ALE to high */ +#define NAND_CTL_SETALE 5 +/* Deselect the address latch by setting ALE to low */ +#define NAND_CTL_CLRALE 6 +/* Set write protection by setting WP to high. Not used! */ +#define NAND_CTL_SETWP 7 +/* Clear write protection by setting WP to low. Not used! */ +#define NAND_CTL_CLRWP 8 + /* * Standard NAND flash commands */ @@ -45,12 +100,104 @@ #define NAND_CMD_READOOB 0x50 #define NAND_CMD_ERASE1 0x60 #define NAND_CMD_STATUS 0x70 +#define NAND_CMD_STATUS_MULTI 0x71 #define NAND_CMD_SEQIN 0x80 #define NAND_CMD_READID 0x90 #define NAND_CMD_ERASE2 0xd0 #define NAND_CMD_RESET 0xff +/* Extended commands for large page devices */ +#define NAND_CMD_READSTART 0x30 +#define NAND_CMD_CACHEDPROG 0x15 + +/* Status bits */ +#define NAND_STATUS_FAIL 0x01 +#define NAND_STATUS_FAIL_N1 0x02 +#define NAND_STATUS_TRUE_READY 0x20 +#define NAND_STATUS_READY 0x40 +#define NAND_STATUS_WP 0x80 + /* + * Constants for ECC_MODES + */ + +/* No ECC. Usage is not recommended ! */ +#define NAND_ECC_NONE 0 +/* Software ECC 3 byte ECC per 256 Byte data */ +#define NAND_ECC_SOFT 1 +/* Hardware ECC 3 byte ECC per 256 Byte data */ +#define NAND_ECC_HW3_256 2 +/* Hardware ECC 3 byte ECC per 512 Byte data */ +#define NAND_ECC_HW3_512 3 +/* Hardware ECC 3 byte ECC per 512 Byte data */ +#define NAND_ECC_HW6_512 4 +/* Hardware ECC 8 byte ECC per 512 Byte data */ +#define NAND_ECC_HW8_512 6 +/* Hardware ECC 12 byte ECC per 2048 Byte data */ +#define NAND_ECC_HW12_2048 7 + +/* + * Constants for Hardware ECC +*/ +/* Reset Hardware ECC for read */ +#define NAND_ECC_READ 0 +/* Reset Hardware ECC for write */ +#define NAND_ECC_WRITE 1 +/* Enable Hardware ECC before syndrom is read back from flash */ +#define NAND_ECC_READSYN 2 + +/* Option constants for bizarre disfunctionality and real +* features +*/ +/* Chip can not auto increment pages */ +#define NAND_NO_AUTOINCR 0x00000001 +/* Buswitdh is 16 bit */ +#define NAND_BUSWIDTH_16 0x00000002 +/* Device supports partial programming without padding */ +#define NAND_NO_PADDING 0x00000004 +/* Chip has cache program function */ +#define NAND_CACHEPRG 0x00000008 +/* Chip has copy back function */ +#define NAND_COPYBACK 0x00000010 +/* AND Chip which has 4 banks and a confusing page / block + * assignment. See Renesas datasheet for further information */ +#define NAND_IS_AND 0x00000020 +/* Chip has a array of 4 pages which can be read without + * additional ready /busy waits */ +#define NAND_4PAGE_ARRAY 0x00000040 + +/* Options valid for Samsung large page devices */ +#define NAND_SAMSUNG_LP_OPTIONS \ + (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) + +/* Macros to identify the above */ +#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR)) +#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) +#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) +#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) + +/* Mask to zero out the chip options, which come from the id table */ +#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) + +/* Non chip related options */ +/* Use a flash based bad block table. This option is passed to the + * default bad block table function. */ +#define NAND_USE_FLASH_BBT 0x00010000 +/* The hw ecc generator provides a syndrome instead a ecc value on read + * This can only work if we have the ecc bytes directly behind the + * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */ +#define NAND_HWECC_SYNDROME 0x00020000 + + +/* Options set by nand scan */ +/* Nand scan has allocated oob_buf */ +#define NAND_OOBBUF_ALLOC 0x40000000 +/* Nand scan has allocated data_buf */ +#define NAND_DATABUF_ALLOC 0x80000000 + + +/* + * nand_state_t - chip states * Enumeration for NAND flash chip state */ typedef enum { @@ -58,71 +205,138 @@ typedef enum { FL_READING, FL_WRITING, FL_ERASING, - FL_SYNCING + FL_SYNCING, + FL_CACHEDPRG, } nand_state_t; +/* Keep gcc happy */ +struct nand_chip; -/* - * NAND Private Flash Chip Data - * - * Structure overview: - * - * IO_ADDR - address to access the 8 I/O lines of the flash device - * - * hwcontrol - hardwarespecific function for accesing control-lines - * - * dev_ready - hardwarespecific function for accesing device ready/busy line - * - * chip_lock - spinlock used to protect access to this structure - * - * wq - wait queue to sleep on if a NAND operation is in progress - * - * state - give the current state of the NAND device - * - * page_shift - number of address bits in a page (column address bits) - * - * data_buf - data buffer passed to/from MTD user modules - * - * data_cache - data cache for redundant page access and shadow for - * ECC failure - * - * ecc_code_buf - used only for holding calculated or read ECCs for - * a page read or written when ECC is in use - * - * reserved - padding to make structure fall on word boundary if - * when ECC is in use +#if 0 +/** + * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices + * @lock: protection lock + * @active: the mtd device which holds the controller currently */ -struct Nand { - char floor, chip; - unsigned long curadr; - unsigned char curmode; - /* Also some erase/write/pipeline info when we get that far */ +struct nand_hw_control { + spinlock_t lock; + struct nand_chip *active; }; +#endif + +/** + * struct nand_chip - NAND Private Flash Chip Data + * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device + * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device + * @read_byte: [REPLACEABLE] read one byte from the chip + * @write_byte: [REPLACEABLE] write one byte to the chip + * @read_word: [REPLACEABLE] read one word from the chip + * @write_word: [REPLACEABLE] write one word to the chip + * @write_buf: [REPLACEABLE] write data from the buffer to the chip + * @read_buf: [REPLACEABLE] read data from the chip into the buffer + * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data + * @select_chip: [REPLACEABLE] select chip nr + * @block_bad: [REPLACEABLE] check, if the block is bad + * @block_markbad: [REPLACEABLE] mark the block bad + * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines + * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line + * If set to NULL no access to ready/busy is available and the ready/busy information + * is read from the chip status register + * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip + * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready + * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware + * @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw) + * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only + * be provided if a hardware ECC is available + * @erase_cmd: [INTERN] erase command write function, selectable due to AND support + * @scan_bbt: [REPLACEABLE] function to scan bad block table + * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines + * @eccsize: [INTERN] databytes used per ecc-calculation + * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step + * @eccsteps: [INTERN] number of ecc calculation steps per page + * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) + * @chip_lock: [INTERN] spinlock used to protect access to this structure and the chip + * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress + * @state: [INTERN] the current state of the NAND device + * @page_shift: [INTERN] number of address bits in a page (column address bits) + * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock + * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry + * @chip_shift: [INTERN] number of address bits in one chip + * @data_buf: [INTERN] internal buffer for one page + oob + * @oob_buf: [INTERN] oob buffer for one eraseblock + * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized + * @data_poi: [INTERN] pointer to a data buffer + * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about + * special functionality. See the defines for further explanation + * @badblockpos: [INTERN] position of the bad block marker in the oob area + * @numchips: [INTERN] number of physical chips + * @chipsize: [INTERN] the size of one chip for multichip arrays + * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 + * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf + * @autooob: [REPLACEABLE] the default (auto)placement scheme + * @bbt: [INTERN] bad block table pointer + * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup + * @bbt_md: [REPLACEABLE] bad block table mirror descriptor + * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan + * @controller: [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices + * @priv: [OPTIONAL] pointer to private chip date + */ struct nand_chip { + void __iomem *IO_ADDR_R; + void __iomem *IO_ADDR_W; + + u_char (*read_byte)(struct mtd_info *mtd); + void (*write_byte)(struct mtd_info *mtd, u_char byte); + u16 (*read_word)(struct mtd_info *mtd); + void (*write_word)(struct mtd_info *mtd, u16 word); + + void (*write_buf)(struct mtd_info *mtd, const u_char *buf, int len); + void (*read_buf)(struct mtd_info *mtd, u_char *buf, int len); + int (*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len); + void (*select_chip)(struct mtd_info *mtd, int chip); + int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); + int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); + void (*hwcontrol)(struct mtd_info *mtd, int cmd); + int (*dev_ready)(struct mtd_info *mtd); + void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); + int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state); + int (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code); + int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc); + void (*enable_hwecc)(struct mtd_info *mtd, int mode); + void (*erase_cmd)(struct mtd_info *mtd, int page); + int (*scan_bbt)(struct mtd_info *mtd); + int eccmode; + int eccsize; + int eccbytes; + int eccsteps; + int chip_delay; +#if 0 + spinlock_t chip_lock; + wait_queue_head_t wq; + nand_state_t state; +#endif int page_shift; + int phys_erase_shift; + int bbt_erase_shift; + int chip_shift; u_char *data_buf; - u_char *data_cache; - int cache_page; - u_char ecc_code_buf[6]; - u_char reserved[2]; - char ChipID; /* Type of DiskOnChip */ - struct Nand *chips; - int chipshift; - char* chips_name; - unsigned long erasesize; - unsigned long mfr; /* Flash IDs - only one type of flash per device */ - unsigned long id; - char* name; - int numchips; - char page256; - char pageadrlen; - unsigned long IO_ADDR; /* address to access the 8 I/O lines to the flash device */ - unsigned long totlen; - uint oobblock; /* Size of OOB blocks (e.g. 512) */ - uint oobsize; /* Amount of OOB data per block (e.g. 16) */ - uint eccsize; - int bus16; + u_char *oob_buf; + int oobdirty; + u_char *data_poi; + unsigned int options; + int badblockpos; + int numchips; + unsigned long chipsize; + int pagemask; + int pagebuf; + struct nand_oobinfo *autooob; + uint8_t *bbt; + struct nand_bbt_descr *bbt_td; + struct nand_bbt_descr *bbt_md; + struct nand_bbt_descr *badblock_pattern; + struct nand_hw_control *controller; + void *priv; }; /* @@ -130,71 +344,125 @@ struct nand_chip { */ #define NAND_MFR_TOSHIBA 0x98 #define NAND_MFR_SAMSUNG 0xec +#define NAND_MFR_FUJITSU 0x04 +#define NAND_MFR_NATIONAL 0x8f +#define NAND_MFR_RENESAS 0x07 +#define NAND_MFR_STMICRO 0x20 -/* - * NAND Flash Device ID Structure - * - * Structure overview: - * - * name - Complete name of device - * - * manufacture_id - manufacturer ID code of device. - * - * model_id - model ID code of device. +/** + * struct nand_flash_dev - NAND Flash Device ID Structure * - * chipshift - total number of address bits for the device which - * is used to calculate address offsets and the total - * number of bytes the device is capable of. - * - * page256 - denotes if flash device has 256 byte pages or not. - * - * pageadrlen - number of bytes minus one needed to hold the - * complete address into the flash array. Keep in - * mind that when a read or write is done to a - * specific address, the address is input serially - * 8 bits at a time. This structure member is used - * by the read/write routines as a loop index for - * shifting the address out 8 bits at a time. - * - * erasesize - size of an erase block in the flash device. + * @name: Identify the device type + * @id: device ID code + * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 + * If the pagesize is 0, then the real pagesize + * and the eraseize are determined from the + * extended id bytes in the chip + * @erasesize: Size of an erase block in the flash device. + * @chipsize: Total chipsize in Mega Bytes + * @options: Bitfield to store chip relevant options */ struct nand_flash_dev { - char * name; - int manufacture_id; - int model_id; - int chipshift; - char page256; - char pageadrlen; + char *name; + int id; + unsigned long pagesize; + unsigned long chipsize; unsigned long erasesize; - int bus16; + unsigned long options; }; +/** + * struct nand_manufacturers - NAND Flash Manufacturer ID Structure + * @name: Manufacturer name + * @id: manufacturer ID code of device. +*/ +struct nand_manufacturers { + int id; + char * name; +}; + +extern struct nand_flash_dev nand_flash_ids[]; +extern struct nand_manufacturers nand_manuf_ids[]; + +/** + * struct nand_bbt_descr - bad block table descriptor + * @options: options for this descriptor + * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE + * when bbt is searched, then we store the found bbts pages here. + * Its an array and supports up to 8 chips now + * @offs: offset of the pattern in the oob area of the page + * @veroffs: offset of the bbt version counter in the oob are of the page + * @version: version read from the bbt page during scan + * @len: length of the pattern, if 0 no pattern check is performed + * @maxblocks: maximum number of blocks to search for a bbt. This number of + * blocks is reserved at the end of the device where the tables are + * written. + * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than + * bad) block in the stored bbt + * @pattern: pattern to identify bad block table or factory marked good / + * bad blocks, can be NULL, if len = 0 + * + * Descriptor for the bad block table marker and the descriptor for the + * pattern which identifies good and bad blocks. The assumption is made + * that the pattern and the version count are always located in the oob area + * of the first block. + */ +struct nand_bbt_descr { + int options; + int pages[NAND_MAX_CHIPS]; + int offs; + int veroffs; + uint8_t version[NAND_MAX_CHIPS]; + int len; + int maxblocks; + int reserved_block_code; + uint8_t *pattern; +}; + +/* Options for the bad block table descriptors */ + +/* The number of bits used per block in the bbt on the device */ +#define NAND_BBT_NRBITS_MSK 0x0000000F +#define NAND_BBT_1BIT 0x00000001 +#define NAND_BBT_2BIT 0x00000002 +#define NAND_BBT_4BIT 0x00000004 +#define NAND_BBT_8BIT 0x00000008 +/* The bad block table is in the last good block of the device */ +#define NAND_BBT_LASTBLOCK 0x00000010 +/* The bbt is at the given page, else we must scan for the bbt */ +#define NAND_BBT_ABSPAGE 0x00000020 +/* The bbt is at the given page, else we must scan for the bbt */ +#define NAND_BBT_SEARCH 0x00000040 +/* bbt is stored per chip on multichip devices */ +#define NAND_BBT_PERCHIP 0x00000080 +/* bbt has a version counter at offset veroffs */ +#define NAND_BBT_VERSION 0x00000100 +/* Create a bbt if none axists */ +#define NAND_BBT_CREATE 0x00000200 +/* Search good / bad pattern through all pages of a block */ +#define NAND_BBT_SCANALLPAGES 0x00000400 +/* Scan block empty during good / bad block scan */ +#define NAND_BBT_SCANEMPTY 0x00000800 +/* Write bbt if neccecary */ +#define NAND_BBT_WRITE 0x00001000 +/* Read and write back block contents when writing bbt */ +#define NAND_BBT_SAVECONTENT 0x00002000 +/* Search good / bad pattern on the first and the second page */ +#define NAND_BBT_SCAN2NDPAGE 0x00004000 + +/* The maximum number of blocks to scan for a bbt */ +#define NAND_BBT_SCAN_MAXBLOCKS 4 + +extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd); +extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs); +extern int nand_default_bbt (struct mtd_info *mtd); +extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt); +extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt); + /* * Constants for oob configuration */ -#define NAND_NOOB_ECCPOS0 0 -#define NAND_NOOB_ECCPOS1 1 -#define NAND_NOOB_ECCPOS2 2 -#define NAND_NOOB_ECCPOS3 3 -#define NAND_NOOB_ECCPOS4 6 -#define NAND_NOOB_ECCPOS5 7 -#define NAND_NOOB_BADBPOS -1 -#define NAND_NOOB_ECCVPOS -1 - -#define NAND_JFFS2_OOB_ECCPOS0 0 -#define NAND_JFFS2_OOB_ECCPOS1 1 -#define NAND_JFFS2_OOB_ECCPOS2 2 -#define NAND_JFFS2_OOB_ECCPOS3 3 -#define NAND_JFFS2_OOB_ECCPOS4 6 -#define NAND_JFFS2_OOB_ECCPOS5 7 -#define NAND_JFFS2_OOB_BADBPOS 5 -#define NAND_JFFS2_OOB_ECCVPOS 4 - -#define NAND_JFFS2_OOB8_FSDAPOS 6 -#define NAND_JFFS2_OOB16_FSDAPOS 8 -#define NAND_JFFS2_OOB8_FSDALEN 2 -#define NAND_JFFS2_OOB16_FSDALEN 8 - -unsigned long nand_probe(unsigned long physadr); +#define NAND_SMALL_BADBLOCK_POS 5 +#define NAND_LARGE_BADBLOCK_POS 0 #endif /* __LINUX_MTD_NAND_H */ diff --git a/include/linux/mtd/nand_ecc.h b/include/linux/mtd/nand_ecc.h new file mode 100644 index 0000000..12c5bc3 --- /dev/null +++ b/include/linux/mtd/nand_ecc.h @@ -0,0 +1,30 @@ +/* + * drivers/mtd/nand_ecc.h + * + * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) + * + * $Id: nand_ecc.h,v 1.4 2004/06/17 02:35:02 dbrown Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This file is the header for the ECC algorithm. + */ + +#ifndef __MTD_NAND_ECC_H__ +#define __MTD_NAND_ECC_H__ + +struct mtd_info; + +/* + * Calculate 3 byte ECC code for 256 byte block + */ +int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code); + +/* + * Detect and correct a 1 bit error for 256 byte block + */ +int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc); + +#endif /* __MTD_NAND_ECC_H__ */ diff --git a/include/linux/mtd/nand_ids.h b/include/linux/mtd/nand_ids.h index a3d0363..d9eb911 100644 --- a/include/linux/mtd/nand_ids.h +++ b/include/linux/mtd/nand_ids.h @@ -28,6 +28,10 @@ #ifndef __LINUX_MTD_NAND_IDS_H #define __LINUX_MTD_NAND_IDS_H +#ifndef CFG_NAND_LEGACY +#error This module is for the legacy NAND support +#endif + static struct nand_flash_dev nand_flash_ids[] = { {"Toshiba TC5816BDC", NAND_MFR_TOSHIBA, 0x64, 21, 1, 2, 0x1000, 0}, {"Toshiba TC5832DC", NAND_MFR_TOSHIBA, 0x6b, 22, 0, 2, 0x2000, 0}, @@ -49,6 +53,7 @@ static struct nand_flash_dev nand_flash_ids[] = { {"Samsung KM29W16000", NAND_MFR_SAMSUNG, 0xea, 21, 1, 2, 0x1000, 0}, {"Samsung K9F5616Q0C", NAND_MFR_SAMSUNG, 0x45, 25, 0, 2, 0x4000, 1}, {"Samsung K9K1216Q0C", NAND_MFR_SAMSUNG, 0x46, 26, 0, 3, 0x4000, 1}, + {"Samsung K9F1G08U0M", NAND_MFR_SAMSUNG, 0xf1, 27, 0, 2, 0, 0}, {NULL,} }; diff --git a/include/linux/mtd/nand_legacy.h b/include/linux/mtd/nand_legacy.h new file mode 100644 index 0000000..a8769e7 --- /dev/null +++ b/include/linux/mtd/nand_legacy.h @@ -0,0 +1,203 @@ +/* + * linux/include/linux/mtd/nand.h + * + * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com> + * Steven J. Hill <sjhill@cotw.com> + * Thomas Gleixner <gleixner@autronix.de> + * + * $Id: nand.h,v 1.7 2003/07/24 23:30:46 a0384864 Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Info: + * Contains standard defines and IDs for NAND flash devices + * + * Changelog: + * 01-31-2000 DMW Created + * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers + * so it can be used by other NAND flash device + * drivers. I also changed the copyright since none + * of the original contents of this file are specific + * to DoC devices. David can whack me with a baseball + * bat later if I did something naughty. + * 10-11-2000 SJH Added private NAND flash structure for driver + * 10-24-2000 SJH Added prototype for 'nand_scan' function + * 10-29-2001 TG changed nand_chip structure to support + * hardwarespecific function for accessing control lines + * 02-21-2002 TG added support for different read/write adress and + * ready/busy line access function + * 02-26-2002 TG added chip_delay to nand_chip structure to optimize + * command delay times for different chips + * 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate + * defines in jffs2/wbuf.c + */ +#ifndef __LINUX_MTD_NAND_LEGACY_H +#define __LINUX_MTD_NAND_LEGACY_H + +#ifndef CFG_NAND_LEGACY +#error This module is for the legacy NAND support +#endif + +/* + * Standard NAND flash commands + */ +#define NAND_CMD_READ0 0 +#define NAND_CMD_READ1 1 +#define NAND_CMD_PAGEPROG 0x10 +#define NAND_CMD_READOOB 0x50 +#define NAND_CMD_ERASE1 0x60 +#define NAND_CMD_STATUS 0x70 +#define NAND_CMD_SEQIN 0x80 +#define NAND_CMD_READID 0x90 +#define NAND_CMD_ERASE2 0xd0 +#define NAND_CMD_RESET 0xff + +/* + * Enumeration for NAND flash chip state + */ +typedef enum { + FL_READY, + FL_READING, + FL_WRITING, + FL_ERASING, + FL_SYNCING +} nand_state_t; + + +/* + * NAND Private Flash Chip Data + * + * Structure overview: + * + * IO_ADDR - address to access the 8 I/O lines of the flash device + * + * hwcontrol - hardwarespecific function for accesing control-lines + * + * dev_ready - hardwarespecific function for accesing device ready/busy line + * + * chip_lock - spinlock used to protect access to this structure + * + * wq - wait queue to sleep on if a NAND operation is in progress + * + * state - give the current state of the NAND device + * + * page_shift - number of address bits in a page (column address bits) + * + * data_buf - data buffer passed to/from MTD user modules + * + * data_cache - data cache for redundant page access and shadow for + * ECC failure + * + * ecc_code_buf - used only for holding calculated or read ECCs for + * a page read or written when ECC is in use + * + * reserved - padding to make structure fall on word boundary if + * when ECC is in use + */ +struct Nand { + char floor, chip; + unsigned long curadr; + unsigned char curmode; + /* Also some erase/write/pipeline info when we get that far */ +}; + +struct nand_chip { + int page_shift; + u_char *data_buf; + u_char *data_cache; + int cache_page; + u_char ecc_code_buf[6]; + u_char reserved[2]; + char ChipID; /* Type of DiskOnChip */ + struct Nand *chips; + int chipshift; + char* chips_name; + unsigned long erasesize; + unsigned long mfr; /* Flash IDs - only one type of flash per device */ + unsigned long id; + char* name; + int numchips; + char page256; + char pageadrlen; + unsigned long IO_ADDR; /* address to access the 8 I/O lines to the flash device */ + unsigned long totlen; + uint oobblock; /* Size of OOB blocks (e.g. 512) */ + uint oobsize; /* Amount of OOB data per block (e.g. 16) */ + uint eccsize; + int bus16; +}; + +/* + * NAND Flash Manufacturer ID Codes + */ +#define NAND_MFR_TOSHIBA 0x98 +#define NAND_MFR_SAMSUNG 0xec + +/* + * NAND Flash Device ID Structure + * + * Structure overview: + * + * name - Complete name of device + * + * manufacture_id - manufacturer ID code of device. + * + * model_id - model ID code of device. + * + * chipshift - total number of address bits for the device which + * is used to calculate address offsets and the total + * number of bytes the device is capable of. + * + * page256 - denotes if flash device has 256 byte pages or not. + * + * pageadrlen - number of bytes minus one needed to hold the + * complete address into the flash array. Keep in + * mind that when a read or write is done to a + * specific address, the address is input serially + * 8 bits at a time. This structure member is used + * by the read/write routines as a loop index for + * shifting the address out 8 bits at a time. + * + * erasesize - size of an erase block in the flash device. + */ +struct nand_flash_dev { + char * name; + int manufacture_id; + int model_id; + int chipshift; + char page256; + char pageadrlen; + unsigned long erasesize; + int bus16; +}; + +/* +* Constants for oob configuration +*/ +#define NAND_NOOB_ECCPOS0 0 +#define NAND_NOOB_ECCPOS1 1 +#define NAND_NOOB_ECCPOS2 2 +#define NAND_NOOB_ECCPOS3 3 +#define NAND_NOOB_ECCPOS4 6 +#define NAND_NOOB_ECCPOS5 7 +#define NAND_NOOB_BADBPOS -1 +#define NAND_NOOB_ECCVPOS -1 + +#define NAND_JFFS2_OOB_ECCPOS0 0 +#define NAND_JFFS2_OOB_ECCPOS1 1 +#define NAND_JFFS2_OOB_ECCPOS2 2 +#define NAND_JFFS2_OOB_ECCPOS3 3 +#define NAND_JFFS2_OOB_ECCPOS4 6 +#define NAND_JFFS2_OOB_ECCPOS5 7 +#define NAND_JFFS2_OOB_BADBPOS 5 +#define NAND_JFFS2_OOB_ECCVPOS 4 + +#define NAND_JFFS2_OOB8_FSDAPOS 6 +#define NAND_JFFS2_OOB16_FSDAPOS 8 +#define NAND_JFFS2_OOB8_FSDALEN 2 +#define NAND_JFFS2_OOB16_FSDALEN 8 + +unsigned long nand_probe(unsigned long physadr); +#endif /* __LINUX_MTD_NAND_LEGACY_H */ diff --git a/include/linux/stat.h b/include/linux/stat.h index 2f7a3b3..f9422cb 100644 --- a/include/linux/stat.h +++ b/include/linux/stat.h @@ -67,7 +67,7 @@ struct stat { #endif /* __PPC__ */ -#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) +#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__blackfin__) struct stat { unsigned short st_dev; diff --git a/include/nand.h b/include/nand.h new file mode 100644 index 0000000..905115b --- /dev/null +++ b/include/nand.h @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2005 + * 2N Telekomunikace, a.s. <www.2n.cz> + * Ladislav Michl <michl@2n.cz> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _NAND_H_ +#define _NAND_H_ + +#include <linux/mtd/compat.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> + +typedef struct mtd_info nand_info_t; + +extern int nand_curr_device; +extern nand_info_t nand_info[]; + +static inline int nand_read(nand_info_t *info, ulong ofs, ulong *len, u_char *buf) +{ + return info->read(info, ofs, *len, (size_t *)len, buf); +} + +static inline int nand_write(nand_info_t *info, ulong ofs, ulong *len, u_char *buf) +{ + return info->write(info, ofs, *len, (size_t *)len, buf); +} + +static inline int nand_block_isbad(nand_info_t *info, ulong ofs) +{ + return info->block_isbad(info, ofs); +} + +static inline int nand_erase(nand_info_t *info, ulong off, ulong size) +{ + struct erase_info instr; + + instr.mtd = info; + instr.addr = off; + instr.len = size; + instr.callback = 0; + + return info->erase(info, &instr); +} + +#endif diff --git a/include/ns16550.h b/include/ns16550.h index e17a11e..d987a8b 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -45,15 +45,15 @@ struct NS16550 { } __attribute__ ((packed)); #elif (CFG_NS16550_REG_SIZE == 4) struct NS16550 { - unsigned long rbr; /* 0 */ - unsigned long ier; /* 1 */ - unsigned long fcr; /* 2 */ - unsigned long lcr; /* 3 */ - unsigned long mcr; /* 4 */ - unsigned long lsr; /* 5 */ - unsigned long msr; /* 6 */ - unsigned long scr; /* 7 */ -} __attribute__ ((packed)); + unsigned long rbr; /* 0 r */ + unsigned long ier; /* 1 rw */ + unsigned long fcr; /* 2 w */ + unsigned long lcr; /* 3 rw */ + unsigned long mcr; /* 4 rw */ + unsigned long lsr; /* 5 r */ + unsigned long msr; /* 6 r */ + unsigned long scr; /* 7 rw */ +}; /* No need to pack an already aligned struct */ #elif (CFG_NS16550_REG_SIZE == -4) struct NS16550 { unsigned char rbr; /* 0 */ @@ -102,7 +102,7 @@ typedef volatile struct NS16550 *NS16550_t; #define MCR_DMA_EN 0x04 #define MCR_TX_DFR 0x08 -#define LCR_WLS_MSK 0x03 /* character length slect mask */ +#define LCR_WLS_MSK 0x03 /* character length select mask */ #define LCR_WLS_5 0x00 /* 5 bit character length */ #define LCR_WLS_6 0x01 /* 6 bit character length */ #define LCR_WLS_7 0x02 /* 7 bit character length */ diff --git a/include/pci.h b/include/pci.h index 8f19997..0fc00e4 100644 --- a/include/pci.h +++ b/include/pci.h @@ -309,6 +309,7 @@ struct pci_region { #define PCI_REGION_MEM 0x00000000 /* PCI memory space */ #define PCI_REGION_IO 0x00000001 /* PCI IO space */ #define PCI_REGION_TYPE 0x00000001 +#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */ #define PCI_REGION_MEMORY 0x00000100 /* System memory */ #define PCI_REGION_RO 0x00000200 /* Read-only memory */ @@ -351,8 +352,8 @@ struct pci_config_table { unsigned long priv[3]; }; -extern void pci_cfgfunc_nothing(struct pci_controller* hose, pci_dev_t dev, - struct pci_config_table *); +extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, + struct pci_config_table *); extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *); @@ -386,7 +387,7 @@ struct pci_controller { int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32); /* Used by auto config */ - struct pci_region *pci_mem, *pci_io; + struct pci_region *pci_mem, *pci_io, *pci_prefetch; /* Used by ppc405 autoconfig*/ struct pci_region *pci_fb; @@ -472,6 +473,7 @@ extern int pciauto_region_allocate(struct pci_region* res, unsigned int size, un extern void pciauto_setup_device(struct pci_controller *hose, pci_dev_t dev, int bars_num, struct pci_region *mem, + struct pci_region *prefetch, struct pci_region *io); int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); diff --git a/include/pci_ids.h b/include/pci_ids.h index 7dec378..8cc3ec0 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -510,6 +510,7 @@ #define PCI_DEVICE_ID_CT_65554 0x00e4 #define PCI_DEVICE_ID_CT_65555 0x00e5 #define PCI_DEVICE_ID_CT_69000 0x00c0 +#define PCI_DEVICE_ID_CT_69030 0x0c30 #define PCI_VENDOR_ID_MIRO 0x1031 #define PCI_DEVICE_ID_MIRO_36050 0x5601 diff --git a/include/version.h b/include/version.h index 4f8b498..b56d2e9 100644 --- a/include/version.h +++ b/include/version.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2003 + * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -24,6 +24,6 @@ #ifndef __VERSION_H__ #define __VERSION_H__ -#define U_BOOT_VERSION "U-Boot 1.1.4" +#include "version_autogenerated.h" #endif /* __VERSION_H__ */ diff --git a/lib_arm/armlinux.c b/lib_arm/armlinux.c index ca630b3..dba2ff7 100644 --- a/lib_arm/armlinux.c +++ b/lib_arm/armlinux.c @@ -124,7 +124,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], checksum = ntohl (hdr->ih_hcrc); hdr->ih_hcrc = 0; - if (crc32 (0, (char *) data, len) != checksum) { + if (crc32 (0, (unsigned char *) data, len) != checksum) { printf ("Bad Header Checksum\n"); SHOW_BOOT_PROGRESS (-11); do_reset (cmdtp, flag, argc, argv); @@ -148,7 +148,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], ulong csum = 0; printf (" Verifying Checksum ... "); - csum = crc32 (0, (char *) data, len); + csum = crc32 (0, (unsigned char *) data, len); if (csum != ntohl (hdr->ih_dcrc)) { printf ("Bad Data CRC\n"); SHOW_BOOT_PROGRESS (-12); diff --git a/lib_arm/board.c b/lib_arm/board.c index fa3c92e..1028b04 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002 + * (C) Copyright 2002-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2002 @@ -25,6 +25,19 @@ * MA 02111-1307 USA */ +/* + * To match the U-Boot user interface on ARM platforms to the U-Boot + * standard (as on PPC platforms), some messages with debug character + * are removed from the default U-Boot build. + * + * Define DEBUG here if you want additional info as shown below + * printed upon startup: + * + * U-Boot code: 00F00000 -> 00F3C774 BSS: -> 00FC3274 + * IRQ Stack: 00ebff7c + * FIQ Stack: 00ebef7c + */ + #include <common.h> #include <command.h> #include <malloc.h> @@ -39,6 +52,8 @@ #include "../drivers/lan91c96.h" #endif +DECLARE_GLOBAL_DATA_PTR; + #if (CONFIG_COMMANDS & CFG_CMD_NAND) void nand_init (void); #endif @@ -106,9 +121,7 @@ void *sbrk (ptrdiff_t increment) static int init_baudrate (void) { - DECLARE_GLOBAL_DATA_PTR; - - uchar tmp[64]; /* long enough for environment variables */ + char tmp[64]; /* long enough for environment variables */ int i = getenv_r ("baudrate", tmp, sizeof (tmp)); gd->bd->bi_baudrate = gd->baudrate = (i > 0) ? (int) simple_strtoul (tmp, NULL, 10) @@ -120,14 +133,14 @@ static int init_baudrate (void) static int display_banner (void) { printf ("\n\n%s\n\n", version_string); - printf ("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", - _armboot_start, _bss_start, _bss_end); + debug ("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", + _armboot_start, _bss_start, _bss_end); #ifdef CONFIG_MODEM_SUPPORT - puts ("Modem Support enabled\n"); + debug ("Modem Support enabled\n"); #endif #ifdef CONFIG_USE_IRQ - printf ("IRQ Stack: %08lx\n", IRQ_STACK_START); - printf ("FIQ Stack: %08lx\n", FIQ_STACK_START); + debug ("IRQ Stack: %08lx\n", IRQ_STACK_START); + debug ("FIQ Stack: %08lx\n", FIQ_STACK_START); #endif return (0); @@ -142,24 +155,35 @@ static int display_banner (void) */ static int display_dram_config (void) { - DECLARE_GLOBAL_DATA_PTR; int i; +#ifdef DEBUG puts ("RAM Configuration:\n"); for(i=0; i<CONFIG_NR_DRAM_BANKS; i++) { printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); print_size (gd->bd->bi_dram[i].size, "\n"); } +#else + ulong size = 0; + + for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) { + size += gd->bd->bi_dram[i].size; + } + puts("DRAM: "); + print_size(size, "\n"); +#endif return (0); } +#ifndef CFG_NO_FLASH static void display_flash_config (ulong size) { puts ("Flash: "); print_size (size, "\n"); } +#endif /* CFG_NO_FLASH */ /* @@ -187,6 +211,8 @@ static void display_flash_config (ulong size) */ typedef int (init_fnc_t) (void); +int print_cpuinfo (void); /* test-only */ + init_fnc_t *init_sequence[] = { cpu_init, /* basic cpu dependent setup */ board_init, /* basic board dependent setup */ @@ -196,21 +222,24 @@ init_fnc_t *init_sequence[] = { serial_init, /* serial communications setup */ console_init_f, /* stage 1 init of console */ display_banner, /* say that we are here */ +#if defined(CONFIG_DISPLAY_CPUINFO) + print_cpuinfo, /* display cpu info (and speed) */ +#endif +#if defined(CONFIG_DISPLAY_BOARDINFO) + checkboard, /* display board info */ +#endif dram_init, /* configure available RAM banks */ display_dram_config, -#if defined(CONFIG_VCMA9) || defined (CONFIG_CMC_PU2) - checkboard, -#endif NULL, }; void start_armboot (void) { - DECLARE_GLOBAL_DATA_PTR; - - ulong size; init_fnc_t **init_fnc_ptr; char *s; +#ifndef CFG_NO_FLASH + ulong size; +#endif #if defined(CONFIG_VFD) || defined(CONFIG_LCD) unsigned long addr; #endif @@ -232,9 +261,11 @@ void start_armboot (void) } } +#ifndef CFG_NO_FLASH /* configure available FLASH banks */ size = flash_init (); display_flash_config (size); +#endif /* CFG_NO_FLASH */ #ifdef CONFIG_VFD # ifndef PAGE_SIZE @@ -291,7 +322,7 @@ void start_armboot (void) int i; ulong reg; char *s, *e; - uchar tmp[64]; + char tmp[64]; i = getenv_r ("ethaddr", tmp, sizeof (tmp)); s = (i > 0) ? tmp : NULL; @@ -301,6 +332,17 @@ void start_armboot (void) if (s) s = (*e) ? e + 1 : e; } + +#ifdef CONFIG_HAS_ETH1 + i = getenv_r ("eth1addr", tmp, sizeof (tmp)); + s = (i > 0) ? tmp : NULL; + + for (reg = 0; reg < 6; ++reg) { + gd->bd->bi_enet1addr[reg] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } +#endif } devices_init (); /* get the devices list going. */ @@ -366,6 +408,8 @@ void hang (void) } #ifdef CONFIG_MODEM_SUPPORT +static inline void mdm_readline(char *buf, int bufsiz); + /* called from main loop (common/main.c) */ extern void dbg(const char *fmt, ...); int mdm_init (void) @@ -374,7 +418,6 @@ int mdm_init (void) char *init_str; int i; extern char console_buffer[]; - static inline void mdm_readline(char *buf, int bufsiz); extern void enable_putc(void); extern int hwflow_onoff(int); diff --git a/lib_blackfin/Makefile b/lib_blackfin/Makefile new file mode 100644 index 0000000..bc280d0 --- /dev/null +++ b/lib_blackfin/Makefile @@ -0,0 +1,47 @@ +# +# U-boot Makefile +# +# Copyright (c) 2005 blackfin.uclinux.org +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(ARCH).a + +AOBJS = + +COBJS = board.o bf533_linux.o bf533_string.o cache.o muldi3.o +OBJS = $(AOBJS) $(COBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/lib_blackfin/bf533_linux.c b/lib_blackfin/bf533_linux.c new file mode 100644 index 0000000..88b4da2 --- /dev/null +++ b/lib_blackfin/bf533_linux.c @@ -0,0 +1,91 @@ +/* + * U-boot - bf533_linux.c + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Dummy functions, currently not in Use */ + +#include <common.h> +#include <command.h> +#include <image.h> +#include <zlib.h> +#include <asm/byteorder.h> + +#define LINUX_MAX_ENVS 256 +#define LINUX_MAX_ARGS 256 + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +#include <status_led.h> +#define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +#define SHOW_BOOT_PROGRESS(arg) +#endif + +#define CMD_LINE_ADDR 0xFF900000 /* L1 scratchpad */ + +#ifdef SHARED_RESOURCES + extern void swap_to(int device_id); +#endif + +static char *make_command_line(void); + +extern image_header_t header; +extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]); +void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], + ulong addr, ulong * len_ptr, int verify) +{ + int (*appl)(char *cmdline); + char *cmdline; + +#ifdef SHARED_RESOURCES + swap_to(FLASH); +#endif + + appl = (int (*)(char *))ntohl(header.ih_ep); + printf("Starting Kernel at = %x\n", appl); + cmdline = make_command_line(); + if(icache_status()){ + flush_instruction_cache(); + icache_disable(); + } + if(dcache_status()){ + flush_data_cache(); + dcache_disable(); + } + (*appl)(cmdline); +} + +char *make_command_line(void) +{ + char *dest = (char *) CMD_LINE_ADDR; + char *bootargs; + + if ( (bootargs = getenv("bootargs")) == NULL ) + return NULL; + + strncpy(dest, bootargs, 0x1000); + dest[0xfff] = 0; + return dest; +} diff --git a/lib_blackfin/bf533_string.c b/lib_blackfin/bf533_string.c new file mode 100644 index 0000000..c8b1a3a --- /dev/null +++ b/lib_blackfin/bf533_string.c @@ -0,0 +1,185 @@ +/* + * U-boot - bf533_string.c Contains library routines. + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/setup.h> +#include <asm/page.h> +#include <asm/cpu/defBF533.h> + +void *dma_memcpy(void *,const void *,size_t); + +char *strcpy(char *dest, const char *src) +{ + char *xdest = dest; + char temp = 0; + + __asm__ __volatile__ + ("1:\t%2 = B [%1++] (Z);\n\t" + "B [%0++] = %2;\n\t" + "CC = %2;\n\t" + "if cc jump 1b (bp);\n":"=a"(dest), "=a"(src), "=d"(temp) + :"0"(dest), "1"(src), "2"(temp):"memory"); + + return xdest; +} + +char *strncpy(char *dest, const char *src, size_t n) +{ + char *xdest = dest; + char temp = 0; + + if (n == 0) + return xdest; + + __asm__ __volatile__ + ("1:\t%3 = B [%1++] (Z);\n\t" + "B [%0++] = %3;\n\t" + "CC = %3;\n\t" + "if ! cc jump 2f;\n\t" + "%2 += -1;\n\t" + "CC = %2 == 0;\n\t" + "if ! cc jump 1b (bp);\n" + "2:\n":"=a"(dest), "=a"(src), "=da"(n), "=d"(temp) + :"0"(dest), "1"(src), "2"(n), "3"(temp) + :"memory"); + + return xdest; +} + +int strcmp(const char *cs, const char *ct) +{ + char __res1, __res2; + + __asm__ + ("1:\t%2 = B[%0++] (Z);\n\t" /* get *cs */ + "%3 = B[%1++] (Z);\n\t" /* get *ct */ + "CC = %2 == %3;\n\t" /* compare a byte */ + "if ! cc jump 2f;\n\t" /* not equal, break out */ + "CC = %2;\n\t" /* at end of cs? */ + "if cc jump 1b (bp);\n\t" /* no, keep going */ + "jump.s 3f;\n" /* strings are equal */ + "2:\t%2 = %2 - %3;\n" /* *cs - *ct */ + "3:\n": "=a"(cs), "=a"(ct), "=d"(__res1), + "=d"(__res2) + : "0"(cs), "1"(ct)); + + return __res1; +} + +int strncmp(const char *cs, const char *ct, size_t count) +{ + char __res1, __res2; + + if (!count) + return 0; + + __asm__ + ("1:\t%3 = B[%0++] (Z);\n\t" /* get *cs */ + "%4 = B[%1++] (Z);\n\t" /* get *ct */ + "CC = %3 == %4;\n\t" /* compare a byte */ + "if ! cc jump 3f;\n\t" /* not equal, break out */ + "CC = %3;\n\t" /* at end of cs? */ + "if ! cc jump 4f;\n\t" /* yes, all done */ + "%2 += -1;\n\t" /* no, adjust count */ + "CC = %2 == 0;\n\t" "if ! cc jump 1b;\n" /* more to do, keep going */ + "2:\t%3 = 0;\n\t" /* strings are equal */ + "jump.s 4f;\n" "3:\t%3 = %3 - %4;\n" /* *cs - *ct */ + "4:": "=a"(cs), "=a"(ct), "=da"(count), "=d"(__res1), + "=d"(__res2) + : "0"(cs), "1"(ct), "2"(count)); + + return __res1; +} + +/* + * memcpy - Copy one area of memory to another + * @dest: Where to copy to + * @src: Where to copy from + * @count: The size of the area. + * + * You should not use this function to access IO space, use memcpy_toio() + * or memcpy_fromio() instead. + */ +void * memcpy(void * dest,const void *src,size_t count) +{ + char *tmp = (char *) dest, *s = (char *) src; + +/* Turn off the cache, if destination in the L1 memory */ + if ( (tmp >= (char *)L1_ISRAM) && (tmp < (char *)L1_ISRAM_END) + || (tmp >= (char *)DATA_BANKA_SRAM) && (tmp < DATA_BANKA_SRAM_END) + || (tmp >= (char *)DATA_BANKB_SRAM) && (tmp < DATA_BANKB_SRAM_END) ){ + if(icache_status()){ + blackfin_icache_flush_range(src, src+count); + icache_disable(); + } + if(dcache_status()){ + blackfin_dcache_flush_range(src, src+count); + dcache_disable(); + } + dma_memcpy(dest,src,count); + }else{ + while(count--) + *tmp++ = *s++; + } + return dest; +} + +void *dma_memcpy(void * dest,const void *src,size_t count) +{ + + *pMDMA_D0_IRQ_STATUS = DMA_DONE | DMA_ERR; + + /* Copy sram functions from sdram to sram */ + /* Setup destination start address */ + *pMDMA_D0_START_ADDR = (volatile void **)dest; + /* Setup destination xcount */ + *pMDMA_D0_X_COUNT = count ; + /* Setup destination xmodify */ + *pMDMA_D0_X_MODIFY = 1; + + /* Setup Source start address */ + *pMDMA_S0_START_ADDR = (volatile void **)src; + /* Setup Source xcount */ + *pMDMA_S0_X_COUNT = count; + /* Setup Source xmodify */ + *pMDMA_S0_X_MODIFY = 1; + + /* Enable source DMA */ + *pMDMA_S0_CONFIG = (DMAEN); + asm("ssync;"); + + *pMDMA_D0_CONFIG = ( WNR | DMAEN); + + while(*pMDMA_D0_IRQ_STATUS & DMA_RUN){ + *pMDMA_D0_IRQ_STATUS |= (DMA_DONE | DMA_ERR); + } + *pMDMA_D0_IRQ_STATUS |= (DMA_DONE | DMA_ERR); + + dest += count; + src += count; + return dest; +} diff --git a/lib_blackfin/blackfin_board.h b/lib_blackfin/blackfin_board.h new file mode 100644 index 0000000..31c16a2 --- /dev/null +++ b/lib_blackfin/blackfin_board.h @@ -0,0 +1,62 @@ +/* + * U-boot - blackfin_board.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BLACKFIN_BOARD_H__ +#define __BLACKFIN_BOARD_H__ + +extern void timer_init(void); +extern void init_IRQ(void); +extern void rtc_init(void); + +extern ulong uboot_end_data; +extern ulong uboot_end; + +ulong monitor_flash_len; + + +#define VERSION_STRING_SIZE 150 /* including 40 bytes buffer to change any string */ +#define VERSION_STRING_FORMAT "%s (%s - %s)\n" +#define VERSION_STRING U_BOOT_VERSION, __DATE__, __TIME__ + +char version_string[VERSION_STRING_SIZE]; + +int *g_addr; +static ulong mem_malloc_start; +static ulong mem_malloc_end; +static ulong mem_malloc_brk; +extern char _sram_in_sdram_start[]; +extern char _sram_inst_size[]; +#ifdef DEBUG +static void display_global_data(void); +#endif + +/* definitions used to check the SMC card availability */ +#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE +#define UPPER_BYTE_MASK 0xFF00 +#define SMC_IDENT 0x3300 + +#endif diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c new file mode 100644 index 0000000..55d13fa --- /dev/null +++ b/lib_blackfin/board.c @@ -0,0 +1,282 @@ +/* + * U-boot - board.c First C file to be called contains init routines + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <devices.h> +#include <version.h> +#include <net.h> +#include <environment.h> +#include "blackfin_board.h" +#include "../drivers/smc91111.h" + +extern flash_info_t flash_info[]; + + +static void mem_malloc_init(void) +{ + mem_malloc_start = CFG_MALLOC_BASE; + mem_malloc_end = (CFG_MALLOC_BASE + CFG_MALLOC_LEN); + mem_malloc_brk = mem_malloc_start; + memset((void *) mem_malloc_start, 0, + mem_malloc_end - mem_malloc_start); +} + +void *sbrk(ptrdiff_t increment) +{ + ulong old = mem_malloc_brk; + ulong new = old + increment; + + if ((new < mem_malloc_start) || (new > mem_malloc_end)) { + return (NULL); + } + mem_malloc_brk = new; + + return ((void *) old); +} + +static int display_banner(void) +{ + sprintf(version_string, VERSION_STRING_FORMAT, VERSION_STRING); + printf("%s\n", version_string); + return (0); +} + +static void display_flash_config(ulong size) +{ + puts("FLASH: "); + print_size(size, "\n"); + return; +} + +static int init_baudrate(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + uchar tmp[64]; + int i = getenv_r("baudrate", tmp, sizeof(tmp)); + gd->bd->bi_baudrate = gd->baudrate = (i > 0) + ? (int) simple_strtoul(tmp, NULL, 10) + : CONFIG_BAUDRATE; + return (0); +} + +#ifdef DEBUG +static void display_global_data(void) +{ + DECLARE_GLOBAL_DATA_PTR; + bd_t *bd; + bd = gd->bd; + printf("--flags:%x\n", gd->flags); + printf("--board_type:%x\n", gd->board_type); + printf("--baudrate:%x\n", gd->baudrate); + printf("--have_console:%x\n", gd->have_console); + printf("--ram_size:%x\n", gd->ram_size); + printf("--reloc_off:%x\n", gd->reloc_off); + printf("--env_addr:%x\n", gd->env_addr); + printf("--env_valid:%x\n", gd->env_valid); + printf("--bd:%x %x\n", gd->bd, bd); + printf("---bi_baudrate:%x\n", bd->bi_baudrate); + printf("---bi_ip_addr:%x\n", bd->bi_ip_addr); + printf("---bi_enetaddr:%x %x %x %x %x %x\n", + bd->bi_enetaddr[0], + bd->bi_enetaddr[1], + bd->bi_enetaddr[2], + bd->bi_enetaddr[3], + bd->bi_enetaddr[4], + bd->bi_enetaddr[5]); + printf("---bi_arch_number:%x\n", bd->bi_arch_number); + printf("---bi_boot_params:%x\n", bd->bi_boot_params); + printf("---bi_memstart:%x\n", bd->bi_memstart); + printf("---bi_memsize:%x\n", bd->bi_memsize); + printf("---bi_flashstart:%x\n", bd->bi_flashstart); + printf("---bi_flashsize:%x\n", bd->bi_flashsize); + printf("---bi_flashoffset:%x\n", bd->bi_flashoffset); + printf("--jt:%x *:%x\n", gd->jt, *(gd->jt)); +} +#endif + +/* + * All attempts to come up with a "common" initialization sequence + * that works for all boards and architectures failed: some of the + * requirements are just _too_ different. To get rid of the resulting + * mess of board dependend #ifdef'ed code we now make the whole + * initialization sequence configurable to the user. + * + * The requirements for any new initalization function is simple: it + * receives a pointer to the "global data" structure as it's only + * argument, and returns an integer return code, where 0 means + * "continue" and != 0 means "fatal error, hang the system". + */ + +void board_init_f(ulong bootflag) +{ + DECLARE_GLOBAL_DATA_PTR; + ulong addr; + bd_t *bd; + + gd = (gd_t *) (CFG_GBL_DATA_ADDR); + memset((void *) gd, 0, sizeof(gd_t)); + + /* Board data initialization */ + addr = (CFG_GBL_DATA_ADDR + sizeof(gd_t)); + + /* Align to 4 byte boundary */ + addr &= ~(4 - 1); + bd = (bd_t*)addr; + gd->bd = bd; + memset((void *) bd, 0, sizeof(bd_t)); + + /* Initialize */ + init_IRQ(); + env_init(); /* initialize environment */ + init_baudrate(); /* initialze baudrate settings */ + serial_init(); /* serial communications setup */ + console_init_f(); + display_banner(); /* say that we are here */ + checkboard(); +#if defined(CONFIG_RTC_BF533) && (CONFIG_COMMANDS & CFG_CMD_DATE) + rtc_init(); +#endif + timer_init(); + printf("Clock: VCO: %lu MHz, Core: %lu MHz, System: %lu MHz\n", \ + CONFIG_VCO_HZ/1000000, CONFIG_CCLK_HZ/1000000, CONFIG_SCLK_HZ/1000000); + printf("SDRAM: "); + print_size(initdram(0), "\n"); + board_init_r((gd_t *) gd, 0x20000010); +} + +void board_init_r(gd_t * id, ulong dest_addr) +{ + DECLARE_GLOBAL_DATA_PTR; + ulong size; + extern void malloc_bin_reloc(void); + char *s, *e; + bd_t *bd; + int i; + gd = id; + gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ + bd = gd->bd; + +#if CONFIG_STAMP + /* There are some other pointer constants we must deal with */ + /* configure available FLASH banks */ + size = flash_init(); + display_flash_config(size); + flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE + 0x1ffff, &flash_info[0]); + bd->bi_flashstart = CFG_FLASH_BASE; + bd->bi_flashsize = size; + bd->bi_flashoffset = 0; +#else + bd->bi_flashstart = 0; + bd->bi_flashsize = 0; + bd->bi_flashoffset = 0; +#endif + /* initialize malloc() area */ + mem_malloc_init(); + malloc_bin_reloc(); + + /* relocate environment function pointers etc. */ + env_relocate(); + + /* board MAC address */ + s = getenv("ethaddr"); + for (i = 0; i < 6; ++i) { + bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + + /* IP Address */ + bd->bi_ip_addr = getenv_IPaddr("ipaddr"); + + /* Initialize devices */ + devices_init(); + jumptable_init(); + + /* Initialize the console (after the relocation and devices init) */ + console_init_r(); + + /* Initialize from environment */ + if ((s = getenv("loadaddr")) != NULL) { + load_addr = simple_strtoul(s, NULL, 16); + } +#if (CONFIG_COMMANDS & CFG_CMD_NET) + if ((s = getenv("bootfile")) != NULL) { + copy_filename(BootFile, s, sizeof(BootFile)); + } +#endif +#if defined(CONFIG_MISC_INIT_R) + /* miscellaneous platform dependent initialisations */ + misc_init_r(); +#endif + +#ifdef CONFIG_DRIVER_SMC91111 +#ifdef SHARED_RESOURCES + /* Switch to Ethernet */ + swap_to(ETHERNET); +#endif + if ( (SMC_inw(BANK_SELECT) & UPPER_BYTE_MASK) != SMC_IDENT ) { + printf("ERROR: Can't find SMC91111 at address %x\n", SMC_BASE_ADDRESS); + } else { + printf("Net: SMC91111 at 0x%08X\n", SMC_BASE_ADDRESS); + } + +#ifdef SHARED_RESOURCES + swap_to(FLASH); +#endif +#endif +#ifdef CONFIG_SOFT_I2C + init_func_i2c(); +#endif + +#ifdef DEBUG + display_global_data(void); +#endif + + /* main_loop() can return to retry autoboot, if so just run it again. */ + for (;;) { + main_loop(); + } +} + +#ifdef CONFIG_SOFT_I2C +static int init_func_i2c (void) +{ + puts ("I2C: "); + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + puts ("ready\n"); + return (0); +} +#endif + +void hang(void) +{ + puts("### ERROR ### Please RESET the board ###\n"); + for (;;); +} diff --git a/lib_blackfin/cache.c b/lib_blackfin/cache.c new file mode 100644 index 0000000..847278d --- /dev/null +++ b/lib_blackfin/cache.c @@ -0,0 +1,40 @@ +/* + * U-boot - cache.c + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* for now: just dummy functions to satisfy the linker */ +extern void blackfin_icache_range (unsigned long *, unsigned long *); +extern void blackfin_dcache_range (unsigned long *, unsigned long *); +void flush_cache (unsigned long dummy1, unsigned long dummy2) +{ + if (icache_status ()) { + blackfin_icache_flush_range (dummy1, dummy1 + dummy2); + } + if (dcache_status ()) { + blackfin_dcache_flush_range (dummy1, dummy1 + dummy2); + } + return; +} diff --git a/lib_blackfin/muldi3.c b/lib_blackfin/muldi3.c new file mode 100644 index 0000000..1fc34e3 --- /dev/null +++ b/lib_blackfin/muldi3.c @@ -0,0 +1,92 @@ +/* + * U-boot - muldi3.c contains routines for mult and div + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Generic function got from GNU gcc package, libgcc2.c */ +#ifndef SI_TYPE_SIZE +#define SI_TYPE_SIZE 32 +#endif +#define __ll_B (1L << (SI_TYPE_SIZE / 2)) +#define __ll_lowpart(t) ((USItype) (t) % __ll_B) +#define __ll_highpart(t) ((USItype) (t) / __ll_B) +#define BITS_PER_UNIT 8 + +#if !defined (umul_ppmm) +#define umul_ppmm(w1, w0, u, v) \ +do { \ + USItype __x0, __x1, __x2, __x3; \ + USItype __ul, __vl, __uh, __vh; \ + \ + __ul = __ll_lowpart (u); \ + __uh = __ll_highpart (u); \ + __vl = __ll_lowpart (v); \ + __vh = __ll_highpart (v); \ + \ + __x0 = (USItype) __ul * __vl; \ + __x1 = (USItype) __ul * __vh; \ + __x2 = (USItype) __uh * __vl; \ + __x3 = (USItype) __uh * __vh; \ + \ + __x1 += __ll_highpart (__x0);/* this can't give carry */ \ + __x1 += __x2; /* but this indeed can */ \ + if (__x1 < __x2) /* did we get it? */ \ + __x3 += __ll_B; /* yes, add it in the proper pos. */ \ + \ + (w1) = __x3 + __ll_highpart (__x1); \ + (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \ +} while (0) +#endif + +#if !defined (__umulsidi3) +#define __umulsidi3(u, v) \ + ({DIunion __w; \ + umul_ppmm (__w.s.high, __w.s.low, u, v); \ + __w.ll; }) +#endif + +typedef unsigned int USItype __attribute__ ((mode (SI))); +typedef int SItype __attribute__ ((mode (SI))); +typedef int DItype __attribute__ ((mode (DI))); +typedef int word_type __attribute__ ((mode (__word__))); + +struct DIstruct {SItype low, high;}; +typedef union +{ + struct DIstruct s; + DItype ll; +} DIunion; + +DItype __muldi3 (DItype u, DItype v) +{ + DIunion w; + DIunion uu, vv; + + uu.ll = u, + vv.ll = v; + /* panic("kernel panic for __muldi3"); */ + w.ll = __umulsidi3 (uu.s.low, vv.s.low); + w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high + + (USItype) uu.s.high * (USItype) vv.s.low); + + return w.ll; +} diff --git a/lib_ppc/board.c b/lib_ppc/board.c index f40bb25..e569e97 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -670,7 +670,8 @@ void board_init_r (gd_t *id, ulong dest_addr) WATCHDOG_RESET(); -#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM) +#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || \ + defined (CONFIG_FLAGADM) || defined(CONFIG_MPC83XX) icache_enable (); /* it's time to enable the instruction cache */ #endif diff --git a/net/bootp.c b/net/bootp.c index 8c56c08..669d74a 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -715,7 +715,7 @@ BootpRequest (void) } #if (CONFIG_COMMANDS & CFG_CMD_DHCP) -static void DhcpOptionsProcess (uchar * popt) +static void DhcpOptionsProcess (uchar * popt, Bootp_t *bp) { uchar *end = popt + BOOTP_HDR_SIZE; int oplen, size; @@ -772,6 +772,34 @@ static void DhcpOptionsProcess (uchar * popt) break; case 59: /* Ignore Rebinding Time Option */ break; + case 66: /* Ignore TFTP server name */ + break; + case 67: /* vendor opt bootfile */ + /* + * I can't use dhcp_vendorex_proc here because I need + * to write into the bootp packet - even then I had to + * pass the bootp packet pointer into here as the + * second arg + */ + size = truncate_sz ("Opt Boot File", + sizeof(bp->bp_file), + oplen); + if (bp->bp_file[0] == '\0' && size > 0) { + /* + * only use vendor boot file if we didn't + * receive a boot file in the main non-vendor + * part of the packet - god only knows why + * some vendors chose not to use this perfectly + * good spot to store the boot file (join on + * Tru64 Unix) it seems mind bogglingly crazy + * to me + */ + printf("*** WARNING: using vendor " + "optional boot file\n"); + memcpy(bp->bp_file, popt + 2, size); + bp->bp_file[size] = '\0'; + } + break; default: #if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) if (dhcp_vendorex_proc (popt)) @@ -882,7 +910,7 @@ DhcpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len) dhcp_state = REQUESTING; if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC)) - DhcpOptionsProcess((u8 *)&bp->bp_vend[4]); + DhcpOptionsProcess((u8 *)&bp->bp_vend[4], bp); BootpCopyNetParams(bp); /* Store net params from reply */ @@ -901,7 +929,7 @@ DhcpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len) char *s; if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC)) - DhcpOptionsProcess((u8 *)&bp->bp_vend[4]); + DhcpOptionsProcess((u8 *)&bp->bp_vend[4], bp); BootpCopyNetParams(bp); /* Store net params from reply */ dhcp_state = BOUND; puts ("DHCP client bound to address "); @@ -222,8 +222,10 @@ void ArpRequest (void) (NetOurIP & NetOurSubnetMask)) { if (NetOurGatewayIP == 0) { puts ("## Warning: gatewayip needed but not set\n"); + NetArpWaitReplyIP = NetArpWaitPacketIP; + } else { + NetArpWaitReplyIP = NetOurGatewayIP; } - NetArpWaitReplyIP = NetOurGatewayIP; } else { NetArpWaitReplyIP = NetArpWaitPacketIP; } diff --git a/rtc/Makefile b/rtc/Makefile index 4ceac76..b08057e 100644 --- a/rtc/Makefile +++ b/rtc/Makefile @@ -28,8 +28,8 @@ include $(TOPDIR)/config.mk LIB = librtc.a OBJS = date.o \ - ds12887.o ds1302.o ds1306.o ds1307.o ds1337.o \ - ds1556.o ds164x.o ds174x.o \ + bf533_rtc.o ds12887.o ds1302.o ds1306.o ds1307.o \ + ds1337.o ds1556.o ds164x.o ds174x.o \ m41t11.o max6900.o m48t35ax.o mc146818.o mk48t59.o \ mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o diff --git a/rtc/bf533_rtc.c b/rtc/bf533_rtc.c new file mode 100644 index 0000000..948be64 --- /dev/null +++ b/rtc/bf533_rtc.c @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * Real Time Clock interface of ADI21535 (Blackfin) for uCLinux + * + * Copyright (C) 2003 Motorola Corporation. All rights reserved. + * Richard Xiao (A2590C@email.mot.com) + * + * Copyright (C) 1996 Paul Gortmaker + * + * + * Based on other minimal char device drivers, like Alan's + * watchdog, Ted's random, etc. etc. + * + * 1.07 Paul Gortmaker. + * 1.08 Miquel van Smoorenburg: disallow certain things on the + * DEC Alpha as the CMOS clock is also used for other things. + * 1.09 Nikita Schmidt: epoch support and some Alpha cleanup. + * 1.09a Pete Zaitcev: Sun SPARC + * 1.09b Jeff Garzik: Modularize, init cleanup + * 1.09c Jeff Garzik: SMP cleanup + * 1.10 Paul Barton-Davis: add support for async I/O + * 1.10a Andrea Arcangeli: Alpha updates + * 1.10b Andrew Morton: SMP lock fix + * 1.10c Cesar Barros: SMP locking fixes and cleanup + * 1.10d Paul Gortmaker: delete paranoia check in rtc_exit + * 1.10e LG Soft India: Register access is different in BF533. + */ + +#include <common.h> +#include <command.h> +#include <rtc.h> + +#if defined(CONFIG_RTC_BF533) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +#include <asm/blackfin.h> +#include <asm/cpu/bf533_rtc.h> + +void rtc_reset (void) +{ + return; /* nothing to do */ +} + +/* Wait for pending writes to complete */ +void wait_for_complete (void) +{ + while (!(*(volatile unsigned short *) RTC_ISTAT & 0x8000)) { + printf (""); + } + *(volatile unsigned short *) RTC_ISTAT = 0x8000; +} + +/* Enable the RTC prescaler enable register */ +void rtc_init () +{ + *(volatile unsigned short *) RTC_PREN = 0x1; + wait_for_complete (); +} + +/* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers + * based on this value. + */ +void rtc_set (struct rtc_time *tmp) +{ + unsigned long n_days_1970 = 0; + unsigned long n_secs_rem = 0; + unsigned long n_hrs = 0; + unsigned long n_mins = 0; + unsigned long n_secs = 0; + unsigned long time_in_secs; + + if (tmp == NULL) { + printf ("Error setting the date/time \n"); + return; + } + + time_in_secs = + mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour, + tmp->tm_min, tmp->tm_sec); + + /* Compute no. of days since 1970 */ + n_days_1970 = (unsigned long) (time_in_secs / (NUM_SECS_IN_DAY)); + + /* From the remining secs, compute the hrs(0-23), mins(0-59) and secs(0-59) */ + n_secs_rem = (unsigned long) (time_in_secs % (NUM_SECS_IN_DAY)); + n_hrs = n_secs_rem / (NUM_SECS_IN_HOUR); + n_secs_rem = n_secs_rem % (NUM_SECS_IN_HOUR); + n_mins = n_secs_rem / (NUM_SECS_IN_MIN); + n_secs = n_secs_rem % (NUM_SECS_IN_MIN); + + /* Store the new time in the RTC_STAT register */ + *(volatile unsigned long *) RTC_STAT = + ((n_days_1970 << DAY_BITS_OFF) | (n_hrs << HOUR_BITS_OFF) | + (n_mins << MIN_BITS_OFF) | (n_secs << SEC_BITS_OFF)); + + wait_for_complete (); +} + +/* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */ +void rtc_get (struct rtc_time *tmp) +{ + unsigned long cur_rtc_stat = 0; + unsigned long time_in_sec; + unsigned long tm_sec = 0, tm_min = 0, tm_hour = 0, tm_day = 0; + + if (tmp == NULL) { + printf ("Error getting the date/time \n"); + return; + } + + /* Read the RTC_STAT register */ + cur_rtc_stat = *(volatile unsigned long *) RTC_STAT; + + /* Get the secs (0-59), mins (0-59), hrs (0-23) and the days since Jan 1970 */ + tm_sec = (cur_rtc_stat >> SEC_BITS_OFF) & 0x3f; + tm_min = (cur_rtc_stat >> MIN_BITS_OFF) & 0x3f; + tm_hour = (cur_rtc_stat >> HOUR_BITS_OFF) & 0x1f; + tm_day = (cur_rtc_stat >> DAY_BITS_OFF) & 0x7fff; + + /* Calculate the total number of seconds since Jan 1970 */ + time_in_sec = (tm_sec) + + MIN_TO_SECS (tm_min) + + HRS_TO_SECS (tm_hour) + + DAYS_TO_SECS (tm_day); + to_tm (time_in_sec, tmp); +} +#endif /* CONFIG_RTC_BF533 && CFG_CMD_DATE */ diff --git a/rtc/rs5c372.c b/rtc/rs5c372.c index 87f38c4..b56808b 100644 --- a/rtc/rs5c372.c +++ b/rtc/rs5c372.c @@ -73,7 +73,7 @@ static unsigned bcd2bin (uchar c); static int setup_done = 0; static int -rs5c372_readram(char *buf, int len) +rs5c372_readram(unsigned char *buf, int len) { int ret; @@ -128,7 +128,7 @@ rs5c372_enable(void) } static void -rs5c372_convert_to_time(struct rtc_time *dt, char *buf) +rs5c372_convert_to_time(struct rtc_time *dt, unsigned char *buf) { /* buf[0] is register 15 */ dt->tm_sec = bcd2bin(buf[1]); diff --git a/tools/mkimage.c b/tools/mkimage.c index fbc1a12..5222bb2 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -93,6 +93,7 @@ table_entry_t arch_name[] = { { IH_CPU_SH, "sh", "SuperH", }, { IH_CPU_SPARC, "sparc", "SPARC", }, { IH_CPU_SPARC64, "sparc64", "SPARC 64 Bit", }, + { IH_CPU_BLACKFIN, "blackfin", "Blackfin", }, { -1, "", "", }, }; @@ -383,7 +384,7 @@ NXTARG: ; if (opt_type == IH_TYPE_MULTI || opt_type == IH_TYPE_SCRIPT) { char *file = datafile; - unsigned long size; + uint32_t size; for (;;) { char *sep = NULL; diff --git a/tools/setlocalversion b/tools/setlocalversion new file mode 100755 index 0000000..9a23825 --- /dev/null +++ b/tools/setlocalversion @@ -0,0 +1,22 @@ +#!/bin/sh +# Print additional version information for non-release trees. + +usage() { + echo "Usage: $0 [srctree]" >&2 + exit 1 +} + +cd "${1:-.}" || usage + +# Check for git and a git repo. +if head=`git rev-parse --verify HEAD 2>/dev/null`; then + # Do we have an untagged version? + if [ "`git name-rev --tags HEAD`" = "HEAD undefined" ]; then + printf '%s%s' -g `echo "$head" | cut -c1-8` + fi + + # Are there uncommitted changes? + if git diff-files | read dummy; then + printf '%s' -dirty + fi +fi |