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-rw-r--r--arch/arm/cpu/armv7/keystone/ddr3.c6
-rw-r--r--arch/arm/include/asm/arch-keystone/ddr3.h55
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware.h39
-rw-r--r--board/ti/k2hk_evm/board.c3
-rw-r--r--board/ti/k2hk_evm/ddr3.c27
5 files changed, 76 insertions, 54 deletions
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c
index 4875db7..bb16551 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -7,10 +7,10 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <asm/arch/hardware.h>
#include <asm/io.h>
+#include <asm/arch/ddr3.h>
-void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
+void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
{
unsigned int tmp;
@@ -57,7 +57,7 @@ void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
;
}
-void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
+void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
{
__raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET);
__raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h
new file mode 100644
index 0000000..05b7e29
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/ddr3.h
@@ -0,0 +1,55 @@
+/*
+ * DDR3
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DDR3_H_
+#define _DDR3_H_
+
+#include <asm/arch/hardware.h>
+
+struct ddr3_phy_config {
+ unsigned int pllcr;
+ unsigned int pgcr1_mask;
+ unsigned int pgcr1_val;
+ unsigned int ptr0;
+ unsigned int ptr1;
+ unsigned int ptr2;
+ unsigned int ptr3;
+ unsigned int ptr4;
+ unsigned int dcr_mask;
+ unsigned int dcr_val;
+ unsigned int dtpr0;
+ unsigned int dtpr1;
+ unsigned int dtpr2;
+ unsigned int mr0;
+ unsigned int mr1;
+ unsigned int mr2;
+ unsigned int dtcr;
+ unsigned int pgcr2;
+ unsigned int zq0cr1;
+ unsigned int zq1cr1;
+ unsigned int zq2cr1;
+ unsigned int pir_v1;
+ unsigned int pir_v2;
+};
+
+struct ddr3_emif_config {
+ unsigned int sdcfg;
+ unsigned int sdtim1;
+ unsigned int sdtim2;
+ unsigned int sdtim3;
+ unsigned int sdtim4;
+ unsigned int zqcfg;
+ unsigned int sdrfc;
+};
+
+void ddr3_init(void);
+void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
+void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index 4e49143..f8f986c 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -22,42 +22,6 @@
typedef volatile unsigned int dv_reg;
typedef volatile unsigned int *dv_reg_p;
-struct ddr3_phy_config {
- unsigned int pllcr;
- unsigned int pgcr1_mask;
- unsigned int pgcr1_val;
- unsigned int ptr0;
- unsigned int ptr1;
- unsigned int ptr2;
- unsigned int ptr3;
- unsigned int ptr4;
- unsigned int dcr_mask;
- unsigned int dcr_val;
- unsigned int dtpr0;
- unsigned int dtpr1;
- unsigned int dtpr2;
- unsigned int mr0;
- unsigned int mr1;
- unsigned int mr2;
- unsigned int dtcr;
- unsigned int pgcr2;
- unsigned int zq0cr1;
- unsigned int zq1cr1;
- unsigned int zq2cr1;
- unsigned int pir_v1;
- unsigned int pir_v2;
-};
-
-struct ddr3_emif_config {
- unsigned int sdcfg;
- unsigned int sdtim1;
- unsigned int sdtim2;
- unsigned int sdtim3;
- unsigned int sdtim4;
- unsigned int zqcfg;
- unsigned int sdrfc;
-};
-
#endif
#define BIT(x) (1 << (x))
@@ -149,9 +113,6 @@ static inline int cpu_revision(void)
void share_all_segments(int priv_id);
int cpu_to_bus(u32 *ptr, u32 length);
-void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
-void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
-void init_ddr3(void);
void sdelay(unsigned long);
#endif
diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c
index ef90f9d..f910ebe 100644
--- a/board/ti/k2hk_evm/board.c
+++ b/board/ti/k2hk_evm/board.c
@@ -12,6 +12,7 @@
#include <fdt_support.h>
#include <libfdt.h>
+#include <asm/arch/ddr3.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#include <asm/io.h>
@@ -63,7 +64,7 @@ static struct pll_init_data pll_config[] = {
int dram_init(void)
{
- init_ddr3();
+ ddr3_init();
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c
index 6092eb8..0085f29 100644
--- a/board/ti/k2hk_evm/ddr3.c
+++ b/board/ti/k2hk_evm/ddr3.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <asm/arch/ddr3.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <i2c.h>
@@ -228,7 +229,7 @@ struct pll_init_data ddr3b_333 = DDR3_PLL_333(B);
struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
struct pll_init_data ddr3b_400 = DDR3_PLL_400(B);
-void init_ddr3(void)
+void ddr3_init(void)
{
char dimm_name[32];
@@ -239,22 +240,26 @@ void init_ddr3(void)
if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
init_pll(&ddr3a_400);
if (cpu_revision() > 0) {
- init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A);
- init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64);
+ ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A);
+ ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE,
+ &ddr3_1600_64);
printf("DRAM: Capacity 8 GiB (includes reported below)\n");
} else {
- init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32);
- init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_32);
+ ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32);
+ ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE,
+ &ddr3_1600_32);
printf("DRAM: Capacity 4 GiB (includes reported below)\n");
}
} else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
init_pll(&ddr3a_333);
if (cpu_revision() > 0) {
- init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A);
- init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64);
+ ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A);
+ ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE,
+ &ddr3_1333_64);
} else {
- init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32);
- init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_32);
+ ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32);
+ ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE,
+ &ddr3_1333_32);
}
} else {
printf("Unknown SO-DIMM. Cannot configure DDR3\n");
@@ -263,6 +268,6 @@ void init_ddr3(void)
}
init_pll(&ddr3b_333);
- init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64);
- init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64);
+ ddr3_init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64);
+ ddr3_init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64);
}
generated by cgit v1.1 at 2024-10-30 14:04:44 +0000