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-rw-r--r--board/amcc/sequoia/sequoia.c7
-rw-r--r--board/amcc/yellowstone/yellowstone.c25
-rw-r--r--board/amcc/yosemite/yosemite.c25
-rw-r--r--cpu/ppc4xx/cpu.c28
-rw-r--r--include/asm-ppc/processor.h13
-rw-r--r--include/configs/yellowstone.h14
-rw-r--r--include/configs/yosemite.h14
7 files changed, 81 insertions, 45 deletions
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 703204f..b2b82c7 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -350,12 +350,19 @@ int misc_init_r(void)
int checkboard(void)
{
char *s = getenv("serial#");
+ u8 rev;
+ u8 val;
#ifdef CONFIG_440EPX
printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
#else
printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
#endif
+
+ rev = *(u8 *)(CFG_CPLD + 0);
+ val = *(u8 *)(CFG_CPLD + 5) & 0x01;
+ printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
+
if (s != NULL) {
puts(", serial# ");
puts(s);
diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c
index 754ae44..04f58e0 100644
--- a/board/amcc/yellowstone/yellowstone.c
+++ b/board/amcc/yellowstone/yellowstone.c
@@ -39,24 +39,6 @@ int board_early_init_f(void)
reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
- mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
- mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
-
- mtebc(pb1ap, 0x00000000);
- mtebc(pb1cr, 0x00000000);
-
- mtebc(pb2ap, 0x04814500);
- /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
-
- mtebc(pb3ap, 0x00000000);
- mtebc(pb3cr, 0x00000000);
-
- mtebc(pb4ap, 0x00000000);
- mtebc(pb4cr, 0x00000000);
-
- mtebc(pb5ap, 0x00000000);
- mtebc(pb5cr, 0x00000000);
-
/*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
@@ -190,8 +172,15 @@ int misc_init_r (void)
int checkboard(void)
{
char *s = getenv("serial#");
+ u8 rev;
+ u8 val;
printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
+
+ rev = *(u8 *)(CFG_CPLD + 0);
+ val = *(u8 *)(CFG_CPLD + 5) & 0x01;
+ printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
+
if (s != NULL) {
puts(", serial# ");
puts(s);
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 588ee90..d47219c 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -39,24 +39,6 @@ int board_early_init_f(void)
reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
- mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
- mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
-
- mtebc(pb1ap, 0x00000000);
- mtebc(pb1cr, 0x00000000);
-
- mtebc(pb2ap, 0x04814500);
- /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
-
- mtebc(pb3ap, 0x00000000);
- mtebc(pb3cr, 0x00000000);
-
- mtebc(pb4ap, 0x00000000);
- mtebc(pb4cr, 0x00000000);
-
- mtebc(pb5ap, 0x00000000);
- mtebc(pb5cr, 0x00000000);
-
/*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
@@ -186,8 +168,15 @@ int misc_init_r (void)
int checkboard(void)
{
char *s = getenv("serial#");
+ u8 rev;
+ u8 val;
printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
+
+ rev = *(u8 *)(CFG_CPLD + 0);
+ val = *(u8 *)(CFG_CPLD + 5) & 0x01;
+ printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
+
if (s != NULL) {
puts(", serial# ");
puts(s);
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 9c5c910..53da5a3 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -332,24 +332,44 @@ int checkcpu (void)
strcpy(addstr, "No Security/Kasumi support");
break;
- case PVR_440SP_RA:
- puts("SP Rev. A");
+ case PVR_440SP_6_RAB:
+ puts("SP Rev. A/B");
+ strcpy(addstr, "RAID 6 support");
break;
- case PVR_440SP_RB:
- puts("SP Rev. B");
+ case PVR_440SP_RAB:
+ puts("SP Rev. A/B");
+ strcpy(addstr, "No RAID 6 support");
+ break;
+
+ case PVR_440SP_6_RC:
+ puts("SP Rev. C");
+ strcpy(addstr, "RAID 6 support");
break;
case PVR_440SP_RC:
puts("SP Rev. C");
+ strcpy(addstr, "No RAID 6 support");
+ break;
+
+ case PVR_440SPe_6_RA:
+ puts("SPe Rev. A");
+ strcpy(addstr, "RAID 6 support");
break;
case PVR_440SPe_RA:
puts("SPe Rev. A");
+ strcpy(addstr, "No RAID 6 support");
+ break;
+
+ case PVR_440SPe_6_RB:
+ puts("SPe Rev. B");
+ strcpy(addstr, "RAID 6 support");
break;
case PVR_440SPe_RB:
puts("SPe Rev. B");
+ strcpy(addstr, "No RAID 6 support");
break;
default:
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 6619686..f102600 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -747,11 +747,14 @@
#define PVR_440GX_RC 0x51B21892
#define PVR_440GX_RF 0x51B21894
#define PVR_405EP_RB 0x51210950
-#define PVR_440SP_RA 0x53221850
-#define PVR_440SP_RB 0x53221891
-#define PVR_440SP_RC 0x53221892
-#define PVR_440SPe_RA 0x53421890
-#define PVR_440SPe_RB 0x53421891
+#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */
+#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */
+#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */
+#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */
+#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */
+#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */
+#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */
+#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */
#define PVR_601 0x00010000
#define PVR_602 0x00050000
#define PVR_603 0x00030000
diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h
index 58717f8..911a52d 100644
--- a/include/configs/yellowstone.h
+++ b/include/configs/yellowstone.h
@@ -302,6 +302,20 @@
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH CFG_FLASH_BASE
+#define CFG_CPLD 0x80000000
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x03017300
+#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000)
+
+/* Memory Bank 2 (CPLD) initialization */
+#define CFG_EBC_PB2AP 0x04814500
+#define CFG_EBC_PB2CR (CFG_CPLD | 0x18000)
+
+/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index 6e942ab..2cc18db 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -307,6 +307,20 @@
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH CFG_FLASH_BASE
+#define CFG_CPLD 0x80000000
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x03017300
+#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000)
+
+/* Memory Bank 2 (CPLD) initialization */
+#define CFG_EBC_PB2AP 0x04814500
+#define CFG_EBC_PB2CR (CFG_CPLD | 0x18000)
+
+/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
generated by cgit v1.1 at 2024-12-22 20:29:41 +0000