diff options
| -rw-r--r-- | CHANGELOG | 200 | ||||
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | cpu/mpc83xx/start.S | 12 | ||||
| -rw-r--r-- | cpu/mpc85xx/speed.c | 4 | ||||
| -rw-r--r-- | cpu/ppc4xx/44x_spd_ddr2.c | 10 | ||||
| -rw-r--r-- | drivers/bios_emulator/x86emu/debug.c | 6 | ||||
| -rw-r--r-- | drivers/net/ax88180.h | 2 | ||||
| -rw-r--r-- | include/asm-ppc/immap_85xx.h | 2 | ||||
| -rw-r--r-- | include/asm-ppc/ppc4xx-sdram.h | 5 |
9 files changed, 231 insertions, 12 deletions
@@ -1,3 +1,203 @@ +commit f7a35a60cf45491871a5c28e9ad24db005487857 +Author: Heiko Schocher <hs@denx.de> +Date: Fri Oct 17 18:24:06 2008 +0200 + + mgcoge: add redundant environment sector + + Signed-off-by: Heiko Schocher <hs@denx.de> + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit c2537ee85954af9d036b18b644f3e18d837bf4a5 +Author: Heiko Schocher <hs@denx.de> +Date: Fri Oct 17 18:23:27 2008 +0200 + + mgsuvd: update size of environment + + Signed-off-by: Heiko Schocher <hs@denx.de> + +commit fa7b1c07e9371aea8f87ee6d3c2ea5564bd8cc8d +Author: Lepcha Suchit <Suchit.Lepcha@freescale.com> +Date: Thu Oct 16 13:38:00 2008 -0500 + + 83xx NAND boot: wait for LTESR[CC] + + At least some revisions of the 8313, and possibly other chips, do not + wait for all pages of the initial 4K NAND region to be loaded before + beginning execution; thus, we wait for it before branching out of the + first NAND page. + + This fixes warm reset problems when booting from NAND on 8313erdb. + + Signed-off-by: Scott Wood <scottwood@freescale.com> + Acked-by: Kim Phillips <kim.phillips@freescale.com> + +commit bf29e0ea0af03d593c64614136acc723a7a022a2 +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Fri Oct 17 12:54:18 2008 +0200 + + ppc4xx: PPC44x MQ initialization + + Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC + values. This fixes the occasional 440SPe hard locking issues when the 440SPe's + dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver). + + Previously the appropriate initialization had been made in Linux, by the + ppc440spe ADMA driver, which is wrong because modifying the MQ configuration + registers after normal operation has begun is not supported and could + have unpredictable results. + + Comment from Stefan: This patch doesn't change the resulting value of the + MQ registers. It explicitly sets/clears all bits to the desired state which + better documents the resulting register value instead of relying on pre-set + default values. + + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit f7d190b1c0b3ab7fc53074ad2862f7de99de37ff +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Oct 16 21:58:50 2008 -0500 + + 85xx: Using proper I2C source clock divider for MPC8544 + + The MPC8544 RM incorrect shows the SEC_CFG bit in PORDEVSR2 as being + bit 26, instead it should be bit 28. This caused in incorrect + interpretation of the i2c_clk which is the same as the SEC clk on + MPC8544. The SEC clk is controlled by cfg_sec_freq that is reported + in PORDEVSR2. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 42653b826adb319a1df06e24ef26096b2a5d9d2a +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Oct 16 21:58:49 2008 -0500 + + Revert "85xx: Using proper I2C source clock divider for MPC8544" + + This reverts commit dffd2446fb041f38ef034b0fcf41e51e5e489159. + + The fix introduced by this patch is not correct. The problem is + that the documentation is not correct for the MPC8544 with regards + to which bit in PORDEVSR2 is for the SEC_CFG. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 2179c4766bffeece98e5e92040629a96c97e230c +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Wed Oct 15 10:19:41 2008 -0500 + + 85xx: Fix compile warning + + mpc8536ds.c: In function 'is_sata_supported': + mpc8536ds.c:614: warning: unused variable 'devdisr' + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 9029b68f3f81b3013044f167ea025e836e6c8c0e +Author: Jason Jin <Jason.jin@freescale.com> +Date: Wed Oct 15 10:40:24 2008 +0800 + + Fix the function conflict in x86emu when DEBUG is on + + The function parse_line() in common/main.c was exposed globally by commit + 6636b62a6efc7f14e6e788788631ae7a7fca4537, Result in conflict with the same + name funciton in drivers/bios_emulator/x86emu/debug.c when define the DEBUG. + This patch fix this by renaming the function in the debug.c file. + + Signed-off-by: Jason Jin <Jason.jin@freescale.com> + +commit b4dbacf69a669a17487054552fc2761149dd6767 +Author: Wolfgang Denk <wd@denx.de> +Date: Wed Oct 15 15:50:45 2008 +0200 + + Coding Style cleanup, update CHANGELOG, prepare 2008.10-rc3 + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 374b9038293d01d8744a46af9b7854a6fd99b228 +Author: Heiko Schocher <hs@denx.de> +Date: Wed Oct 15 09:51:19 2008 +0200 + + Fix compiler warning in lib_ppc/board.c + + Fix compiler warning introduced by commit 0f8cbc18 + + Signed-off-by: Heiko Schocher <hs@denx.de> + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 9724555755a6f1066636481b41f7094e0ce93a69 +Author: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> +Date: Thu Oct 9 10:29:14 2008 +0530 + + mpc83xx: wait till UPM completes the write to array + + Reference manual states that MxMR[MAD] increment is the indication + of write to UPM array is complete. Honour that. Also, make the dummy + write explicit. + + also fix the comment. + + Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 03e2dbb18e858e2f7a6aaa437f290f3690d02d51 +Author: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> +Date: Wed Oct 8 18:12:20 2008 -0500 + + Remove unwanted ';' at end of define. + + Currently this is not creating any problem. But it will result + in compilation error when used as below. + + printf("CFG_SDRAM_CFG2 - %08x\n", CFG_SDRAM_CFG2); + + Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> + + continuation of the theme based on git grep "^#define CFG_.*;$" include/ + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit b2934a56650e9a6c54432f9ce6dc36757967385e +Author: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> +Date: Mon Oct 6 10:53:59 2008 -0400 + + ARM DaVinci: Add maintainer information for SFFSDR board. + + Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> + +commit 12c6670f873ed632c264a6f3e8bf1297d5c3ddbc +Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com> +Date: Sat Oct 4 19:26:16 2008 +0200 + + api: fix type mismatch + + This patch fixes a type mismatch and thus removes a compiler + warning when compiling with CONFIG_API on powerpc. + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> + +commit 9bc2e4eee3bcb8e63847d7a733e0c607807d6141 +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Wed Oct 1 12:25:04 2008 -0500 + + cmd_i2c: Fix help for CONFIG_I2C_CMD_TREE && !CONFIG_I2C_MULTI_BUS + + Original code displayed: + => help i2c + i2c i2c speed [speed] - show or set I2C bus speed + i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device + ... + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit a0b1b610e980e253d4c2519ee15bd0937c3f8be1 +Author: Wolfgang Denk <wd@denx.de> +Date: Tue Oct 14 22:13:41 2008 +0200 + + Update CHANGELOG + + Signed-off-by: Wolfgang Denk <wd@denx.de> + commit 0f8cbc1829d9c7d9616fd29b366a99d037facdcd Author: Jason Jin <Jason.jin@freescale.com> Date: Fri Oct 10 11:41:01 2008 +0800 @@ -24,7 +24,7 @@ VERSION = 2008 PATCHLEVEL = 10 SUBLEVEL = -EXTRAVERSION = -rc2 +EXTRAVERSION = ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 565cc39..cd566b2 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -167,6 +167,18 @@ boot_warm: /* time t 5 */ /* Initialise the E300 processor core */ /*------------------------------------------*/ +#ifdef CONFIG_NAND_SPL + /* The FCM begins execution after only the first page + * is loaded. Wait for the rest before branching + * to another flash page. + */ + addi r7, r3, 0x50b0 +1: dcbi 0, r7 + lwz r6, 0(r7) + andi. r6, r6, 1 + beq 1b +#endif + bl init_e300_core #ifdef CONFIG_SYS_FLASHBOOT diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index d9f9a8c..1e0f483 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -102,9 +102,9 @@ int get_clocks (void) * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. */ if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) - gd->i2c1_clk = sys_info.freqSystemBus / 2; - else gd->i2c1_clk = sys_info.freqSystemBus / 3; + else + gd->i2c1_clk = sys_info.freqSystemBus / 2; #else /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ gd->i2c1_clk = sys_info.freqSystemBus / 2; diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 30c2e44..4544b78 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -2261,10 +2261,12 @@ static void program_memory_queue(unsigned long *dimm_populated, /* * Set optimal value for Memory Queue HB/LL Configuration registers */ - mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR | - SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE); - mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR | - SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE); + mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) | + SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE | + SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL); + mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) | + SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE | + SDRAM_CONF1LL_RPLM); mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN); #endif } diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c index 5cbcc95..29fe3f1 100644 --- a/drivers/bios_emulator/x86emu/debug.c +++ b/drivers/bios_emulator/x86emu/debug.c @@ -50,7 +50,7 @@ static void print_encoded_bytes(u16 s, u16 o); static void print_decoded_instruction(void); -static int parse_line(char *s, int *ps, int *n); +static int x86emu_parse_line(char *s, int *ps, int *n); /* should look something like debug's output. */ void X86EMU_trace_regs(void) @@ -257,7 +257,7 @@ void x86emu_single_step(void) offset = M.x86.saved_ip; while (!done) { printk("-"); - cmd = parse_line(s, ps, &ntok); + cmd = x86emu_parse_line(s, ps, &ntok); switch (cmd) { case 'u': disassemble_forward(M.x86.saved_cs, (u16) offset, 10); @@ -331,7 +331,7 @@ int X86EMU_trace_off(void) return M.x86.debug &= ~(DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F); } -static int parse_line(char *s, int *ps, int *n) +static int x86emu_parse_line(char *s, int *ps, int *n) { int cmd; diff --git a/drivers/net/ax88180.h b/drivers/net/ax88180.h index 5254e7d..d2113df 100644 --- a/drivers/net/ax88180.h +++ b/drivers/net/ax88180.h @@ -182,7 +182,7 @@ struct ax88180_private { #define RXCURT (CMD_BASE + 0x0034) #define DEFAULT_RXCURT 0x00000000 #define RXBOUND (CMD_BASE + 0x0038) - #define DEFAULT_RXBOUND 0x7FF //RX pages 0~7FFh + #define DEFAULT_RXBOUND 0x7FF /* RX pages 0~7FFh */ #define MACCFG0 (CMD_BASE + 0x0040) #define MACCFG0_BIT3_0 0x00000007 #define IPGT_VAL 0x00000150 diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 52f5495..2399243 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1579,7 +1579,7 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */ -#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000020 +#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 char res1[8]; uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ char res2[12]; diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 8efa557..98faced 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -272,8 +272,11 @@ #define SDRAM_CONF1HB_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ #define SDRAM_CONF1HB_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ #define SDRAM_CONF1HB_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ +#define SDRAM_CONF1HB_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */ #define SDRAM_CONF1HB_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ #define SDRAM_CONF1HB_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ +#define SDRAM_CONF1HB_WRCL 0x00000080 /* MCIF Cycle Limit 1 - Bits 22..24 */ +#define SDRAM_CONF1HB_MASK 0x0000F380 /* RPLM & WRCL mask */ #define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */ #define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */ @@ -284,8 +287,10 @@ #define SDRAM_CONF1LL_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ #define SDRAM_CONF1LL_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ #define SDRAM_CONF1LL_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ +#define SDRAM_CONF1LL_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */ #define SDRAM_CONF1LL_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ #define SDRAM_CONF1LL_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ +#define SDRAM_CONF1LL_MASK 0x0000F000 /* RPLM mask */ #define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */ #define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */ |