diff options
59 files changed, 6783 insertions, 1878 deletions
@@ -1,604 +1,107 @@ -commit 8092fef4c29b395958bb649647da7e3775731517 -Author: Martin Krause <Martin.Krause@tqs.de> -Date: Tue Dec 12 14:26:01 2006 +0100 - - Add functions to list of exported functions - - Additionally export the following fuctions (to make trab_config build again): - - simple_strtol() - - strcmp() - - Also bump the ABI version to reflect this change - - Signed-off-by: Martin Krause <martin.krause@tqs.de> - -commit 63cec5814fab5d2b1c86982327433807a5ac0249 -Author: Ed Swarthout <Ed.Swarthout@freescale.com> -Date: Thu Aug 2 14:09:49 2007 -0500 - - Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. - - All of the PCI/PCI-Express driver and initialization code that - was in the MPC8641HPCN port has now been moved into the common - drivers/fsl_pci_init.c. In a subsequent patch, this will be - utilized by the 85xx ports as well. - - Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. - - Also enable the second PCI-Express controller on 8641 - by getting its BATS and CFG_ setup right. - - Fixed a u16 vendor compiler warning in AHCI driver too. - - Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> - Signed-off-by: Zhang Wei <wei.zhang@freescale.com> - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit c7e717ebc2b044d7a71062552c9dc0f54ea9b779 -Author: Andy Fleming <afleming@freescale.com> -Date: Fri Aug 3 04:05:25 2007 -0500 - - Add Marvell 1149 PHY support to the TSEC - -commit 63e22764d2f8653f68888c667eb65b3996b52680 +commit b1b54e352028ed370c3aa95d6fdeb9d64c5d2f86 Author: Wolfgang Denk <wd@denx.de> -Date: Thu Aug 2 10:11:18 2007 +0200 - - Minor cleanup of <board>_nand build rules. +Date: Thu Aug 2 21:27:46 2007 +0200 -commit cdd917a43da6fa7fc8f54a3cc9f420ce5ecf3197 -Author: Wolfgang Denk <wd@denx.de> -Date: Thu Aug 2 00:48:45 2007 +0200 - - Fix build errors and warnings / code cleanup. + Coding style cleanup, update CHANGELOG Signed-off-by: Wolfgang Denk <wd@denx.de> -commit 5a56af3b522ba47fb33a3fee84d23bf1e5429654 -Author: Andy Fleming <afleming@freescale.com> -Date: Fri Jun 8 16:41:18 2007 -0500 - - Remove erroneous errata code from Marvel 88E1111S driver - - The Marvel 88E1111S driver for the TSEC was copied from the - 88E1101 driver, and included a fix for an erratum which does not - exist on that part. Now it is removed - - Signed-off-by: Andy Fleming <afleming@freescale.com> - -commit 982efcf23fd03647e01e2fbe28a7a36239156cc0 -Author: Andy Fleming <afleming@freescale.com> -Date: Tue Jun 5 16:38:44 2007 -0500 - - From: eran liberty <eran.liberty@gmail.com> - - adds the reset register to 85xx immap - - Signed-off-by: Eran Liberty <eran.liberty@gmail.com> - Signed-off-by: Andy Fleming <afleming@freescale.com> - -commit d3ec0d943a045bdb99e159e7bbc77430e09f11d7 -Author: Andy Fleming <afleming@freescale.com> -Date: Thu May 10 17:50:01 2007 -0500 - - Polished the 85xx ADS config files - - Made the boot commands use device trees by default. - Also moved the ramdisk to 1000000 (I think the previous address - was getting overridden during boot). - - Signed-off-by: Andy Fleming <afleming@freescale.com> - -commit bfb37b32d1b0b03f18077dba49cc66a6e76fa038 -Author: Ed Swarthout <Ed.Swarthout@freescale.com> -Date: Wed May 9 11:03:32 2007 -0500 - - 8544ds: Fix Makefile after moving pixis to board/freescale. - - The OBJTREE != SRCTREE build scenario was broken. - This fixes it. - - Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 2a3cee43c3b71fa5b8d91db19f05067865290f3e -Author: Andy Fleming <afleming@freescale.com> -Date: Wed May 9 00:54:20 2007 -0500 - - tsec: Fix PHY code to match first driver - - Jarrold Wen noticed that the generic PHY code always matches - under the current implementation. Change it so the first match - wins, and *only* unknown PHYs trigger the generic driver - - Signed-off-by: Andy Fleming <afleming@freescale.com> - -commit ccc091aac61a38cd998d575d92f7232e256d6312 -Author: Andy Fleming <afleming@freescale.com> -Date: Tue May 8 17:27:43 2007 -0500 - - Add support for CPM device tree configuration to 8560 ADS - - * Adds code to modify CPM frequencies - * Cleans up the config file to #define TSEC and (for now) #undef FCC - * Adds the MII command for all 8560 ADS configurations - * Updates config file to provide convenience commands for booting - with a device tree - - Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com> - Signed-off-by: Andy Fleming <afleming@freescale.com> - -commit 7507d56ccaf7aae1c474342a9a5540165cd7e9d9 -Author: Andy Fleming <afleming@freescale.com> -Date: Tue May 8 17:23:02 2007 -0500 - - Fix Marvell 88e1145 PHY init code - - Fix a bug in the Marvell 88e1145 PHY init code in the TSEC driver - where the reset was being done after the errata code instead of - before. - - Signed-off-by: Haiying Wang <haiying.wang@freescale.com> - Signed-off-by: Andy Fleming <afleming@freescale.com> - -commit 5dc210dec5bace98a50b6ba905347890091a9bb0 -Author: Ed Swarthout <Ed.Swarthout@freescale.com> -Date: Wed Jul 11 14:52:16 2007 -0500 - - Add simple agent/end-point configuration in PCI AutoConfig for PCI_CLASS_PROCESSOR_POWERPC. - - Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> - -commit e8b85f3ba4cd8930e0a2fea2100c815d64201765 -Author: Ed Swarthout <Ed.Swarthout@freescale.com> -Date: Wed Jul 11 14:52:08 2007 -0500 - - pciauto setup bridge - - The P2P bridge bus numbers programmed into the device are relative to - hose->first_busno. - - Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> - -commit 571f49fa717004ca4268b4e24057efc7bf9f987b -Author: Ed Swarthout <Ed.Swarthout@freescale.com> -Date: Wed Jul 11 14:52:01 2007 -0500 - - Support PCIe extended config registers - - FSL PCIe block has extended cfg registers in the 100 and 400 range. - For example, to read the LTSSM register: pci display <busn>.0 404 1 - - Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> - -commit ba5feb12581bb2912ce301e4866b71f846e9fc07 -Author: Ed Swarthout <Ed.Swarthout@freescale.com> -Date: Wed Jul 11 14:51:48 2007 -0500 - - Minor improvements to drivers/pci_auto.c - - - Make pciauto_{pre,post}scan_setup_bridge non-static - - Added physical address display in debug messages. - - Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> - -commit 40e81addab7bb74d20ddf681ce9babc880a828ee -Author: Ed Swarthout <Ed.Swarthout@freescale.com> -Date: Wed Jul 11 14:51:35 2007 -0500 - - Start pci hose scan from hose->current_busno. - - Ensure hose->current_busno is not less than first_busno. This fixes - broken board code which leaves current_busno=0 when first_busno is - greater than 0 for the cases with multiple controllers. - - Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> - -commit 3865b1fb7843a08ad49a6319a36415752276ff48 -Author: Stefan Roese <sr@denx.de> -Date: Wed Jul 11 12:13:53 2007 +0200 - - Fix some compile problems introduced by the latest CFG_CMD_xxx cleanup - - Signed-off-by: Stefan Roese <sr@denx.de> - -commit e9514751cfa5cce61ea699fa0d3eb37898a5eeb5 -Author: Stefan Roese <sr@denx.de> -Date: Sun Jul 8 13:44:27 2007 +0200 - - Fix malloc problem introduced with the relocation fixup for the PPC platform - - The relocation fixup didn't handle the malloc pointer initialization - correctly. This patch fixes this problem. Tested successfully on 4xx. - The relocation fixup patches for 4xx will follow soon. - - Signed-off-by: Stefan Roese <sr@denx.de> - -commit b3aff0cb9ecf236d7e8c93761dd1dadf6837a582 -Author: Jon Loeliger <jdl@freescale.com> -Date: Tue Jul 10 11:19:50 2007 -0500 - - disk/ doc/ lib_*/ and tools/: Remove lingering references to CFG_CMD_* symbols. - - Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. - Those always evaluated TRUE, and thus were always compiled - even when IDE really wasn't defined/wanted. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit ddb5d86f0215bcb6c293510c50eb050e92883b7a -Author: Jon Loeliger <jdl@freescale.com> -Date: Tue Jul 10 11:13:21 2007 -0500 - - drivers/: Remove lingering references to CFG_CMD_* symbols. - - Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. - Those always evaluated TRUE, and thus were always compiled - even when IDE really wasn't defined/wanted. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit f40a7f3e3888b42a43674b099e5470022c8c544c -Author: Jon Loeliger <jdl@freescale.com> -Date: Tue Jul 10 11:07:56 2007 -0500 - - fs/: Remove lingering references to CFG_CMD_* symbols. - - Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. - Those always evaluated TRUE, and thus were always compiled - even when IDE really wasn't defined/wanted. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 610f2e9c28a9c101e09fa1b78143cf5f00ed1593 -Author: Jon Loeliger <jdl@freescale.com> -Date: Tue Jul 10 11:05:02 2007 -0500 - - net/: Remove lingering references to CFG_CMD_* symbols. - - Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. - Those always evaluated TRUE, and thus were always compiled - even when IDE really wasn't defined/wanted. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 902531788376046da212afd1661cffb62f3daa1c -Author: Jon Loeliger <jdl@freescale.com> -Date: Tue Jul 10 11:02:44 2007 -0500 - - common/: Remove lingering references to CFG_CMD_* symbols. - - Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. - Those always evaluated TRUE, and thus were always compiled - even when IDE really wasn't defined/wanted. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit d39b57415838c73fb0a37eca84de3c68ba990586 -Author: Jon Loeliger <jdl@freescale.com> -Date: Tue Jul 10 10:48:22 2007 -0500 - - board/[j-z]*: Remove lingering references to CFG_CMD_* symbols. - - Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. - Those always evaluated TRUE, and thus were always compiled - even when IDE really wasn't defined/wanted. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 77a318545d57aefa844752465b94c7e09a3f26d0 -Author: Jon Loeliger <jdl@freescale.com> -Date: Tue Jul 10 10:39:10 2007 -0500 - - board/[A-Za-i]*: Remove lingering references to CFG_CMD_* symbols. - - Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. - Those always evaluated TRUE, and thus were always compiled - even when IDE really wasn't defined/wanted. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 068b60a0eb7e73b243ca55399f2a7df76e2c3f3d -Author: Jon Loeliger <jdl@freescale.com> -Date: Tue Jul 10 10:27:39 2007 -0500 - - cpu/ rtc/ include/: Remove lingering references to CFG_CMD_* symbols. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 079a136c3588814784561d6e4856970ee82d6e2a -Author: Jon Loeliger <jdl@freescale.com> -Date: Tue Jul 10 10:12:10 2007 -0500 - - include/configs/[p-z]* + misc: Cleanup BOOTP and lingering CFG_CMD_*. - - Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h - used to be included but CONFIG_BOOTP_MASK was not defined. - - Remove lingering references to CFG_CMD_* symbols. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 7f5c01577400c74cc5bac74f41dd0d3c79df623c -Author: Jon Loeliger <jdl@freescale.com> -Date: Tue Jul 10 09:38:02 2007 -0500 - - include/configs/[g-o]*: Cleanup BOOTP and lingering CFG_CMD_*. - - Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h - used to be included but CONFIG_BOOTP_MASK was not defined. - - Remove lingering references to CFG_CMD_* symbols. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 80ff4f99b84b64edca3fd10da365ec1493be1c95 -Author: Jon Loeliger <jdl@freescale.com> -Date: Tue Jul 10 09:29:01 2007 -0500 - - include/configs/[a-e]*: Cleanup BOOTP and lingering CFG_CMD_*. - - Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h - used to be included but CONFIG_BOOTP_MASK was not defined. - - Remove lingering references to CFG_CMD_* symbols. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit a1aa0bb502e25fd598b5e0ccdfb2c174921d714a -Author: Jon Loeliger <jdl@freescale.com> -Date: Tue Jul 10 09:22:23 2007 -0500 - - include/configs/[P-Z]*: Cleanup BOOTP and lingering CFG_CMD_*. - - Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h - used to be included but CONFIG_BOOTP_MASK was not defined. - - Remove lingering references to CFG_CMD_* symbols. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 659e2f6736232a08acca8785c206e2b4d9cd07d7 -Author: Jon Loeliger <jdl@freescale.com> -Date: Tue Jul 10 09:10:49 2007 -0500 - - include/configs/[J-O]*: Cleanup BOOTP and lingering CFG_CMD_*. - - Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h - used to be included but CONFIG_BOOTP_MASK was not defined. - - Remove lingering references to CFG_CMD_* symbols. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 11799434c5ff15a612577bb1ad1f4ea1a0595e4b -Author: Jon Loeliger <jdl@freescale.com> -Date: Tue Jul 10 09:02:57 2007 -0500 - - include/configs/[A-I]*: Cleanup BOOTP and lingering CFG_CMD_*. - - Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h - used to be included but CONFIG_BOOTP_MASK was not defined. - - Remove lingering references to CFG_CMD_* symbols. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 1fe80d79c5c4e52d3410a7ab4b8515da095cdab3 -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 22:08:34 2007 -0500 - - Finally retire cmd_confdefs.h and CONFIG_BOOTP_MASK! - - All of the choices for CONFIG_BOOTP_ are now documented in - the README file. You must now individually select exactly - the set that you want using a series of - #define CONFIG_BOOTP_<x> - statements in the board port config files now. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit d3b8c1a743dcd31625c99e6a44590f207eb00028 -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 21:57:31 2007 -0500 - - include/configs/[m-z]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 2fd90ce575b02d189cbf443c85309bcd001aa393 -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 21:48:26 2007 -0500 - - include/configs/[a-m]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 37d4bb70586659dedef1658ce1bed071be098aec -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 21:38:02 2007 -0500 - - include/configs/[T-Z]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 18225e8dd1950bd6dbf35011e436db7f474c187d -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 21:31:24 2007 -0500 - - include/configs/[P-S]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 7be044e4ea644b0ef1c486dadc1a4c2665b4374d -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 21:24:19 2007 -0500 - - include/configs/[H-N]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 5d2ebe1b3ef0055c661bb1a0d252bf252380069f -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 21:16:53 2007 -0500 - - include/configs/[A-G]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit f55f7f8d83f36021ab1f0e3d738f5d8c8083a7e3 -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 19:12:30 2007 -0500 - - Retire CONFIG_COMMANDS finally. - Strip old CFG_CMD_* symbols out. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit b5501f7d720fed99ab0b42c83f5dea52868ce007 -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 19:10:03 2007 -0500 - - Update README.* to reference new CONFIG_CMD_* names now. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 4431283c7e6d54ae180d466e51bf2d97471a0ad9 -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 19:06:00 2007 -0500 - - cpu/m*: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 3a1ed1e1f922c419bb71f7df4949d783ade369fa -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 18:57:22 2007 -0500 - - cpu/[7a-ln-z]*: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit ab3abcbabd840928fb1eb5122118ca466b5e5013 -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 18:45:16 2007 -0500 - - board/[q-z]*: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 3fe00109a5f12de55b6e25b1f98dfc24bc9090c9 -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 18:38:39 2007 -0500 - - board/[m-p]*: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit c508a4cefd8a953fc64957650506a035e6e3d9d1 -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 18:31:28 2007 -0500 - - board/[f-l]*: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit b9307262f8a9f3b5c9e15a6067eadc17407146f6 -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 18:24:55 2007 -0500 - - board/[d-e]*: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit fcec2eb93e126400009729328e797f12bc94f1fd -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 18:19:09 2007 -0500 - - board/[A-Za-c]*: Remove obsolete references to CONFIG_COMMANDS +commit 8993e54b6f397973794f3d6f47d3b3c0c98dd4f6 +Author: Rafal Jaworowski <raj@semihalf.com> +Date: Fri Jul 27 14:43:59 2007 +0200 - Signed-off-by: Jon Loeliger <jdl@freescale.com> + [ADS5121] Support for the ADS5121 board -commit a593814f2be0c9cdc3133cd550b167b8a988328f -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 18:10:50 2007 -0500 + The following MPC5121e subsystems are supported: - rtc/: Remove obsolete references to CONFIG_COMMANDS + - low-level CPU init + - NOR Boot Flash (common CFI driver) + - DDR SDRAM + - FEC + - I2C + - Watchdog - Signed-off-by: Jon Loeliger <jdl@freescale.com> + Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> + Signed-off-by: Rafal Jaworowski <raj@semihalf.com> + Signed-off-by: Jan Wrobel <wrr@semihalf.com> -commit 67350568f9d46e66c21829f3513b3db0caeb948b -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 18:05:38 2007 -0500 +commit 1863cfb7b100ba0ee3401799457a01dc058745f8 +Author: Rafal Jaworowski <raj@semihalf.com> +Date: Fri Jul 27 14:22:04 2007 +0200 - lib_{arm,avr32,blackfin,generic,i386}/: Remove obsolete references to CONFIG_COMMANDS + [PPC] Remove unused MSR_USER definition - Signed-off-by: Jon Loeliger <jdl@freescale.com> + Signed-off-by: Rafal Jaworowski <raj@semihalf.com> -commit 7def6b34f910f08d7ef0a14646da067719237ca2 -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 18:02:11 2007 -0500 +commit cc3023b9f95d7ac959a764471a65001062aecf41 +Author: Rafal Jaworowski <raj@semihalf.com> +Date: Thu Jul 19 17:12:28 2007 +0200 - lib_{m68k,microblaze,mips,ppc}/: Remove obsolete references to CONFIG_COMMANDS + Fix breakage of 8xx boards from recent commit. - Signed-off-by: Jon Loeliger <jdl@freescale.com> + This patch fixes the negative consequences for 8xx of the recent + "ppc4xx: Clean up 440 exceptions handling" commit. -commit dd60d1223b99a88a7216f3e041fe40634ad4c2bb -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 17:56:50 2007 -0500 + Signed-off-by: Rafal Jaworowski <raj@semihalf.com> - fs/: Remove obsolete references to CONFIG_COMMANDS +commit 3a6cab844cf74f76639d795e0be8717e02c86af7 +Author: Wolfgang Denk <wd@denx.de> +Date: Sat Jul 14 22:51:02 2007 +0200 - Signed-off-by: Jon Loeliger <jdl@freescale.com> + Update CHANGELOG -commit c91898bbc505aff3e12a807af88e76da18efb7ee -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 17:46:09 2007 -0500 + Signed-off-by: Wolfgang Denk <wd@denx.de> - tools/: Remove obsolete references to CONFIG_COMMANDS +commit 011595307731a7a67a7445d107c279d031e8ab97 +Author: Heiko Schocher <hs@pollux.denx.de> +Date: Sat Jul 14 01:06:58 2007 +0200 - Signed-off-by: Jon Loeliger <jdl@freescale.com> + [PCS440EP] - fix compile error, if BUILD_DIR is used -commit 643d1ab23960950b52e0a2803c2d3ea4c558fa01 -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 17:45:14 2007 -0500 +commit fad63407154f46246ce80d53a9c669a44362ac67 +Author: Heiko Schocher <hs@pollux.denx.de> +Date: Fri Jul 13 09:54:17 2007 +0200 - net/: Remove obsolete references to CONFIG_COMMANDS + make show_boot_progress () weak. - Signed-off-by: Jon Loeliger <jdl@freescale.com> + Signed-off-by: Heiko Schocher <hs@denx.de> -commit cb51c0bf88f95a1bca68324b0126f8eed8b43273 -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 17:39:42 2007 -0500 +commit 907902472391b6ca1876ec300687562ecaf459b1 +Author: Heiko Schocher <hs@pollux.denx.de> +Date: Fri Jul 13 08:26:05 2007 +0200 - drivers/[n-z]*: Remove obsolete references to CONFIG_COMMANDS + [PCS440EP] - The DIAG LEDs are now blinking, if an error occur + - fix compile error, if BUILD_DIR is used - Signed-off-by: Jon Loeliger <jdl@freescale.com> + Signed-off-by: Heiko Schocher <hs@denx.de> -commit 07d38a17e964aec4c7827f0ee9a583bc8cc1ad6b -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 17:30:01 2007 -0500 +commit 239f05ee4dd4cfe0b50f251b533dcebe9e67c360 +Author: Wolfgang Denk <wd@denx.de> +Date: Thu Jul 12 01:45:34 2007 +0200 - drivers/[a-m]*: Remove obsolete references to CONFIG_COMMANDS + Update CHANGELOG, minor coding style cleanup. - Signed-off-by: Jon Loeliger <jdl@freescale.com> + Signed-off-by: Wolfgang Denk <wd@denx.de> -commit cde5c64d17cf4834aa7b5c373f288bc7dad27b29 -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 17:22:37 2007 -0500 +commit fa1df308926a6f70e3504c57514ef27ac31fd13a +Author: Bartlomiej Sieka <tur@semihalf.com> +Date: Wed Jul 11 20:11:07 2007 +0200 - disk/: Remove obsolete references to CONFIG_COMMANDS + CM1.QP1: Support for the Schindler CM1.QP1 board. - Signed-off-by: Jon Loeliger <jdl@freescale.com> + Signed-off-by: Piotr Kruszynski <ppk@semihalf.com> + Signed-off-by: Bartlomiej Sieka <tur@semihalf.com> -commit 639221c76c88215bd55af83ad174fc30d1940f8f -Author: Jon Loeliger <jdl@freescale.com> -Date: Mon Jul 9 17:15:49 2007 -0500 +commit 96e1d75be8193ca79e4215a368bf9d7f2362450f +Author: Heiko Schocher <hs@pollux.denx.de> +Date: Wed Jul 11 18:39:11 2007 +0200 - include/: Remove obsolete references to CONFIG_COMMANDS - Mostly removed from comments here. + [PCS440EP] - Show on the DIAG LEDs, if the SHA1 check failed + - now the Flash ST M29W040B is supported (not tested) + - fix the "led" command + - fix compile error, if BUILD_DIR is used - Signed-off-by: Jon Loeliger <jdl@freescale.com> + Signed-off-by: Heiko Schocher <hs@denx.de> commit 4ef218f6fdf8d747f4589da5252b004e7d2c2876 Author: Wolfgang Denk <wd@denx.de> @@ -608,201 +111,6 @@ Date: Tue Jul 10 00:01:28 2007 +0200 Signed-off-by: Wolfgang Denk <wd@denx.de> -commit c3517f919d0f61650cf3027fd4faf0f631142f6c -Author: Jon Loeliger <jdl@freescale.com> -Date: Sun Jul 8 18:10:08 2007 -0500 - - common/* non-cmd*: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit fd9bcaa35be64fe41a4223fdb6ecdbad52470b39 -Author: Jon Loeliger <jdl@freescale.com> -Date: Sun Jul 8 18:05:39 2007 -0500 - - common/cmd_[p-x]*: Remove obsolete references to CONFIG_COMMANDS. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit c76fe47425afc7d5d670ff0539823c85d65d9c42 -Author: Jon Loeliger <jdl@freescale.com> -Date: Sun Jul 8 18:02:23 2007 -0500 - - common/cmd_[i-n]*: Remove obsolete references to CONFIG_COMMANDS. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit baa26db4113679b80970ff447d91cc10217742a6 -Author: Jon Loeliger <jdl@freescale.com> -Date: Sun Jul 8 17:51:39 2007 -0500 - - common/cmd_[af]*: Remove obsolete references to CONFIG_COMMANDS. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit af075ee96e52dda7b6bca6c937588aeaaec5f2cd -Author: Jon Loeliger <jdl@freescale.com> -Date: Sun Jul 8 17:02:01 2007 -0500 - - Clear up confusion over the CMD_POST and POST_DIAG mess. - - For some reason, CONFIG_POST permeated as CONFIG_CMD_POST_DIAG - when it really means just CONFIG_CMD_DIAG. There is no CMD_POST. - Clear this mess up some. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit b3631487105a57ab7cbadfc26efbaf9676275018 -Author: Jon Loeliger <jdl@freescale.com> -Date: Sun Jul 8 15:45:08 2007 -0500 - - Remove references to the old cmd_confdefs.h include file. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit a22d4da95e20049b4daa1c2a022f61e8a72f2fb6 -Author: Jon Loeliger <jdl@freescale.com> -Date: Sun Jul 8 15:42:59 2007 -0500 - - include/configs: Catch some CONFIG_CMD_* conversion stragglers. - - Use new CONFIG_CMD_* in lwmon5.h board config file. - Fix CONFIG_CMD_* typo braindamage in omap1510inn.h - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit a5562901661bd428f7e5feb333f796372cb81019 -Author: Jon Loeliger <jdl@freescale.com> -Date: Sun Jul 8 15:31:57 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various [TUVWZYZ]* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit fe7f782d5b8c64a0195c68c31a0a11d4f641355e -Author: Jon Loeliger <jdl@freescale.com> -Date: Sun Jul 8 15:02:44 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various S* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit e9a0f8f15c11f337967aa0600ad6e8af33037f50 -Author: Jon Loeliger <jdl@freescale.com> -Date: Sun Jul 8 15:12:40 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various R* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 12aa9fd23d724bd6ab88e1baa0db35133a27303f -Author: Jon Loeliger <jdl@freescale.com> -Date: Sun Jul 8 14:55:07 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various Q* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit acf0269779422f3e147d2ddfb499c9f6ff10ad5e -Author: Jon Loeliger <jdl@freescale.com> -Date: Sun Jul 8 14:49:44 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various P* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit e18a1061a8630cb67995fdf99afd3fb50d1b187d -Author: Jon Loeliger <jdl@freescale.com> -Date: Sun Jul 8 14:21:43 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various [NO]* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 8353e139bfad9059c54f5b2421f1a3090e15a2e2 -Author: Jon Loeliger <jdl@freescale.com> -Date: Sun Jul 8 14:14:17 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various M* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 348f258f24253433e4a2302a0bbceb6740a67246 -Author: Jon Loeliger <jdl@freescale.com> -Date: Sun Jul 8 13:46:18 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various [IJKL]* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 6c4f4da9bfc9f9403f54fce678ed0364b7c86a6a -Author: Jon Loeliger <jdl@freescale.com> -Date: Sun Jul 8 10:09:35 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various H* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 60a0876b5106b34220e459c208bbf648073306c0 -Author: Jon Loeliger <jdl@freescale.com> -Date: Sat Jul 7 21:04:26 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various F* and G* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit dcaa71562826a2466e894c868d132509dcda8444 -Author: Jon Loeliger <jdl@freescale.com> -Date: Sat Jul 7 20:56:05 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various E* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 3c3227f3c737502311b25b72084573901cbbf17d -Author: Jon Loeliger <jdl@freescale.com> -Date: Sat Jul 7 20:40:43 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various D* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 49cf7e8ee7ef943fdfe866ce28410b0bfbf6a26c -Author: Jon Loeliger <jdl@freescale.com> -Date: Thu Jul 5 19:52:35 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various C* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit de8b2a6e33298dcdb10bdda48db25e53c3089eba -Author: Jon Loeliger <jdl@freescale.com> -Date: Thu Jul 5 19:32:07 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various B* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 498ff9a228485bd4b9f23d066bada268f9add1dd -Author: Jon Loeliger <jdl@freescale.com> -Date: Thu Jul 5 19:13:52 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various A* named board config files. - - Since ADS860.h includes "board/fads/fads.h" with ramifications - on the CONFIG_COMMAND treatment, it too has to be adjusted to - exclude already configured commands in this same commit. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 6b0a174a1e6f55e1f5a1fbb223cdad7645a4646e -Author: Stefan Roese <sr@denx.de> -Date: Fri Jul 6 09:45:47 2007 +0200 - - Fix problem with get/setdcr commands introduced by cfg patches - - Signed-off-by: Stefan Roese <sr@denx.de> - commit f1152f8c28db4a22087c21c618a3f7baa48e9a4f Author: Wolfgang Denk <wd@denx.de> Date: Fri Jul 6 02:50:19 2007 +0200 @@ -811,220 +119,6 @@ Date: Fri Jul 6 02:50:19 2007 +0200 Signed-off-by: Wolfgang Denk <wd@denx.de> -commit e4dbe1b215f5c6c462e76909d240bd96472b84de -Author: Wolfgang Denk <wd@denx.de> -Date: Thu Jul 5 17:56:27 2007 +0200 - - Fixing some typos etc. introduced mainly by cfg patches. - - Signed-off-by: Wolfgang Denk <wd@denx.de> - -commit b6b4684546809f89c8bac72863ca49b5fd8ac0cd -Author: Wolfgang Denk <wd@denx.de> -Date: Thu Jul 5 11:12:16 2007 +0200 - - Minor coding style cleanup. Update CHANGELOG. - -commit dca3b3d6d6396b67e5e84af53452164923c73443 -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:33:46 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various [v-z]* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 6c18eb9804b525f3e4f3bb3d014dd69a200d9fa7 -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:33:38 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various t* and u* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 46da1e96b7db14f4fcd2c92544e7c0862024bc76 -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:33:30 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various s* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 90cc3eb6d2be856d9ddd81436de9cf343bc6b5c8 -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:33:23 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various q* and r* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 26a34560d56a9df5bc2ae23525d9229736134757 -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:33:17 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various p* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit a5cb23092a7d31490a33d4ec871468b63babfa3c -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:33:13 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various o* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 929a2bfd142737003a8fc32e1b86e1f2c1850257 -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:33:07 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various n* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 5dc11a511960d490f7f01ffd746edfe6277f99b0 -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:33:01 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various m* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 9bbb1c0820c1fbd3811ab6ee4ba0f6c6f76b27e4 -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:32:57 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various l* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit bc234c129fa04fb9fa33530930e5cbc6084cd47a -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:32:51 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various j* and k* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 1d2c6bc491969f8d8fb34c8e30e8bea7a2af9c31 -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:32:32 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various i* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 48d5d102a2f2e619c92050b9aedbb69689185bc0 -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:32:25 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various h* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 72eb0efaed7048afcc61fc6f0085c49394b5dc36 -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:32:19 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various g* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 1bec3d3002d3bbbae6f2468a0f7376db1120d33e -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:32:10 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various e* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit ab999ba1b31ebe78dd16374394a55d7c6e5aa6e4 -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:32:03 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various d* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 37e4f24b87fa255ae456d193b7cd23c18dd1d56b -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:31:56 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various c* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit ba2351f9d1e841bd00ea6dad1e3c16d0259ad264 -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:31:49 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various b* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 0b361c916617aff79e647b40f0e43361e0bbaccf -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:31:42 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various a* named board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit b730cda82e362df6a22f4c59c0a9b97e885b1014 -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:31:35 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in mpc5xx board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit d794cfefead5fc177cf4f41164e80382e9c9484a -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:31:15 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various 5200 board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit ef0df52ab49eea4a30c15087fd27d54c1d946f2c -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:31:07 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in STx board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 866e3089bfc826bb4dc74637f8aad87a3bab79fc -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:30:58 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in sbc* board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 2694690e285acaa34922f55f4b5ae030da60c55a -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:30:50 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in TQM board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 1cc4c458329765b58e584a19821e796b3c10e976 -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:30:28 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in 82xx board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 8ea5499afdaba0acf60923dd99001c399d4a7c8e -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jul 4 22:30:06 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in 83xx board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - commit b44896215a09c60fa40cae906f7ed207bbc2c492 Author: Sergei Poselenov <sposelenov@emcraft.com> Date: Thu Jul 5 08:17:37 2007 +0200 @@ -1033,40 +127,6 @@ Date: Thu Jul 5 08:17:37 2007 +0200 Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> -commit b24629fa377214d63bb40d1360e354b6d3e4af56 -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jun 13 13:23:15 2007 -0500 - - mpc86xx: Remove old CFG_CMD_* references. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 46175d9764da129bb4fd341cd2554dc7d55f5b2a -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jun 13 13:22:54 2007 -0500 - - Add MPC8568MDS to MAKEALL 85xx target. - - It was missing from the original port submission. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 2835e518c969e5124ba1174eef3e8375e12fa7d5 -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jun 13 13:22:08 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in 85xx board config files. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 56b304ac2091689506088a9ae67f63fd6300cf16 -Author: Jon Loeliger <jdl@jdl.com> -Date: Wed Jun 13 13:21:37 2007 -0500 - - Fix #if typo in CONFIG_CMD_* changes. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - commit f780b83316d9af1f61d71cc88b1917b387b9b995 Author: Niklaus Giger <niklausgiger@gmx.ch> Date: Wed Jun 27 18:11:38 2007 +0200 @@ -1089,548 +149,6 @@ Date: Wed Jul 4 10:06:30 2007 +0200 Signed-off-by: Stefan Roese <sr@denx.de> -commit 6810a34677dbc446334f5e451f1682426dd33b49 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:17:28 2007 -0600 - - Fix Makefile to use $(MKCONFIG) macro for all board ports - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit 90b1b2d69b9396ff2f01165ebc16c9a594eb5926 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:17:28 2007 -0600 - - Fix Makefile to use $(MKCONFIG) macro for all board ports - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit 057004f4a4863554d56cc56268bfa7c7d9738e27 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:34:49 2007 -0600 - - Correct fixup relocation for mpc83xx - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit 5af61b2f4b838a05f79be274f3e5a66edd2d9c96 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:34:44 2007 -0600 - - Correct fixup relocation for mpc8260 - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit f3a52fe05923935db86985daf9438e2f70ac39aa -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:34:39 2007 -0600 - - Correct fixup relocation for mpc824x - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit a85dd254c0577fca13627c46e93fc2ad4c4f1f00 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:34:34 2007 -0600 - - Correct fixup relocation for mpc8220 - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit 6f7576b20ecf0d040c3ac3b032b5cbc860e38a90 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:34:29 2007 -0600 - - Correct fixup relocation for MPC5xxx - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit 3649cd99ba815b6601868735765602f00ef3692b -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:34:24 2007 -0600 - - Correct relocation fixup for mpc5xx - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit f82b3b6304b620ef7e28bfaa1ea887a2ad2fa325 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:34:19 2007 -0600 - - Don't set gd->reloc_off if relocation of .fixup works correctly - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit e1a6144c32dc7de73bcdd33995de0148cbd0bd28 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:34:14 2007 -0600 - - Remove obsolete mpc83xx linker scripts - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit 17e32fc3908bf7089d3f16fc82a1c3ae674dd65b -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:34:09 2007 -0600 - - Consolidate mpc8260 linker scripts - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit af7d38b393690d7eeaf418ac85a1e831a50d5fd0 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:34:04 2007 -0600 - - Remove obsolete mpc824x linker scripts - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit f94a3aecebc40ca0939c7d66d010009cf51be9e2 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:33:59 2007 -0600 - - Remove obsolete mpc824x linker scripts (3 of 4) - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit a71c084f3ac7fedf144537db2b2da47323068833 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:33:53 2007 -0600 - - Remove obsolete mpc824x linker scripts (2 of 4) - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit f670a15468d1365241d40022b9408e1004181f5e -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:33:48 2007 -0600 - - Remove obsolete mpc824x linker scripts (1 of 4) - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit 09555bd45a04c0e54f172528d21bc18896550d28 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:33:43 2007 -0600 - - Remove obsolete mpc8220 linker scripts - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit 5efb992f046e51225c93d52f80fecbe433abd789 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:33:38 2007 -0600 - - Remove obsolete mpc5xxx linker scripts (3 of 3) - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit 07c13dfef65b31647e69d8b61daa1eec598add1a -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:33:33 2007 -0600 - - Remove obsolete mpc5xxx linker scripts (2 of 3) - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit b4f67513a624ce85866c66c575bd2d9d7977d7f0 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:33:28 2007 -0600 - - Remove obsolete mpc5xxx linker scripts (1 of 3) - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit b7d8e05f8675249b5f208aa73babeed384a4519d -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:33:23 2007 -0600 - - Remove obsolete mpc5xx linker scripts - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit 416a0b6d40f6eba3a2fc547253c16bda28d922f7 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:33:18 2007 -0600 - - Consolidate mpc83xx linker scripts - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit 5fc59175b92883ed5d2666a04e6bc49e70a4a365 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:33:13 2007 -0600 - - Consolidate mpc8260 linker scripts - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit 737f9eb02d7335df2b3e4d7a4d3348784d1da207 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:33:08 2007 -0600 - - Consolidate mpc824x linker scripts - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit 9c757b789a59a855db57b448dd825329c4e9c4a0 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:33:03 2007 -0600 - - Consolidate mpc8220 linker scripts - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit d181c9a15cd41863fe24840d17848429f27d3c8c -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:32:58 2007 -0600 - - Consolidate mpc5xxx linker scripts - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit 287ac924adb7291bebe5086652a362a30ab28b13 -Author: Grant Likely <grant.likely@secretlab.ca> -Date: Tue Jul 3 00:32:53 2007 -0600 - - Consolidate mpc5xx linker scripts - - Signed-off-by: Grant Likely <grant.likely@secretlab.ca> - -commit 52b8704d0245e589f86d462e9ec25aeb7ecbbbdd -Author: Wolfgang Denk <wd@denx.de> -Date: Wed Jul 4 00:43:53 2007 +0200 - - Fix a few file permission problems. - - Signed-off-by: Wolfgang Denk <wd@denx.de> - -commit 78e0cf2de7be7f1eaeeb622eb61fd50e4d5e205c -Author: Wolfgang Denk <wd@denx.de> -Date: Wed Jul 4 00:38:38 2007 +0200 - - Minor coding style cleanup. Rebuild CHANGELOG file. - -commit 2f9c19e496acb6bb50d9299e1aab377625d48c38 -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:03:44 2007 -0500 - - configs/ mpc86xx: Rewrite command line options using new CONFIG_CMD-* style. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 602ad3b33d9ceef83dbab46be68646d645d637ee -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:03:39 2007 -0500 - - README: Rewrite command line config to use CONFIG_CMD_* names. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 72a074cec68e5bad60d63206c050974e08afd804 -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:03:34 2007 -0500 - - include/ non-config: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 5fcf543e0b6628c76ff48705b1b0566bfd11507b -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:03:28 2007 -0500 - - tools/ : Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 9107ebe0d352420895ab69b715697bdebc8caf50 -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:03:23 2007 -0500 - - board/[k-z]*: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 5e378003d592ea828ec69d6defcd4de79096dd5c -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:03:19 2007 -0500 - - board/[Ma-i]*: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 737184114ec9c9e0ab94d6713536126073bd2472 -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:03:15 2007 -0500 - - cpu/ non-mpc*: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit f48070fe5fe440dfb5ee5268c920de70e48ea327 -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:03:08 2007 -0500 - - cpu/mpc*/ : Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 0c505db0a0dc1f670b13ce3b4d3fbf1ec5b3cbd2 -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:03:03 2007 -0500 - - lib_*/: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 73f032021ec5f13cda8faa4e34b6de80960eb86f -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:02:58 2007 -0500 - - lib_ppc/: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 98b79003c21c2578206003256de4e781d6b36ca8 -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:02:53 2007 -0500 - - rtc/: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 6e2115acb6a892d53a6881bf253ae41d3df39156 -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:02:49 2007 -0500 - - net/: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 45cdb9b72c94655c7308b464a2666057c0b286e0 -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:02:34 2007 -0500 - - disk/: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 4e109ae98294a5ca7ff848b7652c7bfd4023a94a -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:02:20 2007 -0500 - - fs/: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit d5be43de93ff905c465e509d45a3164ef48d26e7 -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:02:10 2007 -0500 - - drivers/: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit b453960d4fdb87b3970d96119b90df2ed024fc4a -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:02:05 2007 -0500 - - common/ non-cmd: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit 65c450b47a62659d522cfa8f4fa1e4e5c60dccd0 -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:01:54 2007 -0500 - - common/cmd_[i-z]* : Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit a76adc8142c1d956385a109e0b70f9319ede4d66 -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:01:43 2007 -0500 - - common/cmd_[a-f]* : Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - -commit ec63b10b61fd68238d4c15c1cd04c0b38228e2c1 -Author: Jon Loeliger <jdl@jdl.com> -Date: Mon Jun 11 19:01:34 2007 -0500 - - Introduce initial versions of new Command Config files. - - Derive three new files from cmd_confdefs.h: - config_bootp.h - Has BOOTP related config options, not commands - config_cmd_all.h - Has a CONFIG_CMD_* definition for every command - config_cmd_default.h - Has a CONFIG_CMD_* definition for default cmds. - - For now, include "config_bootp.h" for compatability until all - users of it directly include it properly. - - Signed-off-by: Jon Loeliger <jdl@freescale.com> - commit 1f2a05898658900dc5717761e27abf2052e67e13 Author: Mushtaq Khan <mushtaqk_921@yahoo.co.in> Date: Sat Jun 30 18:50:48 2007 +0200 @@ -2694,7 +1212,7 @@ Date: Sat May 5 08:12:30 2007 +0200 5xxx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -2836,7 +1354,7 @@ Date: Sat May 5 08:12:30 2007 +0200 5xxx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -2967,7 +1485,7 @@ Date: Mon Apr 30 13:59:50 2007 -0500 Fix memory initialization on MPC8349E-mITX Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP. - This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary + This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary on some ITX boards, notably those with a revision 3.1 CPU. Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into @@ -3124,7 +1642,7 @@ Date: Mon Feb 12 13:34:55 2007 -0600 85xx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -3433,7 +1951,7 @@ Date: Fri Apr 20 14:12:26 2007 -0500 mpc86xx; Write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -3486,7 +2004,7 @@ Date: Thu Apr 19 23:14:39 2007 -0400 What was suppose to be a stack variable was declared as a pointer, overwriting random memory. - Also moved the libfdt.a requirement into the main Makefile. That is + Also moved the libfdt.a requirement into the main Makefile. That is The U-Boot Way. commit d21686263574e95cb3e9e9b0496f968b1b897fdb @@ -4081,7 +2599,7 @@ Date: Sat Mar 31 12:22:10 2007 -0400 Add a flattened device tree (fdt) command (1 of 2) The fdt command uses David Gibson's libfdt library to manipulate as well - as print the flattened device tree. This patch is the new command, + as print the flattened device tree. This patch is the new command, the second part is the modifications to the existing code. commit 3af0d587d93e0be5f96e1b30fa41e662f8b0803e @@ -4782,7 +3300,7 @@ Date: Tue Feb 13 10:41:42 2007 -0600 mpc83xx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, this patch + and some have both. To support all of these device trees, this patch updates ftp_cpu_setup() to write the MAC address to mac-address if it exists. This function already updates local-mac-address. @@ -5005,7 +3523,7 @@ Date: Wed Dec 6 21:23:55 2006 -0500 mpc83xx: Put the version (and magic) after the HRCW. - Put the version (and magic) after the HRCW. This puts it in a fixed + Put the version (and magic) after the HRCW. This puts it in a fixed location in flash, not at the start of flash but as close as we can get. Signed-off-by: Jerry Van Baren <vanbaren@cideas.com> @@ -5299,7 +3817,7 @@ Date: Tue Feb 20 09:05:31 2007 +0100 [PATCH 7_9] Replace ace_readw_ace_writeb functions with macros - Register read/write does not need to be wrapped in a full function. The + Register read/write does not need to be wrapped in a full function. The patch replaces them with macros. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> @@ -5602,7 +4120,7 @@ commit fdef388758506765d4d6a7155c8f1584c63ff581 Author: roy zang <tie-fei.zang@freescale.com> Date: Mon Jan 22 13:19:21 2007 +0800 - use CFG_WRITE_SWAPPED_DATA define instead of define CFG_FLASH_CFI_SWAP + use CFG_WRITE_SWAPPED_DATA define instead of define CFG_FLASH_CFI_SWAP The patch by Heiko Schocher <hs@pollux.denx.de> on Jan, 19, 2007 fixes cfi_driver bug for mpc7448hpc2 board. The default cfi_driver can support mpc7448hpc2 board. @@ -6290,7 +4808,7 @@ Date: Mon Nov 27 17:04:06 2006 +0100 [PATCH] Allow CONFIG_OF_FLAT_TREE to boot a non-arch/powerpc kernel This patch allows an arch/ppc kernel to be booted by just passing 1 or 2 - arguments to bootm. It removes the getenv("disable_of") test that used + arguments to bootm. It removes the getenv("disable_of") test that used to be used for this purpose. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> @@ -6866,7 +5384,7 @@ Date: Thu Nov 2 19:08:55 2006 +0800 Gigabit Ethernet ports,E0 and E1. It uses a single Management interface to manage the two physical connection devices (PHYs). Each Ethernet port has its own statistics monitor that tracks and reports key interface - statistics. Each port supports a 256-entry hash table for address + statistics. Each port supports a 256-entry hash table for address filtering. In addition, each port is bridged to the Switch Fabric through a 2-Kbyte transmit FIFO and a 4-Kbyte Receive FIFO. @@ -6912,7 +5430,7 @@ commit 87c4db09699c6b89176b31004afcb83eb1585d47 Author: roy zang <tie-fei.zang@freescale.com> Date: Thu Nov 2 18:59:15 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. mpc7448hpc2 board support high level code:tsi108 init + mpc7448hpc2. Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> @@ -6922,7 +5440,7 @@ commit 27801b8ab11c61b577e45742a515bb3b23b80241 Author: roy zang <tie-fei.zang@freescale.com> Date: Thu Nov 2 18:57:21 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. Make ,config.mk and link file for the mpc7448hpc2 board. Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> @@ -6932,7 +5450,7 @@ commit c6411c0c3bbc79f9ba8aef58296a42d8f9d8a0a6 Author: roy zang <tie-fei.zang@freescale.com> Date: Thu Nov 2 18:55:04 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. The mpc7448hpc2 board support header file. Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> @@ -6942,7 +5460,7 @@ commit 625bb5ddb50b243f931262ca8c46956409471917 Author: roy zang <tie-fei.zang@freescale.com> Date: Thu Nov 2 18:52:21 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. The mpc7448hpc2 board support low level assemble language init code. Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> @@ -7167,7 +5685,7 @@ Date: Tue Oct 24 23:47:37 2006 -0500 If a Multi-Image file contains a third image we try to use it as a device tree. The device tree image is assumed to be uncompressed in the - image file. We automatically allocate space for the device tree in memory + image file. We automatically allocate space for the device tree in memory and provide an 8k pad to allow more than a reasonable amount of growth. Additionally, a device tree that was contained in flash will now automatically @@ -35,12 +35,20 @@ LIST_5xx=" \ ######################################################################### LIST_5xxx=" \ - BC3450 cpci5200 EVAL5200 fo300 \ - icecube_5100 icecube_5200 lite5200b mcc200 \ - mecp5200 motionpro o2dnt pf5200 \ - PM520 TB5200 Total5100 Total5200 \ - Total5200_Rev2 TQM5200 TQM5200_B TQM5200S \ - v38b \ + BC3450 cm1_qp1 cpci5200 EVAL5200 \ + fo300 icecube_5100 icecube_5200 lite5200b \ + mcc200 mecp5200 motionpro o2dnt \ + pf5200 PM520 TB5200 Total5100 \ + Total5200 Total5200_Rev2 TQM5200 TQM5200_B \ + TQM5200S v38b \ +" + +######################################################################### +## MPC512x Systems +######################################################################### + +LIST_512x=" \ + ads5121 \ " ######################################################################### @@ -366,7 +374,7 @@ do microblaze| \ mips|mips_el| \ nios|nios2| \ - ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \ + ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \ x86|I486) for target in `eval echo '$LIST_'${arg}` do @@ -268,7 +268,7 @@ $(obj)u-boot.img: $(obj)u-boot.bin -d $< $@ $(obj)u-boot.sha1: $(obj)u-boot.bin - ./tools/ubsha1 $(obj)u-boot.bin + $(obj)tools/ubsha1 $(obj)u-boot.bin $(obj)u-boot.dis: $(obj)u-boot $(OBJDUMP) -d $< > $@ @@ -532,6 +532,14 @@ PM520_ROMBOOT_DDR_config: unconfig smmaco4_config: unconfig @$(MKCONFIG) -a smmaco4 ppc mpc5xxx tqm5200 +cm1_qp1_config: unconfig + @ >include/config.h + @[ -z "$(findstring cm1_qp1,$@)" ] || \ + { echo "... with 64 MByte SDRAM" ; \ + echo "... with 32 MByte Flash" ; \ + } + @./mkconfig -a cm1_qp1 ppc mpc5xxx cm1_qp1 + spieval_config: unconfig @$(MKCONFIG) -a spieval ppc mpc5xxx tqm5200 @@ -634,6 +642,13 @@ motionpro_config: unconfig ######################################################################### +## MPC512x Systems +######################################################################### +ads5121_config: unconfig + @$(MKCONFIG) ads5121 ppc mpc512x ads5121 + + +######################################################################### ## MPC8xx Systems ######################################################################### diff --git a/board/ads5121/Makefile b/board/ads5121/Makefile new file mode 100644 index 0000000..cd8148c --- /dev/null +++ b/board/ads5121/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c new file mode 100644 index 0000000..c8bfdb8 --- /dev/null +++ b/board/ads5121/ads5121.c @@ -0,0 +1,188 @@ +/* + * (C) Copyright 2007 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <mpc512x.h> +#include <asm/bitops.h> +#include <command.h> + +/* Clocks in use */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC_EN) + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_SPDIF_EN | \ + CLOCK_SCCR2_I2C_EN) + +#define CSAW_START(start) ((start) & 0xFFFF0000) +#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) + +long int fixed_sdram(void); + +int board_early_init_f (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 lpcaw; + + /* + * Initialize Local Window for the CPLD registers access (CS2 selects + * the CPLD chip) + */ + im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) | + CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE); + im->lpc.cs_cfg[2] = CFG_CS2_CFG; + + /* + * According to MPC5121e RM, configuring local access windows should + * be followed by a dummy read of the config register that was + * modified last and an isync + */ + lpcaw = im->sysconf.lpcs2aw; + __asm__ __volatile__ ("isync"); + + /* + * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control + * + * Without this the flash identification routine fails, as it needs to issue + * write commands in order to establish the device ID. + */ + *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1; + + /* + * Enable clocks + */ + im->clk.sccr[0] = SCCR1_CLOCKS_EN; + im->clk.sccr[1] = SCCR2_CLOCKS_EN; + + return 0; +} + +long int initdram (int board_type) +{ + u32 msize = 0; + + puts ("Initializing\n"); + msize = fixed_sdram (); + puts (" DDR RAM: "); + + return msize; +} + +/* + * fixed sdram init -- the board doesn't use memory modules that have serial presence + * detect or similar mechanism for discovery of the DRAM settings + */ +long int fixed_sdram (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = CFG_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2 (msize); + u32 i; + + /* Initialize IO Control */ + im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR; + + /* Initialize DDR Local Window */ + im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000; + im->sysconf.ddrlaw.ar = msize_log2 - 1; + + /* + * According to MPC5121e RM, configuring local access windows should + * be followed by a dummy read of the config register that was + * modified last and an isync + */ + i = im->sysconf.ddrlaw.ar; + __asm__ __volatile__ ("isync"); + + /* Enable DDR */ + im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN; + + /* Initialize DDR Priority Manager */ + im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1; + im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2; + im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG; + im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU; + im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU; + im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU; + im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU; + im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU; + im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML; + im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML; + im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML; + im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML; + im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML; + im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU; + im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU; + im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU; + im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU; + im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU; + im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AU; + im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL; + im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL; + im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL; + im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL; + + /* Initialize MDDRC */ + im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG; + im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0; + im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1; + im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2; + + /* Initialize DDR */ + for (i = 0; i < 10; i++) + im->mddrc.ddr_command = CFG_MICRON_NOP; + + im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; + im->mddrc.ddr_command = CFG_MICRON_EM2; + im->mddrc.ddr_command = CFG_MICRON_EM3; + im->mddrc.ddr_command = CFG_MICRON_EN_DLL; + im->mddrc.ddr_command = CFG_MICRON_RST_DLL; + im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; + im->mddrc.ddr_command = CFG_MICRON_RFSH; + im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT; + im->mddrc.ddr_command = CFG_MICRON_OCD_EXIT; + + for (i = 0; i < 10; i++) + im->mddrc.ddr_command = CFG_MICRON_NOP; + + /* Start MDDRC */ + im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN; + im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN; + + return msize; +} + +int checkboard (void) +{ + ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00); + uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02); + + printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n", + brd_rev, cpld_rev); + return 0; +} diff --git a/board/ads5121/config.mk b/board/ads5121/config.mk new file mode 100644 index 0000000..14998f4 --- /dev/null +++ b/board/ads5121/config.mk @@ -0,0 +1,23 @@ +# +# (C) Copyright 2007 DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFF00000 diff --git a/board/ads5121/u-boot.lds b/board/ads5121/u-boot.lds new file mode 100644 index 0000000..038d849 --- /dev/null +++ b/board/ads5121/u-boot.lds @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2007 DENX Software Engineering. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc512x/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/cm1_qp1/Makefile b/board/cm1_qp1/Makefile new file mode 100644 index 0000000..e739326 --- /dev/null +++ b/board/cm1_qp1/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2003-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o cmd_cm1_qp1.o fwupdate.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/cm1_qp1/cm1_qp1.c b/board/cm1_qp1/cm1_qp1.c new file mode 100644 index 0000000..b49298f --- /dev/null +++ b/board/cm1_qp1/cm1_qp1.c @@ -0,0 +1,222 @@ +/* + * (C) Copyright 2003-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2004-2005 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc5xxx.h> +#include <pci.h> +#include <asm/processor.h> +#include <i2c.h> +#ifdef CONFIG_OF_FLAT_TREE +#include <ft_build.h> +#endif /* CONFIG_OF_FLAT_TREE */ + +#include "fwupdate.h" + +#ifndef CFG_RAMBOOT +/* + * Helper function to initialize SDRAM controller. + */ +static void sdram_start(int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | + hi_addr_bit; + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | + hi_addr_bit; + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | + hi_addr_bit; + + /* auto refresh, second time */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | + hi_addr_bit; + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; +} +#endif /* CFG_RAMBOOT */ + +/* + * Initalize SDRAM - configure SDRAM controller, detect memory size. + */ +long int initdram(int board_type) +{ + ulong dramsize = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* configure SDRAM start/end for detection */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + + sdram_start(0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else + dramsize = test2; + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) + dramsize = 0; + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + + __builtin_ffs(dramsize >> 20) - 1; + } else + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ +#else /* CFG_RAMBOOT */ + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) + dramsize = (1 << (dramsize - 0x13)) << 20; + else + dramsize = 0; +#endif /* CFG_RAMBOOT */ + + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of + * the MPC5200B User's Manual. + */ + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + + return dramsize; +} + + +int checkboard(void) +{ + puts("Board: CM1.QP1\n"); + return 0; +} + + +int board_early_init_r(void) +{ + /* + * Now, when we are in RAM, enable flash write access for detection + * process. Note that CS_BOOT cannot be cleared when executing in + * flash. + */ + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ + return 0; +} + + +#ifdef CONFIG_POST +int post_hotkeys_pressed(void) +{ + return 0; +} +#endif /* CONFIG_POST */ + + +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) +void post_word_store(ulong a) +{ + vu_long *save_addr = (vu_long *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); + *save_addr = a; +} + + +ulong post_word_load(void) +{ + vu_long *save_addr = (vu_long *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); + return *save_addr; +} +#endif /* CONFIG_POST || CONFIG_LOGBUFFER */ + + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) + uchar buf[6]; + char str[18]; + + /* Read ethaddr from EEPROM */ + if (i2c_read(CFG_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) { + sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); + /* Check if MAC addr is owned by Schindler */ + if (strstr(str, "00:06:C3") != str) { + printf(LOG_PREFIX "Warning - Illegal MAC address (%s)" + " in EEPROM.\n", str); + printf(LOG_PREFIX "Using MAC from environment\n"); + } else { + printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n", + str); + setenv("ethaddr", str); + } + } else { + printf(LOG_PREFIX "Warning - Unable to read MAC from I2C" + " device at address %02X:%04X\n", CFG_I2C_EEPROM, + CONFIG_MAC_OFFSET); + printf(LOG_PREFIX "Using MAC from environment\n"); + } + return 0; +#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) */ +} +#endif /* CONFIG_MISC_INIT_R */ + + +#ifdef CONFIG_LAST_STAGE_INIT +int last_stage_init(void) +{ +#ifdef CONFIG_USB_STORAGE + cm1_fwupdate(); +#endif /* CONFIG_USB_STORAGE */ + return 0; +} +#endif /* CONFIG_LAST_STAGE_INIT */ + + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/cm1_qp1/cmd_cm1_qp1.c b/board/cm1_qp1/cmd_cm1_qp1.c new file mode 100644 index 0000000..4a01d2a --- /dev/null +++ b/board/cm1_qp1/cmd_cm1_qp1.c @@ -0,0 +1,446 @@ +/* + * (C) Copyright 2007 Markus Kappeler <markus.kappeler@objectxp.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> +#include <usb.h> + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +int do_i2c(char *argv[]) +{ + unsigned char temp, temp1; + + printf("Starting I2C Test\n" + "Please set Jumper:\nI2C SDA 2-3\nI2C SCL 2-3\n\n" + "Please press any key to start\n\n"); + getc(); + + temp = 0xf0; /* set io 0-4 as output */ + i2c_write(CFG_I2C_IO, 3, 1, (uchar *)&temp, 1); + + printf("Press I2C4-7. LED I2C0-3 should have the same state\n\n" + "Press any key to stop\n\n"); + + while (!tstc()) { + i2c_read(CFG_I2C_IO, 0, 1, (uchar *)&temp, 1); + temp1 = (temp >> 4) & 0x03; + temp1 |= (temp >> 3) & 0x08; /* S302 -> LED303 */ + temp1 |= (temp >> 5) & 0x04; /* S303 -> LED302 */ + temp = temp1; + i2c_write(CFG_I2C_IO, 1, 1, (uchar *)&temp, 1); + } + getc(); + + return 0; +} + +int do_usbtest(char *argv[]) +{ + int i; + static int usb_stor_curr_dev = -1; /* current device */ + + printf("Starting USB Test\n" + "Please insert USB Memmory Stick\n\n" + "Please press any key to start\n\n"); + getc(); + + usb_stop(); + printf("(Re)start USB...\n"); + i = usb_init(); +#ifdef CONFIG_USB_STORAGE + /* try to recognize storage devices immediately */ + if (i >= 0) + usb_stor_curr_dev = usb_stor_scan(1); +#endif /* CONFIG_USB_STORAGE */ + if (usb_stor_curr_dev >= 0) + printf("Found USB Storage Dev continue with Test...\n"); + else { + printf("No USB Storage Device detected.. Stop Test\n"); + return 1; + } + + usb_stor_info(); + + printf("stopping USB..\n"); + usb_stop(); + + return 0; +} + +int do_led(char *argv[]) +{ + int i = 0; + struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + + printf("Starting LED Test\n" + "Please set Switch S500 all off\n\n" + "Please press any key to start\n\n"); + getc(); + + /* configure timer 2-3 for simple GPIO output High */ + gpt->gpt2.emsr |= 0x00000034; + gpt->gpt3.emsr |= 0x00000034; + + (*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x80000000; + (*(vu_long *)MPC5XXX_WU_GPIO_DIR) |= 0x80000000; + printf("Please press any key to stop\n\n"); + while (!tstc()) { + if (i == 1) { + (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000; + gpt->gpt2.emsr &= ~0x00000010; + gpt->gpt3.emsr &= ~0x00000010; + } else if (i == 2) { + (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000; + gpt->gpt2.emsr &= ~0x00000010; + gpt->gpt3.emsr |= 0x00000010; + } else if (i >= 3) { + (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000; + gpt->gpt3.emsr &= ~0x00000010; + gpt->gpt2.emsr |= 0x00000010; + i = 0; + } + i++; + udelay(200000); + } + getc(); + + (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000; + gpt->gpt2.emsr |= 0x00000010; + gpt->gpt3.emsr |= 0x00000010; + + return 0; +} + +int do_rs232(char *argv[]) +{ + int error_status = 0; + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1; + + /* Configure PSC 2-3-6 as GPIO */ + gpio->port_config &= 0xFF0FF80F; + + switch (simple_strtoul(argv[2], NULL, 10)) { + case 1: + /* check RTS <-> CTS loop */ + /* set rts to 0 */ + printf("Uart 1 test: RX TX tested by using U-Boot\n" + "Please connect RTS with CTS on Uart1 plug\n\n" + "Press any key to start\n\n"); + getc(); + + psc1->op1 |= 0x01; + + /* wait some time before requesting status */ + udelay(10); + + /* check status at cts */ + if ((psc1->ip & 0x01) != 0) { + error_status = 3; + printf("%s: failure at rs232_1, cts status is %d " + "(should be 0)\n", + __FUNCTION__, (psc1->ip & 0x01)); + } + + /* set rts to 1 */ + psc1->op0 |= 0x01; + + /* wait some time before requesting status */ + udelay(10); + + /* check status at cts */ + if ((psc1->ip & 0x01) != 1) { + error_status = 3; + printf("%s: failure at rs232_1, cts status is %d " + "(should be 1)\n", + __FUNCTION__, (psc1->ip & 0x01)); + } + break; + case 2: + /* set PSC2_0, PSC2_2 as output and PSC2_1, PSC2_3 as input */ + printf("Uart 2 test: Please use RS232 Loopback plug on UART2\n" + "\nPress any key to start\n\n"); + getc(); + + gpio->simple_gpioe &= ~(0x000000F0); + gpio->simple_gpioe |= 0x000000F0; + gpio->simple_ddr &= ~(0x000000F0); + gpio->simple_ddr |= 0x00000050; + + /* check TXD <-> RXD loop */ + /* set TXD to 1 */ + gpio->simple_dvo |= (1 << 4); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000020) != 0x00000020) { + error_status = 2; + printf("%s: failure at rs232_2, rxd status is %d " + "(should be 1)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000020) >> 5); + } + + /* set TXD to 0 */ + gpio->simple_dvo &= ~(1 << 4); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000020) != 0x00000000) { + error_status = 2; + printf("%s: failure at rs232_2, rxd status is %d " + "(should be 0)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000020) >> 5); + } + + /* check RTS <-> CTS loop */ + /* set RTS to 1 */ + gpio->simple_dvo |= (1 << 6); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000080) != 0x00000080) { + error_status = 3; + printf("%s: failure at rs232_2, cts status is %d " + "(should be 1)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000080) >> 7); + } + + /* set RTS to 0 */ + gpio->simple_dvo &= ~(1 << 6); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000080) != 0x00000000) { + error_status = 3; + printf("%s: failure at rs232_2, cts status is %d " + "(should be 0)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000080) >> 7); + } + break; + case 3: + /* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */ + printf("Uart 3 test: Please use RS232 Loopback plug on UART2\n" + "\nPress any key to start\n\n"); + getc(); + + gpio->simple_gpioe &= ~(0x00000F00); + gpio->simple_gpioe |= 0x00000F00; + + gpio->simple_ddr &= ~(0x00000F00); + gpio->simple_ddr |= 0x00000500; + + /* check TXD <-> RXD loop */ + /* set TXD to 1 */ + gpio->simple_dvo |= (1 << 8); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000200) != 0x00000200) { + error_status = 2; + printf("%s: failure at rs232_3, rxd status is %d " + "(should be 1)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000200) >> 9); + } + + /* set TXD to 0 */ + gpio->simple_dvo &= ~(1 << 8); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000200) != 0x00000000) { + error_status = 2; + printf("%s: failure at rs232_3, rxd status is %d " + "(should be 0)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000200) >> 9); + } + + /* check RTS <-> CTS loop */ + /* set RTS to 1 */ + gpio->simple_dvo |= (1 << 10); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000800) != 0x00000800) { + error_status = 3; + printf("%s: failure at rs232_3, cts status is %d " + "(should be 1)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000800) >> 11); + } + + /* set RTS to 0 */ + gpio->simple_dvo &= ~(1 << 10); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000800) != 0x00000000) { + error_status = 3; + printf("%s: failure at rs232_3, cts status is %d " + "(should be 0)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000800) >> 11); + } + break; + case 4: + /* set PSC6_2, PSC6_3 as output and PSC6_0, PSC6_1 as input */ + printf("Uart 4 test: Please use RS232 Loopback plug on UART2\n" + "\nPress any key to start\n\n"); + getc(); + + gpio->simple_gpioe &= ~(0xF0000000); + gpio->simple_gpioe |= 0x30000000; + + gpio->simple_ddr &= ~(0xf0000000); + gpio->simple_ddr |= 0x30000000; + + (*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x30000000; + (*(vu_long *)MPC5XXX_WU_GPIO_DIR) &= ~(0x30000000); + + /* check TXD <-> RXD loop */ + /* set TXD to 1 */ + gpio->simple_dvo |= (1 << 28); + + /* wait some time before requesting status */ + udelay(10); + + if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) != + 0x10000000) { + error_status = 2; + printf("%s: failure at rs232_4, rxd status is %d " + "(should be 1)\n", __FUNCTION__, + ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & + 0x10000000) >> 28); + } + + /* set TXD to 0 */ + gpio->simple_dvo &= ~(1 << 28); + + /* wait some time before requesting status */ + udelay(10); + + if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) != + 0x00000000) { + error_status = 2; + printf("%s: failure at rs232_4, rxd status is %d " + "(should be 0)\n", __FUNCTION__, + ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & + 0x10000000) >> 28); + } + + /* check RTS <-> CTS loop */ + /* set RTS to 1 */ + gpio->simple_dvo |= (1 << 29); + + /* wait some time before requesting status */ + udelay(10); + + if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) != + 0x20000000) { + error_status = 3; + printf("%s: failure at rs232_4, cts status is %d " + "(should be 1)\n", __FUNCTION__, + ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & + 0x20000000) >> 29); + } + + /* set RTS to 0 */ + gpio->simple_dvo &= ~(1 << 29); + + /* wait some time before requesting status */ + udelay(10); + + if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) != + 0x00000000) { + error_status = 3; + printf("%s: failure at rs232_4, cts status is %d " + "(should be 0)\n", __FUNCTION__, + ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & + 0x20000000) >> 29); + } + break; + default: + printf("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]); + error_status = 1; + break; + } + gpio->port_config |= (CFG_GPS_PORT_CONFIG & 0xFF0FF80F); + + return error_status; +} + +int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode = -1; + + switch (argc) { + case 2: + if (strncmp(argv[1], "i2c", 3) == 0) + rcode = do_i2c(argv); + else if (strncmp(argv[1], "led", 3) == 0) + rcode = do_led(argv); + else if (strncmp(argv[1], "usb", 3) == 0) + rcode = do_usbtest(argv); + break; + case 3: + if (strncmp(argv[1], "rs232", 3) == 0) + rcode = do_rs232(argv); + break; + } + + switch (rcode) { + case -1: + printf("Usage:\n" + "fkt { i2c | led | usb }\n" + "fkt rs232 number\n"); + rcode = 1; + break; + case 0: + printf("Test passed\n"); + break; + default: + printf("Test failed with code: %d\n", rcode); + } + + return rcode; +} + +U_BOOT_CMD( + fkt, 4, 1, cmd_fkt, + "fkt - Function test routines\n", + "i2c\n" + " - Test I2C communication\n" + "fkt led\n" + " - Test LEDs\n" + "fkt rs232 number\n" + " - Test RS232 (loopback plug(s) for RS232 required)\n" + "fkt usb\n" + " - Test USB communication\n" +); +#endif /* CFG_CMD_BSP */ diff --git a/board/cm1_qp1/config.mk b/board/cm1_qp1/config.mk new file mode 100644 index 0000000..7f06139 --- /dev/null +++ b/board/cm1_qp1/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xfc000000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/cm1_qp1/fwupdate.c b/board/cm1_qp1/fwupdate.c new file mode 100644 index 0000000..637375e --- /dev/null +++ b/board/cm1_qp1/fwupdate.c @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2007 Schindler Lift Inc. + * (C) Copyright 2007 Semihalf + * + * Author: Michel Marti <mma@objectxp.com> + * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>: + * - code clean-up + * - bugfix for overwriting bootargs by user + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <image.h> +#include <usb.h> +#include <fat.h> + +#include "fwupdate.h" + +extern int do_bootm(cmd_tbl_t *, int, int, char *[]); +extern long do_fat_read(const char *, void *, unsigned long, int); +extern int do_fat_fsload(cmd_tbl_t *, int, int, char *[]); + +static int load_rescue_image(ulong); + +void cm1_fwupdate(void) +{ + cmd_tbl_t *bcmd; + char *rsargs; + char *tmp = NULL; + char ka[16]; + char *argv[3] = { "bootm", ka, NULL }; + + /* Check if rescue system is disabled... */ + if (getenv("norescue")) { + printf(LOG_PREFIX "Rescue System disabled.\n"); + return; + } + + /* Check if we have a USB storage device and load image */ + if (load_rescue_image(LOAD_ADDR)) + return; + + bcmd = find_cmd("bootm"); + if (!bcmd) + return; + + sprintf(ka, "%lx", LOAD_ADDR); + + /* prepare our bootargs */ + rsargs = getenv("rs-args"); + if (!rsargs) + rsargs = RS_BOOTARGS; + else { + tmp = malloc(strlen(rsargs+1)); + if (!tmp) { + printf(LOG_PREFIX "Memory allocation failed\n"); + return; + } + strcpy(tmp, rsargs); + rsargs = tmp; + } + + setenv("bootargs", rsargs); + + if (rsargs == tmp) + free(rsargs); + + printf(LOG_PREFIX "Starting update system (bootargs=%s)...\n", rsargs); + do_bootm(bcmd, 0, 2, argv); +} + +static int load_rescue_image(ulong addr) +{ + disk_partition_t info; + int devno; + int partno; + int i; + char fwdir[64]; + char nxri[128]; + char *tmp; + char dev[7]; + char addr_str[16]; + char *argv[6] = { "fatload", "usb", dev, addr_str, nxri, NULL }; + block_dev_desc_t *stor_dev = NULL; + cmd_tbl_t *bcmd; + + /* Get name of firmware directory */ + tmp = getenv("fw-dir"); + + /* Copy it into fwdir */ + strncpy(fwdir, tmp ? tmp : FW_DIR, sizeof(fwdir)); + fwdir[sizeof(fwdir) - 1] = 0; /* Terminate string */ + + printf(LOG_PREFIX "Checking for firmware image directory '%s' on USB" + " storage...\n", fwdir); + usb_stop(); + if (usb_init() != 0) + return 1; + + /* Check for storage device */ + if (usb_stor_scan(1) != 0) { + usb_stop(); + return 1; + } + + /* Detect storage device */ + for (devno = 0; devno < USB_MAX_STOR_DEV; devno++) { + stor_dev = usb_stor_get_dev(devno); + if (stor_dev->type != DEV_TYPE_UNKNOWN) + break; + } + if (!stor_dev || stor_dev->type == DEV_TYPE_UNKNOWN) { + printf(LOG_PREFIX "No valid storage device found...\n"); + usb_stop(); + return 1; + } + + /* Detect partition */ + for (partno = -1, i = 0; i < 6; i++) { + if (get_partition_info(stor_dev, i, &info) == 0) { + if (fat_register_device(stor_dev, i) == 0) { + /* Check if rescue image is present */ + FW_DEBUG("Looking for firmware directory '%s'" + " on partition %d\n", fwdir, i); + if (do_fat_read(fwdir, NULL, 0, LS_NO) == -1) { + FW_DEBUG("No NX rescue image on " + "partition %d.\n", i); + } else { + partno = i; + FW_DEBUG("Partition %d contains " + "firmware directory\n", partno); + break; + } + } + } + } + + if (partno == -1) { + printf(LOG_PREFIX "Error: No valid (FAT) partition detected\n"); + usb_stop(); + return 1; + } + + /* Load the rescue image */ + bcmd = find_cmd("fatload"); + if (!bcmd) { + printf(LOG_PREFIX "Error - 'fatload' command not present.\n"); + usb_stop(); + return 1; + } + + tmp = getenv("nx-rescue-image"); + sprintf(nxri, "%s/%s", fwdir, tmp ? tmp : RESCUE_IMAGE); + sprintf(dev, "%d:%d", devno, partno); + sprintf(addr_str, "%lx", addr); + + FW_DEBUG("fat_fsload device='%s', addr='%s', file: %s\n", + dev, addr_str, nxri); + + if (do_fat_fsload(bcmd, 0, 5, argv) != 0) { + usb_stop(); + return 1; + } + + /* Stop USB */ + usb_stop(); + return 0; +} diff --git a/board/cm1_qp1/fwupdate.h b/board/cm1_qp1/fwupdate.h new file mode 100644 index 0000000..119c2d6 --- /dev/null +++ b/board/cm1_qp1/fwupdate.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2007 Schindler Lift Inc. + * + * Author: Michel Marti <mma@objectxp.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FW_UPDATE_H +#define __FW_UPDATE_H + +/* Default prefix for output messages */ +#define LOG_PREFIX "CM1: " + +/* Extra debug macro */ +#ifdef CONFIG_FWUPDATE_DEBUG +#define FW_DEBUG(fmt...) printf(LOG_PREFIX fmt) +#else +#define FW_DEBUG(fmt...) +#endif + +/* Name of the directory holding firmware images */ +#define FW_DIR "nx-fw" +#define RESCUE_IMAGE "nxrs.img" +#define LOAD_ADDR 0x400000 +#define RS_BOOTARGS "ramdisk=8192K" + +/* Main function for fwupdate */ +void cm1_fwupdate(void); + +#endif /* __FW_UPDATE_H */ diff --git a/board/cm1_qp1/u-boot.lds b/board/cm1_qp1/u-boot.lds new file mode 100644 index 0000000..8fa9c0f --- /dev/null +++ b/board/cm1_qp1/u-boot.lds @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2003-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/pcs440ep/flash.c b/board/pcs440ep/flash.c index 7001440..c5a62e2 100644 --- a/board/pcs440ep/flash.c +++ b/board/pcs440ep/flash.c @@ -82,6 +82,7 @@ void flash_print_info(flash_info_t *info) case FLASH_MAN_AMD: printf ("AMD "); break; case FLASH_MAN_FUJ: printf ("FUJITSU "); break; case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("ST Micro"); break; case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break; case FLASH_MAN_MX: printf ("MXIC "); break; default: printf ("Unknown Vendor "); break; @@ -118,6 +119,8 @@ void flash_print_info(flash_info_t *info) break; case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n"); break; + case STM_ID_M29W040B: printf ("ST Micro M29W040B (4 Mbit, uniform sector size)\n"); + break; default: printf ("Unknown Chip Type\n"); break; } @@ -193,6 +196,9 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: info->flash_id = FLASH_MAN_SST; break; + case (CFG_FLASH_WORD_SIZE)STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT: info->flash_id = FLASH_MAN_EXCEL; break; @@ -226,6 +232,11 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) info->sector_count = 8; info->size = 0x0080000; /* => 0.5 MB */ break; + case (CFG_FLASH_WORD_SIZE)STM_ID_M29W040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 0,5 MB */ + break; case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T: info->flash_id += FLASH_AM800T; diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index ada6b82..696423e 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -85,8 +85,9 @@ static void status_led_blink (void) /* set all LED which are on, to state BLINKING */ for (i = 0; i < 4; i++) { - if (val & 0x08) status_led_set (i, STATUS_LED_BLINKING); - val = val << 1; + if (val & 0x01) status_led_set (3 - i, STATUS_LED_BLINKING); + else status_led_set (3 - i, STATUS_LED_OFF); + val = val >> 1; } } @@ -113,12 +114,14 @@ void show_boot_progress (int val) status_led_set (1, STATUS_LED_ON); status_led_set (2, STATUS_LED_ON); break; +#if 0 case 64: /* starting Ethernet configuration */ status_led_set (0, STATUS_LED_OFF); status_led_set (1, STATUS_LED_OFF); status_led_set (2, STATUS_LED_ON); break; +#endif case 80: /* loading Image */ status_led_set (0, STATUS_LED_ON); @@ -235,7 +238,13 @@ void load_sernum_ethaddr (void) } /* Env doesnt exist -> hang */ status_led_blink (); - hang (); + /* here we do this "handy" because we have no interrupts + at this time */ + puts ("### EEPROM ERROR ### Please RESET the board ###\n"); + for (;;) { + __led_toggle (12); + udelay (100000); + } return; } @@ -404,13 +413,22 @@ static void pcs440ep_checksha1 (void) int ret; char *cs_test; + status_led_set (0, STATUS_LED_OFF); + status_led_set (1, STATUS_LED_OFF); + status_led_set (2, STATUS_LED_ON); ret = pcs440ep_sha1 (1); if (ret == 0) return; if ((cs_test = getenv ("cs_test")) == NULL) { /* Env doesnt exist -> hang */ status_led_blink (); - hang (); + /* here we do this "handy" because we have no interrupts + at this time */ + puts ("### SHA1 ERROR ### Please RESET the board ###\n"); + for (;;) { + __led_toggle (2); + udelay (100000); + } } if (strncmp (cs_test, "off", 3) == 0) { @@ -511,7 +529,7 @@ void spd_ddr_init_hang (void) status_led_set (1, STATUS_LED_ON); /* we cannot use hang() because we are still running from Flash, and so the status_led driver is not initialized */ - puts ("### ERROR ### Please RESET the board ###\n"); + puts ("### SDRAM ERROR ### Please RESET the board ###\n"); for (;;) { __led_toggle (4); udelay (100000); @@ -751,28 +769,41 @@ void hw_watchdog_reset(void) ************************************************************************/ int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - int rcode = 0; + int rcode = 0, i; ulong pattern = 0; - pattern = simple_strtoul (argv[1], NULL, 10); - if (pattern > 200) { + pattern = simple_strtoul (argv[1], NULL, 16); + if (pattern > 0x400) { + int val = GET_LEDS; + printf ("led: %x\n", val); + return rcode; + } + if (pattern > 0x200) { status_led_blink (); hang (); return rcode; } - if (pattern > 100) { + if (pattern > 0x100) { status_led_blink (); return rcode; } pattern &= 0x0f; - set_leds (pattern); + for (i = 0; i < 4; i++) { + if (pattern & 0x01) status_led_set (i, STATUS_LED_ON); + else status_led_set (i, STATUS_LED_OFF); + pattern = pattern >> 1; + } return rcode; } U_BOOT_CMD( led, 2, 1, do_led, - "led - set the led\n", - NULL + "led [bitmask] - set the DIAG-LED\n", + "[bitmask] 0x01 = DIAG 1 on\n" + " 0x02 = DIAG 2 on\n" + " 0x04 = DIAG 3 on\n" + " 0x08 = DIAG 4 on\n" + " > 0x100 set the LED, who are on, to state blinking\n" ); #if defined(CONFIG_SHA1_CHECK_UB_IMG) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index c371f0e..2436581 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -56,13 +56,6 @@ DECLARE_GLOBAL_DATA_PTR; #include <hush.h> #endif -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include <status_led.h> -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - #ifdef CFG_INIT_RAM_LOCK #include <asm/cache.h> #endif @@ -176,7 +169,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) addr = simple_strtoul(argv[1], NULL, 16); } - SHOW_BOOT_PROGRESS (1); + show_boot_progress (1); printf ("## Booting image at %08lx ...\n", addr); /* Copy header so we can blank CRC field for re-calculation */ @@ -200,11 +193,11 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif /* __I386__ */ { puts ("Bad Magic Number\n"); - SHOW_BOOT_PROGRESS (-1); + show_boot_progress (-1); return 1; } } - SHOW_BOOT_PROGRESS (2); + show_boot_progress (2); data = (ulong)&header; len = sizeof(image_header_t); @@ -214,10 +207,10 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (crc32 (0, (uchar *)data, len) != checksum) { puts ("Bad Header Checksum\n"); - SHOW_BOOT_PROGRESS (-2); + show_boot_progress (-2); return 1; } - SHOW_BOOT_PROGRESS (3); + show_boot_progress (3); #ifdef CONFIG_HAS_DATAFLASH if (addr_dataflash(addr)){ @@ -238,12 +231,12 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts (" Verifying Checksum ... "); if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) { printf ("Bad Data CRC\n"); - SHOW_BOOT_PROGRESS (-3); + show_boot_progress (-3); return 1; } puts ("OK\n"); } - SHOW_BOOT_PROGRESS (4); + show_boot_progress (4); len_ptr = (ulong *)data; @@ -272,10 +265,10 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif { printf ("Unsupported Architecture 0x%x\n", hdr->ih_arch); - SHOW_BOOT_PROGRESS (-4); + show_boot_progress (-4); return 1; } - SHOW_BOOT_PROGRESS (5); + show_boot_progress (5); switch (hdr->ih_type) { case IH_TYPE_STANDALONE: @@ -297,10 +290,10 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) data += 4; break; default: printf ("Wrong Image Type for %s command\n", cmdtp->name); - SHOW_BOOT_PROGRESS (-5); + show_boot_progress (-5); return 1; } - SHOW_BOOT_PROGRESS (6); + show_boot_progress (6); /* * We have reached the point of no return: we are going to @@ -351,7 +344,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (gunzip ((void *)ntohl(hdr->ih_load), unc_len, (uchar *)data, &len) != 0) { puts ("GUNZIP ERROR - must RESET board to recover\n"); - SHOW_BOOT_PROGRESS (-6); + show_boot_progress (-6); do_reset (cmdtp, flag, argc, argv); } break; @@ -368,7 +361,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) CFG_MALLOC_LEN < (4096 * 1024), 0); if (i != BZ_OK) { printf ("BUNZIP2 ERROR %d - must RESET board to recover\n", i); - SHOW_BOOT_PROGRESS (-6); + show_boot_progress (-6); udelay(100000); do_reset (cmdtp, flag, argc, argv); } @@ -378,11 +371,11 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (iflag) enable_interrupts(); printf ("Unimplemented compression type %d\n", hdr->ih_comp); - SHOW_BOOT_PROGRESS (-7); + show_boot_progress (-7); return 1; } puts ("OK\n"); - SHOW_BOOT_PROGRESS (7); + show_boot_progress (7); switch (hdr->ih_type) { case IH_TYPE_STANDALONE: @@ -409,10 +402,10 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (iflag) enable_interrupts(); printf ("Can't boot image type %d\n", hdr->ih_type); - SHOW_BOOT_PROGRESS (-8); + show_boot_progress (-8); return 1; } - SHOW_BOOT_PROGRESS (8); + show_boot_progress (8); switch (hdr->ih_os) { default: /* handled by (original) Linux case */ @@ -458,7 +451,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif } - SHOW_BOOT_PROGRESS (-9); + show_boot_progress (-9); #ifdef DEBUG puts ("\n## Control returned to monitor - resetting...\n"); do_reset (cmdtp, flag, argc, argv); @@ -637,7 +630,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, #endif if (argc >= 3) { debug ("Not skipping initrd\n"); - SHOW_BOOT_PROGRESS (9); + show_boot_progress (9); addr = simple_strtoul(argv[2], NULL, 16); @@ -648,7 +641,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, if (ntohl(hdr->ih_magic) != IH_MAGIC) { puts ("Bad Magic Number\n"); - SHOW_BOOT_PROGRESS (-10); + show_boot_progress (-10); do_reset (cmdtp, flag, argc, argv); } @@ -660,11 +653,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, if (crc32 (0, (uchar *)data, len) != checksum) { puts ("Bad Header Checksum\n"); - SHOW_BOOT_PROGRESS (-11); + show_boot_progress (-11); do_reset (cmdtp, flag, argc, argv); } - SHOW_BOOT_PROGRESS (10); + show_boot_progress (10); print_image_hdr (hdr); @@ -697,19 +690,19 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, if (csum != ntohl(hdr->ih_dcrc)) { puts ("Bad Data CRC\n"); - SHOW_BOOT_PROGRESS (-12); + show_boot_progress (-12); do_reset (cmdtp, flag, argc, argv); } puts ("OK\n"); } - SHOW_BOOT_PROGRESS (11); + show_boot_progress (11); if ((hdr->ih_os != IH_OS_LINUX) || (hdr->ih_arch != IH_CPU_PPC) || (hdr->ih_type != IH_TYPE_RAMDISK) ) { puts ("No Linux PPC Ramdisk Image\n"); - SHOW_BOOT_PROGRESS (-13); + show_boot_progress (-13); do_reset (cmdtp, flag, argc, argv); } @@ -720,7 +713,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, u_long tail = ntohl(len_ptr[0]) % 4; int i; - SHOW_BOOT_PROGRESS (13); + show_boot_progress (13); /* skip kernel length and terminator */ data = (ulong)(&len_ptr[2]); @@ -739,7 +732,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, /* * no initrd image */ - SHOW_BOOT_PROGRESS (14); + show_boot_progress (14); len = data = 0; } @@ -890,7 +883,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, initrd_start = nsp; } - SHOW_BOOT_PROGRESS (12); + show_boot_progress (12); debug ("## initrd at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n", data, data + len - 1, len, len); @@ -926,7 +919,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, debug ("## Transferring control to Linux (at address %08lx) ...\n", (ulong)kernel); - SHOW_BOOT_PROGRESS (15); + show_boot_progress (15); #if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) unlock_ram_in_cache(); @@ -1115,7 +1108,7 @@ do_bootm_netbsd (cmd_tbl_t *cmdtp, int flag, printf ("## Transferring control to NetBSD stage-2 loader (at address %08lx) ...\n", (ulong)loader); - SHOW_BOOT_PROGRESS (15); + show_boot_progress (15); /* * NetBSD Stage-2 Loader Parameters: @@ -1578,7 +1571,7 @@ do_bootm_rtems (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], printf ("## Transferring control to RTEMS (at address %08lx) ...\n", (ulong)entry_point); - SHOW_BOOT_PROGRESS (15); + show_boot_progress (15); /* * RTEMS Parameters: diff --git a/common/cmd_doc.c b/common/cmd_doc.c index a172b3b..d6d3aff 100644 --- a/common/cmd_doc.c +++ b/common/cmd_doc.c @@ -12,13 +12,6 @@ #include <malloc.h> #include <asm/io.h> -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include <status_led.h> -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - #if defined(CONFIG_CMD_DOC) #include <linux/mtd/nftl.h> @@ -216,7 +209,7 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) image_header_t *hdr; int rcode = 0; - SHOW_BOOT_PROGRESS (34); + show_boot_progress (34); switch (argc) { case 1: addr = CFG_LOAD_ADDR; @@ -237,27 +230,27 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; default: printf ("Usage:\n%s\n", cmdtp->usage); - SHOW_BOOT_PROGRESS (-35); + show_boot_progress (-35); return 1; } - SHOW_BOOT_PROGRESS (35); + show_boot_progress (35); if (!boot_device) { puts ("\n** No boot device **\n"); - SHOW_BOOT_PROGRESS (-36); + show_boot_progress (-36); return 1; } - SHOW_BOOT_PROGRESS (36); + show_boot_progress (36); dev = simple_strtoul(boot_device, &ep, 16); if ((dev >= CFG_MAX_DOC_DEVICE) || (doc_dev_desc[dev].ChipID == DOC_ChipID_UNKNOWN)) { printf ("\n** Device %d not available\n", dev); - SHOW_BOOT_PROGRESS (-37); + show_boot_progress (-37); return 1; } - SHOW_BOOT_PROGRESS (37); + show_boot_progress (37); printf ("\nLoading from device %d: %s at 0x%lX (offset 0x%lX)\n", dev, doc_dev_desc[dev].name, doc_dev_desc[dev].physadr, @@ -266,10 +259,10 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (doc_rw (doc_dev_desc + dev, 1, offset, SECTORSIZE, NULL, (u_char *)addr)) { printf ("** Read error on %d\n", dev); - SHOW_BOOT_PROGRESS (-38); + show_boot_progress (-38); return 1; } - SHOW_BOOT_PROGRESS (38); + show_boot_progress (38); hdr = (image_header_t *)addr; @@ -281,18 +274,18 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) cnt -= SECTORSIZE; } else { puts ("\n** Bad Magic Number **\n"); - SHOW_BOOT_PROGRESS (-39); + show_boot_progress (-39); return 1; } - SHOW_BOOT_PROGRESS (39); + show_boot_progress (39); if (doc_rw (doc_dev_desc + dev, 1, offset + SECTORSIZE, cnt, NULL, (u_char *)(addr+SECTORSIZE))) { printf ("** Read error on %d\n", dev); - SHOW_BOOT_PROGRESS (-40); + show_boot_progress (-40); return 1; } - SHOW_BOOT_PROGRESS (40); + show_boot_progress (40); /* Loading ok, update default load address */ diff --git a/common/cmd_ide.c b/common/cmd_ide.c index cbfc303..89fefed 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -59,13 +59,6 @@ unsigned long mips_io_port_base = 0; #endif #endif -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include <status_led.h> -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - #ifdef CONFIG_IDE_8xx_DIRECT DECLARE_GLOBAL_DATA_PTR; #endif @@ -385,7 +378,7 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) image_header_t *hdr; int rcode = 0; - SHOW_BOOT_PROGRESS (41); + show_boot_progress (41); switch (argc) { case 1: addr = CFG_LOAD_ADDR; @@ -401,50 +394,50 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; default: printf ("Usage:\n%s\n", cmdtp->usage); - SHOW_BOOT_PROGRESS (-42); + show_boot_progress (-42); return 1; } - SHOW_BOOT_PROGRESS (42); + show_boot_progress (42); if (!boot_device) { puts ("\n** No boot device **\n"); - SHOW_BOOT_PROGRESS (-43); + show_boot_progress (-43); return 1; } - SHOW_BOOT_PROGRESS (43); + show_boot_progress (43); dev = simple_strtoul(boot_device, &ep, 16); if (ide_dev_desc[dev].type==DEV_TYPE_UNKNOWN) { printf ("\n** Device %d not available\n", dev); - SHOW_BOOT_PROGRESS (-44); + show_boot_progress (-44); return 1; } - SHOW_BOOT_PROGRESS (44); + show_boot_progress (44); if (*ep) { if (*ep != ':') { puts ("\n** Invalid boot device, use `dev[:part]' **\n"); - SHOW_BOOT_PROGRESS (-45); + show_boot_progress (-45); return 1; } part = simple_strtoul(++ep, NULL, 16); } - SHOW_BOOT_PROGRESS (45); + show_boot_progress (45); if (get_partition_info (&ide_dev_desc[dev], part, &info)) { - SHOW_BOOT_PROGRESS (-46); + show_boot_progress (-46); return 1; } - SHOW_BOOT_PROGRESS (46); + show_boot_progress (46); if ((strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) && (strncmp((char *)info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) { printf ("\n** Invalid partition type \"%.32s\"" " (expect \"" BOOT_PART_TYPE "\")\n", info.type); - SHOW_BOOT_PROGRESS (-47); + show_boot_progress (-47); return 1; } - SHOW_BOOT_PROGRESS (47); + show_boot_progress (47); printf ("\nLoading from IDE device %d, partition %d: " "Name: %.32s Type: %.32s\n", @@ -455,29 +448,29 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (ide_dev_desc[dev].block_read (dev, info.start, 1, (ulong *)addr) != 1) { printf ("** Read error on %d:%d\n", dev, part); - SHOW_BOOT_PROGRESS (-48); + show_boot_progress (-48); return 1; } - SHOW_BOOT_PROGRESS (48); + show_boot_progress (48); hdr = (image_header_t *)addr; if (ntohl(hdr->ih_magic) != IH_MAGIC) { printf("\n** Bad Magic Number **\n"); - SHOW_BOOT_PROGRESS (-49); + show_boot_progress (-49); return 1; } - SHOW_BOOT_PROGRESS (49); + show_boot_progress (49); checksum = ntohl(hdr->ih_hcrc); hdr->ih_hcrc = 0; if (crc32 (0, (uchar *)hdr, sizeof(image_header_t)) != checksum) { puts ("\n** Bad Header Checksum **\n"); - SHOW_BOOT_PROGRESS (-50); + show_boot_progress (-50); return 1; } - SHOW_BOOT_PROGRESS (50); + show_boot_progress (50); hdr->ih_hcrc = htonl(checksum); /* restore checksum for later use */ print_image_hdr (hdr); @@ -490,10 +483,10 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (ide_dev_desc[dev].block_read (dev, info.start+1, cnt, (ulong *)(addr+info.blksz)) != cnt) { printf ("** Read error on %d:%d\n", dev, part); - SHOW_BOOT_PROGRESS (-51); + show_boot_progress (-51); return 1; } - SHOW_BOOT_PROGRESS (51); + show_boot_progress (51); /* Loading ok, update default load address */ diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 8832db9..c72612d 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -25,14 +25,6 @@ #include <watchdog.h> #include <malloc.h> #include <asm/byteorder.h> - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include <status_led.h> -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - #include <jffs2/jffs2.h> #include <nand.h> @@ -486,19 +478,19 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, r = nand_read(nand, offset, &cnt, (u_char *) addr); if (r) { puts("** Read error\n"); - SHOW_BOOT_PROGRESS(-56); + show_boot_progress (-56); return 1; } - SHOW_BOOT_PROGRESS(56); + show_boot_progress (56); hdr = (image_header_t *) addr; if (ntohl(hdr->ih_magic) != IH_MAGIC) { printf("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic); - SHOW_BOOT_PROGRESS(-57); + show_boot_progress (-57); return 1; } - SHOW_BOOT_PROGRESS(57); + show_boot_progress (57); print_image_hdr(hdr); @@ -507,10 +499,10 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, r = nand_read(nand, offset, &cnt, (u_char *) addr); if (r) { puts("** Read error\n"); - SHOW_BOOT_PROGRESS(-58); + show_boot_progress (-58); return 1; } - SHOW_BOOT_PROGRESS(58); + show_boot_progress (58); /* Loading ok, update default load address */ @@ -562,7 +554,7 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } #endif - SHOW_BOOT_PROGRESS(52); + show_boot_progress(52); switch (argc) { case 1: addr = CFG_LOAD_ADDR; @@ -586,26 +578,26 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) usage: #endif printf("Usage:\n%s\n", cmdtp->usage); - SHOW_BOOT_PROGRESS(-53); + show_boot_progress(-53); return 1; } - SHOW_BOOT_PROGRESS(53); + show_boot_progress(53); if (!boot_device) { puts("\n** No boot device **\n"); - SHOW_BOOT_PROGRESS(-54); + show_boot_progress(-54); return 1; } - SHOW_BOOT_PROGRESS(54); + show_boot_progress(54); idx = simple_strtoul(boot_device, NULL, 16); if (idx < 0 || idx >= CFG_MAX_NAND_DEVICE || !nand_info[idx].name) { printf("\n** Device %d not available\n", idx); - SHOW_BOOT_PROGRESS(-55); + show_boot_progress(-55); return 1; } - SHOW_BOOT_PROGRESS(55); + show_boot_progress(55); return nand_load_image(cmdtp, &nand_info[idx], offset, addr, argv[0]); } @@ -627,11 +619,11 @@ U_BOOT_CMD(nboot, 4, 1, do_nandboot, #include <asm/io.h> #include <watchdog.h> -#ifdef CONFIG_SHOW_BOOT_PROGRESS +#ifdef CONFIG_show_boot_progress # include <status_led.h> -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +# define show_boot_progress(arg) show_boot_progress(arg) #else -# define SHOW_BOOT_PROGRESS(arg) +# define show_boot_progress(arg) #endif #if defined(CONFIG_CMD_NAND) @@ -894,7 +886,7 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong offset = 0; image_header_t *hdr; int rcode = 0; - SHOW_BOOT_PROGRESS(52); + show_boot_progress (52); switch (argc) { case 1: addr = CFG_LOAD_ADDR; @@ -915,27 +907,27 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; default: printf ("Usage:\n%s\n", cmdtp->usage); - SHOW_BOOT_PROGRESS (-53); + show_boot_progress (-53); return 1; } - SHOW_BOOT_PROGRESS(53); + show_boot_progress (53); if (!boot_device) { puts ("\n** No boot device **\n"); - SHOW_BOOT_PROGRESS (-54); + show_boot_progress (-54); return 1; } - SHOW_BOOT_PROGRESS(54); + show_boot_progress (54); dev = simple_strtoul(boot_device, &ep, 16); if ((dev >= CFG_MAX_NAND_DEVICE) || (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN)) { printf ("\n** Device %d not available\n", dev); - SHOW_BOOT_PROGRESS (-55); + show_boot_progress (-55); return 1; } - SHOW_BOOT_PROGRESS(55); + show_boot_progress (55); printf ("\nLoading from device %d: %s at 0x%lx (offset 0x%lx)\n", dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR, @@ -944,10 +936,10 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, offset, SECTORSIZE, NULL, (u_char *)addr)) { printf ("** Read error on %d\n", dev); - SHOW_BOOT_PROGRESS (-56); + show_boot_progress (-56); return 1; } - SHOW_BOOT_PROGRESS(56); + show_boot_progress (56); hdr = (image_header_t *)addr; @@ -959,19 +951,19 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) cnt -= SECTORSIZE; } else { printf ("\n** Bad Magic Number 0x%x **\n", ntohl(hdr->ih_magic)); - SHOW_BOOT_PROGRESS (-57); + show_boot_progress (-57); return 1; } - SHOW_BOOT_PROGRESS(57); + show_boot_progress (57); if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, offset + SECTORSIZE, cnt, NULL, (u_char *)(addr+SECTORSIZE))) { printf ("** Read error on %d\n", dev); - SHOW_BOOT_PROGRESS (-58); + show_boot_progress (-58); return 1; } - SHOW_BOOT_PROGRESS(58); + show_boot_progress (58); /* Loading ok, update default load address */ diff --git a/common/cmd_net.c b/common/cmd_net.c index fa4f968..0715fbc 100644 --- a/common/cmd_net.c +++ b/common/cmd_net.c @@ -30,14 +30,6 @@ #if defined(CONFIG_CMD_NET) -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include <status_led.h> -extern void show_boot_progress (int val); -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress (arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - extern int do_bootm (cmd_tbl_t *, int, int, char *[]); static int netboot_common (proto_t, cmd_tbl_t *, int , char *[]); @@ -193,23 +185,23 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[]) break; default: printf ("Usage:\n%s\n", cmdtp->usage); - SHOW_BOOT_PROGRESS(-80); + show_boot_progress (-80); return 1; } - SHOW_BOOT_PROGRESS(80); + show_boot_progress (80); if ((size = NetLoop(proto)) < 0) { - SHOW_BOOT_PROGRESS(-81); + show_boot_progress (-81); return 1; } - SHOW_BOOT_PROGRESS(81); + show_boot_progress (81); /* NetLoop ok, update environment */ netboot_update_env(); /* done if no file was loaded (no errors though) */ if (size == 0) { - SHOW_BOOT_PROGRESS(-82); + show_boot_progress (-82); return 0; } @@ -224,23 +216,21 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[]) printf ("Automatic boot of image at addr 0x%08lX ...\n", load_addr); - SHOW_BOOT_PROGRESS(82); + show_boot_progress (82); rcode = do_bootm (cmdtp, 0, 1, local_args); } #ifdef CONFIG_AUTOSCRIPT if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)) { printf("Running autoscript at addr 0x%08lX ...\n", load_addr); - SHOW_BOOT_PROGRESS(83); + show_boot_progress (83); rcode = autoscript (load_addr); } #endif -#if defined(CONFIG_SHOW_BOOT_PROGRESS) if (rcode < 0) - SHOW_BOOT_PROGRESS(-83); + show_boot_progress (-83); else - SHOW_BOOT_PROGRESS(84); -#endif + show_boot_progress (84); return rcode; } diff --git a/common/env_common.c b/common/env_common.c index 0462cad6..a494812 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -30,13 +30,6 @@ #include <linux/stddef.h> #include <malloc.h> -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include <status_led.h> -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_AMIGAONEG3SE @@ -232,7 +225,7 @@ void env_relocate (void) puts ("Using default environment\n\n"); #else puts ("*** Warning - bad CRC, using default environment\n\n"); - SHOW_BOOT_PROGRESS (-60); + show_boot_progress (-60); #endif if (sizeof(default_environment) > ENV_SIZE) diff --git a/common/main.c b/common/main.c index c6a65b0..379695c 100644 --- a/common/main.c +++ b/common/main.c @@ -44,6 +44,12 @@ DECLARE_GLOBAL_DATA_PTR; #endif +/* + * Board-specific Platform code can reimplement show_boot_progress () if needed + */ +void inline __show_boot_progress (int val) {} +void inline show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress"))); + #if defined(CONFIG_BOOT_RETRY_TIME) && defined(CONFIG_RESET_TO_RETRY) extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /* for do_reset() prototype */ #endif diff --git a/cpu/mpc512x/Makefile b/cpu/mpc512x/Makefile new file mode 100644 index 0000000..2be35b2 --- /dev/null +++ b/cpu/mpc512x/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2007 DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/mpc512x/config.mk b/cpu/mpc512x/config.mk new file mode 100644 index 0000000..8a07c5a --- /dev/null +++ b/cpu/mpc512x/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2007 DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi + +PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \ + -ffixed-r2 -ffixed-r29 -msoft-float -mcpu=603e diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c new file mode 100644 index 0000000..3be565a --- /dev/null +++ b/cpu/mpc512x/cpu.c @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * (C) Copyright 2007 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code for the MPC512x family. + * + * Derived from the MPC83xx code. + */ + +#include <common.h> +#include <command.h> +#include <mpc512x.h> +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkcpu (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + ulong clock = gd->cpu_clk; + u32 pvr = get_pvr (); + u32 spridr = immr->sysconf.spridr; + char buf[32]; + + puts("CPU: "); + + switch (spridr & 0xffff0000) { + case SPR_5121E: + puts ("MPC5121e "); + break; + default: + printf ("Unknown part ID %08x ", spridr & 0xffff0000); + } + printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr)); + + switch (pvr & 0xffff0000) { + case PVR_E300C4: + puts ("e300c4 "); + break; + default: + puts ("unknown "); + } + printf ("at %s MHz, CSB at %3d MHz\n", strmhz(buf, clock), + gd->csb_clk / 1000000); + return 0; +} + + +int +do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong msr; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + /* Interrupts and MMU off */ + __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); + + msr &= ~( MSR_EE | MSR_IR | MSR_DR); + __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); + + /* + * Enable Reset Control Reg - "RSTE" is the magic word that let us go + */ + immap->reset.rpr = 0x52535445; + + /* Verify Reset Control Reg is enabled */ + while (!((immap->reset.rcer) & RCER_CRE)) + ; + + printf ("Resetting the board.\n"); + udelay(200); + + /* Perform reset */ + immap->reset.rcr = RCR_SWHR; + + /* Unreached... */ + return 1; +} + + +/* + * Get timebase clock frequency (like cpu_clk in Hz) + */ +unsigned long get_tbclk (void) +{ + ulong tbclk; + + tbclk = (gd->bus_clk + 3L) / 4L; + + return tbclk; +} + + +#if defined(CONFIG_WATCHDOG) +void watchdog_reset (void) +{ + int re_enable = disable_interrupts (); + + /* Reset watchdog */ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + immr->wdt.swsrr = 0x556c; + immr->wdt.swsrr = 0xaa39; + + if (re_enable) + enable_interrupts (); +} +#endif diff --git a/cpu/mpc512x/cpu_init.c b/cpu/mpc512x/cpu_init.c new file mode 100644 index 0000000..d6949f6 --- /dev/null +++ b/cpu/mpc512x/cpu_init.c @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * (C) Copyright 2007 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Derived from the MPC83xx code. + * + */ + +#include <common.h> +#include <mpc512x.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Set up the memory map, initialize registers, + */ +void cpu_init_f (volatile immap_t * im) +{ + u32 ips_div; + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + + /* system performance tweaking */ + +#ifdef CFG_ACR_PIPE_DEP + /* Arbiter pipeline depth */ + im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | + (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); +#endif + +#ifdef CFG_ACR_RPTCNT + /* Arbiter repeat count */ + im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | + (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT)); +#endif + + /* RSR - Reset Status Register - clear all status */ + gd->reset_status = im->reset.rsr; + im->reset.rsr = ~(RSR_RES); + + /* + * RMR - Reset Mode Register - enable checkstop reset + */ + im->reset.rmr = (RMR_CSRE & (1 << RMR_CSRE_SHIFT)); + + /* Set IPS-CSB divider: IPS = 1/2 CSB */ + ips_div = im->clk.scfr[0]; + ips_div &= ~(SCFR1_IPS_DIV_MASK); + ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT; + im->clk.scfr[0] = ips_div; + + /* + * Enable Time Base/Decrementer + * + * NOTICE: TB needs to be enabled as early as possible in order to + * have udelay() working; if not enabled, usually leads to a hang, like + * during FLASH chip identification etc. + */ + im->sysconf.spcr |= SPCR_TBEN; +} + +int cpu_init_r (void) +{ + return 0; +} diff --git a/cpu/mpc512x/fec.c b/cpu/mpc512x/fec.c new file mode 100644 index 0000000..1c87a53 --- /dev/null +++ b/cpu/mpc512x/fec.c @@ -0,0 +1,801 @@ +/* + * (C) Copyright 2003-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Derived from the MPC8xx FEC driver. + * Adapted for MPC512x by Grzegorz Bernacki <gjb@semihalf.com> + */ + +#include <common.h> +#include <mpc512x.h> +#include <malloc.h> +#include <net.h> +#include <miiphy.h> +#include "fec.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define DEBUG 0 + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_MPC512x_FEC) + +#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) +#error "CONFIG_MII has to be defined!" +#endif + +#if (DEBUG & 0x40) +static uint32 local_crc32(char *string, unsigned int crc_value, int len); +#endif + +int fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal); +int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data); +int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis); + +/********************************************************************/ +#if (DEBUG & 0x2) +static void mpc512x_fec_phydump (char *devname) +{ + uint16 phyStatus, i; + uint8 phyAddr = CONFIG_PHY_ADDR; + uint8 reg_mask[] = { + /* regs to print: 0...8, 21,27,31 */ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, + }; + + for (i = 0; i < 32; i++) { + if (reg_mask[i]) { + miiphy_read (devname, phyAddr, i, &phyStatus); + printf ("Mii reg %d: 0x%04x\n", i, phyStatus); + } + } +} +#endif + +/********************************************************************/ +static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec) +{ + int ix; + + /* + * Receive BDs init + */ + for (ix = 0; ix < FEC_RBD_NUM; ix++) { + fec->bdBase->rbd[ix].dataPointer = (uint32)&fec->bdBase->recv_frames[ix]; + fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY; + fec->bdBase->rbd[ix].dataLength = 0; + } + + /* + * have the last RBD to close the ring + */ + fec->bdBase->rbd[ix - 1].status |= FEC_RBD_WRAP; + fec->rbdIndex = 0; + + /* + * Trasmit BDs init + */ + for (ix = 0; ix < FEC_TBD_NUM; ix++) { + fec->bdBase->tbd[ix].status = 0; + } + + /* + * Have the last TBD to close the ring + */ + fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP; + + /* + * Initialize some indices + */ + fec->tbdIndex = 0; + fec->usedTbdIndex = 0; + fec->cleanTbdNum = FEC_TBD_NUM; + + return 0; +} + +/********************************************************************/ +static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRbd) +{ + /* + * Reset buffer descriptor as empty + */ + if ((fec->rbdIndex) == (FEC_RBD_NUM - 1)) + pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY); + else + pRbd->status = FEC_RBD_EMPTY; + + pRbd->dataLength = 0; + + /* + * Increment BD count + */ + fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM; + + /* + * Now, we have an empty RxBD, notify FEC + */ + fec->eth->r_des_active = 0x01000000; /* Descriptor polling active */ +} + +/********************************************************************/ +static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec) +{ + volatile FEC_TBD *pUsedTbd; + +#if (DEBUG & 0x1) + printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n", + fec->cleanTbdNum, fec->usedTbdIndex); +#endif + + /* + * process all the consumed TBDs + */ + while (fec->cleanTbdNum < FEC_TBD_NUM) { + pUsedTbd = &fec->bdBase->tbd[fec->usedTbdIndex]; + if (pUsedTbd->status & FEC_TBD_READY) { +#if (DEBUG & 0x20) + printf ("Cannot clean TBD %d, in use\n", fec->usedTbdIndex); +#endif + return; + } + + /* + * clean this buffer descriptor + */ + if (fec->usedTbdIndex == (FEC_TBD_NUM - 1)) + pUsedTbd->status = FEC_TBD_WRAP; + else + pUsedTbd->status = 0; + + /* + * update some indeces for a correct handling of the TBD ring + */ + fec->cleanTbdNum++; + fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM; + } +} + +/********************************************************************/ +static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, char *mac) +{ + uint8 currByte; /* byte for which to compute the CRC */ + int byte; /* loop - counter */ + int bit; /* loop - counter */ + uint32 crc = 0xffffffff; /* initial value */ + + /* + * The algorithm used is the following: + * we loop on each of the six bytes of the provided address, + * and we compute the CRC by left-shifting the previous + * value by one position, so that each bit in the current + * byte of the address may contribute the calculation. If + * the latter and the MSB in the CRC are different, then + * the CRC value so computed is also ex-ored with the + * "polynomium generator". The current byte of the address + * is also shifted right by one bit at each iteration. + * This is because the CRC generatore in hardware is implemented + * as a shift-register with as many ex-ores as the radixes + * in the polynomium. This suggests that we represent the + * polynomiumm itself as a 32-bit constant. + */ + for (byte = 0; byte < 6; byte++) { + currByte = mac[byte]; + for (bit = 0; bit < 8; bit++) { + if ((currByte & 0x01) ^ (crc & 0x01)) { + crc >>= 1; + crc = crc ^ 0xedb88320; + } else { + crc >>= 1; + } + currByte >>= 1; + } + } + + crc = crc >> 26; + + /* + * Set individual hash table register + */ + if (crc >= 32) { + fec->eth->iaddr1 = (1 << (crc - 32)); + fec->eth->iaddr2 = 0; + } else { + fec->eth->iaddr1 = 0; + fec->eth->iaddr2 = (1 << crc); + } + + /* + * Set physical address + */ + fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; + fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808; +} + +/********************************************************************/ +static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) +{ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + +#if (DEBUG & 0x1) + printf ("mpc512x_fec_init... Begin\n"); +#endif + + /* Set interrupt mask register */ + fec->eth->imask = 0x00000000; + + /* Clear FEC-Lite interrupt event register(IEVENT) */ + fec->eth->ievent = 0xffffffff; + + /* Set transmit fifo watermark register(X_WMRK), default = 64 */ + fec->eth->x_wmrk = 0x0; + + /* Set Opcode/Pause Duration Register */ + fec->eth->op_pause = 0x00010020; + + /* Frame length=1518; MII mode */ + fec->eth->r_cntrl = 0x05ee000c; + + /* Half-duplex, heartbeat disabled */ + fec->eth->x_cntrl = 0x00000000; + + /* Enable MIB counters */ + fec->eth->mib_control = 0x0; + + /* Setup recv fifo start and buff size */ + fec->eth->r_fstart = 0x500; + fec->eth->r_buff_size = 0x5e0; + + /* Setup BD base addresses */ + fec->eth->r_des_start = (uint32)fec->bdBase->rbd; + fec->eth->x_des_start = (uint32)fec->bdBase->tbd; + + /* DMA Control */ + fec->eth->dma_control = 0xc0000000; + + /* Enable FEC */ + fec->eth->ecntrl |= 0x00000006; + + /* Initilize addresses and status words of BDs */ + mpc512x_fec_bd_init (fec); + + /* Descriptor polling active */ + fec->eth->r_des_active = 0x01000000; + +#if (DEBUG & 0x1) + printf("mpc512x_fec_init... Done \n"); +#endif + return 1; +} + +/********************************************************************/ +int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis) +{ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */ + int timeout = 1; + uint16 phyStatus; + +#if (DEBUG & 0x1) + printf ("mpc512x_fec_init_phy... Begin\n"); +#endif + + /* + * Clear FEC-Lite interrupt event register(IEVENT) + */ + fec->eth->ievent = 0xffffffff; + + /* + * Set interrupt mask register + */ + fec->eth->imask = 0x00000000; + + if (fec->xcv_type != SEVENWIRE) { + /* + * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock + * and do not drop the Preamble. + */ + fec->eth->mii_speed = (((gd->ipb_clk / 1000000) / 5) + 1) << 1; + + /* + * Reset PHY, then delay 300ns + */ + miiphy_write (dev->name, phyAddr, 0x0, 0x8000); + udelay (1000); + + if (fec->xcv_type == MII10) { + /* + * Force 10Base-T, FDX operation + */ +#if (DEBUG & 0x2) + printf ("Forcing 10 Mbps ethernet link... "); +#endif + miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); + + miiphy_write (dev->name, phyAddr, 0x0, 0x0180); + + timeout = 20; + do { /* wait for link status to go down */ + udelay (10000); + if ((timeout--) == 0) { +#if (DEBUG & 0x2) + printf ("hmmm, should not have waited..."); +#endif + break; + } + miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); +#if (DEBUG & 0x2) + printf ("="); +#endif + } while ((phyStatus & 0x0004)); /* !link up */ + + timeout = 1000; + do { /* wait for link status to come back up */ + udelay (10000); + if ((timeout--) == 0) { + printf ("failed. Link is down.\n"); + break; + } + miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); +#if (DEBUG & 0x2) + printf ("+"); +#endif + } while (!(phyStatus & 0x0004)); /* !link up */ + +#if (DEBUG & 0x2) + printf ("done.\n"); +#endif + } else { /* MII100 */ + /* + * Set the auto-negotiation advertisement register bits + */ + miiphy_write (dev->name, phyAddr, 0x4, 0x01e1); + + /* + * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation + */ + miiphy_write (dev->name, phyAddr, 0x0, 0x1200); + + /* + * Wait for AN completion + */ + timeout = 50000; + do { + udelay (1000); + + if ((timeout--) == 0) { +#if (DEBUG & 0x2) + printf ("PHY auto neg 0 failed...\n"); +#endif + return -1; + } + + if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != 0) { +#if (DEBUG & 0x2) + printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus); +#endif + return -1; + } + } while (!(phyStatus & 0x0004)); + +#if (DEBUG & 0x2) + printf ("PHY auto neg complete! \n"); +#endif + } + } + +#if (DEBUG & 0x2) + if (fec->xcv_type != SEVENWIRE) + mpc512x_fec_phydump (dev->name); +#endif + +#if (DEBUG & 0x1) + printf ("mpc512x_fec_init_phy... Done \n"); +#endif + return 1; +} + +/********************************************************************/ +static void mpc512x_fec_halt (struct eth_device *dev) +{ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + int counter = 0xffff; + +#if (DEBUG & 0x2) + if (fec->xcv_type != SEVENWIRE) + mpc512x_fec_phydump (dev->name); +#endif + + /* + * mask FEC chip interrupts + */ + fec->eth->imask = 0; + + /* + * issue graceful stop command to the FEC transmitter if necessary + */ + fec->eth->x_cntrl |= 0x00000001; + + /* + * wait for graceful stop to register + */ + while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ; + + /* + * Disable the Ethernet Controller + */ + fec->eth->ecntrl &= 0xfffffffd; + + /* + * Issue a reset command to the FEC chip + */ + fec->eth->ecntrl |= 0x1; + + /* + * wait at least 16 clock cycles + */ + udelay (10); +#if (DEBUG & 0x3) + printf ("Ethernet task stopped\n"); +#endif +} + +/********************************************************************/ + +static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data, + int data_length) +{ + /* + * This routine transmits one frame. This routine only accepts + * 6-byte Ethernet addresses. + */ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + volatile FEC_TBD *pTbd; + +#if (DEBUG & 0x20) + printf("tbd status: 0x%04x\n", fec->tbdBase[fec->tbdIndex].status); +#endif + + /* + * Clear Tx BD ring at first + */ + mpc512x_fec_tbd_scrub (fec); + + /* + * Check for valid length of data. + */ + if ((data_length > 1500) || (data_length <= 0)) { + return -1; + } + + /* + * Check the number of vacant TxBDs. + */ + if (fec->cleanTbdNum < 1) { +#if (DEBUG & 0x20) + printf ("No available TxBDs ...\n"); +#endif + return -1; + } + + /* + * Get the first TxBD to send the mac header + */ + pTbd = &fec->bdBase->tbd[fec->tbdIndex]; + pTbd->dataLength = data_length; + pTbd->dataPointer = (uint32)eth_data; + pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; + fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM; + + /* Activate transmit Buffer Descriptor polling */ + fec->eth->x_des_active = 0x01000000; /* Descriptor polling active */ + +#if (DEBUG & 0x8) + printf ( "+" ); +#endif + + fec->cleanTbdNum -= 1; + + /* + * wait until frame is sent . + */ + while (pTbd->status & FEC_TBD_READY) { + udelay (10); +#if (DEBUG & 0x8) + printf ("TDB status = %04x\n", pTbd->status); +#endif + } + + return 0; +} + + +/********************************************************************/ +static int mpc512x_fec_recv (struct eth_device *dev) +{ + /* + * This command pulls one frame from the card + */ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex]; + unsigned long ievent; + int frame_length, len = 0; + uchar buff[FEC_MAX_PKT_SIZE]; + +#if (DEBUG & 0x1) + printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex); +#endif +#if (DEBUG & 0x8) + printf( "-" ); +#endif + + /* + * Check if any critical events have happened + */ + ievent = fec->eth->ievent; + fec->eth->ievent = ievent; + if (ievent & 0x20060000) { + /* BABT, Rx/Tx FIFO errors */ + mpc512x_fec_halt (dev); + mpc512x_fec_init (dev, NULL); + return 0; + } + if (ievent & 0x80000000) { + /* Heartbeat error */ + fec->eth->x_cntrl |= 0x00000001; + } + if (ievent & 0x10000000) { + /* Graceful stop complete */ + if (fec->eth->x_cntrl & 0x00000001) { + mpc512x_fec_halt (dev); + fec->eth->x_cntrl &= ~0x00000001; + mpc512x_fec_init (dev, NULL); + } + } + + if (!(pRbd->status & FEC_RBD_EMPTY)) { + if ((pRbd->status & FEC_RBD_LAST) && + !(pRbd->status & FEC_RBD_ERR) && + ((pRbd->dataLength - 4) > 14)) { + + /* + * Get buffer size + */ + frame_length = pRbd->dataLength - 4; + +#if (DEBUG & 0x20) + { + int i; + printf ("recv data hdr:"); + for (i = 0; i < 14; i++) + printf ("%x ", *((uint8*)pRbd->dataPointer + i)); + printf("\n"); + } +#endif + + /* + * Fill the buffer and pass it to upper layers + */ + memcpy (buff, (void*)pRbd->dataPointer, frame_length); + NetReceive ((uchar*)buff, frame_length); + len = frame_length; + } + + /* + * Reset buffer descriptor as empty + */ + mpc512x_fec_rbd_clean (fec, pRbd); + } + + /* Try to fill Buffer Descriptors */ + fec->eth->r_des_active = 0x01000000; /* Descriptor polling active */ + return len; +} + +/********************************************************************/ +int mpc512x_fec_initialize (bd_t * bis) +{ + + immap_t *im = (immap_t*) CFG_IMMR; + mpc512x_fec_priv *fec; + struct eth_device *dev; + int i; + char *tmp, *end, env_enetaddr[6]; + uint32 *reg; + void * bd; + + fec = (mpc512x_fec_priv *) malloc (sizeof(*fec)); + dev = (struct eth_device *) malloc (sizeof(*dev)); + memset (dev, 0, sizeof *dev); + + fec->eth = (ethernet_regs *) MPC512X_FEC; + +# ifndef CONFIG_FEC_10MBIT + fec->xcv_type = MII100; +# else + fec->xcv_type = MII10; +# endif + dev->priv = (void *)fec; + dev->iobase = MPC512X_FEC; + dev->init = mpc512x_fec_init; + dev->halt = mpc512x_fec_halt; + dev->send = mpc512x_fec_send; + dev->recv = mpc512x_fec_recv; + + sprintf (dev->name, "FEC ETHERNET"); + eth_register (dev); + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_register (dev->name, + fec512x_miiphy_read, fec512x_miiphy_write); +#endif + + /* + * Initialize I\O pins + */ + reg = (uint32 *) &(im->io_ctrl.regs[PSC0_0_IDX]); + + for (i = 0; i < 15; i++) + reg[i] = IOCTRL_MUX_FEC | 0x00000001; + + im->io_ctrl.regs[SPDIF_TXCLOCK_IDX] = IOCTRL_MUX_FEC | 0x00000001; + im->io_ctrl.regs[SPDIF_TX_IDX] = IOCTRL_MUX_FEC | 0x00000001; + im->io_ctrl.regs[SPDIF_RX_IDX] = IOCTRL_MUX_FEC | 0x00000001; + + /* Clean up space FEC's MIB and FIFO RAM ...*/ + memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400); + + /* + * Malloc space for BDs (must be quad word-aligned) + * this pointer is lost, so cannot be freed + */ + bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f); + fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0); + memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f); + + /* + * Set interrupt mask register + */ + fec->eth->imask = 0x00000000; + + /* + * Clear FEC-Lite interrupt event register(IEVENT) + */ + fec->eth->ievent = 0xffffffff; + + /* + * Try to set the mac address now. The fec mac address is + * a garbage after reset. When not using fec for booting + * the Linux fec driver will try to work with this garbage. + */ + tmp = getenv ("ethaddr"); + if (tmp) { + for (i=0; i<6; i++) { + env_enetaddr[i] = tmp ? simple_strtoul (tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + mpc512x_fec_set_hwaddr (fec, env_enetaddr); + fec->eth->gaddr1 = 0x00000000; + fec->eth->gaddr2 = 0x00000000; + } + + mpc512x_fec_init_phy (dev, bis); + + return 1; +} + +/* MII-interface related functions */ +/********************************************************************/ +int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal) +{ + ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC; + uint32 reg; /* convenient holder for the PHY register */ + uint32 phy; /* convenient holder for the PHY */ + int timeout = 0xffff; + + /* + * reading from any PHY's register is done by properly + * programming the FEC's MII data register. + */ + reg = regAddr << FEC_MII_DATA_RA_SHIFT; + phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + + eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg); + + /* + * wait for the related interrupt + */ + while ((timeout--) && (!(eth->ievent & 0x00800000))) ; + + if (timeout == 0) { +#if (DEBUG & 0x2) + printf ("Read MDIO failed...\n"); +#endif + return -1; + } + + /* + * clear mii interrupt bit + */ + eth->ievent = 0x00800000; + + /* + * it's now safe to read the PHY's register + */ + *retVal = (uint16) eth->mii_data; + + return 0; +} + +/********************************************************************/ +int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 data) +{ + ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC; + uint32 reg; /* convenient holder for the PHY register */ + uint32 phy; /* convenient holder for the PHY */ + int timeout = 0xffff; + + reg = regAddr << FEC_MII_DATA_RA_SHIFT; + phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + + eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | + FEC_MII_DATA_TA | phy | reg | data); + + /* + * wait for the MII interrupt + */ + while ((timeout--) && (!(eth->ievent & 0x00800000))) ; + + if (timeout == 0) { +#if (DEBUG & 0x2) + printf ("Write MDIO failed...\n"); +#endif + return -1; + } + + /* + * clear MII interrupt bit + */ + eth->ievent = 0x00800000; + + return 0; +} + +#if (DEBUG & 0x40) +static uint32 local_crc32 (char *string, unsigned int crc_value, int len) +{ + int i; + char c; + unsigned int crc, count; + + /* + * crc32 algorithm + */ + /* + * crc = 0xffffffff; * The initialized value should be 0xffffffff + */ + crc = crc_value; + + for (i = len; --i >= 0;) { + c = *string++; + for (count = 0; count < 8; count++) { + if ((c & 0x01) ^ (crc & 0x01)) { + crc >>= 1; + crc = crc ^ 0xedb88320; + } else { + crc >>= 1; + } + c >>= 1; + } + } + + /* + * In big endian system, do byte swaping for crc value + */ + /**/ return crc; +} +#endif /* DEBUG */ + +#endif /* CONFIG_MPC512x_FEC */ diff --git a/cpu/mpc512x/fec.h b/cpu/mpc512x/fec.h new file mode 100644 index 0000000..d2d877a --- /dev/null +++ b/cpu/mpc512x/fec.h @@ -0,0 +1,224 @@ +/* + * (C) Copyright 2003 - 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Derived from the MPC8xx driver's header file. + */ + +#ifndef __MPC512X_FEC_H +#define __MPC512X_FEC_H + +#include <common.h> +#include <mpc512x.h> + +typedef unsigned long uint32; +typedef unsigned short uint16; +typedef unsigned char uint8; + +typedef struct ethernet_register_set { + +/* [10:2]addr = 00 */ + +/* Control and status Registers (offset 000-1FF) */ + + volatile uint32 fec_id; /* MBAR_ETH + 0x000 */ + volatile uint32 ievent; /* MBAR_ETH + 0x004 */ + volatile uint32 imask; /* MBAR_ETH + 0x008 */ + + volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */ + volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */ + volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */ + + volatile uint32 RES1[3]; /* MBAR_ETH + 0x018-020 */ + volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */ + + volatile uint32 RES2[6]; /* MBAR_ETH + 0x028-03C */ + volatile uint32 mii_data; /* MBAR_ETH + 0x040 */ + volatile uint32 mii_speed; /* MBAR_ETH + 0x044 */ + + volatile uint32 RES3[7]; /* MBAR_ETH + 0x048-060 */ + volatile uint32 mib_control; /* MBAR_ETH + 0x064 */ + + volatile uint32 RES4[7]; /* MBAR_ETH + 0x068-80 */ + volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */ + volatile uint32 r_hash; /* MBAR_ETH + 0x088 */ + + volatile uint32 RES5[14]; /* MBAR_ETH + 0x08c-0C0 */ + volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */ + + volatile uint32 RES6[7]; /* MBAR_ETH + 0x0C8-0E0 */ + volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */ + volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */ + volatile uint32 op_pause; /* MBAR_ETH + 0x0EC */ + + volatile uint32 RES7[10]; /* MBAR_ETH + 0x0F0-114 */ + volatile uint32 iaddr1; /* MBAR_ETH + 0x118 */ + volatile uint32 iaddr2; /* MBAR_ETH + 0x11C */ + volatile uint32 gaddr1; /* MBAR_ETH + 0x120 */ + volatile uint32 gaddr2; /* MBAR_ETH + 0x124 */ + + volatile uint32 RES8[6]; /* MBAR_ETH + 0x128-13C */ + volatile uint32 fifo_id; /* MBAR_ETH + 0x140 */ + volatile uint32 x_wmrk; /* MBAR_ETH + 0x144 */ + volatile uint32 RES9[1]; /* MBAR_ETH + 0x148 */ + volatile uint32 r_bound; /* MBAR_ETH + 0x14C */ + volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */ + + volatile uint32 RES10[11]; /* MBAR_ETH + 0x154-17C */ + volatile uint32 r_des_start; /* MBAR_ETH + 0x180 */ + volatile uint32 x_des_start; /* MBAR_ETH + 0x184 */ + volatile uint32 r_buff_size; /* MBAR_ETH + 0x188 */ + volatile uint32 RES11[26]; /* MBAR_ETH + 0x18C-1F0 */ + volatile uint32 dma_control; /* MBAR_ETH + 0x1F4 */ + volatile uint32 RES12[2]; /* MBAR_ETH + 0x1F8-1FC */ + +/* MIB COUNTERS (Offset 200-2FF) */ + + volatile uint32 rmon_t_drop; /* MBAR_ETH + 0x200 */ + volatile uint32 rmon_t_packets; /* MBAR_ETH + 0x204 */ + volatile uint32 rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */ + volatile uint32 rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */ + volatile uint32 rmon_t_crc_align; /* MBAR_ETH + 0x210 */ + volatile uint32 rmon_t_undersize; /* MBAR_ETH + 0x214 */ + volatile uint32 rmon_t_oversize; /* MBAR_ETH + 0x218 */ + volatile uint32 rmon_t_frag; /* MBAR_ETH + 0x21C */ + volatile uint32 rmon_t_jab; /* MBAR_ETH + 0x220 */ + volatile uint32 rmon_t_col; /* MBAR_ETH + 0x224 */ + volatile uint32 rmon_t_p64; /* MBAR_ETH + 0x228 */ + volatile uint32 rmon_t_p65to127; /* MBAR_ETH + 0x22C */ + volatile uint32 rmon_t_p128to255; /* MBAR_ETH + 0x230 */ + volatile uint32 rmon_t_p256to511; /* MBAR_ETH + 0x234 */ + volatile uint32 rmon_t_p512to1023; /* MBAR_ETH + 0x238 */ + volatile uint32 rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */ + volatile uint32 rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */ + volatile uint32 rmon_t_octets; /* MBAR_ETH + 0x244 */ + volatile uint32 ieee_t_drop; /* MBAR_ETH + 0x248 */ + volatile uint32 ieee_t_frame_ok; /* MBAR_ETH + 0x24C */ + volatile uint32 ieee_t_1col; /* MBAR_ETH + 0x250 */ + volatile uint32 ieee_t_mcol; /* MBAR_ETH + 0x254 */ + volatile uint32 ieee_t_def; /* MBAR_ETH + 0x258 */ + volatile uint32 ieee_t_lcol; /* MBAR_ETH + 0x25C */ + volatile uint32 ieee_t_excol; /* MBAR_ETH + 0x260 */ + volatile uint32 ieee_t_macerr; /* MBAR_ETH + 0x264 */ + volatile uint32 ieee_t_cserr; /* MBAR_ETH + 0x268 */ + volatile uint32 ieee_t_sqe; /* MBAR_ETH + 0x26C */ + volatile uint32 t_fdxfc; /* MBAR_ETH + 0x270 */ + volatile uint32 ieee_t_octets_ok; /* MBAR_ETH + 0x274 */ + + volatile uint32 RES13[2]; /* MBAR_ETH + 0x278-27C */ + volatile uint32 rmon_r_drop; /* MBAR_ETH + 0x280 */ + volatile uint32 rmon_r_packets; /* MBAR_ETH + 0x284 */ + volatile uint32 rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */ + volatile uint32 rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */ + volatile uint32 rmon_r_crc_align; /* MBAR_ETH + 0x290 */ + volatile uint32 rmon_r_undersize; /* MBAR_ETH + 0x294 */ + volatile uint32 rmon_r_oversize; /* MBAR_ETH + 0x298 */ + volatile uint32 rmon_r_frag; /* MBAR_ETH + 0x29C */ + volatile uint32 rmon_r_jab; /* MBAR_ETH + 0x2A0 */ + + volatile uint32 rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */ + + volatile uint32 rmon_r_p64; /* MBAR_ETH + 0x2A8 */ + volatile uint32 rmon_r_p65to127; /* MBAR_ETH + 0x2AC */ + volatile uint32 rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */ + volatile uint32 rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */ + volatile uint32 rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */ + volatile uint32 rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */ + volatile uint32 rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */ + volatile uint32 rmon_r_octets; /* MBAR_ETH + 0x2C4 */ + volatile uint32 ieee_r_drop; /* MBAR_ETH + 0x2C8 */ + volatile uint32 ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */ + volatile uint32 ieee_r_crc; /* MBAR_ETH + 0x2D0 */ + volatile uint32 ieee_r_align; /* MBAR_ETH + 0x2D4 */ + volatile uint32 r_macerr; /* MBAR_ETH + 0x2D8 */ + volatile uint32 r_fdxfc; /* MBAR_ETH + 0x2DC */ + volatile uint32 ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */ + + volatile uint32 RES14[6]; /* MBAR_ETH + 0x2E4-2FC */ + + volatile uint32 RES15[64]; /* MBAR_ETH + 0x300-3FF */ +} ethernet_regs; + +/* Receive & Transmit Buffer Descriptor definitions */ +typedef struct BufferDescriptor { + uint16 status; + uint16 dataLength; + uint32 dataPointer; +} FEC_RBD; + +typedef struct { + uint16 status; + uint16 dataLength; + uint32 dataPointer; +} FEC_TBD; + +/* private structure */ +typedef enum { + SEVENWIRE, /* 7-wire */ + MII10, /* MII 10Mbps */ + MII100 /* MII 100Mbps */ +} xceiver_type; + +/* BD Numer definitions */ +#define FEC_TBD_NUM 48 /* The user can adjust this value */ +#define FEC_RBD_NUM 32 /* The user can adjust this value */ + +/* packet size limit */ +#define FEC_MAX_PKT_SIZE 1536 + +typedef struct { + uint8 frame[FEC_MAX_PKT_SIZE]; +} mpc512x_frame; + +typedef struct { + FEC_RBD rbd[FEC_RBD_NUM]; /* RBD ring */ + FEC_TBD tbd[FEC_TBD_NUM]; /* TBD ring */ + mpc512x_frame recv_frames[FEC_RBD_NUM]; /* receive buff */ +} mpc512x_buff_descs; + +typedef struct { + ethernet_regs *eth; + xceiver_type xcv_type; /* transceiver type */ + mpc512x_buff_descs *bdBase; /* BD rings and recv buffer */ + uint16 rbdIndex; /* next receive BD to read */ + uint16 tbdIndex; /* next transmit BD to send */ + uint16 usedTbdIndex; /* next transmit BD to clean */ + uint16 cleanTbdNum; /* the number of available transmit BDs */ +} mpc512x_fec_priv; + +/* RBD bits definitions */ +#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */ +#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */ +#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */ +#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */ +#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */ +#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */ +#define FEC_RBD_LG 0x0020 /* Frame length violation */ +#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */ +#define FEC_RBD_SH 0x0008 /* Short frame */ +#define FEC_RBD_CR 0x0004 /* CRC error */ +#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */ +#define FEC_RBD_TR 0x0001 /* Frame is truncated */ +#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \ + FEC_RBD_OV | FEC_RBD_TR) + +/* TBD bits definitions */ +#define FEC_TBD_READY 0x8000 /* Buffer is ready */ +#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */ +#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */ +#define FEC_TBD_TC 0x0400 /* Transmit the CRC */ +#define FEC_TBD_ABC 0x0200 /* Append bad CRC */ + +/* MII-related definitios */ +#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ +#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ +#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ +#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ +#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ +#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */ +#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ + +#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ +#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ + +#endif /* __MPC512X_FEC_H */ diff --git a/cpu/mpc512x/i2c.c b/cpu/mpc512x/i2c.c new file mode 100644 index 0000000..00e28d6 --- /dev/null +++ b/cpu/mpc512x/i2c.c @@ -0,0 +1,431 @@ +/* + * (C) Copyright 2003 - 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Based on the MPC5xxx code. + */ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_HARD_I2C + +#include <mpc512x.h> +#include <i2c.h> + +#define immr ((immap_t *)CFG_IMMR) + +/* by default set I2C bus 0 active */ +static unsigned int bus_num = 0; + +#define I2C_TIMEOUT 100 +#define I2C_RETRIES 3 + +struct mpc512x_i2c_tap { + int scl2tap; + int tap2tap; +}; + +static int mpc_reg_in(volatile u32 *reg); +static void mpc_reg_out(volatile u32 *reg, int val, int mask); +static int wait_for_bb(void); +static int wait_for_pin(int *status); +static int do_address(uchar chip, char rdwr_flag); +static int send_bytes(uchar chip, char *buf, int len); +static int receive_bytes(uchar chip, char *buf, int len); +static int mpc_get_fdr(int); + +static int mpc_reg_in (volatile u32 *reg) +{ + int ret = *reg >> 24; + __asm__ __volatile__ ("eieio"); + return ret; +} + +static void mpc_reg_out (volatile u32 *reg, int val, int mask) +{ + int tmp; + + if (!mask) { + *reg = val << 24; + } else { + tmp = mpc_reg_in (reg); + *reg = ((tmp & ~mask) | (val & mask)) << 24; + } + __asm__ __volatile__ ("eieio"); + + return; +} + +static int wait_for_bb (void) +{ + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int timeout = I2C_TIMEOUT; + int status; + + status = mpc_reg_in (®s->msr); + + while (timeout-- && (status & I2C_BB)) { + volatile int temp; + mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); + temp = mpc_reg_in (®s->mdr); + mpc_reg_out (®s->mcr, 0, I2C_STA); + mpc_reg_out (®s->mcr, 0, 0); + mpc_reg_out (®s->mcr, I2C_EN, 0); + + udelay (1000); + status = mpc_reg_in (®s->msr); + } + + return (status & I2C_BB); +} + +static int wait_for_pin (int *status) +{ + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int timeout = I2C_TIMEOUT; + + *status = mpc_reg_in (®s->msr); + + while (timeout-- && !(*status & I2C_IF)) { + udelay (1000); + *status = mpc_reg_in (®s->msr); + } + + if (!(*status & I2C_IF)) { + return -1; + } + + mpc_reg_out (®s->msr, 0, I2C_IF); + + return 0; +} + +static int do_address (uchar chip, char rdwr_flag) +{ + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int status; + + chip <<= 1; + + if (rdwr_flag) { + chip |= 1; + } + + mpc_reg_out (®s->mcr, I2C_TX, I2C_TX); + mpc_reg_out (®s->mdr, chip, 0); + + if (wait_for_pin (&status)) { + return -2; + } + + if (status & I2C_RXAK) { + return -3; + } + + return 0; +} + +static int send_bytes (uchar chip, char *buf, int len) +{ + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int wrcount; + int status; + + for (wrcount = 0; wrcount < len; ++wrcount) { + + mpc_reg_out (®s->mdr, buf[wrcount], 0); + + if (wait_for_pin (&status)) { + break; + } + + if (status & I2C_RXAK) { + break; + } + + } + + return !(wrcount == len); +} + +static int receive_bytes (uchar chip, char *buf, int len) +{ + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int dummy = 1; + int rdcount = 0; + int status; + int i; + + mpc_reg_out (®s->mcr, 0, I2C_TX); + + for (i = 0; i < len; ++i) { + buf[rdcount] = mpc_reg_in (®s->mdr); + + if (dummy) { + dummy = 0; + } else { + rdcount++; + } + + if (wait_for_pin (&status)) { + return -4; + } + } + + mpc_reg_out (®s->mcr, I2C_TXAK, I2C_TXAK); + buf[rdcount++] = mpc_reg_in (®s->mdr); + + if (wait_for_pin (&status)) { + return -5; + } + + mpc_reg_out (®s->mcr, 0, I2C_TXAK); + + return 0; +} + +/**************** I2C API ****************/ + +void i2c_init (int speed, int saddr) +{ + int i; + for(i = 0; i < I2C_BUS_CNT; i++){ + i2c512x_dev_t *regs = &immr->i2c.dev[i]; + mpc_reg_out (®s->mcr, 0, 0); + + /* Set clock */ + mpc_reg_out (®s->mfdr, mpc_get_fdr (speed), 0); + mpc_reg_out (®s->madr, saddr << 1, 0); + + /* Enable module */ + mpc_reg_out (®s->mcr, I2C_EN, I2C_INIT_MASK); + mpc_reg_out (®s->msr, 0, I2C_IF); + } + + /* Disable interrupts */ + immr->i2c.icr = 0; + /* Turn off filters */ + immr->i2c.mifr = 0; + return; +} + +static int mpc_get_fdr (int speed) +{ + static int fdr = -1; + + if (fdr == -1) { + ulong best_speed = 0; + ulong divider; + ulong ipb, scl; + ulong bestmatch = 0xffffffffUL; + int best_i = 0, best_j = 0, i, j; + int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8}; + struct mpc512x_i2c_tap scltap[] = { + {4, 1}, + {4, 2}, + {6, 4}, + {6, 8}, + {14, 16}, + {30, 32}, + {62, 64}, + {126, 128} + }; + + ipb = gd->ipb_clk; + for (i = 7; i >= 0; i--) { + for (j = 7; j >= 0; j--) { + scl = 2 * (scltap[j].scl2tap + + (SCL_Tap[i] - 1) * scltap[j].tap2tap + + 2); + if (ipb <= speed*scl) { + if ((speed*scl - ipb) < bestmatch) { + bestmatch = speed*scl - ipb; + best_i = i; + best_j = j; + best_speed = ipb/scl; + } + } + } + } + divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2); + if (gd->flags & GD_FLG_RELOC) { + fdr = divider; + } else { + debug("%ld kHz, \n", best_speed / 1000); + return divider; + } + } + + return fdr; +} + +int i2c_probe (uchar chip) +{ + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int i; + + for (i = 0; i < I2C_RETRIES; i++) { + mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); + + if (! do_address (chip, 0)) { + mpc_reg_out (®s->mcr, 0, I2C_STA); + udelay (500); + break; + } + + mpc_reg_out (®s->mcr, 0, I2C_STA); + udelay (500); + } + + return (i == I2C_RETRIES); +} + +int i2c_read (uchar chip, uint addr, int alen, uchar *buf, int len) +{ + char xaddr[4]; + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int ret = -1; + + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + + if (wait_for_bb ()) { + printf ("i2c_read: bus is busy\n"); + goto Done; + } + + mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); + if (do_address (chip, 0)) { + printf ("i2c_read: failed to address chip\n"); + goto Done; + } + + if (send_bytes (chip, &xaddr[4-alen], alen)) { + printf ("i2c_read: send_bytes failed\n"); + goto Done; + } + + mpc_reg_out (®s->mcr, I2C_RSTA, I2C_RSTA); + if (do_address (chip, 1)) { + printf ("i2c_read: failed to address chip\n"); + goto Done; + } + + if (receive_bytes (chip, (char *)buf, len)) { + printf ("i2c_read: receive_bytes failed\n"); + goto Done; + } + + ret = 0; +Done: + mpc_reg_out (®s->mcr, 0, I2C_STA); + return ret; +} + +int i2c_write (uchar chip, uint addr, int alen, uchar *buf, int len) +{ + char xaddr[4]; + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int ret = -1; + + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + + if (wait_for_bb ()) { + printf ("i2c_write: bus is busy\n"); + goto Done; + } + + mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); + if (do_address (chip, 0)) { + printf ("i2c_write: failed to address chip\n"); + goto Done; + } + + if (send_bytes (chip, &xaddr[4-alen], alen)) { + printf ("i2c_write: send_bytes failed\n"); + goto Done; + } + + if (send_bytes (chip, (char *)buf, len)) { + printf ("i2c_write: send_bytes failed\n"); + goto Done; + } + + ret = 0; +Done: + mpc_reg_out (®s->mcr, 0, I2C_STA); + return ret; +} + +uchar i2c_reg_read (uchar chip, uchar reg) +{ + uchar buf; + + i2c_read (chip, reg, 1, &buf, 1); + + return buf; +} + +void i2c_reg_write (uchar chip, uchar reg, uchar val) +{ + i2c_write (chip, reg, 1, &val, 1); + + return; +} + + +int i2c_set_bus_num (unsigned int bus) +{ + if (bus >= I2C_BUS_CNT) { + return -1; + } + bus_num = bus; + + return 0; +} + +unsigned int i2c_get_bus_num (void) +{ + return bus_num; +} + +/* TODO */ +unsigned int i2c_get_bus_speed (void) +{ + return -1; +} + +int i2c_set_bus_speed (unsigned int speed) +{ + if (speed != CFG_I2C_SPEED) + return -1; + + return 0; +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc512x/interrupts.c b/cpu/mpc512x/interrupts.c new file mode 100644 index 0000000..8cc241c --- /dev/null +++ b/cpu/mpc512x/interrupts.c @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2000-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright 2004 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Derived from the MPC83xx code. + */ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct irq_action { + interrupt_handler_t *handler; + void *arg; + ulong count; +}; + +int interrupt_init_cpu (unsigned *decrementer_count) +{ + *decrementer_count = get_tbclk () / CFG_HZ; + + return 0; +} + +/* + * Install and free an interrupt handler. + */ +void +irq_install_handler (int irq, interrupt_handler_t * handler, void *arg) +{ +} + +void irq_free_handler (int irq) +{ +} + +void timer_interrupt_cpu (struct pt_regs *regs) +{ + /* nothing to do here */ + return; +} diff --git a/cpu/mpc512x/serial.c b/cpu/mpc512x/serial.c new file mode 100644 index 0000000..200ff2c --- /dev/null +++ b/cpu/mpc512x/serial.c @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2000 - 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Based ont the MPC5200 PSC driver. + * Adapted for MPC512x by Jan Wrobel <wrr@semihalf.com> + */ + +/* + * Minimal serial functions needed to use one of the PSC ports + * as serial console interface. + */ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_PSC_CONSOLE) + +static void fifo_init (volatile psc512x_t *psc) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + + /* reset Rx & Tx fifo slice */ + psc->rfcmd = PSC_FIFO_RESET_SLICE; + psc->tfcmd = PSC_FIFO_RESET_SLICE; + + /* disable Tx & Rx FIFO interrupts */ + psc->rfintmask = 0; + psc->tfintmask = 0; + + psc->tfsize = CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16); + psc->rfsize = CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16); + + /* enable Tx & Rx FIFO slice */ + psc->rfcmd = PSC_FIFO_ENABLE_SLICE; + psc->tfcmd = PSC_FIFO_ENABLE_SLICE; + + im->fifoc.fifoc_cmd = FIFOC_DISABLE_CLOCK_GATE; + __asm__ volatile ("sync"); +} + +int serial_init(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + unsigned long baseclk; + int div; + + fifo_init (psc); + + /* set MR register to point to MR1 */ + psc->command = PSC_SEL_MODE_REG_1; + + /* disable Tx/Rx */ + psc->command = PSC_TX_DISABLE | PSC_RX_DISABLE; + + /* choose the prescaler by 16 for the Tx/Rx clock generation */ + psc->psc_clock_select = 0xdd00; + + /* switch to UART mode */ + psc->sicr = 0; + + /* mode register points to mr1 */ + /* configure parity, bit length and so on in mode register 1*/ + psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; + /* now, mode register points to mr2 */ + psc->mode = PSC_MODE_1_STOPBIT; + + /* calculate dividor for setting PSC CTUR and CTLR registers */ + baseclk = (gd->ipb_clk + 8) / 16; + div = (baseclk + (gd->baudrate / 2)) / gd->baudrate; + + psc->ctur = (div >> 8) & 0xff; + /* set baudrate */ + psc->ctlr = div & 0xff; + + /* disable all interrupts */ + psc->psc_imr = 0; + + /* reset and enable Rx/Tx */ + psc->command = PSC_RST_RX; + psc->command = PSC_RST_TX; + psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE; + + return 0; +} + +void serial_putc (const char c) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + + if (c == '\n') + serial_putc ('\r'); + + /* Wait for last character to go. */ + while (!(psc->psc_status & PSC_SR_TXEMP)) + ; + + psc->tfdata_8 = c; +} + +void serial_putc_raw (const char c) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + + /* Wait for last character to go. */ + while (!(psc->psc_status & PSC_SR_TXEMP)) + ; + + psc->tfdata_8 = c; +} + + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int serial_getc (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + + /* Wait for a character to arrive. */ + while (psc->rfstat & PSC_FIFO_EMPTY) + ; + + return psc->rfdata_8; +} + +int serial_tstc (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + + return !(psc->rfstat & PSC_FIFO_EMPTY); +} + +void serial_setbrg (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + unsigned long baseclk, div; + + baseclk = (gd->csb_clk + 8) / 16; + div = (baseclk + (gd->baudrate / 2)) / gd->baudrate; + + psc->ctur = (div >> 8) & 0xFF; + psc->ctlr = div & 0xff; /* set baudrate */ +} + +void serial_setrts(int s) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + + if (s) { + /* Assert RTS (become LOW) */ + psc->op1 = 0x1; + } + else { + /* Negate RTS (become HIGH) */ + psc->op0 = 0x1; + } +} + +int serial_getcts(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + + return (psc->ip & 0x1) ? 0 : 1; +} +#endif /* CONFIG_PSC_CONSOLE */ diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c new file mode 100644 index 0000000..a609827 --- /dev/null +++ b/cpu/mpc512x/speed.c @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2000-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Based on the MPC83xx code. + */ + +#include <common.h> +#include <mpc512x.h> +#include <command.h> +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int spmf_mult[] = { + 68, 1, 12, 16, + 20, 24, 28, 32, + 36, 40, 44, 48, + 52, 56, 60, 64 +}; + +static int cpmf_mult[][2] = { + {0, 1}, {0, 1}, /* 0 and 1 are not valid */ + {1, 1}, {3, 2}, + {2, 1}, {5, 2}, + {3, 1}, {7, 2}, + {0, 1}, {0, 1}, /* and all above 7 are not valid too */ + {0, 1}, {0, 1}, + {0, 1}, {0, 1}, + {0, 1}, {0, 1} +}; + +static int sys_dividors[][2] = { + {2, 1}, {5, 2}, {3, 1}, {7, 2}, {4, 1}, + {9, 2}, {5, 1}, {7, 1}, {6, 1}, {8, 1}, + {9, 1}, {11, 1}, {10, 1}, {12, 1}, {13, 1}, + {15, 1}, {14, 1}, {16, 1}, {17, 1}, {19, 1}, + {18, 1}, {20, 1}, {21, 1}, {23, 1}, {22, 1}, + {24, 1}, {25, 1}, {27, 1}, {26, 1}, {28, 1}, + {29, 1}, {31, 1}, {30, 1}, {32, 1}, {33, 1} +}; + +int get_clocks (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u8 spmf; + u8 cpmf; + u8 sys_div; + u8 ips_div; + u32 ref_clk = CFG_MPC512X_CLKIN; + u32 spll; + u32 sys_clk; + u32 core_clk; + u32 csb_clk; + u32 ips_clk; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; + spll = ref_clk * spmf_mult[spmf]; + + sys_div = (im->clk.scfr[1] & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT; + sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0]; + + csb_clk = sys_clk / 2; + + cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT; + core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1]; + + ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT; + if (ips_div != 0) { + ips_clk = csb_clk / ips_div; + } else { + /* in case we cannot get a sane IPS divisor, fail gracefully */ + ips_clk = 0; + } + + gd->ipb_clk = ips_clk; + gd->csb_clk = csb_clk; + gd->cpu_clk = core_clk; + gd->bus_clk = csb_clk; + return 0; + +} + +/******************************************** + * get_bus_freq + * return system bus freq in Hz + *********************************************/ +ulong get_bus_freq (ulong dummy) +{ + return gd->csb_clk; +} + +int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + printf ("Clock configuration:\n"); + printf (" CPU: %4d MHz\n", gd->cpu_clk / 1000000); + printf (" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000); + printf (" IPS Bus: %4d MHz\n", gd->ipb_clk / 1000000); + printf (" DDR: %4d MHz\n", 2 * gd->csb_clk / 1000000); + return 0; +} + +U_BOOT_CMD(clocks, 1, 0, do_clocks, + "clocks - print clock configuration\n", + " clocks\n" +); + +int prt_mpc512x_clks (void) +{ + do_clocks (NULL, 0, 0, NULL); + return (0); +} diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S new file mode 100644 index 0000000..244c69b --- /dev/null +++ b/cpu/mpc512x/start.S @@ -0,0 +1,780 @@ +/* + * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> + * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> + * Copyright (C) 2000, 2001, 2002, 2007 Wolfgang Denk <wd@denx.de> + * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Based on the MPC83xx code. + */ + +/* + * U-Boot - Startup Code for MPC512x based Embedded Boards + */ + +#include <config.h> +#include <mpc512x.h> +#include <version.h> + +#define CONFIG_521X 1 /* needed for Linux kernel header files*/ + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#include <asm/cache.h> +#include <asm/mmu.h> + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "MPC512X" +#endif + +/* + * Floating Point enable, Machine Check and Recoverable Interr. + */ +#undef MSR_KERNEL +#ifdef DEBUG +#define MSR_KERNEL (MSR_FP|MSR_RI) +#else +#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) +#endif + +/* Macros for manipulating CSx_START/STOP */ +#define START_REG(start) ((start) >> 16) +#define STOP_REG(start, size) (((start) + (size) - 1) >> 16) + +/* + * Set up GOT: Global Offset Table + * + * Use r14 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) + + GOT_ENTRY(__init_end) + GOT_ENTRY(_end) + GOT_ENTRY(__bss_start) + END_GOT + +/* + * Magic number and version string + */ + .long 0x27051956 /* U-Boot Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii " ", CONFIG_IDENT_STRING, "\0" + +/* + * Vector Table + */ + .text + . = EXC_OFF_SYS_RESET + + .globl _start + /* Start from here after reset/power on */ +_start: + li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */ + b boot_cold + + .globl _start_of_vectors +_start_of_vectors: + +/* Machine check */ + STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) + +/* Data Storage exception. */ + STD_EXCEPTION(0x300, DataStorage, UnknownException) + +/* Instruction Storage exception. */ + STD_EXCEPTION(0x400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x500, ExtInterrupt, UnknownException) + +/* Alignment exception. */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG(SRR0, SRR1) + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_Alignment: + .long AlignmentException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Program check exception */ + . = 0x700 +ProgramCheck: + EXCEPTION_PROLOG(SRR0, SRR1) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_ProgramCheck: + .long ProgramCheckException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Floating Point Unit unavailable exception */ + STD_EXCEPTION(0x800, FPUnavailable, UnknownException) + +/* Decrementer */ + STD_EXCEPTION(0x900, Decrementer, timer_interrupt) + +/* Critical interrupt */ + STD_EXCEPTION(0xa00, Critical, UnknownException) + +/* System Call */ + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + +/* Trace interrupt */ + STD_EXCEPTION(0xd00, Trace, UnknownException) + +/* Performance Monitor interrupt */ + STD_EXCEPTION(0xf00, PerfMon, UnknownException) + +/* Intruction Translation Miss */ + STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) + +/* Data Load Translation Miss */ + STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) + +/* Data Store Translation Miss */ + STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) + +/* Instruction Address Breakpoint */ + STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException) + +/* System Management interrupt */ + STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException) + + .globl _end_of_vectors +_end_of_vectors: + + . = 0x3000 +boot_cold: + /* Save msr contents */ + mfmsr r5 + + /* Set IMMR area to our preferred location */ + lis r4, CONFIG_DEFAULT_IMMR@h + lis r3, CFG_IMMR@h + ori r3, r3, CFG_IMMR@l + stw r3, IMMRBAR(r4) + mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */ + + /* Initialise the machine */ + bl cpu_early_init + + /* + * Set up Local Access Windows: + * + * 1) Boot/CS0 (boot FLASH) + * 2) On-chip SRAM (initial stack purposes) + */ + + /* Boot CS/CS0 window range */ + lis r3, CFG_IMMR@h + ori r3, r3, CFG_IMMR@l + + lis r4, START_REG(CFG_FLASH_BASE) + ori r4, r4, STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE) + stw r4, LPCS0AW(r3) + + /* + * The SRAM window has a fixed size (256K), so only the start address + * is necessary + */ + lis r4, START_REG(CFG_SRAM_BASE) & 0xff00 + stw r4, SRAMBAR(r3) + + /* + * According to MPC5121e RM, configuring local access windows should + * be followed by a dummy read of the config register that was + * modified last and an isync + */ + lwz r4, SRAMBAR(r3) + isync + + /* + * Set configuration of the Boot/CS0, the SRAM window does not have a + * config register so no params can be set for it + */ + lis r3, (CFG_IMMR + LPC_OFFSET)@h + ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l + + lis r4, CFG_CS0_CFG@h + ori r4, r4, CFG_CS0_CFG@l + stw r4, CS0_CONFIG(r3) + + /* Master enable all CS's */ + lis r4, CS_CTRL_ME@h + ori r4, r4, CS_CTRL_ME@l + stw r4, CS_CTRL(r3) + + lis r4, (CFG_MONITOR_BASE)@h + ori r4, r4, (CFG_MONITOR_BASE)@l + addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET + mtlr r5 + blr + +in_flash: + lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h + ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l + + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + + /* let the C-code set up the rest */ + /* */ + /* Be careful to keep code relocatable & stack humble */ + /*------------------------------------------------------*/ + + GET_GOT /* initialize GOT access */ + + /* r3: IMMR */ + lis r3, CFG_IMMR@h + /* run low-level CPU init code (in Flash) */ + bl cpu_init_f + + /* r3: BOOTFLAG */ + mr r3, r21 + /* run 1st part of board init code (in Flash) */ + bl board_init_f + + /* NOTREACHED - board_init_f() does not return */ + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + +/* + * This code initialises the machine, it expects original MSR contents to be in r5. + */ +cpu_early_init: + /* Initialize machine status; enable machine check interrupt */ + /*-----------------------------------------------------------*/ + + li r3, MSR_KERNEL /* Set ME and RI flags */ + rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */ +#ifdef DEBUG + rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */ +#endif + mtmsr r3 + SYNC + mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */ + + lis r3, CFG_IMMR@h + +#if defined(CONFIG_WATCHDOG) + /* Initialise the watchdog and reset it */ + /*--------------------------------------*/ + lis r4, CFG_WATCHDOG_VALUE + ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) + stw r4, SWCRR(r3) + + /* reset */ + li r4, 0x556C + sth r4, SWSRR@l(r3) + li r4, 0x0 + ori r4, r4, 0xAA39 + sth r4, SWSRR@l(r3) +#else + /* Disable the watchdog */ + /*----------------------*/ + lwz r4, SWCRR(r3) + /* + * Check to see if it's enabled for disabling: once disabled by s/w + * it's not possible to re-enable it + */ + andi. r4, r4, 0x4 + beq 1f + xor r4, r4, r4 + stw r4, SWCRR(r3) +1: +#endif /* CONFIG_WATCHDOG */ + + /* Initialize the Hardware Implementation-dependent Registers */ + /* HID0 also contains cache control */ + /*------------------------------------------------------*/ + lis r3, CFG_HID0_INIT@h + ori r3, r3, CFG_HID0_INIT@l + SYNC + mtspr HID0, r3 + + lis r3, CFG_HID0_FINAL@h + ori r3, r3, CFG_HID0_FINAL@l + SYNC + mtspr HID0, r3 + + lis r3, CFG_HID2@h + ori r3, r3, CFG_HID2@l + SYNC + mtspr HID2, r3 + sync + blr + + +/* Cache functions. + * + * Note: requires that all cache bits in + * HID0 are in the low half word. + */ + .globl icache_enable +icache_enable: + mfspr r3, HID0 + ori r3, r3, HID0_ICE + lis r4, 0 + ori r4, r4, HID0_ILOCK + andc r3, r3, r4 + ori r4, r3, HID0_ICFI + isync + mtspr HID0, r4 /* sets enable and invalidate, clears lock */ + isync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl icache_disable +icache_disable: + mfspr r3, HID0 + lis r4, 0 + ori r4, r4, HID0_ICE|HID0_ILOCK + andc r3, r3, r4 + ori r4, r3, HID0_ICFI + isync + mtspr HID0, r4 /* sets invalidate, clears enable and lock*/ + isync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl icache_status +icache_status: + mfspr r3, HID0 + rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 + blr + + .globl dcache_enable +dcache_enable: + mfspr r3, HID0 + li r5, HID0_DCFI|HID0_DLOCK + andc r3, r3, r5 + mtspr HID0, r3 /* no invalidate, unlock */ + ori r3, r3, HID0_DCE + ori r5, r3, HID0_DCFI + mtspr HID0, r5 /* enable + invalidate */ + mtspr HID0, r3 /* enable */ + sync + blr + + .globl dcache_disable +dcache_disable: + mfspr r3, HID0 + lis r4, 0 + ori r4, r4, HID0_DCE|HID0_DLOCK + andc r3, r3, r4 + ori r4, r3, HID0_DCI + sync + mtspr HID0, r4 /* sets invalidate, clears enable and lock */ + sync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl dcache_status +dcache_status: + mfspr r3, HID0 + rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 + blr + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbf */ +/* Description: Data Cache block flush */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbf +ppcDcbf: + dcbf r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbi */ +/* Description: Data Cache block Invalidate */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbi +ppcDcbi: + dcbi r0,r3 + blr + +/*-------------------------------------------------------------------------- + * Function: ppcDcbz + * Description: Data Cache block zero. + * Input: r3 = effective address + * Output: none. + *-------------------------------------------------------------------------- */ + + .globl ppcDcbz +ppcDcbz: + dcbz r0,r3 + blr + + .globl ppcDWstore +ppcDWstore: + lfd 1, 0(r4) + stfd 1, 0(r3) + blr + + .globl ppcDWload +ppcDWload: + lfd 1, 0(r3) + stfd 1, 0(r4) + blr + +/*-------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + mr r1, r3 /* Set new stack pointer */ + mr r9, r4 /* Save copy of Global Data pointer */ + mr r10, r5 /* Save copy of Destination Address */ + + mr r3, r5 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + * + Destination Address + * + * Offset: + */ + sub r15, r10, r4 + + /* First our own GOT */ + add r14, r14, r15 + /* then the one used by the C code */ + add r30, r30, r15 + + /* + * Now relocate code + */ + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + la r8,-4(r4) + la r7,-4(r3) + + /* copy */ +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + + addi r0,r5,3 + srwi. r0,r0,2 + mtctr r0 + la r8,-4(r4) + la r7,-4(r3) + + /* and compare */ +20: lwzu r20,4(r8) + lwzu r21,4(r7) + xor. r22, r20, r21 + bne 30f + bdnz 20b + b 4f + + /* compare failed */ +30: li r3, 0 + blr + +2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + mtlr r0 + blr + +in_ram: + /* + * Relocation Function, r14 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + add r0,r0,r11 + stw r0,0(r3) + bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ +2: li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + add r0,r0,r11 + stw r10,0(r3) + stw r0,0(r4) + bdnz 3b +4: +clear_bss: + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(_end) + + cmplw 0, r3, r4 + beq 6f + + li r0, 0 +5: + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 + bne 5b +6: + mr r3, r9 /* Global Data pointer */ + mr r4, r10 /* Destination Address */ + bl board_init_r + + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) + + li r9, 0x100 /* reset vector at 0x100 */ + + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ + + mflr r4 /* save link register */ +1: + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r8, Alignment - _start + EXC_OFF_SYS_RESET +2: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r8, SystemCall - _start + EXC_OFF_SYS_RESET +3: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 3b + + li r7, .L_Trace - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET +4: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 4b + + mfmsr r3 /* now that the vectors have */ + lis r7, MSR_IP@h /* relocated into low memory */ + ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ + andc r3, r3, r7 /* (if it was on) */ + SYNC /* Some chip revs need this... */ + mtmsr r3 + SYNC + + mtlr r4 /* restore link register */ + blr + + /* + * Function: relocate entries for one exception vector + */ +trap_reloc: + lwz r0, 0(r7) /* hdlr ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 0(r7) + + lwz r0, 4(r7) /* int_return ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 4(r7) + + blr diff --git a/cpu/mpc512x/traps.c b/cpu/mpc512x/traps.c new file mode 100644 index 0000000..40281a2 --- /dev/null +++ b/cpu/mpc512x/traps.c @@ -0,0 +1,205 @@ +/* + * (C) Copyright 2000 - 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Derived from the MPC83xx code. + */ + +/* + * This file handles the architecture-dependent parts of hardware + * exceptions + */ + +#include <common.h> +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern unsigned long search_exception_table(unsigned long); + +#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) + +/* + * Trap & Exception support + */ + +void +print_backtrace (unsigned long *sp) +{ + int cnt = 0; + unsigned long i; + + puts ("Call backtrace: "); + while (sp) { + if ((uint)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + putc ('\n'); + printf ("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *) *sp; + } + putc ('\n'); +} + +void show_regs (struct pt_regs * regs) +{ + int i; + + printf ("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + printf ("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr & MSR_EE ? 1 : 0, regs->msr & MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr & MSR_ME ? 1 : 0, + regs->msr & MSR_IR ? 1 : 0, + regs->msr & MSR_DR ? 1 : 0); + + putc ('\n'); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) { + printf ("GPR%02d: ", i); + } + + printf ("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) { + putc ('\n'); + } + } +} + + +void +_exception (int signr, struct pt_regs *regs) +{ + show_regs (regs); + print_backtrace ((unsigned long *)regs->gpr[1]); + panic ("Exception at pc %lx signal %d", regs->nip,signr); +} + + +void +MachineCheckException (struct pt_regs *regs) +{ + unsigned long fixup; + + if ((fixup = search_exception_table (regs->nip)) != 0) { + regs->nip = fixup; + return; + } + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + puts ("Machine check.\nCaused by (from msr): "); + printf ("regs %p ",regs); + switch (regs->msr & 0x00FF0000) { + case (0x80000000 >> 10): + puts ("Instruction cache parity signal\n"); + break; + case (0x80000000 >> 11): + puts ("Data cache parity signal\n"); + break; + case (0x80000000 >> 12): + puts ("Machine check signal\n"); + break; + case (0x80000000 >> 13): + puts ("Transfer error ack signal\n"); + break; + case (0x80000000 >> 14): + puts ("Data parity signal\n"); + break; + case (0x80000000 >> 15): + puts ("Address parity signal\n"); + break; + default: + puts ("Unknown values in msr\n"); + } + show_regs (regs); + print_backtrace ((unsigned long *)regs->gpr[1]); + + panic ("machine check"); +} + +void +AlignmentException (struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs (regs); + print_backtrace ((unsigned long *)regs->gpr[1]); + panic ("Alignment Exception"); +} + +void +ProgramCheckException (struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs (regs); + print_backtrace ((unsigned long *)regs->gpr[1]); + panic ("Program Check Exception"); +} + +void +SoftEmuException (struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs (regs); + print_backtrace ((unsigned long *)regs->gpr[1]); + panic ("Software Emulation Exception"); +} + + +void +UnknownException (struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + printf ("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception (0, regs); +} + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +extern void do_bedbug_breakpoint (struct pt_regs *); +#endif + +void +DebugException (struct pt_regs *regs) +{ + printf ("Debugger trap at @ %lx\n", regs->nip ); + show_regs (regs); +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) + do_bedbug_breakpoint (regs); +#endif +} diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c index 727f954..1a4d2f2 100644 --- a/cpu/mpc5xxx/fec.c +++ b/cpu/mpc5xxx/fec.c @@ -889,13 +889,20 @@ int mpc5xxx_fec_initialize(bd_t * bis) fec->eth = (ethernet_regs *)MPC5XXX_FEC; fec->tbdBase = (FEC_TBD *)FEC_BD_BASE; fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD)); -#if defined(CONFIG_CANMB) || defined(CONFIG_HMI1001) || \ - defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \ - defined(CONFIG_JUPITER) || defined(CONFIG_MCC200) || \ - defined(CONFIG_MOTIONPRO)|| defined(CONFIG_O2DNT) || \ - defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \ - defined(CONFIG_TQM5200) || defined(CONFIG_UC101) || \ - defined(CONFIG_V38B) +#if defined(CONFIG_CANMB) || \ + defined(CONFIG_CM1_QP1) || \ + defined(CONFIG_HMI1001) || \ + defined(CONFIG_ICECUBE) || \ + defined(CONFIG_INKA4X0) || \ + defined(CONFIG_JUPITER) || \ + defined(CONFIG_MCC200) || \ + defined(CONFIG_MOTIONPRO) || \ + defined(CONFIG_O2DNT) || \ + defined(CONFIG_PM520) || \ + defined(CONFIG_TOP5200) || \ + defined(CONFIG_TQM5200) || \ + defined(CONFIG_UC101) || \ + defined(CONFIG_V38B) # ifndef CONFIG_FEC_10MBIT fec->xcv_type = MII100; # else diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index 4a31d32..6d6fba1 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -1017,7 +1017,7 @@ static int short_mem_test(void) */ for (i = 0; i < NUMMEMTESTS; i++) { for (j = 0; j < NUMMEMWORDS; j++) { - /*printf("bank enabled base:%x\n", &membase[j]);*/ + /* printf("bank enabled base:%x\n", &membase[j]); */ membase[j] = test[i][j]; ppcDcbf((unsigned long)&(membase[j])); } diff --git a/doc/README.sha1 b/doc/README.sha1 new file mode 100644 index 0000000..7992f7f --- /dev/null +++ b/doc/README.sha1 @@ -0,0 +1,57 @@ +SHA1 usage: +----------- + +In the U-Boot Image for the pcs440ep board is a SHA1 checksum integrated. +This SHA1 sum is used, to check, if the U-Boot Image in Flash is not +corrupted. + +The following command is available: + +=> help sha1 +sha1 address len [addr] calculate the SHA1 sum [save at addr] + -p calculate the SHA1 sum from the U-Boot image in flash and print + -c check the U-Boot image in flash + +"sha1 -p" + calculates and prints the SHA1 sum, from the Image stored in Flash + +"sha1 -c" + check, if the SHA1 sum from the Image stored in Flash is correct + + +It is possible to calculate a SHA1 checksum from a memoryrange with: + +"sha1 address len" + +If you want to store a new Image in Flash for the pcs440ep board, +which has no SHA1 sum, you can do the following: + +a) cp the new Image on a position in RAM (here 0x300000) + (for this example we use the Image from Flash, stored at 0xfffa0000 and + 0x60000 Bytes long) + +"cp.b fffa0000 300000 60000" + +b) Initialize the SHA1 sum in the Image with 0x00 + The SHA1 sum is stored in Flash at: + CFG_MONITOR_BASE + CFG_MONITOR_LEN + SHA1_SUM_POS + for the pcs440ep Flash: 0xfffa0000 + 0x60000 + -0x20 + = 0xffffffe0 + for the example in RAM: 0x300000 + 0x60000 + -0x20 + = 0x35ffe0 + + note: a SHA1 checksum is 20 bytes long. + +"mw.b 35ffe0 0 14" + +c) now calculate the SHA1 sum from the memoryrange and write + the calculated checksum at the right place: + +"sha1 300000 60000 35ffe0" + +Now you have a U-Boot-Image for the pcs440ep board with the correct SHA1 sum. + +If you do a "./MAKEALL pcs440ep" or a "make all" to get the U-Boot image, +the correct SHA1 sum will be automagically included in the U-Boot image. + +Heiko Schocher, 11 Jul 2007 diff --git a/drivers/nand_legacy/nand_legacy.c b/drivers/nand_legacy/nand_legacy.c index fcb6d2b..49d2ebb 100644 --- a/drivers/nand_legacy/nand_legacy.c +++ b/drivers/nand_legacy/nand_legacy.c @@ -15,13 +15,6 @@ #include <asm/io.h> #include <watchdog.h> -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include <status_led.h> -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - #if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) #include <linux/mtd/nand_legacy.h> diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h index d1bb159..de82399 100644 --- a/include/asm-ppc/e300.h +++ b/include/asm-ppc/e300.h @@ -9,6 +9,7 @@ #define PVR_E300C1 0x80830000 #define PVR_E300C2 0x80840000 #define PVR_E300C3 0x80850000 +#define PVR_E300C4 0x80860000 /* * Hardware Implementation-Dependent Register 0 (HID0) diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index cd24636..bbaeb3f 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -85,6 +85,10 @@ typedef struct global_data { unsigned long ipb_clk; unsigned long pci_clk; #endif +#if defined(CONFIG_MPC512X) + u32 ipb_clk; + u32 csb_clk; +#endif /* CONFIG_MPC512X */ #if defined(CONFIG_MPC8220) unsigned long bExtUart; unsigned long inp_clk; diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h new file mode 100644 index 0000000..23d10d4 --- /dev/null +++ b/include/asm-ppc/immap_512x.h @@ -0,0 +1,569 @@ +/* + * (C) Copyright 2007 DENX Software Engineering + * + * MPC512x Internal Memory Map + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Based on the MPC83xx header. + */ + +#ifndef __IMMAP_512x__ +#define __IMMAP_512x__ + +#include <asm/types.h> + +typedef struct law512x { + u32 bar; /* Base Addr Register */ + u32 ar; /* Attributes Register */ +} law521x_t; + +/* + * System configuration registers + */ +typedef struct sysconf512x { + u32 immrbar; /* Internal memory map base address register */ + u8 res0[0x1c]; + u32 lpbaw; /* LP Boot Access Window */ + u32 lpcs0aw; /* LP CS0 Access Window */ + u32 lpcs1aw; /* LP CS1 Access Window */ + u32 lpcs2aw; /* LP CS2 Access Window */ + u32 lpcs3aw; /* LP CS3 Access Window */ + u32 lpcs4aw; /* LP CS4 Access Window */ + u32 lpcs5aw; /* LP CS5 Access Window */ + u32 lpcs6aw; /* LP CS6 Access Window */ + u32 lpcs7aw; /* LP CS7 Access Window */ + u8 res1[0x1c]; + law521x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */ + u8 res2[0x28]; + law521x_t ddrlaw; /* DDR Local Access Window */ + u8 res3[0x18]; + u32 mbxbar; /* MBX Base Address */ + u32 srambar; /* SRAM Base Address */ + u32 nfcbar; /* NFC Base Address */ + u8 res4[0x34]; + u32 spridr; /* System Part and Revision ID Register */ + u32 spcr; /* System Priority Configuration Register */ + u8 res5[0xf8]; +} sysconf512x_t; + +/* + * Watch Dog Timer (WDT) Registers + */ +typedef struct wdt512x { + u8 res0[4]; + u32 swcrr; /* System watchdog control register */ + u32 swcnr; /* System watchdog count register */ + u8 res1[2]; + u16 swsrr; /* System watchdog service register */ + u8 res2[0xF0]; +} wdt512x_t; + +/* + * RTC Module Registers + */ +typedef struct rtclk512x { + u8 fixme[0x100]; +} rtclk512x_t; + +/* + * General Purpose Timer + */ +typedef struct gpt512x { + u8 fixme[0x100]; +} gpt512x_t; + +/* + * Integrated Programmable Interrupt Controller + */ +typedef struct ipic512x { + u8 fixme[0x100]; +} ipic512x_t; + +/* + * System Arbiter Registers + */ +typedef struct arbiter512x { + u32 acr; /* Arbiter Configuration Register */ + u32 atr; /* Arbiter Timers Register */ + u32 ater; /* Arbiter Transfer Error Register */ + u32 aer; /* Arbiter Event Register */ + u32 aidr; /* Arbiter Interrupt Definition Register */ + u32 amr; /* Arbiter Mask Register */ + u32 aeatr; /* Arbiter Event Attributes Register */ + u32 aeadr; /* Arbiter Event Address Register */ + u32 aerr; /* Arbiter Event Response Register */ + u8 res1[0xDC]; +} arbiter512x_t; + +/* + * Reset Module + */ +typedef struct reset512x { + u32 rcwl; /* Reset Configuration Word Low Register */ + u32 rcwh; /* Reset Configuration Word High Register */ + u8 res0[8]; + u32 rsr; /* Reset Status Register */ + u32 rmr; /* Reset Mode Register */ + u32 rpr; /* Reset protection Register */ + u32 rcr; /* Reset Control Register */ + u32 rcer; /* Reset Control Enable Register */ + u8 res1[0xDC]; +} reset512x_t; + +/* + * Clock Module + */ +typedef struct clk512x { + u32 spmr; /* System PLL Mode Register */ + u32 sccr[2]; /* System Clock Control Registers */ + u32 scfr[2]; /* System Clock Frequency Registers */ + u8 res0[4]; + u32 bcr; /* Bread Crumb Register */ + u32 pscccr[12]; /* PSC0-11 Clock Control Registers */ + u32 spccr; /* SPDIF Clock Control Registers */ + u32 cccr; /* CFM Clock Control Registers */ + u32 dccr; /* DIU Clock Control Registers */ + u8 res1[0xa8]; +} clk512x_t; + +/* + * Power Management Control Module + */ +typedef struct pmc512x { + u8 fixme[0x100]; +} pmc512x_t; + +/* + * General purpose I/O module + */ +typedef struct gpio512x { + u8 fixme[0x100]; +} gpio512x_t; + +/* + * DDR Memory Controller Memory Map + */ +typedef struct ddr512x { + u32 ddr_sys_config; /* System Configuration Register */ + u32 ddr_time_config0; /* Timing Configuration Register */ + u32 ddr_time_config1; /* Timing Configuration Register */ + u32 ddr_time_config2; /* Timing Configuration Register */ + u32 ddr_command; /* Command Register */ + u32 ddr_compact_command; /* Compact Command Register */ + u32 self_refresh_cmd_0; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_1; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_2; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_3; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_4; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */ + u32 DQS_config_offset_count; /* DQS Config Offset Count */ + u32 DQS_config_offset_time; /* DQS Config Offset Time */ + u32 DQS_delay_status; /* DQS Delay Status */ + u32 res0[0xF]; + u32 prioman_config1; /* Priority Manager Configuration */ + u32 prioman_config2; /* Priority Manager Configuration */ + u32 hiprio_config; /* High Priority Configuration */ + u32 lut_table0_main_upper; /* LUT0 Main Upper */ + u32 lut_table1_main_upper; /* LUT1 Main Upper */ + u32 lut_table2_main_upper; /* LUT2 Main Upper */ + u32 lut_table3_main_upper; /* LUT3 Main Upper */ + u32 lut_table4_main_upper; /* LUT4 Main Upper */ + u32 lut_table0_main_lower; /* LUT0 Main Lower */ + u32 lut_table1_main_lower; /* LUT1 Main Lower */ + u32 lut_table2_main_lower; /* LUT2 Main Lower */ + u32 lut_table3_main_lower; /* LUT3 Main Lower */ + u32 lut_table4_main_lower; /* LUT4 Main Lower */ + u32 lut_table0_alternate_upper; /* LUT0 Alternate Upper */ + u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */ + u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */ + u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */ + u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */ + u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */ + u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */ + u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */ + u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */ + u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */ + u32 performance_monitor_config; + u32 event_time_counter; + u32 event_time_preset; + u32 performance_monitor1_address_low; + u32 performance_monitor2_address_low; + u32 performance_monitor1_address_hi; + u32 performance_monitor2_address_hi; + u32 res1[2]; + u32 performance_monitor1_read_counter; + u32 performance_monitor2_read_counter; + u32 performance_monitor1_write_counter; + u32 performance_monitor2_write_counter; + u32 granted_ack_counter0; + u32 granted_ack_counter1; + u32 granted_ack_counter2; + u32 granted_ack_counter3; + u32 granted_ack_counter4; + u32 cumulative_wait_counter0; + u32 cumulative_wait_counter1; + u32 cumulative_wait_counter2; + u32 cumulative_wait_counter3; + u32 cumulative_wait_counter4; + u32 summed_priority_counter0; + u32 summed_priority_counter1; + u32 summed_priority_counter2; + u32 summed_priority_counter3; + u32 summed_priority_counter4; + u32 res2[0x3AD]; +} ddr512x_t; + + +/* + * DMA/Messaging Unit + */ +typedef struct dma512x { + u8 fixme[0x1800]; +} dma512x_t; + +/* + * PCI Software Configuration Registers + */ +typedef struct pciconf512x { + u8 fixme[0x80]; +} pciconf512x_t; + +/* + * Sequencer + */ +typedef struct ios512x { + u8 fixme[0x100]; +} ios512x_t; + +/* + * PCI Controller + */ +typedef struct pcictrl512x { + u8 fixme[0x100]; +} pcictrl512x_t; + + +/* + * MSCAN + */ +typedef struct mscan512x { + u8 fixme[0x100]; +} mscan512x_t; + +/* + * BDLC + */ +typedef struct bdlc512x { + u8 fixme[0x100]; +} bdlc512x_t; + +/* + * SDHC + */ +typedef struct sdhc512x { + u8 fixme[0x100]; +} sdhc512x_t; + +/* + * SPDIF + */ +typedef struct spdif512x { + u8 fixme[0x100]; +} spdif512x_t; + +/* + * I2C + */ +typedef struct i2c512x_dev { + volatile u32 madr; /* I2Cn + 0x00 */ + volatile u32 mfdr; /* I2Cn + 0x04 */ + volatile u32 mcr; /* I2Cn + 0x08 */ + volatile u32 msr; /* I2Cn + 0x0C */ + volatile u32 mdr; /* I2Cn + 0x10 */ + u8 res0[0x0C]; +} i2c512x_dev_t; + +typedef struct i2c512x { + i2c512x_dev_t dev[3]; + volatile u32 icr; + volatile u32 mifr; + u8 res0[0x98]; +} i2c512x_t; + +/* + * AXE + */ +typedef struct axe512x { + u8 fixme[0x100]; +} axe512x_t; + +/* + * DIU + */ +typedef struct diu512x { + u8 fixme[0x100]; +} diu512x_t; + +/* + * CFM + */ +typedef struct cfm512x { + u8 fixme[0x100]; +} cfm512x_t; + +/* + * FEC + */ +typedef struct fec512x { + u8 fixme[0x800]; +} fec512x_t; + +/* + * ULPI + */ +typedef struct ulpi512x { + u8 fixme[0x600]; +} ulpi512x_t; + +/* + * UTMI + */ +typedef struct utmi512x { + u8 fixme[0x3000]; +} utmi512x_t; + +/* + * PCI DMA + */ +typedef struct pcidma512x { + u8 fixme[0x300]; +} pcidma512x_t; + +/* + * IO Control + */ +typedef struct ioctrl512x { + u32 regs[0x400]; +} ioctrl512x_t; + +/* + * IIM + */ +typedef struct iim512x { + u8 fixme[0x1000]; +} iim512x_t; + +/* + * LPC + */ +typedef struct lpc512x { + u32 cs_cfg[8]; /* Chip Select N Configuration Registers + No dedicated entry for CS Boot as == CS0 */ + u32 cs_cr; /* Chip Select Control Register */ + u32 cs_sr; /* Chip Select Status Register */ + u32 cs_bcr; /* Chip Select Burst Control Register */ + u32 cs_dccr; /* Chip Select Deadcycle Control Register */ + u32 cs_hccr; /* Chip Select Holdcycle Control Register */ + u8 res0[0xcc]; + u32 sclpc_psr; /* SCLPC Packet Size Register */ + u32 sclpc_sar; /* SCLPC Start Address Register */ + u32 sclpc_cr; /* SCLPC Control Register */ + u32 sclpc_er; /* SCLPC Enable Register */ + u32 sclpc_nar; /* SCLPC NextAddress Register */ + u32 sclpc_sr; /* SCLPC Status Register */ + u32 sclpc_bdr; /* SCLPC Bytes Done Register */ + u32 emb_scr; /* EMB Share Counter Register */ + u32 emb_pcr; /* EMB Pause Control Register */ + u8 res1[0x1c]; + u32 lpc_fdwr; /* LPC RX/TX FIFO Data Word Register */ + u32 lpc_fsr; /* LPC RX/TX FIFO Status Register */ + u32 lpc_cr; /* LPC RX/TX FIFO Control Register */ + u32 lpc_ar; /* LPC RX/TX FIFO Alarm Register */ + u8 res2[0xb0]; +} lpc512x_t; + +/* + * PATA + */ +typedef struct pata512x { + u8 fixme[0x100]; +} pata512x_t; + +/* + * PSC + */ +typedef struct psc512x { + volatile u8 mode; /* PSC + 0x00 */ + volatile u8 res0[3]; + union { /* PSC + 0x04 */ + volatile u16 status; + volatile u16 clock_select; + } sr_csr; +#define psc_status sr_csr.status +#define psc_clock_select sr_csr.clock_select + volatile u16 res1; + volatile u8 command; /* PSC + 0x08 */ + volatile u8 res2[3]; + union { /* PSC + 0x0c */ + volatile u8 buffer_8; + volatile u16 buffer_16; + volatile u32 buffer_32; + } buffer; +#define psc_buffer_8 buffer.buffer_8 +#define psc_buffer_16 buffer.buffer_16 +#define psc_buffer_32 buffer.buffer_32 + union { /* PSC + 0x10 */ + volatile u8 ipcr; + volatile u8 acr; + } ipcr_acr; +#define psc_ipcr ipcr_acr.ipcr +#define psc_acr ipcr_acr.acr + volatile u8 res3[3]; + union { /* PSC + 0x14 */ + volatile u16 isr; + volatile u16 imr; + } isr_imr; +#define psc_isr isr_imr.isr +#define psc_imr isr_imr.imr + volatile u16 res4; + volatile u8 ctur; /* PSC + 0x18 */ + volatile u8 res5[3]; + volatile u8 ctlr; /* PSC + 0x1c */ + volatile u8 res6[3]; + volatile u32 ccr; /* PSC + 0x20 */ + volatile u8 res7[12]; + volatile u8 ivr; /* PSC + 0x30 */ + volatile u8 res8[3]; + volatile u8 ip; /* PSC + 0x34 */ + volatile u8 res9[3]; + volatile u8 op1; /* PSC + 0x38 */ + volatile u8 res10[3]; + volatile u8 op0; /* PSC + 0x3c */ + volatile u8 res11[3]; + volatile u32 sicr; /* PSC + 0x40 */ + volatile u8 res12[60]; + volatile u32 tfcmd; /* PSC + 0x80 */ + volatile u32 tfalarm; /* PSC + 0x84 */ + volatile u32 tfstat; /* PSC + 0x88 */ + volatile u32 tfintstat; /* PSC + 0x8C */ + volatile u32 tfintmask; /* PSC + 0x90 */ + volatile u32 tfcount; /* PSC + 0x94 */ + volatile u16 tfwptr; /* PSC + 0x98 */ + volatile u16 tfrptr; /* PSC + 0x9A */ + volatile u32 tfsize; /* PSC + 0x9C */ + volatile u8 res13[28]; + union { /* PSC + 0xBC */ + volatile u8 buffer_8; + volatile u16 buffer_16; + volatile u32 buffer_32; + } tfdata_buffer; +#define tfdata_8 tfdata_buffer.buffer_8 +#define tfdata_16 tfdata_buffer.buffer_16 +#define tfdata_32 tfdata_buffer.buffer_32 + + volatile u32 rfcmd; /* PSC + 0xC0 */ + volatile u32 rfalarm; /* PSC + 0xC4 */ + volatile u32 rfstat; /* PSC + 0xC8 */ + volatile u32 rfintstat; /* PSC + 0xCC */ + volatile u32 rfintmask; /* PSC + 0xD0 */ + volatile u32 rfcount; /* PSC + 0xD4 */ + volatile u16 rfwptr; /* PSC + 0xD8 */ + volatile u16 rfrptr; /* PSC + 0xDA */ + volatile u32 rfsize; /* PSC + 0xDC */ + volatile u8 res18[28]; + union { /* PSC + 0xFC */ + volatile u8 buffer_8; + volatile u16 buffer_16; + volatile u32 buffer_32; + } rfdata_buffer; +#define rfdata_8 rfdata_buffer.buffer_8 +#define rfdata_16 rfdata_buffer.buffer_16 +#define rfdata_32 rfdata_buffer.buffer_32 +} psc512x_t; + +/* + * FIFOC + */ +typedef struct fifoc512x { + u32 fifoc_cmd; + u32 fifoc_int; + u32 fifoc_dma; + u32 fifoc_axe; + u32 fifoc_debug; + u8 fixme[0xEC]; +} fifoc512x_t; + +/* + * SATA + */ +typedef struct sata512x { + u8 fixme[0x2000]; +} sata512x_t; + +typedef struct immap { + sysconf512x_t sysconf; /* System configuration */ + u8 res0[0x700]; + wdt512x_t wdt; /* Watch Dog Timer (WDT) */ + rtclk512x_t rtc; /* Real Time Clock Module */ + gpt512x_t gpt; /* General Purpose Timer */ + ipic512x_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter512x_t arbiter; /* CSB Arbiter */ + reset512x_t reset; /* Reset Module */ + clk512x_t clk; /* Clock Module */ + pmc512x_t pmc; /* Power Management Control Module */ + gpio512x_t gpio; /* General purpose I/O module */ + u8 res1[0x100]; + mscan512x_t mscan; /* MSCAN */ + bdlc512x_t bdlc; /* BDLC */ + sdhc512x_t sdhc; /* SDHC */ + spdif512x_t spdif; /* SPDIF */ + i2c512x_t i2c; /* I2C Controllers */ + u8 res2[0x800]; + axe512x_t axe; /* AXE */ + diu512x_t diu; /* Display Interface Unit */ + cfm512x_t cfm; /* Clock Frequency Measurement */ + u8 res3[0x500]; + fec512x_t fec; /* Fast Ethernet Controller */ + ulpi512x_t ulpi; /* USB ULPI */ + u8 res4[0xa00]; + utmi512x_t utmi; /* USB UTMI */ + u8 res5[0x1000]; + pcidma512x_t pci_dma; /* PCI DMA */ + pciconf512x_t pci_conf; /* PCI Configuration */ + u8 res6[0x80]; + ios512x_t ios; /* PCI Sequencer */ + pcictrl512x_t pci_ctrl; /* PCI Controller Control and Status */ + u8 res7[0xa00]; + ddr512x_t mddrc; /* Multi-port DDR Memory Controller */ + ioctrl512x_t io_ctrl; /* IO Control */ + iim512x_t iim; /* IC Identification module */ + u8 res8[0x4000]; + lpc512x_t lpc; /* LocalPlus Controller */ + pata512x_t pata; /* Parallel ATA */ + u8 res9[0xd00]; + psc512x_t psc[12]; /* PSCs */ + u8 res10[0x300]; + fifoc512x_t fifoc; /* FIFO Controller */ + u8 res11[0x2000]; + dma512x_t dma; /* DMA */ + u8 res12[0xa800]; + sata512x_t sata; /* Serial ATA */ + u8 res13[0xde000]; +} immap_t; +#endif /* __IMMAP_512x__ */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 9780fe1..71e2e84 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -58,7 +58,6 @@ #else #define MSR_KERNEL MSR_ME #endif -#define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE /* Floating Point Status and Control Register (FPSCR) Fields */ @@ -628,6 +627,12 @@ #define MAS6 SPRN_MAS6 #define MAS7 SPRN_MAS7 +#if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx) +#define DAR_DEAR DEAR +#else +#define DAR_DEAR DAR +#endif + /* Device Control Registers */ #define DCRN_BEAR 0x090 /* Bus Error Address Register */ diff --git a/include/common.h b/include/common.h index d89617a..ac29d3a 100644 --- a/include/common.h +++ b/include/common.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2004 + * (C) Copyright 2000-2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -67,6 +67,10 @@ typedef volatile unsigned char vu_char; #elif defined(CONFIG_MPC5xxx) #include <mpc5xxx.h> #define CONFIG_RELOC_FIXUP_WORKS +#elif defined(CONFIG_MPC512X) +#include <mpc512x.h> +#include <asm/immap_512x.h> +#define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_MPC8220) #include <asm/immap_8220.h> #define CONFIG_RELOC_FIXUP_WORKS @@ -455,6 +459,9 @@ int prt_8260_clks (void); #elif defined(CONFIG_MPC5xxx) int prt_mpc5xxx_clks (void); #endif +#if defined(CONFIG_MPC512x) +int prt_mpc512xxx_clks (void); +#endif #if defined(CONFIG_MPC8220) int prt_mpc8220_clks (void); #endif @@ -633,9 +640,13 @@ int fgetc(int file); int pcmcia_init (void); -#ifdef CONFIG_SHOW_BOOT_PROGRESS -void show_boot_progress (int status); +#ifdef CONFIG_STATUS_LED +# include <status_led.h> #endif +/* + * Board-specific Platform code can reimplement show_boot_progress () if needed + */ +void inline show_boot_progress (int val); #ifdef CONFIG_INIT_CRITICAL #error CONFIG_INIT_CRITICAL is deprecated! diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h new file mode 100644 index 0000000..89564a9 --- /dev/null +++ b/include/configs/ads5121.h @@ -0,0 +1,411 @@ +/* + * (C) Copyright 2007 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * ADS5121 board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define DEBUG +#undef DEBUG + +/* + * Memory map for the ADS5121 board: + * + * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB) + * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) + * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) + * 0x8200_0000 - 0x8200_001F CPLD (32 B) + * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) + */ + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC512X 1 /* MPC512X family */ + +#undef CONFIG_PCI + +#define CFG_MPC512X_CLKIN 66000000 /* in Hz */ + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ + +#define CFG_IMMR 0x80000000 + +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * DDR Setup - manually set all parameters as there's no SPD etc. + */ +#define CFG_DDR_SIZE 256 /* MB */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE + +/* DDR Controller Configuration + * + * SYS_CFG: + * [31:31] MDDRC Soft Reset: Diabled + * [30:30] DRAM CKE pin: Enabled + * [29:29] DRAM CLK: Enabled + * [28:28] Command Mode: Enabled (For initialization only) + * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] + * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] + * [20:19] Read Test: DON'T USE + * [18:18] Self Refresh: Enabled + * [17:17] 16bit Mode: Disabled + * [16:13] Ready Delay: 2 + * [12:12] Half DQS Delay: Disabled + * [11:11] Quarter DQS Delay: Disabled + * [10:08] Write Delay: 2 + * [07:07] Early ODT: Disabled + * [06:06] On DIE Termination: Disabled + * [05:05] FIFO Overflow Clear: DON'T USE here + * [04:04] FIFO Underflow Clear: DON'T USE here + * [03:03] FIFO Overflow Pending: DON'T USE here + * [02:02] FIFO Underlfow Pending: DON'T USE here + * [01:01] FIFO Overlfow Enabled: Enabled + * [00:00] FIFO Underflow Enabled: Enabled + * TIME_CFG0 + * [31:16] DRAM Refresh Time: 0 CSB clocks + * [15:8] DRAM Command Time: 0 CSB clocks + * [07:00] DRAM Precharge Time: 0 CSB clocks + * TIME_CFG1 + * [31:26] DRAM tRFC: + * [25:21] DRAM tWR1: + * [20:17] DRAM tWRT1: + * [16:11] DRAM tDRR: + * [10:05] DRAM tRC: + * [04:00] DRAM tRAS: + * TIME_CFG2 + * [31:28] DRAM tRCD: + * [27:23] DRAM tFAW: + * [22:19] DRAM tRTW1: + * [18:15] DRAM tCCD: + * [14:10] DRAM tRTP: + * [09:05] DRAM tRP: + * [04:00] DRAM tRPA + */ + +#define CFG_MDDRC_SYS_CFG 0xF8604200 +#define CFG_MDDRC_SYS_CFG_RUN 0xE8604200 +#define CFG_MDDRC_SYS_CFG_EN 0x30000000 +#define CFG_MDDRC_TIME_CFG0 0x0000281E +#define CFG_MDDRC_TIME_CFG0_RUN 0x01F4281E +#define CFG_MDDRC_TIME_CFG1 0x54EC1168 +#define CFG_MDDRC_TIME_CFG2 0x35210864 + +#define CFG_MICRON_NOP 0x01380000 +#define CFG_MICRON_PCHG_ALL 0x01100400 +#define CFG_MICRON_MR 0x01000022 +#define CFG_MICRON_EM2 0x01020000 +#define CFG_MICRON_EM3 0x01030000 +#define CFG_MICRON_EN_DLL 0x01010000 +#define CFG_MICRON_RST_DLL 0x01000932 +#define CFG_MICRON_RFSH 0x01080000 +#define CFG_MICRON_INIT_DEV_OP 0x01000832 +#define CFG_MICRON_OCD_DEFAULT 0x01010780 +#define CFG_MICRON_OCD_EXIT 0x01010400 + +/* DDR Priority Manager Configuration */ +#define CFG_MDDRCGRP_PM_CFG1 0x000777AA +#define CFG_MDDRCGRP_PM_CFG2 0x00000055 +#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000000 +#define CFG_MDDRCGRP_LUT0_MU 0x11111117 +#define CFG_MDDRCGRP_LUT0_ML 0x7777777A +#define CFG_MDDRCGRP_LUT1_MU 0x4444EEEE +#define CFG_MDDRCGRP_LUT1_ML 0xEEEEEEEE +#define CFG_MDDRCGRP_LUT2_MU 0x44444444 +#define CFG_MDDRCGRP_LUT2_ML 0x44444444 +#define CFG_MDDRCGRP_LUT3_MU 0x55555555 +#define CFG_MDDRCGRP_LUT3_ML 0x55555558 +#define CFG_MDDRCGRP_LUT4_MU 0x11111111 +#define CFG_MDDRCGRP_LUT4_ML 0x1111117C +#define CFG_MDDRCGRP_LUT0_AU 0x33333377 +#define CFG_MDDRCGRP_LUT0_AL 0x7777EEEE +#define CFG_MDDRCGRP_LUT1_AU 0x11111111 +#define CFG_MDDRCGRP_LUT1_AL 0x11111111 +#define CFG_MDDRCGRP_LUT2_AU 0x11111111 +#define CFG_MDDRCGRP_LUT2_AL 0x11111111 +#define CFG_MDDRCGRP_LUT3_AU 0x11111111 +#define CFG_MDDRCGRP_LUT3_AL 0x11111111 +#define CFG_MDDRCGRP_LUT4_AU 0x11111111 +#define CFG_MDDRCGRP_LUT4_AL 0x11111111 + +/* + * NOR FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH */ +#define CFG_FLASH_SIZE 0x04000000 /* max flash size in bytes */ +#define CFG_FLASH_USE_BUFFER_WRITE + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ + +#undef CFG_FLASH_CHECKSUM + +/* + * CPLD registers area is really only 32 bytes in size, but the smallest possible LP + * window is 64KB + */ +#define CFG_CPLD_BASE 0x82000000 +#define CFG_CPLD_SIZE 0x00010000 /* 64 KB */ + +#define CFG_SRAM_BASE 0x30000000 +#define CFG_SRAM_SIZE 0x00020000 /* 128 KB */ + +#define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */ +#define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ + +/* Use SRAM for initial stack */ +#define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END CFG_SRAM_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ +#if CONFIG_PSC_CONSOLE != 3 +#error CONFIG_PSC_CONSOLE must be 3 +#endif +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE +#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR +#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE +#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#if 0 +#define CFG_I2C_NOPROBES {{0,0x69}} * Don't probe these addrs */ +#endif + +/* + * Ethernet configuration + */ +#define CONFIG_MPC512x_FEC 1 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_ADDR 0x1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_ETHADDR 00:e0:5e:00:e5:14 + +#if 0 +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ +#endif + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +/* This has to be a multiple of the Flash sector size */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_NET \ + | CFG_CMD_PING \ + ) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_NET \ + | CFG_CMD_PING \ + | CFG_CMD_MII \ + | CFG_CMD_I2C) +#endif + +#include <cmd_confdefs.h> + +/* + * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock. + * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set + * to 0xFFFF, watchdog timeouts after about 64s. For details refer + * to chapter 36 of the MPC5121e Reference Manual. + */ +#define CONFIG_WATCHDOG /* enable watchdog */ +#define CFG_WATCHDOG_VALUE 0xFFFF + + /* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + + +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CFG_HID2 HID2_HBE + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_HOSTNAME ads5121 +#define CONFIG_ROOTPATH /nfsroot/rootfs +#define CONFIG_BOOTFILE uImage + +#define CONFIG_IPADDR 192.168.160.77 +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.0.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +//#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#define CONFIG_BOOTDELAY -1 +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "load=tftp 100000 /tftpboot/ads5121/u-boot.bin\0" \ + "update=protect off fff00000 fff3ffff; " \ + "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ + "upd=run load;run update\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#endif /* __CONFIG_H */ diff --git a/include/configs/cm1_qp1.h b/include/configs/cm1_qp1.h new file mode 100644 index 0000000..effa41c --- /dev/null +++ b/include/configs/cm1_qp1.h @@ -0,0 +1,358 @@ +/* + * (C) Copyright 2003-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_CM1_QP1 1 /* ... on CM1.QP1 module */ + + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_I2C | \ + CFG_CMD_FLASH | \ + CFG_CMD_MII | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_DIAG | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SNTP | \ + CFG_CMD_BSP | \ + CFG_CMD_USB | \ + CFG_CMD_FAT | \ + CFG_CMD_JFFS2) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 57600 /* ... at 57600 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */ +/* use misc_init_r() to read ethaddr from I2C EEPROM (see CFG_I2C_EEPROM) */ +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */ + + +/* + * POST support + */ +#define CONFIG_POST (CFG_POST_MEMORY | CFG_POST_CPU | CFG_POST_I2C) +#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) +/* List of I2C addresses to be verified by POST */ +#define I2C_ADDR_LIST { CFG_I2C_SLAVE, CFG_I2C_IO, CFG_I2C_EEPROM } + + +/* display image timestamps */ +#define CONFIG_TIMESTAMP 1 + + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \ + "echo" +#undef CONFIG_BOOTARGS + +/* + * Default environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=cm1_qp1\0" \ + "netmask=255.255.0.0\0" \ + "ipaddr=192.168.160.33\0" \ + "serverip=192.168.1.1\0" \ + "gatewayip=192.168.1.1\0" \ + "console=ttyPSC0\0" \ + "u-boot_addr=100000\0" \ + "kernel_addr=200000\0" \ + "kernel_addr_flash=fc0c0000\0" \ + "fdt_addr=400000\0" \ + "fdt_addr_flash=fc0a0000\0" \ + "ramdisk_addr=500000\0" \ + "rootpath=/opt/eldk-4.1/ppc_6xx\0" \ + "u-boot=/tftpboot/cm1_qp1/u-boot.bin\0" \ + "bootfile=/tftpboot/cm1_qp1/uImage\0" \ + "fdt_file=/tftpboot/cm1_qp1/cm1_qp1.dtb\0" \ + "load=tftp ${u-boot_addr} ${u-boot}\0" \ + "update=prot off fc000000 fc05ffff; era fc000000 fc05ffff; " \ + "cp.b ${u-boot_addr} fc000000 ${filesize}; " \ + "prot on fc000000 fc05ffff\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \ + "addcons=setenv bootargs ${bootargs} " \ + "console=${console},${baudrate}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off panic=1\0" \ + "flash_flash=run flashargs addinit addip addcons;" \ + "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \ + "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \ + "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \ + "addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_flash" + + +/* + * Low level configuration + */ + + +/* + * Clock configuration + */ +#define CFG_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */ +#define CFG_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */ + + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +#define CFG_LOWBOOT 1 + +/* Use ON-Chip SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#ifdef CONFIG_POST +/* preserve space for the post_word at end of on-chip SRAM */ +#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE +#else +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE +#endif + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT 1 +#endif + + +/* + * Chip selects configuration + */ +/* Boot Chipselect */ +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */ +/* use board_early_init_r to enable flash write in CS_BOOT */ +#define CONFIG_BOARD_EARLY_INIT_R + +/* Flash memory addressing */ +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +/* No burst, dead cycle = 1 for CS0 (Flash) */ +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x00000001 + + +/* + * SDRAM configuration + * settings for k4s561632E-xx75, assuming XLB = 132 MHz + */ +#define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */ +#define SDRAM_CONTROL 0x514F0000 +#define SDRAM_CONFIG1 0xE2333900 +#define SDRAM_CONFIG2 0x8EE70000 + + +/* + * Flash configuration + */ +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#define CFG_FLASH_BASE TEXT_BASE +/* we need these despite using CFI */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 256 /* max num of sectors on one chip */ +#define CFG_FLASH_SIZE 0x02000000 /* 32 MiB */ + + +/* + * MTD configuration + */ +#define CONFIG_JFFS2_CMDLINE 1 +#define MTDIDS_DEFAULT "nor0=cm1qp1-0" +#define MTDPARTS_DEFAULT "mtdparts=cm1qp1-0:" \ + "384k(uboot),128k(env)," \ + "128k(redund_env),128k(dtb)," \ + "2m(kernel),27904k(rootfs)," \ + "-(config)" + + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #2 */ +#define CFG_I2C_SPEED 40000 /* 40 kHz */ +#define CFG_I2C_SLAVE 0x0 +#define CFG_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */ +#define CFG_I2C_EEPROM 0x53 /* I2C EEPROM device address */ + + +/* + * RTC configuration + */ +#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ + + +/* + * USB configuration + */ +#define CONFIG_USB_OHCI 1 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 +/* Partitions (for USB) */ +#define CONFIG_MAC_PARTITION 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_ISO_PARTITION 1 + +/* + * Invoke our last_stage_init function - needed by fwupdate + */ +#define CONFIG_LAST_STAGE_INIT 1 + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) +/* Configuration of redundant environment */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + + +/* + * Pin multiplexing configuration + */ + +/* + * CS1/GPIO_WKUP_6: GPIO (default) + * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1 + * IRDA/PSC6: UART + * Ether: Ethernet 100Mbit with MD + * PCI_DIS: PCI controller disabled + * USB: USB + * PSC3: SPI with UART3 + * PSC2: UART + * PSC1: UART + */ +#define CFG_GPS_PORT_CONFIG 0x10559C44 + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_ALT_MEMTEST 1 +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */ + +#define CONFIG_LOOPW 1 + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + + +/* + * Various low-level settings + */ +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_XLB_PIPELINING 1 /* enable transaction pipeling */ + + +/* + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + +/* + * Flat Device Tree support + */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define OF_FLAT_TREE_MAX_SIZE 8192 /* max size of the flat tree (8K) */ +#define OF_CPU "PowerPC,5200@0" +#define OF_SOC "soc5200@f0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" + +#endif /* __CONFIG_H */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 0b79de0..8e51d2d 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -197,16 +197,16 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ #define CONFIG_BOARD_SPECIFIC_LED 1 -#define STATUS_LED_BIT 0x08 /* LED 1 is on GPIO_PPC_1 */ +#define STATUS_LED_BIT 0x08 /* DIAG1 is on GPIO_PPC_1 */ #define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ #define STATUS_LED_STATE STATUS_LED_OFF -#define STATUS_LED_BIT1 0x04 /* LED 2 is on GPIO_PPC_2 */ +#define STATUS_LED_BIT1 0x04 /* DIAG2 is on GPIO_PPC_2 */ #define STATUS_LED_PERIOD1 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ #define STATUS_LED_STATE1 STATUS_LED_ON -#define STATUS_LED_BIT2 0x02 /* LED 3 is on GPIO_PPC_3 */ +#define STATUS_LED_BIT2 0x02 /* DIAG3 is on GPIO_PPC_3 */ #define STATUS_LED_PERIOD2 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ #define STATUS_LED_STATE2 STATUS_LED_OFF -#define STATUS_LED_BIT3 0x01 /* LED 4 is on GPIO_PPC_4 */ +#define STATUS_LED_BIT3 0x01 /* DIAG4 is on GPIO_PPC_4 */ #define STATUS_LED_PERIOD3 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ #define STATUS_LED_STATE3 STATUS_LED_OFF diff --git a/include/mpc512x.h b/include/mpc512x.h new file mode 100644 index 0000000..a100b22 --- /dev/null +++ b/include/mpc512x.h @@ -0,0 +1,398 @@ +/* + * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * (C) Copyright 2007 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * Derived from the MPC83xx header. + */ + +#ifndef __MPC512X_H__ +#define __MPC512X_H__ + +#include <config.h> +#if defined(CONFIG_E300) +#include <asm/e300.h> +#endif + +/* System reset offset (PowerPC standard) + */ +#define EXC_OFF_SYS_RESET 0x0100 +#define _START_OFFSET EXC_OFF_SYS_RESET + + +/* IMMRBAR - Internal Memory Register Base Address + */ +#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ +#define IMMRBAR 0x0000 /* Register offset to immr */ +#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ +#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) + +/* LAWBAR - Local Access Window Base Address Register + */ +#define LPBAW 0x0020 /* Register offset to immr */ +#define LPCS0AW 0x0024 +#define LPCS1AW 0x0028 +#define LPCS2AW 0x002C +#define LPCS3AW 0x0030 +#define LPCS4AW 0x0034 +#define LPCS5AW 0x0038 +#define LPCS6AW 0x003C +#define LPCA7AW 0x0040 +#define SRAMBAR 0x00C4 + +#define LPC_OFFSET 0x10000 + +#define CS0_CONFIG 0x00000 +#define CS1_CONFIG 0x00004 +#define CS2_CONFIG 0x00008 +#define CS3_CONFIG 0x0000C +#define CS4_CONFIG 0x00010 +#define CS5_CONFIG 0x00014 +#define CS6_CONFIG 0x00018 +#define CS7_CONFIG 0x0001C + +#define CS_CTRL 0x00020 +#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */ +#define CS_CTRL_IE 0x08000000 /* CS Interrupt Enable bit */ + +/* SPRIDR - System Part and Revision ID Register + */ +#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ +#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ + +#define SPR_5121E 0x80180000 + +/* SPCR - System Priority Configuration Register + */ +#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ +#define SPCR_PCIHPE_SHIFT (31-3) +#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ +#define SPCR_PCIPR_SHIFT (31-7) +#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ +#define SPCR_TBEN_SHIFT (31-9) +#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ +#define SPCR_COREPR_SHIFT (31-11) + +/* SWCRR - System Watchdog Control Register + */ +#define SWCRR 0x0904 /* Register offset to immr */ +#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ +#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ +#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ +#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ +#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) + +/* SWCNR - System Watchdog Counter Register + */ +#define SWCNR 0x0908 /* Register offset to immr */ +#define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ +#define SWCNR_RES ~(SWCNR_SWCN) + +/* SWSRR - System Watchdog Service Register + */ +#define SWSRR 0x090E /* Register offset to immr */ + +/* ACR - Arbiter Configuration Register + */ +#define ACR_COREDIS 0x10000000 /* Core disable */ +#define ACR_COREDIS_SHIFT (31-7) +#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ +#define ACR_PIPE_DEP_SHIFT (31-15) +#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ +#define ACR_PCI_RPTCNT_SHIFT (31-19) +#define ACR_RPTCNT 0x00000700 /* Repeat count */ +#define ACR_RPTCNT_SHIFT (31-23) +#define ACR_APARK 0x00000030 /* Address parking */ +#define ACR_APARK_SHIFT (31-27) +#define ACR_PARKM 0x0000000F /* Parking master */ +#define ACR_PARKM_SHIFT (31-31) + +/* ATR - Arbiter Timers Register + */ +#define ATR_DTO 0x00FF0000 /* Data time out */ +#define ATR_ATO 0x000000FF /* Address time out */ + +/* AER - Arbiter Event Register + */ +#define AER_ETEA 0x00000020 /* Transfer error */ +#define AER_RES 0x00000010 /* Reserved transfer type */ +#define AER_ECW 0x00000008 /* External control word transfer type */ +#define AER_AO 0x00000004 /* Address Only transfer type */ +#define AER_DTO 0x00000002 /* Data time out */ +#define AER_ATO 0x00000001 /* Address time out */ + +/* AEATR - Arbiter Event Address Register + */ +#define AEATR_EVENT 0x07000000 /* Event type */ +#define AEATR_MSTR_ID 0x001F0000 /* Master Id */ +#define AEATR_TBST 0x00000800 /* Transfer burst */ +#define AEATR_TSIZE 0x00000700 /* Transfer Size */ +#define AEATR_TTYPE 0x0000001F /* Transfer Type */ + +/* RSR - Reset Status Register + */ +#define RSR_SWSR 0x00002000 /* software soft reset */ +#define RSR_SWSR_SHIFT 13 +#define RSR_SWHR 0x00001000 /* software hard reset */ +#define RSR_SWHR_SHIFT 12 +#define RSR_JHRS 0x00000200 /* jtag hreset */ +#define RSR_JHRS_SHIFT 9 +#define RSR_JSRS 0x00000100 /* jtag sreset status */ +#define RSR_JSRS_SHIFT 8 +#define RSR_CSHR 0x00000010 /* checkstop reset status */ +#define RSR_CSHR_SHIFT 4 +#define RSR_SWRS 0x00000008 /* software watchdog reset status */ +#define RSR_SWRS_SHIFT 3 +#define RSR_BMRS 0x00000004 /* bus monitop reset status */ +#define RSR_BMRS_SHIFT 2 +#define RSR_SRS 0x00000002 /* soft reset status */ +#define RSR_SRS_SHIFT 1 +#define RSR_HRS 0x00000001 /* hard reset status */ +#define RSR_HRS_SHIFT 0 +#define RSR_RES ~(RSR_SWSR | RSR_SWHR |\ + RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ + RSR_BMRS | RSR_SRS | RSR_HRS) +/* RMR - Reset Mode Register + */ +#define RMR_CSRE 0x00000001 /* checkstop reset enable */ +#define RMR_CSRE_SHIFT 0 +#define RMR_RES ~(RMR_CSRE) + +/* RCR - Reset Control Register + */ +#define RCR_SWHR 0x00000002 /* software hard reset */ +#define RCR_SWSR 0x00000001 /* software soft reset */ +#define RCR_RES ~(RCR_SWHR | RCR_SWSR) + +/* RCER - Reset Control Enable Register + */ +#define RCER_CRE 0x00000001 /* software hard reset */ +#define RCER_RES ~(RCER_CRE) + +/* SPMR - System PLL Mode Register + */ +#define SPMR_SPMF 0x0F000000 +#define SPMR_SPMF_SHIFT 24 +#define SPMR_CPMF 0x000F0000 +#define SPMR_CPMF_SHIFT 16 + +/* SCFR1 System Clock Frequency Register 1 + */ +#define SCFR1_IPS_DIV 0x2 +#define SCFR1_IPS_DIV_MASK 0x03800000 +#define SCFR1_IPS_DIV_SHIFT 23 + +/* SCFR2 System Clock Frequency Register 2 + */ +#define SCFR2_SYS_DIV 0xFC000000 +#define SCFR2_SYS_DIV_SHIFT 26 + +/* SCCR - System Clock Control Registers + */ + +/* System Clock Control Register 1 commands */ +#define CLOCK_SCCR1_CFG_EN 0x80000000 +#define CLOCK_SCCR1_LPC_EN 0x40000000 +#define CLOCK_SCCR1_NFC_EN 0x20000000 +#define CLOCK_SCCR1_PATA_EN 0x10000000 +#define CLOCK_SCCR1_PSC_EN(cn) (0x08000000 >> (cn)) +#define CLOCK_SCCR1_PSCFIFO_EN 0x00008000 +#define CLOCK_SCCR1_SATA_EN 0x00004000 +#define CLOCK_SCCR1_FEC_EN 0x00002000 +#define CLOCK_SCCR1_TPR_EN 0x00001000 +#define CLOCK_SCCR1_PCI_EN 0x00000800 +#define CLOCK_SCCR1_DDR_EN 0x00000400 + +/* System Clock Control Register 2 commands */ +#define CLOCK_SCCR2_DIU_EN 0x80000000 +#define CLOCK_SCCR2_AXE_EN 0x40000000 +#define CLOCK_SCCR2_MEM_EN 0x20000000 +#define CLOCK_SCCR2_USB2_EN 0x10000000 +#define CLOCK_SCCR2_USB1_EN 0x08000000 +#define CLOCK_SCCR2_I2C_EN 0x04000000 +#define CLOCK_SCCR2_BDLC_EN 0x02000000 +#define CLOCK_SCCR2_SDHC_EN 0x01000000 +#define CLOCK_SCCR2_SPDIF_EN 0x00800000 +#define CLOCK_SCCR2_MBX_BUS_EN 0x00400000 +#define CLOCK_SCCR2_MBX_EN 0x00200000 +#define CLOCK_SCCR2_MBX_3D_EN 0x00100000 +#define CLOCK_SCCR2_IIM_EN 0x00080000 + +/* PSC FIFO Command values */ +#define PSC_FIFO_RESET_SLICE 0x80 +#define PSC_FIFO_ENABLE_SLICE 0x01 + +/* PSC FIFO Controller Command values */ +#define FIFOC_ENABLE_CLOCK_GATE 0x01 +#define FIFOC_DISABLE_CLOCK_GATE 0x00 + +/* PSC FIFO status */ +#define PSC_FIFO_EMPTY 0x01 + +/* PSC Command values */ +#define PSC_RX_ENABLE 0x01 +#define PSC_RX_DISABLE 0x02 +#define PSC_TX_ENABLE 0x04 +#define PSC_TX_DISABLE 0x08 +#define PSC_SEL_MODE_REG_1 0x10 +#define PSC_RST_RX 0x20 +#define PSC_RST_TX 0x30 +#define PSC_RST_ERR_STAT 0x40 +#define PSC_RST_BRK_CHG_INT 0x50 +#define PSC_START_BRK 0x60 +#define PSC_STOP_BRK 0x70 + +/* PSC status register bits */ +#define PSC_SR_CDE 0x0080 +#define PSC_SR_TXEMP 0x0800 +#define PSC_SR_OE 0x1000 +#define PSC_SR_PE 0x2000 +#define PSC_SR_FE 0x4000 +#define PSC_SR_RB 0x8000 + +/* PSC mode fields */ +#define PSC_MODE_5_BITS 0x00 +#define PSC_MODE_6_BITS 0x01 +#define PSC_MODE_7_BITS 0x02 +#define PSC_MODE_8_BITS 0x03 +#define PSC_MODE_PAREVEN 0x00 +#define PSC_MODE_PARODD 0x04 +#define PSC_MODE_PARFORCE 0x08 +#define PSC_MODE_PARNONE 0x10 +#define PSC_MODE_ENTIMEOUT 0x20 +#define PSC_MODE_RXRTS 0x80 +#define PSC_MODE_1_STOPBIT 0x07 + +/* + * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs + * + * NOTE: individual PSC units are free to use whatever area (and size) of the + * FIFOC internal memory, so make sure memory areas for FIFO slices used by + * different PSCs do not overlap! + * + * Overall size of FIFOC memory is not documented in the MPC5121e RM, but + * tests indicate that it is 1024 words total. + */ +#define FIFOC_PSC0_TX_SIZE 0x0 /* number of 4-byte words for FIFO slice */ +#define FIFOC_PSC0_TX_ADDR 0x0 +#define FIFOC_PSC0_RX_SIZE 0x0 +#define FIFOC_PSC0_RX_ADDR 0x0 + +#define FIFOC_PSC1_TX_SIZE 0x0 +#define FIFOC_PSC1_TX_ADDR 0x0 +#define FIFOC_PSC1_RX_SIZE 0x0 +#define FIFOC_PSC1_RX_ADDR 0x0 + +#define FIFOC_PSC2_TX_SIZE 0x0 +#define FIFOC_PSC2_TX_ADDR 0x0 +#define FIFOC_PSC2_RX_SIZE 0x0 +#define FIFOC_PSC2_RX_ADDR 0x0 + +#define FIFOC_PSC3_TX_SIZE 0x04 +#define FIFOC_PSC3_TX_ADDR 0x0 +#define FIFOC_PSC3_RX_SIZE 0x04 +#define FIFOC_PSC3_RX_ADDR 0x10 + +#define FIFOC_PSC4_TX_SIZE 0x0 +#define FIFOC_PSC4_TX_ADDR 0x0 +#define FIFOC_PSC4_RX_SIZE 0x0 +#define FIFOC_PSC4_RX_ADDR 0x0 + +#define FIFOC_PSC5_TX_SIZE 0x0 +#define FIFOC_PSC5_TX_ADDR 0x0 +#define FIFOC_PSC5_RX_SIZE 0x0 +#define FIFOC_PSC5_RX_ADDR 0x0 + +#define FIFOC_PSC6_TX_SIZE 0x0 +#define FIFOC_PSC6_TX_ADDR 0x0 +#define FIFOC_PSC6_RX_SIZE 0x0 +#define FIFOC_PSC6_RX_ADDR 0x0 + +#define FIFOC_PSC7_TX_SIZE 0x0 +#define FIFOC_PSC7_TX_ADDR 0x0 +#define FIFOC_PSC7_RX_SIZE 0x0 +#define FIFOC_PSC7_RX_ADDR 0x0 + +#define FIFOC_PSC8_TX_SIZE 0x0 +#define FIFOC_PSC8_TX_ADDR 0x0 +#define FIFOC_PSC8_RX_SIZE 0x0 +#define FIFOC_PSC8_RX_ADDR 0x0 + +#define FIFOC_PSC9_TX_SIZE 0x0 +#define FIFOC_PSC9_TX_ADDR 0x0 +#define FIFOC_PSC9_RX_SIZE 0x0 +#define FIFOC_PSC9_RX_ADDR 0x0 + +#define FIFOC_PSC10_TX_SIZE 0x0 +#define FIFOC_PSC10_TX_ADDR 0x0 +#define FIFOC_PSC10_RX_SIZE 0x0 +#define FIFOC_PSC10_RX_ADDR 0x0 + +#define FIFOC_PSC11_TX_SIZE 0x0 +#define FIFOC_PSC11_TX_ADDR 0x0 +#define FIFOC_PSC11_RX_SIZE 0x0 +#define FIFOC_PSC11_RX_ADDR 0x0 + +/* IO Control Register + */ + +/* Indexes in regs array */ +#define MEM_IDX 0x00 +#define SPDIF_TXCLOCK_IDX 0x73 +#define SPDIF_TX_IDX 0x74 +#define SPDIF_RX_IDX 0x75 +#define PSC0_0_IDX 0x83 +#define PSC0_1_IDX 0x84 +#define PSC0_2_IDX 0x85 +#define PSC0_3_IDX 0x86 +#define PSC0_4_IDX 0x87 +#define PSC1_0_IDX 0x88 +#define PSC1_1_IDX 0x89 +#define PSC1_2_IDX 0x8a +#define PSC1_3_IDX 0x8b +#define PSC1_4_IDX 0x8c +#define PSC2_0_IDX 0x8d +#define PSC2_1_IDX 0x8e +#define PSC2_2_IDX 0x8f +#define PSC2_3_IDX 0x90 +#define PSC2_4_IDX 0x91 + +#define IOCTRL_FUNCMUX_SHIFT 7 +#define IOCTRL_FUNCMUX_FEC 1 +#define IOCTRL_MUX_FEC (IOCTRL_FUNCMUX_FEC << IOCTRL_FUNCMUX_SHIFT) + +/* Set for DDR */ +#define IOCTRL_MUX_DDR 0x00000036 + + /* Register Offset Base */ +#define MPC512X_FEC (CFG_IMMR + 0x02800) + +/* Number of I2C buses */ +#define I2C_BUS_CNT 3 + +/* I2Cn control register bits */ +#define I2C_EN 0x80 +#define I2C_IEN 0x40 +#define I2C_STA 0x20 +#define I2C_TX 0x10 +#define I2C_TXAK 0x08 +#define I2C_RSTA 0x04 +#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) + +/* I2Cn status register bits */ +#define I2C_CF 0x80 +#define I2C_AAS 0x40 +#define I2C_BB 0x20 +#define I2C_AL 0x10 +#define I2C_SRW 0x04 +#define I2C_IF 0x02 +#define I2C_RXAK 0x01 + +#endif /* __MPC512X_H__ */ diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index 9f4029f..ac8f317 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -235,7 +235,7 @@ stw r22,_CTR(r21); \ mfspr r20,XER; \ stw r20,_XER(r21); \ - mfspr r20,DEAR; \ + mfspr r20, DAR_DEAR; \ stw r20,_DAR(r21); \ mfspr r22,reg1; \ mfspr r23,reg2; \ diff --git a/lib_arm/armlinux.c b/lib_arm/armlinux.c index 56b7fca..6d32a41 100644 --- a/lib_arm/armlinux.c +++ b/lib_arm/armlinux.c @@ -66,13 +66,6 @@ static void setup_videolfb_tag (gd_t *gd); static struct tag *params; #endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include <status_led.h> -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - extern image_header_t header; /* from cmd_bootm.c */ @@ -96,7 +89,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], * Check if there is an initrd image */ if (argc >= 3) { - SHOW_BOOT_PROGRESS (9); + show_boot_progress (9); addr = simple_strtoul (argv[2], NULL, 16); @@ -114,7 +107,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], if (ntohl (hdr->ih_magic) != IH_MAGIC) { printf ("Bad Magic Number\n"); - SHOW_BOOT_PROGRESS (-10); + show_boot_progress (-10); do_reset (cmdtp, flag, argc, argv); } @@ -126,11 +119,11 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], if (crc32 (0, (unsigned char *) data, len) != checksum) { printf ("Bad Header Checksum\n"); - SHOW_BOOT_PROGRESS (-11); + show_boot_progress (-11); do_reset (cmdtp, flag, argc, argv); } - SHOW_BOOT_PROGRESS (10); + show_boot_progress (10); print_image_hdr (hdr); @@ -151,19 +144,19 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], csum = crc32 (0, (unsigned char *) data, len); if (csum != ntohl (hdr->ih_dcrc)) { printf ("Bad Data CRC\n"); - SHOW_BOOT_PROGRESS (-12); + show_boot_progress (-12); do_reset (cmdtp, flag, argc, argv); } printf ("OK\n"); } - SHOW_BOOT_PROGRESS (11); + show_boot_progress (11); if ((hdr->ih_os != IH_OS_LINUX) || (hdr->ih_arch != IH_CPU_ARM) || (hdr->ih_type != IH_TYPE_RAMDISK)) { printf ("No Linux ARM Ramdisk Image\n"); - SHOW_BOOT_PROGRESS (-13); + show_boot_progress (-13); do_reset (cmdtp, flag, argc, argv); } @@ -182,7 +175,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], ulong tail = ntohl (len_ptr[0]) % 4; int i; - SHOW_BOOT_PROGRESS (13); + show_boot_progress (13); /* skip kernel length and terminator */ data = (ulong) (&len_ptr[2]); @@ -201,7 +194,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], /* * no initrd image */ - SHOW_BOOT_PROGRESS (14); + show_boot_progress (14); len = data = 0; } @@ -220,7 +213,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], initrd_end = 0; } - SHOW_BOOT_PROGRESS (15); + show_boot_progress (15); debug ("## Transferring control to Linux (at address %08lx) ...\n", (ulong) theKernel); diff --git a/lib_avr32/avr32_linux.c b/lib_avr32/avr32_linux.c index 6095e2f..62afbd2 100644 --- a/lib_avr32/avr32_linux.c +++ b/lib_avr32/avr32_linux.c @@ -36,13 +36,6 @@ extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /* CPU-specific hook to allow flushing of caches, etc. */ extern void prepare_to_boot(void); -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include <status_led.h> -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - extern image_header_t header; /* from cmd_bootm.c */ static struct tag *setup_start_tag(struct tag *params) @@ -204,7 +197,7 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], * Check if there is an initrd image */ if (argc >= 3) { - SHOW_BOOT_PROGRESS(9); + show_boot_progress (9); addr = simple_strtoul(argv[2], NULL, 16); @@ -215,7 +208,7 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], if (ntohl(hdr->ih_magic) != IH_MAGIC) { puts("Bad Magic Number\n"); - SHOW_BOOT_PROGRESS(-10); + show_boot_progress (-10); do_reset(cmdtp, flag, argc, argv); } @@ -226,11 +219,11 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], if (crc32(0, (unsigned char *)data, len) != checksum) { puts("Bad Header Checksum\n"); - SHOW_BOOT_PROGRESS(-11); + show_boot_progress (-11); do_reset(cmdtp, flag, argc, argv); } - SHOW_BOOT_PROGRESS(10); + show_boot_progress (10); print_image_hdr(hdr); @@ -244,26 +237,26 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], csum = crc32(0, (unsigned char *)data, len); if (csum != ntohl(hdr->ih_dcrc)) { puts("Bad Data CRC\n"); - SHOW_BOOT_PROGRESS(-12); + show_boot_progress (-12); do_reset(cmdtp, flag, argc, argv); } puts("OK\n"); } - SHOW_BOOT_PROGRESS(11); + show_boot_progress (11); if ((hdr->ih_os != IH_OS_LINUX) || (hdr->ih_arch != IH_CPU_AVR32) || (hdr->ih_type != IH_TYPE_RAMDISK)) { puts("Not a Linux/AVR32 RAMDISK image\n"); - SHOW_BOOT_PROGRESS(-13); + show_boot_progress (-13); do_reset(cmdtp, flag, argc, argv); } } else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) { ulong tail = ntohl (len_ptr[0]) % 4; int i; - SHOW_BOOT_PROGRESS (13); + show_boot_progress (13); /* skip kernel length and terminator */ data = (ulong) (&len_ptr[2]); @@ -279,7 +272,7 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], len = ntohl (len_ptr[1]); } else { /* no initrd image */ - SHOW_BOOT_PROGRESS(14); + show_boot_progress (14); len = data = 0; } @@ -291,7 +284,7 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], initrd_end = 0; } - SHOW_BOOT_PROGRESS(15); + show_boot_progress (15); params = params_start = (struct tag *)gd->bd->bi_boot_params; params = setup_start_tag(params); diff --git a/lib_blackfin/bf533_linux.c b/lib_blackfin/bf533_linux.c index 3b9c4df..80a3dc7 100644 --- a/lib_blackfin/bf533_linux.c +++ b/lib_blackfin/bf533_linux.c @@ -36,13 +36,6 @@ #define LINUX_MAX_ENVS 256 #define LINUX_MAX_ARGS 256 -#ifdef CONFIG_SHOW_BOOT_PROGRESS -#include <status_led.h> -#define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -#define SHOW_BOOT_PROGRESS(arg) -#endif - #define CMD_LINE_ADDR 0xFF900000 /* L1 scratchpad */ #ifdef SHARED_RESOURCES diff --git a/lib_blackfin/post.c b/lib_blackfin/post.c index 0e76026..7c9478d 100644 --- a/lib_blackfin/post.c +++ b/lib_blackfin/post.c @@ -132,9 +132,7 @@ void post_output_backlog(void) post_log("PASSED\n"); else { post_log("FAILED\n"); -#ifdef CONFIG_SHOW_BOOT_PROGRESS - show_boot_progress(-31); -#endif + show_boot_progress (-31); } } } @@ -245,9 +243,7 @@ static int post_run_single(struct post_test *test, } else { if ((*test->test) (flags) != 0) { post_log("FAILED\n"); -#ifdef CONFIG_SHOW_BOOT_PROGRESS - show_boot_progress(-32); -#endif + show_boot_progress (-32); } else post_log("PASSED\n"); } diff --git a/lib_m68k/m68k_linux.c b/lib_m68k/m68k_linux.c index f87f56e..6c194f8 100644 --- a/lib_m68k/m68k_linux.c +++ b/lib_m68k/m68k_linux.c @@ -34,13 +34,6 @@ DECLARE_GLOBAL_DATA_PTR; #define LINUX_MAX_ENVS 256 #define LINUX_MAX_ARGS 256 -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include <status_led.h> -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - extern image_header_t header; /* from cmd_bootm.c */ extern int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]); @@ -73,7 +66,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], * Check if there is an initrd image */ if (argc >= 3) { - SHOW_BOOT_PROGRESS (9); + show_boot_progress (9); addr = simple_strtoul (argv[2], NULL, 16); @@ -84,7 +77,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], if (ntohl (hdr->ih_magic) != IH_MAGIC) { printf ("Bad Magic Number\n"); - SHOW_BOOT_PROGRESS (-10); + show_boot_progress (-10); do_reset (cmdtp, flag, argc, argv); } @@ -96,11 +89,11 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], if (crc32 (0, (char *) data, len) != checksum) { printf ("Bad Header Checksum\n"); - SHOW_BOOT_PROGRESS (-11); + show_boot_progress (-11); do_reset (cmdtp, flag, argc, argv); } - SHOW_BOOT_PROGRESS (10); + show_boot_progress (10); print_image_hdr (hdr); @@ -114,19 +107,19 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], csum = crc32 (0, (char *) data, len); if (csum != ntohl (hdr->ih_dcrc)) { printf ("Bad Data CRC\n"); - SHOW_BOOT_PROGRESS (-12); + show_boot_progress (-12); do_reset (cmdtp, flag, argc, argv); } printf ("OK\n"); } - SHOW_BOOT_PROGRESS (11); + show_boot_progress (11); if ((hdr->ih_os != IH_OS_LINUX) || (hdr->ih_arch != IH_CPU_M68K) || (hdr->ih_type != IH_TYPE_RAMDISK)) { printf ("No Linux M68K Ramdisk Image\n"); - SHOW_BOOT_PROGRESS (-13); + show_boot_progress (-13); do_reset (cmdtp, flag, argc, argv); } @@ -137,7 +130,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], ulong tail = ntohl (len_ptr[0]) % 4; int i; - SHOW_BOOT_PROGRESS (13); + show_boot_progress (13); /* skip kernel length and terminator */ data = (ulong) (&len_ptr[2]); @@ -156,7 +149,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], /* * no initrd image */ - SHOW_BOOT_PROGRESS (14); + show_boot_progress (14); data = 0; } @@ -175,7 +168,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], initrd_end = 0; } - SHOW_BOOT_PROGRESS (15); + show_boot_progress (15); #ifdef DEBUG printf ("## Transferring control to Linux (at address %08lx) ...\n", diff --git a/lib_microblaze/microblaze_linux.c b/lib_microblaze/microblaze_linux.c index 2c7885c..68b58d4 100644 --- a/lib_microblaze/microblaze_linux.c +++ b/lib_microblaze/microblaze_linux.c @@ -32,13 +32,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include <status_led.h> -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - extern image_header_t header; /* from cmd_bootm.c */ /*cmd_boot.c*/ extern int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]); @@ -59,7 +52,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], /* Check if there is an initrd image */ if (argc >= 3) { - SHOW_BOOT_PROGRESS (9); + show_boot_progress (9); addr = simple_strtoul (argv[2], NULL, 16); @@ -70,7 +63,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], if (ntohl (hdr->ih_magic) != IH_MAGIC) { printf ("Bad Magic Number\n"); - SHOW_BOOT_PROGRESS (-10); + show_boot_progress (-10); do_reset (cmdtp, flag, argc, argv); } @@ -82,11 +75,11 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], if (crc32 (0, (char *)data, len) != checksum) { printf ("Bad Header Checksum\n"); - SHOW_BOOT_PROGRESS (-11); + show_boot_progress (-11); do_reset (cmdtp, flag, argc, argv); } - SHOW_BOOT_PROGRESS (10); + show_boot_progress (10); print_image_hdr (hdr); @@ -100,19 +93,19 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], csum = crc32 (0, (char *)data, len); if (csum != ntohl (hdr->ih_dcrc)) { printf ("Bad Data CRC\n"); - SHOW_BOOT_PROGRESS (-12); + show_boot_progress (-12); do_reset (cmdtp, flag, argc, argv); } printf ("OK\n"); } - SHOW_BOOT_PROGRESS (11); + show_boot_progress (11); if ((hdr->ih_os != IH_OS_LINUX) || (hdr->ih_arch != IH_CPU_MICROBLAZE) || (hdr->ih_type != IH_TYPE_RAMDISK)) { printf ("No Linux Microblaze Ramdisk Image\n"); - SHOW_BOOT_PROGRESS (-13); + show_boot_progress (-13); do_reset (cmdtp, flag, argc, argv); } @@ -122,7 +115,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], } else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) { ulong tail = ntohl (len_ptr[0]) % 4; - SHOW_BOOT_PROGRESS (13); + show_boot_progress (13); /* skip kernel length and terminator */ data = (ulong) (&len_ptr[2]); @@ -141,7 +134,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], /* * no initrd image */ - SHOW_BOOT_PROGRESS (14); + show_boot_progress (14); data = 0; } @@ -160,7 +153,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], initrd_end = 0; } - SHOW_BOOT_PROGRESS (15); + show_boot_progress (15); #ifdef DEBUG printf ("## Transferring control to Linux (at address %08lx) ...\n", diff --git a/lib_mips/mips_linux.c b/lib_mips/mips_linux.c index 952d5a9..556b180 100644 --- a/lib_mips/mips_linux.c +++ b/lib_mips/mips_linux.c @@ -33,13 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; #define LINUX_MAX_ENVS 256 #define LINUX_MAX_ARGS 256 -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include <status_led.h> -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - extern image_header_t header; /* from cmd_bootm.c */ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); @@ -73,7 +66,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], * Check if there is an initrd image */ if (argc >= 3) { - SHOW_BOOT_PROGRESS (9); + show_boot_progress (9); addr = simple_strtoul (argv[2], NULL, 16); @@ -84,7 +77,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], if (ntohl (hdr->ih_magic) != IH_MAGIC) { printf ("Bad Magic Number\n"); - SHOW_BOOT_PROGRESS (-10); + show_boot_progress (-10); do_reset (cmdtp, flag, argc, argv); } @@ -96,11 +89,11 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], if (crc32 (0, (uchar *) data, len) != checksum) { printf ("Bad Header Checksum\n"); - SHOW_BOOT_PROGRESS (-11); + show_boot_progress (-11); do_reset (cmdtp, flag, argc, argv); } - SHOW_BOOT_PROGRESS (10); + show_boot_progress (10); print_image_hdr (hdr); @@ -114,19 +107,19 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], csum = crc32 (0, (uchar *) data, len); if (csum != ntohl (hdr->ih_dcrc)) { printf ("Bad Data CRC\n"); - SHOW_BOOT_PROGRESS (-12); + show_boot_progress (-12); do_reset (cmdtp, flag, argc, argv); } printf ("OK\n"); } - SHOW_BOOT_PROGRESS (11); + show_boot_progress (11); if ((hdr->ih_os != IH_OS_LINUX) || (hdr->ih_arch != IH_CPU_MIPS) || (hdr->ih_type != IH_TYPE_RAMDISK)) { printf ("No Linux MIPS Ramdisk Image\n"); - SHOW_BOOT_PROGRESS (-13); + show_boot_progress (-13); do_reset (cmdtp, flag, argc, argv); } @@ -137,7 +130,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], ulong tail = ntohl (len_ptr[0]) % 4; int i; - SHOW_BOOT_PROGRESS (13); + show_boot_progress (13); /* skip kernel length and terminator */ data = (ulong) (&len_ptr[2]); @@ -156,7 +149,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], /* * no initrd image */ - SHOW_BOOT_PROGRESS (14); + show_boot_progress (14); data = 0; } @@ -175,7 +168,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], initrd_end = 0; } - SHOW_BOOT_PROGRESS (15); + show_boot_progress (15); #ifdef DEBUG printf ("## Transferring control to Linux (at address %08lx) ...\n", diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 163aaeb..325f5c2 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -1124,9 +1124,7 @@ void board_init_r (gd_t *id, ulong dest_addr) void hang (void) { puts ("### ERROR ### Please RESET the board ###\n"); -#ifdef CONFIG_SHOW_BOOT_PROGRESS show_boot_progress(-30); -#endif for (;;); } @@ -28,14 +28,6 @@ #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -#if defined(CONFIG_SHOW_BOOT_PROGRESS) -# include <status_led.h> -extern void show_ethcfg_progress (int arg); -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress (arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - #ifdef CFG_GT_6426x extern int gt6426x_eth_initialize(bd_t *bis); #endif @@ -48,6 +40,7 @@ extern int eth_3com_initialize(bd_t*); extern int fec_initialize(bd_t*); extern int inca_switch_initialize(bd_t*); extern int mpc5xxx_fec_initialize(bd_t*); +extern int mpc512x_fec_initialize(bd_t*); extern int mpc8220_fec_initialize(bd_t*); extern int mv6436x_eth_initialize(bd_t *); extern int mv6446x_eth_initialize(bd_t *); @@ -150,6 +143,7 @@ int eth_initialize(bd_t *bis) eth_devices = NULL; eth_current = NULL; + show_boot_progress (64); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_init(); #endif @@ -175,6 +169,9 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_MPC5xxx_FEC) mpc5xxx_fec_initialize(bis); #endif +#if defined(CONFIG_MPC512x_FEC) + mpc512x_fec_initialize (bis); +#endif #if defined(CONFIG_MPC8220_FEC) mpc8220_fec_initialize(bis); #endif @@ -255,12 +252,12 @@ int eth_initialize(bd_t *bis) if (!eth_devices) { puts ("No ethernet found.\n"); - SHOW_BOOT_PROGRESS(-64); + show_boot_progress (-64); } else { struct eth_device *dev = eth_devices; char *ethprime = getenv ("ethprime"); - SHOW_BOOT_PROGRESS(65); + show_boot_progress (65); do { if (eth_number) puts (", "); diff --git a/post/post.c b/post/post.c index 28435cc..4ff75ee 100644 --- a/post/post.c +++ b/post/post.c @@ -129,9 +129,7 @@ void post_output_backlog ( void ) post_log ("PASSED\n"); else { post_log ("FAILED\n"); -#ifdef CONFIG_SHOW_BOOT_PROGRESS - show_boot_progress(-31); -#endif + show_boot_progress (-31); } } } @@ -241,9 +239,7 @@ static int post_run_single (struct post_test *test, } else { if ((*test->test) (flags) != 0) { post_log ("FAILED\n"); -#ifdef CONFIG_SHOW_BOOT_PROGRESS - show_boot_progress(-32); -#endif + show_boot_progress (-32); } else post_log ("PASSED\n"); |