diff options
| -rw-r--r-- | arch/arm/cpu/armv7/mx7/clock.c | 33 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx7/imx-regs.h | 1 |
2 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx7/clock.c b/arch/arm/cpu/armv7/mx7/clock.c index 4945916..583e45f 100644 --- a/arch/arm/cpu/armv7/mx7/clock.c +++ b/arch/arm/cpu/armv7/mx7/clock.c @@ -718,6 +718,25 @@ static void init_clk_wdog(void) } +#ifdef CONFIG_MXC_EPDC +static void init_clk_epdc(void) +{ + u32 target; + + /* disable the clock gate first */ + clock_enable(CCGR_EPDC, 0); + + /* 24Mhz */ + target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV12); + clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target); + + /* enable the clock gate */ + clock_enable(CCGR_EPDC, 1); +} +#endif + static int enable_pll_enet(void) { u32 reg; @@ -993,6 +1012,9 @@ void clock_init(void) init_clk_weim(); init_clk_ecspi(); init_clk_wdog(); +#ifdef CONFIG_MXC_EPDC + init_clk_epdc(); +#endif enable_usboh3_clk(1); @@ -1015,6 +1037,17 @@ void hab_caam_clock_disable(void) } #endif +#ifdef CONFIG_MXC_EPDC +void epdc_clock_enable(void) +{ + clock_enable(CCGR_EPDC, 1); +} +void epdc_clock_disable(void) +{ + clock_enable(CCGR_EPDC, 0); +} +#endif + /* * Dump some core clockes. */ diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index db148e9..3f82807 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -139,6 +139,7 @@ #define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC0000) #define PCIE_PHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xD0000) #define EPDC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xF0000) +#define EPDC_BASE_ADDR EPDC_IPS_BASE_ADDR #define EPXP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x100000) #define CSI1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x110000) #define ELCDIF1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x130000) |