diff options
308 files changed, 13272 insertions, 5433 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 1520312..4597798 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -428,6 +428,7 @@ Heiko Schocher <hs@denx.de> sc3 PPC405GP suen3 ARM926EJS (Kirkwood SoC) uc101 MPC5200 + ve8313 MPC8313 Peter De Schrijver <p2@mind.be> @@ -447,6 +448,7 @@ Timur Tabi <timur@freescale.com> MPC8349E-mITX MPC8349 MPC8349E-mITX-GP MPC8349 + P1022DS P1022 Erik Theisen <etheisen@mindspring.com> @@ -490,6 +492,10 @@ Stephen Williams <steve@icarus.com> JSE PPC405GPr +Ilya Yanok <yanok@emcraft.com> + + MPC8308RDB MPC8308 + Roy Zang <tie-fei.zang@freescale.com> mpc7448hpc2 MPC7448 @@ -871,9 +877,6 @@ Scott McNutt <smcnutt@psyent.com> PCI5441 Nios-II PK1C20 Nios-II - EP1C20 Nios-II - EP1S10 Nios-II - EP1S40 Nios-II nios2-generic Nios-II ######################################################################### @@ -1000,6 +1003,8 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org> BF548-EZKIT BF548 BF561-EZKIT BF561 + BF527-AD7160-EVAL BF527 + Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> Blackfin Team <u-boot-devel@blackfin.uclinux.org> @@ -360,6 +360,7 @@ LIST_8260=" \ LIST_83xx=" \ caddy2 \ kmeter1 \ + MPC8308RDB \ MPC8313ERDB_33 \ MPC8313ERDB_NAND_66 \ MPC8315ERDB \ @@ -380,6 +381,7 @@ LIST_83xx=" \ sbc8349 \ SIMPC8313_LP \ TQM834x \ + ve8313 \ vme8349 \ " @@ -408,6 +410,7 @@ LIST_85xx=" \ MPC8569MDS_NAND \ MPC8572DS \ MPC8572DS_36BIT \ + P1022DS \ P2020DS \ P2020DS_36BIT \ P1011RDB \ @@ -704,6 +707,7 @@ LIST_at91=" \ LIST_pxa=" \ cerf250 \ + colibri_pxa270 \ cradle \ csb226 \ delta \ @@ -713,10 +717,13 @@ LIST_pxa=" \ polaris \ pxa255_idp \ trizepsiv \ + vpac270_nor \ + vpac270_onenand \ wepep250 \ xaeniax \ xm250 \ xsengine \ + zipitz2 \ zylonite \ " @@ -826,9 +833,6 @@ LIST_x86=" \ ######################################################################### LIST_nios2=" \ - EP1C20 \ - EP1S10 \ - EP1S40 \ PCI5441 \ PK1C20 \ nios2-generic \ @@ -894,6 +898,7 @@ LIST_avr32=" \ LIST_blackfin=" \ bf518f-ezbrd \ bf526-ezbrd \ + bf527-ad7160-eval \ bf527-ezkit \ bf527-ezkit-v2 \ bf533-ezkit \ @@ -221,6 +221,7 @@ LIBS += drivers/power/libpower.a LIBS += drivers/spi/libspi.a ifeq ($(CPU),mpc83xx) LIBS += drivers/qe/qe.a +LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.a endif ifeq ($(CPU),mpc85xx) LIBS += drivers/qe/qe.a @@ -2178,6 +2179,15 @@ trizepsiv_config : unconfig fi; @$(MKCONFIG) -n $@ -a trizepsiv arm pxa trizepsiv +vpac270_nor_config \ +vpac270_onenand_config : unconfig + @mkdir -p $(obj)include + @if [ "$(findstring onenand,$@)" ] ; then \ + echo "#define CONFIG_ONENAND_U_BOOT" \ + >>$(obj)include/config.h ; \ + fi; + @$(MKCONFIG) -n $@ -a vpac270 arm pxa vpac270 + ######################################################################### ## ARM1136 Systems ######################################################################### @@ -2443,7 +2453,6 @@ clean: $(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \ $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \ $(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds \ - $(obj)arch/blackfin/lib/u-boot.lds \ $(obj)u-boot.lds \ $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] @rm -f $(obj)include/bmp_logo.h diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index 6fc3902..c63e864 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -378,10 +378,10 @@ int arch_misc_init(void) } #endif /* CONFIG_ARCH_MISC_INIT */ -#ifdef CONFIG_KIRKWOOD_EGIGA +#ifdef CONFIG_MVGBE int cpu_eth_init(bd_t *bis) { - kirkwood_egiga_initialize(bis); + mvgbe_initialize(bis); return 0; } #endif diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index 03c6d06..f3c1e21 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -268,3 +268,11 @@ int arch_misc_init(void) return 0; } #endif /* CONFIG_ARCH_MISC_INIT */ + +#ifdef CONFIG_MVGBE +int cpu_eth_init(bd_t *bis) +{ + mvgbe_initialize(bis); + return 0; +} +#endif diff --git a/arch/arm/cpu/pxa/pxafb.c b/arch/arm/cpu/pxa/pxafb.c index d56c5f0..524a03b 100644 --- a/arch/arm/cpu/pxa/pxafb.c +++ b/arch/arm/cpu/pxa/pxafb.c @@ -112,6 +112,39 @@ vidinfo_t panel_info = { vl_efw: 0, }; #endif /* CONFIG_SHARP_LM8V31 */ +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_VOIPAC_LCD + +# define LCD_BPP LCD_COLOR8 +# define LCD_INVERT_COLORS + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x043008f8 +# define REG_LCCR3 0x0340FF08 + +vidinfo_t panel_info = { + vl_col: 640, + vl_row: 480, + vl_width: 157, + vl_height: 118, + vl_clkp: CONFIG_SYS_HIGH, + vl_oep: CONFIG_SYS_HIGH, + vl_hsp: CONFIG_SYS_HIGH, + vl_vsp: CONFIG_SYS_HIGH, + vl_dp: CONFIG_SYS_HIGH, + vl_bpix: LCD_BPP, + vl_lbw: 0, + vl_splt: 1, + vl_clor: 1, + vl_tft: 1, + vl_hpw: 32, + vl_blw: 144, + vl_elw: 32, + vl_vpw: 2, + vl_bfw: 13, + vl_efw: 30, +}; +#endif /* CONFIG_VOIPAC_LCD */ /*----------------------------------------------------------------------*/ #ifdef CONFIG_HITACHI_SX14 @@ -147,6 +180,40 @@ vidinfo_t panel_info = { #endif /* CONFIG_HITACHI_SX14 */ /*----------------------------------------------------------------------*/ +#ifdef CONFIG_LMS283GF05 + +# define LCD_BPP LCD_COLOR8 +//# define LCD_INVERT_COLORS + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x043008f8 +# define REG_LCCR3 0x03b00009 + +vidinfo_t panel_info = { + vl_col: 240, + vl_row: 320, + vl_width: 240, + vl_height: 320, + vl_clkp: CONFIG_SYS_HIGH, + vl_oep: CONFIG_SYS_LOW, + vl_hsp: CONFIG_SYS_LOW, + vl_vsp: CONFIG_SYS_LOW, + vl_dp: CONFIG_SYS_HIGH, + vl_bpix: LCD_BPP, + vl_lbw: 0, + vl_splt: 1, + vl_clor: 1, + vl_tft: 1, + vl_hpw: 4, + vl_blw: 4, + vl_elw: 8, + vl_vpw: 4, + vl_bfw: 4, + vl_efw: 8, +}; +#endif /* CONFIG_LMS283GF05 */ + +/*----------------------------------------------------------------------*/ #if LCD_BPP == LCD_COLOR8 void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue); @@ -292,7 +359,9 @@ static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid) return 0; } - +#ifdef CONFIG_CPU_MONAHANS +static inline void pxafb_setup_gpio (vidinfo_t *vid) {} +#else static void pxafb_setup_gpio (vidinfo_t *vid) { u_long lccr0; @@ -349,6 +418,7 @@ static void pxafb_setup_gpio (vidinfo_t *vid) printf("pxafb_setup_gpio: unable to determine bits per pixel\n"); } } +#endif static void pxafb_enable_controller (vidinfo_t *vid) { @@ -363,7 +433,11 @@ static void pxafb_enable_controller (vidinfo_t *vid) FDADR1 = vid->pxa.fdadr1; LCCR0 |= LCCR0_ENB; +#ifdef CONFIG_CPU_MONAHANS + CKENA |= CKENA_1_LCD; +#else CKEN |= CKEN16_LCD; +#endif debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0); debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1); diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index e07c8c2..8010b0e 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -34,6 +34,25 @@ .globl _start _start: b reset +#ifdef CONFIG_PRELOADER + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + +_hang: + .word do_hang + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 /* now 16*4=64 */ +#else ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -49,6 +68,7 @@ _data_abort: .word data_abort _not_used: .word not_used _irq: .word irq _fiq: .word fiq +#endif /* CONFIG_PRELOADER */ .balignl 16,0xdeadbeef @@ -117,8 +137,10 @@ reset: relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ +#ifndef CONFIG_PRELOADER cmp r0, r1 /* don't reloc during debug */ beq stack_setup +#endif ldr r2, _armboot_start ldr r3, _bss_start @@ -135,28 +157,37 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ - sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ +#ifdef CONFIG_PRELOADER + sub sp, r0, #128 /* leave 32 words for abort-stack */ +#else + sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ + sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif /* CONFIG_USE_IRQ */ sub sp, r0, #12 /* leave 3 words for abort-stack */ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ +#endif clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ mov r2, #0x00000000 /* clear */ +#ifndef CONFIG_PRELOADER clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 ble clbss_l +#endif ldr pc, _start_armboot +#ifdef CONFIG_ONENAND_IPL +_start_armboot: .word start_oneboot +#else _start_armboot: .word start_armboot - +#endif /****************************************************************************/ /* */ @@ -296,7 +327,7 @@ setspeed_done: */ mov pc, lr - +#ifndef CONFIG_PRELOADER /****************************************************************************/ /* */ /* Interrupt handling */ @@ -394,6 +425,7 @@ setspeed_done: .macro get_fiq_stack @ setup FIQ stack ldr sp, FIQ_STACK_START .endm +#endif /* CONFIG_PRELOADER */ /****************************************************************************/ @@ -402,6 +434,12 @@ setspeed_done: /* */ /****************************************************************************/ +#ifdef CONFIG_PRELOADER + .align 5 +do_hang: + ldr sp, _TEXT_BASE /* use 32 words abort stack */ + bl hang /* hang and never return */ +#else /* !CONFIG_PRELOADER */ .align 5 undefined_instruction: get_bad_stack @@ -461,7 +499,7 @@ fiq: get_bad_stack bad_save_user_regs bl do_fiq - +#endif /* CONFIG_PRELOADER */ #endif /* CONFIG_USE_IRQ */ /****************************************************************************/ diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h index 2470efb..9edb0be 100644 --- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h +++ b/arch/arm/include/asm/arch-kirkwood/kirkwood.h @@ -60,6 +60,11 @@ #define KW_EGIGA0_BASE (KW_REGISTER(0x72000)) #define KW_EGIGA1_BASE (KW_REGISTER(0x76000)) +/* Kirkwood GbE controller has two ports */ +#define MAX_MVGBE_DEVS 2 +#define MVGBE0_BASE KW_EGIGA0_BASE +#define MVGBE1_BASE KW_EGIGA1_BASE + #if defined (CONFIG_KW88F6281) #include <asm/arch/kw88f6281.h> #elif defined (CONFIG_KW88F6192) diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h index 4008c84..d257b66 100644 --- a/arch/arm/include/asm/arch-orion5x/orion5x.h +++ b/arch/arm/include/asm/arch-orion5x/orion5x.h @@ -56,6 +56,10 @@ #define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000)) #define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000)) +/* Orion5x GbE controller has a single port */ +#define MAX_MVGBE_DEVS 1 +#define MVGBE0_BASE ORION5X_EGIGA_BASE + #define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024) /* include here SoC variants. 5181, 5281, 6183 should go here when diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h new file mode 100644 index 0000000..035a57e --- /dev/null +++ b/arch/arm/include/asm/arch-pxa/macro.h @@ -0,0 +1,324 @@ +/* + * arch/arm/include/asm/arch-pxa/macro.h + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_PXA_MACRO_H__ +#define __ASM_ARCH_PXA_MACRO_H__ +#ifdef __ASSEMBLY__ + +#include <asm/macro.h> +#include <asm/arch/pxa-regs.h> + +/* + * This macro performs a 32bit write to a memory location and makes sure the + * write operation really happened by performing a read back. + * + * Clobbered regs: r4, r5 + */ +.macro write32rb addr, data + ldr r4, =\addr + ldr r5, =\data + str r5, [r4] + ldr r5, [r4] +.endm + +/* + * This macro waits according to OSCR incrementation + * + * Clobbered regs: r4, r5, r6 + */ +.macro pxa_wait_ticks ticks + ldr r4, =OSCR + mov r5, #0 + str r5, [r4] + ldr r5, =\ticks +1: + ldr r6, [r4] + cmp r5, r6 + bgt 1b +.endm + +/* + * This macro sets up the GPIO pins of the PXA2xx/PXA3xx CPU + * + * Clobbered regs: r4, r5 + */ +.macro pxa_gpio_setup + write32 GPSR0, CONFIG_SYS_GPSR0_VAL + write32 GPSR1, CONFIG_SYS_GPSR1_VAL + write32 GPSR2, CONFIG_SYS_GPSR2_VAL +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) + write32 GPSR3, CONFIG_SYS_GPSR3_VAL +#endif + + write32 GPCR0, CONFIG_SYS_GPCR0_VAL + write32 GPCR1, CONFIG_SYS_GPCR1_VAL + write32 GPCR2, CONFIG_SYS_GPCR2_VAL +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) + write32 GPCR3, CONFIG_SYS_GPCR3_VAL +#endif + + write32 GPDR0, CONFIG_SYS_GPDR0_VAL + write32 GPDR1, CONFIG_SYS_GPDR1_VAL + write32 GPDR2, CONFIG_SYS_GPDR2_VAL +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) + write32 GPDR3, CONFIG_SYS_GPDR3_VAL +#endif + + write32 GAFR0_L, CONFIG_SYS_GAFR0_L_VAL + write32 GAFR0_U, CONFIG_SYS_GAFR0_U_VAL + write32 GAFR1_L, CONFIG_SYS_GAFR1_L_VAL + write32 GAFR1_U, CONFIG_SYS_GAFR1_U_VAL + write32 GAFR2_L, CONFIG_SYS_GAFR2_L_VAL + write32 GAFR2_U, CONFIG_SYS_GAFR2_U_VAL +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) + write32 GAFR3_L, CONFIG_SYS_GAFR3_L_VAL + write32 GAFR3_U, CONFIG_SYS_GAFR3_U_VAL +#endif + + write32 PSSR, CONFIG_SYS_PSSR_VAL +.endm + +/* + * This macro sets up the Memory controller of the PXA2xx CPU + * + * Clobbered regs: r3, r4, r5 + */ +.macro pxa_mem_setup + /* This comes handy when setting MDREFR */ + ldr r3, =MEMC_BASE + + /* + * 1) Initialize Asynchronous static memory controller + */ + + /* MSC0: nCS(0,1) */ + write32rb (MEMC_BASE + MSC0_OFFSET), CONFIG_SYS_MSC0_VAL + /* MSC1: nCS(2,3) */ + write32rb (MEMC_BASE + MSC1_OFFSET), CONFIG_SYS_MSC1_VAL + /* MSC2: nCS(4,5) */ + write32rb (MEMC_BASE + MSC2_OFFSET), CONFIG_SYS_MSC2_VAL + + /* + * 2) Initialize Card Interface + */ + + /* MECR: Memory Expansion Card Register */ + write32rb (MEMC_BASE + MECR_OFFSET), CONFIG_SYS_MECR_VAL + /* MCMEM0: Card Interface slot 0 timing */ + write32rb (MEMC_BASE + MCMEM0_OFFSET), CONFIG_SYS_MCMEM0_VAL + /* MCMEM1: Card Interface slot 1 timing */ + write32rb (MEMC_BASE + MCMEM1_OFFSET), CONFIG_SYS_MCMEM1_VAL + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + write32rb (MEMC_BASE + MCATT0_OFFSET), CONFIG_SYS_MCATT0_VAL + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + write32rb (MEMC_BASE + MCATT1_OFFSET), CONFIG_SYS_MCATT1_VAL + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + write32rb (MEMC_BASE + MCIO0_OFFSET), CONFIG_SYS_MCIO0_VAL + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + write32rb (MEMC_BASE + MCIO1_OFFSET), CONFIG_SYS_MCIO1_VAL + + /* + * 3) Configure Fly-By DMA register + */ + + write32rb (MEMC_BASE + FLYCNFG_OFFSET), CONFIG_SYS_FLYCNFG_VAL + + /* + * 4) Initialize Timing for Sync Memory (SDCLK0) + */ + + /* + * Before accessing MDREFR we need a valid DRI field, so we set + * this to power on defaults + DRI field. + */ + ldr r5, [r3, #MDREFR_OFFSET] + bic r5, r5, #0x0ff + bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */ + + ldr r4, =CONFIG_SYS_MDREFR_VAL + mov r6, r4 + lsl r4, #20 + lsr r4, #20 /* Get a valid DRI field */ + + orr r5, r5, r4 /* MDREFR user config with correct DRI */ + + orr r5, #MDREFR_K0RUN + orr r5, #MDREFR_SLFRSH + bic r5, #MDREFR_APD + bic r5, #MDREFR_E1PIN + + str r5, [r3, #MDREFR_OFFSET] + ldr r4, [r3, #MDREFR_OFFSET] + + /* + * 5) Initialize Synchronous Static Memory (Flash/Peripherals) + */ + + /* Initialize SXCNFG register. Assert the enable bits. + * + * Write SXMRS to cause an MRS command to all enabled banks of + * synchronous static memory. Note that SXLCR need not be written + * at this time. + */ + write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL + + /* + * 6) Initialize SDRAM + */ + + bic r6, #MDREFR_SLFRSH + str r6, [r3, #MDREFR_OFFSET] + ldr r4, [r3, #MDREFR_OFFSET] + + orr r6, #MDREFR_E1PIN + str r6, [r3, #MDREFR_OFFSET] + ldr r4, [r3, #MDREFR_OFFSET] + + /* + * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure + * but not enable each SDRAM partition pair. + */ + + /* Fetch platform value of MDCNFG */ + ldr r4, =CONFIG_SYS_MDCNFG_VAL + /* Disable all sdram banks */ + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) + /* Write initial value of MDCNFG, w/o enabling sdram banks */ + str r4, [r3, #MDCNFG_OFFSET] + ldr r4, [r3, #MDCNFG_OFFSET] + + /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */ + pxa_wait_ticks 0x300 + + /* + * 8) Trigger a number (usually 8) refresh cycles by attempting + * non-burst read or write accesses to disabled SDRAM, as commonly + * specified in the power up sequence documented in SDRAM data + * sheets. The address(es) used for this purpose must not be + * cacheable. + */ + + ldr r4, =CONFIG_SYS_DRAM_BASE +.rept 9 + str r5, [r4] +.endr + + /* + * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1). + */ + + ldr r5, =CONFIG_SYS_MDCNFG_VAL + ldr r4, =(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3) + and r5, r5, r4 + ldr r4, [r3, #MDCNFG_OFFSET] + orr r4, r4, r5 + str r4, [r3, #MDCNFG_OFFSET] + ldr r4, [r3, #MDCNFG_OFFSET] + + /* + * 10) Write MDMRS. + */ + + ldr r4, =CONFIG_SYS_MDMRS_VAL + str r4, [r3, #MDMRS_OFFSET] + ldr r4, [r3, #MDMRS_OFFSET] + + /* + * 11) Enable APD + */ + + ldr r4, [r3, #MDREFR_OFFSET] + and r6, r6, #MDREFR_APD + orr r4, r4, r6 + str r4, [r3, #MDREFR_OFFSET] + ldr r4, [r3, #MDREFR_OFFSET] +.endm + +/* + * This macro tests if the CPU woke up from sleep and eventually resumes + * + * Clobbered regs: r4, r5 + */ +.macro pxa_wakeup + ldr r4, =RCSR + ldr r5, [r4] + and r5, r5, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) + str r5, [r4] + teq r5, #RCSR_SMR + + bne pxa_wakeup_exit + + ldr r4, =PSSR + mov r5, #PSSR_PH + str r5, [r4] + + ldr r4, =PSPR + ldr pc, [r4] +pxa_wakeup_exit: +.endm + +/* + * This macro disables all interupts on PXA2xx/PXA3xx CPU + * + * Clobbered regs: r4, r5 + */ +.macro pxa_intr_setup + write32 ICLR, 0 + write32 ICMR, 0 +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) + write32 ICLR2, 0 + write32 ICMR2, 0 +#endif +.endm + +/* + * This macro configures clock on PXA2xx/PXA3xx CPU + * + * Clobbered regs: r4, r5 + */ +.macro pxa_clock_setup + /* Disable the peripheral clocks, and set the core clock frequency */ + + /* Turn Off ALL on-chip peripheral clocks for re-configuration */ + write32 CKEN, CONFIG_SYS_CKEN + + /* Write CCCR */ + write32 CCCR, CONFIG_SYS_CCCR + +#ifdef CONFIG_RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + write32 OSCC, #OSCC_OON + ldr r4, =OSCC + + /* Spin here until OSCC.OOK get set, meaning the PLL has settled. */ +2: + ldr r5, [r4] + ands r5, r5, #1 + beq 2b +#endif +.endm + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_PXA_MACRO_H__ */ diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h index cd7b7f9..d442fb0 100644 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h @@ -1132,10 +1132,18 @@ typedef void (*ExcpHndlr) (void) ; #define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */ #define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */ -#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */ +#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1 Control Register */ #define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */ #define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */ +#define PWM_CTRL2 __REG(0x40B00010) /* PWM 2 Control Register */ +#define PWM_PWDUTY2 __REG(0x40B00014) /* PWM 2 Duty Cycle Register */ +#define PWM_PERVAL2 __REG(0x40B00018) /* PWM 2 Period Control Register */ + +#define PWM_CTRL3 __REG(0x40C00010) /* PWM 3 Control Register */ +#define PWM_PWDUTY3 __REG(0x40C00014) /* PWM 3 Duty Cycle Register */ +#define PWM_PERVAL3 __REG(0x40C00018) /* PWM 3 Period Control Register */ + /* * Interrupt Controller */ diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile index 211b8d5..b7f991d 100644 --- a/arch/blackfin/cpu/Makefile +++ b/arch/blackfin/cpu/Makefile @@ -17,7 +17,10 @@ EXTRA := CEXTRA := initcode.o SEXTRA := start.o SOBJS := interrupt.o cache.o +COBJS-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount.o +COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o COBJS-y += cpu.o +COBJS-y += gpio.o COBJS-y += interrupts.o COBJS-$(CONFIG_JTAG_CONSOLE) += jtag-console.o COBJS-y += os_log.o diff --git a/arch/blackfin/cpu/bootcount.c b/arch/blackfin/cpu/bootcount.c new file mode 100644 index 0000000..6cf6dd5 --- /dev/null +++ b/arch/blackfin/cpu/bootcount.c @@ -0,0 +1,34 @@ +/* + * functions for handling bootcount support + * + * Copyright (c) 2010 Analog Devices Inc. + * + * Licensed under the 2-clause BSD. + */ + +/* This version uses one 32bit storage and combines the magic/count */ + +#include <common.h> + +/* We abuse the EVT0 MMR for bootcount storage by default */ +#ifndef CONFIG_SYS_BOOTCOUNT_ADDR +# define CONFIG_SYS_BOOTCOUNT_ADDR EVT0 +#endif + +#define MAGIC_MASK 0xffff0000 +#define COUNT_MASK 0x0000ffff + +void bootcount_store(ulong cnt) +{ + ulong magic = (BOOTCOUNT_MAGIC & MAGIC_MASK) | (cnt & COUNT_MASK); + bfin_write32(CONFIG_SYS_BOOTCOUNT_ADDR, magic); +} + +ulong bootcount_load(void) +{ + ulong magic = bfin_read32(CONFIG_SYS_BOOTCOUNT_ADDR); + if ((magic & MAGIC_MASK) == (BOOTCOUNT_MAGIC & MAGIC_MASK)) + return magic & COUNT_MASK; + else + return 0; +} diff --git a/arch/blackfin/cpu/cmd_gpio.c b/arch/blackfin/cpu/cmd_gpio.c new file mode 100644 index 0000000..9e505b6 --- /dev/null +++ b/arch/blackfin/cpu/cmd_gpio.c @@ -0,0 +1,120 @@ +/* + * Control GPIO pins on the fly + * + * Copyright (c) 2008-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <command.h> + +#include <asm/blackfin.h> +#include <asm/gpio.h> + +enum { + GPIO_INPUT, + GPIO_SET, + GPIO_CLEAR, + GPIO_TOGGLE, +}; + +int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc == 2 && !strcmp(argv[1], "status")) { + bfin_gpio_labels(); + return 0; + } + + if (argc != 3) { + show_usage: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* parse the behavior */ + ulong sub_cmd; + switch (argv[1][0]) { + case 'i': sub_cmd = GPIO_INPUT; break; + case 's': sub_cmd = GPIO_SET; break; + case 'c': sub_cmd = GPIO_CLEAR; break; + case 't': sub_cmd = GPIO_TOGGLE; break; + default: goto show_usage; + } + + /* parse the pin with format: [p][port]<#> */ + const char *str_pin = argv[2]; + + /* grab the [p]<port> portion */ + ulong port_base; + if (*str_pin == 'p') ++str_pin; + switch (*str_pin) { +#ifdef GPIO_PA0 + case 'a': port_base = GPIO_PA0; break; +#endif +#ifdef GPIO_PB0 + case 'b': port_base = GPIO_PB0; break; +#endif +#ifdef GPIO_PC0 + case 'c': port_base = GPIO_PC0; break; +#endif +#ifdef GPIO_PD0 + case 'd': port_base = GPIO_PD0; break; +#endif +#ifdef GPIO_PE0 + case 'e': port_base = GPIO_PE0; break; +#endif +#ifdef GPIO_PF0 + case 'f': port_base = GPIO_PF0; break; +#endif +#ifdef GPIO_PG0 + case 'g': port_base = GPIO_PG0; break; +#endif +#ifdef GPIO_PH0 + case 'h': port_base = GPIO_PH0; break; +#endif +#ifdef GPIO_PI0 + case 'i': port_base = GPIO_PI0; break; +#endif +#ifdef GPIO_PJ + case 'j': port_base = GPIO_PJ0; break; +#endif + default: goto show_usage; + } + + /* grab the <#> portion */ + ulong pin = simple_strtoul(str_pin + 1, NULL, 10); + if (pin > 15) + goto show_usage; + + /* grab the pin before we tweak it */ + ulong gpio = port_base + pin; + gpio_request(gpio, "cmd_gpio"); + + /* finally, let's do it: set direction and exec command */ + if (sub_cmd == GPIO_INPUT) { + gpio_direction_input(gpio); + printf("gpio: pin %lu on port %c set to input\n", pin, *str_pin); + return 0; + } + + ulong value; + switch (sub_cmd) { + case GPIO_SET: value = 1; break; + case GPIO_CLEAR: value = 0; break; + case GPIO_TOGGLE: value = !gpio_get_value(gpio); break; + default: goto show_usage; + } + gpio_direction_output(gpio, value); + printf("gpio: pin %lu on port %c (gpio %lu) value is %lu\n", + pin, *str_pin, gpio, value); + + gpio_free(gpio); + + return 0; +} + +U_BOOT_CMD(gpio, 3, 0, do_gpio, + "set/clear/toggle gpio output pins", + "<set|clear|toggle> <port><pin>\n" + " - set/clear/toggle the specified pin (e.g. PF10)"); diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c index 2c8fd86..18dbdf7 100644 --- a/arch/blackfin/cpu/cpu.c +++ b/arch/blackfin/cpu/cpu.c @@ -91,7 +91,9 @@ int irq_init(void) #else bfin_write_SIC_IMASK(0); #endif - bfin_write_EVT2(evt_default); /* NMI */ + /* Set up a dummy NMI handler if needed. */ + if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219) + bfin_write_EVT2(evt_nmi); /* NMI */ bfin_write_EVT5(evt_default); /* hardware error */ bfin_write_EVT6(evt_default); /* core timer */ bfin_write_EVT7(evt_default); diff --git a/arch/blackfin/cpu/cpu.h b/arch/blackfin/cpu/cpu.h index 0a13c28..ba85e0b 100644 --- a/arch/blackfin/cpu/cpu.h +++ b/arch/blackfin/cpu/cpu.h @@ -29,10 +29,12 @@ void board_reset(void) __attribute__((__weak__)); void bfin_reset_or_hang(void) __attribute__((__noreturn__)); +void bfin_dump(struct pt_regs *reg); void bfin_panic(struct pt_regs *reg); void dump(struct pt_regs *regs); asmlinkage void trap(void); +asmlinkage void evt_nmi(void); asmlinkage void evt_default(void); #endif diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c new file mode 100644 index 0000000..488ca11 --- /dev/null +++ b/arch/blackfin/cpu/gpio.c @@ -0,0 +1,854 @@ +/* + * GPIO Abstraction Layer + * + * Copyright 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/portmux.h> + +#if ANOMALY_05000311 || ANOMALY_05000323 +enum { + AWA_data = SYSCR, + AWA_data_clear = SYSCR, + AWA_data_set = SYSCR, + AWA_toggle = SYSCR, + AWA_maska = UART_SCR, + AWA_maska_clear = UART_SCR, + AWA_maska_set = UART_SCR, + AWA_maska_toggle = UART_SCR, + AWA_maskb = UART_GCTL, + AWA_maskb_clear = UART_GCTL, + AWA_maskb_set = UART_GCTL, + AWA_maskb_toggle = UART_GCTL, + AWA_dir = SPORT1_STAT, + AWA_polar = SPORT1_STAT, + AWA_edge = SPORT1_STAT, + AWA_both = SPORT1_STAT, +#if ANOMALY_05000311 + AWA_inen = TIMER_ENABLE, +#elif ANOMALY_05000323 + AWA_inen = DMA1_1_CONFIG, +#endif +}; + /* Anomaly Workaround */ +#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name) +#else +#define AWA_DUMMY_READ(...) do { } while (0) +#endif + +static struct gpio_port_t * const gpio_array[] = { +#if defined(BF533_FAMILY) + (struct gpio_port_t *) FIO_FLAG_D, +#elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) \ + || defined(BF538_FAMILY) + (struct gpio_port_t *) PORTFIO, +# if !defined(BF538_FAMILY) + (struct gpio_port_t *) PORTGIO, + (struct gpio_port_t *) PORTHIO, +# endif +#elif defined(BF561_FAMILY) + (struct gpio_port_t *) FIO0_FLAG_D, + (struct gpio_port_t *) FIO1_FLAG_D, + (struct gpio_port_t *) FIO2_FLAG_D, +#elif defined(CONFIG_BF54x) + (struct gpio_port_t *)PORTA_FER, + (struct gpio_port_t *)PORTB_FER, + (struct gpio_port_t *)PORTC_FER, + (struct gpio_port_t *)PORTD_FER, + (struct gpio_port_t *)PORTE_FER, + (struct gpio_port_t *)PORTF_FER, + (struct gpio_port_t *)PORTG_FER, + (struct gpio_port_t *)PORTH_FER, + (struct gpio_port_t *)PORTI_FER, + (struct gpio_port_t *)PORTJ_FER, +#else +# error no gpio arrays defined +#endif +}; + +#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) +static unsigned short * const port_fer[] = { + (unsigned short *) PORTF_FER, + (unsigned short *) PORTG_FER, + (unsigned short *) PORTH_FER, +}; + +# if !defined(BF537_FAMILY) +static unsigned short * const port_mux[] = { + (unsigned short *) PORTF_MUX, + (unsigned short *) PORTG_MUX, + (unsigned short *) PORTH_MUX, +}; + +static const +u8 pmux_offset[][16] = { +# if defined(CONFIG_BF52x) + { 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */ + { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */ + { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */ +# elif defined(CONFIG_BF51x) + { 0, 2, 2, 2, 2, 2, 2, 4, 6, 6, 6, 8, 8, 8, 8, 10 }, /* PORTF */ + { 0, 0, 0, 2, 4, 6, 6, 6, 8, 10, 10, 12, 14, 14, 14, 14 }, /* PORTG */ + { 0, 0, 0, 0, 2, 2, 4, 6, 10, 10, 10, 10, 10, 10, 10, 10 }, /* PORTH */ +# endif +}; +# endif + +#elif defined(BF538_FAMILY) +static unsigned short * const port_fer[] = { + (unsigned short *) PORTCIO_FER, + (unsigned short *) PORTDIO_FER, + (unsigned short *) PORTEIO_FER, +}; +#endif + +#ifdef CONFIG_BFIN_GPIO_TRACK +#define RESOURCE_LABEL_SIZE 16 + +static struct str_ident { + char name[RESOURCE_LABEL_SIZE]; +} str_ident[MAX_RESOURCES]; + +static void gpio_error(unsigned gpio) +{ + printf("bfin-gpio: GPIO %d wasn't requested!\n", gpio); +} + +static void set_label(unsigned short ident, const char *label) +{ + if (label) { + strncpy(str_ident[ident].name, label, + RESOURCE_LABEL_SIZE); + str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0; + } +} + +static char *get_label(unsigned short ident) +{ + return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN"); +} + +static int cmp_label(unsigned short ident, const char *label) +{ + if (label == NULL) + printf("bfin-gpio: please provide none-null label\n"); + + if (label) + return strcmp(str_ident[ident].name, label); + else + return -EINVAL; +} + +#define map_entry(m, i) reserved_##m##_map[gpio_bank(i)] +#define is_reserved(m, i, e) (map_entry(m, i) & gpio_bit(i)) +#define reserve(m, i) (map_entry(m, i) |= gpio_bit(i)) +#define unreserve(m, i) (map_entry(m, i) &= ~gpio_bit(i)) +#define DECLARE_RESERVED_MAP(m, c) static unsigned short reserved_##m##_map[c] +#else +#define is_reserved(m, i, e) (!(e)) +#define reserve(m, i) +#define unreserve(m, i) +#define DECLARE_RESERVED_MAP(m, c) +#define gpio_error(gpio) +#define set_label(...) +#define get_label(...) "" +#define cmp_label(...) 1 +#endif + +DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM); +DECLARE_RESERVED_MAP(peri, gpio_bank(MAX_RESOURCES)); + +inline int check_gpio(unsigned gpio) +{ +#if defined(CONFIG_BF54x) + if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 + || gpio == GPIO_PH14 || gpio == GPIO_PH15 + || gpio == GPIO_PJ14 || gpio == GPIO_PJ15) + return -EINVAL; +#endif + if (gpio >= MAX_BLACKFIN_GPIOS) + return -EINVAL; + return 0; +} + +static void port_setup(unsigned gpio, unsigned short usage) +{ +#if defined(BF538_FAMILY) + /* + * BF538/9 Port C,D and E are special. + * Inverted PORT_FER polarity on CDE and no PORF_FER on F + * Regular PORT F GPIOs are handled here, CDE are exclusively + * managed by GPIOLIB + */ + + if (gpio < MAX_BLACKFIN_GPIOS || gpio >= MAX_RESOURCES) + return; + + gpio -= MAX_BLACKFIN_GPIOS; + + if (usage == GPIO_USAGE) + *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio); + else + *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio); + SSYNC(); + return; +#endif + + if (check_gpio(gpio)) + return; + +#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) + if (usage == GPIO_USAGE) + *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio); + else + *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio); + SSYNC(); +#elif defined(CONFIG_BF54x) + if (usage == GPIO_USAGE) + gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio); + else + gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio); + SSYNC(); +#endif +} + +#ifdef BF537_FAMILY +static struct { + unsigned short res; + unsigned short offset; +} port_mux_lut[] = { + {.res = P_PPI0_D13, .offset = 11}, + {.res = P_PPI0_D14, .offset = 11}, + {.res = P_PPI0_D15, .offset = 11}, + {.res = P_SPORT1_TFS, .offset = 11}, + {.res = P_SPORT1_TSCLK, .offset = 11}, + {.res = P_SPORT1_DTPRI, .offset = 11}, + {.res = P_PPI0_D10, .offset = 10}, + {.res = P_PPI0_D11, .offset = 10}, + {.res = P_PPI0_D12, .offset = 10}, + {.res = P_SPORT1_RSCLK, .offset = 10}, + {.res = P_SPORT1_RFS, .offset = 10}, + {.res = P_SPORT1_DRPRI, .offset = 10}, + {.res = P_PPI0_D8, .offset = 9}, + {.res = P_PPI0_D9, .offset = 9}, + {.res = P_SPORT1_DRSEC, .offset = 9}, + {.res = P_SPORT1_DTSEC, .offset = 9}, + {.res = P_TMR2, .offset = 8}, + {.res = P_PPI0_FS3, .offset = 8}, + {.res = P_TMR3, .offset = 7}, + {.res = P_SPI0_SSEL4, .offset = 7}, + {.res = P_TMR4, .offset = 6}, + {.res = P_SPI0_SSEL5, .offset = 6}, + {.res = P_TMR5, .offset = 5}, + {.res = P_SPI0_SSEL6, .offset = 5}, + {.res = P_UART1_RX, .offset = 4}, + {.res = P_UART1_TX, .offset = 4}, + {.res = P_TMR6, .offset = 4}, + {.res = P_TMR7, .offset = 4}, + {.res = P_UART0_RX, .offset = 3}, + {.res = P_UART0_TX, .offset = 3}, + {.res = P_DMAR0, .offset = 3}, + {.res = P_DMAR1, .offset = 3}, + {.res = P_SPORT0_DTSEC, .offset = 1}, + {.res = P_SPORT0_DRSEC, .offset = 1}, + {.res = P_CAN0_RX, .offset = 1}, + {.res = P_CAN0_TX, .offset = 1}, + {.res = P_SPI0_SSEL7, .offset = 1}, + {.res = P_SPORT0_TFS, .offset = 0}, + {.res = P_SPORT0_DTPRI, .offset = 0}, + {.res = P_SPI0_SSEL2, .offset = 0}, + {.res = P_SPI0_SSEL3, .offset = 0}, +}; + +static void portmux_setup(unsigned short per) +{ + u16 y, offset, muxreg; + u16 function = P_FUNCT2MUX(per); + + for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) { + if (port_mux_lut[y].res == per) { + + /* SET PORTMUX REG */ + + offset = port_mux_lut[y].offset; + muxreg = bfin_read_PORT_MUX(); + + if (offset != 1) + muxreg &= ~(1 << offset); + else + muxreg &= ~(3 << 1); + + muxreg |= (function << offset); + bfin_write_PORT_MUX(muxreg); + } + } +} +#elif defined(CONFIG_BF54x) +inline void portmux_setup(unsigned short per) +{ + u32 pmux; + u16 ident = P_IDENT(per); + u16 function = P_FUNCT2MUX(per); + + pmux = gpio_array[gpio_bank(ident)]->port_mux; + + pmux &= ~(0x3 << (2 * gpio_sub_n(ident))); + pmux |= (function & 0x3) << (2 * gpio_sub_n(ident)); + + gpio_array[gpio_bank(ident)]->port_mux = pmux; +} + +inline u16 get_portmux(unsigned short per) +{ + u32 pmux; + u16 ident = P_IDENT(per); + + pmux = gpio_array[gpio_bank(ident)]->port_mux; + + return (pmux >> (2 * gpio_sub_n(ident)) & 0x3); +} +#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) +inline void portmux_setup(unsigned short per) +{ + u16 pmux, ident = P_IDENT(per), function = P_FUNCT2MUX(per); + u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)]; + + pmux = *port_mux[gpio_bank(ident)]; + pmux &= ~(3 << offset); + pmux |= (function & 3) << offset; + *port_mux[gpio_bank(ident)] = pmux; + SSYNC(); +} +#else +# define portmux_setup(...) do { } while (0) +#endif + +#ifndef CONFIG_BF54x +/*********************************************************** +* +* FUNCTIONS: Blackfin General Purpose Ports Access Functions +* +* INPUTS/OUTPUTS: +* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS +* +* +* DESCRIPTION: These functions abstract direct register access +* to Blackfin processor General Purpose +* Ports Regsiters +* +* CAUTION: These functions do not belong to the GPIO Driver API +************************************************************* +* MODIFICATION HISTORY : +**************************************************************/ + +/* Set a specific bit */ + +#define SET_GPIO(name) \ +void set_gpio_ ## name(unsigned gpio, unsigned short arg) \ +{ \ + unsigned long flags; \ + local_irq_save(flags); \ + if (arg) \ + gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \ + else \ + gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \ + AWA_DUMMY_READ(name); \ + local_irq_restore(flags); \ +} + +SET_GPIO(dir) /* set_gpio_dir() */ +SET_GPIO(inen) /* set_gpio_inen() */ +SET_GPIO(polar) /* set_gpio_polar() */ +SET_GPIO(edge) /* set_gpio_edge() */ +SET_GPIO(both) /* set_gpio_both() */ + + +#define SET_GPIO_SC(name) \ +void set_gpio_ ## name(unsigned gpio, unsigned short arg) \ +{ \ + unsigned long flags; \ + if (ANOMALY_05000311 || ANOMALY_05000323) \ + local_irq_save(flags); \ + if (arg) \ + gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \ + else \ + gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \ + if (ANOMALY_05000311 || ANOMALY_05000323) { \ + AWA_DUMMY_READ(name); \ + local_irq_restore(flags); \ + } \ +} + +SET_GPIO_SC(maska) +SET_GPIO_SC(maskb) +SET_GPIO_SC(data) + +void set_gpio_toggle(unsigned gpio) +{ + unsigned long flags; + if (ANOMALY_05000311 || ANOMALY_05000323) + local_irq_save(flags); + gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio); + if (ANOMALY_05000311 || ANOMALY_05000323) { + AWA_DUMMY_READ(toggle); + local_irq_restore(flags); + } +} + +/* Set current PORT date (16-bit word) */ + +#define SET_GPIO_P(name) \ +void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \ +{ \ + unsigned long flags; \ + if (ANOMALY_05000311 || ANOMALY_05000323) \ + local_irq_save(flags); \ + gpio_array[gpio_bank(gpio)]->name = arg; \ + if (ANOMALY_05000311 || ANOMALY_05000323) { \ + AWA_DUMMY_READ(name); \ + local_irq_restore(flags); \ + } \ +} + +SET_GPIO_P(data) +SET_GPIO_P(dir) +SET_GPIO_P(inen) +SET_GPIO_P(polar) +SET_GPIO_P(edge) +SET_GPIO_P(both) +SET_GPIO_P(maska) +SET_GPIO_P(maskb) + +/* Get a specific bit */ +#define GET_GPIO(name) \ +unsigned short get_gpio_ ## name(unsigned gpio) \ +{ \ + unsigned long flags; \ + unsigned short ret; \ + if (ANOMALY_05000311 || ANOMALY_05000323) \ + local_irq_save(flags); \ + ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \ + if (ANOMALY_05000311 || ANOMALY_05000323) { \ + AWA_DUMMY_READ(name); \ + local_irq_restore(flags); \ + } \ + return ret; \ +} + +GET_GPIO(data) +GET_GPIO(dir) +GET_GPIO(inen) +GET_GPIO(polar) +GET_GPIO(edge) +GET_GPIO(both) +GET_GPIO(maska) +GET_GPIO(maskb) + +/* Get current PORT date (16-bit word) */ + +#define GET_GPIO_P(name) \ +unsigned short get_gpiop_ ## name(unsigned gpio) \ +{ \ + unsigned long flags; \ + unsigned short ret; \ + if (ANOMALY_05000311 || ANOMALY_05000323) \ + local_irq_save(flags); \ + ret = (gpio_array[gpio_bank(gpio)]->name); \ + if (ANOMALY_05000311 || ANOMALY_05000323) { \ + AWA_DUMMY_READ(name); \ + local_irq_restore(flags); \ + } \ + return ret; \ +} + +GET_GPIO_P(data) +GET_GPIO_P(dir) +GET_GPIO_P(inen) +GET_GPIO_P(polar) +GET_GPIO_P(edge) +GET_GPIO_P(both) +GET_GPIO_P(maska) +GET_GPIO_P(maskb) + +#else /* CONFIG_BF54x */ + +unsigned short get_gpio_dir(unsigned gpio) +{ + return (0x01 & (gpio_array[gpio_bank(gpio)]->dir_clear >> gpio_sub_n(gpio))); +} + +#endif /* CONFIG_BF54x */ + +/*********************************************************** +* +* FUNCTIONS: Blackfin Peripheral Resource Allocation +* and PortMux Setup +* +* INPUTS/OUTPUTS: +* per Peripheral Identifier +* label String +* +* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API +* +* CAUTION: +************************************************************* +* MODIFICATION HISTORY : +**************************************************************/ + +int peripheral_request(unsigned short per, const char *label) +{ + unsigned short ident = P_IDENT(per); + + /* + * Don't cares are pins with only one dedicated function + */ + + if (per & P_DONTCARE) + return 0; + + if (!(per & P_DEFINED)) + return -ENODEV; + + BUG_ON(ident >= MAX_RESOURCES); + + /* If a pin can be muxed as either GPIO or peripheral, make + * sure it is not already a GPIO pin when we request it. + */ + if (unlikely(!check_gpio(ident) && is_reserved(gpio, ident, 1))) { + printf("%s: Peripheral %d is already reserved as GPIO by %s !\n", + __func__, ident, get_label(ident)); + return -EBUSY; + } + + if (unlikely(is_reserved(peri, ident, 1))) { + + /* + * Pin functions like AMC address strobes my + * be requested and used by several drivers + */ + +#ifdef CONFIG_BF54x + if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) { +#else + if (!(per & P_MAYSHARE)) { +#endif + /* + * Allow that the identical pin function can + * be requested from the same driver twice + */ + + if (cmp_label(ident, label) == 0) + goto anyway; + + printf("%s: Peripheral %d function %d is already reserved by %s !\n", + __func__, ident, P_FUNCT2MUX(per), get_label(ident)); + return -EBUSY; + } + } + + anyway: + reserve(peri, ident); + + portmux_setup(per); + port_setup(ident, PERIPHERAL_USAGE); + + set_label(ident, label); + + return 0; +} + +int peripheral_request_list(const unsigned short per[], const char *label) +{ + u16 cnt; + int ret; + + for (cnt = 0; per[cnt] != 0; cnt++) { + + ret = peripheral_request(per[cnt], label); + + if (ret < 0) { + for ( ; cnt > 0; cnt--) + peripheral_free(per[cnt - 1]); + + return ret; + } + } + + return 0; +} + +void peripheral_free(unsigned short per) +{ + unsigned short ident = P_IDENT(per); + + if (per & P_DONTCARE) + return; + + if (!(per & P_DEFINED)) + return; + + if (unlikely(!is_reserved(peri, ident, 0))) + return; + + if (!(per & P_MAYSHARE)) + port_setup(ident, GPIO_USAGE); + + unreserve(peri, ident); + + set_label(ident, "free"); +} + +void peripheral_free_list(const unsigned short per[]) +{ + u16 cnt; + for (cnt = 0; per[cnt] != 0; cnt++) + peripheral_free(per[cnt]); +} + +/*********************************************************** +* +* FUNCTIONS: Blackfin GPIO Driver +* +* INPUTS/OUTPUTS: +* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS +* label String +* +* DESCRIPTION: Blackfin GPIO Driver API +* +* CAUTION: +************************************************************* +* MODIFICATION HISTORY : +**************************************************************/ + +int bfin_gpio_request(unsigned gpio, const char *label) +{ + if (check_gpio(gpio) < 0) + return -EINVAL; + + /* + * Allow that the identical GPIO can + * be requested from the same driver twice + * Do nothing and return - + */ + + if (cmp_label(gpio, label) == 0) + return 0; + + if (unlikely(is_reserved(gpio, gpio, 1))) { + printf("bfin-gpio: GPIO %d is already reserved by %s !\n", + gpio, get_label(gpio)); + return -EBUSY; + } + if (unlikely(is_reserved(peri, gpio, 1))) { + printf("bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", + gpio, get_label(gpio)); + return -EBUSY; + } +#ifndef CONFIG_BF54x + else { /* Reset POLAR setting when acquiring a gpio for the first time */ + set_gpio_polar(gpio, 0); + } +#endif + + reserve(gpio, gpio); + set_label(gpio, label); + + port_setup(gpio, GPIO_USAGE); + + return 0; +} + +void bfin_gpio_free(unsigned gpio) +{ + if (check_gpio(gpio) < 0) + return; + + if (unlikely(!is_reserved(gpio, gpio, 0))) { + gpio_error(gpio); + return; + } + + unreserve(gpio, gpio); + + set_label(gpio, "free"); +} + +#ifdef BFIN_SPECIAL_GPIO_BANKS +DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES)); + +int bfin_special_gpio_request(unsigned gpio, const char *label) +{ + /* + * Allow that the identical GPIO can + * be requested from the same driver twice + * Do nothing and return - + */ + + if (cmp_label(gpio, label) == 0) + return 0; + + if (unlikely(is_reserved(special_gpio, gpio, 1))) { + printf("bfin-gpio: GPIO %d is already reserved by %s !\n", + gpio, get_label(gpio)); + return -EBUSY; + } + if (unlikely(is_reserved(peri, gpio, 1))) { + printf("bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", + gpio, get_label(gpio)); + + return -EBUSY; + } + + reserve(special_gpio, gpio); + reserve(peri, gpio); + + set_label(gpio, label); + port_setup(gpio, GPIO_USAGE); + + return 0; +} + +void bfin_special_gpio_free(unsigned gpio) +{ + if (unlikely(!is_reserved(special_gpio, gpio, 0))) { + gpio_error(gpio); + return; + } + + reserve(special_gpio, gpio); + reserve(peri, gpio); + set_label(gpio, "free"); +} +#endif + +static inline void __bfin_gpio_direction_input(unsigned gpio) +{ +#ifdef CONFIG_BF54x + gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio); +#else + gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio); +#endif + gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio); +} + +int bfin_gpio_direction_input(unsigned gpio) +{ + unsigned long flags; + + if (!is_reserved(gpio, gpio, 0)) { + gpio_error(gpio); + return -EINVAL; + } + + local_irq_save(flags); + __bfin_gpio_direction_input(gpio); + AWA_DUMMY_READ(inen); + local_irq_restore(flags); + + return 0; +} + +void bfin_gpio_toggle_value(unsigned gpio) +{ +#ifdef CONFIG_BF54x + gpio_set_value(gpio, !gpio_get_value(gpio)); +#else + gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio); +#endif +} + +void bfin_gpio_set_value(unsigned gpio, int arg) +{ + if (arg) + gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio); + else + gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio); +} + +int bfin_gpio_direction_output(unsigned gpio, int value) +{ + unsigned long flags; + + if (!is_reserved(gpio, gpio, 0)) { + gpio_error(gpio); + return -EINVAL; + } + + local_irq_save(flags); + + gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio); + gpio_set_value(gpio, value); +#ifdef CONFIG_BF54x + gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio); +#else + gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio); +#endif + + AWA_DUMMY_READ(dir); + local_irq_restore(flags); + + return 0; +} + +int bfin_gpio_get_value(unsigned gpio) +{ +#ifdef CONFIG_BF54x + return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio))); +#else + unsigned long flags; + + if (unlikely(get_gpio_edge(gpio))) { + int ret; + local_irq_save(flags); + set_gpio_edge(gpio, 0); + ret = get_gpio_data(gpio); + set_gpio_edge(gpio, 1); + local_irq_restore(flags); + return ret; + } else + return get_gpio_data(gpio); +#endif +} + +/* If we are booting from SPI and our board lacks a strong enough pull up, + * the core can reset and execute the bootrom faster than the resistor can + * pull the signal logically high. To work around this (common) error in + * board design, we explicitly set the pin back to GPIO mode, force /CS + * high, and wait for the electrons to do their thing. + * + * This function only makes sense to be called from reset code, but it + * lives here as we need to force all the GPIO states w/out going through + * BUG() checks and such. + */ +void bfin_reset_boot_spi_cs(unsigned short pin) +{ + unsigned short gpio = P_IDENT(pin); + port_setup(gpio, GPIO_USAGE); + gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio); + AWA_DUMMY_READ(data_set); + udelay(1); +} + +#ifdef CONFIG_BFIN_GPIO_TRACK +void bfin_gpio_labels(void) +{ + int c, gpio; + + for (c = 0; c < MAX_RESOURCES; c++) { + gpio = is_reserved(gpio, c, 1); + if (!check_gpio(c) && gpio) + printf("GPIO_%d:\t%s\tGPIO %s\n", c, + get_label(c), + get_gpio_dir(c) ? "OUTPUT" : "INPUT"); + else if (is_reserved(peri, c, 1)) + printf("GPIO_%d:\t%s\tPeripheral\n", c, get_label(c)); + else + continue; + } +} +#endif diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index 5f80ad6..007f5ce 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -101,6 +101,28 @@ static inline void serial_putc(char c) continue; } +__attribute__((always_inline)) static inline void +program_nmi_handler(void) +{ + u32 tmp1, tmp2; + + /* Older bootroms don't create a dummy NMI handler, + * so make one ourselves ASAP in case it fires. + */ + if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219) + return; + + asm volatile ( + "%0 = RETS;" /* Save current RETS */ + "CALL 1f;" /* Figure out current PC */ + "RTN;" /* The simple NMI handler */ + "1:" + "%1 = RETS;" /* Load addr of NMI handler */ + "RETS = %0;" /* Restore RETS */ + "[%2] = %1;" /* Write NMI handler */ + : "=r"(tmp1), "=r"(tmp2) : "ab"(EVT2) + ); +} /* Max SCLK can be 133MHz ... dividing that by (2*4) gives * us a freq of 16MHz for SPI which should generally be @@ -640,6 +662,9 @@ void initcode(ADI_BOOT_DATA *bs) { ADI_BOOT_DATA bootstruct_scratch; + /* Setup NMI handler before anything else */ + program_nmi_handler(); + serial_init(); serial_putc('A'); @@ -675,7 +700,12 @@ void initcode(ADI_BOOT_DATA *bs) #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1 serial_putc('I'); - /* tell the bootrom where our entry point is */ + /* Tell the bootrom where our entry point is so that it knows + * where to jump to when finishing processing the LDR. This + * allows us to avoid small jump blocks in the LDR, and also + * works around anomaly 05000389 (init address in external + * memory causes bootrom to trigger external addressing IVHW). + */ if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE); #endif diff --git a/arch/blackfin/cpu/interrupt.S b/arch/blackfin/cpu/interrupt.S index 69bba3f..0e5e59e 100644 --- a/arch/blackfin/cpu/interrupt.S +++ b/arch/blackfin/cpu/interrupt.S @@ -150,3 +150,8 @@ ENTRY(_evt_default) RESTORE_ALL_SYS rti; ENDPROC(_evt_default) + +/* NMI handler */ +ENTRY(_evt_nmi) + rtn; +ENDPROC(_evt_nmi) diff --git a/arch/blackfin/cpu/serial.h b/arch/blackfin/cpu/serial.h index 5f9be86..f9e311f 100644 --- a/arch/blackfin/cpu/serial.h +++ b/arch/blackfin/cpu/serial.h @@ -26,6 +26,8 @@ #ifndef __ASSEMBLY__ +#include <asm/portmux.h> + #define LOB(x) ((x) & 0xFF) #define HIB(x) (((x) >> 8) & 0xFF) @@ -103,6 +105,23 @@ struct bfin_mmr_serial { __attribute__((always_inline)) static inline void serial_do_portmux(void) { + if (!BFIN_DEBUG_EARLY_SERIAL) { + const unsigned short pins[] = { +#if CONFIG_UART_CONSOLE == 0 + P_UART0_TX, P_UART0_RX, +#elif CONFIG_UART_CONSOLE == 1 + P_UART1_TX, P_UART1_RX, +#elif CONFIG_UART_CONSOLE == 2 + P_UART2_TX, P_UART2_RX, +#elif CONFIG_UART_CONSOLE == 3 + P_UART3_TX, P_UART3_RX, +#endif + 0, + }; + peripheral_request_list(pins, "bfin-uart"); + return; + } + #if defined(__ADSPBF51x__) # define DO_MUX(port, mux_tx, mux_rx, tx, rx) \ bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_2 | PORT_x_MUX_##mux_rx##_FUNC_2); \ diff --git a/arch/blackfin/cpu/traps.c b/arch/blackfin/cpu/traps.c index caaea94..09388aa 100644 --- a/arch/blackfin/cpu/traps.c +++ b/arch/blackfin/cpu/traps.c @@ -29,14 +29,26 @@ #include <asm/deferred.h> #include "cpu.h" +#ifdef CONFIG_DEBUG_DUMP +# define ENABLE_DUMP 1 +#else +# define ENABLE_DUMP 0 +#endif + #define trace_buffer_save(x) \ do { \ + if (!ENABLE_DUMP) \ + break; \ (x) = bfin_read_TBUFCTL(); \ bfin_write_TBUFCTL((x) & ~TBUFEN); \ } while (0) #define trace_buffer_restore(x) \ - bfin_write_TBUFCTL((x)) + do { \ + if (!ENABLE_DUMP) \ + break; \ + bfin_write_TBUFCTL((x)); \ + } while (0); /* The purpose of this map is to provide a mapping of address<->cplb settings * rather than an exact map of what is actually addressable on the part. This @@ -82,8 +94,16 @@ int trap_c(struct pt_regs *regs, uint32_t level) { uint32_t ret = 0; uint32_t trapnr = (regs->seqstat & EXCAUSE); + unsigned long tflags; bool data = false; + /* + * Keep the trace buffer so that a miss here points people + * to the right place (their code). Crashes here rarely + * happen. If they do, only the Blackfin maintainer cares. + */ + trace_buffer_save(tflags); + switch (trapnr) { /* 0x26 - Data CPLB Miss */ case VEC_CPLB_M: @@ -97,7 +117,7 @@ int trap_c(struct pt_regs *regs, uint32_t level) */ if (last_cplb_fault_retx != regs->retx) { last_cplb_fault_retx = regs->retx; - return ret; + break; } } @@ -110,7 +130,6 @@ int trap_c(struct pt_regs *regs, uint32_t level) uint32_t new_cplb_addr = 0, new_cplb_data = 0; static size_t last_evicted; size_t i; - unsigned long tflags; #ifdef CONFIG_EXCEPTION_DEFER /* This should never happen */ @@ -118,13 +137,6 @@ int trap_c(struct pt_regs *regs, uint32_t level) bfin_panic(regs); #endif - /* - * Keep the trace buffer so that a miss here points people - * to the right place (their code). Crashes here rarely - * happen. If they do, only the Blackfin maintainer cares. - */ - trace_buffer_save(tflags); - new_cplb_addr = (data ? bfin_read_DCPLB_FAULT_ADDR() : bfin_read_ICPLB_FAULT_ADDR()) & ~(4 * 1024 * 1024 - 1); for (i = 0; i < ARRAY_SIZE(bfin_memory_map); ++i) { @@ -180,7 +192,6 @@ int trap_c(struct pt_regs *regs, uint32_t level) for (i = 0; i < 16; ++i) debug("%2i 0x%p 0x%08X\n", i, *CPLB_ADDR++, *CPLB_DATA++); - trace_buffer_restore(tflags); break; } #ifdef CONFIG_CMD_KGDB @@ -208,23 +219,21 @@ int trap_c(struct pt_regs *regs, uint32_t level) #ifdef CONFIG_CMD_KGDB if (level == 3) { /* We need to handle this at EVT5, so try again */ + bfin_dump(regs); ret = 1; break; } if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return 0; + break; #endif bfin_panic(regs); } + + trace_buffer_restore(tflags); + return ret; } -#ifdef CONFIG_DEBUG_DUMP -# define ENABLE_DUMP 1 -#else -# define ENABLE_DUMP 0 -#endif - #ifndef CONFIG_KALLSYMS const char *symbol_lookup(unsigned long addr, unsigned long *caddr) { @@ -364,17 +373,14 @@ void dump(struct pt_regs *fp) printf("\n"); } -void dump_bfin_trace_buffer(void) +static void _dump_bfin_trace_buffer(void) { char buf[150]; - unsigned long tflags; int i = 0; if (!ENABLE_DUMP) return; - trace_buffer_save(tflags); - printf("Hardware Trace:\n"); if (bfin_read_TBUFSTAT() & TBUFCNT) { @@ -385,16 +391,21 @@ void dump_bfin_trace_buffer(void) printf(" Source : %s\n", buf); } } +} +void dump_bfin_trace_buffer(void) +{ + unsigned long tflags; + trace_buffer_save(tflags); + _dump_bfin_trace_buffer(); trace_buffer_restore(tflags); } -void bfin_panic(struct pt_regs *regs) +void bfin_dump(struct pt_regs *regs) { - if (ENABLE_DUMP) { - unsigned long tflags; - trace_buffer_save(tflags); - } + unsigned long tflags; + + trace_buffer_save(tflags); puts( "\n" @@ -404,7 +415,16 @@ void bfin_panic(struct pt_regs *regs) "\n" ); dump(regs); - dump_bfin_trace_buffer(); + _dump_bfin_trace_buffer(); puts("\n"); + + trace_buffer_restore(tflags); +} + +void bfin_panic(struct pt_regs *regs) +{ + unsigned long tflags; + trace_buffer_save(tflags); + bfin_dump(regs); bfin_reset_or_hang(); } diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h index 3fd34b3..48f793a 100644 --- a/arch/blackfin/include/asm/blackfin_local.h +++ b/arch/blackfin/include/asm/blackfin_local.h @@ -75,7 +75,15 @@ extern void blackfin_dcache_flush_invalidate_range(const void *, const void *); * regions can only be accessed via DMA, so if the address in question is in * that region, make sure we attempt to DMA indirectly. */ -# define addr_bfin_on_chip_mem(addr) (((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000) +# ifdef __ADSPBF561__ + /* Core B regions all need dma from Core A */ +# define addr_bfin_on_chip_mem(addr) \ + ((((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000) || \ + (((unsigned long)(addr) & 0xFFC00000) == 0xFF400000)) +# else +# define addr_bfin_on_chip_mem(addr) \ + (((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000) +# endif # include <asm/system.h> diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h new file mode 100644 index 0000000..b650ef0 --- /dev/null +++ b/arch/blackfin/include/asm/gpio.h @@ -0,0 +1,201 @@ +/* + * Copyright 2006-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ARCH_BLACKFIN_GPIO_H__ +#define __ARCH_BLACKFIN_GPIO_H__ + +#define gpio_bank(x) ((x) >> 4) +#define gpio_bit(x) (1<<((x) & 0xF)) +#define gpio_sub_n(x) ((x) & 0xF) + +#define GPIO_BANKSIZE 16 +#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE) + +#define GPIO_0 0 +#define GPIO_1 1 +#define GPIO_2 2 +#define GPIO_3 3 +#define GPIO_4 4 +#define GPIO_5 5 +#define GPIO_6 6 +#define GPIO_7 7 +#define GPIO_8 8 +#define GPIO_9 9 +#define GPIO_10 10 +#define GPIO_11 11 +#define GPIO_12 12 +#define GPIO_13 13 +#define GPIO_14 14 +#define GPIO_15 15 +#define GPIO_16 16 +#define GPIO_17 17 +#define GPIO_18 18 +#define GPIO_19 19 +#define GPIO_20 20 +#define GPIO_21 21 +#define GPIO_22 22 +#define GPIO_23 23 +#define GPIO_24 24 +#define GPIO_25 25 +#define GPIO_26 26 +#define GPIO_27 27 +#define GPIO_28 28 +#define GPIO_29 29 +#define GPIO_30 30 +#define GPIO_31 31 +#define GPIO_32 32 +#define GPIO_33 33 +#define GPIO_34 34 +#define GPIO_35 35 +#define GPIO_36 36 +#define GPIO_37 37 +#define GPIO_38 38 +#define GPIO_39 39 +#define GPIO_40 40 +#define GPIO_41 41 +#define GPIO_42 42 +#define GPIO_43 43 +#define GPIO_44 44 +#define GPIO_45 45 +#define GPIO_46 46 +#define GPIO_47 47 + +#define PERIPHERAL_USAGE 1 +#define GPIO_USAGE 0 + +#ifndef __ASSEMBLY__ + +#ifndef CONFIG_BF54x +void set_gpio_dir(unsigned, unsigned short); +void set_gpio_inen(unsigned, unsigned short); +void set_gpio_polar(unsigned, unsigned short); +void set_gpio_edge(unsigned, unsigned short); +void set_gpio_both(unsigned, unsigned short); +void set_gpio_data(unsigned, unsigned short); +void set_gpio_maska(unsigned, unsigned short); +void set_gpio_maskb(unsigned, unsigned short); +void set_gpio_toggle(unsigned); +void set_gpiop_dir(unsigned, unsigned short); +void set_gpiop_inen(unsigned, unsigned short); +void set_gpiop_polar(unsigned, unsigned short); +void set_gpiop_edge(unsigned, unsigned short); +void set_gpiop_both(unsigned, unsigned short); +void set_gpiop_data(unsigned, unsigned short); +void set_gpiop_maska(unsigned, unsigned short); +void set_gpiop_maskb(unsigned, unsigned short); +unsigned short get_gpio_dir(unsigned); +unsigned short get_gpio_inen(unsigned); +unsigned short get_gpio_polar(unsigned); +unsigned short get_gpio_edge(unsigned); +unsigned short get_gpio_both(unsigned); +unsigned short get_gpio_maska(unsigned); +unsigned short get_gpio_maskb(unsigned); +unsigned short get_gpio_data(unsigned); +unsigned short get_gpiop_dir(unsigned); +unsigned short get_gpiop_inen(unsigned); +unsigned short get_gpiop_polar(unsigned); +unsigned short get_gpiop_edge(unsigned); +unsigned short get_gpiop_both(unsigned); +unsigned short get_gpiop_maska(unsigned); +unsigned short get_gpiop_maskb(unsigned); +unsigned short get_gpiop_data(unsigned); + +struct gpio_port_t { + unsigned short data; + unsigned short dummy1; + unsigned short data_clear; + unsigned short dummy2; + unsigned short data_set; + unsigned short dummy3; + unsigned short toggle; + unsigned short dummy4; + unsigned short maska; + unsigned short dummy5; + unsigned short maska_clear; + unsigned short dummy6; + unsigned short maska_set; + unsigned short dummy7; + unsigned short maska_toggle; + unsigned short dummy8; + unsigned short maskb; + unsigned short dummy9; + unsigned short maskb_clear; + unsigned short dummy10; + unsigned short maskb_set; + unsigned short dummy11; + unsigned short maskb_toggle; + unsigned short dummy12; + unsigned short dir; + unsigned short dummy13; + unsigned short polar; + unsigned short dummy14; + unsigned short edge; + unsigned short dummy15; + unsigned short both; + unsigned short dummy16; + unsigned short inen; +}; +#endif + +#ifdef CONFIG_BFIN_GPIO_TRACK +void bfin_gpio_labels(void); +#else +#define bfin_gpio_labels() +#define bfin_gpio_request(gpio, label) bfin_gpio_request(gpio) +#define bfin_special_gpio_request(gpio, label) bfin_special_gpio_request(gpio) +#endif + +#ifdef BFIN_SPECIAL_GPIO_BANKS +void bfin_special_gpio_free(unsigned gpio); +int bfin_special_gpio_request(unsigned gpio, const char *label); +#endif + +int bfin_gpio_request(unsigned gpio, const char *label); +void bfin_gpio_free(unsigned gpio); +int bfin_gpio_direction_input(unsigned gpio); +int bfin_gpio_direction_output(unsigned gpio, int value); +int bfin_gpio_get_value(unsigned gpio); +void bfin_gpio_set_value(unsigned gpio, int value); +void bfin_gpio_toggle_value(unsigned gpio); + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return bfin_gpio_request(gpio, label); +} + +static inline void gpio_free(unsigned gpio) +{ + return bfin_gpio_free(gpio); +} + +static inline int gpio_direction_input(unsigned gpio) +{ + return bfin_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + return bfin_gpio_direction_output(gpio, value); +} + +static inline int gpio_get_value(unsigned gpio) +{ + return bfin_gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + return bfin_gpio_set_value(gpio, value); +} + +static inline int gpio_is_valid(int number) +{ + return number >= 0 && number < MAX_BLACKFIN_GPIOS; +} + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_BLACKFIN_GPIO_H__ */ diff --git a/arch/blackfin/include/asm/mach-bf527/anomaly.h b/arch/blackfin/include/asm/mach-bf527/anomaly.h index 0fd7e31..9358afa 100644 --- a/arch/blackfin/include/asm/mach-bf527/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf527/anomaly.h @@ -1,19 +1,28 @@ /* - * File: include/asm-blackfin/mach-bf527/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. + * Copyright 2004-2010 Analog Devices Inc. + * Licensed under the ADI BSD license. + * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: - * - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List - * - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List + * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List + * - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_ +/* We do not support old silicon - sorry */ +#if __SILICON_REVISION__ < 0 +# error will not work on BF526/BF527 silicon version +#endif + #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) # define ANOMALY_BF526 1 #else @@ -25,10 +34,14 @@ # define ANOMALY_BF527 0 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526) +#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527) +#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527)) + +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ +#define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ @@ -40,167 +53,226 @@ /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ -#define ANOMALY_05000313 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Incorrect Access of OTP_STATUS During otp_write() Function */ -#define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000328 (_ANOMALY_BF527(< 2)) /* Host DMA Boot Modes Are Not Functional */ #define ANOMALY_05000330 (__SILICON_REVISION__ < 2) /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ -#define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000337 (_ANOMALY_BF527(< 2)) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ -#define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000341 (_ANOMALY_BF527(< 2)) /* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ -#define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000342 (_ANOMALY_BF527(< 2)) /* USB Calibration Value Is Not Initialized */ -#define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2)) /* USB Calibration Value to use */ #define ANOMALY_05000346_value 0xE510 /* Preboot Routine Incorrectly Alters Reset Value of USB Register */ -#define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000347 (_ANOMALY_BF527(< 2)) /* Security Features Are Not Functional */ -#define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1) +#define ANOMALY_05000348 (_ANOMALY_BF527(< 1)) /* bfrom_SysControl() Firmware Function Performs Improper System Reset */ -#define ANOMALY_05000353 (ANOMALY_BF526) +#define ANOMALY_05000353 (_ANOMALY_BF526(< 1)) /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ -#define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000355 (_ANOMALY_BF527(< 2)) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000357 (_ANOMALY_BF527(< 2)) /* Incorrect Revision Number in DSPID Register */ -#define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1) +#define ANOMALY_05000364 (_ANOMALY_BF527(== 1)) /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ #define ANOMALY_05000366 (1) /* Incorrect Default CSEL Value in PLL_DIV */ -#define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000368 (_ANOMALY_BF527(< 2)) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000371 (_ANOMALY_BF527(< 2)) /* Authentication Fails To Initiate */ -#define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000376 (_ANOMALY_BF527(< 2)) /* Data Read From L3 Memory by USB DMA May be Corrupted */ -#define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000380 (_ANOMALY_BF527(< 2)) /* 8-Bit NAND Flash Boot Mode Not Functional */ -#define ANOMALY_05000382 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Boot from OTP Memory Not Functional */ -#define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000385 (_ANOMALY_BF527(< 2)) /* bfrom_SysControl() Firmware Routine Not Functional */ -#define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000386 (_ANOMALY_BF527(< 2)) /* Programmable Preboot Settings Not Functional */ -#define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000387 (_ANOMALY_BF527(< 2)) /* CRC32 Checksum Support Not Functional */ -#define ANOMALY_05000388 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Reset Vector Must Not Be in SDRAM Memory Space */ -#define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000389 (_ANOMALY_BF527(< 2)) /* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000392 (_ANOMALY_BF527(< 2)) /* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000393 (_ANOMALY_BF527(< 2)) /* Log Buffer Not Functional */ -#define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000394 (_ANOMALY_BF527(< 2)) /* Hook Routine Not Functional */ -#define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000395 (_ANOMALY_BF527(< 2)) /* Header Indirect Bit Not Functional */ -#define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000396 (_ANOMALY_BF527(< 2)) /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ -#define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000397 (_ANOMALY_BF527(< 2)) /* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */ -#define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000398 (_ANOMALY_BF527(< 2)) /* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */ -#define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000399 (_ANOMALY_BF527(< 2)) /* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ -#define ANOMALY_05000401 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ -#define ANOMALY_05000403 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Lockbox SESR Disallows Certain User Interrupts */ -#define ANOMALY_05000404 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ #define ANOMALY_05000405 (1) /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ -#define ANOMALY_05000407 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ #define ANOMALY_05000408 (1) /* Lockbox firmware leaves MDMA0 channel enabled */ -#define ANOMALY_05000409 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Incorrect Default Internal Voltage Regulator Setting */ -#define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000410 (_ANOMALY_BF527(< 2)) /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ -#define ANOMALY_05000411 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2)) /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ -#define ANOMALY_05000414 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2)) /* DEB2_URGENT Bit Not Functional */ -#define ANOMALY_05000415 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Speculative Fetches Can Cause Undesired External FIFO Operations */ #define ANOMALY_05000416 (1) /* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */ -#define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000417 (_ANOMALY_BF527(< 2)) /* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */ -#define ANOMALY_05000418 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2)) /* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */ -#define ANOMALY_05000420 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2)) /* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ #define ANOMALY_05000421 (1) /* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ -#define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) +#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1)) /* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */ -#define ANOMALY_05000423 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Internal Voltage Regulator Not Trimmed */ -#define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +#define ANOMALY_05000424 (_ANOMALY_BF527(< 2)) /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ -#define ANOMALY_05000425 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ #define ANOMALY_05000426 (1) /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ -#define ANOMALY_05000429 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2)) /* Software System Reset Corrupts PLL_LOCKCNT Register */ -#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) +#define ANOMALY_05000430 (_ANOMALY_BF527(> 1)) /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ #define ANOMALY_05000431 (1) /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ -#define ANOMALY_05000432 (ANOMALY_BF526) +#define ANOMALY_05000432 (_ANOMALY_BF526(< 1)) +/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ +#define ANOMALY_05000434 (1) /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ -#define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527) +#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0)) /* Preboot Cannot be Used to Alter the PLL_DIV Register */ -#define ANOMALY_05000439 (1) +#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0)) /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ -#define ANOMALY_05000440 (1) +#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0)) /* OTP Write Accesses Not Supported */ -#define ANOMALY_05000442 (__SILICON_REVISION__ < 1) +#define ANOMALY_05000442 (_ANOMALY_BF527(< 1)) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) /* The WURESET Bit in the SYSCR Register is not Functional */ #define ANOMALY_05000445 (1) +/* USB DMA Mode 1 Short Packet Data Corruption */ +#define ANOMALY_05000450 (1) /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ #define ANOMALY_05000451 (1) /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ -#define ANOMALY_05000452 (1) +#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0)) /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ #define ANOMALY_05000456 (1) /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ #define ANOMALY_05000457 (1) +/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ +#define ANOMALY_05000460 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_05000461 (1) +/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ +#define ANOMALY_05000462 (1) +/* USB Rx DMA hang */ +#define ANOMALY_05000465 (1) +/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ +#define ANOMALY_05000466 (1) +/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ +#define ANOMALY_05000467 (1) +/* PLL Latches Incorrect Settings During Reset */ +#define ANOMALY_05000469 (1) +/* Incorrect Default MSEL Value in PLL_CTL */ +#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0)) +/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +#define ANOMALY_05000473 (1) +/* Possible Lockup Condition whem Modifying PLL from External Memory */ +#define ANOMALY_05000475 (1) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) +/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ +#define ANOMALY_05000481 (1) +/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */ +#define ANOMALY_05000483 (1) +/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ +#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3)) +/* IFLUSH sucks at life */ +#define ANOMALY_05000491 (1) /* Anomalies that don't exist on this proc */ +#define ANOMALY_05000099 (0) +#define ANOMALY_05000120 (0) #define ANOMALY_05000125 (0) +#define ANOMALY_05000149 (0) #define ANOMALY_05000158 (0) #define ANOMALY_05000171 (0) +#define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000183 (0) +#define ANOMALY_05000189 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) +#define ANOMALY_05000215 (0) +#define ANOMALY_05000219 (0) +#define ANOMALY_05000220 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) +#define ANOMALY_05000231 (0) +#define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000242 (0) #define ANOMALY_05000244 (0) +#define ANOMALY_05000248 (0) +#define ANOMALY_05000250 (0) +#define ANOMALY_05000257 (0) #define ANOMALY_05000261 (0) #define ANOMALY_05000263 (0) #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) +#define ANOMALY_05000274 (0) #define ANOMALY_05000278 (0) +#define ANOMALY_05000281 (0) +#define ANOMALY_05000283 (0) #define ANOMALY_05000285 (0) +#define ANOMALY_05000287 (0) +#define ANOMALY_05000301 (0) #define ANOMALY_05000305 (0) #define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000312 (0) +#define ANOMALY_05000315 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) +#define ANOMALY_05000400 (0) +#define ANOMALY_05000402 (0) #define ANOMALY_05000412 (0) #define ANOMALY_05000447 (0) #define ANOMALY_05000448 (0) +#define ANOMALY_05000474 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf527/def_local.h b/arch/blackfin/include/asm/mach-bf527/def_local.h index 81eca83..1ffa239 100644 --- a/arch/blackfin/include/asm/mach-bf527/def_local.h +++ b/arch/blackfin/include/asm/mach-bf527/def_local.h @@ -1,2 +1,6 @@ +#include "gpio.h" #include "mem_map.h" +#include "portmux.h" #include "ports.h" + +#define CONFIG_BF52x 1 /* Linux glue */ diff --git a/arch/blackfin/include/asm/mach-bf527/gpio.h b/arch/blackfin/include/asm/mach-bf527/gpio.h new file mode 100644 index 0000000..f80c299 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf527/gpio.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2008 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + + +#ifndef _MACH_GPIO_H_ +#define _MACH_GPIO_H_ + +#define MAX_BLACKFIN_GPIOS 48 + +#define GPIO_PF0 0 +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 +#define GPIO_PG0 16 +#define GPIO_PG1 17 +#define GPIO_PG2 18 +#define GPIO_PG3 19 +#define GPIO_PG4 20 +#define GPIO_PG5 21 +#define GPIO_PG6 22 +#define GPIO_PG7 23 +#define GPIO_PG8 24 +#define GPIO_PG9 25 +#define GPIO_PG10 26 +#define GPIO_PG11 27 +#define GPIO_PG12 28 +#define GPIO_PG13 29 +#define GPIO_PG14 30 +#define GPIO_PG15 31 +#define GPIO_PH0 32 +#define GPIO_PH1 33 +#define GPIO_PH2 34 +#define GPIO_PH3 35 +#define GPIO_PH4 36 +#define GPIO_PH5 37 +#define GPIO_PH6 38 +#define GPIO_PH7 39 +#define GPIO_PH8 40 +#define GPIO_PH9 41 +#define GPIO_PH10 42 +#define GPIO_PH11 43 +#define GPIO_PH12 44 +#define GPIO_PH13 45 +#define GPIO_PH14 46 +#define GPIO_PH15 47 + +#define PORT_F GPIO_PF0 +#define PORT_G GPIO_PG0 +#define PORT_H GPIO_PH0 + +#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf527/portmux.h b/arch/blackfin/include/asm/mach-bf527/portmux.h new file mode 100644 index 0000000..aa16558 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf527/portmux.h @@ -0,0 +1,220 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + +#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) +#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) +#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) +#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) + +#if !defined(CONFIG_BF527_SPORT0_PORTG) +#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) +#else +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) +#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1)) +#if !defined(CONFIG_BF527_SPORT0_TSCLK_PG14) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1)) +#else +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) +#endif +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) +#endif + +#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) + +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2)) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2)) + +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2)) + +#if !defined(CONFIG_BF527_UART1_PORTG) +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2)) +#else +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1)) +#endif + +#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(3)) +#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(3)) +#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(3)) + +#define P_HWAIT (P_DONTCARE) + +#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG1 +#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1 + +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2)) +#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2)) +#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2)) +#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) +/* #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */ +#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) +#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) +#define P_MDC (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1)) +#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) +#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) + +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2)) + +#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2)) +#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2)) +#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2)) +#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2)) +#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2)) + +#if defined(CONFIG_BF527_NAND_D_PORTF) +#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2)) +#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2)) +#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2)) +#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2)) +#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2)) +#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2)) +#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2)) +#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2)) +#else /*if defined(CONFIG_BF527_NAND_D_PORTH)*/ +#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) +#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) +#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) +#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) +#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) +#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) +#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) +#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) +#endif + +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0)) +#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0)) +#define P_NAND_WE (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0)) +#define P_NAND_RE (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0)) +#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0)) +#define P_NAND_CLE (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0)) +#define P_NAND_ALE (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0)) + +#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2)) +#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2)) +#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2)) +#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2)) +#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2)) +#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2)) +#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2)) +#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2)) +#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2)) +#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2)) +#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2)) +#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2)) +#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2)) +#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2)) +#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2)) +#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2)) + +#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1)) +#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1)) +#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1)) +#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1)) +#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1)) +#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1)) +#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1)) +#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) +#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1)) +#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1)) +#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1)) +#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1)) +#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1)) +#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1)) +#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) +#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1)) +#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) +#define P_MDIO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1)) + +#define P_TWI0_SCL (P_DONTCARE) +#define P_TWI0_SDA (P_DONTCARE) +#define P_PPI0_FS1 (P_DONTCARE) +#define P_TMR0 (P_DONTCARE) +#define P_TMRCLK (P_DONTCARE) +#define P_PPI0_CLK (P_DONTCARE) + +#define P_MII0 {\ + P_MII0_ETxD0, \ + P_MII0_ETxD1, \ + P_MII0_ETxD2, \ + P_MII0_ETxD3, \ + P_MII0_ETxEN, \ + P_MII0_TxCLK, \ + P_MII0_PHYINT, \ + P_MII0_COL, \ + P_MII0_ERxD0, \ + P_MII0_ERxD1, \ + P_MII0_ERxD2, \ + P_MII0_ERxD3, \ + P_MII0_ERxDV, \ + P_MII0_ERxCLK, \ + P_MII0_ERxER, \ + P_MII0_CRS, \ + P_MDC, \ + P_MDIO, 0} + +#define P_RMII0 {\ + P_MII0_ETxD0, \ + P_MII0_ETxD1, \ + P_MII0_ETxEN, \ + P_MII0_ERxD0, \ + P_MII0_ERxD1, \ + P_MII0_ERxER, \ + P_RMII0_REF_CLK, \ + P_RMII0_MDINT, \ + P_RMII0_CRS_DV, \ + P_MDC, \ + P_MDIO, 0} + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf533/anomaly.h b/arch/blackfin/include/asm/mach-bf533/anomaly.h index c98747f..78f8721 100644 --- a/arch/blackfin/include/asm/mach-bf533/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf533/anomaly.h @@ -1,9 +1,13 @@ /* - * File: include/asm-blackfin/mach-bf533/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. + * Copyright 2004-2010 Analog Devices Inc. + * Licensed under the ADI BSD license. + * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: @@ -34,7 +38,7 @@ # define ANOMALY_BF533 0 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) @@ -46,7 +50,7 @@ #define ANOMALY_05000122 (1) /* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */ #define ANOMALY_05000158 (__SILICON_REVISION__ < 5) -/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ +/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ #define ANOMALY_05000167 (1) @@ -56,13 +60,13 @@ #define ANOMALY_05000180 (1) /* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ #define ANOMALY_05000183 (__SILICON_REVISION__ < 4) -/* False Protection Exceptions */ +/* False Protection Exceptions when Speculative Fetch Is Cancelled */ #define ANOMALY_05000189 (__SILICON_REVISION__ < 4) /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ #define ANOMALY_05000193 (__SILICON_REVISION__ < 4) /* Restarting SPORT in Specific Modes May Cause Data Corruption */ #define ANOMALY_05000194 (__SILICON_REVISION__ < 4) -/* Failing MMR Accesses When Stalled by Preceding Memory Read */ +/* Failing MMR Accesses when Preceding Memory Read Stalls */ #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) /* Current DMA Address Shows Wrong Value During Carry Fix */ #define ANOMALY_05000199 (__SILICON_REVISION__ < 4) @@ -74,7 +78,7 @@ #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) /* Specific Sequence That Can Cause DMA Error or DMA Stopping */ #define ANOMALY_05000203 (__SILICON_REVISION__ < 4) -/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ +/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ #define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533) /* Recovery from "Brown-Out" Condition */ #define ANOMALY_05000207 (__SILICON_REVISION__ < 4) @@ -106,7 +110,7 @@ #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) -/* Data CPLBs Should Prevent Spurious Hardware Errors */ +/* Data CPLBs Should Prevent False Hardware Errors */ #define ANOMALY_05000246 (__SILICON_REVISION__ < 5) /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ == 4) @@ -148,21 +152,21 @@ #define ANOMALY_05000277 (__SILICON_REVISION__ < 6) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 6) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 6) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 6) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (__SILICON_REVISION__ < 6) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 6) /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ #define ANOMALY_05000301 (__SILICON_REVISION__ < 6) -/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ +/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ #define ANOMALY_05000302 (__SILICON_REVISION__ < 5) /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) -/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ +/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */ #define ANOMALY_05000306 (__SILICON_REVISION__ < 5) /* SCKELOW Bit Does Not Maintain State Through Hibernate */ #define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ @@ -170,11 +174,11 @@ #define ANOMALY_05000310 (1) /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ #define ANOMALY_05000311 (__SILICON_REVISION__ < 6) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (__SILICON_REVISION__ < 6) /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (__SILICON_REVISION__ < 6) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 6) /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ #define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6) @@ -200,6 +204,18 @@ #define ANOMALY_05000426 (1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_05000461 (1) +/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +#define ANOMALY_05000473 (1) +/* Possible Lockup Condition whem Modifying PLL from External Memory */ +#define ANOMALY_05000475 (1) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) +/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ +#define ANOMALY_05000481 (1) +/* IFLUSH sucks at life */ +#define ANOMALY_05000491 (1) /* These anomalies have been "phased" out of analog.com anomaly sheets and are * here to show running on older silicon just isn't feasible. @@ -213,17 +229,17 @@ #define ANOMALY_05000070 (__SILICON_REVISION__ < 2) /* Writing FIO_DIR can corrupt a programmable flag's data */ #define ANOMALY_05000079 (__SILICON_REVISION__ < 2) -/* Timer Auto-Baud Mode requires the UART clock to be enabled */ +/* Timer Auto-Baud Mode requires the UART clock to be enabled. */ #define ANOMALY_05000086 (__SILICON_REVISION__ < 2) /* Internal Clocking Modes on SPORT0 not supported */ #define ANOMALY_05000088 (__SILICON_REVISION__ < 2) /* Internal voltage regulator does not wake up from an RTC wakeup */ #define ANOMALY_05000092 (__SILICON_REVISION__ < 2) -/* The IFLUSH instruction must be preceded by a CSYNC instruction */ +/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */ #define ANOMALY_05000093 (__SILICON_REVISION__ < 2) -/* Vectoring to an instruction that is presently being filled into the instruction cache may cause erroneous behavior */ +/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */ #define ANOMALY_05000095 (__SILICON_REVISION__ < 2) -/* PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC */ +/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */ #define ANOMALY_05000096 (__SILICON_REVISION__ < 2) /* Performance Monitor 0 and 1 are swapped when monitoring memory events */ #define ANOMALY_05000097 (__SILICON_REVISION__ < 2) @@ -233,45 +249,45 @@ #define ANOMALY_05000100 (__SILICON_REVISION__ < 2) /* Reading X_MODIFY or Y_MODIFY while DMA channel is active */ #define ANOMALY_05000101 (__SILICON_REVISION__ < 2) -/* Descriptor-based MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ +/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ #define ANOMALY_05000102 (__SILICON_REVISION__ < 2) -/* Incorrect value written to the cycle counters */ +/* Incorrect Value Written to the Cycle Counters */ #define ANOMALY_05000103 (__SILICON_REVISION__ < 2) -/* Stores to L1 Data memory incorrect when a specific sequence is followed */ +/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */ #define ANOMALY_05000104 (__SILICON_REVISION__ < 2) /* Programmable Flag (PF3) functionality not supported in all PPI modes */ #define ANOMALY_05000106 (__SILICON_REVISION__ < 2) /* Data store can be lost when targeting a cache line fill */ #define ANOMALY_05000107 (__SILICON_REVISION__ < 2) -/* Reserved bits in SYSCFG register not set at power on */ +/* Reserved Bits in SYSCFG Register Not Set at Power-On */ #define ANOMALY_05000109 (__SILICON_REVISION__ < 3) /* Infinite Core Stall */ #define ANOMALY_05000114 (__SILICON_REVISION__ < 2) -/* PPI_FSx may glitch when generated by the on chip Timers */ +/* PPI_FSx may glitch when generated by the on chip Timers. */ #define ANOMALY_05000115 (__SILICON_REVISION__ < 2) -/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ +/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) /* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */ #define ANOMALY_05000117 (__SILICON_REVISION__ < 2) /* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */ #define ANOMALY_05000118 (__SILICON_REVISION__ < 2) -/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */ +/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */ #define ANOMALY_05000123 (__SILICON_REVISION__ < 3) /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ #define ANOMALY_05000124 (__SILICON_REVISION__ < 3) -/* Erroneous exception when enabling cache */ +/* Erroneous Exception when Enabling Cache */ #define ANOMALY_05000125 (__SILICON_REVISION__ < 3) /* SPI clock polarity and phase bits incorrect during booting */ #define ANOMALY_05000126 (__SILICON_REVISION__ < 3) -/* DMEM_CONTROL is not set on Reset */ +/* DMEM_CONTROL<12> Is Not Set on Reset */ #define ANOMALY_05000137 (__SILICON_REVISION__ < 3) /* SPI boot will not complete if there is a zero fill block in the loader file */ #define ANOMALY_05000138 (__SILICON_REVISION__ == 2) -/* Timerx_Config must be set for using the PPI in GP output mode with internal Frame Syncs */ +/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */ #define ANOMALY_05000139 (__SILICON_REVISION__ < 2) /* Allowing the SPORT RX FIFO to fill will cause an overflow */ #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ +/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) @@ -285,7 +301,7 @@ #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) -/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */ +/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */ #define ANOMALY_05000148 (__SILICON_REVISION__ < 3) /* Frame Delay in SPORT Multichannel Mode */ #define ANOMALY_05000153 (__SILICON_REVISION__ < 3) @@ -293,13 +309,13 @@ #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) /* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ #define ANOMALY_05000155 (__SILICON_REVISION__ < 3) -/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) -/* SPORT transmit data is not gated by external frame sync in certain conditions */ +/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) -/* SDRAM auto-refresh and subsequent Power Ups */ +/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ #define ANOMALY_05000168 (__SILICON_REVISION__ < 3) -/* DATA CPLB page miss can result in lost write-through cache data writes */ +/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ #define ANOMALY_05000169 (__SILICON_REVISION__ < 3) /* DMA vs Core accesses to external memory */ #define ANOMALY_05000173 (__SILICON_REVISION__ < 3) @@ -307,32 +323,47 @@ #define ANOMALY_05000174 (__SILICON_REVISION__ < 3) /* Overlapping Sequencer and Memory Stalls */ #define ANOMALY_05000175 (__SILICON_REVISION__ < 3) -/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ +/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ #define ANOMALY_05000176 (__SILICON_REVISION__ < 3) -/* Disabling the PPI resets the PPI configuration registers */ +/* Disabling the PPI Resets the PPI Configuration Registers */ #define ANOMALY_05000181 (__SILICON_REVISION__ < 3) -/* PPI TX Mode with 2 External Frame Syncs */ +/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ #define ANOMALY_05000185 (__SILICON_REVISION__ < 3) /* PPI does not invert the Driving PPICLK edge in Transmit Modes */ #define ANOMALY_05000191 (__SILICON_REVISION__ < 3) -/* In PPI Transmit Modes with External Frame Syncs POLC */ +/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */ #define ANOMALY_05000192 (__SILICON_REVISION__ < 3) /* Internal Voltage Regulator may not start up */ #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) /* Anomalies that don't exist on this proc */ +#define ANOMALY_05000120 (0) +#define ANOMALY_05000149 (0) #define ANOMALY_05000171 (0) +#define ANOMALY_05000182 (0) +#define ANOMALY_05000220 (0) +#define ANOMALY_05000248 (0) #define ANOMALY_05000266 (0) +#define ANOMALY_05000274 (0) +#define ANOMALY_05000287 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000353 (1) #define ANOMALY_05000362 (1) +#define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) #define ANOMALY_05000386 (1) +#define ANOMALY_05000389 (0) #define ANOMALY_05000412 (0) #define ANOMALY_05000430 (0) #define ANOMALY_05000432 (0) #define ANOMALY_05000435 (0) #define ANOMALY_05000447 (0) #define ANOMALY_05000448 (0) +#define ANOMALY_05000456 (0) +#define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) +#define ANOMALY_05000474 (0) +#define ANOMALY_05000485 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf533/def_local.h b/arch/blackfin/include/asm/mach-bf533/def_local.h index 14c111f..c545b54 100644 --- a/arch/blackfin/include/asm/mach-bf533/def_local.h +++ b/arch/blackfin/include/asm/mach-bf533/def_local.h @@ -1 +1,5 @@ +#include "gpio.h" +#include "portmux.h" #include "ports.h" + +#define BF533_FAMILY 1 /* Linux glue */ diff --git a/arch/blackfin/include/asm/mach-bf533/gpio.h b/arch/blackfin/include/asm/mach-bf533/gpio.h new file mode 100644 index 0000000..e02416d --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf533/gpio.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2008 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + + +#ifndef _MACH_GPIO_H_ +#define _MACH_GPIO_H_ + +#define MAX_BLACKFIN_GPIOS 16 + +#define GPIO_PF0 0 +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 + +#define PORT_F GPIO_PF0 + +#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf533/portmux.h b/arch/blackfin/include/asm/mach-bf533/portmux.h new file mode 100644 index 0000000..96f5d91 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf533/portmux.h @@ -0,0 +1,71 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + +#define P_PPI0_CLK (P_DONTCARE) +#define P_PPI0_FS1 (P_DONTCARE) +#define P_PPI0_FS2 (P_DONTCARE) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11)) +#define P_PPI0_D0 (P_DONTCARE) +#define P_PPI0_D1 (P_DONTCARE) +#define P_PPI0_D2 (P_DONTCARE) +#define P_PPI0_D3 (P_DONTCARE) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12)) + +#define P_SPORT1_TSCLK (P_DONTCARE) +#define P_SPORT1_RSCLK (P_DONTCARE) +#define P_SPORT0_TSCLK (P_DONTCARE) +#define P_SPORT0_RSCLK (P_DONTCARE) +#define P_UART0_RX (P_DONTCARE) +#define P_UART0_TX (P_DONTCARE) +#define P_SPORT1_DRSEC (P_DONTCARE) +#define P_SPORT1_RFS (P_DONTCARE) +#define P_SPORT1_DTPRI (P_DONTCARE) +#define P_SPORT1_DTSEC (P_DONTCARE) +#define P_SPORT1_TFS (P_DONTCARE) +#define P_SPORT1_DRPRI (P_DONTCARE) +#define P_SPORT0_DRSEC (P_DONTCARE) +#define P_SPORT0_RFS (P_DONTCARE) +#define P_SPORT0_DTPRI (P_DONTCARE) +#define P_SPORT0_DTSEC (P_DONTCARE) +#define P_SPORT0_TFS (P_DONTCARE) +#define P_SPORT0_DRPRI (P_DONTCARE) + +#define P_SPI0_MOSI (P_DONTCARE) +#define P_SPI0_MISO (P_DONTCARE) +#define P_SPI0_SCK (P_DONTCARE) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) +#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2 +#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2 + +#define P_TMR2 (P_DONTCARE) +#define P_TMR1 (P_DONTCARE) +#define P_TMR0 (P_DONTCARE) +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1)) + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf537/anomaly.h b/arch/blackfin/include/asm/mach-bf537/anomaly.h index b7f1a3f..43df6af 100644 --- a/arch/blackfin/include/asm/mach-bf537/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf537/anomaly.h @@ -1,9 +1,13 @@ /* - * File: include/asm-blackfin/mach-bf537/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. + * Copyright 2004-2010 Analog Devices Inc. + * Licensed under the ADI BSD license. + * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: @@ -34,13 +38,13 @@ # define ANOMALY_BF537 0 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ #define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ #define ANOMALY_05000157 (__SILICON_REVISION__ < 2) /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ #define ANOMALY_05000180 (1) @@ -50,11 +54,11 @@ #define ANOMALY_05000244 (__SILICON_REVISION__ < 3) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) -/* CLKIN Buffer Output Enable Reset Behavior Is Changed */ +/* Buffered CLKIN Output Is Disabled by Default */ #define ANOMALY_05000247 (1) /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ < 3) -/* EMAC Tx DMA error after an early frame abort */ +/* EMAC TX DMA Error After an Early Frame Abort */ #define ANOMALY_05000252 (__SILICON_REVISION__ < 3) /* Maximum External Clock Speed for Timers */ #define ANOMALY_05000253 (__SILICON_REVISION__ < 3) @@ -62,7 +66,7 @@ #define ANOMALY_05000254 (__SILICON_REVISION__ > 2) /* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ #define ANOMALY_05000255 (__SILICON_REVISION__ < 3) -/* EMAC MDIO input latched on wrong MDC edge */ +/* EMAC MDIO Input Latched on Wrong MDC Edge */ #define ANOMALY_05000256 (__SILICON_REVISION__ < 3) /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ #define ANOMALY_05000257 (__SILICON_REVISION__ < 3) @@ -80,7 +84,7 @@ #define ANOMALY_05000264 (__SILICON_REVISION__ < 3) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) -/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */ +/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */ #define ANOMALY_05000268 (__SILICON_REVISION__ < 3) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ #define ANOMALY_05000270 (__SILICON_REVISION__ < 3) @@ -92,15 +96,15 @@ #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) -/* SPI Master boot mode does not work well with Atmel Data flash devices */ +/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */ #define ANOMALY_05000280 (1) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 3) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 3) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (__SILICON_REVISION__ < 3) -/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */ +/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */ #define ANOMALY_05000285 (__SILICON_REVISION__ < 3) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 3) @@ -112,25 +116,25 @@ #define ANOMALY_05000305 (__SILICON_REVISION__ < 3) /* SCKELOW Bit Does Not Maintain State Through Hibernate */ #define ANOMALY_05000307 (__SILICON_REVISION__ < 3) -/* Writing UART_THR while UART clock is disabled sends erroneous start bit */ +/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */ #define ANOMALY_05000309 (__SILICON_REVISION__ < 3) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (1) /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (1) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 3) -/* EMAC RMII mode: collisions occur in Full Duplex mode */ +/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */ #define ANOMALY_05000316 (__SILICON_REVISION__ < 3) -/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */ +/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */ #define ANOMALY_05000321 (__SILICON_REVISION__ < 3) -/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ +/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */ #define ANOMALY_05000322 (1) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) -/* New Feature: UART Remains Enabled after UART Boot */ +/* UART Gets Disabled after UART Boot */ #define ANOMALY_05000350 (__SILICON_REVISION__ >= 3) /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ #define ANOMALY_05000355 (1) @@ -143,7 +147,7 @@ /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (1) /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) +#define ANOMALY_05000402 (__SILICON_REVISION__ == 2) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ #define ANOMALY_05000403 (1) /* Speculative Fetches Can Cause Undesired External FIFO Operations */ @@ -154,29 +158,66 @@ #define ANOMALY_05000426 (1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_05000461 (1) +/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +#define ANOMALY_05000473 (1) +/* Possible Lockup Condition whem Modifying PLL from External Memory */ +#define ANOMALY_05000475 (1) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) +/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ +#define ANOMALY_05000481 (1) +/* IFLUSH sucks at life */ +#define ANOMALY_05000491 (1) /* Anomalies that don't exist on this proc */ +#define ANOMALY_05000099 (0) +#define ANOMALY_05000120 (0) #define ANOMALY_05000125 (0) +#define ANOMALY_05000149 (0) #define ANOMALY_05000158 (0) #define ANOMALY_05000171 (0) +#define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000183 (0) +#define ANOMALY_05000189 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) +#define ANOMALY_05000215 (0) +#define ANOMALY_05000219 (0) +#define ANOMALY_05000220 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) +#define ANOMALY_05000231 (0) +#define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000242 (0) +#define ANOMALY_05000248 (0) #define ANOMALY_05000266 (0) +#define ANOMALY_05000274 (0) +#define ANOMALY_05000287 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000353 (1) #define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) +#define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) #define ANOMALY_05000386 (1) +#define ANOMALY_05000389 (0) +#define ANOMALY_05000400 (0) #define ANOMALY_05000412 (0) #define ANOMALY_05000430 (0) #define ANOMALY_05000432 (0) #define ANOMALY_05000435 (0) #define ANOMALY_05000447 (0) #define ANOMALY_05000448 (0) +#define ANOMALY_05000456 (0) +#define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) +#define ANOMALY_05000474 (0) +#define ANOMALY_05000485 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf537/def_local.h b/arch/blackfin/include/asm/mach-bf537/def_local.h index 14c111f..e210db9 100644 --- a/arch/blackfin/include/asm/mach-bf537/def_local.h +++ b/arch/blackfin/include/asm/mach-bf537/def_local.h @@ -1 +1,5 @@ +#include "gpio.h" +#include "portmux.h" #include "ports.h" + +#define BF537_FAMILY 1 /* Linux glue */ diff --git a/arch/blackfin/include/asm/mach-bf537/gpio.h b/arch/blackfin/include/asm/mach-bf537/gpio.h new file mode 100644 index 0000000..f80c299 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf537/gpio.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2008 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + + +#ifndef _MACH_GPIO_H_ +#define _MACH_GPIO_H_ + +#define MAX_BLACKFIN_GPIOS 48 + +#define GPIO_PF0 0 +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 +#define GPIO_PG0 16 +#define GPIO_PG1 17 +#define GPIO_PG2 18 +#define GPIO_PG3 19 +#define GPIO_PG4 20 +#define GPIO_PG5 21 +#define GPIO_PG6 22 +#define GPIO_PG7 23 +#define GPIO_PG8 24 +#define GPIO_PG9 25 +#define GPIO_PG10 26 +#define GPIO_PG11 27 +#define GPIO_PG12 28 +#define GPIO_PG13 29 +#define GPIO_PG14 30 +#define GPIO_PG15 31 +#define GPIO_PH0 32 +#define GPIO_PH1 33 +#define GPIO_PH2 34 +#define GPIO_PH3 35 +#define GPIO_PH4 36 +#define GPIO_PH5 37 +#define GPIO_PH6 38 +#define GPIO_PH7 39 +#define GPIO_PH8 40 +#define GPIO_PH9 41 +#define GPIO_PH10 42 +#define GPIO_PH11 43 +#define GPIO_PH12 44 +#define GPIO_PH13 45 +#define GPIO_PH14 46 +#define GPIO_PH15 47 + +#define PORT_F GPIO_PF0 +#define PORT_G GPIO_PG0 +#define PORT_H GPIO_PH0 + +#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf537/portmux.h b/arch/blackfin/include/asm/mach-bf537/portmux.h new file mode 100644 index 0000000..71d9eae --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf537/portmux.h @@ -0,0 +1,152 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */ + +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) +#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) +#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) +#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) +#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) +#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) +#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) +#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) +#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) +#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) +#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF10 +#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1 + +#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) +#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) +#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) +#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) +#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) + +#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) +#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) +#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) +#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) +#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) +#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) +#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) +#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) +#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0)) +#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0)) +#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0)) +#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0)) +#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0)) +#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0)) +#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0)) +#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0)) +#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1)) +#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) +#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1)) + +#define PORT_PJ0 (GPIO_PH15 + 1) +#define PORT_PJ1 (GPIO_PH15 + 2) +#define PORT_PJ2 (GPIO_PH15 + 3) +#define PORT_PJ3 (GPIO_PH15 + 4) +#define PORT_PJ4 (GPIO_PH15 + 5) +#define PORT_PJ5 (GPIO_PH15 + 6) +#define PORT_PJ6 (GPIO_PH15 + 7) +#define PORT_PJ7 (GPIO_PH15 + 8) +#define PORT_PJ8 (GPIO_PH15 + 9) +#define PORT_PJ9 (GPIO_PH15 + 10) +#define PORT_PJ10 (GPIO_PH15 + 11) +#define PORT_PJ11 (GPIO_PH15 + 12) + +#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0)) +#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0)) +#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0)) +#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0)) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0)) +#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0)) +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0)) +#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1)) +#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1)) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2)) + +#define P_MII0 {\ + P_MII0_ETxD0, \ + P_MII0_ETxD1, \ + P_MII0_ETxD2, \ + P_MII0_ETxD3, \ + P_MII0_ETxEN, \ + P_MII0_TxCLK, \ + P_MII0_PHYINT, \ + P_MII0_COL, \ + P_MII0_ERxD0, \ + P_MII0_ERxD1, \ + P_MII0_ERxD2, \ + P_MII0_ERxD3, \ + P_MII0_ERxDV, \ + P_MII0_ERxCLK, \ + P_MII0_ERxER, \ + P_MII0_CRS, \ + P_MDC, \ + P_MDIO, 0} + +#define P_RMII0 {\ + P_MII0_ETxD0, \ + P_MII0_ETxD1, \ + P_MII0_ETxEN, \ + P_MII0_ERxD0, \ + P_MII0_ERxD1, \ + P_MII0_ERxER, \ + P_RMII0_REF_CLK, \ + P_RMII0_MDINT, \ + P_RMII0_CRS_DV, \ + P_MDC, \ + P_MDIO, 0} + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf548/anomaly.h b/arch/blackfin/include/asm/mach-bf548/anomaly.h index 192dd67..7bda09c 100644 --- a/arch/blackfin/include/asm/mach-bf548/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf548/anomaly.h @@ -1,41 +1,54 @@ /* - * File: include/asm-blackfin/mach-bf548/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. + * Copyright 2004-2010 Analog Devices Inc. + * Licensed under the ADI BSD license. + * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: - * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List + * - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_ -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* We do not support 0.0 or 0.1 silicon - sorry */ +/* XXX: let u-boot slide +#if __SILICON_REVISION__ < 2 +# error will not work on BF548 silicon version 0.0, or 0.1 +#endif +*/ + +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ #define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) +/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */ +#define ANOMALY_05000220 (1) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) -/* False Hardware Error Exception When ISR Context Is Not Restored */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 1) /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ #define ANOMALY_05000304 (__SILICON_REVISION__ < 1) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (__SILICON_REVISION__ < 1) /* TWI Slave Boot Mode Is Not Functional */ #define ANOMALY_05000324 (__SILICON_REVISION__ < 1) -/* External FIFO Boot Mode Is Not Functional */ +/* FIFO Boot Mode Not Functional */ #define ANOMALY_05000325 (__SILICON_REVISION__ < 2) /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ #define ANOMALY_05000327 (__SILICON_REVISION__ < 1) @@ -157,6 +170,8 @@ #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ #define ANOMALY_05000431 (__SILICON_REVISION__ < 3) +/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ +#define ANOMALY_05000434 (1) /* OTP Write Accesses Not Supported */ #define ANOMALY_05000442 (__SILICON_REVISION__ < 1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ @@ -170,32 +185,93 @@ /* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */ #define ANOMALY_05000449 (__SILICON_REVISION__ == 1) /* USB DMA Mode 1 Short Packet Data Corruption */ -#define ANOMALY_05000450 (1 +#define ANOMALY_05000450 (1) +/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ +#define ANOMALY_05000452 (__SILICON_REVISION__ < 1) +/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ +#define ANOMALY_05000456 (1) +/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ +#define ANOMALY_05000457 (1) +/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ +#define ANOMALY_05000460 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_05000461 (1) +/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ +#define ANOMALY_05000462 (1) +/* USB DMA RX Data Corruption */ +#define ANOMALY_05000463 (1) +/* USB TX DMA Hang */ +#define ANOMALY_05000464 (1) +/* USB Rx DMA hang */ +#define ANOMALY_05000465 (1) +/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ +#define ANOMALY_05000466 (1) +/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ +#define ANOMALY_05000467 (1) +/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +#define ANOMALY_05000473 (1) +/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */ +#define ANOMALY_05000474 (1) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) +/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ +#define ANOMALY_05000481 (1) +/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */ +#define ANOMALY_05000483 (1) +/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ +#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2) +/* IFLUSH sucks at life */ +#define ANOMALY_05000491 (1) /* Anomalies that don't exist on this proc */ +#define ANOMALY_05000099 (0) +#define ANOMALY_05000120 (0) #define ANOMALY_05000125 (0) +#define ANOMALY_05000149 (0) #define ANOMALY_05000158 (0) #define ANOMALY_05000171 (0) +#define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) #define ANOMALY_05000183 (0) +#define ANOMALY_05000189 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) +#define ANOMALY_05000215 (0) +#define ANOMALY_05000219 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) +#define ANOMALY_05000231 (0) +#define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000242 (0) #define ANOMALY_05000244 (0) +#define ANOMALY_05000248 (0) +#define ANOMALY_05000250 (0) +#define ANOMALY_05000254 (0) +#define ANOMALY_05000257 (0) #define ANOMALY_05000261 (0) #define ANOMALY_05000263 (0) #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) +#define ANOMALY_05000274 (0) #define ANOMALY_05000278 (0) +#define ANOMALY_05000283 (0) +#define ANOMALY_05000287 (0) +#define ANOMALY_05000301 (0) #define ANOMALY_05000305 (0) #define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) +#define ANOMALY_05000315 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) +#define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) +#define ANOMALY_05000400 (0) +#define ANOMALY_05000402 (0) #define ANOMALY_05000412 (0) #define ANOMALY_05000432 (0) #define ANOMALY_05000435 (0) +#define ANOMALY_05000475 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf548/def_local.h b/arch/blackfin/include/asm/mach-bf548/def_local.h index 81eca83..f1e69a7 100644 --- a/arch/blackfin/include/asm/mach-bf548/def_local.h +++ b/arch/blackfin/include/asm/mach-bf548/def_local.h @@ -1,2 +1,6 @@ +#include "gpio.h" #include "mem_map.h" +#include "portmux.h" #include "ports.h" + +#define CONFIG_BF54x 1 /* Linux glue */ diff --git a/arch/blackfin/include/asm/mach-bf548/gpio.h b/arch/blackfin/include/asm/mach-bf548/gpio.h new file mode 100644 index 0000000..28037e3 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf548/gpio.h @@ -0,0 +1,203 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + + +#ifndef _MACH_GPIO_H_ +#define _MACH_GPIO_H_ + +#define GPIO_PA0 0 +#define GPIO_PA1 1 +#define GPIO_PA2 2 +#define GPIO_PA3 3 +#define GPIO_PA4 4 +#define GPIO_PA5 5 +#define GPIO_PA6 6 +#define GPIO_PA7 7 +#define GPIO_PA8 8 +#define GPIO_PA9 9 +#define GPIO_PA10 10 +#define GPIO_PA11 11 +#define GPIO_PA12 12 +#define GPIO_PA13 13 +#define GPIO_PA14 14 +#define GPIO_PA15 15 +#define GPIO_PB0 16 +#define GPIO_PB1 17 +#define GPIO_PB2 18 +#define GPIO_PB3 19 +#define GPIO_PB4 20 +#define GPIO_PB5 21 +#define GPIO_PB6 22 +#define GPIO_PB7 23 +#define GPIO_PB8 24 +#define GPIO_PB9 25 +#define GPIO_PB10 26 +#define GPIO_PB11 27 +#define GPIO_PB12 28 +#define GPIO_PB13 29 +#define GPIO_PB14 30 +#define GPIO_PB15 31 /* N/A */ +#define GPIO_PC0 32 +#define GPIO_PC1 33 +#define GPIO_PC2 34 +#define GPIO_PC3 35 +#define GPIO_PC4 36 +#define GPIO_PC5 37 +#define GPIO_PC6 38 +#define GPIO_PC7 39 +#define GPIO_PC8 40 +#define GPIO_PC9 41 +#define GPIO_PC10 42 +#define GPIO_PC11 43 +#define GPIO_PC12 44 +#define GPIO_PC13 45 +#define GPIO_PC14 46 /* N/A */ +#define GPIO_PC15 47 /* N/A */ +#define GPIO_PD0 48 +#define GPIO_PD1 49 +#define GPIO_PD2 50 +#define GPIO_PD3 51 +#define GPIO_PD4 52 +#define GPIO_PD5 53 +#define GPIO_PD6 54 +#define GPIO_PD7 55 +#define GPIO_PD8 56 +#define GPIO_PD9 57 +#define GPIO_PD10 58 +#define GPIO_PD11 59 +#define GPIO_PD12 60 +#define GPIO_PD13 61 +#define GPIO_PD14 62 +#define GPIO_PD15 63 +#define GPIO_PE0 64 +#define GPIO_PE1 65 +#define GPIO_PE2 66 +#define GPIO_PE3 67 +#define GPIO_PE4 68 +#define GPIO_PE5 69 +#define GPIO_PE6 70 +#define GPIO_PE7 71 +#define GPIO_PE8 72 +#define GPIO_PE9 73 +#define GPIO_PE10 74 +#define GPIO_PE11 75 +#define GPIO_PE12 76 +#define GPIO_PE13 77 +#define GPIO_PE14 78 +#define GPIO_PE15 79 +#define GPIO_PF0 80 +#define GPIO_PF1 81 +#define GPIO_PF2 82 +#define GPIO_PF3 83 +#define GPIO_PF4 84 +#define GPIO_PF5 85 +#define GPIO_PF6 86 +#define GPIO_PF7 87 +#define GPIO_PF8 88 +#define GPIO_PF9 89 +#define GPIO_PF10 90 +#define GPIO_PF11 91 +#define GPIO_PF12 92 +#define GPIO_PF13 93 +#define GPIO_PF14 94 +#define GPIO_PF15 95 +#define GPIO_PG0 96 +#define GPIO_PG1 97 +#define GPIO_PG2 98 +#define GPIO_PG3 99 +#define GPIO_PG4 100 +#define GPIO_PG5 101 +#define GPIO_PG6 102 +#define GPIO_PG7 103 +#define GPIO_PG8 104 +#define GPIO_PG9 105 +#define GPIO_PG10 106 +#define GPIO_PG11 107 +#define GPIO_PG12 108 +#define GPIO_PG13 109 +#define GPIO_PG14 110 +#define GPIO_PG15 111 +#define GPIO_PH0 112 +#define GPIO_PH1 113 +#define GPIO_PH2 114 +#define GPIO_PH3 115 +#define GPIO_PH4 116 +#define GPIO_PH5 117 +#define GPIO_PH6 118 +#define GPIO_PH7 119 +#define GPIO_PH8 120 +#define GPIO_PH9 121 +#define GPIO_PH10 122 +#define GPIO_PH11 123 +#define GPIO_PH12 124 +#define GPIO_PH13 125 +#define GPIO_PH14 126 /* N/A */ +#define GPIO_PH15 127 /* N/A */ +#define GPIO_PI0 128 +#define GPIO_PI1 129 +#define GPIO_PI2 130 +#define GPIO_PI3 131 +#define GPIO_PI4 132 +#define GPIO_PI5 133 +#define GPIO_PI6 134 +#define GPIO_PI7 135 +#define GPIO_PI8 136 +#define GPIO_PI9 137 +#define GPIO_PI10 138 +#define GPIO_PI11 139 +#define GPIO_PI12 140 +#define GPIO_PI13 141 +#define GPIO_PI14 142 +#define GPIO_PI15 143 +#define GPIO_PJ0 144 +#define GPIO_PJ1 145 +#define GPIO_PJ2 146 +#define GPIO_PJ3 147 +#define GPIO_PJ4 148 +#define GPIO_PJ5 149 +#define GPIO_PJ6 150 +#define GPIO_PJ7 151 +#define GPIO_PJ8 152 +#define GPIO_PJ9 153 +#define GPIO_PJ10 154 +#define GPIO_PJ11 155 +#define GPIO_PJ12 156 +#define GPIO_PJ13 157 +#define GPIO_PJ14 158 /* N/A */ +#define GPIO_PJ15 159 /* N/A */ + +#define MAX_BLACKFIN_GPIOS 160 + +#ifndef __ASSEMBLY__ + +struct gpio_port_t { + unsigned short port_fer; + unsigned short dummy1; + unsigned short data; + unsigned short dummy2; + unsigned short data_set; + unsigned short dummy3; + unsigned short data_clear; + unsigned short dummy4; + unsigned short dir_set; + unsigned short dummy5; + unsigned short dir_clear; + unsigned short dummy6; + unsigned short inen; + unsigned short dummy7; + unsigned int port_mux; +}; + +struct gpio_port_s { + unsigned short fer; + unsigned short data; + unsigned short dir; + unsigned short inen; + unsigned int mux; +}; + +#endif + +#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf548/portmux.h b/arch/blackfin/include/asm/mach-bf548/portmux.h new file mode 100644 index 0000000..e222462 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf548/portmux.h @@ -0,0 +1,320 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + +#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) +#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) +#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0)) +#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0)) +#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0)) +#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0)) +#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0)) +#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0)) +#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0)) +#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0)) +#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0)) +#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0)) +#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0)) +#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0)) +#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0)) +#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1)) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1)) + +#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0)) +#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0)) +#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0)) +#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0)) +#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0)) +#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0)) +#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0)) +#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0)) +#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0)) +#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0)) +#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0)) +#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0)) +#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0)) +#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0)) +#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1)) + +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0)) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0)) +#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0)) +#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0)) +#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0)) +#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0)) +#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0)) +#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0)) +#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0)) +#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1)) +#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1)) + +#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0)) +#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0)) +#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0)) +#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0)) +#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0)) +#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0)) +#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0)) +#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0)) +#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0)) +#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0)) +#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0)) +#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0)) +#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0)) +#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0)) +#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0)) +#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0)) + +#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1)) +#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1)) +#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1)) +#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1)) +#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1)) +#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1)) +#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1)) +#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1)) +#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1)) +#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1)) +#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1)) +#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1)) +#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1)) +#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1)) +#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1)) +#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2)) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2)) +#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2)) +#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2)) +#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2)) +#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2)) +#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2)) +#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2)) +#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2)) +#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2)) +#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2)) +#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3)) +#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3)) +#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3)) +#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3)) +#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3)) +#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3)) +#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3)) +#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3)) +#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3)) +#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3)) +#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3)) +#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3)) +#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3)) +#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3)) + +#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PE4 +#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1 +#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0)) +#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0)) +#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0)) +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0)) +#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0)) +#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0)) +#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0)) +#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0)) +#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0)) +#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0)) +#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0)) +#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1)) +#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1)) +#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1)) +#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1)) +#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1)) +#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1)) +#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1)) +#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1)) + +#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) +#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) +#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) +#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) + +#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT +# define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) +# define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) +# define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) +# define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) +# define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) +# define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) +# define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) +# define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) +# define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) +# define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) +# define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) +# define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) +# define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) +# define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) +# define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) +# define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) +#else +# define P_ATAPI_D0A (P_DONTCARE) +# define P_ATAPI_D1A (P_DONTCARE) +# define P_ATAPI_D2A (P_DONTCARE) +# define P_ATAPI_D3A (P_DONTCARE) +# define P_ATAPI_D4A (P_DONTCARE) +# define P_ATAPI_D5A (P_DONTCARE) +# define P_ATAPI_D6A (P_DONTCARE) +# define P_ATAPI_D7A (P_DONTCARE) +# define P_ATAPI_D8A (P_DONTCARE) +# define P_ATAPI_D9A (P_DONTCARE) +# define P_ATAPI_D10A (P_DONTCARE) +# define P_ATAPI_D11A (P_DONTCARE) +# define P_ATAPI_D12A (P_DONTCARE) +# define P_ATAPI_D13A (P_DONTCARE) +# define P_ATAPI_D14A (P_DONTCARE) +# define P_ATAPI_D15A (P_DONTCARE) +#endif + +#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) +#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) +#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) +#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) +#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) +#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) +#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) +#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) +#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) +#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) +#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) +#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) +#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) +#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) +#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) +#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT +# define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1)) +# define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1)) +# define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) +#else +# define P_ATAPI_A0A (P_DONTCARE) +# define P_ATAPI_A1A (P_DONTCARE) +# define P_ATAPI_A2A (P_DONTCARE) +#endif +#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1)) +#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) +#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) +#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) +#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2)) +#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) +#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2)) +#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3)) + +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) +#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) +#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) +#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) +#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) +#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) +#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) +#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0)) +#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0)) +#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0)) +#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0)) +#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0)) +#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0)) +#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) +#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1)) +#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1)) +#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1)) +#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1)) +#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1)) +#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2)) +#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2)) +#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2)) + +#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0)) +#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0)) +#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0)) +#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0)) +#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0)) +#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0)) +#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0)) +#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0)) +#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0)) +#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0)) +#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0)) +#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0)) +#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0)) +#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0)) +#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0)) +#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0)) +#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1)) + +#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0)) +#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0)) +#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0)) +#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0)) +#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0)) +#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0)) +#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0)) +#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0)) +#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0)) +#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0)) +#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0)) +#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0)) +#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0)) +#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0)) + + +#define P_NAND_D0 (P_DONTCARE) +#define P_NAND_D1 (P_DONTCARE) +#define P_NAND_D2 (P_DONTCARE) +#define P_NAND_D3 (P_DONTCARE) +#define P_NAND_D4 (P_DONTCARE) +#define P_NAND_D5 (P_DONTCARE) +#define P_NAND_D6 (P_DONTCARE) +#define P_NAND_D7 (P_DONTCARE) +#define P_NAND_WE (P_DONTCARE) +#define P_NAND_RE (P_DONTCARE) +#define P_NAND_CLE (P_DONTCARE) +#define P_NAND_ALE (P_DONTCARE) + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf561/anomaly.h b/arch/blackfin/include/asm/mach-bf561/anomaly.h index e4aa20c..4c108c9 100644 --- a/arch/blackfin/include/asm/mach-bf561/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf561/anomaly.h @@ -1,9 +1,13 @@ /* - * File: include/asm-blackfin/mach-bf561/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. + * Copyright 2004-2010 Analog Devices Inc. + * Licensed under the ADI BSD license. + * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: @@ -18,19 +22,19 @@ # error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 #endif -/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) -/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ +/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) -/* Testset instructions restricted to 32-bit aligned memory locations */ +/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */ #define ANOMALY_05000120 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Erroneous exception when enabling cache */ +/* Erroneous Exception when Enabling Cache */ #define ANOMALY_05000125 (__SILICON_REVISION__ < 3) -/* Signbits instruction not functional under certain conditions */ +/* SIGNBITS Instruction Not Functional under Certain Conditions */ #define ANOMALY_05000127 (1) /* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ #define ANOMALY_05000134 (__SILICON_REVISION__ < 3) @@ -40,7 +44,7 @@ #define ANOMALY_05000136 (__SILICON_REVISION__ < 3) /* Allowing the SPORT RX FIFO to fill will cause an overflow */ #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ +/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) @@ -52,7 +56,7 @@ #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) -/* IMDMA S1/D1 channel may stall */ +/* IMDMA S1/D1 Channel May Stall */ #define ANOMALY_05000149 (1) /* DMA engine may lose data due to incorrect handshaking */ #define ANOMALY_05000150 (__SILICON_REVISION__ < 3) @@ -66,7 +70,7 @@ #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) /* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ #define ANOMALY_05000156 (__SILICON_REVISION__ < 4) -/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ #define ANOMALY_05000159 (__SILICON_REVISION__ < 3) @@ -76,17 +80,17 @@ #define ANOMALY_05000161 (__SILICON_REVISION__ < 3) /* DMEM_CONTROL<12> is not set on Reset */ #define ANOMALY_05000162 (__SILICON_REVISION__ < 3) -/* SPORT transmit data is not gated by external frame sync in certain conditions */ +/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) -/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ +/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ #define ANOMALY_05000167 (1) -/* SDRAM auto-refresh and subsequent Power Ups */ +/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ #define ANOMALY_05000168 (__SILICON_REVISION__ < 5) -/* DATA CPLB page miss can result in lost write-through cache data writes */ +/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ #define ANOMALY_05000169 (__SILICON_REVISION__ < 5) -/* Boot-ROM code modifies SICA_IWRx wakeup registers */ +/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */ #define ANOMALY_05000171 (__SILICON_REVISION__ < 5) /* DSPID register values incorrect */ #define ANOMALY_05000172 (__SILICON_REVISION__ < 3) @@ -96,29 +100,29 @@ #define ANOMALY_05000174 (__SILICON_REVISION__ < 5) /* Overlapping Sequencer and Memory Stalls */ #define ANOMALY_05000175 (__SILICON_REVISION__ < 5) -/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ +/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ #define ANOMALY_05000176 (__SILICON_REVISION__ < 5) /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ #define ANOMALY_05000179 (__SILICON_REVISION__ < 5) /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ #define ANOMALY_05000180 (1) -/* Disabling the PPI resets the PPI configuration registers */ +/* Disabling the PPI Resets the PPI Configuration Registers */ #define ANOMALY_05000181 (__SILICON_REVISION__ < 5) -/* IMDMA does not operate to full speed for 600MHz and higher devices */ +/* Internal Memory DMA Does Not Operate at Full Speed */ #define ANOMALY_05000182 (1) -/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */ +/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ #define ANOMALY_05000184 (__SILICON_REVISION__ < 5) -/* PPI TX Mode with 2 External Frame Syncs */ +/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ #define ANOMALY_05000185 (__SILICON_REVISION__ < 5) -/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */ +/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */ #define ANOMALY_05000186 (__SILICON_REVISION__ < 5) /* IMDMA Corrupted Data after a Halt */ #define ANOMALY_05000187 (1) /* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */ #define ANOMALY_05000188 (__SILICON_REVISION__ < 5) -/* False Protection Exceptions */ +/* False Protection Exceptions when Speculative Fetch Is Cancelled */ #define ANOMALY_05000189 (__SILICON_REVISION__ < 5) -/* PPI not functional at core voltage < 1Volt */ +/* PPI Not Functional at Core Voltage < 1Volt */ #define ANOMALY_05000190 (1) /* PPI does not invert the Driving PPICLK edge in Transmit Modes */ #define ANOMALY_05000191 (__SILICON_REVISION__ < 3) @@ -126,7 +130,7 @@ #define ANOMALY_05000193 (__SILICON_REVISION__ < 5) /* Restarting SPORT in Specific Modes May Cause Data Corruption */ #define ANOMALY_05000194 (__SILICON_REVISION__ < 5) -/* Failing MMR Accesses When Stalled by Preceding Memory Read */ +/* Failing MMR Accesses when Preceding Memory Read Stalls */ #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) /* Current DMA Address Shows Wrong Value During Carry Fix */ #define ANOMALY_05000199 (__SILICON_REVISION__ < 5) @@ -134,9 +138,9 @@ #define ANOMALY_05000200 (__SILICON_REVISION__ < 5) /* Possible Infinite Stall with Specific Dual-DAG Situation */ #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) -/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ +/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ #define ANOMALY_05000204 (__SILICON_REVISION__ < 5) -/* Specific sequence that can cause DMA error or DMA stopping */ +/* Specific Sequence that Can Cause DMA Error or DMA Stopping */ #define ANOMALY_05000205 (__SILICON_REVISION__ < 5) /* Recovery from "Brown-Out" Condition */ #define ANOMALY_05000207 (__SILICON_REVISION__ < 5) @@ -148,8 +152,8 @@ #define ANOMALY_05000215 (__SILICON_REVISION__ < 5) /* NMI Event at Boot Time Results in Unpredictable State */ #define ANOMALY_05000219 (__SILICON_REVISION__ < 5) -/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */ -#define ANOMALY_05000220 (__SILICON_REVISION__ < 5) +/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */ +#define ANOMALY_05000220 (__SILICON_REVISION__ < 4) /* Incorrect Pulse-Width of UART Start Bit */ #define ANOMALY_05000225 (__SILICON_REVISION__ < 5) /* Scratchpad Memory Bank Reads May Return Incorrect Data */ @@ -158,7 +162,7 @@ #define ANOMALY_05000230 (__SILICON_REVISION__ < 5) /* UART STB Bit Incorrectly Affects Receiver Setting */ #define ANOMALY_05000231 (__SILICON_REVISION__ < 5) -/* SPORT data transmit lines are incorrectly driven in multichannel mode */ +/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */ #define ANOMALY_05000232 (__SILICON_REVISION__ < 5) /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ #define ANOMALY_05000242 (__SILICON_REVISION__ < 5) @@ -166,7 +170,7 @@ #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (__SILICON_REVISION__ < 5) -/* TESTSET operation forces stall on the other core */ +/* TESTSET Operation Forces Stall on the Other Core */ #define ANOMALY_05000248 (__SILICON_REVISION__ < 5) /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5) @@ -192,9 +196,9 @@ #define ANOMALY_05000264 (__SILICON_REVISION__ < 5) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (__SILICON_REVISION__ < 5) -/* IMDMA destination IRQ status must be read prior to using IMDMA */ +/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */ #define ANOMALY_05000266 (__SILICON_REVISION__ > 3) -/* IMDMA may corrupt data under certain conditions */ +/* IMDMA May Corrupt Data under Certain Conditions */ #define ANOMALY_05000267 (1) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ #define ANOMALY_05000269 (1) @@ -202,7 +206,7 @@ #define ANOMALY_05000270 (1) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) -/* Data cache write back to external synchronous memory may be lost */ +/* Data Cache Write Back to External Synchronous Memory May Be Lost */ #define ANOMALY_05000274 (1) /* PPI Timing and Sampling Information Updates */ #define ANOMALY_05000275 (__SILICON_REVISION__ > 2) @@ -212,17 +216,21 @@ #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 5) -/* False Hardware Error Exception When ISR Context Is Not Restored */ -#define ANOMALY_05000281 (__SILICON_REVISION__ < 5) -/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ +/* False Hardware Error Exception when ISR Context Is Not Restored */ +/* Temporarily walk around for bug 5423 till this issue is confirmed by + * official anomaly document. It looks 05000281 still exists on bf561 + * v0.5. + */ +#define ANOMALY_05000281 (__SILICON_REVISION__ <= 5) +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (1) -/* A read will receive incorrect data under certain conditions */ +/* Reads Will Receive Incorrect Data under Certain Conditions */ #define ANOMALY_05000287 (__SILICON_REVISION__ < 5) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 5) /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ #define ANOMALY_05000301 (1) -/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ +/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ #define ANOMALY_05000302 (1) /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) @@ -230,25 +238,25 @@ #define ANOMALY_05000307 (__SILICON_REVISION__ < 5) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (1) /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (1) -/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (1) -/* PF2 Output Remains Asserted After SPI Master Boot */ +/* PF2 Output Remains Asserted after SPI Master Boot */ #define ANOMALY_05000320 (__SILICON_REVISION__ > 3) -/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */ +/* Erroneous GPIO Flag Pin Operations under Specific Sequences */ #define ANOMALY_05000323 (1) -/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */ +/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */ #define ANOMALY_05000326 (__SILICON_REVISION__ > 3) -/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */ +/* 24-Bit SPI Boot Mode Is Not Functional */ #define ANOMALY_05000331 (__SILICON_REVISION__ < 5) -/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */ +/* Slave SPI Boot Mode Is Not Functional */ #define ANOMALY_05000332 (__SILICON_REVISION__ < 5) -/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */ +/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */ #define ANOMALY_05000333 (__SILICON_REVISION__ < 5) -/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */ +/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */ #define ANOMALY_05000339 (__SILICON_REVISION__ < 5) /* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */ #define ANOMALY_05000343 (__SILICON_REVISION__ < 5) @@ -262,6 +270,8 @@ #define ANOMALY_05000366 (1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (1) +/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ +#define ANOMALY_05000402 (__SILICON_REVISION__ == 4) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ #define ANOMALY_05000403 (1) /* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ @@ -276,19 +286,43 @@ #define ANOMALY_05000428 (__SILICON_REVISION__ > 3) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_05000461 (1) +/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +#define ANOMALY_05000473 (1) +/* Possible Lockup Condition whem Modifying PLL from External Memory */ +#define ANOMALY_05000475 (__SILICON_REVISION__ < 4) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) +/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ +#define ANOMALY_05000481 (1) +/* IFLUSH sucks at life */ +#define ANOMALY_05000491 (1) /* Anomalies that don't exist on this proc */ +#define ANOMALY_05000119 (0) #define ANOMALY_05000158 (0) #define ANOMALY_05000183 (0) +#define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) #define ANOMALY_05000273 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000353 (1) +#define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) #define ANOMALY_05000386 (1) +#define ANOMALY_05000389 (0) +#define ANOMALY_05000400 (0) #define ANOMALY_05000430 (0) #define ANOMALY_05000432 (0) #define ANOMALY_05000435 (0) #define ANOMALY_05000447 (0) #define ANOMALY_05000448 (0) +#define ANOMALY_05000456 (0) +#define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) +#define ANOMALY_05000474 (0) +#define ANOMALY_05000485 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf561/def_local.h b/arch/blackfin/include/asm/mach-bf561/def_local.h index 597dcec..08e37e5 100644 --- a/arch/blackfin/include/asm/mach-bf561/def_local.h +++ b/arch/blackfin/include/asm/mach-bf561/def_local.h @@ -9,4 +9,8 @@ #define bfin_write_WDOG_CTL(val) bfin_write_WDOGA_CTL(val) #define bfin_write_WDOG_STAT(val) bfin_write_WDOGA_STAT(val) +#include "gpio.h" +#include "portmux.h" #include "ports.h" + +#define BF561_FAMILY 1 /* Linux glue */ diff --git a/arch/blackfin/include/asm/mach-bf561/gpio.h b/arch/blackfin/include/asm/mach-bf561/gpio.h new file mode 100644 index 0000000..4f8aa5d --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf561/gpio.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2008 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + + +#ifndef _MACH_GPIO_H_ +#define _MACH_GPIO_H_ + +#define MAX_BLACKFIN_GPIOS 48 + +#define GPIO_PF0 0 +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 +#define GPIO_PF16 16 +#define GPIO_PF17 17 +#define GPIO_PF18 18 +#define GPIO_PF19 19 +#define GPIO_PF20 20 +#define GPIO_PF21 21 +#define GPIO_PF22 22 +#define GPIO_PF23 23 +#define GPIO_PF24 24 +#define GPIO_PF25 25 +#define GPIO_PF26 26 +#define GPIO_PF27 27 +#define GPIO_PF28 28 +#define GPIO_PF29 29 +#define GPIO_PF30 30 +#define GPIO_PF31 31 +#define GPIO_PF32 32 +#define GPIO_PF33 33 +#define GPIO_PF34 34 +#define GPIO_PF35 35 +#define GPIO_PF36 36 +#define GPIO_PF37 37 +#define GPIO_PF38 38 +#define GPIO_PF39 39 +#define GPIO_PF40 40 +#define GPIO_PF41 41 +#define GPIO_PF42 42 +#define GPIO_PF43 43 +#define GPIO_PF44 44 +#define GPIO_PF45 45 +#define GPIO_PF46 46 +#define GPIO_PF47 47 + +#define PORT_FIO0 GPIO_0 +#define PORT_FIO1 GPIO_16 +#define PORT_FIO2 GPIO_32 + +#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf561/portmux.h b/arch/blackfin/include/asm/mach-bf561/portmux.h new file mode 100644 index 0000000..2339ffd --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf561/portmux.h @@ -0,0 +1,97 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + +#define P_PPI0_CLK (P_DONTCARE) +#define P_PPI0_FS1 (P_DONTCARE) +#define P_PPI0_FS2 (P_DONTCARE) +#define P_PPI0_FS3 (P_DONTCARE) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40)) +#define P_PPI0_D0 (P_DONTCARE) +#define P_PPI0_D1 (P_DONTCARE) +#define P_PPI0_D2 (P_DONTCARE) +#define P_PPI0_D3 (P_DONTCARE) +#define P_PPI0_D4 (P_DONTCARE) +#define P_PPI0_D5 (P_DONTCARE) +#define P_PPI0_D6 (P_DONTCARE) +#define P_PPI0_D7 (P_DONTCARE) +#define P_PPI1_CLK (P_DONTCARE) +#define P_PPI1_FS1 (P_DONTCARE) +#define P_PPI1_FS2 (P_DONTCARE) +#define P_PPI1_FS3 (P_DONTCARE) +#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39)) +#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38)) +#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37)) +#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36)) +#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35)) +#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34)) +#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33)) +#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32)) +#define P_PPI1_D0 (P_DONTCARE) +#define P_PPI1_D1 (P_DONTCARE) +#define P_PPI1_D2 (P_DONTCARE) +#define P_PPI1_D3 (P_DONTCARE) +#define P_PPI1_D4 (P_DONTCARE) +#define P_PPI1_D5 (P_DONTCARE) +#define P_PPI1_D6 (P_DONTCARE) +#define P_PPI1_D7 (P_DONTCARE) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27)) +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21)) +#define P_SPORT1_DRPRI (P_DONTCARE) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17)) +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16)) +#define P_SPORT0_DRPRI (P_DONTCARE) +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15)) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) +#define P_TMR11 (P_DONTCARE) +#define P_TMR10 (P_DONTCARE) +#define P_TMR9 (P_DONTCARE) +#define P_TMR8 (P_DONTCARE) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0)) +#define P_SPI0_MOSI (P_DONTCARE) +#define P_SPI0_MISO (P_DONTCARE) +#define P_SPI0_SCK (P_DONTCARE) +#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2 +#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2 + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h new file mode 100644 index 0000000..b17207f --- /dev/null +++ b/arch/blackfin/include/asm/portmux.h @@ -0,0 +1,1194 @@ +/* + * Common header file for Blackfin family of processors + * + * Copyright 2007-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _PORTMUX_H_ +#define _PORTMUX_H_ + +#define P_IDENT(x) ((x) & 0x1FF) +#define P_FUNCT(x) (((x) & 0x3) << 9) +#define P_FUNCT2MUX(x) (((x) >> 9) & 0x3) +#define P_DEFINED 0x8000 +#define P_UNDEF 0x4000 +#define P_MAYSHARE 0x2000 +#define P_DONTCARE 0x1000 + +#ifndef CONFIG_BFIN_GPIO_TRACK +#define peripheral_request(per, label) peripheral_request(per) +#define peripheral_request_list(per, label) peripheral_request_list(per) +#endif + +int peripheral_request(unsigned short per, const char *label); +void peripheral_free(unsigned short per); +int peripheral_request_list(const unsigned short per[], const char *label); +void peripheral_free_list(const unsigned short per[]); + +#include <asm/blackfin.h> + +#ifndef P_SPORT2_TFS +#define P_SPORT2_TFS P_UNDEF +#endif + +#ifndef P_SPORT2_DTSEC +#define P_SPORT2_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT2_DTPRI +#define P_SPORT2_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT2_TSCLK +#define P_SPORT2_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT2_RFS +#define P_SPORT2_RFS P_UNDEF +#endif + +#ifndef P_SPORT2_DRSEC +#define P_SPORT2_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT2_DRPRI +#define P_SPORT2_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT2_RSCLK +#define P_SPORT2_RSCLK P_UNDEF +#endif + +#ifndef P_SPORT3_TFS +#define P_SPORT3_TFS P_UNDEF +#endif + +#ifndef P_SPORT3_DTSEC +#define P_SPORT3_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT3_DTPRI +#define P_SPORT3_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT3_TSCLK +#define P_SPORT3_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT3_RFS +#define P_SPORT3_RFS P_UNDEF +#endif + +#ifndef P_SPORT3_DRSEC +#define P_SPORT3_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT3_DRPRI +#define P_SPORT3_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT3_RSCLK +#define P_SPORT3_RSCLK P_UNDEF +#endif + +#ifndef P_TMR4 +#define P_TMR4 P_UNDEF +#endif + +#ifndef P_TMR5 +#define P_TMR5 P_UNDEF +#endif + +#ifndef P_TMR6 +#define P_TMR6 P_UNDEF +#endif + +#ifndef P_TMR7 +#define P_TMR7 P_UNDEF +#endif + +#ifndef P_TWI1_SCL +#define P_TWI1_SCL P_UNDEF +#endif + +#ifndef P_TWI1_SDA +#define P_TWI1_SDA P_UNDEF +#endif + +#ifndef P_UART3_RTS +#define P_UART3_RTS P_UNDEF +#endif + +#ifndef P_UART3_CTS +#define P_UART3_CTS P_UNDEF +#endif + +#ifndef P_UART2_TX +#define P_UART2_TX P_UNDEF +#endif + +#ifndef P_UART2_RX +#define P_UART2_RX P_UNDEF +#endif + +#ifndef P_UART3_TX +#define P_UART3_TX P_UNDEF +#endif + +#ifndef P_UART3_RX +#define P_UART3_RX P_UNDEF +#endif + +#ifndef P_SPI2_SS +#define P_SPI2_SS P_UNDEF +#endif + +#ifndef P_SPI2_SSEL1 +#define P_SPI2_SSEL1 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL2 +#define P_SPI2_SSEL2 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL3 +#define P_SPI2_SSEL3 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL4 +#define P_SPI2_SSEL4 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL5 +#define P_SPI2_SSEL5 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL6 +#define P_SPI2_SSEL6 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL7 +#define P_SPI2_SSEL7 P_UNDEF +#endif + +#ifndef P_SPI2_SCK +#define P_SPI2_SCK P_UNDEF +#endif + +#ifndef P_SPI2_MOSI +#define P_SPI2_MOSI P_UNDEF +#endif + +#ifndef P_SPI2_MISO +#define P_SPI2_MISO P_UNDEF +#endif + +#ifndef P_TMR0 +#define P_TMR0 P_UNDEF +#endif + +#ifndef P_TMR1 +#define P_TMR1 P_UNDEF +#endif + +#ifndef P_TMR2 +#define P_TMR2 P_UNDEF +#endif + +#ifndef P_TMR3 +#define P_TMR3 P_UNDEF +#endif + +#ifndef P_SPORT0_TFS +#define P_SPORT0_TFS P_UNDEF +#endif + +#ifndef P_SPORT0_DTSEC +#define P_SPORT0_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT0_DTPRI +#define P_SPORT0_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT0_TSCLK +#define P_SPORT0_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT0_RFS +#define P_SPORT0_RFS P_UNDEF +#endif + +#ifndef P_SPORT0_DRSEC +#define P_SPORT0_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT0_DRPRI +#define P_SPORT0_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT0_RSCLK +#define P_SPORT0_RSCLK P_UNDEF +#endif + +#ifndef P_SD_D0 +#define P_SD_D0 P_UNDEF +#endif + +#ifndef P_SD_D1 +#define P_SD_D1 P_UNDEF +#endif + +#ifndef P_SD_D2 +#define P_SD_D2 P_UNDEF +#endif + +#ifndef P_SD_D3 +#define P_SD_D3 P_UNDEF +#endif + +#ifndef P_SD_CLK +#define P_SD_CLK P_UNDEF +#endif + +#ifndef P_SD_CMD +#define P_SD_CMD P_UNDEF +#endif + +#ifndef P_MMCLK +#define P_MMCLK P_UNDEF +#endif + +#ifndef P_MBCLK +#define P_MBCLK P_UNDEF +#endif + +#ifndef P_PPI1_D0 +#define P_PPI1_D0 P_UNDEF +#endif + +#ifndef P_PPI1_D1 +#define P_PPI1_D1 P_UNDEF +#endif + +#ifndef P_PPI1_D2 +#define P_PPI1_D2 P_UNDEF +#endif + +#ifndef P_PPI1_D3 +#define P_PPI1_D3 P_UNDEF +#endif + +#ifndef P_PPI1_D4 +#define P_PPI1_D4 P_UNDEF +#endif + +#ifndef P_PPI1_D5 +#define P_PPI1_D5 P_UNDEF +#endif + +#ifndef P_PPI1_D6 +#define P_PPI1_D6 P_UNDEF +#endif + +#ifndef P_PPI1_D7 +#define P_PPI1_D7 P_UNDEF +#endif + +#ifndef P_PPI1_D8 +#define P_PPI1_D8 P_UNDEF +#endif + +#ifndef P_PPI1_D9 +#define P_PPI1_D9 P_UNDEF +#endif + +#ifndef P_PPI1_D10 +#define P_PPI1_D10 P_UNDEF +#endif + +#ifndef P_PPI1_D11 +#define P_PPI1_D11 P_UNDEF +#endif + +#ifndef P_PPI1_D12 +#define P_PPI1_D12 P_UNDEF +#endif + +#ifndef P_PPI1_D13 +#define P_PPI1_D13 P_UNDEF +#endif + +#ifndef P_PPI1_D14 +#define P_PPI1_D14 P_UNDEF +#endif + +#ifndef P_PPI1_D15 +#define P_PPI1_D15 P_UNDEF +#endif + +#ifndef P_HOST_D8 +#define P_HOST_D8 P_UNDEF +#endif + +#ifndef P_HOST_D9 +#define P_HOST_D9 P_UNDEF +#endif + +#ifndef P_HOST_D10 +#define P_HOST_D10 P_UNDEF +#endif + +#ifndef P_HOST_D11 +#define P_HOST_D11 P_UNDEF +#endif + +#ifndef P_HOST_D12 +#define P_HOST_D12 P_UNDEF +#endif + +#ifndef P_HOST_D13 +#define P_HOST_D13 P_UNDEF +#endif + +#ifndef P_HOST_D14 +#define P_HOST_D14 P_UNDEF +#endif + +#ifndef P_HOST_D15 +#define P_HOST_D15 P_UNDEF +#endif + +#ifndef P_HOST_D0 +#define P_HOST_D0 P_UNDEF +#endif + +#ifndef P_HOST_D1 +#define P_HOST_D1 P_UNDEF +#endif + +#ifndef P_HOST_D2 +#define P_HOST_D2 P_UNDEF +#endif + +#ifndef P_HOST_D3 +#define P_HOST_D3 P_UNDEF +#endif + +#ifndef P_HOST_D4 +#define P_HOST_D4 P_UNDEF +#endif + +#ifndef P_HOST_D5 +#define P_HOST_D5 P_UNDEF +#endif + +#ifndef P_HOST_D6 +#define P_HOST_D6 P_UNDEF +#endif + +#ifndef P_HOST_D7 +#define P_HOST_D7 P_UNDEF +#endif + +#ifndef P_SPORT1_TFS +#define P_SPORT1_TFS P_UNDEF +#endif + +#ifndef P_SPORT1_DTSEC +#define P_SPORT1_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT1_DTPRI +#define P_SPORT1_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT1_TSCLK +#define P_SPORT1_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT1_RFS +#define P_SPORT1_RFS P_UNDEF +#endif + +#ifndef P_SPORT1_DRSEC +#define P_SPORT1_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT1_DRPRI +#define P_SPORT1_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT1_RSCLK +#define P_SPORT1_RSCLK P_UNDEF +#endif + +#ifndef P_PPI2_D0 +#define P_PPI2_D0 P_UNDEF +#endif + +#ifndef P_PPI2_D1 +#define P_PPI2_D1 P_UNDEF +#endif + +#ifndef P_PPI2_D2 +#define P_PPI2_D2 P_UNDEF +#endif + +#ifndef P_PPI2_D3 +#define P_PPI2_D3 P_UNDEF +#endif + +#ifndef P_PPI2_D4 +#define P_PPI2_D4 P_UNDEF +#endif + +#ifndef P_PPI2_D5 +#define P_PPI2_D5 P_UNDEF +#endif + +#ifndef P_PPI2_D6 +#define P_PPI2_D6 P_UNDEF +#endif + +#ifndef P_PPI2_D7 +#define P_PPI2_D7 P_UNDEF +#endif + +#ifndef P_PPI0_D18 +#define P_PPI0_D18 P_UNDEF +#endif + +#ifndef P_PPI0_D19 +#define P_PPI0_D19 P_UNDEF +#endif + +#ifndef P_PPI0_D20 +#define P_PPI0_D20 P_UNDEF +#endif + +#ifndef P_PPI0_D21 +#define P_PPI0_D21 P_UNDEF +#endif + +#ifndef P_PPI0_D22 +#define P_PPI0_D22 P_UNDEF +#endif + +#ifndef P_PPI0_D23 +#define P_PPI0_D23 P_UNDEF +#endif + +#ifndef P_KEY_ROW0 +#define P_KEY_ROW0 P_UNDEF +#endif + +#ifndef P_KEY_ROW1 +#define P_KEY_ROW1 P_UNDEF +#endif + +#ifndef P_KEY_ROW2 +#define P_KEY_ROW2 P_UNDEF +#endif + +#ifndef P_KEY_ROW3 +#define P_KEY_ROW3 P_UNDEF +#endif + +#ifndef P_KEY_COL0 +#define P_KEY_COL0 P_UNDEF +#endif + +#ifndef P_KEY_COL1 +#define P_KEY_COL1 P_UNDEF +#endif + +#ifndef P_KEY_COL2 +#define P_KEY_COL2 P_UNDEF +#endif + +#ifndef P_KEY_COL3 +#define P_KEY_COL3 P_UNDEF +#endif + +#ifndef P_SPI0_SCK +#define P_SPI0_SCK P_UNDEF +#endif + +#ifndef P_SPI0_MISO +#define P_SPI0_MISO P_UNDEF +#endif + +#ifndef P_SPI0_MOSI +#define P_SPI0_MOSI P_UNDEF +#endif + +#ifndef P_SPI0_SS +#define P_SPI0_SS P_UNDEF +#endif + +#ifndef P_SPI0_SSEL1 +#define P_SPI0_SSEL1 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL2 +#define P_SPI0_SSEL2 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL3 +#define P_SPI0_SSEL3 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL4 +#define P_SPI0_SSEL4 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL5 +#define P_SPI0_SSEL5 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL6 +#define P_SPI0_SSEL6 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL7 +#define P_SPI0_SSEL7 P_UNDEF +#endif + +#ifndef P_UART0_TX +#define P_UART0_TX P_UNDEF +#endif + +#ifndef P_UART0_RX +#define P_UART0_RX P_UNDEF +#endif + +#ifndef P_UART1_RTS +#define P_UART1_RTS P_UNDEF +#endif + +#ifndef P_UART1_CTS +#define P_UART1_CTS P_UNDEF +#endif + +#ifndef P_PPI1_CLK +#define P_PPI1_CLK P_UNDEF +#endif + +#ifndef P_PPI1_FS1 +#define P_PPI1_FS1 P_UNDEF +#endif + +#ifndef P_PPI1_FS2 +#define P_PPI1_FS2 P_UNDEF +#endif + +#ifndef P_TWI0_SCL +#define P_TWI0_SCL P_UNDEF +#endif + +#ifndef P_TWI0_SDA +#define P_TWI0_SDA P_UNDEF +#endif + +#ifndef P_KEY_COL7 +#define P_KEY_COL7 P_UNDEF +#endif + +#ifndef P_KEY_ROW6 +#define P_KEY_ROW6 P_UNDEF +#endif + +#ifndef P_KEY_COL6 +#define P_KEY_COL6 P_UNDEF +#endif + +#ifndef P_KEY_ROW5 +#define P_KEY_ROW5 P_UNDEF +#endif + +#ifndef P_KEY_COL5 +#define P_KEY_COL5 P_UNDEF +#endif + +#ifndef P_KEY_ROW4 +#define P_KEY_ROW4 P_UNDEF +#endif + +#ifndef P_KEY_COL4 +#define P_KEY_COL4 P_UNDEF +#endif + +#ifndef P_KEY_ROW7 +#define P_KEY_ROW7 P_UNDEF +#endif + +#ifndef P_PPI0_D0 +#define P_PPI0_D0 P_UNDEF +#endif + +#ifndef P_PPI0_D1 +#define P_PPI0_D1 P_UNDEF +#endif + +#ifndef P_PPI0_D2 +#define P_PPI0_D2 P_UNDEF +#endif + +#ifndef P_PPI0_D3 +#define P_PPI0_D3 P_UNDEF +#endif + +#ifndef P_PPI0_D4 +#define P_PPI0_D4 P_UNDEF +#endif + +#ifndef P_PPI0_D5 +#define P_PPI0_D5 P_UNDEF +#endif + +#ifndef P_PPI0_D6 +#define P_PPI0_D6 P_UNDEF +#endif + +#ifndef P_PPI0_D7 +#define P_PPI0_D7 P_UNDEF +#endif + +#ifndef P_PPI0_D8 +#define P_PPI0_D8 P_UNDEF +#endif + +#ifndef P_PPI0_D9 +#define P_PPI0_D9 P_UNDEF +#endif + +#ifndef P_PPI0_D10 +#define P_PPI0_D10 P_UNDEF +#endif + +#ifndef P_PPI0_D11 +#define P_PPI0_D11 P_UNDEF +#endif + +#ifndef P_PPI0_D12 +#define P_PPI0_D12 P_UNDEF +#endif + +#ifndef P_PPI0_D13 +#define P_PPI0_D13 P_UNDEF +#endif + +#ifndef P_PPI0_D14 +#define P_PPI0_D14 P_UNDEF +#endif + +#ifndef P_PPI0_D15 +#define P_PPI0_D15 P_UNDEF +#endif + +#ifndef P_ATAPI_D0A +#define P_ATAPI_D0A P_UNDEF +#endif + +#ifndef P_ATAPI_D1A +#define P_ATAPI_D1A P_UNDEF +#endif + +#ifndef P_ATAPI_D2A +#define P_ATAPI_D2A P_UNDEF +#endif + +#ifndef P_ATAPI_D3A +#define P_ATAPI_D3A P_UNDEF +#endif + +#ifndef P_ATAPI_D4A +#define P_ATAPI_D4A P_UNDEF +#endif + +#ifndef P_ATAPI_D5A +#define P_ATAPI_D5A P_UNDEF +#endif + +#ifndef P_ATAPI_D6A +#define P_ATAPI_D6A P_UNDEF +#endif + +#ifndef P_ATAPI_D7A +#define P_ATAPI_D7A P_UNDEF +#endif + +#ifndef P_ATAPI_D8A +#define P_ATAPI_D8A P_UNDEF +#endif + +#ifndef P_ATAPI_D9A +#define P_ATAPI_D9A P_UNDEF +#endif + +#ifndef P_ATAPI_D10A +#define P_ATAPI_D10A P_UNDEF +#endif + +#ifndef P_ATAPI_D11A +#define P_ATAPI_D11A P_UNDEF +#endif + +#ifndef P_ATAPI_D12A +#define P_ATAPI_D12A P_UNDEF +#endif + +#ifndef P_ATAPI_D13A +#define P_ATAPI_D13A P_UNDEF +#endif + +#ifndef P_ATAPI_D14A +#define P_ATAPI_D14A P_UNDEF +#endif + +#ifndef P_ATAPI_D15A +#define P_ATAPI_D15A P_UNDEF +#endif + +#ifndef P_PPI0_CLK +#define P_PPI0_CLK P_UNDEF +#endif + +#ifndef P_PPI0_FS1 +#define P_PPI0_FS1 P_UNDEF +#endif + +#ifndef P_PPI0_FS2 +#define P_PPI0_FS2 P_UNDEF +#endif + +#ifndef P_PPI0_D16 +#define P_PPI0_D16 P_UNDEF +#endif + +#ifndef P_PPI0_D17 +#define P_PPI0_D17 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL1 +#define P_SPI1_SSEL1 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL2 +#define P_SPI1_SSEL2 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL3 +#define P_SPI1_SSEL3 P_UNDEF +#endif + + +#ifndef P_SPI1_SSEL4 +#define P_SPI1_SSEL4 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL5 +#define P_SPI1_SSEL5 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL6 +#define P_SPI1_SSEL6 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL7 +#define P_SPI1_SSEL7 P_UNDEF +#endif + +#ifndef P_SPI1_SCK +#define P_SPI1_SCK P_UNDEF +#endif + +#ifndef P_SPI1_MISO +#define P_SPI1_MISO P_UNDEF +#endif + +#ifndef P_SPI1_MOSI +#define P_SPI1_MOSI P_UNDEF +#endif + +#ifndef P_SPI1_SS +#define P_SPI1_SS P_UNDEF +#endif + +#ifndef P_CAN0_TX +#define P_CAN0_TX P_UNDEF +#endif + +#ifndef P_CAN0_RX +#define P_CAN0_RX P_UNDEF +#endif + +#ifndef P_CAN1_TX +#define P_CAN1_TX P_UNDEF +#endif + +#ifndef P_CAN1_RX +#define P_CAN1_RX P_UNDEF +#endif + +#ifndef P_ATAPI_A0A +#define P_ATAPI_A0A P_UNDEF +#endif + +#ifndef P_ATAPI_A1A +#define P_ATAPI_A1A P_UNDEF +#endif + +#ifndef P_ATAPI_A2A +#define P_ATAPI_A2A P_UNDEF +#endif + +#ifndef P_HOST_CE +#define P_HOST_CE P_UNDEF +#endif + +#ifndef P_HOST_RD +#define P_HOST_RD P_UNDEF +#endif + +#ifndef P_HOST_WR +#define P_HOST_WR P_UNDEF +#endif + +#ifndef P_MTXONB +#define P_MTXONB P_UNDEF +#endif + +#ifndef P_PPI2_FS2 +#define P_PPI2_FS2 P_UNDEF +#endif + +#ifndef P_PPI2_FS1 +#define P_PPI2_FS1 P_UNDEF +#endif + +#ifndef P_PPI2_CLK +#define P_PPI2_CLK P_UNDEF +#endif + +#ifndef P_CNT_CZM +#define P_CNT_CZM P_UNDEF +#endif + +#ifndef P_UART1_TX +#define P_UART1_TX P_UNDEF +#endif + +#ifndef P_UART1_RX +#define P_UART1_RX P_UNDEF +#endif + +#ifndef P_ATAPI_RESET +#define P_ATAPI_RESET P_UNDEF +#endif + +#ifndef P_HOST_ADDR +#define P_HOST_ADDR P_UNDEF +#endif + +#ifndef P_HOST_ACK +#define P_HOST_ACK P_UNDEF +#endif + +#ifndef P_MTX +#define P_MTX P_UNDEF +#endif + +#ifndef P_MRX +#define P_MRX P_UNDEF +#endif + +#ifndef P_MRXONB +#define P_MRXONB P_UNDEF +#endif + +#ifndef P_A4 +#define P_A4 P_UNDEF +#endif + +#ifndef P_A5 +#define P_A5 P_UNDEF +#endif + +#ifndef P_A6 +#define P_A6 P_UNDEF +#endif + +#ifndef P_A7 +#define P_A7 P_UNDEF +#endif + +#ifndef P_A8 +#define P_A8 P_UNDEF +#endif + +#ifndef P_A9 +#define P_A9 P_UNDEF +#endif + +#ifndef P_PPI1_FS3 +#define P_PPI1_FS3 P_UNDEF +#endif + +#ifndef P_PPI2_FS3 +#define P_PPI2_FS3 P_UNDEF +#endif + +#ifndef P_TMR8 +#define P_TMR8 P_UNDEF +#endif + +#ifndef P_TMR9 +#define P_TMR9 P_UNDEF +#endif + +#ifndef P_TMR10 +#define P_TMR10 P_UNDEF +#endif +#ifndef P_TMR11 +#define P_TMR11 P_UNDEF +#endif + +#ifndef P_DMAR0 +#define P_DMAR0 P_UNDEF +#endif + +#ifndef P_DMAR1 +#define P_DMAR1 P_UNDEF +#endif + +#ifndef P_PPI0_FS3 +#define P_PPI0_FS3 P_UNDEF +#endif + +#ifndef P_CNT_CDG +#define P_CNT_CDG P_UNDEF +#endif + +#ifndef P_CNT_CUD +#define P_CNT_CUD P_UNDEF +#endif + +#ifndef P_A10 +#define P_A10 P_UNDEF +#endif + +#ifndef P_A11 +#define P_A11 P_UNDEF +#endif + +#ifndef P_A12 +#define P_A12 P_UNDEF +#endif + +#ifndef P_A13 +#define P_A13 P_UNDEF +#endif + +#ifndef P_A14 +#define P_A14 P_UNDEF +#endif + +#ifndef P_A15 +#define P_A15 P_UNDEF +#endif + +#ifndef P_A16 +#define P_A16 P_UNDEF +#endif + +#ifndef P_A17 +#define P_A17 P_UNDEF +#endif + +#ifndef P_A18 +#define P_A18 P_UNDEF +#endif + +#ifndef P_A19 +#define P_A19 P_UNDEF +#endif + +#ifndef P_A20 +#define P_A20 P_UNDEF +#endif + +#ifndef P_A21 +#define P_A21 P_UNDEF +#endif + +#ifndef P_A22 +#define P_A22 P_UNDEF +#endif + +#ifndef P_A23 +#define P_A23 P_UNDEF +#endif + +#ifndef P_A24 +#define P_A24 P_UNDEF +#endif + +#ifndef P_A25 +#define P_A25 P_UNDEF +#endif + +#ifndef P_NOR_CLK +#define P_NOR_CLK P_UNDEF +#endif + +#ifndef P_TMRCLK +#define P_TMRCLK P_UNDEF +#endif + +#ifndef P_AMC_ARDY_NOR_WAIT +#define P_AMC_ARDY_NOR_WAIT P_UNDEF +#endif + +#ifndef P_NAND_CE +#define P_NAND_CE P_UNDEF +#endif + +#ifndef P_NAND_RB +#define P_NAND_RB P_UNDEF +#endif + +#ifndef P_ATAPI_DIOR +#define P_ATAPI_DIOR P_UNDEF +#endif + +#ifndef P_ATAPI_DIOW +#define P_ATAPI_DIOW P_UNDEF +#endif + +#ifndef P_ATAPI_CS0 +#define P_ATAPI_CS0 P_UNDEF +#endif + +#ifndef P_ATAPI_CS1 +#define P_ATAPI_CS1 P_UNDEF +#endif + +#ifndef P_ATAPI_DMACK +#define P_ATAPI_DMACK P_UNDEF +#endif + +#ifndef P_ATAPI_DMARQ +#define P_ATAPI_DMARQ P_UNDEF +#endif + +#ifndef P_ATAPI_INTRQ +#define P_ATAPI_INTRQ P_UNDEF +#endif + +#ifndef P_ATAPI_IORDY +#define P_ATAPI_IORDY P_UNDEF +#endif + +#ifndef P_AMC_BR +#define P_AMC_BR P_UNDEF +#endif + +#ifndef P_AMC_BG +#define P_AMC_BG P_UNDEF +#endif + +#ifndef P_AMC_BGH +#define P_AMC_BGH P_UNDEF +#endif + +/* EMAC */ + +#ifndef P_MII0_ETxD0 +#define P_MII0_ETxD0 P_UNDEF +#endif + +#ifndef P_MII0_ETxD1 +#define P_MII0_ETxD1 P_UNDEF +#endif + +#ifndef P_MII0_ETxD2 +#define P_MII0_ETxD2 P_UNDEF +#endif + +#ifndef P_MII0_ETxD3 +#define P_MII0_ETxD3 P_UNDEF +#endif + +#ifndef P_MII0_ETxEN +#define P_MII0_ETxEN P_UNDEF +#endif + +#ifndef P_MII0_TxCLK +#define P_MII0_TxCLK P_UNDEF +#endif + +#ifndef P_MII0_PHYINT +#define P_MII0_PHYINT P_UNDEF +#endif + +#ifndef P_MII0_COL +#define P_MII0_COL P_UNDEF +#endif + +#ifndef P_MII0_ERxD0 +#define P_MII0_ERxD0 P_UNDEF +#endif + +#ifndef P_MII0_ERxD1 +#define P_MII0_ERxD1 P_UNDEF +#endif + +#ifndef P_MII0_ERxD2 +#define P_MII0_ERxD2 P_UNDEF +#endif + +#ifndef P_MII0_ERxD3 +#define P_MII0_ERxD3 P_UNDEF +#endif + +#ifndef P_MII0_ERxDV +#define P_MII0_ERxDV P_UNDEF +#endif + +#ifndef P_MII0_ERxCLK +#define P_MII0_ERxCLK P_UNDEF +#endif + +#ifndef P_MII0_ERxER +#define P_MII0_ERxER P_UNDEF +#endif + +#ifndef P_MII0_CRS +#define P_MII0_CRS P_UNDEF +#endif + +#ifndef P_RMII0_REF_CLK +#define P_RMII0_REF_CLK P_UNDEF +#endif + +#ifndef P_RMII0_MDINT +#define P_RMII0_MDINT P_UNDEF +#endif + +#ifndef P_RMII0_CRS_DV +#define P_RMII0_CRS_DV P_UNDEF +#endif + +#ifndef P_MDC +#define P_MDC P_UNDEF +#endif + +#ifndef P_MDIO +#define P_MDIO P_UNDEF +#endif + +#endif /* _PORTMUX_H_ */ diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h index 6bc7208..952438e 100644 --- a/arch/blackfin/include/asm/system.h +++ b/arch/blackfin/include/asm/system.h @@ -118,4 +118,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, return tmp; } +void bfin_reset_boot_spi_cs(unsigned short pin); + #endif /* _BLACKFIN_SYSTEM_H */ diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk index 793cc43..aba96b3 100644 --- a/arch/nios2/config.mk +++ b/arch/nios2/config.mk @@ -30,3 +30,6 @@ PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__ PLATFORM_CPPFLAGS += -G0 LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds + +LDFLAGS += --gc-sections +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections diff --git a/arch/nios2/include/asm/gpio.h b/arch/nios2/include/asm/gpio.h index 76c425e..cff1dd9 100644 --- a/arch/nios2/include/asm/gpio.h +++ b/arch/nios2/include/asm/gpio.h @@ -21,6 +21,11 @@ #ifdef CONFIG_SYS_GPIO_BASE #include <asm/io.h> +static inline int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + static inline int gpio_direction_input(unsigned gpio) { writel(1, CONFIG_SYS_GPIO_BASE + (gpio << 2)); @@ -43,6 +48,7 @@ static inline void gpio_set_value(unsigned gpio, int value) writel(value ? 3 : 2, CONFIG_SYS_GPIO_BASE + (gpio << 2)); } #else +extern int gpio_request(unsigned gpio, const char *label); extern int gpio_direction_input(unsigned gpio); extern int gpio_direction_output(unsigned gpio, int value); extern int gpio_get_value(unsigned gpio); diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c index e4093a8..e25a113 100644 --- a/arch/nios2/lib/bootm.c +++ b/arch/nios2/lib/bootm.c @@ -34,6 +34,18 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima char *commandline = getenv("bootargs"); ulong initrd_start = images->rd_start; ulong initrd_end = images->rd_end; + char *of_flat_tree = NULL; +#if defined(CONFIG_OF_LIBFDT) + ulong of_size = 0; + + /* find flattened device tree */ + if (boot_get_fdt(flag, argc, argv, images, &of_flat_tree, &of_size)) + return 1; +#endif + if (!of_flat_tree) + of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16); + if (of_flat_tree) + initrd_end = (ulong)of_flat_tree; if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) return 1; @@ -45,6 +57,15 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima debug("bootargs=%s @ 0x%lx\n", commandline, (ulong)&commandline); debug("initrd=0x%lx-0x%lx\n", (ulong)initrd_start, (ulong)initrd_end); + /* kernel parameters passing + * r4 : NIOS magic + * r5 : initrd start + * r6 : initrd end or fdt + * r7 : kernel command line + * fdt is passed to kernel via r6, the same as initrd_end. fdt will be + * verified with fdt magic. when both initrd and fdt are used at the + * same time, fdt must follow immediately after initrd. + */ kernel(NIOS_MAGIC, initrd_start, initrd_end, commandline); /* does not return */ diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index b664c64..6635109 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -55,6 +55,7 @@ int checkcpu(void) char name[15]; u32 partid; } cpu_type_list [] = { + CPU_TYPE_ENTRY(8308), CPU_TYPE_ENTRY(8311), CPU_TYPE_ENTRY(8313), CPU_TYPE_ENTRY(8314), @@ -125,72 +126,6 @@ int checkcpu(void) return 0; } - -/* - * Program a UPM with the code supplied in the table. - * - * The 'dummy' variable is used to increment the MAD. 'dummy' is - * supposed to be a pointer to the memory of the device being - * programmed by the UPM. The data in the MDR is written into - * memory and the MAD is incremented every time there's a write - * to 'dummy'. Unfortunately, the current prototype for this - * function doesn't allow for passing the address of this - * device, and changing the prototype will break a number lots - * of other code, so we need to use a round-about way of finding - * the value for 'dummy'. - * - * The value can be extracted from the base address bits of the - * Base Register (BR) associated with the specific UPM. To find - * that BR, we need to scan all 8 BRs until we find the one that - * has its MSEL bits matching the UPM we want. Once we know the - * right BR, we can extract the base address bits from it. - * - * The MxMR and the BR and OR of the chosen bank should all be - * configured before calling this function. - * - * Parameters: - * upm: 0=UPMA, 1=UPMB, 2=UPMC - * table: Pointer to an array of values to program - * size: Number of elements in the array. Must be 64 or less. - */ -void upmconfig (uint upm, uint *table, uint size) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbus = &immap->lbus; - volatile uchar *dummy = NULL; - const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */ - volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */ - uint i; - - /* Scan all the banks to determine the base address of the device */ - for (i = 0; i < 8; i++) { - if ((lbus->bank[i].br & BR_MSEL) == msel) { - dummy = (uchar *) (lbus->bank[i].br & BR_BA); - break; - } - } - - if (!dummy) { - printf("Error: %s() could not find matching BR\n", __FUNCTION__); - hang(); - } - - /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */ - *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000; - - for (i = 0; i < size; i++) { - lbus->mdr = table[i]; - __asm__ __volatile__ ("sync"); - *dummy = 0; /* Write the value to memory and increment MAD */ - __asm__ __volatile__ ("sync"); - while(((*mxmr & 0x3f) != ((i + 1) & 0x3f))); - } - - /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */ - *mxmr &= 0xCFFFFFC0; -} - - int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index f3b67ae..83cba93 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -236,8 +236,8 @@ void cpu_init_f (volatile immap_t * im) /* LCRR - Clock Ratio Register (10.3.1.16) * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description */ - clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val); - __raw_readl(&im->lbus.lcrr); + clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val); + __raw_readl(&im->im_lbc.lcrr); isync(); /* Enable Time Base & Decrementer ( so we will have udelay() )*/ @@ -267,80 +267,41 @@ void cpu_init_f (volatile immap_t * im) /* Config QE ioports */ config_qe_ioports(); #endif + /* Set up preliminary BR/OR regs */ + init_early_memctl_regs(); - /* - * Memory Controller: - */ - - /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary - * addresses - these have to be modified later when FLASH size - * has been determined - */ - -#if defined(CONFIG_SYS_BR0_PRELIM) \ - && defined(CONFIG_SYS_OR0_PRELIM) \ - && defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \ - && defined(CONFIG_SYS_LBLAWAR0_PRELIM) - im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM; - im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM; + /* Local Access window setup */ +#if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM) im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM; im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM; #else -#error CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined +#error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined #endif -#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) - im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM; - im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM; -#endif #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM) im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM; im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM; #endif -#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) - im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM; - im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM; -#endif #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM) im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM; im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM; #endif -#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) - im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM; - im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM; -#endif #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM) im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM; im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM; #endif -#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) - im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM; - im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM; -#endif #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM) im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM; im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM; #endif -#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) - im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM; - im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM; -#endif #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM) im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM; im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM; #endif -#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) - im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM; - im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM; -#endif #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM) im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM; im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM; #endif -#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) - im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM; - im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM; -#endif #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM) im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM; im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM; diff --git a/arch/powerpc/cpu/mpc83xx/nand_init.c b/arch/powerpc/cpu/mpc83xx/nand_init.c index 38e141a..d1648b7 100644 --- a/arch/powerpc/cpu/mpc83xx/nand_init.c +++ b/arch/powerpc/cpu/mpc83xx/nand_init.c @@ -88,8 +88,8 @@ void cpu_init_f (volatile immap_t * im) && defined(CONFIG_SYS_NAND_OR_PRELIM) \ && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \ && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM) - im->lbus.bank[0].br = CONFIG_SYS_NAND_BR_PRELIM; - im->lbus.bank[0].or = CONFIG_SYS_NAND_OR_PRELIM; + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM; im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM; #else diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index b5076a9..93e9f1c 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -100,7 +100,8 @@ int get_clocks(void) u32 lcrr; u32 csb_clk; -#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; @@ -132,7 +133,8 @@ int get_clocks(void) u32 qe_clk; u32 brg_clk; #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC837x) u32 pciexp1_clk; u32 pciexp2_clk; #endif @@ -164,7 +166,8 @@ int get_clocks(void) sccr = im->clk.sccr; -#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: tsec1_clk = 0; @@ -202,7 +205,8 @@ int get_clocks(void) } #endif -#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \ + defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { case 0: tsec2_clk = 0; @@ -319,7 +323,7 @@ int get_clocks(void) i2c1_clk = csb_clk; #elif defined(CONFIG_MPC832x) i2c1_clk = enc_clk; -#elif defined(CONFIG_MPC831x) +#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) i2c1_clk = enc_clk; #elif defined(CONFIG_FSL_ESDHC) i2c1_clk = sdhc_clk; @@ -328,7 +332,8 @@ int get_clocks(void) i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ #endif -#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC837x) switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) { case 0: pciexp1_clk = 0; @@ -388,7 +393,7 @@ int get_clocks(void) lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); - lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; + lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; switch (lcrr) { case 2: case 4: @@ -444,7 +449,8 @@ int get_clocks(void) #endif gd->csb_clk = csb_clk; -#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) gd->tsec1_clk = tsec1_clk; gd->tsec2_clk = tsec2_clk; gd->usbdr_clk = usbdr_clk; @@ -525,7 +531,8 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_FSL_ESDHC) printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk)); #endif -#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk)); printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk)); printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk)); diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index f064fee..4ee0e9a 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -32,6 +32,7 @@ START = start.o resetvec.o SOBJS-$(CONFIG_MP) += release.o SOBJS = $(SOBJS-y) +COBJS-$(CONFIG_CMD_ERRATA) += cmd_errata.o COBJS-$(CONFIG_CPM2) += commproc.o # supports ddr1 @@ -63,6 +64,7 @@ COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_MP) += mp.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o +COBJS-$(CONFIG_P1022) += p1022_serdes.o COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_CPM2) += serial_scc.o diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c new file mode 100644 index 0000000..d7835c8 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -0,0 +1,51 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <linux/compiler.h> +#include <asm/processor.h> + +static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + __maybe_unused u32 svr = get_svr(); + +#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) + if (IS_SVR_REV(svr, 1, 0)) { + switch (SVR_SOC_VER(svr)) { + case SVR_P1013: + case SVR_P1013_E: + case SVR_P1022: + case SVR_P1022_E: + puts("Work-around for Erratum SATA A001 enabled\n"); + } + } +#endif + + return 0; +} + +U_BOOT_CMD( + errata, 1, 0, do_errata, + "Report errata workarounds", + "" +); diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 6f81fdf..fe2b52d 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -32,6 +32,8 @@ #include <fsl_esdhc.h> #include <asm/cache.h> #include <asm/io.h> +#include <asm/mmu.h> +#include <asm/fsl_law.h> DECLARE_GLOBAL_DATA_PTR; @@ -93,18 +95,26 @@ int checkcpu (void) minor = PVR_MIN(pvr); printf("Core: "); - switch (fam) { - case PVR_FAM(PVR_85xx): - puts("E500"); - break; - default: - puts("Unknown"); - break; + if (PVR_FAM(PVR_85xx)) { + switch(PVR_MEM(pvr)) { + case 0x1: + case 0x2: + puts("E500"); + break; + case 0x3: + puts("E500MC"); + break; + case 0x4: + puts("E5500"); + break; + default: + puts("Unknown"); + break; + } + } else { + puts("Unknown"); } - if (PVR_MEM(pvr) == 0x03) - puts("MC"); - printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); get_sys_info(&sysinfo); @@ -250,71 +260,6 @@ reset_85xx_watchdog(void) #endif /* CONFIG_WATCHDOG */ /* - * Configures a UPM. The function requires the respective MxMR to be set - * before calling this function. "size" is the number or entries, not a sizeof. - */ -void upmconfig (uint upm, uint * table, uint size) -{ - int i, mdr, mad, old_mad = 0; - volatile u32 *mxmr; - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); - volatile u32 *brp,*orp; - volatile u8* dummy = NULL; - int upmmask; - - switch (upm) { - case UPMA: - mxmr = &lbc->mamr; - upmmask = BR_MS_UPMA; - break; - case UPMB: - mxmr = &lbc->mbmr; - upmmask = BR_MS_UPMB; - break; - case UPMC: - mxmr = &lbc->mcmr; - upmmask = BR_MS_UPMC; - break; - default: - printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm); - hang(); - } - - /* Find the address for the dummy write transaction */ - for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8; - i++, brp += 2, orp += 2) { - - /* Look for a valid BR with selected UPM */ - if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) { - dummy = (volatile u8*)(in_be32(brp) & BR_BA); - break; - } - } - - if (i == 8) { - printf("Error: %s() could not find matching BR\n", __FUNCTION__); - hang(); - } - - for (i = 0; i < size; i++) { - /* 1 */ - out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i); - /* 2 */ - out_be32(&lbc->mdr, table[i]); - /* 3 */ - mdr = in_be32(&lbc->mdr); - /* 4 */ - *(volatile u8 *)dummy = 0; - /* 5 */ - do { - mad = in_be32(mxmr) & MxMR_MAD_MSK; - } while (mad <= old_mad && !(!mad && i == (size-1))); - old_mad = mad; - } - out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM); -} - -/* * Initializes on-chip MMC controllers. * to override, implement board_mmc_init() */ @@ -326,3 +271,14 @@ int cpu_mmc_init(bd_t *bis) return 0; #endif } + +/* + * Print out the state of various machine registers. + * Currently prints out LAWs, BR0/OR0, and TLBs + */ +void mpc85xx_reginfo(void) +{ + print_tlbcam(); + print_laws(); + print_lbc_regs(); +} diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 99431dc..d491e2a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -154,7 +154,6 @@ static void corenet_tb_init(void) void cpu_init_f (void) { - volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); extern void m8560_cpm_reset (void); #ifdef CONFIG_MPC8548 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); @@ -177,60 +176,7 @@ void cpu_init_f (void) config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); #endif - /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary - * addresses - these have to be modified later when FLASH size - * has been determined - */ -#if defined(CONFIG_SYS_OR0_REMAP) - out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP); -#endif -#if defined(CONFIG_SYS_OR1_REMAP) - out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP); -#endif - - /* now restrict to preliminary range */ - /* if cs1 is already set via debugger, leave cs0/cs1 alone */ - if (! memctl->br1 & 1) { -#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM) - out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM); - out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM); -#endif - -#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) - out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM); - out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM); -#endif - } - -#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) - out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM); - out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM); -#endif - -#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) - out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM); - out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM); -#endif - -#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) - out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM); - out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM); -#endif - -#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) - out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM); - out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM); -#endif - -#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) - out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM); - out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM); -#endif - -#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) - out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM); - out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM); -#endif + init_early_memctl_regs(); #if defined(CONFIG_CPM2) m8560_cpm_reset(); @@ -263,7 +209,7 @@ void cpu_init_f (void) int cpu_init_r(void) { #ifdef CONFIG_SYS_LBC_LCRR - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; #endif puts ("L2: "); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c index 184cca4..8fb27ab 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c @@ -25,7 +25,7 @@ void cpu_init_f(void) { - ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + fsl_lbc_t *lbc = LBC_BASE_ADDR; /* * LCRR - Clock Ratio Register - set up local bus timing @@ -34,8 +34,8 @@ void cpu_init_f(void) out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8); #if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM) - out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM); - out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM); + set_lbc_br(0, CONFIG_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_NAND_OR_PRELIM); #else #error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined #endif diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 1d11ab4..2628cc5 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -404,8 +404,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_MP ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); -#endif ft_fixup_num_cores(blob); +#endif ft_fixup_cache(blob); diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index ddbc221..e05257c 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -77,6 +77,13 @@ int cpu_disable(int nr) return 0; } + +int is_core_disabled(int nr) { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 coredisrl = in_be32(&gur->coredisrl); + + return (coredisrl & (1 << nr)); +} #else int cpu_disable(int nr) { @@ -96,6 +103,22 @@ int cpu_disable(int nr) return 0; } + +int is_core_disabled(int nr) { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr = in_be32(&gur->devdisr); + + switch (nr) { + case 0: + return (devdisr & MPC85xx_DEVDISR_CPU0); + case 1: + return (devdisr & MPC85xx_DEVDISR_CPU1); + default: + printf("Invalid cpu number for disable %d\n", nr); + } + + return 0; +} #endif static u8 boot_entry_map[4] = { diff --git a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c new file mode 100644 index 0000000..6b0fbf2 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c @@ -0,0 +1,98 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Author: Timur Tabi <timur@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 +#define SRDS2_MAX_LANES 2 + +static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x00] = {NONE, NONE, NONE, NONE}, + [0x01] = {NONE, NONE, NONE, NONE}, + [0x02] = {NONE, NONE, NONE, NONE}, + [0x03] = {NONE, NONE, NONE, NONE}, + [0x04] = {NONE, NONE, NONE, NONE}, + [0x06] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2}, + [0x07] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2}, + [0x09] = {PCIE1, NONE, NONE, NONE}, + [0x0a] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2}, + [0x0b] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2}, + [0x0d] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x0e] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x0f] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x15] = {PCIE1, PCIE3, PCIE2, PCIE2}, + [0x16] = {PCIE1, PCIE3, PCIE2, PCIE2}, + [0x17] = {PCIE1, PCIE3, PCIE2, PCIE2}, + [0x18] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x19] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1a] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1b] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1c] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x1d] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1e] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1f] = {PCIE1, PCIE1, PCIE2, PCIE2}, +}; + +static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x00] = {PCIE3, PCIE3}, + [0x01] = {PCIE2, PCIE3}, + [0x02] = {SATA1, SATA2}, + [0x03] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x04] = {NONE, NONE}, + [0x06] = {SATA1, SATA2}, + [0x07] = {NONE, NONE}, + [0x09] = {PCIE3, PCIE2}, + [0x0a] = {SATA1, SATA2}, + [0x0b] = {NONE, NONE}, + [0x0d] = {PCIE3, PCIE2}, + [0x0e] = {SATA1, SATA2}, + [0x0f] = {NONE, NONE}, + [0x15] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x16] = {SATA1, SATA2}, + [0x17] = {NONE, NONE}, + [0x18] = {PCIE3, PCIE3}, + [0x19] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x1a] = {SATA1, SATA2}, + [0x1b] = {NONE, NONE}, + [0x1c] = {PCIE3, PCIE3}, + [0x1d] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x1e] = {SATA1, SATA2}, + [0x1f] = {NONE, NONE}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + unsigned int i; + + debug("%s: dev = %d\n", __FUNCTION__, device); + debug("PORDEVSR[IO_SEL] = 0x%x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds_cfg); + return 0; + } + + for (i = 0; i < SRDS1_MAX_LANES; i++) { + if (serdes1_cfg_tbl[srds_cfg][i] == device) + return 1; + if (serdes2_cfg_tbl[srds_cfg][i] == device) + return 1; + } + + return 0; +} diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 8132115..dd4c6b3 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -172,10 +172,7 @@ void get_sys_info (sys_info_t * sysInfo) /* We will program LCRR to this value later */ lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; #else - { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); - lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV; - } + lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; #endif if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { #if defined(CONFIG_FSL_CORENET) diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index b3037ac..f2833a5 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -55,7 +55,45 @@ void init_tlbs(void) return ; } +void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, + phys_addr_t *rpn) +{ + u32 _mas1; + + mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0)); + asm volatile("tlbre;isync"); + _mas1 = mfspr(MAS1); + + *valid = (_mas1 & MAS1_VALID); + *tsize = (_mas1 >> 8) & 0xf; + *epn = mfspr(MAS2) & MAS2_EPN; + *rpn = mfspr(MAS3) & MAS3_RPN; +#ifdef CONFIG_ENABLE_36BIT_PHYS + *rpn |= ((u64)mfspr(MAS7)) << 32; +#endif +} + #ifndef CONFIG_NAND_SPL +void print_tlbcam(void) +{ + int i; + unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; + + /* walk all the entries */ + printf("TLBCAM entries\n"); + for (i = 0; i < num_cam; i++) { + unsigned long epn; + u32 tsize, valid; + phys_addr_t rpn; + + read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn); + printf("entry %02d: V: %d EPN 0x%08x RPN 0x%08llx size:", + i, (valid == 0) ? 0 : 1, (unsigned int)epn, + (unsigned long long)rpn); + print_size(TSIZE_TO_BYTES(tsize), "\n"); + } +} + static inline void use_tlb_cam(u8 idx) { int i = idx / 32; @@ -82,15 +120,9 @@ void init_used_tlb_cams(void) /* walk all the entries */ for (i = 0; i < num_cam; i++) { - u32 _mas1; - mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0)); - asm volatile("tlbre;isync"); - _mas1 = mfspr(MAS1); - - /* if the entry isn't valid skip it */ - if ((_mas1 & MAS1_VALID)) + if (mfspr(MAS1) & MAS1_VALID) use_tlb_cam(i); } } @@ -134,7 +166,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn, #ifdef CONFIG_ADDR_MAP if ((tlb == 1) && (gd->flags & GD_FLG_RELOC)) - addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel); + addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel); #endif } @@ -201,26 +233,12 @@ void init_addr_map(void) /* walk all the entries */ for (i = 0; i < num_cam; i++) { unsigned long epn; - u32 tsize, _mas1; + u32 tsize, valid; phys_addr_t rpn; - mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0)); - - asm volatile("tlbre;isync"); - _mas1 = mfspr(MAS1); - - /* if the entry isn't valid skip it */ - if (!(_mas1 & MAS1_VALID)) - continue; - - tsize = (_mas1 >> 8) & 0xf; - epn = mfspr(MAS2) & MAS2_EPN; - rpn = mfspr(MAS3) & MAS3_RPN; -#ifdef CONFIG_ENABLE_36BIT_PHYS - rpn |= ((phys_addr_t)mfspr(MAS7)) << 32; -#endif - - addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), i); + read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn); + if (valid & MAS1_VALID) + addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i); } return ; diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c index 9064e78..4e90fd2 100644 --- a/arch/powerpc/cpu/mpc86xx/cpu.c +++ b/arch/powerpc/cpu/mpc86xx/cpu.c @@ -180,22 +180,9 @@ watchdog_reset(void) */ void mpc86xx_reginfo(void) { - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - ccsr_lbc_t *lbc = &immap->im_lbc; - print_bats(); print_laws(); - - printf ("Local Bus Controller Registers\n" - "\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0)); - printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1)); - printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2)); - printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3)); - printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4)); - printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5)); - printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6)); - printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7)); - + print_lbc_regs(); } /* diff --git a/arch/powerpc/cpu/mpc86xx/cpu_init.c b/arch/powerpc/cpu/mpc86xx/cpu_init.c index b4f047d..82c216b 100644 --- a/arch/powerpc/cpu/mpc86xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc86xx/cpu_init.c @@ -46,9 +46,6 @@ DECLARE_GLOBAL_DATA_PTR; void cpu_init_f(void) { - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_lbc_t *memctl = &immap->im_lbc; - /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); @@ -61,58 +58,8 @@ void cpu_init_f(void) setup_bats(); - /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary - * addresses - these have to be modified later when FLASH size - * has been determined - */ - -#if defined(CONFIG_SYS_OR0_REMAP) - memctl->or0 = CONFIG_SYS_OR0_REMAP; -#endif -#if defined(CONFIG_SYS_OR1_REMAP) - memctl->or1 = CONFIG_SYS_OR1_REMAP; -#endif - - /* now restrict to preliminary range */ -#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM) - memctl->br0 = CONFIG_SYS_BR0_PRELIM; - memctl->or0 = CONFIG_SYS_OR0_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) - memctl->or1 = CONFIG_SYS_OR1_PRELIM; - memctl->br1 = CONFIG_SYS_BR1_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) - memctl->or2 = CONFIG_SYS_OR2_PRELIM; - memctl->br2 = CONFIG_SYS_BR2_PRELIM; -#endif + init_early_memctl_regs(); -#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) - memctl->or3 = CONFIG_SYS_OR3_PRELIM; - memctl->br3 = CONFIG_SYS_BR3_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) - memctl->or4 = CONFIG_SYS_OR4_PRELIM; - memctl->br4 = CONFIG_SYS_BR4_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) - memctl->or5 = CONFIG_SYS_OR5_PRELIM; - memctl->br5 = CONFIG_SYS_BR5_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) - memctl->or6 = CONFIG_SYS_OR6_PRELIM; - memctl->br6 = CONFIG_SYS_BR6_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) - memctl->or7 = CONFIG_SYS_OR7_PRELIM; - memctl->br7 = CONFIG_SYS_BR7_PRELIM; -#endif #if defined(CONFIG_FSL_DMA) dma_init(); #endif diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c index 51f3f4c..ff89ee5 100644 --- a/arch/powerpc/cpu/mpc86xx/fdt.c +++ b/arch/powerpc/cpu/mpc86xx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008,2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -55,6 +55,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); if (off < 0) printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); -#endif + ft_fixup_num_cores(blob); +#endif } diff --git a/arch/powerpc/cpu/mpc86xx/mp.c b/arch/powerpc/cpu/mpc86xx/mp.c index 24eb30a..30c99eb 100644 --- a/arch/powerpc/cpu/mpc86xx/mp.c +++ b/arch/powerpc/cpu/mpc86xx/mp.c @@ -66,6 +66,23 @@ int cpu_disable(int nr) return 0; } +int is_core_disabled(int nr) { + immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; + ccsr_gur_t *gur = &immap->im_gur; + u32 devdisr = in_be32(&gur->devdisr); + + switch (nr) { + case 0: + return (devdisr & MPC86xx_DEVDISR_CPU0); + case 1: + return (devdisr & MPC86xx_DEVDISR_CPU1); + default: + printf("Invalid cpu number for disable %d\n", nr); + } + + return 0; +} + int cpu_release(int nr, int argc, char * const argv[]) { /* dummy function so common/cmd_mp.c will build diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c index 64a3479..a2d0a8a 100644 --- a/arch/powerpc/cpu/mpc86xx/speed.c +++ b/arch/powerpc/cpu/mpc86xx/speed.c @@ -97,10 +97,7 @@ void get_sys_info(sys_info_t *sysInfo) /* We will program LCRR to this value later */ lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; #else - { - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV; - } + lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV; #endif if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { sysInfo->freqLocalBus = sysInfo->freqSystemBus / (lcrr_div * 2); diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index 481f9e5..ea51222 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2009 Freescale Semiconductor, Inc. +# Copyright 2009-2010 Freescale Semiconductor, Inc. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License @@ -10,9 +10,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib8xxx.a +ifneq ($(CPU),mpc83xx) COBJS-y += cpu.o -COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_PCI) += pci_cfg.o +endif + +COBJS-$(CONFIG_OF_LIBFDT) += fdt.o +COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index ccefaf5..88c47d1 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains @@ -26,6 +26,27 @@ #include <common.h> #include <libfdt.h> #include <fdt_support.h> +#include <asm/mp.h> + +#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) +static int ft_del_cpuhandle(void *blob, int cpuhandle) +{ + int off, ret = -FDT_ERR_NOTFOUND; + + /* if we find a match, we'll delete at it which point the offsets are + * invalid so we start over from the beginning + */ + off = fdt_node_offset_by_prop_value(blob, -1, "cpu-handle", + &cpuhandle, 4); + while (off != -FDT_ERR_NOTFOUND) { + fdt_delprop(blob, off, "cpu-handle"); + ret = 1; + off = fdt_node_offset_by_prop_value(blob, -1, "cpu-handle", + &cpuhandle, 4); + } + + return ret; +} void ft_fixup_num_cores(void *blob) { int off, num_cores, del_cores; @@ -37,13 +58,18 @@ void ft_fixup_num_cores(void *blob) { while (off != -FDT_ERR_NOTFOUND) { u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); - /* if we find a cpu node outside of what we expect delete it - * and reset the offset back to the start since we can't - * trust the offsets anymore - */ - if (*reg > num_cores-1) { - fdt_del_node(blob, off); - del_cores++; + if ((*reg > num_cores-1) || (is_core_disabled(*reg))) { + int ph = fdt_get_phandle(blob, off); + + /* Delete the cpu node once there are no cpu handles */ + if (-FDT_ERR_NOTFOUND == ft_del_cpuhandle(blob, ph)) { + fdt_del_node(blob, off); + del_cores++; + } + /* either we deleted some cpu handles or the cpu node + * so we reset the offset back to the start since we + * can't trust the offsets anymore + */ off = -1; } off = fdt_node_offset_by_prop_value(blob, off, @@ -53,3 +79,139 @@ void ft_fixup_num_cores(void *blob) { debug ("deleted %d extra core entry entries from device tree\n", del_cores); } +#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */ + +#ifdef CONFIG_HAS_FSL_DR_USB +void fdt_fixup_dr_usb(void *blob, bd_t *bd) +{ + char *mode; + char *type; + const char *compat = "fsl-usb2-dr"; + const char *prop_mode = "dr_mode"; + const char *prop_type = "phy_type"; + int node_offset; + int err; + + mode = getenv("usb_dr_mode"); + type = getenv("usb_phy_type"); + if (!mode && !type) + return; + + node_offset = fdt_node_offset_by_compatible(blob, 0, compat); + if (node_offset < 0) { + printf("WARNING: could not find compatible node %s: %s.\n", + compat, fdt_strerror(node_offset)); + return; + } + + if (mode) { + err = fdt_setprop(blob, node_offset, prop_mode, mode, + strlen(mode) + 1); + if (err < 0) + printf("WARNING: could not set %s for %s: %s.\n", + prop_mode, compat, fdt_strerror(err)); + } + + if (type) { + err = fdt_setprop(blob, node_offset, prop_type, type, + strlen(type) + 1); + if (err < 0) + printf("WARNING: could not set %s for %s: %s.\n", + prop_type, compat, fdt_strerror(err)); + } +} +#endif /* CONFIG_HAS_FSL_DR_USB */ + +/* + * update crypto node properties to a specified revision of the SEC + * called with sec_rev == 0 if not on an E processor + */ +#if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */ +void fdt_fixup_crypto_node(void *blob, int sec_rev) +{ + const struct sec_rev_prop { + u32 sec_rev; + u32 num_channels; + u32 channel_fifo_len; + u32 exec_units_mask; + u32 descriptor_types_mask; + } sec_rev_prop_list [] = { + { 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */ + { 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */ + { 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */ + { 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */ + { 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */ + { 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */ + { 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */ + }; + char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) * + sizeof("fsl,secX.Y")]; + int crypto_node, sec_idx, err; + char *p; + u32 val; + + /* locate crypto node based on lowest common compatible */ + crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0"); + if (crypto_node == -FDT_ERR_NOTFOUND) + return; + + /* delete it if not on an E-processor */ + if (crypto_node > 0 && !sec_rev) { + fdt_del_node(blob, crypto_node); + return; + } + + /* else we got called for possible uprev */ + for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++) + if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev) + break; + + if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) { + puts("warning: unknown SEC revision number\n"); + return; + } + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels); + err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask); + err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask); + err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len); + err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = 0; + while (sec_idx >= 0) { + p = compat_strlist + val; + val += sprintf(p, "fsl,sec%d.%d", + (sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8, + sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1; + sec_idx--; + } + err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, val); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); +} +#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */ +void fdt_fixup_crypto_node(void *blob, int sec_rev) +{ + if (!sec_rev) + fdt_del_node_and_alias(blob, "crypto"); +} +#endif diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c new file mode 100644 index 0000000..fcef40c --- /dev/null +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -0,0 +1,134 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <asm/fsl_lbc.h> + +void print_lbc_regs(void) +{ + int i; + + printf("\nLocal Bus Controller Registers\n"); + for (i = 0; i < 8; i++) { + printf("BR%d\t0x%08X\tOR%d\t0x%08X\n", + i, get_lbc_br(i), i, get_lbc_or(i)); + } +} + +void init_early_memctl_regs(void) +{ + uint init_br1 = 1; + +#ifdef CONFIG_MPC85xx + /* if cs1 is already set via debugger, leave cs0/cs1 alone */ + if (get_lbc_br(1) & BR_V) + init_br1 = 0; +#endif + + /* + * Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at + * preliminary addresses - these have to be modified later + * when FLASH size has been determined + */ +#if defined(CONFIG_SYS_OR0_REMAP) + set_lbc_or(0, CONFIG_SYS_OR0_REMAP); +#endif +#if defined(CONFIG_SYS_OR1_REMAP) + set_lbc_or(1, CONFIG_SYS_OR1_REMAP); +#endif + /* now restrict to preliminary range */ + if (init_br1) { + set_lbc_br(0, CONFIG_SYS_BR0_PRELIM); + set_lbc_or(0, CONFIG_SYS_OR0_PRELIM); + +#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) + set_lbc_or(1, CONFIG_SYS_OR1_PRELIM); + set_lbc_br(1, CONFIG_SYS_BR1_PRELIM); +#endif + } + +#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); +#endif + +#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) + set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); + set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); +#endif + +#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) + set_lbc_or(4, CONFIG_SYS_OR4_PRELIM); + set_lbc_br(4, CONFIG_SYS_BR4_PRELIM); +#endif + +#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) + set_lbc_or(5, CONFIG_SYS_OR5_PRELIM); + set_lbc_br(5, CONFIG_SYS_BR5_PRELIM); +#endif + +#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) + set_lbc_or(6, CONFIG_SYS_OR6_PRELIM); + set_lbc_br(6, CONFIG_SYS_BR6_PRELIM); +#endif + +#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) + set_lbc_or(7, CONFIG_SYS_OR7_PRELIM); + set_lbc_br(7, CONFIG_SYS_BR7_PRELIM); +#endif +} + +/* + * Configures a UPM. The function requires the respective MxMR to be set + * before calling this function. "size" is the number or entries, not a sizeof. + */ +void upmconfig(uint upm, uint *table, uint size) +{ + fsl_lbc_t *lbc = LBC_BASE_ADDR; + int i, mdr, mad, old_mad = 0; + u32 mask = (~MxMR_OP_MSK & ~MxMR_MAD_MSK); + u32 msel = BR_UPMx_TO_MSEL(upm); + u32 *mxmr = &lbc->mamr + upm; + volatile u8 *dummy = NULL; + + if (upm < UPMA || upm > UPMC) { + printf("Error: %s() Bad UPM index %d\n", __func__, upm); + hang(); + } + + /* + * Find the address for the dummy write - scan all of the BRs until we + * find one matching the UPM and extract the base address bits from it. + */ + for (i = 0; i < 8; i++) { + if ((get_lbc_br(i) & (BR_V | BR_MSEL)) == (BR_V | msel)) { + dummy = (volatile u8 *)(get_lbc_br(i) & BR_BA); + break; + } + } + + if (!dummy) { + printf("Error: %s() No matching BR\n", __func__); + hang(); + } + + /* Program UPM using steps outlined by the reference manual */ + for (i = 0; i < size; i++) { + out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_WARR | i); + out_be32(&lbc->mdr, table[i]); + mdr = in_be32(&lbc->mdr); + *dummy = 0; + do { + mad = in_be32(mxmr) & MxMR_MAD_MSK; + } while (mad <= old_mad && !(!mad && i == (size-1))); + old_mad = mad; + } + + /* Return to normal operation */ + out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_NORM); +} diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index fc3facb..d88c282 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -66,6 +66,15 @@ #define CONFIG_TSECV2 #endif +/* + * SEC (crypto unit) major compatible version determination + */ +#if defined(CONFIG_FSL_CORENET) +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx) +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#endif + /* Number of TLB CAM entries we have on FSL Book-E chips */ #if defined(CONFIG_E500MC) #define CONFIG_SYS_NUM_TLBCAMS 64 @@ -76,4 +85,10 @@ /* Relocation to SDRAM works on all PPC boards */ #define CONFIG_RELOC_FIXUP_WORKS +/* Since so many PPC SOCs have a semi-common LBC, define this here */ +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ + defined(CONFIG_MPC83xx) +#define CONFIG_FSL_LBC +#endif + #endif /* _ASM_CONFIG_H_ */ diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 34c56a2..12ba1a6 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -47,6 +47,7 @@ enum law_size { }; #define law_size_bits(sz) (__ilog2_u64(sz) - 1) +#define lawar_size(x) (1ULL << ((x & 0x3f) + 1)) #ifdef CONFIG_FSL_CORENET enum law_trgt_if { diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 03ae6a7..82d24ab 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -14,6 +14,7 @@ #define __ASM_PPC_FSL_LBC_H #include <config.h> +#include <common.h> /* BR - Base Registers */ @@ -61,6 +62,8 @@ #define BR_V 0x00000001 #define BR_V_SHIFT 0 +#define BR_UPMx_TO_MSEL(x) ((x + 4) << BR_MSEL_SHIFT) + #define UPMA 0 #define UPMB 1 #define UPMC 2 @@ -453,49 +456,70 @@ #define LTESR_CC 0x00000001 #ifndef __ASSEMBLY__ -/* - * Local Bus Controller Registers. - */ -typedef struct lbus_bank { - u32 br; /* Base Register */ - u32 or; /* Option Register */ -} lbus_bank_t; - -typedef struct fsl_lbus { - lbus_bank_t bank[8]; - u8 res0[0x28]; - u32 mar; /* UPM Address Register */ - u8 res1[0x4]; - u32 mamr; /* UPMA Mode Register */ - u32 mbmr; /* UPMB Mode Register */ - u32 mcmr; /* UPMC Mode Register */ - u8 res2[0x8]; - u32 mrtpr; /* Memory Refresh Timer Prescaler Register */ - u32 mdr; /* UPM Data Register */ - u8 res3[0x4]; - u32 lsor; /* Special Operation Initiation Register */ - u32 lsdmr; /* SDRAM Mode Register */ - u8 res4[0x8]; - u32 lurt; /* UPM Refresh Timer */ - u32 lsrt; /* SDRAM Refresh Timer */ - u8 res5[0x8]; - u32 ltesr; /* Transfer Error Status Register */ - u32 ltedr; /* Transfer Error Disable Register */ - u32 lteir; /* Transfer Error Interrupt Register */ - u32 lteatr; /* Transfer Error Attributes Register */ - u32 ltear; /* Transfer Error Address Register */ - u8 res6[0xC]; - u32 lbcr; /* Configuration Register */ - u32 lcrr; /* Clock Ratio Register */ - u8 res7[0x8]; - u32 fmr; /* Flash Mode Register */ - u32 fir; /* Flash Instruction Register */ - u32 fcr; /* Flash Command Register */ - u32 fbar; /* Flash Block Addr Register */ - u32 fpar; /* Flash Page Addr Register */ - u32 fbcr; /* Flash Byte Count Register */ - u8 res8[0xF08]; -} fsl_lbus_t; -#endif /* __ASSEMBLY__ */ +#include <asm/io.h> + +extern void print_lbc_regs(void); +extern void init_early_memctl_regs(void); +extern void upmconfig(uint upm, uint *table, uint size); + +#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR) +#define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br)) +#define get_lbc_or(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].or)) +#define set_lbc_br(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].br, v)) +#define set_lbc_or(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].or, v)) + +typedef struct lbc_bank { + u32 br; + u32 or; +} lbc_bank_t; +/* Local Bus Controller Registers */ +typedef struct fsl_lbc { + lbc_bank_t bank[8]; + u8 res1[40]; + u32 mar; /* LBC UPM Addr */ + u8 res2[4]; + u32 mamr; /* LBC UPMA Mode */ + u32 mbmr; /* LBC UPMB Mode */ + u32 mcmr; /* LBC UPMC Mode */ + u8 res3[8]; + u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */ + u32 mdr; /* LBC UPM Data */ +#ifdef CONFIG_FSL_ELBC + u8 res4[4]; + u32 lsor; + u8 res5[12]; + u32 lurt; /* LBC UPM Refresh Timer */ + u8 res6[4]; +#else + u8 res4[8]; + u32 lsdmr; /* LBC SDRAM Mode */ + u8 res5[8]; + u32 lurt; /* LBC UPM Refresh Timer */ + u32 lsrt; /* LBC SDRAM Refresh Timer */ +#endif + u8 res7[8]; + u32 ltesr; /* LBC Transfer Error Status */ + u32 ltedr; /* LBC Transfer Error Disable */ + u32 lteir; /* LBC Transfer Error IRQ */ + u32 lteatr; /* LBC Transfer Error Attrs */ + u32 ltear; /* LBC Transfer Error Addr */ + u8 res8[12]; + u32 lbcr; /* LBC Configuration */ + u32 lcrr; /* LBC Clock Ratio */ +#ifdef CONFIG_NAND_FSL_ELBC + u8 res9[0x8]; + u32 fmr; /* Flash Mode Register */ + u32 fir; /* Flash Instruction Register */ + u32 fcr; /* Flash Command Register */ + u32 fbar; /* Flash Block Addr Register */ + u32 fpar; /* Flash Page Addr Register */ + u32 fbcr; /* Flash Byte Count Register */ + u8 res10[0xF08]; +#else + u8 res9[0xF28]; +#endif +} fsl_lbc_t; + +#endif /* __ASSEMBLY__ */ #endif /* __ASM_PPC_FSL_LBC_H */ diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index db61e7e..bb87543 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -162,14 +162,15 @@ typedef struct ccsr_pci { } ccsr_fsl_pci_t; struct fsl_pci_info { - unsigned long regs; - pci_addr_t mem_bus; - phys_size_t mem_phys; - pci_size_t mem_size; - pci_addr_t io_bus; - phys_size_t io_phys; - pci_size_t io_size; - int pci_num; + unsigned long regs; + pci_addr_t mem_bus; + phys_size_t mem_phys; + pci_size_t mem_size; + pci_addr_t io_bus; + phys_size_t io_phys; + pci_size_t io_size; + enum law_trgt_if law; + int pci_num; }; int fsl_pci_init_port(struct fsl_pci_info *pci_info, @@ -184,6 +185,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \ x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \ x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \ + x.law = LAW_TRGT_IF_PCI_##num; \ x.pci_num = num; \ } @@ -196,6 +198,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \ x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \ x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \ + x.law = LAW_TRGT_IF_PCIE_##num; \ x.pci_num = num; \ } diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index d3dd44e..c854ce9 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -60,7 +60,8 @@ typedef struct global_data { #if defined(CONFIG_MPC83xx) /* There are other clocks in the MPC83XX */ u32 csb_clk; -#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; @@ -76,7 +77,8 @@ typedef struct global_data { u32 lbiu_clk; u32 lclk_clk; u32 pci_clk; -#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC837x) u32 pciexp1_clk; u32 pciexp2_clk; #endif diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 6b42a73..cc0293a 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -73,7 +73,11 @@ typedef struct sysconf83xx { u32 obir; /* Output Buffer Impedance Register */ u8 res8[0xC]; u32 pecr1; /* PCI Express control register 1 */ +#ifdef CONFIG_MPC8308 + u32 sdhccr; /* eSDHC Control Registers for MPC8308 */ +#else u32 pecr2; /* PCI Express control register 2 */ +#endif u8 res9[0xB8]; } sysconf83xx_t; @@ -589,7 +593,14 @@ typedef struct sdhc83xx { * SerDes */ typedef struct serdes83xx { - u8 fixme[0x100]; + u32 srdscr0; + u32 srdscr1; + u32 srdscr2; + u32 srdscr3; + u32 srdscr4; + u8 res0[0xc]; + u32 srdsrstctl; + u8 res1[0xdc]; } serdes83xx_t; /* @@ -635,7 +646,7 @@ typedef struct immap { u8 res2[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res3[0x900]; - fsl_lbus_t lbus; /* Local Bus Controller Registers */ + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ u8 res4[0x1000]; spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ @@ -675,7 +686,7 @@ typedef struct immap { u8 res1[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res2[0x900]; - fsl_lbus_t lbus; /* Local Bus Controller Registers */ + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ u8 res3[0x1000]; spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ @@ -691,7 +702,7 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t; -#elif defined(CONFIG_MPC8315) +#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ @@ -710,7 +721,7 @@ typedef struct immap { u8 res1[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res2[0x900]; - fsl_lbus_t lbus; /* Local Bus Controller Registers */ + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ u8 res3[0x1000]; spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ @@ -755,7 +766,7 @@ typedef struct immap { u8 res1[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res2[0x900]; - fsl_lbus_t lbus; /* Local Bus Controller Registers */ + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ u8 res3[0x1000]; spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ @@ -805,7 +816,7 @@ typedef struct immap { u8 res4[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res5[0x900]; - fsl_lbus_t lbus; /* Local Bus Controller Registers */ + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ u8 res6[0x2000]; dma83xx_t dma; /* DMA */ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ @@ -844,7 +855,7 @@ typedef struct immap { u8 res3[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res4[0x900]; - fsl_lbus_t lbus; /* Local Bus Controller Registers */ + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ u8 res5[0x2000]; dma83xx_t dma; /* DMA */ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ @@ -868,6 +879,7 @@ typedef struct immap { #endif #define CONFIG_SYS_MPC83xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET) +#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) #define CONFIG_SYS_TSEC1_OFFSET 0x24000 #define CONFIG_SYS_MDIO1_OFFSET 0x24000 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 5b205d1..4e665d3 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -266,50 +266,6 @@ typedef struct ccsr_duart { } ccsr_duart_t; #endif -/* Local Bus Controller Registers */ -typedef struct ccsr_lbc { - u32 br0; /* LBC Base 0 */ - u32 or0; /* LBC Options 0 */ - u32 br1; /* LBC Base 1 */ - u32 or1; /* LBC Options 1 */ - u32 br2; /* LBC Base 2 */ - u32 or2; /* LBC Options 2 */ - u32 br3; /* LBC Base 3 */ - u32 or3; /* LBC Options 3 */ - u32 br4; /* LBC Base 4 */ - u32 or4; /* LBC Options 4 */ - u32 br5; /* LBC Base 5 */ - u32 or5; /* LBC Options 5 */ - u32 br6; /* LBC Base 6 */ - u32 or6; /* LBC Options 6 */ - u32 br7; /* LBC Base 7 */ - u32 or7; /* LBC Options 7 */ - u8 res1[40]; - u32 mar; /* LBC UPM Addr */ - u8 res2[4]; - u32 mamr; /* LBC UPMA Mode */ - u32 mbmr; /* LBC UPMB Mode */ - u32 mcmr; /* LBC UPMC Mode */ - u8 res3[8]; - u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */ - u32 mdr; /* LBC UPM Data */ - u8 res4[8]; - u32 lsdmr; /* LBC SDRAM Mode */ - u8 res5[8]; - u32 lurt; /* LBC UPM Refresh Timer */ - u32 lsrt; /* LBC SDRAM Refresh Timer */ - u8 res6[8]; - u32 ltesr; /* LBC Transfer Error Status */ - u32 ltedr; /* LBC Transfer Error Disable */ - u32 lteir; /* LBC Transfer Error IRQ */ - u32 lteatr; /* LBC Transfer Error Attrs */ - u32 ltear; /* LBC Transfer Error Addr */ - u8 res7[12]; - u32 lbcr; /* LBC Configuration */ - u32 lcrr; /* LBC Clock Ratio */ - u8 res8[3880]; -} ccsr_lbc_t; - /* eSPI Registers */ typedef struct ccsr_espi { u32 mode; /* eSPI mode */ @@ -2045,6 +2001,41 @@ enum { FSL_SRDS_B3_LANE_D = 23, }; +/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ +#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 +typedef struct ccsr_sec { + u8 res1[0xfa0]; + u32 crnr_ms; /* CHA Revision Number Register, MS */ + u32 crnr_ls; /* CHA Revision Number Register, LS */ + u32 ctpr_ms; /* Compile Time Parameters Register, MS */ +#define SEC_CTPR_MS_AXI_LIODN 0x08000000 +#define SEC_CTPR_MS_QI 0x02000000 + u32 ctpr_ls; /* Compile Time Parameters Register, LS */ + u8 res2[0x10]; + u32 far_ms; /* Fault Address Register, MS */ + u32 far_ls; /* Fault Address Register, LS */ + u32 falr; /* Fault Address LIODN Register */ + u32 fadr; /* Fault Address Detail Register */ + u8 res3[0x4]; + u32 csta; /* CAAM Status Register */ + u8 res4[0x8]; + u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ +#define SEC_RVID_MA 0x0f000000 + u32 ccbvid; /* CHA Cluster Block Version ID Register */ + u32 chavid_ms; /* CHA Version ID Register, MS */ + u32 chavid_ls; /* CHA Version ID Register, LS */ + u32 chanum_ms; /* CHA Number Register, MS */ +#define SEC_CHANUM_MS_JQNUM_MASK 0xf0000000 +#define SEC_CHANUM_MS_JQNUM_SHIFT 28 +#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 +#define SEC_CHANUM_MS_DECONUM_SHIFT 24 + u32 chanum_ls; /* CHA Number Register, LS */ + u32 caamvid_ms; /* CAAM Version ID Register, MS */ + u32 caamvid_ls; /* CAAM Version ID Register, LS */ + u8 res5[0xf000]; +} ccsr_sec_t; +#endif + #ifdef CONFIG_FSL_CORENET #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 @@ -2059,6 +2050,7 @@ enum { #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000 +#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 #define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000 #define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000 #define CONFIG_SYS_TSEC1_OFFSET 0x4e0000 /* FM1@DTSEC0 */ @@ -2111,7 +2103,7 @@ enum { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) #define CONFIG_SYS_MPC85xx_DDR2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) -#define CONFIG_SYS_MPC85xx_LBC_ADDR \ +#define CONFIG_SYS_LBC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) #define CONFIG_SYS_MPC85xx_ESPI_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) @@ -2143,6 +2135,8 @@ enum { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) #define CONFIG_SYS_MPC85xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) +#define CONFIG_SYS_FSL_SEC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h index fd7acdb..b9e02db 100644 --- a/arch/powerpc/include/asm/immap_86xx.h +++ b/arch/powerpc/include/asm/immap_86xx.h @@ -12,6 +12,7 @@ #include <asm/types.h> #include <asm/fsl_dma.h> +#include <asm/fsl_lbc.h> #include <asm/fsl_i2c.h> /* Local-Access Registers and MCM Registers(0x0000-0x2000) */ @@ -190,51 +191,6 @@ typedef struct ccsr_duart { char res5[2543]; } ccsr_duart_t; - -/* Local Bus Controller Registers(0x5000-0x6000) */ -typedef struct ccsr_lbc { - uint br0; /* 0x5000 - LBC Base Register 0 */ - uint or0; /* 0x5004 - LBC Options Register 0 */ - uint br1; /* 0x5008 - LBC Base Register 1 */ - uint or1; /* 0x500c - LBC Options Register 1 */ - uint br2; /* 0x5010 - LBC Base Register 2 */ - uint or2; /* 0x5014 - LBC Options Register 2 */ - uint br3; /* 0x5018 - LBC Base Register 3 */ - uint or3; /* 0x501c - LBC Options Register 3 */ - uint br4; /* 0x5020 - LBC Base Register 4 */ - uint or4; /* 0x5024 - LBC Options Register 4 */ - uint br5; /* 0x5028 - LBC Base Register 5 */ - uint or5; /* 0x502c - LBC Options Register 5 */ - uint br6; /* 0x5030 - LBC Base Register 6 */ - uint or6; /* 0x5034 - LBC Options Register 6 */ - uint br7; /* 0x5038 - LBC Base Register 7 */ - uint or7; /* 0x503c - LBC Options Register 7 */ - char res1[40]; - uint mar; /* 0x5068 - LBC UPM Address Register */ - char res2[4]; - uint mamr; /* 0x5070 - LBC UPMA Mode Register */ - uint mbmr; /* 0x5074 - LBC UPMB Mode Register */ - uint mcmr; /* 0x5078 - LBC UPMC Mode Register */ - char res3[8]; - uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */ - uint mdr; /* 0x5088 - LBC UPM Data Register */ - char res4[8]; - uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */ - char res5[8]; - uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */ - uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */ - char res6[8]; - uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */ - uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */ - uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */ - uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */ - uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */ - char res7[12]; - uint lbcr; /* 0x50d0 - LBC Configuration Register */ - uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */ - char res8[3880]; -} ccsr_lbc_t; - /* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */ typedef struct ccsr_pex { uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */ @@ -1270,7 +1226,7 @@ typedef struct immap { ccsr_ddr_t im_ddr1; ccsr_i2c_t im_i2c; ccsr_duart_t im_duart; - ccsr_lbc_t im_lbc; + fsl_lbc_t im_lbc; ccsr_ddr_t im_ddr2; char res1[4096]; ccsr_pex_t im_pex1; @@ -1303,6 +1259,7 @@ extern immap_t *immr; #define CONFIG_SYS_TSEC1_OFFSET 0x24000 #define CONFIG_SYS_MDIO1_OFFSET 0x24000 +#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index 5166507..c01c85f 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -402,6 +402,7 @@ extern void print_bats(void); #define MAS1_TID(x) ((x << 16) & 0x3FFF0000) #define MAS1_TS 0x00001000 #define MAS1_TSIZE(x) ((x << 8) & 0x00000F00) +#define TSIZE_TO_BYTES(x) ((phys_addr_t)(1UL << ((tsize * 2) + 10))) #define MAS2_EPN 0xFFFFF000 #define MAS2_X0 0x00000040 @@ -485,6 +486,7 @@ extern void init_tlbs(void); extern int find_tlb_idx(void *addr, u8 tlbsel); extern void init_used_tlb_cams(void); extern int find_free_tlbcam(void); +extern void print_tlbcam(void); extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); diff --git a/arch/powerpc/include/asm/mp.h b/arch/powerpc/include/asm/mp.h index 5388c95..3ffa30b 100644 --- a/arch/powerpc/include/asm/mp.h +++ b/arch/powerpc/include/asm/mp.h @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -26,5 +26,6 @@ void setup_mp(void); void cpu_mp_lmb_reserve(struct lmb *lmb); u32 determine_mp_bootpg(void); +int is_core_disabled(int nr); #endif diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index 41737d3..b0082af 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -27,9 +27,10 @@ #include <asm/types.h> -#if defined(CONFIG_MPC834x) || \ +#if defined(CONFIG_MPC8308) || \ defined(CONFIG_MPC8313) || \ defined(CONFIG_MPC8315) || \ + defined(CONFIG_MPC834x) || \ defined(CONFIG_MPC837x) typedef struct spi8xxx { diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 9ec319a..844552c 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -534,9 +534,11 @@ #define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ #define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ +#define BUCSR_STAC_EN 0x01000000 /* Segment target addr cache enable */ +#define BUCSR_LS_EN 0x00400000 /* Link stack enable */ #define BUCSR_BBFI 0x00000200 /* Branch buffer flash invalidate */ #define BUCSR_BPEN 0x00000001 /* Branch prediction enable */ -#define BUCSR_ENABLE (BUCSR_BBFI|BUCSR_BPEN) +#define BUCSR_ENABLE (BUCSR_STAC_EN|BUCSR_LS_EN|BUCSR_BBFI|BUCSR_BPEN) #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ #define SPRN_PID1 0x279 /* Process ID Register 1 */ diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c index 54c0ffe..bb388ed 100644 --- a/board/LaCie/edminiv2/edminiv2.c +++ b/board/LaCie/edminiv2/edminiv2.c @@ -27,6 +27,7 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/orion5x.h> +#include "edminiv2.h" DECLARE_GLOBAL_DATA_PTR; @@ -90,3 +91,38 @@ int board_init(void) return 0; } + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +/* Configure and enable MV88E1116 PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/LaCie/edminiv2/edminiv2.h b/board/LaCie/edminiv2/edminiv2.h new file mode 100644 index 0000000..88e62b2 --- /dev/null +++ b/board/LaCie/edminiv2/edminiv2.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2009 + * Net Insight <www.netinsight.net> + * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> + * + * Based on sheevaplug.h: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __EDMINIV2_BASE_H +#define __EDMINIV2_BASE_H + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __EDMINIV2_BASE_H */ diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c index 4652672..3c37557 100644 --- a/board/afeb9260/afeb9260.c +++ b/board/afeb9260/afeb9260.c @@ -167,13 +167,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/altera/ep1c20/config.mk b/board/altera/ep1c20/config.mk deleted file mode 100644 index dab2740..0000000 --- a/board/altera/ep1c20/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2005, Psyent Corporation <www.psyent.com> -# Scott McNutt <smcnutt@psyent.com> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x01fc0000 - -PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h index 761f605..a11add5 100644 --- a/board/altera/nios2-generic/custom_fpga.h +++ b/board/altera/nios2-generic/custom_fpga.h @@ -35,6 +35,16 @@ #define CONFIG_SMC91111 #define CONFIG_SMC_USE_32_BIT +/* epcs_controller.epcs_control_port is a altera_avalon_epcs_flash_controller */ +#define EPCS_CONTROLLER_REG_BASE 0x82100200 +#define CONFIG_SYS_ALTERA_SPI_LIST { EPCS_CONTROLLER_REG_BASE } +#define CONFIG_ALTERA_SPI +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + /* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */ #define CONFIG_SYS_JTAG_UART_BASE 0x821208b0 diff --git a/board/altera/nios2-generic/gpio.c b/board/altera/nios2-generic/gpio.c index 6c9c6c2..d449684 100644 --- a/board/altera/nios2-generic/gpio.c +++ b/board/altera/nios2-generic/gpio.c @@ -15,6 +15,11 @@ static u32 pio_data_reg; static u32 pio_dir_reg; +int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + int gpio_direction_input(unsigned gpio) { u32 mask = 1 << gpio; diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c index 258d1ea..2ab8bc2 100644 --- a/board/atmel/at91cap9adk/at91cap9adk.c +++ b/board/atmel/at91cap9adk/at91cap9adk.c @@ -339,13 +339,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index ed47360..64c6d17 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -179,13 +179,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 5cd7aa7..91efc07 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -284,13 +284,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 8fa0449..f92b20f 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -291,13 +291,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index c11a5c3..4f7d935 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -47,7 +47,7 @@ int board_early_init_f (void) int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); if ((uint)&gur->porpllsr != 0xe00e0000) { diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c b/board/bf518f-ezbrd/bf518f-ezbrd.c index 85b350f..ff1ac4c 100644 --- a/board/bf518f-ezbrd/bf518f-ezbrd.c +++ b/board/bf518f-ezbrd/bf518f-ezbrd.c @@ -14,6 +14,7 @@ #include <spi.h> #include <asm/blackfin.h> #include <asm/net.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/otp.h> #include <asm/sdh.h> @@ -61,6 +62,7 @@ static void board_init_enetaddr(uchar *mac_addr) #define KSZ_WRITE 0x02 #define KSZ_READ 0x03 +#define KSZ_REG_CHID 0x00 /* Register 0: Chip ID0 */ #define KSZ_REG_STPID 0x01 /* Register 1: Chip ID1 / Start Switch */ #define KSZ_REG_GC9 0x0b /* Register 11: Global Control 9 */ #define KSZ_REG_P3C0 0x30 /* Register 48: Port 3 Control 0 */ @@ -78,15 +80,17 @@ static int ksz8893m_reg_set(struct spi_slave *slave, uchar reg, uchar data) return ksz8893m_transfer(slave, KSZ_WRITE, reg, data, din); } -static int ksz8893m_reg_clear(struct spi_slave *slave, uchar reg, uchar mask) +static int ksz8893m_reg_read(struct spi_slave *slave, uchar reg) { - int ret = 0; + int ret; unsigned char din[3]; + ret = ksz8893m_transfer(slave, KSZ_READ, reg, 0, din); + return ret ? ret : din[2]; +} - ret |= ksz8893m_transfer(slave, KSZ_READ, reg, 0, din); - ret |= ksz8893m_reg_set(slave, reg, din[2] & mask); - - return ret; +static int ksz8893m_reg_clear(struct spi_slave *slave, uchar reg, uchar mask) +{ + return ksz8893m_reg_set(slave, reg, ksz8893m_reg_read(slave, reg) & mask); } static int ksz8893m_reset(struct spi_slave *slave) @@ -107,16 +111,16 @@ static int ksz8893m_reset(struct spi_slave *slave) int board_eth_init(bd_t *bis) { - static bool switch_is_alive = false; + static bool switch_is_alive = false, phy_is_ksz = true; int ret; if (!switch_is_alive) { struct spi_slave *slave = spi_setup_slave(0, 1, KSZ_MAX_HZ, SPI_MODE_3); if (slave) { if (!spi_claim_bus(slave)) { - ret = ksz8893m_reset(slave); - if (!ret) - switch_is_alive = true; + phy_is_ksz = (ksz8893m_reg_read(slave, KSZ_REG_CHID) == 0x88); + ret = phy_is_ksz ? ksz8893m_reset(slave) : 0; + switch_is_alive = (ret == 0); spi_release_bus(slave); } spi_free_slave(slave); @@ -143,18 +147,11 @@ int misc_init_r(void) int board_early_init_f(void) { -#if !defined(CONFIG_SYS_NO_FLASH) - /* setup BF518-EZBRD GPIO pin PG11 to AMS2. */ - bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2); - bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG11); - -# if !defined(CONFIG_BFIN_SPI) - /* setup BF518-EZBRD GPIO pin PG15 to AMS3. */ - bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_7_MASK) | PORT_x_MUX_7_FUNC_3); - bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG15); -# endif -#endif - return 0; + /* connect async banks by default */ + const unsigned short pins[] = { + P_AMS2, P_AMS3, 0, + }; + return peripheral_request_list(pins, "async"); } #ifdef CONFIG_BFIN_SDH diff --git a/board/bf526-ezbrd/Makefile b/board/bf526-ezbrd/Makefile index a9ff760..f2bd2c2 100644 --- a/board/bf526-ezbrd/Makefile +++ b/board/bf526-ezbrd/Makefile @@ -30,7 +30,6 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS-y := $(BOARD).o -COBJS-$(CONFIG_STATUS_LED) += status-led.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/bf526-ezbrd/status-led.c b/board/bf526-ezbrd/status-led.c deleted file mode 100644 index 6327022..0000000 --- a/board/bf526-ezbrd/status-led.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * U-boot - status leds - * - * Copyright (c) 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <config.h> -#include <command.h> -#include <status_led.h> - -static void set_led_f(int pf, int state) -{ - switch (state) { - case STATUS_LED_OFF: bfin_write_PORTFIO_CLEAR(pf); break; - case STATUS_LED_BLINKING: bfin_write_PORTFIO_TOGGLE(pf); break; - case STATUS_LED_ON: bfin_write_PORTFIO_SET(pf); break; - } -} -static void set_led_g(int pf, int state) -{ - switch (state) { - case STATUS_LED_OFF: bfin_write_PORTGIO_CLEAR(pf); break; - case STATUS_LED_BLINKING: bfin_write_PORTGIO_TOGGLE(pf); break; - case STATUS_LED_ON: bfin_write_PORTGIO_SET(pf); break; - } -} - -static void set_leds(led_id_t mask, int state) -{ - if (mask & 0x1) set_led_f(PF8, state); - if (mask & 0x2) set_led_g(PG11, state); - if (mask & 0x4) set_led_g(PG12, state); -} - -void __led_init(led_id_t mask, int state) -{ - bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~(PF8)); - bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~(PG11 | PG12)); - bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() & ~(PF8)); - bfin_write_PORTGIO_INEN(bfin_read_PORTGIO_INEN() & ~(PG11 | PG12)); - bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | (PF8)); - bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | (PG11 | PG12)); -} - -void __led_set(led_id_t mask, int state) -{ - set_leds(mask, state); -} - -void __led_toggle(led_id_t mask) -{ - set_leds(mask, STATUS_LED_BLINKING); -} diff --git a/board/bf527-ad7160-eval/Makefile b/board/bf527-ad7160-eval/Makefile new file mode 100644 index 0000000..f2bd2c2 --- /dev/null +++ b/board/bf527-ad7160-eval/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/bf527-ad7160-eval/bf527-ad7160-eval.c b/board/bf527-ad7160-eval/bf527-ad7160-eval.c new file mode 100644 index 0000000..b06d5ab --- /dev/null +++ b/board/bf527-ad7160-eval/bf527-ad7160-eval.c @@ -0,0 +1,25 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <asm/blackfin.h> +#include <asm/mach-common/bits/pll.h> + +int checkboard(void) +{ + printf("Board: ADI BF527 AD7160-EVAL board\n"); + printf(" Support: http://blackfin.uclinux.org/\n"); + return 0; +} + +int misc_init_r(void) +{ + /* CLKIN Buffer Output Enable */ + *pVR_CTL |= CLKBUFOE; + return 0; +} diff --git a/board/altera/ep1s40/config.mk b/board/bf527-ad7160-eval/config.mk index dab2740..f85bef5 100644 --- a/board/altera/ep1s40/config.mk +++ b/board/bf527-ad7160-eval/config.mk @@ -1,6 +1,8 @@ # -# (C) Copyright 2005, Psyent Corporation <www.psyent.com> -# Scott McNutt <smcnutt@psyent.com> +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this # project. @@ -21,11 +23,11 @@ # MA 02111-1307 USA # -TEXT_BASE = 0x01fc0000 +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me -PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif +# Set some default LDR flags based on boot mode. +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf527-ezkit/bf527-ezkit.c b/board/bf527-ezkit/bf527-ezkit.c index a911880..211cf24 100644 --- a/board/bf527-ezkit/bf527-ezkit.c +++ b/board/bf527-ezkit/bf527-ezkit.c @@ -12,6 +12,7 @@ #include <net.h> #include <netdev.h> #include <asm/blackfin.h> +#include <asm/gpio.h> #include <asm/net.h> #include <asm/mach-common/bits/otp.h> @@ -75,9 +76,7 @@ void board_musb_init(void) /* * BF527 EZ-KITs require PG13 to be high for HOST mode */ - bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~PG13); - bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | PG13); - bfin_write_PORTGIO_SET(PG13); - SSYNC(); + gpio_request(GPIO_PG13, "musb-vbus"); + gpio_direction_output(GPIO_PG13, 1); } #endif diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c index 8f6ea23..891070b 100644 --- a/board/bf527-ezkit/video.c +++ b/board/bf527-ezkit/video.c @@ -11,6 +11,7 @@ #include <config.h> #include <malloc.h> #include <asm/blackfin.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/dma.h> #include <spi.h> #include <linux/types.h> @@ -171,13 +172,11 @@ void DisablePPI(void) void Init_Ports(void) { - *pPORTF_MUX &= ~PORT_x_MUX_0_MASK; - *pPORTF_MUX |= PORT_x_MUX_0_FUNC_1; - *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF7; - - *pPORTG_MUX &= ~PORT_x_MUX_1_MASK; - *pPORTG_MUX |= PORT_x_MUX_1_FUNC_1; - *pPORTG_FER |= PG5; + const unsigned short pins[] = { + P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4, + P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_FS2, 0, + }; + peripheral_request_list(pins, "lcd"); } void Init_PPI(void) diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index 4abad08..935aad2 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -27,8 +27,7 @@ #include <common.h> #include <netdev.h> -#include <asm/io.h> -#include "bf533-stamp.h" +#include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -46,15 +45,10 @@ int checkboard(void) */ void swap_to(int device_id) { - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); - SSYNC(); - bfin_write_FIO_FLAG_C(PF1); - if (device_id == ETHERNET) - bfin_write_FIO_FLAG_S(PF0); - else if (device_id == FLASH) - bfin_write_FIO_FLAG_C(PF0); - else - printf("Unknown device to switch\n"); + gpio_request(GPIO_PF0, "eth_flash_swap"); + gpio_request(GPIO_PF1, "eth_flash_swap"); + gpio_direction_output(GPIO_PF0, device_id == ETHERNET); + gpio_direction_output(GPIO_PF1, 0); SSYNC(); } @@ -75,24 +69,23 @@ int misc_init_r(void) #define STATUS_LED_OFF 0 #define STATUS_LED_ON 1 +static int gpio_setup; + static void stamp_led_set(int LED1, int LED2, int LED3) { - bfin_write_FIO_INEN(bfin_read_FIO_INEN() & ~(PF2 | PF3 | PF4)); - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (PF2 | PF3 | PF4)); - - if (LED1 == STATUS_LED_OFF) - *pFIO_FLAG_S = PF2; - else - *pFIO_FLAG_C = PF2; - if (LED2 == STATUS_LED_OFF) - *pFIO_FLAG_S = PF3; - else - *pFIO_FLAG_C = PF3; - if (LED3 == STATUS_LED_OFF) - *pFIO_FLAG_S = PF4; - else - *pFIO_FLAG_C = PF4; - SSYNC(); + if (!gpio_setup) { + gpio_request(GPIO_PF2, "boot_progress"); + gpio_request(GPIO_PF3, "boot_progress"); + gpio_request(GPIO_PF4, "boot_progress"); + gpio_direction_output(GPIO_PF2, LED1); + gpio_direction_output(GPIO_PF3, LED2); + gpio_direction_output(GPIO_PF4, LED3); + gpio_setup = 1; + } else { + gpio_set_value(GPIO_PF2, LED1); + gpio_set_value(GPIO_PF3, LED2); + gpio_set_value(GPIO_PF4, LED3); + } } void show_boot_progress(int status) @@ -134,43 +127,6 @@ void show_boot_progress(int status) } #endif -#ifdef CONFIG_STATUS_LED -#include <status_led.h> - -static void set_led(int pf, int state) -{ - switch (state) { - case STATUS_LED_OFF: bfin_write_FIO_FLAG_S(pf); break; - case STATUS_LED_BLINKING: bfin_write_FIO_FLAG_T(pf); break; - case STATUS_LED_ON: bfin_write_FIO_FLAG_C(pf); break; - } -} - -static void set_leds(led_id_t mask, int state) -{ - if (mask & 0x1) set_led(PF2, state); - if (mask & 0x2) set_led(PF3, state); - if (mask & 0x4) set_led(PF4, state); -} - -void __led_init(led_id_t mask, int state) -{ - bfin_write_FIO_INEN(bfin_read_FIO_INEN() & ~(PF2 | PF3 | PF4)); - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (PF2 | PF3 | PF4)); -} - -void __led_set(led_id_t mask, int state) -{ - set_leds(mask, state); -} - -void __led_toggle(led_id_t mask) -{ - set_leds(mask, STATUS_LED_BLINKING); -} - -#endif - #ifdef CONFIG_SMC91111 int board_eth_init(bd_t *bis) { diff --git a/board/bf533-stamp/bf533-stamp.h b/board/bf533-stamp/bf533-stamp.h deleted file mode 100644 index ebd39c7..0000000 --- a/board/bf533-stamp/bf533-stamp.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * U-boot - stamp.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef __STAMP_H__ -#define __STAMP_H__ - -extern void init_Flags(void); - -extern volatile unsigned long *ambctl0; -extern volatile unsigned long *ambctl1; -extern volatile unsigned long *amgctl; - -/* Definitions used in Compact Flash Boot support */ -#define FIO_EDGE_CF_BITS 0x0000 -#define FIO_POLAR_CF_BITS 0x0000 -#define FIO_EDGE_BITS 0x1E0 -#define FIO_POLAR_BITS 0x160 - -/* Compact flash status bits in status register */ -#define CF_STAT_BITS 0x00000060 - -/* CF Flags used to switch between expansion and external - * memory banks - */ -#define CF_PF0 0x0001 -#define CF_PF1 0x0002 -#define CF_PF1_PF0 0x0003 - -#endif diff --git a/board/bf533-stamp/ide-cf.c b/board/bf533-stamp/ide-cf.c index 23e786b..3e4080e 100644 --- a/board/bf533-stamp/ide-cf.c +++ b/board/bf533-stamp/ide-cf.c @@ -11,7 +11,6 @@ #include <common.h> #include <config.h> #include <asm/blackfin.h> -#include "bf533-stamp.h" void cf_outb(unsigned char val, volatile unsigned char *addr) { @@ -66,6 +65,15 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) swap_to(FLASH); } +/* Definitions used in Compact Flash Boot support */ +#define FIO_EDGE_CF_BITS 0x0000 +#define FIO_POLAR_CF_BITS 0x0000 +#define FIO_EDGE_BITS 0x1E0 +#define FIO_POLAR_BITS 0x160 + +/* Compact flash status bits in status register */ +#define CF_STAT_BITS 0x00000060 + void cf_ide_init(void) { int i, cf_stat; diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile index f728e2c..4f8985b 100644 --- a/board/bf537-stamp/Makefile +++ b/board/bf537-stamp/Makefile @@ -29,9 +29,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS-y := $(BOARD).o cmd_bf537led.o +COBJS-y := $(BOARD).o COBJS-$(CONFIG_BFIN_IDE) += ide-cf.o -COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o COBJS-$(CONFIG_POST) += post.o post-memory.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index 3911be6..ec888d4 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -46,11 +46,8 @@ int checkboard(void) void board_reset(void) { /* workaround for weak pull ups on ssel */ - if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) { - bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF10); - bfin_write_PORTFIO_SET(PF10); - udelay(1); - } + if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) + bfin_reset_boot_spi_cs(GPIO_PF10); } #ifdef CONFIG_BFIN_MAC diff --git a/board/bf537-stamp/cmd_bf537led.c b/board/bf537-stamp/cmd_bf537led.c deleted file mode 100644 index 7d8f3ea..0000000 --- a/board/bf537-stamp/cmd_bf537led.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * U-boot - cmd_bf537led.c - * - * Copyright (C) 2006 Aaron Gage, Ocean Optics Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <config.h> -#include <command.h> -#include <asm/blackfin.h> -#include <asm/string.h> -#ifdef CONFIG_BF537_STAMP_LEDCMD - -/* Define the command usage in a reusable way */ -#define USAGE_LONG \ - "led <number> <action>\n" \ - " <number> - Index (0-5) of LED to change, or \"all\"\n" \ - " <action> - Must be one of:\n" \ - " on off toggle" - -/* Number of LEDs supported by the board */ -#define NUMBER_LEDS 6 -/* The BF537 stamp has 6 LEDs. This mask indicates that all should be lit. */ -#define LED_ALL_MASK 0x003F - -void show_cmd_usage(void); -void set_led_state(int index, int state); -void configure_GPIO_to_output(int index); - -/* Map of LEDs according to their GPIO ports. This can be rearranged or - * otherwise changed to account for different GPIO configurations. - */ -int led_ports[] = { PF6, PF7, PF8, PF9, PF10, PF11 }; - -#define ACTION_TOGGLE -1 -#define ACTION_OFF 0 -#define ACTION_ON 1 - -#define LED_STATE_OFF 0 -#define LED_STATE_ON 1 - -/* This is a trivial atoi implementation since we don't have one available */ -int atoi(char *string) -{ - int length; - int retval = 0; - int i; - int sign = 1; - - length = strlen(string); - for (i = 0; i < length; i++) { - if (0 == i && string[0] == '-') { - sign = -1; - continue; - } - if (string[i] > '9' || string[i] < '0') { - break; - } - retval *= 10; - retval += string[i] - '0'; - } - retval *= sign; - return retval; -} - -int do_bf537led(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - int led_mask = 0; - int led_current_state = 0; - int action = ACTION_OFF; - int temp; - - if (3 != argc) { - /* Not enough arguments, so just show usage information */ - show_cmd_usage(); - return 1; - } - - if (strcmp(argv[1], "all") == 0) { - led_mask = LED_ALL_MASK; - } else { - temp = atoi(argv[1]); - if (temp < 0 || temp >= NUMBER_LEDS) { - printf("Invalid LED number [%s]\n", argv[1]); - show_cmd_usage(); - return 2; - } - led_mask |= (1 << temp); - } - - if (strcmp(argv[2], "off") == 0) { - action = ACTION_OFF; - } else if (strcmp(argv[2], "on") == 0) { - action = ACTION_ON; - } else if (strcmp(argv[2], "toggle") == 0) { - action = ACTION_TOGGLE; - } else { - printf("Invalid action [%s]\n", argv[2]); - show_cmd_usage(); - return 3; - } - - for (temp = 0; temp < NUMBER_LEDS; temp++) { - if ((led_mask & (1 << temp)) > 0) { - /* - * It is possible that the user has wired one of PF6-PF11 to - * something other than an LED, so this will only change a pin - * to output if the user has indicated a state change. This may - * happen a lot, but this way is safer than just setting all pins - * to output. - */ - configure_GPIO_to_output(temp); - - led_current_state = - ((*pPORTFIO & led_ports[temp]) > - 0) ? LED_STATE_ON : LED_STATE_OFF; - /* - printf("LED state for index %d (%x) is %d\n", temp, led_ports[temp], - led_current_state); - printf("*pPORTFIO is %x\n", *pPORTFIO); - */ - if (ACTION_ON == action - || (ACTION_TOGGLE == action - && 0 == led_current_state)) { - printf("Turning LED %d on\n", temp); - set_led_state(temp, LED_STATE_ON); - } else { - printf("Turning LED %d off\n", temp); - set_led_state(temp, LED_STATE_OFF); - } - } - } - - return 0; -} - -/* - * The GPIO pins that go to the LEDs on the BF537 stamp must be configured - * as output. This function simply configures them that way. This could - * be done to all of the GPIO lines at once, but if a user is using a - * custom board, this will try to be nice and only change the GPIO lines - * that the user specifically names. - */ -void configure_GPIO_to_output(int index) -{ - int port; - - port = led_ports[index]; - - /* Clear the Port F Function Enable Register */ - *pPORTF_FER &= ~port; - /* Set the Port F I/O direction register */ - *pPORTFIO_DIR |= port; - /* Clear the Port F I/O Input Enable Register */ - *pPORTFIO_INEN &= ~port; -} - -/* Enforce the given state on the GPIO line for the indicated LED */ -void set_led_state(int index, int state) -{ - int port; - - port = led_ports[index]; - - if (LED_STATE_OFF == state) { - /* Clear the bit to turn off the LED */ - *pPORTFIO &= ~port; - } else { - /* Set the bit to turn on the LED */ - *pPORTFIO |= port; - } -} - -/* Display usage information */ -void show_cmd_usage() -{ - printf("Usage:\n%s\n", USAGE_LONG); -} - -/* Register information for u-boot to find this command */ -U_BOOT_CMD(led, 3, 1, do_bf537led, - "Control BF537 stamp LEDs", USAGE_LONG); - -#endif diff --git a/board/bf537-stamp/spi_flash.c b/board/bf537-stamp/spi_flash.c deleted file mode 100644 index 7b753ad..0000000 --- a/board/bf537-stamp/spi_flash.c +++ /dev/null @@ -1,996 +0,0 @@ -/* - * SPI flash driver - * - * Enter bugs at http://blackfin.uclinux.org/ - * - * Copyright (c) 2005-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -/* Configuration options: - * CONFIG_SPI_BAUD - value to load into SPI_BAUD (divisor of SCLK to get SPI CLK) - * CONFIG_SPI_FLASH_SLOW_READ - force usage of the slower read - * WARNING: make sure your SCLK + SPI_BAUD is slow enough - */ - -#include <common.h> -#include <malloc.h> -#include <asm/io.h> -#include <asm/mach-common/bits/spi.h> -#include <asm/mach-common/bits/dma.h> - -/* Forcibly phase out these */ -#ifdef CONFIG_SPI_FLASH_NUM_SECTORS -# error do not set CONFIG_SPI_FLASH_NUM_SECTORS -#endif -#ifdef CONFIG_SPI_FLASH_SECTOR_SIZE -# error do not set CONFIG_SPI_FLASH_SECTOR_SIZE -#endif - -#if defined(CONFIG_SPI) - -struct flash_info { - char *name; - uint16_t id; - uint16_t ext_id; - unsigned sector_size; - unsigned num_sectors; -}; - -/* SPI Speeds: 50 MHz / 33 MHz */ -static struct flash_info flash_spansion_serial_flash[] = { - { "S25FL016", 0x0215, 0, 64 * 1024, 32 }, - { "S25FL032", 0x0216, 0, 64 * 1024, 64 }, - { "S25FL064", 0x0217, 0, 64 * 1024, 128 }, - { "S25FL128-00", 0x2018, 0x0301, 64 * 1024, 256 }, /* Package marking FL128PIF */ - { "S25FL128-01", 0x2018, 0x0300, 128 * 1024, 64 }, /* Package marking FL128PIFL */ - { NULL, 0, 0, 0, 0 } -}; - -/* SPI Speeds: 50 MHz / 20 MHz */ -static struct flash_info flash_st_serial_flash[] = { - { "m25p05", 0x2010, 0, 32 * 1024, 2 }, - { "m25p10", 0x2011, 0, 32 * 1024, 4 }, - { "m25p20", 0x2012, 0, 64 * 1024, 4 }, - { "m25p40", 0x2013, 0, 64 * 1024, 8 }, - { "m25p80", 0x20FF, 0, 64 * 1024, 16 }, - { "m25p16", 0x2015, 0, 64 * 1024, 32 }, - { "m25p32", 0x2016, 0, 64 * 1024, 64 }, - { "m25p64", 0x2017, 0, 64 * 1024, 128 }, - { "m25p128", 0x2018, 0, 256 * 1024, 64 }, - { NULL, 0, 0, 0, 0 } -}; - -/* SPI Speeds: 20 MHz / 40 MHz */ -static struct flash_info flash_sst_serial_flash[] = { - { "SST25WF512", 0x2501, 0, 4 * 1024, 128 }, - { "SST25WF010", 0x2502, 0, 4 * 1024, 256 }, - { "SST25WF020", 0x2503, 0, 4 * 1024, 512 }, - { "SST25WF040", 0x2504, 0, 4 * 1024, 1024 }, - { NULL, 0, 0, 0, 0 } -}; - -/* SPI Speeds: 66 MHz / 33 MHz */ -static struct flash_info flash_atmel_dataflash[] = { - { "AT45DB011x", 0x0c, 0, 264, 512 }, - { "AT45DB021x", 0x14, 0, 264, 1025 }, - { "AT45DB041x", 0x1c, 0, 264, 2048 }, - { "AT45DB081x", 0x24, 0, 264, 4096 }, - { "AT45DB161x", 0x2c, 0, 528, 4096 }, - { "AT45DB321x", 0x34, 0, 528, 8192 }, - { "AT45DB642x", 0x3c, 0, 1056, 8192 }, - { NULL, 0, 0, 0, 0 } -}; - -/* SPI Speed: 50 MHz / 25 MHz or 40 MHz / 20 MHz */ -static struct flash_info flash_winbond_serial_flash[] = { - { "W25X10", 0x3011, 0, 16 * 256, 32 }, - { "W25X20", 0x3012, 0, 16 * 256, 64 }, - { "W25X40", 0x3013, 0, 16 * 256, 128 }, - { "W25X80", 0x3014, 0, 16 * 256, 256 }, - { "W25P80", 0x2014, 0, 256 * 256, 16 }, - { "W25P16", 0x2015, 0, 256 * 256, 32 }, - { NULL, 0, 0, 0, 0 } -}; - -struct flash_ops { - uint8_t read, write, erase, status; -}; - -#ifdef CONFIG_SPI_FLASH_SLOW_READ -# define OP_READ 0x03 -#else -# define OP_READ 0x0B -#endif -static struct flash_ops flash_st_ops = { - .read = OP_READ, - .write = 0x02, - .erase = 0xD8, - .status = 0x05, -}; - -static struct flash_ops flash_sst_ops = { - .read = OP_READ, - .write = 0x02, - .erase = 0x20, - .status = 0x05, -}; - -static struct flash_ops flash_atmel_ops = { - .read = OP_READ, - .write = 0x82, - .erase = 0x81, - .status = 0xD7, -}; - -static struct flash_ops flash_winbond_ops = { - .read = OP_READ, - .write = 0x02, - .erase = 0x20, - .status = 0x05, -}; - -struct manufacturer_info { - const char *name; - uint8_t id; - struct flash_info *flashes; - struct flash_ops *ops; -}; - -static struct { - struct manufacturer_info *manufacturer; - struct flash_info *flash; - struct flash_ops *ops; - uint8_t manufacturer_id, device_id1, device_id2, device_extid1, device_extid2; - unsigned int write_length; - unsigned long sector_size, num_sectors; -} flash; - -enum { - JED_MANU_SPANSION = 0x01, - JED_MANU_ST = 0x20, - JED_MANU_SST = 0xBF, - JED_MANU_ATMEL = 0x1F, - JED_MANU_WINBOND = 0xEF, -}; - -static struct manufacturer_info flash_manufacturers[] = { - { - .name = "Spansion", - .id = JED_MANU_SPANSION, - .flashes = flash_spansion_serial_flash, - .ops = &flash_st_ops, - }, - { - .name = "ST", - .id = JED_MANU_ST, - .flashes = flash_st_serial_flash, - .ops = &flash_st_ops, - }, - { - .name = "SST", - .id = JED_MANU_SST, - .flashes = flash_sst_serial_flash, - .ops = &flash_sst_ops, - }, - { - .name = "Atmel", - .id = JED_MANU_ATMEL, - .flashes = flash_atmel_dataflash, - .ops = &flash_atmel_ops, - }, - { - .name = "Winbond", - .id = JED_MANU_WINBOND, - .flashes = flash_winbond_serial_flash, - .ops = &flash_winbond_ops, - }, -}; - -#define TIMEOUT 5000 /* timeout of 5 seconds */ - -/* If part has multiple SPI flashes, assume SPI0 as that is - * the one we can boot off of ... - */ -#ifndef pSPI_CTL -# define pSPI_CTL pSPI0_CTL -# define pSPI_BAUD pSPI0_BAUD -# define pSPI_FLG pSPI0_FLG -# define pSPI_RDBR pSPI0_RDBR -# define pSPI_STAT pSPI0_STAT -# define pSPI_TDBR pSPI0_TDBR -#endif - -/* Default to the SPI SSEL that we boot off of: - * BF54x, BF537, (everything new?): SSEL1 - * BF51x, BF533, BF561: SSEL2 - */ -#ifndef CONFIG_SPI_FLASH_SSEL -# define CONFIG_SPI_FLASH_SSEL BFIN_BOOT_SPI_SSEL -#endif -#define SSEL_MASK (1 << CONFIG_SPI_FLASH_SSEL) - -static void SPI_INIT(void) -{ - /* [#3541] This delay appears to be necessary, but not sure - * exactly why as the history behind it is non-existant. - */ - *pSPI_CTL = 0; - udelay(CONFIG_CCLK_HZ / 25000000); - - /* enable SPI pins: SSEL, MOSI, MISO, SCK */ -#ifdef __ADSPBF54x__ - *pPORTE_FER |= (PE0 | PE1 | PE2 | PE4); -#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) - *pPORTF_FER |= (PF10 | PF11 | PF12 | PF13); -#elif defined(__ADSPBF52x__) - bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_3); - bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG1 | PG2 | PG3 | PG4); -#elif defined(__ADSPBF51x__) - bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_7_MASK) | PORT_x_MUX_7_FUNC_1); - bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG12 | PG13 | PG14 | PG15); -#endif - - /* initate communication upon write of TDBR */ - *pSPI_CTL = (SPE | MSTR | CPHA | CPOL | TDBR_CORE); - *pSPI_BAUD = CONFIG_SPI_BAUD; -} - -static void SPI_DEINIT(void) -{ - *pSPI_CTL = 0; - *pSPI_BAUD = 0; - SSYNC(); -} - -static void SPI_ON(void) -{ - /* toggle SSEL to reset the device so it'll take a new command */ - *pSPI_FLG = 0xFF00 | SSEL_MASK; - SSYNC(); - - *pSPI_FLG = ((0xFF & ~SSEL_MASK) << 8) | SSEL_MASK; - SSYNC(); -} - -static void SPI_OFF(void) -{ - /* put SPI settings back to reset state */ - *pSPI_FLG = 0xFF00; - SSYNC(); -} - -static uint8_t spi_write_read_byte(uint8_t transmit) -{ - *pSPI_TDBR = transmit; - SSYNC(); - - while ((*pSPI_STAT & TXS)) - if (ctrlc()) - break; - while (!(*pSPI_STAT & SPIF)) - if (ctrlc()) - break; - while (!(*pSPI_STAT & RXS)) - if (ctrlc()) - break; - - /* Read dummy to empty the receive register */ - return *pSPI_RDBR; -} - -static uint8_t read_status_register(void) -{ - uint8_t status_register; - - /* send instruction to read status register */ - SPI_ON(); - spi_write_read_byte(flash.ops->status); - /* send dummy to receive the status register */ - status_register = spi_write_read_byte(0); - SPI_OFF(); - - return status_register; -} - -static int wait_for_ready_status(void) -{ - ulong start = get_timer(0); - - while (get_timer(0) - start < TIMEOUT) { - switch (flash.manufacturer_id) { - case JED_MANU_SPANSION: - case JED_MANU_ST: - case JED_MANU_SST: - case JED_MANU_WINBOND: - if (!(read_status_register() & 0x01)) - return 0; - break; - - case JED_MANU_ATMEL: - if (read_status_register() & 0x80) - return 0; - break; - } - - if (ctrlc()) { - puts("\nAbort\n"); - return -1; - } - } - - puts("Timeout\n"); - return -1; -} - -static int enable_writing(void) -{ - ulong start; - - if (flash.manufacturer_id == JED_MANU_ATMEL) - return 0; - - /* A write enable instruction must previously have been executed */ - SPI_ON(); - spi_write_read_byte(0x06); - SPI_OFF(); - - /* The status register will be polled to check the write enable latch "WREN" */ - start = get_timer(0); - while (get_timer(0) - start < TIMEOUT) { - if (read_status_register() & 0x02) - return 0; - - if (ctrlc()) { - puts("\nAbort\n"); - return -1; - } - } - - puts("Timeout\n"); - return -1; -} - -static void write_status_register(uint8_t val) -{ - if (flash.manufacturer_id != JED_MANU_SST) - hang(); - - if (enable_writing()) - return; - - /* send instruction to write status register */ - SPI_ON(); - spi_write_read_byte(0x01); - /* and clear it! */ - spi_write_read_byte(val); - SPI_OFF(); -} - -/* Request and read the manufacturer and device id of parts which - * are compatible with the JEDEC standard (JEP106) and use that to - * setup other operating conditions. - */ -static int spi_detect_part(void) -{ - uint16_t dev_id, dev_extid; - size_t i; - - static char called_init; - if (called_init) - return 0; - -#ifdef CONFIG_SPI_FLASH_M25P80 - flash.manufacturer_id = JED_MANU_ST; - flash.device_id1 = 0x20; - flash.device_id2 = 0xFF; -#else - SPI_ON(); - - /* Send the request for the part identification */ - spi_write_read_byte(0x9F); - - /* Now read in the manufacturer id bytes */ - do { - flash.manufacturer_id = spi_write_read_byte(0); - if (flash.manufacturer_id == 0x7F) - puts("Warning: unhandled manufacturer continuation byte!\n"); - } while (flash.manufacturer_id == 0x7F); - - /* Now read in the first device id byte */ - flash.device_id1 = spi_write_read_byte(0); - - /* Now read in the second device id byte */ - flash.device_id2 = spi_write_read_byte(0); - - /* Read extended device ids */ - flash.device_extid1 = spi_write_read_byte(0); - flash.device_extid2 = spi_write_read_byte(0); - - SPI_OFF(); -#endif - - dev_id = (flash.device_id1 << 8) | flash.device_id2; - dev_extid = (flash.device_extid1 << 8) | flash.device_extid2; - - for (i = 0; i < ARRAY_SIZE(flash_manufacturers); ++i) { - if (flash.manufacturer_id == flash_manufacturers[i].id) - break; - } - if (i == ARRAY_SIZE(flash_manufacturers)) - goto unknown; - - flash.manufacturer = &flash_manufacturers[i]; - flash.ops = flash_manufacturers[i].ops; - - switch (flash.manufacturer_id) { - case JED_MANU_SPANSION: - case JED_MANU_ST: - case JED_MANU_SST: - case JED_MANU_WINBOND: - for (i = 0; flash.manufacturer->flashes[i].name; ++i) { - if (dev_id == flash.manufacturer->flashes[i].id && - (flash.manufacturer->flashes[i].ext_id == 0 || - flash.manufacturer->flashes[i].ext_id == dev_extid)) - break; - } - if (!flash.manufacturer->flashes[i].name) - goto unknown; - - flash.flash = &flash.manufacturer->flashes[i]; - flash.sector_size = flash.flash->sector_size; - flash.num_sectors = flash.flash->num_sectors; - - if (flash.manufacturer_id == JED_MANU_SST) - flash.write_length = 1; /* pwnt :( */ - else - flash.write_length = 256; - break; - - case JED_MANU_ATMEL: { - uint8_t status = read_status_register(); - - for (i = 0; flash.manufacturer->flashes[i].name; ++i) { - if ((status & 0x3c) == flash.manufacturer->flashes[i].id) - break; - } - if (!flash.manufacturer->flashes[i].name) - goto unknown; - - flash.flash = &flash.manufacturer->flashes[i]; - flash.sector_size = flash.flash->sector_size; - flash.num_sectors = flash.flash->num_sectors; - - /* see if flash is in "power of 2" mode */ - if (status & 0x1) - flash.sector_size &= ~(1 << (ffs(flash.sector_size) - 1)); - - flash.write_length = flash.sector_size; - break; - } - } - - /* the SST parts power up with software protection enabled by default */ - if (flash.manufacturer_id == JED_MANU_SST) - write_status_register(0); - - called_init = 1; - return 0; - - unknown: - printf("Unknown SPI device: 0x%02X 0x%02X 0x%02X\n", - flash.manufacturer_id, flash.device_id1, flash.device_id2); - return 1; -} - -/* - * Function: spi_init_f - * Description: Init SPI-Controller (ROM part) - * return: --- - */ -void spi_init_f(void) -{ -} - -/* - * Function: spi_init_r - * Description: Init SPI-Controller (RAM part) - - * The malloc engine is ready and we can move our buffers to - * normal RAM - * return: --- - */ -void spi_init_r(void) -{ -#if defined(CONFIG_POST) && (CONFIG_POST & CONFIG_SYS_POST_SPI) - /* Our testing strategy here is pretty basic: - * - fill src memory with an 8-bit pattern - * - write the src memory to the SPI flash - * - read the SPI flash into the dst memory - * - compare src and dst memory regions - * - repeat a few times - * The variations we test for: - * - change the 8-bit pattern a bit - * - change the read/write block size so we know: - * - writes smaller/equal/larger than the buffer work - * - writes smaller/equal/larger than the sector work - * - change the SPI offsets so we know: - * - writing partial sectors works - */ - uint8_t *mem_src, *mem_dst; - size_t i, c, l, o; - size_t test_count, errors; - uint8_t pattern; - - SPI_INIT(); - - if (spi_detect_part()) - goto out; - eeprom_info(); - - ulong lengths[] = { - flash.write_length, - flash.write_length * 2, - flash.write_length / 2, - flash.sector_size, - flash.sector_size * 2, - flash.sector_size / 2 - }; - ulong offsets[] = { - 0, - flash.write_length, - flash.write_length * 2, - flash.write_length / 2, - flash.write_length / 4, - flash.sector_size, - flash.sector_size * 2, - flash.sector_size / 2, - flash.sector_size / 4, - }; - - /* the exact addresses are arbitrary ... they just need to not overlap */ - mem_src = (void *)(0); - mem_dst = (void *)(max(flash.write_length, flash.sector_size) * 2); - - test_count = 0; - errors = 0; - pattern = 0x00; - - for (i = 0; i < 16; ++i) { /* 16 = 8 bits * 2 iterations */ - for (l = 0; l < ARRAY_SIZE(lengths); ++l) { - for (o = 0; o < ARRAY_SIZE(offsets); ++o) { - ulong len = lengths[l]; - ulong off = offsets[o]; - - printf("Testing pattern 0x%02X of length %5lu and offset %5lu: ", pattern, len, off); - - /* setup the source memory region */ - memset(mem_src, pattern, len); - - test_count += 4; - for (c = 0; c < 4; ++c) { /* 4 is just a random repeat count */ - if (ctrlc()) { - puts("\nAbort\n"); - goto out; - } - - /* make sure background fill pattern != pattern */ - memset(mem_dst, pattern ^ 0xFF, len); - - /* write out the source memory and then read it back and compare */ - eeprom_write(0, off, mem_src, len); - eeprom_read(0, off, mem_dst, len); - - if (memcmp(mem_src, mem_dst, len)) { - for (c = 0; c < len; ++c) - if (mem_src[c] != mem_dst[c]) - break; - printf(" FAIL @ offset %u, skipping repeats ", c); - ++errors; - break; - } - - /* XXX: should shrink write region here to test with - * leading/trailing canaries so we know surrounding - * bytes don't get screwed. - */ - } - puts("\n"); - } - } - - /* invert the pattern every other run and shift out bits slowly */ - pattern ^= 0xFF; - if (i % 2) - pattern = (pattern | 0x01) << 1; - } - - if (errors) - printf("SPI FAIL: Out of %i tests, there were %i errors ;(\n", test_count, errors); - else - printf("SPI PASS: %i tests worked!\n", test_count); - - out: - SPI_DEINIT(); - -#endif -} - -static void transmit_address(uint32_t addr) -{ - /* Send the highest byte of the 24 bit address at first */ - spi_write_read_byte(addr >> 16); - /* Send the middle byte of the 24 bit address at second */ - spi_write_read_byte(addr >> 8); - /* Send the lowest byte of the 24 bit address finally */ - spi_write_read_byte(addr); -} - -/* - * Read a value from flash for verify purpose - * Inputs: unsigned long ulStart - holds the SPI start address - * int pnData - pointer to store value read from flash - * long lCount - number of elements to read - */ -#ifdef CONFIG_SPI_READFLASH_NODMA -static int read_flash(unsigned long address, long count, uchar *buffer) -{ - size_t i, j; - - /* Send the read command to SPI device */ - SPI_ON(); - spi_write_read_byte(flash.ops->read); - transmit_address(address); - -#ifndef CONFIG_SPI_FLASH_SLOW_READ - /* Send dummy byte when doing SPI fast reads */ - spi_write_read_byte(0); -#endif - - /* After the SPI device address has been placed on the MOSI pin the data can be */ - /* received on the MISO pin. */ - j = flash.sector_size << 1; - for (i = 1; i <= count; ++i) { - *buffer++ = spi_write_read_byte(0); - if (!j--) { - puts("."); - j = flash.sector_size; - } - } - - SPI_OFF(); - - return 0; -} -#else - -#ifdef __ADSPBF54x__ -#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA4_IRQ_STATUS -#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA4_IRQ_STATUS -#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA4_CURR_DESC_PTR -#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA4_CONFIG -#elif defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) || \ - defined(__ADSPBF538__) || defined(__ADSPBF539__) -#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA5_IRQ_STATUS -#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA5_IRQ_STATUS -#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA5_CURR_DESC_PTR -#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA5_CONFIG -#elif defined(__ADSPBF561__) -#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA16_IRQ_STATUS -#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA16_IRQ_STATUS -#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA16_CURR_DESC_PTR -#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA16_CONFIG -#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) || \ - defined(__ADSPBF52x__) || defined(__ADSPBF51x__) -#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA7_IRQ_STATUS -#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA7_IRQ_STATUS -#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA7_CURR_DESC_PTR -#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA7_CONFIG -#else -#error "Please provide SPI DMA channel defines" -#endif - -struct dmadesc_array { - unsigned long start_addr; - unsigned short cfg; - unsigned short x_count; - short x_modify; - unsigned short y_count; - short y_modify; -} __attribute__((packed)); - -/* - * Read a value from flash for verify purpose - * Inputs: unsigned long ulStart - holds the SPI start address - * int pnData - pointer to store value read from flash - * long lCount - number of elements to read - */ - -static int read_flash(unsigned long address, long count, uchar *buffer) -{ - unsigned int ndsize; - struct dmadesc_array dma[2]; - /* Send the read command to SPI device */ - - if (!count) - return 0; - - dma[0].start_addr = (unsigned long)buffer; - dma[0].x_modify = 1; - if (count <= 65536) { - blackfin_dcache_flush_invalidate_range(buffer, buffer + count); - ndsize = NDSIZE_5; - dma[0].cfg = NDSIZE_0 | WNR | WDSIZE_8 | FLOW_STOP | DMAEN | DI_EN; - dma[0].x_count = count; - } else { - blackfin_dcache_flush_invalidate_range(buffer, buffer + 65536 - 1); - ndsize = NDSIZE_7; - dma[0].cfg = NDSIZE_5 | WNR | WDSIZE_8 | FLOW_ARRAY | DMAEN | DMA2D; - dma[0].x_count = 0; /* 2^16 */ - dma[0].y_count = count >> 16; /* count / 2^16 */ - dma[0].y_modify = 1; - dma[1].start_addr = (unsigned long)(buffer + (count & ~0xFFFF)); - dma[1].cfg = NDSIZE_0 | WNR | WDSIZE_8 | FLOW_STOP | DMAEN | DI_EN; - dma[1].x_count = count & 0xFFFF; /* count % 2^16 */ - dma[1].x_modify = 1; - } - - bfin_write_DMA_SPI_CONFIG(0); - bfin_write_DMA_SPI_IRQ_STATUS(DMA_DONE | DMA_ERR); - bfin_write_DMA_SPI_CURR_DESC_PTR(dma); - - SPI_ON(); - - spi_write_read_byte(flash.ops->read); - transmit_address(address); - -#ifndef CONFIG_SPI_FLASH_SLOW_READ - /* Send dummy byte when doing SPI fast reads */ - spi_write_read_byte(0); -#endif - - bfin_write_DMA_SPI_CONFIG(ndsize | FLOW_ARRAY | DMAEN); - *pSPI_CTL = (MSTR | CPHA | CPOL | RDBR_DMA | SPE | SZ); - SSYNC(); - - /* - * We already invalidated the first 64k, - * now while we just wait invalidate the remaining part. - * Its not likely that the DMA is going to overtake - */ - if (count > 65536) - blackfin_dcache_flush_invalidate_range(buffer + 65536, - buffer + count); - - while (!(bfin_read_DMA_SPI_IRQ_STATUS() & DMA_DONE)) - if (ctrlc()) - break; - - SPI_OFF(); - - *pSPI_CTL = 0; - - bfin_write_DMA_SPI_CONFIG(0); - - *pSPI_CTL = (SPE | MSTR | CPHA | CPOL | TDBR_CORE); - - return 0; -} -#endif - -static long address_to_sector(unsigned long address) -{ - if (address > (flash.num_sectors * flash.sector_size) - 1) - return -1; - return address / flash.sector_size; -} - -static int erase_sector(int address) -{ - /* sector gets checked in higher function, so assume it's valid - * here and figure out the offset of the sector in flash - */ - if (enable_writing()) - return -1; - - /* - * Send the erase block command to the flash followed by the 24 address - * to point to the start of a sector - */ - SPI_ON(); - spi_write_read_byte(flash.ops->erase); - transmit_address(address); - SPI_OFF(); - - return wait_for_ready_status(); -} - -/* Write [count] bytes out of [buffer] into the given SPI [address] */ -static long write_flash(unsigned long address, long count, uchar *buffer) -{ - long i, write_buffer_size; - - if (enable_writing()) - return -1; - - /* Send write command followed by the 24 bit address */ - SPI_ON(); - spi_write_read_byte(flash.ops->write); - transmit_address(address); - - /* Shoot out a single write buffer */ - write_buffer_size = min(count, flash.write_length); - for (i = 0; i < write_buffer_size; ++i) - spi_write_read_byte(buffer[i]); - - SPI_OFF(); - - /* Wait for the flash to do its thing */ - if (wait_for_ready_status()) { - puts("SPI Program Time out! "); - return -1; - } - - return i; -} - -/* Write [count] bytes out of [buffer] into the given SPI [address] */ -static int write_sector(unsigned long address, long count, uchar *buffer) -{ - long write_cnt; - - while (count != 0) { - write_cnt = write_flash(address, count, buffer); - if (write_cnt == -1) - return -1; - - /* Now that we've sent some bytes out to the flash, update - * our counters a bit - */ - count -= write_cnt; - address += write_cnt; - buffer += write_cnt; - } - - /* return the appropriate error code */ - return 0; -} - -/* - * Function: spi_write - */ -ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) -{ - unsigned long offset; - int start_sector, end_sector; - int start_byte, end_byte; - uchar *temp = NULL; - int num, ret = 0; - - SPI_INIT(); - - if (spi_detect_part()) - goto out; - - offset = addr[0] << 16 | addr[1] << 8 | addr[2]; - - /* Get the start block number */ - start_sector = address_to_sector(offset); - if (start_sector == -1) { - puts("Invalid sector! "); - goto out; - } - end_sector = address_to_sector(offset + len - 1); - if (end_sector == -1) { - puts("Invalid sector! "); - goto out; - } - - /* Since flashes operate in sector units but the eeprom command - * operates as a continuous stream of bytes, we need to emulate - * the eeprom behavior. So here we read in the sector, overlay - * any bytes we're actually modifying, erase the sector, and - * then write back out the new sector. - */ - temp = malloc(flash.sector_size); - if (!temp) { - puts("Malloc for sector failed! "); - goto out; - } - - for (num = start_sector; num <= end_sector; num++) { - unsigned long address = num * flash.sector_size; - - /* XXX: should add an optimization when spanning sectors: - * No point in reading in a sector if we're going to be - * clobbering the whole thing. Need to also add a test - * case to make sure the optimization is correct. - */ - if (read_flash(address, flash.sector_size, temp)) { - puts("Read sector failed! "); - len = 0; - break; - } - - start_byte = max(address, offset); - end_byte = address + flash.sector_size - 1; - if (end_byte > (offset + len)) - end_byte = (offset + len - 1); - - memcpy(temp + start_byte - address, - buffer + start_byte - offset, - end_byte - start_byte + 1); - - if (erase_sector(address)) { - puts("Erase sector failed! "); - goto out; - } - - if (write_sector(address, flash.sector_size, temp)) { - puts("Write sector failed! "); - goto out; - } - - puts("."); - } - - ret = len; - - out: - free(temp); - - SPI_DEINIT(); - - return ret; -} - -/* - * Function: spi_read - */ -ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) -{ - unsigned long offset; - - SPI_INIT(); - - if (spi_detect_part()) - len = 0; - else { - offset = addr[0] << 16 | addr[1] << 8 | addr[2]; - read_flash(offset, len, buffer); - } - - SPI_DEINIT(); - - return len; -} - -/* - * Spit out some useful information about the SPI eeprom - */ -int eeprom_info(void) -{ - int ret = 0; - - SPI_INIT(); - - if (spi_detect_part()) - ret = 1; - else - printf("SPI Device: %s 0x%02X (%s) 0x%02X 0x%02X\n" - "Parameters: num sectors = %lu, sector size = %lu, write size = %i\n" - "Flash Size: %lu mbit (%lu mbyte)\n" - "Status: 0x%02X\n", - flash.flash->name, flash.manufacturer_id, flash.manufacturer->name, - flash.device_id1, flash.device_id2, flash.num_sectors, - flash.sector_size, flash.write_length, - (flash.num_sectors * flash.sector_size) >> 17, - (flash.num_sectors * flash.sector_size) >> 20, - read_status_register()); - - SPI_DEINIT(); - - return ret; -} - -#endif diff --git a/board/bf548-ezkit/bf548-ezkit.c b/board/bf548-ezkit/bf548-ezkit.c index 65fb81a..cb9ee86 100644 --- a/board/bf548-ezkit/bf548-ezkit.c +++ b/board/bf548-ezkit/bf548-ezkit.c @@ -7,10 +7,12 @@ */ #include <common.h> -#include <netdev.h> #include <config.h> #include <command.h> +#include <netdev.h> #include <asm/blackfin.h> +#include <asm/gpio.h> +#include <asm/portmux.h> #include <asm/sdh.h> DECLARE_GLOBAL_DATA_PTR; @@ -24,53 +26,13 @@ int checkboard(void) int board_early_init_f(void) { - /* Port H: PH8 - PH13 == A4 - A9 - * address lines of the parallel asynchronous memory interface - */ - - /************************************************ - * configure GPIO * - * set port H function enable register * - * configure PH8-PH13 as peripheral (not GPIO) * - *************************************************/ - bfin_write_PORTH_FER(0x3F03); - - /************************************************ - * set port H MUX to configure PH8-PH13 * - * 1st Function (MUX = 00) (bits 16-27 == 0) * - * Set to address signals A4-A9 * - *************************************************/ - bfin_write_PORTH_MUX(0); - - /************************************************ - * set port H direction register * - * enable PH8-PH13 as outputs * - *************************************************/ - bfin_write_PORTH_DIR_SET(0x3F00); - - /* Port I: PI0 - PH14 == A10 - A24 - * address lines of the parallel asynchronous memory interface - */ - - /************************************************ - * set port I function enable register * - * configure PI0-PI14 as peripheral (not GPIO) * - *************************************************/ - bfin_write_PORTI_FER(0x7fff); - - /************************************************** - * set PORT I MUX to configure PI14-PI0 as * - * 1st Function (MUX=00) - address signals A10-A24 * - ***************************************************/ - bfin_write_PORTI_MUX(0); - - /**************************************** - * set PORT I direction register * - * enable PI0 - PI14 as outputs * - *****************************************/ - bfin_write_PORTI_DIR_SET(0x7fff); - - return 0; + /* Set async addr lines as peripheral */ + const unsigned short pins[] = { + P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12, + P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, + P_A21, P_A22, P_A23, P_A24, 0 + }; + return peripheral_request_list(pins, "async"); } #ifdef CONFIG_SMC911X @@ -96,9 +58,7 @@ void board_musb_init(void) * be low for device mode and high for host mode. We set it high * here because we are in host mode. */ - bfin_write_PORTE_FER(bfin_read_PORTE_FER() & ~PE7); - bfin_write_PORTE_DIR_SET(PE7); - bfin_write_PORTE_SET(PE7); - SSYNC(); + gpio_request(GPIO_PE7, "musb-vbus"); + gpio_direction_output(GPIO_PE7, 1); } #endif diff --git a/board/bf548-ezkit/video.c b/board/bf548-ezkit/video.c index 10b08e2..af3d58b 100644 --- a/board/bf548-ezkit/video.c +++ b/board/bf548-ezkit/video.c @@ -11,6 +11,8 @@ #include <config.h> #include <malloc.h> #include <asm/blackfin.h> +#include <asm/gpio.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/dma.h> #include <i2c.h> #include <linux/types.h> @@ -173,22 +175,21 @@ void Init_DMA(void *dst) void Init_Ports(void) { - *pPORTF_MUX = 0x00000000; - *pPORTF_FER |= 0xFFFF; /* PPI0..15 */ - - *pPORTG_MUX &= ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK); - *pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4; /* CLK, FS1, FS2, PPI16..17 */ - + const unsigned short pins[] = { + P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4, + P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9, + P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, + P_PPI0_D15, P_PPI0_D16, P_PPI0_D17, #if !defined(CONFIG_VIDEO_RGB666) - *pPORTD_MUX &= ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK); - *pPORTD_MUX |= (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 | PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4); - *pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5; /* PPI18..23 */ + P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, + P_PPI0_D23, #endif + P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0, + }; + peripheral_request_list(pins, "lcd"); - *pPORTE_FER &= ~PE3; /* DISP */ - *pPORTE_DIR_SET = PE3; - *pPORTE_SET = PE3; - + gpio_request(GPIO_PE3, "lcd-disp"); + gpio_direction_output(GPIO_PE3, 1); } void EnableDMA(void) diff --git a/board/blackstamp/blackstamp.c b/board/blackstamp/blackstamp.c index 6355c10..06d004a 100644 --- a/board/blackstamp/blackstamp.c +++ b/board/blackstamp/blackstamp.c @@ -13,7 +13,7 @@ #include <common.h> #include <netdev.h> -#include <asm/io.h> +#include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -27,14 +27,8 @@ int checkboard(void) #ifdef SHARED_RESOURCES void swap_to(int device_id) { - bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF0); - SSYNC(); - if (device_id == ETHERNET) - bfin_write_FIO_FLAG_S(PF0); - else if (device_id == FLASH) - bfin_write_FIO_FLAG_C(PF0); - else - printf("Unknown device to switch\n"); + gpio_request(GPIO_PF0, "eth_flash_swap"); + gpio_direction_output(GPIO_PF0, device_id == ETHERNET); SSYNC(); } #endif diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c b/board/calao/sbc35_a9g20/sbc35_a9g20.c index da34b40..9df45c0 100644 --- a/board/calao/sbc35_a9g20/sbc35_a9g20.c +++ b/board/calao/sbc35_a9g20/sbc35_a9g20.c @@ -177,13 +177,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/cm-bf527/Makefile b/board/cm-bf527/Makefile index c2cd244..bad018a 100644 --- a/board/cm-bf527/Makefile +++ b/board/cm-bf527/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS-y := $(BOARD).o gpio.o gpio_cfi_flash.o +COBJS-y := $(BOARD).o gpio_cfi_flash.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/cm-bf527/gpio.c b/board/cm-bf527/gpio.c deleted file mode 100644 index 7e0babe..0000000 --- a/board/cm-bf527/gpio.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Control GPIO pins on the fly - * - * Copyright (c) 2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <command.h> - -#include <asm/blackfin.h> - -int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc != 3) { - show_usage: - printf("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - /* parse the behavior */ - ulong port_cmd = 0; - switch (argv[1][0]) { - case 'i': break; - case 's': port_cmd = (PORTFIO_SET - PORTFIO); break; - case 'c': port_cmd = (PORTFIO_CLEAR - PORTFIO); break; - case 't': port_cmd = (PORTFIO_TOGGLE - PORTFIO); break; - default: goto show_usage; - } - - /* parse the pin with format: [p]<fgh><#> */ - const char *str_pin = argv[2]; - - /* grab the [p]<fgh> portion */ - ulong port_base; - if (*str_pin == 'p') ++str_pin; - switch (*str_pin) { - case 'f': port_base = PORTFIO; break; - case 'g': port_base = PORTGIO; break; - case 'h': port_base = PORTHIO; break; - default: goto show_usage; - } - - /* grab the <#> portion */ - ulong pin = simple_strtoul(str_pin+1, NULL, 10); - ulong pin_mask = (1 << pin); - if (pin > 15) - goto show_usage; - - /* finally, let's do it: set direction and exec command */ - switch (*str_pin) { - case 'f': bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~pin_mask); break; - case 'g': bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~pin_mask); break; - case 'h': bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~pin_mask); break; - } - - ulong port_dir = port_base + (PORTFIO_DIR - PORTFIO); - if (argv[1][0] == 'i') - bfin_write16(port_dir, bfin_read16(port_dir) & ~pin_mask); - else { - bfin_write16(port_dir, bfin_read16(port_dir) | pin_mask); - bfin_write16(port_base + port_cmd, pin_mask); - } - - printf("gpio: pin %li on port %c has been %c\n", pin, *str_pin, argv[1][0]); - - return 0; -} - -U_BOOT_CMD(gpio, 3, 0, do_gpio, - "gpio - set/clear/toggle gpio output pins\n", - "<s|c|t> <port><pin>\n" - " - set/clear/toggle the specified pin\n"); diff --git a/board/cm-bf527/gpio_cfi_flash.c b/board/cm-bf527/gpio_cfi_flash.c index 7167680..f8ccc07 100644 --- a/board/cm-bf527/gpio_cfi_flash.c +++ b/board/cm-bf527/gpio_cfi_flash.c @@ -8,12 +8,13 @@ #include <common.h> #include <asm/blackfin.h> +#include <asm/gpio.h> #include <asm/io.h> #include "gpio_cfi_flash.h" -#define GPIO_PIN_1 PH9 +#define GPIO_PIN_1 GPIO_PH9 #define GPIO_MASK_1 (1 << 21) -#define GPIO_PIN_2 PG11 +#define GPIO_PIN_2 GPIO_PG11 #define GPIO_MASK_2 (1 << 22) #define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2) @@ -21,16 +22,10 @@ void *gpio_cfi_flash_swizzle(void *vaddr) { unsigned long addr = (unsigned long)vaddr; - if (addr & GPIO_MASK_1) - bfin_write_PORTHIO_SET(GPIO_PIN_1); - else - bfin_write_PORTHIO_CLEAR(GPIO_PIN_1); + gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); #ifdef GPIO_MASK_2 - if (addr & GPIO_MASK_2) - bfin_write_PORTGIO_SET(GPIO_PIN_2); - else - bfin_write_PORTGIO_CLEAR(GPIO_PIN_2); + gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); #endif SSYNC(); @@ -57,7 +52,9 @@ MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ void gpio_cfi_flash_init(void) { - bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() | GPIO_PIN_1); - bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | GPIO_PIN_2); + gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); +#ifdef GPIO_MASK_2 + gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); +#endif gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); } diff --git a/board/cm-bf537e/Makefile b/board/cm-bf537e/Makefile index 3812ba1..bad018a 100644 --- a/board/cm-bf537e/Makefile +++ b/board/cm-bf537e/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS-y := $(BOARD).o flash.o gpio_cfi_flash.o +COBJS-y := $(BOARD).o gpio_cfi_flash.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/cm-bf537e/flash.c b/board/cm-bf537e/flash.c deleted file mode 100644 index a4c1ec0..0000000 --- a/board/cm-bf537e/flash.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * flash.c - helper commands for working with GPIO-assisted flash - * - * Copyright (c) 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <command.h> -#include <asm/blackfin.h> -#include "gpio_cfi_flash.h" - -int do_pf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong faddr = CONFIG_SYS_FLASH_BASE; - ushort data; - ulong dflg; - - if (argc > 1) { - dflg = simple_strtoul(argv[1], NULL, 16); - faddr |= (dflg << 21); - gpio_cfi_flash_swizzle((void *)faddr); - } else { - data = bfin_read_PORTFIO(); - printf("Port F data %04x (PF4:%i)\n", data, !!(data & PF4)); - } - - return 0; -} - -U_BOOT_CMD(pf, 3, 0, do_pf, - "set/clear PF4 GPIO flash bank switch\n", - "<pf4> - set PF4 GPIO pin state\n"); diff --git a/board/cm-bf537e/gpio_cfi_flash.c b/board/cm-bf537e/gpio_cfi_flash.c index a9e69cf..79ee844 100644 --- a/board/cm-bf537e/gpio_cfi_flash.c +++ b/board/cm-bf537e/gpio_cfi_flash.c @@ -8,10 +8,11 @@ #include <common.h> #include <asm/blackfin.h> +#include <asm/gpio.h> #include <asm/io.h> #include "gpio_cfi_flash.h" -#define GPIO_PIN_1 PF4 +#define GPIO_PIN_1 GPIO_PF4 #define GPIO_MASK_1 (1 << 21) #define GPIO_MASK (GPIO_MASK_1) @@ -19,16 +20,10 @@ void *gpio_cfi_flash_swizzle(void *vaddr) { unsigned long addr = (unsigned long)vaddr; - if (addr & GPIO_MASK_1) - bfin_write_PORTFIO_SET(GPIO_PIN_1); - else - bfin_write_PORTFIO_CLEAR(GPIO_PIN_1); + gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); #ifdef GPIO_MASK_2 - if (addr & GPIO_MASK_2) - bfin_write_PORTGIO_SET(GPIO_PIN_2); - else - bfin_write_PORTGIO_CLEAR(GPIO_PIN_2); + gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); #endif SSYNC(); @@ -55,6 +50,9 @@ MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ void gpio_cfi_flash_init(void) { - bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | GPIO_PIN_1); + gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); +#ifdef GPIO_MASK_2 + gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); +#endif gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); } diff --git a/board/cm-bf537u/Makefile b/board/cm-bf537u/Makefile index 3812ba1..bad018a 100644 --- a/board/cm-bf537u/Makefile +++ b/board/cm-bf537u/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS-y := $(BOARD).o flash.o gpio_cfi_flash.o +COBJS-y := $(BOARD).o gpio_cfi_flash.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/cm-bf537u/flash.c b/board/cm-bf537u/flash.c deleted file mode 100644 index 52abe79..0000000 --- a/board/cm-bf537u/flash.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * flash.c - helper commands for working with GPIO-assisted flash - * - * Copyright (c) 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <command.h> -#include <asm/blackfin.h> -#include "gpio_cfi_flash.h" - -int do_ph(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong faddr = CONFIG_SYS_FLASH_BASE; - ushort data; - ulong dflg; - - if (argc > 1) { - dflg = simple_strtoul(argv[1], NULL, 16); - faddr |= (dflg << 21); - gpio_cfi_flash_swizzle((void *)faddr); - } else { - data = bfin_read_PORTHIO(); - printf("Port H data %04x (PH0:%i)\n", data, !!(data & PH0)); - } - - return 0; -} - -U_BOOT_CMD(ph, 3, 0, do_ph, - "set/clear PH0 GPIO flash bank switch\n", - "<ph0> - set PH0 GPIO pin state\n"); diff --git a/board/cm-bf537u/gpio_cfi_flash.c b/board/cm-bf537u/gpio_cfi_flash.c index 68633ec..416c689 100644 --- a/board/cm-bf537u/gpio_cfi_flash.c +++ b/board/cm-bf537u/gpio_cfi_flash.c @@ -8,10 +8,11 @@ #include <common.h> #include <asm/blackfin.h> +#include <asm/gpio.h> #include <asm/io.h> #include "gpio_cfi_flash.h" -#define GPIO_PIN_1 PH0 +#define GPIO_PIN_1 GPIO_PH0 #define GPIO_MASK_1 (1 << 21) #define GPIO_MASK (GPIO_MASK_1) @@ -19,16 +20,10 @@ void *gpio_cfi_flash_swizzle(void *vaddr) { unsigned long addr = (unsigned long)vaddr; - if (addr & GPIO_MASK_1) - bfin_write_PORTHIO_SET(GPIO_PIN_1); - else - bfin_write_PORTHIO_CLEAR(GPIO_PIN_1); + gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); #ifdef GPIO_MASK_2 - if (addr & GPIO_MASK_2) - bfin_write_PORTGIO_SET(GPIO_PIN_2); - else - bfin_write_PORTGIO_CLEAR(GPIO_PIN_2); + gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); #endif SSYNC(); @@ -55,6 +50,9 @@ MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ void gpio_cfi_flash_init(void) { - bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() | GPIO_PIN_1); + gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); +#ifdef GPIO_MASK_2 + gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); +#endif gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); } diff --git a/board/cm-bf548/cm-bf548.c b/board/cm-bf548/cm-bf548.c index 3627586..90ce4c3 100644 --- a/board/cm-bf548/cm-bf548.c +++ b/board/cm-bf548/cm-bf548.c @@ -11,6 +11,7 @@ #include <command.h> #include <netdev.h> #include <asm/blackfin.h> +#include <asm/portmux.h> DECLARE_GLOBAL_DATA_PTR; @@ -23,53 +24,13 @@ int checkboard(void) int board_early_init_f(void) { - /* Port H: PH8 - PH13 == A4 - A9 - * address lines of the parallel asynchronous memory interface - */ - - /************************************************ - * configure GPIO * - * set port H function enable register * - * configure PH8-PH13 as peripheral (not GPIO) * - *************************************************/ - bfin_write_PORTH_FER(0x3F03); - - /************************************************ - * set port H MUX to configure PH8-PH13 * - * 1st Function (MUX = 00) (bits 16-27 == 0) * - * Set to address signals A4-A9 * - *************************************************/ - bfin_write_PORTH_MUX(0); - - /************************************************ - * set port H direction register * - * enable PH8-PH13 as outputs * - *************************************************/ - bfin_write_PORTH_DIR_SET(0x3F00); - - /* Port I: PI0 - PH14 == A10 - A24 - * address lines of the parallel asynchronous memory interface - */ - - /************************************************ - * set port I function enable register * - * configure PI0-PI14 as peripheral (not GPIO) * - *************************************************/ - bfin_write_PORTI_FER(0x7fff); - - /************************************************** - * set PORT I MUX to configure PI14-PI0 as * - * 1st Function (MUX=00) - address signals A10-A24 * - ***************************************************/ - bfin_write_PORTI_MUX(0); - - /**************************************** - * set PORT I direction register * - * enable PI0 - PI14 as outputs * - *****************************************/ - bfin_write_PORTI_DIR_SET(0x7fff); - - return 0; + /* Set async addr lines as peripheral */ + const unsigned short pins[] = { + P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12, + P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, + P_A21, P_A22, P_A23, P_A24, 0 + }; + return peripheral_request_list(pins, "async"); } int board_eth_init(bd_t *bis) diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c index 4097f09..d43f5a1 100644 --- a/board/cm-bf548/video.c +++ b/board/cm-bf548/video.c @@ -11,6 +11,8 @@ #include <config.h> #include <malloc.h> #include <asm/blackfin.h> +#include <asm/gpio.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/dma.h> #include <i2c.h> #include <linux/types.h> @@ -174,28 +176,21 @@ void Init_DMA(void *dst) void Init_Ports(void) { - *pPORTF_MUX = 0x00000000; - *pPORTF_FER |= 0xFFFF; /* PPI0..15 */ - - *pPORTG_MUX &= - ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | - PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK); - *pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4; /* CLK, FS1, FS2, PPI16..17 */ - + const unsigned short pins[] = { + P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4, + P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9, + P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, + P_PPI0_D15, P_PPI0_D16, P_PPI0_D17, #if !defined(CONFIG_VIDEO_RGB666) - *pPORTD_MUX &= - ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | - PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK); - *pPORTD_MUX |= - (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 | - PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4); - *pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5; /* PPI18..23 */ + P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, + P_PPI0_D23, #endif + P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0, + }; + peripheral_request_list(pins, "lcd"); - *pPORTE_FER &= ~PE3; /* DISP */ - *pPORTE_DIR_SET = PE3; - *pPORTE_SET = PE3; - + gpio_request(GPIO_PE3, "lcd-disp"); + gpio_direction_output(GPIO_PE3, 1); } void EnableDMA(void) diff --git a/board/colibri_pxa270/Makefile b/board/colibri_pxa270/Makefile new file mode 100644 index 0000000..44d73cc --- /dev/null +++ b/board/colibri_pxa270/Makefile @@ -0,0 +1,45 @@ +# +# Toradex Colibri PXA270 Support +# +# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := colibri_pxa270.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/colibri_pxa270/colibri_pxa270.c new file mode 100644 index 0000000..d3822f0 --- /dev/null +++ b/board/colibri_pxa270/colibri_pxa270.c @@ -0,0 +1,118 @@ +/* + * Toradex Colibri PXA270 Support + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/hardware.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations + */ +extern struct serial_device serial_ffuart_device; +extern struct serial_device serial_btuart_device; +extern struct serial_device serial_stuart_device; + +struct serial_device *default_serial_console (void) +{ + return &serial_ffuart_device; +} + +int board_init (void) +{ + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of vpac270 */ + gd->bd->bi_arch_number = MACH_TYPE_COLIBRI; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +#ifdef CONFIG_CMD_USB +int usb_board_init(void) +{ + UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + + UHCHR |= UHCHR_FSBIR; + + while (UHCHR & UHCHR_FSBIR); + + UHCHR &= ~UHCHR_SSE; + UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); + + /* Clear any OTG Pin Hold */ + if (PSSR & PSSR_OTGPH) + PSSR |= PSSR_OTGPH; + + UHCRHDA &= ~(0x200); + UHCRHDA |= 0x100; + + /* Set port power control mask bits, only 3 ports. */ + UHCRHDB |= (0x7<<17); + + /* enable port 2 */ + UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; + + return 0; +} + +void usb_board_init_fail(void) +{ + return; +} + +void usb_board_stop(void) +{ + UHCHR |= UHCHR_FHR; + udelay(11); + UHCHR &= ~UHCHR_FHR; + + UHCCOMS |= 1; + udelay(10); + + CKEN &= ~CKEN10_USBHOST; + + return; +} +#endif + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + return dm9000_initialize(bis); +} +#endif diff --git a/board/colibri_pxa270/config.mk b/board/colibri_pxa270/config.mk new file mode 100644 index 0000000..1d650ac --- /dev/null +++ b/board/colibri_pxa270/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xa1000000 diff --git a/board/colibri_pxa270/lowlevel_init.S b/board/colibri_pxa270/lowlevel_init.S new file mode 100644 index 0000000..a43dac2 --- /dev/null +++ b/board/colibri_pxa270/lowlevel_init.S @@ -0,0 +1,36 @@ +/* + * Toradex Colibri PXA270 Lowlevel Hardware Initialization + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> +#include <asm/arch/macro.h> + +.globl lowlevel_init +lowlevel_init: + pxa_gpio_setup + pxa_wait_ticks 0x8000 + pxa_mem_setup + pxa_wakeup + pxa_intr_setup + pxa_clock_setup + + mov pc, lr diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c index b0ebad7..96698e7 100644 --- a/board/esd/vme8349/vme8349.c +++ b/board/esd/vme8349/vme8349.c @@ -105,7 +105,7 @@ int misc_init_r() { immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - clrsetbits_be32(&im->lbus.lcrr, LBCR_LDIS, 0); + clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0); return 0; } diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c index af8a4a2..61b6c33 100644 --- a/board/eukrea/cpu9260/cpu9260.c +++ b/board/eukrea/cpu9260/cpu9260.c @@ -200,13 +200,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index df289aa..2d48d7e 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -42,6 +42,10 @@ COBJS-$(CONFIG_MPC8541CDS) += cds_pci_ft.o COBJS-$(CONFIG_MPC8548CDS) += cds_pci_ft.o COBJS-$(CONFIG_MPC8555CDS) += cds_pci_ft.o +COBJS-$(CONFIG_MPC8536DS) += ics307_clk.o +COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o +COBJS-$(CONFIG_P1022DS) += ics307_clk.o +COBJS-$(CONFIG_P2020DS) += ics307_clk.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c new file mode 100644 index 0000000..89d8810 --- /dev/null +++ b/board/freescale/common/ics307_clk.c @@ -0,0 +1,88 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> + +#include "ics307_clk.h" + +#ifdef CONFIG_FSL_NGPIXIS +#include "ngpixis.h" +#else +#include "pixis.h" +#endif + +/* decode S[0-2] to Output Divider (OD) */ +static u8 ics307_s_to_od[] = { + 10, 2, 8, 4, 5, 7, 3, 6 +}; + +/* + * Calculate frequency being generated by ICS307-02 clock chip based upon + * the control bytes being programmed into it. + */ +static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2) +{ + const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ; + unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); + unsigned long rdw = cw2 & 0x7F; + unsigned long od = ics307_s_to_od[cw0 & 0x7]; + unsigned long freq; + + /* + * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD) + * + * cw0: C1 C0 TTL F1 F0 S2 S1 S0 + * cw1: V8 V7 V6 V5 V4 V3 V2 V1 + * cw2: V0 R6 R5 R4 R3 R2 R1 R0 + * + * R6:R0 = Reference Divider Word (RDW) + * V8:V0 = VCO Divider Word (VDW) + * S2:S0 = Output Divider Select (OD) + * F1:F0 = Function of CLK2 Output + * TTL = duty cycle + * C1:C0 = internal load capacitance for cyrstal + * + */ + + freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od); + + debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2, + freq); + return freq; +} + +unsigned long get_board_sys_clk(void) +{ + return ics307_clk_freq( + in_8(&pixis->sclk[0]), + in_8(&pixis->sclk[1]), + in_8(&pixis->sclk[2])); +} + +unsigned long get_board_ddr_clk(void) +{ + return ics307_clk_freq( + in_8(&pixis->dclk[0]), + in_8(&pixis->dclk[1]), + in_8(&pixis->dclk[2])); +} diff --git a/board/freescale/common/ics307_clk.h b/board/freescale/common/ics307_clk.h new file mode 100644 index 0000000..db3dbc4 --- /dev/null +++ b/board/freescale/common/ics307_clk.h @@ -0,0 +1,30 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ICS_CLK_H_ +#define __ICS_CLK_H_ 1 + +#ifndef __ASSEMBLY__ +extern unsigned long get_board_sys_clk(void); +extern unsigned long get_board_ddr_clk(void); +#endif + +#endif /* __ICS_CLK_H_ */ diff --git a/board/freescale/common/ngpixis.h b/board/freescale/common/ngpixis.h index 3c59ea8..089408b 100644 --- a/board/freescale/common/ngpixis.h +++ b/board/freescale/common/ngpixis.h @@ -45,7 +45,7 @@ typedef struct ngpixis { u8 sw; u8 en; } s[8]; -} ngpixis_t __attribute__ ((aligned(1))); +} __attribute__ ((packed)) ngpixis_t; /* Pointer to the PIXIS register set */ #define pixis ((ngpixis_t *)PIXIS_BASE) diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h new file mode 100644 index 0000000..7f86de7 --- /dev/null +++ b/board/freescale/common/pixis.h @@ -0,0 +1,182 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __PIXIS_H_ +#define __PIXIS_H_ 1 + +/* PIXIS register set. */ +#if defined(CONFIG_MPC8536DS) +typedef struct pixis { + u8 id; + u8 ver; + u8 pver; + u8 csr; + u8 rst; + u8 rst2; + u8 aux1; + u8 spd; + u8 aux2; + u8 csr2; + u8 watch; + u8 led; + u8 pwr; + u8 res[3]; + u8 vctl; + u8 vstat; + u8 vcfgen0; + u8 vcfgen1; + u8 vcore0; + u8 res1; + u8 vboot; + u8 vspeed[3]; + u8 sclk[3]; + u8 dclk[3]; + u8 i2cdacr; + u8 vcoreacc[4]; + u8 vcorecnt[3]; + u8 vcoremax[2]; + u8 vplatacc[4]; + u8 vplatcnt[3]; + u8 vplatmax[2]; + u8 vtempacc[4]; + u8 vtempcnt[3]; + u8 vtempmax[2]; + u8 res2[4]; +} __attribute__ ((packed)) pixis_t; + +#elif defined(CONFIG_MPC8544DS) +typedef struct pixis { + u8 id; + u8 ver; + u8 pver; + u8 csr; + u8 rst; + u8 pwr; + u8 aux1; + u8 spd; + u8 res[8]; + u8 vctl; + u8 vstat; + u8 vcfgen0; + u8 vcfgen1; + u8 vcore0; + u8 res1; + u8 vboot; + u8 vspeed[2]; + u8 vclkh; + u8 vclkl; + u8 watch; + u8 led; + u8 vspeed2; + u8 res2[34]; +} __attribute__ ((packed)) pixis_t; + +#elif defined(CONFIG_MPC8572DS) +typedef struct pixis { + u8 id; + u8 ver; + u8 pver; + u8 csr; + u8 rst; + u8 pwr1; + u8 aux1; + u8 spd; + u8 aux2; + u8 res[7]; + u8 vctl; + u8 vstat; + u8 vcfgen0; + u8 vcfgen1; + u8 vcore0; + u8 res1; + u8 vboot; + u8 vspeed[3]; + u8 res2[2]; + u8 sclk[3]; + u8 dclk[3]; + u8 res3[2]; + u8 watch; + u8 led; + u8 res4[25]; +} __attribute__ ((packed)) pixis_t; + +#elif defined(CONFIG_MPC8610HPCD) +typedef struct pixis { + u8 id; + u8 ver; /* also called arch */ + u8 pver; + u8 csr; + u8 rst; + u8 pwr; + u8 aux; + u8 spd; + u8 brdcfg0; + u8 brdcfg1; + u8 res[4]; + u8 led; + u8 serno; + u8 vctl; + u8 vstat; + u8 vcfgen0; + u8 vcfgen1; + u8 vcore0; + u8 res1; + u8 vboot; + u8 vspeed[2]; + u8 res2; + u8 sclk[3]; + u8 res3; + u8 watch; + u8 res4[33]; +} __attribute__ ((packed)) pixis_t; + +#elif defined(CONFIG_MPC8641HPCN) +typedef struct pixis { + u8 id; + u8 ver; + u8 pver; + u8 csr; + u8 rst; + u8 pwr; + u8 aux; + u8 spd; + u8 res[8]; + u8 vctl; + u8 vstat; + u8 vcfgen0; + u8 vcfgen1; + u8 vcore0; + u8 res1; + u8 vboot; + u8 vspeed[2]; + u8 vclkh; + u8 vclkl; + u8 watch; + u8 res3[36]; +} __attribute__ ((packed)) pixis_t; +#else +#error Need to define pixis_t for this board +#endif + +/* Pointer to the PIXIS register set */ +#define pixis ((pixis_t *)PIXIS_BASE) + +#endif /* __PIXIS_H_ */ diff --git a/board/altera/ep1c20/Makefile b/board/freescale/mpc8308rdb/Makefile index acad2aa..e9bfa2b 100644 --- a/board/altera/ep1c20/Makefile +++ b/board/freescale/mpc8308rdb/Makefile @@ -1,6 +1,8 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2010 +# Ilya Yanok, Emcraft Systems, yanok@emcraft.com # # See file CREDITS for list of people who contributed to this # project. @@ -22,15 +24,10 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif LIB = $(obj)lib$(BOARD).a -COMOBJS := ../common/AMDLV065D.o ../common/epled.o - -COBJS := $(BOARD).o $(COMOBJS) +COBJS := $(BOARD).o sdram.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8308rdb/config.mk b/board/freescale/mpc8308rdb/config.mk new file mode 100644 index 0000000..f768264 --- /dev/null +++ b/board/freescale/mpc8308rdb/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xFE000000 diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c new file mode 100644 index 0000000..a864189 --- /dev/null +++ b/board/freescale/mpc8308rdb/mpc8308rdb.c @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <hwconfig.h> +#include <i2c.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <pci.h> +#include <mpc83xx.h> +#include <vsc7385.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_mpc83xx_serdes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + + if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) + gd->flags |= GD_FLG_SILENT; + + return 0; +} + +static u8 read_board_info(void) +{ + u8 val8; + i2c_set_bus_num(0); + + if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) + return val8; + else + return 0; +} + +int checkboard(void) +{ + static const char * const rev_str[] = { + "1.0", + "<reserved>", + "<reserved>", + "<reserved>", + "<unknown>", + }; + u8 info; + int i; + + info = read_board_info(); + i = (!info) ? 4 : info & 0x03; + + printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]); + + return 0; +} + +static struct pci_region pcie_regions_0[] = { + { + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, + .size = CONFIG_SYS_PCIE1_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE1_IO_BASE, + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, + .size = CONFIG_SYS_PCIE1_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +void pci_init_board(void) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + sysconf83xx_t *sysconf = &immr->sysconf; + clk83xx_t *clk = (clk83xx_t *)&immr->clk; + law83xx_t *pcie_law = sysconf->pcielaw; + struct pci_region *pcie_reg[] = { pcie_regions_0 }; + + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + + clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM , + SCCR_PCIEXP1CM_1); + + /* Deassert the resets in the control register */ + out_be32(&sysconf->pecr1, 0xE0008000); + udelay(2000); + + /* Configure PCI Express Local Access Windows */ + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + mpc83xx_pcie_init(1, pcie_reg, 0); +} +/* + * Miscellaneous late-boot configurations + * + * If a VSC7385 microcode image is present, then upload it. +*/ +int misc_init_r(void) +{ +#ifdef CONFIG_VSC7385_IMAGE + if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, + CONFIG_VSC7385_IMAGE_SIZE)) { + puts("Failure uploading VSC7385 microcode.\n"); + return 1; + } +#endif + + return 0; +} +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + fdt_fixup_dr_usb(blob, bd); +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rv, num_if = 0; + + /* Initialize TSECs first */ + if ((rv = cpu_eth_init(bis)) >= 0) + num_if += rv; + else + printf("ERROR: failed to initialize TSECs.\n"); + + if ((rv = pci_eth_init(bis)) >= 0) + num_if += rv; + else + printf("ERROR: failed to initialize PCI Ethernet.\n"); + + return num_if; +} diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c new file mode 100644 index 0000000..939c1b8 --- /dev/null +++ b/board/freescale/mpc8308rdb/sdram.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com + * + * Authors: Nick.Spence@freescale.com + * Wilson.Lo@freescale.com + * scottwood@freescale.com + * + * This files is mostly identical to the original from + * board\freescale\mpc8315erdb\sdram.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc83xx.h> + +#include <asm/bitops.h> +#include <asm/io.h> + +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void resume_from_sleep(void) +{ + u32 magic = *(u32 *)0; + + typedef void (*func_t)(void); + func_t resume = *(func_t *)4; + + if (magic == 0xf5153ae5) + resume(); + + gd->flags &= ~GD_FLG_SILENT; + puts("\nResume from sleep failed: bad magic word\n"); +} + +/* Fixed sdram init -- doesn't use serial presence detect. + * + * This is useful for faster booting in configs where the RAM is unlikely + * to be changed, or for things like NAND booting where space is tight. + */ +static long fixed_sdram(void) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2(msize); + + out_be32(&im->sysconf.ddrlaw[0].bar, + CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); + out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); + + /* + * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], + * or the DDR2 controller may fail to initialize correctly. + */ + udelay(50000); + + out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); + out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); + + /* Currently we use only one CS, so disable the other bank. */ + out_be32(&im->ddr.cs_config[1], 0); + + out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); + out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + + if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) { + out_be32(&im->ddr.sdram_cfg, + CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI); + } else { + out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); + } + + out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); + out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); + + out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); + sync(); + + /* enable DDR controller */ + setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); + sync(); + + return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); +} + +phys_size_t initdram(int board_type) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize; + + if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM */ + msize = fixed_sdram(); + + if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) + resume_from_sleep(); + + /* return total bus SDRAM size(bytes) -- DDR */ + return msize; +} diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index 0c4fd68..7aede13 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -110,7 +110,7 @@ static long fixed_sdram(void) phys_size_t initdram(int board_type) { volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbc = &im->lbus; + volatile fsl_lbc_t *lbc = &im->im_lbc; u32 msize; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 61d1249..365ac37 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -192,7 +192,7 @@ int checkboard (void) void sdram_init(void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbc = &immap->lbus; + volatile fsl_lbc_t *lbc = &immap->im_lbc; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; /* diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 7da39f1..5647579 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -221,15 +221,14 @@ int misc_init_f(void) 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 }; volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbus = &immap->lbus; - lbus->bank[3].br = CONFIG_SYS_BR3_PRELIM; - lbus->bank[3].or = CONFIG_SYS_OR3_PRELIM; + set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); + set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000, GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000 */ - lbus->mamr = 0x08404440; + immap->im_lbc.mamr = 0x08404440; upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 4f55732..59ada9c 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -280,7 +280,7 @@ int checkboard(void) static int sdram_init(unsigned int base) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbc = &immap->lbus; + fsl_lbc_t *lbc = LBC_BASE_ADDR; const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024; int rem = base % sdram_size; uint *sdram_addr; @@ -293,8 +293,8 @@ static int sdram_init(unsigned int base) /* * Setup SDRAM Base and Option Registers */ - immap->lbus.bank[2].br = base | CONFIG_SYS_BR2; - immap->lbus.bank[2].or = CONFIG_SYS_OR2; + set_lbc_br(2, base | CONFIG_SYS_BR2); + set_lbc_or(2, CONFIG_SYS_OR2); immap->sysconf.lblaw[2].bar = base; immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2; diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c index 9ffffb4..92d56a3 100644 --- a/board/freescale/mpc8360erdk/nand.c +++ b/board/freescale/mpc8360erdk/nand.c @@ -82,9 +82,9 @@ static struct fsl_upm_nand fun = { int board_nand_init(struct nand_chip *nand) { - fun.upm.mxmr = &im->lbus.mamr; - fun.upm.mdr = &im->lbus.mdr; - fun.upm.mar = &im->lbus.mar; + fun.upm.mxmr = &im->im_lbc.mamr; + fun.upm.mdr = &im->im_lbc.mdr; + fun.upm.mar = &im->im_lbc.mar; upm_setup(&fun.upm); diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 1968106..50ca3ca 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -350,154 +350,6 @@ int board_early_init_r(void) return 0; } -#ifdef CONFIG_GET_CLK_FROM_ICS307 -/* decode S[0-2] to Output Divider (OD) */ -static unsigned char -ics307_S_to_OD[] = { - 10, 2, 8, 4, 5, 7, 3, 6 -}; - -/* Calculate frequency being generated by ICS307-02 clock chip based upon - * the control bytes being programmed into it. */ -/* XXX: This function should probably go into a common library */ -static unsigned long -ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) -{ - const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; - unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); - unsigned long RDW = cw2 & 0x7F; - unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; - unsigned long freq; - - /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ - - /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 - * cw1: V8 V7 V6 V5 V4 V3 V2 V1 - * cw2: V0 R6 R5 R4 R3 R2 R1 R0 - * - * R6:R0 = Reference Divider Word (RDW) - * V8:V0 = VCO Divider Word (VDW) - * S2:S0 = Output Divider Select (OD) - * F1:F0 = Function of CLK2 Output - * TTL = duty cycle - * C1:C0 = internal load capacitance for cyrstal - */ - - /* Adding 1 to get a "nicely" rounded number, but this needs - * more tweaking to get a "properly" rounded number. */ - - freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); - - debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, - freq); - return freq; -} - -unsigned long -get_board_sys_clk(ulong dummy) -{ - u8 *pixis_base = (u8 *)PIXIS_BASE; - - return ics307_clk_freq ( - in_8(pixis_base + PIXIS_VSYSCLK0), - in_8(pixis_base + PIXIS_VSYSCLK1), - in_8(pixis_base + PIXIS_VSYSCLK2) - ); -} - -unsigned long -get_board_ddr_clk(ulong dummy) -{ - u8 *pixis_base = (u8 *)PIXIS_BASE; - - return ics307_clk_freq ( - in_8(pixis_base + PIXIS_VDDRCLK0), - in_8(pixis_base + PIXIS_VDDRCLK1), - in_8(pixis_base + PIXIS_VDDRCLK2) - ); -} -#else -unsigned long -get_board_sys_clk(ulong dummy) -{ - u8 i; - ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - i = in_8(pixis_base + PIXIS_SPD); - i &= 0x07; - - switch (i) { - case 0: - val = 33333333; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66666666; - break; - case 4: - val = 83333333; - break; - case 5: - val = 100000000; - break; - case 6: - val = 133333333; - break; - case 7: - val = 166666666; - break; - } - - return val; -} - -unsigned long -get_board_ddr_clk(ulong dummy) -{ - u8 i; - ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - i = in_8(pixis_base + PIXIS_SPD); - i &= 0x38; - i >>= 3; - - switch (i) { - case 0: - val = 33333333; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66666666; - break; - case 4: - val = 83333333; - break; - case 5: - val = 100000000; - break; - case 6: - val = 133333333; - break; - case 7: - val = 166666666; - break; - } - return val; -} -#endif - int board_eth_init(bd_t *bis) { #ifdef CONFIG_TSEC_ENET diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index 9e3f677..f9ff827 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -117,7 +117,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; @@ -176,7 +176,7 @@ local_bus_init(void) void sdram_init(void) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; puts(" SDRAM: "); @@ -185,8 +185,8 @@ sdram_init(void) /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CONFIG_SYS_OR2_PRELIM; - lbc->br2 = CONFIG_SYS_BR2_PRELIM; + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index c30d966..0580fe7 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -291,7 +291,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; @@ -340,7 +340,7 @@ sdram_init(void) #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) uint idx; - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint cpu_board_rev; uint lsdmr_common; @@ -352,16 +352,11 @@ sdram_init(void) /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CONFIG_SYS_OR2_PRELIM; - asm("msync"); - - lbc->br2 = CONFIG_SYS_BR2_PRELIM; - asm("msync"); - + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); - lbc->lsrt = CONFIG_SYS_LBC_LSRT; lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("msync"); diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 0be2d89..581d5f2 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -40,7 +40,7 @@ int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); u8 vboot; u8 *pixis_base = (u8 *)PIXIS_BASE; diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index aa3f32b..f016995 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -118,7 +118,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; @@ -154,7 +154,7 @@ sdram_init(void) #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) uint idx; - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint cpu_board_rev; uint lsdmr_common; @@ -166,16 +166,11 @@ sdram_init(void) /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CONFIG_SYS_OR2_PRELIM; - asm("msync"); - - lbc->br2 = CONFIG_SYS_BR2_PRELIM; - asm("msync"); - + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); - lbc->lsrt = CONFIG_SYS_LBC_LSRT; lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("msync"); diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index ecddd0d..b7e0e0c 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -291,7 +291,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; @@ -340,7 +340,7 @@ sdram_init(void) #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) uint idx; - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint cpu_board_rev; uint lsdmr_common; @@ -352,12 +352,8 @@ sdram_init(void) /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CONFIG_SYS_OR2_PRELIM; - asm("msync"); - - lbc->br2 = CONFIG_SYS_BR2_PRELIM; - asm("msync"); - + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 2bca0f2..489f90b 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -322,7 +322,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; @@ -381,7 +381,7 @@ local_bus_init(void) void sdram_init(void) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; puts(" SDRAM: "); @@ -390,8 +390,8 @@ sdram_init(void) /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CONFIG_SYS_OR2_PRELIM; - lbc->br2 = CONFIG_SYS_BR2_PRELIM; + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 4ec13a9..036bf95 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -181,7 +181,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; @@ -214,7 +214,7 @@ sdram_init(void) #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) uint idx; - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint lsdmr_common; @@ -225,16 +225,13 @@ sdram_init(void) /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CONFIG_SYS_OR2_PRELIM; - asm("msync"); - - lbc->br2 = CONFIG_SYS_BR2_PRELIM; + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); asm("msync"); lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); - lbc->lsrt = CONFIG_SYS_LBC_LSRT; lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("msync"); diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 1eddeef..81e8ff5 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -308,7 +308,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 6029a51..81d481a 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -284,149 +284,6 @@ int board_early_init_r(void) return 0; } -#ifdef CONFIG_GET_CLK_FROM_ICS307 -/* decode S[0-2] to Output Divider (OD) */ -static unsigned char ics307_S_to_OD[] = { - 10, 2, 8, 4, 5, 7, 3, 6 -}; - -/* Calculate frequency being generated by ICS307-02 clock chip based upon - * the control bytes being programmed into it. */ -/* XXX: This function should probably go into a common library */ -static unsigned long -ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) -{ - const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ; - unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); - unsigned long RDW = cw2 & 0x7F; - unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; - unsigned long freq; - - /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ - - /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 - * cw1: V8 V7 V6 V5 V4 V3 V2 V1 - * cw2: V0 R6 R5 R4 R3 R2 R1 R0 - * - * R6:R0 = Reference Divider Word (RDW) - * V8:V0 = VCO Divider Word (VDW) - * S2:S0 = Output Divider Select (OD) - * F1:F0 = Function of CLK2 Output - * TTL = duty cycle - * C1:C0 = internal load capacitance for cyrstal - */ - - /* Adding 1 to get a "nicely" rounded number, but this needs - * more tweaking to get a "properly" rounded number. */ - - freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); - - debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, - freq); - return freq; -} - -unsigned long get_board_sys_clk(ulong dummy) -{ - u8 *pixis_base = (u8 *)PIXIS_BASE; - - return ics307_clk_freq ( - in_8(pixis_base + PIXIS_VSYSCLK0), - in_8(pixis_base + PIXIS_VSYSCLK1), - in_8(pixis_base + PIXIS_VSYSCLK2) - ); -} - -unsigned long get_board_ddr_clk(ulong dummy) -{ - u8 *pixis_base = (u8 *)PIXIS_BASE; - - return ics307_clk_freq ( - in_8(pixis_base + PIXIS_VDDRCLK0), - in_8(pixis_base + PIXIS_VDDRCLK1), - in_8(pixis_base + PIXIS_VDDRCLK2) - ); -} -#else -unsigned long get_board_sys_clk(ulong dummy) -{ - u8 i; - ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - i = in_8(pixis_base + PIXIS_SPD); - i &= 0x07; - - switch (i) { - case 0: - val = 33333333; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66666666; - break; - case 4: - val = 83333333; - break; - case 5: - val = 100000000; - break; - case 6: - val = 133333333; - break; - case 7: - val = 166666666; - break; - } - - return val; -} - -unsigned long get_board_ddr_clk(ulong dummy) -{ - u8 i; - ulong val = 0; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - i = in_8(pixis_base + PIXIS_SPD); - i &= 0x38; - i >>= 3; - - switch (i) { - case 0: - val = 33333333; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66666666; - break; - case 4: - val = 83333333; - break; - case 5: - val = 100000000; - break; - case 6: - val = 133333333; - break; - case 7: - val = 166666666; - break; - } - return val; -} -#endif - #ifdef CONFIG_TSEC_ENET int board_eth_init(bd_t *bis) { diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile new file mode 100644 index 0000000..8ede2d6 --- /dev/null +++ b/board/freescale/p1022ds/Makefile @@ -0,0 +1,39 @@ +# +# Copyright 2010 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/p1022ds/config.mk b/board/freescale/p1022ds/config.mk new file mode 100644 index 0000000..4581d20 --- /dev/null +++ b/board/freescale/p1022ds/config.mk @@ -0,0 +1,14 @@ +# +# Copyright 2010 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# + +ifndef TEXT_BASE +TEXT_BASE = 0xeff80000 +endif + +RESET_VECTOR_ADDRESS = 0xeffffffc diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c new file mode 100644 index 0000000..7ecfb3e --- /dev/null +++ b/board/freescale/p1022ds/ddr.c @@ -0,0 +1,106 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> + * Timur Tabi <timur@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <i2c.h> + +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) +{ + int ret; + + /* + * The P1022 has only one DDR controller, and the board has only one + * DIMM slot. + */ + ret = i2c_read(SPD_EEPROM_ADDRESS1, 0, 1, (u8 *)ctrl_dimms_spd, + sizeof(ddr3_spd_eeprom_t)); + if (ret) { + debug("DDR: failed to read SPD from address %u\n", + SPD_EEPROM_ADDRESS1); + memset(ctrl_dimms_spd, 0, sizeof(ddr3_spd_eeprom_t)); + } +} + +typedef struct { + u32 datarate_mhz_low; + u32 datarate_mhz_high; + u32 n_ranks; + u32 clk_adjust; /* Range: 0-8 */ + u32 cpo; /* Range: 2-31 */ + u32 write_data_delay; /* Range: 0-6 */ + u32 force_2T; +} board_specific_parameters_t; + +static const board_specific_parameters_t bsp[] = { +/* + * lo| hi| num| clk| cpo|wrdata|2T + * mhz| mhz|ranks|adjst| | delay| + */ + { 0, 333, 1, 5, 31, 3, 0}, + {334, 400, 1, 5, 31, 3, 0}, + {401, 549, 1, 5, 31, 3, 0}, + {550, 680, 1, 5, 31, 5, 0}, + {681, 850, 1, 5, 31, 5, 0}, + { 0, 333, 2, 5, 31, 3, 0}, + {334, 400, 2, 5, 31, 3, 0}, + {401, 549, 2, 5, 31, 3, 0}, + {550, 680, 2, 5, 31, 5, 0}, + {681, 850, 2, 5, 31, 5, 0}, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + unsigned long ddr_freq; + unsigned int i; + + /* set odt_rd_cfg and odt_wr_cfg. */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 1; + } + + /* + * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + for (i = 0; i < ARRAY_SIZE(bsp); i++) { + if (ddr_freq >= bsp[i].datarate_mhz_low && + ddr_freq <= bsp[i].datarate_mhz_high && + pdimm->n_ranks == bsp[i].n_ranks) { + popts->clk_adjust = bsp[i].clk_adjust; + popts->cpo_override = bsp[i].cpo; + popts->write_data_delay = bsp[i].write_data_delay; + popts->twoT_en = bsp[i].force_2T; + break; + } + } + + popts->half_strength_driver_enable = 1; + + /* Per AN4039, enable ZQ calibration. */ + popts->zq_en = 1; + + /* + * For wake-up on ARP, we need auto self refresh enabled + */ + popts->auto_self_refresh_en = 1; + popts->sr_it = 0xb; +} diff --git a/board/freescale/p1022ds/law.c b/board/freescale/p1022ds/law.c new file mode 100644 index 0000000..b23b8f9 --- /dev/null +++ b/board/freescale/p1022ds/law.c @@ -0,0 +1,21 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> + * Timur Tabi <timur@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c new file mode 100644 index 0000000..be692cb --- /dev/null +++ b/board/freescale/p1022ds/p1022ds.c @@ -0,0 +1,354 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> + * Timur Tabi <timur@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_pci.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_serdes.h> +#include <asm/io.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <tsec.h> +#include <asm/fsl_law.h> +#include <asm/mp.h> +#include <netdev.h> +#include <i2c.h> + +#include "../common/ngpixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Set pmuxcr to allow both i2c1 and i2c2 */ + setbits_be32(&gur->pmuxcr, 0x1000); + + /* Read back the register to synchronize the write. */ + in_be32(&gur->pmuxcr); + + /* Set the pin muxing to enable ETSEC2. */ + clrbits_be32(&gur->pmuxcr2, 0x001F8000); + + return 0; +} + +int checkboard(void) +{ + u8 sw; + + puts("Board: P1022DS "); + + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); + + sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); + + switch ((sw & PIXIS_LBMAP_MASK) >> 6) { + case 0: + printf ("vBank: %u\n", ((sw & 0x30) >> 4)); + break; + case 1: + printf ("NAND\n"); + break; + case 2: + case 3: + puts ("Promjet\n"); + break; + } + + return 0; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = 0; + + puts("Initializing....\n"); + + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000; + + puts(" DDR: "); + return dram_size; +} + +#define CONFIG_TFP410_I2C_ADDR 0x38 + +int misc_init_r(void) +{ + u8 temp; + + /* Enable the TFP410 Encoder */ + + temp = 0xBF; + if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) + return -1; + + /* Verify if enabled */ + temp = 0; + if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) + return -1; + + debug("DVI Encoder Read: 0x%02x\n", temp); + + temp = 0x10; + if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) + return -1; + + /* Verify if enabled */ + temp = 0; + if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) + return -1; + + debug("DVI Encoder Read: 0x%02x\n",temp); + + return 0; +} + +/* + * A list of PCI and SATA slots + */ +enum slot_id { + SLOT_PCIE1 = 1, + SLOT_PCIE2, + SLOT_PCIE3, + SLOT_PCIE4, + SLOT_PCIE5, + SLOT_SATA1, + SLOT_SATA2 +}; + +/* + * This array maps the slot identifiers to their names on the P1022DS board. + */ +static const char *slot_names[] = { + [SLOT_PCIE1] = "Slot 1", + [SLOT_PCIE2] = "Slot 2", + [SLOT_PCIE3] = "Slot 3", + [SLOT_PCIE4] = "Slot 4", + [SLOT_PCIE5] = "Mini-PCIe", + [SLOT_SATA1] = "SATA 1", + [SLOT_SATA2] = "SATA 2", +}; + +/* + * This array maps a given SERDES configuration and SERDES device to the PCI or + * SATA slot that it connects to. This mapping is hard-coded in the FPGA. + */ +static u8 serdes_dev_slot[][SATA2 + 1] = { + [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 }, + [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, + [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4, + [PCIE2] = SLOT_PCIE5 }, + [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, + [PCIE2] = SLOT_PCIE3, + [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, + [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, + [PCIE2] = SLOT_PCIE3 }, + [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3, + [PCIE2] = SLOT_PCIE3, + [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, + [0x1c] = { [PCIE1] = SLOT_PCIE1, + [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, + [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 }, + [0x1f] = { [PCIE1] = SLOT_PCIE1 }, +}; + + +/* + * Returns the name of the slot to which the PCIe or SATA controller is + * connected + */ +const char *serdes_slot_name(enum srds_prtcl device) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + enum slot_id slot = serdes_dev_slot[srds_cfg][device]; + const char *name = slot_names[slot]; + + if (name) + return name; + else + return "Nothing"; +} + +static void configure_pcie(struct fsl_pci_info *info, + struct pci_controller *hose, + const char *connected) +{ + static int bus_number = 0; + int is_endpoint; + + set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); + set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); + is_endpoint = fsl_setup_hose(hose, info->regs); + printf(" PCIE%u connected to %s as %s (base addr %lx)\n", + info->pci_num, connected, + is_endpoint ? "Endpoint" : "Root Complex", info->regs); + bus_number = fsl_pci_init_port(info, hose, bus_number); +} + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif + +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif + +#ifdef CONFIG_PCIE3 +static struct pci_controller pcie3_hose; +#endif + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + struct fsl_pci_info pci_info; + u32 devdisr = in_be32(&gur->devdisr); + +#ifdef CONFIG_PCIE1 + if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) { + SET_STD_PCIE_INFO(pci_info, 1); + configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1)); + } else { + printf(" PCIE1: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ +#endif + +#ifdef CONFIG_PCIE2 + if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { + SET_STD_PCIE_INFO(pci_info, 2); + configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2)); + } else { + printf(" PCIE2: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ +#endif + +#ifdef CONFIG_PCIE3 + if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { + SET_STD_PCIE_INFO(pci_info, 3); + configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3)); + } else { + printf(" PCIE3: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ +#endif +} +#endif + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + return 0; +} + +/* + * Initialize on-board and/or PCI Ethernet devices + * + * Returns: + * <0, error + * 0, no ethernet devices found + * >0, number of ethernet devices initialized + */ +int board_eth_init(bd_t *bis) +{ + struct tsec_info_struct tsec_info[2]; + unsigned int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif + + return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis); +} + +#ifdef CONFIG_OF_BOARD_SETUP +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCIE1 + ft_fsl_pci_setup(blob, "pci0", &pcie1_hose); +#else + ft_fsl_pci_setup(blob, "pci0", NULL); +#endif + +#ifdef CONFIG_PCIE2 + ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); +#else + ft_fsl_pci_setup(blob, "pci1", NULL); +#endif + +#ifdef CONFIG_PCIE3 + ft_fsl_pci_setup(blob, "pci2", &pcie3_hose); +#else + ft_fsl_pci_setup(blob, "pci2", NULL); +#endif + +#ifdef CONFIG_FSL_SGMII_RISER + fsl_sgmii_riser_fdt_fixup(blob); +#endif +} +#endif + +#ifdef CONFIG_MP +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c new file mode 100644 index 0000000..e620112 --- /dev/null +++ b/board/freescale/p1022ds/tlb.c @@ -0,0 +1,76 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> + * Timur Tabi <timur@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* W**G* - Flash/promjet, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_4K, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index f0ff209..be4b2eb 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -313,155 +313,6 @@ int board_early_init_r(void) return 0; } -#ifdef CONFIG_GET_CLK_FROM_ICS307 -/* decode S[0-2] to Output Divider (OD) */ -static unsigned char ics307_S_to_OD[] = { - 10, 2, 8, 4, 5, 7, 3, 6 -}; - -/* Calculate frequency being generated by ICS307-02 clock chip based upon - * the control bytes being programmed into it. */ -/* XXX: This function should probably go into a common library */ -static unsigned long -ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2) -{ - const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ; - unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); - unsigned long RDW = cw2 & 0x7F; - unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; - unsigned long freq; - - /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ - - /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 - * cw1: V8 V7 V6 V5 V4 V3 V2 V1 - * cw2: V0 R6 R5 R4 R3 R2 R1 R0 - * - * R6:R0 = Reference Divider Word (RDW) - * V8:V0 = VCO Divider Word (VDW) - * S2:S0 = Output Divider Select (OD) - * F1:F0 = Function of CLK2 Output - * TTL = duty cycle - * C1:C0 = internal load capacitance for cyrstal - */ - - /* Adding 1 to get a "nicely" rounded number, but this needs - * more tweaking to get a "properly" rounded number. */ - - freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); - - debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2, - freq); - return freq; -} - -unsigned long get_board_sys_clk(ulong dummy) -{ - return gd->bus_clk; -} - -unsigned long get_board_ddr_clk(ulong dummy) -{ - return gd->mem_clk; -} - -unsigned long calculate_board_sys_clk(ulong dummy) -{ - ulong val; - - val = ics307_clk_freq(in_8(&pixis->sclk[0]), in_8(&pixis->sclk[1]), - in_8(&pixis->sclk[2])); - debug("sysclk val = %lu\n", val); - return val; -} - -unsigned long calculate_board_ddr_clk(ulong dummy) -{ - ulong val; - - val = ics307_clk_freq(in_8(&pixis->dclk[0]), in_8(&pixis->dclk[1]), - in_8(&pixis->dclk[2])); - debug("ddrclk val = %lu\n", val); - return val; -} -#else -unsigned long get_board_sys_clk(ulong dummy) -{ - u8 i; - ulong val = 0; - - i = in_8(&pixis->spd); - i &= 0x07; - - switch (i) { - case 0: - val = 33333333; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66666666; - break; - case 4: - val = 83333333; - break; - case 5: - val = 100000000; - break; - case 6: - val = 133333333; - break; - case 7: - val = 166666666; - break; - } - - return val; -} - -unsigned long get_board_ddr_clk(ulong dummy) -{ - u8 i; - ulong val = 0; - - i = in_8(&pixis->spd); - i &= 0x38; - i >>= 3; - - switch (i) { - case 0: - val = 33333333; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66666666; - break; - case 4: - val = 83333333; - break; - case 5: - val = 100000000; - break; - case 6: - val = 133333333; - break; - case 7: - val = 166666666; - break; - } - return val; -} -#endif - #ifdef CONFIG_TSEC_ENET int board_eth_init(bd_t *bis) { diff --git a/board/ibf-dsp561/ibf-dsp561.c b/board/ibf-dsp561/ibf-dsp561.c index b5bebd4..d2ac7a5 100644 --- a/board/ibf-dsp561/ibf-dsp561.c +++ b/board/ibf-dsp561/ibf-dsp561.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -16,3 +17,10 @@ int checkboard(void) printf(" Support: http://www.i-syst.com/\n"); return 0; } + +#ifdef CONFIG_DRIVER_AX88180 +int board_eth_init(bd_t *bis) +{ + return ax88180_initialize(bis); +} +#endif diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index 7c27233..054d644 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -69,7 +69,7 @@ phys_size_t initdram (int board_type) long dram_size = 0; #if !defined(CONFIG_RAM_AS_FLASH) - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; sys_info_t sysinfo; uint temp_lbcdll = 0; #endif @@ -110,8 +110,8 @@ phys_size_t initdram (int board_type) gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; asm("sync;isync;msync"); } - lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */ - lbc->br2 = CONFIG_SYS_BR2_PRELIM; + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */ + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); lbc->lbcr = CONFIG_SYS_LBC_LBCR; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; asm("sync"); diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index 5353d73..a302b91 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -134,7 +134,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index b14a3d3..f9d92d9 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -290,7 +290,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index c7835de..e41c84c 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -387,13 +387,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 34861d4..50fae7c 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -160,7 +160,7 @@ int checkboard (void) void sdram_init(void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbc = &immap->lbus; + volatile fsl_lbc_t *lbc = &immap->im_lbc; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; puts("\n SDRAM on Local Bus: "); diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 194f6ab..d62cfd1 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -116,7 +116,7 @@ void local_bus_init(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; uint lbc_hz; @@ -152,7 +152,7 @@ sdram_init(void) #if defined(CONFIG_SYS_LBC_SDRAM_SIZE) uint idx; - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint lsdmr_common; @@ -163,22 +163,14 @@ sdram_init(void) /* * Setup SDRAM Base and Option Registers */ - out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM); - asm("msync"); - - out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM); - asm("msync"); - - out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM); - asm("msync"); - - out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM); - asm("msync"); + set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); + set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); + set_lbc_or(4, CONFIG_SYS_OR4_PRELIM); + set_lbc_br(4, CONFIG_SYS_BR4_PRELIM); out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); asm("msync"); - out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT); out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); asm("msync"); diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index c40b5e3..10ba62f 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -269,7 +269,7 @@ phys_size_t initdram (int board_type) #if 0 #if !defined(CONFIG_RAM_AS_FLASH) - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; sys_info_t sysinfo; uint temp_lbcdll = 0; #endif @@ -310,8 +310,8 @@ phys_size_t initdram (int board_type) gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; asm("sync;isync;msync"); } - lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */ - lbc->br2 = CONFIG_SYS_BR2_PRELIM; + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */ + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); lbc->lbcr = CONFIG_SYS_LBC_LBCR; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; asm("sync"); diff --git a/board/sheldon/simpc8313/sdram.c b/board/sheldon/simpc8313/sdram.c index ebb70a2..ba59943 100644 --- a/board/sheldon/simpc8313/sdram.c +++ b/board/sheldon/simpc8313/sdram.c @@ -129,7 +129,7 @@ void si_read_i2c(u32 lbyte, int count, u8 *buffer) phys_size_t initdram(int board_type) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbc= &im->lbus; + volatile fsl_lbc_t *lbc = &im->im_lbc; u32 msize; if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im) diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c index cb30b48..c2164c9 100644 --- a/board/sheldon/simpc8313/simpc8313.c +++ b/board/sheldon/simpc8313/simpc8313.c @@ -93,7 +93,7 @@ int misc_init_r(void) { int rc = 0; immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - fsl_lbus_t *lbus = &immap->lbus; + fsl_lbc_t *lbus = &immap->im_lbc; u32 *mxmr = &lbus->mamr; /* Pointer to mamr */ /* UPM Table Configuration Code */ diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 9183c15..72e7401 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -87,8 +87,6 @@ int checkboard (void) int misc_init_r (void) { - volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); - /* * Adjust flash start and offset to detected values */ @@ -99,8 +97,10 @@ int misc_init_r (void) * Check if boot FLASH isn't max size */ if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) { - memctl->or0 = gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff); - memctl->br0 = gd->bd->bi_flashstart | (CONFIG_SYS_BR0_PRELIM & 0x00007fff); + set_lbc_or(0, gd->bd->bi_flashstart | + (CONFIG_SYS_OR0_PRELIM & 0x00007fff)); + set_lbc_br(0, gd->bd->bi_flashstart | + (CONFIG_SYS_BR0_PRELIM & 0x00007fff)); /* * Re-check to get correct base address @@ -112,8 +112,8 @@ int misc_init_r (void) * Check if only one FLASH bank is available */ if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { - memctl->or1 = 0; - memctl->br1 = 0; + set_lbc_or(1, 0); + set_lbc_br(1, 0); /* * Re-do flash protection upon new addresses @@ -148,7 +148,7 @@ int misc_init_r (void) */ void local_bus_init (void) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); sys_info_t sysinfo; uint clkdiv; @@ -299,26 +299,25 @@ const gdc_regs *board_get_regs (void) int lime_probe(void) { - volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint cfg_br2; uint cfg_or2; int type; - cfg_br2 = memctl->br2; - cfg_or2 = memctl->or2; + cfg_br2 = get_lbc_br(2); + cfg_or2 = get_lbc_or(2); /* Configure GPCM for CS2 */ - memctl->br2 = 0; - memctl->or2 = 0xfc000410; - memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901; + set_lbc_br(2, 0); + set_lbc_or(2, 0xfc000410); + set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901); /* Get controller type */ type = mb862xx_probe(CONFIG_SYS_LIME_BASE); /* Restore previous CS2 configuration */ - memctl->br2 = 0; - memctl->or2 = cfg_or2; - memctl->br2 = cfg_br2; + set_lbc_br(2, 0); + set_lbc_or(2, cfg_or2); + set_lbc_br(2, cfg_br2); return (type == MB862XX_TYPE_LIME) ? 1 : 0; } diff --git a/board/tcm-bf537/Makefile b/board/tcm-bf537/Makefile index 3812ba1..bad018a 100644 --- a/board/tcm-bf537/Makefile +++ b/board/tcm-bf537/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS-y := $(BOARD).o flash.o gpio_cfi_flash.o +COBJS-y := $(BOARD).o gpio_cfi_flash.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/tcm-bf537/flash.c b/board/tcm-bf537/flash.c deleted file mode 100644 index 14055c6..0000000 --- a/board/tcm-bf537/flash.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * flash.c - helper commands for working with GPIO-assisted flash - * - * Copyright (c) 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <command.h> -#include <asm/blackfin.h> -#include "gpio_cfi_flash.h" - -int do_pf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong faddr = CONFIG_SYS_FLASH_BASE; - ushort data; - ulong dflg; - - if (argc == 3) { - dflg = simple_strtoul(argv[1], NULL, 16); - faddr |= (dflg << 21); - dflg = simple_strtoul(argv[2], NULL, 16); - faddr |= (dflg << 22); - gpio_cfi_flash_swizzle((void *)faddr); - } else { - data = bfin_read_PORTFIO(); - printf("Port F data %04x (PF4:%i PF5:%i)\n", data, - !!(data & PF4), !!(data & PF5)); - } - - return 0; -} - -U_BOOT_CMD(pf, 3, 0, do_pf, - "set/clear PF4/PF5 GPIO flash bank switch\n", - "<pf4> <pf5> - set PF4/PF5 GPIO pin state\n"); diff --git a/board/tcm-bf537/gpio_cfi_flash.c b/board/tcm-bf537/gpio_cfi_flash.c index ac8587c..08ea7af 100644 --- a/board/tcm-bf537/gpio_cfi_flash.c +++ b/board/tcm-bf537/gpio_cfi_flash.c @@ -8,12 +8,13 @@ #include <common.h> #include <asm/blackfin.h> +#include <asm/gpio.h> #include <asm/io.h> #include "gpio_cfi_flash.h" -#define GPIO_PIN_1 PF4 +#define GPIO_PIN_1 GPIO_PF4 #define GPIO_MASK_1 (1 << 21) -#define GPIO_PIN_2 PF5 +#define GPIO_PIN_2 GPIO_PF5 #define GPIO_MASK_2 (1 << 22) #define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2) @@ -21,16 +22,10 @@ void *gpio_cfi_flash_swizzle(void *vaddr) { unsigned long addr = (unsigned long)vaddr; - if (addr & GPIO_MASK_1) - bfin_write_PORTFIO_SET(GPIO_PIN_1); - else - bfin_write_PORTFIO_CLEAR(GPIO_PIN_1); + gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); #ifdef GPIO_MASK_2 - if (addr & GPIO_MASK_2) - bfin_write_PORTFIO_SET(GPIO_PIN_2); - else - bfin_write_PORTFIO_CLEAR(GPIO_PIN_2); + gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); #endif SSYNC(); @@ -57,6 +52,9 @@ MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ void gpio_cfi_flash_init(void) { - bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | GPIO_PIN_1 | GPIO_PIN_2); + gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); +#ifdef GPIO_MASK_2 + gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); +#endif gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); } diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index e564879..8d046f4 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -253,10 +253,10 @@ static int detect_num_flash_banks(void) debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks); /* set OR0 and BR0 */ - im->lbus.bank[0].or = CONFIG_SYS_OR_TIMING_FLASH | - (-(total_size) & OR_GPCM_AM); - im->lbus.bank[0].br = (CONFIG_SYS_FLASH_BASE & BR_BA) | - (BR_MS_GPCM | BR_PS_32 | BR_V); + set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH | + (-(total_size) & OR_GPCM_AM)); + set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) | + (BR_MS_GPCM | BR_PS_32 | BR_V)); return (0); } diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c index 3da689a..4b16c31 100644 --- a/board/tqc/tqm85xx/nand.c +++ b/board/tqc/tqm85xx/nand.c @@ -377,7 +377,7 @@ volatile const u32 *nand_upm_patt; */ static void upmb_write (u_char addr, ulong val) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; out_be32 (&lbc->mdr, val); @@ -393,14 +393,14 @@ static void upmb_write (u_char addr, ulong val) /* * Initialize UPM for NAND flash access. */ -static void nand_upm_setup (volatile ccsr_lbc_t *lbc) +static void nand_upm_setup (volatile fsl_lbc_t *lbc) { uint i, j; uint or3 = CONFIG_SYS_OR3_PRELIM; uint clock = get_lbc_clock (); - out_be32 (&lbc->br3, 0); /* disable bank and reset all bits */ - out_be32 (&lbc->br3, CONFIG_SYS_BR3_PRELIM); + set_lbc_br(3, 0); /* disable bank and reset all bits */ + set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); /* * Search appropriate UPM table for bus clock. @@ -424,7 +424,7 @@ static void nand_upm_setup (volatile ccsr_lbc_t *lbc) /* EAD must be set due to TQM8548 timing specification */ or3 |= OR_UPM_EAD; - out_be32 (&lbc->or3, or3); + set_lbc_or(3, or3); /* Assign address of table */ nand_upm_patt = upm_freq_table[i].upm_patt; @@ -458,7 +458,7 @@ void board_nand_select_device (struct nand_chip *nand, int chip) int board_nand_init (struct nand_chip *nand) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; if (!nand_upm_patt) nand_upm_setup (lbc); diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 8c9d586..fc2a6cb 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -269,8 +269,6 @@ int checkboard (void) int misc_init_r (void) { - volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); - /* * Adjust flash start and offset to detected values */ @@ -281,26 +279,27 @@ int misc_init_r (void) * Recalculate CS configuration if second FLASH bank is available */ if (flash_info[0].size > 0) { - memctl->or1 = ((-flash_info[0].size) & 0xffff8000) | - (CONFIG_SYS_OR1_PRELIM & 0x00007fff); - memctl->br1 = gd->bd->bi_flashstart | - (CONFIG_SYS_BR1_PRELIM & 0x00007fff); + set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) | + (CONFIG_SYS_OR1_PRELIM & 0x00007fff)); + set_lbc_br(1, gd->bd->bi_flashstart | + (CONFIG_SYS_BR1_PRELIM & 0x00007fff)); /* * Re-check to get correct base address for bank 1 */ flash_get_size (gd->bd->bi_flashstart, 0); } else { - memctl->or1 = 0; - memctl->br1 = 0; + set_lbc_or(1, 0); + set_lbc_br(1, 0); } /* * If bank 1 is equipped, bank 0 is mapped after bank 1 */ - memctl->or0 = ((-flash_info[1].size) & 0xffff8000) | - (CONFIG_SYS_OR0_PRELIM & 0x00007fff); - memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) | - (CONFIG_SYS_BR0_PRELIM & 0x00007fff); + set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) | + (CONFIG_SYS_OR0_PRELIM & 0x00007fff)); + set_lbc_br(0, gd->bd->bi_flashstart | + (CONFIG_SYS_BR0_PRELIM & 0x00007fff)); + /* * Re-check to get correct base address for bank 0 */ @@ -341,7 +340,7 @@ int misc_init_r (void) */ static void upmc_write (u_char addr, uint val) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; out_be32 (&lbc->mdr, val); @@ -358,7 +357,7 @@ static void upmc_write (u_char addr, uint val) uint get_lbc_clock (void) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; sys_info_t sys_info; ulong clkdiv = lbc->lcrr & LCRR_CLKDIV; @@ -386,7 +385,7 @@ uint get_lbc_clock (void) void local_bus_init (void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint lbc_mhz = get_lbc_clock () / 1000000; #ifdef CONFIG_MPC8548 @@ -502,10 +501,10 @@ void local_bus_init (void) * set if Local Bus Clock is > 83 MHz. */ if (lbc_mhz > 83) - out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD); + set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD); else - out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN); - out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN); + set_lbc_or(2, CONFIG_SYS_OR2_CAN); + set_lbc_br(2, CONFIG_SYS_BR2_CAN); /* LGPL4 is UPWAIT */ out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X); diff --git a/board/altera/ep1s40/Makefile b/board/ve8313/Makefile index acad2aa..c95f90e 100644 --- a/board/altera/ep1s40/Makefile +++ b/board/ve8313/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,15 +22,10 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif LIB = $(obj)lib$(BOARD).a -COMOBJS := ../common/AMDLV065D.o ../common/epled.o - -COBJS := $(BOARD).o $(COMOBJS) +COBJS := $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/ve8313/config.mk b/board/ve8313/config.mk new file mode 100644 index 0000000..02dd33e --- /dev/null +++ b/board/ve8313/config.mk @@ -0,0 +1,7 @@ +ifndef NAND_SPL +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp +endif + +ifndef TEXT_BASE +TEXT_BASE = 0xfe000000 +endif diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c new file mode 100644 index 0000000..8ba1b19 --- /dev/null +++ b/board/ve8313/ve8313.c @@ -0,0 +1,215 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 + * + * Author: Scott Wood <scottwood@freescale.com> + * + * (C) Copyright 2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <libfdt.h> +#include <pci.h> +#include <mpc83xx.h> +#include <ns16550.h> +#include <nand.h> + +#include <asm/bitops.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern void disable_addr_trans (void); +extern void enable_addr_trans (void); + +int checkboard(void) +{ + puts("Board: ve8313\n"); + return 0; +} + +static long fixed_sdram(void) +{ + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; + +#ifndef CONFIG_SYS_RAMBOOT + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + u32 msize_log2 = __ilog2(msize); + + out_be32(&im->sysconf.ddrlaw[0].bar, + (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000)); + out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1))); + out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); + + /* + * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], + * or the DDR2 controller may fail to initialize correctly. + */ + __udelay(50000); + + out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); + out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG); + + /* Currently we use only one CS, so disable the other bank. */ + out_be32(&im->ddr.cs_config[1], 0); + + out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); + out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + + out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG); + + out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2); + out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2); + + out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); + sync(); + + /* enable DDR controller */ + setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); + + /* now check the real size */ + disable_addr_trans (); + msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize); + enable_addr_trans (); +#endif + + return msize; +} + +phys_size_t initdram(int board_type) +{ + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile fsl_lbus_t *lbc = &im->lbus; + u32 msize; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + msize = fixed_sdram(); + + /* Local Bus setup lbcr and mrtpr */ + out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); + out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); + sync(); + + /* return total bus SDRAM size(bytes) -- DDR */ + return msize; +} + +#define VE8313_WDT_EN 0x00020000 +#define VE8313_WDT_TRIG 0x00040000 + +int board_early_init_f (void) +{ + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio; + +#if defined(CONFIG_HW_WATCHDOG) + /* enable WDT */ + clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG); +#else + /* disable WDT */ + setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG); +#endif + /* set WDT pins as output */ + setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG); + + return 0; +} + +#if defined(CONFIG_HW_WATCHDOG) +void hw_watchdog_reset(void) +{ + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio; + unsigned long reg; + + reg = in_be32(&gpio->dat); + if (reg & VE8313_WDT_TRIG) + clrbits_be32(&gpio->dat, VE8313_WDT_TRIG); + else + setbits_be32(&gpio->dat, VE8313_WDT_TRIG); +} +#endif + + +#if defined(CONFIG_PCI) +static struct pci_region pci_regions[] = { + { + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + struct pci_region *reg[] = { pci_regions }; + int warmboot; + + /* Enable all 3 PCI_CLK_OUTPUTs. */ + setbits_be32(&clk->occr, 0xe0000000); + + /* + * Configure PCI Local Access Windows + */ + out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR); + out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR); + out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB); + + warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; + + mpc83xx_pci_init(1, reg, warmboot); +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif diff --git a/board/altera/ep1s10/config.mk b/board/vpac270/Makefile index dab2740..0f3eacd 100644 --- a/board/altera/ep1s10/config.mk +++ b/board/vpac270/Makefile @@ -1,6 +1,7 @@ + # -# (C) Copyright 2005, Psyent Corporation <www.psyent.com> -# Scott McNutt <smcnutt@psyent.com> +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this # project. @@ -21,11 +22,27 @@ # MA 02111-1307 USA # -TEXT_BASE = 0x01fc0000 +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := vpac270.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include +-include .depend -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif +######################################################################### diff --git a/board/vpac270/config.mk b/board/vpac270/config.mk new file mode 100644 index 0000000..1d650ac --- /dev/null +++ b/board/vpac270/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xa1000000 diff --git a/board/altera/ep1c20/ep1c20.c b/board/vpac270/lowlevel_init.S index 82900f7..ec0d12c 100644 --- a/board/altera/ep1c20/ep1c20.c +++ b/board/vpac270/lowlevel_init.S @@ -1,6 +1,8 @@ /* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> + * Voipac PXA270 Lowlevel Hardware Initialization + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * * * See file CREDITS for list of people who contributed to this * project. @@ -21,32 +23,18 @@ * MA 02111-1307 USA */ -#include <common.h> -#include <netdev.h> - -int board_early_init_f (void) -{ - return 0; -} - -int checkboard (void) -{ - puts ("BOARD : Altera EP-1C20\n"); - return 0; -} +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> +#include <asm/arch/macro.h> -phys_size_t initdram (int board_type) -{ - return (0); -} +.globl lowlevel_init +lowlevel_init: + pxa_gpio_setup + pxa_wait_ticks 0x8000 + pxa_mem_setup + pxa_wakeup + pxa_intr_setup + pxa_clock_setup -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif + mov pc, lr diff --git a/board/vpac270/u-boot.lds b/board/vpac270/u-boot.lds new file mode 100644 index 0000000..58c371d --- /dev/null +++ b/board/vpac270/u-boot.lds @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c new file mode 100644 index 0000000..48e93ab --- /dev/null +++ b/board/vpac270/vpac270.c @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/hardware.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations + */ +extern struct serial_device serial_ffuart_device; +extern struct serial_device serial_btuart_device; +extern struct serial_device serial_stuart_device; + +struct serial_device *default_serial_console (void) +{ + return &serial_ffuart_device; +} + +int board_init (void) +{ + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of vpac270 */ + gd->bd->bi_arch_number = MACH_TYPE_VPAC270; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + + return 0; +} + +int usb_board_init(void) +{ + UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + + UHCHR |= UHCHR_FSBIR; + + while (UHCHR & UHCHR_FSBIR); + + UHCHR &= ~UHCHR_SSE; + UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); + + /* Clear any OTG Pin Hold */ + if (PSSR & PSSR_OTGPH) + PSSR |= PSSR_OTGPH; + + UHCRHDA &= ~(0x200); + UHCRHDA |= 0x100; + + /* Set port power control mask bits, only 3 ports. */ + UHCRHDB |= (0x7<<17); + + /* enable port 2 */ + UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; + + return 0; +} + +void usb_board_init_fail(void) +{ + return; +} + +void usb_board_stop(void) +{ + UHCHR |= UHCHR_FHR; + udelay(11); + UHCHR &= ~UHCHR_FHR; + + UHCCOMS |= 1; + udelay(10); + + CKEN &= ~CKEN10_USBHOST; + + return; +} + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + return dm9000_initialize(bis); +} +#endif diff --git a/board/xes/xpedite5170/xpedite5170.c b/board/xes/xpedite5170/xpedite5170.c index f4231a9..5822941 100644 --- a/board/xes/xpedite5170/xpedite5170.c +++ b/board/xes/xpedite5170/xpedite5170.c @@ -56,8 +56,6 @@ int checkboard(void) */ static void flash_cs_fixup(void) { - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - ccsr_lbc_t *lbc = &immap->im_lbc; int flash_sel; /* @@ -70,11 +68,11 @@ static void flash_cs_fixup(void) printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); if (flash_sel) { - out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM); - out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM); + set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); + set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); - out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM); - out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM); + set_lbc_br(1, CONFIG_SYS_BR0_PRELIM); + set_lbc_or(1, CONFIG_SYS_OR0_PRELIM); } } diff --git a/board/xes/xpedite5200/xpedite5200.c b/board/xes/xpedite5200/xpedite5200.c index 7109771..a2627f8 100644 --- a/board/xes/xpedite5200/xpedite5200.c +++ b/board/xes/xpedite5200/xpedite5200.c @@ -38,7 +38,7 @@ extern void ft_board_pci_setup(void *blob, bd_t *bd); int checkboard(void) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); char *s; @@ -65,7 +65,6 @@ int checkboard(void) static void flash_cs_fixup(void) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); int flash_sel; /* @@ -78,11 +77,11 @@ static void flash_cs_fixup(void) printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); if (flash_sel) { - out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM); - out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM); + set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); + set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); - out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM); - out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM); + set_lbc_br(1, CONFIG_SYS_BR0_PRELIM); + set_lbc_or(1, CONFIG_SYS_OR0_PRELIM); } } diff --git a/board/xes/xpedite5370/xpedite5370.c b/board/xes/xpedite5370/xpedite5370.c index 48d9fc8..2a060c2 100644 --- a/board/xes/xpedite5370/xpedite5370.c +++ b/board/xes/xpedite5370/xpedite5370.c @@ -58,7 +58,6 @@ int checkboard(void) static void flash_cs_fixup(void) { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); int flash_sel; /* @@ -71,11 +70,11 @@ static void flash_cs_fixup(void) printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); if (flash_sel) { - out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM); - out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM); + set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); + set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); - out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM); - out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM); + set_lbc_br(1, CONFIG_SYS_BR0_PRELIM); + set_lbc_or(1, CONFIG_SYS_OR0_PRELIM); } } diff --git a/board/altera/ep1s10/Makefile b/board/zipitz2/Makefile index acad2aa..2673835 100644 --- a/board/altera/ep1s10/Makefile +++ b/board/zipitz2/Makefile @@ -1,6 +1,9 @@ + +# +# Copyright (C) 2009 +# Marek Vasut <marek.vasut@gmail.com> # -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Heavily based on pxa255_idp platform # # See file CREDITS for list of people who contributed to this # project. @@ -22,22 +25,18 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif LIB = $(obj)lib$(BOARD).a -COMOBJS := ../common/AMDLV065D.o ../common/epled.o - -COBJS := $(BOARD).o $(COMOBJS) +COBJS := zipitz2.o +SOBJS := lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/zipitz2/config.mk b/board/zipitz2/config.mk new file mode 100644 index 0000000..1d650ac --- /dev/null +++ b/board/zipitz2/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xa1000000 diff --git a/board/altera/ep1s10/ep1s10.c b/board/zipitz2/lowlevel_init.S index cf886da..82a52e8 100644 --- a/board/altera/ep1s10/ep1s10.c +++ b/board/zipitz2/lowlevel_init.S @@ -1,6 +1,8 @@ /* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> + * Aeronix Zipit Z2 Lowlevel Hardware Initialization + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * * * See file CREDITS for list of people who contributed to this * project. @@ -21,32 +23,18 @@ * MA 02111-1307 USA */ -#include <common.h> -#include <netdev.h> - -int board_early_init_f (void) -{ - return 0; -} - -int checkboard (void) -{ - puts ("BOARD : Altera EP-1S10\n"); - return 0; -} +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> +#include <asm/arch/macro.h> -phys_size_t initdram (int board_type) -{ - return (0); -} +.globl lowlevel_init +lowlevel_init: + pxa_gpio_setup + pxa_wait_ticks 0x8000 + pxa_mem_setup + pxa_wakeup + pxa_intr_setup + pxa_clock_setup -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif + mov pc, lr diff --git a/board/zipitz2/u-boot.lds b/board/zipitz2/u-boot.lds new file mode 100644 index 0000000..fb4358b --- /dev/null +++ b/board/zipitz2/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c new file mode 100644 index 0000000..14d1d76 --- /dev/null +++ b/board/zipitz2/zipitz2.c @@ -0,0 +1,213 @@ +/* + * Copyright (C) 2009 + * Marek Vasut <marek.vasut@gmail.com> + * + * Heavily based on pxa255_idp platform + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <serial.h> +#include <asm/arch/hardware.h> +#include <spi.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CMD_SPI +void lcd_start(void); +#else +inline void lcd_start(void) {}; +#endif + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of Lubbock-Board */ + gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + /* Enable LCD */ + lcd_start(); + + return 0; +} + +int board_late_init(void) +{ + setenv("stdout", "serial"); + setenv("stderr", "serial"); + return 0; +} + +struct serial_device *default_serial_console (void) +{ + return &serial_stuart_device; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +#ifdef CONFIG_CMD_SPI + +struct { + unsigned char reg; + unsigned short data; + unsigned char mdelay; +} lcd_data[] = { + { 0x07, 0x0000, 0 }, + { 0x13, 0x0000, 10 }, + { 0x11, 0x3004, 0 }, + { 0x14, 0x200F, 0 }, + { 0x10, 0x1a20, 0 }, + { 0x13, 0x0040, 50 }, + { 0x13, 0x0060, 0 }, + { 0x13, 0x0070, 200 }, + { 0x01, 0x0127, 0 }, + { 0x02, 0x0700, 0 }, + { 0x03, 0x1030, 0 }, + { 0x08, 0x0208, 0 }, + { 0x0B, 0x0620, 0 }, + { 0x0C, 0x0110, 0 }, + { 0x30, 0x0120, 0 }, + { 0x31, 0x0127, 0 }, + { 0x32, 0x0000, 0 }, + { 0x33, 0x0503, 0 }, + { 0x34, 0x0727, 0 }, + { 0x35, 0x0124, 0 }, + { 0x36, 0x0706, 0 }, + { 0x37, 0x0701, 0 }, + { 0x38, 0x0F00, 0 }, + { 0x39, 0x0F00, 0 }, + { 0x40, 0x0000, 0 }, + { 0x41, 0x0000, 0 }, + { 0x42, 0x013f, 0 }, + { 0x43, 0x0000, 0 }, + { 0x44, 0x013f, 0 }, + { 0x45, 0x0000, 0 }, + { 0x46, 0xef00, 0 }, + { 0x47, 0x013f, 0 }, + { 0x48, 0x0000, 0 }, + { 0x07, 0x0015, 30 }, + { 0x07, 0x0017, 0 }, + { 0x20, 0x0000, 0 }, + { 0x21, 0x0000, 0 }, + { 0x22, 0x0000, 0 }, +}; + +void zipitz2_spi_sda(int set) +{ + /* GPIO 13 */ + if (set) + GPSR0 = (1 << 13); + else + GPCR0 = (1 << 13); +} + +void zipitz2_spi_scl(int set) +{ + /* GPIO 22 */ + if (set) + GPCR0 = (1 << 22); + else + GPSR0 = (1 << 22); +} + +unsigned char zipitz2_spi_read(void) +{ + /* GPIO 40 */ + return !!(GPLR1 & (1 << 8)); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + /* Always valid */ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* GPIO 88 low */ + GPCR2 = (1 << 24); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* GPIO 88 high */ + GPSR2 = (1 << 24); + +} + +void lcd_start(void) +{ + int i; + unsigned char reg[3] = { 0x74, 0x00, 0 }; + unsigned char data[3] = { 0x76, 0, 0 }; + unsigned char dummy[3] = { 0, 0, 0 }; + + /* PWM2 AF */ + GAFR0_L |= 0x00800000; + /* Enable clock to all PWM */ + CKEN |= 0x3; + /* Configure PWM2 */ + PWM_CTRL2 = 0x4f; + PWM_PWDUTY2 = 0x2ff; + PWM_PERVAL2 = 792; + + /* Toggle the reset pin to reset the LCD */ + GPSR0 = (1 << 19); + udelay(100000); + GPCR0 = (1 << 19); + udelay(20000); + GPSR0 = (1 << 19); + udelay(20000); + + /* Program the LCD init sequence */ + for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) { + reg[0] = 0x74; + reg[1] = 0x0; + reg[2] = lcd_data[i].reg; + spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END); + + data[0] = 0x76; + data[1] = lcd_data[i].data >> 8; + data[2] = lcd_data[i].data & 0xff; + spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END); + + if (lcd_data[i].mdelay) + udelay(lcd_data[i].mdelay * 1000); + } + + GPSR0 = (1 << 11); +} +#endif @@ -52,6 +52,7 @@ actux3 arm ixp actux4 arm ixp ixdp425 arm ixp cerf250 arm pxa +colibri_pxa270 arm pxa cradle arm pxa csb226 arm pxa delta arm pxa @@ -61,6 +62,7 @@ lubbock arm pxa pleb2 arm pxa xaeniax arm pxa xm250 arm pxa +zipitz2 arm pxa B2 arm s3c44b0 - dave assabet arm sa1100 dnp1110 arm sa1100 @@ -75,9 +77,6 @@ M5272C3 m68k mcf52x2 m5272c3 freescale EP2500 m68k mcf52x2 ep2500 Mercury purple mips mips tb0229 mips mips -EP1C20 nios2 nios2 ep1c20 altera -EP1S10 nios2 nios2 ep1s10 altera -EP1S40 nios2 nios2 ep1s40 altera PCI5441 nios2 nios2 pci5441 psyent PK1C20 nios2 nios2 pk1c20 psyent P3G4 powerpc 74xx_7xx evb64260 @@ -132,6 +131,7 @@ ZPC1900 powerpc mpc8260 zpc1900 mgcoge powerpc mpc8260 - keymile SCM powerpc mpc8260 - siemens TQM8272 powerpc mpc8260 tqm8272 tqc +ve8313 powerpc mpc83xx ve8313 kmeter1 powerpc mpc83xx kmeter1 keymile MVBLM7 powerpc mpc83xx mvblm7 matrix_vision TQM834x powerpc mpc83xx tqm834x tqc @@ -284,6 +284,7 @@ favr-32-ezkit avr32 at32ap - earthlcd at32ap700x hammerhead avr32 at32ap - miromico at32ap700x bf518f-ezbrd blackfin blackfin bf526-ezbrd blackfin blackfin +bf527-ad7160-eval blackfin blackfin bf527-ezkit blackfin blackfin bf533-ezkit blackfin blackfin bf533-stamp blackfin blackfin @@ -333,6 +334,7 @@ ppmc8260 powerpc mpc8260 RPXsuper powerpc mpc8260 rpxsuper rsdproto powerpc mpc8260 MPC8266ADS powerpc mpc8260 mpc8266ads freescale +MPC8308RDB powerpc mpc83xx mpc8308rdb freescale MPC8323ERDB powerpc mpc83xx mpc8323erdb freescale MPC8349EMDS powerpc mpc83xx mpc8349emds freescale MPC837XERDB powerpc mpc83xx mpc837xerdb freescale @@ -344,6 +346,7 @@ MPC8560ADS powerpc mpc85xx mpc8560ads freescale MPC8568MDS powerpc mpc85xx mpc8568mds freescale XPEDITE5200 powerpc mpc85xx xpedite5200 xes XPEDITE5370 powerpc mpc85xx xpedite5370 xes +P1022DS powerpc mpc85xx p1022ds freescale sbc8641d powerpc mpc86xx MPC8610HPCD powerpc mpc86xx mpc8610hpcd freescale XPEDITE5170 powerpc mpc86xx xpedite5170 xes diff --git a/common/cmd_nand.c b/common/cmd_nand.c index ea80555..84b6272 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -4,6 +4,10 @@ * (c) 1999 Machine Vision Holdings, Inc. * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org> * + * Ported 'dynenv' to 'nand env.oob' command + * (C) 2010 Nanometrics, Inc. + * 'dynenv' -- Dynamic environment offset in NAND OOB + * (C) Copyright 2006-2007 OpenMoko, Inc. * Added 16-bit nand support * (C) 2004 Texas Instruments */ @@ -193,6 +197,90 @@ static void do_nand_status(nand_info_t *nand) } #endif +#ifdef CONFIG_ENV_OFFSET_OOB +unsigned long nand_env_oob_offset; + +int do_nand_env_oob(cmd_tbl_t *cmdtp, nand_info_t *nand, + int argc, char * const argv[]) +{ + int ret; + uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)]; + + char *cmd = argv[1]; + + if (!strcmp(cmd, "get")) { + ret = get_nand_env_oob(nand, &nand_env_oob_offset); + if (ret) + return 1; + + printf("0x%08lx\n", nand_env_oob_offset); + } else if (!strcmp(cmd, "set")) { + ulong addr; + size_t dummy_size; + struct mtd_oob_ops ops; + + if (argc < 3) + goto usage; + + if (arg_off_size(argc - 2, argv + 2, nand, &addr, + &dummy_size) < 0) { + printf("Offset or partition name expected\n"); + return 1; + } + + if (nand->oobavail < ENV_OFFSET_SIZE) { + printf("Insufficient available OOB bytes:\n" + "%d OOB bytes available but %d required for " + "env.oob support\n", + nand->oobavail, ENV_OFFSET_SIZE); + return 1; + } + + if ((addr & (nand->erasesize - 1)) != 0) { + printf("Environment offset must be block-aligned\n"); + return 1; + } + + ops.datbuf = NULL; + ops.mode = MTD_OOB_AUTO; + ops.ooboffs = 0; + ops.ooblen = ENV_OFFSET_SIZE; + ops.oobbuf = (void *) oob_buf; + + oob_buf[0] = ENV_OOB_MARKER; + oob_buf[1] = addr / nand->erasesize; + + ret = nand->write_oob(nand, ENV_OFFSET_SIZE, &ops); + if (ret) { + printf("Error writing OOB block 0\n"); + return ret; + } + + ret = get_nand_env_oob(nand, &nand_env_oob_offset); + if (ret) { + printf("Error reading env offset in OOB\n"); + return ret; + } + + if (addr != nand_env_oob_offset) { + printf("Verification of env offset in OOB failed: " + "0x%08lx expected but got 0x%08lx\n", + addr, nand_env_oob_offset); + return 1; + } + } else { + goto usage; + } + + return ret; + +usage: + cmd_usage(cmdtp); + return 1; +} + +#endif + static void nand_print_info(int idx) { nand_info_t *nand = &nand_info[idx]; @@ -272,9 +360,21 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 && strcmp(cmd, "scrub") != 0 && strcmp(cmd, "markbad") != 0 && strcmp(cmd, "biterr") != 0 && - strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 ) + strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 +#ifdef CONFIG_ENV_OFFSET_OOB + && strcmp(cmd, "env.oob") != 0 +#endif + ) goto usage; +#ifdef CONFIG_ENV_OFFSET_OOB + /* this command operates only on the first nand device */ + if (strcmp(cmd, "env.oob") == 0) { + return do_nand_env_oob(cmdtp, &nand_info[0], + argc - 1, argv + 1); + } +#endif + /* the following commands operate on the current device */ if (nand_curr_device < 0 || nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[nand_curr_device].name) { @@ -502,6 +602,13 @@ U_BOOT_CMD(nand, CONFIG_SYS_MAXARGS, 1, do_nand, " bring nand to lock state or display locked pages\n" "nand unlock [offset] [size] - unlock section" #endif +#ifdef CONFIG_ENV_OFFSET_OOB + "\n" + "nand env.oob - environment offset in OOB of block 0 of" + " first device.\n" + "nand env.oob set off|partition - set enviromnent offset\n" + "nand env.oob get - get environment offset" +#endif ); static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c index 94b8d58..908876c 100644 --- a/common/cmd_reginfo.c +++ b/common/cmd_reginfo.c @@ -33,6 +33,8 @@ extern void ppc4xx_reginfo(void); #include <mpc5xxx.h> #elif defined (CONFIG_MPC86xx) extern void mpc86xx_reginfo(void); +#elif defined(CONFIG_MPC85xx) +extern void mpc85xx_reginfo(void); #endif int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -183,6 +185,9 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #elif defined(CONFIG_MPC86xx) mpc86xx_reginfo(); +#elif defined(CONFIG_MPC85xx) + mpc85xx_reginfo(); + #elif defined(CONFIG_BLACKFIN) puts("\nSystem Configuration registers\n"); diff --git a/common/env_nand.c b/common/env_nand.c index 50bc111..a5e1038 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -38,6 +38,7 @@ #include <linux/stddef.h> #include <malloc.h> #include <nand.h> +#include <asm/errno.h> #if defined(CONFIG_CMD_SAVEENV) && defined(CONFIG_CMD_NAND) #define CMD_SAVEENV @@ -284,6 +285,38 @@ int readenv (size_t offset, u_char * buf) return 0; } +#ifdef CONFIG_ENV_OFFSET_OOB +int get_nand_env_oob(nand_info_t *nand, unsigned long *result) +{ + struct mtd_oob_ops ops; + uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)]; + int ret; + + ops.datbuf = NULL; + ops.mode = MTD_OOB_AUTO; + ops.ooboffs = 0; + ops.ooblen = ENV_OFFSET_SIZE; + ops.oobbuf = (void *) oob_buf; + + ret = nand->read_oob(nand, ENV_OFFSET_SIZE, &ops); + if (ret) { + printf("error reading OOB block 0\n"); + return ret; + } + + if (oob_buf[0] == ENV_OOB_MARKER) { + *result = oob_buf[1] * nand->erasesize; + } else if (oob_buf[0] == ENV_OOB_MARKER_OLD) { + *result = oob_buf[1]; + } else { + printf("No dynamic environment marker in OOB block 0\n"); + return -ENOENT; + } + + return 0; +} +#endif + #ifdef CONFIG_ENV_OFFSET_REDUND void env_relocate_spec (void) { @@ -353,6 +386,17 @@ void env_relocate_spec (void) #if !defined(ENV_IS_EMBEDDED) int ret; +#if defined(CONFIG_ENV_OFFSET_OOB) + ret = get_nand_env_oob(&nand_info[0], &nand_env_oob_offset); + /* If unable to read environment offset from NAND OOB then fall through + * to the normal environment reading code below + */ + if (!ret) + printf("Found Environment offset in OOB..\n"); + else + return use_default(); +#endif + ret = readenv(CONFIG_ENV_OFFSET, (u_char *) env_ptr); if (ret) return use_default(); diff --git a/common/fdt_support.c b/common/fdt_support.c index a8ac617..4d87135 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -474,135 +474,6 @@ void fdt_fixup_ethernet(void *fdt) } } -#ifdef CONFIG_HAS_FSL_DR_USB -void fdt_fixup_dr_usb(void *blob, bd_t *bd) -{ - char *mode; - char *type; - const char *compat = "fsl-usb2-dr"; - const char *prop_mode = "dr_mode"; - const char *prop_type = "phy_type"; - int node_offset; - int err; - - mode = getenv("usb_dr_mode"); - type = getenv("usb_phy_type"); - if (!mode && !type) - return; - - node_offset = fdt_node_offset_by_compatible(blob, 0, compat); - if (node_offset < 0) { - printf("WARNING: could not find compatible node %s: %s.\n", - compat, fdt_strerror(node_offset)); - return; - } - - if (mode) { - err = fdt_setprop(blob, node_offset, prop_mode, mode, - strlen(mode) + 1); - if (err < 0) - printf("WARNING: could not set %s for %s: %s.\n", - prop_mode, compat, fdt_strerror(err)); - } - - if (type) { - err = fdt_setprop(blob, node_offset, prop_type, type, - strlen(type) + 1); - if (err < 0) - printf("WARNING: could not set %s for %s: %s.\n", - prop_type, compat, fdt_strerror(err)); - } -} -#endif /* CONFIG_HAS_FSL_DR_USB */ - -#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) -/* - * update crypto node properties to a specified revision of the SEC - * called with sec_rev == 0 if not on an mpc8xxxE processor - */ -void fdt_fixup_crypto_node(void *blob, int sec_rev) -{ - const struct sec_rev_prop { - u32 sec_rev; - u32 num_channels; - u32 channel_fifo_len; - u32 exec_units_mask; - u32 descriptor_types_mask; - } sec_rev_prop_list [] = { - { 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */ - { 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */ - { 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */ - { 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */ - { 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */ - { 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */ - { 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */ - }; - char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) * - sizeof("fsl,secX.Y")]; - int crypto_node, sec_idx, err; - char *p; - u32 val; - - /* locate crypto node based on lowest common compatible */ - crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0"); - if (crypto_node == -FDT_ERR_NOTFOUND) - return; - - /* delete it if not on an E-processor */ - if (crypto_node > 0 && !sec_rev) { - fdt_del_node(blob, crypto_node); - return; - } - - /* else we got called for possible uprev */ - for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++) - if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev) - break; - - if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) { - puts("warning: unknown SEC revision number\n"); - return; - } - - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels); - err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); - - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask); - err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", &val, 4); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); - - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask); - err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); - - val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len); - err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); - - val = 0; - while (sec_idx >= 0) { - p = compat_strlist + val; - val += sprintf(p, "fsl,sec%d.%d", - (sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8, - sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1; - sec_idx--; - } - err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, val); - if (err < 0) - printf("WARNING: could not set crypto property: %s\n", - fdt_strerror(err)); -} -#endif /* defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) */ - /* Resize the fdt to its actual size + a bit of padding */ int fdt_resize(void *blob) { diff --git a/common/lcd.c b/common/lcd.c index 93ddedf..d854c21 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -41,7 +41,7 @@ #include <lcd.h> #include <watchdog.h> -#if defined(CONFIG_PXA250) +#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS #include <asm/byteorder.h> #endif @@ -503,7 +503,7 @@ void bitmap_plot (int x, int y) uchar *bmap; uchar *fb; ushort *fb16; -#if defined(CONFIG_PXA250) +#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS struct pxafb_info *fbi = &panel_info.pxa; #elif defined(CONFIG_MPC823) volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; @@ -519,7 +519,7 @@ void bitmap_plot (int x, int y) if (NBITS(panel_info.vl_bpix) < 12) { /* Leave room for default color map */ -#if defined(CONFIG_PXA250) +#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS cmap = (ushort *)fbi->palette; #elif defined(CONFIG_MPC823) cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]); @@ -615,7 +615,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) unsigned long pwidth = panel_info.vl_col; unsigned colors, bpix, bmp_bpix; unsigned long compression; -#if defined(CONFIG_PXA250) +#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS struct pxafb_info *fbi = &panel_info.pxa; #elif defined(CONFIG_MPC823) volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; @@ -656,7 +656,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) #if !defined(CONFIG_MCC200) /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */ if (bmp_bpix == 8) { -#if defined(CONFIG_PXA250) +#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS cmap = (ushort *)fbi->palette; #elif defined(CONFIG_MPC823) cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]); @@ -745,7 +745,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) WATCHDOG_RESET(); for (j = 0; j < width; j++) { if (bpix != 16) { -#if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD) +#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS || defined(CONFIG_ATMEL_LCD) *(fb++) = *(bmap++); #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200) *(fb++) = 255 - *(bmap++); diff --git a/doc/README.designware_eth b/doc/README.designware_eth new file mode 100644 index 0000000..25ec6bd --- /dev/null +++ b/doc/README.designware_eth @@ -0,0 +1,25 @@ +This driver supports Designware Ethernet Controller provided by Synopsis. + +The driver is enabled by CONFIG_DESIGNWARE_ETH. + +The driver has been developed and tested on SPEAr platforms. By default, the +MDIO interface works at 100/Full. #defining the below options in board +configuration file changes this behavior. + +Call an subroutine from respective board/.../board.c +designware_initialize(u32 id, ulong base_addr, u32 phy_addr); + +The various options suported by the driver are +1. CONFIG_DW_ALTDESCRIPTOR + Define this to use the Alternate/Enhanced Descriptor configurations. +1. CONFIG_DW_AUTONEG + Define this to autonegotiate with the host before proceeding with mac + level configuration. This obviates the definitions of CONFIG_DW_SPEED10M + and CONFIG_DW_DUPLEXHALF. +2. CONFIG_DW_SPEED10M + Define this to change the default behavior from 100Mbps to 10Mbps. +3. CONFIG_DW_DUPLEXHALF + Define this to change the default behavior from Full Duplex to Half. +4. CONFIG_DW_SEARCH_PHY + Define this to search the phy address. This would overwrite the value + passed as 3rd arg from designware_initialize routine. diff --git a/drivers/block/pata_bfin.c b/drivers/block/pata_bfin.c index f16dabe..847c032 100644 --- a/drivers/block/pata_bfin.c +++ b/drivers/block/pata_bfin.c @@ -14,6 +14,7 @@ #include <asm/byteorder.h> #include <asm/io.h> #include <asm/errno.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/pata.h> #include <ata.h> #include <libata.h> @@ -769,19 +770,17 @@ static int bfin_ata_reset_port(struct ata_port *ap) */ static int bfin_config_atapi_gpio(struct ata_port *ap) { - bfin_write_PORTH_FER(bfin_read_PORTH_FER() | 0x4); - bfin_write_PORTH_MUX(bfin_read_PORTH_MUX() & ~0x30); - bfin_write_PORTH_DIR_SET(0x4); - - bfin_write_PORTJ_FER(0x7f8); - bfin_write_PORTJ_MUX(bfin_read_PORTI_MUX() & ~0x3fffc0); - bfin_write_PORTJ_DIR_SET(0x5f8); - bfin_write_PORTJ_DIR_CLEAR(0x200); - bfin_write_PORTJ_INEN(0x200); - - bfin_write_PINT2_ASSIGN(0x0707); - bfin_write_PINT2_MASK_SET(0x200); - SSYNC(); + const unsigned short pins[] = { + P_ATAPI_RESET, P_ATAPI_DIOR, P_ATAPI_DIOW, P_ATAPI_CS0, + P_ATAPI_CS1, P_ATAPI_DMACK, P_ATAPI_DMARQ, P_ATAPI_INTRQ, + P_ATAPI_IORDY, P_ATAPI_D0A, P_ATAPI_D1A, P_ATAPI_D2A, + P_ATAPI_D3A, P_ATAPI_D4A, P_ATAPI_D5A, P_ATAPI_D6A, + P_ATAPI_D7A, P_ATAPI_D8A, P_ATAPI_D9A, P_ATAPI_D10A, + P_ATAPI_D11A, P_ATAPI_D12A, P_ATAPI_D13A, P_ATAPI_D14A, + P_ATAPI_D15A, P_ATAPI_A0A, P_ATAPI_A1A, P_ATAPI_A2A, 0, + }; + + peripheral_request_list(pins, "pata_bfin"); return 0; } diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 8255175..628bd59 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -50,86 +50,61 @@ DECLARE_GLOBAL_DATA_PTR; #endif #ifdef CONFIG_FSL_CORENET -void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) -{ - volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); - - gd->used_laws |= (1 << idx); +#define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR) +#define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar) +#define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh) +#define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl) +#define LAWBAR_SHIFT 0 +#else +#define LAW_BASE (CONFIG_SYS_IMMR + 0xc08) +#define LAWAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x + 2) +#define LAWBAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x) +#define LAWBAR_SHIFT 12 +#endif - out_be32(&ccm->law[idx].lawar, 0); - out_be32(&ccm->law[idx].lawbarh, ((u64)addr >> 32)); - out_be32(&ccm->law[idx].lawbarl, addr & 0xffffffff); - out_be32(&ccm->law[idx].lawar, LAW_EN | ((u32)id << 20) | (u32)sz); - /* Read back so that we sync the writes */ - in_be32(&ccm->law[idx].lawar); -} - -void disable_law(u8 idx) +static inline phys_addr_t get_law_base_addr(int idx) { - volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); - - gd->used_laws &= ~(1 << idx); - - out_be32(&ccm->law[idx].lawar, 0); - out_be32(&ccm->law[idx].lawbarh, 0); - out_be32(&ccm->law[idx].lawbarl, 0); - - /* Read back so that we sync the writes */ - in_be32(&ccm->law[idx].lawar); - - return; +#ifdef CONFIG_FSL_CORENET + return (phys_addr_t) + ((u64)in_be32(LAWBARH_ADDR(idx)) << 32) | + in_be32(LAWBARL_ADDR(idx)); +#else + return (phys_addr_t)in_be32(LAWBAR_ADDR(idx)) << LAWBAR_SHIFT; +#endif } -#ifndef CONFIG_NAND_SPL -static int get_law_entry(u8 i, struct law_entry *e) +static inline void set_law_base_addr(int idx, phys_addr_t addr) { - volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); - u32 lawar; - - lawar = in_be32(&ccm->law[i].lawar); - - if (!(lawar & LAW_EN)) - return 0; - - e->addr = ((u64)in_be32(&ccm->law[i].lawbarh) << 32) | - in_be32(&ccm->law[i].lawbarl); - e->size = lawar & 0x3f; - e->trgt_id = (lawar >> 20) & 0xff; - - return 1; -} -#endif +#ifdef CONFIG_FSL_CORENET + out_be32(LAWBARL_ADDR(idx), addr & 0xffffffff); + out_be32(LAWBARH_ADDR(idx), (u64)addr >> 32); #else + out_be32(LAWBAR_ADDR(idx), addr >> LAWBAR_SHIFT); +#endif +} + void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { - volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); - volatile u32 *lawbar = base + 8 * idx; - volatile u32 *lawar = base + 8 * idx + 2; - gd->used_laws |= (1 << idx); - out_be32(lawar, 0); - out_be32(lawbar, addr >> 12); - out_be32(lawar, LAW_EN | ((u32)id << 20) | (u32)sz); + out_be32(LAWAR_ADDR(idx), 0); + set_law_base_addr(idx, addr); + out_be32(LAWAR_ADDR(idx), LAW_EN | ((u32)id << 20) | (u32)sz); /* Read back so that we sync the writes */ - in_be32(lawar); + in_be32(LAWAR_ADDR(idx)); } void disable_law(u8 idx) { - volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); - volatile u32 *lawbar = base + 8 * idx; - volatile u32 *lawar = base + 8 * idx + 2; - gd->used_laws &= ~(1 << idx); - out_be32(lawar, 0); - out_be32(lawbar, 0); + out_be32(LAWAR_ADDR(idx), 0); + set_law_base_addr(idx, 0); /* Read back so that we sync the writes */ - in_be32(lawar); + in_be32(LAWAR_ADDR(idx)); return; } @@ -137,24 +112,20 @@ void disable_law(u8 idx) #ifndef CONFIG_NAND_SPL static int get_law_entry(u8 i, struct law_entry *e) { - volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); - volatile u32 *lawbar = base + 8 * i; - volatile u32 *lawar = base + 8 * i + 2; - u32 temp; + u32 lawar; - temp = in_be32(lawar); + lawar = in_be32(LAWAR_ADDR(i)); - if (!(temp & LAW_EN)) + if (!(lawar & LAW_EN)) return 0; - e->addr = (u64)in_be32(lawbar) << 12; - e->size = temp & 0x3f; - e->trgt_id = (temp >> 20) & 0xff; + e->addr = get_law_base_addr(i); + e->size = lawar & 0x3f; + e->trgt_id = (lawar >> 20) & 0xff; return 1; } #endif -#endif int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { @@ -216,17 +187,23 @@ struct law_entry find_law(phys_addr_t addr) void print_laws(void) { - volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); - volatile u32 *lawbar = base; - volatile u32 *lawar = base + 2; int i; + u32 lawar; printf("\nLocal Access Window Configuration\n"); - for(i = 0; i < FSL_HW_NUM_LAWS; i++) { - printf("\tLAWBAR%d : 0x%08x, LAWAR%d : 0x%08x\n", - i, in_be32(lawbar), i, in_be32(lawar)); - lawbar += 8; - lawar += 8; + for (i = 0; i < FSL_HW_NUM_LAWS; i++) { + lawar = in_be32(LAWAR_ADDR(i)); +#ifdef CONFIG_FSL_CORENET + printf("LAWBARH%02d: 0x%08x LAWBARL%02d: 0x%08x", + i, in_be32(LAWBARH_ADDR(i)), + i, in_be32(LAWBARL_ADDR(i))); +#else + printf("LAWBAR%02d: 0x%08x", i, in_be32(LAWBAR_ADDR(i))); +#endif + printf(" LAWAR0x%02d: 0x%08x\n", i, lawar); + printf("\t(EN: %d TGT: 0x%02x SIZE: ", + (lawar & LAW_EN) ? 1 : 0, (lawar >> 20) & 0xff); + print_size(lawar_size(lawar), ")\n"); } return; diff --git a/drivers/misc/gpio_led.c b/drivers/misc/gpio_led.c index acd6a90..3fedddc 100644 --- a/drivers/misc/gpio_led.c +++ b/drivers/misc/gpio_led.c @@ -2,26 +2,22 @@ * Status LED driver based on GPIO access conventions of Linux * * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Licensed under the GPL-2 or later. */ #include <common.h> #include <status_led.h> #include <asm/gpio.h> -/* assume led is active low */ - void __led_init(led_id_t mask, int state) { - gpio_direction_output(mask, (state == STATUS_LED_ON) ? 0 : 1); + gpio_request(mask, "gpio_led"); + gpio_direction_output(mask, state == STATUS_LED_ON); } void __led_set(led_id_t mask, int state) { - gpio_set_value(mask, (state == STATUS_LED_ON) ? 0 : 1); + gpio_set_value(mask, state == STATUS_LED_ON); } void __led_toggle(led_id_t mask) diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c index f9d560a..4a77779 100644 --- a/drivers/mmc/bfin_sdh.c +++ b/drivers/mmc/bfin_sdh.c @@ -15,6 +15,7 @@ #include <asm/errno.h> #include <asm/byteorder.h> #include <asm/blackfin.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/sdh.h> #include <asm/mach-common/bits/dma.h> @@ -41,11 +42,15 @@ # define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT # define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY # define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG +# define PORTMUX_PINS \ + { P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 } #elif defined(__ADSPBF54x__) # define bfin_write_DMA_START_ADDR bfin_write_DMA22_START_ADDR # define bfin_write_DMA_X_COUNT bfin_write_DMA22_X_COUNT # define bfin_write_DMA_X_MODIFY bfin_write_DMA22_X_MODIFY # define bfin_write_DMA_CONFIG bfin_write_DMA22_CONFIG +# define PORTMUX_PINS \ + { P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 } #else # error no support for this proc yet #endif @@ -208,18 +213,13 @@ static void bfin_sdh_set_ios(struct mmc *mmc) static int bfin_sdh_init(struct mmc *mmc) { - + const unsigned short pins[] = PORTMUX_PINS; u16 pwr_ctl = 0; -/* Initialize sdh controller */ + + /* Initialize sdh controller */ + peripheral_request_list(pins, "bfin_sdh"); #if defined(__ADSPBF54x__) bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1); - bfin_write_PORTC_FER(bfin_read_PORTC_FER() | 0x3F00); - bfin_write_PORTC_MUX(bfin_read_PORTC_MUX() & ~0xFFF0000); -#elif defined(__ADSPBF51x__) - bfin_write_PORTG_FER(bfin_read_PORTG_FER() | 0x01F8); - bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~0x3FC) | 0x154); -#else -# error no portmux for this proc yet #endif bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN); /* Disable card detect pin */ diff --git a/drivers/mtd/nand/bfin_nand.c b/drivers/mtd/nand/bfin_nand.c index 6d3d450..3ee060f 100644 --- a/drivers/mtd/nand/bfin_nand.c +++ b/drivers/mtd/nand/bfin_nand.c @@ -26,6 +26,7 @@ #include <nand.h> #include <asm/blackfin.h> +#include <asm/portmux.h> /* Bit masks for NFC_CTL */ @@ -337,6 +338,12 @@ static struct nand_ecclayout bootrom_ecclayout = { */ int board_nand_init(struct nand_chip *chip) { + const unsigned short pins[] = { + P_NAND_CE, P_NAND_RB, P_NAND_D0, P_NAND_D1, P_NAND_D2, + P_NAND_D3, P_NAND_D4, P_NAND_D5, P_NAND_D6, P_NAND_D7, + P_NAND_WE, P_NAND_RE, P_NAND_CLE, P_NAND_ALE, 0, + }; + pr_stamp(); /* set width/ecc/timings/etc... */ @@ -347,14 +354,7 @@ int board_nand_init(struct nand_chip *chip) bfin_write_NFC_IRQSTAT(0xffff); /* enable GPIO function enable register */ -#ifdef __ADSPBF54x__ - bfin_write_PORTJ_FER(bfin_read_PORTJ_FER() | 6); -#elif defined(__ADSPBF52x__) - bfin_write_PORTH_FER(bfin_read_PORTH_FER() | 0xFCFF); - bfin_write_PORTH_MUX(0); -#else -# error no support for this variant -#endif + peripheral_request_list(pins, "bfin_nand"); chip->cmd_ctrl = bfin_nfc_cmd_ctrl; chip->read_buf = bfin_nfc_read_buf; diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 146e9bf..acdb431 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -75,7 +75,7 @@ struct fsl_elbc_ctrl { struct fsl_elbc_mtd *chips[MAX_BANKS]; /* device info */ - fsl_lbus_t *regs; + fsl_lbc_t *regs; u8 __iomem *addr; /* Address of assigned FCM buffer */ unsigned int page; /* Last page written to / read from */ unsigned int read_bytes; /* Number of bytes read during command */ @@ -171,7 +171,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) struct nand_chip *chip = mtd->priv; struct fsl_elbc_mtd *priv = chip->priv; struct fsl_elbc_ctrl *ctrl = priv->ctrl; - fsl_lbus_t *lbc = ctrl->regs; + fsl_lbc_t *lbc = ctrl->regs; int buf_num; ctrl->page = page_addr; @@ -211,7 +211,7 @@ static int fsl_elbc_run_command(struct mtd_info *mtd) struct nand_chip *chip = mtd->priv; struct fsl_elbc_mtd *priv = chip->priv; struct fsl_elbc_ctrl *ctrl = priv->ctrl; - fsl_lbus_t *lbc = ctrl->regs; + fsl_lbc_t *lbc = ctrl->regs; long long end_tick; u32 ltesr; @@ -261,7 +261,7 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob) { struct fsl_elbc_mtd *priv = chip->priv; struct fsl_elbc_ctrl *ctrl = priv->ctrl; - fsl_lbus_t *lbc = ctrl->regs; + fsl_lbc_t *lbc = ctrl->regs; if (priv->page_size) { out_be32(&lbc->fir, @@ -295,7 +295,7 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, struct nand_chip *chip = mtd->priv; struct fsl_elbc_mtd *priv = chip->priv; struct fsl_elbc_ctrl *ctrl = priv->ctrl; - fsl_lbus_t *lbc = ctrl->regs; + fsl_lbc_t *lbc = ctrl->regs; ctrl->use_mdr = 0; @@ -633,7 +633,7 @@ static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip) { struct fsl_elbc_mtd *priv = chip->priv; struct fsl_elbc_ctrl *ctrl = priv->ctrl; - fsl_lbus_t *lbc = ctrl->regs; + fsl_lbc_t *lbc = ctrl->regs; if (ctrl->status != LTESR_CC) return NAND_STATUS_FAIL; @@ -697,11 +697,7 @@ static void fsl_elbc_ctrl_init(void) if (!elbc_ctrl) return; -#ifdef CONFIG_MPC85xx - elbc_ctrl->regs = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR; -#else - elbc_ctrl->regs = &((immap_t *)CONFIG_SYS_IMMR)->lbus; -#endif + elbc_ctrl->regs = LBC_BASE_ADDR; /* clear event registers */ out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK); diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 7171bdd..ed1c9c9 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2652,8 +2652,12 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, } } - if (!type) + if (!type) { + printk(KERN_INFO "%s: unknown NAND device: Manufacturer ID:" + " 0x%02x, Chip ID: 0x%02x\n", __func__, + *maf_id, dev_id); return ERR_PTR(-ENODEV); + } if (!mtd->name) mtd->name = type->name; diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 077c305..25b22ec 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -83,6 +83,7 @@ struct nand_flash_dev nand_flash_ids[] = { /* 1 Gigabit */ {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS}, {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS}, + {"NAND 128MiB 3,3V 8-bit", 0xD1, 0, 128, 0, LP_OPTIONS}, {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16}, {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16}, diff --git a/drivers/mtd/nand/nand_plat.c b/drivers/mtd/nand/nand_plat.c index b35492b..37a0206 100644 --- a/drivers/mtd/nand/nand_plat.c +++ b/drivers/mtd/nand/nand_plat.c @@ -16,6 +16,10 @@ #include <common.h> #include <asm/io.h> +#ifdef NAND_PLAT_GPIO_DEV_READY +# include <asm/gpio.h> +# define NAND_PLAT_DEV_READY(chip) gpio_get_value(NAND_PLAT_GPIO_DEV_READY) +#endif #include <nand.h> @@ -43,7 +47,14 @@ static int plat_dev_ready(struct mtd_info *mtd) int board_nand_init(struct nand_chip *nand) { +#ifdef NAND_PLAT_GPIO_DEV_READY + gpio_request(NAND_PLAT_GPIO_DEV_READY, "nand-plat"); + gpio_direction_input(NAND_PLAT_GPIO_DEV_READY); +#endif + +#ifdef NAND_PLAT_INIT NAND_PLAT_INIT(); +#endif nand->cmd_ctrl = plat_cmd_ctrl; nand->dev_ready = plat_dev_ready; diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index 2fac641..144b851 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -1095,6 +1095,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) miiphy_write (dev->name, reg, 0x18, 0x4101); miiphy_write (dev->name, reg, 0x09, 0x0e00); miiphy_write (dev->name, reg, 0x04, 0x01e1); +#if defined(CONFIG_M88E1111_DISABLE_FIBER) + miiphy_read(dev->name, reg, 0x1b, ®_short); + reg_short |= 0x8000; + miiphy_write(dev->name, reg, 0x1b, reg_short); +#endif #endif #if defined(CONFIG_M88E1112_PHY) if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) { diff --git a/drivers/net/Makefile b/drivers/net/Makefile index b75c02f..218eeff 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o COBJS-$(CONFIG_CS8900) += cs8900.o COBJS-$(CONFIG_TULIP) += dc2114x.o +COBJS-$(CONFIG_DESIGNWARE_ETH) += designware.o COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o COBJS-$(CONFIG_DNET) += dnet.o COBJS-$(CONFIG_E1000) += e1000.o @@ -46,13 +47,13 @@ COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o COBJS-$(CONFIG_FTMAC100) += ftmac100.o COBJS-$(CONFIG_GRETH) += greth.o COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o -COBJS-$(CONFIG_KIRKWOOD_EGIGA) += kirkwood_egiga.o COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o COBJS-$(CONFIG_LAN91C96) += lan91c96.o COBJS-$(CONFIG_MACB) += macb.o COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o +COBJS-$(CONFIG_MVGBE) += mvgbe.o COBJS-$(CONFIG_NATSEMI) += natsemi.o COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c index 2399569..245da12 100644 --- a/drivers/net/at91_emac.c +++ b/drivers/net/at91_emac.c @@ -53,6 +53,10 @@ Please decrease the CONFIG_SYS_RX_ETH_BUFFER value #endif +#ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR +#define CONFIG_DRIVER_AT91EMAC_PHYADDR 0 +#endif + /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */ #if (AT91C_MASTER_CLOCK > 80000000) #define HCLK_DIV AT91_EMAC_CFG_MCLK_64 @@ -198,12 +202,15 @@ static int at91emac_phy_reset(struct eth_device *netdev) emac = (at91_emac_t *) netdev->iobase; adv = ADVERTISE_CSMA | ADVERTISE_ALL; - at91emac_write(emac, 0, MII_ADVERTISE, adv); + at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, + MII_ADVERTISE, adv); VERBOSEP("%s: Starting autonegotiation...\n", netdev->name); - at91emac_write(emac, 0, MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART)); + at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR, + (BMCR_ANENABLE | BMCR_ANRESTART)); for (i = 0; i < 100000 / 100; i++) { - at91emac_read(emac, 0, MII_BMSR, &status); + at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, + MII_BMSR, &status); if (status & BMSR_ANEGCOMPLETE) break; udelay(100); @@ -229,13 +236,15 @@ static int at91emac_phy_init(struct eth_device *netdev) emac = (at91_emac_t *) netdev->iobase; /* Check if the PHY is up to snuff... */ - at91emac_read(emac, 0, MII_PHYSID1, &phy_id); + at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, + MII_PHYSID1, &phy_id); if (phy_id == 0xffff) { printf("%s: No PHY present\n", netdev->name); return 1; } - at91emac_read(emac, 0, MII_BMSR, &status); + at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, + MII_BMSR, &status); if (!(status & BMSR_LSTATUS)) { /* Try to re-negotiate if we don't have link already. */ @@ -243,7 +252,8 @@ static int at91emac_phy_init(struct eth_device *netdev) return 2; for (i = 0; i < 100000 / 100; i++) { - at91emac_read(emac, 0, MII_BMSR, &status); + at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, + MII_BMSR, &status); if (status & BMSR_LSTATUS) break; udelay(100); @@ -253,8 +263,10 @@ static int at91emac_phy_init(struct eth_device *netdev) VERBOSEP("%s: link down\n", netdev->name); return 3; } else { - at91emac_read(emac, 0, MII_ADVERTISE, &adv); - at91emac_read(emac, 0, MII_LPA, &lpa); + at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, + MII_ADVERTISE, &adv); + at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, + MII_LPA, &lpa); media = mii_nway_result(lpa & adv); speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0); @@ -271,7 +283,7 @@ int at91emac_UpdateLinkSpeed(at91_emac_t *emac) { unsigned short stat1; - at91emac_read(emac, 0, MII_BMSR, &stat1); + at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1); if (!(stat1 & BMSR_LSTATUS)) /* link status up? */ return 1; @@ -348,14 +360,6 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd) writel(1 << AT91_ID_EMAC, &pmc->pcer); writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl); - DEBUG_AT91EMAC("init MAC-ADDR %x%x \n", - cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), - cpu_to_le32(*((u32 *)netdev->enetaddr))); - writel(cpu_to_le32(*((u32 *)netdev->enetaddr)), &emac->sa2l); - writel(cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), &emac->sa2h); - DEBUG_AT91EMAC("init MAC-ADDR %x%x \n", - readl(&emac->sa2h), readl(&emac->sa2l)); - /* Init Ethernet buffers */ for (i = 0; i < RBF_FRAMEMAX; i++) { dev->rbfdt[i].addr = (unsigned long) NetRxPackets[i]; @@ -372,7 +376,7 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd) value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC | HCLK_DIV; #ifdef CONFIG_RMII - value |= AT91C_EMAC_RMII; + value |= AT91_EMAC_CFG_RMII; #endif writel(value, &emac->cfg); @@ -456,6 +460,25 @@ static int at91emac_recv(struct eth_device *netdev) return 0; } +static int at91emac_write_hwaddr(struct eth_device *netdev) +{ + emac_device *dev; + at91_emac_t *emac; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + emac = (at91_emac_t *) netdev->iobase; + dev = (emac_device *) netdev->priv; + + writel(1 << AT91_ID_EMAC, &pmc->pcer); + DEBUG_AT91EMAC("init MAC-ADDR %x%x \n", + cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), + cpu_to_le32(*((u32 *)netdev->enetaddr))); + writel(cpu_to_le32(*((u32 *)netdev->enetaddr)), &emac->sa2l); + writel(cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), &emac->sa2h); + DEBUG_AT91EMAC("init MAC-ADDR %x%x \n", + readl(&emac->sa2h), readl(&emac->sa2l)); + return 0; +} + int at91emac_register(bd_t *bis, unsigned long iobase) { emac_device *emac; @@ -488,6 +511,7 @@ int at91emac_register(bd_t *bis, unsigned long iobase) dev->halt = at91emac_halt; dev->send = at91emac_send; dev->recv = at91emac_recv; + dev->write_hwaddr = at91emac_write_hwaddr; eth_register(dev); diff --git a/drivers/net/ax88180.c b/drivers/net/ax88180.c index d843397..bc3e6ad 100644 --- a/drivers/net/ax88180.c +++ b/drivers/net/ax88180.c @@ -41,6 +41,7 @@ #include <command.h> #include <net.h> #include <malloc.h> +#include <linux/mii.h> #include "ax88180.h" /* @@ -50,9 +51,9 @@ */ static void ax88180_rx_handler (struct eth_device *dev); static int ax88180_phy_initial (struct eth_device *dev); -static void ax88180_meidia_config (struct eth_device *dev); -static unsigned long get_CicadaPHY_meida_mode (struct eth_device *dev); -static unsigned long get_MarvellPHY_meida_mode (struct eth_device *dev); +static void ax88180_media_config (struct eth_device *dev); +static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev); +static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev); static unsigned short ax88180_mdio_read (struct eth_device *dev, unsigned long regaddr); static void ax88180_mdio_write (struct eth_device *dev, @@ -112,10 +113,10 @@ static int ax88180_phy_reset (struct eth_device *dev) { unsigned short delay_cnt = 500; - ax88180_mdio_write (dev, BMCR, (PHY_RESET | AUTONEG_EN)); + ax88180_mdio_write (dev, MII_BMCR, (BMCR_RESET | BMCR_ANENABLE)); /* Wait for the reset to complete, or time out (500 ms) */ - while (ax88180_mdio_read (dev, BMCR) & PHY_RESET) { + while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) { udelay (1000); if (--delay_cnt == 0) { printf ("Failed to reset PHY!\n"); @@ -255,52 +256,78 @@ static int ax88180_phy_initial (struct eth_device *dev) { struct ax88180_private *priv = (struct ax88180_private *)dev->priv; unsigned long tmp_regval; + unsigned short phyaddr; - /* Check avaliable PHY chipset */ - priv->PhyAddr = MARVELL_88E1111_PHYADDR; - priv->PhyID0 = ax88180_mdio_read (dev, PHYIDR0); - - if (priv->PhyID0 == MARVELL_88E1111_PHYIDR0) { - - debug ("ax88180: Found Marvell 88E1111 PHY." - " (PHY Addr=0x%x)\n", priv->PhyAddr); - - tmp_regval = ax88180_mdio_read (dev, M88_EXT_SSR); - if ((tmp_regval & HWCFG_MODE_MASK) == RGMII_COPPER_MODE) { + /* Search for first avaliable PHY chipset */ +#ifdef CONFIG_PHY_ADDR + phyaddr = CONFIG_PHY_ADDR; +#else + for (phyaddr = 0; phyaddr < 32; ++phyaddr) +#endif + { + priv->PhyAddr = phyaddr; + priv->PhyID0 = ax88180_mdio_read(dev, MII_PHYSID1); + priv->PhyID1 = ax88180_mdio_read(dev, MII_PHYSID2); + + switch (priv->PhyID0) { + case MARVELL_ALASKA_PHYSID0: + debug("ax88180: Found Marvell Alaska PHY family." + " (PHY Addr=0x%x)\n", priv->PhyAddr); + + switch (priv->PhyID1) { + case MARVELL_88E1118_PHYSID1: + ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 2); + ax88180_mdio_write(dev, M88E1118_CR, + M88E1118_CR_DEFAULT); + ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 3); + ax88180_mdio_write(dev, M88E1118_LEDCTL, + M88E1118_LEDCTL_DEFAULT); + ax88180_mdio_write(dev, M88E1118_LEDMIX, + M88E1118_LEDMIX_LED050 | M88E1118_LEDMIX_LED150 | 0x15); + ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 0); + default: /* Default to 88E1111 Phy */ + tmp_regval = ax88180_mdio_read(dev, M88E1111_EXT_SSR); + if ((tmp_regval & HWCFG_MODE_MASK) != RGMII_COPPER_MODE) + ax88180_mdio_write(dev, M88E1111_EXT_SCR, + DEFAULT_EXT_SCR); + } - ax88180_mdio_write (dev, M88_EXT_SCR, DEFAULT_EXT_SCR); - if (ax88180_phy_reset (dev) < 0) + if (ax88180_phy_reset(dev) < 0) return 0; - ax88180_mdio_write (dev, M88_IER, LINK_CHANGE_INT); - } - } else { + ax88180_mdio_write(dev, M88_IER, LINK_CHANGE_INT); - priv->PhyAddr = CICADA_CIS8201_PHYADDR; - priv->PhyID0 = ax88180_mdio_read (dev, PHYIDR0); + return 1; - if (priv->PhyID0 == CICADA_CIS8201_PHYIDR0) { + case CICADA_CIS8201_PHYSID0: + debug("ax88180: Found CICADA CIS8201 PHY" + " chipset. (PHY Addr=0x%x)\n", priv->PhyAddr); - debug ("ax88180: Found CICADA CIS8201 PHY" - " chipset. (PHY Addr=0x%x)\n", priv->PhyAddr); - ax88180_mdio_write (dev, CIS_IMR, + ax88180_mdio_write(dev, CIS_IMR, (CIS_INT_ENABLE | LINK_CHANGE_INT)); /* Set CIS_SMI_PRIORITY bit before force the media mode */ - tmp_regval = - ax88180_mdio_read (dev, CIS_AUX_CTRL_STATUS); + tmp_regval = ax88180_mdio_read(dev, CIS_AUX_CTRL_STATUS); tmp_regval &= ~CIS_SMI_PRIORITY; - ax88180_mdio_write (dev, CIS_AUX_CTRL_STATUS, - tmp_regval); - } else { - printf ("ax88180: Unknown PHY chipset!!\n"); - return 0; + ax88180_mdio_write(dev, CIS_AUX_CTRL_STATUS, tmp_regval); + + return 1; + + case 0xffff: + /* No PHY at this addr */ + break; + + default: + printf("ax88180: Unknown PHY chipset %#x at addr %#x\n", + priv->PhyID0, priv->PhyAddr); + break; } } - return 1; + printf("ax88180: Unknown PHY chipset!!\n"); + return 0; } -static void ax88180_meidia_config (struct eth_device *dev) +static void ax88180_media_config (struct eth_device *dev) { struct ax88180_private *priv = (struct ax88180_private *)dev->priv; unsigned long bmcr_val, bmsr_val; @@ -310,20 +337,20 @@ static void ax88180_meidia_config (struct eth_device *dev) /* Waiting 2 seconds for PHY link stable */ for (i = 0; i < 20000; i++) { - bmsr_val = ax88180_mdio_read (dev, BMSR); - if (bmsr_val & LINKOK) { + bmsr_val = ax88180_mdio_read (dev, MII_BMSR); + if (bmsr_val & BMSR_LSTATUS) { break; } udelay (100); } - bmsr_val = ax88180_mdio_read (dev, BMSR); + bmsr_val = ax88180_mdio_read (dev, MII_BMSR); debug ("ax88180: BMSR=0x%04x\n", (unsigned int)bmsr_val); - if (bmsr_val & LINKOK) { - bmcr_val = ax88180_mdio_read (dev, BMCR); + if (bmsr_val & BMSR_LSTATUS) { + bmcr_val = ax88180_mdio_read (dev, MII_BMCR); - if (bmcr_val & AUTONEG_EN) { + if (bmcr_val & BMCR_ANENABLE) { /* * Waiting for Auto-negotiation completion, this may @@ -332,8 +359,8 @@ static void ax88180_meidia_config (struct eth_device *dev) debug ("ax88180: Auto-negotiation is " "enabled. Waiting for NWay completion..\n"); for (i = 0; i < 50000; i++) { - bmsr_val = ax88180_mdio_read (dev, BMSR); - if (bmsr_val & AUTONEG_COMPLETE) { + bmsr_val = ax88180_mdio_read (dev, MII_BMSR); + if (bmsr_val & BMSR_ANEGCOMPLETE) { break; } udelay (100); @@ -345,12 +372,16 @@ static void ax88180_meidia_config (struct eth_device *dev) (unsigned int)bmcr_val, (unsigned int)bmsr_val); /* Get real media mode here */ - if (priv->PhyID0 == MARVELL_88E1111_PHYIDR0) { - RealMediaMode = get_MarvellPHY_meida_mode (dev); - } else if (priv->PhyID0 == CICADA_CIS8201_PHYIDR0) { - RealMediaMode = get_CicadaPHY_meida_mode (dev); - } else { + switch (priv->PhyID0) { + case MARVELL_ALASKA_PHYSID0: + RealMediaMode = get_MarvellPHY_media_mode(dev); + break; + case CICADA_CIS8201_PHYSID0: + RealMediaMode = get_CicadaPHY_media_mode(dev); + break; + default: RealMediaMode = MEDIA_1000FULL; + break; } priv->LinkState = INS_LINK_UP; @@ -424,7 +455,7 @@ static void ax88180_meidia_config (struct eth_device *dev) return; } -static unsigned long get_MarvellPHY_meida_mode (struct eth_device *dev) +static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev) { unsigned long m88_ssr; unsigned long MediaMode; @@ -457,7 +488,7 @@ static unsigned long get_MarvellPHY_meida_mode (struct eth_device *dev) return MediaMode; } -static unsigned long get_CicadaPHY_meida_mode (struct eth_device *dev) +static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev) { unsigned long tmp_regval; unsigned long MediaMode; @@ -522,7 +553,7 @@ static int ax88180_init (struct eth_device *dev, bd_t * bd) dev->enetaddr[4] | (((unsigned short)dev->enetaddr[5]) << 8); OUTW (dev, tmp_regval, MACID2); - ax88180_meidia_config (dev); + ax88180_media_config (dev); OUTW (dev, DEFAULT_RXFILTER, RXFILTER); @@ -558,7 +589,7 @@ static int ax88180_recv (struct eth_device *dev) if (ISR_Status & ISR_PHY) { /* Read ISR register once to clear PHY interrupt bit */ tmp_regval = ax88180_mdio_read (dev, M88_ISR); - ax88180_meidia_config (dev); + ax88180_media_config (dev); } if ((ISR_Status & ISR_RX) || (ISR_Status & ISR_RXBUFFOVR)) { diff --git a/drivers/net/ax88180.h b/drivers/net/ax88180.h index d2113df..daf18e0 100644 --- a/drivers/net/ax88180.h +++ b/drivers/net/ax88180.h @@ -19,6 +19,7 @@ #ifndef _AX88180_H_ #define _AX88180_H_ +#include <asm/io.h> #include <asm/types.h> #include <config.h> @@ -33,6 +34,7 @@ struct ax88180_private { unsigned char PadSize; unsigned short PhyAddr; unsigned short PhyID0; + unsigned short PhyID1; unsigned short FirstTxDesc; unsigned short NextTxDesc; ax88180_link_state LinkState; @@ -63,11 +65,10 @@ struct ax88180_private { /* Max Rx Jumbo size is 15K Bytes */ #define MAX_RX_SIZE 0x3C00 -#define MARVELL_88E1111_PHYADDR 0x18 -#define MARVELL_88E1111_PHYIDR0 0x0141 +#define MARVELL_ALASKA_PHYSID0 0x141 +#define MARVELL_88E1118_PHYSID1 0xE40 -#define CICADA_CIS8201_PHYADDR 0x01 -#define CICADA_CIS8201_PHYIDR0 0x000F +#define CICADA_CIS8201_PHYSID0 0x000F #define MEDIA_AUTO 0 #define MEDIA_1000FULL 1 @@ -278,50 +279,6 @@ struct ax88180_private { #define SOFTRST_NORMAL 0x00000003 #define SOFTRST_RESET_MAC 0x00000002 -/* External PHY Register Definition */ -#define BMCR 0x0000 - #define LINE_SPEED_MSB 0x0040 - #define DUPLEX_MODE 0x0100 - #define RESTART_AUTONEG 0x0200 - #define POWER_DOWN 0x0800 - #define AUTONEG_EN 0x1000 - #define LINE_SPEED_LSB 0x2000 - #define PHY_RESET 0x8000 - - #define MEDIAMODE_MASK (LINE_SPEED_MSB | LINE_SPEED_LSB |\ - DUPLEX_MODE) - #define BMCR_SPEED_1000 LINE_SPEED_MSB - #define BMCR_SPEED_100 LINE_SPEED_LSB - #define BMCR_SPEED_10 0x0000 - - #define BMCR_1000FULL (BMCR_SPEED_1000 | DUPLEX_MODE) - #define BMCR_100FULL (BMCR_SPEED_100 | DUPLEX_MODE) - #define BMCR_100HALF BMCR_SPEED_100 - #define BMCR_10FULL DUPLEX_MODE - #define BMCR_10HALF 0x0000 -#define BMSR 0x0001 - #define LINKOK 0x0004 - #define AUTONEG_ENABLE_STS 0x0008 - #define AUTONEG_COMPLETE 0x0020 -#define PHYIDR0 0x0002 -#define PHYIDR1 0x0003 -#define ANAR 0x0004 - #define ANAR_PAUSE 0x0400 - #define ANAR_100FULL 0x0100 - #define ANAR_100HALF 0x0080 - #define ANAR_10FULL 0x0040 - #define ANAR_10HALF 0x0020 - #define ANAR_8023BIT 0x0001 -#define ANLPAR 0x0005 -#define ANER 0x0006 -#define AUX_1000_CTRL 0x0009 - #define ENABLE_1000HALF 0x0100 - #define ENABLE_1000FULL 0x0200 - #define DEFAULT_AUX_1000_CTRL (ENABLE_1000HALF | ENABLE_1000FULL) -#define AUX_1000_STATUS 0x000A - #define LP_1000HALF 0x0400 - #define LP_1000FULL 0x0800 - /* Marvell 88E1111 Gigabit PHY Register Definition */ #define M88_SSR 0x0011 #define SSR_SPEED_MASK 0xC000 @@ -342,14 +299,36 @@ struct ax88180_private { #define LINK_CHANGE_INT 0x0400 #define M88_ISR 0x0013 #define LINK_CHANGE_STATUS 0x0400 -#define M88_EXT_SCR 0x0014 +#define M88E1111_EXT_SCR 0x0014 #define RGMII_RXCLK_DELAY 0x0080 #define RGMII_TXCLK_DELAY 0x0002 #define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY) -#define M88_EXT_SSR 0x001B +#define M88E1111_EXT_SSR 0x001B #define HWCFG_MODE_MASK 0x000F #define RGMII_COPPER_MODE 0x000B +/* Marvell 88E1118 Gigabit PHY Register Definition */ +#define M88E1118_CR 0x14 + #define M88E1118_CR_RGMII_RXCLK_DELAY 0x0020 + #define M88E1118_CR_RGMII_TXCLK_DELAY 0x0010 + #define M88E1118_CR_DEFAULT (M88E1118_CR_RGMII_TXCLK_DELAY | \ + M88E1118_CR_RGMII_RXCLK_DELAY) +#define M88E1118_LEDCTL 0x10 /* Reg 16 on page 3 */ + #define M88E1118_LEDCTL_LED2INT 0x200 + #define M88E1118_LEDCTL_LED2BLNK 0x400 + #define M88E1118_LEDCTL_LED0DUALMODE1 0xc + #define M88E1118_LEDCTL_LED0DUALMODE2 0xd + #define M88E1118_LEDCTL_LED0DUALMODE3 0xe + #define M88E1118_LEDCTL_LED0DUALMODE4 0xf + #define M88E1118_LEDCTL_DEFAULT (M88E1118_LEDCTL_LED2BLNK | \ + M88E1118_LEDCTL_LED0DUALMODE4) + +#define M88E1118_LEDMIX 0x11 /* Reg 17 on page 3 */ + #define M88E1118_LEDMIX_LED050 0x4 + #define M88E1118_LEDMIX_LED150 0x8 + +#define M88E1118_PAGE_SEL 0x16 /* Reg page select */ + /* CICADA CIS8201 Gigabit PHY Register Definition */ #define CIS_IMR 0x0019 #define CIS_INT_ENABLE 0x8000 @@ -376,36 +355,41 @@ struct ax88180_private { static inline unsigned short INW (struct eth_device *dev, unsigned long addr) { - return le16_to_cpu (*(volatile unsigned short *) (addr + dev->iobase)); -} - -static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr) -{ - *(volatile unsigned short *) ((addr + dev->iobase)) = cpu_to_le16 (command); + return le16_to_cpu(readw(addr + (void *)dev->iobase)); } /* Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer */ #if defined (CONFIG_DRIVER_AX88180_16BIT) +static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr) +{ + writew(cpu_to_le16(command), addr + (void *)dev->iobase); +} + static inline unsigned short READ_RXBUF (struct eth_device *dev) { - return le16_to_cpu (*(volatile unsigned short *) (RXBUFFER_START + dev->iobase)); + return le16_to_cpu(readw(RXBUFFER_START + (void *)dev->iobase)); } static inline void WRITE_TXBUF (struct eth_device *dev, unsigned short data) { - *(volatile unsigned short *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le16 (data); + writew(cpu_to_le16(data), TXBUFFER_START + (void *)dev->iobase); } #else +static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr) +{ + writel(cpu_to_le32(command), addr + (void *)dev->iobase); +} + static inline unsigned long READ_RXBUF (struct eth_device *dev) { - return le32_to_cpu (*(volatile unsigned long *) (RXBUFFER_START + dev->iobase)); + return le32_to_cpu(readl(RXBUFFER_START + (void *)dev->iobase)); } static inline void WRITE_TXBUF (struct eth_device *dev, unsigned long data) { - *(volatile unsigned long *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le32 (data); + writel(cpu_to_le32(data), TXBUFFER_START + (void *)dev->iobase); } #endif diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index 720e126..e691bdf 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -16,6 +16,7 @@ #include <linux/mii.h> #include <asm/blackfin.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/dma.h> #include <asm/mach-common/bits/emac.h> #include <asm/mach-common/bits/pll.h> @@ -98,7 +99,7 @@ int bfin_EMAC_initialize(bd_t *bis) hang(); memset(dev, 0, sizeof(*dev)); - sprintf(dev->name, "Blackfin EMAC"); + strcpy(dev->name, "bfin_mac"); dev->iobase = 0; dev->priv = 0; @@ -213,8 +214,17 @@ static int bfin_EMAC_recv(struct eth_device *dev) /* MDC = SCLK / MDC_freq / 2 - 1 */ #define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1) +#ifndef CONFIG_BFIN_MAC_PINS +# ifdef CONFIG_RMII +# define CONFIG_BFIN_MAC_PINS P_RMII0 +# else +# define CONFIG_BFIN_MAC_PINS P_MII0 +# endif +#endif + static int bfin_miiphy_init(struct eth_device *dev, int *opmode) { + const unsigned short pins[] = CONFIG_BFIN_MAC_PINS; u16 phydat; size_t count; @@ -222,42 +232,7 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode) *pVR_CTL |= CLKBUFOE; /* Set all the pins to peripheral mode */ -#ifdef CONFIG_RMII - /* grab RMII pins */ -# if defined(__ADSPBF51x__) - *pPORTF_MUX = (*pPORTF_MUX & \ - ~(PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \ - PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1; - *pPORTF_FER |= PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15; - *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1; - *pPORTG_FER |= PG0 | PG1 | PG2; -# elif defined(__ADSPBF52x__) - *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2; - *pPORTG_FER |= PG14 | PG15; - *pPORTH_MUX = (*pPORTH_MUX & ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK)) | \ - PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2; - *pPORTH_FER |= PH0 | PH1 | PH2 | PH3 | PH4 | PH5 | PH6 | PH7 | PH8; -# else - *pPORTH_FER |= PH0 | PH1 | PH4 | PH5 | PH6 | PH8 | PH9 | PH14 | PH15; -# endif -#else - /* grab MII & RMII pins */ -# if defined(__ADSPBF51x__) - *pPORTF_MUX = (*pPORTF_MUX & \ - ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \ - PORT_x_MUX_0_FUNC_1 | PORT_x_MUX_1_FUNC_1 | PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1; - *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15; - *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1; - *pPORTG_FER |= PG0 | PG1 | PG2; -# elif defined(__ADSPBF52x__) - *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2; - *pPORTG_FER |= PG14 | PG15; - *pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2; - *pPORTH_FER = -1; /* all pins */ -# else - *pPORTH_FER = -1; /* all pins */ -# endif -#endif + peripheral_request_list(pins, "bfin_mac"); /* Odd word alignment for Receive Frame DMA word */ /* Configure checksum support and rcve frame word alignment */ diff --git a/drivers/net/designware.c b/drivers/net/designware.c new file mode 100644 index 0000000..d0d9827 --- /dev/null +++ b/drivers/net/designware.c @@ -0,0 +1,531 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Designware ethernet IP driver for u-boot + */ + +#include <common.h> +#include <miiphy.h> +#include <malloc.h> +#include <linux/err.h> +#include <asm/io.h> +#include "designware.h" + +static void tx_descs_init(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; + char *txbuffs = &priv->txbuffs[0]; + struct dmamacdescr *desc_p; + u32 idx; + + for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { + desc_p = &desc_table_p[idx]; + desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE]; + desc_p->dmamac_next = &desc_table_p[idx + 1]; + +#if defined(CONFIG_DW_ALTDESCRIPTOR) + desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | + DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \ + DESC_TXSTS_TXCHECKINSCTRL | \ + DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); + + desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; + desc_p->dmamac_cntl = 0; + desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); +#else + desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; + desc_p->txrx_status = 0; +#endif + } + + /* Correcting the last pointer of the chain */ + desc_p->dmamac_next = &desc_table_p[0]; + + writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); +} + +static void rx_descs_init(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; + char *rxbuffs = &priv->rxbuffs[0]; + struct dmamacdescr *desc_p; + u32 idx; + + for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { + desc_p = &desc_table_p[idx]; + desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; + desc_p->dmamac_next = &desc_table_p[idx + 1]; + + desc_p->dmamac_cntl = + (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \ + DESC_RXCTRL_RXCHAIN; + + desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; + } + + /* Correcting the last pointer of the chain */ + desc_p->dmamac_next = &desc_table_p[0]; + + writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); +} + +static void descs_init(struct eth_device *dev) +{ + tx_descs_init(dev); + rx_descs_init(dev); +} + +static int mac_reset(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + + int timeout = CONFIG_MACRESET_TIMEOUT; + + writel(DMAMAC_SRST, &dma_p->busmode); + writel(MII_PORTSELECT, &mac_p->conf); + + do { + if (!(readl(&dma_p->busmode) & DMAMAC_SRST)) + return 0; + udelay(1000); + } while (timeout--); + + return -1; +} + +static int dw_write_hwaddr(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 macid_lo, macid_hi; + u8 *mac_id = &dev->enetaddr[0]; + + macid_lo = mac_id[0] + (mac_id[1] << 8) + \ + (mac_id[2] << 16) + (mac_id[3] << 24); + macid_hi = mac_id[4] + (mac_id[5] << 8); + + writel(macid_hi, &mac_p->macaddr0hi); + writel(macid_lo, &mac_p->macaddr0lo); + + return 0; +} + +static int dw_eth_init(struct eth_device *dev, bd_t *bis) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + u32 conf; + + /* Reset ethernet hardware */ + if (mac_reset(dev) < 0) + return -1; + + writel(FIXEDBURST | PRIORXTX_41 | BURST_16, + &dma_p->busmode); + + writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode); + writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode); + + conf = FRAMEBURSTENABLE | DISABLERXOWN; + + if (priv->speed != SPEED_1000M) + conf |= MII_PORTSELECT; + + if (priv->duplex == FULL_DUPLEX) + conf |= FULLDPLXMODE; + + writel(conf, &mac_p->conf); + + descs_init(dev); + + /* + * Start/Enable xfer at dma as well as mac level + */ + writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); + writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode); + + writel(readl(&mac_p->conf) | RXENABLE, &mac_p->conf); + writel(readl(&mac_p->conf) | TXENABLE, &mac_p->conf); + + return 0; +} + +static int dw_eth_send(struct eth_device *dev, volatile void *packet, + int length) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + u32 desc_num = priv->tx_currdescnum; + struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; + + /* Check if the descriptor is owned by CPU */ + if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { + printf("CPU not owner of tx frame\n"); + return -1; + } + + memcpy((void *)desc_p->dmamac_addr, (void *)packet, length); + +#if defined(CONFIG_DW_ALTDESCRIPTOR) + desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; + desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ + DESC_TXCTRL_SIZE1MASK; + + desc_p->txrx_status &= ~(DESC_TXSTS_MSK); + desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; +#else + desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \ + DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \ + DESC_TXCTRL_TXFIRST; + + desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; +#endif + + /* Test the wrap-around condition. */ + if (++desc_num >= CONFIG_TX_DESCR_NUM) + desc_num = 0; + + priv->tx_currdescnum = desc_num; + + /* Start the transmission */ + writel(POLL_DATA, &dma_p->txpolldemand); + + return 0; +} + +static int dw_eth_recv(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + u32 desc_num = priv->rx_currdescnum; + struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; + + u32 status = desc_p->txrx_status; + int length = 0; + + /* Check if the owner is the CPU */ + if (!(status & DESC_RXSTS_OWNBYDMA)) { + + length = (status & DESC_RXSTS_FRMLENMSK) >> \ + DESC_RXSTS_FRMLENSHFT; + + NetReceive(desc_p->dmamac_addr, length); + + /* + * Make the current descriptor valid again and go to + * the next one + */ + desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; + + /* Test the wrap-around condition. */ + if (++desc_num >= CONFIG_RX_DESCR_NUM) + desc_num = 0; + } + + priv->rx_currdescnum = desc_num; + + return length; +} + +static void dw_eth_halt(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + + mac_reset(dev); + priv->tx_currdescnum = priv->rx_currdescnum = 0; +} + +static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 miiaddr; + int timeout = CONFIG_MDIO_TIMEOUT; + + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ + ((reg << MIIREGSHIFT) & MII_REGMSK); + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + do { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { + *val = readl(&mac_p->miidata); + return 0; + } + udelay(1000); + } while (timeout--); + + return -1; +} + +static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 miiaddr; + int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; + u16 value; + + writel(val, &mac_p->miidata); + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ + ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + do { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) + ret = 0; + udelay(1000); + } while (timeout--); + + /* Needed as a fix for ST-Phy */ + eth_mdio_read(dev, addr, reg, &value); + + return ret; +} + +#if defined(CONFIG_DW_SEARCH_PHY) +static int find_phy(struct eth_device *dev) +{ + int phy_addr = 0; + u16 ctrl, oldctrl; + + do { + eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl); + oldctrl = ctrl & PHY_BMCR_AUTON; + + ctrl ^= PHY_BMCR_AUTON; + eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl); + eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl); + ctrl &= PHY_BMCR_AUTON; + + if (ctrl == oldctrl) { + phy_addr++; + } else { + ctrl ^= PHY_BMCR_AUTON; + eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl); + + return phy_addr; + } + } while (phy_addr < 32); + + return -1; +} +#endif + +static int dw_reset_phy(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + u16 ctrl; + int timeout = CONFIG_PHYRESET_TIMEOUT; + u32 phy_addr = priv->address; + + eth_mdio_write(dev, phy_addr, PHY_BMCR, PHY_BMCR_RESET); + do { + eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl); + if (!(ctrl & PHY_BMCR_RESET)) + break; + udelay(1000); + } while (timeout--); + + if (timeout < 0) + return -1; + +#ifdef CONFIG_PHY_RESET_DELAY + udelay(CONFIG_PHY_RESET_DELAY); +#endif + return 0; +} + +static int configure_phy(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + int phy_addr; + u16 bmcr, ctrl; +#if defined(CONFIG_DW_AUTONEG) + u16 bmsr; + u32 timeout; + u16 anlpar, btsr; +#endif + +#if defined(CONFIG_DW_SEARCH_PHY) + phy_addr = find_phy(dev); + if (phy_addr > 0) + priv->address = phy_addr; + else + return -1; +#endif + if (dw_reset_phy(dev) < 0) + return -1; + +#if defined(CONFIG_DW_AUTONEG) + bmcr = PHY_BMCR_AUTON | PHY_BMCR_RST_NEG | PHY_BMCR_100MB | \ + PHY_BMCR_DPLX | PHY_BMCR_1000_MBPS; +#else + bmcr = PHY_BMCR_100MB | PHY_BMCR_DPLX; + +#if defined(CONFIG_DW_SPEED10M) + bmcr &= ~PHY_BMCR_100MB; +#endif +#if defined(CONFIG_DW_DUPLEXHALF) + bmcr &= ~PHY_BMCR_DPLX; +#endif +#endif + if (eth_mdio_write(dev, phy_addr, PHY_BMCR, bmcr) < 0) + return -1; + + /* Read the phy status register and populate priv structure */ +#if defined(CONFIG_DW_AUTONEG) + timeout = CONFIG_AUTONEG_TIMEOUT; + do { + eth_mdio_read(dev, phy_addr, PHY_BMSR, &bmsr); + if (bmsr & PHY_BMSR_AUTN_COMP) + break; + udelay(1000); + } while (timeout--); + + eth_mdio_read(dev, phy_addr, PHY_ANLPAR, &anlpar); + eth_mdio_read(dev, phy_addr, PHY_1000BTSR, &btsr); + + if (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { + priv->speed = SPEED_1000M; + if (btsr & PHY_1000BTSR_1000FD) + priv->duplex = FULL_DUPLEX; + else + priv->duplex = HALF_DUPLEX; + } else { + if (anlpar & PHY_ANLPAR_100) + priv->speed = SPEED_100M; + else + priv->speed = SPEED_10M; + + if (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) + priv->duplex = FULL_DUPLEX; + else + priv->duplex = HALF_DUPLEX; + } +#else + if (eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl) < 0) + return -1; + + if (ctrl & PHY_BMCR_DPLX) + priv->duplex = FULL_DUPLEX; + else + priv->duplex = HALF_DUPLEX; + + if (ctrl & PHY_BMCR_1000_MBPS) + priv->speed = SPEED_1000M; + else if (ctrl & PHY_BMCR_100_MBPS) + priv->speed = SPEED_100M; + else + priv->speed = SPEED_10M; +#endif + return 0; +} + +#if defined(CONFIG_MII) +static int dw_mii_read(char *devname, u8 addr, u8 reg, u16 *val) +{ + struct eth_device *dev; + + dev = eth_get_dev_by_name(devname); + if (dev) + eth_mdio_read(dev, addr, reg, val); + + return 0; +} + +static int dw_mii_write(char *devname, u8 addr, u8 reg, u16 val) +{ + struct eth_device *dev; + + dev = eth_get_dev_by_name(devname); + if (dev) + eth_mdio_write(dev, addr, reg, val); + + return 0; +} +#endif + +int designware_initialize(u32 id, ulong base_addr, u32 phy_addr) +{ + struct eth_device *dev; + struct dw_eth_dev *priv; + + dev = (struct eth_device *) malloc(sizeof(struct eth_device)); + if (!dev) + return -ENOMEM; + + /* + * Since the priv structure contains the descriptors which need a strict + * buswidth alignment, memalign is used to allocate memory + */ + priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev)); + if (!priv) { + free(dev); + return -ENOMEM; + } + + memset(dev, 0, sizeof(struct eth_device)); + memset(priv, 0, sizeof(struct dw_eth_dev)); + + sprintf(dev->name, "mii%d", id); + dev->iobase = (int)base_addr; + dev->priv = priv; + + eth_getenv_enetaddr_by_index(id, &dev->enetaddr[0]); + + priv->dev = dev; + priv->mac_regs_p = (struct eth_mac_regs *)base_addr; + priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + + DW_DMA_BASE_OFFSET); + priv->address = phy_addr; + + if (mac_reset(dev) < 0) + return -1; + + if (configure_phy(dev) < 0) { + printf("Phy could not be configured\n"); + return -1; + } + + dev->init = dw_eth_init; + dev->send = dw_eth_send; + dev->recv = dw_eth_recv; + dev->halt = dw_eth_halt; + dev->write_hwaddr = dw_write_hwaddr; + + eth_register(dev); + +#if defined(CONFIG_MII) + miiphy_register(dev->name, dw_mii_read, dw_mii_write); +#endif + return 1; +} diff --git a/drivers/net/designware.h b/drivers/net/designware.h new file mode 100644 index 0000000..e5828a6 --- /dev/null +++ b/drivers/net/designware.h @@ -0,0 +1,264 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DW_ETH_H +#define _DW_ETH_H + +#define CONFIG_TX_DESCR_NUM 16 +#define CONFIG_RX_DESCR_NUM 16 +#define CONFIG_ETH_BUFSIZE 2048 +#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) +#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) + +#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ) + +struct eth_mac_regs { + u32 conf; /* 0x00 */ + u32 framefilt; /* 0x04 */ + u32 hashtablehigh; /* 0x08 */ + u32 hashtablelow; /* 0x0c */ + u32 miiaddr; /* 0x10 */ + u32 miidata; /* 0x14 */ + u32 flowcontrol; /* 0x18 */ + u32 vlantag; /* 0x1c */ + u32 version; /* 0x20 */ + u8 reserved_1[20]; + u32 intreg; /* 0x38 */ + u32 intmask; /* 0x3c */ + u32 macaddr0hi; /* 0x40 */ + u32 macaddr0lo; /* 0x44 */ +}; + +/* MAC configuration register definitions */ +#define FRAMEBURSTENABLE (1 << 21) +#define MII_PORTSELECT (1 << 15) +#define FES_100 (1 << 14) +#define DISABLERXOWN (1 << 13) +#define FULLDPLXMODE (1 << 11) +#define RXENABLE (1 << 2) +#define TXENABLE (1 << 3) + +/* MII address register definitions */ +#define MII_BUSY (1 << 0) +#define MII_WRITE (1 << 1) +#define MII_CLKRANGE_60_100M (0) +#define MII_CLKRANGE_100_150M (0x4) +#define MII_CLKRANGE_20_35M (0x8) +#define MII_CLKRANGE_35_60M (0xC) +#define MII_CLKRANGE_150_250M (0x10) +#define MII_CLKRANGE_250_300M (0x14) + +#define MIIADDRSHIFT (11) +#define MIIREGSHIFT (6) +#define MII_REGMSK (0x1F << 6) +#define MII_ADDRMSK (0x1F << 11) + + +struct eth_dma_regs { + u32 busmode; /* 0x00 */ + u32 txpolldemand; /* 0x04 */ + u32 rxpolldemand; /* 0x08 */ + u32 rxdesclistaddr; /* 0x0c */ + u32 txdesclistaddr; /* 0x10 */ + u32 status; /* 0x14 */ + u32 opmode; /* 0x18 */ + u32 intenable; /* 0x1c */ + u8 reserved[40]; + u32 currhosttxdesc; /* 0x48 */ + u32 currhostrxdesc; /* 0x4c */ + u32 currhosttxbuffaddr; /* 0x50 */ + u32 currhostrxbuffaddr; /* 0x54 */ +}; + +#define DW_DMA_BASE_OFFSET (0x1000) + +/* Bus mode register definitions */ +#define FIXEDBURST (1 << 16) +#define PRIORXTX_41 (3 << 14) +#define PRIORXTX_31 (2 << 14) +#define PRIORXTX_21 (1 << 14) +#define PRIORXTX_11 (0 << 14) +#define BURST_1 (1 << 8) +#define BURST_2 (2 << 8) +#define BURST_4 (4 << 8) +#define BURST_8 (8 << 8) +#define BURST_16 (16 << 8) +#define BURST_32 (32 << 8) +#define RXHIGHPRIO (1 << 1) +#define DMAMAC_SRST (1 << 0) + +/* Poll demand definitions */ +#define POLL_DATA (0xFFFFFFFF) + +/* Operation mode definitions */ +#define STOREFORWARD (1 << 21) +#define FLUSHTXFIFO (1 << 20) +#define TXSTART (1 << 13) +#define TXSECONDFRAME (1 << 2) +#define RXSTART (1 << 1) + +/* Descriptior related definitions */ +#define MAC_MAX_FRAME_SZ (2048) + +struct dmamacdescr { + u32 txrx_status; + u32 dmamac_cntl; + void *dmamac_addr; + struct dmamacdescr *dmamac_next; +}; + +/* + * txrx_status definitions + */ + +/* tx status bits definitions */ +#if defined(CONFIG_DW_ALTDESCRIPTOR) + +#define DESC_TXSTS_OWNBYDMA (1 << 31) +#define DESC_TXSTS_TXINT (1 << 30) +#define DESC_TXSTS_TXLAST (1 << 29) +#define DESC_TXSTS_TXFIRST (1 << 28) +#define DESC_TXSTS_TXCRCDIS (1 << 27) + +#define DESC_TXSTS_TXPADDIS (1 << 26) +#define DESC_TXSTS_TXCHECKINSCTRL (3 << 22) +#define DESC_TXSTS_TXRINGEND (1 << 21) +#define DESC_TXSTS_TXCHAIN (1 << 20) +#define DESC_TXSTS_MSK (0x1FFFF << 0) + +#else + +#define DESC_TXSTS_OWNBYDMA (1 << 31) +#define DESC_TXSTS_MSK (0x1FFFF << 0) + +#endif + +/* rx status bits definitions */ +#define DESC_RXSTS_OWNBYDMA (1 << 31) +#define DESC_RXSTS_DAFILTERFAIL (1 << 30) +#define DESC_RXSTS_FRMLENMSK (0x3FFF << 16) +#define DESC_RXSTS_FRMLENSHFT (16) + +#define DESC_RXSTS_ERROR (1 << 15) +#define DESC_RXSTS_RXTRUNCATED (1 << 14) +#define DESC_RXSTS_SAFILTERFAIL (1 << 13) +#define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12) +#define DESC_RXSTS_RXDAMAGED (1 << 11) +#define DESC_RXSTS_RXVLANTAG (1 << 10) +#define DESC_RXSTS_RXFIRST (1 << 9) +#define DESC_RXSTS_RXLAST (1 << 8) +#define DESC_RXSTS_RXIPC_GIANT (1 << 7) +#define DESC_RXSTS_RXCOLLISION (1 << 6) +#define DESC_RXSTS_RXFRAMEETHER (1 << 5) +#define DESC_RXSTS_RXWATCHDOG (1 << 4) +#define DESC_RXSTS_RXMIIERROR (1 << 3) +#define DESC_RXSTS_RXDRIBBLING (1 << 2) +#define DESC_RXSTS_RXCRC (1 << 1) + +/* + * dmamac_cntl definitions + */ + +/* tx control bits definitions */ +#if defined(CONFIG_DW_ALTDESCRIPTOR) + +#define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0) +#define DESC_TXCTRL_SIZE1SHFT (0) +#define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16) +#define DESC_TXCTRL_SIZE2SHFT (16) + +#else + +#define DESC_TXCTRL_TXINT (1 << 31) +#define DESC_TXCTRL_TXLAST (1 << 30) +#define DESC_TXCTRL_TXFIRST (1 << 29) +#define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27) +#define DESC_TXCTRL_TXCRCDIS (1 << 26) +#define DESC_TXCTRL_TXRINGEND (1 << 25) +#define DESC_TXCTRL_TXCHAIN (1 << 24) + +#define DESC_TXCTRL_SIZE1MASK (0x7FF << 0) +#define DESC_TXCTRL_SIZE1SHFT (0) +#define DESC_TXCTRL_SIZE2MASK (0x7FF << 11) +#define DESC_TXCTRL_SIZE2SHFT (11) + +#endif + +/* rx control bits definitions */ +#if defined(CONFIG_DW_ALTDESCRIPTOR) + +#define DESC_RXCTRL_RXINTDIS (1 << 31) +#define DESC_RXCTRL_RXRINGEND (1 << 15) +#define DESC_RXCTRL_RXCHAIN (1 << 14) + +#define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0) +#define DESC_RXCTRL_SIZE1SHFT (0) +#define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16) +#define DESC_RXCTRL_SIZE2SHFT (16) + +#else + +#define DESC_RXCTRL_RXINTDIS (1 << 31) +#define DESC_RXCTRL_RXRINGEND (1 << 25) +#define DESC_RXCTRL_RXCHAIN (1 << 24) + +#define DESC_RXCTRL_SIZE1MASK (0x7FF << 0) +#define DESC_RXCTRL_SIZE1SHFT (0) +#define DESC_RXCTRL_SIZE2MASK (0x7FF << 11) +#define DESC_RXCTRL_SIZE2SHFT (11) + +#endif + +struct dw_eth_dev { + u32 address; + u32 speed; + u32 duplex; + u32 tx_currdescnum; + u32 rx_currdescnum; + u32 padding; + + struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; + struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; + + char txbuffs[TX_TOTAL_BUFSIZE]; + char rxbuffs[RX_TOTAL_BUFSIZE]; + + struct eth_mac_regs *mac_regs_p; + struct eth_dma_regs *dma_regs_p; + + struct eth_device *dev; +} __attribute__ ((aligned(8))); + +/* Speed specific definitions */ +#define SPEED_10M 1 +#define SPEED_100M 2 +#define SPEED_1000M 3 + +/* Duplex mode specific definitions */ +#define HALF_DUPLEX 1 +#define FULL_DUPLEX 2 + +#endif diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index 137e41f..709f67a 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -117,12 +117,12 @@ static void DM9000_iow(int reg, u8 value); /* DM9000 network board routine ---------------------------- */ -#define DM9000_outb(d,r) writeb(d, r) -#define DM9000_outw(d,r) writew(d, r) -#define DM9000_outl(d,r) writel(d, r) -#define DM9000_inb(r) readb(r) -#define DM9000_inw(r) readw(r) -#define DM9000_inl(r) readl(r) +#define DM9000_outb(d,r) writeb(d, (volatile u8 *)(r)) +#define DM9000_outw(d,r) writew(d, (volatile u16 *)(r)) +#define DM9000_outl(d,r) writel(d, (volatile u32 *)(r)) +#define DM9000_inb(r) readb((volatile u8 *)(r)) +#define DM9000_inw(r) readw((volatile u16 *)(r)) +#define DM9000_inl(r) readl((volatile u32 *)(r)) #ifdef CONFIG_DM9000_DEBUG static void diff --git a/drivers/net/kirkwood_egiga.h b/drivers/net/kirkwood_egiga.h deleted file mode 100644 index 30c773c..0000000 --- a/drivers/net/kirkwood_egiga.h +++ /dev/null @@ -1,505 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef __EGIGA_H__ -#define __EGIGA_H__ - -#define MAX_KWGBE_DEVS 2 /*controller has two ports */ - -/* PHY_BASE_ADR is board specific and can be configured */ -#if defined (CONFIG_PHY_BASE_ADR) -#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR -#else -#define PHY_BASE_ADR 0x08 /* default phy base addr */ -#endif - -/* Constants */ -#define INT_CAUSE_UNMASK_ALL 0x0007ffff -#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff -#define MRU_MASK 0xfff1ffff -#define PHYADR_MASK 0x0000001f -#define PHYREG_MASK 0x0000001f -#define QTKNBKT_DEF_VAL 0x3fffffff -#define QMTBS_DEF_VAL 0x000003ff -#define QTKNRT_DEF_VAL 0x0000fcff -#define RXUQ 0 /* Used Rx queue */ -#define TXUQ 0 /* Used Rx queue */ - -#define to_dkwgbe(_kd) container_of(_kd, struct kwgbe_device, dev) -#define KWGBEREG_WR(adr, val) writel(val, &adr) -#define KWGBEREG_RD(adr) readl(&adr) -#define KWGBEREG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr) -#define KWGBEREG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr) - -/* Default port configuration value */ -#define PRT_CFG_VAL ( \ - KWGBE_UCAST_MOD_NRML | \ - KWGBE_DFLT_RXQ(RXUQ) | \ - KWGBE_DFLT_RX_ARPQ(RXUQ) | \ - KWGBE_RX_BC_IF_NOT_IP_OR_ARP | \ - KWGBE_RX_BC_IF_IP | \ - KWGBE_RX_BC_IF_ARP | \ - KWGBE_CPTR_TCP_FRMS_DIS | \ - KWGBE_CPTR_UDP_FRMS_DIS | \ - KWGBE_DFLT_RX_TCPQ(RXUQ) | \ - KWGBE_DFLT_RX_UDPQ(RXUQ) | \ - KWGBE_DFLT_RX_BPDUQ(RXUQ)) - -/* Default port extend configuration value */ -#define PORT_CFG_EXTEND_VALUE \ - KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \ - KWGBE_PARTITION_DIS | \ - KWGBE_TX_CRC_GENERATION_EN - -#define GT_KWGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8) - -/* Default sdma control value */ -#define PORT_SDMA_CFG_VALUE ( \ - KWGBE_RX_BURST_SIZE_16_64BIT | \ - KWGBE_BLM_RX_NO_SWAP | \ - KWGBE_BLM_TX_NO_SWAP | \ - GT_KWGBE_IPG_INT_RX(RXUQ) | \ - KWGBE_TX_BURST_SIZE_16_64BIT) - -/* Default port serial control value */ -#define PORT_SERIAL_CONTROL_VALUE ( \ - KWGBE_FORCE_LINK_PASS | \ - KWGBE_DIS_AUTO_NEG_FOR_DUPLX | \ - KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ - KWGBE_ADV_NO_FLOW_CTRL | \ - KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - KWGBE_FORCE_BP_MODE_NO_JAM | \ - (1 << 9) /* Reserved bit has to be 1 */ | \ - KWGBE_DO_NOT_FORCE_LINK_FAIL | \ - KWGBE_EN_AUTO_NEG_SPEED_GMII | \ - KWGBE_DTE_ADV_0 | \ - KWGBE_MIIPHY_MAC_MODE | \ - KWGBE_AUTO_NEG_NO_CHANGE | \ - KWGBE_MAX_RX_PACKET_1552BYTE | \ - KWGBE_CLR_EXT_LOOPBACK | \ - KWGBE_SET_FULL_DUPLEX_MODE | \ - KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX) - -/* Tx WRR confoguration macros */ -#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ -#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */ -#define PORT_TOKEN_RATE 1023 /* PTTBRC reg (default) */ -/* MAC accepet/reject macros */ -#define ACCEPT_MAC_ADDR 0 -#define REJECT_MAC_ADDR 1 -/* Size of a Tx/Rx descriptor used in chain list data structure */ -#define KW_RXQ_DESC_ALIGNED_SIZE \ - (((sizeof(struct kwgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN) -/* Buffer offset from buffer pointer */ -#define RX_BUF_OFFSET 0x2 - -/* Port serial status reg (PSR) */ -#define KWGBE_INTERFACE_GMII_MII 0 -#define KWGBE_INTERFACE_PCM 1 -#define KWGBE_LINK_IS_DOWN 0 -#define KWGBE_LINK_IS_UP (1 << 1) -#define KWGBE_PORT_AT_HALF_DUPLEX 0 -#define KWGBE_PORT_AT_FULL_DUPLEX (1 << 2) -#define KWGBE_RX_FLOW_CTRL_DISD 0 -#define KWGBE_RX_FLOW_CTRL_ENBALED (1 << 3) -#define KWGBE_GMII_SPEED_100_10 0 -#define KWGBE_GMII_SPEED_1000 (1 << 4) -#define KWGBE_MII_SPEED_10 0 -#define KWGBE_MII_SPEED_100 (1 << 5) -#define KWGBE_NO_TX 0 -#define KWGBE_TX_IN_PROGRESS (1 << 7) -#define KWGBE_BYPASS_NO_ACTIVE 0 -#define KWGBE_BYPASS_ACTIVE (1 << 8) -#define KWGBE_PORT_NOT_AT_PARTN_STT 0 -#define KWGBE_PORT_AT_PARTN_STT (1 << 9) -#define KWGBE_PORT_TX_FIFO_NOT_EMPTY 0 -#define KWGBE_PORT_TX_FIFO_EMPTY (1 << 10) - -/* These macros describes the Port configuration reg (Px_cR) bits */ -#define KWGBE_UCAST_MOD_NRML 0 -#define KWGBE_UNICAST_PROMISCUOUS_MODE 1 -#define KWGBE_DFLT_RXQ(_x) (_x << 1) -#define KWGBE_DFLT_RX_ARPQ(_x) (_x << 4) -#define KWGBE_RX_BC_IF_NOT_IP_OR_ARP 0 -#define KWGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7) -#define KWGBE_RX_BC_IF_IP 0 -#define KWGBE_REJECT_BC_IF_IP (1 << 8) -#define KWGBE_RX_BC_IF_ARP 0 -#define KWGBE_REJECT_BC_IF_ARP (1 << 9) -#define KWGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12) -#define KWGBE_CPTR_TCP_FRMS_DIS 0 -#define KWGBE_CPTR_TCP_FRMS_EN (1 << 14) -#define KWGBE_CPTR_UDP_FRMS_DIS 0 -#define KWGBE_CPTR_UDP_FRMS_EN (1 << 15) -#define KWGBE_DFLT_RX_TCPQ(_x) (_x << 16) -#define KWGBE_DFLT_RX_UDPQ(_x) (_x << 19) -#define KWGBE_DFLT_RX_BPDUQ(_x) (_x << 22) -#define KWGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25) - -/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ -#define KWGBE_CLASSIFY_EN 1 -#define KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0 -#define KWGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1) -#define KWGBE_PARTITION_DIS 0 -#define KWGBE_PARTITION_EN (1 << 2) -#define KWGBE_TX_CRC_GENERATION_EN 0 -#define KWGBE_TX_CRC_GENERATION_DIS (1 << 3) - -/* These macros describes the Port Sdma configuration reg (SDCR) bits */ -#define KWGBE_RIFB 1 -#define KWGBE_RX_BURST_SIZE_1_64BIT 0 -#define KWGBE_RX_BURST_SIZE_2_64BIT (1 << 1) -#define KWGBE_RX_BURST_SIZE_4_64BIT (1 << 2) -#define KWGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1)) -#define KWGBE_RX_BURST_SIZE_16_64BIT (1 << 3) -#define KWGBE_BLM_RX_NO_SWAP (1 << 4) -#define KWGBE_BLM_RX_BYTE_SWAP 0 -#define KWGBE_BLM_TX_NO_SWAP (1 << 5) -#define KWGBE_BLM_TX_BYTE_SWAP 0 -#define KWGBE_DESCRIPTORS_BYTE_SWAP (1 << 6) -#define KWGBE_DESCRIPTORS_NO_SWAP 0 -#define KWGBE_TX_BURST_SIZE_1_64BIT 0 -#define KWGBE_TX_BURST_SIZE_2_64BIT (1 << 22) -#define KWGBE_TX_BURST_SIZE_4_64BIT (1 << 23) -#define KWGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22)) -#define KWGBE_TX_BURST_SIZE_16_64BIT (1 << 24) - -/* These macros describes the Port serial control reg (PSCR) bits */ -#define KWGBE_SERIAL_PORT_DIS 0 -#define KWGBE_SERIAL_PORT_EN 1 -#define KWGBE_FORCE_LINK_PASS (1 << 1) -#define KWGBE_DO_NOT_FORCE_LINK_PASS 0 -#define KWGBE_EN_AUTO_NEG_FOR_DUPLX 0 -#define KWGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2) -#define KWGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0 -#define KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) -#define KWGBE_ADV_NO_FLOW_CTRL 0 -#define KWGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4) -#define KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 -#define KWGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5) -#define KWGBE_FORCE_BP_MODE_NO_JAM 0 -#define KWGBE_FORCE_BP_MODE_JAM_TX (1 << 7) -#define KWGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8) -#define KWGBE_FORCE_LINK_FAIL 0 -#define KWGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10) -#define KWGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13) -#define KWGBE_EN_AUTO_NEG_SPEED_GMII 0 -#define KWGBE_DTE_ADV_0 0 -#define KWGBE_DTE_ADV_1 (1 << 14) -#define KWGBE_MIIPHY_MAC_MODE 0 -#define KWGBE_MIIPHY_PHY_MODE (1 << 15) -#define KWGBE_AUTO_NEG_NO_CHANGE 0 -#define KWGBE_RESTART_AUTO_NEG (1 << 16) -#define KWGBE_MAX_RX_PACKET_1518BYTE 0 -#define KWGBE_MAX_RX_PACKET_1522BYTE (1 << 17) -#define KWGBE_MAX_RX_PACKET_1552BYTE (1 << 18) -#define KWGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17)) -#define KWGBE_MAX_RX_PACKET_9192BYTE (1 << 19) -#define KWGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17)) -#define KWGBE_SET_EXT_LOOPBACK (1 << 20) -#define KWGBE_CLR_EXT_LOOPBACK 0 -#define KWGBE_SET_FULL_DUPLEX_MODE (1 << 21) -#define KWGBE_SET_HALF_DUPLEX_MODE 0 -#define KWGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22) -#define KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 -#define KWGBE_SET_GMII_SPEED_TO_10_100 0 -#define KWGBE_SET_GMII_SPEED_TO_1000 (1 << 23) -#define KWGBE_SET_MII_SPEED_TO_10 0 -#define KWGBE_SET_MII_SPEED_TO_100 (1 << 24) - -/* SMI register fields */ -#define KWGBE_PHY_SMI_TIMEOUT 10000 -#define KWGBE_PHY_SMI_DATA_OFFS 0 /* Data */ -#define KWGBE_PHY_SMI_DATA_MASK (0xffff << KWGBE_PHY_SMI_DATA_OFFS) -#define KWGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ -#define KWGBE_PHY_SMI_DEV_ADDR_MASK (PHYADR_MASK << KWGBE_PHY_SMI_DEV_ADDR_OFFS) -#define KWGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */ -#define KWGBE_SMI_REG_ADDR_MASK (PHYADR_MASK << KWGBE_SMI_REG_ADDR_OFFS) -#define KWGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ -#define KWGBE_PHY_SMI_OPCODE_MASK (3 << KWGBE_PHY_SMI_OPCODE_OFFS) -#define KWGBE_PHY_SMI_OPCODE_WRITE (0 << KWGBE_PHY_SMI_OPCODE_OFFS) -#define KWGBE_PHY_SMI_OPCODE_READ (1 << KWGBE_PHY_SMI_OPCODE_OFFS) -#define KWGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */ -#define KWGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */ - -/* SDMA command status fields macros */ -/* Tx & Rx descriptors status */ -#define KWGBE_ERROR_SUMMARY 1 -/* Tx & Rx descriptors command */ -#define KWGBE_BUFFER_OWNED_BY_DMA (1 << 31) -/* Tx descriptors status */ -#define KWGBE_LC_ERROR 0 -#define KWGBE_UR_ERROR (1 << 1) -#define KWGBE_RL_ERROR (1 << 2) -#define KWGBE_LLC_SNAP_FORMAT (1 << 9) -#define KWGBE_TX_LAST_FRAME (1 << 20) - -/* Rx descriptors status */ -#define KWGBE_CRC_ERROR 0 -#define KWGBE_OVERRUN_ERROR (1 << 1) -#define KWGBE_MAX_FRAME_LENGTH_ERROR (1 << 2) -#define KWGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1)) -#define KWGBE_VLAN_TAGGED (1 << 19) -#define KWGBE_BPDU_FRAME (1 << 20) -#define KWGBE_TCP_FRAME_OVER_IP_V_4 0 -#define KWGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21) -#define KWGBE_OTHER_FRAME_TYPE (1 << 22) -#define KWGBE_LAYER_2_IS_KWGBE_V_2 (1 << 23) -#define KWGBE_FRAME_TYPE_IP_V_4 (1 << 24) -#define KWGBE_FRAME_HEADER_OK (1 << 25) -#define KWGBE_RX_LAST_DESC (1 << 26) -#define KWGBE_RX_FIRST_DESC (1 << 27) -#define KWGBE_UNKNOWN_DESTINATION_ADDR (1 << 28) -#define KWGBE_RX_EN_INTERRUPT (1 << 29) -#define KWGBE_LAYER_4_CHECKSUM_OK (1 << 30) - -/* Rx descriptors byte count */ -#define KWGBE_FRAME_FRAGMENTED (1 << 2) - -/* Tx descriptors command */ -#define KWGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10) -#define KWGBE_FRAME_SET_TO_VLAN (1 << 15) -#define KWGBE_TCP_FRAME 0 -#define KWGBE_UDP_FRAME (1 << 16) -#define KWGBE_GEN_TCP_UDP_CHECKSUM (1 << 17) -#define KWGBE_GEN_IP_V_4_CHECKSUM (1 << 18) -#define KWGBE_ZERO_PADDING (1 << 19) -#define KWGBE_TX_LAST_DESC (1 << 20) -#define KWGBE_TX_FIRST_DESC (1 << 21) -#define KWGBE_GEN_CRC (1 << 22) -#define KWGBE_TX_EN_INTERRUPT (1 << 23) -#define KWGBE_AUTO_MODE (1 << 30) - -/* Address decode parameters */ -/* Ethernet Base Address Register bits */ -#define EBAR_TARGET_DRAM 0x00000000 -#define EBAR_TARGET_DEVICE 0x00000001 -#define EBAR_TARGET_CBS 0x00000002 -#define EBAR_TARGET_PCI0 0x00000003 -#define EBAR_TARGET_PCI1 0x00000004 -#define EBAR_TARGET_CUNIT 0x00000005 -#define EBAR_TARGET_AUNIT 0x00000006 -#define EBAR_TARGET_GUNIT 0x00000007 - -/* Window attrib */ -#define EBAR_DRAM_CS0 0x00000E00 -#define EBAR_DRAM_CS1 0x00000D00 -#define EBAR_DRAM_CS2 0x00000B00 -#define EBAR_DRAM_CS3 0x00000700 - -/* DRAM Target interface */ -#define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000 -#define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000 -#define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000 - -/* Device Bus Target interface */ -#define EBAR_DEVICE_DEVCS0 0x00001E00 -#define EBAR_DEVICE_DEVCS1 0x00001D00 -#define EBAR_DEVICE_DEVCS2 0x00001B00 -#define EBAR_DEVICE_DEVCS3 0x00001700 -#define EBAR_DEVICE_BOOTCS3 0x00000F00 - -/* PCI Target interface */ -#define EBAR_PCI_BYTE_SWAP 0x00000000 -#define EBAR_PCI_NO_SWAP 0x00000100 -#define EBAR_PCI_BYTE_WORD_SWAP 0x00000200 -#define EBAR_PCI_WORD_SWAP 0x00000300 -#define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 -#define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400 -#define EBAR_PCI_IO_SPACE 0x00000000 -#define EBAR_PCI_MEMORY_SPACE 0x00000800 -#define EBAR_PCI_REQ64_FORCE 0x00000000 -#define EBAR_PCI_REQ64_SIZE 0x00001000 - -/* Window access control */ -#define EWIN_ACCESS_NOT_ALLOWED 0 -#define EWIN_ACCESS_READ_ONLY 1 -#define EWIN_ACCESS_FULL ((1 << 1) | 1) - -/* structures represents Controller registers */ -struct kwgbe_barsz { - u32 bar; - u32 size; -}; - -struct kwgbe_rxcdp { - struct kwgbe_rxdesc *rxcdp; - u32 rxcdp_pad[3]; -}; - -struct kwgbe_tqx { - u32 qxttbc; - u32 tqxtbc; - u32 tqxac; - u32 tqxpad; -}; - -struct kwgbe_registers { - u32 phyadr; - u32 smi; - u32 euda; - u32 eudid; - u8 pad1[0x080 - 0x00c - 4]; - u32 euic; - u32 euim; - u8 pad2[0x094 - 0x084 - 4]; - u32 euea; - u32 euiae; - u8 pad3[0x0b0 - 0x098 - 4]; - u32 euc; - u8 pad3a[0x200 - 0x0b0 - 4]; - struct kwgbe_barsz barsz[6]; - u8 pad4[0x280 - 0x22c - 4]; - u32 ha_remap[4]; - u32 bare; - u32 epap; - u8 pad5[0x400 - 0x294 - 4]; - u32 pxc; - u32 pxcx; - u32 mii_ser_params; - u8 pad6[0x410 - 0x408 - 4]; - u32 evlane; - u32 macal; - u32 macah; - u32 sdc; - u32 dscp[7]; - u32 psc0; - u32 vpt2p; - u32 ps0; - u32 tqc; - u32 psc1; - u32 ps1; - u32 mrvl_header; - u8 pad7[0x460 - 0x454 - 4]; - u32 ic; - u32 ice; - u32 pim; - u32 peim; - u8 pad8[0x474 - 0x46c - 4]; - u32 pxtfut; - u32 pad9; - u32 pxmfs; - u32 pad10; - u32 pxdfc; - u32 pxofc; - u8 pad11[0x494 - 0x488 - 4]; - u32 peuiae; - u8 pad12[0x4bc - 0x494 - 4]; - u32 eth_type_prio; - u8 pad13[0x4dc - 0x4bc - 4]; - u32 tqfpc; - u32 pttbrc; - u32 tqc1; - u32 pmtu; - u32 pmtbs; - u8 pad14[0x60c - 0x4ec - 4]; - struct kwgbe_rxcdp rxcdp[7]; - struct kwgbe_rxdesc *rxcdp7; - u32 rqc; - struct kwgbe_txdesc *tcsdp; - u8 pad15[0x6c0 - 0x684 - 4]; - struct kwgbe_txdesc *tcqdp[8]; - u8 pad16[0x700 - 0x6dc - 4]; - struct kwgbe_tqx tqx[8]; - u32 pttbc; - u8 pad17[0x7a8 - 0x780 - 4]; - u32 tqxipg0; - u32 pad18[3]; - u32 tqxipg1; - u8 pad19[0x7c0 - 0x7b8 - 4]; - u32 hitkninlopkt; - u32 hitkninasyncpkt; - u32 lotkninasyncpkt; - u32 pad20; - u32 ts; - u8 pad21[0x3000 - 0x27d0 - 4]; - u32 pad20_1[32]; /* mib counter registes */ - u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32]; - u32 dfsmt[64]; - u32 dfomt[64]; - u32 dfut[4]; - u8 pad23[0xe20c0 - 0x7360c - 4]; - u32 pmbus_top_arbiter; -}; - -/* structures/enums needed by driver */ -enum kwgbe_adrwin { - KWGBE_WIN0, - KWGBE_WIN1, - KWGBE_WIN2, - KWGBE_WIN3, - KWGBE_WIN4, - KWGBE_WIN5 -}; - -enum kwgbe_target { - KWGBE_TARGET_DRAM, - KWGBE_TARGET_DEV, - KWGBE_TARGET_CBS, - KWGBE_TARGET_PCI0, - KWGBE_TARGET_PCI1 -}; - -struct kwgbe_winparam { - enum kwgbe_adrwin win; /* Window number */ - enum kwgbe_target target; /* System targets */ - u16 attrib; /* BAR attrib. See above macros */ - u32 base_addr; /* Window base address in u32 form */ - u32 high_addr; /* Window high address in u32 form */ - u32 size; /* Size in MBytes. Must be % 64Kbyte. */ - int enable; /* Enable/disable access to the window. */ - u16 access_ctrl; /*Access ctrl register. see above macros */ -}; - -struct kwgbe_rxdesc { - u32 cmd_sts; /* Descriptor command status */ - u16 buf_size; /* Buffer size */ - u16 byte_cnt; /* Descriptor buffer byte count */ - u8 *buf_ptr; /* Descriptor buffer pointer */ - struct kwgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */ -}; - -struct kwgbe_txdesc { - u32 cmd_sts; /* Descriptor command status */ - u16 l4i_chk; /* CPU provided TCP Checksum */ - u16 byte_cnt; /* Descriptor buffer byte count */ - u8 *buf_ptr; /* Descriptor buffer ptr */ - struct kwgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */ -}; - -/* port device data struct */ -struct kwgbe_device { - struct eth_device dev; - struct kwgbe_registers *regs; - struct kwgbe_txdesc *p_txdesc; - struct kwgbe_rxdesc *p_rxdesc; - struct kwgbe_rxdesc *p_rxdesc_curr; - u8 *p_rxbuf; - u8 *p_aligned_txbuf; -}; - -#endif /* __EGIGA_H__ */ diff --git a/drivers/net/macb.c b/drivers/net/macb.c index dcb8850..6a58a37 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -439,8 +439,6 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) { struct macb_device *macb = to_macb(netdev); unsigned long paddr; - u32 hwaddr_bottom; - u16 hwaddr_top; int i; /* @@ -469,12 +467,6 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) macb_writel(macb, RBQP, macb->rx_ring_dma); macb_writel(macb, TBQP, macb->tx_ring_dma); - /* set hardware address */ - hwaddr_bottom = cpu_to_le32(*((u32 *)netdev->enetaddr)); - macb_writel(macb, SA1B, hwaddr_bottom); - hwaddr_top = cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))); - macb_writel(macb, SA1T, hwaddr_top); - /* choose RMII or MII mode. This depends on the board */ #ifdef CONFIG_RMII #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ @@ -521,6 +513,20 @@ static void macb_halt(struct eth_device *netdev) macb_writel(macb, NCR, MACB_BIT(CLRSTAT)); } +static int macb_write_hwaddr(struct eth_device *dev) +{ + struct macb_device *macb = to_macb(dev); + u32 hwaddr_bottom; + u16 hwaddr_top; + + /* set hardware address */ + hwaddr_bottom = cpu_to_le32(*((u32 *)dev->enetaddr)); + macb_writel(macb, SA1B, hwaddr_bottom); + hwaddr_top = cpu_to_le16(*((u16 *)(dev->enetaddr + 4))); + macb_writel(macb, SA1T, hwaddr_top); + return 0; +} + int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) { struct macb_device *macb; @@ -554,6 +560,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) netdev->halt = macb_halt; netdev->send = macb_send; netdev->recv = macb_recv; + netdev->write_hwaddr = macb_write_hwaddr; /* * Do some basic initialization so that we at least can talk diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/mvgbe.c index 932792e..cad4023 100644 --- a/drivers/net/kirkwood_egiga.c +++ b/drivers/net/mvgbe.c @@ -35,11 +35,19 @@ #include <asm/errno.h> #include <asm/types.h> #include <asm/byteorder.h> + +#if defined(CONFIG_KIRKWOOD) #include <asm/arch/kirkwood.h> -#include "kirkwood_egiga.h" +#elif defined(CONFIG_ORION5X) +#include <asm/arch/orion5x.h> +#endif + +#include "mvgbe.h" -#define KIRKWOOD_PHY_ADR_REQUEST 0xee -#define KWGBE_SMI_REG (((struct kwgbe_registers *)KW_EGIGA0_BASE)->smi) +DECLARE_GLOBAL_DATA_PTR; + +#define MV_PHY_ADR_REQUEST 0xee +#define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi) /* * smi_reg_read - miiphy_read callback function. @@ -49,16 +57,16 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data) { struct eth_device *dev = eth_get_dev_by_name(devname); - struct kwgbe_device *dkwgbe = to_dkwgbe(dev); - struct kwgbe_registers *regs = dkwgbe->regs; + struct mvgbe_device *dmvgbe = to_mvgbe(dev); + struct mvgbe_registers *regs = dmvgbe->regs; u32 smi_reg; u32 timeout; /* Phyadr read request */ - if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST && - reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) { + if (phy_adr == MV_PHY_ADR_REQUEST && + reg_ofs == MV_PHY_ADR_REQUEST) { /* */ - *data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK); + *data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK); return 0; } /* check parameters */ @@ -73,42 +81,43 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data) return -EFAULT; } - timeout = KWGBE_PHY_SMI_TIMEOUT; + timeout = MVGBE_PHY_SMI_TIMEOUT; /* wait till the SMI is not busy */ do { /* read smi register */ - smi_reg = KWGBEREG_RD(KWGBE_SMI_REG); + smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); if (timeout-- == 0) { printf("Err..(%s) SMI busy timeout\n", __FUNCTION__); return -EFAULT; } - } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK); + } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK); /* fill the phy address and regiser offset and read opcode */ - smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS) - | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS) - | KWGBE_PHY_SMI_OPCODE_READ; + smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS) + | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS) + | MVGBE_PHY_SMI_OPCODE_READ; /* write the smi register */ - KWGBEREG_WR(KWGBE_SMI_REG, smi_reg); + MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg); /*wait till read value is ready */ - timeout = KWGBE_PHY_SMI_TIMEOUT; + timeout = MVGBE_PHY_SMI_TIMEOUT; do { /* read smi register */ - smi_reg = KWGBEREG_RD(KWGBE_SMI_REG); + smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); if (timeout-- == 0) { printf("Err..(%s) SMI read ready timeout\n", __FUNCTION__); return -EFAULT; } - } while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK)); + } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK)); /* Wait for the data to update in the SMI register */ - for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ; + for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++) + ; - *data = (u16) (KWGBEREG_RD(KWGBE_SMI_REG) & KWGBE_PHY_SMI_DATA_MASK); + *data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK); debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr, reg_ofs, *data); @@ -125,15 +134,15 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data) static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data) { struct eth_device *dev = eth_get_dev_by_name(devname); - struct kwgbe_device *dkwgbe = to_dkwgbe(dev); - struct kwgbe_registers *regs = dkwgbe->regs; + struct mvgbe_device *dmvgbe = to_mvgbe(dev); + struct mvgbe_registers *regs = dmvgbe->regs; u32 smi_reg; u32 timeout; /* Phyadr write request*/ - if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST && - reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) { - KWGBEREG_WR(regs->phyadr, data); + if (phy_adr == MV_PHY_ADR_REQUEST && + reg_ofs == MV_PHY_ADR_REQUEST) { + MVGBE_REG_WR(regs->phyadr, data); return 0; } @@ -148,24 +157,24 @@ static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data) } /* wait till the SMI is not busy */ - timeout = KWGBE_PHY_SMI_TIMEOUT; + timeout = MVGBE_PHY_SMI_TIMEOUT; do { /* read smi register */ - smi_reg = KWGBEREG_RD(KWGBE_SMI_REG); + smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); if (timeout-- == 0) { printf("Err..(%s) SMI busy timeout\n", __FUNCTION__); return -ETIME; } - } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK); + } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK); /* fill the phy addr and reg offset and write opcode and data */ - smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS); - smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS) - | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS); - smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ; + smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS); + smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS) + | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS); + smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ; /* write the smi register */ - KWGBEREG_WR(KWGBE_SMI_REG, smi_reg); + MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg); return 0; } @@ -202,52 +211,52 @@ static void stop_queue(u32 * qreg) * @regs Register struct pointer. * @param Address decode parameter struct. */ -static void set_access_control(struct kwgbe_registers *regs, - struct kwgbe_winparam *param) +static void set_access_control(struct mvgbe_registers *regs, + struct mvgbe_winparam *param) { u32 access_prot_reg; /* Set access control register */ - access_prot_reg = KWGBEREG_RD(regs->epap); + access_prot_reg = MVGBE_REG_RD(regs->epap); /* clear window permission */ access_prot_reg &= (~(3 << (param->win * 2))); access_prot_reg |= (param->access_ctrl << (param->win * 2)); - KWGBEREG_WR(regs->epap, access_prot_reg); + MVGBE_REG_WR(regs->epap, access_prot_reg); /* Set window Size reg (SR) */ - KWGBEREG_WR(regs->barsz[param->win].size, + MVGBE_REG_WR(regs->barsz[param->win].size, (((param->size / 0x10000) - 1) << 16)); /* Set window Base address reg (BA) */ - KWGBEREG_WR(regs->barsz[param->win].bar, + MVGBE_REG_WR(regs->barsz[param->win].bar, (param->target | param->attrib | param->base_addr)); /* High address remap reg (HARR) */ if (param->win < 4) - KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr); + MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr); /* Base address enable reg (BARER) */ if (param->enable == 1) - KWGBEREG_BITS_RESET(regs->bare, (1 << param->win)); + MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win)); else - KWGBEREG_BITS_SET(regs->bare, (1 << param->win)); + MVGBE_REG_BITS_SET(regs->bare, (1 << param->win)); } -static void set_dram_access(struct kwgbe_registers *regs) +static void set_dram_access(struct mvgbe_registers *regs) { - struct kwgbe_winparam win_param; + struct mvgbe_winparam win_param; int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { /* Set access parameters for DRAM bank i */ win_param.win = i; /* Use Ethernet window i */ /* Window target - DDR */ - win_param.target = KWGBE_TARGET_DRAM; + win_param.target = MVGBE_TARGET_DRAM; /* Enable full access */ win_param.access_ctrl = EWIN_ACCESS_FULL; win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = kw_sdram_bar(i); - win_param.size = kw_sdram_bs(i); /* Get bank size */ + /* Get bank base and size */ + win_param.base_addr = gd->bd->bi_dram[i].start; + win_param.size = gd->bd->bi_dram[i].size; if (win_param.size == 0) win_param.enable = 0; else @@ -268,7 +277,7 @@ static void set_dram_access(struct kwgbe_registers *regs) win_param.attrib = EBAR_DRAM_CS3; break; default: - /* invalide bank, disable access */ + /* invalid bank, disable access */ win_param.enable = 0; win_param.attrib = 0; break; @@ -284,19 +293,19 @@ static void set_dram_access(struct kwgbe_registers *regs) * Go through all the DA filter tables (Unicast, Special Multicast & Other * Multicast) and set each entry to 0. */ -static void port_init_mac_tables(struct kwgbe_registers *regs) +static void port_init_mac_tables(struct mvgbe_registers *regs) { int table_index; /* Clear DA filter unicast table (Ex_dFUT) */ for (table_index = 0; table_index < 4; ++table_index) - KWGBEREG_WR(regs->dfut[table_index], 0); + MVGBE_REG_WR(regs->dfut[table_index], 0); for (table_index = 0; table_index < 64; ++table_index) { /* Clear DA filter special multicast table (Ex_dFSMT) */ - KWGBEREG_WR(regs->dfsmt[table_index], 0); + MVGBE_REG_WR(regs->dfsmt[table_index], 0); /* Clear DA filter other multicast table (Ex_dFOMT) */ - KWGBEREG_WR(regs->dfomt[table_index], 0); + MVGBE_REG_WR(regs->dfomt[table_index], 0); } } @@ -314,7 +323,7 @@ static void port_init_mac_tables(struct kwgbe_registers *regs) * * RETURN: 1 if output succeeded. 0 if option parameter is invalid. */ -static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble, +static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble, int option) { u32 unicast_reg; @@ -334,16 +343,16 @@ static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble, * Clear accepts frame bit at specified unicast * DA table entry */ - unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]); + unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]); unicast_reg &= (0xFF << (8 * reg_offset)); - KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg); + MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg); break; case ACCEPT_MAC_ADDR: /* Set accepts frame bit at unicast DA filter table entry */ - unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]); + unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]); unicast_reg &= (0xFF << (8 * reg_offset)); unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset)); - KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg); + MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg); break; default: return 0; @@ -354,7 +363,7 @@ static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble, /* * port_uc_addr_set - This function Set the port Unicast address. */ -static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr) +static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr) { u32 mac_h; u32 mac_l; @@ -363,92 +372,95 @@ static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr) mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | (p_addr[3] << 0); - KWGBEREG_WR(regs->macal, mac_l); - KWGBEREG_WR(regs->macah, mac_h); + MVGBE_REG_WR(regs->macal, mac_l); + MVGBE_REG_WR(regs->macah, mac_h); /* Accept frames of this address */ port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR); } /* - * kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. + * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. */ -static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe) +static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe) { - struct kwgbe_rxdesc *p_rx_desc; + struct mvgbe_rxdesc *p_rx_desc; int i; /* initialize the Rx descriptors ring */ - p_rx_desc = dkwgbe->p_rxdesc; + p_rx_desc = dmvgbe->p_rxdesc; for (i = 0; i < RINGSZ; i++) { p_rx_desc->cmd_sts = - KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT; + MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT; p_rx_desc->buf_size = PKTSIZE_ALIGN; p_rx_desc->byte_cnt = 0; - p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN; + p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN; if (i == (RINGSZ - 1)) - p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc; + p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc; else { - p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *) - ((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE); + p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *) + ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE); p_rx_desc = p_rx_desc->nxtdesc_p; } } - dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc; + dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc; } -static int kwgbe_init(struct eth_device *dev) +static int mvgbe_init(struct eth_device *dev) { - struct kwgbe_device *dkwgbe = to_dkwgbe(dev); - struct kwgbe_registers *regs = dkwgbe->regs; + struct mvgbe_device *dmvgbe = to_mvgbe(dev); + struct mvgbe_registers *regs = dmvgbe->regs; #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \ && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN) int i; #endif /* setup RX rings */ - kwgbe_init_rx_desc_ring(dkwgbe); + mvgbe_init_rx_desc_ring(dmvgbe); /* Clear the ethernet port interrupts */ - KWGBEREG_WR(regs->ic, 0); - KWGBEREG_WR(regs->ice, 0); + MVGBE_REG_WR(regs->ic, 0); + MVGBE_REG_WR(regs->ice, 0); /* Unmask RX buffer and TX end interrupt */ - KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL); + MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL); /* Unmask phy and link status changes interrupts */ - KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT); + MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT); set_dram_access(regs); port_init_mac_tables(regs); - port_uc_addr_set(regs, dkwgbe->dev.enetaddr); + port_uc_addr_set(regs, dmvgbe->dev.enetaddr); /* Assign port configuration and command. */ - KWGBEREG_WR(regs->pxc, PRT_CFG_VAL); - KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE); - KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE); + MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL); + MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE); + MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE); /* Assign port SDMA configuration */ - KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE); - KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL); - KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL); + MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE); + MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL); + MVGBE_REG_WR(regs->tqx[0].tqxtbc, + (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL); /* Turn off the port/RXUQ bandwidth limitation */ - KWGBEREG_WR(regs->pmtu, 0); + MVGBE_REG_WR(regs->pmtu, 0); /* Set maximum receive buffer to 9700 bytes */ - KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE - | (KWGBEREG_RD(regs->psc0) & MRU_MASK)); + MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE + | (MVGBE_REG_RD(regs->psc0) & MRU_MASK)); /* Enable port initially */ - KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN); + MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN); /* * Set ethernet MTU for leaky bucket mechanism to 0 - this will * disable the leaky bucket mechanism . */ - KWGBEREG_WR(regs->pmtu, 0); + MVGBE_REG_WR(regs->pmtu, 0); /* Assignment of Rx CRDB of given RXUQ */ - KWGBEREG_WR(regs->rxcdp[RXUQ], (u32) dkwgbe->p_rxdesc_curr); + MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr); + /* ensure previous write is done before enabling Rx DMA */ + isb(); /* Enable port Rx. */ - KWGBEREG_WR(regs->rqc, (1 << RXUQ)); + MVGBE_REG_WR(regs->rqc, (1 << RXUQ)); #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \ && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN) @@ -456,8 +468,8 @@ static int kwgbe_init(struct eth_device *dev) for (i = 0; i < 5; i++) { u16 phyadr; - miiphy_read(dev->name, KIRKWOOD_PHY_ADR_REQUEST, - KIRKWOOD_PHY_ADR_REQUEST, &phyadr); + miiphy_read(dev->name, MV_PHY_ADR_REQUEST, + MV_PHY_ADR_REQUEST, &phyadr); /* Return if we get link up */ if (miiphy_link(dev->name, phyadr)) return 0; @@ -470,50 +482,50 @@ static int kwgbe_init(struct eth_device *dev) return 0; } -static int kwgbe_halt(struct eth_device *dev) +static int mvgbe_halt(struct eth_device *dev) { - struct kwgbe_device *dkwgbe = to_dkwgbe(dev); - struct kwgbe_registers *regs = dkwgbe->regs; + struct mvgbe_device *dmvgbe = to_mvgbe(dev); + struct mvgbe_registers *regs = dmvgbe->regs; /* Disable all gigE address decoder */ - KWGBEREG_WR(regs->bare, 0x3f); + MVGBE_REG_WR(regs->bare, 0x3f); stop_queue(®s->tqc); stop_queue(®s->rqc); /* Disable port */ - KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN); + MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN); /* Set port is not reset */ - KWGBEREG_BITS_RESET(regs->psc1, 1 << 4); + MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4); #ifdef CONFIG_SYS_MII_MODE /* Set MMI interface up */ - KWGBEREG_BITS_RESET(regs->psc1, 1 << 3); + MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3); #endif /* Disable & mask ethernet port interrupts */ - KWGBEREG_WR(regs->ic, 0); - KWGBEREG_WR(regs->ice, 0); - KWGBEREG_WR(regs->pim, 0); - KWGBEREG_WR(regs->peim, 0); + MVGBE_REG_WR(regs->ic, 0); + MVGBE_REG_WR(regs->ice, 0); + MVGBE_REG_WR(regs->pim, 0); + MVGBE_REG_WR(regs->peim, 0); return 0; } -static int kwgbe_write_hwaddr(struct eth_device *dev) +static int mvgbe_write_hwaddr(struct eth_device *dev) { - struct kwgbe_device *dkwgbe = to_dkwgbe(dev); - struct kwgbe_registers *regs = dkwgbe->regs; + struct mvgbe_device *dmvgbe = to_mvgbe(dev); + struct mvgbe_registers *regs = dmvgbe->regs; /* Programs net device MAC address after initialization */ - port_uc_addr_set(regs, dkwgbe->dev.enetaddr); + port_uc_addr_set(regs, dmvgbe->dev.enetaddr); return 0; } -static int kwgbe_send(struct eth_device *dev, volatile void *dataptr, +static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize) { - struct kwgbe_device *dkwgbe = to_dkwgbe(dev); - struct kwgbe_registers *regs = dkwgbe->regs; - struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc; + struct mvgbe_device *dmvgbe = to_mvgbe(dev); + struct mvgbe_registers *regs = dmvgbe->regs; + struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc; void *p = (void *)dataptr; u32 cmd_sts; @@ -525,30 +537,35 @@ static int kwgbe_send(struct eth_device *dev, volatile void *dataptr, return -1; } - memcpy(dkwgbe->p_aligned_txbuf, p, datasize); - p = dkwgbe->p_aligned_txbuf; + memcpy(dmvgbe->p_aligned_txbuf, p, datasize); + p = dmvgbe->p_aligned_txbuf; } - p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC; - p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC; - p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA; - p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT; + p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC; + p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC; + p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA; + p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT; p_txdesc->buf_ptr = (u8 *) p; p_txdesc->byte_cnt = datasize; + /* Set this tc desc as zeroth TXUQ */ + MVGBE_REG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc); + + /* ensure tx desc writes above are performed before we start Tx DMA */ + isb(); + /* Apply send command using zeroth TXUQ */ - KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc); - KWGBEREG_WR(regs->tqc, (1 << TXUQ)); + MVGBE_REG_WR(regs->tqc, (1 << TXUQ)); /* * wait for packet xmit completion */ cmd_sts = readl(&p_txdesc->cmd_sts); - while (cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) { + while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) { /* return fail if error is detected */ - if ((cmd_sts & (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME)) == - (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME) && - cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) { + if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) == + (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) && + cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) { printf("Err..(%s) in xmit packet\n", __FUNCTION__); return -1; } @@ -557,22 +574,22 @@ static int kwgbe_send(struct eth_device *dev, volatile void *dataptr, return 0; } -static int kwgbe_recv(struct eth_device *dev) +static int mvgbe_recv(struct eth_device *dev) { - struct kwgbe_device *dkwgbe = to_dkwgbe(dev); - struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr; + struct mvgbe_device *dmvgbe = to_mvgbe(dev); + struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr; u32 cmd_sts; u32 timeout = 0; /* wait untill rx packet available or timeout */ do { - if (timeout < KWGBE_PHY_SMI_TIMEOUT) + if (timeout < MVGBE_PHY_SMI_TIMEOUT) timeout++; else { debug("%s time out...\n", __FUNCTION__); return -1; } - } while (readl(&p_rxdesc_curr->cmd_sts) & KWGBE_BUFFER_OWNED_BY_DMA); + } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA); if (p_rxdesc_curr->byte_cnt != 0) { debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n", @@ -589,13 +606,13 @@ static int kwgbe_recv(struct eth_device *dev) cmd_sts = readl(&p_rxdesc_curr->cmd_sts); if ((cmd_sts & - (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) - != (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) { + (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) + != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) { printf("Err..(%s) Dropping packet spread on" " multiple descriptors\n", __FUNCTION__); - } else if (cmd_sts & KWGBE_ERROR_SUMMARY) { + } else if (cmd_sts & MVGBE_ERROR_SUMMARY) { printf("Err..(%s) Dropping packet with errors\n", __FUNCTION__); @@ -613,62 +630,72 @@ static int kwgbe_recv(struct eth_device *dev) * free these descriptors and point next in the ring */ p_rxdesc_curr->cmd_sts = - KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT; + MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT; p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; p_rxdesc_curr->byte_cnt = 0; - writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dkwgbe->p_rxdesc_curr); + writel((unsigned)p_rxdesc_curr->nxtdesc_p, + (u32) &dmvgbe->p_rxdesc_curr); return 0; } -int kirkwood_egiga_initialize(bd_t * bis) +int mvgbe_initialize(bd_t *bis) { - struct kwgbe_device *dkwgbe; + struct mvgbe_device *dmvgbe; struct eth_device *dev; int devnum; char *s; - u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS; + u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS; - for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) { + for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) { /*skip if port is configured not to use */ if (used_ports[devnum] == 0) continue; - if (!(dkwgbe = malloc(sizeof(struct kwgbe_device)))) + dmvgbe = malloc(sizeof(struct mvgbe_device)); + + if (!dmvgbe) goto error1; - memset(dkwgbe, 0, sizeof(struct kwgbe_device)); + memset(dmvgbe, 0, sizeof(struct mvgbe_device)); + + dmvgbe->p_rxdesc = + (struct mvgbe_rxdesc *)memalign(PKTALIGN, + MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1); - if (!(dkwgbe->p_rxdesc = - (struct kwgbe_rxdesc *)memalign(PKTALIGN, - KW_RXQ_DESC_ALIGNED_SIZE - * RINGSZ + 1))) + if (!dmvgbe->p_rxdesc) goto error2; - if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ - * PKTSIZE_ALIGN + 1))) + dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, + RINGSZ*PKTSIZE_ALIGN + 1); + + if (!dmvgbe->p_rxbuf) goto error3; - if (!(dkwgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN))) + dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN); + + if (!dmvgbe->p_aligned_txbuf) goto error4; - if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *) - memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) { - free(dkwgbe->p_aligned_txbuf); - error4: - free(dkwgbe->p_rxbuf); - error3: - free(dkwgbe->p_rxdesc); - error2: - free(dkwgbe); - error1: + dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign( + PKTALIGN, sizeof(struct mvgbe_txdesc) + 1); + + if (!dmvgbe->p_txdesc) { + free(dmvgbe->p_aligned_txbuf); +error4: + free(dmvgbe->p_rxbuf); +error3: + free(dmvgbe->p_rxdesc); +error2: + free(dmvgbe); +error1: printf("Err.. %s Failed to allocate memory\n", __FUNCTION__); return -1; } - dev = &dkwgbe->dev; + dev = &dmvgbe->dev; /* must be less than NAMESIZE (16) */ sprintf(dev->name, "egiga%d", devnum); @@ -676,13 +703,15 @@ int kirkwood_egiga_initialize(bd_t * bis) /* Extract the MAC address from the environment */ switch (devnum) { case 0: - dkwgbe->regs = (void *)KW_EGIGA0_BASE; + dmvgbe->regs = (void *)MVGBE0_BASE; s = "ethaddr"; break; +#if defined(MVGBE1_BASE) case 1: - dkwgbe->regs = (void *)KW_EGIGA1_BASE; + dmvgbe->regs = (void *)MVGBE1_BASE; s = "eth1addr"; break; +#endif default: /* this should never happen */ printf("Err..(%s) Invalid device number %d\n", __FUNCTION__, devnum); @@ -690,29 +719,37 @@ int kirkwood_egiga_initialize(bd_t * bis) } while (!eth_getenv_enetaddr(s, dev->enetaddr)) { - /* Generate Random Private MAC addr if not set */ + /* Generate Private MAC addr if not set */ dev->enetaddr[0] = 0x02; dev->enetaddr[1] = 0x50; dev->enetaddr[2] = 0x43; +#if defined (CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION) + /* Generate fixed lower MAC half using devnum */ + dev->enetaddr[3] = 0; + dev->enetaddr[4] = 0; + dev->enetaddr[5] = devnum; +#else + /* Generate random lower MAC half */ dev->enetaddr[3] = get_random_hex(); dev->enetaddr[4] = get_random_hex(); dev->enetaddr[5] = get_random_hex(); +#endif eth_setenv_enetaddr(s, dev->enetaddr); } - dev->init = (void *)kwgbe_init; - dev->halt = (void *)kwgbe_halt; - dev->send = (void *)kwgbe_send; - dev->recv = (void *)kwgbe_recv; - dev->write_hwaddr = (void *)kwgbe_write_hwaddr; + dev->init = (void *)mvgbe_init; + dev->halt = (void *)mvgbe_halt; + dev->send = (void *)mvgbe_send; + dev->recv = (void *)mvgbe_recv; + dev->write_hwaddr = (void *)mvgbe_write_hwaddr; eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register(dev->name, smi_reg_read, smi_reg_write); /* Set phy address of the port */ - miiphy_write(dev->name, KIRKWOOD_PHY_ADR_REQUEST, - KIRKWOOD_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum); + miiphy_write(dev->name, MV_PHY_ADR_REQUEST, + MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum); #endif } return 0; diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h new file mode 100644 index 0000000..3de98d0 --- /dev/null +++ b/drivers/net/mvgbe.h @@ -0,0 +1,505 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * based on - Driver for MV64360X ethernet ports + * Copyright (C) 2002 rabeeh@galileo.co.il + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __MVGBE_H__ +#define __MVGBE_H__ + +/* PHY_BASE_ADR is board specific and can be configured */ +#if defined (CONFIG_PHY_BASE_ADR) +#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR +#else +#define PHY_BASE_ADR 0x08 /* default phy base addr */ +#endif + +/* Constants */ +#define INT_CAUSE_UNMASK_ALL 0x0007ffff +#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff +#define MRU_MASK 0xfff1ffff +#define PHYADR_MASK 0x0000001f +#define PHYREG_MASK 0x0000001f +#define QTKNBKT_DEF_VAL 0x3fffffff +#define QMTBS_DEF_VAL 0x000003ff +#define QTKNRT_DEF_VAL 0x0000fcff +#define RXUQ 0 /* Used Rx queue */ +#define TXUQ 0 /* Used Rx queue */ + +#define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev) +#define MVGBE_REG_WR(adr, val) writel(val, &adr) +#define MVGBE_REG_RD(adr) readl(&adr) +#define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr) +#define MVGBE_REG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr) + +/* Default port configuration value */ +#define PRT_CFG_VAL ( \ + MVGBE_UCAST_MOD_NRML | \ + MVGBE_DFLT_RXQ(RXUQ) | \ + MVGBE_DFLT_RX_ARPQ(RXUQ) | \ + MVGBE_RX_BC_IF_NOT_IP_OR_ARP | \ + MVGBE_RX_BC_IF_IP | \ + MVGBE_RX_BC_IF_ARP | \ + MVGBE_CPTR_TCP_FRMS_DIS | \ + MVGBE_CPTR_UDP_FRMS_DIS | \ + MVGBE_DFLT_RX_TCPQ(RXUQ) | \ + MVGBE_DFLT_RX_UDPQ(RXUQ) | \ + MVGBE_DFLT_RX_BPDUQ(RXUQ)) + +/* Default port extend configuration value */ +#define PORT_CFG_EXTEND_VALUE \ + MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \ + MVGBE_PARTITION_DIS | \ + MVGBE_TX_CRC_GENERATION_EN + +#define GT_MVGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8) + +/* Default sdma control value */ +#define PORT_SDMA_CFG_VALUE ( \ + MVGBE_RX_BURST_SIZE_16_64BIT | \ + MVGBE_BLM_RX_NO_SWAP | \ + MVGBE_BLM_TX_NO_SWAP | \ + GT_MVGBE_IPG_INT_RX(RXUQ) | \ + MVGBE_TX_BURST_SIZE_16_64BIT) + +/* Default port serial control value */ +#define PORT_SERIAL_CONTROL_VALUE ( \ + MVGBE_FORCE_LINK_PASS | \ + MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ + MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ + MVGBE_ADV_NO_FLOW_CTRL | \ + MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + MVGBE_FORCE_BP_MODE_NO_JAM | \ + (1 << 9) /* Reserved bit has to be 1 */ | \ + MVGBE_DO_NOT_FORCE_LINK_FAIL | \ + MVGBE_EN_AUTO_NEG_SPEED_GMII | \ + MVGBE_DTE_ADV_0 | \ + MVGBE_MIIPHY_MAC_MODE | \ + MVGBE_AUTO_NEG_NO_CHANGE | \ + MVGBE_MAX_RX_PACKET_1552BYTE | \ + MVGBE_CLR_EXT_LOOPBACK | \ + MVGBE_SET_FULL_DUPLEX_MODE | \ + MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX) + +/* Tx WRR confoguration macros */ +#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ +#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */ +#define PORT_TOKEN_RATE 1023 /* PTTBRC reg (default) */ +/* MAC accepet/reject macros */ +#define ACCEPT_MAC_ADDR 0 +#define REJECT_MAC_ADDR 1 +/* Size of a Tx/Rx descriptor used in chain list data structure */ +#define MV_RXQ_DESC_ALIGNED_SIZE \ + (((sizeof(struct mvgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN) +/* Buffer offset from buffer pointer */ +#define RX_BUF_OFFSET 0x2 + +/* Port serial status reg (PSR) */ +#define MVGBE_INTERFACE_GMII_MII 0 +#define MVGBE_INTERFACE_PCM 1 +#define MVGBE_LINK_IS_DOWN 0 +#define MVGBE_LINK_IS_UP (1 << 1) +#define MVGBE_PORT_AT_HALF_DUPLEX 0 +#define MVGBE_PORT_AT_FULL_DUPLEX (1 << 2) +#define MVGBE_RX_FLOW_CTRL_DISD 0 +#define MVGBE_RX_FLOW_CTRL_ENBALED (1 << 3) +#define MVGBE_GMII_SPEED_100_10 0 +#define MVGBE_GMII_SPEED_1000 (1 << 4) +#define MVGBE_MII_SPEED_10 0 +#define MVGBE_MII_SPEED_100 (1 << 5) +#define MVGBE_NO_TX 0 +#define MVGBE_TX_IN_PROGRESS (1 << 7) +#define MVGBE_BYPASS_NO_ACTIVE 0 +#define MVGBE_BYPASS_ACTIVE (1 << 8) +#define MVGBE_PORT_NOT_AT_PARTN_STT 0 +#define MVGBE_PORT_AT_PARTN_STT (1 << 9) +#define MVGBE_PORT_TX_FIFO_NOT_EMPTY 0 +#define MVGBE_PORT_TX_FIFO_EMPTY (1 << 10) + +/* These macros describes the Port configuration reg (Px_cR) bits */ +#define MVGBE_UCAST_MOD_NRML 0 +#define MVGBE_UNICAST_PROMISCUOUS_MODE 1 +#define MVGBE_DFLT_RXQ(_x) (_x << 1) +#define MVGBE_DFLT_RX_ARPQ(_x) (_x << 4) +#define MVGBE_RX_BC_IF_NOT_IP_OR_ARP 0 +#define MVGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7) +#define MVGBE_RX_BC_IF_IP 0 +#define MVGBE_REJECT_BC_IF_IP (1 << 8) +#define MVGBE_RX_BC_IF_ARP 0 +#define MVGBE_REJECT_BC_IF_ARP (1 << 9) +#define MVGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12) +#define MVGBE_CPTR_TCP_FRMS_DIS 0 +#define MVGBE_CPTR_TCP_FRMS_EN (1 << 14) +#define MVGBE_CPTR_UDP_FRMS_DIS 0 +#define MVGBE_CPTR_UDP_FRMS_EN (1 << 15) +#define MVGBE_DFLT_RX_TCPQ(_x) (_x << 16) +#define MVGBE_DFLT_RX_UDPQ(_x) (_x << 19) +#define MVGBE_DFLT_RX_BPDUQ(_x) (_x << 22) +#define MVGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25) + +/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ +#define MVGBE_CLASSIFY_EN 1 +#define MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0 +#define MVGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1) +#define MVGBE_PARTITION_DIS 0 +#define MVGBE_PARTITION_EN (1 << 2) +#define MVGBE_TX_CRC_GENERATION_EN 0 +#define MVGBE_TX_CRC_GENERATION_DIS (1 << 3) + +/* These macros describes the Port Sdma configuration reg (SDCR) bits */ +#define MVGBE_RIFB 1 +#define MVGBE_RX_BURST_SIZE_1_64BIT 0 +#define MVGBE_RX_BURST_SIZE_2_64BIT (1 << 1) +#define MVGBE_RX_BURST_SIZE_4_64BIT (1 << 2) +#define MVGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1)) +#define MVGBE_RX_BURST_SIZE_16_64BIT (1 << 3) +#define MVGBE_BLM_RX_NO_SWAP (1 << 4) +#define MVGBE_BLM_RX_BYTE_SWAP 0 +#define MVGBE_BLM_TX_NO_SWAP (1 << 5) +#define MVGBE_BLM_TX_BYTE_SWAP 0 +#define MVGBE_DESCRIPTORS_BYTE_SWAP (1 << 6) +#define MVGBE_DESCRIPTORS_NO_SWAP 0 +#define MVGBE_TX_BURST_SIZE_1_64BIT 0 +#define MVGBE_TX_BURST_SIZE_2_64BIT (1 << 22) +#define MVGBE_TX_BURST_SIZE_4_64BIT (1 << 23) +#define MVGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22)) +#define MVGBE_TX_BURST_SIZE_16_64BIT (1 << 24) + +/* These macros describes the Port serial control reg (PSCR) bits */ +#define MVGBE_SERIAL_PORT_DIS 0 +#define MVGBE_SERIAL_PORT_EN 1 +#define MVGBE_FORCE_LINK_PASS (1 << 1) +#define MVGBE_DO_NOT_FORCE_LINK_PASS 0 +#define MVGBE_EN_AUTO_NEG_FOR_DUPLX 0 +#define MVGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2) +#define MVGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0 +#define MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) +#define MVGBE_ADV_NO_FLOW_CTRL 0 +#define MVGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4) +#define MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 +#define MVGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5) +#define MVGBE_FORCE_BP_MODE_NO_JAM 0 +#define MVGBE_FORCE_BP_MODE_JAM_TX (1 << 7) +#define MVGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8) +#define MVGBE_FORCE_LINK_FAIL 0 +#define MVGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10) +#define MVGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13) +#define MVGBE_EN_AUTO_NEG_SPEED_GMII 0 +#define MVGBE_DTE_ADV_0 0 +#define MVGBE_DTE_ADV_1 (1 << 14) +#define MVGBE_MIIPHY_MAC_MODE 0 +#define MVGBE_MIIPHY_PHY_MODE (1 << 15) +#define MVGBE_AUTO_NEG_NO_CHANGE 0 +#define MVGBE_RESTART_AUTO_NEG (1 << 16) +#define MVGBE_MAX_RX_PACKET_1518BYTE 0 +#define MVGBE_MAX_RX_PACKET_1522BYTE (1 << 17) +#define MVGBE_MAX_RX_PACKET_1552BYTE (1 << 18) +#define MVGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17)) +#define MVGBE_MAX_RX_PACKET_9192BYTE (1 << 19) +#define MVGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17)) +#define MVGBE_SET_EXT_LOOPBACK (1 << 20) +#define MVGBE_CLR_EXT_LOOPBACK 0 +#define MVGBE_SET_FULL_DUPLEX_MODE (1 << 21) +#define MVGBE_SET_HALF_DUPLEX_MODE 0 +#define MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22) +#define MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 +#define MVGBE_SET_GMII_SPEED_TO_10_100 0 +#define MVGBE_SET_GMII_SPEED_TO_1000 (1 << 23) +#define MVGBE_SET_MII_SPEED_TO_10 0 +#define MVGBE_SET_MII_SPEED_TO_100 (1 << 24) + +/* SMI register fields */ +#define MVGBE_PHY_SMI_TIMEOUT 10000 +#define MVGBE_PHY_SMI_DATA_OFFS 0 /* Data */ +#define MVGBE_PHY_SMI_DATA_MASK (0xffff << MVGBE_PHY_SMI_DATA_OFFS) +#define MVGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ +#define MVGBE_PHY_SMI_DEV_ADDR_MASK \ + (PHYADR_MASK << MVGBE_PHY_SMI_DEV_ADDR_OFFS) +#define MVGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */ +#define MVGBE_SMI_REG_ADDR_MASK \ + (PHYADR_MASK << MVGBE_SMI_REG_ADDR_OFFS) +#define MVGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ +#define MVGBE_PHY_SMI_OPCODE_MASK (3 << MVGBE_PHY_SMI_OPCODE_OFFS) +#define MVGBE_PHY_SMI_OPCODE_WRITE (0 << MVGBE_PHY_SMI_OPCODE_OFFS) +#define MVGBE_PHY_SMI_OPCODE_READ (1 << MVGBE_PHY_SMI_OPCODE_OFFS) +#define MVGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */ +#define MVGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */ + +/* SDMA command status fields macros */ +/* Tx & Rx descriptors status */ +#define MVGBE_ERROR_SUMMARY 1 +/* Tx & Rx descriptors command */ +#define MVGBE_BUFFER_OWNED_BY_DMA (1 << 31) +/* Tx descriptors status */ +#define MVGBE_LC_ERROR 0 +#define MVGBE_UR_ERROR (1 << 1) +#define MVGBE_RL_ERROR (1 << 2) +#define MVGBE_LLC_SNAP_FORMAT (1 << 9) +#define MVGBE_TX_LAST_FRAME (1 << 20) + +/* Rx descriptors status */ +#define MVGBE_CRC_ERROR 0 +#define MVGBE_OVERRUN_ERROR (1 << 1) +#define MVGBE_MAX_FRAME_LENGTH_ERROR (1 << 2) +#define MVGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1)) +#define MVGBE_VLAN_TAGGED (1 << 19) +#define MVGBE_BPDU_FRAME (1 << 20) +#define MVGBE_TCP_FRAME_OVER_IP_V_4 0 +#define MVGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21) +#define MVGBE_OTHER_FRAME_TYPE (1 << 22) +#define MVGBE_LAYER_2_IS_MVGBE_V_2 (1 << 23) +#define MVGBE_FRAME_TYPE_IP_V_4 (1 << 24) +#define MVGBE_FRAME_HEADER_OK (1 << 25) +#define MVGBE_RX_LAST_DESC (1 << 26) +#define MVGBE_RX_FIRST_DESC (1 << 27) +#define MVGBE_UNKNOWN_DESTINATION_ADDR (1 << 28) +#define MVGBE_RX_EN_INTERRUPT (1 << 29) +#define MVGBE_LAYER_4_CHECKSUM_OK (1 << 30) + +/* Rx descriptors byte count */ +#define MVGBE_FRAME_FRAGMENTED (1 << 2) + +/* Tx descriptors command */ +#define MVGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10) +#define MVGBE_FRAME_SET_TO_VLAN (1 << 15) +#define MVGBE_TCP_FRAME 0 +#define MVGBE_UDP_FRAME (1 << 16) +#define MVGBE_GEN_TCP_UDP_CHECKSUM (1 << 17) +#define MVGBE_GEN_IP_V_4_CHECKSUM (1 << 18) +#define MVGBE_ZERO_PADDING (1 << 19) +#define MVGBE_TX_LAST_DESC (1 << 20) +#define MVGBE_TX_FIRST_DESC (1 << 21) +#define MVGBE_GEN_CRC (1 << 22) +#define MVGBE_TX_EN_INTERRUPT (1 << 23) +#define MVGBE_AUTO_MODE (1 << 30) + +/* Address decode parameters */ +/* Ethernet Base Address Register bits */ +#define EBAR_TARGET_DRAM 0x00000000 +#define EBAR_TARGET_DEVICE 0x00000001 +#define EBAR_TARGET_CBS 0x00000002 +#define EBAR_TARGET_PCI0 0x00000003 +#define EBAR_TARGET_PCI1 0x00000004 +#define EBAR_TARGET_CUNIT 0x00000005 +#define EBAR_TARGET_AUNIT 0x00000006 +#define EBAR_TARGET_GUNIT 0x00000007 + +/* Window attrib */ +#define EBAR_DRAM_CS0 0x00000E00 +#define EBAR_DRAM_CS1 0x00000D00 +#define EBAR_DRAM_CS2 0x00000B00 +#define EBAR_DRAM_CS3 0x00000700 + +/* DRAM Target interface */ +#define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000 +#define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000 +#define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000 + +/* Device Bus Target interface */ +#define EBAR_DEVICE_DEVCS0 0x00001E00 +#define EBAR_DEVICE_DEVCS1 0x00001D00 +#define EBAR_DEVICE_DEVCS2 0x00001B00 +#define EBAR_DEVICE_DEVCS3 0x00001700 +#define EBAR_DEVICE_BOOTCS3 0x00000F00 + +/* PCI Target interface */ +#define EBAR_PCI_BYTE_SWAP 0x00000000 +#define EBAR_PCI_NO_SWAP 0x00000100 +#define EBAR_PCI_BYTE_WORD_SWAP 0x00000200 +#define EBAR_PCI_WORD_SWAP 0x00000300 +#define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 +#define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400 +#define EBAR_PCI_IO_SPACE 0x00000000 +#define EBAR_PCI_MEMORY_SPACE 0x00000800 +#define EBAR_PCI_REQ64_FORCE 0x00000000 +#define EBAR_PCI_REQ64_SIZE 0x00001000 + +/* Window access control */ +#define EWIN_ACCESS_NOT_ALLOWED 0 +#define EWIN_ACCESS_READ_ONLY 1 +#define EWIN_ACCESS_FULL ((1 << 1) | 1) + +/* structures represents Controller registers */ +struct mvgbe_barsz { + u32 bar; + u32 size; +}; + +struct mvgbe_rxcdp { + struct mvgbe_rxdesc *rxcdp; + u32 rxcdp_pad[3]; +}; + +struct mvgbe_tqx { + u32 qxttbc; + u32 tqxtbc; + u32 tqxac; + u32 tqxpad; +}; + +struct mvgbe_registers { + u32 phyadr; + u32 smi; + u32 euda; + u32 eudid; + u8 pad1[0x080 - 0x00c - 4]; + u32 euic; + u32 euim; + u8 pad2[0x094 - 0x084 - 4]; + u32 euea; + u32 euiae; + u8 pad3[0x0b0 - 0x098 - 4]; + u32 euc; + u8 pad3a[0x200 - 0x0b0 - 4]; + struct mvgbe_barsz barsz[6]; + u8 pad4[0x280 - 0x22c - 4]; + u32 ha_remap[4]; + u32 bare; + u32 epap; + u8 pad5[0x400 - 0x294 - 4]; + u32 pxc; + u32 pxcx; + u32 mii_ser_params; + u8 pad6[0x410 - 0x408 - 4]; + u32 evlane; + u32 macal; + u32 macah; + u32 sdc; + u32 dscp[7]; + u32 psc0; + u32 vpt2p; + u32 ps0; + u32 tqc; + u32 psc1; + u32 ps1; + u32 mrvl_header; + u8 pad7[0x460 - 0x454 - 4]; + u32 ic; + u32 ice; + u32 pim; + u32 peim; + u8 pad8[0x474 - 0x46c - 4]; + u32 pxtfut; + u32 pad9; + u32 pxmfs; + u32 pad10; + u32 pxdfc; + u32 pxofc; + u8 pad11[0x494 - 0x488 - 4]; + u32 peuiae; + u8 pad12[0x4bc - 0x494 - 4]; + u32 eth_type_prio; + u8 pad13[0x4dc - 0x4bc - 4]; + u32 tqfpc; + u32 pttbrc; + u32 tqc1; + u32 pmtu; + u32 pmtbs; + u8 pad14[0x60c - 0x4ec - 4]; + struct mvgbe_rxcdp rxcdp[7]; + struct mvgbe_rxdesc *rxcdp7; + u32 rqc; + struct mvgbe_txdesc *tcsdp; + u8 pad15[0x6c0 - 0x684 - 4]; + struct mvgbe_txdesc *tcqdp[8]; + u8 pad16[0x700 - 0x6dc - 4]; + struct mvgbe_tqx tqx[8]; + u32 pttbc; + u8 pad17[0x7a8 - 0x780 - 4]; + u32 tqxipg0; + u32 pad18[3]; + u32 tqxipg1; + u8 pad19[0x7c0 - 0x7b8 - 4]; + u32 hitkninlopkt; + u32 hitkninasyncpkt; + u32 lotkninasyncpkt; + u32 pad20; + u32 ts; + u8 pad21[0x3000 - 0x27d0 - 4]; + u32 pad20_1[32]; /* mib counter registes */ + u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32]; + u32 dfsmt[64]; + u32 dfomt[64]; + u32 dfut[4]; + u8 pad23[0xe20c0 - 0x7360c - 4]; + u32 pmbus_top_arbiter; +}; + +/* structures/enums needed by driver */ +enum mvgbe_adrwin { + MVGBE_WIN0, + MVGBE_WIN1, + MVGBE_WIN2, + MVGBE_WIN3, + MVGBE_WIN4, + MVGBE_WIN5 +}; + +enum mvgbe_target { + MVGBE_TARGET_DRAM, + MVGBE_TARGET_DEV, + MVGBE_TARGET_CBS, + MVGBE_TARGET_PCI0, + MVGBE_TARGET_PCI1 +}; + +struct mvgbe_winparam { + enum mvgbe_adrwin win; /* Window number */ + enum mvgbe_target target; /* System targets */ + u16 attrib; /* BAR attrib. See above macros */ + u32 base_addr; /* Window base address in u32 form */ + u32 high_addr; /* Window high address in u32 form */ + u32 size; /* Size in MBytes. Must be % 64Kbyte. */ + int enable; /* Enable/disable access to the window. */ + u16 access_ctrl; /*Access ctrl register. see above macros */ +}; + +struct mvgbe_rxdesc { + u32 cmd_sts; /* Descriptor command status */ + u16 buf_size; /* Buffer size */ + u16 byte_cnt; /* Descriptor buffer byte count */ + u8 *buf_ptr; /* Descriptor buffer pointer */ + struct mvgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */ +}; + +struct mvgbe_txdesc { + u32 cmd_sts; /* Descriptor command status */ + u16 l4i_chk; /* CPU provided TCP Checksum */ + u16 byte_cnt; /* Descriptor buffer byte count */ + u8 *buf_ptr; /* Descriptor buffer ptr */ + struct mvgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */ +}; + +/* port device data struct */ +struct mvgbe_device { + struct eth_device dev; + struct mvgbe_registers *regs; + struct mvgbe_txdesc *p_txdesc; + struct mvgbe_rxdesc *p_rxdesc; + struct mvgbe_rxdesc *p_rxdesc_curr; + u8 *p_rxbuf; + u8 *p_aligned_txbuf; +}; + +#endif /* __MVGBE_H__ */ diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 5fa6f61..54c4a70 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -95,14 +95,23 @@ static struct tsec_info_struct tsec_info[] = { #endif }; +/* + * Initialize all the TSEC devices + * + * Returns the number of TSEC devices that were initialized + */ int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num) { int i; + int ret, count = 0; - for (i = 0; i < num; i++) - tsec_initialize(bis, &tsecs[i]); + for (i = 0; i < num; i++) { + ret = tsec_initialize(bis, &tsecs[i]); + if (ret > 0) + count += ret; + } - return 0; + return count; } int tsec_standard_init(bd_t *bis) @@ -1631,6 +1640,27 @@ static struct phy_info phy_info_dm9161 = { }, }; +/* micrel KSZ804 */ +static struct phy_info phy_info_ksz804 = { + 0x0022151, + "Micrel KSZ804 PHY", + 4, + (struct phy_cmd[]) { /* config */ + {PHY_BMCR, PHY_BMCR_RESET, NULL}, + {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + {PHY_BMSR, miim_read, NULL}, + {PHY_BMSR, miim_read, &mii_parse_sr}, + {PHY_BMSR, miim_read, &mii_parse_link}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + } +}; + /* a generic flavor. */ static struct phy_info phy_info_generic = { 0, @@ -1794,6 +1824,7 @@ static struct phy_info *phy_info[] = { &phy_info_M88E1145, &phy_info_M88E1149S, &phy_info_dm9161, + &phy_info_ksz804, &phy_info_lxt971, &phy_info_VSC8211, &phy_info_VSC8244, diff --git a/drivers/net/uli526x.c b/drivers/net/uli526x.c index 9477851..56eee7b 100644 --- a/drivers/net/uli526x.c +++ b/drivers/net/uli526x.c @@ -225,7 +225,7 @@ int uli526x_initialize(bd_t *bis) iobase &= ~0xf; dev = (struct eth_device *)malloc(sizeof *dev); - sprintf(dev->name, "uli526x#%d\n", card_number); + sprintf(dev->name, "uli526x#%d", card_number); db = (struct uli526x_board_info *) malloc(sizeof(struct uli526x_board_info)); diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c index f28d42b..e0ad029 100644 --- a/drivers/spi/bfin_spi.c +++ b/drivers/spi/bfin_spi.c @@ -13,6 +13,8 @@ #include <spi.h> #include <asm/blackfin.h> +#include <asm/gpio.h> +#include <asm/portmux.h> #include <asm/mach-common/bits/spi.h> struct bfin_spi_slave { @@ -33,54 +35,110 @@ MAKE_SPI_FUNC(SPI_BAUD, 0x14) #define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave) -__attribute__((weak)) +#define MAX_CTRL_CS 7 + +#define gpio_cs(cs) ((cs) - MAX_CTRL_CS) +#ifdef CONFIG_BFIN_SPI_GPIO_CS +# define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS) +#else +# define is_gpio_cs(cs) 0 +#endif + int spi_cs_is_valid(unsigned int bus, unsigned int cs) { -#if defined(__ADSPBF538__) || defined(__ADSPBF539__) - /* The SPI1/SPI2 buses are weird ... only 1 CS */ - if (bus > 0 && cs != 1) - return 0; -#endif - return (cs >= 1 && cs <= 7); + if (is_gpio_cs(cs)) + return gpio_is_valid(gpio_cs(cs)); + else + return (cs >= 1 && cs <= MAX_CTRL_CS); } -__attribute__((weak)) void spi_cs_activate(struct spi_slave *slave) { struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); - write_SPI_FLG(bss, - (read_SPI_FLG(bss) & - ~((!bss->flg << 8) << slave->cs)) | - (1 << slave->cs)); + + if (is_gpio_cs(slave->cs)) { + unsigned int cs = gpio_cs(slave->cs); + gpio_set_value(cs, bss->flg); + debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs)); + } else { + write_SPI_FLG(bss, + (read_SPI_FLG(bss) & + ~((!bss->flg << 8) << slave->cs)) | + (1 << slave->cs)); + debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss)); + } + SSYNC(); - debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss)); } -__attribute__((weak)) void spi_cs_deactivate(struct spi_slave *slave) { struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); - u16 flg; - - /* make sure we force the cs to deassert rather than let the - * pin float back up. otherwise, exact timings may not be - * met some of the time leading to random behavior (ugh). - */ - flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs); - write_SPI_FLG(bss, flg); - SSYNC(); - debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss)); - flg &= ~(1 << slave->cs); - write_SPI_FLG(bss, flg); + if (is_gpio_cs(slave->cs)) { + unsigned int cs = gpio_cs(slave->cs); + gpio_set_value(cs, !bss->flg); + debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs)); + } else { + u16 flg; + + /* make sure we force the cs to deassert rather than let the + * pin float back up. otherwise, exact timings may not be + * met some of the time leading to random behavior (ugh). + */ + flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs); + write_SPI_FLG(bss, flg); + SSYNC(); + debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss)); + + flg &= ~(1 << slave->cs); + write_SPI_FLG(bss, flg); + debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss)); + } + SSYNC(); - debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss)); } void spi_init() { } +#ifdef SPI_CTL +# define SPI0_CTL SPI_CTL +#endif + +#define SPI_PINS(n) \ + [n] = { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 } +static unsigned short pins[][5] = { +#ifdef SPI0_CTL + SPI_PINS(0), +#endif +#ifdef SPI1_CTL + SPI_PINS(1), +#endif +#ifdef SPI2_CTL + SPI_PINS(2), +#endif +}; + +#define SPI_CS_PINS(n) \ + [n] = { \ + P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \ + P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \ + P_SPI##n##_SSEL7, \ + } +static const unsigned short cs_pins[][7] = { +#ifdef SPI0_CTL + SPI_CS_PINS(0), +#endif +#ifdef SPI1_CTL + SPI_CS_PINS(1), +#endif +#ifdef SPI2_CTL + SPI_CS_PINS(2), +#endif +}; + struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { @@ -92,11 +150,14 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!spi_cs_is_valid(bus, cs)) return NULL; + if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) { + debug("%s: invalid bus %u\n", __func__, bus); + return NULL; + } switch (bus) { -#ifdef SPI_CTL -# define SPI0_CTL SPI_CTL -#endif +#ifdef SPI0_CTL case 0: mmr_base = SPI0_CTL; break; +#endif #ifdef SPI1_CTL case 1: mmr_base = SPI1_CTL; break; #endif @@ -142,168 +203,21 @@ void spi_free_slave(struct spi_slave *slave) free(bss); } -static void spi_portmux(struct spi_slave *slave) -{ -#if defined(__ADSPBF51x__) -#define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func) - u16 f_mux = bfin_read_PORTF_MUX(); - u16 f_fer = bfin_read_PORTF_FER(); - u16 g_mux = bfin_read_PORTG_MUX(); - u16 g_fer = bfin_read_PORTG_FER(); - u16 h_mux = bfin_read_PORTH_MUX(); - u16 h_fer = bfin_read_PORTH_FER(); - switch (slave->bus) { - case 0: - /* set SCK/MISO/MOSI */ - SET_MUX(g, 7, 1); - g_fer |= PG12 | PG13 | PG14; - switch (slave->cs) { - case 1: SET_MUX(f, 2, 1); f_fer |= PF7; break; - case 2: /* see G above */ g_fer |= PG15; break; - case 3: SET_MUX(h, 1, 3); f_fer |= PH4; break; - case 4: /* no muxing */ h_fer |= PH8; break; - case 5: SET_MUX(g, 1, 3); h_fer |= PG3; break; - case 6: /* no muxing */ break; - case 7: /* no muxing */ break; - } - case 1: - /* set SCK/MISO/MOSI */ - SET_MUX(h, 0, 2); - h_fer |= PH1 | PH2 | PH3; - switch (slave->cs) { - case 1: SET_MUX(h, 2, 3); h_fer |= PH6; break; - case 2: SET_MUX(f, 0, 3); f_fer |= PF0; break; - case 3: SET_MUX(g, 0, 3); g_fer |= PG0; break; - case 4: SET_MUX(f, 3, 3); f_fer |= PF8; break; - case 5: SET_MUX(g, 6, 3); h_fer |= PG11; break; - case 6: /* no muxing */ break; - case 7: /* no muxing */ break; - } - } - bfin_write_PORTF_MUX(f_mux); - bfin_write_PORTF_FER(f_fer); - bfin_write_PORTG_MUX(g_mux); - bfin_write_PORTG_FER(g_fer); - bfin_write_PORTH_MUX(h_mux); - bfin_write_PORTH_FER(h_fer); -#elif defined(__ADSPBF52x__) -#define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func) - u16 f_mux = bfin_read_PORTF_MUX(); - u16 f_fer = bfin_read_PORTF_FER(); - u16 g_mux = bfin_read_PORTG_MUX(); - u16 g_fer = bfin_read_PORTG_FER(); - u16 h_mux = bfin_read_PORTH_MUX(); - u16 h_fer = bfin_read_PORTH_FER(); - /* set SCK/MISO/MOSI */ - SET_MUX(g, 0, 3); - g_fer |= PG2 | PG3 | PG4; - switch (slave->cs) { - case 1: /* see G above */ g_fer |= PG1; break; - case 2: SET_MUX(f, 4, 3); f_fer |= PF12; break; - case 3: SET_MUX(f, 4, 3); f_fer |= PF13; break; - case 4: SET_MUX(h, 1, 1); h_fer |= PH8; break; - case 5: SET_MUX(h, 2, 1); h_fer |= PH9; break; - case 6: SET_MUX(f, 1, 3); f_fer |= PF9; break; - case 7: SET_MUX(f, 2, 3); f_fer |= PF10; break; - } - bfin_write_PORTF_MUX(f_mux); - bfin_write_PORTF_FER(f_fer); - bfin_write_PORTG_MUX(g_mux); - bfin_write_PORTG_FER(g_fer); - bfin_write_PORTH_MUX(h_mux); - bfin_write_PORTH_FER(h_fer); -#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) - u16 mux = bfin_read_PORT_MUX(); - u16 f_fer = bfin_read_PORTF_FER(); - /* set SCK/MISO/MOSI */ - f_fer |= PF11 | PF12 | PF13; - switch (slave->cs) { - case 1: f_fer |= PF10; break; - case 2: mux |= PJSE; break; - case 3: mux |= PJSE; break; - case 4: mux |= PFS4E; f_fer |= PF6; break; - case 5: mux |= PFS5E; f_fer |= PF5; break; - case 6: mux |= PFS6E; f_fer |= PF4; break; - case 7: mux |= PJCE_SPI; break; - } - bfin_write_PORT_MUX(mux); - bfin_write_PORTF_FER(f_fer); -#elif defined(__ADSPBF538__) || defined(__ADSPBF539__) - u16 fer, pins; - if (slave->bus == 1) - pins = PD0 | PD1 | PD2 | (slave->cs == 1 ? PD4 : 0); - else if (slave->bus == 2) - pins = PD5 | PD6 | PD7 | (slave->cs == 1 ? PD9 : 0); - else - pins = 0; - if (pins) { - fer = bfin_read_PORTDIO_FER(); - fer &= ~pins; - bfin_write_PORTDIO_FER(fer); - } -#elif defined(__ADSPBF54x__) -#define DO_MUX(port, pin) \ - mux = ((mux & ~PORT_x_MUX_##pin##_MASK) | PORT_x_MUX_##pin##_FUNC_1); \ - fer |= P##port##pin; - u32 mux; - u16 fer; - switch (slave->bus) { - case 0: - mux = bfin_read_PORTE_MUX(); - fer = bfin_read_PORTE_FER(); - /* set SCK/MISO/MOSI */ - DO_MUX(E, 0); - DO_MUX(E, 1); - DO_MUX(E, 2); - switch (slave->cs) { - case 1: DO_MUX(E, 4); break; - case 2: DO_MUX(E, 5); break; - case 3: DO_MUX(E, 6); break; - } - bfin_write_PORTE_MUX(mux); - bfin_write_PORTE_FER(fer); - break; - case 1: - mux = bfin_read_PORTG_MUX(); - fer = bfin_read_PORTG_FER(); - /* set SCK/MISO/MOSI */ - DO_MUX(G, 8); - DO_MUX(G, 9); - DO_MUX(G, 10); - switch (slave->cs) { - case 1: DO_MUX(G, 5); break; - case 2: DO_MUX(G, 6); break; - case 3: DO_MUX(G, 7); break; - } - bfin_write_PORTG_MUX(mux); - bfin_write_PORTG_FER(fer); - break; - case 2: - mux = bfin_read_PORTB_MUX(); - fer = bfin_read_PORTB_FER(); - /* set SCK/MISO/MOSI */ - DO_MUX(B, 12); - DO_MUX(B, 13); - DO_MUX(B, 14); - switch (slave->cs) { - case 1: DO_MUX(B, 9); break; - case 2: DO_MUX(B, 10); break; - case 3: DO_MUX(B, 11); break; - } - bfin_write_PORTB_MUX(mux); - bfin_write_PORTB_FER(fer); - break; - } -#endif -} - int spi_claim_bus(struct spi_slave *slave) { struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); - spi_portmux(slave); + if (is_gpio_cs(slave->cs)) { + unsigned int cs = gpio_cs(slave->cs); + gpio_request(cs, "bfin-spi"); + gpio_direction_output(cs, !bss->flg); + pins[slave->bus][0] = P_DONTCARE; + } else + pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1]; + peripheral_request_list(pins[slave->bus], "bfin-spi"); + write_SPI_CTL(bss, bss->ctl); write_SPI_BAUD(bss, bss->baud); SSYNC(); @@ -314,7 +228,13 @@ int spi_claim_bus(struct spi_slave *slave) void spi_release_bus(struct spi_slave *slave) { struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + + peripheral_free_list(pins[slave->bus]); + if (is_gpio_cs(slave->cs)) + gpio_free(gpio_cs(slave->cs)); + write_SPI_CTL(bss, 0); SSYNC(); } diff --git a/examples/standalone/smc911x_eeprom.c b/examples/standalone/smc911x_eeprom.c index c51a050..00e8266 100644 --- a/examples/standalone/smc911x_eeprom.c +++ b/examples/standalone/smc911x_eeprom.c @@ -240,7 +240,7 @@ static void dump_eeprom(struct eth_device *dev) static int smc911x_init(struct eth_device *dev) { /* See if there is anything there */ - if (!smc911x_detect_chip(dev)) + if (smc911x_detect_chip(dev)) return 1; smc911x_reset(dev); diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h deleted file mode 100644 index 3920d35..0000000 --- a/include/configs/EP1C20.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*------------------------------------------------------------------------ - * BOARD/CPU - *----------------------------------------------------------------------*/ -#define CONFIG_EP1C20 1 /* EP1C20 board */ -#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ - -#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */ -#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * CACHE -- the following will support II/s and II/f. The II/s does not - * have dcache, so the cache instructions will behave as NOPs. - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */ -#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */ -#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ -#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ - -/*------------------------------------------------------------------------ - * MEMORY BASE ADDRESSES - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */ -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */ -#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */ -#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */ -#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/ - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 128k */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */ - -/*------------------------------------------------------------------------ - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN) - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#define CONFIG_ALTERA_UART 1 /* Use altera uart */ -#if defined(CONFIG_ALTERA_JTAG_UART) -#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ -#else -#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ -#endif - -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ -#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ - -/*------------------------------------------------------------------------ - * EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for - * epcs device access is enabled. The base address is the epcs - * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK. - * The register base is currently at offset 0x600 from the memory base. - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NIOS_EPCSBASE 0x02100200 /* EPCS register base */ - -/*------------------------------------------------------------------------ - * DEBUG - *----------------------------------------------------------------------*/ -#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ - -/*------------------------------------------------------------------------ - * TIMEBASE -- - * - * The high res timer defaults to 1 msec. Since it includes the period - * registers, the interrupt frequency can be reduced using TMRCNT. - * If the default period is acceptable, TMRCNT can be left undefined. - * TMRMS represents the desired mecs per tick (msecs per interrupt). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_HZ 1000 /* Always 1000 */ -#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ -#define CONFIG_SYS_NIOS_TMRCNT \ - (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) - -/*------------------------------------------------------------------------ - * STATUS LED -- Provides a simple blinking led. For Nios2 each board - * must implement its own led routines -- leds are, after all, - * board-specific, no? - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ -#define CONFIG_STATUS_LED /* Enable status driver */ - -#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ -#define STATUS_LED_STATE 1 /* Blinking */ -#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */ - -/*------------------------------------------------------------------------ - * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... - * and really doesn't need any additional clutter. So I choose the lazy - * way out to avoid changes there -- define the base address to ensure - * cache bypass so there's no need to monkey with inx/outx macros. - *----------------------------------------------------------------------*/ -#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ -#define CONFIG_NET_MULTI -#define CONFIG_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES - -#undef CONFIG_CMD_BOOTD -#undef CONFIG_CMD_CONSOLE -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_ITEST -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_SETGETDCR -#undef CONFIG_CMD_SOURCE -#undef CONFIG_CMD_XIMG - - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* Provide extended help*/ -#define CONFIG_SYS_PROMPT "==> " /* Command prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ -#define CONFIG_SYS_MAXARGS 16 /* Max command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */ -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000 - -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -#endif /* __CONFIG_H */ diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h deleted file mode 100644 index bfbf8c1..0000000 --- a/include/configs/EP1S10.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*------------------------------------------------------------------------ - * BOARD/CPU - *----------------------------------------------------------------------*/ -#define CONFIG_EP1S10 1 /* EP1S10 board */ -#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ - -#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */ -#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */ - -/*------------------------------------------------------------------------ - * CACHE -- the following will support II/s and II/f. The II/s does not - * have dcache, so the cache instructions will behave as NOPs. - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */ -#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */ -#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ -#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ - -/*------------------------------------------------------------------------ - * MEMORY BASE ADDRESSES - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */ -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */ -#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */ -#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */ -#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB */ - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256k */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) /* 256k heap */ - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ - -/*------------------------------------------------------------------------ - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_FLASH_BASE, since we assume that u-boot is stored at the bottom - * of flash memory. This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#define CONFIG_ALTERA_UART 1 /* Use altera uart */ -#if defined(CONFIG_ALTERA_JTAG_UART) -#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ -#else -#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ -#endif - -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ -#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ - -/*------------------------------------------------------------------------ - * EPCS Device -- None for stratix. - *----------------------------------------------------------------------*/ -#undef CONFIG_SYS_NIOS_EPCSBASE - -/*------------------------------------------------------------------------ - * DEBUG - *----------------------------------------------------------------------*/ -#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ - -/*------------------------------------------------------------------------ - * TIMEBASE -- - * - * The high res timer defaults to 1 msec. Since it includes the period - * registers, the interrupt frequency can be reduced using TMRCNT. - * If the default period is acceptable, TMRCNT can be left undefined. - * TMRMS represents the desired mecs per tick (msecs per interrupt). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_HZ 1000 /* Always 1000 */ -#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ -#define CONFIG_SYS_NIOS_TMRCNT \ - (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) - -/*------------------------------------------------------------------------ - * STATUS LED -- Provides a simple blinking led. For Nios2 each board - * must implement its own led routines -- since leds are board-specific. - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ -#define CONFIG_STATUS_LED /* Enable status driver */ - -#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ -#define STATUS_LED_STATE 1 /* Blinking */ -#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */ - -/*------------------------------------------------------------------------ - * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... - * and really doesn't need any additional clutter. So I choose the lazy - * way out to avoid changes there -- define the base address to ensure - * cache bypass so there's no need to monkey with inx/outx macros. - *----------------------------------------------------------------------*/ -#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ -#define CONFIG_NET_MULTI -#define CONFIG_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_BDI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVES - - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* Provide extended help*/ -#define CONFIG_SYS_PROMPT "==> " /* Command prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ -#define CONFIG_SYS_MAXARGS 16 /* Max command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */ -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000 - -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -#endif /* __CONFIG_H */ diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h deleted file mode 100644 index 4d905fe..0000000 --- a/include/configs/EP1S40.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*------------------------------------------------------------------------ - * BOARD/CPU - *----------------------------------------------------------------------*/ -#define CONFIG_EP1S40 1 /* EP1S40 board */ -#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ - -#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */ -#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */ - -/*------------------------------------------------------------------------ - * CACHE -- the following will support II/s and II/f. The II/s does not - * have dcache, so the cache instructions will behave as NOPs. - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */ -#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */ -#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ -#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ - -/*------------------------------------------------------------------------ - * MEMORY BASE ADDRESSES - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */ -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */ -#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */ -#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */ -#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB */ - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256k */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) /* 256k heap */ - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ - -/*------------------------------------------------------------------------ - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_FLASH_BASE, since we assume that u-boot is stored at the bottom - * of flash memory. This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#define CONFIG_ALTERA_UART 1 /* Use altera uart */ -#if defined(CONFIG_ALTERA_JTAG_UART) -#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ -#else -#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ -#endif - -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ -#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ - -/*------------------------------------------------------------------------ - * EPCS Device -- None for stratix. - *----------------------------------------------------------------------*/ -#undef CONFIG_SYS_NIOS_EPCSBASE - -/*------------------------------------------------------------------------ - * DEBUG - *----------------------------------------------------------------------*/ -#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ - -/*------------------------------------------------------------------------ - * TIMEBASE -- - * - * The high res timer defaults to 1 msec. Since it includes the period - * registers, the interrupt frequency can be reduced using TMRCNT. - * If the default period is acceptable, TMRCNT can be left undefined. - * TMRMS represents the desired mecs per tick (msecs per interrupt). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_HZ 1000 /* Always 1000 */ -#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec) */ -#define CONFIG_SYS_NIOS_TMRCNT \ - (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) - -/*------------------------------------------------------------------------ - * STATUS LED -- Provides a simple blinking led. For Nios2 each board - * must implement its own led routines -- since leds are board-specific. - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ -#define CONFIG_STATUS_LED /* Enable status driver */ - -#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ -#define STATUS_LED_STATE 1 /* Blinking */ -#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */ - -/*------------------------------------------------------------------------ - * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... - * and really doesn't need any additional clutter. So I choose the lazy - * way out to avoid changes there -- define the base address to ensure - * cache bypass so there's no need to monkey with inx/outx macros. - *----------------------------------------------------------------------*/ -#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ -#define CONFIG_NET_MULTI -#define CONFIG_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_BDI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVES - - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* Provide extended help*/ -#define CONFIG_SYS_PROMPT "==> " /* Command prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ -#define CONFIG_SYS_MAXARGS 16 /* Max command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */ -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000 - -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h new file mode 100644 index 0000000..6cd5da7 --- /dev/null +++ b/include/configs/MPC8308RDB.h @@ -0,0 +1,560 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ +#define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */ + +#define CONFIG_MISC_INIT_R + +/* + * On-board devices + * + * TSEC1 is SoC TSEC + * TSEC2 is VSC switch + */ +#define CONFIG_TSEC1 +#define CONFIG_VSC7385_ENET + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +/* + * Hardware Reset Configuration Word + * if CLKIN is 66.66MHz, then + * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz + * We choose the A type silicon as default, so the core is 400Mhz. + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_SVCOD_DIV_2 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_CORE_TO_CSB_3X1) +/* + * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits + * in 8308's HRCWH according to the manual, but original Freescale's + * code has them and I've expirienced some problems using the board + * with BDI3000 attached when I've tried to set these bits to zero + * (UART doesn't work after the 'reset run' command). + */ +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN) + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH 0x01b7d103 +#define CONFIG_SYS_SICRL 0x00000040 /* 3.3V, no delay */ + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * SERDES + */ +#define CONFIG_FSL_SERDES +#define CONFIG_FSL_SERDES1 0xe3000 + +/* + * Arbiter Setup + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ +#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ + | DDRCDR_PZ_LOZ \ + | DDRCDR_NZ_LOZ \ + | DDRCDR_ODT \ + | DDRCDR_Q_DRN) + /* 0x7b880001 */ +/* + * Manually set up DDR parameters + * consist of two chips HY5PS12621BFP-C4 from HYNIX + */ + +#define CONFIG_SYS_DDR_SIZE 128 /* MB */ + +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | 0x00010000 /* ODT_WR to CSn */ \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) + /* 0x80010102 */ +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00220802 */ +#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (5 << TIMING_CFG1_CASLAT_SHIFT) \ + | (6 << TIMING_CFG1_REFREC_SHIFT) \ + | (2 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x27256222 */ +#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (4 << TIMING_CFG2_CPO_SHIFT) \ + | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x121048c5 */ +#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x03600100 */ +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_32_BE) + /* 0x43080000 */ + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ +#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0232 << SDRAM_MODE_SD_SHIFT)) + /* ODT 150ohm CL=3, AL=1 on SDRAM */ +#define CONFIG_SYS_DDR_MODE2 0x00000000 + +/* + * Memory test + */ +#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x07f00000 + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 +#define CONFIG_SYS_LBC_LBCR 0x00040000 + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ + +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */ + +#define CONFIG_SYS_BR0_PRELIM (\ + CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\ + (2 << BR_PS_SHIFT) /* 16 bit port size */ |\ + BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX \ + | OR_GPCM_EHTR \ + | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +/* 127 64KB sectors and 8 8KB top sectors per device */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 + +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* + * NAND Flash on the Local Bus + */ +#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ +#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V ) /* valid */ +#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR ) + /* 0xFFFF8396 */ + +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ + +#ifdef CONFIG_VSC7385_ENET +#define CONFIG_TSEC2 +#define CONFIG_SYS_VSC7385_BASE 0xF0000000 +#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ +#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ +/* Access window base at VSC7385 base */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE +/* Access window size 128K */ +#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 +/* The flash address and size of the VSC7385 firmware image */ +#define CONFIG_VSC7385_IMAGE 0xFE7FE000 +#define CONFIG_VSC7385_IMAGE_SIZE 8192 +#endif +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES {{0x51}} /* Don't probe these addrs */ +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + + +/* + * Board info - revision and where boot from + */ +#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 + +/* + * Config on-board RTC + */ +#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCIE1_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 +#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 + +/* + * Fake PCIE2 definitions: there is no PCIE2 on this board but the code + * in arch/powerpc/cpu/mpc83xx/pcie.c doesn't compile without this + */ +#define CONFIG_SYS_PCIE2_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 +#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 +#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 + +#define CONFIG_PCI +#define CONFIG_PCIE + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ +#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 + +/* + * TSEC + */ +#define CONFIG_NET_MULTI +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) + +/* + * TSEC ethernet configuration + */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2_NAME "eTSEC1" +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: eTSEC[0-1] */ +#define CONFIG_ETHPRIME "eTSEC0" + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ + +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=${consoledev},${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addmisc=setenv bootargs ${bootargs}\0" \ + "kernel_addr=FE080000\0" \ + "fdt_addr=FE280000\0" \ + "ramdisk_addr=FE290000\0" \ + "u-boot=mpc8308rdb/u-boot.bin\0" \ + "kernel_addr_r=1000000\0" \ + "fdt_addr_r=C00000\0" \ + "hostname=mpc8308rdb\0" \ + "bootfile=mpc8308rdb/uImage\0" \ + "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ + "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ + "flash_self=run ramargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ + "run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "bootcmd=run flash_self\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};cp.b ${fileaddr} " \ + xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 9a40adc..524afa5 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -36,6 +36,7 @@ #define CONFIG_MPC8313ERDB 1 #define CONFIG_PCI +#define CONFIG_FSL_ELBC 1 #define CONFIG_MISC_INIT_R diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 6972fe8..f1b110b 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -197,6 +197,7 @@ #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00040000 +#define CONFIG_FSL_ELBC 1 /* * FLASH on the Local Bus diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index b30d0e3..9092755 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -223,6 +223,7 @@ #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 #define CONFIG_SYS_LBC_LBCR 0x00000000 +#define CONFIG_FSL_ELBC 1 /* * FLASH on the Local Bus diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 1654f46..79dadc4 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -246,6 +246,7 @@ #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 #define CONFIG_SYS_LBC_LBCR 0x00000000 +#define CONFIG_FSL_ELBC 1 /* * FLASH on the Local Bus diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index da4313a..a014ad0 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2009,2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include "../board/freescale/common/ics307_clk.h" + #ifdef CONFIG_MK_36BIT #define CONFIG_PHYS_64BIT 1 #endif @@ -70,15 +72,9 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#ifndef __ASSEMBLY__ -extern unsigned long get_board_sys_clk(unsigned long dummy); -extern unsigned long get_board_ddr_clk(unsigned long dummy); -#endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ -#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq - from ICS307 instead of switches */ /* * These can be toggled for performance analysis, otherwise use default. @@ -669,6 +665,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 95ea275..7daf934 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -294,6 +294,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index e945da2..ae4fba8 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -403,6 +403,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 799d946..faba353 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -420,6 +420,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 3eb0049..fdd3597 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -462,6 +462,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 07a8e61..5011e5a 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -401,6 +401,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 4a4a9ed..98677e5 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -416,6 +416,7 @@ #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 6973538..0cc2d47 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -421,6 +421,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 0c43b2b..bb7bb47 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -539,6 +539,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 78b7369..57c2f2f 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Freescale Semiconductor, Inc. + * Copyright 2007-2008,2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include "../board/freescale/common/ics307_clk.h" + #ifdef CONFIG_MK_36BIT #define CONFIG_PHYS_64BIT #endif @@ -53,15 +55,9 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#ifndef __ASSEMBLY__ -extern unsigned long get_board_sys_clk(unsigned long dummy); -extern unsigned long get_board_ddr_clk(unsigned long dummy); -#endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ -#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq - from ICS307 instead of switches */ /* * These can be toggled for performance analysis, otherwise use default. @@ -574,6 +570,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h new file mode 100644 index 0000000..b42b5d0 --- /dev/null +++ b/include/configs/P1022DS.h @@ -0,0 +1,470 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> + * Timur Tabi <timur@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "../board/freescale/common/ics307_clk.h" + +/* High Level Configuration Options */ +#define CONFIG_BOOKE /* BOOKE */ +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ +#define CONFIG_P1022 +#define CONFIG_P1022DS +#define CONFIG_MP /* support multiple processors */ + +#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_PHYS_64BIT +#define CONFIG_ENABLE_36BIT_PHYS +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE +#define CONFIG_BTB + +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END 0x7fffffff + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR + +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) /* pci0 */ +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) /* pci1 */ +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000) /* pci2 */ + +/* DDR Setup */ +#define CONFIG_DDR_SPD +#define CONFIG_VERY_BIG_RAM +#define CONFIG_FSL_DDR3 + +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +/* I2C addresses of SPD EEPROMs */ +#define CONFIG_SYS_SPD_BUS_NUM 1 +#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable + * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable + * + * Localbus cacheable (TBD) + * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable + * + * Localbus non-cacheable + * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable + * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable + * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + */ + +/* + * Local Bus Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull + +#define CONFIG_FLASH_BR_PRELIM \ + (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) +#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) + +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ + +#define CONFIG_SYS_BR1_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM + +#define CONFIG_SYS_FLASH_BANKS_LIST \ + {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R + +#define CONFIG_FSL_NGPIXIS +#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#define PIXIS_BASE_PHYS 0xfffdf0000ull + +#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) + +#define PIXIS_LBMAP_SWITCH 7 +#define PIXIS_LBMAP_MASK 0xE0 +#define PIXIS_LBMAP_ALTBANK 0x20 + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_FSL_DIU_FB +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) + +/* Video */ +/* #define CONFIG_VIDEO */ +#ifdef CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* + * I2C2 EEPROM + */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_BUS_NUM 1 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, Slot 2, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, direct to uli, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 3, Base address b000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#endif + +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#ifdef CONFIG_FSL_SATA +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_GENERIC_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#endif + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +#define CONFIG_TSEC_ENET +#ifdef CONFIG_TSEC_ENET + +#define CONFIG_TSECV2 +#define CONFIG_NET_MULTI + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" + +#define TSEC1_PHY_ADDR 1 +#define TSEC2_PHY_ADDR 2 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 + +#define CONFIG_LOADS_ECHO +#define CONFIG_SYS_LOADS_BAUD_CHANGE + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* + * USB + */ +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_FAT +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_HZ 1000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#define CONFIG_HOSTNAME p1022ds +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#define CONFIG_BOOTARGS + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "perf_mode=stable\0" \ + "memctl_intlv_ctl=2\0" \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=uramdisk\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=p1022ds.dtb\0" \ + "bdev=sda3\0" \ + "diuregs=md e002c000 1d\0" \ + "dium=mw e002c01c\0" \ + "diuerr=md e002c014 1\0" \ + "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \ + "monitor=0-DVI\0" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#endif diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index b891730..3cebbab 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -74,6 +74,7 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_E1000 1 /* E1000 pci Ethernet card*/ #ifndef __ASSEMBLY__ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif @@ -84,6 +85,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_MP #endif +#define CONFIG_HWCONFIG + /* * These can be toggled for performance analysis, otherwise use default. */ @@ -475,6 +478,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_NET diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 66be725..569da4f 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include "../board/freescale/common/ics307_clk.h" + #ifdef CONFIG_MK_36BIT #define CONFIG_PHYS_64BIT #endif @@ -54,17 +56,9 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#ifndef __ASSEMBLY__ -extern unsigned long calculate_board_sys_clk(unsigned long dummy); -extern unsigned long calculate_board_ddr_clk(unsigned long dummy); -/* extern unsigned long get_board_sys_clk(unsigned long dummy); */ -/* extern unsigned long get_board_ddr_clk(unsigned long dummy); */ -#endif -#define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0) /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */ +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ -#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq - from ICS307 instead of switches */ /* * These can be toggled for performance analysis, otherwise use default. @@ -553,6 +547,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 4b9bcca..7426bca 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -326,6 +326,7 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_DATE #define CONFIG_CMD_EEPROM +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 1db20bc..0bd28fc 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -325,6 +325,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_DATE #define CONFIG_CMD_EEPROM +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 1989e5a..5d424dd 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -380,6 +380,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index eb8657b..70b7489 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -37,6 +37,7 @@ #define CONFIG_MPC8313 1 #define CONFIG_PCI +#define CONFIG_FSL_ELBC 1 #define CONFIG_MISC_INIT_R diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index d44fb07..90abe14 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -593,6 +593,7 @@ #define CONFIG_CMD_EEPROM #define CONFIG_CMD_DTT #define CONFIG_CMD_MII +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h index 1a56c60..df5ef78 100644 --- a/include/configs/XPEDITE5200.h +++ b/include/configs/XPEDITE5200.h @@ -338,6 +338,7 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_PING #define CONFIG_CMD_SNTP +#define CONFIG_CMD_REGINFO /* * Miscellaneous configurable options diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index 7fd3668..1d6091c 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -47,6 +47,7 @@ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_ELBC 1 /* * Multicore config @@ -396,6 +397,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_PING #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_SNTP +#define CONFIG_CMD_REGINFO /* * Miscellaneous configurable options diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h index 1e821d9..6eec1c9 100644 --- a/include/configs/bf518f-ezbrd.h +++ b/include/configs/bf518f-ezbrd.h @@ -63,6 +63,26 @@ #if !defined(__ADSPBF512__) && !defined(__ADSPBF514__) #define ADI_CMDS_NETWORK 1 #define CONFIG_BFIN_MAC +#define CONFIG_BFIN_MAC_PINS \ + { \ + P_MII0_ETxD0, \ + P_MII0_ETxD1, \ + P_MII0_ETxD2, \ + P_MII0_ETxD3, \ + P_MII0_ETxEN, \ + P_MII0_TxCLK, \ + P_MII0_PHYINT, \ + P_MII0_COL, \ + P_MII0_ERxD0, \ + P_MII0_ERxD1, \ + P_MII0_ERxD2, \ + P_MII0_ERxD3, \ + P_MII0_ERxDV, \ + P_MII0_ERxCLK, \ + P_MII0_CRS, \ + P_MII0_MDC, \ + P_MII0_MDIO, \ + 0 } #define CONFIG_NETCONSOLE 1 #define CONFIG_NET_MULTI 1 #endif @@ -117,8 +137,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h index 711fa27..82396d0 100644 --- a/include/configs/bf526-ezbrd.h +++ b/include/configs/bf526-ezbrd.h @@ -134,8 +134,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* @@ -160,23 +158,19 @@ /* define to enable run status via led */ /* #define CONFIG_STATUS_LED */ #ifdef CONFIG_STATUS_LED +#define CONFIG_GPIO_LED #define CONFIG_BOARD_SPECIFIC_LED -#ifndef __ASSEMBLY__ -typedef unsigned int led_id_t; -void __led_init(led_id_t mask, int state); -void __led_set(led_id_t mask, int state); -void __led_toggle(led_id_t mask); -#endif /* use LED0 to indicate booting/alive */ #define STATUS_LED_BOOT 0 -#define STATUS_LED_BIT 1 +#define STATUS_LED_BIT GPIO_PF8 #define STATUS_LED_STATE STATUS_LED_ON #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4) /* use LED1 to indicate crash */ #define STATUS_LED_CRASH 1 -#define STATUS_LED_BIT1 2 +#define STATUS_LED_BIT1 GPIO_PG11 #define STATUS_LED_STATE1 STATUS_LED_ON #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +/* #define STATUS_LED_BIT2 GPIO_PG12 */ #endif diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h new file mode 100644 index 0000000..eb3a2b7 --- /dev/null +++ b/include/configs/bf527-ad7160-eval.h @@ -0,0 +1,148 @@ +/* + * U-boot - Configuration file for BF527 AD7160-EVAL board + */ + +#ifndef __CONFIG_BF527_AD7160_EVAL_H__ +#define __CONFIG_BF527_AD7160_EVAL_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf527-0.2 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 24000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 25 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 10 +#define CONFIG_MEM_SIZE 64 + +#define CONFIG_EBIU_SDRRC_VAL 0x03F6 +#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS) + +#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (640 * 1024) + + +/* + * NAND Settings + * (can't be used same time as ethernet) + */ +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) +# define CONFIG_BFIN_NFC +# define CONFIG_BFIN_NFC_BOOTROM_ECC +#endif +#ifdef CONFIG_BFIN_NFC +#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 +#define CONFIG_DRIVER_NAND_BFIN +#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#endif + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 259 + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + + +/* + * Env Storage Settings + */ +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR +#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SIZE 0x20000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x2000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR +#endif + + +/* + * I2C Settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 + + +/* + * SPI_MMC Settings + */ +#define CONFIG_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_SPI_MMC +#define CONFIG_SPI_MMC_DEFAULT_CS (7 + GPIO_PH3) + + +/* + * Misc Settings + */ +#define CONFIG_MISC_INIT_R +#define CONFIG_UART_CONSOLE 0 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h index 7800c32..07e4ce8 100644 --- a/include/configs/bf527-ezkit.h +++ b/include/configs/bf527-ezkit.h @@ -138,8 +138,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index c80ddca..37a7059 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -136,8 +136,6 @@ } while (0) #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 #endif diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 80c4884..02c8bc3 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -180,8 +180,6 @@ } while (0) #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 #endif @@ -230,23 +228,19 @@ /* define to enable run status via led */ /* #define CONFIG_STATUS_LED */ #ifdef CONFIG_STATUS_LED +#define CONFIG_GPIO_LED #define CONFIG_BOARD_SPECIFIC_LED -#ifndef __ASSEMBLY__ -typedef unsigned int led_id_t; -void __led_init(led_id_t mask, int state); -void __led_set(led_id_t mask, int state); -void __led_toggle(led_id_t mask); -#endif -/* use LED1 to indicate booting/alive */ +/* use LED0 to indicate booting/alive */ #define STATUS_LED_BOOT 0 -#define STATUS_LED_BIT 1 +#define STATUS_LED_BIT GPIO_PF2 #define STATUS_LED_STATE STATUS_LED_ON #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4) -/* use LED2 to indicate crash */ +/* use LED1 to indicate crash */ #define STATUS_LED_CRASH 1 -#define STATUS_LED_BIT1 2 +#define STATUS_LED_BIT1 GPIO_PF3 #define STATUS_LED_STATE1 STATUS_LED_ON #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +/* #define STATUS_LED_BIT2 GPIO_PF4 */ #endif /* define to enable splash screen support */ diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index cf40d06..39bbb41 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -132,7 +132,6 @@ #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_READY PF12 #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ @@ -141,13 +140,7 @@ #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTHIO() & BFIN_NAND_READY) -#define NAND_PLAT_INIT() \ - do { \ - bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~BFIN_NAND_READY); \ - bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~BFIN_NAND_READY); \ - bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | BFIN_NAND_READY); \ - } while (0) +#define NAND_PLAT_GPIO_DEV_READY GPIO_PF12 /* @@ -155,8 +148,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 92ceb38..96704d7 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -137,8 +137,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* @@ -157,7 +155,6 @@ #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_READY PF3 #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ @@ -166,13 +163,7 @@ #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTFIO() & BFIN_NAND_READY) -#define NAND_PLAT_INIT() \ - do { \ - bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~BFIN_NAND_READY); \ - bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~BFIN_NAND_READY); \ - bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | BFIN_NAND_READY); \ - } while (0) +#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3 /* @@ -268,8 +259,6 @@ #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 0 -/* #define CONFIG_BF537_STAMP_LEDCMD 1 */ - /* Define if want to do post memory test */ #undef CONFIG_POST #ifdef CONFIG_POST diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h index 59e0565..1c14b6b 100644 --- a/include/configs/bf538f-ezkit.h +++ b/include/configs/bf538f-ezkit.h @@ -134,8 +134,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h index f9c9711..60cca0c 100644 --- a/include/configs/bf548-ezkit.h +++ b/include/configs/bf548-ezkit.h @@ -140,8 +140,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h index 0be170c..0c0204f 100644 --- a/include/configs/bf561-acvilon.h +++ b/include/configs/bf561-acvilon.h @@ -131,7 +131,6 @@ #define CONFIG_ENV_SECT_SIZE (1056 * 8) #define CONFIG_ENV_OFFSET ((16 + 256) * 1056) #define CONFIG_ENV_SIZE (8 * 1056) -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) /* @@ -145,7 +144,6 @@ #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3)) -#define BFIN_NAND_READY PF10 #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ @@ -154,12 +152,7 @@ #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO0_FLAG_D() & BFIN_NAND_READY) -#define NAND_PLAT_INIT() \ - do { \ - bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() & ~BFIN_NAND_READY); \ - bfin_write_FIO0_INEN(bfin_read_FIO0_INEN() | BFIN_NAND_READY); \ - } while (0) +#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10 /* diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index 1e3fdef..036bfe4 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -151,8 +151,6 @@ } while (0) #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 #endif diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 1896cf5..901a32f 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -83,6 +83,7 @@ # define CONFIG_CMD_CPLBINFO # define CONFIG_CMD_ELF # define CONFIG_ELF_SIMPLE_LOAD +# define CONFIG_CMD_GPIO # define CONFIG_CMD_KGDB # define CONFIG_CMD_REGINFO # define CONFIG_CMD_STRINGS @@ -247,12 +248,26 @@ # define CONFIG_SYS_AUTOLOAD "no" # endif # endif +# define CONFIG_IP_DEFRAG # define CONFIG_NET_RETRY_COUNT 20 #endif /* + * I2C Settings + */ +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) +# ifndef CONFIG_SYS_I2C_SPEED +# define CONFIG_SYS_I2C_SPEED 50000 +# endif +# ifndef CONFIG_SYS_I2C_SLAVE +# define CONFIG_SYS_I2C_SLAVE 0 +# endif +#endif + +/* * Misc Settings */ +#define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */ #define CONFIG_LZMA #endif diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h index ad1dd12..e0c6d53 100644 --- a/include/configs/cm-bf527.h +++ b/include/configs/cm-bf527.h @@ -117,8 +117,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h index 8d0bc12..742df9c 100644 --- a/include/configs/cm-bf537e.h +++ b/include/configs/cm-bf537e.h @@ -119,8 +119,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h index bbea3ab..9def99f 100644 --- a/include/configs/cm-bf537u.h +++ b/include/configs/cm-bf537u.h @@ -120,8 +120,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h index 93c4c8d..63b9399 100644 --- a/include/configs/cm-bf548.h +++ b/include/configs/cm-bf548.h @@ -107,8 +107,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h new file mode 100644 index 0000000..277ff67 --- /dev/null +++ b/include/configs/colibri_pxa270.h @@ -0,0 +1,278 @@ +/* + * Toradex Colibri PXA270 configuration file + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Board Configuration Options + */ +#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ +#define CONFIG_VPAC270 1 /* Toradex Colibri PXA270 board */ + +#undef BOARD_LATE_INIT +#undef CONFIG_SKIP_RELOCATE_UBOOT +#undef CONFIG_USE_IRQ +#undef CONFIG_SKIP_LOWLEVEL_INIT + +/* + * Environment settings + */ +#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +#define CONFIG_ENV_OVERWRITE /* override default environment */ + +#define CONFIG_BOOTCOMMAND \ + "if mmc init && fatload mmc 0 0xa0000000 uImage; then " \ + "bootm 0xa0000000; " \ + "fi; " \ + "if usb reset && fatload usb 0 0xa0000000 uImage; then " \ + "bootm 0xa0000000; " \ + "fi; " \ + "bootm 0x80000;" +#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" +#define CONFIG_TIMESTAMP +#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +#define CONFIG_LZMA /* LZMA compression support */ + +/* + * Serial Console Configuration + */ +#define CONFIG_PXA_SERIAL +#define CONFIG_FFUART 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Bootloader Components Configuration + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_NET +#define CONFIG_CMD_ENV +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_MMC +#define CONFIG_CMD_USB +#define CONFIG_CMD_FLASH + +/* + * Networking Configuration + * chip on the Voipac PXA270 board + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP + +#define CONFIG_NET_MULTI 1 +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x08000000 +#define DM9000_IO (CONFIG_DM9000_BASE) +#define DM9000_DATA (CONFIG_DM9000_BASE + 4) +#define CONFIG_NET_RETRY_COUNT 10 + +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#endif + +/* + * MMC Card Configuration + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_PXA_MMC +#define CONFIG_SYS_MMC_BASE 0xF0000000 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * KGDB + */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * HUSH Shell Configuration + */ +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_DEVICE_NULLDEV 1 + +/* + * Clock Configuration + */ +#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ +#define CONFIG_SYS_CPUSPEED 0x290 /* 520 MHz */ + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * DRAM Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ +#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ + +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR (0xa1000000) + +/* + * NOR FLASH + */ +#ifdef CONFIG_CMD_FLASH +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER 1 + +#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_FLASH_PROTECTION 1 + +#define CONFIG_ENV_IS_IN_FLASH 1 + +#else /* No flash */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_ENV_IS_NOWHERE +#endif + +#define CONFIG_SYS_MONITOR_BASE 0x000000 +#define CONFIG_SYS_MONITOR_LEN 0x40000 + +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x40000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + + +/* + * GPIO settings + */ +#define CONFIG_SYS_GPSR0_VAL 0x00000000 +#define CONFIG_SYS_GPSR1_VAL 0x00020000 +#define CONFIG_SYS_GPSR2_VAL 0x0002C000 +#define CONFIG_SYS_GPSR3_VAL 0x00000000 + +#define CONFIG_SYS_GPCR0_VAL 0x00000000 +#define CONFIG_SYS_GPCR1_VAL 0x00000000 +#define CONFIG_SYS_GPCR2_VAL 0x00000000 +#define CONFIG_SYS_GPCR3_VAL 0x00000000 + +#define CONFIG_SYS_GPDR0_VAL 0x08000000 +#define CONFIG_SYS_GPDR1_VAL 0x0002A981 +#define CONFIG_SYS_GPDR2_VAL 0x0202FC00 +#define CONFIG_SYS_GPDR3_VAL 0x00000000 + +#define CONFIG_SYS_GAFR0_L_VAL 0x00100000 +#define CONFIG_SYS_GAFR0_U_VAL 0x00C00010 +#define CONFIG_SYS_GAFR1_L_VAL 0x999A901A +#define CONFIG_SYS_GAFR1_U_VAL 0xAAA00008 +#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA +#define CONFIG_SYS_GAFR2_U_VAL 0x0109A000 +#define CONFIG_SYS_GAFR3_L_VAL 0x54000300 +#define CONFIG_SYS_GAFR3_U_VAL 0x00024001 + +#define CONFIG_SYS_PSSR_VAL 0x30 + +/* + * Clock settings + */ +#define CONFIG_SYS_CKEN 0x00500240 +#define CONFIG_SYS_CCCR 0x02000290 + +/* + * Memory settings + */ +#define CONFIG_SYS_MSC0_VAL 0x000095f2 +#define CONFIG_SYS_MSC1_VAL 0x00007ff4 +#define CONFIG_SYS_MSC2_VAL 0x00000000 +#define CONFIG_SYS_MDCNFG_VAL 0x08000ac9 +#define CONFIG_SYS_MDREFR_VAL 0x2013e01e +#define CONFIG_SYS_MDMRS_VAL 0x00320032 +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x40044004 + +/* + * PCMCIA and CF Interfaces + */ +#define CONFIG_SYS_MECR_VAL 0x00000001 +#define CONFIG_SYS_MCMEM0_VAL 0x00014307 +#define CONFIG_SYS_MCMEM1_VAL 0x00014307 +#define CONFIG_SYS_MCATT0_VAL 0x0001c787 +#define CONFIG_SYS_MCATT1_VAL 0x0001c787 +#define CONFIG_SYS_MCIO0_VAL 0x0001430f +#define CONFIG_SYS_MCIO1_VAL 0x0001430f + +/* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_BOARD_INIT +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "tdex270" +#define CONFIG_USB_STORAGE +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h index b4fda76..049298c 100644 --- a/include/configs/cpuat91.h +++ b/include/configs/cpuat91.h @@ -131,15 +131,12 @@ (CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512 * 1024) #define CONFIG_NET_MULTI 1 -#ifdef CONFIG_NET_MULTI #define CONFIG_DRIVER_AT91EMAC 1 #define CONFIG_SYS_RX_ETH_BUFFER 8 -#else -#define CONFIG_DRIVER_ETHER 1 -#endif +#define CONFIG_RMII 1 +#define CONFIG_MII 1 +#define CONFIG_DRIVER_AT91EMAC_PHYADDR 1 #define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_AT91C_USE_RMII 1 -#define CONFIG_PHY_ADDRESS (1 << 5) #define CONFIG_KS8721_PHY 1 #define CONFIG_SYS_FLASH_CFI 1 diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index c3d95a0..055931c 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -131,12 +131,23 @@ * Commands configuration - using default command set for now */ #include <config_cmd_default.h> + /* - * Disabling some default commands for staggered bring-up + * Network */ -#undef CONFIG_CMD_BOOTD /* no bootd since no net */ -#undef CONFIG_CMD_NET /* no net since no eth */ -#undef CONFIG_CMD_NFS /* no NFS since no net */ + +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE /* Enable Marvell GbE Driver */ +#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ +#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ +#define CONFIG_PHY_BASE_ADR 0x8 +#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* specify more that one ports available */ +#define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#endif /* * Environment variables configurations diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h index 2fbc6ad..eb3fa57 100644 --- a/include/configs/guruplug.h +++ b/include/configs/guruplug.h @@ -172,9 +172,9 @@ #define CONFIG_NET_MULTI /* specify more that one ports available */ #define CONFIG_MII /* expose smi ove miiphy interface */ #define CONFIG_CMD_MII -#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */ +#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ -#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */ +#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ #define CONFIG_PHY_BASE_ADR 0 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv88e1121 PHY */ diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h index 2eef5ef..2c0a263 100644 --- a/include/configs/ibf-dsp561.h +++ b/include/configs/ibf-dsp561.h @@ -58,6 +58,18 @@ /* + * Network Settings + */ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_NET_MULTI +#define CONFIG_DRIVER_AX88180 1 +#define AX88180_BASE 0x2c000000 +#define CONFIG_HOSTNAME ibf-dsp561 +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ + + +/* * Flash Settings */ #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ @@ -126,8 +138,6 @@ } while (0) #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 #endif diff --git a/include/configs/ip04.h b/include/configs/ip04.h index 425a745..c024d78 100644 --- a/include/configs/ip04.h +++ b/include/configs/ip04.h @@ -116,7 +116,6 @@ #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_READY PF10 #define BFIN_NAND_WRITE(addr, cmd) \ do { \ bfin_write8(addr, cmd); \ @@ -125,14 +124,7 @@ #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO_FLAG_D() & BFIN_NAND_READY) -#define NAND_PLAT_INIT() \ - do { \ - bfin_write_FIO_DIR(bfin_read_FIO_DIR() & ~BFIN_NAND_READY); \ - bfin_write_FIO_INEN(bfin_read_FIO_INEN() | BFIN_NAND_READY); \ - bfin_write_FIO_EDGE(bfin_read_FIO_EDGE() & ~BFIN_NAND_READY); \ - bfin_write_FIO_POLAR(bfin_read_FIO_POLAR() & ~BFIN_NAND_READY); \ - } while (0) +#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10 /* diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index a928c2c..6519c90 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -127,9 +127,9 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_NET_MULTI /* specify more that one ports available */ #define CONFIG_MII /* expose smi ove miiphy interface */ -#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */ +#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ -#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */ +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ #define CONFIG_RESET_PHY_R /* use reset_phy() to init 88E1118 PHY */ diff --git a/include/configs/mv88f6281gtw_ge.h b/include/configs/mv88f6281gtw_ge.h index 96b4d1c..9ef03a6 100644 --- a/include/configs/mv88f6281gtw_ge.h +++ b/include/configs/mv88f6281gtw_ge.h @@ -172,9 +172,9 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_NET_MULTI /* specify more that one ports available */ #define CONFIG_MII /* expose smi ove miiphy interface */ -#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */ +#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ -#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */ +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ #endif /* CONFIG_CMD_NET */ diff --git a/include/configs/openrd_base.h b/include/configs/openrd_base.h index d2f4502..52fa73d 100644 --- a/include/configs/openrd_base.h +++ b/include/configs/openrd_base.h @@ -183,9 +183,9 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_NET_MULTI /* specify more that one ports available */ #define CONFIG_MII /* expose smi ove miiphy interface */ -#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */ +#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ -#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */ +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0x8 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h index 3d8e25c..5857301 100644 --- a/include/configs/rd6281a.h +++ b/include/configs/rd6281a.h @@ -171,8 +171,8 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_NET_MULTI /* specify more that one ports available */ #define CONFIG_MII /* expose smi ove miiphy interface */ -#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */ -#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */ +#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ +#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ #define CONFIG_MV88E61XX_MULTICHIP_ADRMODE #define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */ #define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index aeac2de..3f4056e 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -487,6 +487,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_ELF +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index dab4f80..53d06ed 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -382,6 +382,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index e9edc44..c5de86e 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -174,9 +174,9 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_NET_MULTI /* specify more that one ports available */ #define CONFIG_MII /* expose smi ove miiphy interface */ -#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */ +#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ -#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */ +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 89f7cc4..ad70109 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -355,6 +355,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_SNTP #define CONFIG_CMD_USB +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 86b231c..891d2bf 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -321,6 +321,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_I2C +#define CONFIG_CMD_REGINFO #if defined(CONFIG_SYS_RAMBOOT) #undef CONFIG_CMD_SAVEENV diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 2783f9e..363f7b4 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -353,6 +353,7 @@ #define CONFIG_CMD_NFS #define CONFIG_CMD_PING #define CONFIG_CMD_SNTP +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h index 9c04d8a..52055e8 100644 --- a/include/configs/tcm-bf518.h +++ b/include/configs/tcm-bf518.h @@ -106,8 +106,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h index 409a042..24ce8f8 100644 --- a/include/configs/tcm-bf537.h +++ b/include/configs/tcm-bf537.h @@ -120,8 +120,6 @@ */ #define CONFIG_BFIN_TWI_I2C 1 #define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h new file mode 100644 index 0000000..1589913 --- /dev/null +++ b/include/configs/ve8313.h @@ -0,0 +1,511 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. + * + * (C) Copyright 2010 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * ve8313 board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 +#define CONFIG_MPC83xx 1 +#define CONFIG_MPC831x 1 +#define CONFIG_MPC8313 1 +#define CONFIG_VE8313 1 + +#define CONFIG_PCI 1 + +#define CONFIG_BOARD_EARLY_INIT_F 1 + +/* + * On-board devices + * + */ +#define CONFIG_83XX_CLKIN 32000000 /* in Hz */ + +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +#define CONFIG_SYS_IMMR 0xE0000000 + +#define CONFIG_SYS_MEMTEST_START 0x00001000 +#define CONFIG_SYS_MEMTEST_END 0x07000000 + +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */ + +/* + * Device configurations + */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE + +/* + * Manually set up DDR parameters, as this board does not + * have the SPD connected to I2C. + */ +#define CONFIG_SYS_DDR_SIZE 128 /* MB */ +#define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \ + | CSCONFIG_AP \ + | 0x00040000 /* TODO */ \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) + /* 0x80840102 */ + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ + | ( 3 << TIMING_CFG0_RRT_SHIFT ) \ + | ( 2 << TIMING_CFG0_WWT_SHIFT ) \ + | ( 7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ + | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) + /* 0x0e720802 */ +#define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \ + | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ + | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \ + | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ + | ( 6 << TIMING_CFG1_REFREC_SHIFT ) \ + | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \ + | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ + | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) + /* 0x26256222 */ +#define CONFIG_SYS_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \ + | ( 5 << TIMING_CFG2_CPO_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ + | ( 1 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ + | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ + | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) ) + /* 0x029028c7 */ +#define CONFIG_SYS_DDR_INTERVAL ( ( 0x320 << SDRAM_INTERVAL_REFINT_SHIFT ) \ + | ( 0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) + /* 0x03202000 */ +#define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_32_BE ) + /* 0x43080000 */ +#define CONFIG_SYS_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \ + | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) + /* 0x44400232 */ +#define CONFIG_SYS_DDR_MODE_2 0x8000C000 + +#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + /*0x02000000*/ +#define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \ + | DDRCDR_PZ_NOMZ \ + | DDRCDR_NZ_NOMZ \ + | DDRCDR_M_ODR ) + /* 0x73000002 */ + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 +#define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ + +#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | \ + (2 << BR_PS_SHIFT) | /* 16 bit */ \ + BR_V) /* valid */ +#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV4 \ + | OR_GPCM_SCY_5 \ + | OR_GPCM_TRLX \ + | OR_GPCM_EAD) + /* 0xfe000c55 */ + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) + +/* + * Local Bus LCRR and LBCR regs + */ +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_3 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 + +#define CONFIG_SYS_LBC_LBCR 0x00040000 + +#define CONFIG_SYS_LBC_MRTPR 0x20000000 + +/* + * NAND settings + */ +#define CONFIG_SYS_NAND_BASE 0x61000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 + +#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ + | BR_PS_8 \ + | BR_DECC_CHK_GEN \ + | BR_MS_FCM \ + | BR_V ) /* valid */ + /* 0x61000c21 */ +#define CONFIG_SYS_NAND_OR_PRELIM (0xffff8000 \ + | OR_FCM_BCTLD \ + | OR_FCM_CHT \ + | OR_FCM_SCY_2 \ + | OR_FCM_RST \ + | OR_FCM_TRLX) + /* 0xffff90ac */ + +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM + +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ + +#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM +#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM + +/* CS2 NvRAM */ +#define CONFIG_SYS_BR2_PRELIM (0x60000000 \ + | BR_PS_8 \ + | BR_V) + /* 0x60000801 */ +#define CONFIG_SYS_OR2_PRELIM (0xfffe0000 \ + | OR_GPCM_CSNT \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_3 \ + | OR_GPCM_TRLX \ + | OR_GPCM_EHTR \ + | OR_GPCM_EAD) + /* 0xfffe0937 */ +/* local bus read write buffer mapping SRAM@0x64000000 */ +#define CONFIG_SYS_BR3_PRELIM (0x62000000 \ + | BR_PS_16 \ + | BR_V) + /* 0x62001001 */ + +#define CONFIG_SYS_OR3_PRELIM (0xfe000000 \ + | OR_GPCM_CSNT \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX \ + | OR_GPCM_EHTR \ + | OR_GPCM_EAD) + /* 0xfe0009f7 */ + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#if defined(CONFIG_PCI) +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ +#endif + +/* + * TSEC + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ + +#define CONFIG_NET_MULTI + +#define CONFIG_TSEC1 +#ifdef CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 +#define CONFIG_TSEC1_NAME "TSEC1" +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define TSEC1_PHY_ADDR 0x01 +#define TSEC1_FLAGS 0 +#define TSEC1_PHYIDX 0 +#endif + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC1" + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x4000 +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_PCI + +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */ +#define CONFIG_SYS_HZ 1000 /* 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* 0x64050000 */ +#define CONFIG_SYS_HRCW_LOW (\ + 0x20000000 /* reserved, must be set */ |\ + HRCWL_DDRCM |\ + HRCWL_CSB_TO_CLKIN_4X1 | \ + HRCWL_CORE_TO_CSB_2_5X1) + +/* 0xa0600004 */ +#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \ + HRCWH_PCI_ARBITER_ENABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_TSEC1M_IN_MII | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_EARLY) + +/* System IO Config */ +#define CONFIG_SYS_SICRH (0x01000000 | \ + SICRH_ETSEC2_B | \ + SICRH_ETSEC2_C | \ + SICRH_ETSEC2_D | \ + SICRH_ETSEC2_E | \ + SICRH_ETSEC2_F | \ + SICRH_ETSEC2_G | \ + SICRH_TSOBI1 | \ + SICRH_TSOBI2) + /* 0x010fff03 */ +#define CONFIG_SYS_SICRL (SICRL_LBC | \ + SICRL_SPI_A | \ + SICRL_SPI_B | \ + SICRL_SPI_C | \ + SICRL_SPI_D | \ + SICRL_ETSEC2_A) + /* 0x33fc0003) */ + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) + +#define CONFIG_SYS_HID2 HID2_HBE + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR @ 0x00000000 */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) + +#if defined(CONFIG_PCI) +/* PCI @ 0x80000000 */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) +#else +#define CONFIG_SYS_IBAT1L (0) +#define CONFIG_SYS_IBAT1U (0) +#define CONFIG_SYS_IBAT2L (0) +#define CONFIG_SYS_IBAT2U (0) +#endif + +/* PCI2 not supported on 8313 */ +#define CONFIG_SYS_IBAT3L (0) +#define CONFIG_SYS_IBAT3U (0) +#define CONFIG_SYS_IBAT4L (0) +#define CONFIG_SYS_IBAT4U (0) + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | \ + BATU_VP) + +/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +/* FPGA, SRAM, NAND @ 0x60000000 */ +#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U +#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_NETDEV eth0 + +#define CONFIG_HOSTNAME ve8313 +#define CONFIG_UBOOTPATH ve8313/u-boot.bin + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#define CONFIG_BAUDRATE 115200 + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "ethprime=" MK_STR(CONFIG_TSEC1_NAME) "\0" \ + "u-boot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "u-boot_addr_r=100000\0" \ + "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ + "update=protect off " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ + "erase " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ + "cp.b ${u-boot_addr_r} " MK_STR(CONFIG_SYS_FLASH_BASE) \ + " ${filesize};" \ + "protect on " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \ + +#undef MK_STR +#undef XMK_STR + +#endif /* __CONFIG_H */ diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h new file mode 100644 index 0000000..6d02995 --- /dev/null +++ b/include/configs/vpac270.h @@ -0,0 +1,323 @@ +/* + * Voipac PXA270 configuration file + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Board Configuration Options + */ +#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ +#define CONFIG_VPAC270 1 /* Voipac PXA270 board */ + +#undef BOARD_LATE_INIT +#undef CONFIG_SKIP_RELOCATE_UBOOT +#undef CONFIG_USE_IRQ +#undef CONFIG_SKIP_LOWLEVEL_INIT + +/* + * Environment settings + */ +#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +#define CONFIG_ENV_OVERWRITE /* override default environment */ + +#define CONFIG_BOOTCOMMAND \ + "if mmc init && fatload mmc 0 0xa4000000 uImage; then " \ + "bootm 0xa4000000; " \ + "fi; " \ + "if usb reset && fatload usb 0 0xa4000000 uImage; then " \ + "bootm 0xa4000000; " \ + "fi; " \ + "bootm 0x40000;" +#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" +#define CONFIG_TIMESTAMP +#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +#define CONFIG_LZMA /* LZMA compression support */ + +/* + * Serial Console Configuration + */ +#define CONFIG_PXA_SERIAL +#define CONFIG_FFUART 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Bootloader Components Configuration + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_NET +#define CONFIG_CMD_ENV +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_MMC +#define CONFIG_CMD_USB +#undef CONFIG_LCD +#define CONFIG_CMD_IDE + +#ifdef CONFIG_ONENAND_U_BOOT +#undef CONFIG_CMD_FLASH +#define CONFIG_CMD_ONENAND +#else +#define CONFIG_CMD_FLASH +#undef CONFIG_CMD_ONENAND +#endif + +/* + * Networking Configuration + * chip on the Voipac PXA270 board + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP + +#define CONFIG_NET_MULTI 1 +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */ +#define DM9000_IO (CONFIG_DM9000_BASE) +#define DM9000_DATA (CONFIG_DM9000_BASE + 4) +#define CONFIG_NET_RETRY_COUNT 10 + +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#endif + +/* + * MMC Card Configuration + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_PXA_MMC +#define CONFIG_SYS_MMC_BASE 0xF0000000 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * KGDB + */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * HUSH Shell Configuration + */ +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_DEVICE_NULLDEV 1 + +/* + * Clock Configuration + */ +#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ +#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * DRAM Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* We have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ + +#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ +#define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */ + +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR (0x5c000000) + +/* + * NOR FLASH + */ +#if defined(CONFIG_CMD_FLASH) /* NOR */ +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER 1 + +#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } + +#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_FLASH_PROTECTION 1 + +#define CONFIG_ENV_IS_IN_FLASH 1 + +#elif defined(CONFIG_CMD_ONENAND) /* OneNAND */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_ONENAND_BASE 0x00000000 +#define CONFIG_ENV_IS_IN_ONENAND 1 + +#else /* No flash */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_ENV_IS_NOWHERE +#endif + +#define CONFIG_SYS_MONITOR_BASE 0x000000 +#define CONFIG_SYS_MONITOR_LEN 0x40000 + +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x40000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +/* + * IDE + */ +#ifdef CONFIG_CMD_IDE +#define CONFIG_LBA48 +#undef CONFIG_IDE_LED +#undef CONFIG_IDE_RESET + +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 + +#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 + +#define CONFIG_SYS_ATA_DATA_OFFSET 0x120 +#define CONFIG_SYS_ATA_REG_OFFSET 0x120 +#define CONFIG_SYS_ATA_ALT_OFFSET 0x120 + +#define CONFIG_SYS_ATA_STRIDE 2 +#endif + +/* + * GPIO settings + */ +#define CONFIG_SYS_GPSR0_VAL 0x01308800 +#define CONFIG_SYS_GPSR1_VAL 0x00cf0000 +#define CONFIG_SYS_GPSR2_VAL 0x922ac000 +#define CONFIG_SYS_GPSR3_VAL 0x0161e800 + +#define CONFIG_SYS_GPCR0_VAL 0x00010000 +#define CONFIG_SYS_GPCR1_VAL 0x0 +#define CONFIG_SYS_GPCR2_VAL 0x0 +#define CONFIG_SYS_GPCR3_VAL 0x0 + +#define CONFIG_SYS_GPDR0_VAL 0xcbb18800 +#define CONFIG_SYS_GPDR1_VAL 0xfccfa981 +#define CONFIG_SYS_GPDR2_VAL 0x922affff +#define CONFIG_SYS_GPDR3_VAL 0x0161e904 + +#define CONFIG_SYS_GAFR0_L_VAL 0x00100000 +#define CONFIG_SYS_GAFR0_U_VAL 0xa5da8510 +#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a0aa +#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa +#define CONFIG_SYS_GAFR2_U_VAL 0x4109a401 +#define CONFIG_SYS_GAFR3_L_VAL 0x54010310 +#define CONFIG_SYS_GAFR3_U_VAL 0x00025401 + +#define CONFIG_SYS_PSSR_VAL 0x30 + +/* + * Clock settings + */ +#define CONFIG_SYS_CKEN 0x00500240 +#define CONFIG_SYS_CCCR 0x02000290 + +/* + * Memory settings + */ +#define CONFIG_SYS_MSC0_VAL 0x3ffc95fa +#define CONFIG_SYS_MSC1_VAL 0x02ccf974 +#define CONFIG_SYS_MSC2_VAL 0x00000000 +#define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3 +#define CONFIG_SYS_MDREFR_VAL 0x201fe01e +#define CONFIG_SYS_MDMRS_VAL 0x00000000 +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x40044004 +#define CONFIG_SYS_MEM_BUF_IMP 0x0f + +/* + * PCMCIA and CF Interfaces + */ +#define CONFIG_SYS_MECR_VAL 0x00000001 +#define CONFIG_SYS_MCMEM0_VAL 0x00014307 +#define CONFIG_SYS_MCMEM1_VAL 0x00014307 +#define CONFIG_SYS_MCATT0_VAL 0x0001c787 +#define CONFIG_SYS_MCATT1_VAL 0x0001c787 +#define CONFIG_SYS_MCIO0_VAL 0x0001430f +#define CONFIG_SYS_MCIO1_VAL 0x0001430f + +/* + * LCD + */ +#ifdef CONFIG_LCD +#define CONFIG_VOIPAC_LCD +#endif + +/* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_BOARD_INIT +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "vpac270" +#define CONFIG_USB_STORAGE +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h new file mode 100644 index 0000000..a5a873b --- /dev/null +++ b/include/configs/zipitz2.h @@ -0,0 +1,259 @@ +/* + * Aeronix Zipit Z2 configuration file + * + * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Board Configuration Options + */ +#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ +#define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */ + +#undef BOARD_LATE_INIT +#undef CONFIG_SKIP_RELOCATE_UBOOT +#undef CONFIG_USE_IRQ +#undef CONFIG_SKIP_LOWLEVEL_INIT + +/* + * Environment settings + */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR 0x40000 +#define CONFIG_ENV_SIZE 0x20000 + +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_STACKSIZE) +#define CONFIG_SYS_GBL_DATA_SIZE 512 + +#define CONFIG_BOOTCOMMAND \ + "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \ + "source 0xa0000000; " \ + "else " \ + "bootm 0x60000; " \ + "fi; " +#define CONFIG_BOOTARGS \ + "console=tty0 console=ttyS2,115200 fbcon=rotate:3" +#define CONFIG_TIMESTAMP +#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +#define CONFIG_LZMA /* LZMA compression support */ + +/* + * Serial Console Configuration + * STUART - the lower serial port on Colibri board + */ +#define CONFIG_PXA_SERIAL +#define CONFIG_STUART 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Bootloader Components Configuration + */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_NET +#define CONFIG_CMD_ENV +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_MMC +#define CONFIG_CMD_SPI + +/* + * MMC Card Configuration + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_PXA_MMC +#define CONFIG_SYS_MMC_BASE 0xF0000000 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#endif + +/* + * SPI and LCD + */ +#ifdef CONFIG_CMD_SPI +#define CONFIG_SOFT_SPI +#define CONFIG_LCD +#define CONFIG_LMS283GF05 +#define CONFIG_VIDEO_LOGO +#define CONFIG_CMD_BMP +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) +#undef SPI_INIT + +#define SPI_DELAY udelay(10) +#define SPI_SDA(val) zipitz2_spi_sda(val) +#define SPI_SCL(val) zipitz2_spi_scl(val) +#define SPI_READ zipitz2_spi_read() +#ifndef __ASSEMBLY__ +void zipitz2_spi_sda(int); +void zipitz2_spi_scl(int); +unsigned char zipitz2_spi_read(void); +#endif +#endif + +/* + * KGDB + */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * HUSH Shell Configuration + */ +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_DEVICE_NULLDEV 1 + +/* + * Clock Configuration + */ +#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ +#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * DRAM Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ +#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ + +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE + +/* + * NOR FLASH + */ +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ +#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_PROTECTION + +/* + * GPIO settings + */ +#define CONFIG_SYS_GAFR0_L_VAL 0x02000140 +#define CONFIG_SYS_GAFR0_U_VAL 0x59188000 +#define CONFIG_SYS_GAFR1_L_VAL 0x63900002 +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950 +#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa +#define CONFIG_SYS_GAFR2_U_VAL 0x29000308 +#define CONFIG_SYS_GAFR3_L_VAL 0x54000000 +#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5 +#define CONFIG_SYS_GPCR0_VAL 0x00000000 +#define CONFIG_SYS_GPCR1_VAL 0x00000020 +#define CONFIG_SYS_GPCR2_VAL 0x00000000 +#define CONFIG_SYS_GPCR3_VAL 0x00000000 +#define CONFIG_SYS_GPDR0_VAL 0xdafcee00 +#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab +#define CONFIG_SYS_GPDR2_VAL 0x8fe1ffff +#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a +#define CONFIG_SYS_GPSR0_VAL 0x06080400 +#define CONFIG_SYS_GPSR1_VAL 0x007f0000 +#define CONFIG_SYS_GPSR2_VAL 0x032a0000 +#define CONFIG_SYS_GPSR3_VAL 0x00000180 + +#define CONFIG_SYS_PSSR_VAL 0x30 + +/* + * Clock settings + */ +#define CONFIG_SYS_CKEN 0x00511220 +#define CONFIG_SYS_CCCR 0x00000190 + +/* + * Memory settings + */ +#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8 +#define CONFIG_SYS_MSC1_VAL 0x0000ccd1 +#define CONFIG_SYS_MSC2_VAL 0x0000b884 +#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9 +#define CONFIG_SYS_MDREFR_VAL 0x2011a01e +#define CONFIG_SYS_MDMRS_VAL 0x00000000 +#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 +#define CONFIG_SYS_SXCNFG_VAL 0x40044004 + +/* + * PCMCIA and CF Interfaces + */ +#define CONFIG_SYS_MECR_VAL 0x00000001 +#define CONFIG_SYS_MCMEM0_VAL 0x00014307 +#define CONFIG_SYS_MCMEM1_VAL 0x00014307 +#define CONFIG_SYS_MCATT0_VAL 0x0001c787 +#define CONFIG_SYS_MCATT1_VAL 0x0001c787 +#define CONFIG_SYS_MCIO0_VAL 0x0001430f +#define CONFIG_SYS_MCIO1_VAL 0x0001430f + +#endif /* __CONFIG_H */ diff --git a/include/environment.h b/include/environment.h index 203f731..fbccf6a 100644 --- a/include/environment.h +++ b/include/environment.h @@ -74,15 +74,24 @@ #endif /* CONFIG_ENV_IS_IN_FLASH */ #if defined(CONFIG_ENV_IS_IN_NAND) -# ifndef CONFIG_ENV_OFFSET -# error "Need to define CONFIG_ENV_OFFSET when using CONFIG_ENV_IS_IN_NAND" -# endif +# if defined(CONFIG_ENV_OFFSET_OOB) +# ifdef CONFIG_ENV_OFFSET_REDUND +# error "CONFIG_ENV_OFFSET_REDUND is not supported when CONFIG_ENV_OFFSET_OOB" +# error "is set" +# endif +extern unsigned long nand_env_oob_offset; +# define CONFIG_ENV_OFFSET nand_env_oob_offset +# else +# ifndef CONFIG_ENV_OFFSET +# error "Need to define CONFIG_ENV_OFFSET when using CONFIG_ENV_IS_IN_NAND" +# endif +# ifdef CONFIG_ENV_OFFSET_REDUND +# define CONFIG_SYS_REDUNDAND_ENVIRONMENT +# endif +# endif /* CONFIG_ENV_OFFSET_OOB */ # ifndef CONFIG_ENV_SIZE # error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_NAND" # endif -# ifdef CONFIG_ENV_OFFSET_REDUND -# define CONFIG_SYS_REDUNDAND_ENVIRONMENT -# endif #endif /* CONFIG_ENV_IS_IN_NAND */ #if defined(CONFIG_ENV_IS_IN_MG_DISK) diff --git a/include/fdt_support.h b/include/fdt_support.h index 9a453af..fc16159 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -59,7 +59,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd); static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {} #endif /* CONFIG_HAS_FSL_DR_USB */ -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx) +#if defined(CONFIG_SYS_FSL_SEC_COMPAT) void fdt_fixup_crypto_node(void *blob, int sec_rev); #else static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {} diff --git a/include/lcd.h b/include/lcd.h index 1f85daa..cd9d49d 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -87,7 +87,7 @@ typedef struct vidinfo { u_char vl_wbf; /* Wait between frames */ } vidinfo_t; -#elif defined CONFIG_PXA250 +#elif defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS /* * PXA LCD DMA descriptor */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 5214911..ba6cdf1 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -65,6 +65,7 @@ #define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16) #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20) +#define SPR_8308 0x8100 #define SPR_831X_FAMILY 0x80B #define SPR_8311 0x80B2 #define SPR_8313 0x80B0 @@ -115,8 +116,9 @@ #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ #define SPCR_TSEC2EP_SHIFT (31-31) -#elif defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) -/* SPCR bits - MPC831x and MPC837x specific */ +#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC837x) +/* SPCR bits - MPC8308, MPC831x and MPC837x specific */ #define SPCR_TSECDP 0x00003000 /* TSEC data priority */ #define SPCR_TSECDP_SHIFT (31-19) #define SPCR_TSECBDP 0x00000C00 /* TSEC buffer descriptor priority */ @@ -473,7 +475,7 @@ #define HRCWL_CE_TO_PLL_1X30 0x0000001E #define HRCWL_CE_TO_PLL_1X31 0x0000001F -#elif defined(CONFIG_MPC8315) +#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) #define HRCWL_SVCOD 0x30000000 #define HRCWL_SVCOD_SHIFT 28 #define HRCWL_SVCOD_DIV_2 0x00000000 @@ -541,7 +543,8 @@ #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 -#if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC837x) #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 @@ -592,7 +595,8 @@ /* RSR - Reset Status Register */ -#if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC837x) #define RSR_RSTSRC 0xF0000000 /* Reset source */ #define RSR_RSTSRC_SHIFT 28 #else @@ -734,8 +738,8 @@ #define SCCR_USBDRCM_2 0x00200000 #define SCCR_USBDRCM_3 0x00300000 -#elif defined(CONFIG_MPC8315) -/* SCCR bits - MPC8315 specific */ +#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) +/* SCCR bits - MPC8315/MPC8308 specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 #define SCCR_TSEC1CM_0 0x00000000 @@ -750,6 +754,13 @@ #define SCCR_TSEC2CM_2 0x20000000 #define SCCR_TSEC2CM_3 0x30000000 +#define SCCR_SDHCCM 0x0c000000 +#define SCCR_SDHCCM_SHIFT 26 +#define SCCR_SDHCCM_0 0x00000000 +#define SCCR_SDHCCM_1 0x04000000 +#define SCCR_SDHCCM_2 0x08000000 +#define SCCR_SDHCCM_3 0x0c000000 + #define SCCR_USBDRCM 0x00c00000 #define SCCR_USBDRCM_SHIFT 22 #define SCCR_USBDRCM_0 0x00000000 diff --git a/include/mpc85xx.h b/include/mpc85xx.h index a4d4d65..2495b99 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -6,8 +6,6 @@ #ifndef __MPC85xx_H__ #define __MPC85xx_H__ -#include <asm/fsl_lbc.h> - /* define for common ppc_asm.tmpl */ #define EXC_OFF_SYS_RESET 0x100 /* System reset */ #define _START_OFFSET 0 diff --git a/include/nand.h b/include/nand.h index 2a81597..8bdf419 100644 --- a/include/nand.h +++ b/include/nand.h @@ -130,3 +130,12 @@ void board_nand_select_device(struct nand_chip *nand, int chip); __attribute__((noreturn)) void nand_boot(void); #endif + +#ifdef CONFIG_ENV_OFFSET_OOB +#define ENV_OOB_MARKER 0x30425645 /*"EVB0" in little-endian -- offset is stored + as block number*/ +#define ENV_OOB_MARKER_OLD 0x30564e45 /*"ENV0" in little-endian -- offset is + stored as byte number */ +#define ENV_OFFSET_SIZE 8 +int get_nand_env_oob(nand_info_t *nand, unsigned long *result); +#endif diff --git a/include/netdev.h b/include/netdev.h index 882642a..94eedfe 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -43,12 +43,14 @@ int cpu_eth_init(bd_t *bis); /* Driver initialization prototypes */ int altera_tse_initialize(u8 dev_num, int mac_base, int sgdma_rx_base, int sgdma_tx_base); +int ax88180_initialize(bd_t *bis); int au1x00_enet_initialize(bd_t*); int at91emac_register(bd_t *bis, unsigned long iobase); int bfin_EMAC_initialize(bd_t *bis); int cs8900_initialize(u8 dev_num, int base_addr); int dc21x4x_initialize(bd_t *bis); int davinci_emac_initialize(void); +int designware_initialize(u32 id, ulong base_addr, u32 phy_addr); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); int eepro100_initialize(bd_t *bis); @@ -61,7 +63,6 @@ int ftmac100_initialize(bd_t *bits); int greth_initialize(bd_t *bis); void gt6426x_eth_initialize(bd_t *bis); int inca_switch_initialize(bd_t *bis); -int kirkwood_egiga_initialize(bd_t *bis); int lan91c96_initialize(u8 dev_num, int base_addr); int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); int mcdmafec_initialize(bd_t *bis); @@ -70,6 +71,7 @@ int mpc512x_fec_initialize(bd_t *bis); int mpc5xxx_fec_initialize(bd_t *bis); int mpc8220_fec_initialize(bd_t *bis); int mpc82xx_scc_enet_initialize(bd_t *bis); +int mvgbe_initialize(bd_t *bis); int natsemi_initialize(bd_t *bis); int npe_initialize(bd_t *bis); int ns8382x_initialize(bd_t *bis); diff --git a/include/status_led.h b/include/status_led.h index 9dbf01f..f213595 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -346,9 +346,6 @@ void status_led_set (int led, int state); #elif defined(CONFIG_NIOS2) /* XXX empty just to avoid the error */ /************************************************************************/ -#elif defined(CONFIG_BLACKFIN) -/* XXX empty just to avoid the error */ -/************************************************************************/ #elif defined(CONFIG_V38B) # define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */ diff --git a/nand_spl/board/freescale/mpc8536ds/nand_boot.c b/nand_spl/board/freescale/mpc8536ds/nand_boot.c index af29dc2..5a0a0c7 100644 --- a/nand_spl/board/freescale/mpc8536ds/nand_boot.c +++ b/nand_spl/board/freescale/mpc8536ds/nand_boot.c @@ -34,12 +34,11 @@ void board_init_f(ulong bootflag) int px_spd; u32 plat_ratio, bus_clk, sys_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - ccsr_lbc_t *lbc = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR; #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) /* for FPGA */ - out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM); - out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM); + set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); + set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); #else #error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined #endif diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c index ff47d55..9547d44 100644 --- a/nand_spl/nand_boot_fsl_elbc.c +++ b/nand_spl/nand_boot_fsl_elbc.c @@ -32,7 +32,7 @@ static void nand_wait(void) { - fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000); + fsl_lbc_t *regs = LBC_BASE_ADDR; for (;;) { uint32_t status = in_be32(®s->ltesr); @@ -49,7 +49,7 @@ static void nand_wait(void) static void nand_load(unsigned int offs, int uboot_size, uchar *dst) { - fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000); + fsl_lbc_t *regs = LBC_BASE_ADDR; uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; int large = in_be32(®s->bank[0].or) & OR_FCM_PGS; int block_shift = large ? 17 : 14; @@ -234,6 +234,9 @@ int eth_initialize(bd_t *bis) puts (" [PRIME]"); } + if (strchr(dev->name, ' ')) + puts("\nWarning: eth device name has a space!\n"); + eth_getenv_enetaddr_by_index(eth_number, env_enetaddr); if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) { diff --git a/onenand_ipl/board/vpac270/Makefile b/onenand_ipl/board/vpac270/Makefile new file mode 100644 index 0000000..22d0410 --- /dev/null +++ b/onenand_ipl/board/vpac270/Makefile @@ -0,0 +1,83 @@ +IPL =onenand_ipl +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds +LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL +CFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL +OBJCFLAGS += --gap-fill=0x00 + +SOBJS := lowlevel_init.o +SOBJS += start.o +COBJS := vpac270.o +COBJS += onenand_read.o +COBJS += onenand_boot.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/onenand_ipl/board/$(BOARDDIR) + +onenandobj := $(OBJTREE)/onenand_ipl/ + +ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin + +all: $(obj).depend $(ALL) + +$(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x5c040400 -O binary $< $@ + +$(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(onenandobj)onenand-ipl: $(OBJS) $(onenandobj)u-boot.lds + cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + -Map $@.map -o $@ + +$(onenandobj)u-boot.lds: $(LDSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + +# create symbolic links from common files + +# from cpu directory +$(obj)start.S: + @rm -f $@ + ln -s $(SRCTREE)/$(CPUDIR)/start.S $@ + +# from onenand_ipl directory +$(obj)onenand_ipl.h: + @rm -f $@ + ln -s $(SRCTREE)/onenand_ipl/onenand_ipl.h $@ + +$(obj)onenand_boot.c: $(obj)onenand_ipl.h + @rm -f $@ + ln -s $(SRCTREE)/onenand_ipl/onenand_boot.c $@ + +$(obj)onenand_read.c: $(obj)onenand_ipl.h + @rm -f $@ + ln -s $(SRCTREE)/onenand_ipl/onenand_read.c $@ + +ifneq ($(OBJTREE), $(SRCTREE)) +$(obj)vpac270.c: + @rm -f $@ + ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/vpac270.c $@ + +$(obj)lowlevel_init.S: + @rm -f $@ + ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/lowlevel_init.S $@ +endif + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)$.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/onenand_ipl/board/vpac270/config.mk b/onenand_ipl/board/vpac270/config.mk new file mode 100644 index 0000000..f071dea --- /dev/null +++ b/onenand_ipl/board/vpac270/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x5c03fc00 diff --git a/onenand_ipl/board/vpac270/lowlevel_init.S b/onenand_ipl/board/vpac270/lowlevel_init.S new file mode 100644 index 0000000..e79d8dd --- /dev/null +++ b/onenand_ipl/board/vpac270/lowlevel_init.S @@ -0,0 +1,34 @@ +/* + * Voipac PXA270 Lowlevel Hardware Initialization + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> +#include <asm/arch/macro.h> + +.globl lowlevel_init +lowlevel_init: + pxa_clock_setup + mov pc, lr diff --git a/onenand_ipl/board/vpac270/u-boot.onenand.lds b/onenand_ipl/board/vpac270/u-boot.onenand.lds new file mode 100644 index 0000000..b2e7557 --- /dev/null +++ b/onenand_ipl/board/vpac270/u-boot.onenand.lds @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/board/altera/ep1s40/ep1s40.c b/onenand_ipl/board/vpac270/vpac270.c index 6395de7..a1eb331 100644 --- a/board/altera/ep1s40/ep1s40.c +++ b/onenand_ipl/board/vpac270/vpac270.c @@ -1,6 +1,13 @@ /* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> * * See file CREDITS for list of people who contributed to this * project. @@ -22,26 +29,14 @@ */ #include <common.h> -#include <netdev.h> +#include <asm/arch/hardware.h> -int checkboard (void) +int board_init (void) { - puts ("BOARD : Altera EP-1S40\n"); return 0; } -phys_size_t initdram (int board_type) -{ - return (0); -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) +int s_init(int skip) { - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; + return 0; } -#endif |