diff options
| -rw-r--r-- | arch/powerpc/cpu/mpc512x/diu.c | 62 | ||||
| -rw-r--r-- | board/davedenx/aria/aria.c | 5 | ||||
| -rw-r--r-- | board/freescale/common/fsl_diu_fb.c | 41 | ||||
| -rw-r--r-- | board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c | 74 | ||||
| -rw-r--r-- | board/freescale/p1022ds/Makefile | 2 | ||||
| -rw-r--r-- | board/freescale/p1022ds/diu.c | 304 | ||||
| -rw-r--r-- | board/pdm360ng/pdm360ng.c | 3 | ||||
| -rw-r--r-- | drivers/video/atmel_lcdfb.c | 3 | ||||
| -rw-r--r-- | include/configs/P1022DS.h | 19 | ||||
| -rw-r--r-- | include/fsl_diu_fb.h (renamed from board/freescale/common/fsl_diu_fb.h) | 1 | ||||
| -rw-r--r-- | include/lcd.h | 1 |
11 files changed, 382 insertions, 133 deletions
diff --git a/arch/powerpc/cpu/mpc512x/diu.c b/arch/powerpc/cpu/mpc512x/diu.c index fa4a0bc..c4108af 100644 --- a/arch/powerpc/cpu/mpc512x/diu.c +++ b/arch/powerpc/cpu/mpc512x/diu.c @@ -27,17 +27,10 @@ #include <command.h> #include <asm/io.h> -#include "../../../../board/freescale/common/fsl_diu_fb.h" - -#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) -#include <stdio_dev.h> -#include <video_fb.h> -#endif +#include <fsl_diu_fb.h> DECLARE_GLOBAL_DATA_PTR; -static int xres, yres; - void diu_set_pixel_clock(unsigned int pixclock) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; @@ -58,61 +51,20 @@ void diu_set_pixel_clock(unsigned int pixclock) debug("DIU: Modified value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr)); } -int mpc5121_diu_init(void) +int platform_diu_init(unsigned int *xres, unsigned int *yres) { unsigned int pixel_format; #if defined(CONFIG_VIDEO_XRES) & defined(CONFIG_VIDEO_YRES) - xres = CONFIG_VIDEO_XRES; - yres = CONFIG_VIDEO_YRES; + *xres = CONFIG_VIDEO_XRES; + *yres = CONFIG_VIDEO_YRES; #else - xres = 1024; - yres = 768; + *xres = 1024; + *yres = 768; #endif pixel_format = 0x88883316; debug("mpc5121_diu_init\n"); - return fsl_diu_init(xres, pixel_format, 0); + return fsl_diu_init(*xres, pixel_format, 0); } - -#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) - -/* - * The Graphic Device - */ -GraphicDevice ctfb; -void *video_hw_init(void) -{ - GraphicDevice *pGD = (GraphicDevice *) &ctfb; - struct fb_info *info; - - if (mpc5121_diu_init() < 0) - return NULL; - - /* fill in Graphic device struct */ - sprintf(pGD->modeIdent, "%dx%dx%d %dkHz %dHz", - xres, yres, 32, 64, 60); - - pGD->frameAdrs = (unsigned int)fsl_fb_open(&info); - pGD->winSizeX = xres; - pGD->winSizeY = yres; - pGD->plnSizeX = pGD->winSizeX; - pGD->plnSizeY = pGD->winSizeY; - - pGD->gdfBytesPP = 4; - pGD->gdfIndex = GDF_32BIT_X888RGB; - - pGD->isaBase = 0; - pGD->pciBase = 0; - pGD->memSize = info->screen_size; - - /* Cursor Start Address */ - pGD->dprBase = 0; - pGD->vprBase = 0; - pGD->cprBase = 0; - - return (void *)pGD; -} - -#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */ diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c index f17df60..31b079b 100644 --- a/board/davedenx/aria/aria.c +++ b/board/davedenx/aria/aria.c @@ -119,11 +119,6 @@ int misc_init_r(void) tmp & 0x000000FF ); -#ifdef CONFIG_FSL_DIU_FB -# if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)) - mpc5121_diu_init(); -# endif -#endif return 0; } diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c index 394b71f..35ed938 100644 --- a/board/freescale/common/fsl_diu_fb.c +++ b/board/freescale/common/fsl_diu_fb.c @@ -28,7 +28,7 @@ #include <malloc.h> #include <asm/io.h> -#include "fsl_diu_fb.h" +#include <fsl_diu_fb.h> struct fb_videomode { const char *name; /* optional */ @@ -472,3 +472,42 @@ static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align) buf->offset = 0; return 0; } + +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) +#include <stdio_dev.h> +#include <video_fb.h> +/* + * The Graphic Device + */ +static GraphicDevice ctfb; + +void *video_hw_init(void) +{ + struct fb_info *info; + + if (platform_diu_init(&ctfb.winSizeX, &ctfb.winSizeY) < 0) + return NULL; + + /* fill in Graphic device struct */ + sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz", + ctfb.winSizeX, ctfb.winSizeY, 32, 64, 60); + + ctfb.frameAdrs = (unsigned int)fsl_fb_open(&info); + ctfb.plnSizeX = ctfb.winSizeX; + ctfb.plnSizeY = ctfb.winSizeY; + + ctfb.gdfBytesPP = 4; + ctfb.gdfIndex = GDF_32BIT_X888RGB; + + ctfb.isaBase = 0; + ctfb.pciBase = 0; + ctfb.memSize = info->screen_size; + + /* Cursor Start Address */ + ctfb.dprBase = 0; + ctfb.vprBase = 0; + ctfb.cprBase = 0; + + return &ctfb; +} +#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */ diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c index 960c8ed..81e53e7 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c @@ -26,17 +26,7 @@ #include <common.h> #include <command.h> #include <asm/io.h> - -#ifdef CONFIG_FSL_DIU_FB - -#include "../common/fsl_diu_fb.h" - -#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) -#include <stdio_dev.h> -#include <video_fb.h> -#endif - -static int xres, yres; +#include <fsl_diu_fb.h> void diu_set_pixel_clock(unsigned int pixclock) { @@ -59,7 +49,7 @@ void diu_set_pixel_clock(unsigned int pixclock) debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); } -int mpc8610hpcd_diu_init(void) +int platform_diu_init(unsigned int *xres, unsigned int *yres) { char *monitor_port; int gamma_fix; @@ -73,8 +63,8 @@ int mpc8610hpcd_diu_init(void) monitor_port = getenv("monitor"); if (!strncmp(monitor_port, "0", 1)) { /* 0 - DVI */ - xres = 1280; - yres = 1024; + *xres = 1280; + *yres = 1024; if (pixis_arch == 0x01) pixel_format = 0x88882317; else @@ -83,68 +73,26 @@ int mpc8610hpcd_diu_init(void) out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08); } else if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */ - xres = 1024; - yres = 768; + *xres = 1024; + *yres = 768; pixel_format = 0x88883316; gamma_fix = 0; out_8(pixis_base + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10); } else if (!strncmp(monitor_port, "2", 1)) { /* 2 - Double link LVDS */ - xres = 1280; - yres = 1024; + *xres = 1280; + *yres = 1024; pixel_format = 0x88883316; gamma_fix = 1; out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xe7); } else { /* DVI */ - xres = 1280; - yres = 1024; + *xres = 1280; + *yres = 1024; pixel_format = 0x88882317; gamma_fix = 0; out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08); } - return fsl_diu_init(xres, pixel_format, gamma_fix); -} - -#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) - -/* - * The Graphic Device - */ -static GraphicDevice ctfb; - -void *video_hw_init(void) -{ - struct fb_info *info; - - if (mpc8610hpcd_diu_init() < 0) - return NULL; - - /* fill in Graphic device struct */ - sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz", xres, yres, 32, 64, 60); - - ctfb.frameAdrs = (unsigned int)fsl_fb_open(&info); - ctfb.winSizeX = xres; - ctfb.winSizeY = yres; - ctfb.plnSizeX = ctfb.winSizeX; - ctfb.plnSizeY = ctfb.winSizeY; - - ctfb.gdfBytesPP = 4; - ctfb.gdfIndex = GDF_32BIT_X888RGB; - - ctfb.isaBase = 0; - ctfb.pciBase = 0; - ctfb.memSize = info->screen_size; - - /* Cursor Start Address */ - ctfb.dprBase = 0; - ctfb.vprBase = 0; - ctfb.cprBase = 0; - - return &ctfb; + return fsl_diu_init(*xres, pixel_format, gamma_fix); } - -#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */ - -#endif /* CONFIG_FSL_DIU_FB */ diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile index 8ede2d6..678eb2a 100644 --- a/board/freescale/p1022ds/Makefile +++ b/board/freescale/p1022ds/Makefile @@ -16,6 +16,8 @@ COBJS-y += ddr.o COBJS-y += law.o COBJS-y += tlb.o +COBJS-$(CONFIG_FSL_DIU_FB) += diu.o + SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/p1022ds/diu.c b/board/freescale/p1022ds/diu.c new file mode 100644 index 0000000..12b40a0 --- /dev/null +++ b/board/freescale/p1022ds/diu.c @@ -0,0 +1,304 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Timur Tabi <timur@freescale.com> + * + * FSL DIU Framebuffer driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> +#include <stdio_dev.h> +#include <video_fb.h> +#include "../common/ngpixis.h" +#include <fsl_diu_fb.h> + +/* The CTL register is called 'csr' in the ngpixis_t structure */ +#define PX_CTL_ALTACC 0x80 + +#define PX_BRDCFG0_ELBC_SPI_MASK 0xc0 +#define PX_BRDCFG0_ELBC_SPI_ELBC 0x00 +#define PX_BRDCFG0_ELBC_SPI_NULL 0xc0 +#define PX_BRDCFG0_ELBC_DIU 0x02 + +#define PX_BRDCFG1_DVIEN 0x80 +#define PX_BRDCFG1_DFPEN 0x40 +#define PX_BRDCFG1_BACKLIGHT 0x20 + +#define PMUXCR_ELBCDIU_MASK 0xc0000000 +#define PMUXCR_ELBCDIU_NOR16 0x80000000 + +/* + * DIU Area Descriptor + * + * Note that we need to byte-swap the value before it's written to the AD + * register. So even though the registers don't look like they're in the same + * bit positions as they are on the MPC8610, the same value is written to the + * AD register on the MPC8610 and on the P1022. + */ +#define AD_BYTE_F 0x10000000 +#define AD_ALPHA_C_SHIFT 25 +#define AD_BLUE_C_SHIFT 23 +#define AD_GREEN_C_SHIFT 21 +#define AD_RED_C_SHIFT 19 +#define AD_PIXEL_S_SHIFT 16 +#define AD_COMP_3_SHIFT 12 +#define AD_COMP_2_SHIFT 8 +#define AD_COMP_1_SHIFT 4 +#define AD_COMP_0_SHIFT 0 + +/* + * Variables used by the DIU/LBC switching code. It's safe to makes these + * global, because the DIU requires DDR, so we'll only run this code after + * relocation. + */ +static u8 px_brdcfg0; +static u32 pmuxcr; +static void *lbc_lcs0_ba; +static void *lbc_lcs1_ba; + +void diu_set_pixel_clock(unsigned int pixclock) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + unsigned long speed_ccb, temp; + u32 pixval; + + speed_ccb = get_bus_freq(0); + temp = 1000000000 / pixclock; + temp *= 1000; + pixval = speed_ccb / temp; + debug("DIU pixval = %lu\n", pixval); + + /* Modify PXCLK in GUTS CLKDVDR */ + temp = in_be32(&gur->clkdvdr) & 0x2000FFFF; + out_be32(&gur->clkdvdr, temp); /* turn off clock */ + out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16)); +} + +int platform_diu_init(unsigned int *xres, unsigned int *yres) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + char *monitor_port; + u32 pixel_format; + u8 temp; + + /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */ + lbc_lcs0_ba = (void *)(get_lbc_br(0) & get_lbc_or(0) & 0xFFFF8000); + lbc_lcs1_ba = (void *)(get_lbc_br(1) & get_lbc_or(1) & 0xFFFF8000); + + pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | + (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | + (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | + (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | + (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); + + temp = in_8(&pixis->brdcfg1); + + monitor_port = getenv("monitor"); + if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */ + *xres = 1024; + *yres = 768; + /* Enable the DFP port, disable the DVI and the backlight */ + temp &= ~(PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT); + temp |= PX_BRDCFG1_DFPEN; + } else { /* DVI */ + *xres = 1280; + *yres = 1024; + /* Enable the DVI port, disable the DFP and the backlight */ + temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT); + temp |= PX_BRDCFG1_DVIEN; + } + + out_8(&pixis->brdcfg1, temp); + + /* + * Enable PIXIS indirect access mode. This is a hack that allows us to + * access PIXIS registers even when the LBC pins have been muxed to the + * DIU. + */ + setbits_8(&pixis->csr, PX_CTL_ALTACC); + + /* + * Route the LAD pins to the DIU. This will disable access to the eLBC, + * which means we won't be able to read/write any NOR flash addresses! + */ + out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); + px_brdcfg0 = in_8(lbc_lcs1_ba); + out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU); + + /* Setting PMUXCR to switch to DVI from ELBC */ + clrsetbits_be32(&gur->pmuxcr, + PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_NOR16); + pmuxcr = in_be32(&gur->pmuxcr); + + return fsl_diu_init(*xres, pixel_format, 0); +} + +#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS + +/* + * set_mux_to_lbc - disable the DIU so that we can read/write to elbc + * + * On the Freescale P1022, the DIU video signal and the LBC address/data lines + * share the same pins, which means that when the DIU is active (e.g. the + * console is on the DVI display), NOR flash cannot be accessed. So we use the + * weak accessor feature of the CFI flash code to temporarily switch the pin + * mux from DIU to LBC whenever we want to read or write flash. This has a + * significant performance penalty, but it's the only way to make it work. + * + * There are two muxes: one on the chip, and one on the board. The chip mux + * controls whether the pins are used for the DIU or the LBC, and it is + * set via PMUXCR. The board mux controls whether those signals go to + * the video connector or the NOR flash chips, and it is set via the ngPIXIS. + */ +static int set_mux_to_lbc(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Switch the muxes only if they're currently set to DIU mode */ + if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) == + PMUXCR_ELBCDIU_NOR16) { + /* + * In DIU mode, the PIXIS can only be accessed indirectly + * since we can't read/write the LBC directly. + */ + + /* Set the board mux to LBC. This will disable the display. */ + out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); + px_brdcfg0 = in_8(lbc_lcs1_ba); + out_8(lbc_lcs1_ba, (px_brdcfg0 & ~(PX_BRDCFG0_ELBC_SPI_MASK + | PX_BRDCFG0_ELBC_DIU)) | PX_BRDCFG0_ELBC_SPI_ELBC); + + /* Disable indirect PIXIS mode */ + out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr)); + clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC); + + /* Set the chip mux to LBC mode, so that writes go to flash. */ + out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) | + PMUXCR_ELBCDIU_NOR16); + in_be32(&gur->pmuxcr); + + return 1; + } + + return 0; +} + +/* + * set_mux_to_diu - re-enable the DIU muxing + * + * This function restores the chip and board muxing to point to the DIU. + */ +static void set_mux_to_diu(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Enable indirect PIXIS mode */ + setbits_8(&pixis->csr, PX_CTL_ALTACC); + + /* Set the board mux to DIU. This will enable the display. */ + out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); + out_8(lbc_lcs1_ba, px_brdcfg0); + in_8(lbc_lcs1_ba); + + /* Set the chip mux to DIU mode. */ + out_be32(&gur->pmuxcr, pmuxcr); + in_be32(&gur->pmuxcr); +} + +void flash_write8(u8 value, void *addr) +{ + int sw = set_mux_to_lbc(); + + __raw_writeb(value, addr); + if (sw) + set_mux_to_diu(); +} + +void flash_write16(u16 value, void *addr) +{ + int sw = set_mux_to_lbc(); + + __raw_writew(value, addr); + if (sw) + set_mux_to_diu(); +} + +void flash_write32(u32 value, void *addr) +{ + int sw = set_mux_to_lbc(); + + __raw_writel(value, addr); + if (sw) + set_mux_to_diu(); +} + +void flash_write64(u64 value, void *addr) +{ + int sw = set_mux_to_lbc(); + + /* There is no __raw_writeq(), so do the write manually */ + *(volatile u64 *)addr = value; + if (sw) + set_mux_to_diu(); +} + +u8 flash_read8(void *addr) +{ + u8 ret; + + int sw = set_mux_to_lbc(); + + ret = __raw_readb(addr); + if (sw) + set_mux_to_diu(); + + return ret; +} + +u16 flash_read16(void *addr) +{ + u16 ret; + + int sw = set_mux_to_lbc(); + + ret = __raw_readw(addr); + if (sw) + set_mux_to_diu(); + + return ret; +} + +u32 flash_read32(void *addr) +{ + u32 ret; + + int sw = set_mux_to_lbc(); + + ret = __raw_readl(addr); + if (sw) + set_mux_to_diu(); + + return ret; +} + +u64 flash_read64(void *addr) +{ + u64 ret; + + int sw = set_mux_to_lbc(); + + /* There is no __raw_readq(), so do the read manually */ + ret = *(volatile u64 *)addr; + if (sw) + set_mux_to_diu(); + + return ret; +} + +#endif diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c index e3abeb8..e8714e3 100644 --- a/board/pdm360ng/pdm360ng.c +++ b/board/pdm360ng/pdm360ng.c @@ -237,9 +237,6 @@ int misc_init_r(void) #endif #ifdef CONFIG_FSL_DIU_FB -# if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)) - mpc5121_diu_init(); -#endif #if defined(CONFIG_SERIAL_MULTI) set_lcd_brightness(0); #endif diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index db86763..c02ffd8 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -143,8 +143,9 @@ void lcd_ctrl_init(void *lcdbase) /* Set contrast */ value = ATMEL_LCDC_PS_DIV8 | - ATMEL_LCDC_POL_POSITIVE | ATMEL_LCDC_ENA_PWMENABLE; + if (!panel_info.vl_cont_pol_low) + value |= ATMEL_LCDC_POL_POSITIVE; lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value); lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT); diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index dcaca2b..2306e7f 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -177,14 +177,23 @@ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_FSL_DIU_FB -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) - /* Video */ -/* #define CONFIG_VIDEO */ -#ifdef CONFIG_VIDEO +#undef CONFIG_FSL_DIU_FB + +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) +#define CONFIG_VIDEO +#define CONFIG_CMD_BMP #define CONFIG_CFB_CONSOLE #define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +/* + * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so + * disable empty flash sector detection, which is I/O-intensive. + */ +#undef CONFIG_SYS_FLASH_EMPTY_INFO #endif /* diff --git a/board/freescale/common/fsl_diu_fb.h b/include/fsl_diu_fb.h index 3a5fc9f..87443e1 100644 --- a/board/freescale/common/fsl_diu_fb.h +++ b/include/fsl_diu_fb.h @@ -57,3 +57,4 @@ struct fb_info { extern char *fsl_fb_open(struct fb_info **info); int fsl_diu_init(int xres, unsigned int pixel_format, int gamma_fix); +int platform_diu_init(unsigned int *xres, unsigned int *yres); diff --git a/include/lcd.h b/include/lcd.h index cd9d49d..0e098d9 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -167,6 +167,7 @@ typedef struct vidinfo { u_long vl_sync; /* Horizontal / vertical sync */ u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ u_long vl_tft; /* 0 = passive, 1 = TFT */ + u_long vl_cont_pol_low; /* contrast polarity is low */ /* Horizontal control register. */ u_long vl_hsync_len; /* Length of horizontal sync */ |