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-rw-r--r--CHANGELOG147
-rw-r--r--Makefile2
-rw-r--r--cpu/mpc83xx/cpu_init.c61
-rw-r--r--drivers/mtd/nand/nand_util.c4
-rw-r--r--include/asm-microblaze/bitops.h2
-rw-r--r--include/configs/MVBLUE.h1
-rw-r--r--include/configs/imx27lite.h1
-rw-r--r--include/configs/microblaze-generic.h2
-rw-r--r--lib_ppc/board.c8
9 files changed, 189 insertions, 39 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 4bf806e..43317f1 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,150 @@
+commit f9476902b789b0481b9df49af88d6ca94fb16fa0
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Dec 15 12:10:47 2009 -0600
+
+ mpc85xx, mpc86xx: Fix gd->cpu pointer after relocation
+
+ The gd->cpu pointer is set to an address located in flash when the
+ probecpu() function is called while U-Boot is executing from flash.
+ This pointer needs to be updated to point to an address in RAM after
+ relocation has occurred otherwise Linux may not be able to boot due to
+ "fdt board" crashing if flash has been erased or changed.
+
+ This bug was introduced in commit
+ a0e2066f392782730f0398095e583c87812d97f2.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Reported-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+ Tested-by: Kumar Gala <galak@kernel.crashing.org>
+ Tested on MPC8527DS.
+ Tested by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit 3363a34b9eeda9783afcbbed5cdd738926d1f4bf
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Sun Dec 13 17:58:34 2009 -0600
+
+ MVBLUE: Remove CONFIG_CMD_IRQ
+
+ Neither the MVBLUE nor its underlying architecture implement the
+ do_irqinfo() function which is required when CONFIG_CMD_IRQ is defined.
+ This change fixes the following MVBLUE compiler error:
+
+ -> ./MAKEALL MVBLUE
+ Configuring for MVBLUE board...
+ common/libcommon.a(cmd_irq.o):(.u_boot_cmd+0x24): undefined reference to `do_irqinfo'
+ make: *** [u-boot] Error 1
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+ Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
+
+commit 18e8ad60ee87431c01cc2686985b60cc54f5dd3b
+Author: Detlev Zundel <dzu@denx.de>
+Date: Mon Dec 14 17:54:40 2009 +0100
+
+ imx27lite: Reenable MTD support on NOR flash.
+
+ The support for this was silently dropped by a configuration
+ split during the merge of the imx27lite board support in commit
+ 864aa034f3a0e10ce710e8bbda171df3cab59414 (cmd_mtdparts: Move to common
+ handling of FLASH devices via MTD layer).
+
+ Signed-off-by: Detlev Zundel <dzu@denx.de>
+
+commit f4cfe42758192d09f8375e384cc000aa70d97029
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Dec 9 09:01:43 2009 +0100
+
+ nand: Fix access to last block in NAND devices
+
+ Currently, the last block of NAND devices can't be accessed. This patch
+ fixes this issue by correcting the boundary checking (off-by-one error).
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+ Cc: Scott Wood <scottwood@freescale.com>
+ Cc: Wolfgang Denk <wd@denx.de>
+
+commit 3b887ca8ce72cc12129183538f6e828db13f4867
+Author: Peter Korsgaard <jacmet@sunsite.dk>
+Date: Tue Dec 8 22:20:34 2009 +0100
+
+ mpc83xx: boot time regression, move LCRR setup back to cpu_init_f
+
+ Commit c7190f02 (retain POR values of non-configured ACR, SPCR, SCCR,
+ and LCRR bitfields) moved the LCRR assignment to after relocation
+ to RAM because of the potential problem with changing the local bus
+ clock while executing from flash.
+
+ This change unfortunately adversely affects the boot time, as running
+ all code up to cpu_init_r can cause significant slowdown.
+
+ E.G. on a 8347 board a bootup time increase of ~600ms has been observed:
+
+ 0.020 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
+ 0.168 RS: 232
+ 0.172 I2C: ready
+ 0.176 DRAM: 64 MB
+ 1.236 FLASH: 32 MB
+
+ Versus:
+
+ 0.016 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
+ 0.092 RS: 232
+ 0.092 I2C: ready
+ 0.096 DRAM: 64 MB
+ 0.644 FLASH: 32 MB
+
+ So far no boards have needed the late LCRR setup, so simply revert it
+ for now - If it is needed at a later time, those boards can either do
+ their own final LCRR setup in board code (E.G. in board_early_init_r),
+ or we can introduce a CONFIG_SYS_LCRR_LATE config option to only do
+ the setup in cpu_init_r.
+
+ Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 386118a896554b13f14ad0f82356276988f7de82
+Author: Michal Simek <monstr@monstr.eu>
+Date: Tue Dec 8 09:12:49 2009 +0100
+
+ microblaze: Correct ffs regression for Microblaze
+
+ We are using generic implementation of ffs. This should
+ be part of Simon's commit 0413cfecea350000eab5e591a0965c3e3ee0ff00
+
+ Here is warning message which this patch removes.
+
+ In file included from /tmp/u-boot-microblaze/include/common.h:38,
+ from cmd_mtdparts.c:87:
+ /tmp/u-boot-microblaze/include/linux/bitops.h:123:1: warning: "ffs" redefined
+ In file included from /tmp/u-boot-microblaze/include/linux/bitops.h:110,
+ from /tmp/u-boot-microblaze/include/common.h:38,
+ from cmd_mtdparts.c:87:
+ /tmp/u-boot-microblaze/include/asm/bitops.h:269:1:
+ warning: this is the location of the previous definition
+
+ Signed-off-by: Michal Simek <monstr@monstr.eu>
+
+commit 8fe7b29f9811322931f0192a56431edcf819d6b9
+Author: Graeme Smecher <graeme.smecher@mail.mcgill.ca>
+Date: Mon Dec 7 08:09:57 2009 -0800
+
+ microblaze: Stop stack clobbering in microblaze-generic.
+
+ A typo caused the stack and malloc regions to overlap, which prevented
+ mem_malloc_init() from returning. This commit makes the memory layout match
+ the example described in include/configs/microblaze-generic.h
+
+ Signed-off-by: Graeme Smecher <graeme.smecher@mail.mcgill.ca>
+ Signed-off-by: Michal Simek <monstr@monstr.eu>
+
+commit 0fc52948bda0734431cb528ee4fd82f1dec8c7b5
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Dec 7 23:14:13 2009 +0100
+
+ Update CHANGELOG, prepare -rc2
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
commit f2352877cb2daac88115192fb09991a2397d0b27
Author: Peter Tyser <ptyser@xes-inc.com>
Date: Sun Dec 6 23:58:28 2009 -0600
diff --git a/Makefile b/Makefile
index 75b2c1e..536ccb3 100644
--- a/Makefile
+++ b/Makefile
@@ -24,7 +24,7 @@
VERSION = 2009
PATCHLEVEL = 11
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION =
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 031e8d5..0d6a5fe 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -171,6 +171,28 @@ void cpu_init_f (volatile immap_t * im)
(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
#endif
0;
+ __be32 lcrr_mask =
+#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
+ LCRR_DBYP |
+#endif
+#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
+ LCRR_EADC |
+#endif
+#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
+ LCRR_CLKDIV |
+#endif
+ 0;
+ __be32 lcrr_val =
+#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
+ CONFIG_SYS_LCRR_DBYP |
+#endif
+#ifdef CONFIG_SYS_LCRR_EADC
+ CONFIG_SYS_LCRR_EADC |
+#endif
+#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
+ CONFIG_SYS_LCRR_CLKDIV |
+#endif
+ 0;
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@@ -199,6 +221,13 @@ void cpu_init_f (volatile immap_t * im)
*/
__raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
+ /* LCRR - Clock Ratio Register (10.3.1.16)
+ * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
+ */
+ clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
+ __raw_readl(&im->lbus.lcrr);
+ isync();
+
/* Enable Time Base & Decrementer ( so we will have udelay() )*/
setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
@@ -331,41 +360,9 @@ void cpu_init_f (volatile immap_t * im)
int cpu_init_r (void)
{
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
#ifdef CONFIG_QE
uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
-#endif
- __be32 lcrr_mask =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
- LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
- LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
- LCRR_CLKDIV |
-#endif
- 0;
- __be32 lcrr_val =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
- CONFIG_SYS_LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC
- CONFIG_SYS_LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
- CONFIG_SYS_LCRR_CLKDIV |
-#endif
- 0;
- /* LCRR - Clock Ratio Register (10.3.1.16)
- * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
- */
- clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
- __raw_readl(&im->lbus.lcrr);
- isync();
-
-#ifdef CONFIG_QE
qe_init(qe_base);
qe_reset();
#endif
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index df7f140..29c42f7 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -486,7 +486,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
len_incl_bad = get_len_incl_bad (nand, offset, *length);
- if ((offset + len_incl_bad) >= nand->size) {
+ if ((offset + len_incl_bad) > nand->size) {
printf ("Attempt to write outside the flash area\n");
return -EINVAL;
}
@@ -558,7 +558,7 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
len_incl_bad = get_len_incl_bad (nand, offset, *length);
- if ((offset + len_incl_bad) >= nand->size) {
+ if ((offset + len_incl_bad) > nand->size) {
printf ("Attempt to read outside the flash area\n");
return -EINVAL;
}
diff --git a/include/asm-microblaze/bitops.h b/include/asm-microblaze/bitops.h
index 5d814f0..e8c835f 100644
--- a/include/asm-microblaze/bitops.h
+++ b/include/asm-microblaze/bitops.h
@@ -266,8 +266,6 @@ found_middle:
return result + ffz(tmp);
}
-#define ffs(x) generic_ffs(x)
-
/*
* hweightN: returns the hamming weight (i.e. the number
* of bits set) of a N-bit word
diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h
index 79c2069..669816c 100644
--- a/include/configs/MVBLUE.h
+++ b/include/configs/MVBLUE.h
@@ -88,7 +88,6 @@
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_RUN
diff --git a/include/configs/imx27lite.h b/include/configs/imx27lite.h
index e219ccc..ee749ec 100644
--- a/include/configs/imx27lite.h
+++ b/include/configs/imx27lite.h
@@ -145,6 +145,7 @@
/*
* MTD
*/
+#define CONFIG_FLASH_CFI_MTD
#define CONFIG_MTD_DEVICE
/*
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index b486c77..9b1569a 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -146,7 +146,7 @@
#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
/* stack */
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MALLOC_BASE
/*#define RAMENV */
#define FLASH
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index 765f97a..dd22f99 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -645,6 +645,14 @@ void board_init_r (gd_t *id, ulong dest_addr)
/* The Malloc area is immediately below the monitor copy in DRAM */
malloc_start = dest_addr - TOTAL_MALLOC_LEN;
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+ /*
+ * The gd->cpu pointer is set to an address in flash before relocation.
+ * We need to update it to point to the same CPU entry in RAM.
+ */
+ gd->cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
+#endif
+
#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
#endif