diff options
| -rw-r--r-- | arch/arm/cpu/armv7/omap4/clocks.c | 61 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/clocks.h | 12 |
2 files changed, 65 insertions, 8 deletions
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index 0db9d18..eda960c 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -66,7 +66,18 @@ static const u32 sys_clk_array[8] = { * Please use this tool for creating the table for any new frequency. */ -/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo) */ +/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */ +static const struct dpll_params mpu_dpll_params_1840mhz[NUM_SYS_CLKS] = { + {230, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {920, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {219, 3, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {575, 11, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {460, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {920, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {575, 23, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */ static const struct dpll_params mpu_dpll_params_1584mhz[NUM_SYS_CLKS] = { {66, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ {792, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ @@ -320,6 +331,47 @@ u32 omap4_ddr_clk(void) return ddr_clk; } +/* + * Lock MPU dpll + * + * Resulting MPU frequencies: + * 4430 ES1.0 : 600 MHz + * 4430 ES2.x : 792 MHz (OPP Turbo) + * 4460 : 920 MHz (OPP Turbo) - DCC disabled + */ +void configure_mpu_dpll(void) +{ + const struct dpll_params *params; + struct dpll_regs *mpu_dpll_regs; + u32 omap4_rev, sysclk_ind; + + omap4_rev = omap_revision(); + sysclk_ind = get_sys_clk_index(); + + if (omap4_rev == OMAP4430_ES1_0) + params = &mpu_dpll_params_1200mhz[sysclk_ind]; + else if (omap4_rev < OMAP4460_ES1_0) + params = &mpu_dpll_params_1584mhz[sysclk_ind]; + else + params = &mpu_dpll_params_1840mhz[sysclk_ind]; + + /* DCC and clock divider settings for 4460 */ + if (omap4_rev >= OMAP4460_ES1_0) { + mpu_dpll_regs = + (struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu; + bypass_dpll(&prcm->cm_clkmode_dpll_mpu); + clrbits_le32(&prcm->cm_mpu_mpu_clkctrl, + MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK); + setbits_le32(&prcm->cm_mpu_mpu_clkctrl, + MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); + clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll, + CM_CLKSEL_DCC_EN_MASK); + } + + do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK); + debug("MPU DPLL locked\n"); +} + static void setup_dplls(void) { u32 sysclk_ind, temp; @@ -349,12 +401,7 @@ static void setup_dplls(void) debug("PER DPLL locked\n"); /* MPU dpll */ - if (omap_revision() == OMAP4430_ES1_0) - params = &mpu_dpll_params_1200mhz[sysclk_ind]; - else - params = &mpu_dpll_params_1584mhz[sysclk_ind]; - do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK); - debug("MPU DPLL locked\n"); + configure_mpu_dpll(); } static void setup_non_essential_dplls(void) diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index 5d9cb50..374e064 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -105,9 +105,11 @@ struct omap4_prcm_regs { u32 cm_ssc_deltamstep_dpll_ddrphy; u32 pad014[5]; u32 cm_shadow_freq_config1; + u32 pad0141[47]; + u32 cm_mpu_mpu_clkctrl; /* cm1.dsp */ - u32 pad015[103]; + u32 pad015[55]; u32 cm_dsp_clkstctrl; u32 pad016[7]; u32 cm_dsp_dsp_clkctrl; @@ -515,6 +517,8 @@ struct omap4_prcm_regs { #define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) #define CM_CLKSEL_DPLL_N_SHIFT 0 #define CM_CLKSEL_DPLL_N_MASK 0x7F +#define CM_CLKSEL_DCC_EN_SHIFT 22 +#define CM_CLKSEL_DCC_EN_MASK (1 << 22) #define OMAP4_DPLL_MAX_N 127 @@ -596,6 +600,12 @@ struct omap4_prcm_regs { /* CM_L3INIT_USBPHY_CLKCTRL */ #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 +/* CM_MPU_MPU_CLKCTRL */ +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) + /* Clock frequencies */ #define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 |